MCP6295T-E/MS [MICROCHIP]
DUAL OP-AMP, 5000 uV OFFSET-MAX, 10 MHz BAND WIDTH, PDSO8, PLASTIC, MO-187, MSOP-8;型号: | MCP6295T-E/MS |
厂家: | MICROCHIP |
描述: | DUAL OP-AMP, 5000 uV OFFSET-MAX, 10 MHz BAND WIDTH, PDSO8, PLASTIC, MO-187, MSOP-8 放大器 光电二极管 |
文件: | 总48页 (文件大小:1016K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MCP6291/1R/2/3/4/5
1.0 mA, 10 MHz Rail-to-Rail Op Amp
Features
Description
• Gain Bandwidth Product: 10 MHz (typical)
• Supply Current: IQ = 1.0 mA
The Microchip Technology Inc. MCP6291/1R/2/3/4/5
family of operational amplifiers (op amps) provide wide
bandwidth for the current. This family has a 10 MHz
Gain Bandwidth Product (GBWP) and a 65° phase
margin. This family also operates from a single supply
voltage as low as 2.4V, while drawing 1 mA (typical)
quiescent current. In addition, the MCP6291/1R/2/3/4/5
supports rail-to-rail input and output swing, with a Com-
mon-mode input voltage range of VDD + 300 mV to
VSS – 300 mV. This family of operational amplifiers is
designed with Microchip’s advanced CMOS process.
• Supply Voltage: 2.4V to 6.0V
• Rail-to-Rail Input/Output
• Extended Temperature Range: -40°C to +125°C
• Available in Single, Dual and Quad Packages
• Single with CS (MCP6293)
• Dual with CS (MCP6295)
Applications
The MCP6295 has a Chip Select (CS) input for dual op
amps in an 8-pin package. This device is manufactured
by cascading the two op amps, with the output of
op amp A being connected to the non-inverting input of
op amp B. The CS input puts the device in a Low-power
mode.
• Automotive
• Portable Equipment
• Photodiode Amplifier
• Analog Filters
• Notebooks and PDAs
• Battery-Powered Systems
The MCP6291/1R/2/3/4/5 family operates over the
Extended Temperature Range of -40°C to +125°C. It
also has a power supply range of 2.4V to 6.0V.
Design Aids
• SPICE Macro Models
• FilterLab® Software
• Mindi™ Simulation Tool
• MAPS (Microchip Advanced Part Selector)
• Analog Demonstration and Evaluation Boards
• Application Notes
Package Types
MCP6291
MCP6291
MCP6291R
MCP6292
PDIP, SOIC, MSOP
PDIP, SOIC, MSOP
SOT-23-5
SOT-23-5
VOUTA
1
2
3
4
NC
VDD
8 NC
8
7
6
5
1
VDD
VSS
VOUT
VSS
VOUT
VDD
1
2
3
5
4
1
5
4
_
_
7
VIN
VIN
VSS
VDD
-
+
VINA
2
-
+
VOUTB
2
3
+
-
-
+
_
VOUT
6
VINA+ 3
-
+
VINB
VIN
+
VIN
–
VIN
+
VIN–
5
VSS
4
NC
VINB
+
MCP6293
PDIP, SOIC, MSOP
MCP6293
MCP6294
PDIP, SOIC, TSSOP
MCP6295
PDIP, SOIC, MSOP
SOT-23-6
NC
1
2
3
4
8 CS
VOUTA
V
14
13
12
11
1
OUTD
VOUTA/VINB
+
VDD
8
7
6
5
1
2
3
4
VDD
CS
VOUT
VSS
1
2
3
6
5
4
_
_
_
VIN
VIN
VSS
VDD
7
-
+
VINA
-
2
-
+
+
VIND
VIND
VSS
_
-
+
VOUTB
VINA
VINA
VSS
+
-
VOUT
NC
6
5
VINA+ 3
+
_
-
VINB
+
VIN
–
+
VIN
+
VDD
4
CS
10
9
5
6
7
VINC
VINC
+
_
VINB
VINB
+
_
+
-
-
+
VOUTB
8 VOUTC
2019 Microchip Technology Inc.
DS20001812F-page 1
MCP6291/1R/2/3/4/5
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD – VSS ........................................................................7.0V
Current at Input Pins .....................................................±2 mA
Analog Inputs (VIN+, VIN–) †† ........ VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V
†† See Section 4.1.2 “Input Voltage and Current Limits”.
Difference Input Voltage ...................................... |VDD – VSS
|
Output Short Circuit Current .................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature....................................–65°C to +150°C
Maximum Junction Temperature (TJ)..........................+150°C
ESD Protection On All Pins (HBM; MM) 4 kV; 400V
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VOUT VDD/2,
V
CM = VDD/2, VL = VDD/2, RL = 10 kto VL and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input Offset
Input Offset Voltage
VOS
VOS
-3.0
-5.0
—
—
+3.0
+5.0
mV
VCM = VSS (Note 1)
TA = -40°C to +125°C,
CM = VSS (Note 1)
µV/°C TA = -40°C to +125°C,
CM = VSS (Note 1)
Input Offset Voltage
(Extended Temperature)
mV
V
Input Offset Temperature Drift
VOS/TA
—
±1.7
90
—
—
V
Power Supply Rejection Ratio
PSRR
70
dB
VCM = VSS (Note 1)
Input Bias, Input Offset Current and Impedance
Input Bias Current
IB
IB
—
—
—
—
—
—
±1.0
50
—
200
5
pA
pA
nA
pA
Note 2
At Temperature
TA = +85°C (Note 2)
TA = +125°C (Note 2)
Note 3
At Temperature
IB
2
Input Offset Current
IOS
ZCM
ZDIFF
±1.0
1013||6
1013||3
—
—
—
Common-mode Input Impedance
Differential Input Impedance
Common-mode (Note 4)
Common-mode Input Range
Common-mode Rejection Ratio
Common-mode Rejection Ratio
Open-Loop Gain
||pF Note 3
||pF Note 3
VCMR
CMRR
CMRR
VSS 0.3
—
85
80
VDD + 0.3
V
70
65
—
—
dB
dB
VCM = -0.3V to 2.5V, VDD = 5V
VCM = -0.3V to 5.3V, VDD = 5V
DC Open-Loop Gain (Large Signal)
AOL
90
110
—
dB
VOUT = 0.2V to VDD – 0.2V,
V
CM = VSS (Note 1)
Output
Maximum Output Voltage Swing
Output Short Circuit Current
Power Supply
VOL, VOH VSS + 15
—
VDD – 15
—
mV
mA
0.5V Input Overdrive
ISC
—
±25
Supply Voltage
VDD
IQ
2.4
0.7
—
6.0
1.3
V
TA = -40°C to +125°C (Note 5)
Quiescent Current per Amplifier
1.0
mA
IO = 0
Note 1: The MCP6295’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV.
2: The current at the MCP6295’s VINB– pin is specified by IB only.
3: This specification does not apply to the MCP6295’s VOUTA/VINB+ pin.
4: The MCP6295’s VINB– pin (op amp B) has a Common-mode range (VCMR) of VSS + 100 mV to VDD – 100 mV.
The MCP6295’s VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL
.
5: All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However,
the other minimum and maximum specifications are measured at 2.4V and or 5.5V.
DS20001812F-page 2
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT VDD/2, VL = VDD/2, RL = 10 kto VL, CL = 60 pF, and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
AC Response
Gain Bandwidth Product
Phase Margin at Unity-Gain
Slew Rate
GBWP
PM
—
—
—
10.0
65
7
—
—
—
MHz
°
G = +1 V/V
SR
V/µs
Noise
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
Eni
eni
ini
—
—
—
4.2
8.7
3
—
—
—
µVP-P
f = 0.1 Hz to 10 Hz
nV/Hz f = 10 kHz
fA/Hz f = 1 kHz
MCP6293/MCP6295 CHIP SELECT (CS) SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT VDD/2, VL = VDD/2, RL = 10 kto VL, CL = 60 pF, and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters
CS Low Specifications
CS Logic Threshold, Low
Sym
Min
Typ
Max
Units
Conditions
VIL
VSS
—
—
0.2 VDD
—
V
CS Input Current, Low
ICSL
0.01
µA
CS = VSS
CS High Specifications
CS Logic Threshold, High
VIH
ICSH
ISS
0.8 VDD
—
VDD
2
V
CS Input Current, High
—
—
—
0.7
µA
µA
µA
CS = VDD
CS = VDD
CS = VDD
GND Current per Amplifier
-0.7
0.01
—
—
Amplifier Output Leakage
—
Dynamic Specifications (Note 1)
CS Low to Valid Amplifier Output,
Turn-on Time
tON
—
4
10
µs
CS Low 0.2 VDD, G = +1 V/V,
V
IN = VDD/2, VOUT = 0.9 VDD/2,
V
DD = 5.0V
CS High to Amplifier Output High-Z
Hysteresis
tOFF
—
—
0.01
0.6
—
—
µs
V
CS High 0.8 VDD, G = +1 V/V,
IN = VDD/2, VOUT = 0.1 VDD/2
V
VHYST
VDD = 5V
Note 1: The input condition (VIN) specified applies to both op amp A and B of the MCP6295. The dynamic specification is tested
at the output of op amp B (VOUTB).
2019 Microchip Technology Inc.
DS20001812F-page 3
MCP6291/1R/2/3/4/5
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.4V to +5.5V and VSS = GND.
Parameters
Temperature Ranges
Sym
Min
Typ
Max
Units
Conditions
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 6L-SOT-23
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 8L-MSOP
Thermal Resistance, 14L-PDIP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
TA
TA
-40
-65
—
—
+125
+150
°C
°C
Note
JA
JA
JA
JA
JA
JA
JA
JA
—
—
—
—
—
—
—
—
256
230
85
—
—
—
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
163
206
70
120
100
Note:
The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
1.1
Test Circuits
CS
The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-2. The bypass
capacitors are laid out according to the rules discussed
in Section 4.6 “Supply Bypass”.
VIL
tON
VIH
tOFF
Hi-Z
Hi-Z
VOUT
VDD
1 µF
0.1 µF
VIN
-0.7 µA
(typical)
-0.7 µA
(typical)
VOUT
RL
RN
RG
-1.0 mA
(typical)
MCP629X
ISS
CL
0.7 µA
(typical)
0.7 µA
(typical)
RF
10 nA
(typical)
VDD/2
ICS
VL
FIGURE 1-2:
Most Non-Inverting Gain Conditions.
AC and DC Test Circuit for
FIGURE 1-1:
Chip Select (CS) pin on the MCP6293 and
MCP6295.
Timing Diagram for the
VDD
1 µF
0.1 µF
VDD/2
VOUT
RL
RN
RG
MCP629X
CL
RF
VIN
VL
FIGURE 1-3:
AC and DC Test Circuit for
Most Inverting Gain Conditions.
DS20001812F-page 4
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 10 k to VL, CL = 60 pF, and CS is tied low.
25%
20%
15%
10%
5%
12%
11%
10%
9%
8%
7%
6%
5%
4%
3%
2%
1%
0%
840 Samples
VCM = VSS
TA = -40°C to +125°C
840 Samples
CM = VSS
V
0%
Input Offset Voltage (mV)
Input Offset Voltage Drift (µV/°C)
FIGURE 2-4:
Input Offset Voltage Drift.
FIGURE 2-1:
Input Offset Voltage.
30%
40%
210 Samples
TA = +125°C
210 Samples
TA = 85°C
25%
20%
15%
10%
5%
35%
30%
25%
20%
15%
10%
5%
0%
0%
0
10
20
30
40
50
60
70
80
90 100
Input Bias Current (pA)
Input Bias Current (pA)
FIGURE 2-5:
Input Bias Current at
FIGURE 2-2:
Input Bias Current at
T = +125 °C.
A
T = +85 °C.
A
800
400
VDD = 5.5V
750
VDD = 2.4V
350
300
250
200
150
100
50
700
650
600
550
500
450
400
350
300
250
200
TA = +125°C
TA
TA
TA
=
=
=
+85°C
+25°C
-40°C
TA
TA
TA
TA
=
=
=
=
-40°C
+25°C
+85°C
+125°C
0
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Common Mode Input Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-6:
Common-mode Input Voltage at V = 5.5V.
Input Offset Voltage vs.
FIGURE 2-3:
Common-mode Input Voltage at V = 2.4V.
Input Offset Voltage vs.
DD
DD
2019 Microchip Technology Inc.
DS20001812F-page 5
MCP6291/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 10 k to VL, CL = 60 pF, and CS is tied low.
700
10,000
VCM = VSS
VCM = VDD
VDD = 5.5V
650
600
550
500
450
400
350
300
250
200
150
100
Representative Part
1,000
100
10
Input Bias Current
Input Offset Current
VDD = 5.5V
VDD = 2.4V
1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
25
35
45
55
65
75
85
95 105 115 125
Ambient Temperature (°C)
FIGURE 2-7:
Input Offset Voltage vs.
FIGURE 2-10:
Input Bias, Input Offset
Output Voltage.
Currents vs. Ambient Temperature.
120
110
110
100
90
CMRR
PSRR-
100
80
CMRR
70
90
PSRR+
60
PSRR
VCM = VSS
80
70
60
50
40
30
20 1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
-50
-25
0
25
50
75
100
125
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Ambient Temperature (°C)
FIGURE 2-8:
CMRR, PSRR vs.
FIGURE 2-11:
CMRR, PSRR vs. Ambient
Frequency.
Temperature.
2.5
55
45
35
25
15
5
TA = +125°C
DD = 5.5V
V
2.0
1.5
Input Bias Current
Input Offset Current
Input Bias Current
1.0
0.5
0.0
-5
TA = +85°C
DD = 5.5V
Input Offset Current
-0.5
-1.0
-15
-25
V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
FIGURE 2-9:
vs. Common-mode Input Voltage at T = +85°C.
Input Bias, Offset Currents
FIGURE 2-12:
vs. Common-mode Input Voltage at
T = +125°C.
Input Bias, Offset Currents
A
A
DS20001812F-page 6
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 10 k to VL, CL = 60 pF, and CS is tied low.
1000
100
10
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
TA = +125°C
TA
TA
TA
=
=
=
+85°C
+25°C
-40°C
VOL - VSS
VDD - VOH
1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
0.01
0.1
1
10
Output Current Magnitude (mA)
FIGURE 2-13:
Quiescent Current vs.
FIGURE 2-16:
Output Voltage Headroom
Power Supply Voltage.
vs. Output Current Magnitude.
120
100
0
16
90
85
80
75
70
65
60
55
50
14
-30
GBWP, VDD = 5.5V
GBWP, VDD = 2.4V
Gain
12
10
8
80
60
40
20
0
-60
Phase
-90
-120
-150
-180
-210
6
4
PM, VDD = 5.5V
PM, VDD = 2.4V
2
0
-20
0.1
1
10 100
1k 10k 100k 1M 10M 100M
-50
-25
0
25
50
75
100
125
Frequency (Hz)
Ambient Temperature (°C)
FIGURE 2-14:
Open-Loop Gain, Phase vs.
FIGURE 2-17:
Gain Bandwidth Product,
Frequency.
Phase Margin vs. Ambient Temperature.
10
12
Falling Edge, VDD = 5.5V
10
VDD = 2.4V
8
6
VDD = 5.5V
V
DD = 2.4V
1
4
Rising Edge, VDD = 5.5V
2
0
VDD = 2.4V
0.1
1k
-50
-25
0
25
50
75
100
125
10k
100k
1M
10M
Frequency (Hz)
Ambient Temperature (°C)
FIGURE 2-15:
Maximum Output Voltage
FIGURE 2-18:
Slew Rate vs. Ambient
Swing vs. Frequency.
Temperature.
2019 Microchip Technology Inc.
DS20001812F-page 7
MCP6291/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 10 k to VL, CL = 60 pF, and CS is tied low.
11
10
9
1,000
100
10
8
f = 10 kHz
VDD = 5.0V
7
6
5
4
3
2
1
0
1
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
0.1
1
10
100
1k
10k
100k
1M
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Common Mode Input Voltage (V)
Frequency (Hz)
FIGURE 2-19:
Input Noise Voltage Density
FIGURE 2-22:
Input Noise Voltage Density
vs. Frequency.
vs. Common-mode Input Voltage at 10 kHz.
35
30
25
20
15
10
5
140
130
120
110
100
TA = +125°C
TA
TA
TA
=
=
=
+85°C
+25°C
-40°C
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
1
10
100
Frequency (kHz)
FIGURE 2-20:
Output Short Circuit Current
FIGURE 2-23:
Channel-to-Channel
vs. Power Supply Voltage.
Separation vs. Frequency (MCP6292, MCP6294
and MCP6295 only).
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.6
VDD = 5.5V
VDD = 2.4V
Op Amp shuts off
Op Amp turns on
Op-Amp shuts off here
Op-Amp turns on here
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Hysteresis
Hysteresis
CS swept
high to low
CS swept
low to high
CS swept
low to high
CS swept
high to low
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
Chip Select Voltage (V)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
FIGURE 2-21:
Quiescent Current vs.
FIGURE 2-24:
Quiescent Current vs.
Chip Select (CS) Voltage at V = 2.4V
Chip Select (CS) Voltage at V = 5.5V
DD
DD
(MCP6293 and MCP6295 only).
(MCP6293 and MCP6295 only).
DS20001812F-page 8
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 10 k to VL, CL = 60 pF, and CS is tied low.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0 0.E+00
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0 0.E+00
G = +1V/V
VDD = 5.0V
G = -1V/V
VDD = 5.0V
1.E-06
2.E-06
3.E-06
4.E-06
5.E-06
6.E-06
7.E-06
8.E-06
9.E-06
1.E-05
1.E-06
2.E-06
3.E-06
4.E-06
5.E-06
6.E-06
7.E-06
8.E-06
9.E-06
1.E-05
Time (1 µs/div)
Time (1 µs/div)
FIGURE 2-25:
Large-Signal Non-inverting
FIGURE 2-28:
Large-Signal Inverting Pulse
Pulse Response.
Response.
G = -1V/V
G = +1V/V
Time (200 ns/div)
Time (200 ns/div)
FIGURE 2-26:
Small-Signal Non-inverting
FIGURE 2-29:
Small-Signal Inverting Pulse
Pulse Response.
Response.
3.0
2.5
2.0
1.5
1.0
0.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
VDD = 2.4V
G = +1V/V
VIN = VSS
VDD = 5.5V
G = +1V/V
VIN = VSS
CS Voltage
CS Voltage
VOUT
Output On
Output On
VOUT
Output High-Z
Output High-Z
0.0 0.E+00
5.E-06
1.E-05
2.E-05
2.E-05
3.E-05
3.E-05
4.E-05
4.E-05
5.E-05
5.E-05
0.0 0.E+00
5.E-06
1.E-05
2.E-05
2.E-05
3.E-05
3.E-05
4.E-05
4.E-05
5.E-05
5.E-05
Time (5 µs/div)
Time (5 µs/div)
FIGURE 2-27:
Chip Select (CS) to
FIGURE 2-30:
Chip Select (CS) to
Amplifier Output Response Time at V = 2.4V
Amplifier Output Response Time at V = 5.5V
DD
DD
(MCP6293 and MCP6295 only).
(MCP6293 and MCP6295 only).
2019 Microchip Technology Inc.
DS20001812F-page 9
MCP6291/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 10 k to VL, CL = 60 pF, and CS is tied low.
1.E1-00m2
6
5
VDD = 5.0V
G = +2V/V
1m
1.E-03
1.E10-004µ
10µ
1.E-05
1µ
1.E-06
100n
1.E- 7
4
VOUT
VIN
3
10n
1.E-08
1n
1.E-09
100p
1.E-10
10p
1.E-11
2
+125°C
+85°C
+25°C
-40°C
1
0
1p
1.E-12
-1 -15
-14
-13
-12
-11
-10
-9
-8
-7
-6
-5
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Time (1 ms/div)
FIGURE 2-31:
Measured Input Current vs.
FIGURE 2-32:
The MCP6291/1R/2/3/4/5
Input Voltage (below V ).
Show No Phase Reversal.
SS
DS20001812F-page 10
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1:
PIN FUNCTION TABLE FOR SINGLE OP AMPS
MCP6291
MCP6293
MCP6291R
Symbol
Description
PDIP, SOIC,
MSOP
PDIP, SOIC,
SOT-23-5
SOT-23-6
MSOP
6
2
1
4
1
4
6
2
1
4
VOUT
Analog Output
VIN
–
+
Inverting Input
3
3
3
3
3
VIN
Non-inverting Input
Positive Power Supply
Negative Power Supply
Chip Select
7
5
2
7
6
VDD
VSS
CS
4
2
5
4
2
—
1,5,8
—
—
—
—
8
5
1,5
—
NC
No Internal Connection
TABLE 3-2:
PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
MCP6292
MCP6294
MCP6295
Symbol
Description
1
2
1
2
—
2
VOUTA
Analog Output (op amp A)
Inverting Input (op amp A)
VINA
–
+
3
3
3
VINA
Non-inverting Input (op amp A)
Positive Power Supply
8
4
8
VDD
5
5
—
6
VINB
+
Non-inverting Input (op amp B)
Inverting Input (op amp B)
Analog Output (op amp B)
Analog Output (op amp C)
Inverting Input (op amp C)
Non-inverting Input (op amp C)
Negative Power Supply
6
6
VINB
–
7
7
7
VOUTB
VOUTC
—
—
—
4
8
—
—
—
4
9
VINC
–
+
10
11
12
13
14
—
—
VINC
VSS
—
—
—
—
—
—
—
—
1
VIND
+
Non-inverting Input (op amp D)
Inverting Input (op amp D)
Analog Output (op amp D)
VIND
–
VOUTD
VOUTA/VINB
CS
+
Analog Output (op amp A)/Non-inverting Input (op amp B)
Chip Select
5
3.1
Analog Outputs
3.4
Chip Select Digital Input
This is a CMOS, Schmitt-triggered input that places the
part into a low power mode of operation.
The output pins are low-impedance voltage sources.
3.2
Analog Inputs
3.5
Power Supply Pins
The non-inverting and inverting inputs are high-
impedance CMOS inputs with low bias currents.
The positive power supply (VDD) is 2.4V to 6.0V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD
.
3.3
MCP6295’s VOUTA/VINB+ Pin
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors
For the MCP6295 only, the output of op amp A is
connected directly to the non-inverting input of
op amp B; this is the VOUTA/VINB+ pin. This connection
makes it possible to provide a Chip Select pin for duals
in 8-pin packages.
2019 Microchip Technology Inc.
DS20001812F-page 11
MCP6291/1R/2/3/4/5
VDD, and dump any currents onto VDD. When
implemented as shown, resistors R1 and R2 also limit
the current through D1 and D2.
4.0
APPLICATION INFORMATION
The MCP6291/1R/2/3/4/5 family of op amps is
manufactured using Microchip’s state of the art CMOS
process, specifically designed for low-cost, low-power
and general purpose applications. The low supply
voltage, low quiescent current and wide bandwidth
makes the MCP6291/1R/2/3/4/5 ideal for battery-pow-
ered applications.
VDD
D1
V1
+
4.1
Rail-to-Rail Inputs
R1
D2
VOUT
MCP629X
–
V2
4.1.1
PHASE REVERSAL
R2
The MCP6291/1R/2/3/4/5 op amp is designed to
prevent phase reversal when the input pins exceed the
supply voltages. Figure 2-32 shows the input voltage
exceeding the supply voltage without any phase rever-
sal.
VSS – (minimum expected V1)
R1 >
R2 >
2 mA
VSS – (minimum expected V2)
2 mA
4.1.2
INPUT VOLTAGE AND CURRENT
LIMITS
FIGURE 4-2:
Inputs.
Protecting the Analog
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
It is also possible to connect the diodes to the left of the
resistor R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs when the Common-mode voltage (VCM) is below
ground (VSS); see Figure 2-31. Applications that are
high impedance may need to limit the usable voltage
range.
Bond
VDD
Pad
4.1.3
NORMAL OPERATION
The input stage of the MCP6291/1R/2/3/4/5 op amps
use two differential CMOS input stages in parallel. One
operates at low Common-mode input voltage (VCM),
while the other operates at high VCM. With this topol-
ogy, the device operates with VCM up to 0.3V past
either supply rail. The input offset voltage (VOS) is mea-
sured at VCM = VSS - 0.3V and VDD + 0.3V to ensure
proper operation.
Bond
Pad
Bond
Pad
Input
Stage
VIN+
VIN–
Bond
Pad
VSS
The transition between the two input stages occurs
when VCM = VDD - 1.1V. For the best distortion and gain
linearity, with non-inverting gains, avoid this region of
operation.
FIGURE 4-1:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must limit the
currents and voltages at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-2
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pins. Diodes D1 and D2 prevent the
input pins (VIN+ and VIN–) from going too far above
4.2
Rail-to-Rail Output
The output voltage range of the MCP6291/1R/2/3/4/5
op amp is VDD – 15 mV (min.) and VSS + 15 mV
(maximum) when RL = 10 k is connected to VDD/2
and VDD = 5.5V. Refer to Figure 2-16 for more
information.
DS20001812F-page 12
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
4.3
Capacitive Loads
4.4
MCP629X Chip Select
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
The MCP6293 and MCP6295 are single and dual op
amps with Chip Select (CS), respectively. When CS is
pulled high, the supply current drops to 0.7 µA (typical)
and flows through the CS pin to VSS. When this
happens, the amplifier output is put into a high-imped-
ance state. By pulling CS low, the amplifier is enabled.
The CS pin has an internal 5 M (typical) pull-down
resistor connected to VSS, so it will go low if the CS pin
is left floating. Figure 1-1 shows the output voltage and
supply current response to a CS pulse.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
4.5
Cascaded Dual Op Amps
(MCP6295)
The MCP6295 is a dual op amp with Chip Select (CS).
The Chip Select input is available on what would be the
non-inverting input of a standard dual op amp (pin 5).
This is available because the output of op amp A
connects to the non-inverting input of op amp B, as
shown in Figure 4-5. The Chip Select input, which can
be connected to a microcontroller I/O line, puts the
device in Low-power mode. Refer to Section 4.4
“MCP629X Chip Select”.
–
RISO
MCP629X
+
VOUT
VIN
CL
VINB–
VOUTA/VINB+
1
FIGURE 4-3:
Output Resistor, R
ISO
6
stabilizes large capacitive loads.
2
3
7
VINA–
VINA+
Figure 4-4 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
VOUTB
B
A
MCP6295
5
CS
100
FIGURE 4-5:
Cascaded Gain Amplifier.
The output of op amp A is loaded by the input imped-
ance of op amp B, which is typically 10136 pF, as
specified in the DC specification table (Refer to
Section 4.3 “Capacitive Loads” for further details
regarding capacitive loads).
GN = 1 V/V
GN 2 V/V
The Common-mode input range of these op amps is
specified in the data sheet as VSS – 300 mV and
VDD + 300 mV. However, since the output of op amp A
is limited to VOL and VOH (20 mV from the rails with a
10 k load), the non-inverting input range of op amp B
is limited to the Common-mode input range of
VSS + 20 mV and VDD – 20 mV.
10
10
100
1,000
10,000
Normalized Load Capacitance; CL/GN (pF)
FIGURE 4-4:
for Capacitive Loads.
Recommended R
Values
ISO
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO's value until the
response is reasonable. Bench evaluation and
simulations with the MCP6291/1R/2/3/4/5 SPICE
macro model are helpful.
2019 Microchip Technology Inc.
DS20001812F-page 13
MCP6291/1R/2/3/4/5
4.6
Supply Bypass
4.8
PCB Surface Leakage
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with nearby analog parts.
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface-leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6291/1R/2/3/4/5 family’s bias current at 25°C
(1 pA, typical).
4.7
Unused Op Amps
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-7.
An unused op amp in a quad package (MCP6294)
should be configured as shown in Figure 4-6. These
circuits prevent the output from toggling and causing
crosstalk. Circuits A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
VIN–
VIN+
VSS
¼ MCP6294 (A)
VDD
¼ MCP6294 (B)
VDD
Guard Ring
Example Guard Ring Layout
VDD
R1
R2
+
–
FIGURE 4-7:
for Inverting Gain.
+
VREF
–
1. For Inverting Gain and Transimpedance
Amplifiers (convert current to voltage, such as
photo detectors):
R2
------------------
VREF = VDD
a.Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
R1 + R2
FIGURE 4-6:
Unused Op Amps.
b.Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
2. Non-inverting Gain and Unity-Gain Buffer:
a.Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b.Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
Common-mode input voltage.
DS20001812F-page 14
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
4.9.3
CASCADED OP AMP
APPLICATIONS
4.9
Application Circuits
4.9.1
MULTIPLE FEEDBACK LOW-PASS
FILTER
The MCP6295 provides the flexibility of Low-power
mode for dual op amps in an 8-pin package. The
MCP6295 eliminates the added cost and space in
battery-powered applications by using two single op
amps with Chip Select lines or a 10-pin device with one
Chip Select line for both op amps. Since the two op
amps are internally cascaded, this device cannot be
used in circuits that require active or passive elements
between the two op amps. However, there are several
applications where this op amp configuration with
Chip Select line becomes suitable. The circuits below
show possible applications for this device.
The MCP6291/1R/2/3/4/5 op amp can be used in
active-filter applications. Figure 4-8 shows an inverting,
third-order, multiple feedback low-pass filter that can be
used as an anti-aliasing filter.
R1
R2
C3
R4
VOUT
VIN
R3
C1
C4
4.9.3.1
Load Isolation
–
With the cascaded op amp configuration, op amp B can
be used to isolate the load from op amp A. In applica-
tions where op amp A is driving capacitive or low
resistance loads in the feedback loop (such as an
integrator circuit or filter circuit), the op amp may not
have sufficient source current to drive the load. In this
case, op amp B can be used as a buffer.
MCP6291
VDD/2
+
FIGURE 4-8:
Pass Filter.
Multiple Feedback Low-
This filter, and others, can be designed using
Microchip’s Filter design software (refer to Section 5.0
“Design Aids”).
–
VOUTB
Load
–
+
B
4.9.2
PHOTODIODE AMPLIFIER
+
A
Figure 4-9 shows a photodiode biased in the photovol-
taic mode for high precision. The resistor R converts
the diode current ID to the voltage VOUT. The capacitor
is used to limit the bandwidth or to stabilize the circuit
against the diode’s capacitance (it is not always
needed).
MCP6295
CS
FIGURE 4-10:
Isolating the Load with a
Buffer.
C
R
ID
VOUT
–
light
MCP6291
VDD/2
+
FIGURE 4-9:
Photodiode Amplifier.
2019 Microchip Technology Inc.
DS20001812F-page 15
MCP6291/1R/2/3/4/5
4.9.3.2
Cascaded Gain
4.9.3.4
Buffered Non-inverting Integrator
Figure 4-11 shows a cascaded gain circuit configura-
tion with Chip Select. Op amps A and B are configured
in a non-inverting amplifier configuration. In this config-
uration, it is important to note that the input offset volt-
age of op amp A is amplified by the gain of op amp A
and B, as shown below:
Figure 4-13 shows a lossy non-inverting integrator that
is buffered and has a Chip Select input. Op amp A is
configured as a non-inverting integrator. In this config-
uration, matching the impedance at each input is
recommended. RF is used to provide a feedback loop
at frequencies << 1/(2R1C1) and makes this a lossy
integrator (it has a finite gain at DC). Op amp B is used
to isolate the load from the integrator.
VOUT = VINGAGB + VOSAGAGB + VOSBGB
Where:
R2
C2
GA
GB
=
=
=
=
op amp A gain
op amp B gain
RF
–
+
–
+
VOUT
B
VOSA
VOSB
op amp A input offset voltage
op amp B input offset voltage
R1
A
VIN
MCP6295
C1
Therefore, it is recommended to set most of the gain
with op amp A and use op amp B with relatively small
gain (e.g., a unity-gain buffer).
CS
R1C1 = R2 RFC2
R4
R3
R2
R1
FIGURE 4-13:
Buffered Non-inverting
Integrator with Chip Select.
4.9.3.5 Inverting Integrator with Active
–
Compensation and Chip Select
VOUT
–
+
B
+
A
Figure 4-14 uses an active compensator (op amp B) to
compensate for the non-ideal op amp characteristics
introduced at higher frequencies. This circuit uses
op amp B as a unity-gain buffer to isolate the
integration capacitor C1 from op amp A and drives the
capacitor with low-impedance source. Since both op
amps are matched very well, they provide a high quality
integrator.
VIN
MCP6295
CS
FIGURE 4-11:
Configuration.
Cascaded Gain Circuit
4.9.3.3
Difference Amplifier
C1
R1
Figure 4-12 shows op amp A as a difference amplifier
with Chip Select. In this configuration, it is
recommended to use well-matched resistors (e.g.,
0.1%) to increase the Common-mode Rejection Ratio
(CMRR). Op amp B can be used for additional gain or
as a unity-gain buffer to isolate the load from the
difference amplifier.
VIN
B
–
+
–
+
VOUT
A
MCP6295
R4
R3
CS
R2
R2
R1
A
VIN2
FIGURE 4-14:
Compensation.
Integrator Circuit with Active
–
–
+
VOUT
B
+
VIN1
MCP6295
R1
CS
FIGURE 4-12:
Difference Amplifier Circuit.
DS20001812F-page 16
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
4.9.3.6
Second-Order MFB Low-Pass Filter
with an Extra Pole-Zero Pair
4.9.3.8
Capacitorless Second-Order
Low-Pass filter with Chip Select
Figure 4-15 is a second-order multiple feedback low-
pass filter with Chip Select. Use the FilterLab® software
from Microchip to determine the R and C values for the
op amp A’s second-order filter. Op amp B can be used
to add a pole-zero pair using C3, R6 and R7.
The low-pass filter shown in Figure 4-17 does not
require external capacitors and uses only three
external resistors; the op amp’s GBWP sets the corner
frequency. R1 and R2 are used to set the circuit gain
and R3 is used to set the Q. To avoid gain peaking in
the frequency response, Q needs to be low (lower
values need to be selected for R3). Note that the
amplifier bandwidth varies greatly over temperature
and process. However, this configuration provides a
low cost solution for applications with high bandwidth
requirements.
R6
C3
R7
R1
C1
A
R3
C2
R2
–
VIN
VOUT
–
+
B
+
R5
R4
R2
R1
MCP6295
VIN
R3
CS
–
+
A
+
FIGURE 4-15:
Second-Order Multiple
Feedback Low-Pass Filter with an Extra Pole-
Zero Pair.
VOUT
B
–
VREF
MCP6295
4.9.3.7
Second-Order Sallen-Key Low-Pass
Filter with an Extra Pole-Zero Pair
CS
FIGURE 4-17:
Low-Pass Filter with Chip Select.
Capacitorless Second-Order
Figure 4-16 is a second-order, Sallen-Key low-pass
filter with Chip Select. Use the FilterLab® software from
Microchip to determine the R and C values for the op
amp A’s second-order filter. Op amp B can be used to
add a pole-zero pair using C3, R5 and R6.
C3
R2
R1
A
R5
R6
–
+
VOUT
–
+
B
R4
R3
VIN
MCP6295
C1
C2
CS
FIGURE 4-16:
Second-Order Sallen-Key
Low-Pass Filter with an Extra Pole-Zero Pair and
Chip Select.
2019 Microchip Technology Inc.
DS20001812F-page 17
MCP6291/1R/2/3/4/5
5.5
Analog Demonstration and
Evaluation Boards
5.0
DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP6291/1R/2/3/4/5 family of op amps.
Microchip offers a broad spectrum of Analog Demon-
stration and Evaluation Boards that are designed to
help you achieve faster time to market. For a complete
listing of these boards and their corresponding user’s
guides and technical information, visit the Microchip
web site at www.microchip.com/analogtools.
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP6291/1R/2/
3/4/5 op amps is available on the Microchip web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See
the model file for information on its capabilities.
Two of our boards that are especially useful are:
• P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP
Evaluation Board
• P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evalu-
ation Board
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.6
Application Notes
The following Microchip Application Notes are avail-
able on the Microchip web site at www.microchip. com/
appnotes and are recommended as supplemental ref-
erence resources.
5.2
FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
ADN003: “Select the Right Operational Amplifier for
your Filtering Circuits,” DS21821
AN722: “Operational Amplifier Topologies and DC
Specifications,” DS00722
AN723: “Operational Amplifier AC Specifications and
Applications,” DS00723
AN884: “Driving Capacitive Loads With Op Amps,”
DS00884
5.3
Mindi™ Simulator Tool
AN990: “Analog Sensor Conditioning Circuits – An
Overview,” DS00990
Microchip’s Mindi™ simulator tool aids in the design of
various circuits useful for active filter, amplifier and
power-management applications. It is a free online
simulation tool available from the Microchip web site at
www.microchip.com/mindi. This interactive simulator
enables designers to quickly generate circuit diagrams,
simulate circuits. Circuits developed using the Mindi
simulation tool can be downloaded to a personal
computer or workstation.
These application notes and others are listed in the
design guide:
“Signal Chain Design Guide,” DS21825
5.4
MAPS (Microchip Advanced Part
Selector)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip web site at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparison
reports. Helpful links are also provided for Data sheets,
Purchase, and Sampling of Microchip parts.
DS20001812F-page 18
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
5-Lead SOT-23 (MCP6291 and MCP6291R)
Example:
Device
Code
MCP6291
CJNN
EVNN
XXNN
CJ25
MCP6291R
Note: Applies to 5-Lead SOT-23
Example:
6-Lead SOT-23 (MCP6283)
Device
MCP6293
Code
CMNN
XXNN
CM25
Note: Applies to 6-Lead SOT-23
8-Lead MSOP
Example:
6291E
436256
8-Lead PDIP (300 mil)
Example:
XXXXXXXX
XXXXXNNN
MCP6291
MCP6291
E/P256
0743
e
3
E/P256
OR
YYWW
0436
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2019 Microchip Technology Inc.
DS20001812F-page 19
MCP6291/1R/2/3/4/5
Package Marking Information (Continued)
8-Lead SOIC (150 mil)
Example:
XXXXXXXX
XXXXYYWW
MCP6291
E/SN0436
MCP6291E
e
3
SN^0743
OR
NNN
256
256
14-Lead PDIP (300 mil) (MCP6294)
Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
MCP6294-E/P
0436256
YYWWNNN
MCP6294
OR
E/P^
e
3
0743256
14-Lead SOIC (150 mil) (MCP6294)
Example:
XXXXXXXXXX
XXXXXXXXXX
MCP6294ESL
0436256
YYWWNNN
MCP6294
OR
E/SL^
e3
0436256
Example:
14-Lead TSSOP (MCP6294)
XXXXXX
YYWW
6294EST
0436
NNN
256
DS20001812F-page 20
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.20 C 2X
D
e1
A
D
N
E/2
E1/2
E1
E
(DATUM D)
(DATUM A-B)
0.15 C D
2X
NOTE 1
1
2
e
B
NX b
0.20
C A-B D
TOP VIEW
A
A2
A1
A
0.20 C
SEATING PLANE
A
SEE SHEET 2
C
SIDE VIEW
Microchip Technology Drawing C04-091-OT Rev E Sheet 1 of 2
2019 Microchip Technology Inc.
DS20001812F-page 21
MCP6291/1R/2/3/4/5
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
c
T
L
L1
VIEW A-A
SHEET 1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
5
0.95 BSC
Outside lead pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
e1
A
A2
A1
E
E1
D
L
1.90 BSC
0.90
0.89
-
-
-
-
1.45
1.30
0.15
2.80 BSC
1.60 BSC
2.90 BSC
0.30
-
0.60
Footprint
Foot Angle
Lead Thickness
Lead Width
L1
0.60 REF
I
0°
0.08
0.20
-
-
-
10°
0.26
0.51
c
b
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-091-OT Rev E Sheet 2 of 2
DS20001812F-page 22
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X
SILK SCREEN
5
Y
Z
C
G
1
2
E
GX
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
0.95 BSC
2.80
MAX
Contact Pitch
E
C
Contact Pad Spacing
Contact Pad Width (X5)
Contact Pad Length (X5)
Distance Between Pads
Distance Between Pads
Overall Width
X
Y
G
GX
Z
0.60
1.10
1.70
0.35
3.90
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091B [OT]
2019 Microchip Technology Inc.
DS20001812F-page 23
MCP6291/1R/2/3/4/5
6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.15 C A-B
D
e1
A
D
E
2
E1
E
E1
2
2X
0.15 C D
2X
0.20 C A-B
e
B
6X b
0.20
C A-B D
TOP VIEW
A2
A
C
SEATING PLANE
6X
A1
c
0.10 C
SIDE VIEW
R1
R
L2
GAUGE PLANE
Ĭ
L
(L1)
END VIEW
Microchip Technology Drawing C04-028C (CH) Sheet 1 of 2
DS20001812F-page 24
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Leads
Pitch
N
e
6
0.95 BSC
Outside lead pitch
Overall Height
Molded Package Thickness
Standoff
e1
A
A2
A1
E
E1
D
L
1.90 BSC
0.90
0.89
0.00
-
1.45
1.30
0.15
1.15
-
2.80 BSC
1.60 BSC
2.90 BSC
0.45
Overall Width
Molded Package Width
Overall Length
Foot Length
0.30
0.60
Footprint
Seating Plane to Gauge Plane
Foot Angle
Lead Thickness
Lead Width
L1
L1
φ
c
b
0.60 REF
0.25 BSC
-
0°
0.08
0.20
10°
0.26
0.51
-
-
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-028C (CH) Sheet 2 of 2
2019 Microchip Technology Inc.
DS20001812F-page 25
MCP6291/1R/2/3/4/5
6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
GX
Y
Z
C
G
G
SILK SCREEN
X
E
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
0.95 BSC
2.80
MAX
Contact Pitch
E
C
Contact Pad Spacing
Contact Pad Width (X3)
Contact Pad Length (X3)
Distance Between Pads
Distance Between Pads
Overall Width
X
Y
G
GX
Z
0.60
1.10
1.70
0.35
3.90
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2028B (CH)
DS20001812F-page 26
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019 Microchip Technology Inc.
DS20001812F-page 27
MCP6291/1R/2/3/4/5
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001812F-page 28
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019 Microchip Technology Inc.
DS20001812F-page 29
MCP6291/1R/2/3/4/5
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
N
B
E1
NOTE 1
1
2
TOP VIEW
E
A2
A
C
PLANE
L
c
A1
e
eB
8X b1
8X b
.010
C
SIDE VIEW
END VIEW
Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2
DS20001812F-page 30
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ALTERNATE LEAD DESIGN
(NOTE 5)
DATUM A
DATUM A
b
b
e
2
e
2
e
e
Units
Dimension Limits
INCHES
NOM
8
.100 BSC
-
MIN
MAX
Number of Pins
Pitch
N
e
A
Top to Seating Plane
-
.210
.195
-
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
A2
A1
E
E1
D
L
c
b1
b
eB
.115
.015
.290
.240
.348
.115
.008
.040
.014
-
.130
-
.310
.250
.365
.130
.010
.060
.018
-
.325
.280
.400
.150
.015
.070
.022
.430
Lower Lead Width
Overall Row Spacing
§
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
5. Lead design above seating plane may vary, based on assembly vendor.
Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2
2019 Microchip Technology Inc.
DS20001812F-page 31
MCP6291/1R/2/3/4/5
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
1
2
NOTE 1
e
NX b
0.25
C A–B D
B
NOTE 5
TOP VIEW
0.10 C
0.10 C
C
A2
A
SEATING
PLANE
8X
SIDE VIEW
A1
h
R0.13
R0.13
h
H
0.23
L
SEE VIEW C
(L1)
VIEW A–A
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2
DS20001812F-page 32
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
8
1.27 BSC
Overall Height
Molded Package Thickness
Standoff
Overall Width
A
-
-
-
-
1.75
-
0.25
A2
A1
E
1.25
0.10
§
6.00 BSC
Molded Package Width
Overall Length
E1
D
3.90 BSC
4.90 BSC
Chamfer (Optional)
Foot Length
h
L
0.25
0.40
-
-
0.50
1.27
Footprint
L1
1.04 REF
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
0°
0.17
0.31
5°
-
-
-
-
-
8°
c
b
0.25
0.51
15°
5°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2
2019 Microchip Technology Inc.
DS20001812F-page 33
MCP6291/1R/2/3/4/5
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Contact Pitch
E
C
X1
Y1
1.27 BSC
5.40
Contact Pad Spacing
Contact Pad Width (X8)
Contact Pad Length (X8)
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev E
DS20001812F-page 34
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
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2019 Microchip Technology Inc.
DS20001812F-page 35
MCP6291/1R/2/3/4/5
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
NOTE 5
A
D
E
N
E
2
E2
2
E1
2X
0.10 C D
NOTE 1
2X N/2 TIPS
0.20 C
1
2
3
e
NX b
0.25
C A–B D
0.10 C
NOTE 5
B
TOP VIEW
C
A2
A
SEATING
PLANE
14X
0.10 C
SIDE VIEW
A1
h
h
R0.13
H
R0.13
c
SEE VIEW C
L
VIEW A–A
(L1)
VIEW C
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 1 of 2
DS20001812F-page 36
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
14
1.27 BSC
Overall Height
Molded Package Thickness
Standoff
Overall Width
A
-
-
-
-
1.75
-
0.25
A2
A1
E
1.25
0.10
§
6.00 BSC
Molded Package Width
Overall Length
Chamfer (Optional)
Foot Length
E1
D
h
3.90 BSC
8.65 BSC
0.25
0.40
-
-
0.50
1.27
L
Footprint
L1
1.04 REF
Lead Angle
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
0°
0°
0.10
0.31
5°
-
-
-
-
-
-
-
8°
0.25
0.51
15°
15°
c
b
5°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimension D does not include mold flash, protrusions or gate burrs, which shall
not exceed 0.15 mm per end. Dimension E1 does not include interlead flash
or protrusion, which shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 2 of 2
2019 Microchip Technology Inc.
DS20001812F-page 37
MCP6291/1R/2/3/4/5
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
14
SILK SCREEN
C
Y
1
2
X
E
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
1.27 BSC
5.40
MAX
Contact Pitch
Contact Pad Spacing
Contact Pad Width (X14)
E
C
X
0.60
1.55
Contact Pad Length (X14)
Y
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2065-SL Rev D
DS20001812F-page 38
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019 Microchip Technology Inc.
DS20001812F-page 39
MCP6291/1R/2/3/4/5
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001812F-page 40
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019 Microchip Technology Inc.
DS20001812F-page 41
MCP6291/1R/2/3/4/5
NOTES:
DS20001812F-page 42
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
APPENDIX A: REVISION HISTORY
Revision F (November 2019)
The following is the list of modifications:
1. Updated Section 6.0 “Packaging Informa-
tion”.
Revision E (November 2007)
The following is the list of modifications:
1. Updated notes to Section 1.0 “Electrical Char-
acteristics”. Increased absolute maximum volt-
age range of input pins. Increased maximum
operating supply voltage (VDD).
2. Added Test Circuits.
3. Added Figure 2-31 and Figure 2-32.
4. Added Section 4.1.1 “Phase Reversal”,
Section 4.1.2 “Input Voltage and Current
Limits”, and Section 4.1.3 “Normal Opera-
tion”.
5. Added Section 4.7 “Unused Op Amps”.
6. Updated Section 5.0 “Design Aids”.
7. Corrected Package Markings.
8. Updated Package Outline Drawing.
Revision D (December 2004)
The following is the list of modifications:
1. Added SOT-23-5 packages for the MCP6291
and MCP6291R single op amps.
2. Added SOT-23-6 package for the MCP6293
single op amp.
3. Added Section 3.0 “Pin Descriptions”.
4. Corrected application circuits (Section 4.9
“Application Circuits”).
5. Added SOT-23-5 and SOT-23-6 packages and
corrected
package
marking
information
(Section 6.0 “Packaging Information”).
6. Added Appendix A: Revision History.
Revision C (June 2004)
• Undocumented changes.
Revision B (October 2003)
• Undocumented changes.
Revision A (June 2003)
• Original data sheet release.
2019 Microchip Technology Inc.
DS20001812F-page 43
MCP6291/1R/2/3/4/5
NOTES:
DS20001812F-page 44
2019 Microchip Technology Inc.
MCP6291/1R/2/3/4/5
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
X
/XX
–
a) MCP6291-E/SN: Extended Tem-
perature,
Temperature
Range
Package
8 lead SOIC package.
b) MCP6291-E/MS:Extended
perature,
Tem-
Device:
MCP6291:
MCP6291T:
Single Op Amp
Single Op Amp
(Tape and Reel)
(SOIC, MSOP, SOT-23-5)
Single Op Amp
8 lead MSOP package.
c) MCP6291-E/P:Extended Tempera-
MCP6291RT:
(Tape and Reel) (SOT-23-5)
Dual Op Amp
Dual Op Amp
ture,
MCP6292:
MCP6292T:
8 lead PDIP package.
(Tape and Reel) (SOIC, MSOP)
Single Op Amp with Chip Select
Single Op Amp with Chip Select
(Tape and Reel)
d) MCP6291T-E/OT:Tape and Reel,
Extended Temperature,
MCP6293:
MCP6293T:
5 lead SOT-23 package.
(SOIC, MSOP, SOT-23-6)
Quad Op Amp
Quad Op Amp
e) MCP6291RT-E/OT:Tape and Reel,
Extended Temperature,
MCP6294:
MCP6294T:
(Tape and Reel) (SOIC, TSSOP)
Dual Op Amp with Chip Select
Dual Op Amp with Chip Select
(Tape and Reel) (SOIC, MSOP)
5 lead SOT-23 package.
MCP6295:
MCP6295T:
a) MCP6292-E/SN:Extended
perature,
Tem-
Tem-
8 lead SOIC package.
Temperature Range:
Package:
E
=
-40° C to +125° C
b) MCP6292-E/MS:Extended
perature,
OT
CH
=
=
Plastic Small Outline Transistor (SOT-23), 5-lead
(MCP6291, MCP6291R)
Plastic Small Outline Transistor (SOT-23), 6-lead
(MCP6293)
8 lead MSOP package.
c) MCP6292-E/P:Extended Tempera-
ture,
MS
P
SN
SL
ST
=
=
=
=
=
Plastic MSOP, 8-lead
Plastic DIP (300 mil body), 8-lead, 14-lead
Plastic SOIC, (3.90 mm body), 8-lead
Plastic SOIC (3.90 mm body), 14-lead
Plastic TSSOP (4.4 mm body), 14-lead
8 lead PDIP package.
d) MCP6292T-E/SN:Tape and Reel,
Extended Temperature,
8 lead SOIC package.
a) MCP6293-E/SN:Extended
perature,
Tem-
Tem-
8 lead SOIC package.
b) MCP6293-E/MS:Extended
perature,
8 lead MSOP package.
2019 Microchip Technology Inc.
DS20001812F-page 45
MCP6291/1R/2/3/4/5
NOTES:
DS20001812F-page 46
2019 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-5298-0
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2019 Microchip Technology Inc.
DS20001812F-page 47
Worldwide Sales and Service
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DS20001812F-page 48
2019 Microchip Technology Inc.
05/14/19
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