MCP6422-E/MS [MICROCHIP]
OP-AMP;
| 型号： | MCP6422-E/MS |
| 厂家： | 
MICROCHIP |
| 描述： | OP-AMP 放大器 光电二极管 |
| 文件： | 总46页 (文件大小：3822K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP6421/2/4
4.4 µA/Amplifier, 90 kHz Op Amp
Features:
Description:
The Microchip Technology Inc. MCP6421/2/4 family of
operational amplifiers operate with a single supply
voltage as low as 1.8V, while drawing low quiescent
current per amplifier (5.5 µA, maximum). This family
also has low-input offset voltage (±1.0 mV, maximum)
and rail-to-rail input and output operation. In addition,
the MCP6421/2/4 family is unity gain stable and has a
gain bandwidth product of 90 kHz (typical). This
combination of features supports battery-powered and
portable applications. The MCP6421/2/4 family has
enhanced EMI protection to minimize any
electromagnetic interference from external sources.
This feature makes it well suited for EMI sensitive
applications such as power lines, radio stations, and
mobile communications, etc.
• Low Quiescent Current:
- 4.4 µA/amplifier (typical)
• Low Input Offset Voltage:
- ±1.0 mV (maximum)
• Enhanced EMI Protection:
- Electromagnetic Interference Rejection Ratio
(EMIRR) at 1.8 GHz: 97 dB
• Supply Voltage Range: 1.8V to 5.5V
• Gain Bandwidth Product: 90 kHz (typical)
• Rail-to-Rail Input/Output
• Slew Rate: 0.05 V/µs (typical)
• Unity Gain Stable
• No Phase Reversal
• Small Packages:
The MCP6421/2/4 family is offered in single
(MCP6421), dual (MCP6422) and quad (MCP6424)
packages. All devices are designed using an advanced
CMOS process and fully specified in extended
temperature range from -40°C to +125°C.
- Singles in SC70-5, SOT-23-5
- Dual in MSOP-8, SOIC-8
- Quad in SOIC-14, TSSOP-14
• Extended Temperature Range:
- -40°C to +125°C
Typical Application
VDD
Applications:
R
VDD
3
R+¨R
R-¨R
100k
MCP6421
• Portable Medical Instruments
• Safety Monitoring
• Battery-Powered Systems
• Remote Sensing
• Supply Current Sensing
• Analog Active Filters
-
R
1
VDD
+
1k
VOUT
MCP6421
V
b
-
V
a
+
VDD
R
2
1k
R
5
-
100k
+
R-¨R R+¨R
Design Aids:
MCP6421
• SPICE Macro Models
100k
VOUT = Va – Vb ----------------
1k
• FilterLab® Software
Strain Gauge
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
• Application Notes
Package Types
MCP6424
SOIC, TSSOP
MCP6422
MSOP, SOIC
MCP6421
SC70-5, SOT-23-5
V
1
2
3
4
5
6
7
14
13
12
11
10
9
VOUTA
OUTD
VOUTA
VDD
1
2
8
7
VOUT
VSS
1
2
3
5
VDD
V
V
V
–
VINA
VINA
–
+
IND
VINA
–
VOUTB
+
IND
VINA+ 3
VSS
6 VINB
5
VINB
–
+
VDD
4
VIN+
VIN–
SS
4
V
+
VINB
VINB
+
–
INC
VINC
–
VOUTC
8
VOUTB
2013 Microchip Technology Inc.
DS20005165B-page 1
MCP6421/2/4
NOTES:
DS20005165B-page 2
2013 Microchip Technology Inc.
MCP6421/2/4
1.0
1.1
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
VDD – VSS ..................................................................................................................................................................6.5V
Current at Analog Input Pins (VIN+, VIN-)................................................................................................................±2 mA
Analog Inputs (VIN+, VIN-)††.....................................................................................................VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ....................................................................................................VSS – 0.3V to VDD + 0.3V
Difference Input Voltage .................................................................................................................................|VDD – VSS
|
Output Short-Circuit Current ..........................................................................................................................Continuous
Current at Input Pins...............................................................................................................................................±2 mA
Current at Output and Supply Pins ......................................................................................................................±30 mA
Storage Temperature ..............................................................................................................................-65°C to +150°C
Maximum Junction Temperature (TJ).................................................................................................................... +150°C
ESD Protection on All Pins (HBM; MM) 4 kV; 400V
ESD Protection on All Pins (HBM; MM) (Dual and Quad) 4 kV; 300V
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
†† See Section 4.1.2 “Input Voltage Limits”.
1.2
Specifications
DC ELECTRICAL SPECIFICATIONS
TABLE 1-1:
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS= GND, VCM = VDD/2,
VOUT = VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 30 pF (refer to Figure 1-1).
Parameters
Input Offset
Input Offset Voltage
Sym.
Min.
Typ.
Max.
Units
Conditions
VOS
-1.0
—
—
1.0
—
mV
VDD = 3.0V; VCM = VDD/4
Input Offset Drift with Temperature VOS/TA
±3.0
µV/°C TA= -40°C to +125°C,
VCM = VSS
Power Supply Rejection Ratio
Input Bias Current and Impedance
Input Bias Current
PSRR
IB
75
90
—
dB
VCM = VSS
—
—
—
—
—
—
±1
20
50
—
—
—
—
—
pA
pA
TA = +85°C
800
pA
TA = +125°C
Input Offset Current
IOS
ZCM
±1
pA
Common Mode Input Impedance
Differential Input Impedance
Common Mode
1013||12
1013||12
||pF
|pF
ZDIFF
Common Mode Input Voltage
Range
VCMR
VSS – 0.3
—
90
85
VDD + 0.3
V
Common Mode Rejection Ratio
CMRR
75
70
—
—
dB
dB
VDD = 5.5V
VCM = -0.3V to 5.8V
VDD = 1.8V
VCM = -0.3V to 2.1V
2013 Microchip Technology Inc.
DS20005165B-page 3
MCP6421/2/4
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS= GND, VCM = VDD/2,
VOUT = VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 30 pF (refer to Figure 1-1).
Parameters
Open-Loop Gain
Sym.
Min.
Typ.
Max.
Units
Conditions
DC Open-Loop Gain
(Large Signal)
AOL
95
115
—
dB
0.3 < VOUT < (VDD –0.3V)
VCM= VSS
VDD = 5.5V
Output
High-Level Output Voltage
VOH
VOL
ISC
VDD – 4 VDD – 1
VDD – 5 VDD – 1
—
—
mV
mV
mV
mV
mA
mA
VDD = 1.8V
VDD = 5.5V
VDD = 1.8V
VDD = 5.5V
VDD = 1.8V
VDD = 5.5V
Low-Level Output Voltage
Output Short-Circuit Current
—
—
—
—
VSS + 1
VSS + 4
VSS + 5
—
VSS + 1
±6
±22
—
Power Supply
Supply Voltage
VDD
IQ
1.8
3
—
5.5
5.5
V
Quiescent Current per Amplifier
4.4
µA
IO = 0, VCM = VDD/4
TABLE 1-2:
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS= GND, VCM = VDD/2,
VOUT = VDD/2, VL = VDD/2, RL = 100 k to VL and CL = 30 pF (refer to Figure 1-1).
Parameters
AC Response
Sym.
Min.
Typ.
Max.
Units
Conditions
Gain Bandwidth Product
Phase Margin
GBWP
PM
—
—
—
90
55
—
—
—
kHz
°
G = +1 V/V
Slew Rate
SR
0.05
V/µs
Noise
Input Noise Voltage
Input Noise Voltage Density
Eni
eni
—
—
—
—
—
15
95
90
0.6
77
—
—
—
—
—
µVP-P
f = 0.1 Hz to 10 Hz
nV/Hz f = 1 kHz
nV/Hz f = 10 kHz
fA/Hz f = 1 kHz
Input Noise Current Density
ini
Electromagnetic Interference
Rejection Ratio
EMIRR
dB
V
IN = 100 mVPK
400 MHz
VIN = 100 mVPK
,
,
,
,
—
—
—
92
97
99
—
—
—
900 MHz
VIN = 100 mVPK
1800 MHz
VIN = 100 mVPK
2400 MHz
DS20005165B-page 4
2013 Microchip Technology Inc.
MCP6421/2/4
TABLE 1-3:
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND.
Parameters
Temperature Ranges
Sym.
Min.
Typ.
Max.
Units
Conditions
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 5L-SC70
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 8L-MSOP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
TA
TA
-40
-65
—
—
+125
+150
°C
°C
Note 1
JA
JA
JA
JA
JA
JA
—
—
—
—
—
—
331
221
211
150
95
—
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
100
Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150°C.
1.3
Test Circuits
CF
The circuit used for most DC and AC tests is shown in
Figure 1-1. This circuit can independently set VCM and
VOUT (see Equation 1-1). Note that VCM is not the
circuit’s Common mode voltage ((VP + VM)/2), and that
6.8 pF
RG
100 k
RF
100 k
V
OST includes VOS plus the effects (on the input offset
error, VOST) of the temperature, CMRR, PSRR and
AOL
VDD/2
VP
VDD
.
VIN+
CB1
100 nF
CB2
1 µF
EQUATION 1-1:
MCP6421
GDM = RF RG
VIN–
VCM = VP + VDD 2 2
VOST = VIN– – VIN+
VOUT
VM
RL
CL
RG
100 k
RF
VOUT = VDD 2 + VP – VM + VOST1 + GDM
Where:
100 k 30 pF
100 k
GDM = Differential Mode Gain
(V/V)
(V)
CF
VL
6.8 pF
VCM = Op Amp’s Common Mode
Input Voltage
FIGURE 1-1:
AC and DC Test Circuit for
VOST = Op Amp’s Total Input Offset Voltage (mV)
Most Specifications.
2013 Microchip Technology Inc.
DS20005165B-page 5
MCP6421/2/4
NOTES:
DS20005165B-page 6
2013 Microchip Technology Inc.
MCP6421/2/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS= GND, VCM = VDD/2, VOUT = VDD/2,
VL = VDD/2, RL = 100 k to VL and CL = 30 pF.
48%
44%
40%
36%
32%
28%
24%
20%
16%
12%
8%
1000
800
600
400
200
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
1253Samples
VDD = 3.0V
VCM = VDD/4
0
-200
-400
-600
-800
-1000
VDD = 5.5V
Representative Part
4%
0%
-0.50.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Common Mode Input Voltage (V)
Input Offset Voltage (μV)
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
Input Offset Voltage vs.
Common Mode Input Voltage.
10%
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
346 Samples
VDD = 3.0V
Representative Part
8%
6%
4%
2%
0%
VCM = VDD/4
TA = -40°C to +125°C
VDD = 5.5V
VDD = 1.8V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-12 -10 -8 -6 -4 -2
0
2
4
6
8 10 12
Output Voltage (V)
Input Offset Voltage Drift (μV/°C)
FIGURE 2-2:
Input Offset Voltage Drift.
FIGURE 2-5:
Input Offset Voltage vs.
Output Voltage.
1000
800
600
400
200
1000
800
600
400
200
0
Representative Part
TA = +125°C
T
A = +85°C
TA = +25°C
A = -40°C
T
0
-200
-400
-600
-800
-1000
-200
-400
-600
-800
-1000
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
VDD = 1.8V
Representative Part
-0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1
Common Mode Input Voltage (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
Power Supply Voltage (V)
FIGURE 2-3:
Input Offset Voltage vs.
FIGURE 2-6:
Input Offset Voltage vs.
Common Mode Input Voltage.
Power Supply Voltage.
2013 Microchip Technology Inc.
DS20005165B-page 7
MCP6421/2/4
Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS= GND, VCM = VDD/2, VOUT = VDD/2,
VL = VDD/2, RL = 100 k to VL and CL = 30 pF.
90
80
70
60
50
40
20
10
0
140
130
120
110
100
90
PSRR
80
CMRR @ VDD = 5.5V
@ VDD = 1.8V
70
f = 10 kHz
DD = 5.5 V
60
V
50
-0.5 0 0.5
1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
-50
-25
0
25
50
75
100
125
Common Mode Input Voltage (V)
Ambient Temperature (°C)
FIGURE 2-7:
Input Noise Voltage Density
FIGURE 2-10:
CMRR, PSRR vs. Ambient
vs. Common Mode Input Voltage.
Temperature.
10,000
1n
VDD = 5.5V
100p
1,000
100
10
Input Bias Current
10p
1p
0.1p
.
Input Offset Current
0.01p
0.1
1
10
100
1k
10k 100k
Ambient Temperature (°C)
Frequency (Hz)
FIGURE 2-8:
Input Noise Voltage Density
FIGURE 2-11:
Input Bias, Offset Current
vs. Frequency.
vs. Ambient Temperature.
1000
900
800
700
600
500
400
300
200
100
0
100
Representative Part
CMRR
TA = +125°C
90
80
70
60
50
40
30
20
PSRR-
PSRR+
TA = +85°C
TA = +25°C
VDD = 5.5 V
-100
100
1k
10k
100k
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
10
Frequency (Hz)
Common Mode Input Voltage (V)
FIGURE 2-9:
CMRR, PSRR vs.
FIGURE 2-12:
Input Bias Current vs.
Frequency.
Common Mode Input Voltage.
DS20005165B-page 8
2013 Microchip Technology Inc.
MCP6421/2/4
Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS= GND, VCM = VDD/2, VOUT = VDD/2,
VL = VDD/2, RL = 100 k to VL and CL = 30 pF.
6
5
6
VDD = 5.5V
VDD = 1.8V
5
4
3
2
1
0
4
3
1
0
VDD = 5.5V
G = +1 V/V
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-13:
Quiescent Current vs.
FIGURE 2-16:
Quiescent Current vs.
Ambient Temperature.
Common Mode Input Voltage.
6
5
4
3
2
1
0
120
0
Open-Loop Gain
100
-30
80
-60
Open-Loop Phase
60
40
20
0
-90
-120
-150
-180
-210
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
-20
1.0E.0021 0.1 1.1E+0 10 100 1.0Ek3 10k 100k
10-1
10+0
10+0
.E4
10E+0
0
0.5
1
1.5
2 2.5 3 3.5 4 4.5 5 5.5 6
Power Supply Voltage (V)
Frequency (Hz)
FIGURE 2-14:
Quiescent Current vs.
FIGURE 2-17:
Open-Loop Gain, Phase vs.
Power Supply Voltage.
Frequency.
6
5
4
3
140
VDD = 5.5V
130
120
110
100
90
VDD = 1.8V
1
VDD = 1.8V
G = +1 V/V
0
80
-50
-25
0
25
50
75
100
125
-0.5 -0.2 0.1 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5
Common Mode Input Voltage (V)
Ambient Temperature (°C)
FIGURE 2-15:
Quiescent Current vs.
FIGURE 2-18:
DC Open-Loop Gain vs.
Common Mode Input Voltage.
Ambient Temperature.
2013 Microchip Technology Inc.
DS20005165B-page 9
MCP6421/2/4
Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS= GND, VCM = VDD/2, VOUT = VDD/2,
VL = VDD/2, RL = 100 k to VL and CL = 30 pF.
150
140
130
120
110
100
90
40
30
Isc+@ TA = +125°C
TA = +85°C
TA = +25°C
20
TA = -40°C
10
0
VDD = 5.5V
VDD = 1.8V
-10
-20
-30
-40
Isc-@ TA = +125°C
TA = +85°C
80
TA = +25°C
TA = -40°C
70
0.00
0.05
Output Voltage Headroom (V)
DD - VOH or VOL - VSS
0.10
0.15
0.20
0.25
0.30
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
V
Power Supply Voltage (V)
FIGURE 2-19:
DC Open-Loop Gain vs.
FIGURE 2-22:
Output Short Circuit Current
Output Voltage Headroom.
vs. Power Supply Voltage.
100.0
90.0
80.0
180
160
140
120
100
80
10
VDD = 5.5V
VDD = 1.8V
Gain Bandwidth Product
70.0
60.0
50.0
40.0
30.0
1
40
Phase Margin
VDD = 5.5V
20
0
0.1
1k
10k
100k
-50 -25
0
25
50
75 100 125
Ambient Temperature (°C)
Frequency (Hz)
FIGURE 2-20:
Gain Bandwidth Product,
FIGURE 2-23:
Output Voltage Swing vs.
Phase Margin vs. Ambient Temperature.
Frequency.
100.0
90.0
80.0
180
160
140
120
100
80
1000
VDD = 1.8V
100
10
1
VDD - VOH
70.0
60.0
50.0
40.0
30.0
Gain Bandwidth Product
Phase Margin
VOL - VSS
40
20
VDD = 1.8V
0.1
0.001
0
0.01
0.1
1
10
100
-50 -25
0
25
50
75 100 125
Ambient Temperature (°C)
Output Current (mA)
FIGURE 2-21:
Phase Margin vs. Ambient Temperature.
Gain Bandwidth Product,
FIGURE 2-24:
vs. Output Current.
Output Voltage Headroom
DS20005165B-page 10
2013 Microchip Technology Inc.
MCP6421/2/4
Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS= GND, VCM = VDD/2, VOUT = VDD/2,
VL = VDD/2, RL = 100 k to VL and CL = 30 pF.
1000
100
10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
VDD = 5.5V
Falling Edge, VDD = 5.5V
Rising Edge, VDD = 5.5V
VDD - VOH
Falling Edge, VDD = 1.8V
Rising Edge, VDD = 1.8V
VOL - VSS
1
0.1
0.01
-50
-25
0
25
50
75
100
125
0.1
1
10
100
Output Current (mA)
Ambient Temperature (°C)
FIGURE 2-25:
Output Voltage Headroom
FIGURE 2-28:
Slew Rate vs. Ambient
vs. Output Current.
Temperature.
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VDD - VOH
VOL - VSS
VDD = 5.5V
G = +1 V/V
VDD = 1.8V
-50
-25
0
25
50
75
100
125
Time (25 μs/div)
Ambient Temperature (°C)
FIGURE 2-26:
Output Voltage Headroom
FIGURE 2-29:
Small Signal Non-Inverting
vs. Ambient Temperature.
Pulse Response.
1.2
1
VOL - VSS
VDD = 5.5 V
G = -1 V/V
0.8
0.6
0.4
0.2
0
VDD - VOH
VDD = 5.5V
100 125
-50
-25
0
25
50
75
Ambient Temperature (°C)
Time (25 μs/div)
FIGURE 2-27:
Output Voltage Headroom
FIGURE 2-30:
Small Signal Inverting Pulse
vs. Ambient Temperature.
Response.
2013 Microchip Technology Inc.
DS20005165B-page 11
MCP6421/2/4
10000
1000
100
10
6
5
4
3
GN:
101 V/V
11 V/V
1 V/V
2
VDD = 5.5 V
G = +1 V/V
1
1
0
.E0
.E4
.E0
.1E0
10
110E002
1.1Ek3
10k
100k
Time (0.1 ms/div)
Frequency (Hz)
FIGURE 2-31:
Large Signal Non-Inverting
FIGURE 2-34:
Closed Loop Output
Pulse Response.
Impedance vs. Frequency.
10μ
6
5
4
3
2
1
0
1μ
VDD = 5.5 V
G = -1 V/V
100n
TA = +125°C
TA = +85°C
TA = +25°C
10n
1n
T
A = -40°C
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
IN (V)
Time (0.1 ms/div)
V
FIGURE 2-32:
Large Signal Inverting Pulse
FIGURE 2-35:
Measured Input Current vs.
Response.
Input Voltage (below VSS).
120
110
100
90
80
70
60
50
40
30
20
10
0
6
5
4
VOUT
3
VIN
2
1
VIN = 100 mVPK
VDD = 5.5V
VDD = 5.5V
G = +2V/V
0
100k
1M
10M
100M
1G
10G
-1
Frequency (Hz)
Time (1 ms/div)
FIGURE 2-33:
The MCP6421/2/4 Device
FIGURE 2-36:
EMIRR vs. Frequency.
Shows No Phase Reversal.
DS20005165B-page 12
2013 Microchip Technology Inc.
MCP6421/2/4
Note: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS= GND, VCM = VDD/2, VOUT = VDD/2,
VL = VDD/2, RL = 100 k to VL and CL = 30 pF.
120
100
80
60
EMIRR @ 2400 MHz
40
EMIRR @ 1800 MHz
EMIRR @ 900 MHz
EMIRR @ 400 MHz
20
0
0.01
0.1
1
RF Input Peak Voltage Voltage (VPK
)
FIGURE 2-37:
EMIRR vs. RF Input Peak-
to-Peak Voltage.
140
130
Input Referred
120
110
100
90
80
70
100
1k
10k
100k
1M
Frequency (Hz)
FIGURE 2-38:
Channel-to-Channel
Separation vs. Frequency.
2013 Microchip Technology Inc.
DS20005165B-page 13
MCP6421/2/4
NOTES:
DS20005165B-page 14
2013 Microchip Technology Inc.
MCP6421/2/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
MCP6421
PIN FUNCTION TABLE
MCP6422
MCP6424
Symbol
Description
SC70-5,
SOT-23-5
MSOP,
SOIC
SOIC,
TSSOP
1
4
1
2
3
8
5
6
1
2
3
4
5
6
VOUT, VOUTA Analog Output (op amp A)
VIN–, VINA
–
Inverting Input (op amp A)
Non-inverting Input (op amp A)
Positive Power Supply
3
VIN+, VINA
VDD
+
5
—
—
VINB
+
–
Non-inverting Input (op amp B)
Inverting Input (op amp B)
VINB
—
—
—
—
2
7
7
VOUTB
VOUTC
Analog Output (op amp B)
Analog Output (op amp C)
Inverting Input (op amp C)
Non-inverting Input (op amp C)
Negative Power Supply
—
—
—
4
8
9
VINC
–
+
10
11
12
13
14
VINC
VSS
—
—
—
—
—
—
VIND+
Non-inverting Input (op amp D)
Inverting Input (op amp D)
Analog Output (op amp D)
VIND
–
VOUTD
3.1
Analog Outputs
The output pin is a low-impedance voltage source.
3.2
Analog Inputs
The non-inverting and inverting inputs are high-
impedance CMOS inputs with low bias currents.
3.3
Power Supply Pins (V , V
)
DD
SS
The positive power supply (VDD) is 1.8V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are at voltages between VSS
and VDD
.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
2013 Microchip Technology Inc.
DS20005165B-page 15
MCP6421/2/4
NOTES:
DS20005165B-page 16
2013 Microchip Technology Inc.
MCP6421/2/4
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs;
Figure 4-2 shows one approach to protecting these
inputs.
4.0
APPLICATION INFORMATION
The MCP6421/2/4 op amps are manufactured using
Microchip’s state-of-the-art CMOS process. This op
amp is unity gain stable and suitable for a wide range
of general purpose applications.
VDD
4.1
Rail-to-Rail Input
D1 D2
4.1.1
PHASE REVERSAL
V1
VOUT
The MCP6421/2/4 op amps are designed to prevent
phase reversal, when the input pins exceed the supply
voltages. Figure 2-33 shows the input voltage
exceeding the supply voltage with no phase reversal.
MCP642X
V2
4.1.2
INPUT VOLTAGE LIMITS
FIGURE 4-2:
Protecting the Analog
Inputs.
In order to prevent damage and/or improper operation
of the amplifier, the circuit must limit the voltages at the
input pins (see Section 1.1, Absolute Maximum
Ratings †).
A significant amount of current can flow out of the
inputs when the Common mode voltage (VCM) is below
ground (VSS); see Figure 2-35.
The Electrostatic Discharge (ESD) protection on the
inputs can be depicted as shown in Figure 4-1. This
structure was chosen to protect the input transistors
against many, but not all, over-voltage conditions, and
to minimize the input bias current (IB).
4.1.3
INPUT CURRENT LIMITS
In order to prevent damage and/or improper operation
of the amplifier, the circuit must limit the currents into
the input pins (see Section 1.1, Absolute Maximum
Ratings †).
Figure 4-3 shows one approach to protecting these
inputs. The resistors R1 and R2 limit the possible
currents in or out of the input pins (and the ESD diodes,
D1 and D2). The diode currents will go through either
Bond
VDD
Pad
VDD or VSS
.
Bond
Pad
Bond
Pad
Input
Stage
VIN+
VIN–
VDD
Bond
Pad
D1 D2
R1
VSS
V1
V2
VOUT
MCP642X
FIGURE 4-1:
Structures.
Simplified Analog Input ESD
R2
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below VSS. They also
clamp any voltages that go well above VDD; their
breakdown voltage is high enough to allow normal
operation, but not low enough to protect against slow
over-voltage (beyond VDD) events. Very fast ESD
events that meet the spec are limited so that damage
does not occur.
VSS – min(V1, V2)
2 mA
min(R1,R2) >
min(R1,R2) >
max(V1,V2) – VDD
2 mA
FIGURE 4-3:
Protecting the Analog
Inputs.
2013 Microchip Technology Inc.
DS20005165B-page 17
MCP6421/2/4
4.1.4
NORMAL OPERATION
100000
10000
1000
100
The input stage of the MCP6421/2/4 op amps uses two
differential input stages in parallel. One operates at a
low Common mode input voltage (VCM), while the other
operates at a high VCM. With this topology, the device
operates with a VCM up to 300 mV above VDD and
300 mV below VSS. The input offset voltage is
measured at VCM = VSS – 0.3V and VDD + 0.3V, to
ensure proper operation.
VDD = 5.5 V
RL = 100 kȍ
GN:
1 V/V
2 V/V
≥ 5 V/V
10
The transition between the input stages occurs when
VCM is near VDD – 0.6V (see Figures 2-3 and 2-4). For
the best distortion performance and gain linearity, with
non-inverting gains, avoid this region of operation.
1
10p
100p
1n
10n
0.1μ
Normalized Load Capacitance; CL/GN (F)
FIGURE 4-5:
Recommended RISO Values
for Capacitive Loads.
4.2
Rail-to-Rail Output
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP6421/2/4 SPICE macro
model are very helpful.
The output voltage range of the MCP6421/2/4 op amps
is 0.001V (typical) and 5.499V (typical) when
RL = 100 k is connected to VDD/2 and VDD = 5.5V.
Refer to Figures 2-24 and 2-26 for more information.
4.3
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases, and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. While a unity-gain buffer (G = +1 V/V) is the
most sensitive to the capacitive loads, all gains show
the same general behavior.
4.4
Supply Bypass
The MCP6421/2/4 op amps’ power supply pin (VDD for
single-supply) should have a local bypass capacitor
(i.e., 0.01 µF to 0.1 µF) within 2 mm for good high
frequency performance. It can use a bulk capacitor
(i.e., 1 µF or larger) within 100 mm to provide large,
slow currents. This bulk capacitor can be shared with
other analog parts.
When driving large capacitive loads with the
MCP6421/2/4 op amps (e.g., > 60 pF when
G = +1 V/V), a small series resistor at the output (RISO
in Figure 4-5) improves the feedback loop’s phase mar-
gin (stability) by making the output load resistive at
higher frequencies. The bandwidth will be generally
lower than the bandwidth with no capacitance load.
4.5
Unused Op Amps
An unused op amp in a quad package (MCP6424)
should be configured as shown in Figure 4-6. These
circuits prevent the output from toggling and causing
crosstalk. Circuit A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp, and the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
–
RISO
VOUT
MCP642X
+
VIN
CL
¼ MCP6424 (A)
¼ MCP6424 (B)
VDD
VDD
FIGURE 4-4:
Stabilizes Large Capacitive Loads.
Output Resistor, RISO
VDD
R1
Figure 4-5 gives the recommended RISO values for the
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
VREF
R2
R
2
V
= V
--------------------
REF
DD
R
+ R
1
2
FIGURE 4-6:
Unused Op Amps.
DS20005165B-page 18
2013 Microchip Technology Inc.
MCP6421/2/4
4.6
PCB Surface Leakage
4.7
Electromagnetic Interference
Rejection Ratio (EMIRR)
Definitions
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6421/2/4 family’s bias current at +25°C (±1 pA,
typical).
The electromagnetic interference (EMI) is the distur-
bance that affects an electrical circuit due to either elec-
tromagnetic induction or electromagnetic radiation
emitted from an external source.
The parameter which describes the EMI robustness of
an op amp is the Electromagnetic Interference
Rejection Ratio (EMIRR). It quantitatively describes the
effect that an RF interfering signal has on op amp
performance. Internal passive filters make EMIRR
better compared with older parts. This means that, with
good PCB layout techniques, your EMC performance
should be better.
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-7.
EMIRR is defined as:
Guard Ring
VIN– VIN+
VSS
EQUATION 4-1:
VRF
EMIRRdB= 20 log -------------
VOS
Where:
VRF = Peak Amplitude of
RF Interfering Signal (VPK
)
FIGURE 4-7:
for Inverting Gain.
Example Guard Ring Layout
VOS = Input Offset Voltage Shift (V)
1. Non-inverting Gain and Unity-Gain Buffer:
a) Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
4.8
4.8.1
Application Circuits
CARBON MONOXIDE GAS SENSOR
b) Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
Common mode input voltage.
A carbon monoxide (CO) gas detector is a device
which detects the presence of carbon monoxide gas
level. Usually this is battery powered and transmits
audible and visible warnings.
2. Inverting Gain and Transimpedance Gain
Amplifiers (convert current to voltage, such as
photo detectors):
The sensor responds to CO gas by reducing its
resistance proportionaly to the amount of CO present in
the air exposed to the internal element. On the sensor
module, this variable is part of a voltage divider formed
by the internal element and potentiometer R1. The
output of this voltage divider is fed into the non-
inverting inputs of the MCP6421 op amp. The device is
configured as a buffer with unity gain and is used to
provide a non-loaded test point for sensor sensitivity.
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
Because this sensor can be corrupted by parasitic elec-
tromagnetic signals, the MCP6421 op amp can be
used for conditioning this sensor.
2013 Microchip Technology Inc.
DS20005165B-page 19
MCP6421/2/4
In Figure 4-8, the variable resistor is used to calibrate
the sensor in different environments.
4.8.3
BATTERY CURRENT SENSING
The MCP6421/2/4 op amps’ Common Mode Input
Range, which goes 0.3V beyond both supply rails,
supports their use in high-side and low-side battery
current sensing applications. The low quiescent current
helps prolong battery life, and the rail-to-rail output sup-
ports detection of low currents.
.
VDD
VREF
VDD
-
VOUT
MCP6421
+
Figure 4-10 shows a high side battery current sensor
circuit. The 10 resistor is sized to minimize power
losses. The battery current (IDD) through the 10
resistor causes its top terminal to be more negative
than the bottom terminal. This keeps the Common
mode input voltage of the op amp below VDD, which is
within its allowed range. The output of the op amp will
also be below VDD, within its Maximum Output Voltage
Swing specification.
R1
FIGURE 4-8:
CO Gas Sensor Circuit.
4.8.2
PRESSURE SENSOR AMPLIFIER
The MCP6421/2/4 op amps are well suited for condi-
tioning sensor signals in battery-powered applications.
Many sensors are configured as Wheatstone bridges.
Strain gauges and pressure sensors are two common
examples.
VDD
VDD
VOUT
10
IDD
MCP6421
Figure 4-9 shows a strain gauge amplifier, using the
MCP6421/2/4 Enhanced EMI protection device. The
difference amplifier with EMI robustness op amp is
used to amplify the signal from the Wheatstone bridge.
The two op amps, configured as buffers and connected
at outputs of pressure sensors, prevents resistive
loading of the bridge by resistor R1 and R2. Resistors
R1,R2 and R3,R5 need to be chosen with very low
tolerance to match the CMRR.
VSS
1.8V
to
5.5V
100 k
1 M
V
– V
DD
OUT
10 V/V 10
I
= -----------------------------------------
DD
High-Side Battery Current Sensor
FIGURE 4-10:
Battery Current Sensing.
VDD
R
VDD
3
R+¨R
R-¨R
100k
MCP6421
-
R
1
VDD
+
1k
VOUT
MCP6421
V
b
-
V
a
+
VDD
R
2
1k
R
5
-
100k
+
R-¨R R+¨R
MCP6421
100k
VOUT = Va – Vb ----------------
1k
Strain Gauge
FIGURE 4-9:
Pressure Sensor Amplifier.
DS20005165B-page 20
2013 Microchip Technology Inc.
MCP6421/2/4
5.4
Analog Demonstration and
Evaluation Boards
5.0
DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP6421/2/4 op amps.
Microchip offers
a
broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
5.1
SPICE Macro Model
a
complete listing of these boards and their
corresponding user’s guides and technical information,
visit the Microchip web site at
www.microchip.com/analogtools.
The latest SPICE macro model for the MCP6421/2/4
op amp is available on the Microchip web site at
www.microchip.com. The model was written and tested
in the official OrCAD (Cadence®) owned PSpice®. For
the other simulators, translation may be required.
Some boards that are especially useful are:
• MCP6XXX Amplifier Evaluation Board 1
• MCP6XXX Amplifier Evaluation Board 2
• MCP6XXX Amplifier Evaluation Board 3
• MCP6XXX Amplifier Evaluation Board 4
• Active Filter Demo Board Kit
The model covers a wide aspect of the op amp's
electrical specifications. Not only does the model cover
voltage, current and resistance of the op amp, but it
also covers the temperature and the noise effects on
the behavior of the op amp. The model has not been
verified outside of the specification range listed in the
op amp data sheet. The model behaviors under these
conditions cannot ensure it will match the actual op
amp performance.
• 5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2
5.5
Application Notes
Moreover, the model is intended to be an initial design
tool. Bench testing is a very important part of any
design and cannot be replaced with simulations. Also,
simulation results using this macro model need to be
validated by comparing them to the data sheet
specifications and characteristic curves.
The following Microchip Analog Design Note and
Application Notes are available on the Microchip web
site at www.microchip.com/appnotes, and are
recommended as supplemental reference resources.
• ADN003 – “Select the Right Operational Amplifier
for your Filtering Circuits”, DS21821
• AN722 – “Operational Amplifier Topologies and
DC Specifications”, DS00722
®
5.2
FilterLab Software
• AN723 – “Operational Amplifier AC Specifications
and Applications”, DS00723
Microchip’s FilterLab software is an innovative software
tool that simplifies analog active filter design using op
amps. Available at no cost from the Microchip web site
at www.microchip.com/filterlab, the FilterLab design
tool provides full schematic diagrams of the filter circuit
with component values. It also outputs the filter circuit
in SPICE format, which can be used with the macro
model to simulate the actual filter performance.
• AN884 – “Driving Capacitive Loads With Op
Amps”, DS00884
• AN990 – “Analog Sensor Conditioning Circuits –
An Overview”, DS00990
• AN1177 – “Op Amp Precision Design: DC Errors”,
DS01177
• AN1228 – “Op Amp Precision Design: Random
Noise”, DS01228
5.3
Microchip Advanced Part Selector
(MAPS)
• AN1297 – “Microchip’s Op Amp SPICE Macro
Models”, DS01297
MAPS is a software tool that helps semiconductor
professionals efficiently identify the Microchip devices
that fit a particular design requirement. Available at no
• AN1332: “Current Sensing Circuit Concepts and
Fundamentals”’ DS01332
cost
from
the
Microchip
website
at
• AN1494: “Using MCP6491 Op Amps for Photode-
tection Applications”’ DS01494
www.microchip.com/ maps, the MAPS is an overall
selection tool for Microchip’s product portfolio that
includes Analog, Memory, MCUs and DSCs. Using this
tool, you can define a filter to sort features for a
parametric search of devices and export side-by-side
technical comparison reports. Helpful links are also
provided for data sheets, purchase and sampling of
Microchip parts.
These application notes and others are listed in the
design guide:
• “Signal Chain Design Guide”, DS21825
2013 Microchip Technology Inc.
DS20005165B-page 21
MCP6421/2/4
NOTES:
DS20005165B-page 22
2013 Microchip Technology Inc.
MCP6421/2/4
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
Example:
DS25
5-Lead SC70 (MCP6421 only)
5-Lead SOT-23 (MCP6421 only)
Example:
3H25
XXNN
8-Lead MSOP (3x3 mm) (MCP6422 only)
Example
6422E
330256
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
e
3
e
3
*
)
Note: In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2013 Microchip Technology Inc.
DS20005165B-page 23
MCP6421/2/4
8-Lead SOIC (150 mil.) (MCP6422 only)
Example
MCP6422E
e
3
SN 1330
256
NNN
14-Lead SOIC (3.90 mm) (MCP6424 only)
Example
MCP6424
E/SL
1330256
14-Lead TSSOP (4.4 mm) (MCP6424 only)
Example
XXXXXXXX
YYWW
6424E/ST
1330
256
NNN
DS20005165B-page 24
2013 Microchip Technology Inc.
MCP6421/2/4
5-Lead Plastic Small Outine Transistor (LTY) [SC70]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
b
1
3
2
E1
E
4
5
e
e
A
A2
c
A1
L
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B
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2013 Microchip Technology Inc.
DS20005165B-page 25
MCP6421/2/4
5-Lead Plastic Small Outine Transistor (LTY) [SC70]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005165B-page 26
2013 Microchip Technology Inc.
MCP6421/2/4
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2013 Microchip Technology Inc.
DS20005165B-page 27
MCP6421/2/4
\
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005165B-page 28
2013 Microchip Technology Inc.
MCP6421/2/4
\
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2013 Microchip Technology Inc.
DS20005165B-page 29
MCP6421/2/4
\
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005165B-page 30
2013 Microchip Technology Inc.
MCP6421/2/4
\
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2013 Microchip Technology Inc.
DS20005165B-page 31
MCP6421/2/4
\
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005165B-page 32
2013 Microchip Technology Inc.
MCP6421/2/4
\
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2013 Microchip Technology Inc.
DS20005165B-page 33
MCP6421/2/4
\
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DS20005165B-page 34
2013 Microchip Technology Inc.
MCP6421/2/4
\
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2013 Microchip Technology Inc.
DS20005165B-page 35
MCP6421/2/4
\
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005165B-page 36
2013 Microchip Technology Inc.
MCP6421/2/4
\
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2013 Microchip Technology Inc.
DS20005165B-page 37
MCP6421/2/4
\
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005165B-page 38
2013 Microchip Technology Inc.
MCP6421/2/4
\
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2013 Microchip Technology Inc.
DS20005165B-page 39
MCP6421/2/4
\
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005165B-page 40
2013 Microchip Technology Inc.
MCP6421/2/4
APPENDIX A: REVISION HISTORY
Revision B (August 2013)
The following is the list of modifications:
1. Added two new devices to the family: dual
version MCP6422 (in 8L-MSOP and 8L-SOIC
packages) and quad version MCP6424 (in
15L-SOIC and 14L-TSSOP packages). Added
related information throughout the document.
2. Updated Package Types drawing with the new
devices’ pinouts.
3. Added ESD Protection on all pins (HBM; MM)
(Dual and Quad) in the Section 1.1, Absolute
Maximum Ratings †.
4. Added the new package temperatures in
Table 1-3.
5. Updated Figures 2-2 and 2-37 in Section 2.0,
Typical Performance Curves. Added new
Figure 2-38.
6. Updated Section 3.0, Pin Descriptions with pin
list and information.
7. Added new Section 4.5, Unused Op Amps.
8. Updated Section 6.0, Packaging Information
with markings and package specification
drawings.
9. Updated Product Identification System.
Revision A (March 2013)
• Original Release of this Document.
2013 Microchip Technology Inc.
DS20005165B-page 41
MCP6421/2/4
NOTES:
DS20005165B-page 42
2013 Microchip Technology Inc.
MCP6421/2/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
-X
/XX
a)
b)
MCP6421T-E/LTY:
MCP6421T-E/OT:
Tape and Reel,
Temperature Package
Range
Extended Temperature,
5LD SC-70 package
Tape and Reel,
Extended Temperature,
5LD SOT-23 package
Device:
MCP6421T:
Single Op Amp (Tape and Reel)
(SC70, SOT-23)
MCP6422:
MCP6422T:
Dual Op Amp (MSOP, SOIC)
Dual Op Amp (Tape and Reel)
(MSOP, SOIC)
Quad Op Amp (SOIC, TSSOP)
Quad Op Amp (Tape and Reel)
(SOIC, TSSOP)
a)
b)
MCP6422-E/MS:
MCP6422T-E/MS:
Extended Temperature,
8LD MSOP package
Tape and Reel,
Extended Temperature,
8LD MSOP package
MCP6424:
MCP6424T:
c) MCP6422-E/SN:
Extended Temperature,
8LD SOIC package
Tape and Reel,
Temperature
Range:
E
= -40°C to +125°C (Extended)
d)
MCP6422T-E/SN:
Extended Temperature,
8LD SOIC package
Package:
LTY* = Plastic Package (SC70), 5-lead
MS
= Plastic Micro Small Outline Package (MSOP),
8-lead
OT
SL
= Plastic Small Outline Transistor (SOT-23), 5-lead
= Plastic Small Outline - Narrow, 3.90 mm Body,
14-lead
= Plastic Small Outline - Narrow, 3.90 mm Body,
8-lead
= Plastic Thin Shrink Small Outline - 4.4 mm Body,
14-lead
a)
b)
MCP6424-E/SL:
MCP6424T-E/SL:
Extended Temperature,
14LD SOIC package
Tape and Reel,
Extended Temperature,
14LD SOIC package
SN
ST
c) MCP6424-E/ST:
d) MCP6424T-E/ST:
Extended Temperature,
14LD TSSOP package
Tape and Reel,
* Y = Nickel palladium gold manufacturing designator. Only
available on the TDFN package.
Extended Temperature,
14LD TSSOP package
2013 Microchip Technology Inc.
DS20005165B-page 43
MCP6421/2/4
NOTES:
DS20005165B-page 44
2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
32
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2013, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62077-382-6
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2013 Microchip Technology Inc.
DS20005165B-page 45
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
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Malaysia - Penang
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Fax: 66-2-694-1350
Toronto
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Canada
China - Xiamen
Tel: 905-673-0699
Fax: 905-673-6509
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
11/29/12
DS20005165B-page 46
2013 Microchip Technology Inc.
相关型号：
MCP6424
The Microchip’s MCP6421/2/4 operational amplifiers (op amps) has low input bias current (1 pA, typ
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