MCP654-E/SL [MICROCHIP]
QUAD OP-AMP, 200 uV OFFSET-MAX, 50 MHz BAND WIDTH, PDSO14, 3.90 MM, LEAD FREE, PLASTIC, SOIC-14;型号: | MCP654-E/SL |
厂家: | MICROCHIP |
描述: | QUAD OP-AMP, 200 uV OFFSET-MAX, 50 MHz BAND WIDTH, PDSO14, 3.90 MM, LEAD FREE, PLASTIC, SOIC-14 光电二极管 |
文件: | 总62页 (文件大小:1887K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MCP651/1S/2/3/4/5/9
50 MHz, 200 µV Op Amps with mCal
Features:
Description:
• Gain-Bandwidth Product: 50 MHz
• Slew Rate: 30 V/µs
The Microchip Technology Inc. MCP651/1S/2/3/4/5/9
family of high bandwidth and high slew rate operational
amplifiers features low offset. At power-up, these op
amps are self-calibrated using mCal. Some package
options also provide a Calibration/Chip Select pin
• Low Input Offset: ±200 µV (maximum)
• Low Input Bias Current: 6 pA (typical)
• Noise: 7.5 nV/Hz, at 1 MHz
• Ease-of-Use:
(CAL/CS) that supports
a Low-Power mode of
operation, with offset calibration at the time normal
operation is re-started. These amplifiers are optimized
for high speed, low noise and distortion, single-supply
operation with rail-to-rail output and an input that
includes the negative rail.
- Unity-Gain Stable
- Rail-to-Rail Output
- Input Range incl. Negative Rail
- No Phase Reversal
This family is offered in single (MCP651 and
MCP651S), single with CAL/CS pin (MCP653), dual
(MCP652), dual with CAL/CS pins (MCP655), quad
(MCP654) and quad with CAL/CS pins (MCP659). All
devices are fully specified from -40°C to +125°C.
• Supply Voltage Range: +2.5V to +5.5V
• High Output Current: ±100 mA
• Supply Current: 6.0 mA/Ch (typical)
• Low-Power Mode: 5 µA/Ch
• Small Packages: SOT23-5, DFN
• Extended Temperature Range: -40°C to +125°C
Typical Application Circuit
MCP65X
VIN
Typical Applications:
VOUT
• Driving A/D Converters
• Fast Low-side Current Sensing
• Power Amplifier Control Loops
• Optical Detector Amplifier
• Barcode Scanners
RL
VDD/2
1 k
100 k
High Gain Amplifier (G = 101V/V)
• Multi-Pole Active Filter
• Consumer Audio
35%
80 Samples
TA = +25°C
VDD = 2.5V and 5.5V
Calibrated at +25°C
30%
25%
20%
15%
10%
5%
Design Aids:
• SPICE Macro Models
• FilterLab® Software
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
- MCP651EV-VOS
0%
-100 -80 -60 -40 -20
0
20 40 60 80 100
• Application Notes
Input Offset Voltage (µV)
High Gain-Bandwidth Op Amp Portfolio
Model Family
Channels/Package Gain-Bandwidth
VOS (max.)
IQ/Ch (typ.)
MCP621/1S/2/3/4/5/9
MCP631/2/3/4/5/9
1, 2, 4
1, 2, 4
20 MHz
24 MHz
50 MHz
60 MHz
0.2 mV
8.0 mV
0.2 mV
8.0 mV
2.5 mA
2.5 mA
6.0 mA
6.0 mA
MCP651/1S/2/3/4/5/9
MCP660/1/2/3/4/5/9
1, 2, 4
1, 2, 3, 4
2009-2014 Microchip Technology Inc.
DS20002146D-page 1
MCP651/1S/2/3/4/5/9
Package Types
MCP654
SOIC, TSSOP
MCP651
MCP651S
SOT-23-5
MCP651
2x3 TDFN *
SOIC
V
NC
CAL/CS
V
OUTA
1
2
8
7
1
2
3
4
5
6
7
14
13
12
11
10
9
OUTD
1
2
3
4
8 CAL/CS
NC
5 V
V
V
1
DD
OUT
V
-
V
V
V
-
V
–
+
V
7
6
5
INA
IND
V
–
V
V
V
EP
9
IN
DD
IN
IN
DD
2
3
SS
V
+
+
INA
IND
V
V
3
4
6
5
V
+
IN
OUT
OUT
CAL
V
+
V
V
–
4
IN
DD
IN
SS
V
V
V
SS
CAL
SS
V
+
V
V
V
+
INB
INC
V
-
-
INB
INC
V
8
OUTB
OUTC
MCP652
3x3 DFN *
MCP652
SOIC
MCP653
SOT-23-6
MCP659
4x4 QFN*
V
1
8
7
6
5
V
DD
V
V
V
1
2
8
OUTA
OUTA
DD
V
1
V
DD
6
OUT
V
V
V
2
3
4
V –
INA
OUTB
V
–
+
7
EP
9
INA
OUTB
V
2
3
CAL/CS
5
4
SS
–
V
+
INB
INA
V
V
V
–
3
4
6
5
INA
INB
+
V
V
–
V
+
INB
SS
IN
IN
V
+
SS
INB
16 15 14 13
MCP655
3x3 DFN *
MCP655
MSOP
V
-
V
12
+
1
INA
IND
V
+
V
SS
11
10
9
2
3
4
INA
EP
17
V
V
V
V
V
1
10
9
V
V
OUTA
DD
1
2
3
10
DD
OUTA
V
+
-
V
INC
INC
DD
V
–
2
3
V
–
+
V
V
V
9
8
7
6
INA
OUTB
INA
OUTB
V
V
+
INB
EP
11
V
–
INA
V
+
–
8
INB
INA
INB
5
6
7
8
V
+
SS 4
INB
V
+
4
5
7
6
SS
INB
CALA/CSA
CALB/CSB
5
CALA/CSA
CALB/CSB
* Includes Exposed Thermal Pad (EP); see Table 3-1.
DS20002146D-page 2
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
1.0
1.1
ELECTRICAL CHARACTERISTICS
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Absolute Maximum Ratings †
V
– V
.......................................................................6.5V
SS
DD
Current at Input Pins ....................................................±2 mA
Analog Inputs (V + and V –) †† . V – 1.0V to V + 1.0V
IN
IN
SS
DD
All other Inputs and Outputs .......... V – 0.3V to V + 0.3V
SS
DD
Difference Input voltage ...................................... |V – V
|
SS
DD
†† See Section 4.2.2 “Input Voltage and Current Limits”.
Output Short Circuit Current ................................Continuous
Current at Output and Supply Pins ..........................±150 mA
Storage Temperature ...................................-65°C to +150°C
Max. Junction Temperature ........................................+150°C
ESD protection on all pins (HBM, MM) 1 kV, 200V
1.2
Specifications
DC ELECTRICAL SPECIFICATIONS
TABLE 1-1:
Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V /3,
DD
A
DD
SS
CM
V
V /2, V = V /2, R = 1 k to V and CAL/CS = V (refer to Figure 1-2).
OUT
DD
L
DD
L
L
SS
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Input Offset
Input Offset Voltage
V
-200
—
—
37
+200
200
—
µV
µV
After calibration (Note 1)
OS
Input Offset Voltage Trim Step
Input Offset Voltage Drift
Power Supply Rejection Ratio
Input Current and Impedance
Input Bias Current
V
OSTRM
V /T
—
±2.5
76
µV/°C T = -40°C to +125°C
OS
A
A
PSRR
61
—
dB
I
I
I
—
—
—
—
—
—
6
—
—
pA
B
B
B
Across Temperature
130
1700
±1
pA
pA
T = +85°C
A
Across Temperature
5,000
—
T = +125°C
A
Input Offset Current
I
pA
OS
13
Common Mode Input Impedance
Differential Input Impedance
Common Mode
Z
10 ||9
—
||pF
||pF
CM
13
Z
10 ||2
—
DIFF
Common Mode Input Voltage Range
Common Mode Rejection Ratio
V
V
0.3
—
81
84
V
1.3
DD
V
(Note 2)
CMR
SS
CMRR
CMRR
65
68
—
dB
dB
V
V
= 2.5V, V
= 5.5V, V
= -0.3 to 1.2V
= -0.3 to 4.2V
DD
DD
CM
—
CM
Open-Loop Gain
DC Open-Loop Gain (large signal)
A
A
88
94
114
123
—
—
dB
dB
V
V
= 2.5V, V
= 5.5V, V
= 0.3V to 2.2V
= 0.3V to 5.2V
OL
DD
DD
OUT
OL
OUT
Output
Maximum Output Voltage Swing
V
V
, V
, V
V
V
+ 25
—
—
V
V
25
mV
mV
V
= 2.5V, G = +2,
DD
OL
OH
OH
SS
DD
DD
0.5V Input Overdrive
V = 5.5V, G = +2,
DD
+ 50
50
OL
SS
0.5V Input Overdrive
Output Short-Circuit Current
I
I
±50
±50
±95
±145
±150
mA
mA
V
V
= 2.5V (Note 3)
= 5.5V (Note 3)
SC
SC
DD
DD
±100
Note 1: Describes the offset (under the specified conditions) right after power-up, or just after the CAL/CS pin is toggled. Thus,
1/f noise effects (an apparent wander in V ; see Figure 2-35) are not included.
OS
2: See Figure 2-6 and Figure 2-7 for temperature effects.
3: The I specifications are for design guidance only; they are not tested.
SC
2009-2014 Microchip Technology Inc.
DS20002146D-page 3
MCP651/1S/2/3/4/5/9
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V
= V /3,
DD
A
DD
SS
CM
V
V /2, V = V /2, R = 1 k to V and CAL/CS = V (refer to Figure 1-2).
OUT
DD
L
DD
L
L
SS
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Calibration Input
Calibration Input Voltage Range
Internal Calibration Voltage
Input Impedance
V
V
+ 0.1
—
V
– 1.4
mV
V
V
pin externally driven
pin open
CALRNG
SS
DD
CAL
CAL
V
Z
0.31V
—
0.33V
0.35V
—
CAL
CAL
DD
DD
DD
100 || 5
k||pF
Power Supply
Supply Voltage
V
2.5
3
—
6
5.5
9
V
DD
Quiescent Current per Amplifier
POR Input Threshold, Low
I
mA
I = 0
O
Q
V
1.15
—
1.40
—
PRL
V
V
POR Input Threshold, High
V
1.40
1.65
PRH
Note 1: Describes the offset (under the specified conditions) right after power-up, or just after the CAL/CS pin is toggled. Thus,
1/f noise effects (an apparent wander in V ; see Figure 2-35) are not included.
OS
2: See Figure 2-6 and Figure 2-7 for temperature effects.
3: The I specifications are for design guidance only; they are not tested.
SC
TABLE 1-2:
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, T = 25°C, V = +2.5V to +5.5V, V = GND, V
= V /2,
DD
A
DD
SS
CM
V
V /2, V = V /2, R = 1 k to V , C = 20 pF and CAL/CS = V (refer to Figure 1-2).
DD L DD L L L SS
OUT
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
AC Response
Gain-Bandwidth Product
Phase Margin
GBWP
PM
—
—
—
50
65
20
—
—
—
MHz
°
G = +1
Open-Loop Output Impedance
AC Distortion
R
OUT
Total Harmonic Distortion plus Noise
THD+N
—
0.0012
—
%
G = +1, V
= 4V , f = 1 kHz,
OUT P-P
V
= 5.5V, BW = 80 kHz
DD
Step Response
Rise Time, 10% to 90%
Slew Rate
t
—
—
6
—
—
ns
G = +1, V
G = +1
= 100 mV
OUT P-P
r
SR
30
V/µs
Noise
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
E
e
—
—
17
7.5
4
—
—
—
µV
f = 0.1 Hz to 10 Hz
ni
P-P
nV/Hz f = 1 MHz
fA/Hz f = 1 kHz
ni
i
ni
DS20002146D-page 4
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
TABLE 1-3:
DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, T = 25°C, V = +2.5V to +5.5V, V = GND, V
= V /2,
DD
A
DD
SS
CM
V
V /2, V = V /2, R = 1 k to V , C = 20 pF and CAL/CS = V (refer to Figure 1-1 and Figure 1-2).
OUT
DD L DD L L L SS
Parameters
Sym.
Min. Typ. Max. Units
Conditions
CAL/CS Low Specifications
CAL/CS Logic Threshold, Low
CAL/CS Input Current, Low
CAL/CS High Specifications
CAL/CS Logic Threshold, High
CAL/CS Input Current, High
GND Current
V
V
—
0
0.2V
—
V
IL
SS
DD
I
—
nA
CAL/CS = 0V
CSL
V
0.8V
—
V
DD
V
IH
DD
I
0.7
-1.8
-4
—
µA
µA
µA
µA
µA
M
nA
CAL/CS = V
DD
CSH
I
I
I
I
-3.5
-8
—
—
—
—
—
—
Single, CAL/CS = V = 2.5V
DD
SS
SS
SS
SS
Single, CAL/CS = V = 5.5V
DD
-5
-2.5
-5
Dual, CAL/CS = V = 2.5V
DD
-10
—
Dual, CAL/CS = V = 5.5V
DD
CAL/CS Internal Pull-Down Resistor
R
5
PD
O(LEAK)
Amplifier Output Leakage
I
—
50
CAL/CS = V
DD
POR Dynamic Specifications
V
Low to Amplifier Off Time
t
—
200
200
—
ns
G = +1 V/V, V = V
,
DD
POFF
L
SS
(output goes High Z)
V
= 2.5V to 0V step to V
= 0.1 (2.5V)
= 0.9 (2.5V)
DD
OUT
OUT
V
High to Amplifier On Time
t
100
300
ms
G = +1 V/V, V = V
,
DD
PON
L
SS
(including calibration)
V
= 0V to 2.5V step to V
DD
CAL/CS Dynamic Specifications
CAL/CS Input Hysteresis
—
1
—
—
V
0.25
—
V
HYST
CAL/CS Setup Time
t
µs
G = +1 V/V, V = V (Notes 2, 3, 4)
L SS
CSU
(between CAL/CS edges)
CAL/CS = 0.8V to V
= 0.1 (V /2)
DD
OUT
DD
CAL/CS High to Amplifier Off Time
(output goes High Z)
t
—
200
—
ns
G = +1 V/V, V = V
,
COFF
L
SS
CAL/CS = 0.8V to V
= 0.1 (V /2)
DD
DD
OUT
CAL/CS Low to Amplifier On Time
(including calibration)
G = +1 V/V, V = V , MCP651 and MCP655,
L SS
t
—
—
3
6
4
8
ms
ms
CON
CAL/CS = 0.2V to V
= 0.9 (V /2)
DD
OUT
DD
G = +1 V/V, V = V , MCP659,
t
L
SS
CON
CAL/CS = 0.2V to V
= 0.9 (V /2)
DD
DD
OUT
Note 1: The MCP652 single, MCP653 single, MCP655 dual and MCP659 quad have their CAL/CS inputs internally pulled down
to V (0V).
SS
2: This time ensures that the internal logic recognizes the edge. However, for the rising edge case, if CAL/CS is raised
before the calibration is complete, the calibration will be aborted and the part will return to Low-Power mode.
3: For the MCP655 dual, there is an additional constraint. CALA/CSA and CALB/CSB can be toggled simultaneously
(within a time much smaller than t
) to make both op amps perform the same function simultaneously. If they are tog-
CSU
gled independently, then CALA/CSA (CALB/CSB) cannot be allowed to toggle while op amp B (op amp A) is in
Calibration mode; allow more than the maximum t time (4 ms) before the other side is toggled.
CON
4: For the MCP659 quad, there is an additional constraint. CALAD/CSAD and CALBC/CSBC can be toggled simultane-
ously (within a time much smaller than t ) to make all four op amps perform the same function simultaneously, and
CSU
the maximum tCON time is approximately doubled (8 ms). If they are toggled independently, then CALAD/CSAD
(CALBC/CSBC) cannot be allowed to toggle while op amps B and C (op amps A and D) are in Calibration mode; allow
more than the maximum t
time (8 ms) before the other side is toggled.
CON
2009-2014 Microchip Technology Inc.
DS20002146D-page 5
MCP651/1S/2/3/4/5/9
TABLE 1-4:
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: V = +2.5V to +5.5V, V = GND.
DD
SS
Parameters
Sym. Min.
Typ.
Max. Units
Conditions
Temperature Ranges
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
T
-40
-40
-65
—
—
—
+125
+125
+150
°C
°C
°C
A
T
(Note 1)
A
T
A
Thermal Package Resistances
Thermal Resistance, 5L-2×3 SOT
Thermal Resistance, 6L-2×3 SOT
Thermal Resistance, 8L-2×3 TDFN
Thermal Resistance, 8L-3×3 DFN
Thermal Resistance, 8L-SOIC
—
—
—
—
—
—
—
—
—
—
220.7
190.5
52.5
63
—
—
—
—
—
—
—
—
—
—
°C/W
°C/W
°C/W
JA
JA
JA
JA
JA
JA
JA
JA
JA
JA
°C/W (Note 2)
°C/W
163
71
Thermal Resistance, 10L-3×3 DFN
Thermal Resistance, 10L-MSOP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
Thermal Resistance, 16L-4x4-QFN
°C/W (Note 2)
°C/W
202
95.3
100
46
°C/W
°C/W
°C/W (Note 2)
Note 1: Operation must not cause T to exceed Maximum Junction Temperature specification (150°C).
J
2: Measured on a standard JC51-7, four-layer printed circuit board with ground plane and vias.
1.3
Timing Diagram
CAL/CS
VIL
VIH
VDD
VPRH
VPRL
tPOFF
tCSU
tPON
High Z
tCOFF
tCON
High Z
VOUT
High Z
On
-6 mA (typical)
On
-6 mA (typical)
ISS -3 µA (typical)
ICS
-3 µA (typical)
-3 µA (typical)
0 nA (typical)
0 nA (typical)
0.7 µA (typical)
Note
:
For the MCP655 dual and the MCP659 quad, there is an additional constraint on toggling the two CAL/CS pins close
together; see the TCON specification in Table 1-3.
FIGURE 1-1:
Timing Diagram.
DS20002146D-page 6
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
1.4
Test Circuits
CF
The circuit used for most DC and AC tests is shown in
Figure 1-2. This circuit can independently set VCM and
VOUT; see Equation 1-1. Note that VCM is not the
circuit’s Common mode voltage ((VP + VM)/2), and that
VOST includes VOS plus the effects (on the input offset
6.8 pF
RG
10 k
RF
10 k
VDD/2
VP
error, VOST) of temperature, CMRR, PSRR and AOL
.
VDD
VIN+
EQUATION 1-1:
CB1
100 nF
CB2
2.2 µF
GDM = RF RG
MCP65X
VCM = VP + VDD 2 2
VOST = VIN– – VIN+
VIN–
VOUT = VDD 2 + VP – VM + VOST1 + GDM
Where:
VOUT
VM
RL
CL
RG
RF
1 k
20 pF
10 k
10 k
GDM = Differential Mode Gain
(V/V)
(V)
VCM = Op Amp’s Common Mode
CF
6.8 pF
Input Voltage
VL
VOST = Op Amp’s Total Input Offset (mV)
Voltage
FIGURE 1-2:
AC and DC Test Circuit for
Most Specifications.
2009-2014 Microchip Technology Inc.
DS20002146D-page 7
MCP651/1S/2/3/4/5/9
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS
.
2.1
DC Signal Inputs
35%
30%
25%
20%
15%
10%
5%
700
600
500
400
300
200
100
0
80 Samples
TA = +25°C
VDD = 2.5V and 5.5V
Calibrated at +25°C
Representative Part
Calibrated at VDD = 6.5V
+125°C
+85°C
+25°C
-40°C
0%
-100
-100 -80 -60 -40 -20
0
20 40 60 80 100
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V)
Input Offset Voltage (µV)
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
Input Offset Voltage vs.
Power Supply Voltage.
20%
50
80 Samples
DD = 2.5V and 5.5V
A = -40°C to +125°C
Representative Part
18%
16%
14%
12%
10%
8%
40
30
V
T
VDD = 2.5V
Calibrated at +25°C
20
10
0
-10
-20
-30
-40
-50
VDD = 5.5V
6%
4%
2%
0%
-10 -8 -6 -4 -2
0
2
4
6
8
10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Input Offset Voltage Drift (µV/°C)
FIGURE 2-2:
Input Offset Voltage Drift.
FIGURE 2-5:
Input Offset Voltage vs.
Output Voltage.
55%
0.0
1 Lot
Low (VCMR_L – VSS
80 Samples
TA = +25°C
DD = 2.5V and 5.5V
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
)
V
-0.1
-0.2
-0.3
-0.4
-0.5
No Change
(includes noise)
VDD = 2.5V
Calibration
Changed
Calibration
Changed
VDD = 5.5V
0%
-100 -80 -60 -40 -20
0
20 40 60 80 100
-50
-25
0
25
50
75
100 125
Input Offset Voltage Repeatability (µV)
Ambient Temperature (°C)
FIGURE 2-3:
Input Offset Voltage
FIGURE 2-6:
Low-Input Common Mode
Repeatability (repeated calibration).
Voltage Headroom vs. Ambient Temperature.
DS20002146D-page 8
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS
.
1.4
110
105
100
95
1 Lot
High (VDD – VCMR_H
)
PSRR
1.3
1.2
1.1
1.0
VDD = 2.5V
90
85
CMRR, VDD = 5.5V
CMRR, VDD = 2.5V
80
75
70
VDD = 5.5V
65
60
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Ambient Temperature (°C)
FIGURE 2-7:
High-Input Common Mode
FIGURE 2-10:
CMRR and PSRR vs.
Voltage Headroom vs. Ambient Temperature.
Ambient Temperature.
1000
130
VDD = 2.5V
Representative Part
800
VDD = 5.5V
125
120
115
110
105
100
95
600
400
200
0
VDD = 2.5V
-200
-40°C
+25°C
+85°C
+125°C
-400
-600
-800
-1000
-50
-25
0
25
50
75
100
125
Input Common Mode Voltage (V)
Ambient Temperature (°C)
FIGURE 2-8:
Input Offset Voltage vs.
FIGURE 2-11:
DC Open-Loop Gain vs.
Common Mode Voltage with VDD = 2.5V.
Ambient Temperature.
1000
10,000
VDD = 5.5V
VCM = VCMR_H
VDD = 5.5V
800
Representative Part
600
400
200
0
1,000
IB
100
10
1
-200
-400
-600
-40°C
+25°C
+85°C
+125°C
-IOS
-800
-1000
25
45
65
85
105
125
Input Common Mode Voltage (V)
Ambient Temperature (°C)
FIGURE 2-9:
Input Offset Voltage vs.
FIGURE 2-12:
Input Bias and Offset
Common Mode Voltage with VDD = 5.5V.
Currents vs. Ambient Temperature with
DD = +5.5V.
V
2009-2014 Microchip Technology Inc.
DS20002146D-page 9
MCP651/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS
.
160
1.E-10m3
1.E10-004µ
TA = +85°C
140
VDD = 5.5V
120
100
80
10µ
1.E-05
IB
1µ
1.E-06
100n
1.E-07
60
40
20
10n
1.E-08
1n
1.E-09
+125°C
+85°C
+25°C
-40°C
IOS
0
100p
1.E-10
-20
-40
-60
10p
1.E-11
1p
1.E-12
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-13:
Input Bias and Offset
FIGURE 2-15:
Input Bias Current vs. Input
Currents vs. Common Mode Input Voltage with
TA = +85°C.
Voltage (below VSS).
2000
TA = +125°C
VDD = 5.5V
1500
1000
500
IB
0
IOS
-500
-1000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
FIGURE 2-14:
Input Bias and Offset
Currents vs. Common Mode Input Voltage with
TA = +125°C.
DS20002146D-page 10
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS
.
2.2
Other DC Voltages and Currents
14
8
7
6
5
4
3
2
1
0
VDD = 5.5V
VOL – VSS
-IOUT
12
10
8
+125°C
+85°C
+25°C
-40°C
6
VDD – VOH
IOUT
4
VDD = 2.5V
2
0
1
10
100
Output Current Magnitude (mA)
Power Supply Voltage (V)
FIGURE 2-16:
Ratio of Output Voltage
FIGURE 2-19:
Supply Current vs. Power
Headroom to Output Current.
Supply Voltage.
14
9
8
7
6
5
RL = 1 kΩ
VDD = 5.5V
VOL – VSS
12
10
8
VDD = 5.5V
VDD = 2.5V
4
3
2
1
0
6
VDD – VOH
4
VDD = 2.5V
2
0
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Common Mode Input Voltage (V)
FIGURE 2-17:
Output Voltage Headroom
FIGURE 2-20:
Supply Current vs. Common
vs. Ambient Temperature.
Mode Input Voltage.
100
80
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
+125°C
+85°C
+25°C
-40°C
60
VPRH
40
20
VPRL
0
-20
-40
-60
-80
-100
-50
-25
0
25
50
75
100
125
Power Supply Voltage (V)
Ambient Temperature (°C)
FIGURE 2-18:
Output Short-Circuit Current
FIGURE 2-21:
Power-On Reset Voltages
vs. Power Supply Voltage.
vs. Ambient Temperature.
2009-2014 Microchip Technology Inc.
DS20002146D-page 11
MCP651/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS
.
30%
140
120
100
80
144 Samples
VDD = 2.5V and 5.5V
25%
20%
15%
10%
5%
60
40
0%
20
0
Normalized Internal Calibration Voltage;
CAL/VDD
-50
-25
0
25
50
75
100
125
V
Ambient Temperature (°C)
FIGURE 2-22:
Normalized Internal
FIGURE 2-23:
VCAL Input Resistance vs.
Calibration Voltage.
Temperature.
DS20002146D-page 12
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS
.
2.3
Frequency Response
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
70
60
50
40
30
20
10
PM
PSRR+
PSRR-
CMRR
VDD = 5.5V
VDD = 2.5V
GBWP
11.E0+02
1.1Ek+3
11.E0+k4
110.E0+k5
11.EM+6
11.0EM+7
Frequency (Hz)
Common Mode Input Voltage (V)
FIGURE 2-24:
CMRR and PSRR vs.
FIGURE 2-27:
Gain-Bandwidth Product
Frequency.
and Phase Margin vs. Common Mode Input
Voltage.
120
100
80
0
60
50
40
30
20
10
0
90
80
70
60
50
40
30
-30
VDD = 5.5V
-60
-90
GBWP
AOL
60
VDD = 2.5V
40
-120
-150
-180
-210
| AOL
|
20
PM
0
-20
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7 1.E+8 1.E+9
10 100 1k 10k 100k 1M 10M 100M 1G
Frequency (Hz)
FIGURE 2-25:
Open-Loop Gain vs.
FIGURE 2-28:
Gain-Bandwidth Product
Frequency.
and Phase Margin vs. Output Voltage.
1000
100
90
80
70
60
50
40
30
70
60
50
40
30
20
10
PM
G = 101 V/V
G = 11 V/V
G = 1 V/V
VDD = 5.5V
VDD = 2.5V
10
1
GBWP
0.1
-50 -25
0
25
50
75 100 125
1k
10k
100k
Frequency (Hz)
1M
10M
100M
1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08
Ambient Temperature (°C)
FIGURE 2-26:
Gain-Bandwidth Product
FIGURE 2-29:
Closed-Loop Output
and Phase Margin vs. Ambient Temperature.
Impedance vs. Frequency.
2009-2014 Microchip Technology Inc.
DS20002146D-page 13
MCP651/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS
.
10
9
8
7
6
150
140
130
120
110
100
90
RS = 0Ω
S = 1 kΩ
R
RTI
VCM = VDD/2
G = +1 V/V
G = 1 V/V
5
G = 2 V/V
4
3
2
1
0
G 4 V/V
80
70
RS = 10 kΩ
S = 100 kΩ
60
R
50
10p
100p
1n
10n
1.0E-09
1k
10k
1.E+04
100k
1.E+05
1M
1.E+06
10M
1.E+07
1.0E-11
1.0E-10
1.E+03
Frequency (Hz)
Normalized Capacitive Load; CL/G (F)
FIGURE 2-30:
Gain Peaking vs.
FIGURE 2-31:
Channel-to-Channel
Normalized Capacitive Load.
Separation vs. Frequency.
DS20002146D-page 14
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS
.
2.4
Input Noise and Distortion
1.E+4
10µ
20
15
10
5
Representative Part
NPBW = 0.1 Hz
1.E+3
1µ
0
1.E+2
100n
-5
-10
-15
-20
1.E+1
10n
1n
1.E+00.1
1
10
100 1k 10k 100k 1M 10M
0
5
10 15 20 25 30 35 40 45 50
1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7
Time (min)
Frequency (Hz)
FIGURE 2-32:
Input Noise Voltage Density
FIGURE 2-35:
Input Noise plus Offset vs.
vs. Frequency.
Time with 0.1 Hz Filter.
160
1
VDD = 5.0V
VDD = 2.5V
140
120
100
80
0.1
VDD = 5.5V
BW = 22 Hz to > 500 kHz
G = 1 V/V
G = 11 V/V
0.01
60
40
0.001
BW = 22 Hz to 80 kHz
20
f = 100 Hz
0
0.0001
11.E0+02
1.1Ek+3
11.E0+k4
11.0E0+5k
Frequency (Hz)
Common Mode Input Voltage (V)
FIGURE 2-33:
Input Noise Voltage Density
FIGURE 2-36:
THD+N vs. Frequency.
vs. Input Common Mode Voltage with f = 100 Hz.
12
11
10
9
VDD = 2.5V
8
7
VDD = 5.5V
6
5
4
3
2
1
f = 1 MHz
0
Common Mode Input Voltage (V)
FIGURE 2-34:
Input Noise Voltage Density
vs. Input Common Mode Voltage with f = 1 MHz.
2009-2014 Microchip Technology Inc.
DS20002146D-page 15
MCP651/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS
.
2.5
Time Response
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD = 5.5V
G = 1
VDD = 5.5V
G = -1
R
F = 499Ω
VIN
VIN
VOUT
VOUT
0
20 40 60 80 100 120 140 160 180 200
Time (ns)
0
100 200 300 400 500 600 700 800
Time (ns)
FIGURE 2-37:
Non-inverting Small Signal
FIGURE 2-40:
Inverting Large Signal Step
Step Response.
Response.
5.5
5.0
4.5
4.0
3.5
3.0
7
6
VDD = 5.5V
G = 1
VDD = 5.5V
G = 2
VIN
5
VOUT
4
3
2.5
VIN
VOUT
2
2.0
1.5
1.0
0.5
0.0
1
0
-1
0
1
2
3
4
5
6
7
8
9
10
0
100 200 300 400 500 600 700 800
Time (ns)
Time (ms)
FIGURE 2-38:
Non-inverting Large Signal
FIGURE 2-41:
The MCP651/1S/2/3/4/5/9
Step Response.
family shows no input phase reversal with
overdrive.
VIN
60
Falling Edge
55
50
45
40
35
30
25
20
15
10
5
VDD = 5.5V
VDD = 5.5V
G = -1
RF = 499Ω
VDD = 2.5V
Rising Edge
VOUT
0
50
100 150 200 250 300 350 400
Time (ns)
0
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-39:
Inverting Small Signal Step
Response.
FIGURE 2-42:
Slew Rate vs. Ambient
Temperature.
DS20002146D-page 16
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS
.
10
VDD = 5.5V
VDD = 2.5V
1
0.1
100k
1M
1.E+06
10M
1.E+07
100M
1.E+08
1.E+05
Frequency (Hz)
FIGURE 2-43:
Maximum Output Voltage
Swing vs. Frequency.
2009-2014 Microchip Technology Inc.
DS20002146D-page 17
MCP651/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS
.
2.6
Calibration and Chip Select Response
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
CAL/CS = VDD
VDD = 5.5V
VDD = 2.5V
-50
-25
0
25
50
75
100
125
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Ambient Temperature (°C)
FIGURE 2-44:
CAL/CS Current vs. Power
FIGURE 2-47:
CAL/CS Hysteresis vs.
Supply Voltage.
Ambient Temperature.
8
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD = 2.5V
6
G = 1
L = 0V
V
4
IDD
2
0
-2
Op Amp
turns off
Op Amp
Calibration
starts
CAL/CS
VOUT
3
2
turns on
1
0
-1
-50
-25
0
25
50
75
100
125
0
1
2
3
4
5
6
7
8
9
10
Time (ms)
Ambient Temperature (°C)
FIGURE 2-45:
CAL/CS Voltage, Output
FIGURE 2-48:
CAL/CS Turn-On Time vs.
Voltage and Supply Current (for Side A) vs. Time
with VDD = 2.5V.
Ambient Temperature.
8
6
5
4
3
2
1
0
-1
10
8
6
4
2
Representative Part
VDD = 5.5V
G = 1
VL = 0V
7
6
5
4
3
2
1
0
IDD
0
Op Amp
turns on
-2
Calibration
starts
Op Amp
turns off
CAL/CS
VOUT
0
1
2
3
4
5
6
7
8
9
10
-50
-25
0
25
50
75
100
125
Time (ms)
Ambient Temperature (°C)
FIGURE 2-46:
CAL/CS Voltage, Output
FIGURE 2-49:
CAL/CS’s Pull-Down
Voltage and Supply Current (for Side A) vs. Time
with VDD = 5.5V.
Resistor (RPD) vs. Ambient Temperature.
DS20002146D-page 18
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 1 kto VL, CL = 20 pF, and CAL/CS = VSS
.
0
1.E-06
1.E-07
1.E-08
1.E-09
1.E-10
1.E-11
CAL/CS = VDD = 5.5V
CAL/CS = VDD
-1
-2
-3
+125°C
+85°C
-4
+125°C
+85°C
+25°C
-40°C
-5
-6
+25°C
-7
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Output Voltage (V)
Power Supply Voltage (V)
FIGURE 2-50:
Quiescent Current in
FIGURE 2-51:
Output Leakage Current vs.
Shutdown vs. Power Supply Voltage.
Output Voltage.
2009-2014 Microchip Technology Inc.
DS20002146D-page 19
MCP651/1S/2/3/4/5/9
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
MCP651
PIN FUNCTION TABLE
MCP651S
MCP652
MCP653
MCP654
MCP655
MCP659
Symbol
Description
SOIC TDFN
SOT
1
SOIC DFN
SOT
1
SOIC TSSOP MSOP DFN
QFN
16
6
2
3
4
6
2
3
4
1
2
3
4
1
2
3
4
1
2
1
2
1
2
3
4
1
2
3
4
V
V
,
Output (op amp A)
OUT
OUTA
4
3
2
4
3
2
1
2
V
V
V
–, V
–
+
Inverting Input (op
amp A)
IN
INA
3
3
+, V
Non-inverting Input
(op amp A)
IN
INA
11
11
11
Negative Power
Supply
SS
8
8
—
—
—
5
—
—
5
5
—
CAL/CS,
CALA/CSA
Calibrate/Chip
Select Digital Input
(op amp A)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
6
—
15
7
CALB/CSB
Calibrate/Chip
Select Digital Input
(op amp B)
—
—
—
—
CALAD/
CSAD
Calibrate/Chip
Select Digital Input
(op amps A and D)
CALBC/
CSBC
Calibrate/Chip
Select Digital Input
(op amps B and C)
—
—
—
—
—
—
5
6
5
6
—
—
5
6
5
6
7
8
7
8
4
5
V
V
+
–
Non-inverting Input
(op amp B)
INB
INB
Inverting Input (op
amp B)
—
—
—
—
—
—
7
7
—
—
7
7
9
9
6
V
V
Output (op amp B)
OUTB
—
—
10
10
—
—
10
+
Non-inverting input
(op amp C)
INC
—
—
—
—
—
—
9
9
—
—
9
V
-
Inverting Input (op
amp C)
INC
—
—
—
—
—
—
—
—
—
—
—
—
8
8
—
—
—
—
8
V
V
Output (op amp C)
OUTC
12
12
12
+
Non-inverting Input
(op amp D)
IND
—
—
—
—
—
—
13
13
—
—
13
V
-
Inverting Input (op
amp D)
IND
—
7
—
7
—
5
—
8
—
8
—
6
14
4
14
4
—
—
14
3
V
V
Output (op amp D)
OUTD
DD
10
10
Positive Power
Supply
5
5
—
—
—
—
—
—
—
—
—
V
Calibration Com-
mon Mode Voltage
Input
CAL
1
1
9
—
—
—
—
—
9
—
—
—
—
—
—
—
—
—
11
—
NC
EP
No Internal
Connection
—
17
Exposed Thermal
Pad (EP); must be
connected to V
SS
DS20002146D-page 20
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
3.1
Analog Outputs
3.5
Calibrate/Chip Select Digital Input
The analog output pins (VOUT) are low-impedance
voltage sources.
This input (CAL/CS, …) is a CMOS, Schmitt-Triggered
input that affects the Calibration and Low-Power
modes of operation. When this pin goes high, the part
is placed into a Low-Power mode and the output is
High Z. When this pin goes low, a calibration sequence
is started (which corrects VOS). At the end of the cali-
bration sequence, the output becomes low-impedance
and the part resumes normal operation.
3.2
Analog Inputs
The non-inverting and inverting inputs (VIN+, VIN–, …)
are high-impedance CMOS inputs with low bias
currents.
An internal POR triggers a calibration event when the
part is powered on, or when the supply voltage drops
too low. Thus, the MCP652 parts are calibrated, even
though they do not have a CAL/CS pin.
3.3
Power Supply Pins
The positive power supply (VDD) is 2.5V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD
.
3.6
Exposed Thermal Pad (EP)
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
There is an internal connection between the Exposed
Thermal Pad (EP) and the VSS pin; they must be
connected to the same potential on the Printed Circuit
Board (PCB).
3.4
Calibration Common Mode
Voltage Input
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (JA).
A low-impedance voltage placed at this input (VCAL
)
will set the op amps’ Common mode input voltage
during calibration. If this pin is left open, the Common
mode input voltage during calibration is approximately
VDD/3. The internal resistor divider is disconnected
from the supplies whenever the part is not in calibra-
tion.
2009-2014 Microchip Technology Inc.
DS20002146D-page 21
MCP651/1S/2/3/4/5/9
For the MCP655 dual and the MCP659 quad, there is
an additional constraint on toggling the two CAL/CS
pins close together; see the tCON specification in
Table 1-3. If the two pins are toggled simultaneously, or
if they are toggled separately with an adequate delay
between them (greater than tCON), then the CAL/CS
inputs are accepted as valid. If one of the two pins
toggles while the other pin’s calibration routine is in
progress, then an invalid input occurs and the result is
unpredictable.
4.0
APPLICATIONS
The MCP651/1S/2/3/4/5/9 family of self-zeroed op
amps is manufactured using Microchip’s state-of-the-
art CMOS process. It is designed for low-cost, low-
power and high-precision applications. Its low supply
voltage, low quiescent current and wide bandwidth
makes the MCP651/1S/2/3/4/5/9 ideal for battery-
powered applications.
4.1
Calibration and Chip Select
4.1.3
INTERNAL POR
These op amps include circuitry for dynamic calibration
of the offset voltage (VOS).
This part includes an internal Power-On Reset (POR)
to protect the internal calibration memory cells. The
POR monitors the power supply voltage (VDD). When
the POR detects a low VDD event, it places the part into
the Low-Power mode of operation. When the POR
detects a normal VDD event, it starts a delay counter,
then triggers an calibration event. The additional delay
gives a total POR turn-on time of 200 ms (typical); this
is also the power-up time (since the POR is triggered at
power-up).
4.1.1
mCal CALIBRATION CIRCUITRY
The internal mCal circuitry, when activated, starts a
delay timer (to wait for the op amp to settle to its new
bias point), then calibrates the input offset voltage
(VOS). The mCal circuitry is triggered at power-up (and
after some power brown-out events) by the internal
POR, and by the memory’s Parity Detector. The power-
up time, when the mCal circuitry triggers the calibration
sequence, is 200 ms (typical).
4.1.4
PARITY DETECTOR
A parity error detector monitors the memory contents
for any corruption. In the rare event that a parity error is
detected (e.g., corruption from an alpha particle), a
POR event is automatically triggered. This will cause
the input offset voltage to be re-corrected, and the op
amp will not return to normal operation for a period of
time (the POR turn-on time, tPON).
4.1.2
CAL/CS PIN
The CAL/CS pin gives the user a means to externally
demand a Low-Power mode of operation, then to
calibrate VOS. Using the CAL/CS pin makes it possible
to correct VOS as it drifts over time (1/f noise and aging;
see Figure 2-35) and across temperature.
The CAL/CS pin performs two functions: it places the
op amp(s) in a Low-Power mode when it is held high,
and starts a calibration event (correction of VOS) after a
rising edge.
4.1.5
CALIBRATION INPUT PIN
A VCAL pin is available in some options (e.g., the single
MCP651) for those applications that need the
calibration to occur at an internally driven Common
mode voltage other than VDD/3.
While in the Low-Power mode, the quiescent current is
quite small (ISS = -3 µA, typical). The output is also in a
High Z state.
Figure 4-1 shows the reference circuit that internally
sets the op amp’s Common mode reference voltage
(VCM_INT
disconnected from the supplies at other times). The
5 k resistor provides over-current protection for the
buffer.
During the calibration event, the quiescent current is
near, but smaller than, the specified quiescent current
(6 mA, typical). The output continues in the High Z
state, and the inputs are disconnected from the
external circuit, to prevent internal signals from
affecting circuit operation. The op amp inputs are
internally connected to a Common mode voltage buffer
and feedback resistors. The offset is corrected (using a
digital state machine, logic and memory), and the
calibration constants are stored in memory.
)
during calibration (the resistors are
To op amp during
VDD
calibration
VCM_INT
300 k
5 k
Once the calibration event is completed, the amplifier is
reconnected to the external circuitry. The turn-on time,
when calibration is started with the CAL/CS pin, is 3 ms
(typical).
VCAL
BUFFER
150 k
There is an internal 5 M pull-down resistor tied to the
CAL/CS pin. If the CAL/CS pin is left floating, the
amplifier operates normally.
VSS
FIGURE 4-1:
Common-Mode Reference’s
Input Circuitry.
DS20002146D-page 22
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
When the VCAL pin is left open, the internal resistor
divider generates a VCM_INT of approximately VDD/3,
which is near the center of the input Common mode
voltage range. It is recommended that an external
capacitor from VCAL to ground be added to improve
noise immunity.
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
Bond
VDD
Pad
When the VCAL pin is driven by an external voltage
source, which is within its specified range, the op amp
will have its input offset voltage calibrated at that
Common mode input voltage. Make sure that VCAL is
within its specified range.
Bond
Pad
Bond
Pad
Input
Stage
VIN+
VIN–
It is possible to use an external resistor voltage divider
to modify VCM_INT; see Figure 4-2. The internal circuitry
at the VCAL pin looks like 100 k tied to VDD/3. The
parallel equivalent of R1 and R2 should be much
smaller than 100 k to minimize differences in
matching and temperature drift between the internal
and external resistors. Again, make sure that VCAL is
within its specified range.
Bond
Pad
VSS
FIGURE 4-3:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Section 1.1
“Absolute Maximum Ratings †”). Figure 4-4 shows
the recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (VIN+
and VIN–) from going too far below ground, and the
resistors R1 and R2 limit the possible current drawn out
of the input pins. Diodes D1 and D2 prevent the input
pins (VIN+ and VIN–) from going too far above VDD, and
dump any currents onto VDD. When implemented as
shown, resistors R1 and R2 also limit the current
through D1 and D2.
VDD
MCP65X
R1
VCAL
C1
R2
VSS
FIGURE 4-2:
Resistors.
Setting VCM with External
VDD
For instance, a design goal to set VCM_INT = 0.1V when
DD = 2.5V could be met with: R1 = 24.3 k,
R2 = 1.00 k and C1 = 100 nF. This will keep VCAL
within its range for any VDD, and should be close
enough to 0V for ground-based applications.
D1
R1
D2
V
MCP65X
V1
V2
VOUT
R2
4.2
Input
PHASE REVERSAL
VSS – (minimum expected V1)
R1 >
R2 >
4.2.1
2 mA
VSS – (minimum expected V2)
2 mA
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-41 shows an input voltage
exceeding both supplies with no phase inversion.
FIGURE 4-4:
Protecting the Analog
Inputs.
4.2.2
INPUT VOLTAGE AND CURRENT
LIMITS
It is also possible to connect the diodes to the left of the
resistor R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
The ESD protection on the inputs can be depicted as
shown in Figure 4-3. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
2009-2014 Microchip Technology Inc.
DS20002146D-page 23
MCP651/1S/2/3/4/5/9
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the Common
mode voltage (VCM) is below ground (VSS); see
Figure 2-15. Applications that are high-impedance may
need to limit the usable voltage range.
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
VOH Limited
(VDD = 5.5V)
RL = 1 kΩ
RL = 100Ω
RL = 10Ω
4.2.3
NORMAL OPERATION
The input stage of the MCP651/1S/2/3/4/5/9 op amps
uses a differential PMOS input stage. It operates at low
Common mode input voltage (VCM), with VCM up to
VDD – 1.3V and down to VSS – 0.3V. The input offset
voltage (VOS) is measured at VCM = VSS – 0.3V and
VDD – 1.3V to ensure proper operation. See Figure 2-6
and Figure 2-7 for temperature effects.
VOL Limited
IOUT (mA)
FIGURE 4-6:
Output Current.
When operating at very low non-inverting gains, the
output voltage is limited at the top by the VCM range
(< VDD – 1.3V); see Figure 4-5.
VDD
MCP65X
VIN
VOUT
VSS VIN VOUT VDD – 1.3V
FIGURE 4-5:
Unity-Gain Voltage
Limitations for Linear Operation.
4.3
Rail-to-Rail Output
4.3.0.1
Maximum Output Voltage
The Maximum Output Voltage (see Figure 2-16 and
Figure 2-17) describes the output range for a given
load. For instance, the output voltage swings to within
15 mV of the negative rail with a 1 k load tied to
VDD/2.
4.3.0.2
Output Current
Figure 4-6 shows the possible combinations of output
voltage (VOUT) and output current (IOUT). IOUT is
positive when it flows out of the op amp into the
external circuit.
DS20002146D-page 24
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
Figure 4-7 shows a capacitive load (CL), which is
driven by a sine wave with DC offset. The capacitive
load causes the op amp to output higher currents at
4.3.0.3
Power Dissipation
Since the output short circuit current (ISC) is specified
at ±100 mA (typical), these op amps are capable of
both delivering and dissipating significant power. Two
common loads, and their impact on the op amp’s power
dissipation, will be discussed.
higher frequencies. Because the output rectifies IOUT
,
the op amp’s dissipated power increases (even though
the capacitor does not dissipate power).
Figure 4-7 shows a resistive load (RL) with a DC output
voltage (VOUT). VL is RL’s ground point, VSS is usually
ground (0V) and IOUT is the output current. The input
currents are assumed to be negligible.
VDD
IDD
IOUT
VOUT
MCP65X
VDD
CL
ISS
IDD
IOUT
VSS
VOUT
MCP65X
FIGURE 4-8:
Power Calculations.
Diagram for Capacitive Load
RL
ISS
The output voltage is assumed to be:
VSS
VL
EQUATION 4-4:
FIGURE 4-7:
Power Calculations.
Diagram for Resistive Load
VOUT = VDC + VAC sint
Where:
The DC currents are:
VDC = DC offset (V)
VAC = Peak output swing (VPK
)
EQUATION 4-1:
= Radian frequency (2 f) (rad/s)
VOUT – VL
IOUT = -------------------------
RL
The op amp’s currents are:
EQUATION 4-5:
IDD IQ + max0, IOUT
ISS –IQ + min0, IOUT
Where:
dVOUT
IOUT = CL ---------------- = VACCL cost
dt
IQ = Quiescent supply current for one
op amp (mA/amplifier)
IDD IQ + max0, IOUT
ISS –IQ + min0, IOUT
VOUT = A DC value (V)
Where:
The DC op amp power is:
IQ = Quiescent supply current for one
EQUATION 4-2:
op amp (mA/amplifier)
POA = IDDVDD – VOUT + ISSVSS – VOUT
The op amp’s instantaneous power, average power
and peak power are:
The maximum op amp power, for resistive loads at DC,
occurs when VOUT is halfway between VDD and VL or
halfway between VSS and VL:
EQUATION 4-6:
POA = IDDVDD – VOUT + ISSVSS – VOUT
EQUATION 4-3:
4VAC fCL
avePOA = VDD – VSS IQ + -----------------------
maxPOA = IDDVDD – VSS
max2VDD – VL VL – VSS
maxPOA = VDD – VSSIQ + 2VAC fCL
+ -----------------------------------------------------------------
4RL
The power dissipated in a package depends on the
powers dissipated by each op amp in that package:
2009-2014 Microchip Technology Inc.
DS20002146D-page 25
MCP651/1S/2/3/4/5/9
When driving large capacitive loads with these op
amps (e.g., > 20 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-9) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
EQUATION 4-7:
n
P
PPKG
=
OA
k = 1
Where:
n = Number of op amps in package (1 or 2)
The maximum ambient to junction temperature rise
(TJA) and junction temperature (TJ) can be calculated
using the maximum expected package power (PPKG),
ambient temperature (TA) and the package thermal
resistance (JA) found in Table 1-4:
RISO
CL
RG
RF
VOUT
MCP65X
Output Resistor, RISO
RN
EQUATION 4-8:
FIGURE 4-9:
TJA = PPKGJA
TJ = TA + TJA
Stabilizes Large Capacitive Loads.
Figure 4-10 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
The worst-case power de-rating for the op amps in a
particular package can be easily calculated:
EQUATION 4-9:
TJmax – TA
PPKG --------------------------
100
JA
Where:
TJmax = Absolute maximum junction
temperature (°C)
10
TA = Ambient temperature (°C)
GN = +1
GN +2
Several techniques are available to reduce TJA for a
given package:
1
10p
100p
1.E-10
1n
1.E-09
10n
1.E-08
• Reduce JA
- Use another package
1.E-11
Normalized Capacitance; CL/GN (F)
- Improve the PCB layout (ground plane, etc.)
- Add heat sinks and air flow
FIGURE 4-10:
for Capacitive Loads.
Recommended RISO Values
• Reduce max(PPKG
- Increase RL
)
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP651/1S/2/3/4/5/9 SPICE
macro model are helpful.
- Decrease CL
- Limit IOUT using RISO (see Figure 4-9)
- Decrease VDD
4.4
4.4.1
Improving Stability
4.4.2
GAIN PEAKING
Figure 4-11 shows an op amp circuit that represents
non-inverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage
and VM is the input). The capacitances CN and CG
represent the total capacitance at the input pins; they
include the op amp’s Common mode input capacitance
(CCM), board parasitic capacitance and any capacitor
placed in parallel.
CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. See Figure 2-30.
A unity-gain buffer
(G = +1) is the most sensitive to capacitive loads,
though all gains show the same general behavior.
DS20002146D-page 26
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
EQUATION 4-10:
Given:
CN
RN
GN1 = 1 + RF RG
MCP65X
VP
GN2 = 1 + CG CF
fF = 1 2RFCF
VOUT
VM
fZ = fFGN1 GN2
We need:
RG
RF
CG
fF fGBWP 2GN2, GN1 < GN2
fF fGBWP 4GN1, GN1 > GN2
FIGURE 4-11:
Amplifier with Parasitic
Capacitance.
4.5
Power Supply
CG acts in parallel with RG (except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
CG also reduces the phase margin of the feedback
loop, which becomes less stable. This effect can be
reduced by either reducing CG or RF.
With this family of operational amplifiers, the Power
Supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. Surface mount,
multilayer ceramic capacitors, or their equivalent,
should be used.
CN and RN form a low-pass filter that affects the signal
at VP. This filter has a single real pole at 1/(2RNCN).
The largest value of RF that should be used depends
on noise gain (see GN in Section 4.4.1 “Capacitive
Loads”) and CG. Figure 4-12 shows the maximum
recommended RF for several CG values.
These op amps require a bulk capacitor (i.e., 2.2 µF or
larger) within 50 mm to provide large, slow currents.
Tantalum capacitors, or their equivalent, may be a good
choice. This bulk capacitor can be shared with other
nearby analog parts as long as crosstalk through the
supplies does not prove to be a problem.
1.E+05
100k
GN > +1 V/V
CG = 10 pF
G = 32 pF
CG = 100 pF
CG = 320 pF
CG = 1 nF
4.6
High-Speed PCB Layout
C
1.E+04
10k
These op amps are fast enough that a little extra care
in the PCB (Printed Circuit Board) layout can make a
significant difference in performance. Good PCB layout
techniques will help achieve the performance shown in
the specifications and Typical Performance Curves; it
will also help minimize EMC (Electro-Magnetic Com-
patibility) issues.
1.E+013k
1.E+10020
1
10
100
Noise Gain; GN (V/V)
Use a solid ground plane. Connect the bypass local
capacitor(s) to this plane with minimal length traces to
cut down inductive and capacitive crosstalk.
FIGURE 4-12:
Maximum Recommended
RF vs. Gain.
Separate digital from analog, low-speed from high-
speed, and low-power from high-power. This will
reduce interference.
Figure 2-37 and Figure 2-38 show the small signal and
large signal step responses at G = +1 V/V. The unity-
gain buffer usually has RF = 0 and RG open.
Keep sensitive traces short and straight. Separate
them from interfering components and traces. This is
especially important for high-frequency (low rise time)
signals.
Figure 2-39 and Figure 2-40 show the small signal and
large signal step responses at G = -1 V/V. Since the
noise gain is 2 V/V and CG 10 pF, the resistors were
chosen to be RF = RG = 499 and RN = 249.
Sometimes, it helps to place guard traces next to victim
traces. They should be on both sides of the victim
trace, and as close as possible. Connect guard traces
to ground plane at both ends, and in the middle for long
traces.
It is also possible to add a capacitor (CF) in parallel with
RF to compensate for the de-stabilizing effect of CG.
This makes it possible to use larger values of RF. The
conditions for stability are summarized in Equation 4-
10.
Use coax cables, or low inductance wiring, to route
signal and power to and from the PCB. Mutual and self
inductance of power wires is often a cause of crosstalk
and unusual behavior.
2009-2014 Microchip Technology Inc.
DS20002146D-page 27
MCP651/1S/2/3/4/5/9
4.7.3
H-BRIDGE DRIVER
4.7
Typical Applications
Figure 4-15 shows the MCP652 dual op amp used as
a H-bridge driver. The load could be a speaker or a DC
motor.
4.7.1
POWER DRIVER WITH HIGH GAIN
Figure 4-13 shows a power driver with high gain
(1 + R2/R1). The MCP651/1S/2/3/4/5/9 op amp’s short-
circuit current makes it possible to drive significant
loads. The calibrated input offset voltage supports
accurate response at high gains. R3 should be small,
and equal to R1||R2, in order to minimize the bias
current induced offset.
½ MCP652
VIN
VOT
RF
RF
RF
R1
R3
R2
RL
RGT
RGB
VDD/2
VOUT
RL
VOB
VIN
MCP65X
VDD/2
½ MCP652
H-Bridge Driver.
FIGURE 4-13:
Power Driver.
FIGURE 4-15:
4.7.2
OPTICAL DETECTOR AMPLIFIER
This circuit automatically makes the noise gains (GN)
equal, when the gains are set properly, so that the
frequency responses match well (in magnitude and in
phase). Equation 4-11 shows how to calculate RGT and
RGB so that both op amps have the same DC gains;
GDM needs to be selected first.
Figure 4-14 shows a transimpedance amplifier, using
the MCP651 op amp, in a photo detector circuit. The
photo detector is a capacitive current source. The op
amp’s input Common mode capacitance (5 pF, typical)
acts in parallel with CD. RF provides enough gain to
produce 10 mV at VOUT. CF stabilizes the gain and lim-
its the transimpedance bandwidth to about 1.1 MHz.
RF’s parasitic capacitance (e.g., 0.2 pF for a 0805
SMD) acts in parallel with CF.
EQUATION 4-11:
VOT – VOB
GDM -------------------------------- 2 V / V
V
IN – VDD 2
RF
CF
1.5 pF
RGT = --------------------------------
GDM 2 – 1
RF
Photo
Detector
RGB = ------------------
RF
GDM 2
100 k
VOUT
Equation 4-12 gives the resulting Common mode and
Differential mode output voltages.
ID
100 nA
CD
30 pF
EQUATION 4-12:
MCP651
VDD/2
VOT + VOB
VDD
-------------------------- = ----------
2
2
FIGURE 4-14:
for an Optical Detector.
Transimpedance Amplifier
VDD
VIN – ----------
VOT – VOB = G
DM
2
DS20002146D-page 28
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
Some boards that are especially useful are:
5.0
DESIGN AIDS
• MCP6XXX Amplifier Evaluation Board 1
• MCP6XXX Amplifier Evaluation Board 2
• MCP6XXX Amplifier Evaluation Board 3
• MCP6XXX Amplifier Evaluation Board 4
• Active Filter Demo Board Kit
Microchip provides the basic design aids needed for
the MCP651/1S/2/3/4/5/9 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the
MCP651/1S/2/3/4/5/9 op amps is available on the
Microchip web site at www.microchip.com. This model
is intended to be an initial design tool that works well in
the op amp’s linear region of operation over the
temperature range. See the model file for information
on its capabilities.
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
5.5
Application Notes
The following Microchip Application Notes are
available on the Microchip web site at www.microchip.
com/appnotes and are recommended as supplemental
reference resources.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
• ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits” (DS21821)
• AN722: “Operational Amplifier Topologies and DC
Specifications” (DS00722)
®
5.2
FilterLab Software
• AN723: “Operational Amplifier AC Specifications
and Applications” (DS00723)
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
• AN884: “Driving Capacitive Loads With Op Amps”
(DS00884)
• AN990: “Analog Sensor Conditioning Circuits –
An Overview” (DS00990)
• AN1177: “Op Amp Precision Design: DC Errors”
(DS01177)
• AN1228: “Op Amp Precision Design: Random
Noise” (DS01228)
• AN1332: “Current Sensing Circuit Concepts and
Fundamentals” (DS01332)
5.3
Microchip Advanced Part Selector
(MAPS)
Some of these application notes, and others, are listed
in the design guide:
MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design require-
ment. Available at no cost from the Microchip web site
at www.microchip.com/maps, the MAPS is an overall
selection tool for Microchip’s product portfolio that
includes Analog, Memory, MCUs and DSCs. Using this
tool, a customer can define a filter to sort features for a
parametric search of devices and export side-by-side
technical comparison reports. Helpful links are also
provided for data sheets, purchase and sampling of
Microchip parts.
• “Signal Chain Design Guide” (DS21825)
5.4
Analog Demonstration and
Evaluation Boards
Microchip offers
a
broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help customers achieve faster time to
market. For a complete listing of these boards and their
corresponding user’s guides and technical information,
visit
the
Microchip
web
site
at
www.microchip.com/analog tools.
2009-2014 Microchip Technology Inc.
DS20002146D-page 29
MCP651/1S/2/3/4/5/9
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
Example:
YW25
5-Lead SOT-23 (2x3) (MCP651S)
XXNN
6-Lead SOT-23 (2x3) (MCP653)
Example:
JD25
XXNN
Example:
8-Lead TDFN(2x3) (MCP651)
AAZ
124
25
Example:
8-Lead DFN (3x3) (MCP652)
Device
MCP652
Code
XXXX
DABP
1124
256
DABP
YYWW
NNN
Note: Applies to 8-Lead
3x3 DFN
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS20002146D-page 30
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
6.2
Package Marking Information
8-Lead SOIC (150 mil) (MCP651, MCP652)
Example:
MCP651E
XXXXXXXX
XXXXYYWW
e
3
SN 1124
256
NNN
Example:
10-Lead DFN (3x3) (MCP655)
XXXX
YYWW
NNN
BAFC
1124
256
Example:
10-Lead MSOP (MCP655)
655EUN
XXXXXX
YWWNNN
124256
14-Lead SOIC (MCP654)
Example:
MCP654
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
e
3
E/SL
1124256
14-Lead TSSOP (MCP654)
Example:
XXXXXXXX
654E/ST
YYWW
NNN
1124
256
16-Lead QFN (4x4) (MCP659)
Example:
659
XXXXXXX
XXXXXXX
YWWNNN
e
3
E/ML
124256
2009-2014 Microchip Technology Inc.
DS20002146D-page 31
MCP651/1S/2/3/4/5/9
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N
E
E1
3
2
1
e
e1
D
A2
c
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L
L1
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ꢠꢜꢡꢢ ꢠꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉꢣꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏꢤꢉꢅꢖꢊꢎꢍꢉꢥꢊꢏꢐꢅꢉꢇꢒꢈꢦꢆꢉꢦꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ
ꢕꢃꢎꢓꢈꢎꢒꢃꢔ ꢣꢅꢎꢒꢆꢈꢏꢈꢚꢤ ꢂꢓꢊꢦꢃꢆꢚ ꢡꢗꢞꢼꢗꢴꢀꢠ
DS20002146D-page 32
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002146D-page 33
MCP651/1S/2/3/4/5/9
6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
b
4
N
E
E1
PIN 1 ID BY
LASER MARK
1
2
3
e
e1
D
c
A
φ
A2
L
A1
L1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
6
0.95 BSC
Outside Lead Pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
Footprint
Foot Angle
Lead Thickness
Lead Width
e1
A
A2
A1
E
E1
D
L
1.90 BSC
0.90
0.89
0.00
2.20
1.30
2.70
0.10
0.35
0°
–
–
–
–
–
–
–
–
–
–
–
1.45
1.30
0.15
3.20
1.80
3.10
0.60
0.80
30°
L1
I
c
b
0.08
0.20
0.26
0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-028B
DS20002146D-page 34
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002146D-page 35
MCP651/1S/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002146D-page 36
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002146D-page 37
MCP651/1S/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002146D-page 38
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002146D-page 39
MCP651/1S/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002146D-page 40
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
ꢝꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢛꢖꢆMꢆꢛꢄꢓꢓꢔ"#ꢆꢙ$%&ꢆꢎꢎꢆ'ꢔꢅ*ꢆꢗꢍꢏ+,ꢚ
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ꢒꢍꢍꢔꢢꢫꢫꢦꢦꢦꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄꢫꢔꢊꢎꢨꢊꢚꢃꢆꢚ
2009-2014 Microchip Technology Inc.
DS20002146D-page 41
MCP651/1S/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002146D-page 42
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002146D-page 43
MCP651/1S/2/3/4/5/9
ꢝꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ.ꢐꢄꢈꢆ/ꢈꢄꢊ#ꢆꢛꢔꢆꢂꢃꢄꢅꢆꢇꢄꢌ0ꢄ1ꢃꢆꢕ4ꢛꢖꢆMꢆꢘ5ꢙ5&$7ꢀꢆꢎꢎꢆ'ꢔꢅ*ꢆꢗꢒ./ꢛꢚ
ꢛꢔꢊꢃꢜ ꢧꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎꢨꢊꢚꢅꢉꢋꢓꢊꢦꢃꢆꢚꢇꢩꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉꢪꢊꢎꢨꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔꢢꢫꢫꢦꢦꢦꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄꢫꢔꢊꢎꢨꢊꢚꢃꢆꢚ
DS20002146D-page 44
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002146D-page 45
MCP651/1S/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002146D-page 46
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002146D-page 47
MCP651/1S/2/3/4/5/9
UN
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002146D-page 48
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
UN
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002146D-page 49
MCP651/1S/2/3/4/5/9
10-Lead Plastic Micro Small Outline Package (UN) [MSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002146D-page 50
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002146D-page 51
MCP651/1S/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002146D-page 52
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
ꢛꢔꢊꢃꢜ ꢧꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎꢨꢊꢚꢅꢉꢋꢓꢊꢦꢃꢆꢚꢇꢩꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉꢪꢊꢎꢨꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ
ꢒꢍꢍꢔꢢꢫꢫꢦꢦꢦꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄꢫꢔꢊꢎꢨꢊꢚꢃꢆꢚ
2009-2014 Microchip Technology Inc.
DS20002146D-page 53
MCP651/1S/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002146D-page 54
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc.
DS20002146D-page 55
MCP651/1S/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002146D-page 56
2009-2014 Microchip Technology Inc.
MCP651/1S/2/3/4/5/9
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ꢯꢌꢧꢢ ꢯꢅꢑꢅꢓꢅꢆꢎꢅꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢩꢉꢐꢇꢐꢊꢏꢏꢤꢉꢦꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢩꢉꢑꢈꢓꢉꢃꢆꢑꢈꢓꢄꢊꢍꢃꢈꢆꢉꢔꢐꢓꢔꢈꢇꢅꢇꢉꢈꢆꢏꢤꢁ
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2009-2014 Microchip Technology Inc.
DS20002146D-page 57
MCP651/1S/2/3/4/5/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002146D-page 58
2009-2014 Microchip Technology Inc.
MCP651/2/3/4/5/9
APPENDIX A: REVISION HISTORY
Revision D (July 2014)
The following is a list of modifications:
1. Updated the title of the document.
2. Added the High Gain-Bandwidth Op Amp
Portfolio table and updated all sections on
page 1.
Revision C (June 2011)
The following is a list of modifications:
3. Added the 2x3 TDFN (8L) package option for
MCP651, SOT-23 (5L) package for MCP651S
and SOT-23 (6L) package option for MCP653
and the related information throughout the
document.
Revision B (March 2011)
The following is a list of modifications:
1. Added the MCP654 and MCP659 amplifiers to
the product family and the related information
throughout the document.
2. Added the corresponding SOIC (14L), TSSOP
(14L) and QFN (16L) package options and
related information.
Revision A (April 2009)
• Original Release of this Document.
2009-2014 Microchip Technology Inc.
DS20002146D-page 59
MCP651/2/3/4/5/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
-X
/XX
a) MCP651ST-E/OT: Tape and Reel,
Extended Temperature,
Temperature
Range
Package
5LD SOT package.
Tape and Reel,
b) MCP651T-E/SN:
Extended Temperature,
8LD SOIC package.
c) MCP651T-E/MNY: Tape and Reel,
Extended Temperature,
Device:
MCP651:
Single Op Amp
MCP651T: Single Op Amp (Tape and Reel) (SOIC)
MCP651S: Single Op Amp (SOT)
MCP652:
MCP652T: Dual Op Amp (Tape and Reel) (DFN and
SOIC)
MCP653T: Single Op Amp (Tape and Reel) (SOT)
8LD TDFN package.
Tape and Reel,
Extended Temperature,
8LD DFN package.
Tape and Reel,
Dual Op Amp
d) MCP652T-E/MF:
e) MCP652T-E/SN:
MCP654:
Quad Op Amp
Extended Temperature,
8LD SOIC package.
MCP654T: Quad Op Amp (Tape and Reel) (TSSOP and
SOIC)
MCP655:
Dual Op Amp
f) MCP653T-E/CHY: Tape and Reel,
Extended Temperature,
MCP655T: Dual Op Amp (Tape and Reel) (DFN and
MSOP)
MCP659:
6LD SOT package.
Quad Op Amp
g) MCP654T-E/SL:
h) MCP654T-E/ST:
i) MCP655T-E/MF:
j) MCP655T-E/UN:
k) MCP659T-E/ML:
Tape and Reel,
Extended Temperature,
14LD SOIC package.
Tape and Reel,
Extended Temperature,
14LD TSSOP package.
Tape and Reel,
Extended Temperature,
10LD DFN package.
Tape and Reel,
Extended Temperature,
10LD MSOP package.
MCP659T: Quad Op Amp (Tape and Reel) (QFN)
Temperature Range:
Package:
E
=
-40°C to +125°C
OT
CHY
SN
MNY
MF
=
=
=
=
=
Plastic Small Outline, (2x3 SOT), 5-lead
Plastic Small Outline, (2x3 SOT), 6-lead
Plastic Small Outline, (3.90 mm), 8-lead
Plastic Dual Flat, (2x3 TDFN), 8-lead
Plastic Dual Flat, No Lead (3x3 DFN),
8-lead, 10-lead
Plastic Micro Small Outline, (MSOP), 10-lead
Plastic Thin Shrink Small Outline, (4.4 mm),
14-lead
Tape and Reel,
Extended Temperature,
16LD QFN package.
UN
ST
=
=
SL
=
=
Plastic Small Outline, Narrow, (3.90 mm),
14-lead
Plastic Quad Flat, No Lead Package,
(4x4x0.9 mm), 16-lead
ML
* Y = Nickel palladium gold manufacturing designator. Only available
on the TDFN package.
DS20002146D-page 60
2009-2014 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
32
OptoLyzer, PIC, PICSTART, PIC logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2014, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63276-393-8
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2009-2014 Microchip Technology Inc.
DS20002146D-page 61
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-3019-1500
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
www.microchip.com
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Germany - Dusseldorf
Tel: 49-2129-3766400
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Austin, TX
Tel: 512-257-3370
Germany - Pforzheim
Tel: 49-7231-424750
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Boston
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
Italy - Venice
Tel: 39-049-7625286
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Poland - Warsaw
Tel: 48-22-3325737
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Sweden - Stockholm
Tel: 46-8-5090-4654
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Detroit
Novi, MI
Tel: 248-848-4000
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Houston, TX
Tel: 281-894-5983
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Taiwan - Kaohsiung
Tel: 886-7-213-7830
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Los Angeles
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
03/25/14
DS20002146D-page 62
2009-2014 Microchip Technology Inc.
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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