MCP654-E/SN_技术文档

MCP651/2/4/5/9

50 MHz, 6 mA Op Amps with mCal

Features

Description

• Gain Bandwidth Product: 50 MHz (typical)

• Short Circuit Current: 100 mA (typical)

• Noise: 7.5 nV/√Hz (typical, at 1 MHz)

• Calibrated Input Offset: ±200 µV (maximum)

• Rail-to-Rail Output

The Microchip Technology, Inc. MCP651/2/4/5/9 family

of operational amplifiers features low offset. At power

up, these op amps are self-calibrated using mCal.

Some package options also provide a calibration/chip

select pin (CAL/CS) that supports a low power mode of

operation, with offset calibration at the time normal

operation is re-started. These amplifiers are optimized

for high speed, low noise and distortion, single-supply

operation with rail-to-rail output and an input that

includes the negative rail.

• Slew Rate: 30 V/µs (typical)

• Supply Current: 6.0 mA (typical)

• Power Supply: 2.5V to 5.5V

• Extended Temperature Range: -40°C to +125°C

This family is offered in single with CAL/CS pin

(MCP651), dual (MCP652), dual with CAL/CS pins

(MCP655), quad (MCP654) and quad with CAL/CS

pins (MCP659). All devices are fully specified from

-40°C to +125°C.

Typical Applications

• Driving A/D Converters

• Power Amplifier Control Loops

• Barcode Scanners

Typical Application Circuit

• Optical Detector Amplifier

R₁

R₂

Design Aids

V_DD/2

V_OUT

R_L

• SPICE Macro Models

R₃

• FilterLab^®Software

MCP65X

V_IN

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

Power Driver with High Gain

Package Types

MCP654

SOIC, TSSOP

MCP651

SOIC

MCP652

3×3 DFN *

MCP652

SOIC

V_OUTA

V_DD

1

8

7

1

2

3

4

8

V

NC

CAL/CS

V_DD

V

OUTA

V_DD

1

2

3

4

5

6

7

14

13

12

11

10

9

OUTD

1

8

7

6

5

V_OUTA

7

6

5

V

-

V_IN

–

+

V_INA

–

+

V_OUTB

V

-

INA

2

V_OUTB

EP

9

2

3

4

IND

V_INA

–

+

V

+

V_IN

V_OUT

V_CAL

V_INB

–

+

V_INA

V_INB

–

+

INA

3

4

6

5

IND

SS

V

V_SS

DD

+

V

+

-

INB

INC

V

-

INB

V

8

OUTB

OUTC

16 15 14 13

MCP659

4x4 QFN*

MCP655

MSOP

V_INA

-

V_IND

V_SS

+

1

12

3×3 DFN *

V_INA

V_DD

V_INB

+

11

10

9

2

3

4

EP

17

V_OUTA

V

DD

1

10

9

V_INC

+

-

V

V_OUTA

1

2

3

4

5

10

9

DD

V_INA

–

+

V_OUTB

+

2

3

V_OUTB

V_INA

–

+

EP

11

5

6

7

8

V_INA

V_INB

–

+

8

V_INB

–

+

8

V_SS

4

5

7

6

7

CALA/CSA

CALB/CSB CALA/CSA

CALB/CSB

6

* Includes Exposed Thermal Pad (EP); see Table 3-1.

DS22146B-page 1

MCP651/2/4/5/9

NOTES:

DS22146B-page 2

MCP651/2/4/5/9

1.0

1.1

ELECTRICAL CHARACTERISTICS

† Notice: Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of

the device at those or any other conditions above those

indicated in the operational listings of this specification is not

implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

Absolute Maximum Ratings †

V

– V

.......................................................................6.5V

SS

DD

Current at Input Pins ....................................................±2 mA

Analog Inputs (V + and V –) †† . V – 1.0V to V + 1.0V

IN

SS

DD

All other Inputs and Outputs .......... V – 0.3V to V + 0.3V

SS

DD

Difference Input voltage ...................................... |V – V

|

SS

DD

†† See Section 4.2.2 “Input Voltage and Current Limits”.

Output Short Circuit Current ................................Continuous

Current at Output and Supply Pins ..........................±150 mA

Storage Temperature ...................................-65°C to +150°C

Max. Junction Temperature ........................................+150°C

ESD protection on all pins (HBM, MM) ................≥ 1 kV, 200V

1.2

Specifications

DC ELECTRICAL SPECIFICATIONS

TABLE 1-1:

Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V

= V /3,

DD

A

DD

SS

CM

V

≈ V /2, V = V /2, R = 1 kΩ to V and CAL/CS = V (refer to Figure 1-2).

OUT

DD

L

DD

L

SS

Parameters

Sym

Min

Typ

Max

Units

Conditions

Input Offset

Input Offset Voltage

V

-200

—

37

+200

200

—

µV

After calibration (Note 1)

OS

Input Offset Voltage Trim Step

Input Offset Voltage Drift

Power Supply Rejection Ratio

Input Current and Impedance

Input Bias Current

V

OSTRM

ΔV /ΔT

—

±2.5

76

µV/°C T = -40°C to +125°C

OS

A

PSRR

61

—

dB

I

—

6

—

pA

B

Across Temperature

130

1700

±1

pA

T = +85°C

A

Across Temperature

5,000

—

T = +125°C

A

Input Offset Current

I

pA

OS

13

Common Mode Input Impedance

Differential Input Impedance

Common Mode

Z

10 ||9

—

Ω||pF

CM

13

Z

10 ||2

—

DIFF

Common-Mode Input Voltage Range

Common-Mode Rejection Ratio

V

− 0.3

—

81

84

V

− 1.3

DD

V

(Note 2)

CMR

SS

CMRR

65

68

—

dB

V

= 2.5V, V

= 5.5V, V

= -0.3 to 1.2V

= -0.3 to 4.2V

DD

CM

—

CM

Open-Loop Gain

DC Open-Loop Gain (large signal)

A

88

94

114

123

—

dB

V

= 2.5V, V

= 5.5V, V

= 0.3V to 2.2V

= 0.3V to 5.2V

OL

DD

OUT

OL

OUT

Output

Maximum Output Voltage Swing

V

, V

V

+ 25

—

V

− 25

mV

V

= 2.5V, G = +2,

DD

OL

OH

SS

DD

0.5V Input Overdrive

V = 5.5V, G = +2,

DD

+ 50

− 50

OL

SS

0.5V Input Overdrive

Output Short Circuit Current

I

±50

±95

±145

±150

mA

V

= 2.5V (Note 3)

= 5.5V (Note 3)

SC

DD

±100

Note 1: Describes the offset (under the specified conditions) right after power up, or just after the CAL/CS pin is toggled. Thus,

1/f noise effects (an apparent wander in V ; see Figure 2-35) are not included.

OS

2: See Figure 2-6 and Figure 2-7 for temperature effects.

3: The I specifications are for design guidance only; they are not tested.

SC

DS22146B-page 3

MCP651/2/4/5/9

TABLE 1-1:

DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +2.5V to +5.5V, V = GND, V

= V /3,

DD

A

DD

SS

CM

V

≈ V /2, V = V /2, R = 1 kΩ to V and CAL/CS = V (refer to Figure 1-2).

OUT

DD

L

DD

L

SS

Parameters

Sym

Min

Typ

Max

Units

Conditions

Calibration Input

Calibration Input Voltage Range

Internal Calibration Voltage

Input Impedance

V

+ 0.1

—

V

– 1.4

mV

V

pin externally driven

pin open

CALRNG

SS

DD

CAL

V

Z

0.31V

—

0.33V

0.35V

—

CAL

DD

100 || 5

kΩ||pF

Power Supply

Supply Voltage

V

2.5

3

—

6

5.5

9

V

DD

Quiescent Current per Amplifier

POR Input Threshold, Low

I

mA

I = 0

O

Q

V

1.15

—

1.40

—

PRL

V

POR Input Threshold, High

V

1.40

1.65

PRH

Note 1: Describes the offset (under the specified conditions) right after power up, or just after the CAL/CS pin is toggled. Thus,

1/f noise effects (an apparent wander in V ; see Figure 2-35) are not included.

OS

2: See Figure 2-6 and Figure 2-7 for temperature effects.

3: The I specifications are for design guidance only; they are not tested.

SC

TABLE 1-2:

AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, T = 25°C, V = +2.5V to +5.5V, V = GND, V

= V /2,

DD

A

DD

SS

CM

V

≈ V /2, V = V /2, R = 1 kΩ to V , C = 20 pF and CAL/CS = V (refer to Figure 1-2).

DD L DD L L L SS

OUT

Parameters

Sym

Min

Typ

Max

Units

Conditions

AC Response

Gain Bandwidth Product

Phase Margin

GBWP

PM

—

50

65

20

—

MHz

°

G = +1

Open-Loop Output Impedance

AC Distortion

R

Ω

OUT

Total Harmonic Distortion plus Noise

THD+N

—

0.0012

—

%

G = +1, V

= 4V , f = 1 kHz,

OUT P-P

V

= 5.5V, BW = 80 kHz

DD

Step Response

Rise Time, 10% to 90%

Slew Rate

t

—

6

—

ns

G = +1, V

G = +1

= 100 mV

OUT P-P

r

SR

30

V/µs

Noise

Input Noise Voltage

Input Noise Voltage Density

Input Noise Current Density

E

e

—

17

7.5

4

—

µV

f = 0.1 Hz to 10 Hz

ni

P-P

nV/√Hz f = 1 MHz

fA/√Hz f = 1 kHz

ni

i

ni

DS22146B-page 4

MCP651/2/4/5/9

TABLE 1-3:

DIGITAL ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, T = 25°C, V = +2.5V to +5.5V, V = GND, V

= V /2,

DD

A

DD

SS

CM

V

≈ V /2, V = V /2, R = 1 kΩ to V , C = 20 pF and CAL/CS = V (refer to Figure 1-1 and Figure 1-2).

OUT

DD L DD L L L SS

Parameters

Sym

Min

Typ

Max Units

Conditions

CAL/CS Low Specifications

CAL/CS Logic Threshold, Low

CAL/CS Input Current, Low

CAL/CS High Specifications

CAL/CS Logic Threshold, High

CAL/CS Input Current, High

GND Current

V

—

0

0.2V

—

V

IL

SS

DD

I

—

nA

CAL/CS = 0V

CSL

V

0.8V

—

V

DD

V

IH

DD

I

0.7

-1.8

-4

—

µA

MΩ

nA

CAL/CS = V

DD

CSH

I

-3.5

-8

—

Single, CAL/CS = V = 2.5V

DD

SS

Single, CAL/CS = V = 5.5V

DD

-5

-2.5

-5

Dual, CAL/CS = V = 2.5V

DD

-10

—

Dual, CAL/CS = V = 5.5V

DD

CAL/CS Internal Pull Down Resistor

R

5

PD

O(LEAK)

Amplifier Output Leakage

I

—

50

CAL/CS = V

DD

POR Dynamic Specifications

V

Low to Amplifier Off Time

t

—

200

—

ns

G = +1 V/V, V = V

,

DD

POFF

L

SS

(output goes High-Z)

V

= 2.5V to 0V step to V

= 0.1 (2.5V)

= 0.9 (2.5V)

DD

OUT

V

High to Amplifier On Time

t

100

300

ms

G = +1 V/V, V = V

,

DD

PON

L

SS

(including calibration)

V

= 0V to 2.5V step to V

DD

CAL/CS Dynamic Specifications

CAL/CS Input Hysteresis

—

1

—

V

0.25

—

V

HYST

CAL/CS Setup Time

t

µs

G = +1 V/V, V = V (Notes 2, 3, 4)

L SS

CSU

(between CAL/CS edges)

CAL/CS = 0.8V to V

= 0.1 (V /2)

DD

OUT

DD

CAL/CS High to Amplifier Off Time

(output goes High-Z)

t

—

200

—

ns

G = +1 V/V, V = V

,

COFF

L

SS

CAL/CS = 0.8V to V

= 0.1 (V /2)

DD

OUT

CAL/CS Low to Amplifier On Time

(including calibration)

G = +1 V/V, V = V , MCP651 and MCP655,

L SS

t

—

3

6

4

8

ms

CON

CAL/CS = 0.2V to V

= 0.9 (V /2)

DD

OUT

DD

G = +1 V/V, V = V , MCP659,

t

L

SS

CON

CAL/CS = 0.2V to V

= 0.9 (V /2)

DD

OUT

Note 1: The MCP652 single, MCP655 dual and MCP659 quad have their CAL/CS inputs internally pulled down to V (0V).

SS

2: This time ensures that the internal logic recognizes the edge. However, for the rising edge case, if CAL/CS is raised

before the calibration is complete, the calibration will be aborted and the part will return to low power mode.

3: For the MCP655 dual, there is an additional constraint. CALA/CSA and CALB/CSB can be toggled simultaneously

(within a time much smaller than t

) to make both op amps perform the same function simultaneously. If they are tog-

CSU

gled independently, then CALA/CSA (CALB/CSB) cannot be allowed to toggle while op amp B (op amp A) is in

calibration mode; allow more than the maximum t time (4 ms) before the other side is toggled.

CON

4: For the MCP659 quad, there is an additional constraint. CALAD/CSAD and CALBC/CSBC can be toggled simultane-

ously (within a time much smaller than t ) to make all four op amps perform the same function simultaneously, and

CSU

the maximum t_CONtime is approximately doubled (8 ms). If they are toggled independently, then CALAD/CSAD

(CALBC/CSBC) cannot be allowed to toggle while op amps B and C (op amps A and D) are in calibration mode; allow

more than the maximum t

time (8 ms) before the other side is toggled.

CON

DS22146B-page 5

MCP651/2/4/5/9

TABLE 1-4:

TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, all limits are specified for: V = +2.5V to +5.5V, V = GND.

DD

SS

Parameters

Sym

Min

Typ

Max Units

Conditions

Temperature Ranges

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

T

-40

-65

—

+125

+150

°C

A

T

(Note 1)

A

T

A

Thermal Package Resistances

Thermal Resistance, 8L-3×3 DFN

Thermal Resistance, 8L-SOIC

θ

—

63

163

71

—

°C/W (Note 2)

°C/W

JA

Thermal Resistance, 10L-3×3 DFN

Thermal Resistance, 10L-MSOP

Thermal Resistance, 14L-SOIC

Thermal Resistance, 14L-TSSOP

Thermal Resistance, 16L-4x4-QFN

°C/W (Note 2)

°C/W

202

95.3

100

46

°C/W

°C/W (Note 2)

Note 1: Operation must not cause T to exceed Maximum Junction Temperature specification (150°C).

J

2: Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.

1.3

Timing Diagram

CAL/CS

V_IL

V_IH

V_DD

V_PRH

V_PRL

t_POFF

t_CSU

t_PON

High-Z

t_COFF

t_CON

High-Z

V_OUT

High-Z

On

-6 mA (typical)

On

-6 mA (typical)

I_SS-3 µA (typical)

I_CS

-3 µA (typical)

0 nA (typical)

0.7 µA (typical)

Note

:

For the MCP655 dual and the MCP659 quad, there is an additional constraint on toggling the two CAL/CS pins close

together; see the T_CONspecification in Table 1-3.

FIGURE 1-1:

Timing Diagram.

DS22146B-page 6

MCP651/2/4/5/9

1.4

Test Circuits

C_F

The circuit used for most DC and AC tests is shown in

Figure 1-2. This circuit can independently set V_CMand

V_OUT; see Equation 1-1. Note that V_CMis not the

circuit’s common mode voltage ((V_P+ V_M)/2), and that

V_OSTincludes V_OSplus the effects (on the input offset

6.8 pF

R_G

10 kΩ

R_F

10 kΩ

V_DD/2

V_DD

V_P

error, V_OST) of temperature, CMRR, PSRR and A_OL

.

V_IN+

EQUATION 1-1:

C_B1

100 nF

C_B2

2.2 µF

G_DM= R_F⁄ R_G

MCP65X

V_CM= (V_P+ V_DD⁄ 2) ⁄ 2

V_OST= V_IN–– V_IN+

V_IN–

V_OUT= (V_DD⁄ 2) + (V_P– V_M) + V_OST(1 + G_DM

Where:

)

V_OUT

V_M

R_L

C_L

R_G

R_F

1 kΩ

20 pF

10 kΩ

G_DM= Differential Mode Gain

(V/V)

(V)

V_CM= Op Amp’s Common Mode

C_F

6.8 pF

Input Voltage

V_L

V_OST= Op Amp’s Total Input Offset (mV)

Voltage

FIGURE 1-2:

AC and DC Test Circuit for

Most Specifications.

DS22146B-page 7

MCP651/2/4/5/9

2.0

TYPICAL PERFORMANCE CURVES

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF, and CAL/CS = V_SS

.

2.1

DC Signal Inputs

35%

30%

25%

20%

15%

10%

5%

700

600

500

400

300

200

100

0

80 Samples

T_A= +25°C

V_DD= 2.5V and 5.5V

Calibrated at +25°C

Representative Part

Calibrated at V_DD= 6.5V

+125°C

+85°C

+25°C

-40°C

0%

-100

-100 -80 -60 -40 -20

0

20 40 60 80 100

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Power Supply Voltage (V)

Input Offset Voltage (µV)

FIGURE 2-1:

Input Offset Voltage.

FIGURE 2-4:

Input Offset Voltage vs.

Power Supply Voltage.

20%

50

80 Samples

V_DD= 2.5V and 5.5V

T_A= -40°C to +125°C

Calibrated at +25°C

Representative Part

18%

16%

14%

12%

10%

8%

40

30

V_DD= 2.5V

20

10

0

-10

-20

-30

-40

-50

V_DD= 5.5V

6%

4%

2%

0%

-10 -8 -6 -4 -2

0

2

4

6

8

10

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

Input Offset Voltage Drift (µV/°C)

FIGURE 2-2:

Input Offset Voltage Drift.

FIGURE 2-5:

Input Offset Voltage vs.

Output Voltage.

55%

0.0

1 Lot

Low (V_{CMR_L}– V_SS

80 Samples

T_A= +25°C

_DD= 2.5V and 5.5V

50%

45%

40%

35%

30%

25%

20%

15%

10%

5%

)

V

-0.1

-0.2

-0.3

-0.4

-0.5

No Change

(includes noise)

V_DD= 2.5V

Calibration

Changed

Calibration

Changed

V_DD= 5.5V

0%

-100 -80 -60 -40 -20

0

20 40 60 80 100

-50

-25

0

25

50

75

100 125

Input Offset Voltage Repeatability (µV)

Ambient Temperature (°C)

FIGURE 2-3:

Input Offset Voltage

FIGURE 2-6:

Low Input Common Mode

Repeatability (repeated calibration).

Voltage Headroom vs. Ambient Temperature.

DS22146B-page 8

MCP651/2/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF, and CAL/CS = V_SS

.

1.4

110

105

100

95

1 Lot

High (V_DD– V_{CMR_H}

)

PSRR

1.3

1.2

1.1

1.0

V_DD= 2.5V

90

85

CMRR, V_DD= 5.5V

CMRR, V_DD= 2.5V

80

75

70

V_DD= 5.5V

65

60

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Ambient Temperature (°C)

FIGURE 2-7:

High Input Common Mode

FIGURE 2-10:

CMRR and PSRR vs.

Voltage Headroom vs. Ambient Temperature.

Ambient Temperature.

1000

130

V_DD= 2.5V

Representative Part

800

V_DD= 5.5V

125

120

115

110

105

100

95

600

400

200

0

V_DD= 2.5V

-200

-40°C

+25°C

+85°C

+125°C

-400

-600

-800

-1000

-50

-25

0

25

50

75

100

125

Input Common Mode Voltage (V)

Ambient Temperature (°C)

FIGURE 2-8:

Input Offset Voltage vs.

FIGURE 2-11:

DC Open-Loop Gain vs.

Common Mode Voltage with V_DD= 2.5V.

Ambient Temperature.

1000

10,000

V_DD= 5.5V

V_CM= V_{CMR_H}

V_DD= 5.5V

800

Representative Part

600

400

200

0

1,000

I_B

100

10

1

-200

-400

-600

-40°C

+25°C

+85°C

+125°C

-I_OS

-800

-1000

25

45

65

85

105

125

Input Common Mode Voltage (V)

Ambient Temperature (°C)

FIGURE 2-9:

Input Offset Voltage vs.

FIGURE 2-12:

Input Bias and Offset

Common Mode Voltage with V_DD= 5.5V.

Currents vs. Ambient Temperature with

_DD= +5.5V.

V

DS22146B-page 9

MCP651/2/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF, and CAL/CS = V_SS

.

160

1.E-10m3

1.E10-004µ

T_A= +85°C

140

V_DD= 5.5V

120

100

80

10µ

1.E-05

I_B

1µ

1.E-06

100n

1.E-07

60

40

20

10n

1.E-08

1n

1.E-09

+125°C

+85°C

+25°C

-40°C

I_OS

0

100p

1.E-10

-20

-40

-60

10p

1.E-11

1p

1.E-12

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Common Mode Input Voltage (V)

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

Input Voltage (V)

FIGURE 2-13:

Input Bias and Offset

FIGURE 2-15:

Input Bias Current vs. Input

Currents vs. Common Mode Input Voltage with

T_A= +85°C.

Voltage (below V_SS).

2000

T_A= +125°C

V_DD= 5.5V

1500

1000

500

I_B

0

I_OS

-500

-1000

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Common Mode Input Voltage (V)

FIGURE 2-14:

Input Bias and Offset

Currents vs. Common Mode Input Voltage with

T_A= +125°C.

DS22146B-page 10

MCP651/2/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF, and CAL/CS = V_SS

.

2.2

Other DC Voltages and Currents

14

8

7

6

5

4

3

2

1

0

V_DD= 5.5V

V_OL– V_SS

-I_OUT

12

10

8

+125°C

+85°C

+25°C

-40°C

6

V_DD– V_OH

I_OUT

4

V_DD= 2.5V

2

0

1

10

100

Output Current Magnitude (mA)

Power Supply Voltage (V)

FIGURE 2-16:

Ratio of Output Voltage

FIGURE 2-19:

Supply Current vs. Power

Headroom to Output Current.

Supply Voltage.

14

9

8

7

6

5

R_L= 1 kΩ

V_DD= 5.5V

V_OL– V_SS

12

10

8

V_DD= 5.5V

V_DD= 2.5V

4

3

2

1

0

6

V_DD– V_OH

4

V_DD= 2.5V

2

0

-50

-25

0

25

50

75

100

125

Ambient Temperature (°C)

Common Mode Input Voltage (V)

FIGURE 2-17:

Output Voltage Headroom

FIGURE 2-20:

Supply Current vs. Common

vs. Ambient Temperature.

Mode Input Voltage.

100

80

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

+125°C

+85°C

+25°C

-40°C

60

V_PRH

40

20

V_PRL

0

-20

-40

-60

-80

-100

-50

-25

0

25

50

75

100

125

Power Supply Voltage (V)

Ambient Temperature (°C)

FIGURE 2-18:

Output Short Circuit Current

FIGURE 2-21:

Power On Reset Voltages

vs. Power Supply Voltage.

vs. Ambient Temperature.

DS22146B-page 11

MCP651/2/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF, and CAL/CS = V_SS

.

30%

140

120

100

80

144 Samples

V_DD= 2.5V and 5.5V

25%

20%

15%

10%

5%

60

40

0%

20

0

Normalized Internal Calibration Voltage;

_CAL/V_DD

-50

-25

0

25

50

75

100

125

V

Ambient Temperature (°C)

FIGURE 2-22:

Normalized Internal

FIGURE 2-23:

V_CALInput Resistance vs.

Calibration Voltage.

Temperature.

DS22146B-page 12

MCP651/2/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF, and CAL/CS = V_SS

.

2.3

Frequency Response

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

70

60

50

40

30

20

10

PM

PSRR+

PSRR-

CMRR

V_DD= 5.5V

V_DD= 2.5V

GBWP

11.E0+02

1.1Ek+3

11.E0+k4

110.E0+k5

11.EM+6

11.0EM+7

Frequency (Hz)

Common Mode Input Voltage (V)

FIGURE 2-24:

CMRR and PSRR vs.

FIGURE 2-27:

Gain Bandwidth Product

Frequency.

and Phase Margin vs. Common Mode Input

Voltage.

120

100

80

0

60

50

40

30

20

10

0

90

80

70

60

50

40

30

-30

V_DD= 5.5V

-60

-90

GBWP

∠

A_OL

60

V_DD= 2.5V

40

-120

-150

-180

-210

| A_OL

|

20

PM

0

-20

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7 1.E+8 1.E+9

10 100 1k 10k 100k 1M 10M 100M 1G

Frequency (Hz)

FIGURE 2-25:

Open-Loop Gain vs.

FIGURE 2-28:

Gain Bandwidth Product

Frequency.

and Phase Margin vs. Output Voltage.

1000

100

90

80

70

60

50

40

30

70

60

50

40

30

20

10

PM

G = 101 V/V

G = 11 V/V

G = 1 V/V

V_DD= 5.5V

V_DD= 2.5V

10

1

GBWP

0.1

-50 -25

0

25

50

75 100 125

1k

10k

100k

Frequency (Hz)

1M

10M

100M

1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08

Ambient Temperature (°C)

FIGURE 2-26:

Gain Bandwidth Product

FIGURE 2-29:

Closed-Loop Output

and Phase Margin vs. Ambient Temperature.

Impedance vs. Frequency.

DS22146B-page 13

MCP651/2/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF, and CAL/CS = V_SS

.

10

9

8

7

6

150

140

130

120

110

100

90

R_S= 0Ω

_S= 1 kΩ

R

RTI

V_CM= V_DD/2

G = +1 V/V

G = 1 V/V

5

G = 2 V/V

4

3

2

1

0

G ꢀ 4 V/V

80

70

R_S= 10 kΩ

_S= 100 kΩ

60

R

50

10p

100p

1n

10n

1.0E-09

1k

10k

1.E+04

100k

1.E+05

1M

1.E+06

10M

1.E+07

1.0E-11

1.0E-10

1.E+03

Frequency (Hz)

Normalized Capacitive Load; C_L/G (F)

FIGURE 2-30:

Gain Peaking vs.

FIGURE 2-31:

Channel-to-Channel

Normalized Capacitive Load.

Separation vs. Frequency.

DS22146B-page 14

MCP651/2/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF, and CAL/CS = V_SS

.

2.4

Input Noise and Distortion

1.E+4

10μ

20

15

10

5

Representative Part

NPBW = 0.1 Hz

1.E+3

1μ

0

1.E+2

100n

-5

-10

-15

-20

1.E+1

10n

1n

^1.E+00.1

1

10

100 1k 10k 100k 1M 10M

0

5

10 15 20 25 30 35 40 45 50

1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7

Time (min)

Frequency (Hz)

FIGURE 2-32:

Input Noise Voltage Density

FIGURE 2-35:

Input Noise plus Offset vs.

vs. Frequency.

Time with 0.1 Hz Filter.

160

1

V_DD= 5.0V

V_DD= 2.5V

140

120

100

80

0.1

V_DD= 5.5V

BW = 22 Hz to > 500 kHz

G = 1 V/V

G = 11 V/V

0.01

60

40

0.001

BW = 22 Hz to 80 kHz

20

f = 100 Hz

0

0.0001

¹1^.E0+0²

^1.1^Ek+3

¹1^.E0+k⁴

1^1.0^E0⁺⁵k

Frequency (Hz)

Common Mode Input Voltage (V)

FIGURE 2-33:

Input Noise Voltage Density

FIGURE 2-36:

THD+N vs. Frequency.

vs. Input Common Mode Voltage with f = 100 Hz.

12

11

10

9

V_DD= 2.5V

8

7

V_DD= 5.5V

6

5

4

3

2

1

f = 1 MHz

0

Common Mode Input Voltage (V)

FIGURE 2-34:

Input Noise Voltage Density

vs. Input Common Mode Voltage with f = 1 MHz.

DS22146B-page 15

MCP651/2/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF, and CAL/CS = V_SS

.

2.5

Time Response

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

V_DD= 5.5V

G = 1

V_DD= 5.5V

G = -1

R

_F= 499Ω

V_IN

V_OUT

0

20 40 60 80 100 120 140 160 180 200

Time (ns)

0

100 200 300 400 500 600 700 800

Time (ns)

FIGURE 2-37:

Non-inverting Small Signal

FIGURE 2-40:

Inverting Large Signal Step

Step Response.

Response.

5.5

5.0

4.5

4.0

3.5

3.0

7

6

V_DD= 5.5V

G = 1

V_DD= 5.5V

G = 2

V_IN

5

V_OUT

4

3

2.5

V_IN

V_OUT

2

2.0

1.5

1.0

0.5

0.0

1

0

-1

0

1

2

3

4

5

6

7

8

9

10

0

100 200 300 400 500 600 700 800

Time (ns)

Time (ms)

FIGURE 2-38:

Non-inverting Large Signal

FIGURE 2-41:

The MCP651/2/4/5/9 family

Step Response.

shows no input phase reversal with overdrive.

60

Falling Edge

55

50

45

40

35

30

25

20

15

10

5

V_DD= 5.5V

V_IN

V_DD= 5.5V

G = -1

_F= 499Ω

R

V_DD= 2.5V

Rising Edge

V_OUT

0

-50

-25

0

25

50

75

100

125

0

50

100 150 200 250 300 350 400

Time (ns)

Ambient Temperature (°C)

FIGURE 2-39:

Inverting Small Signal Step

FIGURE 2-42:

Slew Rate vs. Ambient

Response.

Temperature.

DS22146B-page 16

MCP651/2/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF, and CAL/CS = V_SS

.

10

V_DD= 5.5V

V_DD= 2.5V

1

0.1

100k

1M

1.E+06

10M

1.E+07

100M

1.E+08

1.E+05

Frequency (Hz)

FIGURE 2-43:

Maximum Output Voltage

Swing vs. Frequency.

DS22146B-page 17

MCP651/2/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF, and CAL/CS = V_SS

.

2.6

Calibration and Chip Select Response

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

CAL/CS = V_DD

V_DD= 5.5V

V_DD= 2.5V

-50

-25

0

25

50

75

100

125

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

Ambient Temperature (°C)

FIGURE 2-44:

CAL/CS Current vs. Power

FIGURE 2-47:

CAL/CS Hysteresis vs.

Supply Voltage.

Ambient Temperature.

9

8

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

V_DD= 2.5V

6

G = 1

_L= 0V

V

7

4

I_DD

6

2

5

0

4

-2

Op Amp

turns off

Op Amp

Calibration

starts

CAL/CS

V_OUT

3

2

turns on -4

-6

-8

1

0

-10

-12

-1

-50

-25

0

25

50

75

100

125

0

1

2

3

4

5

6

7

8

9

10

Time (ms)

Ambient Temperature (°C)

FIGURE 2-45:

CAL/CS Voltage, Output

FIGURE 2-48:

CAL/CS Turn On Time vs.

Voltage and Supply Current (for Side A) vs. Time

with V_DD= 2.5V.

Ambient Temperature.

8

11

10

9

8

7

6

5

4

3

2

1

0

-1

10

8

6

4

2

Representative Part

V_DD= 5.5V

G = 1

V_L= 0V

7

6

5

4

3

2

1

0

I_DD

0

Op Amp

turns on

-2

-4

-6

-8

-10

-12

-14

Calibration

starts

Op Amp

turns off

CAL/CS

V_OUT

0

1

2

3

4

5

6

7

8

9

10

-50

-25

0

25

50

75

100

125

Time (ms)

Ambient Temperature (°C)

FIGURE 2-46:

CAL/CS Voltage, Output

FIGURE 2-49:

CAL/CS’s Pull-down

Voltage and Supply Current (for Side A) vs. Time

with V_DD= 5.5V.

Resistor (R_PD) vs. Ambient Temperature.

DS22146B-page 18

MCP651/2/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF, and CAL/CS = V_SS

.

0

1.E-06

1.E-07

1.E-08

1.E-09

1.E-10

1.E-11

CAL/CS = V_DD= 5.5V

CAL/CS = V_DD

-1

-2

-3

+125°C

+85°C

-4

+125°C

+85°C

+25°C

-40°C

-5

-6

+25°C

-7

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Output Voltage (V)

Power Supply Voltage (V)

FIGURE 2-50:

Quiescent Current in

FIGURE 2-51:

Output Leakage Current vs.

Shutdown vs. Power Supply Voltage.

Output Voltage.

DS22146B-page 19

MCP651/2/4/5/9

3.0

PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

PIN FUNCTION TABLE

MCP652 MCP654 MCP655

MCP651

MCP659

QFN

Symbol

Description

SOIC SOIC DFN SOIC TSSOP MSOP DFN

6

2

3

4

1

2

3

4

1

2

3

4

1

2

1

2

1

2

3

4

1

2

3

4

16

1

V_OUT, V_OUTAOutput (op amp A)

V_IN–, V_INA

V_IN+, V_INA

V_SS

–

Inverting Input (op amp A)

Non-inverting Input (op amp A)

Negative Power Supply

3

2

+

11

8

—

5

—

CAL/CS,

CALA/CSA

Calibrate/Chip Select Digital Input

(op amp A)

—

6

—

15

7

CALB/CSB

Calibrate/Chip Select Digital Input

(op amp B)

—

CALAD/CSAD Calibrate/Chip Select Digital Input

(op amps A and D)

CALBC/CSBC Calibrate/Chip Select Digital Input

(op amps B and C)

—

7

5

6

5

6

5

6

7

8

7

8

4

5

V_INB

+

–

Non-inverting Input (op amp B)

Inverting Input (op amp B)

Output (op amp B)

6

V_INB

7

9

6

V_OUTB

—

8

—

8

10

9

10

9

—

10

—

10

—

10

9

V_INC

+

-

Non-inverting input (op amp C)

Inverting Input (op amp C)

Output (op amp C)

V_INC

8

V_OUTC

12

13

14

4

12

13

14

4

12

13

14

3

V_IND

+

-

Non-inverting Input (op amp D)

Inverting Input (op amp D)

Output (op amp D)

V_IND

V_OUTD

V_DD

Positive Power Supply

5

—

V_CAL

Calibration Common Mode Voltage

Input

1

—

9

—

11

—

NC

EP

No Internal Connection

—

17

Exposed Thermal Pad (EP);

must be connected to V_SS

Typically, these parts are used in a single (positive)

supply configuration. In this case, V_SSis connected to

ground and V_DDis connected to the supply. V_DDwill

need bypass capacitors.

3.1

Analog Outputs

The analog output pins (V_OUT) are low-impedance

voltage sources.

3.2

Analog Inputs

3.4

Calibration Common Mode

Voltage Input

The non-inverting and inverting inputs (V_IN+, V_IN–, …)

are high-impedance CMOS inputs with low bias

currents.

A low impedance voltage placed at this input (V_CAL

)

analog input will set the op amps’ common mode input

voltage during calibration. If this pin is left open, the

common mode input voltage during calibration is

approximately V_DD/3. The internal resistor divider is

disconnected from the supplies whenever the part is

not in calibration.

3.3

Power Supply Pins

The positive power supply (V_DD) is 2.5V to 5.5V higher

than the negative power supply (V_SS). For normal

operation, the other pins are between V_SSand V_DD

.

DS22146B-page 20

MCP651/2/4/5/9

3.5

Calibrate/Chip Select Digital Input

3.6

Exposed Thermal Pad (EP)

This input (CAL/CS, …) is a CMOS, Schmitt-triggered

input that affects the calibration and low power modes

of operation. When this pin goes high, the part is placed

into a low power mode and the output is high-Z. When

this pin goes low, a calibration sequence is started

(which corrects V_OS). At the end of the calibration

sequence, the output becomes low impedance and the

part resumes normal operation.

There is an internal connection between the Exposed

Thermal Pad (EP) and the V_SSpin; they must be con-

nected to the same potential on the Printed Circuit

Board (PCB).

This pad can be connected to a PCB ground plane to

provide a larger heat sink. This improves the package

thermal resistance (θ_JA).

An internal POR triggers a calibration event when the

part is powered on, or when the supply voltage drops

too low. Thus, the MCP652 parts are calibrated, even

though they do not have a CAL/CS pin.

DS22146B-page 21

MCP651/2/4/5/9

NOTES:

DS22146B-page 22

MCP651/2/4/5/9

For the MCP655 dual and the MCP659 quad, there is

an additional constraint on toggling the two CAL/CS

pins close together; see the t_CONspecification in

Table 1-3. If the two pins are toggled simultaneously, or

if they are toggled separately with an adequate delay

between them (greater than t_CON), then the CAL/CS

inputs are accepted as valid. If one of the two pins

toggles while the other pin’s claibration routine is in

progress, then an invalid input occurs and the result is

unpredictable.

4.0

APPLICATIONS

The MCP651/2/4/5/9 family of self-zeroed op amps is

manufactured using Microchip’s state of the art CMOS

process. It is designed for low cost, low power and high

precision applications. Its low supply voltage, low

quiescent current and wide bandwidth makes the

MCP651/2/4/5/9 ideal for battery-powered applica-

tions.

4.1

Calibration and Chip Select

4.1.3

INTERNAL POR

These op amps include circuitry for dynamic calibration

of the offset voltage (V_OS).

This part includes an internal Power On Reset (POR)

to protect the internal calibration memory cells. The

POR monitors the power supply voltage (V_DD). When

the POR detects a low V_DDevent, it places the part into

the low power mode of operation. When the POR

detects a normal V_DDevent, it starts a delay counter,

then triggers an calibration event. The additional delay

gives a total POR turn on time of 200 ms (typical); this

is also the power up time (since the POR is triggered at

power up).

4.1.1

mCal CALIBRATION CIRCUITRY

The internal mCal circuitry, when activated, starts a

delay timer (to wait for the op amp to settle to its new

bias point), then calibrates the input offset voltage

(V_OS). The mCal circuitry is triggered at power-up (and

after some power brown out events) by the internal

POR, and by the memory’s Parity Detector. The power

up time, when the mCal circuitry triggers the calibration

sequence, is 200 ms (typical).

4.1.4

PARITY DETECTOR

A parity error detector monitors the memory contents

for any corruption. In the rare event that a parity error is

detected (e.g., corruption from an alpha particle), a

POR event is automatically triggered. This will cause

the input offset voltage to be re-corrected, and the op

amp will not return to normal operation for a period of

time (the POR turn on time, t_PON).

4.1.2

CAL/CS PIN

The CAL/CS pin gives the user a means to externally

demand a low power mode of operation, then to

calibrate V_OS. Using the CAL/CS pin makes it possible

to correct V_OSas it drifts over time (1/f noise and aging;

see Figure 2-35) and across temperature.

The CAL/CS pin performs two functions: it places the

op amp(s) in a low power mode when it is held high,

and starts a calibration event (correction of V_OS) after a

rising edge.

4.1.5

CALIBRATION INPUT PIN

A V_CALpin is available in some options (e.g., the single

MCP651) for those applications that need the calibra-

tion to occur at an internally driven common mode

voltage other than V_DD/3.

While in the low power mode, the quiescent current is

quite small (I_SS= -3 µA, typical). The output is also is in

a High-Z state.

Figure 4-1 shows the reference circuit that internally

sets the op amp’s common mode reference voltage

(V_{CM_INT}) during calibration (the resistors are discon-

nected from the supplies at other times). The 5 kΩ

resistor provides over-current protection for the buffer.

During the calibration event, the quiescent current is

near, but smaller than, the specified quiescent current

(6 mA, typical). The output continues in the High-Z

state, and the inputs are disconnected from the

external circuit, to prevent internal signals from

affecting circuit operation. The op amp inputs are inter-

nally connected to a common mode voltage buffer and

feedback resistors. The offset is corrected (using a

digital state machine, logic and memory), and the

calibration constants are stored in memory.

To op amp during

V_DD

calibration

V_{CM_INT}

300 kΩ

5 kΩ

Once the calibration event is completed, the amplifier is

reconnected to the external circuitry. The turn on time,

when calibration is started with the CAL/CS pin, is 3 ms

(typical).

V_CAL

BUFFER

150 kΩ

There is an internal 5 MΩ pull-down resistor tied to the

CAL/CS pin. If the CAL/CS pin is left floating, the ampli-

fier operates normally.

V_SS

FIGURE 4-1:

Common-Mode Reference’s

Input Circuitry.

DS22146B-page 23

MCP651/2/4/5/9

When the V_CALpin is left open, the internal resistor

divider generates a V_{CM_INT}of approximately V_DD/3,

which is near the center of the input common mode

voltage range. It is recommended that an external

capacitor from V_CALto ground be added to improve

noise immunity.

above V_DD; their breakdown voltage is high enough to

allow normal operation, and low enough to bypass

quick ESD events within the specified limits.

Bond

V_DD

Pad

When the V_CALpin is driven by an external voltage

source, which is within its specified range, the op amp

will have its input offset voltage calibrated at that com-

mon mode input voltage. Make sure that V_CALis within

its specified range.

Bond

Pad

Bond

Pad

Input

Stage

V_IN+

V_IN–

It is possible to use an external resistor voltage divider

to modify V_{CM_INT}; see Figure 4-2. The internal circuitry

at the V_CALpin looks like 100 kΩ tied to V_DD/3. The

parallel equivalent of R₁and R₂should be much

smaller than 100 kΩ to minimize differences in match-

ing and temperature drift between the internal and

external resistors. Again, make sure that V_CALis within

its specified range.

Bond

Pad

V_SS

FIGURE 4-3:

Structures.

Simplified Analog Input ESD

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the currents

(and voltages) at the input pins (see Section 1.1

“Absolute Maximum Ratings †”). Figure 4-4 shows

the recommended approach to protecting these inputs.

The internal ESD diodes prevent the input pins (V_IN+

and V_IN–) from going too far below ground, and the

resistors R₁and R₂limit the possible current drawn out

of the input pins. Diodes D₁and D₂prevent the input

pins (V_IN+ and V_IN–) from going too far above V_DD, and

dump any currents onto V_DD. When implemented as

shown, resistors R₁and R₂also limit the current

through D₁and D₂.

V_DD

MCP65X

R₁

V_CAL

C₁

R₂

V_SS

FIGURE 4-2:

Resistors.

Setting V_CMwith External

V_DD

For instance, a design goal to set V_{CM_INT}= 0.1V when

_DD= 2.5V could be met with: R₁= 24.3 kΩ,

R₂= 1.00 kΩ and C₁= 100 nF. This will keep V_CAL

within its range for any V_DD, and should be close

enough to 0V for ground based applications.

D₁

R₁

D₂

V

MCP65X

V₁

V₂

V_OUT

R₂

4.2

Input

PHASE REVERSAL

V_SS– (minimum expected V₁)

R₁>

R₂>

2 mA

V_SS– (minimum expected V₂)

2 mA

4.2.1

The input devices are designed to not exhibit phase

inversion when the input pins exceed the supply

voltages. Figure 2-41 shows an input voltage

exceeding both supplies with no phase inversion.

FIGURE 4-4:

Protecting the Analog

Inputs.

4.2.2

INPUT VOLTAGE AND CURRENT

LIMITS

It is also possible to connect the diodes to the left of the

resistor R₁and R₂. In this case, the currents through

the diodes D₁and D₂need to be limited by some other

mechanism. The resistors then serve as in-rush current

limiters; the DC current into the input pins (V_IN+ and

V_IN–) should be very small.

The ESD protection on the inputs can be depicted as

shown in Figure 4-3. This structure was chosen to

protect the input transistors, and to minimize input bias

current (I_B). The input ESD diodes clamp the inputs

when they try to go more than one diode drop below

V_SS. They also clamp any voltages that go too far

DS22146B-page 24

MCP651/2/4/5/9

A significant amount of current can flow out of the

inputs (through the ESD diodes) when the common

mode voltage (V_CM) is below ground (V_SS); see

Figure 2-15. Applications that are high impedance may

need to limit the usable voltage range.

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

-0.5

V_OHLimited

(V_DD= 5.5V)

R_L= 1 kΩ

R_L= 100Ω

R_L= 10Ω

4.2.3

NORMAL OPERATION

The input stage of the MCP651/2/4/5/9 op amps uses

a differential PMOS input stage. It operates at low com-

V_OLLimited

mon mode input voltage (V_CM), with V_CMup to V_DD

1.3V and down to V_SS– 0.3V. The input offset voltage

(V_OS) is measured at V_CM= V_SS– 0.3V and V_DD

–

I_OUT(mA)

1.3V to ensure proper operation. See Figure 2-6 and

Figure 2-7 for temperature effects.

FIGURE 4-6:

Output Current.

When operating at very low non-inverting gains, the

output voltage is limited at the top by the V_CMrange

(< V_DD– 1.3V); see Figure 4-5

V_DD

MCP65X

V_IN

V_OUT

V_SS< V_IN, V_OUT≤ V_DD– 1.3V

FIGURE 4-5:

Unity Gain Voltage

Limitations for Linear Operation.

4.3

Rail-to-Rail Output

Maximum Output Voltage

4.3.0.1

The Maximum Output Voltage (see Figure 2-16 and

Figure 2-17) describes the output range for a given

load. For instance, the output voltage swings to within

15 mV of the negative rail with a 1 kΩ load tied to

V_DD/2.

4.3.0.2

Output Current

Figure 4-6 shows the possible combinations of output

voltage (V_OUT) and output current (I_OUT). I_OUTis

positive when it flows out of the op amp into the

external circuit.

DS22146B-page 25

MCP651/2/4/5/9

Figure 4-7 shows a capacitive load (C_L), which is

driven by a sine wave with DC offset. The capacitive

load causes the op amp to output higher currents at

4.3.0.3

Power Dissipation

Since the output short circuit current (I_SC) is specified

at ±100 mA (typical), these op amps are capable of

both delivering and dissipating significant power. Two

common loads, and their impact on the op amp’s power

dissipation, will be discussed.

higher frequencies. Because the output rectifies I_OUT

,

the op amp’s dissipated power increases (even though

the capacitor does not dissipate power).

Figure 4-7 shows a resistive load (R_L) with a DC output

voltage (V_OUT). V_Lis R_L’s ground point, V_SSis usually

ground (0V) and I_OUTis the output current. The input

currents are assumed to be negligible.

V_DD

I_DD

I_OUT

V_OUT

MCP65X

V_DD

C_L

I_SS

I_DD

I_OUT

V_SS

V_OUT

MCP65X

FIGURE 4-8:

Power Calculations.

Diagram for Capacitive Load

R_L

I_SS

The output voltage is assumed to be:

V_SS

V_L

EQUATION 4-4:

FIGURE 4-7:

Power Calculations.

Diagram for Resistive Load

V_OUT= V_DC+ V_ACsin(ωt)

Where:

The DC currents are:

V_DC= DC offset (V)

V_AC= Peak output swing (V_PK

)

EQUATION 4-1:

ω = Radian frequency (2π f) (rad/s)

V_OUT– V_L

I_OUT= -------------------------

R_L

The op amp’s currents are:

EQUATION 4-5:

I_DD≈ I_Q+ max(0, I_OUT

I_SS≈ –I_Q+ min(0, I_OUT

)

Where:

dV_OUT

I_OUT= C_L⋅ ---------------- = V_ACωC_Lcos(ωt)

dt

I_Q= Quiescent supply current for one

op amp (mA/amplifier)

I_DD≈ I_Q+ max(0, I_OUT

I_SS≈ –I_Q+ min(0, I_OUT

)

V_OUT= A DC value (V)

Where:

The DC op amp power is:

I_Q= Quiescent supply current for one

EQUATION 4-2:

op amp (mA/amplifier)

P_OA= I_DD(V_DD– V_OUT) + I_SS(V_SS– V_OUT

)

The op amp’s instantaneous power, average power

and peak power are:

The maximum op amp power, for resistive loads at DC,

occurs when V_OUTis halfway between V_DDand V_Lor

halfway between V_SSand V_L:

EQUATION 4-6:

P_OA= I_DD(V_DD– V_OUT) + I_SS(V_SS– V_OUT

)

EQUATION 4-3:

4V_ACfC_L

⎛

⎞

⎠

ave(P_OA) = (V_DD– V_SS) I_Q+ -----------------------

max(P_OA) = I_DD(V_DD– V_SS

)

⎝

π

max²(V_DD– V_L, V_L– V_SS

)

max(P_OA) = (V_DD– V_SS)(I_Q+ 2V_ACfC_L)

+ -----------------------------------------------------------------

4R_L

The power dissipated in a package depends on the

powers dissipated by each op amp in that package:

DS22146B-page 26

MCP651/2/4/5/9

When driving large capacitive loads with these op

amps (e.g., > 20 pF when G = +1), a small series

resistor at the output (R_ISOin Figure 4-9) improves the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The

bandwidth will be generally lower than the bandwidth

with no capacitive load.

EQUATION 4-7:

n

P_PKG

=

P_OA

∑

k = 1

Where:

n = Number of op amps in package (1 or 2)

The maximum ambient to junction temperature rise

(ΔT_JA) and junction temperature (T_J) can be calculated

using the maximum expected package power (P_PKG),

ambient temperature (T_A) and the package thermal

resistance (θ_JA) found in Table 1-4:

R_ISO

C_L

R_G

R_F

V_OUT

MCP65X

R_N

EQUATION 4-8:

FIGURE 4-9:

Stabilizes Large Capacitive Loads.

Output Resistor, R_ISO

ΔT_JA= P_PKGθ_JA

T_J= T_A+ ΔT_JA

Figure 4-10 gives recommended R_ISOvalues for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (C_L/G_N), where G_Nis the

circuit’s noise gain. For non-inverting gains, G_Nand the

Signal Gain are equal. For inverting gains, G_Nis

1+|Signal Gain| (e.g., -1 V/V gives G_N= +2 V/V).

The worst case power de-rating for the op amps in a

particular package can be easily calculated:

EQUATION 4-9:

T_Jmax– T_A

P_PKG≤ --------------------------

100

θ_JA

Where:

T_Jmax= Absolute maximum junction

temperature (°C)

10

T_A= Ambient temperature (°C)

G_N= +1

≥

G_N+2

Several techniques are available to reduce ΔT_JAfor a

given package:

1

10p

100p

1.E-10

1n

1.E-09

10n

1.E-08

• Reduce θ_JA

- Use another package

1.E-11

Normalized Capacitance; C_L/G_N(F)

- Improve the PCB layout (ground plane, etc.)

- Add heat sinks and air flow

FIGURE 4-10:

for Capacitive Loads.

Recommended R_ISOValues

• Reduce max(P_PKG

- Increase R_L

)

After selecting R_ISOfor your circuit, double check the

resulting frequency response peaking and step

response overshoot. Modify R_ISO’s value until the

response is reasonable. Bench evaluation and

simulations with the MCP651/2/4/5/9 SPICE macro

model are helpful.

- Decrease C_L

- Limit I_OUTusing R_ISO(see Figure 4-9)

- Decrease V_DD

4.4

4.4.1

Improving Stability

4.4.2

GAIN PEAKING

Figure 4-11 shows an op amp circuit that represents

non-inverting amplifiers (V_Mis a DC voltage and V_Pis

the input) or inverting amplifiers (V_Pis a DC voltage

and V_Mis the input). The capacitances C_Nand C_G

represent the total capacitance at the input pins; they

include the op amp’s common mode input capacitance

(C_CM), board parasitic capacitance and any capacitor

placed in parallel.

CAPACITIVE LOADS

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. See Figure 2-30. A unity gain buffer (G = +1)

is the most sensitive to capacitive loads, though all

gains show the same general behavior.

DS22146B-page 27

MCP651/2/4/5/9

EQUATION 4-10:

Given:

C_N

R_N

G_N1= 1 + R_F⁄ R_G

MCP65X

V_P

G_N2= 1 + C_G⁄ C_F

f_F= 1 ⁄ (2πR_FC_F)

V_OUT

V_M

f_Z= f_F(G_N1⁄ G_N2

We need:

)

R_G

R_F

C_G

f_F≤ f_GBWP⁄ (2G_N2), G_N1< G_N2

f_F≤ f_GBWP⁄ (4G_N1), G_N1> G_N2

FIGURE 4-11:

Amplifier with Parasitic

Capacitance.

4.5

Power Supply

C_Gacts in parallel with R_G(except for a gain of +1 V/V),

which causes an increase in gain at high frequencies.

C_Galso reduces the phase margin of the feedback

loop, which becomes less stable. This effect can be

reduced by either reducing C_Gor R_F.

With this family of operational amplifiers, the power

supply pin (V_DDfor single supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

for good high frequency performance. Surface mount,

multilayer ceramic capacitors, or their equivalent,

should be used.

C_Nand R_Nform a low-pass filter that affects the signal

at V_P. This filter has a single real pole at 1/(2πR_NC_N).

The largest value of R_Fthat should be used depends

on noise gain (see G_Nin Section 4.4.1 “Capacitive

Loads”) and C_G. Figure 4-12 shows the maximum

recommended R_Ffor several C_Gvalues.

These op amps require a bulk capacitor (i.e., 2.2 µF or

larger) within 50 mm to provide large, slow currents.

Tantalum capacitors, or their equivalent, may be a good

choice. This bulk capacitor can be shared with other

nearby analog parts as long as crosstalk through the

supplies does not prove to be a problem.

1.E+05

100k

G_N> +1 V/V

C_G= 10 pF

_G= 32 pF

C_G= 100 pF

4.6

High Speed PCB Layout

C

1.E+04

10k

C

_G= 320 pF

C_G= 1 nF

These op amps are fast enough that a little extra care

in the PCB (Printed Circuit Board) layout can make a

significant difference in performance. Good PC board

layout techniques will help you achieve the

performance shown in the specifications and Typical

Performance Curves; it will also help you minimize

EMC (Electro-Magnetic Compatibility) issues.

1.E+013k

1.E+10020

1

10

100

Noise Gain; G_N(V/V)

Use a solid ground plane. Connect the bypass local

capacitor(s) to this plane with minimal length traces.

This cuts down inductive and capacitive crosstalk.

FIGURE 4-12:

Maximum Recommended

R_Fvs. Gain.

Separate digital from analog, low speed from high

speed, and low power from high power. This will reduce

interference.

Figure 2-37 and Figure 2-38 show the small signal and

large signal step responses at G = +1 V/V. The unity

gain buffer usually has R_F= 0Ω and R_Gopen.

Keep sensitive traces short and straight. Separate

them from interfering components and traces. This is

especially important for high frequency (low rise time)

signals.

Figure 2-39 and Figure 2-40 show the small signal and

large signal step responses at G = -1 V/V. Since the

noise gain is 2 V/V and C_G≈ 10 pF, the resistors were

chosen to be R_F= R_G= 499Ω and R_N= 249Ω.

Sometimes, it helps to place guard traces next to victim

traces. They should be on both sides of the victim

trace, and as close as possible. Connect guard traces

to ground plane at both ends, and in the middle for long

traces.

It is also possible to add a capacitor (C_F) in parallel with

R_Fto compensate for the de-stabilizing effect of C_G.

This makes it possible to use larger values of R_F. The

conditions for stability are summarized in

Equation 4-10.

Use coax cables, or low inductance wiring, to route

signal and power to and from the PCB. Mutual and self

inductance of power wires is often a cause of crosstalk

and unusual behavior.

DS22146B-page 28

MCP651/2/4/5/9

4.7.3

H-BRIDGE DRIVER

4.7

Typical Applications

Figure 4-15 shows the MCP652 dual op amp used as

a H-bridge driver. The load could be a speaker or a DC

motor.

4.7.1

POWER DRIVER WITH HIGH GAIN

Figure 4-13 shows a power driver with high gain

(1 + R₂/R₁). The MCP651/2/4/5/9 op amp’s short cir-

cuit current makes it possible to drive significant loads.

The calibrated input offset voltage supports accurate

response at high gains. R₃should be small, and equal

to R₁||R₂, in order to minimize the bias current induced

offset.

½ MCP652

V_IN

V_OT

R_F

R₁

R₃

R₂

R_L

R_GT

R_GB

V_DD/2

V_OUT

R_L

V_OB

V_IN

MCP65X

V_DD/2

½ MCP652

H-Bridge Driver.

FIGURE 4-13:

Power Driver.

FIGURE 4-15:

4.7.2

OPTICAL DETECTOR AMPLIFIER

This circuit automatically makes the noise gains (G_N)

equal, when the gains are set properly, so that the fre-

quency responses match well (in magnitude and in

phase). Equation 4-11 shows how to calculate R_GTand

R_GBso that both op amps have the same DC gains;

G_DMneeds to be selected first.

Figure 4-14 shows a transimpedance amplifier, using

the MCP651 op amp, in a photo detector circuit. The

photo detector is a capacitive current source. The op

amp’s input common mode capacitance (5 pF, typical)

acts in parallel with C_D. R_Fprovides enough gain to

produce 10 mV at V_OUT. C_Fstabilizes the gain and lim-

its the transimpedance bandwidth to about 1.1 MHz.

R_F’s parasitic capacitance (e.g., 0.2 pF for a 0805

SMD) acts in parallel with C_F.

EQUATION 4-11:

V_OT– V_OB

G_DM≡ -------------------------------- ≥ 2 V / V

V

_IN– V_DD⁄ 2

R_F

C_F

1.5 pF

R_GT= --------------------------------

(G_DM⁄ 2) – 1

R_F

Photo

Detector

R_GB= ------------------

R_F

G_DM⁄ 2

100 kΩ

V_OUT

Equation 4-12 gives the resulting common mode and

differential mode output voltages.

I_D

100 nA

C_D

30pF

MCP651

EQUATION 4-12:

V_DD/2

V_OT+ V_OB

-------------------------- = ----------

V_DD

2

FIGURE 4-14:

for an Optical Detector.

Transimpedance Amplifier

V_DD

⎛

⎝

⎞

V_OT– V_OB= G_DM

V

_IN– ----------

⎠

2

DS22146B-page 29

MCP651/2/4/5/9

NOTES:

DS22146B-page 30

MCP651/2/4/5/9

• MCP6XXX Amplifier Evaluation Board 3

5.0

DESIGN AIDS

• MCP6XXX Amplifier Evaluation Board 4

• Active Filter Demo Board Kit

Microchip provides the basic design aids needed for

the MCP651/2/4/5/9 family of op amps.

• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,

P/N SOIC8EV

5.1

SPICE Macro Model

The latest SPICE macro model for the MCP651/2/4/5/9

op amps is available on the Microchip web site at

www.microchip.com. This model is intended to be an

initial design tool that works well in the op amp’s linear

region of operation over the temperature range. See

the model file for information on its capabilities.

5.5

Application Notes

The following Microchip Application Notes are

available on the Microchip web site at www.microchip.

com/appnotes and are recommended as supplemental

reference resources.

• ADN003: “Select the Right Operational Amplifier

for your Filtering Circuits”, DS21821

Bench testing is a very important part of any design and

cannot be replaced with simulations. Also, simulation

results using this macro model need to be validated by

comparing them to the data sheet specifications and

characteristic curves.

• AN722: “Operational Amplifier Topologies and DC

Specifications”, DS00722

• AN723: “Operational Amplifier AC Specifications

and Applications”, DS00723

®

5.2

FilterLab Software

• AN884: “Driving Capacitive Loads With Op

Amps”, DS00884

Microchip’s FilterLab^®software is an innovative

software tool that simplifies analog active filter (using

op amps) design. Available at no cost from the

Microchip web site at www.microchip.com/filterlab, the

Filter-Lab design tool provides full schematic diagrams

of the filter circuit with component values. It also

outputs the filter circuit in SPICE format, which can be

used with the macro model to simulate actual filter

performance.

• AN990: “Analog Sensor Conditioning Circuits –

An Overview”, DS00990

• AN1177: “Op Amp Precision Design: DC Errors”,

DS01177

• AN1228: “Op Amp Precision Design: Random

Noise”, DS01228

• AN1332: “Current Sensing Circuit Concepts and

Fundamentals”, DS01332

Some of these application notes, and others, are listed

in the design guide:

5.3

Microchip Advanced Part Selector

(MAPS)

• “Signal Chain Design Guide”, DS21825

MAPS is a software tool that helps efficiently identify

Microchip devices that fit a particular design require-

ment. Available at no cost from the Microchip website

at www.microchip.com/maps, the MAPS is an overall

selection tool for Microchip’s product portfolio that

includes Analog, Memory, MCUs and DSCs. Using this

tool, a customer can define a filter to sort features for a

parametric search of devices and export side-by-side

technical comparison reports. Helpful links are also

provided for Data sheets, Purchase and Sampling of

Microchip parts.

5.4

Analog Demonstration and

Evaluation Boards

Microchip offers a broad spectrum of Analog Demon-

stration and Evaluation Boards that are designed to

help customers achieve faster time to market. For a

complete listing of these boards and their correspond-

ing user’s guides and technical information, visit the

Microchip web site at www.microchip.com/analog

tools.

Some boards that are especially useful are:

• MCP6XXX Amplifier Evaluation Board 1

• MCP6XXX Amplifier Evaluation Board 2

DS22146B-page 31

MCP651/2/4/5/9

NOTES:

DS22146B-page 32

MCP651/2/4/5/9

6.0

6.1

PACKAGING INFORMATION

Package Marking Information

Example:

8-Lead DFN (3x3) (MCP652)

Device

MCP652

Code

XXXX

DABP

1105

256

DABP

YYWW

NNN

Note: Applies to 8-Lead

3x3 DFN

8-Lead SOIC (150 mil) (MCP651, MCP652)

Example:

MCP651E

XXXXXXXX

e

3

SN 1105

XXXXYYWW

256

NNN

10-Lead DFN (3x3) (MCP655)

Example:

XXXX

YYWW

NNN

BAFC

1105

256

Example:

10-Lead MSOP (MCP655)

655EUN

XXXXXX

YWWNNN

105256

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

e

3

*

)

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS22146B-page 33

MCP651/2/4/5/9

6.2

Package Marking Information

14-Lead SOIC (MCP654)

Example:

MCP654

XXXXXXXXXXX

YYWWNNN

e

3

E/SL

1105256

14-Lead TSSOP (MCP654)

Example:

XXXXXXXX

654E/ST

YYWW

NNN

1105

256

16-Lead QFN (4x4) (MCP659)

Example:

659

XXXXXXX

YWWNNN

e

3

E/ML

1105256

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

e

3

e

3

*

)

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS22146B-page 34

MCP651/2/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22146B-page 35

MCP651/2/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22146B-page 36

MCP651/2/4/5/9

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢈꢄꢊꢐꢆꢑꢒꢆꢂꢃꢄꢅꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢖꢏꢗꢆꢘꢆꢙꢚꢙꢚꢛꢜꢝꢆꢞꢞꢆꢟꢒꢅꢠꢆꢡꢍꢏꢑꢢ

ꢑꢒꢊꢃꢣ ꢀꢁꢂꢃꢄꢅꢆꢃꢇꢁꢈꢄꢃꢉꢊꢂꢂꢆꢋꢄꢃꢌꢍꢉꢎꢍꢏꢆꢃꢐꢂꢍꢑꢒꢋꢏꢈꢓꢃꢌꢔꢆꢍꢈꢆꢃꢈꢆꢆꢃꢄꢅꢆꢃꢕꢒꢉꢂꢁꢉꢅꢒꢌꢃꢖꢍꢉꢎꢍꢏꢒꢋꢏꢃꢗꢌꢆꢉꢒꢘꢒꢉꢍꢄꢒꢁꢋꢃꢔꢁꢉꢍꢄꢆꢐꢃꢍꢄꢃ

ꢅꢄꢄꢌꢙꢚꢚꢑꢑꢑꢛꢇꢒꢉꢂꢁꢉꢅꢒꢌꢛꢉꢁꢇꢚꢌꢍꢉꢎꢍꢏꢒꢋꢏ

DS22146B-page 37

MCP651/2/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22146B-page 38

MCP651/2/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22146B-page 39

MCP651/2/4/5/9

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢤꢞꢄꢈꢈꢆꢥꢎꢊꢈꢋꢦꢃꢆꢕꢤꢑꢗꢆꢘꢆꢑꢄꢧꢧꢒꢨꢐꢆꢙꢜꢝꢛꢆꢞꢞꢆꢟꢒꢅꢠꢆꢡꢤꢥꢩꢪꢢ

ꢑꢒꢊꢃꢣ ꢀꢁꢂꢃꢄꢅꢆꢃꢇꢁꢈꢄꢃꢉꢊꢂꢂꢆꢋꢄꢃꢌꢍꢉꢎꢍꢏꢆꢃꢐꢂꢍꢑꢒꢋꢏꢈꢓꢃꢌꢔꢆꢍꢈꢆꢃꢈꢆꢆꢃꢄꢅꢆꢃꢕꢒꢉꢂꢁꢉꢅꢒꢌꢃꢖꢍꢉꢎꢍꢏꢒꢋꢏꢃꢗꢌꢆꢉꢒꢘꢒꢉꢍꢄꢒꢁꢋꢃꢔꢁꢉꢍꢄꢆꢐꢃꢍꢄꢃ

ꢅꢄꢄꢌꢙꢚꢚꢑꢑꢑꢛꢇꢒꢉꢂꢁꢉꢅꢒꢌꢛꢉꢁꢇꢚꢌꢍꢉꢎꢍꢏꢒꢋꢏ

DS22146B-page 40

MCP651/2/4/5/9

ꢫꢛꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢈꢄꢊꢐꢆꢑꢒꢆꢂꢃꢄꢅꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢖꢏꢗꢆꢘꢆꢙꢚꢙꢚꢛꢜꢝꢆꢞꢞꢆꢟꢒꢅꢠꢆꢡꢍꢏꢑꢢ

ꢑꢒꢊꢃꢣ ꢀꢁꢂꢃꢄꢅꢆꢃꢇꢁꢈꢄꢃꢉꢊꢂꢂꢆꢋꢄꢃꢌꢍꢉꢎꢍꢏꢆꢃꢐꢂꢍꢑꢒꢋꢏꢈꢓꢃꢌꢔꢆꢍꢈꢆꢃꢈꢆꢆꢃꢄꢅꢆꢃꢕꢒꢉꢂꢁꢉꢅꢒꢌꢃꢖꢍꢉꢎꢍꢏꢒꢋꢏꢃꢗꢌꢆꢉꢒꢘꢒꢉꢍꢄꢒꢁꢋꢃꢔꢁꢉꢍꢄꢆꢐꢃꢍꢄꢃ

ꢅꢄꢄꢌꢙꢚꢚꢑꢑꢑꢛꢇꢒꢉꢂꢁꢉꢅꢒꢌꢛꢉꢁꢇꢚꢌꢍꢉꢎꢍꢏꢒꢋꢏ

D

e

b

N

L

K

E

E2

EXPOSED

PAD

NOTE 1

2

1

2

D2

BOTTOM VIEW

TOP VIEW

A

A1

A3

NOTE 2

@ꢋꢒꢄꢈ

ꢕꢣAAꢣꢕ;ꢡ;ꢢꢗ

ꢟꢒꢇꢆꢋꢈꢒꢁꢋꢃAꢒꢇꢒꢄꢈ

ꢕꢣE

EGꢕ

1ꢤ

ꢤꢛ=ꢤꢃ>ꢗ?

ꢤꢛꢦꢤ

ꢕꢠH

Eꢊꢇ7ꢆꢂꢃꢁꢘꢃꢖꢒꢋꢈ

ꢖꢒꢄꢉꢅ

G3ꢆꢂꢍꢔꢔꢃJꢆꢒꢏꢅꢄ

ꢗꢄꢍꢋꢐꢁꢘꢘꢃ

?ꢁꢋꢄꢍꢉꢄꢃꢡꢅꢒꢉꢎꢋꢆꢈꢈ

G3ꢆꢂꢍꢔꢔꢃAꢆꢋꢏꢄꢅ

;6ꢌꢁꢈꢆꢐꢃꢖꢍꢐꢃAꢆꢋꢏꢄꢅ

G3ꢆꢂꢍꢔꢔꢃKꢒꢐꢄꢅ

E

ꢆ

ꢠ

ꢠ1

ꢠ8

ꢟ

ꢟꢝ

;

ꢤꢛꢥꢤ

ꢤꢛꢤꢤ

1ꢛꢤꢤ

ꢤꢛꢤ=

ꢤꢛꢤꢝ

ꢤꢛꢝꢤꢃꢢ;ꢀ

8ꢛꢤꢤꢃ>ꢗ?

ꢝꢛ8=

8ꢛꢤꢤꢃ>ꢗ?

1ꢛ=ꢥ

ꢤꢛꢝ=

ꢤꢛꢞꢤ

ꢩ

ꢝꢛꢝꢤ

ꢝꢛꢞꢥ

;6ꢌꢁꢈꢆꢐꢃꢖꢍꢐꢃKꢒꢐꢄꢅ

?ꢁꢋꢄꢍꢉꢄꢃKꢒꢐꢄꢅ

?ꢁꢋꢄꢍꢉꢄꢃAꢆꢋꢏꢄꢅ

?ꢁꢋꢄꢍꢉꢄꢨꢄꢁꢨ;6ꢌꢁꢈꢆꢐꢃꢖꢍꢐ

;ꢝ

7

A

1ꢛꢞꢤ

ꢤꢛ1ꢥ

ꢤꢛ8ꢤ

ꢤꢛꢝꢤ

1ꢛꢧ=

ꢤꢛ8ꢤ

ꢤꢛ=ꢤ

ꢩ

L

ꢑꢒꢊꢃꢉꢣ

1ꢛ ꢖꢒꢋꢃ1ꢃ3ꢒꢈꢊꢍꢔꢃꢒꢋꢐꢆ6ꢃꢘꢆꢍꢄꢊꢂꢆꢃꢇꢍꢜꢃ3ꢍꢂꢜꢓꢃ7ꢊꢄꢃꢇꢊꢈꢄꢃ7ꢆꢃꢔꢁꢉꢍꢄꢆꢐꢃꢑꢒꢄꢅꢒꢋꢃꢄꢅꢆꢃꢅꢍꢄꢉꢅꢆꢐꢃꢍꢂꢆꢍꢛ

ꢝꢛ ꢖꢍꢉꢎꢍꢏꢆꢃꢇꢍꢜꢃꢅꢍ3ꢆꢃꢁꢋꢆꢃꢁꢂꢃꢇꢁꢂꢆꢃꢆ6ꢌꢁꢈꢆꢐꢃꢄꢒꢆꢃ7ꢍꢂꢈꢃꢍꢄꢃꢆꢋꢐꢈꢛ

8ꢛ ꢖꢍꢉꢎꢍꢏꢆꢃꢒꢈꢃꢈꢍꢑꢃꢈꢒꢋꢏꢊꢔꢍꢄꢆꢐꢛ

ꢞꢛ ꢟꢒꢇꢆꢋꢈꢒꢁꢋꢒꢋꢏꢃꢍꢋꢐꢃꢄꢁꢔꢆꢂꢍꢋꢉꢒꢋꢏꢃꢌꢆꢂꢃꢠꢗꢕ;ꢃ<1ꢞꢛ=ꢕꢛ

>ꢗ?ꢙ >ꢍꢈꢒꢉꢃꢟꢒꢇꢆꢋꢈꢒꢁꢋꢛꢃꢡꢅꢆꢁꢂꢆꢄꢒꢉꢍꢔꢔꢜꢃꢆ6ꢍꢉꢄꢃ3ꢍꢔꢊꢆꢃꢈꢅꢁꢑꢋꢃꢑꢒꢄꢅꢁꢊꢄꢃꢄꢁꢔꢆꢂꢍꢋꢉꢆꢈꢛ

ꢢ;ꢀꢙ ꢢꢆꢘꢆꢂꢆꢋꢉꢆꢃꢟꢒꢇꢆꢋꢈꢒꢁꢋꢓꢃꢊꢈꢊꢍꢔꢔꢜꢃꢑꢒꢄꢅꢁꢊꢄꢃꢄꢁꢔꢆꢂꢍꢋꢉꢆꢓꢃꢘꢁꢂꢃꢒꢋꢘꢁꢂꢇꢍꢄꢒꢁꢋꢃꢌꢊꢂꢌꢁꢈꢆꢈꢃꢁꢋꢔꢜꢛ

ꢕꢒꢉꢂꢁꢉꢅꢒꢌ ꢡꢆꢉꢅꢋꢁꢔꢁꢏꢜ ꢟꢂꢍꢑꢒꢋꢏ ?ꢤꢞꢨꢤO8>

DS22146B-page 41

MCP651/2/4/5/9

ꢫꢛꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢈꢄꢊꢐꢆꢑꢒꢆꢂꢃꢄꢅꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢖꢏꢗꢆꢘꢆꢙꢚꢙꢚꢛꢜꢝꢆꢞꢞꢆꢟꢒꢅꢠꢆꢡꢍꢏꢑꢢ

ꢑꢒꢊꢃꢣ ꢀꢁꢂꢃꢄꢅꢆꢃꢇꢁꢈꢄꢃꢉꢊꢂꢂꢆꢋꢄꢃꢌꢍꢉꢎꢍꢏꢆꢃꢐꢂꢍꢑꢒꢋꢏꢈꢓꢃꢌꢔꢆꢍꢈꢆꢃꢈꢆꢆꢃꢄꢅꢆꢃꢕꢒꢉꢂꢁꢉꢅꢒꢌꢃꢖꢍꢉꢎꢍꢏꢒꢋꢏꢃꢗꢌꢆꢉꢒꢘꢒꢉꢍꢄꢒꢁꢋꢃꢔꢁꢉꢍꢄꢆꢐꢃꢍꢄꢃ

ꢅꢄꢄꢌꢙꢚꢚꢑꢑꢑꢛꢇꢒꢉꢂꢁꢉꢅꢒꢌꢛꢉꢁꢇꢚꢌꢍꢉꢎꢍꢏꢒꢋꢏ

DS22146B-page 42

MCP651/2/4/5/9

ꢫꢛꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢖꢋꢌꢧꢒꢆꢤꢞꢄꢈꢈꢆꢥꢎꢊꢈꢋꢦꢃꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢬꢑꢗꢆꢡꢖꢤꢥꢇꢢ

ꢑꢒꢊꢃꢣ ꢀꢁꢂꢃꢄꢅꢆꢃꢇꢁꢈꢄꢃꢉꢊꢂꢂꢆꢋꢄꢃꢌꢍꢉꢎꢍꢏꢆꢃꢐꢂꢍꢑꢒꢋꢏꢈꢓꢃꢌꢔꢆꢍꢈꢆꢃꢈꢆꢆꢃꢄꢅꢆꢃꢕꢒꢉꢂꢁꢉꢅꢒꢌꢃꢖꢍꢉꢎꢍꢏꢒꢋꢏꢃꢗꢌꢆꢉꢒꢘꢒꢉꢍꢄꢒꢁꢋꢃꢔꢁꢉꢍꢄꢆꢐꢃꢍꢄꢃ

ꢅꢄꢄꢌꢙꢚꢚꢑꢑꢑꢛꢇꢒꢉꢂꢁꢉꢅꢒꢌꢛꢉꢁꢇꢚꢌꢍꢉꢎꢍꢏꢒꢋꢏ

D

N

E

E1

NOTE 1

1

2

b

e

c

A

A2

φ

L

A1

L1

@ꢋꢒꢄꢈ

ꢕꢣAAꢣꢕ;ꢡ;ꢢꢗ

ꢟꢒꢇꢆꢋꢈꢒꢁꢋꢃAꢒꢇꢒꢄꢈ

ꢕꢣE

EGꢕ

ꢕꢠH

Eꢊꢇ7ꢆꢂꢃꢁꢘꢃꢖꢒꢋꢈ

ꢖꢒꢄꢉꢅ

E

ꢆ

1ꢤ

ꢤꢛ=ꢤꢃ>ꢗ?

G3ꢆꢂꢍꢔꢔꢃJꢆꢒꢏꢅꢄ

ꢕꢁꢔꢐꢆꢐꢃꢖꢍꢉꢎꢍꢏꢆꢃꢡꢅꢒꢉꢎꢋꢆꢈꢈ

ꢗꢄꢍꢋꢐꢁꢘꢘꢃ

G3ꢆꢂꢍꢔꢔꢃKꢒꢐꢄꢅ

ꢕꢁꢔꢐꢆꢐꢃꢖꢍꢉꢎꢍꢏꢆꢃKꢒꢐꢄꢅ

G3ꢆꢂꢍꢔꢔꢃAꢆꢋꢏꢄꢅ

ꢀꢁꢁꢄꢃAꢆꢋꢏꢄꢅ

ꢠ

ꢩ

ꢤꢛꢧ=

ꢤꢛꢤꢤ

ꢩ

ꢤꢛꢥ=

1ꢛ1ꢤ

ꢤꢛꢦ=

ꢤꢛ1=

ꢠꢝ

ꢠ1

;

;1

ꢟ

ꢩ

ꢞꢛꢦꢤꢃ>ꢗ?

8ꢛꢤꢤꢃ>ꢗ?

ꢤꢛOꢤ

A

ꢤꢛꢞꢤ

ꢤꢛꢥꢤ

ꢀꢁꢁꢄꢌꢂꢒꢋꢄ

ꢀꢁꢁꢄꢃꢠꢋꢏꢔꢆ

A1

ꢀ

ꢤꢛꢦ=ꢃꢢ;ꢀ

ꢩ

ꢤꢪ

ꢥꢪ

Aꢆꢍꢐꢃꢡꢅꢒꢉꢎꢋꢆꢈꢈ

AꢆꢍꢐꢃKꢒꢐꢄꢅ

ꢉ

7

ꢤꢛꢤꢥ

ꢤꢛ1=

ꢩ

ꢤꢛꢝ8

ꢤꢛ88

ꢑꢒꢊꢃꢉꢣ

1ꢛ ꢖꢒꢋꢃ1ꢃ3ꢒꢈꢊꢍꢔꢃꢒꢋꢐꢆ6ꢃꢘꢆꢍꢄꢊꢂꢆꢃꢇꢍꢜꢃ3ꢍꢂꢜꢓꢃ7ꢊꢄꢃꢇꢊꢈꢄꢃ7ꢆꢃꢔꢁꢉꢍꢄꢆꢐꢃꢑꢒꢄꢅꢒꢋꢃꢄꢅꢆꢃꢅꢍꢄꢉꢅꢆꢐꢃꢍꢂꢆꢍꢛ

ꢝꢛ ꢟꢒꢇꢆꢋꢈꢒꢁꢋꢈꢃꢟꢃꢍꢋꢐꢃ;1ꢃꢐꢁꢃꢋꢁꢄꢃꢒꢋꢉꢔꢊꢐꢆꢃꢇꢁꢔꢐꢃꢘꢔꢍꢈꢅꢃꢁꢂꢃꢌꢂꢁꢄꢂꢊꢈꢒꢁꢋꢈꢛꢃꢕꢁꢔꢐꢃꢘꢔꢍꢈꢅꢃꢁꢂꢃꢌꢂꢁꢄꢂꢊꢈꢒꢁꢋꢈꢃꢈꢅꢍꢔꢔꢃꢋꢁꢄꢃꢆ6ꢉꢆꢆꢐꢃꢤꢛ1=ꢃꢇꢇꢃꢌꢆꢂꢃꢈꢒꢐꢆꢛ

8ꢛ ꢟꢒꢇꢆꢋꢈꢒꢁꢋꢒꢋꢏꢃꢍꢋꢐꢃꢄꢁꢔꢆꢂꢍꢋꢉꢒꢋꢏꢃꢌꢆꢂꢃꢠꢗꢕ;ꢃ<1ꢞꢛ=ꢕꢛ

>ꢗ?ꢙ >ꢍꢈꢒꢉꢃꢟꢒꢇꢆꢋꢈꢒꢁꢋꢛꢃꢡꢅꢆꢁꢂꢆꢄꢒꢉꢍꢔꢔꢜꢃꢆ6ꢍꢉꢄꢃ3ꢍꢔꢊꢆꢃꢈꢅꢁꢑꢋꢃꢑꢒꢄꢅꢁꢊꢄꢃꢄꢁꢔꢆꢂꢍꢋꢉꢆꢈꢛ

ꢢ;ꢀꢙ ꢢꢆꢘꢆꢂꢆꢋꢉꢆꢃꢟꢒꢇꢆꢋꢈꢒꢁꢋꢓꢃꢊꢈꢊꢍꢔꢔꢜꢃꢑꢒꢄꢅꢁꢊꢄꢃꢄꢁꢔꢆꢂꢍꢋꢉꢆꢓꢃꢘꢁꢂꢃꢒꢋꢘꢁꢂꢇꢍꢄꢒꢁꢋꢃꢌꢊꢂꢌꢁꢈꢆꢈꢃꢁꢋꢔꢜꢛ

ꢕꢒꢉꢂꢁꢉꢅꢒꢌ ꢡꢆꢉꢅꢋꢁꢔꢁꢏꢜ ꢟꢂꢍꢑꢒꢋꢏ ?ꢤꢞꢨꢤꢝ1>

DS22146B-page 43

MCP651/2/4/5/9

ꢫꢭꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢤꢞꢄꢈꢈꢆꢥꢎꢊꢈꢋꢦꢃꢆꢕꢤꢂꢗꢆꢘꢆꢑꢄꢧꢧꢒꢨꢐꢆꢙꢜꢝꢛꢆꢞꢞꢆꢟꢒꢅꢠꢆꢡꢤꢥꢩꢪꢢ

ꢑꢒꢊꢃꢣ ꢀꢁꢂꢃꢄꢅꢆꢃꢇꢁꢈꢄꢃꢉꢊꢂꢂꢆꢋꢄꢃꢌꢍꢉꢎꢍꢏꢆꢃꢐꢂꢍꢑꢒꢋꢏꢈꢓꢃꢌꢔꢆꢍꢈꢆꢃꢈꢆꢆꢃꢄꢅꢆꢃꢕꢒꢉꢂꢁꢉꢅꢒꢌꢃꢖꢍꢉꢎꢍꢏꢒꢋꢏꢃꢗꢌꢆꢉꢒꢘꢒꢉꢍꢄꢒꢁꢋꢃꢔꢁꢉꢍꢄꢆꢐꢃꢍꢄꢃ

ꢅꢄꢄꢌꢙꢚꢚꢑꢑꢑꢛꢇꢒꢉꢂꢁꢉꢅꢒꢌꢛꢉꢁꢇꢚꢌꢍꢉꢎꢍꢏꢒꢋꢏ

D

N

E

E1

NOTE 1

1

2

3

e

h

b

α

h

c

φ

A2

A

L

A1

β

L1

@ꢋꢒꢄꢈ

ꢕꢣAAꢣꢕ;ꢡ;ꢢꢗ

ꢟꢒꢇꢆꢋꢈꢒꢁꢋꢃAꢒꢇꢒꢄꢈ

ꢕꢣE

EGꢕ

ꢕꢠH

Eꢊꢇ7ꢆꢂꢃꢁꢘꢃꢖꢒꢋꢈ

ꢖꢒꢄꢉꢅ

E

ꢆ

1ꢞ

1ꢛꢝꢧꢃ>ꢗ?

G3ꢆꢂꢍꢔꢔꢃJꢆꢒꢏꢅꢄ

ꢕꢁꢔꢐꢆꢐꢃꢖꢍꢉꢎꢍꢏꢆꢃꢡꢅꢒꢉꢎꢋꢆꢈꢈ

ꢗꢄꢍꢋꢐꢁꢘꢘꢃꢃ"

ꢠ

ꢩ

1ꢛꢝ=

ꢤꢛ1ꢤ

ꢩ

1ꢛꢧ=

ꢩ

ꢤꢛꢝ=

ꢠꢝ

ꢠ1

;

G3ꢆꢂꢍꢔꢔꢃKꢒꢐꢄꢅ

Oꢛꢤꢤꢃ>ꢗ?

ꢕꢁꢔꢐꢆꢐꢃꢖꢍꢉꢎꢍꢏꢆꢃKꢒꢐꢄꢅ

G3ꢆꢂꢍꢔꢔꢃAꢆꢋꢏꢄꢅ

?ꢅꢍꢇꢘꢆꢂꢃUꢁꢌꢄꢒꢁꢋꢍꢔV

ꢀꢁꢁꢄꢃAꢆꢋꢏꢄꢅ

;1

ꢟ

ꢅ

8ꢛꢦꢤꢃ>ꢗ?

ꢥꢛO=ꢃ>ꢗ?

ꢤꢛꢝ=

ꢤꢛꢞꢤ

ꢩ

ꢤꢛ=ꢤ

1ꢛꢝꢧ

A

ꢀꢁꢁꢄꢌꢂꢒꢋꢄ

ꢀꢁꢁꢄꢃꢠꢋꢏꢔꢆ

Aꢆꢍꢐꢃꢡꢅꢒꢉꢎꢋꢆꢈꢈ

AꢆꢍꢐꢃKꢒꢐꢄꢅ

ꢕꢁꢔꢐꢃꢟꢂꢍꢘꢄꢃꢠꢋꢏꢔꢆꢃꢡꢁꢌ

ꢕꢁꢔꢐꢃꢟꢂꢍꢘꢄꢃꢠꢋꢏꢔꢆꢃ>ꢁꢄꢄꢁꢇ

A1

ꢀ

1ꢛꢤꢞꢃꢢ;ꢀ

ꢤꢪ

ꢤꢛ1ꢧ

ꢤꢛ81

=ꢪ

ꢩ

ꢥꢪ

ꢉ

7

ꢁ

ꢤꢛꢝ=

ꢤꢛ=1

1=ꢪ

ꢂ

=ꢪ

1=ꢪ

ꢑꢒꢊꢃꢉꢣ

1ꢛ ꢖꢒꢋꢃ1ꢃ3ꢒꢈꢊꢍꢔꢃꢒꢋꢐꢆ6ꢃꢘꢆꢍꢄꢊꢂꢆꢃꢇꢍꢜꢃ3ꢍꢂꢜꢓꢃ7ꢊꢄꢃꢇꢊꢈꢄꢃ7ꢆꢃꢔꢁꢉꢍꢄꢆꢐꢃꢑꢒꢄꢅꢒꢋꢃꢄꢅꢆꢃꢅꢍꢄꢉꢅꢆꢐꢃꢍꢂꢆꢍꢛ

ꢝꢛ "ꢃꢗꢒꢏꢋꢒꢘꢒꢉꢍꢋꢄꢃ?ꢅꢍꢂꢍꢉꢄꢆꢂꢒꢈꢄꢒꢉꢛ

8ꢛ ꢟꢒꢇꢆꢋꢈꢒꢁꢋꢈꢃꢟꢃꢍꢋꢐꢃ;1ꢃꢐꢁꢃꢋꢁꢄꢃꢒꢋꢉꢔꢊꢐꢆꢃꢇꢁꢔꢐꢃꢘꢔꢍꢈꢅꢃꢁꢂꢃꢌꢂꢁꢄꢂꢊꢈꢒꢁꢋꢈꢛꢃꢕꢁꢔꢐꢃꢘꢔꢍꢈꢅꢃꢁꢂꢃꢌꢂꢁꢄꢂꢊꢈꢒꢁꢋꢈꢃꢈꢅꢍꢔꢔꢃꢋꢁꢄꢃꢆ6ꢉꢆꢆꢐꢃꢤꢛ1=ꢃꢇꢇꢃꢌꢆꢂꢃꢈꢒꢐꢆꢛ

ꢞꢛ ꢟꢒꢇꢆꢋꢈꢒꢁꢋꢒꢋꢏꢃꢍꢋꢐꢃꢄꢁꢔꢆꢂꢍꢋꢉꢒꢋꢏꢃꢌꢆꢂꢃꢠꢗꢕ;ꢃ<1ꢞꢛ=ꢕꢛ

>ꢗ?ꢙ >ꢍꢈꢒꢉꢃꢟꢒꢇꢆꢋꢈꢒꢁꢋꢛꢃꢡꢅꢆꢁꢂꢆꢄꢒꢉꢍꢔꢔꢜꢃꢆ6ꢍꢉꢄꢃ3ꢍꢔꢊꢆꢃꢈꢅꢁꢑꢋꢃꢑꢒꢄꢅꢁꢊꢄꢃꢄꢁꢔꢆꢂꢍꢋꢉꢆꢈꢛ

ꢢ;ꢀꢙ ꢢꢆꢘꢆꢂꢆꢋꢉꢆꢃꢟꢒꢇꢆꢋꢈꢒꢁꢋꢓꢃꢊꢈꢊꢍꢔꢔꢜꢃꢑꢒꢄꢅꢁꢊꢄꢃꢄꢁꢔꢆꢂꢍꢋꢉꢆꢓꢃꢘꢁꢂꢃꢒꢋꢘꢁꢂꢇꢍꢄꢒꢁꢋꢃꢌꢊꢂꢌꢁꢈꢆꢈꢃꢁꢋꢔꢜꢛ

ꢕꢒꢉꢂꢁꢉꢅꢒꢌ ꢡꢆꢉꢅꢋꢁꢔꢁꢏꢜ ꢟꢂꢍꢑꢒꢋꢏ ?ꢤꢞꢨꢤO=>

DS22146B-page 44

MCP651/2/4/5/9

14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]

ꢑꢒꢊꢃꢣ ꢀꢁꢂꢃꢄꢅꢆꢃꢇꢁꢈꢄꢃꢉꢊꢂꢂꢆꢋꢄꢃꢌꢍꢉꢎꢍꢏꢆꢃꢐꢂꢍꢑꢒꢋꢏꢈꢓꢃꢌꢔꢆꢍꢈꢆꢃꢈꢆꢆꢃꢄꢅꢆꢃꢕꢒꢉꢂꢁꢉꢅꢒꢌꢃꢖꢍꢉꢎꢍꢏꢒꢋꢏꢃꢗꢌꢆꢉꢒꢘꢒꢉꢍꢄꢒꢁꢋꢃꢔꢁꢉꢍꢄꢆꢐꢃꢍꢄꢃ

ꢅꢄꢄꢌꢙꢚꢚꢑꢑꢑꢛꢇꢒꢉꢂꢁꢉꢅꢒꢌꢛꢉꢁꢇꢚꢌꢍꢉꢎꢍꢏꢒꢋꢏ

DS22146B-page 45

MCP651/2/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22146B-page 46

MCP651/2/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22146B-page 47

MCP651/2/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22146B-page 48

MCP651/2/4/5/9

ꢫꢮꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢯꢎꢄꢅꢆꢏꢈꢄꢊꢐꢆꢑꢒꢆꢂꢃꢄꢅꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢖꢂꢗꢆꢘꢆꢭꢚꢭꢚꢛꢜꢝꢆꢞꢞꢆꢟꢒꢅꢠꢆꢡꢯꢏꢑꢢ

ꢑꢒꢊꢃꢣ ꢀꢁꢂꢃꢄꢅꢆꢃꢇꢁꢈꢄꢃꢉꢊꢂꢂꢆꢋꢄꢃꢌꢍꢉꢎꢍꢏꢆꢃꢐꢂꢍꢑꢒꢋꢏꢈꢓꢃꢌꢔꢆꢍꢈꢆꢃꢈꢆꢆꢃꢄꢅꢆꢃꢕꢒꢉꢂꢁꢉꢅꢒꢌꢃꢖꢍꢉꢎꢍꢏꢒꢋꢏꢃꢗꢌꢆꢉꢒꢘꢒꢉꢍꢄꢒꢁꢋꢃꢔꢁꢉꢍꢄꢆꢐꢃꢍꢄꢃ

ꢅꢄꢄꢌꢙꢚꢚꢑꢑꢑꢛꢇꢒꢉꢂꢁꢉꢅꢒꢌꢛꢉꢁꢇꢚꢌꢍꢉꢎꢍꢏꢒꢋꢏ

D

D2

EXPOSED

PAD

e

E

E2

2

1

2

b

1

K

N

NOTE 1

L

TOP VIEW

BOTTOM VIEW

A3

A

A1

@ꢋꢒꢄꢈ

ꢕꢣAAꢣꢕ;ꢡ;ꢢꢗ

ꢟꢒꢇꢆꢋꢈꢒꢁꢋꢃAꢒꢇꢒꢄꢈ

ꢕꢣE

EGꢕ

1O

ꢤꢛO=ꢃ>ꢗ?

ꢤꢛꢦꢤ

ꢕꢠH

Eꢊꢇ7ꢆꢂꢃꢁꢘꢃꢖꢒꢋꢈ

ꢖꢒꢄꢉꢅ

G3ꢆꢂꢍꢔꢔꢃJꢆꢒꢏꢅꢄ

ꢗꢄꢍꢋꢐꢁꢘꢘꢃ

?ꢁꢋꢄꢍꢉꢄꢃꢡꢅꢒꢉꢎꢋꢆꢈꢈ

G3ꢆꢂꢍꢔꢔꢃKꢒꢐꢄꢅ

;6ꢌꢁꢈꢆꢐꢃꢖꢍꢐꢃKꢒꢐꢄꢅ

G3ꢆꢂꢍꢔꢔꢃAꢆꢋꢏꢄꢅ

;6ꢌꢁꢈꢆꢐꢃꢖꢍꢐꢃAꢆꢋꢏꢄꢅ

?ꢁꢋꢄꢍꢉꢄꢃKꢒꢐꢄꢅ

?ꢁꢋꢄꢍꢉꢄꢃAꢆꢋꢏꢄꢅ

E

ꢆ

ꢠ

ꢠ1

ꢠ8

;

;ꢝ

ꢟ

ꢤꢛꢥꢤ

ꢤꢛꢤꢤ

1ꢛꢤꢤ

ꢤꢛꢤ=

ꢤꢛꢤꢝ

ꢤꢛꢝꢤꢃꢢ;ꢀ

ꢞꢛꢤꢤꢃ>ꢗ?

ꢝꢛO=

ꢞꢛꢤꢤꢃ>ꢗ?

ꢝꢛO=

ꢤꢛ8ꢤ

ꢤꢛꢞꢤ

ꢩ

ꢝꢛ=ꢤ

ꢝꢛꢥꢤ

ꢟꢝ

7

A

ꢝꢛ=ꢤ

ꢤꢛꢝ=

ꢤꢛ8ꢤ

ꢤꢛꢝꢤ

ꢝꢛꢥꢤ

ꢤꢛ8=

ꢤꢛ=ꢤ

ꢩ

?ꢁꢋꢄꢍꢉꢄꢨꢄꢁꢨ;6ꢌꢁꢈꢆꢐꢃꢖꢍꢐ

L

ꢑꢒꢊꢃꢉꢣ

1ꢛ ꢖꢒꢋꢃ1ꢃ3ꢒꢈꢊꢍꢔꢃꢒꢋꢐꢆ6ꢃꢘꢆꢍꢄꢊꢂꢆꢃꢇꢍꢜꢃ3ꢍꢂꢜꢓꢃ7ꢊꢄꢃꢇꢊꢈꢄꢃ7ꢆꢃꢔꢁꢉꢍꢄꢆꢐꢃꢑꢒꢄꢅꢒꢋꢃꢄꢅꢆꢃꢅꢍꢄꢉꢅꢆꢐꢃꢍꢂꢆꢍꢛ

ꢝꢛ ꢖꢍꢉꢎꢍꢏꢆꢃꢒꢈꢃꢈꢍꢑꢃꢈꢒꢋꢏꢊꢔꢍꢄꢆꢐꢛ

8ꢛ ꢟꢒꢇꢆꢋꢈꢒꢁꢋꢒꢋꢏꢃꢍꢋꢐꢃꢄꢁꢔꢆꢂꢍꢋꢉꢒꢋꢏꢃꢌꢆꢂꢃꢠꢗꢕ;ꢃ<1ꢞꢛ=ꢕꢛ

>ꢗ?ꢙ >ꢍꢈꢒꢉꢃꢟꢒꢇꢆꢋꢈꢒꢁꢋꢛꢃꢡꢅꢆꢁꢂꢆꢄꢒꢉꢍꢔꢔꢜꢃꢆ6ꢍꢉꢄꢃ3ꢍꢔꢊꢆꢃꢈꢅꢁꢑꢋꢃꢑꢒꢄꢅꢁꢊꢄꢃꢄꢁꢔꢆꢂꢍꢋꢉꢆꢈꢛ

ꢢ;ꢀꢙ ꢢꢆꢘꢆꢂꢆꢋꢉꢆꢃꢟꢒꢇꢆꢋꢈꢒꢁꢋꢓꢃꢊꢈꢊꢍꢔꢔꢜꢃꢑꢒꢄꢅꢁꢊꢄꢃꢄꢁꢔꢆꢂꢍꢋꢉꢆꢓꢃꢘꢁꢂꢃꢒꢋꢘꢁꢂꢇꢍꢄꢒꢁꢋꢃꢌꢊꢂꢌꢁꢈꢆꢈꢃꢁꢋꢔꢜꢛ

ꢕꢒꢉꢂꢁꢉꢅꢒꢌ ꢡꢆꢉꢅꢋꢁꢔꢁꢏꢜ ꢟꢂꢍꢑꢒꢋꢏ ?ꢤꢞꢨ1ꢝꢧ>

DS22146B-page 49

MCP651/2/4/5/9

20-Lead Plastic Quad Flat, No Lead Package (ML) - 4x4 mm Body [QFN]

With 0.40 mm Contact Length

ꢑꢒꢊꢃꢣ ꢀꢁꢂꢃꢄꢅꢆꢃꢇꢁꢈꢄꢃꢉꢊꢂꢂꢆꢋꢄꢃꢌꢍꢉꢎꢍꢏꢆꢃꢐꢂꢍꢑꢒꢋꢏꢈꢓꢃꢌꢔꢆꢍꢈꢆꢃꢈꢆꢆꢃꢄꢅꢆꢃꢕꢒꢉꢂꢁꢉꢅꢒꢌꢃꢖꢍꢉꢎꢍꢏꢒꢋꢏꢃꢗꢌꢆꢉꢒꢘꢒꢉꢍꢄꢒꢁꢋꢃꢔꢁꢉꢍꢄꢆꢐꢃꢍꢄꢃ

ꢅꢄꢄꢌꢙꢚꢚꢑꢑꢑꢛꢇꢒꢉꢂꢁꢉꢅꢒꢌꢛꢉꢁꢇꢚꢌꢍꢉꢎꢍꢏꢒꢋꢏ

DS22146B-page 50

MCP651/2/4/5/9

APPENDIX A: REVISION HISTORY

Revision B (March 2011)

The following is a list of modifications:

1. Added the MCP654 and MCP659 amplifiers to

the product family and the related information

throughout the document.

2. Added the corresponding SOIC (14L), TSSOP

(14L) and QFN (16L) package options and

related information.

Revision A (April 2009)

• Original Release of this Document.

DS22146B-page 51

MCP651/2/4/5/9

NOTES:

DS22146B-page 52

MCP651/2/4/5/9

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

X

/XX

a) MCP651T-E/SN:

b) MCP652T-E/MF:

c) MCP652T-E/SN:

d) MCP654T-E/SL:

e) MCP654T-E/ST:

f) MCP655T-E/MF:

g) MCP655T-E/UN:

h) MCP659T-E/ML:

Tape and Reel,

Extended Temperature,

8LD SOIC package.

Tape and Reel,

Extended Temperature,

8LD DFN package.

Tape and Reel,

Extended Temperature,

8LD SOIC package.

Tape and Reel,

Extended Temperature,

14LD SOIC package.

Tape and Reel,

Extended Temperature,

14LD TSSOP package.

Tape and Reel,

Extended Temperature,

10LD DFN package.

Tape and Reel,

Extended Temperature,

10LD MSOP package.

Temperature

Range

Package

Device:

MCP651:

MCP651T:

Single Op Amp

Single Op Amp (Tape and Reel)

(DFN and SOIC)

Dual Op Amp

Dual Op Amp (Tape and Reel)

(DFN and SOIC)

MCP652:

MCP652T:

MCP654:

MCP654T:

Dual Op Amp

Dual Op Amp (Tape and Reel)

(TSSOP and SOIC)

Dual Op Amp

Dual Op Amp (Tape and Reel)

(DFN and MSOP)

Quad Op Amp

Quad Op Amp (Tape and Reel)

(QFN)

MCP655:

MCP655T:

MCP659:

MCP659T:

Tape and Reel,

Extended Temperature,

16LD QFN package.

Temperature Range:

Package:

E

= -40°C to +125°C

MF

=Plastic Dual Flat, No Lead (3x3 DFN),

8-lead, 10-lead

SN

UN

ST

=Plastic Small Outline, (3.90 mm), 8-lead

=Plastic Micro Small Outline, (MSOP), 10-lead

=Plastic Thin Shrink Small Outline, (4.4 mm), 14-

lead

SL

=Plastic Small Outline, Narrow, (3.90 mm), 14-

lead

ML

=Plastic Quad Flat, No Lead Package,

(4x4x0.9 mm), 16-lead

DS22146B-page 53

MCP651/2/4/5/9

NOTES:

DS22146B-page 54

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,

TSHARC, UniWinDriver, WiperLock and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-024-0

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS22146B-page 55

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Web Address:

www.microchip.com

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Cleveland

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-6578-300

Fax: 886-3-6578-370

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Fax: 886-7-330-9305

Los Angeles

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Toronto

Mississauga, Ontario,

Canada

China - Zhuhai

Tel: 905-673-0699

Fax: 905-673-6509

Tel: 86-756-3210040

Fax: 86-756-3210049

02/18/11

DS22146B-page 56


型号：	MCP654-E/SN
厂家：	MICROCHIP
描述：	DUAL OP-AMP, 200 uV OFFSET-MAX, 50 MHz BAND WIDTH, PDSO8, 3.90 MM, LEAD FREE, PLASTIC, SOIC-8 光电二极管
文件：	总56页 (文件大小：1679K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP654-E/SN [MICROCHIP]

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