MCP6541-I/P_技术文档

MCP6541/1R/1U/2/3/4

Push-Pull Output Sub-Microamp Comparators

Description

Features

• Low Quiescent Current: 600 nA/comparator (typ.)

• Rail-to-Rail Input: V_SS- 0.3V to V_DD+ 0.3V

• CMOS/TTL-Compatible Output

The Microchip Technology Inc. MCP6541/2/3/4 family

of comparators is offered in single (MCP6541,

MCP6541R, MCP6541U), single with Chip Select (CS)

(MCP6543), dual (MCP6542) and quad (MCP6544)

configurations. The outputs are push-pull (CMOS/TTL-

compatible) and are capable of driving heavy DC or

capacitive loads.

• Propagation Delay: 4 µs (typ., 100 mV Overdrive)

• Wide Supply Voltage Range: 1.6V to 5.5V

• Available in Single, Dual and Quad

• Single available in SOT-23-5, SC-70-5 * packages

• Chip Select (CS) with MCP6543

• Low Switching Current

These comparators are optimized for low power, single-

supply operation with greater than rail-to-rail input

operation.

The

push-pull

output

of

the

MCP6541/1R/1U/2/3/4 family supports rail-to-rail output

swing and interfaces with TTL/CMOS logic. The internal

input hysteresis eliminates output switching due to inter-

nal input noise voltage, reducing current draw. The out-

put limits supply current surges and dynamic power

consumption while switching. This product family oper-

ates with a single-supply voltage as low as 1.6V and

draws less than 1 µA/comparator of quiescent current.

• Internal Hysteresis: 3.3 mV (typ.)

• Temperature Ranges:

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

Typical Applications

• Laptop Computers

• Mobile Phones

The related MCP6546/7/8/9 family of comparators from

Microchip has an open-drain output. Used with a pull-up

resistor, these devices can be used as level-shifters for

any desired voltage up to 10V and in wired-OR logic.

• Metering Systems

• Hand-held Electronics

• RC Timers

* SC-70-5 E-Temp parts not available at this release of

the data sheet.

• Alarm and Monitoring Circuits

• Windowed Comparators

• Multi-vibrators

MCP6541U SOT-23-5 is E-Temp only.

Related Devices

• Open-Drain Output: MCP6546/7/8/9

Package Types

MCP6541

MCP6541R

MCP6542

MCP6544

PDIP, SOIC, MSOP

PDIP, SOIC, TSSOP

PDIP, SOIC, MSOP

SOT-23-5

V_DD

OUTA

14 OUTD

OUTA

1

2

3

4

V_SS

5

1

2

3

4

8

7

6

5

NC

1

2

3

4

8 NC

OUT

V_DD

1

V_INA

–

+

- + + 13 V_IND

-

–

+

V_INA

–

+

OUTB

-

+

V –

-

+

V_DD

7

-

2

3

IN

V_INA

12 V_IND

V_INA

+

V_INB

–

+

-

V +

6

5

OUT

NC

V_IN+

V_IN–

4

IN

V_DD

V

11

V_SS

SS

V_INB

+

–

10 V_INC

+

–

5

6

7

MCP6541

SOT-23-5, SC-70-5

MCP6541U

MCP6543

PDIP, SOIC, MSOP

-

+ +

V_INB

9 V_INC

SOT-23-5

OUTB

8 OUTC

NC

V_IN–

V_IN+

V_SS

CS

V_DD

5

1

2

3

4

8

7

6

5

OUT

V_SS

V_IN–

V_SS

1

2

3

5

1

-

+

-

+

-

2

3

OUT

NC

V_IN+

V_IN– V_IN+

OUT

4

DS21696E-page 1

MCP6541/1R/1U/2/3/4

† Notice: Stresses above those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the

device at those or any other conditions above those indicated

in the operational listings of this specification is not implied.

Exposure to maximum rating conditions for extended periods

may affect device reliability.

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

V_DD- V_SS.........................................................................7.0V

Current at Analog Input Pin (V_IN+, V_IN-.........................±2 mA

Analog Input (V_IN) †† ...................... V_SS- 1.0V to V_DD+ 1.0V

All other Inputs and Outputs........... V_SS- 0.3V to V_DD+ 0.3V

†† See Section 4.1.2 “Input Voltage and Current

Limits”

Difference Input voltage ....................................... |V_DD- V_SS

|

Output Short-Circuit Current .................................continuous

Current at Input Pins ....................................................±2 mA

Current at Output and Supply Pins ............................±30 mA

Storage temperature .....................................-65°C to +150°C

Maximum Junction Temperature (T_J)..........................+150°C

ESD protection on all pins (HBM;MM) ...................4 kV; 400V

DC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V_DD= +1.6V to +5.5V, V_SS= GND, T_A= +25°C,V_IN+ = V_DD/2,

V_IN– = V_SS, and R_L= 100 kΩ to V_DD/2 (Refer to Figure 1-3).

Parameters

Sym

Min

Typ

Max

Units

Conditions

Power Supply

Supply Voltage

V_DD

I_Q

1.6

0.3

—

5.5

1.0

V

Quiescent Current per comparator

Input

0.6

µA

I_OUT= 0

Input Voltage Range

V_CMR

CMRR

PSRR

V_OS

V_SS−0.3

55

—

70

V_DD+0.3

—

V

Common Mode Rejection Ratio

Power Supply Rejection Ratio

Input Offset Voltage

dB

mV

V_DD= 5V, V_CM= -0.3V to 5.3V

V_DD= 5V, V_CM= 2.5V to 5.3V

V_DD= 5V, V_CM= -0.3V to 2.5V

V_CM= V_SS

50

65

—

55

70

—

63

80

—

-7.0

—

±1.5

±3

+7.0

—

V_CM= V_SS(Note 1)

Drift with Temperature

ΔV_OS/ΔT_A

V_HYST

TC₁

µV/°C T_A= -40°C to +125°C, V_CM= V_SS

mV V_CM= V_SS(Note 1)

Input Hysteresis Voltage

Linear Temp. Co. (Note 2)

Quadratic Temp. Co. (Note 2)

Input Bias Current

1.5

—

3.3

6.5

—

6.7

µV/°C T_A= -40°C to +125°C, V_CM= V_SS

µV/°C²T_A= -40°C to +125°C, V_CM= V_SS

TC₂

—

-0.035

1

—

I_B

—

pA

V_CM= V_SS

At Temperature (I-Temp parts)

At Temperature (E-Temp parts)

Input Offset Current

I_B

—

25

100

5000

—

T_A= +85°C, V_CM= V_SS(Note 3)

T_A= +125°C, V_CM= V_SS(Note 3)

V_CM= V_SS

I_B

—

1200

pA

I_OS

—

±1

pA

Common Mode Input Impedance

Differential Input Impedance

Z_CM

—

10¹³||4

10¹³||2

—

Ω||pF

Z_DIFF

—

Note 1: The input offset voltage is the center (average) of the input-referred trip points. The input hysteresis is the difference

between the input-referred trip points.

2:

V

_HYSTat different temperatures is estimated using V_HYST(T_A) = V_HYST+ (T_A- 25°C) TC₁+ (T_A- 25°C)²TC₂.

3: Input bias current at temperature is not tested for SC-70-5 package.

4: Limit the output current to Absolute Maximum Rating of 30 mA.

DS21696E-page 2

MCP6541/1R/1U/2/3/4

DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, V_DD= +1.6V to +5.5V, V_SS= GND, T_A= +25°C,V_IN+ = V_DD/2,

V_IN– = V_SS, and R_L= 100 kΩ to V_DD/2 (Refer to Figure 1-3).

Parameters

Sym

Min

Typ

Max

Units

Conditions

Push-Pull Output

High-Level Output Voltage

Low-Level Output Voltage

Short-Circuit Current

V_OH

V_OL

I_SC

V_DD−0.2

—

V_SS+0.2

—

V

I

= -2 mA, V = 5V

DD

OUT

—

= 2 mA, V = 5V

OUT

DD

-2.5, +1.5

±30

mA

V_DD= 1.6V (Note 4)

V_DD= 5.5V (Note 4)

I_SC

—

Note 1: The input offset voltage is the center (average) of the input-referred trip points. The input hysteresis is the difference

between the input-referred trip points.

2: V_HYSTat different temperatures is estimated using V_HYST(T_A) = V_HYST+ (T_A- 25°C) TC₁+ (T_A- 25°C)²TC₂.

3: Input bias current at temperature is not tested for SC-70-5 package.

4: Limit the output current to Absolute Maximum Rating of 30 mA.

AC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V_DD= +1.6V to +5.5V, V_SS= GND, T_A= +25°C, V_IN+ = V_DD/2,

Step = 200 mV, Overdrive = 100 mV, and C_L= 36 pF (Refer to Figure 1-2 and Figure 1-3).

Parameters

Sym

Min

Typ

Max

Units

Conditions

Rise Time

Fall Time

t_R

—

0.85

4

—

8

µs

t_F

Propagation Delay (High-to-Low)

Propagation Delay (Low-to-High)

Propagation Delay Skew

t_PHL

t_PLH

t_PDS

f_MAX

E_ni

4

8

±0.2

160

120

200

—

(Note 1)

Maximum Toggle Frequency

kHz V_DD= 1.6V

kHz V_DD= 5.5V

Input Noise Voltage

µV_P-P10 Hz to 100 kHz

Note 1: Propagation Delay Skew is defined as: t_PDS= t_PLH- t_PHL

.

MCP6543 CHIP SELECT (CS) CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V_DD= +1.6V to +5.5V, V_SS= GND, T_A= +25°C, V_IN+ = V_DD/2, V_IN– = V_SS

,

and C_L= 36 pF (Refer to Figures 1-1 and 1-3).

Parameters

Sym

Min

Typ

Max Units

Conditions

CS Low Specifications

CS Logic Threshold, Low

V_IL

V_SS

—

0.2 V_DD

—

V

CS Input Current, Low

I_CSL

5.0

pA

CS = V_SS

CS High Specifications

CS Logic Threshold, High

V_IH

I_CSH

I_DD

0.8 V_DD

—

1

V_DD

—

V

CS Input Current, High

—

pA

CS = V_DD

CS Input High, V_DDCurrent

CS Input High, GND Current

Comparator Output Leakage

CS Dynamic Specifications

18

–20

1

—

I_SS

—

I_O(LEAK)

—

V_OUT= V_DD, CS = V_DD

CS Low to Comparator Output Low

Turn-on Time

t_ON

t_OFF

—

2

50

—

ms

µs

V

CS = 0.2 V_DDto V_OUT= V_DD/2,

V

_IN– = V_DD

CS = 0.8 V_DDto V_OUT= V_DD/2,

_IN– = V_DD

V_DD= 5V

CS High to Comparator Output

High Z Turn-off Time

10

0.6

V

CS Hysteresis

V_{CS_HYST}

DS21696E-page 3

MCP6541/1R/1U/2/3/4

CS

V_IL

V_IH

V_IN–

100 mV

t_ON

Hi-Z

t_OFF

V_IN+ = V_DD/2

t_PHL

100 mV

V_OUT

Hi-Z

t_PLH

V_OH

-0.6 µA (typ.)

-20 pA (typ.)

1 pA (typ.)

-20 pA (typ.)

1 pA (typ.)

I_SS

I_CS

V_OUT

V_OL

FIGURE 1-1:

Timing Diagram for the CS

FIGURE 1-2:

Propagation Delay Timing

Pin on the MCP6543.

Diagram.

DS21696E-page 4

MCP6541/1R/1U/2/3/4

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V_DD= +1.6V to +5.5V and V_SS= GND.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Temperature Ranges

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

Thermal Package Resistances

Thermal Resistance, 5L-SC-70

Thermal Resistance, 5L-SOT-23

Thermal Resistance, 8L-PDIP

Thermal Resistance, 8L-SOIC

Thermal Resistance, 8L-MSOP

Thermal Resistance, 14L-PDIP

Thermal Resistance, 14L-SOIC

Thermal Resistance, 14L-TSSOP

T_A

-40

-65

—

+85

+125

+150

°C

°C Note

°C

θ_JA

—

331

256

85

—

°C/W

163

206

70

120

100

Note:

The MCP6541/2/3/4 I-Temp parts operate over this extended temperature range, but with reduced perfor-

mance. In any case, the Junction Temperature (T_J) must not exceed the Absolute Maximum specification

of +150°C.

1.1

Test Circuit Configuration

This test circuit configuration is used to determine the

AC and DC specifications.

V_DD

200 kΩ

MCP654X

200 kΩ

V_OUT

36 pF

200 kΩ

V_IN= V_SS

200 kΩ

V_SS= 0V

FIGURE 1-3:

AC and DC Test Circuit for

the Push-Pull Output Comparators.

DS21696E-page 5

MCP6541/1R/1U/2/3/4

2.0

TYPICAL PERFORMANCE CURVES

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, V_DD= +1.6V to +5.5V, V_SS= GND, T_A= +25°C, V_IN+ = V_DD/2, V_IN– = GND,

R_L= 100 kΩ to V_DD/2, and C_L= 36 pF.

14%

12%

10%

8%

18%

16%

14%

12%

10%

8%

1200 Samples

_CM= V_SS

1200 Samples

_CM= V_SS

V

6%

4%

2%

0%

-7 -6 -5 -4 -3 -2 -1

0

1

2

3

4

5

6

7

1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0

Input Hysteresis Voltage (mV)

Input Offset Voltage (mV)

FIGURE 2-1:

Input Offset Voltage at

FIGURE 2-4:

Input Hysteresis Voltage at

V

= V

.

V

= V

.

CM

SS

CM

SS

25%

20%

15%

10%

5%

16%

14%

596 Samples

1200 Samples

_CM= V_SS

V

_CM= V_SS

V

T_A= -40°C to +125°C

12% T_A= -40°C to +125°C

10%

8%

6%

4%

2%

0%

V_DD= 5.5V

V_DD= 1.6V

0%

Input Hysteresis Voltage –

Linear Temp. Co.; TC₁(µV/°C)

Input Offset Voltage Drift (µV/°C)

FIGURE 2-2:

Input Offset Voltage Drift at

FIGURE 2-5:

Input Hysteresis Voltage

V

= V

.

Linear Temp. Co. (TC ) at V

= V

.

CM

SS

1

CM

SS

20%

18%

7

6

596 Samples

V_DD= 5.5V

V_CM= V_SS

16%

14%

12%

10%

8%

T_A= -40°C to +125°C

V_OUT

5

V_DD= 5.5V

4

3

V_DD= 1.6V

6%

4%

2%

0%

2

1

V_IN–

0

-1

Input Hysteresis Voltage –

Quadratic Temp. Co.; TC₂(µV/°C²)

0

1

2

3

4

5

6

7

8

9

10

Time (1 ms/div)

FIGURE 2-3:

The MCP6541/1R/1U/2/3/4

FIGURE 2-6:

Input Hysteresis Voltage

comparators show no phase reversal.

Quadratic Temp. Co. (TC ) at V

= V

.

2

CM

SS

DS21696E-page 6

MCP6541/1R/1U/2/3/4

Note: Unless otherwise indicated, V_DD= +1.6V to +5.5V, V_SS= GND, T_A= 25°C, V_IN+ = V_DD/2, V_IN– = GND,

R_L= 100 kΩ to V_DD/2, and C_L= 36 pF.

1.0

0.8

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

V_CM= V_SS

0.6

0.4

V_DD= 1.6V

V_DD= 5.5V

0.2

0.0

V_DD= 1.6V

V_DD= 5.5V

-0.2

-0.4

-0.6

-0.8

-1.0

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Ambient Temperature (°C)

FIGURE 2-7:

Input Offset Voltage vs.

FIGURE 2-10:

Input Hysteresis Voltage vs.

Ambient Temperature at V

= V

.

Ambient Temperature at V

= V

.

CM

SS

CM

SS

2.0

6.0

V_DD= 1.6V

T_A= +125°C

5.5

1.5

T

_A= +85°C

_A= +25°C

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

T_A= +125°C

0.0

T

_A= +85°C

_A= +25°C

T_A= +125°C

-0.5

-1.0

-1.5

-2.0

T_A= -40°C

Common Mode Input Voltage (V)

FIGURE 2-8:

Input Offset Voltage vs.

FIGURE 2-11:

Input Hysteresis Voltage vs.

Common Mode Input Voltage at V = 1.6V.

DD

2.0

6.0

V_DD= 5.5V

1.5

V_DD= 5.5V

T_A= +125°C

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

T

_A= +85°C

_A= +25°C

T_A= -40°C

_A= +25°C

1.0

T

T_A= -40°C

0.5

0.0

-0.5

-1.0

-1.5

-2.0

T_A= +85°C

_A= +125°C

T

Common Mode Input Voltage (V)

FIGURE 2-9:

Input Offset Voltage vs.

FIGURE 2-12:

Input Hysteresis Voltage vs.

Common Mode Input Voltage at V = 5.5V.

DD

DS21696E-page 7

MCP6541/1R/1U/2/3/4

Note: Unless otherwise indicated, V_DD= +1.6V to +5.5V, V_SS= GND, T_A= 25°C, V_IN+ = V_DD/2, V_IN– = GND,

R_L= 100 kΩ to V_DD/2, and C_L= 36 pF.

90

85

80

75

70

65

60

55

100100n

10010n

V_DD= 5.5V

Input Referred

I_B, T_A= +125°C

I_B, T_A= +85°C

100p

1 0

PSRR, V_IN+ = V_SS, V_DD= 1.6V to 5.5V

CMRR, V_IN+ = -0.3 to 5.3V, V_DD= 5.0V

10p

10

I_OS, T_A= +125°C

I_OS, T_A= +85°C

1p

1

100f

0.1

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Common Mode Input Voltage (V)

-50

-25

0

25

50

75

100

125

Ambient Temperature (°C)

FIGURE 2-13:

CMRR,PSRR vs. Ambient

FIGURE 2-16:

Input Bias Current, Input

Temperature.

Offset Current vs. Common Mode Input Voltage.

1000

0.7

0.6

0.5

0.4

V_DD= 5.5V

V_CM= V_DD

100

10

1

I_B

T_A= +125°C

_A= +85°C

T_A= +25°C

_A= -40°C

0.3

0.2

0.1

0.0

| I_OS

|

T

0.1

55

65

75

85

95 105 115 125

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

Ambient Temperature (°C)

FIGURE 2-14:

Input Bias Current, Input

FIGURE 2-17:

Quiescent Current vs.

Offset Current vs. Ambient Temperature.

Power Supply Voltage.

0.7

V_DD= 1.6V

V_DD= 5.5V

0.6

0.5

0.4

0.3

0.6

0.5

0.4

0.3

0.2

Sweep V_IN+, V_IN– = V_DD/2

0.1

0.0

0.1

Sweep V_IN–, V_IN+ = V_DD/2

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Common Mode Input Voltage (V)

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

Common Mode Input Voltage (V)

FIGURE 2-15:

Quiescent Current vs.

FIGURE 2-18:

Quiescent Current vs.

Common Mode Input Voltage at V = 1.6V.

Common Mode Input Voltage at V = 5.5V.

DD

DS21696E-page 8

MCP6541/1R/1U/2/3/4

Note: Unless otherwise indicated, V_DD= +1.6V to +5.5V, V_SS= GND, T_A= 25°C, V_IN+ = V_DD/2, V_IN– = GND,

R_L= 100 kΩ to V_DD/2, and C_L= 36 pF.

35

10

T_A= -40°C

T_A= +25°C

_A= +85°C

_A= +125°C

100 mV Overdrive

_CM= V_DD/2

R_L= infinity

30

25

20

15

10

5

V

T

1

V_DD= 5.5V

V_DD= 1.6V

0

0.1

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

0.1

1

10

100

Toggle Frequency (kHz)

FIGURE 2-19:

Supply Current vs. Toggle

FIGURE 2-22:

Output Short Circuit Current

Frequency.

Magnitude vs. Power Supply Voltage.

1.0

0.8

V_OL– V_SS

T_A= +125°C

T_A= +85°C

:

V_DD= 1.6V

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

V_OL–V_SS

:

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

T_A= +125°C

T_A

=

+85°C

+25°C

-40°C

T_A= +25°C

T_A= -40°C

V_DD– V_OH

:

V_DD–V_OH

:

T_A= +125°C

T_A= +85°C

T_A= +125°C

T_A= +85°C

T_A= +25°C

T_A= -40°C

T

_A= +25°C

_A= -40°C

V_DD= 5.5V

10

0

5

15

20

25

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Output Current (mA)

FIGURE 2-20:

Output Voltage Headroom

FIGURE 2-23:

Output Voltage Headroom

vs. Output Current at V = 1.6V.

vs. Output Current at V = 5.5V.

DD

45%

600 Samples

100 mV Overdrive

600 Samples

100 mV Overdrive

V_CM= V_DD/2

40%

35%

30%

25%

20%

15%

10%

5%

35%

V

_CM= V_DD/2

30%

25%

20%

15%

10%

5%

V_DD= 1.6V

V_DD= 5.5V

V_DD= 1.6V

V_DD= 5.5V

0%

0

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

7

8

High-to-Low Propagation Delay (µs)

Low-to-High Propagation Delay (µs)

FIGURE 2-21:

High-to-Low Propagation

FIGURE 2-24:

Low-to-High Propagation

Delay.

DS21696E-page 9

MCP6541/1R/1U/2/3/4

Note: Unless otherwise indicated, V_DD= +1.6V to +5.5V, V_SS= GND, T_A= 25°C, V_IN+ = V_DD/2, V_IN– = GND,

R_L= 100 kΩ to V_DD/2, and C_L= 36 pF.

45%

40%

35%

30%

25%

20%

15%

10%

5%

8

7

6

5

4

3

2

1

0

100 mV Overdrive

_CM= V_DD/2

600 Samples

100 mV Overdrive

V

_CM= V_DD/2

t_PLH@ V_DD= 5.5V

t_PHL@ V_DD= 5.5V

V_DD= 1.6V

V_DD= 5.5V

t_PLH@ V_DD= 1.6V

t_PHL@ V_DD= 1.6V

0%

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0

Propagation Delay Skew (µs)

-50

-25

0

25

50

75

100

125

Ambient Temperature (°C)

FIGURE 2-25:

Propagation Delay Skew.

FIGURE 2-28:

Propagation Delay vs.

Ambient Temperature.

14

100

V_CM= V_DD/2

t_PLH@ 10 mV Overdrive

13

12

11

10

9

V_CM= V_DD/2

t_PHL@ V_DD= 5.5V

t

_PLH@ V_DD= 1.6V

_PHL@ V_DD= 1.6V

8

7

t_PHL@ 10 mV Overdrive

t_PLH@ 100 mV Overdrive

10

6

5

4

t_PLH@ V_DD= 5.5V

3

t_PHL@ 100 mV Overdrive

2

1

0

1

1.5

2.0

2.5

3.0 3.5

4.0

4.5

5.0 5.5

1

10

100

1000

Power Supply Voltage (V)

Input Overdrive (mV)

FIGURE 2-26:

Propagation Delay vs.

FIGURE 2-29:

Propagation Delay vs. Input

Power Supply Voltage.

Overdrive.

8

V_DD= 1.6V

100 mV Overdrive

V_DD= 5.5V

7

100 mV Overdrive

6

5

4

3

2

1

0

6

5

4

3

2

1

0

t_PHL

t_PLH

t_PHL

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Common Mode Input Voltage (V)

FIGURE 2-27:

Propagation Delay vs.

FIGURE 2-30:

Propagation Delay vs.

Common Mode Input Voltage at V = 1.6V.

Common Mode Input Voltage at V = 5.5V.

DD

DS21696E-page 10

MCP6541/1R/1U/2/3/4

Note: Unless otherwise indicated, V_DD= +1.6V to +5.5V, V_SS= GND, T_A= 25°C, V_IN+ = V_DD/2, V_IN– = GND,

R_L= 100 kΩ to V_DD/2, and C_L= 36 pF.

6.0

50

V_DD= 5.5V

100 mV Overdrive

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

-0.5

45

40

35

30

25

20

15

10

5

V_CM= V_DD/2

t_PHL@ V_DD= 1.6V

t_PLH@ V_DD= 1.6V

V_OUT

CS

t_PHL@ V_DD= 5.5V

t_PLH@ V_DD= 5.5V

0

10 20 30 40 50 60 70 80 90

Load Capacitance (nF)

0

1

2

3

4

5

6

7

8

9

10

Time (ms)

FIGURE 2-31:

Propagation Delay vs. Load

FIGURE 2-34:

Chip Select (CS) Step

Capacitance.

Response (MCP6543 only).

1.E-10m3

1.E-03

1m

Comparator

Turns On

Comparator

Shuts Off

Comparator

Turns On

Comparator

Shuts Off

100µ

1.E-04

1.E- 4

100µ

10µ

1.E-05

10µ

1.E- 5

1µ

1.E-06

1µ

1.E-06

CS Hysteresis

CS

Hysteresis

100n

1.E-07

100n

1.E- 7

10n

1.E-08

10n

1.E- 8

CS

High-to-Low

CS

1n

1.E-09

1n

1.E-09

Low-to-High

High-to-Low

Low-to-High

100p

1.E-10

100p

1.E-10

V_DD= 1.6V

V_DD= 5.5V

10p

1.E-11

10p

1.E-11

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

Chip Select (CS) Voltage (V)

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Chip Select (CS) Voltage (V)

FIGURE 2-32:

Supply Current (shoot

FIGURE 2-35:

Supply Current (shoot

through current) vs. Chip Select (CS) Voltage at

V

= 1.6V (MCP6543 only).

V

= 5.5V (MCP6543 only).

DD

200

180

6

30

25

1.6

V_OUT

CS

3

0.0

V_OUT

160

0

CS

140

-3

20

-1.6

-3.2

-4.9

-6.5

-8.1

120

-6

V_DD= 1.6V

Start-up I_DD

100

80

60

40

20

0

-9

15

V_DD= 5.5V

Start-up

I_DD

-12

-15

-18

-21

-24

Charging output

capacitance

10

5

Charging output

capacitance

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Time (0.5 ms/div)

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14

Time (1 ms/div)

FIGURE 2-33:

Supply Current (charging

FIGURE 2-36:

Supply Current (charging

current) vs. Chip Select (CS) pulse at V = 1.6V

current) vs. Chip Select (CS) pulse at V = 5.5V

DD

(MCP6543 only).

DS21696E-page 11

MCP6541/1R/1U/2/3/4

Note: Unless otherwise indicated, V_DD= +1.6V to +5.5V, V_SS= GND, T_A= 25°C, V_IN+ = V_DD/2, V_IN– = GND,

R_L= 100 kΩ to V_DD/2, and C_L= 36 pF.

1.E-02

10m

1.E-03

1m

1.E-04

100µ

1.E1-005µ

1.E-016µ

100n

1.E-07

10n

1.E-08

1n

1.E-09

100p

1.E-10

10p

1.E-11

+125°C

+85°C

+25°C

-40°C

1p

1.E-12

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

Input Voltage (V)

FIGURE 2-37:

Input Bias Current vs. Input

Voltage

DS21696E-page 12

MCP6541/1R/1U/2/3/4

3.0

PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

PIN FUNCTION TABLE

MCP6541

(PDIP,

SOIC,

MCP6541

(SOT-23-5,

MSOP)

SC-70-5)

Symbol

Description

6

2

1

4

1

2

6

2

1

2

OUT, OUTA Digital Output (comparator A)

V_IN–, V_INA– Inverting Input (comparator A)

V_IN+, V_INA+ Non-inverting Input (comparator A)

4

1

3

7

5

2

5

8

7

4

V_DD

Positive Power Supply

—

4

—

2

—

5

—

2

5

—

4

5

V_INB

+

Non-inverting Input (comparator B)

Inverting Input (comparator B)

Digital Output (comparator B)

Digital Output (comparator C)

Inverting Input (comparator C)

Non-inverting Input (comparator C)

Negative Power Supply

6

V_INB

–

7

OUTB

OUTC

—

4

8

9

V_INC

–

+

10

11

12

13

14

—

V_INC

V_SS

—

1, 5, 8

—

8

V_IND

+

Non-inverting Input (comparator D)

Inverting Input (comparator D)

Digital Output (comparator D)

Chip Select

–

OUTD

CS

1, 5

NC

No Internal Connection

3.1

Analog Inputs

3.4

Power Supply (V_SSand V_DD)

The comparator non-inverting and inverting inputs are

high-impedance CMOS inputs with low bias currents.

The positive power supply pin (V_DD) is 1.6V to 5.5V

higher than the negative power supply pin (V_SS). For

normal operation, the other pins are at voltages

between V_SSand V_DD

.

3.2

CS Digital Input

Typically, these parts are used in a single (positive)

supply configuration. In this case, V_SSis connected to

ground and V_DDis connected to the supply. V_DDwill

need a local bypass capacitor (typically 0.01 µF to

0.1 µF) within 2 mm of the V_DDpin. These can share a

bulk capacitor with nearby analog parts (within

100 mm), but it is not required.

This is a CMOS, Schmitt-triggered input that places the

part into a low power mode of operation.

3.3

Digital Outputs

The comparator outputs are CMOS, push-pull digital

outputs. They are designed to be compatible with

CMOS and TTL logic and are capable of driving heavy

DC or capacitive loads.

DS21696E-page 13

MCP6541/1R/1U/2/3/4

the resistors R₁and R₂limit the possible current drawn

out of the input pin. Diodes D₁and D₂prevent the input

4.0

APPLICATIONS INFORMATION

The MCP6541/2/3/4 family of push-pull output compar-

ators are fabricated on Microchip’s state-of-the-art

CMOS process. They are suitable for a wide range of

applications requiring very low power consumption.

pin (V_IN+ and V_IN–) from going too far above V_DD

.

When implemented as shown, resistors R₁and R₂also

limit the current through D₁and D₂.

V_DD

4.1

Comparator Inputs

4.1.1

PHASE REVERSAL

D₁

The MCP6541/1R/1U/2/3/4 comparator family uses

CMOS transistors at the input. They are designed to

prevent phase inversion when the input pins exceed

the supply voltages. Figure 2-3 shows an input voltage

exceeding both supplies with no resulting phase

inversion.

+

V₁

R₁

V_OUT

MCP6G0X

–

D₂

V₂

R₂

R₃

4.1.2

INPUT VOLTAGE AND CURRENT

LIMITS

V_SS– (minimum expected V₁)

2 mA

R₁≥

R₂≥

The ESD protection on the inputs can be depicted as

shown in Figure 4-1. This structure was chosen to pro-

tect the input transistors, and to minimize input bias

current (IB). The input ESD diodes clamp the inputs

when they try to go more than one diode drop below

V_SS. They also clamp any voltages that go too far

above V_DD; their breakdown voltage is high enough to

allow normal operation, and low enough to bypass ESD

events within the specified limits.

V_SS– (minimum expected V₂)

2 mA

FIGURE 4-2:

Protecting the Analog Inputs.

It is also possible to connect the diodes to the left of the

resistors R₁and R₂. In this case, the currents through

the diodes D₁and D₂need to be limited by some other

mechanism. The resistor then serves as in-rush current

limiter; the DC current into the input pins (V_IN+ and

V_IN–) should be very small.

Bond

V_DD

Pad

A significant amount of current can flow out of the

inputs when the common mode voltage (V_CM) is below

ground (V_SS); see Figure 2-37. Applications that are

high impedance may need to limit the useable voltage

range.

Bond

Pad

Bond

Pad

Input

Stage

V_IN+

V_IN–

4.1.3

NORMAL OPERATION

Bond

Pad

The input stage of this family of devices uses two

differential input stages in parallel: one operates at low

input voltages and the other at high input voltages. With

this topology, the input voltage is 0.3V above V_DDand

0.3V below V_SS. Therefore, the input offset voltage is

measured at both V_SS- 0.3V and V_DD+ 0.3V to ensure

proper operation.

V_SS

FIGURE 4-1:

Structures.

Simplified Analog Input ESD

In order to prevent damage and/or improper operation

of these amplifiers, the circuits they are in must limit the

currents (and voltages) at the V_IN+ and V_IN– pins (see

Absolute Maximum Ratings † at the beginning of

Section 1.0 “Electrical Characteristics”). Figure 4-3

shows the recommended approach to protecting these

inputs. The internal ESD diodes prevent the input pins

(V_IN+ and V_IN–) from going too far below ground, and

The MCP6541/1R/1U/2/3/4 family has internally-set

hysteresis that is small enough to maintain input offset

accuracy (<7 mV) and large enough to eliminate output

chattering caused by the comparator’s own input noise

voltage (200 µV_p-p). Figure 4-3 depicts this behavior.

DS21696E-page 14

MCP6541/1R/1U/2/3/4

4.4

Externally Set Hysteresis

8

7

25

20

15

10

5

V_DD= 5.0V

Greater flexibility in selecting hysteresis (or input trip

points) is achieved by using external resistors.

6

V_IN–

5

Input offset voltage (V_OS) is the center (average) of the

(input-referred) low-high and high-low trip points. Input

hysteresis voltage (V_HYST) is the difference between

the same trip points. Hysteresis reduces output

chattering when one input is slowly moving past the

other and thus reduces dynamic supply current. It also

helps in systems where it is best not to cycle between

states too frequently (e.g., air conditioner thermostatic

control).

V_OUT

4

3

0

2

-5

Hysteresis

1

-10

-15

-20

-25

-30

0

-1

-2

-3

Time (100 ms/div)

FIGURE 4-3:

comparators’ internal hysteresis eliminates

output chatter caused by input noise voltage.

The MCP6541/2/3/4

4.4.1

NON-INVERTING CIRCUIT

Figure 4-4 shows a non-inverting circuit for single-

supply applications using just two resistors. The

resulting hysteresis diagram is shown in Figure 4-5.

4.2

Push-Pull Output

The push-pull output is designed to be compatible with

CMOS and TTL logic, while the output transistors are

configured to give rail-to-rail output performance. They

are driven with circuitry that minimizes any switching

current (shoot-through current from supply-to-supply)

when the output is transitioned from high-to-low, or from

low-to-high (see Figures 2-15, 2-18, 2-32 through 2-36

for more information).

V_DD

V_REF

-

V_OUT

MCP654X

+

V_IN

R₁

R_F

Non-inverting circuit with

4.3

MCP6543 Chip Select (CS)

The MCP6543 is a single comparator with Chip Select

(CS). When CS is pulled high, the total current

consumption drops to 20 pA (typ.); 1 pA (typ.) flows

through the CS pin, 1 pA (typ.) flows through the out-

put pin and 18 pA (typ.) flows through the V_DDpin, as

shown in Figure 1-1. When this happens, the

comparator output is put into a high-impedance state.

By pulling CS low, the comparator is enabled. If the CS

pin is left floating, the comparator will not operate

properly. Figure 1-1 shows the output voltage and

supply current response to a CS pulse.

FIGURE 4-4:

hysteresis for single-supply.

V_OUT

V_DD

V_OH

High-to-Low

Low-to-High

V_IN

V_OL

V_SS

The internal CS circuitry is designed to minimize

glitches when cycling the CS pin. This helps conserve

power, which is especially important in battery-powered

applications.

V_SS

V_THLV_TLH

V_DD

FIGURE 4-5:

Hysteresis Diagram for the

Non-Inverting Circuit.

The trip points for Figures 4-4 and 4-5 are:

EQUATION 4-1:

R

⎛

⎜

⎝

⎞

⎛

⎞

⎟

⎠

1

------

⎜

V

= V

1 +------ – V

⎟

TLH

REF

OL

R

⎠

⎝

F

R

⎞

⎛

⎜

⎝

⎛

⎜

⎝

⎞

⎟

⎠

1

------

V

= V

1 +------ – V

⎟

THL

REF

OH

R

F

R

⎠

F

V_TLH= trip voltage from low to high

V_THL= trip voltage from high to low

DS21696E-page 15

MCP6541/1R/1U/2/3/4

Where:

4.4.2

INVERTING CIRCUIT

Figure 4-6 shows an inverting circuit for single-supply

using three resistors. The resulting hysteresis diagram

is shown in Figure 4-7.

R₂R₃

R₂₃= ------------------

R₂+ R₃

R₃

------------------

V_DD

V₂₃

=

× V_DD

R₂+ R₃

V_IN

Using this simplified circuit, the trip voltage can be

calculated using the following equation:

V_DD

V_OUT

MCP654X

R₂

R₃

EQUATION 4-2:

R₂₃

R_F

⎛

⎜

⎝

⎞

⎟

⎠

⎛

⎝

⎞

⎠

----------------------

---------------------

R₂₃+ R_F

V_THL= V_OH

+ V

R_F

23

R

₂₃+ R

F

R₂₃

R_F

⎛

⎜

⎝

⎞

⎟

⎠

⎛

⎝

⎞

⎠

----------------------

---------------------

V_TLH= V_OL

23

R

₂₃+ R

R₂₃+ R_F

F

FIGURE 4-6:

Hysteresis.

Inverting Circuit With

V

_TLH= trip voltage from low to high

V_THL= trip voltage from high to low

V_OUT

Figure 2-20 and Figure 2-23 can be used to determine

typical values for V_OHand V_OL

V_DD

V_OH

.

Low-to-High

High-to-Low

4.5

Bypass Capacitors

With this family of comparators, the power supply pin

(V_DDfor single supply) should have a local bypass

capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good

edge rate performance.

V_IN

V_OL

V_SS

V_TLHV_THL

V_DD

FIGURE 4-7:

Hysteresis Diagram for the

Inverting Circuit.

4.6

Capacitive Loads

In order to determine the trip voltages (V_THLand V_TLH

)

Reasonable capacitive loads (e.g., logic gates) have

little impact on propagation delay (see Figure 2-31).

The supply current increases with increasing toggle

frequency (Figure 2-19), especially with higher

capacitive loads.

for the circuit shown in Figure 4-6, R₂and R₃can be

simplified to the Thevenin equivalent circuit with

respect to V_DD, as shown in Figure 4-8.

V_DD

4.7

Battery Life

-

MCP654X

In order to maximize battery life in portable

applications, use large resistors and small capacitive

loads. Avoid toggling the output more than necessary.

Do not use Chip Select (CS) frequently to conserve

start-up power. Capacitive loads will draw additional

power at start-up.

V_OUT

+

V_SS

V₂₃

R₂₃

R_F

Thevenin Equivalent Circuit.

FIGURE 4-8:

DS21696E-page 16

MCP6541/1R/1U/2/3/4

4.8

PCB Surface Leakage

4.9

Unused Comparators

In applications where low input bias current is critical,

PCB (Printed Circuit Board) surface leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low humidity conditions, a typical resistance

between nearby traces is 10¹²Ω. A 5V difference would

cause 5 pA of current to flow. This is greater than the

MCP6541/1R/1U/2/3/4 family’s bias current at 25°C

(1 pA, typ.).

An unused amplifier in a quad package (MCP6544)

should be configured as shown in Figure 4-10. This

circuit prevents the output from toggling and causing

crosstalk. It uses the minimum number of components

and draws minimal current (see Figure 2-15 and

Figure 2-18).

¼ MCP6544

V_DD

The easiest way to reduce surface leakage is to use a

guard ring around sensitive pins (or traces). The guard

ring is biased at the same voltage as the sensitive pin.

An example of this type of layout is shown in

Figure 4-9.

–

+

V_IN-

V_IN+

V_SS

FIGURE 4-10:

Unused Comparators.

Guard Ring

Example Guard Ring Layout

FIGURE 4-9:

for Inverting Circuit.

1. Inverting Configuration (Figures 4-6 and 4-9):

a. Connect the guard ring to the non-inverting

input pin (V_IN+). This biases the guard ring

to the same reference voltage as the

comparator (e.g., V_DD/2 or ground).

b. Connect the inverting pin (V_IN–) to the input

pad without touching the guard ring.

2. Non-inverting Configuration (Figure 4-4):

a. Connect the non-inverting pin (V_IN+) to the

input pad without touching the guard ring.

b. Connect the guard ring to the inverting input

pin (V_IN–).

DS21696E-page 17

MCP6541/1R/1U/2/3/4

4.10.3

BISTABLE MULTI-VIBRATOR

4.10 Typical Applications

A simple bistable multi-vibrator design is shown in

Figure 4-13. V_REFneeds to be between the power

supplies (V_SS= GND and V_DD) to achieve oscillation.

4.10.1

PRECISE COMPARATOR

Some applications require higher DC precision. An

easy way to solve this problem is to use an amplifier

(such as the MCP6041) to gain-up the input signal

before it reaches the comparator. Figure 4-11 shows an

example of this approach.

The output duty cycle changes with V_REF

.

R₁

R₂

V_REF

V_DD

V_REF

V_OUT

MCP6541

MCP6041

V_DD

MCP654X

V_IN

C₁

R₃

R₁

R₂

V_REF

V_OUT

FIGURE 4-13:

Bistable Multi-vibrator.

FIGURE 4-11:

Precise Inverting

Comparator.

4.10.2

WINDOWED COMPARATOR

Figure 4-12 shows one approach to designing a win-

dowed comparator. The AND gate produces a logic ‘1’

when the input voltage is between V_RBand V_RT(where

V_RT> V_RB).

V_RT

1/2

MCP6542

V_IN

1/2

MCP6542

V_RB

FIGURE 4-12:

Windowed Comparator.

DS21696E-page 18

MCP6541/1R/1U/2/3/4

5.0

5.1

PACKAGING INFORMATION

Package Marking Information

5-Lead SC-70 (MCP6541)

Example:

I-Temp

Code

E-Temp

Code

Device

XXNN Front)

YWW (Back)

AB25 Front)

636 (Back)

MCP6541U

ABNN

Note 2

Note 1: I-Temp parts prior to March

2005 are marked “ABN”

2: SC-70-5 E-Temp parts not

available at this release of

this data sheet.

Example:

5-Lead SOT-23 (MCP6541, MCP6541R, MCP6541U)

I-Temp

Code

E-Temp

Code

Device

MCP6541

MCP6541R

MCP6541U

Note:

ABNN

AGNN

—

GTNN

GUNN

ATNN

XXNN

AB25

Applies to 5-Lead SOT-23

8-Lead PDIP (300 mil)

Example:

XXXXXXXX

XXXXXNNN

MCP6541

I/P256

0636

MCP6541

E/P^^256

0636

e

3

OR

YYWW

8-Lead SOIC (150 mil)

Example:

MCP6542

XXXXXXXX

XXXXYYWW

MCP6541E

I/SN0636

SN^^0636

e

3

OR

NNN

256

Example:

8-Lead MSOP

XXXXXX

YWWNNN

6543I

636256

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

e

3

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e

3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS21696E-page 19

MCP6541/1R/1U/2/3/4

Package Marking Information (Continued)

14-Lead PDIP (300 mil) (MCP6544)

Example:

MCP6544-I/P

XXXXXXXXXXXXXX

YYWWNNN

0636256

e

3

MCP6544E/P

OR

0636256

MCP6544

I/P^^

e

3

0636256

14-Lead SOIC (150 mil) (MCP6544)

Example:

MCP6544ISL

XXXXXXXXXX

YYWWNNN

0636256

MCP6544

e

3

E/SL^^

OR

0636256

Example:

14-Lead TSSOP (MCP6544)

XXXXXXXX

YYWW

MCP6544I

0636

NNN

256

DS21696E-page 20

MCP6541/1R/1U/2/3/4

5-Lead Plastic Small Outline Transistor (LT) (SC-70)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

E

E1

D

p

B

n

1

Q1

A2

A

c

A1

L

Units

INCHES

NOM

MILLIMETERS

NOM

*

Dimension Limits

MIN

MAX

MIN

MAX

n

p

Number of Pins

Pitch

5

.026 (BSC)

0.65 (BSC)

Overall Height

A

A2

A1

E

.031

.043

0.80

1.10

Molded Package Thickness

Standoff

.031

.000

.071

.045

.071

.004

.039

.004

.094

.053

.087

.012

0.80

0.00

1.80

1.15

1.80

0.10

1.00

0.10

2.40

1.35

2.20

0.30

Overall Width

Molded Package Width

Overall Length

E1

D

Foot Length

L

Top of Molded Pkg to

Lead Shoulder

Q1

.004

.016

0.10

0.40

c

Lead Thickness

Lead Width

.004

.006

.007

.012

0.10

0.15

0.18

0.30

B

*

Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

See ASME Y14.5M

JEITA (EIAJ) Standard: SC-70

Revised 07-19-05

Drawing No. C04-061

DS21696E-page 21

MCP6541/1R/1U/2/3/4

5-Lead Plastic Small Outline Transistor (OT) (SOT23)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

E

E1

p

B

p1

D

n

1

α

c

A

A2

φ

L

A1

β

Units

INCHES

NOM

*

MILLIMETERS

NOM

5

Dimension Limits

MIN

MAX

MIN

MAX

n

p

Number of Pins

Pitch

5

.038

0.95

p1

A

Outside lead pitch (basic)

Overall Height

.075

.046

.043

.003

.110

.064

.116

.018

1.90

.035

.057

0.90

1.18

1.45

1.30

0.15

3.00

1.75

3.10

0.55

Molded Package Thickness

Standoff

A2

A1

E

.035

.000

.102

.059

.110

.014

.051

.006

.118

.069

.122

.022

10

0.90

0.00

2.60

1.50

2.80

0.35

1.10

0.08

Overall Width

2.80

Molded Package Width

Overall Length

E1

D

1.63

2.95

Foot Length

L

f

0.45

Foot Angle

0

5

0

5

10

c

Lead Thickness

Lead Width

.004

.014

.006

.017

.008

.020

10

0.09

0.35

0.15

0.43

0.20

0.50

B

a

Mold Draft Angle Top

Mold Draft Angle Bottom

0

5

0

5

10

b

10

0

*

Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.

EIAJ Equivalent: SC-74A

Revised 09-12-05

Drawing No. C04-091

DS21696E-page 22

MCP6541/1R/1U/2/3/4

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

E1

D

2

n

1

α

E

A2

A

L

c

A1

β

B1

B

p

eB

Units

INCHES*

NOM

8

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

8

MAX

n

p

Number of Pins

Pitch

.100

2.54

Top to Seating Plane

A

.140

.155

.130

.170

3.56

2.92

3.94

3.30

4.32

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.300

.240

.360

.125

.008

.045

.014

.310

5

.145

3.68

0.38

7.62

6.10

9.14

3.18

0.20

1.14

0.36

7.87

5

.313

.250

.373

.130

.012

.058

.018

.370

10

.325

.260

.385

.135

.015

.070

.022

.430

15

7.94

6.35

9.46

3.30

0.29

1.46

0.46

9.40

10

8.26

6.60

9.78

3.43

0.38

1.78

0.56

10.92

15

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

B1

B

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

§

eB

α

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MS-001

Drawing No. C04-018

DS21696E-page 23

MCP6541/1R/1U/2/3/4

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

E

E1

p

D

2

B

n

1

h

α

45°

c

A2

A

φ

β

L

A1

Units

INCHES*

MILLIMETERS

Dimension Limits

MIN

NOM

8

MAX

MIN

NOM

8

MAX

n

p

Number of Pins

Pitch

.050

1.27

Overall Height

A

.053

.061

.056

.007

.237

.154

.193

.015

.025

4

.069

1.35

1.32

1.55

1.42

0.18

6.02

3.91

4.90

0.38

0.62

4

1.75

Molded Package Thickness

Standoff

A2

A1

E

.052

.004

.228

.146

.189

.010

.019

0

.061

.010

.244

.157

.197

.020

.030

8

1.55

0.25

6.20

3.99

5.00

0.51

0.76

8

§

0.10

5.79

3.71

4.80

0.25

0.48

0

Overall Width

Molded Package Width

Overall Length

E1

D

Chamfer Distance

Foot Length

h

L

φ

Foot Angle

c

Lead Thickness

Lead Width

.008

.013

0

.009

.017

12

.010

.020

15

0.20

0.33

0

0.23

0.42

12

0.25

0.51

15

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

* Controlling Parameter

§ Significant Characteristic

Notes:

0

12

15

0

12

15

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-057

DS21696E-page 24

MCP6541/1R/1U/2/3/4

8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

2

b

1

e

c

ϕ

A2

A

L1

L

A1

Units

MILLIMETERS

Dimension Limits

NOM

8

MAX

MIN

Number of Pins

Pitch

N

e

0.65 BSC

—

Overall Height

A

1.10

0.95

0.15

0.75

0.00

0.85

Molded Package Thickness

Standoff

A2

A1

E

—

4.90 BSC

3.00 BSC

0.60

Overall Width

Molded Package Width

Overall Length

Foot Length

E1

D

0.40

L

0.80

0.95 REF

—

Footprint

L1

0°

Foot Angle

ϕ

8°

0.08

0.22

—

Lead Thickness

Lead Width

c

0.23

0.40

—

b

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions

shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing No. C04–111, Sept. 8, 2006

DS21696E-page 25

MCP6541/1R/1U/2/3/4

14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

E1

D

2

n

1

α

E

A2

A

L

c

A1

B1

β

eB

p

B

Units

INCHES*

NOM

14

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

14

MAX

n

p

Number of Pins

Pitch

.100

2.54

Top to Seating Plane

A

.140

.155

.130

.170

3.56

2.92

0.38

7.62

6.10

18.80

3.18

0.20

1.14

0.36

7.87

5

3.94

3.30

4.32

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.300

.240

.740

.125

.008

.045

.014

.310

5

.145

3.68

.313

.250

.750

.130

.012

.058

.018

.370

10

.325

.260

.760

.135

.015

.070

.022

.430

15

7.94

6.35

19.05

3.30

0.29

1.46

0.46

9.40

10

8.26

6.60

19.30

3.43

0.38

1.78

0.56

10.92

15

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

B1

B

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

§

eB

α

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MS-001

Drawing No. C04-005

DS21696E-page 26

MCP6541/1R/1U/2/3/4

14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

E

E1

p

D

2

B

n

1

α

h

45°

c

A2

A

φ

A1

L

β

Units

INCHES*

NOM

14

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

14

MAX

n

p

Number of Pins

Pitch

.050

.061

.056

.007

.236

.154

.342

.015

.033

4

1.27

Overall Height

A

.053

.069

1.35

1.32

1.55

1.42

0.18

5.99

3.90

8.69

0.38

0.84

4

1.75

Molded Package Thickness

A2

A1

E

.052

.004

.228

.150

.337

.010

.016

0

.061

.010

.244

.157

.347

.020

.050

8

1.55

0.25

6.20

3.99

8.81

0.51

1.27

8

Standoff

§

0.10

5.79

3.81

8.56

0.25

0.41

0

Overall Width

Molded Package Width

Overall Length

E1

D

Chamfer Distance

Foot Length

h

L

φ

Foot Angle

c

Lead Thickness

Lead Width

.008

.014

0

.009

.017

12

.010

.020

15

0.20

0.36

0

0.23

0.42

12

0.25

0.51

15

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

* Controlling Parameter

§ Significant Characteristic

Notes:

0

12

15

0

12

15

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-065

Revised 7-20-06

DS21696E-page 27

MCP6541/1R/1U/2/3/4

14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

E

E1

p

D

2

1

n

B

α

A

c

φ

β

L

A1

A2

Units

INCHES

NOM

MILLIMETERS

NOM

14

*

Dimension Limits

MIN

MAX

MIN

MAX

n

p

Number of Pins

Pitch

14

.026 BSC

.041

0.65 BSC

1.05

Overall Height

A

A2

A1

E

.039

.033

.002

.246

.169

.193

.020

.043

1.00

1.10

Molded Package Thickness

Standoff

.035

.004

.251

.173

.197

.024

.037

.006

.256

.177

.201

.028

0.85

0.05

6.25

4.30

4.90

0.50

0.90

0.95

0.15

6.50

4.50

5.10

0.70

0.10

Overall Width

6.38

Molded Package Width

Molded Package Length

Foot Length

E1

D

4.40

5.00

L

0.60

φ

Foot Angle

0°

4°

8°

0°

4°

0.15

0.25

12° REF

8°

c

Lead Thickness

.004

.007

.006

.010

.008

.012

0.09

0.19

0.20

0.30

Lead Width

B

α

Mold Draft Angle Top

Mold Draft Angle Bottom

12° REF

β

*

Controlling Parameter

Notes:

Dimensions D and E1 do not include mold fla sh or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

See ASME Y14.5M

REF: Reference Dimension, usually without tole rance, for information purposes only.

See ASME Y14.5M

JEDEC Equivalent: MO-153 AB-1

Drawing No. C04-087

Revised: 08-17-05

DS21696E-page 28

MCP6541/1R/1U/2/3/4

APPENDIX A: REVISION HISTORY

Revision E (September 2006)

The following is the list of modifications:

1. Added MCP6541U pinout for the SOT-23-5

package.

2. Clarified Absolute Maximum Analog Input

Voltage and Current Specifications.

3. Added applications writeups on unused

comparators.

4. Added disclaimer to package outline drawings.

Revision D (May 2006)

The following is the list of modifications:

1. Added E-temp parts.

2. Changed V_HYSTtemperature specification to

linear and quadratic temperature coefficients.

3. Changed specifications and plots for E-Temp.

4. Added Section 3.0 Pin Descriptions

5. Corrected package marking (See Section 5.1

“Package Marking Information”)

6. Added Appendix A: Revision History.

Revision C (September 2003)

Revision B (November 2002)

Revision A (March 2002)

• Original Release of this Document.

DS21696E-page 29

MCP6541/1R/1U/2/3/4

NOTES:

DS21696E-page 30

MCP6541/1R/1U/2/3/4

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

-X

/XX

a)

b)

MCP6541T-I/LT: Tape and Reel,

Temperature Package

Range

Industrial Temperature,

5LD SC-70.

MCP6541T-I/OT: Tape and Reel,

Industrial Temperature,

5LD SOT-23.

Device:

MCP6541:

MCP6541T:

Single Comparator

Single Comparator (Tape and Reel)

(SC-70, SOT-23, SOIC, MSOP)

c)

d)

MCP6541-E/P:

Extended Temperature,

8LD PDIP.

MCP6541RT: Single Comparator (Rotated - Tape and

Reel) (SOT-23 only)

MCP6541UT: Single Comparator (Tape and Reel)

(SOT-23-5 is E-Temp only)

MCP6541RT-I/OT: Tape and Reel,

Industrial Temperature,

5LD SOT23.

MCP6541-E/SN: Extended Temperature,

8LD SOIC.

MCP6542:

MCP6542T:

Dual Comparator

e)

f)

(Tape and Reel for SOIC and MSOP)

Single Comparator with CS

(Tape and Reel for SOIC and MSOP)

Quad Comparator

MCP6543:

MCP6543T:

MCP6541UT-E/OT:Tape and Reel,

Extended Temperature,

MCP6544:

MCP6544T:

5LD SOT23.

Quad Comparator

(Tape and Reel for SOIC and TSSOP)

a)

b)

MCP6542-I/MS: Industrial Temperature,

8LD MSOP.

Temperature Range:

Package:

I

=

-40°C to +85°C

-40°C to +125°C

MCP6542T-I/MS: Tape and Reel,

Industrial Temperature,

8LD MSOP.

E *

* SC-70-5 E-Temp parts not available at this release of the

data sheet.

c)

d)

MCP6542-I/P:

Industrial Temperature,

8LD PDIP.

LT

=

Plastic Package (SC-70), 5-lead

Plastic Small Outline Transistor (SOT-23), 5-lead

Plastic MSOP, 8-lead

Plastic DIP (300 mil Body), 8-lead, 14-lead

Plastic SOIC (150 mil Body), 8-lead

Plastic SOIC (150 mil Body), 14-lead (MCP6544)

Plastic TSSOP (4.4mm Body), 14-lead (MCP6544)

OT

MS

P

SN

SL

ST

MCP6542-E/SN: Extended Temperature,

8LD SOIC.

a)

b)

MCP6543-I/SN: Industrial Temperature,

8LD SOIC.

MCP6543T-I/SN: Tape and Reel,

Industrial Temperature,

8LD SOIC.

c)

d)

MCP6543-I/P:

Industrial Temperature,

8LD PDIP.

MCP6543-E/SN: Extended Temperature,

8LD SOIC.

a)

b)

MCP6544T-I/SL: Tape and Reel,

Industrial Temperature,

14LD SOIC.

MCP6544T-E/SL: Tape and Reel,

Extended Temperature,

14LD SOIC.

c)

d)

MCP6544-I/P:

Industrial Temperature,

14LD PDIP.

MCP6544T-E/ST: Tape and Reel,

Extended Temperature,

14LD TSSOP.

DS21696E-page 31

MCP6541/1R/1U/2/3/4

NOTES:

DS21696E-page 32

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its

PICmicro^®8-bit MCUs, KEELOQ^®code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

DS21696E-page 33

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Habour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-3910

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Alpharetta, GA

Tel: 770-640-0034

Fax: 770-640-0307

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

08/29/06

DS21696E-page 34


型号：	MCP6541-I/P
厂家：	MICROCHIP
描述：	Push-Pull Output Sub-Microamp Comparators 推挽输出亚微安比较比较器放大器放大器电路光电二极管 PC
文件：	总34页 (文件大小：1169K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP6541-I/P [MICROCHIP]

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