MCP662-E/SN_技术文档

MCP661/2/3/5

60 MHz, 6 mA Op Amps

Features

Description

• Gain Bandwidth Product: 60 MHz (typical)

• Short Circuit Current: 90 mA (typical)

• Noise: 6.8 nV/√Hz (typical, at 1 MHz)

• Rail-to-Rail Output

The Microchip Technology, Inc. MCP661/2/3/5 family of

operational amplifiers features high gain bandwidth

product (60 MHz, typical) and high output short circuit

current (90 mA, typical). Some also provide a Chip

Select pin (CS) that supports a low power mode of

operation. These amplifiers are optimized for high

speed, low noise and distortion, single-supply

operation with rail-to-rail output and an input that

includes the negative rail.

• Slew Rate: 32 V/µs (typical)

• Supply Current: 6.0 mA (typical)

• Power Supply: 2.5V to 5.5V

• Extended Temperature Range: -40°C to +125°C

This family is offered in single (MCP661), single with

CS pin (MCP663), dual (MCP662) and dual with

two CS pins (MCP665). All devices are fully specified

from -40°C to +125°C.

Typical Applications

• Driving A/D Converters

• Power Amplifier Control Loops

• Barcode Scanners

Typical Application Circuit

• Optical Detector Amplifier

R₁

R₂

V_DD/2

V_OUT

R_L

Design Aids

R₃

• SPICE Macro Models

• FilterLab^®Software

V_IN

MCP66X

• Mindi™ Circuit Designer & Simulator

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

• Application Notes

Power Driver with High Gain

Package Types

MCP663

MCP661

MCP662

MCP665

SOIC

MSOP

V_DD

V

DD

V_OUTA

1

8

7

6

5

1

8

7

6

5

1

8

7

6

5

V_OUTA

1

2

3

10

9

NC

CS

NC

V_OUTB

V_INA

–

+

V_OUTB

2

3

4

2

3

4

2

3

4

V_INA

–

+

V_IN

–

+

V_DD

V_OUT

NC

V_IN

–

+

V_DD

V_OUT

NC

V_INA

V_INB

–

+

V_INA

V_INB

–

+

8

V_IN

V_{SS 4}

V_SS

7

V_SS

CSA

5

CSB

6

MCP662

3x3 DFN *

MCP665

3x3 DFN *

1

2

3

4

5

10

V_DD

V_OUTA

V_DD

V_OUTA

1

8

7

6

5

V_INA

–

+

V_OUTB

9

8

7

6

V_INA

V_SS

–

V_OUTB

2

3

4

V_INB

–

+

V_INB

–

+

V_SS

CSA

CSB

* Includes Exposed Thermal Pad (EP); see Table 3-1.

DS22194A-page 1

MCP661/2/3/5

NOTES:

DS22194A-page 2

MCP661/2/3/5

† Notice: Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of

the device at those or any other conditions above those

indicated in the operational listings of this specification is not

implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

1.0

1.1

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

V_DD– V_SS.......................................................................6.5V

Current at Input Pins ....................................................±2 mA

Analog Inputs (V_IN+ and V_IN–) †† . V_SS– 1.0V to V_DD+ 1.0V

All other Inputs and Outputs .......... V_SS– 0.3V to V_DD+ 0.3V

Output Short Circuit Current ................................Continuous

Current at Output and Supply Pins ..........................±150 mA

Storage Temperature ...................................-65°C to +150°C

Max. Junction Temperature ........................................+150°C

ESD protection on all pins (HBM, MM) ................≥ 1 kV, 200V

†† See Section 4.1.2 “Input Voltage and Current Limits”.

1.2

Specifications

TABLE 1-1:

DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to +5.5V, V_SS= GND, V_CM= V_DD/3,

V_OUT≈ V_DD/2, V_L= V_DD/2, R_L= 1 kΩ to V_Land CS = V_SS(refer to Figure 1-2).

Conditions

Parameters

Sym

Min

Typ

Max

Units

Input Offset

Input Offset Voltage

V_OS

-8

—

61

±1.8

±2.0

76

+8

—

mV

Input Offset Voltage Drift

Power Supply Rejection Ratio

Input Current and Impedance

Input Bias Current

ΔV_OS/ΔT_A

PSRR

µV/°C T_A= -40°C to +125°C

dB

I_B

—

6

—

pA

Across Temperature

130

pA

T_A= +85°C

Across Temperature

I_B

1700

5,000

—

T_A= +125°C

Input Offset Current

I_OS

Z_CM

Z_DIFF

±10

pA

Common Mode Input Impedance

Differential Input Impedance

Common Mode

10¹³||9

10¹³||2

—

Ω||pF

—

Common-Mode Input Voltage Range

Common-Mode Rejection Ratio

V_CMR

CMRR

V_SS− 0.3

—

79

81

V_DD− 1.3

V

(Note 1)

64

66

—

dB

V_DD= 2.5V, V_CM= -0.3 to 1.2V

V_DD= 5.5V, V_CM= -0.3 to 4.2V

Open Loop Gain

DC Open Loop Gain (large signal)

A_OL

88

94

117

126

—

dB

V_DD= 2.5V, V_OUT= 0.3V to 2.2V

V_DD= 5.5V, V_OUT= 0.3V to 5.2V

Output

Maximum Output Voltage Swing

V_OL, V_OHV_SS+ 25

_OL, V_OHV_SS+ 50

—

V_DD− 25

V_DD− 50

mV

V_DD= 2.5V, G = +2,

0.5V Input Overdrive

V

V_DD= 5.5V, G = +2,

0.5V Input Overdrive

Output Short Circuit Current

I_SC

±45

±40

±90

±80

±145

±150

mA

V_DD= 2.5V (Note 2)

V_DD= 5.5V (Note 2)

Power Supply

Supply Voltage

V_DD

I_Q

2.5

3

—

6

5.5

9

V

Quiescent Current per Amplifier

mA

No Load Current

Note 1: See Figure 2-5 for temperature effects.

2: The I_SCspecifications are for design guidance only; they are not tested.

DS22194A-page 3

MCP661/2/3/5

TABLE 1-2:

AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to +5.5V, V_SS= GND, V_CM= V_DD/2,

V_OUT≈ V_DD/2, V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF and CS = V_SS(refer to Figure 1-2).

Parameters

Sym

Min

Typ

Max Units

Conditions

AC Response

Gain Bandwidth Product

Phase Margin

GBWP

PM

—

60

65

10

—

MHz

°

G = +1

Open Loop Output Impedance

AC Distortion

R_OUT

Ω

Total Harmonic Distortion plus Noise

THD+N

DG

—

0.003

0.3

—

%

°

G = +1, V_OUT= 2V_P-P, f = 1 kHz,

_DD= 5.5V, BW = 80 kHz

V

Differential Gain, Positive Video (Note 1)

Differential Gain, Negative Video (Note 1)

Differential Phase, Positive Video (Note 1)

Differential Phase, Negative Video (Note 1)

NTSC, V_DD= +2.5V, V_SS= -2.5V,

G = +2, V_L= 0V, DC V_IN= 0V to 0.7V

DG

0.3

NTSC, V_DD= +2.5V, V_SS= -2.5V,

G = +2, V_L= 0V, DC V_IN= 0V to -0.7V

DP

0.3

NTSC, V_DD= +2.5V, V_SS= -2.5V,

G = +2, V_L= 0V, DC V_IN= 0V to 0.7V

DP

0.9

°

NTSC, V_DD= +2.5V, V_SS= -2.5V,

G = +2, V_L= 0V, DC V_IN= 0V to -0.7V

Step Response

Rise Time, 10% to 90%

Slew Rate

t_r

—

5

—

ns

G = +1, V_OUT= 100 mV_P-P

SR

32

V/µs G = +1

Noise

Input Noise Voltage

Input Noise Voltage Density

Input Noise Current Density

E_ni

e_ni

i_ni

—

14

6.8

4

—

µV_P-Pf = 0.1 Hz to 10 Hz

nV/√Hz f = 1 MHz

fA/√Hz f = 1 kHz

Note 1: These specifications are described in detail in Section 4.3 “Distortion”.

TABLE 1-3:

DIGITAL ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to +5.5V, V_SS= GND, V_CM= V_DD/2,

V_OUT≈ V_DD/2, V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF and CS = V_SS(refer to Figure 1-1 and Figure 1-2).

Parameters

Sym

Min

Typ

Max Units

Conditions

CS Low Specifications

CS Logic Threshold, Low

CS Input Current, Low

CS High Specifications

CS Logic Threshold, High

CS Input Current, High

GND Current

V_IL

V_SS

—

0.2V_DD

—

V

I_CSL

-0.1

nA

CS = 0V

V_IH

I_CSH

0.8V_DD

V_DD

—

V

—

-2

-0.7

-1

µA

MΩ

nA

CS = V_DD

I_SS

—

CS Internal Pull Down Resistor

Amplifier Output Leakage

CS Dynamic Specifications

CS Input Hysteresis

R_PD

—

5

—

I_O(LEAK)

40

—

CS = V_DD, T_A= +125°C

—

V_HYST

t_OFF

0.25

200

V

CS High to Amplifier Off Time

(output goes High-Z)

ns

G = +1 V/V, V_L= V_SS

CS = 0.8V_DDto V_OUT= 0.1(V_DD/2)

G = +1 V/V, V_L= V_SS

CS = 0.2V_DDto V_OUT= 0.9(V_DD/2)

,

CS Low to Amplifier On Time

t_ON

—

2

10

µs

DS22194A-page 4

MCP661/2/3/5

TABLE 1-4:

TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, all limits are specified for: V_DD= +2.5V to +5.5V, V_SS= GND.

Parameters

Temperature Ranges

Sym

Min

Typ

Max Units

Conditions

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

T_A

-40

-65

—

+125

+150

°C

(Note 1)

Thermal Package Resistances

Thermal Resistance, 8L-3x3 DFN

Thermal Resistance, 8L-SOIC

θ_JA

—

60

149.5

57

—

°C/W (Note 2)

°C/W

Thermal Resistance, 10L-3x3 DFN

Thermal Resistance, 10L-MSOP

°C/W (Note 2)

°C/W

202

Note 1: Operation must not cause T_Jto exceed Maximum Junction Temperature specification (150°C).

2: Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.

EQUATION 1-1:

1.3

Timing Diagram

G_DM= R_F⁄ R_G

V_CM= (V_P+ V_DD⁄ 2) ⁄ 2

V_OST= V_IN–– V_IN+

0 nA

(typical)

1 µA

(typical)

1 µA

(typical)

I_CS

CS

V_OUT= (V_DD⁄ 2) + (V_P– V_M) + V_OST(1 + G_DM

Where:

)

V_IH

V_IL

G_DM= Differential Mode Gain

(V/V)

(V)

t_ON

t_OFF

V_CM= Op Amp’s Common Mode

V_OUT

Input Voltage

High-Z

On

V_OST= Op Amp’s Total Input Offset (mV)

-6 mA

(typical)

Voltage

-1 µA

(typical)

-1 µA

(typical)

I_SS

FIGURE 1-1:

Timing Diagram.

C_F

6.8 pF

1.4

Test Circuits

R_G

10 kΩ

R_F

10 kΩ

The circuit used for most DC and AC tests is shown in

Figure 1-2. This circuit can independently set V_CMand

V_OUT; see Equation 1-1. Note that V_CMis not the

circuit’s common mode voltage ((V_P+ V_M)/2), and that

V_DD/2

V_P

V_DD

V_IN+

V_OSTincludes V_OSplus the effects (on the input offset

C_B1

100 nF

C_B2

2.2 µF

error, V_OST) of temperature, CMRR, PSRR and A_OL

.

MCP66X

V_IN–

V_OUT

V_M

R_L

C_L

R_G

R_F

1 kΩ

20 pF

10 kΩ

C_F

6.8 pF

V_L

FIGURE 1-2:

AC and DC Test Circuit for

Most Specifications.

DS22194A-page 5

MCP661/2/3/5

NOTES:

DS22194A-page 6

MCP661/2/3/5

2.0

TYPICAL PERFORMANCE CURVES

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF and CS = V_SS

.

2.1

DC Signal Inputs

22%

20%

18%

16%

14%

12%

10%

8%

6%

4%

2%

0%

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

100 Samples

T_A= +25°C

V_DD= 2.5V and 5.5V

Representative Part

V_DD= 5.5V

V_DD= 2.5V

-6 -5 -4 -3 -2 -1

0

1

2

3

4

5

6

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

Input Offset Voltage (mV)

FIGURE 2-1:

Input Offset Voltage.

FIGURE 2-4:

Input Offset Voltage vs.

Output Voltage.

24%

0.0

100 Samples

_DD= 2.5V and 5.5V

T_A= -40°C to +125°C

1 Lot

Low (V_{CMR_L}– V_SS

22%

20%

18%

16%

14%

12%

10%

8%

6%

4%

2%

0%

V

)

-0.1

-0.2

-0.3

-0.4

-0.5

V_DD= 2.5V

V_DD= 5.5V

-12 -10 -8 -6 -4 -2

0

2

4

6

8

10 12

-50

-25

0

25

50

75

100 125

Ambient Temperature (°C)

Input Offset Voltage Drift (µV/°C)

FIGURE 2-2:

Input Offset Voltage Drift.

FIGURE 2-5:

Low Input Common Mode

Voltage Headroom vs. Ambient Temperature.

0.0

1.4

Representative Part

V_CM= V_SS

1 Lot

High (V_DD– V_{CMR_H}

-0.2

-0.4

-0.6

-0.8

-1.0

-1.2

-1.4

-1.6

-1.8

-2.0

)

1.3

1.2

1.1

1.0

V_DD= 2.5V

+125°C

+85°C

+25°C

-40°C

V_DD= 5.5V

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Power Supply Voltage (V)

-50

-25

0

25

50

75

100

125

Ambient Temperature (°C)

FIGURE 2-3:

Input Offset Voltage vs.

FIGURE 2-6:

High Input Common Mode

Power Supply Voltage with V

= 0V.

Voltage Headroom vs. Ambient Temperature.

CM

DS22194A-page 7

MCP661/2/3/5

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF and CS = V_SS

.

130

125

120

115

110

105

100

2.0

V_DD= 2.5V

Representative Part

1.5

1.0

V_DD= 5.5V

V_DD= 2.5V

-40°C

+25°C

+85°C

+125°

0.5

0.0

-0.5

-1.0

-1.5

-2.0

-50

-25

0

25

50

75

100

125

Input Common Mode Voltage (V)

Ambient Temperature (°C)

FIGURE 2-7:

Input Offset Voltage vs.

FIGURE 2-10:

DC Open-Loop Gain vs.

Common Mode Voltage with V = 2.5V.

Ambient Temperature.

DD

130

2.0

V_DD= 5.5V

Representative Part

1.5

1.0

125

120

115

110

105

100

95

0.5

+125°

C

+85°C

+25°C

V_DD= 2.5V

0.0

-0.5

-1.0

-1.5

-2.0

100

1k

1.E+03

10k

1.E+04

100k

1.E+05

1.E+02

Input Common Mode Voltage (V)

Load Resistance (Ω)

FIGURE 2-8:

Input Offset Voltage vs.

FIGURE 2-11:

DC Open-Loop Gain vs.

Common Mode Voltage with V = 5.5V.

Load Resistance.

DD

110

105

100

95

1.E-08

10n

V_DD= 5.5V

V_CM= V_{CMR_H}

1n

1.E-09

90

I_B

PSRR

85

80

100p

1.E-10

75

CMRR, V_DD= 2.5V

CMRR, V_DD= 5.5V

10p

1.E-11

70

65

60

| I_OS

|

1p

1.E-12

-50

-25

0

25

50

75

100

125

25

45

65

85

105

125

Ambient Temperature (°C)

FIGURE 2-9:

CMRR and PSRR vs.

FIGURE 2-12:

Input Bias and Offset

Ambient Temperature.

Currents vs. Ambient Temperature with

= +5.5V.

V

DD

DS22194A-page 8

MCP661/2/3/5

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF and CS = V_SS

.

1000

800

600

400

200

0

1.E-10m3

1.E10-004µ

I_B

10µ

1.E-05

1µ

1.E-06

Representative Part

T_A= +125°C

100n

1.E-07

V_DD= 5.5V

10n

1.E- 8

1n

1.E-09

+125°C

+85°C

+25°C

-40°C

100p

1.E-10

I_OS

-200

-400

10p

1.E-11

1p

1.E-12

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

Input Voltage (V)

Common Mode Input Voltage (V)

FIGURE 2-13:

Input Bias Current vs. Input

FIGURE 2-15:

Input Bias and Offset

Voltage (below V ).

Currents vs. Common Mode Input Voltage with

T = +125°C.

SS

A

60

40

20

0

I_B

I_OS

-20

-40

-60

Representative Part

_A= +85°C

V_DD= 5.5V

-80

-100

-120

T

Common Mode Input Voltage (V)

FIGURE 2-14:

Input Bias and Offset

Currents vs. Common Mode Input Voltage with

T = +85°C.

A

DS22194A-page 9

MCP661/2/3/5

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF and CS = V_SS

.

2.2

Other DC Voltages and Currents

1000

9

8

7

6

5

4

3

2

1

0

V_DD= 5.5V

100

10

1

V_DD= 2.5V

V_OL– V_SS

+125°C

+85°C

+25°C

-40°C

V_DD– V_OH

0.1

1

10

100

Power Supply Voltage (V)

Output Current Magnitude (mA)

FIGURE 2-16:

Output Voltage Headroom

FIGURE 2-19:

Supply Current vs. Power

vs. Output Current.

Supply Voltage.

45

7

6

5

R_L= 1 kΩ

40

35

V_OL– V_SS

V_DD= 5.5V

30

V_DD= 2.5V

4

3

2

1

0

25

20

15

10

5

V_DD= 2.5V

V_DD– V_OH

0

-50

-25

0

25

50

75

100

125

Common Mode Input Voltage (V)

Ambient Temperature (°C)

FIGURE 2-17:

Output Voltage Headroom

FIGURE 2-20:

Supply Current vs. Common

vs. Ambient Temperature.

Mode Input Voltage.

100

80

60

+125°C

+85°C

+25°C

-40°C

40

20

0

-20

-40

-60

-80

-100

Power Supply Voltage (V)

FIGURE 2-18:

Output Short Circuit Current

vs. Power Supply Voltage.

DS22194A-page 10

MCP661/2/3/5

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF and CS = V_SS

.

2.3

Frequency Response

100

90

80

70

60

50

40

30

20

10

80

75

70

65

60

55

50

45

40

80

75

70

65

60

55

50

45

40

PM

V_DD= 5.5V

V_DD= 2.5V

CMRR

PSRR+

PSRR-

GBWP

100

₁1_.Ek₊₃

10k

100k

1M

10M

1.E+7

1.E+2

1.E+4

1.E+5

1.E+6

Common Mode Input Voltage (V)

Frequency (Hz)

FIGURE 2-21:

CMRR and PSRR vs.

FIGURE 2-24:

Gain Bandwidth Product

Frequency.

and Phase Margin vs. Common Mode Input

Voltage.

140

120

100

80

0

80

75

70

65

60

55

50

45

40

80

75

70

65

60

55

50

45

40

-30

-60

-90

PM

∠A_OL

V_DD= 5.5V

_DD= 2.5V

V

60

-120

-150

-180

-210

-240

40

| A_OL

|

GBWP

20

0

-20

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

1

0

10 100 1k 10k100k ₁1_.M_E+10M 100M₁1_.EG₊

1.E+ 1.E+

1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+

1

2

3

4

6

7

8

9

Frequenc⁵y (Hz)

FIGURE 2-22:

Open-Loop Gain vs.

FIGURE 2-25:

Gain Bandwidth Product

Frequency.

and Phase Margin vs. Output Voltage.

100

80

75

70

65

80

75

70

65

60

55

50

45

40

10

PM

G = 101 V/V

G = 11 V/V

G = 1 V/V

V_DD= 5.5V

V_DD= 2.5V

60

55

50

45

40

1

GBWP

0.1

-50 -25

0

25

50

75 100 125

10k

100k

1.0E+05

1M

10M

1.0E+07

100M

1.0E+04

1.0E+06

1.0E+08

Ambient Temperature (°C)

Frequency (Hz)

FIGURE 2-23:

Gain Bandwidth Product

FIGURE 2-26:

Closed-Loop Output

and Phase Margin vs. Ambient Temperature.

Impedance vs. Frequency.

DS22194A-page 11

MCP661/2/3/5

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF and CS = V_SS

.

10

9

150

140

130

120

110

100

90

R_S= 0Ω

R

_S= 100Ω

_S= 1 kΩ

8

V_CM= V_DD/2

G = +1 V/V

7

G_N= 1 V/V

G_N= 2 V/V

6

G_N≥ 4 V/V

5

4

3

2

1

0

80

70

R_S= 10 kΩ

R_S= 100 kΩ

60

50

10p

1.0E-11

100p

1.0E-10

Normalized Capacitive Load; C_L/G_N(F)

1n

1.0E-09

1k

10k

1.E+04

100k

1.E+05

1M

1.E+06

10M

1.E+07

1.E+03

Frequency (Hz)

FIGURE 2-27:

Gain Peaking vs.

FIGURE 2-28:

Channel-to-Channel

Normalized Capacitive Load.

Separation vs. Frequency.

DS22194A-page 12

MCP661/2/3/5

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF and CS = V_SS

.

2.4

Noise and Distortion

1.E+4

10µ

20

15

10

5

Representative Part

1.E+3

1µ

0

1.E+2

100n

-5

-10

-15

-20

Analog NPBW = 0.1 Hz

Sample Rate = 2 SPS

V_OS= -953 µV

¹1^.E0+n¹

^1.E1+n⁰

0

5 10 15 20 25 30 35 40 45 50 55 60 65

0.1

1

10 100 _1.1_E+k₃10k 100k ₁1_.EM₊₆10M

1.E-1 1.E+0 1.E+1 1.E+2 1.E+4 1.E+5 1.E+7

Frequency (Hz)

Time (min)

FIGURE 2-29:

Input Noise Voltage Density

FIGURE 2-32:

Input Noise vs. Time with

vs. Frequency.

0.1 Hz Filter.

200

180

1

V_DD= 5.0V

_OUT= 2 V_P-P

V

V_DD= 2.5V

160

140

120

100

80

0.1

0.01

G = 1 V/V

G = 11 V/V

BW = 22 Hz to > 500 kHz

BW = 22 Hz to 80 kHz

V_DD= 5.5V

60

0.001

0.0001

40

20

f = 100 Hz

0

100

1k

1.E+3

10k

1.E+4

100k

1.E+5

1.E+2

Frequency (Hz)

Common Mode Input Voltage (V)

FIGURE 2-30:

Input Noise Voltage Density

FIGURE 2-33:

THD+N vs. Frequency.

vs. Input Common Mode Voltage with f = 100 Hz.

20

18

16

0.2

0.1

0.0

0.2

Positive Video

0.1

Negative Video

0.0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1.0

-0.1

-0.2

-0.3

14

V_DD= 2.5V

12

10

8

V_DD= 5.5V

Δ(|G|)

Δ(∠G)

Representative Part

-0.4

V

_DD= 2.5V

_SS= -2.5V

_L= 0V

_L= 150Ω

Normalized to DC V_IN= 0V

NTSC

-0.5

-0.6

-0.7

-0.8

-0.9

-1.0

6

R

4

2

f = 1 MHz

0

-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8

DC Input Voltage (V)

Common Mode Input Voltage (V)

FIGURE 2-31:

Input Noise Voltage Density

FIGURE 2-34:

Change in Gain Magnitude

vs. Input Common Mode Voltage with f = 1 MHz.

and Phase vs. DC Input Voltage.

DS22194A-page 13

MCP661/2/3/5

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF and CS = V_SS

.

2.5

Time Response

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

V_DD= 5.5V

G = 1

V_DD= 5.5V

G = -1

R_F= 402Ω

V_IN

V_OUT

0

20 40 60 80 100 120 140 160 180 200

Time (ns)

0

100

200

300

Time (ns)

400

500

600

FIGURE 2-35:

Non-inverting Small Signal

FIGURE 2-38:

Inverting Large Signal Step

Step Response.

Response.

5.5

5.0

4.5

4.0

3.5

3.0

7

6

V_DD= 5.5V

G = 2

V_DD= 5.5V

G = 1

V_OUT

5

V_IN

4

3

2.5

V_IN

V_OUT

2

2.0

1.5

1.0

0.5

0.0

1

0

-1

0

100 200 300 400 500 600 700 800

Time (ns)

0

1

2

3

4

5

6

7

8

9

10

Time (µs)

FIGURE 2-36:

Non-inverting Large Signal

FIGURE 2-39:

The MCP661/2/3/5 family

Step Response.

shows no input phase reversal with overdrive.

50

Falling Edge

V_IN

45

V_DD= 5.5V

40

35

30

V_DD= 5.5V

G = -1

R_F= 402Ω

25

V_DD= 2.5V

20

15

10

5

Rising Edge

V_OUT

0

50 100 150 200 250 300 350 400 450 500

Time (ns)

-50

-25

0

25

50

75

100

125

Ambient Temperature (°C)

FIGURE 2-37:

Inverting Small Signal Step

FIGURE 2-40:

Slew Rate vs. Ambient

Response.

Temperature.

DS22194A-page 14

MCP661/2/3/5

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF and CS = V_SS

.

10

V_DD= 5.5V

V_DD= 2.5V

1

0.1

100k

1M

1.E+06

10M

1.E+07

100M

1.E+08

1.E+05

Frequency (Hz)

FIGURE 2-41:

Maximum Output Voltage

Swing vs. Frequency.

DS22194A-page 15

MCP661/2/3/5

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF and CS = V_SS

.

2.6

Chip Select Response

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

CS = V_DD

V_DD= 5.5V

V_DD= 2.5V

-50

-25

0

25

50

75

100

125

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

Ambient Temperature (°C)

FIGURE 2-42:

CS Current vs. Power

FIGURE 2-45:

CS Hysteresis vs. Ambient

Supply Voltage.

Temperature.

3.0

5

4

3

2

1

0

V_DD= 2.5V

G = 1

V_L= 0V

2.5

CS

2.0

1.5

1.0

0.5

V_DD= 2.5V

V_OUT

On

V_DD= 5.5V

0.0

Off

-0.5

-50

-25

0

25

50

75

100

125

0

2

4

6

8

10 12 14 16 18 20

Time (µs)

Ambient Temperature (°C)

FIGURE 2-43:

CS and Output Voltages vs.

FIGURE 2-46:

CS Turn On Time vs.

Time with V = 2.5V.

Ambient Temperature.

DD

6

8

V_DD= 5.5V

Representative Part

CS

G = 1

V_L= 0V

7

6

5

4

3

2

1

0

5

4

3

V_OUT

2

On

1

0

Off

-1

-50

-25

0

25

50

75

100

125

0

1

2

3

4

5

6

7

8

9

10

Time (µs)

Ambient Temperature (°C)

FIGURE 2-44:

CS and Output Voltages vs.

FIGURE 2-47:

CS’s Pull-down Resistor

Time with V = 5.5V.

(R ) vs. Ambient Temperature.

DD

PD

DS22194A-page 16

MCP661/2/3/5

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kΩ to V_L, C_L= 20 pF and CS = V_SS

.

0.0

1.E-016µ

CS = V_DD= 5.5V

CS = V_DD

-0.2

-0.4

-0.6

-0.8

-1.0

100n

1.E-07

+125°C

+85°C

10n

1.E-08

-1.2

-1.4

-1.6

-1.8

-2.0

+125°C

+85°C

+25°C

-40°C

1n

1.E-09

100p

1.E-10

+25°C

10p

1.E-11

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Output Voltage (V)

Power Supply Voltage (V)

FIGURE 2-48:

Shutdown vs. Power Supply Voltage.

Quiescent Current in

FIGURE 2-49:

Output Voltage.

Output Leakage Current vs.

DS22194A-page 17

MCP661/2/3/5

NOTES:

DS22194A-page 18

MCP661/2/3/5

3.0

PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

MCP661

PIN FUNCTION TABLE

MCP662

SOIC DFN

MCP663

MCP665

MSOP DFN

Symbol

Description

SOIC

6

2

3

4

1

2

3

4

1

2

3

4

6

2

3

4

1

2

3

4

1

2

3

4

V_OUT, V_OUTAOutput (op amp A)

V_IN–, V_INA

V_IN+, V_INA

V_SS

–

Inverting Input (op amp A)

Non-inverting Input (op amp A)

Negative Power Supply

+

—

8

5

CS, CSA

CSB

Chip Select Digital Input (op amp A)

—

5

—

5

—

7

6

7

6

7

Chip Select Digital Input (op amp B)

Non-inverting Input (op amp B)

Inverting Input (op amp B)

Output (op amp B)

V_INB

+

–

—

6

8

V_INB

—

7

9

V_OUTB

V_DD

NC

7

8

10

—

10

—

11

Positive Power Supply

1,5,8

—

9

1,5

—

No Internal Connection

EP

Exposed Thermal Pad (EP);

must be connected to V_SS

3.1

Analog Outputs

3.4

Chip Select Digital Input (CS)

The analog output pins (V_OUT) are low-impedance

voltage sources.

This input (CS) is a CMOS, Schmitt-triggered input that

places the part into a low power mode of operation.

3.2

Analog Inputs

3.5

Exposed Thermal Pad (EP)

The non-inverting and inverting inputs (V_IN+, V_IN–, …)

are high-impedance CMOS inputs with low bias

currents.

There is an internal connection between the Exposed

Thermal Pad (EP) and the V_SSpin; they must be

connected to the same potential on the Printed Circuit

Board (PCB).

3.3

Power Supply Pins

This pad can be connected to a PCB ground plane to

provide a larger heat sink. This improves the package

thermal resistance (θ_JA).

The positive power supply (V_DD) is 2.5V to 5.5V higher

than the negative power supply (V_SS). For normal

operation, the other pins are between V_SSand V_DD

.

Typically, these parts are used in a single (positive)

supply configuration. In this case, V_SSis connected to

ground and V_DDis connected to the supply. V_DDwill

need bypass capacitors.

DS22194A-page 19

MCP661/2/3/5

NOTES:

DS22194A-page 20

MCP661/2/3/5

4.0

APPLICATIONS

V_DD

The MCP661/2/3/5 family op amps is manufactured

using Microchip’s state of the art CMOS process. It is

designed for low cost, low power and high speed

applications. Its low supply voltage, low quiescent

current and wide bandwidth make the MCP661/2/3/5

ideal for battery-powered applications.

D₁

R₁

D₂

MCP66X

V₁

V₂

V_OUT

R₂

4.1

Input

V_SS– (minimum expected V₁)

R₁>

R₂>

4.1.1

PHASE REVERSAL

2 mA

V_SS– (minimum expected V₂)

2 mA

The input devices are designed to not exhibit phase

inversion when the input pins exceed the supply

voltages. Figure 2-39 shows an input voltage

exceeding both supplies with no phase inversion.

FIGURE 4-2:

Protecting the Analog

Inputs.

4.1.2

INPUT VOLTAGE AND CURRENT

LIMITS

It is also possible to connect the diodes to the left of the

resistor R₁and R₂. In this case, the currents through

the diodes D₁and D₂need to be limited by some other

mechanism. The resistors then serve as in-rush

current limiters; the DC current into the input pins

(V_IN+ and V_IN–) should be very small.

The ESD protection on the inputs can be depicted as

shown in Figure 4-1. This structure was chosen to

protect the input transistors, and to minimize input bias

current (I_B). The input ESD diodes clamp the inputs

when they try to go more than one diode drop below

V_SS. They also clamp any voltages that go too far

above V_DD; their breakdown voltage is high enough to

allow normal operation, and low enough to bypass

quick ESD events within the specified limits.

A significant amount of current can flow out of the

inputs (through the ESD diodes) when the common

mode voltage (V_CM) is below ground (V_SS); see

Figure 2-13. Applications that are high impedance may

need to limit the usable voltage range.

4.1.3

NORMAL OPERATION

Bond

V_DD

The input stage of the MCP661/2/3/5 op amps uses a

differential PMOS input stage. It operates at

low common mode input voltages (V_CM), with V_CM

between V_SS– 0.3V and V_DD– 1.3V. To ensure proper

operation, the input offset voltage (V_OS) is measured

Pad

Bond

Pad

Bond

Pad

Input

Stage

V_IN+

V_IN–

at both

V_CM= V_SS– 0.3V

and

V_DD– 1.3V.

See Figure 2-5 and Figure 2-6 for temperature effects.

When operating at very low non-inverting gains, the

output voltage is limited at the top by the V_CMrange

(< V_DD– 1.3V); see Figure 4-3.

Bond

Pad

V_SS

FIGURE 4-1:

Structures.

Simplified Analog Input ESD

V_DD

MCP66X

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the currents

(and voltages) at the input pins (see Section 1.1

“Absolute Maximum Ratings †”). Figure 4-2 shows

the recommended approach to protecting these inputs.

The internal ESD diodes prevent the input pins

(V_IN+ and V_IN–) from going too far below ground, and

the resistors R₁and R₂limit the possible current drawn

out of the input pins. Diodes D₁and D₂prevent the

input pins (V_IN+ and V_IN–) from going too far above

V_DD, and dump any currents onto V_DD. When

implemented as shown, resistors R₁and R₂also limit

the current through D₁and D₂.

V_IN

V_OUT

V_SS< V_IN, V_OUT≤ V_DD– 1.3V

FIGURE 4-3:

Unity Gain Voltage

Limitations for Linear Operation.

DS22194A-page 21

MCP661/2/3/5

4.2

Rail-to-Rail Output

V_DD

4.2.1

MAXIMUM OUTPUT VOLTAGE

V_OUT

I_DD

The Maximum Output Voltage (see Figure 2-16 and

Figure 2-17) describes the output range for a given

load. For instance, the output voltage swings to within

50 mV of the negative rail with a 1 kΩ load tied to

V_DD/2.

I_OUT

R_SER

V_L

MCP66X

I_L

R_L

I_SS

4.2.2

OUTPUT CURRENT

V_LG

V_SS

Figure 4-4 shows the possible combinations of output

voltage (V_OUT) and output current (I_OUT), when

V_DD= 5.5V. I_OUTis positive when it flows out of the op

amp into the external circuit.

FIGURE 4-5:

Calculations.

Diagram for Power

The instantaneous op amp power (P_OA(t)), R_SERpower

(P_RSER(t)) and load power (P_L(t)) are:

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

-0.5

V_OHLimited

(V_DD= 5.5V)

EQUATION 4-2:

R_L= 1 kΩ

R_L= 100Ω

P_OA(t) = I_DD(V_DD– V_OUT) + I_SS(V_SS– V_OUT

)

R_L= 10Ω

2

P

_RSER(t) = I_OUTR_SER

2

P_L(t) = I_LR_L

V_OLLimited

The maximum op amp power, for resistive loads,

occurs when V_OUTis halfway between V_DDand V_LGor

halfway between V_SSand V_LG

:

I_OUT(mA)

FIGURE 4-4:

Output Current.

EQUATION 4-3:

2

4.2.3 POWER DISSIPATION

max (V – V , V – V )

DD

LG

SS

P

≤

OAmax

4(R

+ R )

L

Since the output short circuit current (I_SC) is specified

at ±90 mA (typical), these op amps are capable of both

delivering and dissipating significant power.

SER

The maximum ambient to junction temperature rise

(ΔT_JA) and junction temperature (T_J) can be calculated

using P_OAmax, ambient temperature (T_A), the package

thermal resistance (θ_JA) found in Table 1-4, and the

number of op amps in the package (assuming equal

power dissipations):

Figure 4-5 show the quantities used in the following

power calculations for a single op amp. R_SERis 0 Ω in

most applications; it can be used to limit I_OUT. V_OUTis

the op amp’s output voltage, V_Lis the voltage at the

load, and V_LGis the load’s ground point. V_SSis usually

ground (0V). The input currents are assumed to be

negligible. The currents shown are approximately:

EQUATION 4-4:

ΔT = P (t) θ ≤ n P

θ

JA

OA

JA

OAmax JA

EQUATION 4-1:

T = T + ΔT

J

A

JA

V_OUT– V_LG

I_OUT= I_L=

Where:

n

R

_SER+ R_L

=

number of op amps in package (1, 2)

I_DD≈ I_Q+ max(0, I_OUT

)

I_SS≈ –I_Q+ min(0, I_OUT

)

Where:

I_Q

=

quiescent supply current

DS22194A-page 22

MCP661/2/3/5

The power de-rating across temperature for an op amp

in a particular package can be easily calculated

(assuming equal power dissipations):

When driving large capacitive loads with these op

amps (e.g., > 20 pF when G = +1), a small series

resistor at the output (R_ISOin Figure 4-6) improves the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The

bandwidth will be generally lower than the bandwidth

with no capacitive load.

EQUATION 4-5:

T

– T

A

Jmax

n θ

P

≤

OAmax

JA

Where:

T_Jmax

R_ISO

C_L

R_G

R_F

V_OUT

=

absolute max. junction temperature

Several techniques are available to reduce ΔT_JAfor a

MCP66X

given P_OAmax

:

R_N

• Lower θ_JA

FIGURE 4-6:

stabilizes large capacitive loads.

Output Resistor, R

ISO

- Use another package

- PCB layout (ground plane, etc.)

- Heat sinks and air flow

• Reduce P_OAmax

Figure 4-7 gives recommended R_ISOvalues for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (C_L/G_N), where G_Nis the

circuit’s noise gain. For non-inverting gains, G_Nand the

Signal Gain are equal. For inverting gains, G_Nis

1+|Signal Gain| (e.g., -1 V/V gives G_N= +2 V/V).

- Increase R_L

- Limit I_OUT(using R_SER

- Decrease V_DD

)

4.3

Distortion

100

Differential Gain (DG) and Differential Phase (DP)

refer to the non-linear distortion produced by a NTSC

(or PAL) video component. Table 1-2 and Figure 2-34

show the typical performance of the MCP661,

configured as a gain of +2 amplifier (see Figure 4-10),

when driving one back-matched video load (150Ω, for

75Ω cable). Our tests use a sine wave at NTSC’s color

sub-carrier frequency of 3.58 MHz, with a 0.286V_P-P

magnitude. The DC input voltage is changed over a

+0.7V range (positive video) or a -0.7V range (negative

video).

10

G_N= +1

G_N≥ +2

1

10p

100p

1.E-10

1n

1.E-09

10n

1.E-11

1.E-08

Normalized Capacitance; C_L/G_N(F)

DG is the peak-to-peak change in the AC gain

magnitude (color hue), as the DC level (luminance) is

changed, in units of %. DP is the peak-to-peak change

in the AC gain phase (color saturation), as the DC level

(luminance) is changed, in units of °.

FIGURE 4-7:

for Capacitive Loads.

Recommended R

Values

ISO

After selecting R_ISOfor your circuit, double check the

resulting frequency response peaking and step

response overshoot. Modify R_ISO’s value until the

response is reasonable. Bench evaluation and

simulations with the MCP661/2/3/5 SPICE macro

model are helpful.

4.4

Improving Stability

4.4.1

CAPACITIVE LOADS

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. A unity gain buffer (G = +1) is the most

sensitive to capacitive loads, though all gains show the

same general behavior.

DS22194A-page 23

MCP661/2/3/5

Figure 2-37 and Figure 2-38 show the small signal and

large signal step responses at G = -1 V/V. Since the

noise gain is 2 V/V and C_G≈ 10 pF, the resistors were

chosen to be R_F= R_G= 401Ω and R_N= 200Ω.

4.4.2

GAIN PEAKING

Figure 4-8 shows an op amp circuit that represents

non-inverting amplifiers (V_Mis a DC voltage and V_Pis

the input) or inverting amplifiers (V_Pis a DC voltage

and V_Mis the input). The capacitances C_Nand C_Grep-

resent the total capacitance at the input pins; they

include the op amp’s common mode input capacitance

(C_CM), board parasitic capacitance and any capacitor

placed in parallel.

It is also possible to add a capacitor (C_F) in parallel with

R_Fto compensate for the de-stabilizing effect of C_G.

This makes it possible to use larger values of R_F. The

conditions for stability are summarized in Equation 4-6.

EQUATION 4-6:

Given:

C_N

R_N

G_N1= 1 + R_F⁄ R_G

MCP66X

G_N2= 1 + C_G⁄ C_F

f_F= 1 ⁄ (2πR_FC_F)

V_P

V_OUT

f_Z= f_F(G_N1⁄ G_N2

We need:

)

V_M

R_G

R_F

C_G

f_F≤ f_GBWP⁄ (2G_N2), G_N1< G_N2

f_F≤ f_GBWP⁄ (4G_N1), G_N1> G_N2

FIGURE 4-8:

Amplifier with Parasitic

Capacitance.

4.5

MCP663 and MCP665 Chip Select

C_Gacts in parallel with R_G(except for a gain of +1 V/V),

which causes an increase in gain at high frequencies.

C_Galso reduces the phase margin of the feedback

loop, which becomes less stable. This effect can be

reduced by either reducing C_Gor R_F.

The MCP663 is a single amplifier with Chip Select

(CS). When CS is pulled high, the supply current drops

to 1 µA (typical) and flows through the CS pin to V_SS

When this happens, the amplifier output is put into a

high-impedance state. By pulling CS low, the amplifier

is enabled. The CS pin has an internal 5 MΩ (typical)

pulldown resistor connected to V_SS, so it will go low if

the CS pin is left floating. Figure 1-1, Figure 2-43 and

Figure 2-44 show the output voltage and supply current

response to a CS pulse.

.

C_Nand R_Nform a low-pass filter that affects the signal

at V_P. This filter has a single real pole at 1/(2πR_NC_N).

The largest value of R_Fthat should be used depends

on noise gain (see G_Nin Section 4.4.1 “Capacitive

Loads”), C_Gand the open-loop gain’s phase shift.

Figure 4-9 shows the maximum recommended R_Ffor

several C_Gvalues. Some applications may modify

these values to reduce either output loading or gain

peaking (step response overshoot).

The MCP665 is a dual amplifier with two CS pins; CSA

controls op amp A and CSB controls op amp B. These

op amps are controlled independently, with an enabled

quiescent current (I_Q) of 6 mA/amplifier (typical) and a

disabled I_Qof 1 µA/amplifier (typical). The I_Qseen at

the supply pins is the sum of the two op amps’ I_Q; the

typical value for the MCP665’s I_Qwill be 2 µA, 6 mA or

12 mA when there are 0, 1 or 2 amplifiers enabled,

respectively.

1.E+05

100k

G_N> +1 V/V

C_G= 10 pF

C_G= 32 pF

C_G= 100 pF

1.E+1004k

C

_G= 320 pF

_G= 1 nF

C

4.6

Power Supply

1k

1.E+03

With this family of operational amplifiers, the power

supply pin (V_DDfor single supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

for good high frequency performance. Surface mount,

multilayer ceramic capacitors, or their equivalent,

should be used.

100

1.E+02

1

10

100

Noise Gain; G_N(V/V)

FIGURE 4-9:

vs. Gain.

Maximum recommended R

F

These op amps require a bulk capacitor (i.e., 2.2 µF or

larger) within 50 mm to provide large, slow currents.

Tantalum capacitors, or their equivalent, may be a good

choice. This bulk capacitor can be shared with other

nearby analog parts as long as crosstalk through the

supplies does not prove to be a problem.

Figure 2-35 and Figure 2-36 show the small signal and

large signal step responses at G = +1 V/V. The unity

gain buffer usually has R_F= 0Ω and R_Gopen.

DS22194A-page 24

MCP661/2/3/5

The output headroom limits would be V_OL= -2.3V and

V_OH= +2.3V (see Figure 2-16), leaving some design

4.7

High Speed PCB Layout

These op amps are fast enough that a little extra care

in the PCB (Printed Circuit Board) layout can make a

significant difference in performance. Good PC board

layout techniques will help you achieve the

performance shown in the specifications and Typical

Performance Curves; it will also help you minimize

EMC (Electro-Magnetic Compatibility) issues.

room for the ±2V signal. The open-loop gain (A_OL

)

typically does not decrease significantly with a 100Ω

load (see Figure 2-11). The maximum power dissipated

is about 48 mW (see Section 4.2.3 “Power

Dissipation”), so the temperature rise (for the

MCP661 in the SOIC-8 package) is under 8°C.

4.8.2

OPTICAL DETECTOR AMPLIFIER

Use a solid ground plane. Connect the bypass local

capacitor(s) to this plane with minimal length traces.

This cuts down inductive and capacitive crosstalk.

Figure 4-11 shows a transimpedance amplifier, using

the MCP661 op amp, in a photo detector circuit. The

photo detector is

R_Fprovides enough gain to produce 10 mV at V_OUT

C_Fstabilizes the gain and limits the transimpedance

bandwidth to about 1.1 MHz. R_F’s parasitic

capacitance (e.g., 0.2 pF for a 0805 SMD) acts in

parallel with C_F.

a capacitive current source.

Separate digital from analog, low speed from high

speed, and low power from high power. This will reduce

interference.

.

Keep sensitive traces short and straight. Separate

them from interfering components and traces. This is

especially important for high frequency (low rise time)

signals.

C_F

1.5 pF

Sometimes, it helps to place guard traces next to victim

traces. They should be on both sides of the victim

trace, and as close as possible. Connect guard traces

to ground plane at both ends, and in the middle for long

traces.

Photo

Detector

R_F

100 kΩ

V_OUT

Use coax cables, or low inductance wiring, to route

signal and power to and from the PCB. Mutual and self

inductance of power wires is often a cause of crosstalk

and unusual behavior.

I_D

100 nA

C_D

30pF

MCP66X

V_DD/2

4.8

Typical Applications

FIGURE 4-11:

for an Optical Detector.

Transimpedance Amplifier

4.8.1

50Ω LINE DRIVER

Figure 4-10 shows the MCP661 driving a 50Ω line. The

large output current (e.g., see Figure 2-18) makes it

possible to drive a back-matched line (R_M2, the 50Ω

line and the 50Ω load at the far end) to more than ±2V

(the load at the far end sees ±1V). It is worth

mentioning that the 50Ω line and the 50Ω load at the far

end together can be modeled as a simple 50Ω resistor

to ground.

4.8.3

H-BRIDGE DRIVER

Figure 4-12 shows the MCP662 dual op amp used as

a H-bridge driver. The load could be a speaker or a DC

motor.

½ MCP662

V_IN

50Ω

Line

+2.5V

-2.5V

MCP66X

V_OT

R_F

R_M1

R_M2

49.9Ω

R_L

49.9Ω

R_GT

R_GB

50Ω

R_G

R_F

V_OB

301Ω

V_DD/2

½ MCP662

H-Bridge Driver.

FIGURE 4-10:

50Ω Line Driver.

FIGURE 4-12:

DS22194A-page 25

MCP661/2/3/5

This circuit automatically makes the noise gains (G_N)

equal, when the gains are set properly, so that the fre-

quency responses match well (in magnitude and in

phase). Equation 4-7 shows how to calculate R_GTand

R_GBso that both op amps have the same DC gains;

G_DMneeds to be selected first.

EQUATION 4-7:

V_OT– V_OB

--------------------------------

≥ 1 V/V

G_DM

≡

V

_IN– V_DD⁄ 2

R_F

R_GT= --------------------------------

(G_DM⁄ 2) – 1

R_F

R_GB= ------------------

G_DM⁄ 2

Equation 4-8 gives the resulting common mode and

differential mode output voltages.

EQUATION 4-8:

V_OT+ V_OB

-------------------------- = ----------

V_DD

2

V_DD

⎛

⎞

⎠

V_OT– V_OB= G_DMV_IN– ----------

⎝

2

DS22194A-page 26

MCP661/2/3/5

5.5

Analog Demonstration and

Evaluation Boards

5.0

DESIGN AIDS

Microchip provides the basic design aids needed for

the MCP661/2/3/5 family of op amps.

Microchip offers

a

broad spectrum of Analog

Demonstration and Evaluation Boards that are

designed to help customers achieve faster time

to market. For a complete listing of these boards

and their corresponding user’s guides and technical

information, visit the Microchip web site at

www.microchip.com/analog tools.

5.1

SPICE Macro Model

The latest SPICE macro model for the MCP661/2/3/5

op amps is available on the Microchip web site at

www.microchip.com. This model is intended to be an

initial design tool that works well in the op amp’s linear

region of operation over the temperature range.

See the model file for information on its capabilities.

Some boards that are especially useful are:

• MCP6XXX Amplifier Evaluation Board 1

• MCP6XXX Amplifier Evaluation Board 2

• MCP6XXX Amplifier Evaluation Board 3

• MCP6XXX Amplifier Evaluation Board 4

• Active Filter Demo Board Kit

Bench testing is a very important part of any design and

cannot be replaced with simulations. Also, simulation

results using this macro model need to be validated by

comparing them to the data sheet specifications and

characteristic curves.

• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,

P/N SOIC8EV

5.2

FilterLab^®Software

Microchip’s FilterLab^®software is an innovative

software tool that simplifies analog active filter

(using op amps) design. Available at no cost from the

Microchip web site at www.microchip.com/filterlab, the

Filter-Lab design tool provides full schematic diagrams

of the filter circuit with component values. It also

outputs the filter circuit in SPICE format, which can be

used with the macro model to simulate actual filter

performance.

5.6

Application Notes

The following Microchip Application Notes are

available on the Microchip web site at www.microchip.

com/appnotes and are recommended as supplemental

reference resources.

• ADN003: “Select the Right Operational Amplifier

for your Filtering Circuits”, DS21821

• AN722: “Operational Amplifier Topologies and DC

Specifications”, DS00722

5.3

Mindi™ Circuit Designer &

Simulator

• AN723: “Operational Amplifier AC Specifications

and Applications”, DS00723

• AN884: “Driving Capacitive Loads With Op

Amps”, DS00884

Microchip’s Mindi™ Circuit Designer & Simulator aids

in the design of various circuits useful for active filter,

amplifier and power management applications. It is a

free online circuit designer & simulator available from

the Microchip web site at www.microchip.com/mindi.

This interactive circuit designer & simulator enables

designers to quickly generate circuit diagrams,

and simulate circuits. Circuits developed using the

Mindi Circuit Designer & Simulator can be downloaded

to a personal computer or workstation.

• AN990: “Analog Sensor Conditioning Circuits –

An Overview”, DS00990

• AN1228: “Op Amp Precision Design: Random

Noise”, DS01228

Some of these application notes, and others, are listed

in the design guide:

• “Signal Chain Design Guide”, DS21825

5.4

Microchip Advanced Part Selector

(MAPS)

MAPS is a software tool that helps efficiently identify

Microchip devices that fit particular design

a

requirement. Available at no cost from the Microchip

website at www.microchip.com/maps, the MAPS is an

overall selection tool for Microchip’s product portfolio

that includes Analog, Memory, MCUs and DSCs. Using

this tool, a customer can define a filter to sort features

for a parametric search of devices and export

side-by-side technical comparison reports. Helpful links

are also provided for Data sheets, Purchase and

Sampling of Microchip parts.

DS22194A-page 27

MCP661/2/3/5

NOTES:

DS22194A-page 28

MCP661/2/3/5

6.0

6.1

PACKAGING INFORMATION

Package Marking Information

8-Lead DFN (3×3) (MCP662)

Example

Device

Code

XXXX

YYWW

NNN

DABQ

0924

256

MCP662

DABQ

Note:

Applies to 8-Lead 3x3 DFN

8-Lead SOIC (150 mil) (MCP661, MCP662, MCP663)

Example:

XXXXXXXX

MCP661E

e

3

XXXXYYWW

SN 0924

NNN

256

10-Lead DFN (3×3) (MCP665)

Example

XXXX

BAFD

0924

256

Device

Code

YYWW

NNN

MCP665

BAFD

Note:

Applies to 10-Lead 3x3 DFN

10-Lead MSOP (MCP665)

Example:

XXXXXX

YWWNNN

665EUN

924256

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

e

3

*

)

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS22194A-page 29

MCP661/2/3/5

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢈꢄꢊꢐꢆꢑꢒꢆꢂꢃꢄꢅꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢖꢏꢗꢆMꢆꢘꢙꢘꢙꢚꢛꢜꢆ ꢆ!ꢒꢅ"ꢆ#ꢍꢏꢑ$

ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ

e

D

b

N

L

EXPOSED PAD

E

E2

K

NOTE 1

1

2

1

D2

BOTTOM VIEW

TOP VIEW

A

NOTE 2

A3

A1

4ꢄꢃ%

ꢖꢙ55ꢙꢖ,ꢗ,ꢘꢕ

ꢓꢃ&ꢉꢄ ꢃꢌꢄꢅ5ꢃ&ꢃ%

ꢖꢙ6

67ꢖ

9

ꢚꢁ:.ꢅ/ꢕ0

ꢚꢁꢛꢚ

ꢖꢔ8

6!&(ꢉꢊꢅꢌ$ꢅꢂꢃꢄ

ꢂꢃ%ꢍꢎ

7ꢆꢉꢊꢇꢈꢈꢅ;ꢉꢃꢐꢎ%

ꢕ%ꢇꢄ"ꢌ$$ꢅ

0ꢌꢄ%ꢇꢍ%ꢅꢗꢎꢃꢍ*ꢄꢉ

7ꢆꢉꢊꢇꢈꢈꢅ5ꢉꢄꢐ%ꢎ

,#ꢑꢌ ꢉ"ꢅꢂꢇ"ꢅ<ꢃ"%ꢎ

7ꢆꢉꢊꢇꢈꢈꢅ<ꢃ"%ꢎ

6

ꢉ

ꢔ

ꢔꢀ

ꢔ+

ꢓ

,ꢏ

,

ꢚꢁ9ꢚ

ꢚꢁꢚꢚ

ꢀꢁꢚꢚ

ꢚꢁꢚ.

ꢚꢁꢚꢏ

ꢚꢁꢏꢚꢅꢘ,2

+ꢁꢚꢚꢅ/ꢕ0

M

+ꢁꢚꢚꢅ/ꢕ0

M

ꢚꢁ+ꢚ

M

ꢚꢁꢚꢚ

ꢀꢁ:ꢚ

,#ꢑꢌ ꢉ"ꢅꢂꢇ"ꢅ5ꢉꢄꢐ%ꢎ

0ꢌꢄ%ꢇꢍ%ꢅ<ꢃ"%ꢎ

0ꢌꢄ%ꢇꢍ%ꢅ5ꢉꢄꢐ%ꢎ

0ꢌꢄ%ꢇꢍ%ꢜ%ꢌꢜ,#ꢑꢌ ꢉ"ꢅꢂꢇ"

ꢓꢏ

(

5

ꢚꢁꢚꢚ

ꢚꢁꢏ.

ꢚꢁꢏꢚ

ꢏꢁꢒꢚ

ꢚꢁ+.

ꢚꢁ..

M

>

ꢑꢒꢊꢃꢉ%

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ !ꢇꢈꢅꢃꢄ"ꢉ#ꢅ$ꢉꢇ%!ꢊꢉꢅ&ꢇꢋꢅꢆꢇꢊꢋ'ꢅ(!%ꢅ&! %ꢅ(ꢉꢅꢈꢌꢍꢇ%ꢉ"ꢅ)ꢃ%ꢎꢃꢄꢅ%ꢎꢉꢅꢎꢇ%ꢍꢎꢉ"ꢅꢇꢊꢉꢇꢁ

ꢏꢁ ꢂꢇꢍ*ꢇꢐꢉꢅ&ꢇꢋꢅꢎꢇꢆꢉꢅꢌꢄꢉꢅꢌꢊꢅ&ꢌꢊꢉꢅꢉ#ꢑꢌ ꢉ"ꢅ%ꢃꢉꢅ(ꢇꢊ ꢅꢇ%ꢅꢉꢄ" ꢁ

+ꢁ ꢂꢇꢍ*ꢇꢐꢉꢅꢃ ꢅ ꢇ)ꢅ ꢃꢄꢐ!ꢈꢇ%ꢉ"ꢁ

ꢒꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢐꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢐꢅꢑꢉꢊꢅꢔꢕꢖ,ꢅ-ꢀꢒꢁ.ꢖꢁ

/ꢕ01 /ꢇ ꢃꢍꢅꢓꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢗꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ

ꢘ,21 ꢘꢉ$ꢉꢊꢉꢄꢍꢉꢅꢓꢃ&ꢉꢄ ꢃꢌꢄ'ꢅ! !ꢇꢈꢈꢋꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ'ꢅ$ꢌꢊꢅꢃꢄ$ꢌꢊ&ꢇ%ꢃꢌꢄꢅꢑ!ꢊꢑꢌ ꢉ ꢅꢌꢄꢈꢋꢁ

ꢖꢃꢍꢊꢌꢍꢎꢃꢑ ꢗꢉꢍꢎꢄꢌꢈꢌꢐꢋ ꢓꢊꢇ)ꢃꢄꢐ 0ꢚꢒꢜꢚ:ꢏ/

DS22194A-page 30

MCP661/2/3/5

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢈꢄꢊꢐꢆꢑꢒꢆꢂꢃꢄꢅꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢖꢏꢗꢆMꢆꢘꢙꢘꢙꢚꢛꢜꢆ ꢆ!ꢒꢅ"ꢆ#ꢍꢏꢑ$

ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ

DS22194A-page 31

MCP661/2/3/5

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ& ꢄꢈꢈꢆ'ꢎꢊꢈꢋ(ꢃꢆꢕ&ꢑꢗꢆMꢆꢑꢄ))ꢒ*ꢐꢆꢘꢛꢜꢚꢆ ꢆ!ꢒꢅ"ꢆ#&'+,$

ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ

D

e

N

E

E1

NOTE 1

1

2

3

α

h

b

h

c

φ

A2

A

L

A1

L1

β

4ꢄꢃ%

ꢖꢙ55ꢙꢖ,ꢗ,ꢘꢕ

ꢓꢃ&ꢉꢄ ꢃꢌꢄꢅ5ꢃ&ꢃ%

ꢖꢙ6

67ꢖ

ꢖꢔ8

6!&(ꢉꢊꢅꢌ$ꢅꢂꢃꢄ

ꢂꢃ%ꢍꢎ

6

ꢉ

9

ꢀꢁꢏꢞꢅ/ꢕ0

7ꢆꢉꢊꢇꢈꢈꢅ;ꢉꢃꢐꢎ%

ꢔ

M

ꢀꢁꢏ.

ꢚꢁꢀꢚ

M

ꢀꢁꢞ.

M

ꢚꢁꢏ.

ꢖꢌꢈ"ꢉ"ꢅꢂꢇꢍ*ꢇꢐꢉꢅꢗꢎꢃꢍ*ꢄꢉ

ꢕ%ꢇꢄ"ꢌ$$ꢅꢅ

ꢔꢏ

ꢔꢀ

,

ꢝ

7ꢆꢉꢊꢇꢈꢈꢅ<ꢃ"%ꢎ

:ꢁꢚꢚꢅ/ꢕ0

ꢖꢌꢈ"ꢉ"ꢅꢂꢇꢍ*ꢇꢐꢉꢅ<ꢃ"%ꢎ

7ꢆꢉꢊꢇꢈꢈꢅ5ꢉꢄꢐ%ꢎ

0ꢎꢇ&$ꢉꢊꢅ@ꢌꢑ%ꢃꢌꢄꢇꢈA

2ꢌꢌ%ꢅ5ꢉꢄꢐ%ꢎ

,ꢀ

ꢓ

ꢎ

+ꢁꢛꢚꢅ/ꢕ0

ꢒꢁꢛꢚꢅ/ꢕ0

ꢚꢁꢏ.

ꢚꢁꢒꢚ

M

ꢚꢁ.ꢚ

ꢀꢁꢏꢞ

5

2ꢌꢌ%ꢑꢊꢃꢄ%

2ꢌꢌ%ꢅꢔꢄꢐꢈꢉ

5ꢉꢇ"ꢅꢗꢎꢃꢍ*ꢄꢉ

5ꢉꢇ"ꢅ<ꢃ"%ꢎ

ꢖꢌꢈ"ꢅꢓꢊꢇ$%ꢅꢔꢄꢐꢈꢉꢅꢗꢌꢑ

ꢖꢌꢈ"ꢅꢓꢊꢇ$%ꢅꢔꢄꢐꢈꢉꢅ/ꢌ%%ꢌ&

5ꢀ

ꢀ

ꢀꢁꢚꢒꢅꢘ,2

ꢚꢟ

ꢚꢁꢀꢞ

ꢚꢁ+ꢀ

.ꢟ

M

9ꢟ

ꢍ

(

ꢁ

ꢚꢁꢏ.

ꢚꢁ.ꢀ

ꢀ.ꢟ

ꢂ

.ꢟ

ꢀ.ꢟ

ꢑꢒꢊꢃꢉ%

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ !ꢇꢈꢅꢃꢄ"ꢉ#ꢅ$ꢉꢇ%!ꢊꢉꢅ&ꢇꢋꢅꢆꢇꢊꢋ'ꢅ(!%ꢅ&! %ꢅ(ꢉꢅꢈꢌꢍꢇ%ꢉ"ꢅ)ꢃ%ꢎꢃꢄꢅ%ꢎꢉꢅꢎꢇ%ꢍꢎꢉ"ꢅꢇꢊꢉꢇꢁ

ꢏꢁ ꢝꢅꢕꢃꢐꢄꢃ$ꢃꢍꢇꢄ%ꢅ0ꢎꢇꢊꢇꢍ%ꢉꢊꢃ %ꢃꢍꢁ

+ꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄ ꢅꢓꢅꢇꢄ"ꢅ,ꢀꢅ"ꢌꢅꢄꢌ%ꢅꢃꢄꢍꢈ!"ꢉꢅ&ꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢁꢅꢖꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢅ ꢎꢇꢈꢈꢅꢄꢌ%ꢅꢉ#ꢍꢉꢉ"ꢅꢚꢁꢀ.ꢅ&&ꢅꢑꢉꢊꢅ ꢃ"ꢉꢁ

ꢒꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢐꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢐꢅꢑꢉꢊꢅꢔꢕꢖ,ꢅ-ꢀꢒꢁ.ꢖꢁ

/ꢕ01 /ꢇ ꢃꢍꢅꢓꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢗꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ

ꢘ,21 ꢘꢉ$ꢉꢊꢉꢄꢍꢉꢅꢓꢃ&ꢉꢄ ꢃꢌꢄ'ꢅ! !ꢇꢈꢈꢋꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ'ꢅ$ꢌꢊꢅꢃꢄ$ꢌꢊ&ꢇ%ꢃꢌꢄꢅꢑ!ꢊꢑꢌ ꢉ ꢅꢌꢄꢈꢋꢁ

ꢖꢃꢍꢊꢌꢍꢎꢃꢑ ꢗꢉꢍꢎꢄꢌꢈꢌꢐꢋ ꢓꢊꢇ)ꢃꢄꢐ 0ꢚꢒꢜꢚ.ꢞ/

DS22194A-page 32

MCP661/2/3/5

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ& ꢄꢈꢈꢆ'ꢎꢊꢈꢋ(ꢃꢆꢕ&ꢑꢗꢆMꢆꢑꢄ))ꢒ*ꢐꢆꢘꢛꢜꢚꢆ ꢆ!ꢒꢅ"ꢆ#&'+,$

ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ

DS22194A-page 33

MCP661/2/3/5

-ꢚꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢈꢄꢊꢐꢆꢑꢒꢆꢂꢃꢄꢅꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢖꢏꢗꢆMꢆꢘꢙꢘꢙꢚꢛꢜꢆ ꢆ!ꢒꢅ"ꢆ#ꢍꢏꢑ$

ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ

D

e

b

N

L

K

E

E2

EXPOSED

PAD

NOTE 1

2

1

2

D2

BOTTOM VIEW

TOP VIEW

A

A1

A3

NOTE 2

4ꢄꢃ%

ꢖꢙ55ꢙꢖ,ꢗ,ꢘꢕ

ꢓꢃ&ꢉꢄ ꢃꢌꢄꢅ5ꢃ&ꢃ%

ꢖꢙ6

67ꢖ

ꢀꢚ

ꢚꢁ.ꢚꢅ/ꢕ0

ꢚꢁꢛꢚ

ꢖꢔ8

6!&(ꢉꢊꢅꢌ$ꢅꢂꢃꢄ

ꢂꢃ%ꢍꢎ

7ꢆꢉꢊꢇꢈꢈꢅ;ꢉꢃꢐꢎ%

ꢕ%ꢇꢄ"ꢌ$$ꢅ

0ꢌꢄ%ꢇꢍ%ꢅꢗꢎꢃꢍ*ꢄꢉ

7ꢆꢉꢊꢇꢈꢈꢅ5ꢉꢄꢐ%ꢎ

,#ꢑꢌ ꢉ"ꢅꢂꢇ"ꢅ5ꢉꢄꢐ%ꢎ

7ꢆꢉꢊꢇꢈꢈꢅ<ꢃ"%ꢎ

6

ꢉ

ꢔ

ꢔꢀ

ꢔ+

ꢓ

ꢓꢏ

,

ꢚꢁ9ꢚ

ꢚꢁꢚꢚ

ꢀꢁꢚꢚ

ꢚꢁꢚ.

ꢚꢁꢚꢏ

ꢚꢁꢏꢚꢅꢘ,2

+ꢁꢚꢚꢅ/ꢕ0

ꢏꢁ+.

+ꢁꢚꢚꢅ/ꢕ0

ꢀꢁ.9

ꢚꢁꢏ.

ꢚꢁꢒꢚ

M

ꢏꢁꢏꢚ

ꢏꢁꢒ9

,#ꢑꢌ ꢉ"ꢅꢂꢇ"ꢅ<ꢃ"%ꢎ

0ꢌꢄ%ꢇꢍ%ꢅ<ꢃ"%ꢎ

0ꢌꢄ%ꢇꢍ%ꢅ5ꢉꢄꢐ%ꢎ

0ꢌꢄ%ꢇꢍ%ꢜ%ꢌꢜ,#ꢑꢌ ꢉ"ꢅꢂꢇ"

,ꢏ

(

5

ꢀꢁꢒꢚ

ꢚꢁꢀ9

ꢚꢁ+ꢚ

ꢚꢁꢏꢚ

ꢀꢁꢞ.

ꢚꢁ+ꢚ

ꢚꢁ.ꢚ

M

>

ꢑꢒꢊꢃꢉ%

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ !ꢇꢈꢅꢃꢄ"ꢉ#ꢅ$ꢉꢇ%!ꢊꢉꢅ&ꢇꢋꢅꢆꢇꢊꢋ'ꢅ(!%ꢅ&! %ꢅ(ꢉꢅꢈꢌꢍꢇ%ꢉ"ꢅ)ꢃ%ꢎꢃꢄꢅ%ꢎꢉꢅꢎꢇ%ꢍꢎꢉ"ꢅꢇꢊꢉꢇꢁ

ꢏꢁ ꢂꢇꢍ*ꢇꢐꢉꢅ&ꢇꢋꢅꢎꢇꢆꢉꢅꢌꢄꢉꢅꢌꢊꢅ&ꢌꢊꢉꢅꢉ#ꢑꢌ ꢉ"ꢅ%ꢃꢉꢅ(ꢇꢊ ꢅꢇ%ꢅꢉꢄ" ꢁ

+ꢁ ꢂꢇꢍ*ꢇꢐꢉꢅꢃ ꢅ ꢇ)ꢅ ꢃꢄꢐ!ꢈꢇ%ꢉ"ꢁ

ꢒꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢐꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢐꢅꢑꢉꢊꢅꢔꢕꢖ,ꢅ-ꢀꢒꢁ.ꢖꢁ

/ꢕ01 /ꢇ ꢃꢍꢅꢓꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢗꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ

ꢘ,21 ꢘꢉ$ꢉꢊꢉꢄꢍꢉꢅꢓꢃ&ꢉꢄ ꢃꢌꢄ'ꢅ! !ꢇꢈꢈꢋꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ'ꢅ$ꢌꢊꢅꢃꢄ$ꢌꢊ&ꢇ%ꢃꢌꢄꢅꢑ!ꢊꢑꢌ ꢉ ꢅꢌꢄꢈꢋꢁ

ꢖꢃꢍꢊꢌꢍꢎꢃꢑ ꢗꢉꢍꢎꢄꢌꢈꢌꢐꢋ ꢓꢊꢇ)ꢃꢄꢐ 0ꢚꢒꢜꢚ:+/

DS22194A-page 34

MCP661/2/3/5

-ꢚꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢈꢄꢊꢐꢆꢑꢒꢆꢂꢃꢄꢅꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢖꢏꢗꢆMꢆꢘꢙꢘꢙꢚꢛꢜꢆ ꢆ!ꢒꢅ"ꢆ#ꢍꢏꢑ$

ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ

DS22194A-page 35

MCP661/2/3/5

-ꢚꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢖꢋꢌ)ꢒꢆ& ꢄꢈꢈꢆ'ꢎꢊꢈꢋ(ꢃꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕ.ꢑꢗꢆ#ꢖ&'ꢇ$

ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ

D

N

E

E1

NOTE 1

1

2

b

e

c

A

A2

φ

L

A1

L1

4ꢄꢃ%

ꢖꢙ55ꢙꢖ,ꢗ,ꢘꢕ

ꢓꢃ&ꢉꢄ ꢃꢌꢄꢅ5ꢃ&ꢃ%

ꢖꢙ6

67ꢖ

ꢖꢔ8

6!&(ꢉꢊꢅꢌ$ꢅꢂꢃꢄ

ꢂꢃ%ꢍꢎ

6

ꢉ

ꢀꢚ

ꢚꢁ.ꢚꢅ/ꢕ0

7ꢆꢉꢊꢇꢈꢈꢅ;ꢉꢃꢐꢎ%

ꢖꢌꢈ"ꢉ"ꢅꢂꢇꢍ*ꢇꢐꢉꢅꢗꢎꢃꢍ*ꢄꢉ

ꢕ%ꢇꢄ"ꢌ$$ꢅ

7ꢆꢉꢊꢇꢈꢈꢅ<ꢃ"%ꢎ

ꢖꢌꢈ"ꢉ"ꢅꢂꢇꢍ*ꢇꢐꢉꢅ<ꢃ"%ꢎ

7ꢆꢉꢊꢇꢈꢈꢅ5ꢉꢄꢐ%ꢎ

2ꢌꢌ%ꢅ5ꢉꢄꢐ%ꢎ

ꢔ

M

ꢚꢁꢞ.

ꢚꢁꢚꢚ

M

ꢚꢁ9.

ꢀꢁꢀꢚ

ꢚꢁꢛ.

ꢚꢁꢀ.

ꢔꢏ

ꢔꢀ

,

,ꢀ

ꢓ

M

ꢒꢁꢛꢚꢅ/ꢕ0

+ꢁꢚꢚꢅ/ꢕ0

ꢚꢁ:ꢚ

5

ꢚꢁꢒꢚ

ꢚꢁ9ꢚ

2ꢌꢌ%ꢑꢊꢃꢄ%

2ꢌꢌ%ꢅꢔꢄꢐꢈꢉ

5ꢀ

ꢀ

ꢚꢁꢛ.ꢅꢘ,2

M

ꢚꢟ

9ꢟ

5ꢉꢇ"ꢅꢗꢎꢃꢍ*ꢄꢉ

5ꢉꢇ"ꢅ<ꢃ"%ꢎ

ꢍ

(

ꢚꢁꢚ9

ꢚꢁꢀ.

M

ꢚꢁꢏ+

ꢚꢁ++

ꢑꢒꢊꢃꢉ%

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ !ꢇꢈꢅꢃꢄ"ꢉ#ꢅ$ꢉꢇ%!ꢊꢉꢅ&ꢇꢋꢅꢆꢇꢊꢋ'ꢅ(!%ꢅ&! %ꢅ(ꢉꢅꢈꢌꢍꢇ%ꢉ"ꢅ)ꢃ%ꢎꢃꢄꢅ%ꢎꢉꢅꢎꢇ%ꢍꢎꢉ"ꢅꢇꢊꢉꢇꢁ

ꢏꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄ ꢅꢓꢅꢇꢄ"ꢅ,ꢀꢅ"ꢌꢅꢄꢌ%ꢅꢃꢄꢍꢈ!"ꢉꢅ&ꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢁꢅꢖꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢅ ꢎꢇꢈꢈꢅꢄꢌ%ꢅꢉ#ꢍꢉꢉ"ꢅꢚꢁꢀ.ꢅ&&ꢅꢑꢉꢊꢅ ꢃ"ꢉꢁ

+ꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢐꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢐꢅꢑꢉꢊꢅꢔꢕꢖ,ꢅ-ꢀꢒꢁ.ꢖꢁ

/ꢕ01 /ꢇ ꢃꢍꢅꢓꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢗꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ

ꢘ,21 ꢘꢉ$ꢉꢊꢉꢄꢍꢉꢅꢓꢃ&ꢉꢄ ꢃꢌꢄ'ꢅ! !ꢇꢈꢈꢋꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ'ꢅ$ꢌꢊꢅꢃꢄ$ꢌꢊ&ꢇ%ꢃꢌꢄꢅꢑ!ꢊꢑꢌ ꢉ ꢅꢌꢄꢈꢋꢁ

ꢖꢃꢍꢊꢌꢍꢎꢃꢑ ꢗꢉꢍꢎꢄꢌꢈꢌꢐꢋ ꢓꢊꢇ)ꢃꢄꢐ 0ꢚꢒꢜꢚꢏꢀ/

DS22194A-page 36

MCP661/2/3/5

APPENDIX A: REVISION HISTORY

Revision A (July 2009)

• Original Release of this Document.

DS22194A-page 37

MCP661/2/3/5

NOTES:

DS22194A-page 38

MCP661/2/3/5

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

-X

/XX

Examples:

a)

MCP661T-E/SN: Tape and Reel

Temperature

Range

Package

Extended temperature,

8LD SOIC package

a)

b)

MCP662T-E/MF: Tape and Reel

Device:

MCP661

MCP661T

Single Op Amp

Single Op Amp (Tape and Reel)

(SOIC)

Dual Op Amp

Dual Op Amp (Tape and Reel)

(DFN and SOIC)

Extended temperature,

8LD DFN package

MCP662T-E/SN: Tape and Reel

MCP662

MCP662T

Extended temperature,

8LD SOIC package

MCP663

MCP663T

Single Op Amp with CS

Single Op Amp with CS (Tape and Reel)

(SOIC)

a)

MCP663T-E/SN: Tape and Reel

Extended temperature,

8LD SOIC package

MCP665

MCP665T

Dual Op Amp with CS

Dual Op Amp with CS (Tape and Reel)

(DFN and MSOP)

a)

b)

MCP665T-E/MF: Tape and Reel

Extended temperature,

10LD DFN package

MCP665T-E/UN: Tape and Reel

Temperature Range:

Package:

E

=

-40°C to +125°C

Extended temperature,

10LD MSOP package

MF

Plastic Dual Flat, No Lead (3×3 DFN),

8-lead, 10-lead

SN

UN

=

Plastic Small Outline (3.90 mm), 8-lead

Plastic Micro Small Outline (MSOP), 10-lead

DS22194A-page 39

MCP661/2/3/5

NOTES:

DS22194A-page 40

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

rfPIC and UNI/O are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICkit, PICDEM, PICDEM.net,

PICtail, PIC³²logo, REAL ICE, rfLAB, Select Mode, Total

Endurance, TSHARC, WiperLock and ZENA are trademarks

of Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS22194A-page 41

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4080

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Cleveland

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Hsin Chu

Tel: 886-3-6578-300

Fax: 886-3-6578-370

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

03/26/09

DS22194A-page 42


型号：	MCP662-E/SN
厂家：	MICROCHIP
描述：	60 MHz, 6 mA Op Amps 60兆赫， 6毫安运算放大器运算放大器放大器电路光电二极管 PC
文件：	总42页 (文件大小：795K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP662-E/SN [MICROCHIP]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E