MCP662T-E/MS_技术文档

MCP660/1/2/3/4/5/9

60 MHz, 32 V/µs Rail-to-Rail Output (RRO) Op Amps

Features:

Description:

• Gain-Bandwidth Product: 60 MHz (typical)

• Slew Rate: 32 V/µs (typical)

The Microchip Technology Inc. MCP660/1/2/3/4/5/9

family of operational amplifiers (op amps) features high

gain-bandwidth product and high slew rate. Some also

provide a Chip Select pin (CS) that supports a low-

power mode of operation. These amplifiers are

optimized for high speed, low noise and distortion,

single-supply operation with rail-to-rail output and an

input that includes the negative rail.

• Noise: 6.8 nV/Hz (typical, at 1 MHz)

• Short Circuit Current: 90 mA (typical)

• Low Input Bias Current: 4 pA (typical)

• Ease of Use:

- Unity-Gain Stable

- Rail-to-Rail Output

This family is offered in single (MCP661), single with

CS pin (MCP663), dual (MCP662) and dual with two

CS pins (MCP665), triple (MCP660), quad (MCP664)

and quad with two CS pins (MCP669). All devices are

fully specified from -40°C to +125°C.

- Input Range including Negative Rail

- No Phase Reversal

• Supply Voltage Range: +2.5V to +5.5V

• High Output Current: ±70 mA

• Supply Current: 6.0 mA/ch (typical)

• Low-Power Mode: 1 µA/ch

Typical Application Circuit

R_ISO

• Small Packages: SOT23-5, DFN

• Extended Temperature Range: -40°C to +125°C

R_G

R_F

V_REF

V_OUT

-

C_L

R_L

Typical Applications:

V_IN

+

• Multi-Pole Active Filter

• Driving A/D Converters

• Power Amplifier Control Loops

• Line Driver

MCP66X

100

10

1

• Video Amplifier

• Barcode Scanners

• Optical Detector Amplifier

G_N= +1

G_Nꢁꢂꢃ

Design Aids:

• SPICE Macro Models

• FilterLab^®Software

10p

1.E-11

100p

1.E-10

1n

1.E-09

10n

1.E-08

• Microchip Advanced Part Selector (MAPS)

• Analog Demonstration and Evaluation Boards

- MCP661DM-LD

Normalized Capacitance; C_L/G_N(F)

• Application Notes

High Gain-Bandwidth Op Amp Portfolio

Model Family

Channels/Package

Gain-Bandwidth

V_OS(max.)

I_Q/Ch (typ.)

MCP621/1S/2/3/4/5/9

MCP631/2/3/4/5/9

1, 2, 4

20 MHz

24 MHz

50 MHz

60 MHz

0.2 mV

8.0 mV

0.2 mV

8.0 mV

2.5 mA

6.0 mA

MCP651/1S/2/3/4/5/9

MCP660/1/2/3/4/5/9

1, 2, 4

1, 2, 3, 4

 2009-2014 Microchip Technology Inc.

DS20002194E-page 1

MCP660/1/2/3/4/5/9

Package Types

MCP660

MCP661

4x4 QFN*

SOIC, TSSOP

SOT-23-5

V

NC

1

2

3

4

5

6

7

14

13

12

11

10

9

OUTC

V

1

2

3

5

4

DD

OUT

V

-

NC

INC

16 15 14 13

V

SS

+

INC

NC

V

+

1

12

11

10

9

INC

V

DD

SS

-

V

+

IN

2

3

4

SS

EP

17

V

+

V

+

INA

INB

+

-

V

-

INB

DD

-

INA

INB

V

+

INB

INA

V

OUTA

8

OUTB

5

6

7

8

MCP661

SOIC

MCP661

2x3 TDFN*

MCP662

MSOP, SOIC

MCP662

3x3 DFN*

V

1

2

3

4

8

V

NC

V

1

2

3

4

8

NC

CS

V

1

2

3

4

8

7

6

5

1

2

8

7

V

OUTA

DD

OUTA

DD

V

7

6

5

V

-

V

-

V

7

6

5

V

-

OUTB

V

–

INA

OUTB

IN

DD

INA

EP

9

IN

DD

EP

9

-

V

+

V

+

V

+

-

INB

INA

IN

OUT

INA

INB

V

+

V

OUT

3

4

6

5

IN

+

V

INB

V

NC

SS

V

+

V

NC

SS

INB

SS

MCP663

SOIC

MCP663

SOT-23-6

MCP664

SOIC, TSSOP

1

8

7

6

5

NC

CS

V

1

2

3

4

5

6

7

14

13

12

11

10

9

OUTD

6

5

OUTA

V

1

2

3

DD

OUT

2

3

4

V

-

V

-

V

-

IN

DD

INA

IND

CS

V

SS

V

+

V

+

INA

IN

OUT

IND

V

NC

DD

SS

V

-

4

V

+

IN

V

+

V

+

INB

INC

V

-

INB

INC

V

8

OUTB

OUTC

MCP665

3x3 DFN*

MCP665

MSOP

MCP669

4x4 QFN*

V

1

2

3

4

5

10

V

1

10

9

DD

OUTA

DD

-

V

9

8

7

6

INA

OUTB

V

-

V

2

3

INA

OUTB

EP

11

+

-

+

INA

INB

V

+

16 15 14 13

-

8

INA

INB

V

SS

INB

V

-

V

+

V

+

1

12

11

10

9

INA

IND

SS 4

7

INB

CSA

CSB

V

+

CSA

CSB

2

3

4

5

6

INA

SS

EP

17

+

-

V

INC

DD

V

+

INC

INB

5

6

7

8

* Includes Exposed Thermal Pad (EP); see Table 3-1.

DS20002194E-page 2

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

† Notice: Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at those or any other conditions

above those indicated in the operational listings of this

specification is not implied. Exposure to maximum rat-

ing conditions for extended periods may affect device

reliability.

1.0

1.1

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

V

– V

.......................................................................6.5V

SS

DD

Current at Input Pins ....................................................±2 mA

Analog Inputs (V + and V –) †† . V – 1.0V to V + 1.0V

IN

SS

DD

†† See Section 4.1.2 “Input Voltage and Current

Limits”.

All Other Inputs and Outputs ......... V – 0.3V to V + 0.3V

SS

DD

Output Short Circuit Current ................................Continuous

Current at Output and Supply Pins ..........................±150 mA

Storage Temperature ...................................-65°C to +150°C

Maximum Junction Temperature ................................+150°C

ESD protection on all pins (HBM, MM)  1 kV, 200V

1.2

Specifications

DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to +5.5V, V_SS= GND,

_CM= V_DD/3, V_OUT V_DD/2, V_L= V_DD/2, R_L= 1 k to V_Land CS = V_SS(refer to Figure 1-2).

V

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Input Offset

Input Offset Voltage

V_OS

-8

—

61

±1.8

±2.0

76

+8

—

mV

Input Offset Voltage Drift

Power Supply Rejection Ratio

Input Current and Impedance

Input Bias Current

V_OS/T_A

PSRR

µV/°C T_A= -40°C to +125°C

dB

I_B

—

6

—

pA

Across Temperature

Input Offset Current

130

T_A= +85°C

T_A= +125°C

pA

I_B

1700

5000

—

I_OS

Z_CM

±10

10¹³||9

Common-Mode Input

Impedance

—

||pF

Differential Input Impedance

Z_DIFF

—

10¹³||2

—

||pF

Common Mode

Common-Mode Input Voltage

Range

V_CMR

V_SS

0.3

V_DD

1.3



V

Note 1

_DD= 2.5V, V_CM= -0.3V to 1.2V

Common-Mode Rejection Ratio

CMRR

64

66

79

81

—

dB

V

dB V_DD= 5.5V, V_CM= -0.3V to 4.2V

Open-Loop Gain

DC Open-Loop Gain

(large signal)

A_OL

88

94

117

126

—

dB V_DD= 2.5V, V_OUT= 0.3V to 2.2V

dB V_DD= 5.5V, V_OUT= 0.3V to 5.2V

Output

Maximum Output Voltage Swing V_OL, V_OHV_SS+ 25

—

V_DD 25 mV V_DD= 2.5V, G = +2,

0.5V Input Overdrive

V_SS+ 50

V_DD 50

V_DD= 5.5V, G = +2,

0.5V Input Overdrive

Output Short-Circuit Current

I_SC

±45

±40

±90

±80

±145

±150

mA V_DD= 2.5V (Note 2)

V

_DD= 5.5V (Note 2)

Note 1: See Figure 2-5 for temperature effects.

2: The I_SCspecifications are for design guidance only; they are not tested.

 2009-2014 Microchip Technology Inc.

DS20002194E-page 3

MCP660/1/2/3/4/5/9

DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to +5.5V, V_SS= GND,

V_CM= V_DD/3, V_OUT V_DD/2, V_L= V_DD/2, R_L= 1 k to V_Land CS = V_SS(refer to Figure 1-2).

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Power Supply

Supply Voltage

V_DD

I_Q

2.5

3

—

6

5.5

9

V

Quiescent Current per Amplifier

mA No Load Current

Note 1: See Figure 2-5 for temperature effects.

2: The I_SCspecifications are for design guidance only; they are not tested.

AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to +5.5V, V_SS= GND,

V_CM= V_DD/2, V_OUT V_DD/2, V_L= V_DD/2, R_L= 1 k to V_L, C_L= 20 pF and CS = V_SS(refer to Figure 1-2).

Parameters

Sym.

Min. Typ. Max. Units

Conditions

AC Response

Gain-Bandwidth Product

Phase Margin

GBWP

PM

—

60

65

10

—

MHz

°

G = +1

Open-Loop Output Impedance

AC Distortion

R_OUT



Total Harmonic Distortion plus Noise THD + N

—

0.003

0.3

—

%

G = +1, V_OUT= 2V_P-P, f = 1 kHz,

_DD= 5.5V, BW = 80 kHz

V

Differential Gain, Positive Video

(Note 1)

DG

DP

NTSC, V_DD= +2.5V, V_SS= -2.5V,

G = +2, V_L= 0V,

DC V_IN= 0V to 0.7V

Differential Gain, Negative Video

(Note 1)

—

0.3

0.9

—

%

°

NTSC, V_DD= +2.5V, V_SS= -2.5V,

G = +2, V_L= 0V,

DC V_IN= 0V to -0.7V

Differential Phase, Positive Video

(Note 1)

NTSC, V_DD= +2.5V, V_SS= -2.5V,

G = +2, V_L= 0V,

DC V_IN= 0V to 0.7V

Differential Phase, Negative Video

°

NTSC, V_DD= +2.5V, V_SS= -2.5V,

G = +2, V_L= 0V,

(Note 1)

DC V_IN= 0V to -0.7V

Step Response

Rise Time, 10% to 90%

Slew Rate

t_r

—

5

—

ns

G = +1, V_OUT= 100 mV_P-P

SR

32

V/µs G = +1

Noise

Input Noise Voltage

Input Noise Voltage Density

Input Noise Current Density

E_ni

e_ni

i_ni

—

14

6.8

4

—

µV_P-Pf = 0.1 Hz to 10 Hz

nV/Hz f = 1 MHz

fA/Hz f = 1 kHz

Note 1: These specifications are described in detail in Section 4.3 “Distortion”. (NTSC refers to a National

Television Standards Committee signal.)

DS20002194E-page 4

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

DIGITAL ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless indicated, T_A= +25°C, V_DD= +2.5V to +5.5V, V_SS= GND, V_CM= V_DD/2,

V_OUT V_DD/2, V_L= V_DD/2, R_L= 1 k to V_L, C_L= 20 pF and CS = V_SS(refer to Figures 1-1 and 2-1).

Parameters

Sym.

Min.

Typ.

Max. Units

Conditions

CS Low Specifications

CS Logic Threshold, Low

CS Input Current, Low

V_IL

V_SS

—

0.2V_DD

—

V

I_CSL

-0.1

nA CS = 0V

CS High Specifications

CS Logic Threshold, High

CS Input Current, High

GND Current

V_IH

I_CSH

0.8V_DD

—

V_DD

—

V

—

-2

-0.7

-1

µA CS = V_DD

I_SS

—

µA

CS Internal Pull-Down Resistor

Amplifier Output Leakage

R_PD

—

5

—

M

I_O(LEAK)

40

—

nA CS = V_DD, T_A= +125°C

CS Dynamic Specifications

—

CS Input Hysteresis

V_HYST

t_OFF

0.25

200

V

CS High to Amplifier Off Time

(output goes High Z)

ns G = +1 V/V, V_L= V_SS

CS = 0.8V_DDto V_OUT= 0.1(V_DD/2)

CS Low to Amplifier On Time

t_ON

—

2

10

µs G = +1 V/V, V_L= V_SS

CS = 0.2V_DDto V_OUT= 0.9(V_DD/2)

TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, all limits are specified for V_DD= +2.5V to +5.5V, V_SS= GND.

Parameters

Temperature Ranges

Sym.

Min.

Typ.

Max. Units

Conditions

Specified Temperature Range

T_A

-40

-65

—

+125

+150

°C

Operating Temperature Range

Storage Temperature Range

Note 1

Thermal Package Resistances

Thermal Resistance, 5L-SOT-23

Thermal Resistance, 6L-SOT-23

Thermal Resistance, 8L-3x3 DFN

Thermal Resistance, 8L-MSOP

Thermal Resistance, 8L-SOIC

Thermal Resistance, 8L-2x3 TDFN

Thermal Resistance, 10L-3x3 DFN

Thermal Resistance, 10L-MSOP

Thermal Resistance, 14L-SOIC

Thermal Resistance, 14L-TSSOP

Thermal Resistance, 16L-QFN

θ_JA

—

201.0

190.5

56.7

211

—

°C/W

°C/W Note 2

°C/W

149.5

52.5

54.0

202

°C/W

°C/W Note 2

°C/W

90.8

100

°C/W

52.1

°C/W

Note 1: Operation must not cause T_Jto exceed the Maximum Junction Temperature specification (+150°C).

2: Measured on a standard JC51-7, four-layer printed circuit board with ground plane and vias.

 2009-2014 Microchip Technology Inc.

DS20002194E-page 5

MCP660/1/2/3/4/5/9

1.3

Timing Diagram

C_F

6.8 pF

0 nA

(typical)

1 µA

(typical)

1 µA

(typical)

I_CS

CS

R_G

R_F

10 k

V_IH

V_IL

V_DD/2

V_P

V_DD

t_ON

t_OFF

V_IN+

C_B1

100 nF

C_B2

2.2 µF

+

-

V_OUT

High Z

On

MCP66X

-6 mA

(typical)

-1 µA

(typical)

-1 µA

(typical)

V_IN-

I_SS

V_OUT

V_M

R_L

1 k

C_L

20 pF

R_G

10 k

R_F

10 k

FIGURE 1-1:

Timing Diagram.

1.4 Test Circuits

C_F

V_L

The circuit used for most DC and AC tests is shown in

Figure 1-2. This circuit can independently set V_CMand

V_OUT; see Equation 1-1. Note that V_CMis not the

circuit’s common-mode voltage ((V_P+ V_M)/2) and that

V_OSTincludes V_OSplus the effects (on the input offset

6.8 pF

FIGURE 1-2:

Most Specifications.

AC and DC Test Circuit for

error, V_OST) of temperature, CMRR, PSRR and A_OL

.

EQUATION 1-1:

R_F

G_DM= ------

R_G

V_DD

V_P+ ----------

2

V_CM= ------------------------

2

V_OST= V_IN-– V_IN+

V_DD

V_OUT= ---------- + V_P– V_M + V_OST1 + G_DM



2

Where:

G_DM= Differential Mode Gain

(V/V)

V_CM= Op Amp’s Common-Mode (V)

Input Voltage

V_OST= Op Amp’s Total Input

Offset Voltage

(mV)

DS20002194E-page 6

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

2.0

TYPICAL PERFORMANCE CURVES

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kto V_L, C_L= 20 pF and CS = V_SS

.

2.1

DC Signal Inputs

22%

20%

18%

16%

14%

12%

10%

8%

6%

4%

2%

0%

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

100 Samples

T_A= +25°C

V_DD= 2.5V and 5.5V

Representative Part

V_DD= 5.5V

V_DD= 2.5V

-6 -5 -4 -3 -2 -1

0

1

2

3

4

5

6

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

Input Offset Voltage (mV)

FIGURE 2-1:

Input Offset Voltage.

FIGURE 2-4:

Input Offset Voltage vs.

Output Voltage.

24%

0.0

100 Samples

_DD= 2.5V and 5.5V

_A= -40°C to +125°C

1 Lot

Low (V_{CMR_L}– V_SS

22%

20%

18%

16%

14%

12%

10%

8%

6%

4%

2%

0%

V

T

)

-0.1

-0.2

-0.3

-0.4

-0.5

V_DD= 2.5V

V_DD= 5.5V

-50

-25

0

25

50

75

100 125

-12 -10 -8 -6 -4 -2

0

2

4

6

8

10 12

Ambient Temperature (°C)

Input Offset Voltage Drift (µV/°C)

FIGURE 2-2:

Input Offset Voltage Drift.

FIGURE 2-5:

Low-Input Common-Mode

Voltage Headroom vs. Ambient Temperature.

0.0

1.4

1 Lot

High (V_DD– V_{CMR_H}

Representative Part

V_CM= V_SS

-0.2

-0.4

-0.6

-0.8

-1.0

-1.2

-1.4

-1.6

-1.8

-2.0

)

1.3

1.2

1.1

1.0

V_DD= 2.5V

+125°C

+85°C

+25°C

-40°C

V_DD= 5.5V

-50

-25

0

25

50

75

100

125

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Power Supply Voltage (V)

Ambient Temperature (°C)

FIGURE 2-3:

Input Offset Voltage vs.

FIGURE 2-6:

High-Input Common-Mode

Power Supply Voltage with V_CM= 0V.

Voltage Headroom vs. Ambient Temperature.

 2009-2014 Microchip Technology Inc.

DS20002194E-page 7

MCP660/1/2/3/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kto V_L, C_L= 20 pF and CS = V_SS

.

130

125

120

115

110

105

100

2.0

V_DD= 2.5V

Representative Part

1.5

1.0

V_DD= 5.5V

V_DD= 2.5V

-40°C

+25°C

+85°C

+125°

0.5

0.0

-0.5

-1.0

-1.5

-2.0

-50

-25

0

25

50

75

100

125

Input Common Mode Voltage (V)

Ambient Temperature (°C)

FIGURE 2-7:

Input Offset Voltage vs.

FIGURE 2-10:

DC Open-Loop Gain vs.

Common-Mode Voltage with V_DD= 2.5V.

Ambient Temperature.

130

2.0

V_DD= 5.5V

1.5 Representative Part

125

120

115

110

105

100

95

1.0

0.5

+125°

V_DD= 2.5V

C

+85°C

+25°C

0.0

-0.5

-1.0

-1.5

-2.0

100

1k

1.E+03

10k

1.E+04

100k

1.E+05

1.E+02

Input Common Mode Voltage (V)

Load Resistance (Ω)

FIGURE 2-8:

Input Offset Voltage vs.

FIGURE 2-11:

DC Open-Loop Gain vs.

Common-Mode Voltage with V_DD= 5.5V.

Load Resistance.

110

105

100

95

1.E-08

10n

V_DD= 5.5V

V

_CM= V_{CMR_H}

1n

1.E-09

90

I_B

PSRR

85

80

100p

1.E-10

75

CMRR, V_DD= 2.5V

CMRR, V_DD= 5.5V

10p

1.E-11

70

65

60

| I_OS

|

1p

1.E-12

-50

-25

0

25

50

75

100

125

25

45

65

85

105

125

Ambient Temperature (°C)

FIGURE 2-9:

CMRR and PSRR vs.

FIGURE 2-12:

Input Bias and Offset

Ambient Temperature.

Currents vs. Ambient Temperature with

_DD= 5.5V.

V

DS20002194E-page 8

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kto V_L, C_L= 20 pF and CS = V_SS

.

1000

800

600

400

200

0

1.E-10m3

1.E10-004µ

I_B

10µ

1.E-05

1µ

1.E-06

Representative Part

T_A= +125°C

100n

1.E-07

V_DD= 5.5V

10n

1.E- 8

1n

1.E-09

+125°C

+85°C

+25°C

-40°C

100p

1.E-10

I_OS

-200

-400

10p

1.E-11

1p

1.E-12

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

Input Voltage (V)

Common Mode Input Voltage (V)

FIGURE 2-13:

Input Bias Current vs. Input

FIGURE 2-15:

Input Bias and Offset

Voltage (below V_SS).

Currents vs. Common-Mode Input Voltage with

T_A= +125°C.

60

40

20

0

I_B

I_OS

-20

-40

-60

Representative Part

T_A= +85°C

V_DD= 5.5V

-80

-100

-120

Common Mode Input Voltage (V)

FIGURE 2-14:

Input Bias and Offset

Currents vs. Common-Mode Input Voltage with

T_A= +85°C.

 2009-2014 Microchip Technology Inc.

DS20002194E-page 9

MCP660/1/2/3/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kto V_L, C_L= 20 pF and CS = V_SS

.

2.2

Other DC Voltages and Currents

1000

9

8

7

6

5

4

3

2

1

0

V_DD= 5.5V

100

10

1

V_DD= 2.5V

V_OL– V_SS

+125°C

+85°C

+25°C

-40°C

V_DD– V_OH

0.1

1

10

100

Power Supply Voltage (V)

Output Current Magnitude (mA)

FIGURE 2-16:

Output Voltage Headroom

FIGURE 2-19:

Supply Current vs. Power

vs. Output Current.

Supply Voltage.

45

7

6

5

R_L= 1 kΩ

40

35

V_OL– V_SS

V_DD= 5.5V

30

V_DD= 2.5V

4

3

2

1

0

25

20

15

10

5

V_DD= 2.5V

V_DD– V_OH

0

-50

-25

0

25

50

75

100

125

Common Mode Input Voltage (V)

Ambient Temperature (°C)

FIGURE 2-17:

Output Voltage Headroom

FIGURE 2-20:

Supply Current vs.

vs. Ambient Temperature.

Common-Mode Input Voltage.

100

80

60

+125°C

+85°C

+25°C

-40°C

40

20

0

-20

-40

-60

-80

-100

Power Supply Voltage (V)

FIGURE 2-18:

Output Short Circuit Current

vs. Power Supply Voltage.

DS20002194E-page 10

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kto V_L, C_L= 20 pF and CS = V_SS

.

2.3

Frequency Response

100

90

80

70

60

50

40

30

20

10

80

75

70

65

60

55

50

45

40

80

75

70

65

60

55

50

45

40

PM

V_DD= 5.5V

V_DD= 2.5V

CMRR

PSRR+

PSRR-

GBWP

100

₁1_.Ek₊₃

10k

100k

1M

10M

1.E+7

1.E+2

1.E+4

1.E+5

1.E+6

Common Mode Input Voltage (V)

Frequency (Hz)

FIGURE 2-21:

CMRR and PSRR vs.

FIGURE 2-24:

Gain-Bandwidth Product

Frequency.

and Phase Margin vs. Common-Mode Input

Voltage.

140

120

100

80

0

80

75

70

65

60

55

50

45

40

80

-30

75

70

65

60

55

50

45

40

-60

-90

PM



A_OL

V_DD= 5.5V

V_DD= 2.5V

60

-120

-150

-180

-210

-240

40

GBWP

| A_OL

|

20

0

-20

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

1

0

10 100 1k 10k100k ₁1_.M_E+10M 100M₁1_.EG₊

1.E+ 1.E+

1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+

1

2

3

4

6

7

8

9

Frequenc⁵y (Hz)

FIGURE 2-25:

Gain-Bandwidth Product

FIGURE 2-22:

Open-Loop Gain vs.

and Phase Margin vs. Output Voltage.

Frequency.

100

80

75

70

65

80

75

70

65

60

55

50

45

40

10

1

G = 101 V/V

G = 11 V/V

G = 1 V/V

PM

V_DD= 5.5V

V_DD= 2.5V

60

55

50

45

40

GBWP

0.1

10k

100k

1.0E+05

1M

10M

1.0E+07

100M

-50 -25

0

25

50

75 100 125

1.0E+04

1.0E+06

1.0E+08

Ambient Temperature (°C)

Frequency (Hz)

FIGURE 2-26:

Closed-Loop Output

FIGURE 2-23:

Gain-Bandwidth Product

Impedance vs. Frequency.

and Phase Margin vs. Ambient Temperature.

 2009-2014 Microchip Technology Inc.

DS20002194E-page 11

MCP660/1/2/3/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kto V_L, C_L= 20 pF and CS = V_SS

.

10

9

150

140

130

120

110

100

90

R_S= 0Ω

R_S= 100Ω

R_S= 1 kΩ

8

V_CM= V_DD/2

G = +1 V/V

7

G_N= 1 V/V

G_N= 2 V/V

6

G_N 4 V/V

5

4

3

2

1

0

80

70

R_S= 10 kΩ

R_S= 100 kΩ

60

50

10p

1.0E-11

100p

1.0E-10

Normalized Capacitive Load; C_L/G_N(F)

1n

1.0E-09

1k

10k

1.E+04

100k

1.E+05

1M

1.E+06

10M

1.E+07

1.E+03

Frequency (Hz)

FIGURE 2-27:

Gain Peaking vs.

FIGURE 2-28:

Channel-to-Channel

Normalized Capacitive Load.

Separation vs. Frequency.

DS20002194E-page 12

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kto V_L, C_L= 20 pF and CS = V_SS

.

2.4

Noise and Distortion

1.E+4

10µ

20

15

10

5

Representative Part

1.E+3

1µ

0

1.E+2

100n

-5

-10

-15

-20

Analog NPBW = 0.1 Hz

Sample Rate = 2 SPS

V_OS= -953 µV

1.E+1

10n

^1.E1+n⁰

0

5 10 15 20 25 30 35 40 45 50 55 60 65

0.1

1

10 100 _1.1_E+k₃10k 100k ₁1_.EM₊₆10M

1.E-1 1.E+0 1.E+1 1.E+2 1.E+4 1.E+5 1.E+7

Frequency (Hz)

Time (min)

FIGURE 2-29:

Input Noise Voltage Density

FIGURE 2-32:

Input Noise vs. Time with

vs. Frequency.

0.1 Hz Filter.

200

180

1

V_DD= 5.0V

V_OUT= 2 V_P-P

V_DD= 2.5V

160

140

120

100

80

0.1

0.01

G = 1 V/V

G = 11 V/V

BW = 22 Hz to > 500 kHz

BW = 22 Hz to 80 kHz

V_DD= 5.5V

60

0.001

0.0001

40

20

f = 100 Hz

0

100

1k

1.E+3

10k

1.E+4

100k

1.E+5

1.E+2

Frequency (Hz)

Common Mode Input Voltage (V)

FIGURE 2-30:

Input Noise Voltage Density

FIGURE 2-33:

THD+N vs. Frequency.

vs. Input Common-Mode Voltage with

f = 100 Hz.

20

18

16

0.2

0.1

0.0

0.2

0.1

0.0

Positive Video

Negative Video

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1.0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1.0

14

V_DD= 2.5V

12

10

8

V_DD= 5.5V

∆(|G|)

Representative Part

V_DD= 2.5V

V_SS= -2.5V

V

_L= 0V

6

R_L= 150Ω

Normalized to DC V_IN= 0V

NTSC

4

2



∆( G)

f = 1 MHz

0

-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8

DC Input Voltage (V)

Common Mode Input Voltage (V)

FIGURE 2-34:

Change in Gain Magnitude

FIGURE 2-31:

Input Noise Voltage Density

and Phase vs. DC Input Voltage.

vs. Input Common-Mode Voltage with f = 1 MHz.

 2009-2014 Microchip Technology Inc.

DS20002194E-page 13

MCP660/1/2/3/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kto V_L, C_L= 20 pF and CS = V_SS

.

2.5

Time Response

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

V_DD= 5.5V

G = 1

V_DD= 5.5V

G = -1

R_F= 402Ω

V_IN

V_OUT

0

20 40 60 80 100 120 140 160 180 200

Time (ns)

0

100

200

300

Time (ns)

400

500

600

FIGURE 2-35:

Non-Inverting Small Signal

FIGURE 2-38:

Inverting Large Signal Step

Step Response.

Response.

5.5

5.0

4.5

4.0

3.5

3.0

7

6

V_DD= 5.5V

G = 2

V_DD= 5.5V

G = 1

V_OUT

5

V_IN

4

3

2.5

V_IN

V_OUT

2

2.0

1.5

1.0

0.5

0.0

1

0

-1

0

100 200 300 400 500 600 700 800

Time (ns)

0

1

2

3

4

5

6

7

8

9

10

Time (µs)

FIGURE 2-36:

Non-Inverting Large Signal

FIGURE 2-39:

The MCP660/1/2/3/4/5/9

Step Response.

Family Shows No Input Phase Reversal with

Overdrive.

50

Falling Edge

V_IN

45

V_DD= 5.5V

40

35

30

V_DD= 5.5V

G = -1

R_F= 402Ω

25

V_DD= 2.5V

20

15

10

5

Rising Edge

V_OUT

0

-50

-25

0

25

50

75

100

125

0

50 100 150 200 250 300 350 400 450 500

Time (ns)

Ambient Temperature (°C)

FIGURE 2-40:

Slew Rate vs. Ambient

FIGURE 2-37:

Inverting Small Signal Step

Temperature.

Response.

DS20002194E-page 14

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kto V_L, C_L= 20 pF and CS = V_SS

.

10

V_DD= 5.5V

V_DD= 2.5V

1

0.1

100k

1M

1.E+06

10M

1.E+07

100M

1.E+08

1.E+05

Frequency (Hz)

FIGURE 2-41:

Maximum Output Voltage

Swing vs. Frequency.

 2009-2014 Microchip Technology Inc.

DS20002194E-page 15

MCP660/1/2/3/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kto V_L, C_L= 20 pF and CS = V_SS

.

2.6

Chip Select Response

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

CS = V_DD

V_DD= 5.5V

V_DD= 2.5V

-50

-25

0

25

50

75

100

125

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

Ambient Temperature (°C)

FIGURE 2-42:

CS Current vs. Power

FIGURE 2-45:

CS Hysteresis vs. Ambient

Supply Voltage.

Temperature.

3.0

5

4

3

2

1

0

V_DD= 2.5V

G = 1

2.5

V_L= 0V

CS

2.0

1.5

1.0

0.5

V_DD= 2.5V

V_OUT

On

V_DD= 5.5V

0.0

Off

-0.5

-50

-25

0

25

50

75

100

125

0

2

4

6

8

10 12 14 16 18 20

Time (µs)

Ambient Temperature (°C)

FIGURE 2-43:

CS and Output Voltages vs.

FIGURE 2-46:

CS Turn-On Time vs.

Time with V_DD= 2.5V.

Ambient Temperature.

6

8

V_DD= 5.5V

G = 1

_L= 0V

Representative Part

CS

7

6

5

4

3

2

1

0

5

4

V

3

V_OUT

2

On

1

0

Off

-1

-50

-25

0

25

50

75

100

125

0

1

2

3

4

5

6

7

8

9

10

Time (µs)

Ambient Temperature (°C)

FIGURE 2-44:

CS and Output Voltages vs.

FIGURE 2-47:

CS’s Pull-Down Resistor

Time with V_DD= 5.5V.

(R_PD) vs. Ambient Temperature.

DS20002194E-page 16

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +2.5V to 5.5V, V_SS= GND, V_CM= V_DD/3, V_OUT= V_DD/2,

V_L= V_DD/2, R_L= 1 kto V_L, C_L= 20 pF and CS = V_SS

.

0.0

1.E-016µ

CS = V_DD= 5.5V

CS = V_DD

-0.2

-0.4

-0.6

-0.8

-1.0

100n

1.E-07

+125°C

+85°C

10n

1.E-08

-1.2

-1.4

-1.6

-1.8

-2.0

1n

1.E-09

+125°C

+85°C

+25°C

-40°C

100p

1.E-10

+25°C

10p

1.E-11

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Output Voltage (V)

Power Supply Voltage (V)

FIGURE 2-48:

Shutdown vs. Power Supply Voltage.

Quiescent Current in

FIGURE 2-49:

Output Voltage.

Output Leakage Current vs.

 2009-2014 Microchip Technology Inc.

DS20002194E-page 17

MCP660/1/2/3/4/5/9

NOTES:

DS20002194E-page 18

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

3.1

Analog Outputs

3.4

Chip Select Digital Input (CS)

The analog output pins (V_OUT) are low-impedance

voltage sources.

The input (CS) is a CMOS, Schmitt-triggered input that

places the part into a low-power mode of operation.

3.2

Analog Inputs

3.5

Exposed Thermal Pad (EP)

The non-inverting and inverting inputs (V_IN+, V_IN-, …)

are high-impedance CMOS inputs with low bias

currents.

There is an internal connection between the exposed

thermal pad (EP) and the V_SSpin; they must be

connected to the same potential on the printed circuit

board (PCB).

3.3

Power Supply Pins

This pad can be connected to a PCB ground plane to

provide a larger heat sink. This improves the package

thermal resistance (_JA).

The positive power supply (V_DD) is 2.5V to 5.5V higher

than the negative power supply (V_SS). For normal

operation, the other pins are between V_SSand V_DD

.

Typically, these parts are used in a single (positive)

supply configuration. In that case, V_SSis connected to

Ground and V_DDis connected to the supply. V_DDwill

need bypass capacitors.

DS20002194E-page 20

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

When implemented as shown, resistors R₁and R₂also

limit the current through D₁and D₂.

4.0

APPLICATIONS

The MCP660/1/2/3/4/5/9 family is manufactured using

the Microchip state-of-the-art CMOS process. It is

designed for low-cost, low-power and high-speed

applications. Its low supply voltage, low quiescent

V_DD

current

MCP660/1/2/3/4/5/9

applications.

and

wide

bandwidth

ideal for

make

battery-powered

the

D₁

R₁

D₂

MCP66X

V₁

V₂

V_OUT

4.1

Input

PHASE REVERSAL

R₂

4.1.1

V_SS– minimum expected V₁

The input devices are designed to not exhibit phase

inversion when the input pins exceed the supply

voltages. Figure 2-39 shows an input voltage

exceeding both supplies with no phase inversion.

R₁ ------------------------------------------------------------------------

2 mA

V_SS– minimum expected V₂

R₂ ------------------------------------------------------------------------

2 mA

4.1.2

INPUT VOLTAGE AND CURRENT

LIMITS

FIGURE 4-2:

Inputs.

Protecting the Analog

The electrostatic discharge (ESD) protection on the

inputs can be depicted as shown in Figure 4-1. This

structure was chosen to protect the input transistors

and to minimize input bias current (I_B). The input ESD

diodes clamp the inputs when they try to go more than

one diode drop below V_SS. They also clamp any

voltages that go too far above V_DD; their breakdown

voltage is high enough to allow normal operation and

low enough to bypass quick ESD events within the

specified limits.

It is also possible to connect the diodes to the left of the

resistors R₁and R₂. If so, the currents through the

diodes D₁and D₂need to be limited by some other

mechanism. The resistors then serve as in-rush current

limiters; the DC current into the input pins (V_IN+ and

V_IN-) should be very small.

A significant amount of current can flow out of the

inputs (through the ESD diodes) when the

common-mode voltage (V_CM) is below ground (V_SS);

see Figure 2-13. Applications that are high-impedance

may need to limit the usable voltage range.

Bond

V_DD

4.1.3

NORMAL OPERATION

Pad

The input stage of the MCP660/1/2/3/4/5/9 op amps

uses a differential PMOS input stage. It operates at low

common-mode input voltages (V_CM), with V_CM

between V_SS– 0.3V and V_DD– 1.3V. To ensure proper

operation, the input offset voltage (V_OS) is measured at

both V_CM= V_SS– 0.3V and V_CM= V_DD– 1.3V. See

Figures 2-5 and 2-6 for temperature effects.

Bond

Pad

Bond

Pad

Input

Stage

V_IN+

V_IN-

Bond

Pad

When operating at very low non-inverting gains, the

output voltage is limited at the top by the V_CMrange

(< V_DD– 1.3V); see Figure 4-3.

V_SS

FIGURE 4-1:

Simplified Analog Input ESD

V_DD

Structures.

MCP66X

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the currents

(and voltages) at the input pins (see Section 1.1

“Absolute Maximum Ratings †”). Figure 4-2 shows

the recommended approach to protecting these inputs.

V_IN

+

-

V_OUT

V_SS V_IN

The internal ESD diodes prevent the input pins (V_IN+

and V_IN-) from going too far below ground, while the

resistors R₁and R₂limit the possible current drawn out

of the input pins. Diodes D₁and D₂prevent the input

pins (V_IN+ and V_IN-) from going too far above V_DDand

V_OUT V_DD– 1.3V

FIGURE 4-3:

Unity-Gain Voltage

Limitations for Linear Operation.

dump any currents onto V_DD

.

 2009-2014 Microchip Technology Inc.

DS20002194E-page 21

MCP660/1/2/3/4/5/9

Figure 4-5 shows the power calculations used for a

single op amp:

4.2

Rail-to-Rail Output

4.2.1

MAXIMUM OUTPUT VOLTAGE

• R_SERis 0 in most applications and can be used

to limit I_OUT

.

The Maximum Output Voltage (see Figures 2-16

and 2-17) describes the output range for a given load.

For example, the output voltage swings to within 50 mV

of the negative rail with a 1 k load tied to V_DD/2.

• V_OUTis the op amp’s output voltage.

• V_Lis the voltage at the load.

• V_LGis the load’s ground point.

• V_SSis usually ground (0V).

4.2.2

OUTPUT CURRENT

The input currents are assumed to be negligible. The

currents shown in Figure 4-5 can be approximated

using Equation 4-1:

Figure 4-4 shows the possible combinations of output

voltage (V_OUT) and output current (I_OUT), when

V_DD= 5.5V.

I_OUTis positive when it flows out of the op amp into the

external circuit.

EQUATION 4-1:

V_OUT– V_LG

I_OUT= I_L= -----------------------------

R

_SER+ R_L

6.0

5.5

V_OHLimited

I_DD I_Q+ max0, I_OUT



(V_DD= 5.5V)

5.0

4.5

R_L= 1 kΩ

I_SS –I_Q+ min0, I_OUT



4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

-0.5

R_L= 100Ω

R_L= 10Ω

Where:

I_Q= Quiescent supply current

The instantaneous op amp power (P_OA(t)), R_SERpower

(P_RSER(t)) and load power (P_L(t)) are calculated in

Equation 4-2:

V_OLLimited

I_OUT(mA)

EQUATION 4-2:

FIGURE 4-4:

Output Current.

P_OA(t) = I_DD(V_DD– V_OUT) + I_SS(V_SS– V_OUT

)

2

4.2.3 POWER DISSIPATION

P_RSER(t) = I_OUTR_SER

P_L(t) = I_L²R_L

Since the output short circuit current (I_SC) is specified

at ±90 mA (typical), these op amps are capable of both

delivering and dissipating significant power.

The maximum op amp power, for resistive loads,

occurs when V_OUTis halfway between V_DDand V_LGor

halfway between V_SSand V_LG

.

V_DD

EQUATION 4-3:

V_OUT

I_DD

max²V_DD– V_LG– V_SS



I_OUT

R_SER

P_OAmax ------------------------------------------------------------

4R_SER+ R_L

+

V_L

MCP66X

-

I_L

The maximum ambient to junction temperature rise

(T_JA) and junction temperature (T_J) can be calculated

using P_OAmax, the ambient temperature (T_A), the

R_L

I_SS

V_LG

V_SS

package thermal resistance (_JA, found in the

Temperature Specifications table) and the number of

op amps in the package (assuming equal power

dissipations), as shown in Equation 4-4:

FIGURE 4-5:

Calculations.

Diagram for Power

EQUATION 4-4:

T_JA= P_OAt_JA nP_OAmax_JA

T_J= T_A+ T_JA

Where:

n = Number of op amps in the package (1, 2)

DS20002194E-page 22

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

The power derating across temperature for an op amp

in a particular package can be easily calculated

(assuming equal power dissipations):

4.4

4.4.1

Improving Stability

CAPACITIVE LOADS

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the phase margin (stability) of

the feedback loop decreases and the closed-loop

bandwidth is reduced. This produces gain peaking in

the frequency response, with overshoot and ringing in

the step response. A unity-gain buffer (G = +1) is the

most sensitive to capacitive loads, though all gains

show the same general behavior.

EQUATION 4-5:

T_Jmax– T_A

P_OAmax --------------------------

n_JA

Where:

T_Jmax= Absolute maximum junction temperature

Several techniques are available to reduce T_JAfor a

When driving large capacitive loads with these op

amps (e.g., > 20 pF when G = +1), a small series

resistor at the output (R_ISOin Figure 4-6) improves the

phase margin of the feedback loop by making the

output load resistive at higher frequencies. The

bandwidth will generally be lower than bandwidth

without the capacitive load.

given P_OAmax

:

• Lower _JA

- Use another package

- PCB layout (ground plane, etc.)

- Heat sinks and air flow

• Reduce P_OAmax

- Increase R_L

R_ISO

C_L

R_G

R_F

- Limit I_OUT(using R_SER

)

V_OUT

- Decrease V_DD

-

+

4.3

Distortion

MCP66X

R_N

Differential gain (DG) and differential phase (DP) refer

to the nonlinear distortion produced by an NTSC or a

phase-alternating line (PAL) video component. The AC

Electrical Specifications table and Figure 2-34 show

the typical performance of the MCP661, configured as

a gain of +2 amplifier (see Figure 4-10), when driving

one back-matched video load (150, for 75 cable).

Microchip tests use a sine wave at NTSC’s color

sub-carrier frequency of 3.58 MHz, with a 0.286V_P-P

magnitude. The DC input voltage is changed over a

+0.7V range (positive video) or a -0.7V range (negative

video).

FIGURE 4-6:

Stabilizes Large Capacitive Loads.

Output Resistor, R_ISO

,

Figure 4-7 gives recommended R_ISOvalues for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (C_L/G_N), where G_Nis the

circuit’s noise gain. For non-inverting gains, G_Nand the

Signal Gain are equal. For inverting gains, G_Nis

1 + |Signal Gain| (e.g., -1 V/V gives G_N= +2 V/V).

100

DG is the peak-to-peak change in the AC gain

magnitude (color hue), as the DC level (luminance) is

changed, in percentile units (%). DP is the

peak-to-peak change in the AC gain phase (color

saturation), as the DC level (luminance) is changed, in

degree (°) units.

10

G_N= +1



G_N+2

1

10p

100p

1.E-10

1n

1.E-09

10n

1.E-08

1.E-11

Normalized Capacitance; C_L/G_N(F)

FIGURE 4-7:

Recommended R_ISOValues

for Capacitive Loads.

After selecting R_ISOfor the circuit, double-check the

resulting frequency response peaking and step

response overshoot. Modify the value of R_ISOuntil the

response is reasonable. Bench evaluation and

simulations with the MCP660/1/2/3/4/5/9 SPICE macro

model are helpful.

 2009-2014 Microchip Technology Inc.

DS20002194E-page 23

MCP660/1/2/3/4/5/9

Figures 2-35 and 2-36 show the small signal and large

signal step responses at G = +1 V/V. The unity-gain

buffer usually has R_F= 0 and R_Gopen.

4.4.2

GAIN PEAKING

Figure 4-8 shows an op amp circuit that represents

non-inverting amplifiers (V_Mis a DC voltage and V_Pis

the input) or inverting amplifiers (V_Pis a DC voltage

and V_Mis the input). The capacitances C_Nand C_G

represent the total capacitance at the input pins; they

include the op amp’s common-mode input capacitance

(C_CM), board parasitic capacitance and any capacitor

placed in parallel.

Figures 2-37 and 2-38 show the small signal and large

signal step responses at G = -1 V/V. Since the noise

gain is 2 V/V and C_G 10 pF, the resistors were

chosen to be R_F= R_G= 401 and R_N= 200.

It is also possible to add a capacitor (C_F) in parallel with

R_Fto compensate for the destabilizing effect of C_G.

This makes it possible to use larger values of R_F. The

conditions for stability are summarized in Equation 4-6.

C_N

R_N

EQUATION 4-6:

MCP66X

+

V_P

Given:

V_OUT

R_F

-

G_N1= 1 + ------

R_G

V_M

C_G

R_G

R_F

G_N2= 1 + ------

C_F

C_G

1

f_F= --------------------

2R_FC_F

FIGURE 4-8:

Capacitance.

Amplifier with Parasitic

G_N1







f_Z= f ---------

^F

G_N2

C_Gacts in parallel with R_G(except for a gain of +1 V/V),

which causes an increase in gain at high frequencies.

C_Galso reduces the phase margin of the feedback

loop, which becomes less stable. This effect can be

reduced by either reducing C_Gor R_F.

We need:

f_GBWP

f  --------------- ,

G_N1 G_N2

F

2G_N2

f_GBWP

C_Nand R_Nform a low-pass filter that affects the signal

at V_P. This filter has a single real pole at 1/(2R_N/C_N).

G

_N1 G_N2

f_F --------------- ,

4G_N1

The largest value of R_Fthat should be used depends

on the noise gain (see G_Nin Section 4.4.1

“Capacitive Loads”), C_Gand the open-loop gain’s

phase shift. Figure 4-9 shows the maximum

recommended R_Ffor several C_Gvalues. Some

applications may modify these values to reduce either

output loading or gain peaking (step response

overshoot).

1.E+05

100k

G_N> +1 V/V

C_G= 10 pF

C_G= 32 pF

C_G= 100 pF

C_G= 320 pF

C_G= 1 nF

10k

1.E+04

1k

1.E+03

100

1.E+02

1

10

100

Noise Gain; G_N(V/V)

FIGURE 4-9:

Maximum Recommended

R_Fvs. Gain.

DS20002194E-page 24

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

4.5

MCP663 and MCP665 Chip Select

4.7

High Speed PCB Layout

The MCP663 is a single amplifier with Chip Select

(CS). When CS is pulled high, the supply current drops

These op amps are fast enough that a little extra care

in the printed circuit board (PCB) layout can make a

significant difference in performance. Good PC board

layout techniques will help you achieve the

performance shown in the specifications and typical

performance curves; it will also help minimize

electromagnetic compatibility (EMC) issues.

to 1 µA (typical) and flows through the CS pin to V_SS

.

When this happens, the amplifier output is put into a

high-impedance state. By pulling CS low, the amplifier

is enabled. The CS pin has an internal 5 M (typical)

pulldown resistor connected to V_SS, so it will go low if

the CS pin is left floating. Figures 1-1, 2-43 and 2-44

show the output voltage and supply current response to

a CS pulse.

Use a solid ground plane. Connect the bypass local

capacitor(s) to this plane with minimal length traces.

This cuts down inductive and capacitive crosstalk.

The MCP665 is a dual amplifier with two CS pins; CSA

controls op amp A and CSB controls op amp B. These

op amps are controlled independently, with an enabled

quiescent current (I_Q) of 6 mA/amplifier (typical) and a

disabled I_Qof 1 µA/amplifier (typical). The I_Qseen at

the supply pins is the sum of the two op amps’ I_Q; the

typical value for the I_Qof the MCP665 will be 2 µA,

6 mA or 12 mA when there are 0, 1 or 2 amplifiers

enabled, respectively.

Separate digital from analog, low-speed from

high-speed and low-power from high-power. This will

reduce interference.

Keep sensitive traces short and straight. Separate

them from interfering components and traces. This is

especially important for high-frequency (low rise time)

signals.

Sometimes, it helps to place guard traces next to victim

traces. They should be on both sides of the victim trace

and as close as possible. Connect guard traces to

ground plane at both ends and in the middle for long

traces.

4.6

Power Supply

With this family of operational amplifiers, the power

supply pin (V_DDfor single supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

for good high-frequency performance. Surface mount,

multilayer ceramic capacitors, or their equivalent,

should be used.

Use coax cables, or low inductance wiring, to route

signal and power to and from the PCB. Mutual and self

inductance of power wires is often a cause of crosstalk

and unusual behavior.

These op amps require a bulk capacitor (i.e., 2.2 µF or

larger) within 50 mm to provide large, slow currents.

Tantalum capacitors, or their equivalent, may be a good

choice. This bulk capacitor can be shared with other

nearby analog parts as long as crosstalk through the

power supplies does not prove to be a problem.

 2009-2014 Microchip Technology Inc.

DS20002194E-page 25

MCP660/1/2/3/4/5/9

4.8.3

H-BRIDGE DRIVER

4.8

Typical Applications

Figure 4-12 shows the MCP662 dual op amp used as

an H-bridge driver. The load could be a speaker or a

DC motor.

4.8.1

50 LINE DRIVER

Figure 4-10 shows the MCP661 driving a 50 line. The

large output current (e.g., see Figure 2-18) makes it

possible to drive a back-matched line (R_M2, the 50

line and the 50 load at the far end) to more than ±2V

(the load at the far end sees ±1V). It is worth

mentioning that the 50 line and the 50 load at the far

end together can be modeled as a simple 50 resistor

to ground.

½ MCP662

V_IN

+

-

V_OT

R_F

R_L

R_GT

R_GB

50

Line

+2.5V

+

MCP66X

V_OB

R_M1

-

R_M2

-

49.9

-2.5V

R_F

49.9

50

+

V_DD/2

½ MCP662

R_G

301

FIGURE 4-12:

H-Bridge Driver.

This circuit automatically makes the noise gains (G_N)

equal, when the gains are set properly, so that the

frequency responses match well (in magnitude and in

phase). Equation 4-7 shows how to calculate R_GTand

R_GBso that both op amps have the same DC gains;

FIGURE 4-10:

50 Line Driver.

The output headroom limits would be V_OL= -2.3V and

V_OH= +2.3V (see Figure 2-16), leaving some design

room for the ±2V signal. The open-loop gain (A_OL

)

G_DMneeds to be selected first.

typically does not decrease significantly with a 100

load (see Figure 2-11). The maximum power dissipated

is about 48 mW (see Section 4.2.3 “Power

Dissipation”), so the temperature rise (for the

MCP661 in the SOIC-8 package) is under 8°C.

EQUATION 4-7:

V_OT– V_OB

G_DM --------------------------  1 V /V

V_DD

V

_IN– ----------

2

4.8.2

OPTICAL DETECTOR AMPLIFIER

R_F

Figure 4-11 shows a transimpedance amplifier, using

the MCP661 op amp, in a photo detector circuit. The

photo detector is a capacitive current source. R_F

provides enough gain to produce 10 mV at V_OUT. C_F

stabilizes the gain and limits the transimpedance

bandwidth to about 1.1 MHz. The parasitic capacitance

of R_F(e.g., 0.2 pF for a 0805 SMD) acts in parallel with

C_F.

R_GT= --------------------

G_DM

----------- – 1

2

R_F

R_GB= -----------

G_DM

-----------

2

Equation 4-8 gives the resulting common-mode and

differential mode output voltages.

C_F

1.5 pF

EQUATION 4-8:

Photo

Detector

V_OT+ V_OB

V_DD

R_F

--------------------------- = ----------

2

100 k

V_OUT

V_DD

 

V_IN– ----------

V_OT– V_OB= G

I_D

100 nA

C_D

30 pF

^DM



2

-

+

MCP661

V_DD/2

FIGURE 4-11:

Transimpedance Amplifier

for an Optical Detector.

DS20002194E-page 26

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

5.4

Analog Demonstration and

Evaluation Boards

5.0

DESIGN AIDS

Microchip provides the basic design aids needed for

the MCP660/1/2/3/4/5/9 family of op amps.

Microchip offers

a

broad spectrum of analog

demonstration and evaluation boards that are

designed to help customers achieve faster time to

market. For a complete listing of these boards and their

corresponding user’s guides and technical information,

5.1

SPICE Macro Model

The latest SPICE macro model for the

MCP660/1/2/3/4/5/9 op amps is available on the

Microchip web site at www.microchip.com. This model

is intended to be an initial design tool that works well in

the linear region of operation over the temperature

range of the op amp. See the model file for information

on its capabilities.

visit

the

Microchip

web

site

at

www.microchip.com/analog tools.

Some boards that are especially useful are:

• MCP6XXX Amplifier Evaluation Board 1,

part number: MCP6XXXEV-AMP1

• MCP6XXX Amplifier Evaluation Board 2,

part number: MCP6XXXEV-AMP2

Bench testing is a very important part of any design and

cannot be replaced with simulations. Also, simulation

results using this macro model need to be validated, by

comparing them to the data sheet specifications and

characteristic curves.

• MCP6XXX Amplifier Evaluation Board 3,

part number: MCP6XXXEV-AMP3

• MCP6XXX Amplifier Evaluation Board 4,

part number: MCP6XXXEV-AMP4

®

5.2

FilterLab Software

• Active Filter Demo Board Kit,

part number: MCP6XXXDM-FLTR

Microchip’s FilterLab^®software is an innovative

software tool that simplifies analog active filter (using

op amps) design. Available at no cost from the

Microchip web site at www.microchip.com/filterlab, the

FilterLab design tool provides full schematic diagrams

of the filter circuit with component values. It also

outputs the filter circuit in SPICE format, which can be

used with the macro model to simulate actual filter

performance.

• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation

Board, part number: SOIC8EV

• MCP661 Line Driver Demo Board,

part number: MCP661DM-LD

5.5

Design and Application Notes

The following Microchip Analog Design Note and

Application Notes are recommended as supplemental

reference resources. They are available on the

Microchip web site at www.microchip.com/appnotes.

5.3

Microchip Advanced Part Selector

(MAPS)

• ADN003: “Select the Right Operational Amplifier

for your Filtering Circuits”, DS21821

MAPS is a software tool that helps efficiently identify

Microchip devices that fit particular design

a

• AN722: “Operational Amplifier Topologies and DC

Specifications”, DS00722

requirement. Available at no cost from the Microchip

web site at www.microchip.com/maps, the MAPS is an

overall selection tool for Microchip’s product portfolio

that includes Analog, Memory, MCUs and DSCs. Using

this tool, a filter can be defined to sort features for a

parametric search of device and export side-by-side

technical comparison reports. Helpful links are also

provided for data sheets, purchase and sampling of

Microchip parts.

• AN723: “Operational Amplifier AC Specifications

and Applications”, DS00723

• AN884: “Driving Capacitive Loads With Op

Amps”, DS00884

• AN990: “Analog Sensor Conditioning Circuits –

An Overview”, DS00990

• AN1228: “Op Amp Precision Design: Random

Noise”, DS01228

Some of these application notes, and others, are listed

in the “Signal Chain Design Guide”, DS21825.

 2009-2014 Microchip Technology Inc.

DS20002194E-page 27

MCP660/1/2/3/4/5/9

NOTES:

DS20002194E-page 28

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

6.0

6.1

PACKAGING INFORMATION

Package Marking Information

Example

YX25

5-Lead SOT-23 (MCP661)

XXNN

6-Lead SOT-23 (MCP663)

Example

JE25

XXNN

8-Lead TDFN (2x3x0.75 mm) (MCP661)

Example

ABJ

423

25

8-Lead DFN (3x3x0.9 mm) (MCP662)

Example

DABQ

1423

256

Device

Code

MCP662T-E/MF

DABQ

Note 1: Applies to 8-lead 3x3 DFN

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC^®designator for Matte Tin (Sn)

e

3

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2009-2014 Microchip Technology Inc.

DS20002194E-page 29

MCP660/1/2/3/4/5/9

8-Lead MSOP (3x3 mm) (MCP662)

Example

662E

423256

8-Lead SOIC (3.90 mm) (MCP661, MCP662, MCP663)

Example

MCP661E

SN^^1423

e3

256

NNN

10-Lead DFN (3x3x0.9 mm) (MCP665)

Example

BAFD

1423

256

Device

Code

MCP665T-E/MF

BAFD

Note 1: Applies to 10-lead 3x3 DFN

10-Lead MSOP (3x3 mm) (MCP665)

Example

665EUN

423256

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC^®designator for Matte Tin (Sn)

e

3

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS20002194E-page 30

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

14-Lead SOIC (3.90 mm) (MCP660, MCP664)

Example

MCP660

e

3

E/SL^^

1423256

14-Lead TSSOP (4.4 mm) (MCP660, MCP664)

Example

XXXXXXXX

YYWW

664E/ST

14/23

256

NNN

16-Lead QFN (4x4x0.9 mm) (MCP669)

Example

PIN 1

669

e

3

E/ML^^

1423256

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC^®designator for Matte Tin (Sn)

e

3

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2009-2014 Microchip Technology Inc.

DS20002194E-page 31

MCP660/1/2/3/4/5/9

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L1

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ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉꢮꢃꢄꢃꢍꢇ

ꢕꢭꢰ

ꢰꢱꢕ

ꢕꢛꢲ

ꢰꢐꢄꢳꢅꢓꢉꢈꢑꢉꢪꢃꢆꢇꢰ

ꢮꢅꢊꢋꢉꢪꢃꢍꢎꢒ

ꢟ

ꢅ

ꢗꢁꢴꢟꢉꢠꢜꢡ

ꢱꢐꢍꢇꢃꢋꢅꢉꢮꢅꢊꢋꢉꢪꢃꢍꢎꢒ

ꢱꢥꢅꢓꢊꢏꢏꢉꢵꢅꢃꢚꢒꢍ

ꢕꢈꢏꢋꢅꢋꢉꢪꢊꢎꢨꢊꢚꢅꢉꢣꢒꢃꢎꢨꢆꢅꢇꢇ

ꢜꢍꢊꢆꢋꢈꢑꢑ

ꢱꢥꢅꢓꢊꢏꢏꢉꢹꢃꢋꢍꢒ

ꢕꢈꢏꢋꢅꢋꢉꢪꢊꢎꢨꢊꢚꢅꢉꢹꢃꢋꢍꢒ

ꢱꢥꢅꢓꢊꢏꢏꢉꢮꢅꢆꢚꢍꢒ

ꢧꢈꢈꢍꢉꢮꢅꢆꢚꢍꢒ

ꢧꢈꢈꢍꢔꢓꢃꢆꢍ

ꢧꢈꢈꢍꢉꢛꢆꢚꢏꢅ

ꢮꢅꢊꢋꢉꢣꢒꢃꢎꢨꢆꢅꢇꢇ

ꢮꢅꢊꢋꢉꢹꢃꢋꢍꢒ

ꢅꢀ

ꢛ

ꢛꢘ

ꢛꢀ

ꢌ

ꢌꢀ

ꢂ

ꢮ

ꢀꢁꢴꢗꢉꢠꢜꢡ

ꢗꢁꢴꢗ

ꢗꢁꢷꢴ

ꢗꢁꢗꢗ

ꢘꢁꢘꢗ

ꢀꢁꢸꢗ

ꢘꢁꢙꢗ

ꢗꢁꢀꢗ

ꢗꢁꢸꢟ

ꢗꢻ

ꢶ

ꢀꢁꢞꢟ

ꢀꢁꢸꢗ

ꢗꢁꢀꢟ

ꢸꢁꢘꢗ

ꢀꢁꢷꢗ

ꢸꢁꢀꢗ

ꢗꢁꢺꢗ

ꢗꢁꢷꢗ

ꢸꢗꢻ

ꢮꢀ

ꢀ

ꢎ

ꢳ

ꢗꢁꢗꢷ

ꢗꢁꢘꢗ

ꢗꢁꢘꢺ

ꢗꢁꢟꢀ

ꢛꢔꢊꢃꢉꢜ

ꢀꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢇꢉꢂꢉꢊꢆꢋꢉꢌꢀꢉꢋꢈꢉꢆꢈꢍꢉꢃꢆꢎꢏꢐꢋꢅꢉꢄꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢁꢉꢕꢈꢏꢋꢉꢑꢏꢊꢇꢒꢉꢈꢓꢉꢔꢓꢈꢍꢓꢐꢇꢃꢈꢆꢇꢉꢇꢒꢊꢏꢏꢉꢆꢈꢍꢉꢅꢖꢎꢅꢅꢋꢉꢗꢁꢀꢘꢙꢉꢄꢄꢉꢔꢅꢓꢉꢇꢃꢋꢅꢁ

ꢘꢁ ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢃꢆꢚꢉꢊꢆꢋꢉꢍꢈꢏꢅꢓꢊꢆꢎꢃꢆꢚꢉꢔꢅꢓꢉꢛꢜꢕꢌꢉꢝꢀꢞꢁꢟꢕꢁ

ꢠꢜꢡꢢ ꢠꢊꢇꢃꢎꢉꢂꢃꢄꢅꢆꢇꢃꢈꢆꢁꢉꢣꢒꢅꢈꢓꢅꢍꢃꢎꢊꢏꢏꢤꢉꢅꢖꢊꢎꢍꢉꢥꢊꢏꢐꢅꢉꢇꢒꢈꢦꢆꢉꢦꢃꢍꢒꢈꢐꢍꢉꢍꢈꢏꢅꢓꢊꢆꢎꢅꢇꢁ

ꢕꢃꢎꢓꢈꢎꢒꢃꢔ ꢣꢅꢎꢒꢆꢈꢏꢈꢚꢤ ꢂꢓꢊꢦꢃꢆꢚ ꢡꢗꢞꢼꢗꢴꢀꢠ

DS20002194E-page 32

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc.

DS20002194E-page 33

MCP660/1/2/3/4/5/9

6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

b

4

N

E

E1

PIN 1 ID BY

LASER MARK

1

2

3

e

e1

D

c

A

φ

A2

L

A1

L1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

6

0.95 BSC

Outside Lead Pitch

Overall Height

Molded Package Thickness

Standoff

Overall Width

Molded Package Width

Overall Length

Foot Length

Footprint

Foot Angle

Lead Thickness

Lead Width

e1

A

A2

A1

E

E1

D

L

1.90 BSC

0.90

0.89

0.00

2.20

1.30

2.70

0.10

0.35

0°

–

1.45

1.30

0.15

3.20

1.80

3.10

0.60

0.80

30°

L1

I

c

b

0.08

0.20

0.26

0.51

Notes:

1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.

2. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-028B

DS20002194E-page 34

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

6-Lead Plastic Small Outline Transistor (CHY) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc.

DS20002194E-page 35

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20002194E-page 36

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc.

DS20002194E-page 37

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20002194E-page 38

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc.

DS20002194E-page 39

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20002194E-page 40

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc.

DS20002194E-page 41

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20002194E-page 42

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc.

DS20002194E-page 43

MCP660/1/2/3/4/5/9

ꢝꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢛꢖꢆMꢆꢛꢄꢓꢓꢔ"#ꢆꢙ$%&ꢆꢎꢎꢆ'ꢔꢅ*ꢆꢗꢍꢏ+,ꢚ

ꢛꢔꢊꢃꢜ ꢧꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎꢨꢊꢚꢅꢉꢋꢓꢊꢦꢃꢆꢚꢇꢩꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉꢪꢊꢎꢨꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ

ꢒꢍꢍꢔꢢꢫꢫꢦꢦꢦꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄꢫꢔꢊꢎꢨꢊꢚꢃꢆꢚ

DS20002194E-page 44

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc.

DS20002194E-page 45

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20002194E-page 46

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

ꢝꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ.ꢐꢄꢈꢆ/ꢈꢄꢊ#ꢆꢛꢔꢆꢂꢃꢄꢅꢆꢇꢄꢌ0ꢄ1ꢃꢆꢕ4ꢛꢖꢆMꢆꢘ5ꢙ5&$7ꢀꢆꢎꢎꢆ'ꢔꢅ*ꢆꢗꢒ./ꢛꢚ

ꢛꢔꢊꢃꢜ ꢧꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎꢨꢊꢚꢅꢉꢋꢓꢊꢦꢃꢆꢚꢇꢩꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉꢪꢊꢎꢨꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ

ꢒꢍꢍꢔꢢꢫꢫꢦꢦꢦꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄꢫꢔꢊꢎꢨꢊꢚꢃꢆꢚ

 2009-2014 Microchip Technology Inc.

DS20002194E-page 47

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20002194E-page 48

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc.

DS20002194E-page 49

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20002194E-page 50

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

UN

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc.

DS20002194E-page 51

MCP660/1/2/3/4/5/9

UN

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20002194E-page 52

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

10-Lead Plastic Micro Small Outline Package (UN) [MSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc.

DS20002194E-page 53

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20002194E-page 54

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc.

DS20002194E-page 55

MCP660/1/2/3/4/5/9

ꢛꢔꢊꢃꢜ ꢧꢈꢓꢉꢍꢒꢅꢉꢄꢈꢇꢍꢉꢎꢐꢓꢓꢅꢆꢍꢉꢔꢊꢎꢨꢊꢚꢅꢉꢋꢓꢊꢦꢃꢆꢚꢇꢩꢉꢔꢏꢅꢊꢇꢅꢉꢇꢅꢅꢉꢍꢒꢅꢉꢕꢃꢎꢓꢈꢎꢒꢃꢔꢉꢪꢊꢎꢨꢊꢚꢃꢆꢚꢉꢜꢔꢅꢎꢃꢑꢃꢎꢊꢍꢃꢈꢆꢉꢏꢈꢎꢊꢍꢅꢋꢉꢊꢍꢉ

ꢒꢍꢍꢔꢢꢫꢫꢦꢦꢦꢁꢄꢃꢎꢓꢈꢎꢒꢃꢔꢁꢎꢈꢄꢫꢔꢊꢎꢨꢊꢚꢃꢆꢚ

DS20002194E-page 56

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc.

DS20002194E-page 57

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20002194E-page 58

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc.

DS20002194E-page 59

MCP660/1/2/3/4/5/9

89ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ;ꢐꢄꢅꢆ/ꢈꢄꢊ#ꢆꢛꢔꢆꢂꢃꢄꢅꢆꢇꢄꢌ0ꢄ1ꢃꢆꢕ4ꢂꢖꢆMꢆ<5<5&$%ꢆꢎꢎꢆ'ꢔꢅ*ꢆꢗ;/ꢛꢚ

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D

D2

EXPOSED

PAD

e

E

E2

2

1

2

b

1

K

N

NOTE 1

L

TOP VIEW

BOTTOM VIEW

A3

A

A1

ꢬꢆꢃꢍꢇꢕꢭꢮꢮꢭꢕꢌꢣꢌꢯꢜ

ꢂꢃꢄꢅꢆꢇꢃꢈꢆꢉꢮꢃꢄꢃꢍꢇ

ꢕꢭꢰ

ꢰꢱꢕ

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ꢜꢍꢊꢆꢋꢈꢑꢑꢉ

ꢡꢈꢆꢍꢊꢎꢍꢉꢣꢒꢃꢎꢨꢆꢅꢇꢇ

ꢱꢥꢅꢓꢊꢏꢏꢉꢹꢃꢋꢍꢒ

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ꢱꢥꢅꢓꢊꢏꢏꢉꢮꢅꢆꢚꢍꢒ

ꢌꢖꢔꢈꢇꢅꢋꢉꢪꢊꢋꢉꢮꢅꢆꢚꢍꢒ

ꢡꢈꢆꢍꢊꢎꢍꢉꢹꢃꢋꢍꢒ

ꢡꢈꢆꢍꢊꢎꢍꢉꢮꢅꢆꢚꢍꢒ

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ꢞꢁꢗꢗꢉꢠꢜꢡ

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ꢘꢁꢺꢟ

ꢛ

ꢗꢁꢷꢗ

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ꢀꢁꢗꢗ

ꢗꢁꢗꢟ

ꢛꢀ

ꢛꢸ

ꢌ

ꢌꢘ

ꢂ

ꢂꢘ

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ꢮ

ꢘꢁꢟꢗ

ꢘꢁꢷꢗ

ꢘꢁꢟꢗ

ꢗꢁꢘꢟ

ꢗꢁꢸꢗ

ꢗꢁꢘꢗ

ꢘꢁꢷꢗ

ꢗꢁꢸꢟ

ꢗꢁꢟꢗ

ꢶ

ꢗꢁꢸꢗ

ꢗꢁꢞꢗ

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DS20002194E-page 60

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2009-2014 Microchip Technology Inc.

DS20002194E-page 61

MCP660/1/2/3/4/5/9

NOTES:

DS20002194E-page 62

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

Revision B (September 2011)

APPENDIX A: REVISION HISTORY

Revision E (July 2014)

The following is the list of modifications:

1. Added the MCP660, MCP664 and MCP669

amplifiers to the product family and the related

information throughout the document.

The following is the list of modifications:

1. Updated the Features: list.

2. Added the 4x4 QFN (16L) package option for

MCP660 and MCP669, SOIC and TSSOP (14L)

package options for MCP660 and MCP665 and

the related information throughout the

document. Updated the Package Types

drawing with pin designation for each new

package.

2. Updated the Typical Application Circuit and

added the High Gain-Bandwidth Op Amp

Portfolio table in the Features: section.

3. Updated Figures 4-6, 4-10 and 4-11.

4. Updated

the

Section 6.0

“Packaging

Information” and Section 6.1 “Package

Marking Information” sections.

3. Updated the Temperature Specifications table to

show the temperature specifications for new

packages.

5. Minor typographical changes.

Revision D (March 2012)

4. Updated Table 3-1 to show all the pin functions.

5. Updated

Section 6.0

“Packaging

The following is the list of modifications:

Information” with markings for the new

additions. Added the corresponding SOIC and

TSSOP (14L), and 4x4 QFN (16L) package

options and related information.

Added the MSOP (8L) package for MCP662 and

all related information throughout the document.

Revision C (November 2011)

6. Updated table description and examples in

Product Identification System.

The following is the list of modifications:

1. Added the SOT-23 (5L) and TDFN (8L) package

option for MCP661 and SOT-23 (6L) package

options for MCP663 and the related information

throughout the document. Updated Package

Types drawing with pin designation for each

new package.

Revision A (July 2009)

Original release of this document.

2. Updated the Temperature Specifications table to

show the temperature specifications for new

packages.

3. Updated Table 3-1 to show all the pin functions.

4. Updated

Section 6.0

“Packaging

Information” with markings for the new

additions. Added the corresponding SOT-23 (5L

and 6L) and 2x3 TDFN (8L) package options

and related information.

5. Updated table description and examples in the

Product Identification System section.

 2009-2014 Microchip Technology Inc.

DS20002194E-page 63

MCP660/1/2/3/4/5/9

NOTES:

DS20002194E-page 64

 2009-2014 Microchip Technology Inc.

MCP660/1/2/3/4/5/9

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

-X

/XX

a)

b)

c)

MCP660T-E/ML:

MCP660T-E/SL:

MCP660T-E/ST:

Tape and Reel

Extended temperature,

16LD QFN package

Tape and Reel

Extended temperature,

14LD SOIC package

Temperature

Range

Package

Device:

MCP660

MCP660T

Triple Op Amp

Triple Op Amp (Tape and Reel)

(SOIC, TSSOP, QFN)

Tape and Reel

Extended temperature,

14LD TSSOP package

MCP661

MCP661T

Single Op Amp

Single Op Amp (Tape and Reel)

(SOIC, SOT-23 and TDFN)

Dual Op Amp

Dual Op Amp (Tape and Reel)

(DFN, MSOP and SOIC)

Single Op Amp with CS

Single Op Amp with CS (Tape and Reel)

(SOIC and SOT-23)

d)

e)

MCP661T-E/SN:

Tape and Reel

Extended temperature,

8LD SOIC package

MCP662

MCP662T

MCP661T-E/MNY: Tape and Reel,

Extended Temperature,

MCP663

MCP663T

8LD TDFN package

MCP664

MCP664T

Quad Op Amp

Quad Op Amp (Tape and Reel)

(SOIC, TSSOP)

Dual Op Amp with CS

Dual Op Amp with CS (Tape and Reel)

(DFN and MSOP)

Quad Op Amp with CS

Quad Op Amp with CS (Tape and Reel)

(QFN)

f)

MCP662T-E/MF:

Tape and Reel

Extended temperature,

8LD DFN package

MCP665

MCP665T

g)

h)

MCP662T-E/MS: Tape and Reel

Extended temperature,

8LD MSOP package

Tape and Reel

Extended temperature,

8LD SOIC package

MCP669

MCP669T

MCP662T-E/SN:

i)

j)

MCP663T-E/SN:

Tape and Reel

Extended temperature,

8LD SOIC package

Temperature

Range:

E

= -40°C to +125°C

MCP663T-E/CHY: Tape and Reel,

Extended Temperature,

Package:

CHY = Plastic Small Outline (SOT-23), 6-lead

MF

6LD SOT-23 package

=

Plastic Dual Flat, No Lead (3×3 DFN),

8-lead, 10-lead

k)

l)

MCP664T-E/SL:

MCP664T-E/ST:

Tape and Reel

Extended temperature,

14LD SOIC package

Tape and Reel

Extended temperature,

14LD TSSOP package

ML

=

Plastic Quad Flat, No Lead Package (4x4 QFN),

(4x4x0.9 mm), 16-lead

MNY= Plastic Dual Flat, No Lead (2x3 TDFN),

8-lead

MS

OT

SL

=

Plastic Micro Small Outline (MSOP), 8-lead

Plastic Small Outline (SOT-23), 5-lead

Plastic Small Outline, Narrow, (3.90 mm SOIC),

14-lead

m) MCP665T-E/MF:

Tape and Reel

Extended temperature,

10LD DFN package

Tape and Reel

Extended temperature,

10LD MSOP package

SN

ST

=

Plastic Small Outline (3.90 mm), 8-lead

Plastic Thin Shrink Small Outline, (4.4 mm TSSOP),

14-lead

n)

o)

MCP665T-E/UN:

MCP669T-E/ML:

UN

=

Plastic Micro Small Outline (MSOP), 10-lead

* Y = Nickel palladium gold manufacturing designator.

Only available on the TDFN package.

Tape and Reel

Extended temperature,

16LD QFN package

 2009-2014 Microchip Technology Inc.

DS20002194E-page 65

MCP660/1/2/3/4/5/9

NOTES:

DS20002194E-page 66

 2009-2014 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,

LANCheck, MediaLB, MOST, MOST logo, MPLAB,

32

OptoLyzer, PIC, PICSTART, PIC logo, RightTouch, SpyNIC,

SST, SST Logo, SuperFlash and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

The Embedded Control Solutions Company and mTouch are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,

CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit

Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,

KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,

MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code

Generation, PICDEM, PICDEM.net, PICkit, PICtail,

RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total

Endurance, TSHARC, USBCheck, VariSense, ViewSpan,

WiperLock, Wireless DNA, and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

GestIC is a registered trademarks of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-63276-368-6

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

== ISO/TS 16949 ==

 2009-2014 Microchip Technology Inc.

DS20002194E-page 67

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2943-5100

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-3019-1500

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Web Address:

www.microchip.com

Japan - Osaka

Tel: 81-6-6152-7160

Fax: 81-6-6152-9310

Germany - Dusseldorf

Tel: 49-2129-3766400

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Beijing

Tel: 86-10-8569-7000

Fax: 86-10-8528-2104

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Tokyo

Tel: 81-3-6880- 3770

Fax: 81-3-6880-3771

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Austin, TX

Tel: 512-257-3370

Germany - Pforzheim

Tel: 49-7231-424750

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Boston

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

China - Hangzhou

Tel: 86-571-8792-8115

Fax: 86-571-8792-8116

Italy - Venice

Tel: 39-049-7625286

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

China - Hong Kong SAR

Tel: 852-2943-5100

Fax: 852-2401-3431

Cleveland

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

Poland - Warsaw

Tel: 48-22-3325737

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Sweden - Stockholm

Tel: 46-8-5090-4654

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Detroit

Novi, MI

Tel: 248-848-4000

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Houston, TX

Tel: 281-894-5983

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

Taiwan - Kaohsiung

Tel: 886-7-213-7830

China - Shenzhen

Tel: 86-755-8864-2200

Fax: 86-755-8203-1760

Taiwan - Taipei

Tel: 886-2-2508-8600

Fax: 886-2-2508-0102

Los Angeles

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

New York, NY

Tel: 631-435-6000

San Jose, CA

Tel: 408-735-9110

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Canada - Toronto

Tel: 905-673-0699

Fax: 905-673-6509

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

03/25/14

DS20002194E-page 68

 2009-2014 Microchip Technology Inc.


型号：	MCP662T-E/MS
厂家：	MICROCHIP
描述：	OP-AMP 放大器光电二极管
文件：	总68页 (文件大小：2605K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP662T-E/MS [MICROCHIP]

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