MCP6C04T-020E [MICROCHIP]
Zero-Drift, 52V High-Side Current Sense Amplifier;
| 型号： | MCP6C04T-020E |
| 厂家： | 
MICROCHIP |
| 描述： | Zero-Drift, 52V High-Side Current Sense Amplifier |
| 文件： | 总54页 (文件大小：2230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP6C04
Zero-Drift, 52V High-Side Current Sense Amplifier
Features
General Description
• Single Amplifier: MCP6C04
• Bidirectional or Unidirectional
• Input (Common-mode) Voltages:
- +3.0V to +52V, specified
- +2.8V to +54V, operating
- -0.3V to +56V, survival
• Power Supply:
The MCP6C04 high-side current sense amplifier is
offered with preset gains of 20, 50 and 100 V/V. The
Common-mode input range (VIP) is +3V to +52V. The
differential-mode input range (VDM = VIP – VIM
supports unidirectional and bidirectional applications.
)
The power supply can be set between 2.0V and 5.5V.
This device is specified from -40°C to +125°C
(E-Temp) and is provided in the SOT-23 package.
- 2.0V to 5.5V
The Zero-Drift architecture supports very low input
errors, that allow a design to use shunt resistors of
lower value (and lower power dissipation).
- Single or Dual (Split) Supplies
• High DC Precision:
- VOS: ±3.3 μV (typical)
Package Types
- CMRR: 150 dB (typical)
- PSRR: 127 dB (typical)
- Gain Error: ±0.2% (typical)
• Preset Gains: 20, 50 and 100 V/V
• POR Protection:
MCP6C04
6-Lead SOT-23
VOUT 1
VSS 2
VDD
VREF
VIM
6
5
4
- HV POR for VIP – VSS
- LV POR for VDD – VSS
• Bandwidth: 500 kHz (typical)
• Supply Currents:
VIP
3
- IDD = 500 μA (typical)
- IBP = 175 μA (typical)
• Enhanced EMI Protection:
- EMIRR: 118 dB at 2.4 GHz (typical)
• Extended Temperature Range (E-Temp):
- -40°C to +125°C
Typical Application Circuit
+5V
2.2 µF
Typical Applications
10 nF
U1 (DUT)
100 nF
• Actuator controls
MCP6C04-100
• Industrial control and automation
• Power management systems
• Motor control
VBAT
+36V
RSH
2.2 mΩ
VOUT
20 kΩ
• Battery monitor/tester
IL < 20A
Related Products
VL
• MCP6C02-020
• MCP6C02-050
• MCP6C02-100
2019 Microchip Technology Inc.
DS20006179A-page 1
MCP6C04
Functional Diagram
Gain Options
Table 1 shows key specifications that differentiate
VDD
between the three different differential gain (GDM
)
VOUT
RF
options. See Section 1.0 “Electrical Characteris-
tics”, Section 6.0 “Packaging Information” and
Product Identification System for further information
on the GDM options available.
VIP
RM3
GM1
Σ
I1
VFG
VIM
I2
GM2
RG
VREF
VSS
TABLE 1:
KEY DIFFERENTIATING SPECIFICATIONS
GDM
VOS
TC1
CMRR
(dB)
Min.
PSRR
(dB)
Min.
VDMH
(V)
Min.
BW
(kHz)
Typ.
Eni
(μVp-p
Typ.
eni
(nV/√Hz)
Typ.
Part No.
(V/V) (± μV) (± nV/°C)
Nom. Max.
)
Max.
MCP6C04-020
MCP6C04-050
MCP6C04-100
20
50
30
27
24
180
140
130
125
132
102
109
110
0.265
0.106
0.053
500
1.54
0.95
0.92
74
46
44
100
390
Note 1:
VOS and TC1 limits are by design and characterization only.
2: TC1 covers the extended temperature range (-40°C to +125°C).
3: CMRR is at VDD = 5.5V.
4: Eni is at f = 0.1 Hz to 10 Hz. eni is at f < 500 Hz.
DS20006179A-page 2
2019 Microchip Technology Inc.
MCP6C04
Figure 1, Figure 2 and Figure 3 show input offset
voltage versus temperature for the three gain options
(GDM = 20, 50 and 100 V/V).
The MCP6C04's CMRR supports applications in noisy
environments. Figure 4 shows how CMRR is high,
even for frequencies near 100 kHz.
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100
90
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GDM = 50
50
GDM = 20
40
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100k
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1.E+05
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FIGURE 1:
Temperature, G
Input Offset Voltage vs.
= 20 V/V.
FIGURE 4:
CMRR vs. Frequency.
DM
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FIGURE 2:
Temperature, G
Input Offset Voltage vs.
= 50 V/V.
DM
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FIGURE 3:
Input Offset Voltage vs.
Temperature, G
= 100 V/V.
DM
2019 Microchip Technology Inc.
DS20006179A-page 3
MCP6C04
NOTES:
DS20006179A-page 4
2019 Microchip Technology Inc.
MCP6C04
1.0
1.1
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
VDD – VSS .................................................................................................................................................. -0.3V to +5.5V
Current at Input Pins (Note 1).................................................................................................................................±2 mA
Analog Inputs (VIP and VIM) (Note 1).......................................................................................................... -0.3V to +56V
All Other Inputs and Outputs.....................................................................................................VSS – 0.3V to VDD + 0.3V
Input Difference Voltage (VDM) (Note 1)...................................................................................................................±1.2V
Output Short-Circuit Current ...........................................................................................................................Continuous
Current at Output and Supply Pins .......................................................................................................................±30 mA
Storage Temperature ..............................................................................................................................-65°C to +150°C
Maximum Junction Temperature........................................................................................................................... +150°C
ESD protection (HBM, CDM, MM) ....................................................................................................... ≥ 2 kV, 2 kV, 300V
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note 1: These voltage and current ratings are physically independent; each required condition must be enforced by
the user (see Section 5.1.1 “Input Voltage Limits” and Section 5.1.2 “Input Current Limits”).
1.2
Voltage and Temperature Ranges
The various voltage and temperature ranges are listed in Table 1-1.
TABLE 1-1: VOLTAGE AND TEMPERATURE RANGES
Parameter Units GDM (V/V) Comment
VDD
Range
Type Sym.
Spec.
Oper.
Abs. Min./Max.
VDD
V
V
All
All
↑
Min.
VDDL
2.0
1.7
-0.3
(Note 2)
(LV POR on)
LV POR
VPLH
–
0.1 Typ.
—
—
Hysteresis
VPLL
—
Typ.
—
2.0 to 5.5
5.5
—
—
5.5
-0.3
Max. VDDH
5.5
2.8
VIP
(Note 2)
VIP
(HV POR on)
VIP
↑
Min.
VIPL
VIPLD
VIPLH
3.0
↓
2.8
2.6
(HV POR on)
HV POR
0.2 Typ.
0.2 Typ.
—
Hysteresis
—
—
Typ.
Max.
Min.
Typ.
Max.
—
VIPH
VRL
—
27.5
52
—
—
56
54
VREF
V
All
0
0
—
-0.3
VDD/4
VDD – 1.3
—
VRH
VDD – 1.2
VDD + 0.3
Note 1: All of this table’s limits are set by design and characterization.
2: The HV POR is triggered by VIP, with hysteresis. The LV POR is triggered by VDD, with hysteresis.
3: VDM = VIP – VIM. VIM is in its range when both VIP and VDM are in their ranges.
4: Allowing the ambient temperature (TA) to exceed the maximum ambient temperature limit (TAH) may
cause parameters to exceed their specified limits. See Section 1.1 “Absolute Maximum Ratings †” for
the absolute maximum junction temperature and storage temperature limits.
5: VOL and VOH are at RL = 1 kΩ.
2019 Microchip Technology Inc.
DS20006179A-page 5
MCP6C04
TABLE 1-1:
VOLTAGE AND TEMPERATURE RANGES (CONTINUED)
Range
Parameter Units GDM (V/V)
Comment
Type Sym.
Spec.
Oper.
Abs. Min./Max.
VOUT
(Note 5)
V
V
All
—
Min.
Typ.
Max.
VOL
—
0.06 Max
0
-0.3
—
V
DD/2
—
VOH
VDD – 0.13
Min
VDD
VDD + 0.3
VDM
20
50, 100
All
—
—
Min.
VDML
-3/GDM
-4.05/GDM
0
-4.25/GDM
-1.2
Typ.
—
—
5.5/GDM
-40
—
+1.2
-40
Max. VDMH
5.3/GDM
-40
TA
°C
All
Min.
Typ.
Max.
TAL
—
25
—
—
TAH
+125
+150
+150
Note 1: All of this table’s limits are set by design and characterization.
2: The HV POR is triggered by VIP, with hysteresis. The LV POR is triggered by VDD, with hysteresis.
3: VDM = VIP – VIM. VIM is in its range when both VIP and VDM are in their ranges.
4: Allowing the ambient temperature (TA) to exceed the maximum ambient temperature limit (TAH) may
cause parameters to exceed their specified limits. See Section 1.1 “Absolute Maximum Ratings †” for
the absolute maximum junction temperature and storage temperature limits.
5: VOL and VOH are at RL = 1 kΩ.
DS20006179A-page 6
2019 Microchip Technology Inc.
MCP6C04
1.3
Specifications
TABLE 1-2:
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 27.5V,
DM = 0V, VREF = VDD/4, VL = VDD/2 and RL = 10 kΩ to VL; see Figure 1-9 and Figure 1-10.
DC ELECTRICAL CHARACTERISTICS
V
Parameter
Sym.
Min.
Typ.
Max.
Units
Gain
Conditions
Input Offset (VIP = VIM) (Note 1)
Input Offset Voltage
VOS
TC1
-30
-27
±3.8
±3.3
±3.0
±13
±11
+30
+27
μV
20
50
Note 2
-24
+24
100
20
V
V
V
OS Drift,
Linear Temp. Co.
-180
-140
-130
—
+180
+140
+130
—
nV/°C
pV/°C2
μV
TA = -40°C to +125°C
(Note 2, Note 3)
50
±10
±60
±95
±105
±0.35
±0.25
±0.2
±4
100
20
OS Drift,
Quadratic Temp. Co.
TC2
50
100
20
OS Aging
ΔVOS
ΔTC1
PSRR
—
—
—
—
—
108 hr at +150°C
(changes measured at +25°C)
50
100
20
TC1 Aging
nV/°C
dB
±2.5
±2
50
100
20
Power Supply Rejection
Ratio
102
109
110
123
129
130
VDD = 2.0V to 5.5V
50
100
Input Current and Impedance (VIP and VIM
VIP's Input Bias Current IBP 100
IM's Input Bias Current IBM
)
175
±0.2
3
240
—
μA
nA
All
VDD = 2.0V to 5.5V
VDD = 5.5V
V
—
IBM2
IBM3
CVIP
CVIM
CVDM
VDD = 5.5V, VDM = VDML
VDD = 5.5V, VDM = VDMH
-2
Capacitance at VIP
—
40
11
—
pF
Capacitance at VIM
Capacitance across VDM
12
Note 1: The VIP input is treated as the Common-mode input (e.g., for CMRR). VDM = (VIP – VIM).
2: Set by design and characterization. VOS is screened in production (see Appendix B: “Offset Test
Screens”).
3: See the discussion in Section 1.6.2, Input Offset Related Errors.
4: See Section 1.6, Explanation of DC Error Specifications.
2019 Microchip Technology Inc.
DS20006179A-page 7
MCP6C04
TABLE 1-2:
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 27.5V,
VDM = 0V, VREF = VDD/4, VL = VDD/2 and RL = 10 kΩ to VL; see Figure 1-9 and Figure 1-10.
Parameter
Sym.
Min.
Typ.
Max.
Units
Gain
Conditions
Input Common-Mode Voltage (VIP)
VIP’s Voltage Range Low
VIPL
VIPLD
VIPLH
VIPH
—
2.4
2.15
0.2
3.0
2.8
—
V
All
VIP
VIP
↑
↓
VIPLH = VIPL – VIPLD
VIP’s Voltage Range High
52
—
145
—
—
Common-Mode Rejection CMRR
Ratio
125
132
dB
20
50
VDD = 2.0V to 5.5V,
VIP = 3V to 52V
152
154
100
All
Common-Mode
INLCM
—
±0.006
—
ppm
VDD = 5.5V, VIP = 3V to 52V
Nonlinearity (Note 4)
Reference Voltage (VREF
)
Reference Voltage
Range (Note 2)
VRL
VRH
—
VDD –1.3
—
—
—
0
V
All
See Section 5.1.5, Setting
the Voltage at VREF
—
—
Gain Resistance
RF + RG
160
165
225
11
kΩ
20
50
100
All
VREF Input Capacitance
CREF
—
—
pF
Differential Input (VDM) (Note 1)
Differential Gain
GDM
20
50
V/V
20
50
MCP6C04-020
MCP6C04-050
100
—
100 MCP6C04-100
Differential Input Voltage
Range
VDML
-3/GDM
—
V
20
VDD = 5.5V, VREF = 4.1V,
VL = 0V
-4.05/GDM
50,
100
VDMH
gE
—
—
5.3/GDM
—
All
VDD = 5.5V, VREF = 0V,
VL = VDD
Differential Gain Error
±0.2
±0.2
±0.2
±0.2
±0.2
%
VDD = 2.0V, VREF = 0.5V,
GDMVDM = -0.4V to 1.4V
-1.6
—
+1.6
—
VDD = 5.5V, VREF = 2.75V,
GDMVDM = -2.65V to 2.65V
VDD = 5.5V, VREF = 0V,
GDMVDM = 0.2V to 5.3V
20
V
DD = 5.5V, VREF = 4.2V,
GDMVDM = -3V to 1.2V
DD = 5.5V, VREF = 4.2V,
50,
V
100 GDMVDM = -4V to 1.2V
Note 1: The VIP input is treated as the Common-mode input (e.g., for CMRR). VDM = (VIP – VIM).
2: Set by design and characterization. VOS is screened in production (see Appendix B: “Offset Test
Screens”).
3: See the discussion in Section 1.6.2, Input Offset Related Errors.
4: See Section 1.6, Explanation of DC Error Specifications.
DS20006179A-page 8
2019 Microchip Technology Inc.
MCP6C04
TABLE 1-2:
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 27.5V,
VDM = 0V, VREF = VDD/4, VL = VDD/2 and RL = 10 kΩ to VL; see Figure 1-9 and Figure 1-10.
Parameter
Sym.
Min.
Typ.
Max.
Units
Gain
Conditions
Differential Input (VDM) – Continued (Note 1)
Differential Gain Drift
gE Aging
ΔgE/ΔTA
—
—
—
±10
±10
±0.3
—
—
—
ppm/°C
All
VDD = 2.0V, VREF = 0.5V,
GDMVDM = -0.4V to 1.4V
VDD = 5.5V, VREF = 2.75V,
GDMVDM = -2.65V to 2.65V
ΔgE
%
408 hr at +150°C,
VDD = 5.5V, VREF = 2.75V,
GDMVDM = -2.65V to 2.65V,
(change measured at +25°C)
Differential Nonlinearity
(Note 4)
INLDM
—
—
±50
—
—
ppm
VDD = 2.0V, VREF = 0.5V,
GDMVDM = -0.4V to 1.4V
±100
VDD = 5.5V, VREF = 2.75V,
GDMVDM = -2.65V to 2.65V
Output (VOUT
)
Minimum Output
Voltage Swing
VOL
3
5
mV
All
VDD = 2.0V, VREF = 0V
VDM = -0.5V/GDM
VDD = 5.5V, VREF = 0V
VDM = -0.5V/GDM
20
3
60
—
VDD = 5.5V, VREF = 0V
VDM = -0.5V/GDM, RL = 1 kΩ
V
DD = 5.5V, VREF = 0V
VDM = -0.5V/GDM, VL = 0V
Output (VOUT) – Continued
Maximum Output
Voltage Swing
VDD
VOH
–
—
6
10
40
5
—
mV
All
VDD = 2.0V, VREF = 0.7V
VDM = 1.8V/GDM
VDD = 5.5V, VREF = 4.2V
VDM = 1.8V/GDM
130
—
VDD = 5.5V, VREF = 4.2V
VDM = 1.8V/GDM, RL = 1 kΩ
VDD = 5.5V, VREF = 0V
VDM = 1.8V/GDM, VL = VDD
Output Short Circuit
Current
ISCP
ISCM
Power Supplies (VDD, VSS and VIP)
—
—
+12
+20
-12
-20
—
VDD = 2.0V, GDMVDM = 1.0V
V
DD = 5.5V, GDMVDM = 2.75V
VDD = 2.0V, GDMVDM = 0V
DD = 5.5V, GDMVDM = 0V
—
V
Low Supply Voltage
VDD
VIP
ISS
IDD
IBP
2.0
—
(see VIP spec)
-675
5.5
V
All
High Supply Voltage
Quiescent Current at VSS
Quiescent Current at VDD
Quiescent Current at VIP
—
—
μA
IO = 0A
250
500
840
(see IBP spec)
Note 1: The VIP input is treated as the Common-mode input (e.g., for CMRR). VDM = (VIP – VIM).
2: Set by design and characterization. VOS is screened in production (see Appendix B: “Offset Test
Screens”).
3: See the discussion in Section 1.6.2, Input Offset Related Errors.
4: See Section 1.6, Explanation of DC Error Specifications.
2019 Microchip Technology Inc.
DS20006179A-page 9
MCP6C04
TABLE 1-2:
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 27.5V,
VDM = 0V, VREF = VDD/4, VL = VDD/2 and RL = 10 kΩ to VL; see Figure 1-9 and Figure 1-10.
Parameter
Sym.
Min.
Typ.
Max.
Units
Gain
Conditions
POR Trip Voltages,
VPLL
1.05
1.35
—
V
All
LV POR turns off (VDD ↓),
Low-Side (VDD
)
VL = 0V, VIP = 3V, VREF = 0V
VPLH
VPHL
—
1.45
1.95
1.7
—
LV POR turns on (VDD ↑),
VL = 0V, VIP = 3V, VREF = 0V
POR Trip Voltages,
High-Side (VIP)
1.7
HV POR turns off (VIP ↓),
RL = open, VDD = 5.5V
(change in ISS
)
VPHH
—
2.05
2.6
HV POR turns on (VIP ↑),
RL = open, VDD = 5.5V
(change in ISS
)
Note 1: The VIP input is treated as the Common-mode input (e.g., for CMRR). VDM = (VIP – VIM).
2: Set by design and characterization. VOS is screened in production (see Appendix B: “Offset Test
Screens”).
3: See the discussion in Section 1.6.2, Input Offset Related Errors.
4: See Section 1.6, Explanation of DC Error Specifications.
TABLE 1-3:
AC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 27.5V,
VDM = 0V, VREF = VDD/4, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF; see Figure 1-11.
Parameter
AC Response
Sym.
Min. Typ. Max. Units
Gain
Conditions
Bandwidth
BW
—
—
500
390
0
—
—
kHz
dB
20, 50 GDMVDM = 0.1Vp-p
100
All
Gain Peaking
GPK
Step Response
V
DM Slew Rate
SR
(Note 1)
4
V/μs
%
All
20
GDMVDM Step = VDD – 0.5V
VDM Step Overshoot
OSDM
—
—
—
—
GDMVDM Step = 0.1V, tr_in = 0.2 μs
Overdrive Recovery,
tIRDL
3
μs
VDD = 5.5V, VREF = 4V,
GDMVDM = -3.5V to -1.25V Step,
90% of VOUT change
Input Differential Mode
(see tORL Spec)
50, 100 (Note 2)
tIRDH
—
3
—
All VDD = 5.5V, VREF = 0.5V,
GDMVDM = +4.5V to +2.25V Step,
90% of VOUT change
Note 1: SR is limited by GBWP; the large signal step response is dominated by the small signal bandwidth.
2: At these gains, we cannot distinguish between overdriving VDM or VOUT
3: See Figure 2-47 for the noise density over a wider frequency range.
.
DS20006179A-page 10
2019 Microchip Technology Inc.
MCP6C04
TABLE 1-3:
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 27.5V,
VDM = 0V, VREF = VDD/4, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF; see Figure 1-11.
Parameter
Sym.
Min. Typ. Max. Units
Gain
Conditions
Overdrive Recovery,
Output
tORL
—
1.5
1.5
1.5
1.5
—
μs
All
VDD = 2.0V, VREF = 0V,
GDMVDM = -0.5V to +1V Step,
90% of VOUT change
VDD = 5.5V, VREF = 0V,
GDMVDM = -0.5V to +2.75V Step,
90% of VOUT change
tORH
—
—
VDD = 2.0V, VREF = 0.7V,
GDMVDM = +1.8V to +0.3V Step,
90% of VOUT change
VDD = 5.5V, VREF = 4.2V,
GDMVDM = +1.8V to -1.2V Step,
90% of VOUT change
Noise
Input Noise Voltage
Eni
—
—
—
0.48
0.30
0.29
1.54
0.95
0.92
74
—
—
—
μVp-p
20
50
f = 0.01 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
f < 500 Hz
100
20
50
100
20
Input Noise Voltage
Density (Note 3)
eni
nV/√Hz
46
50
44
100
All
f < 1 kHz
f = 1 kHz
Input Current Noise
Density – At VIP
inip
—
—
10
—
—
pA/√Hz
fA/√Hz
Input Current Noise
Density – At VIM
inim
8
f = 1 kHz, VDM = 0V
33
f = 1 kHz, VDM = 0.15V
EMI Protection
EMI Rejection Ratio
EMIRR
—
96
91
—
dB
All
All
VIN = 0.1VPK, f = 400 MHz
V
V
IN = 0.1VPK, f = 900 MHz
IN = 0.1VPK, f = 1800 MHz
114
118
121
VIN = 0.1VPK, f = 2400 MHz
IN = 0.1VPK, f = 6000 MHz
V
Power Up/Down
Power On Time (VDD ↑),
VOUT Settles
tPON
—
—
65
140
8
—
—
μs
VDD = 0V to 2.0V, VL = 0V,
90% of VOUT change
V
DD = 0V to 5.5V, VL = 0V,
90% of VOUT change
Power Off Time (VDD ↓),
VOUT Settles
tPOFF
VDD = 2.0V to 0V, VL = 0V,
90% of VOUT change
5.5
VDD = 5.5V to 0V, VL = 0V,
90% of VOUT change
Note 1: SR is limited by GBWP; the large signal step response is dominated by the small signal bandwidth.
2: At these gains, we cannot distinguish between overdriving VDM or VOUT
3: See Figure 2-47 for the noise density over a wider frequency range.
.
2019 Microchip Technology Inc.
DS20006179A-page 11
MCP6C04
TABLE 1-4:
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 2.0V to 5.5V, VSS = GND and
VIP = 27.5V.
Parameters
Sym. Min.
Typ.
Max. Units
Conditions
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Resistance, 6L-SOT-23
TA
-40
-40
-60
—
—
—
+125
+150
+150
—
°C
Note 1
—
No power
θJA
191
°C/W
Note 1: Operation must not cause TJ to exceed the absolute maximum junction temperature specification, which is
150°C. See Section 4.1.5, Temperature Performance for design tips.
1.4.2
TIMING DIAGRAMS
1.4
Simplified Diagrams
1.4.1
VOLTAGE RANGE DIAGRAMS
VDM
±(1V)/GDM
These ranges are constant across temperature.
VIP
tIRC
VIP Range (V)
VOUT
VIPH – VSS
FIGURE 1-4:
Common-Mode Input
Overdrive Recovery Timing Diagram.
VIPL – VSS
VIP
-40
25
85
125 150
27.5V
VDM
TA (°C)
Common-Mode Input
tIRD
FIGURE 1-1:
VOUT
Voltage Range vs. Temperature.
FIGURE 1-5:
Differential-Mode Input
Overdrive Recovery Timing Diagram.
VDM Range (V)
VDMH
VIP
27.5V
TA (°C)
VDM
-40
25
85
125 150
VDML
Differential Input Voltage
tOR
VOUT
FIGURE 1-6:
Timing Diagram.
Output Overdrive Recovery
FIGURE 1-2:
Range vs. Temperature.
VPLH + 0.1V
VPLL + 0.1V
VREF Range (V)
VDD
0V
VDD
tPOFF
tPON
High-Z
VOUT
On
VRH
FIGURE 1-7:
V
Power On/Off Timing
OUT
TA (°C)
VRL
Diagram, Low-Side.
-40
25
85
125 150
FIGURE 1-3:
Reference Voltage Range
vs. Temperature.
DS20006179A-page 12
2019 Microchip Technology Inc.
MCP6C04
1.5.2
DC DIFFERENTIAL GAIN TEST
CIRCUIT
VPHH + 0.1V
VPHL + 0.1V
Figure 1-10 is used for testing the differential gain error,
nonlinearity and input voltage range (gE, INLDM, VDML
0V
tPHOFF
High-Z
VIP
tPHON
and VDMH). We compare VMEAS with the ideal VOUT
,
then extract the above parameters.
VOUT
On
FIGURE 1-8:
Diagram, High-Side.
V
Power On/Off Timing
OUT
VIP
VDD
U1 (DUT)
RWIP
MCP6C04
1.5
Simplified Test Circuits
VMEAS
LPF
1.5.1
V
TEST CIRCUIT
OS
RWR
CL
RWIM
VIM
Figure 1-9 tests the MCP6C04’s input offset errors
(VOS, 1/CMRR, 1/CMRR2 and 1/PSRR, etc.). RWIP is
set very low, so IBP does not affect the result. VOUT is
filtered and amplified before measuring the result.
VOUT
RL
VSS
VL
Differential Gain Test
VIP
VDD
FIGURE 1-10:
Circuit.
U1 (DUT)
RWIP
MCP6C04
LPF
and
Gain
When measuring the differential input range, all of the
voltages must be in range except VDM
VMEAS
.
When measuring differential errors (gE, ΔgE/ΔTA and
INLDM), all voltages are held constant, except VDM
RWR
RWIM
VOUT
RL
.
For accuracy, the wiring resistances at the DUT need
to be very small (see Equation 1-2).
VSS
CL
VL
Input Offset Test Circuit for
1.5.3
AC GAINS TEST CIRCUIT
Figure 1-11 is used for testing the INA’s different AC
gains. The AC voltages are:
FIGURE 1-9:
the MCP6C04.
• vout is the AC output
When MCP6C04 is in its normal range of operation, the
DC output voltages are (VE is the sum of input offset
errors and gE is the gain error):
• vip is the AC Common-mode input, used for
CMRR plots
• vdm is the AC differential input, used for GDM plots
(also for CMRR and PSRR)
EQUATION 1-1:
• vdd and vss are the AC supply inputs, used for
PSRR plots (including PSRR+ and PSRR-)
GDM
=
DM Gain
VOUT = GDM(1 + gE)VE + VREF
VMEAS = GPAVOUT
VDD + vdd
U1 (DUT)
VIP + vip
The resistances at the Device Under Test (DUT) need
to be small enough for accuracy (see Figure 1-10).
These resistances include wires, traces, vias, etc.
MCP6C04
VOUT + vout
CL
~
RWR
EQUATION 1-2:
VDM + vdm
RL
VL
AC Gain Test Circuit.
RWIP ≤ 4 mΩ
RWIM ≤ 0.1Ω
RWR ≤ 1Ω
VSS + vss
FIGURE 1-11:
2019 Microchip Technology Inc.
DS20006179A-page 13
MCP6C04
The impedance at VREF (shown here as RWR) needs to
have a magnitude less than 1Ω, for gain accuracy in the
signal bandwidth. The magnitude needs to be < 50Ω,
when f < 1 MHz, to maintain good stability.
EQUATION 1-4:
VOUT = VREF + GDM(1 + gE)VE
The input offset error (VE) is extracted from input offset
measurements (see Section 1.5.1 “VOS Test
Circuit”):
1.6
Explanation of DC Error
Specifications
1.6.1
LINEAR RESPONSE MODEL
EQUATION 1-5:
When the inputs and the output are in their normal
ranges, and the nonlinear errors are negligible, the out-
put voltage (VOUT) is:
VOUT – VREF
--------------------------------
=
VE
GDM(1 + gE)
EQUATION 1-3:
We usually assume gE = 0, in Equation 1-5, when
extracting VE. The result is accurate enough, since gE
is so low.
VOUT = VREF + GDM(1 + gE)(VDM + VE)
VE has several terms, that assume a linear response to
VDM is the input voltage. VE is the sum of input offset
errors (due to VOS, PSRR, CMRR, CMRR2, TC1, TC2,
etc.). gE is the Gain Error (GDM is the nominal gain).
changes in VDD, VSS, VIP and VREF
.
VOS’s dependence on temperature (TA) is a quadratic
polynomial (VOS, TC1 and TC2). The aging specs
(ΔVOS and ΔTC1) are not included, for simplicity.
1.6.2
INPUT OFFSET RELATED ERRORS
When VDM = 0V, the linear response model for VOUT
becomes:
EQUATION 1-6:
ΔV
– ΔV
ΔV
ΔV
REF
2
DD
SS
IP
------------------------------------ --------------- ------------------
V
= V
+
+
+
+ ΔT TC + ΔT TC
E
OS
A
1
A
2
PSRR
CMRR CMRR2
Where:
PSRR, CMRR and CMRR2 are in units of V/V
ΔTA is in units of °C
VDM = 0
1.6.3
INPUT OFFSET’S COMMON-MODE
VOLTAGE NONLINEARITY
VE, VE_LIN (V)
VE_LIN
VE
The input offset error (VE) changes nonlinearly with VIP.
Figure 1-12 shows the MCP6C04’s VE vs. VIP, as well
as a linear fit line (VE_LIN), that goes through the center
point (VC, V2) and has the same slope as the end
points.
V3
V2
V1
ΔVE
VIP (V)
VIPL
VC
VIPH
FIGURE 1-12:
Input Offset Error vs.
Common-Mode Input Voltage.
DS20006179A-page 14
2019 Microchip Technology Inc.
MCP6C04
The part is in standard conditions (ΔVOUT = 0, VDM = 0,
etc.). VIP sweeps from VIPL to VIPH. The test circuit is in
Section 1.5.1, VOS Test Circuit. Calculate VE at each
point with Equation 1-5.
VED, VED_LIN (V)
VED_LIN
VED
V3
V2
Based on the measured VE data, we obtain the
following linear fit:
EQUATION 1-7:
VE_LIN = V2 + (VIP – VC) ⁄ CMRR
Where:
V1
ΔVED
VC = (VIPL + VIPH) ⁄ 2
VDM (V)
1 ⁄ CMRR = (V3 – V1) ⁄ (VIPH – VIPL
)
VD1
VC
VD2
The remaining error (ΔVE) is described by the
Common-mode Nonlinearity spec:
FIGURE 1-13:
Differential Input Voltage.
Differential Input Error vs.
Based on the measured VED data, we obtain the
following linear fit:
EQUATION 1-8:
INLCMH = max(ΔVE) ⁄ (VIPH – VIPL
INLCML = min(ΔVE) ⁄ (VIPH – VIPL
)
)
EQUATION 1-10:
INLCM = INLCMH
= INLCML
,
INLCMH ≥ INLCML
otherwise
VED_LIN = V2 + (VDM – VC)gE
,
Where:
Where:
VC = (VD1 + VD2) ⁄ 2
gE = (V3 – V1) ⁄ (VD2 – VD1
ΔVE = VE – VE_LIN
)
The remaining error (ΔVED) is described by the
Differential Nonlinearity spec:
1.6.4
DIFFERENTIAL GAIN ERROR AND
NONLINEARITY
The differential errors are extracted from differential
gain measurements (see Section 1.5.2, DC
Differential Gain Test Circuit), based on
Equation 1-3. These errors are then split into the
differential Gain Error (gE) and the input nonlinearity
EQUATION 1-11:
INLDMH = max(ΔVED) ⁄ (VD2 – VD1
INLDML = min(ΔVED) ⁄ (VD2 – VD1
INLDM = INLDMH
= INLDML
)
)
,
INLDMH ≥ INLDML
error INLDM
.
,
otherwise
The error VED is calculated by subtracting the ideal
Where:
output from VOUT, then dividing by the ideal gain GDM
.
ΔVED = VED – VED_LIN
EQUATION 1-9:
The aging spec ΔgE is not included here, for simplicity.
VDM sweeps are not always centered on VDM = 0V; the
INLDM spec will interact with the VOS spec.
VED = (VOUT – (VREF + GDM ⋅ VDM)) ⁄ GDM
Figure 1-13 shows VED vs. VDM, as well as a linear fit
line (VED_LIN) based on VDM and gE. The amplifier is in
one of the standard condition sets. The linear fit line
(VED_LIN) goes through the center point (VC, V2) and
has the same slope as the end points.
2019 Microchip Technology Inc.
DS20006179A-page 15
MCP6C04
NOTES:
DS20006179A-page 16
2019 Microchip Technology Inc.
MCP6C04
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise indicated, TA = +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 27.5V, VDM = 0V,
VREF = VDD/4, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
2.1
DC Precision
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FIGURE 2-4:
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Input Offset Voltage,
FIGURE 2-5:
Linear Input Offset Voltage
G
= 50.
Drift, G
= 50.
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Input Offset Voltage,
FIGURE 2-6:
Linear Input Offset Voltage
G
Drift, G
= 100.
DM
DM
2019 Microchip Technology Inc.
DS20006179A-page 17
MCP6C04
Note:
Unless otherwise indicated, TA = +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 27.5V, VDM = 0V,
VREF = VDD/4, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
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FIGURE 2-10:
Power Supply Voltage, with G
Input Offset Voltage vs.
= 20.
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ꢀꢄꢃ
ꢀꢆꢃ
ꢃ
ꢆꢃ
ꢄꢃ
ꢁꢂꢃ
ꢃꢍꢃ ꢃꢍꢇ ꢁꢍꢃ ꢁꢍꢇ ꢂꢍꢃ ꢂꢍꢇ ꢏꢍꢃ ꢏꢍꢇ ꢆꢍꢃ ꢆꢍꢇ ꢇꢍꢃ ꢇꢍꢇ
3RZHUꢉ6XSSO\ꢉ9ROWDJHꢊꢉ9'' ꢋ9ꢌ
,QSXWꢉ2IIVHWꢉ9ROWDJHꢉ'ULIWꢊꢉ7&ꢂ ꢋS9ꢐ&ꢂꢌ
FIGURE 2-8:
Quadratic Input Offset
FIGURE 2-11:
Input Offset Voltage vs.
Voltage Drift, G
= 50.
Power Supply Voltage, with G
= 50.
DM
DM
ꢅ
ꢇ
ꢆꢇꢎ
*
ꢉꢁꢃꢃ
7$'0 ꢉꢀꢆꢃ&ꢉWRꢉꢑꢁꢂꢇ&
ꢂꢈꢉ6DPSOHV
ꢆꢃꢎ
ꢏꢇꢎ
ꢏꢃꢎ
ꢂꢇꢎ
ꢂꢃꢎ
ꢁꢇꢎ
ꢁꢃꢎ
ꢇꢎ
ꢆ
ꢏ
ꢂ
ꢁ
9'' ꢉꢇꢍꢇ9
9'' ꢉꢂꢍꢃ9
ꢃ
ꢀꢁ
ꢀꢂ
ꢁꢂꢇ&
ꢀꢏ
ꢄꢇ&
ꢀꢆ
ꢀꢇ
ꢀꢅ
ꢂꢇ&
*
9
ꢉꢁꢃꢃ
'0
ꢀꢆꢃ&
ꢉꢏ9
,3
5HSUHVHQWDWLYHꢉ3DUW
ꢃꢎ
ꢀꢁꢂꢃ
ꢀꢄꢃ
ꢀꢆꢃ
ꢃ
ꢆꢃ
ꢄꢃ
ꢁꢂꢃ
ꢃꢍꢃ ꢃꢍꢇ ꢁꢍꢃ ꢁꢍꢇ ꢂꢍꢃ ꢂꢍꢇ ꢏꢍꢃ ꢏꢍꢇ ꢆꢍꢃ ꢆꢍꢇ ꢇꢍꢃ ꢇꢍꢇ
3RZHUꢉ6XSSO\ꢉ9ROWDJHꢊꢉ9'' ꢋ9ꢌ
,QSXWꢉ2IIVHWꢉ9ROWDJHꢉ'ULIWꢊꢉ7&ꢂ ꢋS9ꢐ&ꢂꢌ
FIGURE 2-9:
Voltage Drift, G
Quadratic Input Offset
= 100.
FIGURE 2-12:
Power Supply Voltage, with G
Input Offset Voltage vs.
= 100.
DM
DM
DS20006179A-page 18
2019 Microchip Technology Inc.
MCP6C04
Note:
Unless otherwise indicated, TA = +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 27.5V, VDM = 0V,
VREF = VDD/4, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
ꢁꢂ
ꢁꢂ
ꢁꢃ
ꢄ
5HSUHVHQWDWLYH 3DUW
ꢁꢃ
ꢄ
ꢅ
ꢅ
ꢆ
ꢆ
ꢂ
ꢂ
ꢃ
ꢃ
ꢀꢂ
ꢀꢆ
ꢀꢅ
ꢀꢂ
ꢀꢆ
ꢀꢅ
ꢀꢄ
ꢀꢁꢃ
ꢀꢁꢂ
ꢁꢂꢇ&
ꢄꢇ&
ꢂꢇ&
ꢀꢆꢃ&
*
9
ꢉꢂꢃ
ꢁꢂꢇ&
ꢄꢇ&
ꢂꢇ&
ꢀꢆꢃ&
'0
ꢀꢄ
ꢀꢁꢃ
ꢀꢁꢂ
*
9
ꢉꢂꢃ
ꢉꢂꢍꢃ9
'0
''
ꢉꢇꢍꢇ9
''
5HSUHVHQWDWLYHꢉ3DUW
ꢃꢍꢃ ꢃꢍꢇ ꢁꢍꢃ ꢁꢍꢇ ꢂꢍꢃ ꢂꢍꢇ ꢏꢍꢃ ꢏꢍꢇ ꢆꢍꢃ ꢆꢍꢇ ꢇꢍꢃ ꢇꢍꢇ
2XWSXWꢉ5HIHUHQFHꢉ9ROWDJHꢊꢉ95() ꢋ9ꢌ
ꢃ
ꢇ
ꢁꢃ ꢁꢇ ꢂꢃ ꢂꢇ ꢏꢃ ꢏꢇ ꢆꢃ ꢆꢇ ꢇꢃ ꢇꢇ ꢅꢃ
&RPPRQꢉ0RGHꢉ,QSXWꢉ9ROWDJHꢊꢉ9,3 ꢋ9ꢌ
FIGURE 2-13:
Input Offset Voltage vs.
FIGURE 2-16:
Input Offset Voltage vs.
Common-Mode Input Voltage, with G
= 20.
Reference Voltage, with G
= 20.
DM
DM
ꢄ
ꢄ
ꢅ
ꢆ
ꢂ
ꢃ
ꢅ
ꢁꢂꢇ&
ꢄꢇ&
ꢆ
ꢂ
ꢂꢇ&
ꢀꢆꢃ&
ꢃ
ꢀꢂ
ꢀꢆ
ꢀꢅ
ꢀꢂ
ꢀꢆꢃ&
ꢂꢇ&
ꢀꢆ
ꢄꢇ&
ꢁꢂꢇ&
ꢀꢅ
ꢀꢄ
*
9
ꢉꢇꢃ
*
9
ꢉꢇꢃ
'0
'0
5HSUHVHQWDWLYHꢉ3DUW
5HSUHVHQWDWLYHꢉ3DUW
ꢉꢇꢍꢇ9
ꢉꢂꢍꢃ9
''
''
ꢀꢄ
ꢃ
ꢇ
ꢁꢃ ꢁꢇ ꢂꢃ ꢂꢇ ꢏꢃ ꢏꢇ ꢆꢃ ꢆꢇ ꢇꢃ ꢇꢇ ꢅꢃ
&RPPRQꢉ0RGHꢉ,QSXWꢉ9ROWDJHꢊꢉ9,3 ꢋ9ꢌ
ꢃꢍꢃ ꢃꢍꢇ ꢁꢍꢃ ꢁꢍꢇ ꢂꢍꢃ ꢂꢍꢇ ꢏꢍꢃ ꢏꢍꢇ ꢆꢍꢃ ꢆꢍꢇ ꢇꢍꢃ ꢇꢍꢇ
2XWSXWꢉ5HIHUHQFHꢉ9ROWDJHꢊꢉ95() ꢋ9ꢌ
FIGURE 2-14:
Input Offset Voltage vs.
FIGURE 2-17:
Input Offset Voltage vs.
Common-Mode Input Voltage, with G
= 50.
Reference Voltage, with G
= 50.
DM
DM
ꢅ
ꢅ
ꢁꢂꢇ&
ꢁꢂꢇ&
ꢇ
ꢇ
ꢄꢇ&
ꢄꢇ&
ꢆ
ꢏ
ꢂꢇ&
ꢆ
ꢏ
ꢂꢇ&
ꢀꢆꢃ&
ꢂ
ꢂ
ꢁ
ꢁ
ꢃ
ꢃ
ꢀꢁ
ꢀꢂ
ꢀꢏ
ꢀꢆ
ꢀꢇ
ꢀꢅ
ꢀꢁ
ꢀꢂ
ꢀꢏ
ꢀꢆ
ꢀꢇ
ꢀꢅ
*
9
ꢉꢁꢃꢃ
*
9
ꢉꢁꢃꢃ
'0
'0
ꢉꢂꢍꢃ9
5HSUHVHQWDWLYHꢉ3DUW
5HSUHVHQWDWLYHꢉ3DUW
ꢉꢇꢍꢇ9
''
''
ꢃ
ꢇ
ꢁꢃ ꢁꢇ ꢂꢃ ꢂꢇ ꢏꢃ ꢏꢇ ꢆꢃ ꢆꢇ ꢇꢃ ꢇꢇ ꢅꢃ
&RPPRQꢉ0RGHꢉ,QSXWꢉ9ROWDJHꢊꢉ9,3 ꢋ9ꢌ
ꢃꢍꢃ ꢃꢍꢇ ꢁꢍꢃ ꢁꢍꢇ ꢂꢍꢃ ꢂꢍꢇ ꢏꢍꢃ ꢏꢍꢇ ꢆꢍꢃ ꢆꢍꢇ ꢇꢍꢃ ꢇꢍꢇ
2XWSXWꢉ5HIHUHQFHꢉ9ROWDJHꢊꢉ95() ꢋ9ꢌ
FIGURE 2-15:
Input Offset Voltage vs.
FIGURE 2-18:
Input Offset Voltage vs.
Common-Mode Input Voltage, with G
= 100.
Reference Voltage, with G
= 100.
DM
DM
2019 Microchip Technology Inc.
DS20006179A-page 19
MCP6C04
Note:
Unless otherwise indicated, TA = +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 27.5V, VDM = 0V,
VREF = VDD/4, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
ꢆꢇꢎ
ꢆꢃꢎ
ꢏꢇꢎ
ꢏꢃꢎ
ꢂꢇꢎ
ꢂꢃꢎ
ꢁꢇꢎ
ꢁꢃꢎ
ꢇꢎ
ꢆꢇꢎ
*
ꢉꢂꢃ
*
ꢉꢂꢃ
7$'0 ꢉꢂꢇ&
7$'0 ꢉꢂꢇ&
ꢆꢃꢎ
ꢏꢇꢎ
ꢏꢃꢎ
ꢂꢇꢎ
ꢂꢃꢎ
ꢁꢇꢎ
ꢁꢃꢎ
ꢇꢎ
9'' ꢉꢂꢍꢃ9ꢉWRꢉꢇꢍꢇ9
ꢂꢄꢉ6DPSOHV
9,3 ꢉꢏ9ꢉWRꢉꢇꢂ9
ꢂꢄꢉ6DPSOHV
9'' ꢉꢂꢍꢃ9
9'' ꢉꢇꢍꢇ9
ꢃꢎ
ꢃꢎ
ꢃꢍꢃꢁꢃ ꢃꢍꢃꢁꢂ ꢃꢍꢃꢁꢆ ꢃꢍꢃꢁꢅ ꢃꢍꢃꢁꢄ ꢃꢍꢃꢂꢃ ꢃꢍꢃꢂꢂ
ꢁꢐ&055ꢉꢋ9ꢐ9ꢌ
ꢀꢃꢍꢏ
ꢀꢃꢍꢂ
ꢀꢃꢍꢁ
ꢃꢍꢃ
ꢃꢍꢁ
ꢃꢍꢂ
ꢃꢍꢏ
ꢁꢐ3655ꢉꢋ9ꢐ9ꢌ
FIGURE 2-19:
1/CMRR, with G
= 20.
FIGURE 2-22:
1/PSRR, with G
= 20.
DM
DM
ꢆꢇꢎ
ꢏꢃꢎ
*
ꢉꢇꢃ
7$'0 ꢉꢂꢇ&
*
ꢉꢇꢃ
7$'0 ꢉꢂꢇ&
ꢆꢃꢎ
ꢏꢇꢎ
ꢏꢃꢎ
ꢂꢇꢎ
ꢂꢃꢎ
ꢁꢇꢎ
ꢁꢃꢎ
ꢇꢎ
9,3 ꢉꢏ9ꢉWRꢉꢇꢂ9
ꢂꢄꢉ6DPSOHV
ꢂꢇꢎ
ꢂꢃꢎ
ꢁꢇꢎ
ꢁꢃꢎ
ꢇꢎ
9'' ꢉꢂꢍꢃ9ꢉWRꢉꢇꢍꢇ9
ꢂꢄꢉ6DPSOHV
9'' ꢉꢇꢍꢇ9
9'' ꢉꢂꢍꢃ9
ꢃꢎ
ꢃꢎ
ꢃꢍꢃꢁꢆ ꢃꢍꢃꢁꢅ ꢃꢍꢃꢁꢄ ꢃꢍꢃꢂꢃ ꢃꢍꢃꢂꢂ ꢃꢍꢃꢂꢆ ꢃꢍꢃꢂꢅ
ꢁꢐ&055ꢉꢋ9ꢐ9ꢌ
ꢀꢃꢍꢁꢂ ꢀꢃꢍꢃꢄ ꢀꢃꢍꢃꢆ ꢃꢍꢃꢃ
ꢃꢍꢃꢆ
ꢃꢍꢃꢄ
ꢃꢍꢁꢂ
ꢁꢐ3655ꢉꢋ9ꢐ9ꢌ
FIGURE 2-20:
1/CMRR, with G
= 50.
FIGURE 2-23:
1/PSRR, with G
= 50.
DM
DM
ꢇꢇꢎ
ꢅꢃꢎ
ꢇꢇꢎ
ꢇꢃꢎ
ꢆꢇꢎ
ꢆꢃꢎ
ꢏꢇꢎ
ꢏꢃꢎ
ꢂꢇꢎ
ꢂꢃꢎ
ꢁꢇꢎ
ꢁꢃꢎ
ꢇꢎ
*
ꢉꢁꢃꢃ
*
ꢉꢁꢃꢃ
7$'0 ꢉꢂꢇ&
9,3 ꢉꢏ9ꢉWRꢉꢇꢂ9
ꢂꢄꢉ6DPSOHV
7$'0 ꢉꢂꢇ&
ꢇꢃꢎ
ꢆꢇꢎ
ꢆꢃꢎ
ꢏꢇꢎ
ꢏꢃꢎ
ꢂꢇꢎ
ꢂꢃꢎ
ꢁꢇꢎ
ꢁꢃꢎ
ꢇꢎ
9'' ꢉꢂꢍꢃ9ꢉWRꢉꢇꢍꢇ9
ꢂꢈꢉ6DPSOHV
9'' ꢉꢇꢍꢇ9
9'' ꢉꢂꢍꢃ9
ꢃꢎ
ꢃꢎ
ꢃꢍꢃꢁꢃ ꢃꢍꢃꢁꢂ ꢃꢍꢃꢁꢆ ꢃꢍꢃꢁꢅ ꢃꢍꢃꢁꢄ ꢃꢍꢃꢂꢃ ꢃꢍꢃꢂꢂ
ꢁꢐ&055ꢉꢋ9ꢐ9ꢌ
ꢀꢃꢍꢁꢂ ꢀꢃꢍꢃꢄ ꢀꢃꢍꢃꢆ ꢃꢍꢃꢃ
ꢃꢍꢃꢆ
ꢃꢍꢃꢄ
ꢃꢍꢁꢂ
ꢁꢐ3655ꢉꢋ9ꢐ9ꢌ
FIGURE 2-21:
1/CMRR, with G
= 100.
FIGURE 2-24:
1/PSRR, with G
= 100.
DM
DM
DS20006179A-page 20
2019 Microchip Technology Inc.
MCP6C04
Note:
Unless otherwise indicated, TA = +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 27.5V, VDM = 0V,
VREF = VDD/4, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
ꢁꢅꢃ
ꢁꢇꢃ
ꢁꢆꢃ
ꢁꢏꢃ
ꢁꢂꢃ
ꢁꢁꢃ
ꢁꢃꢃ
*
*
*
ꢉꢁꢃꢃ
ꢉꢇꢃ
ꢉꢂꢃ
'0
'0
'0
9,3 ꢉꢏ9ꢉWRꢉꢇꢂ9
ꢂꢄꢉ6DPSOHV
ꢀꢇꢃ
ꢀꢂꢇ
ꢃ
ꢂꢇ
ꢇꢃ
ꢈꢇ
ꢁꢃꢃ
ꢁꢂꢇ
$PELHQWꢉ7HPSHUDWXUHꢊꢉ7$ ꢋ&ꢌ
FIGURE 2-25:
CMRR vs. Ambient
Temperature.
ꢁꢅꢃ
ꢁꢇꢃ
ꢁꢆꢃ
ꢁꢏꢃ
ꢁꢂꢃ
ꢁꢁꢃ
*
*
*
ꢉꢁꢃꢃ
ꢉꢇꢃ
ꢉꢂꢃ
'0
'0
'0
9'' ꢉꢂꢍꢃ9ꢉWRꢉꢇꢍꢇ9
ꢂꢄꢉ6DPSOHV
ꢁꢃꢃ
ꢀꢇꢃ
ꢀꢂꢇ
ꢃ
ꢂꢇ
ꢇꢃ
ꢈꢇ
ꢁꢃꢃ
ꢁꢂꢇ
$PELHQWꢉ7HPSHUDWXUHꢊꢉ7$ ꢋ&ꢌ
FIGURE 2-26:
PSRR vs. Ambient
Temperature.
FIGURE 2-27:
Gain Error.
2019 Microchip Technology Inc.
DS20006179A-page 21
ꢁꢍ(
ꢁꢃꢃ
MCP6C04
Note:
Unless otherwise indicated, TA = +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 27.5V, VDM = 0V,
VREF = VDD/4, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
2.2
Other DC Voltages and Currents
ꢂꢂꢃ
ꢂꢃꢃ
4
3
VDM = VDML
GDM = 20
:
5HSUHVHQWDWLYHꢉ3DUW
G
G
DM = 50
ꢁꢄꢃ
ꢁꢅꢃ
ꢁꢆꢃ
ꢁꢂꢃ
ꢁꢃꢃ
ꢄꢃ
ꢅꢃ
ꢆꢃ
ꢂꢃ
DM = 100
2
1
ꢀꢆꢃ&
0
ꢑꢂꢇ&
ꢑꢄꢇ&
ꢑꢁꢂꢇ&
-1
-2
-3
-4
VDM = VDMH
:
GDM = 100
GDM = 50
G
DM = 20
ꢃ
ꢃꢉ ꢇꢉ ꢁꢃꢉ ꢁꢇꢉ ꢂꢃꢉ ꢂꢇꢉ ꢏꢃꢉ ꢏꢇꢉ ꢆꢃꢉ ꢆꢇꢉ ꢇꢃꢉ ꢇꢇꢉ ꢅꢃ
1RQ,QYHUWLQJꢉ,QSXWꢉ9ROWDJHꢊꢉ9,3ꢉꢋ9ꢌ
Differential Input Voltage;VDM (V)
FIGURE 2-28:
V
Pin Input Bias Current
FIGURE 2-31:
V
Pin Input Bias Current
IM
IP
vs. Input Common-Mode Voltage.
vs. Differential Input Voltage.
ꢁꢃ
*
'09'0 ꢉꢀꢏ9
ꢑꢁꢂꢇ&
ꢑꢄꢇ&
ꢑꢂꢇ&
ꢀꢆꢃ&
ꢁꢂꢇ&
ꢄꢇ&
9'' ꢉꢇꢍꢇ9
*
ꢉꢂꢃ
ꢂꢇ&
'0
ꢁꢍ(ꢀꢃꢇ
ꢁꢃ
ꢀꢆꢃ&
ꢁꢍ(ꢀꢃꢅ
ꢁ
ꢁ
ꢁꢍ(ꢀꢃꢈ
ꢁꢃꢃQ
ꢁꢍ(ꢀꢃꢄ
ꢁꢃQ
ꢃꢍꢁ
ꢁꢍ(ꢀꢃꢒ
ꢁQ
ꢁꢃꢃQ
ꢃ
ꢇ
ꢁꢃ ꢁꢇ ꢂꢃ ꢂꢇ ꢏꢃ ꢏꢇ ꢆꢃ ꢆꢇ ꢇꢃ ꢇꢇ ꢅꢃ
,QYHUWLQJꢉ,QSXWꢉ9ROWDJHꢊꢉ9,0 ꢋ9ꢌ
ꢀꢃꢍꢏꢃ ꢀꢃꢍꢂꢇ ꢀꢃꢍꢂꢃ ꢀꢃꢍꢁꢇ ꢀꢃꢍꢁꢃ ꢀꢃꢍꢃꢇ
,QSXWꢉ&RPPRQꢉ0RGHꢉ9ROWDJHꢊꢉ9,3 ꢋ9ꢌ
ꢃꢍꢃꢃ
FIGURE 2-29:
V
Pin Input Bias Current
FIGURE 2-32:
Input Bias Current vs. Input
IM
vs. Input Common-Mode Voltage, V
= V
.
Common-Mode Voltage (below V ).
DM
DML
SS
ꢁꢃ
ꢒ
ꢄ
ꢇꢅ
ꢇꢇ
ꢇꢆ
ꢇꢏ
ꢇꢂ
ꢇꢁ
ꢇꢃ
ꢆꢒ
ꢆꢄ
ꢆꢈ
ꢆꢅ
ꢁꢃ
ꢑꢁꢂꢇ&
ꢑꢄꢇ&
ꢑꢂꢇ&
ꢀꢆꢃ&
*
'09'0 ꢉꢀꢏ9
9'' ꢉꢇꢍꢇ9
*
ꢉꢂꢃ
'0
9,3+ ± 966
ꢈ
ꢅ
ꢇ
ꢆ
ꢏ
ꢂ
ꢁ
ꢃ
ꢁ
ꢁ
9,3/ ± 966
ꢃꢍꢁ
ꢁꢃꢃQ
ꢃ
ꢇ
ꢁꢃ ꢁꢇ ꢂꢃ ꢂꢇ ꢏꢃ ꢏꢇ ꢆꢃ ꢆꢇ ꢇꢃ ꢇꢇ ꢅꢃ
,QYHUWLQJꢉ,QSXWꢉ9ROWDJHꢊꢉ9,0 ꢋ9ꢌ
ꢀꢇꢃ ꢀꢂꢇ
ꢃ
ꢂꢇ ꢇꢃ ꢈꢇ ꢁꢃꢃ ꢁꢂꢇ ꢁꢇꢃ
$PELHQWꢉ7HPSHUDWXUHꢊꢉ7$ ꢋ&ꢌ
FIGURE 2-30:
V
Pin Input Bias Current
FIGURE 2-33:
Common-Mode Input Range
IM
vs. Input Common-Mode Voltage, V
= V
.
vs. Ambient Temperature.
DM
DMH
DS20006179A-page 22
2019 Microchip Technology Inc.
MCP6C04
Note:
Unless otherwise indicated, TA = +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 27.5V, VDM = 0V,
VREF = VDD/4, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
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FIGURE 2-34:
Reference Voltage Range
FIGURE 2-37:
Supply Current vs. Power
vs. Ambient Temperature.
Supply Voltage.
50
40
1000
6-Lead SOT-23
30
20
10
-40°C
+25°C
+85°C
100
10
+125°C
0
+125°C
+85°C
+25°C
-40°C
-10
-20
-30
-40
-50
VDD – VOH
VOL – VSS
1
0.1
1
10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage; VDD (V)
Output Current Magnitude; | IOUT | (mA)
FIGURE 2-35:
Output Voltage Range vs.
FIGURE 2-38:
Output Short Circuit Current
Output Current.
vs. Power Supply Voltage.
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FIGURE 2-36:
Output Voltage Range vs.
FIGURE 2-39:
LV POR (for V ) Trip
DD
Ambient Temperature.
Points vs. Ambient Temperature.
2019 Microchip Technology Inc.
DS20006179A-page 23
MCP6C04
Note:
Unless otherwise indicated, TA = +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 27.5V, VDM = 0V,
VREF = VDD/4, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
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FIGURE 2-40:
HV POR (for V ) Trip Points
IP
vs. Ambient Temperature.
DS20006179A-page 24
2019 Microchip Technology Inc.
ꢁꢍꢁꢃN
ꢆ
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MCP6C04
Note:
Unless otherwise indicated, TA = +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 27.5V, VDM = 0V,
VREF = VDD/4, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
2.3
Frequency Response
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DM = 100
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1.E+7
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100k
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FIGURE 2-41:
Gain vs. Frequency, with
FIGURE 2-44:
Closed-Loop Output
Capacitive Load.
Impedance Magnitude vs. Frequency.
100
90
80
70
60
50
40
140
VIPꢉ= 0.1VPK
120
100
80
60
40
20
0
GDM = 100
GDM = 50
GDM = 20
10k
1.E+04
100k
1M
1.E+06
1.E+05
100M
1.0E+08
1G
10G
1.0E+10
1.0E+09
Frequency; f (Hz)
Frequency; f (Hz)
FIGURE 2-42:
CMRR vs. Frequency.
FIGURE 2-45:
EMI Rejection Ratio vs.
Frequency.
120
110
100
90
80
70
60
50
40
30
20
10
0
140
120
100
80
f:
60
6.0 GHz
4.0 GHz
2.4 GHz
1.8 GHz
0.9 GHz
0.4 GHz
GDM = 100
40
GDM
GDM
=
=
50
20
20
0
0.01
1k
10k
1.E+4
100k
1.E+5
1M
1.E+6
10M
1.E+7
0.1
Input Common Mode Voltage; VIP (VPK
1
1.E+3
Frequency; f (Hz)
)
FIGURE 2-43:
PSRR vs. Frequency.
FIGURE 2-46:
EMI Rejection Ratio vs.
Signal Strength.
2019 Microchip Technology Inc.
DS20006179A-page 25
MCP6C04
Note:
Unless otherwise indicated, TA = +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 27.5V, VDM = 0V,
VREF = VDD/4, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
2.4
Noise and Intermodulation Distortion
300n
GDM = 20
GDM = 50
GDM = 100
GDM = 20
SAM = 40 SPS
f
NPBW = 10 Hz
NPBW = 1 Hz
1.E-7
100n
1.E-8
10n
0.1
1
10
100
1k
10k
100k
0
20 40 60 80 100 120 140 160 180 200
Time; t (s)
1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5
Frequency; f (Hz)
FIGURE 2-47:
vs. Frequency.
Input Noise Voltage Density
FIGURE 2-50:
Time, G = 20.
Input Noise Voltage vs.
DM
1.E-4
100μ
GDM = 50
GDM = 20
fSAM = 40 SPS
G
DM = 50
GDM = 100
NPBW = 10 Hz
NPBW = 1 Hz
1.E-5
10μ
1.E-6
1μ
1.E-7
100n
1.E-8
10n
0.1
1
10
100
1k
10k
100k
0
20 40 60 80 100 120 140 160 180 200
Time; t (s)
1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5
Frequency; f (Hz)
FIGURE 2-48:
Frequency.
Input Noise Voltage vs.
FIGURE 2-51:
Time, G = 50.
Input Noise Voltage vs.
DM
1.E-03
GDM = 100
GDM = 20
fSAM = 40 SPS
VDD = 5.5V, at DC
= 0.1 VPK, at 100 Hz
No VDD bypass cap
NPBW = 10 Hz
NPBW = 1 Hz
1.E-04
1.E-05
1.E-06
Residual Tone
at 100 Hz
Δf = 2 Hz, f ≤ 3201 Hz
= 64 Hz, f ≥ 3250 Hz
0
20 40 60 80 100 120 140 160 180 200
Time; t (s)
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
Frequency; f (Hz)
FIGURE 2-49:
vs. Frequency, with V Disturbance.
Intermodulation Distortion
FIGURE 2-52:
Time, G = 100.
Input Noise Voltage vs.
DD
DM
DS20006179A-page 26
2019 Microchip Technology Inc.
MCP6C04
Note:
Unless otherwise indicated, TA = +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 27.5V, VDM = 0V,
VREF = VDD/4, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
2.5
Time Response
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
6
5
4
VDD (V)
3
VOUT (V)
2
1
GDM = 20
VOS ≈ (VOUT – 0.5V)/GDM
0
GDM = 100
GDM = 50
GDM = 20
-1
-2
-3
tSettle
tON
0
50 100 150 200 250 300 350 400 450 500
Time; t (μs)
Time; t (2 μs/div)
FIGURE 2-56:
to Differential Input Voltage.
Small Signal Step Response
FIGURE 2-53:
Time, at Power-Up.
Input Offset Voltage vs.
6
5
4
3
2
1
0
-1
GDM = 20
VIP
GDM = 50
GDM = 100
VOUT
VOUT
GDMVDM
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Time; t (μs)
Time; t (ms)
FIGURE 2-57:
to Common-Mode Input Voltage.
Small Signal Step Response
FIGURE 2-54:
Phase Reversal vs. Differential Input Overdrive.
The MCP6C04 Shows No
70
60
50
40
30
20
10
0
7
6
5
4
3
2
1
0
VDD = 5.0V
VIP
VOUT
On
3
Off
0
1
2
4
5
6
7
8
9
10
Time; t (ms)
FIGURE 2-55:
The MCP6C04 Shows No
Phase Reversal vs. Input Common-Mode
Overdrive.
2019 Microchip Technology Inc.
DS20006179A-page 27
MCP6C04
Note:
Unless otherwise indicated, TA = +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 27.5V, VDM = 0V,
VREF = VDD/4, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF; see Figure 1-9, Figure 1-10 and Figure 1-11.
2.0
GDM = 20
RISO = 0Ω
RISO = 0Ω
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
GDM = 100
GDM = 50
GDM = 20
CL = 100 pF
CL = 1 nF
CL = 10 nF
1n
1.E-9
10n
1.E-8
0
10
20
30
40
50
60
70
80
90 100
10p
100p
1.E-10
1.E-11
t (μs)
Capacitive Load; CL (F)
FIGURE 2-58:
Small Signal Step Response
FIGURE 2-60:
Small Signal Step Response
to Differential Input Voltage, with Capacitive
Rise Time, with Capacitive Load (C ).
L
Load (C ).
L
70%
RISO = 0Ω
60%
50%
40%
30%
20%
10%
0%
GDM = 100
GDM = 50
GDM = 20
1n
1.E-9
10n
1.E-8
10p
1.E-11
100p
1.E-10
Capacitive Load; CL (F)
FIGURE 2-59:
Small Signal Step Response
Overshoot, with Capacitive Load (C ).
L
DS20006179A-page 28
2019 Microchip Technology Inc.
MCP6C04
NOTES:
2019 Microchip Technology Inc.
DS20006179A-page 29
MCP6C04
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
Symbol
VOUT
MCP6C04
SOT-23
Description
1
2
3
4
5
6
Output voltage
VSS
VIP
Negative power supply
Noninverting input (at load’s RSH) and positive (high-side) power supply
VIM
Inverting input (at load’s RSH
)
VREF
VDD
Output reference
Positive (low-side) power supply
3.1
Noninverting Analog Signal Input
(VIP)
3.4
Analog Output (VOUT)
The analog output pin (VOUT) is a low-impedance
voltage source.
The noninverting input (VIP) is a high-impedance
CMOS input. It is designed to operate over a wide
voltage range, with a voltage source to drive it. In this
data sheet, it is treated as the Common-mode input
voltage.
3.5
Low-Side Power Supplies
(VDD, VSS
)
VDD is normally between VSS + 2.0V and VSS + 5.5V,
while the VREF and VOUT pins are usually between VSS
and VDD. VDD – VSS triggers the LV POR.
VIP is the high voltage power supply pin, and is
normally between VSS + 3V and VSS + 52V. It supplies
the current needed to operate the high voltage circuitry.
VIP should have a good bypass capacitor (e.g., 10 nF).
VIP – VSS triggers the HV POR.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need good bypass capacitors.
VIP is treated as the Common-mode voltage in this data
sheet, due to the inputs' architecture. Since VDM is
relatively small, this simplification is accurate; it also
simplifies the specifications and applications
information.
In split supply configurations, including dual supplies,
ground is between VSS and VDD. Both supply pins will
need good bypass capacitors.
In a single (negative) supply configuration, VDD
connects to ground and VSS connects to the supply.
VSS will need good bypass capacitors.
3.2
Inverting Analog Signal Input (VIM)
The inverting input (VIM) is a high-impedance CMOS
input, with low input bias current. VIM is designed to
operate near the VIP voltage. The difference voltage
VDM (or VIP – VIM) is the input signal for this amplifier.
3.3
Analog Output Reference Voltage
(VREF
)
The analog output reference voltage is
a
high-impedance CMOS input. VREF is set to a DC
voltage, which shifts VOUT. Its dynamic response helps
reject power surges and glitches at the VIP, VDD and
VSS pins.
DS20006179A-page 30
2019 Microchip Technology Inc.
MCP6C04
NOTES:
2019 Microchip Technology Inc.
DS20006179A-page 31
MCP6C04
The input (differential) signal is applied to GM1. Due to
its architecture, the MCP6C04’s signal inputs are best
described by VIP and VDM. The inverting input is then:
4.0
DEVICE OPERATION
This chapter includes additional information on basic
operations and major functions.
EQUATION 4-2:
4.1
Basic Performance
VIM = VIP – VDM
4.1.1
IDEAL PERFORMANCE
Figure 4-1 shows the basic circuit; inputs, supplies and
output. When the inputs (VIP, VIM, VDD, VSS and VREF
and output (VOUT) are in their specified ranges, and the
part is nearly ideal, the output voltage is:
The negative feedback loop includes GM2, RM3, RF and
RG. These blocks set the DC open-loop gain (AOL) and
the nominal differential gain (GDM):
)
EQUATION 4-3:
EQUATION 4-1:
A
= G
R
OL
M2 M3
= 1 + R ⁄ R
G
VOUT ≈ VREF + GDMVDM
G
DM
F
Where:
GDM
VIP
=
=
=
Differential-Mode Gain
AOL is very high, so the current into RM3 (I1 + I2) is
nearly zero. This makes the differential inputs to GM1
and GM2 equal in magnitude and opposite in polarity.
Ideally, this gives:
Common-Mode Input (and HV supply)
VDM
Differential-Mode Input (VIP – VIM)
EQUATION 4-4:
VDD
U1 (DUT)
VFG – VREF = VDM
MCP6C04
VIP
VIM
VOUT = VREF + GDMVDM
VOUT
For an ideal part, within the operating ranges, changing
VIP, VSS or VDD produces no change in VOUT. VREF
shifts VOUT as needed in the design.
VREF
VSS
The different GDM options change GM1, GM2, RF, RG
and the internal compensation capacitor. This results in
the performance trade-offs highlighted in Table 1.
FIGURE 4-1:
Basic Circuit.
For normal operation, keep:
• VIP between VIPL and VIPH
• VDM between VDML and VDMH
• VREF between VRL and VRH
4.1.3
DC PERFORMANCE
DC Voltage Errors
4.1.3.1
• VOUT between 0.1V to VDD – 0.1V, usually
- VOL and VOH are hard limits
Section 1.6, Explanation of DC Error Specifications
covers some DC specifications. The input offset error
(with temperature coefficients), gain error and
nonlinearities are discussed in detail.
4.1.2
ANALOG ARCHITECTURE
Figure 4-2 shows the block diagram for these high-side
current sense amplifiers, without any details on offset
correction.
Plots in Section 2.1, DC Precision and Section 2.2,
Other DC Voltages and Currents give useful
information.
In this data sheet, CMRR is based on changes in VIP
(i.e., CMRR = ΔVIP/ΔVOS). This is accurate since VDM
is relatively small. This CMRR describes the rejection
of errors at the high voltage supply, without any
VDD
VOUT
VIP
VIM
RM3
GM1
Σ
contribution from VDM
.
I1
RF
VFG
I2
GM2
RG
VREF
VSS
FIGURE 4-2:
MCP6C04 Block Diagram.
DS20006179A-page 32
2019 Microchip Technology Inc.
MCP6C04
These parts are compensated to have a stable
response. For instance, step response overshoot is
low. To be stable, VREF must see a low impedance and
VOUT must have a low capacitive load (see Figure 4-6
to compensate large capacitive loads).
4.1.3.2
Figure 4-3 shows the resistors and currents that
change the DC bias point. The input bias currents (IBP
IBM and IBR), together with a circuit’s external input
resistances, give an DC error (see Equation 1-2).
DC Current Errors
,
In this data sheet, the AC CMRR is measured at VIP.
This is accurate, since VDM is relatively small.
VDD
4.1.5
TEMPERATURE PERFORMANCE
The input offset voltage’s temperature drift is detailed in
Equation 1-6. Other temperature responses are shown
in Section 1.3, Specifications and Section 2.0
“Typical Performance Curves”.
VOUT
Σ
RWIP
IBP
RWIM
RF
IBM
IBR
RG
Since there are three power supply pins (VIP, VDD and
VSS), and VIP reaches 52V, power and temperature rise
calculations are important.
RSH
VHV
VSS
IL
The power dissipated is calculated as follows (IOUT is
positive when it flows out of the VOUT pin):
U1
MCP6C04
RWR
Load
EQUATION 4-6:
FIGURE 4-3:
Currents.
DC Bias Resistors and
PTOT = PDD + PBP + POUT
RSH is set by the design requirements, given the load
current (IL). For most applications, RSH would be
between 100 µΩ and 1Ω.
Where:
IOUT
PDD
=
=
=
=
=
(VOUT – VL)/RL
(VDD – VSS)IDD
The DC input offset error due to the input currents is:
VOS_IR = VDM – ILRSH
PBP
(VIP – VSS)IBP
POUT
(VDD – VOUT)IOUT, IOUT ≥ 0A
(VSS – VOUT)IOUT, IOUT < 0A
= IBM(RSH + RWIM) – IBPRWIP
Since these currents do not correlate, minimize the
magnitude of each resistance. IBPRIP will dominate in
many designs.
Now we can estimate the junction temperature of the
device (see Table 1-4):
RWR modifies the gain error and the DC output offset
error (VOUT changes IBR):
EQUATION 4-7:
TJ = TA + PTOTθJA
EQUATION 4-5:
ΔVREF = –IBRRWR
4.1.6
NOISE PERFORMANCE
ΔgE ≈ (–RWRGDM) ⁄ (RF + RG)
This part is designed to have low input noise voltage
density at lower frequencies. The offset correction
(Section 4.2.2, Chopping Action) modulates high
frequency white noise down to DC; it also modulates
low frequency 1/f noise to higher frequencies.
VOUT ≈ (VREF + ΔVREF) + GDMVDM(1 + gE + ΔgE)
4.1.4
AC PERFORMANCE
The bandwidth of these parts (fBW) is set internally to
either 500 kHz (GDM = 20 or 50) or 390 kHz
(GDM = 100).
The measured input noise voltage density is shown in
Figure 2-47. That figure also shows Integrated Input
Noise Voltage (Eni, in units of VRMS) between 0 Hz and
f (between 0.1 Hz and 100 kHz).
The large signal bandwidth is close to the small signal
bandwidth. The slew rate (SR) has little effect on VOUT
(a benefit of our Current-mode architecture).
The Input Noise Voltage Density (eni) changes with
VDM. However, that relationship is a weak one.
The bandwidth at the maximum output swing is called
the Full Power Bandwidth (fFPBW). It is limited by the
Slew Rate (SR) for many amplifiers, but is close to fBW
for these parts. This is a benefit of the Current-mode
architecture these parts have.
2019 Microchip Technology Inc.
DS20006179A-page 33
MCP6C04
4.2
Overview of Zero-Drift Operation
Figure 4-4 shows a diagram of the MCP6C04; It explains how slow voltage errors at the input are reduced in this archi-
tecture (much better VOS, TC1 TC2, CMRR, CMRR2, PSRR and 1/f noise).
VIP
DM
EMI
Clamps
Filters
VIM
GM1
Chopper
Input
Switches
Chopper
Output
Switches
Low-Pass
Filter
GA1
EMI
Filter
VREF
RG
RF
GM2
Chopper
Input
Switches
Chopper
Output
Switches
Low-Pass
Filter
VFG
GA2
RM4
VOUT
FIGURE 4-4:
MCP6C04 Block Diagram.
The internal LV POR (for VDD – VSS) starts the part in
a known good state, protecting against power supply
4.2.1
BUILDING BLOCKS
The Main Amplifiers (GM1 and GM2) are designed for
high gain and bandwidth, with a differential topology.
The main input pairs (+ and - pins at the top left) are for
the higher frequency portion of the input signal. The
auxiliary input pairs (+ and - pins at the bottom left) are
for the low frequency and high precision portion of the
input signal and correct the input offset voltage. Both
inputs are added together internally
brown-outs. The internal HV POR (for VIP – VSS
)
ensures protection of the low voltage circuitry, as well
as proper functioning.
4.2.2
CHOPPING ACTION
Figure 4-5 shows the amplifier connections for the first
phase of the Chopping Clock and Figure 4-6 shows
them for the second phase. The slow voltage errors
alternate in polarity, making the average error small.
The auxiliary amplifiers (GA1 and GA2), the chopper
input switches and the chopper output switches provide
a high DC gain to the input signal. DC errors are
modulated to higher frequencies and white noise to low
frequencies.
VIP
VIM
The low-pass filter reduces high-frequency content,
including harmonics of the chopping clock.
Low-
Pass
Filter
GA1
The output buffer (RM4) converts current to voltage,
drives the external load at VOUT and creates a negative
feedback loop through RF and RG. RF and RG help set
the differential gain.
VREF
VFG
Low-
Pass
Filter
The oscillator runs at fCLK = 50 kHz for the gains of 20
and 50, and at fCLK = 100 kHz for the gain of 100. fCLK
is divided by 2, to produce the chopping clock rate
(25 kHz and 50 kHz, respectively).
GA2
FIGURE 4-5:
First Chopping Clock Phase;
Simplified Diagram.
DS20006179A-page 34
2019 Microchip Technology Inc.
MCP6C04
The VIP and VIM input pins have an ESD structure
designed to limit VIP – VSS and VDM. The double
parallel diode structure that limits ESD damage through
VDM also limits VDM in other conditions.
VIP
VIM
Low-
Pass
Filter
GA1
VIP
VIM
VREF
VFG
HV
ESD
HV
POR
DM ESD
VSS
Low-
Pass
Filter
GA2
FIGURE 4-7:
(i.e., for V ) and V – V .
SS
Input Protection for V
DM
IM
IP
FIGURE 4-6:
Phase; Simplified Diagram.
Second Chopping Clock
The VREF, VOUT and VDD pins have ESD structures that
limit their voltages above VSS (i.e., limit VREF – VSS
,
VOUT – VSS and VDD – VSS).
4.2.3
FINAL TEST VS. BENCH
Due to limitations in the final test environment
(e.g., equipment accuracies, thermocouple effects
crosstalk and test time), final test measurements are
not as accurate as bench measurements. For this
reason, the input offset voltage related specifications
(VOS, TC1, TC2, ..., CMRR and PSRR) are significantly
wider than the histograms from bench measurements.
VREF
VOUT
LV
ESD
LV
ESD
VSS
VDD
VSS
The bench results will give good guidance on how to
design your circuit. The specified limits (for final test)
give min/max limits used to screen outliers in
production.
LV
ESD
LV
POR
VSS
4.2.4
INTERMODULATION DISTORTION
(IMD)
FIGURE 4-8:
and V
Input Protection for V
,
REF
V
.
DD
OUT
These amplifiers will show intermodulation distortion
(IMD) products when an AC signal is present.
4.3.2
PHASE REVERSAL
This part is designed to not exhibit phase inversion
when the input signals (VIP, VDM and VREF) exceed
their specified ranges (but not their absolute ranges).
The signal and clock can be decomposed into sine
wave tones (Fourier series components). These tones
interact with the zero-drift circuitry’s nonlinear
response to produce IMD tones at sum and difference
frequencies. Each of the square wave clock’s
harmonics has a series of IMD tones centered on it.
4.3
Protection
The MCP6C04 helps the designer provide enough
protection against undesired conditions and signals in
their environment.
4.3.1
INTERNAL PROTECTION DEVICES
All of the ESD structures clamp their inputs when they
try to go too far below VSS. Their breakdown voltage is
high enough to allow normal operation, but not low
enough to protect against slow over-voltage events.
Very fast ESD events (that meet the specification) are
limited so that damage does not occur.
The supply inputs (VIP – VSS and VDD – VSS) are also
connected to PORs, so that internal power up
sequencing is well controlled.
2019 Microchip Technology Inc.
DS20006179A-page 35
MCP6C04
5.1.3
BYPASS CAPACITORS
5.0
APPLICATIONS
Be sure to specify capacitors that will support your
application. Be sure to look at:
This chapter includes design recommendations and
typical application circuits.
• Voltage rating (well above the maximum value for
its pins)
The Common-mode rejection (see Figure 2-13,
Figure 2-14, Figure 2-15 and Figure 2-42) supports
applications in noisy environments. Our Current-mode
architecture gives high CMRR at higher frequencies
than was traditional (e.g., 80 dB near 80 kHz, instead
of near 60 Hz).
• Dielectrics (good Temp. Cos. and reasonable
Volt. Cos.
• Size
• Surface mount vs. leaded
• Cost vs. availability
The power supply rejection (see Figure 2-43) also has
excellent rejection at higher frequencies than
traditional.
If possible, connect VSS to ground. This will make your
design simpler.
Bypass VIP to VSS with a local bypass capacitor next to
these pins (e.g.,10 nF). If needed, a bulk bypass
capacitor can also be added (e.g.,1 µF).
5.1
Recommended Design Practices
Some simple design practices help take advantage of
the MCP6C04's performance in high-side current
sensing applications.
Bypass VDD to VSS with a local bypass capacitor next
to these pins (e.g.,100 nF). A bulk bypass capacitor
should also be added close by (e.g.,2.2 µF); placing it
next to the local bypass capacitor is a good choice.
5.1.1
INPUT VOLTAGE LIMITS
To prevent damage and/or improper operation of these
amplifiers, the circuit must limit the voltages at the VIP
and VIM input pins, as well as the differential input
voltage VDM (see Section 1.1, Absolute Maximum
Ratings †). These requirements are independent of
the current limits discussed below.
5.1.4
SETTING THE VOLTAGES AT V
IP
AND V
IM
VIP is tied to a voltage source, to minimize glitches and
crosstalk. This part’s excellent CMRR versus
frequency helps reject Common-mode (i.e., at VIP)
noise and glitches. A local pass capacitor to VSS can
help, when the design allows it; 10 nF is usually a good
choice (see the Typical Application Circuit on Page 1).
The ESD protection on the VIP and VDM inputs was
discussed in Section 4.3.1, Internal Protection
Devices. This structure was chosen to protect the input
transistors against many (but not all) overvoltage
conditions, and to minimize input bias currents (IBP and
IBM).
A shunt resistor (RSH) is connected between VIP and
VIM, then to the load (which is grounded). It is selected
for the trade-off between accuracy (high RSH) and
power dissipation (low RSH). Low power dissipation
also leads to reduced size and cost. RSH also helps
protect these pins against large glitches; make sure it
will never fail open.
To protect the inputs, always drive VIP with a low
impedance source and use a shunt resistor (RSH) with
low resistance (designed to not fail open). Placing
zener diode(s) or a transorb across RSH will also help
protect the inputs.
Bypass capacitors on VIP and VIM can reduce the risk
of high over-voltage events when the current changes
abruptly, such as an inductive load opening.
5.1.2
INPUT CURRENT LIMITS
To prevent damage to (or improper operation of) these
amplifiers, the circuit must limit the currents into the VIP
and VIM input pins (see Section 1.1, Absolute
A good layout is necessary to minimize DC and AC
errors. Figure 5-1 shows a layout that minimizes input
resistances seen by IBN and IBM. The critical paths are
between RSH and the pins VIP and VIM (RWIP and
RWIM).
Maximum
Ratings †).
This
requirement
is
independent of the voltage limits discussed above.
One way to ensure the input currents are limited is to
always drive VIP with a low impedance source, and to
use a shunt resistor (RSH) with low resistance
(designed to not fail open). Placing zener diode(s) or a
transorb across RSH will also help protect the inputs.
Pin VIP
Pin VIM
(trace = RWIP
)
(trace = RWIM)
trace to VHV
trace to load
RSH
FIGURE 5-1:
PCB Layout for R
SH
(connections to V and V ).
IP
IM
DS20006179A-page 36
2019 Microchip Technology Inc.
MCP6C04
For accuracy, the wiring resistances at the DUT inputs
need to be small:
VDD
U1 (DUT)
U2 (ADC)
EQUATION 5-1:
MCP6C04
MCP3xxx
VIP
VIM
R
RWIP ≤ 4 mΩ
RWIM ≤ 0.1Ω
C
VOUT
R
5.1.5
SETTING THE VOLTAGE AT V
REF
VDD
For designs with VREF = VSS, short the VREF and VSS
pins together; connect them to ground (or other
reference) using one low impedance via (or trace). This
minimizes DC and AC errors.
RR
VREF
CR
For designs with VREF ≥ VSS + 0.1V, connect VREF and
VSS with a relatively large capacitor. Since VREF needs
a low impedance source, we recommend the following
two design approaches.
VSS
Use when VREF ≥ VSS + 0.1V
V Bypass Circuit #2.
REF
The DC resistance seen at VREF needs to be small.
This resistance includes trace resistance, via
resistance and output resistance of any driving
amplifiers. For good gain error in the signal band,
maintain this resistance in that band.
FIGURE 5-3:
Replacing Figure 5-3 with a simple resistor divider and
capacitor will cause potential issues. The equivalent
resistance needs to be low (see Equation 5-2), so the
divider will draw a lot of current. The capacitor will need
to be large, to set a reasonable pole, increasing cost
and PCB space.
EQUATION 5-2:
RWR ≤ 1Ω
We strongly recommend against designs with
VSS < VREF < VSS + 0.1V, since AC glitches may
become an problem.
The AC impedance seen at VREF needs to support
stability at frequencies near the bandwidth. See
Section 5.1.7.1, Driving VREF for more information.
5.1.6
TEMPERATURE RISE
Figure 5-2 shorts VREF and VSS together. The ADC
connects its negative input to VREF, so it can reject
glitches on VSS and VREF (notice only one connection
to VSS is shown, for good precision).
Make sure that TJ does not exceed the absolute
maximum junction temperature spec (see Section 1.1,
Absolute Maximum Ratings †). This is a strong
concern when TA is high (e.g., above 125°C), when
IOUT’s magnitude is large (e.g., near the short circuit
limit) or when VIP is high.
Figure 5-3 uses an IC VREF to generate VREF – VSS
,
an R-C low-pass filter to reject fast glitches seen at
VREF – VSS and an op amp buffer (≥ 1 MHz) to drive
VREF with a low impedance source (see Equation 1-2)
(notice only one connection to VSS is shown, for good
precision).
Formulas needed for this part of the design are found
in Section 4.1.5, Temperature Performance.
Temperature ramp rates need to be limited, for best
performance. The PCB and other components cause
external offset shifts, while the temperature ramp rate
is high.
VDD
U1 (DUT)
U2 (ADC)
MCP6C04
MCP3xxx
5.1.7
ENSURING STABILITY
VIP
VIM
A few simple design techniques will help take
advantage of these stable parts. Simulations and
bench measurements help to verify the solutions (e.g.,
look at step response overshoot and ringing).
R
R
C
VOUT
VSS
Use when VREF = VSS
FIGURE 5-2:
V
Bypass Circuit #1.
REF
2019 Microchip Technology Inc.
DS20006179A-page 37
MCP6C04
5.1.7.1
Driving V
REF
ꢁꢂ
ꢁꢃ
ꢄ
ꢁꢓꢂꢃꢃ
ꢁꢓꢃꢃꢃ
ꢄꢃꢃ
ꢅꢃꢃ
ꢆꢃꢃ
ꢂꢃꢃ
ꢃ
5,62 ꢉꢃ
The voltage source driving the VREF pin must be low
impedance (see Equation 1-2), so that the signal gain
is constant within the signal bandwidth.
*3.ꢉ± 6ROLGꢉ/LQHV
%:ꢉ± 'DVKHGꢉ/LQHV
When the frequency is near the bandwidth (e.g.,
between BW/4 and 4 BW), the source’s impedance
magnitude should be below 50Ω.
ꢅ
ꢆ
*
ꢉꢂꢃ
ꢉꢇꢃ
'0
*
'0
5.1.7.2
Source Impedances
*
ꢉꢁꢃꢃ
'0
ꢂ
The recommended DC source resistances (at VIP, VIM
and VREF; see Equation 5-2) will help ensure stability,
by keeping R-C time constants very fast.
ꢃ
ꢁS
ꢁꢃS
ꢁꢃꢃS
ꢁQ
ꢁꢃQ
ꢁꢃꢃQ
ꢁꢍ(ꢀꢁꢂ ꢁꢍ(ꢀꢁꢁ ꢁꢍ(ꢀꢁꢃ ꢁꢍ(ꢀꢃꢒ ꢁꢍ(ꢀꢃꢄ ꢁꢍ(ꢀꢃꢈ
&DSDFLWLYHꢉ/RDGꢊꢉ&/ ꢋ)ꢌ
FIGURE 5-5:
Bandwidth and Gain
5.1.7.3
Capacitive Loads
Peaking vs. Capacitive Load, without R
.
ISO
Driving large capacitive loads can cause stability
problems for voltage amplifiers. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth
reduces. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. Lower gains (GDM) exhibit greater sensitivity
to capacitive loads.
1.E+ 4
10k
1.E+03
1k
When driving large capacitive loads with these parts
(e.g., > 80 pF), a small series resistor at the output
(RISO in Figure 5-4) improves the feedback loop’s
phase margin (stability) by making the output load
resistive at higher frequencies. The bandwidth will be
generally lower than the bandwidth with no capacitive
load.
1.E+02
100
GDM = 100
G
G
DM = 50
DM = 20
1.E+01
10
10p
100p
1.E-10
1n
10n
1.E-08
100n
1.E-07
1.E-11
1.E-09
Capacitive Load; CL (F)
FIGURE 5-6:
Recommended R
vs.
ISO
Capacitive Load.
VDD
U1 (DUT)
5.1.8
NOISE DESIGN
MCP6C04
As shown in Figure 2-47 and Table 1-3, the input noise
voltage density is white (and low) at low frequencies.
This supports accurate averages (DC estimates) in
applications.
VIP
VOUT
RISO
CL
VIM
VREF
VSS
1/f noise is negligible for almost all applications. As a
result, the time domain data in Figure 2-50, Figure 2-51
and Figure 2-52 is well behaved.
FIGURE 5-4:
Recommended R
Values
ISO
Figure 2-47 also shows a curve of the Integrated Input
Noise Voltage (Eni, in units of VRMS) between 0 Hz and
f (between 0.1 Hz and 100 kHz). To estimate Eni
between the frequencies f1 and f2, simply take the RMS
for Capacitive Loads.
Figure 5-5 shows the typical responses versus CL,
when RISO is a short circuit (see Figure 2-58).
difference (i.e., Eni f1 to f2
= sqrt(Eni22 – Eni12)).
|
Figure 5-6 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
load capacitance (CL).
The Input Noise Voltage Density (eni) changes with
VDM; however, that it is a weak relationship, so it can be
neglected in designs.
After selecting RISO for the circuit, double check the
resulting frequency response peaking and step
response overshoot on the bench. Modify RISO’s value
until the response is reasonable.
Figure 5-7 and Figure 5-8 show the device noise as a
Signal-to-Noise ratio (SNR), assuming the signal is a
full-scale sine wave (at VOUT). The x-axis is the circuit’s
bandwidth (BW), to make it easy to evaluate a
particular design.
The input offset voltage is shown as a Signal-to-Offset
ratio (SVosR), to indicate where the DC offset
dominates the error.
DS20006179A-page 38
2019 Microchip Technology Inc.
MCP6C04
5.1.10
BIDIRECTIONAL APPLICATIONS
Figure 5-3 shows ways to connect VREF and VSS for
best performance.
130
120
110
100
90
VDD = 2.0V
Dashed Lines = SVosR
Solid Lines = SNR
To maximize headroom, reduce VOL and VOH by
setting RL high.
5.1.11
SUPPLY PINS
80
As described in Section 3.5 “Low-Side Power
Supplies (VDD, VSS)”, the ground potential (GND)
can be set where needed in your design. The most
common design approach has VSS = GND (positive
single supply). Other common design approaches
have VDD = GND (negative single supply) or
VSS < GND < VDD (dual, or split, supplies).
70
GDM = 20
GDM = 50
GDM = 100
60
50
1.E+0
1
10
1.E+1
100
1.E+2
1k
1.E+3
10k
1.E+4
100k
1.E+5
Bandwidth; f (Hz)
FIGURE 5-7:
Estimates, V = 2.0V.
SNR vs. Bandwidth
DD
Setting VSS = GND has the potential to increase
rejection of crosstalk and glitches. In any case, a good
ground design (e.g., ground plane on a PCB) and
appropriate bypass capacitors are needed to realize
these benefits. It pays to be sure that your capacitor's
voltage rating and dielectric will support your needs
over your voltage and temperature ranges. With some
dielectrics, it pays to also take aging (changes over
time) into account too.
130
120
110
100
90
VDD = 5.5V
Dashed Lines = SVosR
Solid Lines = SNR
80
70
GDM = 20
GDM = 50
60
GDM = 100
50
1
10
1.E+1
100
1.E+2
1k
1.E+3
10k
1.E+4
100k
1.E+5
1.E+0
Bandwidth; f (Hz)
FIGURE 5-8:
SNR vs. Bandwidth
Estimates, V = 5.5V.
DD
5.1.9
UNIDIRECTIONAL APPLICATIONS
In unidirectional applications where VREF = VSS, it is
important to minimize output headroom (VOL). The
lower VOL is, the more accurate the zero scale reading
is.
To reduce VOL, make IOUT as low as possible. This is
done by making RL high and by tying VL to VSS
.
Figure 5-2 shows how to connect VREF and VSS for
best performance.
2019 Microchip Technology Inc.
DS20006179A-page 39
MCP6C04
H-Bridge motor drive circuits can place their current
monitors in several positions. Figure 5-10 shows a few
possibilities:
5.2
Typical Application Circuits
The following circuits give guidance on using the
MCP6C04 within common applications. They leave out
details and the design requirements followed.
• Position A – This uses a unidirectional monitor
(MCP6C04 at VA1 and VA2), with current polarity
determined by the timing of the switches (SWLT,
etc.)
5.2.1
MOTOR CURRENT MONITORS
Figure 5-9 shows a simplified DC motor current monitor
circuit with a regulated voltage supply. The MCP6C04
and its circuit are all connected to the same ground, for
better glitch performance. In this case, since IL is
• Positions B and C – This uses two unidirectional
monitors (on MCP6C04 at VB1 and VB2 and the
other at VC1 and VC2), with each one representing
one current polarity
non-negative, we choose VREF = VSS
.
• Position D – This uses a bidirectional monitor
(MCP6C04 at VD1 and VD2), with current polarity
determined by the output
The ADC operates on a different supply; its ground will
be different due to I-R drops and glitches. The
differential input is tied to VREF, so that its CMRR can
reject differences between grounds.
- The monitor must function at and below
ground
- The monitor must withstand large switching
steps and glitches
+5V
- We caution that the MCP6C04 should not be
used in these conditions
2.2 µF
10 nF
U1 (DUT)
100 nF
+48V
MCP6C04-100
Obviously, choosing different locations for the
monitor(s) gives trade-offs in accuracy and complexity.
For instance, the monitor at Position D directly
measures the motor current, but will have large voltage
swings at its VIP pin.
RSH
VOUT
2.2 mΩ
20 kΩ
IL < 20A
VREF
The switches are discrete semiconductor switches
(i.e., CMOS, Bipolar, IGFET, etc.).
+5V
VHV
2.2 µF
U2 (ADC)
VA1
MCP3xxx
R
R
100 nF
VOUT
VREF
IA
RA
C
VA2
VC1
RC
VB1
RB
FIGURE 5-9:
Regulated Supply Voltage.
Motor Current Monitor for
IB
IC
VC2
VB2
SWLT
SWRT
VD2
ID
VD1
RD
SWLB
SWRB
FIGURE 5-10:
H-Bridge Motor Current
Monitor, With a Few Possible Monitor Locations.
DS20006179A-page 40
2019 Microchip Technology Inc.
MCP6C04
5.2.2
ANALOG LEVEL SHIFTER
The MCP6C04 can be used to shift analog voltages
from a high positive voltage down to a low voltage.
Many possibilities exist; Figure 5-11 is just one possible
implementation.
+5V
2.2 µF
10 nF
100 nF
V1
The input attenuator (R1 and R2) allow a wider range of
voltages to be measured. No resistor is placed
between V1 and the noninverting input, so that the input
current IBP doesn’t cause an offset shift. The attenuator
resistors' accuracy and values may affect the circuit's
gain error and offset.
R1
R2
VOUT
100 kΩ
V2
U1
MCP6C04
+2.5V
+5V
The +2.5V reference level allows bidirectional voltage
sensing; it needs to be very low impedance and reject
glitches on the supply or ground (see Figure 5-3 for
recommendations on this part of the circuit).
2.2 µF
U2
100 nF
MCP3xxx
VOUT
R
R
C
+2.5V
FIGURE 5-11:
Analog Level Shifter.
2019 Microchip Technology Inc.
DS20006179A-page 41
MCP6C04
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
6-Lead SOT-23
Example
Part Number
Code
MCP6C04T-020E/CHY
MCP6C04T-050E/CHY
MCP6C04T-100E/CHY
42
45
41
4247
Legend: XX...X Device-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available charac-
ters for customer-specific information.
DS20006179A-page 42
2019 Microchip Technology Inc.
MCP6C04
6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.15 C A-B
D
e1
A
D
E
2
E1
E
E1
2
2X
0.15 C D
2X
0.20 C A-B
e
B
6X b
0.20
C A-B D
TOP VIEW
A2
A
C
SEATING PLANE
6X
A1
c
0.10 C
SIDE VIEW
R1
R
L2
GAUGE PLANE
Ĭ
L
(L1)
END VIEW
Microchip Technology Drawing C04-028C (CH) Sheet 1 of 2
2019 Microchip Technology Inc.
DS20006179A-page 43
MCP6C04
6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
MIN
NOM
MAX
Number of Leads
Pitch
Outside lead pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
N
6
e
0.95 BSC
1.90 BSC
e1
A
A2
A1
E
E1
D
L
0.90
0.89
0.00
-
1.45
1.30
0.15
1.15
-
2.80 BSC
1.60 BSC
2.90 BSC
0.45
0.30
0.60
Footprint
Seating Plane to Gauge Plane
Foot Angle
Lead Thickness
Lead Width
L1
L1
φ
c
b
0.60 REF
0.25 BSC
-
0°
0.08
0.20
10°
0.26
0.51
-
-
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-028C (CH) Sheet 2 of 2
DS20006179A-page 44
2019 Microchip Technology Inc.
MCP6C04
6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
GX
Y
Z
C
G
G
SILK SCREEN
X
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
MIN
NOM
0.95 BSC
2.80
MAX
Contact Pitch
E
C
Contact Pad Spacing
Contact Pad Width (X3)
Contact Pad Length (X3)
Distance Between Pads
Distance Between Pads
Overall Width
X
Y
G
GX
Z
0.60
1.10
1.70
0.35
3.90
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2028B (CH)
2019 Microchip Technology Inc.
DS20006179A-page 45
MCP6C04
NOTES:
DS20006179A-page 46
2019 Microchip Technology Inc.
MCP6C04
APPENDIX A: REVISION HISTORY
Revision A (March 2019)
• Initial release of this document.
2019 Microchip Technology Inc.
DS20006179A-page 47
MCP6C04
NOTES:
2019 Microchip Technology Inc.
DS20006179A-page 48
MCP6C04
We use production screens to support the quality of our
VOS specification in outgoing products. The screen
limits are wider and are used to eliminate fliers; see
Table B-1.
APPENDIX B: OFFSET TEST
SCREENS
Input offset voltage specifications in the DC spec table
(Table 1-1) are based on bench measurements (see
Section 2.1, DC Precision). These measurements are
much more accurate than at test, because:
• More compact circuit
• Parts soldered on the PCB
• More time spent averaging (reduced noise)
• Better temperature control
- Reduced temperature gradients
- Greater accuracy
TABLE B-1:
OFFSET TEST SCREENS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 2.0V to 5.5V, VSS = GND, VIP = 27.5V,
VDM = 0V, VREF = VDD/4, VL = VDD/2 and RL = 10 kΩ to VL; see Figure 1-9 and Figure 1-10.
Parameters
Sym.
Min.
Max.
Units
Gain
Conditions
Test Screen
Input Offset Voltage
VOS
-36
-33
-30
+36
+33
+30
μV
20
50
100
2019 Microchip Technology Inc.
DS20006179A-page 49
MCP6C04
NOTES:
2019 Microchip Technology Inc.
DS20006179A-page 50
MCP6C04
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
(1)
Examples:
-XXX
X
/XXX
[X]
PART NO.
Device
a) MCP6C04T-020E/CHY: Tape and Reel,
Differential Gain = 20,
Gain Option
Temperature
Range
Package
Tape and Reel
Option
Extended Temperature,
6LD SOT-23
b) MCP6C04T-050E/CHY: Tape and Reel,
Device:
MCP6C04: Zero-Drift, 52V High-Side Current Sense Amp
Differential Gain = 50,
Extended Temperature,
6LD SOT-23
(1)
Tape and Reel
Option:
T
= Tape and Reel
c) MCP6C04T-100E/CHY: Tape and Reel,
Differential Gain = 100,
Extended Temperature,
6LD SOT-23
Gain Option:
020
050
100
= Differential Gain of 20 V/V
= Differential Gain of 50 V/V
= Differential Gain of 100 V/V
Temperature
Range:
E
=
=
-40°C to +125°C (Extended))
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This identifier
is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
Package:
CHY
Plastic Small Outline Transistor (SOT-23), 6-Lead
2019 Microchip Technology Inc.
DS20006179A-page 51
MCP6C04
NOTES:
DS20006179A-page 52
2019 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
© 2019, Microchip Technology Incorporated, All Rights
Reserved.
ISBN: 978-1-5224-4265-3
== ISO/TS 16949 ==
2019 Microchip Technology Inc.
DS20006179A-page 53
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Australia - Sydney
Tel: 61-2-9868-6733
India - Bangalore
Tel: 91-80-3090-4444
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Beijing
Tel: 86-10-8569-7000
India - New Delhi
Tel: 91-11-4160-8631
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
China - Chengdu
Tel: 86-28-8665-5511
India - Pune
Tel: 91-20-4121-0141
Finland - Espoo
Tel: 358-9-4520-820
China - Chongqing
Tel: 86-23-8980-9588
Japan - Osaka
Tel: 81-6-6152-7160
Web Address:
www.microchip.com
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
China - Dongguan
Tel: 86-769-8702-9880
Japan - Tokyo
Tel: 81-3-6880- 3770
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
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Tel: 86-20-8755-8029
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Tel: 82-53-744-4301
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Tel: 49-8931-9700
China - Hangzhou
Tel: 86-571-8792-8115
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Tel: 82-2-554-7200
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Tel: 49-2129-3766400
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Tel: 512-257-3370
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Tel: 852-2943-5100
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Tel: 49-7131-67-3636
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Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
China - Nanjing
Tel: 86-25-8473-2460
Malaysia - Penang
Tel: 60-4-227-8870
Germany - Karlsruhe
Tel: 49-721-625370
China - Qingdao
Philippines - Manila
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Tel: 86-532-8502-7355
Tel: 63-2-634-9065
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Fax: 630-285-0075
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Tel: 86-24-2334-2829
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Tel: 886-3-577-8366
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Addison, TX
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Fax: 972-818-2924
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Tel: 86-755-8864-2200
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Tel: 886-7-213-7830
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Tel: 39-0331-742611
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Tel: 886-2-2508-8600
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Thailand - Bangkok
Tel: 66-2-694-1351
Italy - Padova
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Netherlands - Drunen
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Fax: 31-416-690340
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Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
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Tel: 86-592-2388138
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Tel: 86-756-3210040
Poland - Warsaw
Tel: 48-22-3325737
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Tel: 949-462-9523
Fax: 949-462-9608
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Tel: 40-21-407-87-50
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Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
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Tel: 919-844-7510
Sweden - Gothenberg
Tel: 46-31-704-60-40
New York, NY
Tel: 631-435-6000
Sweden - Stockholm
Tel: 46-8-5090-4654
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS20006179A-page 54
2019 Microchip Technology Inc.
08/15/18
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