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MCP6V28-EMS [MICROCHIP]

620 μA, 2 MHz Auto-Zeroed Op Amps;
MCP6V28-EMS
型号： MCP6V28-EMS
厂家： MICROCHIP    MICROCHIP
描述：

620 μA, 2 MHz Auto-Zeroed Op Amps
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MCP6V26/7/8  
620 µA, 2 MHz Auto-Zeroed Op Amps  
Features  
Description  
• High DC Precision:  
The Microchip Technology Inc. MCP6V26/7/8 family of  
operational amplifiers provides input offset voltage  
correction for very low offset and offset drift. These  
devices have a wide gain bandwidth product (2 MHz,  
typical) and strongly reject switching noise. They are  
unity gain stable, have no 1/f noise, and have good  
power supply rejection ratio (PSRR) and common  
mode rejection ratio (CMRR). These products operate  
with a single supply voltage as low as 2.3V, while  
drawing 620 µA/amplifier (typical) of quiescent current.  
- VOS Drift: ±50 nV/°C (maximum)  
- VOS: ±2 µV (maximum)  
- AOL: 125 dB (minimum)  
- PSRR: 125 dB (minimum)  
- CMRR: 120 dB (minimum)  
- Eni: 1.0 µVP-P (typical), f = 0.1 Hz to 10 Hz  
- Eni: 0.32 µVP-P (typical), f = 0.01 Hz to 1 Hz  
• Low Power and Supply Voltages:  
- IQ: 620 µA/amplifier (typical)  
- Wide Supply Voltage Range: 2.3V to 5.5V  
• Easy to Use:  
The Microchip Technology Inc. MCP6V26/7/8 op amps  
are offered as a single (MCP6V26), single with Chip  
Select (CS) (MCP6V28) and dual (MCP6V27). They  
were designed using an advanced CMOS process.  
- Rail-to-Rail Input/Output  
- Gain Bandwidth Product: 2 MHz (typical)  
- Unity Gain Stable  
Package Types (top view)  
MCP6V26  
MCP6V26  
- Available in Single and Dual  
- Single with Chip Select (CS): MCP6V28  
• Extended Temperature Range: -40°C to +125°C  
MSOP, SOIC  
2×3 TDFN *  
NC  
8
NC  
NC  
1
8
1
2
3
4
NC  
VDD  
VOUT  
NC  
7
6
5
VIN–  
VIN+  
VSS  
VDD  
VOUT  
NC  
VIN–  
VIN+  
VSS  
2
3
4
7
6
5
EP  
9
Typical Applications  
• Portable Instrumentation  
• Sensor Conditioning  
MCP6V27  
MSOP, SOIC  
MCP6V27  
4×4 DFN *  
• Temperature Measurement  
• DC Offset Correction  
VDD  
1
2
3
4
8
7
6
5
VDD  
VOUTA  
VOUTA  
1
8
7
6
5
VOUTB  
VINA  
VINA  
–
+
VOUTB  
2
3
4
VINA–  
EP  
9
• Medical Instrumentation  
VINB  
VINB  
–
+
VINB  
VINB  
–
+
VINA+  
VSS  
VSS  
Design Aids  
• SPICE Macro Models  
• FilterLab® Software  
MCP6V28  
MSOP, SOIC  
MCP6V28  
2×3 TDFN *  
• Microchip Advanced Part Selector (MAPS)  
• Analog Demonstration and Evaluation Boards  
• Application Notes  
NC  
CS  
1
8
CS  
NC 1  
8
7
6
5
VIN–  
VIN+  
VSS  
VDD  
2
3
4
7
6
5
VDD  
2
3
4
VIN–  
VIN+  
VSS  
EP  
9
VOUT  
NC  
VOUT  
NC  
Related Parts  
* Includes Exposed Thermal Pad (EP); see Table 3-1.  
Parts with lower power, lower bandwidth and higher  
noise:  
• MCP6V01/2/3: Spread clock  
• MCP6V06/7/8: Non-spread clock  
© 2011 Microchip Technology Inc.  
DS25007B-page 1  
MCP6V26/7/8  
Typical Application Circuit  
10 kΩ  
10 kΩ  
VIN  
VOUT  
10 kΩ  
10 nF  
500 kΩ  
5 kΩ  
U2  
MCP661  
10 kΩ  
VDD/2  
U1  
MCP6V26  
VDD/2  
Offset Voltage Correction for Power Driver  
DS25007B-page 2  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
† Notice: Stresses above those listed under “Absolute  
Maximum Ratings” may cause permanent damage to  
the device. This is a stress rating only and functional  
operation of the device at those or any other  
conditions above those indicated in the operational  
listings of this specification is not implied. Exposure to  
maximum rating conditions for extended periods may  
affect device reliability.  
1.0  
1.1  
ELECTRICAL  
CHARACTERISTICS  
Absolute Maximum Ratings †  
V
– V ..............................................................................6.5V  
SS  
DD  
Current at Input Pins †† ......................................................±2 mA  
Analog Inputs (V + and V –) †† .......... V – 1.0V to V +1.0V  
IN  
IN  
SS  
DD  
All other Inputs and Outputs .................. V – 0.3V to V +0.3V  
†† See Section 4.2.1, Rail-to-Rail Inputs.  
SS  
DD  
Difference Input voltage ............................................. |V – V  
|
SS  
DD  
Output Short Circuit Current .......................................Continuous  
Current at Output and Supply Pins ...................................±30 mA  
Storage Temperature ..........................................-65°C to +150°C  
Max. Junction Temperature ..............................................+150°C  
ESD protection on all pins (HBM, CDM, MM) ≥ 4 kV,1.5 kV, 300V  
1.2  
Specifications  
DC ELECTRICAL SPECIFICATIONS  
TABLE 1-1:  
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND,  
VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CS = GND (refer to Figure 1-5 and Figure 1-6).  
Parameters  
Sym  
Min  
Typ  
Max  
Units  
Conditions  
Input Offset  
Input Offset Voltage  
VOS  
TC1  
-2  
—
—
+2  
µV  
TA = +25°C (Note 1)  
Input Offset Voltage Drift  
-50  
+50  
nV/°C TA = -40 to +125°C  
with Temperature (linear Temp. Co.)  
(Note 1)  
Input Offset Voltage Quadratic  
Temperature Coefficient  
TC2  
—
±0.2  
142  
—
—
nV/°C2 TA = -40 to +125°C  
Power Supply Rejection  
Input Bias Current and Impedance  
Input Bias Current  
PSRR  
125  
dB  
(Note 1)  
IB  
IB  
—
—
+7  
—
—
pA  
pA  
Input Bias Current across  
Temperature  
+110  
TA = +85°C  
IB  
—
—
—
+1.2  
±70  
±50  
+5  
—
—
nA  
pA  
pA  
TA = +125°C  
Input Offset Current  
IOS  
IOS  
Input Offset Current across  
Temperature  
TA = +85°C  
IOS  
ZCM  
—
—
—
±60  
—
—
—
pA  
TA = +125°C  
Common Mode Input Impedance  
Differential Input Impedance  
1013||12  
1013||12  
Ω||pF  
Ω||pF  
ZDIFF  
Note 1: Set by design and characterization. Due to thermal junction and other effects in the production  
environment, these parts can only be screened in production (except TC1; see Appendix B: “Offset  
Related Test Screens”).  
2: Figure 2-18 shows how VCML and VCMH changed across temperature for the first production lot.  
© 2011 Microchip Technology Inc.  
DS25007B-page 3  
MCP6V26/7/8  
TABLE 1-1:  
DC ELECTRICAL SPECIFICATIONS (CONTINUED)  
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND,  
VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CS = GND (refer to Figure 1-5 and Figure 1-6).  
Parameters  
Common Mode  
Sym  
Min  
Typ  
Max  
Units  
Conditions  
Common-Mode Input  
Voltage Range Low  
VCML  
—
—
—
VSS − 0.15  
V
V
(Note 2)  
Common-Mode Input  
Voltage Range High  
VCMH VDD + 0.2  
—
—
(Note 2)  
Common-Mode Rejection  
CMRR  
CMRR  
120  
125  
136  
dB  
VDD = 2.3V,  
VCM = -0.15V to 2.5V  
(Note 1, Note 2)  
142  
—
dB  
VDD = 5.5V,  
VCM = -0.15V to 5.7V  
(Note 1, Note 2)  
Open-Loop Gain  
DC Open-Loop Gain (large signal)  
AOL  
125  
133  
147  
155  
—
—
dB  
dB  
VDD = 2.3V,  
VOUT = 0.2V to 2.1V  
(Note 1)  
AOL  
VDD = 5.5V,  
VOUT = 0.2V to 5.3V  
(Note 1)  
Output  
Minimum Output Voltage Swing  
VOL  
VOH  
—
VSS + 5 VSS + 15  
mV G = +2, 0.5V  
input overdrive  
Maximum Output Voltage Swing  
Output Short Circuit Current  
VDD – 15 VDD − 5  
—
mV G = +2, 0.5V  
input overdrive  
ISC  
ISC  
—
—
±12  
±22  
—
—
mA VDD = 2.3V  
mA VDD = 5.5V  
Power Supply  
Supply Voltage  
VDD  
IQ  
2.3  
450  
1.15  
—
620  
—
5.5  
800  
1.65  
V
Quiescent Current per amplifier  
POR Trip Voltage  
µA  
V
IO = 0  
VPOR  
Note 1: Set by design and characterization. Due to thermal junction and other effects in the production  
environment, these parts can only be screened in production (except TC1; see Appendix B: “Offset  
Related Test Screens”).  
2: Figure 2-18 shows how VCML and VCMH changed across temperature for the first production lot.  
DS25007B-page 4  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
TABLE 1-2:  
AC ELECTRICAL SPECIFICATIONS  
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND,  
VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND (refer to Figure 1-5 and  
Figure 1-6).  
Parameters  
Sym Min Typ Max  
Units  
Conditions  
Amplifier AC Response  
Gain Bandwidth Product  
Slew Rate  
GBWP  
SR  
—
—
—
2.0  
1.0  
65  
—
—
—
MHz  
V/µs  
°
Phase Margin  
PM  
G = +1  
Amplifier Noise Response  
Input Noise Voltage  
Eni  
Eni  
eni  
eni  
ini  
—
—
—
—
—
0.32  
1.0  
50  
—
—
—
—
—
µVP-P f = 0.01 Hz to 1 Hz  
µVP-P f = 0.1 Hz to 10 Hz  
nV/√Hz f < 5 kHz  
nV/√Hz f = 100 kHz  
fA/√Hz  
Input Noise Voltage Density  
29  
Input Noise Current Density  
Amplifier Distortion (Note 1)  
Intermodulation Distortion (AC)  
0.6  
IMD  
—
40  
—
µVPK  
VCM tone = 50 mVPK at 1 kHz,  
GN = 1  
Amplifier Step Response  
Start Up Time  
tSTR  
tSTL  
—
—
—
75  
150  
45  
—
—
—
µs  
µs  
µs  
G = +1, VOS within 50 µV of its final value  
(Note 2)  
Offset Correction Settling Time  
Output Overdrive Recovery Time  
G = +1, VIN step of 2V,  
VOS within 50 µV of its final value  
tODR  
G = -100, ±0.5V input overdrive to VDD/2,  
VIN 50% point to VOUT 90% point  
(Note 3)  
Note 1: These parameters were characterized using the circuit in Figure 1-7. In Figure 2-37 and Figure 2-38, there  
is an IMD tone at DC, a residual tone at 1 kHz, other IMD tones and clock tones.  
2: High gains behave differently; see Section 4.3.3, Offset at Power Up.  
3: tODR includes some uncertainty due to clock edge timing.  
© 2011 Microchip Technology Inc.  
DS25007B-page 5  
MCP6V26/7/8  
TABLE 1-3:  
DIGITAL ELECTRICAL SPECIFICATIONS  
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND,  
VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kW to VL, CL = 60 pF, and CS = GND (refer to Figure 1-5 and  
Figure 1-6).  
Parameters  
Sym  
Min  
Typ  
Max Units  
Conditions  
CS Pull-Down Resistor (MCP6V28)  
CS Pull-Down Resistor  
RPD  
3
5
—
MΩ  
CS Low Specifications (MCP6V28)  
CS Logic Threshold, Low  
VIL  
VSS  
—
—
5
0.3VDD  
—
V
CS Input Current, Low  
ICSL  
pA  
CS = VSS  
CS = VDD  
CS High Specifications (MCP6V28)  
CS Logic Threshold, High  
VIH  
ICSH  
ISS  
0.7VDD  
—
—
VDD  
—
V
CS Input Current, High  
VDD/RPD  
pA  
CS Input High,  
—
—
—
-0.4  
-1  
—
—
—
µA  
µA  
pA  
CS = VDD, VDD = 2.3V  
CS = VDD, VDD = 5.5V  
CS = VDD  
GND Current per amplifier  
ISS  
Amplifier Output Leakage,  
CS High  
IO_LEAK  
20  
CS Dynamic Specifications (MCP6V28)  
CS Low to Amplifier Output On  
Turn-on Time  
tON  
—
—
—
4
1
50  
—
—
µs  
µs  
V
CS Low = VSS+0.3 V, G = +1 V/V,  
VOUT = 0.9 VDD/2  
CS High to Amplifier Output  
High-Z  
tOFF  
CS High = VDD – 0.3 V, G = +1 V/V,  
VOUT = 0.1 VDD/2  
Internal Hysteresis  
VHYST  
0.2  
TABLE 1-4:  
TEMPERATURE SPECIFICATIONS  
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.3V to +5.5V, VSS = GND.  
Parameters  
Temperature Ranges  
Sym  
Min  
Typ  
Max  
Units  
Conditions  
Specified Temperature Range  
Operating Temperature Range  
Storage Temperature Range  
TA  
TA  
TA  
-40  
-40  
-65  
—
—
—
+125  
+125  
+150  
°C  
°C  
°C  
(Note 1)  
Thermal Package Resistances  
Thermal Resistance, 8L-4x4 DFN  
θJA  
θJA  
θJA  
θJA  
—
—
—
—
48  
211  
150  
53  
—
—
—
—
°C/W (Note 2)  
°C/W  
Thermal Resistance, 8L-MSOP  
Thermal Resistance, 8L-SOIC  
Thermal Resistance, 8L-2x3 TDFN  
°C/W  
°C/W (Note 2)  
Note 1: Operation must not cause TJ to exceed Maximum Junction Temperature specification (+150°C).  
2: Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.  
DS25007B-page 6  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
1.3  
Timing Diagrams  
1.4  
Test Circuits  
The circuits used for the DC and AC tests are shown in  
Figure 1-5 and Figure 1-6. Lay the bypass capacitors  
out as discussed in Section 4.3.10, Supply Bypass-  
ing and Filtering. RN is equal to the parallel combina-  
tion of RF and RG to minimize bias current effects.  
2.3V to 5.5V  
2.3V  
0V  
VDD  
tSTR  
VOS + 50 µV  
VOS – 50 µV  
VOS  
VDD  
1 µF  
RN  
VIN  
RISO  
CL  
VOUT  
U1  
FIGURE 1-1:  
Amplifier Start Up.  
MCP6V2X  
RL  
100 nF  
RF  
VDD/3  
VIN  
VL  
RG  
tSTL  
VOS + 50 µV  
OS + 50 µV  
FIGURE 1-5:  
Most Non-Inverting Gain Conditions.  
AC and DC Test Circuit for  
VOS  
V
VDD  
1 µF  
FIGURE 1-2:  
Time.  
Offset Correction Settling  
RN  
VDD/3  
RISO  
CL  
VOUT  
U1  
MCP6V2X  
RL  
VIN  
100 nF  
RF  
VIN  
tODR  
VL  
RG  
VDD  
FIGURE 1-6:  
AC and DC Test Circuit for  
Most Inverting Gain Conditions.  
tODR  
VOUT  
The circuit in Figure 1-7 tests the op amp input’s  
dynamic behavior (i.e., IMD, tSTR, tSTL and tODR). The  
potentiometer balances the resistor network (VOUT  
should equal VREF at DC). The op amp’s common  
mode input voltage is VCM = VIN/2. The error at the  
input (VERR) appears at VOUT with a noise gain of  
10 V/V.  
VDD/2  
VSS  
FIGURE 1-3:  
Output Overdrive Recovery.  
CS  
VIL  
VIH  
tON  
tOFF  
20.0 kΩ 20.0 kΩ 50Ω  
0.1%  
0.1% 25 turn  
VREF  
VOUT  
High-Z  
1 µA  
High-Z  
1 µA  
VDD  
1 µF  
(typical)  
(typical)  
300 µA  
IDD  
(typical)  
300 µA  
RISO  
CL  
VOUT  
RL  
VIN  
(typical)  
-2 µA  
(typical)  
-2 µA  
ISS  
100 nF  
(typical)  
5 pA  
(typical)  
MCP6V2X  
U1  
VL  
ICS  
VDD/5 MΩ  
(typical)  
VDD/5 MΩ  
(typical)  
20.0 kΩ  
0.1%  
20.0 kΩ 24.9 Ω  
0.1%  
FIGURE 1-4:  
Chip Select (MCP6V28).  
FIGURE 1-7:  
Test Circuit for Dynamic  
Input Behavior.  
© 2011 Microchip Technology Inc.  
DS25007B-page 7  
MCP6V26/7/8  
2.0  
TYPICAL PERFORMANCE CURVES  
Note:  
The graphs and tables provided following this note are a statistical summary based on a limited number of  
samples and are provided for informational purposes only. The performance characteristics listed herein  
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified  
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.  
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND.  
2.1  
DC Input Precision  
40%  
20 Samples  
A = +25°C  
VDD = 2.3V and 5.5V  
35%  
30%  
25%  
20%  
15%  
10%  
5%  
T
0%  
Input Offset Voltage (µV)  
FIGURE 2-1:  
Input Offset Voltage.  
FIGURE 2-4:  
Input Offset Voltage vs.  
Power Supply Voltage with VCM = VCML  
.
30%  
20 Samples  
VDD = 2.3V and 5.5V  
25%  
20%  
15%  
10%  
5%  
0%  
Input Offset Voltage Drift; TC1 (nV/°C)  
FIGURE 2-2:  
Input Offset Voltage Drift.  
FIGURE 2-5:  
Input Offset Voltage vs.  
Power Supply Voltage with VCM = VCMH  
.
5
Representative Part  
4
3
2
VDD = 2.3V  
1
0
VDD = 5.5V  
-1  
-2  
-3  
-4  
-5  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Output Voltage (V)  
FIGURE 2-3:  
Quadratic Temperature Coefficient.  
Input Offset Voltage  
FIGURE 2-6:  
Output Voltage.  
Input Offset Voltage vs.  
DS25007B-page 8  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND.  
5
4
30%  
25%  
20%  
15%  
10%  
5%  
VDD = 2.3V  
Representative Part  
20 Samples  
TA = +25°C  
3
2
1
0
-1  
-2  
-3  
-4  
-5  
-40°C  
+25°C  
+85°C  
+125°C  
0%  
-0.5  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
Input Common Mode Voltage (V)  
1/PSRR (µV/V)  
FIGURE 2-7:  
Input Offset Voltage vs.  
FIGURE 2-10:  
PSRR.  
Common Mode Voltage with VDD = 2.3V.  
100%  
5
20 Samples  
TA = +25°C  
-40°C  
+25°C  
+85°C  
+125°C  
VDD = 5.5V  
Representative Part  
90%  
80%  
70%  
60%  
50%  
40%  
30%  
20%  
10%  
0%  
4
3
2
1
VDD = 5.5V  
VDD = 2.3V  
0
-1  
-2  
-3  
-4  
-5  
Input Common Mode Voltage (V)  
1/AOL (µV/V)  
FIGURE 2-8:  
Input Offset Voltage vs.  
FIGURE 2-11:  
DC Open-Loop Gain.  
Common Mode Voltage with VDD = 5.5V.  
35%  
160  
155  
150  
145  
140  
20 Samples  
TA = +25°C  
30%  
PSRR  
25%  
20%  
VDD = 5.5V  
VDD = 2.3V  
15%  
10%  
5%  
135  
CMRR  
VDD = 5.5V  
VDD = 2.3V  
130  
125  
120  
0%  
-50  
-25  
0
25  
50  
75  
100  
125  
Ambient Temperature (°C)  
1/CMRR (µV/V)  
FIGURE 2-9:  
CMRR.  
FIGURE 2-12:  
CMRR and PSRR vs.  
Ambient Temperature.  
© 2011 Microchip Technology Inc.  
DS25007B-page 9  
MCP6V26/7/8  
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND.  
10n  
10,
160  
155  
150  
145  
140  
135  
130  
125  
120  
VDD = 5.5V  
1n  
1,0
VDD = 5.5V  
DD = 2.3V  
V
-IOS  
100p  
10p  
IB  
1p  
-50  
-25  
0
25  
50  
75  
100  
125  
25 35 45 55 65 75 85 95 105 115 125  
Ambient Temperature (°C)  
Ambient Temperature (°C)  
FIGURE 2-13:  
DC Open-Loop Gain vs.  
FIGURE 2-16:  
Input Bias and Offset  
Ambient Temperature.  
Currents vs. Ambient Temperature with  
VDD = +5.5V.  
200  
1.E-02  
10m  
TA = +85°C  
V
DD = 5.5V  
1.E-03  
1m  
150  
100  
50  
1.E-04  
100µ  
1.E-05  
10µ  
IB  
1.E-06  
1µ  
1.E- 7  
100n  
0
1.E- 8  
10n  
+125°C  
+85°C  
+25°C  
-40°C  
IOS  
1.E-10n9  
1.1E0-10p0  
-50  
-100  
10p  
1.E-11  
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0  
Input Voltage (V)  
Common Mode Input Voltage (V)  
FIGURE 2-14:  
Input Bias and Offset  
FIGURE 2-17:  
Input Bias Current vs. Input  
Currents vs. Common Mode Input Voltage with  
TA = +85°C.  
Voltage (below VSS).  
2000  
TA = +125°C  
1800  
VDD = 5.5V  
1600  
1400  
1200  
1000  
800  
600  
400  
200  
0
IB  
IOS  
-200  
-400  
Common Mode Input Voltage (V)  
FIGURE 2-15:  
Input Bias and Offset  
Currents vs. Common Mode Input Voltage with  
TA = +125°C.  
DS25007B-page 10  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND.  
2.2  
Other DC Voltages and Currents  
0.4  
40  
30  
1 Wafer Lot  
-40°C  
+25°C  
+85°C  
+125°C  
0.3  
0.2  
Upper ( VCMH – VDD  
)
20  
10  
0.1  
0
0.0  
-10  
-20  
-30  
-40  
-0.1  
-0.2  
-0.3  
-0.4  
+125°C  
+85°C  
+25°C  
-40°C  
Lower (VCML – VSS  
)
-50  
-25  
0
25  
50  
75  
100 125  
Ambient Temperature (°C)  
Power Supply Voltage (V)  
FIGURE 2-18:  
Input Common Mode  
FIGURE 2-21:  
Output Short Circuit Current  
Voltage Headroom (Range) vs. Ambient  
Temperature.  
vs. Power Supply Voltage.  
800  
700  
600  
500  
400  
1000  
VDD = 5.5V  
VDD = 2.3V  
100  
+125°C  
+85°C  
+25°C  
-40°C  
VDD – VOH  
300  
200  
100  
0
VOL – VSS  
10  
0.1  
1
10  
Power Supply Voltage (V)  
Output Current Magnitude (mA)  
FIGURE 2-22:  
Supply Current vs. Power  
FIGURE 2-19:  
Output Voltage Headroom  
Supply Voltage.  
vs. Output Current.  
40%  
10  
820 Samples  
1 Wafer Lot  
TA = +25°C  
RL = 10 kΩ  
9
35%  
30%  
25%  
20%  
15%  
10%  
5%  
8
7
6
VDD = 5.5V  
VDD – VOH  
5
4
3
VOL – VSS  
2
VDD = 2.3V  
1
0
0%  
-50  
-25  
0
25  
50  
75  
100  
125  
POR Trip Voltage (V)  
Ambient Temperature (°C)  
FIGURE 2-23:  
Power On Reset Trip  
FIGURE 2-20:  
Output Voltage Headroom  
Voltage.  
vs. Ambient Temperature.  
© 2011 Microchip Technology Inc.  
DS25007B-page 11  
MCP6V26/7/8  
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND.  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
-50  
-25  
0
25  
50  
75  
100  
125  
Ambient Temperature (°C)  
FIGURE 2-24:  
Power On Reset Voltage vs.  
Ambient Temperature.  
DS25007B-page 12  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND.  
2.3  
Frequency Response  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
100  
90  
80  
70  
60  
50  
40  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
VDD = 5.5V  
VDD = 2.3V  
GBWP  
CMRR  
PM  
PSRR+  
PSRR-  
100  
1.E+02  
10k  
100k  
1.E+05  
1M  
1.E+06  
1k  
-50 -25  
0
25  
50  
75 100
 
125  
1.E+03  
1.E+04  
Frequency (Hz)  
Ambient Temperature (°C)  
FIGURE 2-25:  
CMRR and PSRR vs.  
FIGURE 2-28:  
Gain Bandwidth Product  
Frequency.  
and Phase Margin vs. Ambient Temperature.  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
120  
110  
100  
90  
70  
60  
50  
40  
30  
20  
10  
0
0
VDD = 2.3V  
CL = 60 pF  
-30  
-60  
VDD = 5.5V  
GBWP  
PM  
∠
AOL  
-90  
VDD = 2.3V  
-120  
-150  
-180  
-210  
-240  
-270  
80  
70  
| AOL  
|
60  
50  
-10  
40  
-20  
1k  
10k  
100k  
1.E+05  
Frequency (Hz)  
1M  
1.E+06  
10M  
1.E+03  
1.E+04  
1.E+07  
Common Mode Input Voltage (V)  
FIGURE 2-26:  
Open-Loop Gain vs.  
FIGURE 2-29:  
Gain Bandwidth Product  
Frequency with VDD = 2.3V.  
and Phase Margin vs. Common Mode Input  
Voltage.  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
120  
70  
60  
50  
40  
30  
20  
0
VDD = 5.5V  
CL = 60 pF  
110  
100  
90  
-30  
-60  
VDD = 2.3V  
PM  
VDD = 5.5V  
-90  
∠
AOL  
-120  
-150  
-180  
-210  
-240  
-270  
80  
70  
10  
| AOL  
|
60  
0
-10  
-20  
GBWP  
50  
40  
10M  
1k  
10k  
1.E+04  
100k  
1.E+05  
Frequency (Hz)  
1M  
1.E+06  
1.E+03  
1.E+07  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Output Voltage (V)  
FIGURE 2-27:  
Open-Loop Gain vs.  
FIGURE 2-30:  
Gain Bandwidth Product  
Frequency with VDD = 5.5V.  
and Phase Margin vs. Output Voltage.  
© 2011 Microchip Technology Inc.  
DS25007B-page 13  
MCP6V26/7/8  
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND.  
1.E+04  
10k  
VDD = 2.3V  
1.E+03  
1k  
1.E+10020  
10  
1.E+01  
G = 1 V/V  
G = 11 V/V  
G = 101 V/V  
1
1.E+00  
100k  
1M  
1.0E+06  
Frequency (Hz)  
10M  
1.0E+07  
100M  
1.0E+08  
1.0E+05  
FIGURE 2-31:  
Closed-Loop Output  
FIGURE 2-33:  
Channel-to-Channel  
Impedance vs. Frequency with VDD = 2.3V.  
Separation vs. Frequency.  
1.E+04  
10k  
10  
VDD = 2.3V  
VDD = 5.5V  
E+03  
1k  
VDD = 2.3V  
E+02  
100  
1
E+01  
10  
G = 1 V/V  
G = 11 V/V  
G = 101 V/V  
0.1  
1.E+00  
1
1k  
10k  
1.E+04  
100k  
1.E+05  
1M  
1.E+06  
1.E+03  
100k  
1.0E+05  
1M  
1.0E+06  
10M  
1.0E+07  
100M  
1.0E+08  
Frequency (Hz)  
Frequency (Hz)  
FIGURE 2-32:  
Closed-Loop Output  
FIGURE 2-34:  
Maximum Output Voltage  
Impedance vs. Frequency with VDD = 5.5V.  
Swing vs. Frequency.  
DS25007B-page 14  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND.  
2.4  
Input Noise and Distortion  
10,000  
1,000  
100  
10  
100  
10  
1
IMD tone at DC  
1 kHz tone  
VDD = 5.5V  
VDD = 5.5V  
DD = 2.3V  
V
1,000  
100  
10  
V
DD = 2.3V  
eni  
GDM = 1 V/V  
VDD tone = 50 mVP-P  
,
f = 1 kHz  
Eni(0 Hz to f)  
1k  
0.1  
1
100  
1k  
1.E+03  
10k  
1.E+04  
100k  
1.E+05  
10  
100  
10k  
100k  
1.E+02  
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05  
Frequency (Hz)  
Frequency (Hz)  
FIGURE 2-35:  
Input Noise Voltage Density  
FIGURE 2-38:  
Intermodulation Distortion  
and Integrated Input Noise Voltage vs.  
Frequency.  
vs. Frequency with VDD Disturbance (see  
Figure 1-7).  
100  
90  
VDD = 2.3V  
f < 5 kHz  
80  
70  
60  
50  
40  
30  
20  
10  
0
VDD = 5.5V  
VDD = 2.3V  
NPBW = 10 Hz  
NPBW = 1 Hz  
0
10 20 30 40 50 60 70 80 90 100  
t (s)  
Common Mode Input Voltage (V)  
FIGURE 2-36:  
Input Noise Voltage Density  
FIGURE 2-39:  
Input Noise vs. Time with  
vs. Input Common Mode Voltage.  
1 Hz and 10 Hz Filters and VDD =2.3V.  
100  
VDD = 5.5V  
IMD tone at DC  
residual 1 kHz tone  
10  
VDD = 2.3V  
VDD = 5.5V  
1
NPBW = 10 Hz  
NPBW = 1 Hz  
GDM = 1 V/V  
VCM tone = 50 mVPK, f = 1 kHz  
0.1  
100  
1k  
1.E+03  
10k  
1.E+04  
100k  
1.E+05  
0
10 20 30 40 50 60 70 80 90 100  
t (s)  
1.E+02  
Frequency (Hz)  
FIGURE 2-37:  
Intermodulation Distortion  
FIGURE 2-40:  
Input Noise vs. Time with  
vs. Frequency with VCM Disturbance (see  
Figure 1-7).  
1 Hz and 10 Hz Filters and VDD =5.5V.  
© 2011 Microchip Technology Inc.  
DS25007B-page 15  
MCP6V26/7/8  
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND.  
2.5  
Time Response  
6
4
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
VDD = 5.5V  
G = 1  
Temperature increased by  
using heat gun for 10 seconds.  
2
0
VOS  
-2  
-4  
-6  
TPCB  
-8  
-10  
-12  
-14  
0
1
2
3
4
5
6
7
8
9
10  
0
20 40 60 80 100 120 140 160 180  
Time (s)  
Time (µs)  
FIGURE 2-41:  
Input Offset Voltage vs.  
FIGURE 2-44:  
Non-inverting Small Signal  
Time with Temperature Change.  
Step Response.  
90  
6
5.5  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
G = 1  
VDD = 5.5V  
G = 1  
80  
5
VDD  
70  
60  
50  
4
3
2
40  
1
POR Trip Point  
30  
20  
0
-1  
-2  
-3  
-4  
VOS  
10  
0
-10  
0
5
10 15 20 25 30 35 40 45 50  
Time (µs)  
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0  
Time (ms)  
FIGURE 2-42:  
Time at Power Up.  
Input Offset Voltage vs.  
FIGURE 2-45:  
Step Response.  
Non-inverting Large Signal  
7
6
5
VDD = 5.5V  
G = -1  
VDD = 5.5V  
G = 1  
VIN  
VOUT  
4
3
2
1
0
-1  
0
1
2
3
4
5
6
7
8
9
10  
0
1
2
3
4
5
6
7
8
9
10  
Time (ms)  
Time (µs)  
FIGURE 2-43:  
Shows No Input Phase Reversal with Overdrive.  
The MCP6V26/7/8 Device  
FIGURE 2-46:  
Response.  
Inverting Small Signal Step  
DS25007B-page 16  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND.  
6.0  
5.0  
4.0  
3.0  
2.0  
1.0  
0.0  
-1.0  
6
5
4
3
2
1
0
-1  
5.5  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
VDD = 5.5V  
G = -1  
G VIN  
VOUT  
VDD = 5.5V  
G = -100 V/V  
0.5V Overdrive  
G VIN  
VOUT  
0
5
10 15 20 25 30 35 40 45 50  
Time (µs)  
Time (50 µs/div)  
FIGURE 2-49:  
vs. Time with G = -100 V/V.  
Output Overdrive Recovery  
FIGURE 2-47:  
Response.  
Inverting Large Signal Step  
1000  
1.6  
1.4  
0.5V Output Overdrive  
VDD = 5.5V  
Falling Edge  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
100  
VDD = 5.5V  
tODR, high  
10  
VDD = 2.3V  
Rising Edge  
VDD = 2.3V  
tODR, low  
1
1
10  
100  
1000  
-50  
-25  
0
25  
50  
75  
100  
125  
Inverting Gain Magnitude (V/V)  
Ambient Temperature (°C)  
FIGURE 2-50:  
Time vs. Inverting Gain.  
Output Overdrive Recovery  
FIGURE 2-48:  
Temperature.  
Slew Rate vs. Ambient  
© 2011 Microchip Technology Inc.  
DS25007B-page 17  
MCP6V26/7/8  
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, and CS = GND.  
2.6  
Chip Select Response (MCP6V28 only)  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0.0  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0.0  
CS = VDD  
VDD = 5.5V  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Power Supply Voltage (V)  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Chip Select Voltage (V)  
FIGURE 2-51:  
Chip Select Current vs.  
FIGURE 2-54:  
Chip Select Current vs. Chip  
Power Supply Voltage.  
Select Voltage.  
700  
600  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
VDD = 2.3V  
G = 1  
VIN = 1.15V  
VOUT On  
VL = 0V  
500  
Op Amp  
Op Amp  
turns off  
here  
turns on  
400  
here  
VOUT Off  
VOUT Off  
300  
Hysteresis  
CS  
200  
100  
0
VDD = 2.3V  
G = +1 V/V  
VIN = VDD  
RL = 10 kꢁ tied to VDD/2  
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4  
Chip Select Voltage (V)  
0
5
10 15 20 25 30 35 40 45 50  
Time (5 μs/div)  
FIGURE 2-52:  
Power Supply Current vs.  
FIGURE 2-55:  
Chip Select Voltage, Output  
Chip Select Voltage with VDD = 2.3V.  
Voltage vs. Time with VDD = 2.3V.  
800  
700  
600  
500  
400  
300  
200  
100  
0
5.5  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
VDD = 5.5V  
G = 1  
VOUT On  
VIN = 2.75V  
VL = 0V  
Op Amp  
turns on  
here  
Op Amp  
turns off  
here  
VOUT Off  
VOUT Off  
Hysteresis  
VDD = 5.5V  
G = +1 V/V  
CS  
VIN = VDD  
RL = 10 kꢁ tied to VDD/2  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Chip Select Voltage (V)  
0
5
10 15 20 25 30 35 40 45 50  
Time (5 μs/div)  
FIGURE 2-53:  
Power Supply Current vs.  
FIGURE 2-56:  
Chip Select Voltage, Output  
Chip Select Voltage with VDD = 5.5V.  
Voltage vs. Time with VDD = 5.5V.  
DS25007B-page 18  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,  
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, and CS = GND.  
70%  
65%  
60%  
55%  
50%  
45%  
40%  
35%  
30%  
7
6
5
4
3
2
1
0
VDD = 5.5V  
VIH/VDD  
VDD = 2.3V  
VIL/VDD  
-50  
-25  
0
25  
50  
75  
100  
125  
-50  
-25  
0
25  
50  
75  
100 125  
Ambient Temperature (°C)  
Ambient Temperature (°C)  
FIGURE 2-57:  
Chip Select Relative Logic  
FIGURE 2-60:  
Chip Select’s Pull-down  
Thresholds vs. Ambient Temperature.  
Resistor (RPD) vs. Ambient Temperature.  
1.4  
0.40  
0.35  
0.30  
0.25  
CS = VDD  
Representative Part  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
+125°C  
+85°C  
+25°C  
-40°C  
VDD = 5.5V  
0.20  
0.15  
0.10  
0.05  
0.00  
VDD = 2.3V  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Power Supply Voltage (V)  
-50  
-25  
0
25  
50  
75  
100 125  
Ambient Temperature (°C)  
FIGURE 2-58:  
Chip Select Hysteresis.  
FIGURE 2-61:  
Quiescent Current in  
Shutdown vs. Power Supply Voltage.  
7
6
5
4
3
2
1
0
VDD = 5.5V  
VDD = 2.3V  
-50  
-25  
0
25  
50  
75  
100  
125  
Ambient Temperature (°C)  
FIGURE 2-59:  
Chip Select Turn On Time  
vs. Ambient Temperature.  
© 2011 Microchip Technology Inc.  
DS25007B-page 19  
MCP6V26/7/8  
3.0  
PIN DESCRIPTIONS  
Descriptions of the pins are listed in Table 3-1.  
TABLE 3-1:  
MCP6V26  
PIN FUNCTION TABLE  
MCP6V27  
MCP6V28  
Symbol  
Description  
TDFN MSOP, SOIC DFN MSOP, SOIC TDFN MSOP, SOIC  
6
2
6
2
1
2
1
2
6
2
6
2
VOUT, VOUTA Output (op amp A)  
VIN–, VINA  
–
+
Inverting Input (op amp A)  
Non-inverting Input (op amp A)  
Negative Power Supply  
Non-inverting Input (op amp B)  
Inverting Input (op amp B)  
Output (op amp B)  
3
3
3
3
3
3
VIN+, VINA  
VSS  
4
4
4
4
4
4
—
—
—
7
—
—
—
7
5
5
—
—
—
7
—
—
—
7
VINB  
+
–
6
6
VINB  
7
7
VOUTB  
VDD  
8
8
Positive Power Supply  
—
—
—
—
8
8
CS  
NC  
EP  
Chip Select (op amp A)  
No Internal Connection  
1, 5, 8  
9
1, 5, 8  
—
—
9
—
—
1, 5  
9
1, 5  
—
Exposed Thermal Pad (EP);  
must be connected to VSS  
3.1  
Analog Outputs  
3.4  
Chip Select (CS) Digital Input  
The analog output pins (VOUT) are low-impedance  
voltage sources.  
This pin (CS) is a CMOS, Schmitt-triggered input that  
places the MCP6V28 op amp into a low power mode of  
operation.  
3.2  
Analog Inputs  
3.5  
Exposed Thermal Pad (EP)  
The non-inverting and inverting inputs (VIN+, VIN–, …)  
are high-impedance CMOS inputs with low bias  
currents.  
There is an internal connection between the Exposed  
Thermal Pad (EP) and the VSS pin; they must be  
connected to the same potential on the Printed Circuit  
Board (PCB).  
3.3  
Power Supply Pins  
This pad can be connected to a PCB ground plane to  
provide a larger heat sink. This improves the package  
thermal resistance (θJA).  
The positive power supply (VDD) is 2.3V to 5.5V higher  
than the negative power supply (VSS). For normal  
operation, the other pins are between VSS and VDD  
.
Typically, these parts are used in a single (positive)  
supply configuration. In this case, VSS is connected to  
ground and VDD is connected to the supply. VDD will  
need bypass capacitors.  
DS25007B-page 20  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
4.1  
Overview of Auto-Zeroing  
Operation  
4.0  
APPLICATIONS  
The MCP6V26/7/8 family of auto-zeroed op amps are  
manufactured using Microchip’s state-of-the-art CMOS  
process. This family is designed for low cost, low power  
and high precision applications. Its low supply voltage,  
low quiescent current and wide bandwidth make the  
MCP6V26/7/8 devices ideal for battery-powered appli-  
cations.  
Figure 4-1 shows  
a
simplified diagram of the  
MCP6V26/7/8 auto-zeroed op amps. This will be used  
to explain how the DC voltage errors are reduced in this  
architecture.  
VIN+  
VIN–  
Main  
Amp.  
NC  
Output  
Buffer  
VOUT  
CFW  
VREF  
Null  
Input  
Switches  
Null  
Output  
Switches  
φ1  
Null  
Amp.  
CH  
POR  
Null  
Correct  
Switches  
φ1  
φ2  
Digital  
Control  
Oscillator  
φ2  
FIGURE 4-1:  
Simplified Auto-Zeroed Op Amp Functional Diagram.  
All of these switches are make-before-break in order to  
minimize glitch-induced errors. They are driven by two  
clock phases (φ1 and φ2) that select between normal  
mode and auto-zeroing mode.  
4.1.1  
BUILDING BLOCKS  
The Null Amplifier and Main Amplifier are designed for  
high gain and accuracy using a differential topology.  
They have a main input pair (+ and - pins at their top  
left) used for the signal. They have an auxiliary input  
pair (+ and - pins at their bottom left) used for correcting  
the offset voltages. Both input pairs are added together  
internally. The capacitors at the auxiliary inputs (CFW  
and CH) hold the corrected values during normal  
operation.  
The clock is derived from an internal R-C oscillator  
running at a rate of fOSC1 = 850 kHz. The oscillator’s  
output is divided down to the desired rate.  
The internal POR ensures the part starts up in a known  
good state. It also provides protection against power  
supply brown-out events.  
The Output Buffer is designed to drive external loads at  
the VOUT pin. It also produces a single-ended output  
voltage (VREF is an internal reference voltage).  
The Digital Control circuitry takes care of all of the  
housekeeping details of the switching operation. It also  
takes care of POR events.  
© 2011 Microchip Technology Inc.  
DS25007B-page 21  
MCP6V26/7/8  
offset voltage on overall performance. Essentially, the  
Null Amplifier and Main Amplifier behave as a regular  
op amp with very high gain (AOL) and very low offset  
voltage (VOS).  
4.1.2  
AUTO-ZEROING ACTION  
Figure 4-2 shows the connections between amplifiers  
during the Normal Mode of operation (φ1). The hold  
capacitor (CH) corrects the Null Amplifier’s input offset.  
Since the Null Amplifier has very high gain, it  
dominates the signal seen by the Main Amplifier. This  
greatly reduces the impact of the Main Amplifier’s input  
VIN+  
VIN–  
Main  
Amp.  
NC  
Output  
Buffer  
VOUT  
CFW  
VREF  
Null  
Amp.  
CH  
FIGURE 4-2:  
Normal Mode of Operation (φ1); Equivalent Amplifier Diagram.  
Figure 4-3 shows the connections between amplifiers  
during the Auto-zeroing Mode of operation (φ2). The  
signal goes directly through the Main Amplifier, and the  
flywheel capacitor (CFW) maintains a constant correc-  
tion on the Main Amplifier’s offset.  
Since these corrections happen every 40 µs, or so, we  
also minimize slow errors, including offset drift with  
temperature (ΔVOS/ΔTA), 1/f noise, and input offset  
aging.  
The Null Amplifier uses its own high open loop gain to  
drive the voltage across CH to the point where its input  
offset voltage is almost zero. Because the signal input  
pair is connected to VIN+, the auto-zeroing action  
corrects the offset at the current common mode input  
voltage (VCM) and supply voltage (VDD). This makes  
the DC CMRR and PSRR very high also.  
VIN+  
VIN–  
Main  
Amp.  
NC  
Output  
Buffer  
VOUT  
CFW  
VREF  
Null  
Amp.  
CH  
FIGURE 4-3:  
Auto-zeroing Mode of Operation (φ2); Equivalent Diagram.  
frequencies. Each of the square wave clock’s  
harmonics has a series of IMD tones centered on it.  
See Figure 2-37 and Figure 2-38.  
4.1.3 INTERMODULATION DISTORTION  
(IMD)  
The MCP6V26/7/8 op amps will show intermodulation  
distortion (IMD), products when an AC signal is  
present.  
The signal and clock can be decomposed into sine  
wave tones (Fourier series components). These tones  
interact with the auto-zeroing circuitry’s non-linear  
response to produce IMD tones at sum and difference  
DS25007B-page 22  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
The input ESD diodes clamp the inputs when they try  
to go more than one diode drop below VSS. They also  
clamp any voltages that are well above VDD; their  
breakdown voltage is high enough to allow normal  
operation, but not low enough to protect against slow  
over-voltage (beyond VDD) events. Very fast ESD  
events (that meet the spec) are limited so that damage  
does not occur.  
4.2  
Other Functional Blocks  
4.2.1  
RAIL-TO-RAIL INPUTS  
The input stage of the MCP6V26/7/8 op amps use two  
differential CMOS input stages in parallel. One  
operates at low common mode input voltage (VCM  
which is approximately equal to VIN+ and VIN– in  
normal operation) and the other at high VCM. With this  
topology, the input operates with VCM up to VDD + 0.2V,  
and down to VSS – 0.15V, at +25°C (see Figure 2-18).  
The input offset voltage (VOS) is measured at  
VCM = VSS – 0.15V and VDD + 0.2V to ensure proper  
operation.  
,
In some applications, it may be necessary to prevent  
excessive voltages from reaching the op amp inputs;  
Figure 4-5 shows one approach to protecting these  
inputs. D1 and D2 may be small signal silicon diodes,  
Schottky diodes for lower clamping voltages or diode-  
connected FETs for low leakage.  
The transition between the input stages occurs when  
VCM ≈ VDD – 1.2V (see Figure 2-7 and Figure 2-8). For  
the best distortion and gain linearity, with non-inverting  
gains, avoid this region of operation.  
VDD  
U1  
4.2.1.1  
Phase Reversal  
D1  
MCP6V2X  
The input devices are designed to not exhibit phase  
inversion when the input pins exceed the supply  
voltages. Figure 2-43 shows an input voltage  
exceeding both supplies with no phase inversion.  
V1  
D2  
VOUT  
V2  
4.2.1.2  
Input Voltage Limits  
FIGURE 4-5:  
Protecting the Analog Inputs  
In order to prevent damage and/or improper operation  
of these amplifiers, the circuit must limit the voltages at  
the input pins (see Section 1.1, Absolute Maximum  
Ratings †). This requirement is independent of the  
current limits discussed later on.  
Against High Voltages.  
4.2.1.3  
Input Current Limits  
In order to prevent damage and/or improper operation  
of these amplifiers, the circuit must limit the currents  
into the input pins (see Section 1.1, Absolute  
The ESD protection on the inputs can be depicted as  
shown in Figure 4-4. This structure was chosen to  
protect the input transistors against many (but not all)  
over-voltage conditions, and to minimize input bias  
current (IB).  
Maximum  
Ratings †).  
This  
requirement  
is  
independent of the voltage limits previously discussed.  
Figure 4-6 shows one approach to protecting these  
inputs. The resistors R1 and R2 limit the possible  
current in or out of the input pins (and into D1 and D2).  
The diode currents will dump onto VDD  
.
Bond  
VDD  
Pad  
VDD  
Bond  
Pad  
Bond  
Pad  
Input  
Stage  
U1  
MCP6V2X  
VOUT  
VIN+  
VIN–  
D1  
V1  
V2  
R1  
R2  
D2  
Bond  
Pad  
VSS  
VSS – min(V1, V2)  
2 mA  
max(V1, V2) – VDD  
2 mA  
FIGURE 4-4:  
Structures.  
Simplified Analog Input ESD  
min(R1, R2) >  
min(R1, R2) >  
FIGURE 4-6:  
Protecting the Analog Inputs  
Against High Currents.  
© 2011 Microchip Technology Inc.  
DS25007B-page 23  
MCP6V26/7/8  
It is also possible to connect the diodes to the left of  
resistors R1 and R2. In this case, the currents through  
diodes D1 and D2 need to be limited by some other  
mechanism. The resistors then serve as in-rush current  
limiters; the DC current into the input pins (VIN+ and  
VIN–) should be very small.  
4.3.2  
DC GAIN PLOTS  
Figure 2-9, Figure 2-10 and Figure 2-11 are histograms  
of the reciprocals (in units of µV/V) of CMRR, PSRR  
and AOL, respectively. They represent the change in  
input offset voltage (VOS) with a change in common  
mode input voltage (VCM), power supply voltage (VDD  
)
A significant amount of current can flow out of the  
inputs (through the ESD diodes) when the common  
mode voltage (VCM) is below ground (VSS); see  
Figure 2-17.  
and output voltage (VOUT).  
The 1/AOL histogram is centered near 0 µV/V because  
the measurements are dominated by the op amp’s  
input noise. The negative values shown represent  
noise, not unstable behavior. We validate the op amps’  
stability by making multiple measurements of VOS; an  
unstable part would fail, because it would show either  
greater variability in VOS, or the output stuck at one of  
the rails.  
4.2.2  
RAIL-TO-RAIL OUTPUT  
The output voltage range of the MCP6V26/7/8  
zero-drift op amps is VDD – 15 mV (minimum) and  
VSS + 15 mV (maximum) when RL = 10 kΩ is  
connected to  
VDD/2 and VDD = 5.5V. Refer to  
Figure 2-19 and Figure 2-20.  
4.3.3  
OFFSET AT POWER UP  
This op amp is designed to drive light loads; use  
another amplifier to buffer the output from heavy loads.  
When these parts power up, the input offset (VOS  
)
starts at its uncorrected value (usually less than  
±5 mV). Circuits with high DC gain can cause the  
output to reach one of the two rails. In this case, the  
time to a valid output is delayed by an output overdrive  
time (like tODR), in addition to the startup time (like  
4.2.3  
CHIP SELECT (CS)  
The single MCP6V28 has a Chip Select (CS) pin.  
When CS is pulled high, the supply current for the  
corresponding op amp drops to about 1 µA (typical),  
and is pulled through the CS pin to VSS. When this  
happens, the amplifier is put into a high impedance  
state. By pulling CS low, the amplifier is enabled. If the  
CS pin is left floating, the internal pull-down resistor  
(about 5 MΩ) will keep the part on. Figure 1-4 shows  
the output voltage and supply current response to a CS  
pulse.  
t
STR).  
It can be simple to avoid this extra startup time.  
Reducing the gain is one method. Adding a capacitor  
across the feedback resistor (RF) is another method.  
4.3.4  
SOURCE RESISTANCES  
The input bias currents have two significant  
components; switching glitches that dominate at room  
temperature and below, and input ESD diode leakage  
currents that dominate at +85°C and above.  
4.3  
Application Tips  
Make the resistances seen by the inputs small and  
equal. This minimizes the output offset caused by the  
input bias currents.  
4.3.1  
INPUT OFFSET VOLTAGE OVER  
TEMPERATURE  
Table 1-1 gives both the linear and quadratic  
temperature coefficients (TC1 and TC2) of input offset  
voltage. The input offset voltage, at any temperature in  
the specified range, can be calculated as follows:  
The inputs should see a resistance on the order of 10Ω  
to 1 kΩ at high frequencies (i.e., above 1 MHz). This  
helps minimize the impact of switching glitches, which  
are very fast, on overall performance. In some cases, it  
may be necessary to add resistors in series with the  
inputs to achieve this improvement in performance.  
EQUATION 4-1:  
VOS(TA) = VOS + TC1ΔT + TC2ΔT2  
Small input resistances are needed for high gains.  
Without them, parasitic capacitances can cause  
positive feedback and instability.  
Where:  
ΔT  
VOS(TA)  
VOS  
=
=
=
=
=
TA – 25°C  
4.3.5  
SOURCE CAPACITANCE  
input offset voltage at TA  
input offset voltage at +25°C  
linear temperature coefficient  
The capacitances seen by the two inputs should be  
small and matched. The internal switches connected to  
the inputs dump charges on these capacitors; an offset  
can be created if the capacitances do not match. Large  
input capacitances and source resistances, together  
with high gain, can lead to positive feedback and  
instability.  
TC1  
TC2  
quadratic temperature  
coefficient  
DS25007B-page 24  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
4.3.6  
CAPACITIVE LOADS  
4.3.7  
STABILIZING OUTPUT LOADS  
Driving large capacitive loads can cause stability  
problems for voltage feedback op amps. As the load  
capacitance increases, the feedback loop’s phase  
margin decreases and the closed-loop bandwidth is  
reduced. This produces gain peaking in the frequency  
response, with overshoot and ringing in the step  
response. These auto-zeroed op amps have a different  
output impedance than most op amps, due to their  
unique topology.  
This family of auto-zeroed op amps has an output  
impedance (Figure 2-31 and Figure 2-32) that has a  
double zero when the gain is low. This can cause a  
large phase shift in feedback networks that have low  
resistance near the part’s bandwidth. This large phase  
shift can cause stability problems.  
Figure 4-9 shows that the load on the output is  
(RL + RISO)||(RF + RG), where RISO is before the load  
(like Figure 4-7). This load needs to be large enough to  
maintain stability; it should be at least (2 kΩ)/GN.  
When driving a capacitive load with these op amps, a  
series resistor at the output (RISO in Figure 4-7)  
improves the feedback loop’s phase margin (stability)  
by making the output load resistive at higher  
frequencies. The bandwidth will be generally lower  
than the bandwidth with no capacitive load.  
RG  
RF  
VOUT  
RL  
CL  
U1  
RISO  
MCP6V2X  
VOUT  
FIGURE 4-9:  
Output Load.  
CL  
4.3.8  
GAIN PEAKING  
Figure 4-10 shows an op amp circuit that represents  
non-inverting amplifiers (VM is a DC voltage and VP is  
the input) or inverting amplifiers (VP is a DC voltage  
and VM is the input). The capacitances CN and CG rep-  
resent the total capacitance at the input pins; they  
include the op amp’s common mode input capacitance  
(CCM), board parasitic capacitance and any capacitor  
placed in parallel. The capacitance CFP represents the  
parasitic capacitance coupling the output and  
non-inverting input pins.  
U1  
MCP6V2X  
FIGURE 4-7:  
Output Resistor, RISO,  
Stabilizes Capacitive Loads.  
Figure 4-8 gives recommended RISO values for  
different capacitive loads and gains. The x-axis is the  
normalized load capacitance (CL/GN2). The y-axis is  
the normalized resistance (GNRISO).  
GN is the circuit’s noise gain. For non-inverting gains,  
GN and the Signal Gain are equal. For inverting gains,  
GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).  
CN  
CFP  
RN  
1000  
1k  
VP  
U1  
MCP6V2X  
100  
100  
VM  
VOUT  
RG  
RF  
10  
CG  
GN = 1  
GN = 2  
GN = 5  
GN ꢃ 10  
1
1
FIGURE 4-10:  
Capacitance.  
Amplifier with Parasitic  
100p  
1n  
1.E-09  
10n  
100n  
1.E-07  
1μ  
1.E-06  
1.E-10  
1.E-08  
CL/GN2 (F)  
CG acts in parallel with RG (except for a gain of +1 V/V),  
which causes an increase in gain at high frequencies.  
CG also reduces the phase margin of the feedback  
loop, which becomes less stable. This effect can be  
reduced by either reducing CG or RF||RG.  
FIGURE 4-8:  
for Capacitive Loads.  
Recommended RISO values  
After selecting RISO for your circuit, double check the  
resulting frequency response peaking and step  
response overshoot. Modify RISO's value until the  
response is reasonable. Bench evaluation and  
simulations with the MCP6V26/7/8 SPICE macro  
model are helpful.  
CN and RN form a low-pass filter that affects the signal  
at VP. This filter has a single real pole at 1/(2πRNCN).  
© 2011 Microchip Technology Inc.  
DS25007B-page 25  
MCP6V26/7/8  
The largest value of RF that should be used depends  
on noise gain (see GN in Section 4.3.6, Capacitive  
Loads), CG and the open-loop gain’s phase shift. An  
approximate limit for RF is:  
supplies. Smaller resistors and capacitors are a better  
choice for designs where the power supply is not as  
noisy.  
VS_ANA  
EQUATION 4-2:  
50Ω  
1/4W  
50Ω  
1/10W  
12 pF  
RF ≤ 2 kΩ × -------------- × G  
CG  
2
0.1 µF  
N
100 µF  
100 µF  
U1  
MCP6V2X  
to other analog parts  
Some applications may modify these values to reduce  
either output loading or gain peaking (step response  
overshoot).  
At high gains, RG and CG need to be small in order to  
prevent positive feedback and oscillations.  
FIGURE 4-11:  
Additional Supply Filtering.  
4.3.11  
PCB DESIGN FOR DC PRECISION  
4.3.9  
REDUCING UNDESIRED NOISE  
AND SIGNALS  
In order to achieve DC precision on the order of ±1 µV,  
many physical errors need to be minimized. The design  
of the Printed Circuit Board (PCB), the wiring and the  
thermal environment has a strong impact on the  
precision achieved. A poor PCB design can easily be  
more than 100 times worse than the MCP6V26/7/8 op  
amps minimum and maximum specifications.  
Reduce undesired noise and signals with:  
• Low bandwidth signal filters:  
- Minimizes random analog noise  
- Reduces interfering signals  
• Good PCB layout techniques:  
- Minimizes crosstalk  
4.3.11.1  
PCB Layout  
- Minimizes parasitic capacitances and  
inductances that interact with fast switching  
edges  
Any time two dissimilar metals are joined together, a  
temperature dependent voltage appears across the  
junction (the Seebeck or thermo-junction effect). This  
effect is used in thermocouples to measure tempera-  
ture. The following are examples of thermo-junctions  
on a PCB:  
• Good power supply design:  
- Provides isolation from other parts  
- Filters interference on supply line(s)  
• Components (resistors, op amps, …) soldered to  
a copper pad  
4.3.10  
SUPPLY BYPASSING AND  
FILTERING  
• Wires mechanically attached to the PCB  
With this family of op amps, the power supply pin (VDD  
for single supply) should have a local bypass capacitor  
(i.e., 0.01 µF to 0.1 µF) within 2 mm of the pin for good  
high-frequency performance.  
• Jumpers  
• Solder joints  
• PCB vias  
Typical thermo-junctions have temperature to voltage  
conversion coefficients of 10 to 100 µV/°C (sometimes  
higher).  
These parts also need a bulk capacitor (i.e., 1 µF or  
larger) within 100 mm to provide large, slow currents.  
This bulk capacitor can be shared with other low noise,  
analog parts.  
Microchip’s AN1258 (“Op Amp Precision Design: PCB  
Layout Techniques”) contains in depth information on  
PCB layout techniques that minimize thermo-junction  
effects. It also discusses other effects, such as  
crosstalk, impedances, mechanical stresses and  
humidity.  
In some cases, high-frequency power supply noise  
(e.g., switched mode power supplies) may cause  
undue intermodulation distortion, with a DC offset shift;  
this noise needs to be filtered. Adding a resistor into the  
supply connection can be helpful. This resistor needs  
to be small enough to prevent a large drop in VDD for  
the op amp, which would cause a reduced output range  
and possible load-induced power supply noise. It also  
needs to be large enough to dissipate little power when  
VDD is turned on and off quickly. Figure 4-11 shows a  
circuit with resistors in the supply connections. It gives  
good rejection out to 1 MHz for switched mode power  
DS25007B-page 26  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
4.3.11.2  
Crosstalk  
4.4  
Typical Applications  
DC crosstalk causes offsets that appear as a larger  
input offset voltage. Common causes include:  
4.4.1  
WHEATSTONE BRIDGE  
Many sensors are configured as Wheatstone bridges.  
Strain gauges and pressure sensors are two common  
examples. These signals can be small and the  
common mode noise large. Amplifier designs with high  
differential gain are desirable.  
• Common mode noise (remote sensors)  
• Ground loops (current return paths)  
• Power supply coupling  
Interference from the mains (usually 50 Hz or 60 Hz),  
and other AC sources, can also affect the DC perfor-  
mance. Non-linear distortion can convert these signals  
to multiple tones, including a DC shift in voltage. When  
the signal is sampled by an ADC, these AC signals can  
also be aliased to DC, causing an apparent shift in  
offset.  
Figure 4-12 shows how to interface to a Wheatstone  
bridge with a minimum of components. Because the  
circuit is not symmetric, the ADC input is single ended,  
there is a minimum of filtering, and the CMRR is good  
enough for moderate common mode noise.  
To reduce interference:  
0.01C  
100R  
VDD  
3 kΩ  
VDD  
- Keep traces and wires as short as possible  
- Use shielding (e.g., encapsulant)  
R
R
ADC  
0.2R  
0.2R  
- Use ground plane (at least a star ground)  
- Place the input signal source near to the DUT  
- Use good PCB layout techniques  
R
R
- Use a separate power supply filter (bypass  
capacitors) for these auto-zeroed op amps  
U1  
MCP6V26  
FIGURE 4-12:  
Simple Design.  
4.3.11.3  
Miscellaneous Effects  
Keep the resistances seen by the input pins as small  
and as near to equal as possible, to minimize bias  
current-related offsets.  
Figure 4-13 shows a higher performance circuit for  
Wheatstone bridges. This circuit is symmetric and has  
high CMRR. Using a differential input to the ADC helps  
with the CMRR.  
Make the (trace) capacitances seen by the input pins  
small and equal. This is helpful in minimizing switching  
glitch-induced offset voltages.  
U1A  
½ MCP6V27  
Bending a coax cable with a radius that is too small  
causes a small voltage drop to appear on the center  
conductor (the tribo-electric effect). Make sure the  
bending radius is large enough to keep the conductors  
and insulation in full contact.  
200 Ω  
VDD  
1 µF  
R
R
R
R
Mechanical stresses can make some capacitor types  
(such as ceramic) to output small voltages. Use more  
appropriate capacitor types in the signal path and  
minimize mechanical stresses and vibration.  
20 kΩ  
3 kΩ  
10 nF  
VDD  
200Ω  
1 µF  
ADC  
Humidity can cause electro-chemical potential voltages  
to appear in a circuit. Proper PCB cleaning helps, as  
does the use of encapsulants.  
200Ω  
3 kΩ  
10 nF  
20 kΩ  
1 µF  
200 Ω  
U1B  
½ MCP6V27  
FIGURE 4-13:  
High Performance Design.  
© 2011 Microchip Technology Inc.  
DS25007B-page 27  
MCP6V26/7/8  
4.4.2  
RTD SENSOR  
4.4.3  
THERMOCOUPLE SENSOR  
The ratiometric circuit in Figure 4-14 conditions a three  
wire RTD. It corrects for the sensor’s wiring resistance  
by subtracting the voltage across the middle RW. The  
top R1 does not change the output voltage; it balances  
the op amp inputs. Failure (open) of the RTD is  
detected by an out-of-range voltage.  
Figure 4-15 shows a simplified diagram of an amplifier  
and temperature sensor used in a thermocouple  
application. The type K thermocouple senses the  
temperature at the hot junction (THJ), and produces a  
voltage at V1 proportional to THJ (in °C). The amplifier’s  
gain is set so that V4/THJ is 10 mV/°C. V3 represents  
the output of a temperature sensor, which produces a  
voltage proportional to the temperature (in °C) at the  
cold junction (TCJ), and with a 0.50V offset. V2 is set so  
that V4 is 0.50V when THJ – TCJ is 0°C.  
U
1A  
½ MCP6V27  
2.49 kΩ  
EQUATION 4-3:  
VDD  
100 nF  
V1 ≈ THJ(40 µV/°C)  
RT  
20 kΩ  
V2 = (1.00V)  
R3  
100 kΩ  
RW  
V3 = TCJ(10 mV/°C) + (0.50V)  
V4 = 250V1 + (V2 – V3)  
≈ (10 mV/°C) (THJ – TCJ) + (0.50V)  
3 kΩ  
VDD  
R1  
R2  
2.55 kΩ  
10 nF  
10 nF  
2.49 kΩ  
1 µF  
RRTD  
100Ω  
ADC  
R2  
2.55 kΩ  
R1  
RTH = Thevenin Equivalent Resistance  
(hot junction  
2.49 kΩ  
at THJ  
)
(RTH  
)
(RTH  
)
3 kΩ  
R3  
100 kΩ  
V2  
(RTH)/250  
V1  
(RTH)/250  
V3  
40 µV/°C  
Type K  
Thermocouple  
RW  
RW  
RB  
20 kΩ  
C
U
1
100 nF  
MCP6V26  
V4  
2.49 kΩ  
(cold junction  
C
U
at TCJ  
)
1B  
½ MCP6V27  
(RTH  
)
(RTH)  
FIGURE 4-15:  
Thermocouple Sensor;  
FIGURE 4-14:  
RTD Sensor.  
Simplified Circuit.  
The voltages at the input of the ADC can be calculated  
with the following:  
Figure 4-16 shows a more complete implementation of  
this circuit. The dashed red arrow indicates a thermally  
conductive connection between the thermocouple and  
the MCP9700A; it needs to be very short and have low  
thermal resistance.  
GRTD = 1 + 2 ⋅ R3 ⁄ R2  
GW = GRTD – R3 ⁄ R1  
VDM = GRTD(VT – VB) + GWVW  
VT + VB + (GRTD + 1 – GW)VW  
RTH = Thevenin Equivalent Resistance (e.g., 10 kΩ)  
VCM = ------------------------------------------------------------------------------  
2
VDD  
0.5696(RTH  
)
4.100(RTH  
)
Where:  
VREF  
VT  
VB  
=
=
=
=
=
Voltage at the top of RRTD  
U
1
C
MCP1541  
Voltage at the bottom of RRTD  
Voltage across top and middle RW’s  
ADC’s common mode input  
ADC’s differential mode input  
(RTH)/250  
U
Type K  
3
VW  
MCP6V26  
V1  
VCM  
VDM  
(RTH)/250  
U
2
VDD  
MCP9700A  
C
V4  
Temp.Sensor  
(RTH  
)
3 kΩ  
(RTH  
)
FIGURE 4-16:  
Thermocouple Sensor.  
DS25007B-page 28  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
The MCP9700A senses the temperature at its physical  
location. It needs to be at the same temperature as the  
cold junction (TCJ), and produces V3 (Figure 4-15).  
The MCP1541 produces a 4.10V output, assuming  
VDD is at 5.0V. This voltage, tied to a resistor ladder of  
4.100(RTH) and 1.3224(RTH), would produce a  
Thevenin equivalent of 1.00V and 250(RTH). The  
1.3224(RTH) resistor is combined in parallel with the  
top right RTH resistor (in Figure 4-15), producing the  
0.5696(RTH) resistor.  
V4 should be converted to digital, then corrected for the  
thermocouple’s non-linearity. The ADC can use the  
MCP1541 as its voltage reference. Alternately, an  
absolute reference inside a PICmicro® device can be  
used instead of the MCP1541.  
4.4.4  
OFFSET VOLTAGE CORRECTION  
Figure 4-17 shows an MCP6V27 correcting the input  
offset voltage of another op amp. R2 and C2 integrate  
the offset error seen at the other op amp’s input; the  
integration needs to be slow enough to be stable (with  
the feedback provided by R1 and R3).  
R1  
R2  
R3  
VIN  
VOUT  
R4  
C2  
U2  
MCP661  
R5  
R2  
VDD/2  
VDD/2  
U1  
MCP6V26  
FIGURE 4-17:  
Offset Correction.  
4.4.5 PRECISION COMPARATOR  
Use high gain before a comparator to improve the  
latter’s performance. Do not use MCP6V26/7/8 as a  
comparator by itself; the VOS correction circuitry does  
not operate properly without a feedback loop.  
U1  
MCP6V26  
VIN  
R1  
R3  
R4  
R2  
1 kΩ  
R5  
VOUT  
VDD/2  
U2  
MCP6541  
FIGURE 4-18:  
Precision Comparator.  
© 2011 Microchip Technology Inc.  
DS25007B-page 29  
MCP6V26/7/8  
NOTES:  
DS25007B-page 30  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
5.4  
Analog Demonstration and  
Evaluation Boards  
5.0  
DESIGN AIDS  
Microchip provides the basic design aids needed for  
the MCP6V26/7/8 family of op amps.  
Microchip offers a broad spectrum of Analog Demon-  
stration and Evaluation Boards that are designed to  
help customers achieve faster time to market. For a  
complete listing of these boards and their correspond-  
ing user’s guides and technical information, visit the  
Microchip web site at www.microchip.com/analogtools.  
5.1  
SPICE Macro Model  
The latest SPICE macro model for the MCP6V26/7/8  
family of op amps is available on the Microchip web site  
at www.microchip.com. This model is intended to be an  
initial design tool that works well in the op amp’s linear  
region of operation over the temperature range. See  
the model file for information on its capabilities.  
Some boards that are especially useful are:  
• MCP6V01 Thermocouple Auto-Zeroed Reference  
Design  
• MCP6XXX Amplifier Evaluation Board 1  
• MCP6XXX Amplifier Evaluation Board 2  
• MCP6XXX Amplifier Evaluation Board 3  
• MCP6XXX Amplifier Evaluation Board 4  
• Active Filter Demo Board Kit  
Bench testing is a very important part of any design and  
cannot be replaced with simulations. Also, simulation  
results using this macro model need to be validated by  
comparing them to the data sheet specifications and  
characteristic curves.  
• P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP  
Evaluation Board  
®
5.2  
FilterLab Software  
Microchip’s FilterLab® software is an innovative  
software tool that simplifies analog active filter (using  
op amps) design. Available at no cost from the  
Microchip web site at www.microchip.com/filterlab, the  
Filter-Lab design tool provides full schematic diagrams  
of the filter circuit with component values. It also  
outputs the filter circuit in SPICE format, which can be  
used with the macro model to simulate actual filter  
performance.  
• P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP  
Evaluation Board  
5.5  
Application Notes  
The following Microchip Application Notes are  
available on the Microchip web site at www.microchip.  
com/appnotes and are recommended as supplemental  
reference resources.  
ADN003: “Select the Right Operational Amplifier for  
your Filtering Circuits”, DS21821  
5.3  
Microchip Advanced Part Selector  
(MAPS)  
AN722: “Operational Amplifier Topologies and DC  
Specifications”, DS00722  
MAPS is a software tool that helps efficiently identify  
Microchip devices that fit a particular design require-  
ment. Available at no cost from the Microchip website  
at www.microchip.com/maps, the MAPS is an overall  
selection tool for Microchip’s product portfolio that  
includes Analog, Memory, MCUs and DSCs. Using this  
tool, a customer can define a filter to sort features for a  
parametric search of devices and export side-by-side  
technical comparison reports. Helpful links are also  
provided for Data sheets, Purchase and Sampling of  
Microchip parts.  
AN723: “Operational Amplifier AC Specifications and  
Applications”, DS00723  
AN884: “Driving Capacitive Loads With Op Amps”,  
DS00884  
AN990: “Analog Sensor Conditioning Circuits – An  
Overview”, DS00990  
AN1177: “Op Amp Precision Design: DC Errors”,  
DS01177  
AN1228: “Op Amp Precision Design: Random Noise”,  
DS01228  
AN1258: “Op Amp Precision Design: PCB Layout  
Techniques”, DS01258  
These application notes and others are listed in the  
design guide:  
“Signal Chain Design Guide”, DS21825  
© 2011 Microchip Technology Inc.  
DS25007B-page 31  
MCP6V26/7/8  
NOTES:  
DS25007B-page 32  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
6.0  
6.1  
PACKAGING INFORMATION  
Package Marking Information  
8-Lead DFN (4x4x0.9 mm) (MCP6V27)  
Example  
XXXXXX  
XXXXXX  
YYWW  
NNN  
6V27  
e
3
E/MD  
1129  
256  
PIN 1  
PIN 1  
8-Lead MSOP (3x3 mm)  
Example  
6V27E  
129256  
8-Lead SOIC (3.90 mm)  
Example  
MCP6V27E  
SN^1129  
e
3
256  
NNN  
8-Lead TDFN (2x3x0.75 mm) (MCP6V26, MCP6V28)  
Example  
Device  
Code  
ABA  
129  
25  
MCP6V26T-E/MNY  
MCP6V28T-E/MNY  
ABA  
ABB  
Legend: XX...X Customer-specific information  
Y
Year code (last digit of calendar year)  
YY  
WW  
NNN  
Year code (last 2 digits of calendar year)  
Week code (week of January 1 is week ‘01’)  
Alphanumeric traceability code  
Pb-free JEDEC designator for Matte Tin (Sn)  
This package is Pb-free. The Pb-free JEDEC designator (  
can be found on the outer packaging for this package.  
e
3
e
3
*
)
Note: In the event the full Microchip part number cannot be marked on one line, it will  
be carried over to the next line, thus limiting the number of available  
characters for customer-specific information.  
© 2011 Microchip Technology Inc.  
DS25007B-page 33  
MCP6V26/7/8  
8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
Microchip Technology Drawing C04-131E Sheet 1 of 2  
DS25007B-page 34  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
Microchip Technology Drawing C04-131E Sheet 2 of 2  
© 2011 Microchip Technology Inc.  
DS25007B-page 35  
MCP6V26/7/8  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS25007B-page 36  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
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D
N
E
E1  
NOTE 1  
2
b
1
e
c
φ
A2  
A
L
L1  
A1  
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© 2011 Microchip Technology Inc.  
DS25007B-page 37  
MCP6V26/7/8  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS25007B-page 38  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
© 2011 Microchip Technology Inc.  
DS25007B-page 39  
MCP6V26/7/8  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS25007B-page 40  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
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ꢜꢐꢋꢄꢝ ꢫꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢜꢉꢖꢬꢉꢡꢌꢅꢋꢐꢉꢗꢃꢄꢡꢇꢓꢅꢜꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢝꢃꢖꢐꢕꢖꢘꢃꢜꢅꢂꢉꢖꢬꢉꢡꢃꢄꢡꢅꢣꢜꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ  
ꢘꢏꢏꢜꢨꢭꢭꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢜꢁꢖꢕꢑꢭꢜꢉꢖꢬꢉꢡꢃꢄꢡ  
© 2011 Microchip Technology Inc.  
DS25007B-page 41  
MCP6V26/7/8  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS25007B-page 42  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
© 2011 Microchip Technology Inc.  
DS25007B-page 43  
MCP6V26/7/8  
ꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢩꢔꢅꢉꢇꢪꢉꢅꢋꢠꢇꢜꢐꢇꢃꢄꢅꢆꢇꢈꢅꢍꢖꢅꢗꢄꢇꢘꢎꢜꢙꢇꢞꢇꢫꢬꢡꢬꢤꢢꢭꢮꢇꢒꢒꢇꢥꢐꢆꢦꢇꢚꢯꢩꢪꢜꢛ  
ꢜꢐꢋꢄꢝ ꢫꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢜꢉꢖꢬꢉꢡꢌꢅꢋꢐꢉꢗꢃꢄꢡꢇꢓꢅꢜꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢝꢃꢖꢐꢕꢖꢘꢃꢜꢅꢂꢉꢖꢬꢉꢡꢃꢄꢡꢅꢣꢜꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ  
ꢘꢏꢏꢜꢨꢭꢭꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢜꢁꢖꢕꢑꢭꢜꢉꢖꢬꢉꢡꢃꢄꢡ  
DS25007B-page 44  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
APPENDIX A: REVISION HISTORY  
Revision B (August 2011)  
The following is the list of modifications:  
1. Added the MCP6V26 and MCP6V28 single op  
amps.  
a) Updated package drawings on page 1.  
b) Updated the pinout table (Table 3-1).  
c) Added 8-lead, 2×3 TDFN package to the  
Thermal Characteristics Table (Table 1-4).  
d) Added 8-lead, 2×3 TDFN package to  
Section 6.0 “Packaging Information”.  
e) Added parts numbers to Product Identifica-  
tion System.  
2. Added Chip Select (CS) information.  
a) Added Digital Electrical Specifications table  
(Table 1-3).  
b) Added Timing Diagram (Figure 1-4).  
c) Added  
Section 2.6  
“Chip  
Select  
Response (MCP6V28 only)” to the Typical  
Performance Curves.  
d) Added Section 4.2.3 “Chip Select (CS)”  
to the applications write up.  
3. Added information on positive feedback and  
parasitic feedback capacitance.  
a) Added  
to  
Section 4.3.4  
“Source  
Resistances”.  
b) Added  
to  
Section 4.3.5  
“Source  
Capacitance”.  
c) Modified Figure 4-10.  
d) Added to Section 4.3.8 “Gain Peaking”.  
4. Other minor typographical corrections.  
Revision A (March 2011)  
• Original data sheet for the MCP6V27 dual op  
amps.  
© 2011 Microchip Technology Inc.  
DS25007B-page 45  
MCP6V26/7/8  
We use production screens to ensure the quality of our  
outgoing products. These screens are set at wider  
limits to eliminate any fliers; see Table B-1.  
APPENDIX B: OFFSET RELATED  
TEST SCREENS  
Input offset voltage-related specifications in the DC  
spec table (Table 1-1) are based on bench  
measurements (see Section 2.1 “DC Input  
Precision”). These measurements are much more  
accurate because:  
• More compact circuit  
• Soldered parts on the PCB (to validate other  
measurements)  
• More time spent averaging (reduces noise)  
• Better temperature control  
- Reduced temperature gradients  
- Greater accuracy  
TABLE B-1:  
OFFSET RELATED TEST SCREENS  
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND,  
VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CS = GND (refer to Figure 1-5 and Figure 1-6).  
Parameters  
Sym  
Min Max Units  
Conditions  
Input Offset  
Input Offset Voltage  
VOS  
-10 +10  
µV TA = +25°C (Note 1, Note 2)  
nV/°C TA = -40 to +125°C (Note 3)  
Input Offset Voltage Drift with Temperature TC1  
(linear Temp. Co.)  
—
—
Power Supply Rejection  
Common Mode  
PSRR 115  
—
dB (Note 1)  
Common Mode Rejection  
CMRR 106  
CMRR 116  
—
—
dB VDD = 2.3V, VCM = -0.15V to 2.5V (Note 1)  
dB VDD = 5.5V, VCM = -0.15V to 5.7V (Note 1)  
Open-Loop Gain  
DC Open-Loop Gain (large signal)  
AOL  
AOL  
114  
122  
—
—
dB VDD = 2.3V, VOUT = 0.2V to 2.1V (Note 1)  
dB VDD = 5.5V, VOUT = 0.2V to 5.3V (Note 1)  
Note 1: Due to thermal junctions and other errors in the production environment, these specifications are only  
screened in production.  
2:  
VOS is also sample screened at +125°C.  
3: TC1 is not measured in production.  
DS25007B-page 46  
© 2011 Microchip Technology Inc.  
MCP6V26/7/8  
PRODUCT IDENTIFICATION SYSTEM  
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.  
Examples:  
PART NO.  
Device  
–X  
/XX  
a)  
MCP6V26T-E/MNY: Extended temperature,  
8LD 2×3 TDFN  
package  
Extended temperature,  
8LD MSOP package  
Tape and Reel,  
Extended temperature,  
8LD SOIC package  
Temperature  
Range  
Package  
b)  
a)  
MCP6V26-E/MS:  
MCP6V26T-E/SN:  
Device:  
MCP6V26  
Single Op Amp  
MCP6V26T Single Op Amp (Tape and Reel)  
MCP6V27 Dual Op Amp  
MCP6V27T Dual Op Amp (Tape and Reel)  
MCP6V28 Single Op Amp with Chip Select  
MCP6V28T Single Op Amp with Chip Select  
(Tape and Reel)  
a)  
b)  
c)  
MCP6V27-E/MD:  
MCP6V27-E/MS:  
MCP6V27-E/SN:  
Extended temperature,  
8LD 4x4 DFN package  
Extended temperature,  
8LD MSOP package  
Extended temperature,  
8LD SOIC package  
Temperature Range:  
Package:  
E
= -40°C to +125°C  
a)  
MCP6V28T-E/MNY: Extended temperature,  
8LD 2×3 TDFN  
package  
Extended temperature,  
8LD MSOP package  
MD  
= Plastic Dual Flat, No-Lead (4×4x0.9), 8-lead  
MNY * = Plastic Dual Flat, No-Lead (2×3x0.75), 8-lead  
MS  
SN  
b)  
c)  
MCP6V28-E/MS:  
MCP6V28T-E/SN:  
=
=
Plastic Micro Small Outline Package, 8-lead  
Plastic SOIC (150mil Body), 8-lead  
Tape and Reel,  
Extended temperature,  
8LD SOIC package  
* Y = Nickel Palladium gold manufacturing designator. Only  
available on the TDFN package.  
© 2011 Microchip Technology Inc.  
DS25007B-page 47  
MCP6V26/7/8  
NOTES:  
DS25007B-page 48  
© 2011 Microchip Technology Inc.  
Note the following details of the code protection feature on Microchip devices:  
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.  
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the  
intended manner and under normal conditions.  
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our  
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data  
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.  
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.  
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not  
mean that we are guaranteeing the product as “unbreakable.”  
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our  
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts  
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.  
Information contained in this publication regarding device  
applications and the like is provided only for your convenience  
and may be superseded by updates. It is your responsibility to  
ensure that your application meets with your specifications.  
MICROCHIP MAKES NO REPRESENTATIONS OR  
WARRANTIES OF ANY KIND WHETHER EXPRESS OR  
IMPLIED, WRITTEN OR ORAL, STATUTORY OR  
OTHERWISE, RELATED TO THE INFORMATION,  
INCLUDING BUT NOT LIMITED TO ITS CONDITION,  
QUALITY, PERFORMANCE, MERCHANTABILITY OR  
FITNESS FOR PURPOSE. Microchip disclaims all liability  
arising from this information and its use. Use of Microchip  
devices in life support and/or safety applications is entirely at  
the buyer’s risk, and the buyer agrees to defend, indemnify and  
hold harmless Microchip from any and all damages, claims,  
suits, or expenses resulting from such use. No licenses are  
conveyed, implicitly or otherwise, under any Microchip  
intellectual property rights.  
Trademarks  
The Microchip name and logo, the Microchip logo, dsPIC,  
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,  
32  
PIC logo, rfPIC and UNI/O are registered trademarks of  
Microchip Technology Incorporated in the U.S.A. and other  
countries.  
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,  
MXDEV, MXLAB, SEEVAL and The Embedded Control  
Solutions Company are registered trademarks of Microchip  
Technology Incorporated in the U.S.A.  
Analog-for-the-Digital Age, Application Maestro, chipKIT,  
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,  
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,  
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,  
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,  
MPLINK, mTouch, Omniscient Code Generation, PICC,  
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,  
rfLAB, Select Mode, Total Endurance, TSHARC,  
UniWinDriver, WiperLock and ZENA are trademarks of  
Microchip Technology Incorporated in the U.S.A. and other  
countries.  
SQTP is a service mark of Microchip Technology Incorporated  
in the U.S.A.  
All other trademarks mentioned herein are property of their  
respective companies.  
© 2011, Microchip Technology Incorporated, Printed in the  
U.S.A., All Rights Reserved.  
Printed on recycled paper.  
ISBN: 978-1-61341-503-0  
Microchip received ISO/TS-16949:2009 certification for its worldwide  
headquarters, design and wafer fabrication facilities in Chandler and  
Tempe, Arizona; Gresham, Oregon and design centers in California  
and India. The Company’s quality system processes and procedures  
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping  
devices, Serial EEPROMs, microperipherals, nonvolatile memory and  
analog products. In addition, Microchip’s quality system for the design  
and manufacture of development systems is ISO 9001:2000 certified.  
© 2011 Microchip Technology Inc.  
DS25007B-page 49  
Worldwide Sales and Service  
AMERICAS  
ASIA/PACIFIC  
ASIA/PACIFIC  
EUROPE  
Corporate Office  
2355 West Chandler Blvd.  
Chandler, AZ 85224-6199  
Tel: 480-792-7200  
Fax: 480-792-7277  
Technical Support:  
http://www.microchip.com/  
support  
Asia Pacific Office  
Suites 3707-14, 37th Floor  
Tower 6, The Gateway  
Harbour City, Kowloon  
Hong Kong  
Tel: 852-2401-1200  
Fax: 852-2401-3431  
India - Bangalore  
Tel: 91-80-3090-4444  
Fax: 91-80-3090-4123  
Austria - Wels  
Tel: 43-7242-2244-39  
Fax: 43-7242-2244-393  
Denmark - Copenhagen  
Tel: 45-4450-2828  
Fax: 45-4485-2829  
India - New Delhi  
Tel: 91-11-4160-8631  
Fax: 91-11-4160-8632  
France - Paris  
Tel: 33-1-69-53-63-20  
Fax: 33-1-69-30-90-79  
India - Pune  
Tel: 91-20-2566-1512  
Fax: 91-20-2566-1513  
Australia - Sydney  
Tel: 61-2-9868-6733  
Fax: 61-2-9868-6755  
Web Address:  
www.microchip.com  
Germany - Munich  
Tel: 49-89-627-144-0  
Fax: 49-89-627-144-44  
Japan - Yokohama  
Tel: 81-45-471- 6166  
Fax: 81-45-471-6122  
Atlanta  
Duluth, GA  
Tel: 678-957-9614  
Fax: 678-957-1455  
China - Beijing  
Tel: 86-10-8569-7000  
Fax: 86-10-8528-2104  
Italy - Milan  
Tel: 39-0331-742611  
Fax: 39-0331-466781  
Korea - Daegu  
Tel: 82-53-744-4301  
Fax: 82-53-744-4302  
China - Chengdu  
Tel: 86-28-8665-5511  
Fax: 86-28-8665-7889  
Boston  
Westborough, MA  
Tel: 774-760-0087  
Fax: 774-760-0088  
Netherlands - Drunen  
Tel: 31-416-690399  
Fax: 31-416-690340  
Korea - Seoul  
China - Chongqing  
Tel: 86-23-8980-9588  
Fax: 86-23-8980-9500  
Tel: 82-2-554-7200  
Fax: 82-2-558-5932 or  
82-2-558-5934  
Chicago  
Itasca, IL  
Tel: 630-285-0071  
Fax: 630-285-0075  
Spain - Madrid  
Tel: 34-91-708-08-90  
Fax: 34-91-708-08-91  
China - Hangzhou  
Tel: 86-571-2819-3187  
Fax: 86-571-2819-3189  
Malaysia - Kuala Lumpur  
Tel: 60-3-6201-9857  
Fax: 60-3-6201-9859  
UK - Wokingham  
Tel: 44-118-921-5869  
Fax: 44-118-921-5820  
Cleveland  
Independence, OH  
Tel: 216-447-0464  
Fax: 216-447-0643  
China - Hong Kong SAR  
Tel: 852-2401-1200  
Fax: 852-2401-3431  
Malaysia - Penang  
Tel: 60-4-227-8870  
Fax: 60-4-227-4068  
Dallas  
Addison, TX  
Tel: 972-818-7423  
Fax: 972-818-2924  
China - Nanjing  
Tel: 86-25-8473-2460  
Fax: 86-25-8473-2470  
Philippines - Manila  
Tel: 63-2-634-9065  
Fax: 63-2-634-9069  
China - Qingdao  
Tel: 86-532-8502-7355  
Fax: 86-532-8502-7205  
Singapore  
Tel: 65-6334-8870  
Fax: 65-6334-8850  
Detroit  
Farmington Hills, MI  
Tel: 248-538-2250  
Fax: 248-538-2260  
China - Shanghai  
Tel: 86-21-5407-5533  
Fax: 86-21-5407-5066  
Taiwan - Hsin Chu  
Tel: 886-3-5778-366  
Fax: 886-3-5770-955  
Indianapolis  
Noblesville, IN  
Tel: 317-773-8323  
Fax: 317-773-5453  
China - Shenyang  
Tel: 86-24-2334-2829  
Fax: 86-24-2334-2393  
Taiwan - Kaohsiung  
Tel: 886-7-536-4818  
Fax: 886-7-330-9305  
Los Angeles  
China - Shenzhen  
Tel: 86-755-8203-2660  
Fax: 86-755-8203-1760  
Taiwan - Taipei  
Tel: 886-2-2500-6610  
Fax: 886-2-2508-0102  
Mission Viejo, CA  
Tel: 949-462-9523  
Fax: 949-462-9608  
China - Wuhan  
Tel: 86-27-5980-5300  
Fax: 86-27-5980-5118  
Thailand - Bangkok  
Tel: 66-2-694-1351  
Fax: 66-2-694-1350  
Santa Clara  
Santa Clara, CA  
Tel: 408-961-6444  
Fax: 408-961-6445  
China - Xian  
Tel: 86-29-8833-7252  
Fax: 86-29-8833-7256  
Toronto  
Mississauga, Ontario,  
Canada  
China - Xiamen  
Tel: 905-673-0699  
Fax: 905-673-6509  
Tel: 86-592-2388138  
Fax: 86-592-2388130  
China - Zhuhai  
Tel: 86-756-3210040  
Fax: 86-756-3210049  
08/02/11  
DS25007B-page 50  
© 2011 Microchip Technology Inc.  

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