MCP6V52 [MICROCHIP]
The MCP6V51/2/4 operational amplifiers provide input offset voltage correction for very low offset;
| 型号： | MCP6V52 |
| 厂家： | 
MICROCHIP |
| 描述： | The MCP6V51/2/4 operational amplifiers provide input offset voltage correction for very low offset |
| 文件： | 总43页 (文件大小：3337K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP6V51
45V, 2 MHz Zero-Drift Op Amp with EMI Filtering
Features
General Description
• High DC Precision:
The Microchip Technology Inc. MCP6V51 operational
amplifier employs dynamic offset correction for very
low offset and offset drift. The device has a gain
bandwidth product of 2 MHz (typical). It is unity-gain
stable, has virtually no 1/f noise and excellent Power
Supply Rejection Ratio (PSRR) and Common Mode
Rejection Ratio (CMRR). The product operates with a
single supply voltage that can range from 4.5V to 45V,
(±2.25V to ±22.5V), while drawing 470 µA (typical) of
quiescent current.
- VOS Drift: 36 nV/°C (max.)
- VOS: 15 µV (max.)
- Open-Loop Gain: 140 dB (min.)
- PSRR: 134 dB (min.)
- CMRR: 135 dB (min.)
• Low Noise:
- 10.2 nV/√ Hz at 1 kHz
- Eni: 0.21 µVP-P, f = 0.1 Hz to 10 Hz
• Low Power:
The MCP6V51 op amp is offered as a single-channel
amplifier and is designed using an advanced CMOS
process.
- IQ: 470 µA/amplifier (typ.)
- Wide Supply Voltage Range: 4.5V to 45V
• Easy to Use:
Package Types
- Input Range incl. Negative Rail
- Rail-to-Rail Output
- EMI Filtered Inputs
MCP6V51
SOT-23-5
MCP6V51
MSOP-8
- Gain Bandwidth Product: 2 MHz
- Slew Rate 1.2V/µs
NC
V
1
8
7
6
5
NC
VOUT
VSS
VDD
1
5
4
- Unity Gain Stable
2
3
4
V
–
+
DD
2
3
IN
• Small Packages: 5-Lead SOT23, 8-Lead MSOP
• Extended Temperature Range: -40°C to +125°C
V
V
OUT
VIN+
VIN–
IN
NC
V
SS
Typical Applications
• Industrial Instrumentation, PLC
• Process Control
• Power Control Loops
• Sensor Conditioning
Typical Application Circuit
40VDD
• Electronic Weight Scales
• Medical Instrumentation
• Automotive Monitors
Load
• Low-side Current Sensing
40VDD
U1
MCP6V51
Design Aids
IL
+
-
VOUT
• Microchip Advanced Part Selector (MAPS)
• Application Notes
RSHUNT
0.05Ω
RG
100Ω
RF
Related Parts
20 kΩ
• MCP6V71/1U/2/4: Zero-Drift, 2 MHz, 1.8V to 5V
• MCP6V81/1U/2/4: Zero-Drift, 5 MHz, 1.8V to 5V
CF
8.2 nF
2018 Microchip Technology Inc.
DS20006136A-page 1
MCP6V51
Figure 1 and Figure 2 show input offset voltage versus
ambient temperature for different power supply
voltages.
As seen in Figure 1 and Figure 2, the MCP6V51 op
amps have excellent performance across temperature.
The input offset voltage temperature drift (TC1) shown
is well within the specified maximum values of
31 nV/°C at VDD = 4.5V and 36 nV/°C at VDD = 45V.
8
22 Samples
VDD = 4.5V
6
This performance supports applications with stringent
DC precision requirements. In many cases, it will not be
necessary to correct for temperature effects (i.e.,
calibrate) in a design. In the other cases, the correction
will be small.
4
2
0
-2
-4
-6
-8
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 1:
Input Offset Voltage vs.
Ambient Temperature with VDD = 4.5V.
8
22 Samples
VDD = 45V
6
4
2
0
-2
-4
-6
-8
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2:
Input Offset Voltage vs.
Ambient Temperature with VDD = 45V.
DS20006136A-page 2
2018 Microchip Technology Inc.
MCP6V51
1.0
1.1
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
VDD - VSS ................................................................................................................................................................49.5V
Current at Input Pins ............................................................................................................................................±10 mA
Analog Inputs (VIN+ and VIN-) (Note 1)..................................................................................... VSS - 1.0V to VDD + 1.0V
All Other Inputs and Outputs .................................................................................................... VSS - 0.3V to VDD + 0.3V
Difference Input Voltage .............................................................................................................................................±1V
Output Short Circuit Current ...........................................................................................................................Continuous
Current at Output and Supply Pins ......................................................................................................................±50 mA
Storage Temperature .............................................................................................................................-65°C to +150°C
Maximum Junction Temperature .......................................................................................................................... +150°C
ESD protection on all pins (HBM, CDM, MM) 2 kV, 750V, 200V
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note 1: See Section 4.2.1, Input Protection.
1.2
Electrical Specifications
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND,
VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 100 pF (refer to Figure 1-4 and Figure 1-5).
Parameters
Input Offset
Sym.
Min.
Typ.
Max.
Units
Conditions
Input Offset Voltage
VOS
TC1
-15
-31
±2.4
±5
+15
+31
µV
TA = +25°C
Input Offset Voltage Drift with
Temperature (Linear Temp. Co.)
nV/°C TA = -40 to +125°C,
VDD = 4.5V (Note 1)
TC1
-36
±7
+36
nV/°C TA = -40 to +125°C,
VDD = 45V
(Note 1)
Input Offset Voltage Quadratic
Temp. Co.
TC2
TC2
—
—
—
±42
±38
±2
—
—
—
nV/ TA = -40 to +125°C
°C2 VDD = 4.5V
nV/ TA = -40 to +125°C
°C2
µV
VDD = 45V
Input Offset Voltage Aging
∆VOS
408 hours Life Test at
+150°C,
measured at +25°C
Power Supply Rejection Ratio
PSRR
134
124
160
138
—
—
dB
dB
TA = -40°C to +125°C
VDD = 45V (Note 1)
Input Bias Current and Impedance
Input Bias Current
IB
-250
±60
+250
pA
VDD = 45V
Note 1: Not production tested. Limits set by characterization and/or simulation and provided as design guidance
only.
2: Figure 2-17 shows how VCML and VCMH changed across temperature for the first production lot.
2018 Microchip Technology Inc.
DS20006136A-page 3
MCP6V51
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND,
VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 100 pF (refer to Figure 1-4 and Figure 1-5).
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
TA = +85°C
Input Bias Current across
Temperature
IB
IB
—
-4
-1
—
-8
—
—
±80
±1.4
—
+4
+1
—
+8
—
—
pA
nA
TA = +125°C (Note 1)
VDD = 45V
Input Offset Current
IOS
IOS
IOS
ZCM
ZDIFF
±0.28
nA
Input Offset Current across
Temperature
±0.32
nA
TA = +85°C
±0.45
nA
TA = +125°C (Note 1)
Common Mode Input Impedance
Differential Input Impedance
Common Mode
120G||3
2.5M||5.2
Ω||pF
Ω||pF
Common Mode
Input Voltage Range Low
VCML
—
—
—
VSS - 0.3
V
V
(Note 2)
(Note 2)
Common Mode
Input Voltage Range High
VCMH VDD - 2.1
—
—
Common Mode Rejection Ratio
CMRR
110
106
135
128
125
dB
VDD = 4.5V,
VCM = -0.3V to 2.4V
(Note 2)
116
150
140
—
—
—
dB
dB
dB
VDD = 4.5V
TA = -40°C to +125°C,
(Note 1)
CMRR
V
DD = 45V,
VCM = -0.3V to 42.9V
(Note 2)
V
DD = 45V
TA = -40°C to +125°C,
(Note 1)
Open-Loop Gain
DC Open-Loop Gain
AOL
124
120
142
139
—
—
dB
dB
VDD = 4.5V,
VOUT = 0.3V to 4.2V
VDD = 4.5V
TA = -40°C to +125°C,
(Note 1)
AOL
140
134
164
160
—
—
dB
dB
VDD = 45V,
VOUT = 0.3V to 44.7V
VDD = 45V
TA = -40°C to +125°C,
(Note 1)
Output
Minimum Output Voltage Swing
VOL
—
—
—
—
VSS + 45
VSS + 60
mV RL = 1 kΩ, VDD = 4.5V
RL = 1 kΩ, VDD = 45V
VSS + 500 VSS + 1000
VSS + 6
VSS + 50
VSS + 20
VSS + 70
RL = 10 kΩ, VDD = 4.5V
RL = 10 kΩ, VDD = 45V
Note 1: Not production tested. Limits set by characterization and/or simulation and provided as design guidance
only.
2: Figure 2-17 shows how VCML and VCMH changed across temperature for the first production lot.
DS20006136A-page 4
2018 Microchip Technology Inc.
MCP6V51
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND,
CM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 100 pF (refer to Figure 1-4 and Figure 1-5).
V
Parameters
Sym.
Min.
VDD - 150 VDD - 100
DD - 2500 VDD - 1500
VDD - 20 VDD - 12
VDD - 200 VDD - 100
Typ.
Max.
Units
Conditions
Maximum Output Voltage Swing
VOH
—
—
—
—
—
—
—
mV RL = 1 kΩ, VDD = 4.5V
RL = 1 kΩ, VDD = 45V
RL = 10 kΩ, VDD = 4.5V
RL = 10 kΩ, VDD = 45V
mA
V
Output Short Circuit Current
ISC
ISC
ROUT
+
—
—
—
46
36
16
-
mA
Closed-loop Output Resistance
Ω
f = 0.1 MHz, IO = 0,
G = 1
Capacitive Load Drive
Power Supply
CL
—
100
—
pF
G = 1
Supply Voltage
VDD
IQ
4.5
310
310
—
—
45
V
Quiescent Current per Amplifier
460
470
540
590
590
670
µA
µA
µA
VDD = 4.5V, IO = 0
VDD = 45V, IO = 0
IO = 0,
TA = -40 to +125°C
(Note 1)
(Figure 2-22)
Power-on Reset (POR) Trip
Voltage
VPOR
—
2.3
—
V
Note 1: Not production tested. Limits set by characterization and/or simulation and provided as design guidance
only.
2: Figure 2-17 shows how VCML and VCMH changed across temperature for the first production lot.
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND,
VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 100 pF (refer to Figure 1-4 and Figure 1-5).
Parameters
Sym. Min. Typ. Max. Units
Conditions
Amplifier AC Response
Gain Bandwidth Product
GBWP
—
—
—
—
1.8
2
—
—
—
—
MHz VDD = 4.5V, VIN = 10 mVpp, Gain = 100
MHz DD = 45V, VIN = 10 mVpp, Gain = 100
V
Slew Rate
SR
PM
1.2
66
V/µs (Figure 2-44)
Phase Margin
deg. VDD = 45V
Amplifier Noise Response
Input Noise Voltage
Eni
Eni
eni
ini
—
—
—
—
0.1
0.21
10.2
4
—
—
—
—
µVP-P f = 0.01 Hz to 1 Hz
µVP-P f = 0.1 Hz to 10 Hz
nV/√Hz f = 1 kHz
Input Noise Voltage Density
Input Noise Current Density
Amplifier Step Response
Start-Up Time
fA/√Hz
tSTR
tSTL
—
—
200
45
—
—
µs
µs
G = +1, 1% VOUT settling (Note 1)
Offset Correction Settling Time
G = +1, VIN step of 2V,
VOS within ±100 µV of its final value
Note 1: Behavior may vary with different gains; see Section 4.3.3 “Offset at Power-Up”.
2: tSTL and tODR include some uncertainty due to clock edge timing.
2018 Microchip Technology Inc.
DS20006136A-page 5
MCP6V51
AC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND,
VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 100 pF (refer to Figure 1-4 and Figure 1-5).
Parameters
Sym. Min. Typ. Max. Units
Conditions
Output Overdrive Recovery Time
tODR
—
65
—
µs
G = -10, ±0.5V input overdrive to VDD/2,
VIN 50% point to VOUT 90% point (Note 2)
EMI Protection
EMI Rejection Ratio
EMIRR
—
—
—
—
—
80
95
—
—
—
—
—
dB
VIN = 0.1 VPK, f = 400 MHz, VDD = 45V
VIN = 0.1 VPK, f = 900 MHz, VDD = 45V
108
109
109
VIN = 0.1 VPK, f = 1800 MHz, VDD = 45V
VIN = 0.1 VPK, f = 2400 MHz, VDD = 45V
VIN = 0.1 VPK, f = 5600 MHz, VDD = 45V
Note 1: Behavior may vary with different gains; see Section 4.3.3 “Offset at Power-Up”.
2: tSTL and tODR include some uncertainty due to clock edge timing.
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +4.5V to +45V, VSS = GND.
Parameters
Temperature Ranges
Sym.
Min.
Typ.
Max.
Units
Conditions
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
TA
TA
TA
-40
-40
-65
—
—
—
+125
+125
+150
°C
°C
°C
(Note 1)
Thermal Package Resistances
Thermal Resistance, 8LD-MSOP
JA
JA
—
—
206
115
—
—
°C/W
°C/W
Thermal Resistance, 5LD-SOT-23
Note 1: Operation must not cause TJ to exceed Maximum Junction Temperature specification (+150°C).
DS20006136A-page 6
2018 Microchip Technology Inc.
MCP6V51
1.3
Timing Diagrams
1.4
Test Circuits
The Timing Diagrams provide a depiction of the
Amplifier Step Response specifications listed under the
AC Electrical Specifications table.
The circuits used for most DC and AC tests are shown
in Figure 1-4 and Figure 1-5. Lay the bypass
capacitors out as discussed in Section 4.3.10 “Supply
Bypassing and Filtering”. RN is equal to the parallel
combination of RF and RG to minimize bias current
effects.
VDD
2.3V
VDD
0V
tSTR
1.01(VDD/3)
0.99(VDD/3)
VDD
1 µF
VOUT
RN
VIN
RISO
CL
VOUT
+
-
MCP6V51
FIGURE 1-1:
Amplifier Start-Up.
RL
100 nF
RF
VDD/3
VIN
VL
RG
tSTL
VOS + 100 µV
OS – 100 µV
FIGURE 1-4:
Most Noninverting Gain Conditions.
AC and DC Test Circuit for
VOS
V
VDD
1 µF
FIGURE 1-2:
Time.
Offset Correction Settling
RN
VDD/3
RISO
CL
VOUT
+
-
MCP6V51
VIN
RL
100 nF
RF
VIN
tODR
VL
RG
VDD
FIGURE 1-5:
Most Inverting Gain Conditions.
AC and DC Test Circuit for
tODR
VOUT
VDD/2
The circuit in Figure 1-6 tests the input’s dynamic
behavior (i.e., tSTR, tSTL and tODR). The potentiometer
balances the resistor network (VOUT should equal VREF
at DC). The op amp’s Common Mode Input Voltage is
VSS
FIGURE 1-3:
Output Overdrive Recovery.
VCM = VIN/3. The error at the input (VERR) appears at
VOUT with a noise gain of approx. 10 V/V.
1.1 kΩ 10 kΩ 500Ω
0.1%
0.1% 25 turn
VREF = VDD/3
VDD
RISO
0 Ω
1 µF
VOUT
VIN
100 nF
CL
100 pF
RL
open
MCP6V51
VL
1.1 kΩ
10 kΩ 249Ω
1%
0.1%
0.1%
FIGURE 1-6:
Test Circuit for Dynamic
Input Behavior.
2018 Microchip Technology Inc.
DS20006136A-page 7
MCP6V51
NOTES:
DS20006136A-page 8
2018 Microchip Technology Inc.
MCP6V51
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 100 pF.
2.1
DC Input Precision
35%
30%
25%
20%
15%
10%
5%
8
6
7611 Samples
TA = 25ºC
Representative Part
VDD = 4.5V
VDD = 45V
4
VDD = 4.5V
2
0
TA = +125°C
TA = +85°C
TA = +25°C
TA = - 40°C
-2
-4
-6
-8
0%
-10 -8 -6 -4 -2
0
2
4
6
8
10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Output Voltage (V)
Input Offset Voltage (μV)
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
Input Offset Voltage vs.
Output Voltage with VDD = 4.5V.
40%
8
22 Samples
TA = -40°C to +125°C
Representative Part
VDD = 45V
35%
30%
25%
20%
15%
10%
5%
6
4
VDD = 45V
2
VDD = 4.5V
0
TA = +125°C
TA = +85°C
TA = +25°C
TA = - 40°C
-2
-4
-6
-8
0%
-18 -15 -12 -9 -6 -3
0
3
6
9
12 15 18
-1
4
9
14 19 24 29 34 39 44
Output Voltage (V)
Input Offset Voltage Drift; TC1 (nV/°C)
FIGURE 2-2:
Input Offset Voltage Drift.
FIGURE 2-5:
Input Offset Voltage vs.
Output Voltage with VDD = 45V.
8.0
20
15
10
5
VDD = 4.5V
Representative Part
6.0
4.0
2.0
0.0
TA = -40°C
TA = +25°C
0
TA = +125°C
-2.0
-4.0
-6.0
-8.0
TA = +85°C
TA = +25°C
TA = - 40°C
-5
TA = +85°C
-10
-15
TA = +125°C
-20
0
-0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4
Common Mode Input Voltage (V)
5
10 15 20 25 30 35 40 45
Power Supply Voltage (V)
FIGURE 2-3:
Input Offset Voltage vs.
FIGURE 2-6:
Input Offset Voltage vs.
Power Supply Voltage.
Common Mode Voltage with VDD = 4.5V
2018 Microchip Technology Inc.
DS20006136A-page 9
MCP6V51
8.0
60%
50%
40%
30%
20%
10%
0%
VDD = 45V
Representative Part
ꢀ474 Samples
6.0
4.0
TA = +25ºC
VDD = 45V
2.0
0.0
-2.0
-4.0
-6.0
-8.0
TA = +125°C
TA = +85°C
TA = +25°C
VDD = 4.5V
TA = - 40°C
-1
4
9
14 19 24 29 34 39 44
Common Mode Input Voltage (V)
1/AOL (μV/V)
FIGURE 2-7:
Input Offset Voltage vs.
FIGURE 2-10:
DC Open-Loop Gain.
Common Mode Voltage with VDD = 45V.
160
150
140
130
120
110
90%
PSRR
80%
70%
60%
50%
40%
30%
20%
10%
0%
ꢀ488 Samples
TA = +25ºC
VDD = 45V
CMRR @ VDD = 45V
@ VDD = 4.5V
VDD = 4.5V
-50
-25
0
25
50
75
100
125
1/CMRR (μV/V)
Ambient Temperature (°C)
FIGURE 2-8:
CMRR.
FIGURE 2-11:
CMRR and PSRR vs.
Ambient Temperature.
170
35%
ꢀ488 Samples
TA = +25ºC
30%
25%
20%
15%
10%
5%
160
VDD= 45V
150
140
130
120
VDD= 4.5V
0%
-50
-25
0
25
50
75
100 125
1/PSRR (μV/V)
Ambient Temperature (°C)
FIGURE 2-9:
PSRR.
FIGURE 2-12:
DC Open-Loop Gain vs.
Ambient Temperature.
DS20006136A-page 10
2018 Microchip Technology Inc.
MCP6V51
1m
100μ
10μ
1μ
500
400
300
200
100
0
-100
-200
-300
-400
-500
VDD = 45V
TA = +85 ºC
Input Offset Current
Input Bias Current
TA = +125°C
100n
10n
1n
T
A = +85°C
TA = +25°C
TA = -40°C
100p
0
5
10 15 20 25 30 35 40 45
Input Common Mode Voltage (V)
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-13:
Input Bias and Offset
FIGURE 2-16:
Input Bias Current vs. Input
Currents vs. Common Mode Input Voltage with
TA = +85°C.
Voltage (Below VSS).
2000
VDD = 45V
TA = +125 ºC
1500
1000
500
Input Bias Current
0
-500
-1000
Input Offset Current
0
5
10 15 20 25 30 35 40 45
Input Common Mode Voltage (V)
FIGURE 2-14:
Input Bias and Offset
Currents vs. Common Mode Input Voltage with
TA = +125°C.
10n
45V
1n
IOS
100p
4.5V
IB
10p
1p
Ambient Temperature (°C)
FIGURE 2-15:
Input Bias and Offset
Currents vs. Ambient Temperature with
VDD = 45V.
2018 Microchip Technology Inc.
DS20006136A-page 11
MCP6V51
Note: Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 100 pF.
2.2
Other DC Voltages and Currents
200
150
100
50
2.5
RL = 10 kȍ
2
1.5
1
Upper (VDD - VCMH
)
VDD - VOH
0.5
0
VDD = 45V
Lower (VCML - VSS
)
VOL - VSS
VDD = 4.5V
-0.5
0
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
Ambient Temperature (°C)
Ambient Temperature (°C)
FIGURE 2-17:
Input Common Mode
FIGURE 2-20:
Output Voltage Headroom
Voltage Headroom (Range) vs. Ambient
Temperature.
vs Temperature RL = 10 kꢀ.
1000
80
60
40
VDD -VOH
100
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
20
0
VDD = 4.5V
VOL -VSS
10
1
-20
-40
-60
VDD = 45V
0
5
10
15
20
25
30
35
40
45
0.1
1
10
Power Supply Voltage (V)
Output Current Magnitude (mA)
FIGURE 2-21:
Output Short Circuit Current
FIGURE 2-18:
Output Voltage Headroom
vs. Power Supply Voltage.
vs. Output Current.
700
600
500
400
300
200
100
0
2000
RL = 1 kȍ
1500
1000
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
VDD - VOH
VDD = 45V
500
VOL - VSS
VDD = 4.5V
0
-50
-25
0
25
50
75
100
125
0
10
20
30
40
50
Power Supply Voltage (V)
Ambient Temperature (°C)
FIGURE 2-19:
Output Voltage Headroom
FIGURE 2-22:
Supply Current vs. Power
vs. Ambient Temperature.
Supply Voltage.
DS20006136A-page 12
2018 Microchip Technology Inc.
MCP6V51
Note: Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 10 kꢀ to VL and CL = 100 pF.
2.3
Frequency Response
180
160
140
120
100
80
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
80
70
60
50
40
30
20
10
VDD = 45V
PM
CMRR
PSRR+
PSRR-
VDD = 45V
VDD = 4.5V
60
GBWP
40
20
0
1
10
100
1k
10k
100k
1M
10M
-50 -25
0
25
50
75 100 125
Ambient Temperature (°C)
Frequency (Hz)
FIGURE 2-23:
CMRR and PSRR vs.
FIGURE 2-26:
Gain Bandwidth Product
Frequency.
and Phase Margin vs. Ambient Temperature.
5
4
3
2
1
0
90
80
70
60
50
40
140
120
100
80
-30
VDD = 45V
-60
Phase
-90
PM
-120
-150
-180
-210
-240
-270
60
Gain
40
GBWP
GBWP = 1.8 MHzꢀ
= 4.5V
V
R
20
0
DDꢀ
= 10 kΩ
Lꢀ
Lꢀ
C
= 100 pF
'RPꢁ3ROHꢂꢀꢃꢀP+]
-20
0
5
10 15 20 25 30 35 40 45
Common Mode Input Voltage (V)
10k
1M 10M
110000 1,000 10,00010100,0k01,000,10,000,000
11
10
1k
Frequency (Hz)
FIGURE 2-24:
Open-Loop Gain vs.
FIGURE 2-27:
Gain Bandwidth Product
Frequency with VDD = 4.5V.
and Phase Margin vs. Common Mode Input
Voltage.
1000
140
120
-30
VDD = 4.5V
100
10
1
-60
Phase
100
80
60
40
20
0
-90
-120
-150
-180
-210
-240
-270
GN:
0.1
0.01
Gain
101 V/V
11 V/V
1 V/V
GBWP = 2 MHz
V
= 45V
= 10 kΩ
= 100 pF
DDꢀ
R
C
Lꢀ
Lꢀ
0.001
0.0001
'RPꢁꢀ3ROHꢂꢀꢃꢀP+]
-20
1
10
100
1k
10k
100k
1M
10M 100M
10k
1M 10M
110000 1,000 10,00010100,0k01,000,10,000,000
11
10
1k
Frequency (Hz)
Frequency (Hz)
FIGURE 2-28:
Impedance vs. Frequency with VDD = 4.5V.
Closed-Loop Output
FIGURE 2-25:
Frequency with VDD = 45V.
Open-Loop Gain vs.
2018 Microchip Technology Inc.
DS20006136A-page 13
MCP6V51
1000
VDD =45V
100
10
GN:
1
101 V/V
11 V/V
1 V/V
0.1
0.01
0.001
0.0001
1
10
100
1k
10k
100k
1M
10M 100M
Frequency (Hz)
FIGURE 2-29:
Closed-Loop Output
Impedance vs. Frequency with VDD = 45V.
100
VDD = 45V
10
VDD = 4.5V
1
0
100
1k
10k
100k
1M
10M
Frequency (Hz)
FIGURE 2-30:
Maximum Output Voltage
Swing vs. Frequency.
120
110
100
90
80
VDD = 45V
70
60
50
40
VDD = 4.5V
30
20
10
VINPK = 100 mV
10M
100M
1G
10G
Frequency (Hz)
FIGURE 2-31:
EMIRR vs. Frequency.
DS20006136A-page 14
2018 Microchip Technology Inc.
MCP6V51
Note: Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 10 kꢀ to VL and CL = 100 pF.
2.4
Input Noise
1000
100
10
1000
100
10
VDD = 45V, green
VDD = 4.5V, blue
eni
Eni (0 Hz to f)
1
1
1
10
100
1k
10k
100k
1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5
Frequency (Hz)
FIGURE 2-32:
Input Noise Voltage Density
and Integrated Input Noise Voltage vs.
Frequency.
VDD = 4.5V
NPBW = 10 Hz
NPBW = 1 Hz
0
10
20
30
40
50
60
Time (s)
FIGURE 2-33:
Input Noise vs. Time with
1 Hz and 10 Hz Filters and VDD = 4.5V.
VDD = 45V
NPBW = 10 Hz
NPBW = 1 Hz
0
10
20
30
40
50
60
Time (s)
FIGURE 2-34:
Input Noise vs. Time with
1 Hz and 10 Hz Filters and VDD = 45V.
2018 Microchip Technology Inc.
DS20006136A-page 15
MCP6V51
Note: Unless otherwise indicated, TA = +25°C, VDD = +4.5V to +45V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 10 kꢀ to VL and CL = 100 pF.
2.5
Time Response
20
15
10
5
100
60
VDD = +/-15V
G = +1 V/V
TPCB
20
VIN
VDD = 45V
VDD = 4.5V
VOUT
-20
-60
-100
VOS
0
Temperature increased by
using heat gun for 3 seconds
-5
0
20 40 60 80 100 120 140 160 180 200
Time (s)
0
1
2
3
4
5
6
7
8
9
10
Time (μs)
FIGURE 2-35:
Input Offset Voltage vs.
FIGURE 2-38:
Noninverting Small Signal
Time with Temperature Change.
Step Response.
2000
48
42
36
30
24
18
12
6
15
10
VDD = +/-15 V
G = +1 V/V
1750
VDD
1500
VDD Bypass = 1PF
5
1250
1000
750
500
250
0
VDD = 45V
G = +1 V/V
VIN
VOUT
0
-5
-10
-15
VOS
0
-250
-6
0
10 20 30 40 50 60 70 80 90 100
Time (μs)
0
2
4
6
8
10 12 14 16 18 20
Time (ms)
FIGURE 2-36:
Input Offset Voltage vs.
FIGURE 2-39:
Noninverting Large Signal
Time at Power-Up.
Step Response.
30
20
30
V
= +/-22.5Vꢀ
VDD = +/-22.5 V
G = +1 V/V
DDꢀ
G = +1 V/V
9
,1
ꢀ ꢀꢃꢄ9
33
20
10
10
VIN
VOUT
0
-10
-20
-30
0
-10
-20
-30
VOUT
VIN
0
20 40 60 80 100 120 140 160 180 200
Time (μs)
Time (100 μs/div)
FIGURE 2-37:
The MCP6V51 Shows No
FIGURE 2-40:
Noninverting 40 VPP Step
Input Phase Reversal with Overdrive.
Response.
DS20006136A-page 16
2018 Microchip Technology Inc.
MCP6V51
2.0
1.8
1.6
1.4
1.2
1.0
0.8
VIN
VOUT
Falling Edge, VDD = 45V
Falling Edge, VDD = 4.5V
Rising Edge, VDD = 45V
Rising Edge, VDD = 4.5V
VDD = +/-15V
G = -1 V/V
-50
-25
0
25
50
75
100 125
0
1
2
3
4
5
6
7
8
9
10
Time (μs)
Ambient Temperature (°C)
FIGURE 2-41:
Inverting Small Signal Step
FIGURE 2-44:
Slew Rate vs. Ambient
Response.
Temperature.
15
10
30
20
10
0
VDD = +/-15 V
G = -1 V/V
GVIN
VOUT
5
VIN
VDD = 45 V
0
-5
G = -10V/V
VOUT
0.5V Overdrive
-10
GVIN
-20
VOUT
-10
-15
-30
0
10 20 30 40 50 60 70 80 90 100
Time (μs)
Time (100 us/div)
FIGURE 2-42:
Inverting Large Signal Step
FIGURE 2-45:
Output Overdrive Recovery
Response.
vs. Time with G = -10 V/V.
30
1m
VDD = +/-22.5 V
G = -1 V/V
0.5V Input Overdrive
VIN
20
VDD = 45V
100μ
10
0
VDD = 4.5V
tODR, high
tODR, low
10μ
1μ
-10
-20
-30
VOUT
1
10
100
1000
0
20 40 60 80 100 120 140 160 180 200
Time (μs)
Inverting Gain Magnitude (V/V)
FIGURE 2-43:
Inverting 40 VPP Step
FIGURE 2-46:
Output Overdrive Recovery
Response.
Time vs. Inverting Gain.
2018 Microchip Technology Inc.
DS20006136A-page 17
MCP6V51
NOTES:
DS20006136A-page 18
2018 Microchip Technology Inc.
MCP6V51
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
MCP6V51
PIN FUNCTION TABLE
Symbol
Description
SOT23-5
MSOP-8
1
4
6
VOUT
VIN-
VIN+
VSS
VDD
NC
Output
2
Inverting Input
3
3
Noninverting Input
Negative Power Supply
Positive Power Supply
2
4
7
5
—
1, 5, 8
Do not connect (no internal connection)
3.1
Analog Output
The analog output pins (VOUT) are low-impedance
voltage sources.
3.2
Analog Inputs
The noninverting and inverting inputs (VIN+, VIN-, …)
are high-impedance CMOS inputs with low bias
currents.
3.3
Power Supply Pins
The positive power supply (VDD) is 4.5V to 45V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD
.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
2018 Microchip Technology Inc.
DS20006136A-page 19
MCP6V51
NOTES:
DS20006136A-page 20
2018 Microchip Technology Inc.
MCP6V51
The Output Buffer drives external loads at the VOUT pin
(VREF is an internal reference voltage).
4.0
APPLICATIONS
The MCP6V51 is designed for precision applications
with requirements for small packages and low power.
Its wide supply voltage range and low quiescent current
make the MCP6V51 devices ideal for industrial
applications.
The Oscillator runs at fOSC1 = 200 kHz. Its output is
divided by two, to produce the chopping clock rate of
fCHOP = 100 kHz.
The internal Power-on Reset (POR) starts the part in a
known good state, protecting against power supply
brown-outs.
4.1
Overview of Zero-Drift Operation
The Digital Control block controls switching and POR
events.
Figure 4-1 shows
MCP6V51 zero-drift op amp. This diagram will be used
to explain how slow voltage errors are reduced in this
architecture (much better VOS
CMRR, PSRR, AOL and 1/f noise).
a simplified diagram of the
4.1.2
CHOPPING ACTION
, VOS/TA (TC1),
Figure 4-2 shows the amplifier connections for the first
phase of the chopping clock and Figure 4-3 shows the
connections for the second phase. Its slow voltage
errors alternate in polarity, making the average error
small.
VREF
-
Output
Buffer
VOUT
VIN+
+
VIN+
VIN-
+
-
+
-
+
-
Main
Amp.
VIN-
+
-
Main
Amp.
NC
+
-
NC
+
-
Low-Pass
Filter
Low-Pass
Filter
+
-
+
-
Aux.
Amp.
Chopper
Input
Switches
Chopper
Output
Switches
+
-
+
-
Aux.
Amp.
FIGURE 4-2:
First Chopping Clock Phase;
Equivalent Amplifier Diagram.
Oscillator
Digital Control
POR
VIN+
FIGURE 4-1:
Simplified Zero-Drift Op
+
-
Amp Functional Diagram.
+
-
Main
Amp.
VIN-
NC
+
-
4.1.1
BUILDING BLOCKS
The Main Amplifier is designed for high gain and
bandwidth, with a differential topology. Its main input
pair (+ and - pins at the top left) is used for the higher
frequency portion of the input signal. Its auxiliary input
pair (+ and - pins at the bottom left) is used for the
low-frequency portion of the input signal and corrects
the op amp’s input offset voltage. Both inputs are
added together internally.
Low-Pass
Filter
+
-
+
-
Aux.
Amp.
The Auxiliary Amplifier, Chopper Input Switches and
Chopper Output Switches provide a high DC gain to the
input signal. DC errors are modulated to higher
frequencies, while white noise is modulated to low
frequency.
FIGURE 4-3:
Phase; Equivalent Amplifier Diagram.
Second Chopping Clock
The Low-Pass Filter reduces high-frequency content,
including harmonics of the chopping clock.
2018 Microchip Technology Inc.
DS20006136A-page 21
MCP6V51
In addition, the input is protected by a pair of back-to-
back diodes across the amplifier’s inputs, which will
limit the voltage that can develop across the inputs to
about +/-1V.
4.2
Other Functional Blocks
4.2.1
INPUT PROTECTION
The MCP6V51 can be operated on a single supply
voltage ranging from 4.5V to 45V, or in a split-supply
application (+/-2.25V to +/- 22.5V). The input common-
mode range extends below the negative rail,
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs;
Figure 4-5 shows one approach of protecting these
inputs. D1 and D2 may be small-signal silicon diodes,
Schottky diodes for lower clamping voltages or
diode-connected FETs for low leakage.
VCML = VSS - 0.3V at 25°C, while maintaining high
CMRR (135 dB min. at 45VDD). The upper range of the
input common-mode is limited to VCMH = VDD - 2.1V.
To ensure proper operation, these VCM limits, along
with any potential overvoltage/current conditions as
described in the following paragraphs, should be taken
into consideration.
VDD
U1
D1
4.2.1.1
Phase Reversal
MCP6V51
V1
V2
+
-
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-37 shows an input voltage
exceeding both supplies with no phase inversion.
D2
VOUT
4.2.1.2
Input Voltage Limits
FIGURE 4-5:
Protecting the Analog Inputs
against High Voltages.
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1, Absolute Maximum
Ratings †). This requirement is independent of the
current limits discussed later on.
4.2.1.3
Input Current Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see Section 1.1, Absolute
The ESD protection on the inputs can be depicted as
shown in Figure 4-4. This structure was chosen to
protect the input transistors against many (but not all)
overvoltage conditions and to minimize input bias
current (IB).
Maximum
Ratings †).
This
requirement
is
independent of the voltage limits discussed previously.
Figure 4-6 shows one approach to protecting these
inputs. The R1 and R2 resistors limit the possible
current in or out of the input pins (and into D1 and D2).
Once the diode is forward biased, any current will flow
into the VDD supply line.
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below VSS. They also
clamp any voltages well above VDD; their breakdown
voltage is high enough to allow normal operation but
not low enough to protect against slow overvoltage
(beyond VDD) events. Very fast ESD events (that meet
the specification) are limited so that damage can
largely be prevented.
VDD
U1
D1
MCP6V51
V1
V2
+
-
R1
R2
D2
VOUT
Bond
VDD
Pad
Bond
Pad
Bond
Pad
Input
Stage
VSS – minV1 V2
VIN+
VIN-
min(R1 R2 --------------------------------------------
10 mA
maxV1 V2 – VDD
min(R1 R2 -----------------------------------------------
Bond
Pad
10 mA
VSS
FIGURE 4-6:
Against High Currents.
Protecting the Analog Inputs
FIGURE 4-4:
Structures.
Simplified Analog Input ESD
DS20006136A-page 22
2018 Microchip Technology Inc.
MCP6V51
It is also possible to connect the diodes to the left of the
R1 and R2 resistors. In this case, the currents through
the D1 and D2 diodes need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN-) should be very small.
To derive the Power dissipation of the device, add the
terms for the devices’ quiescent power and the load
power as shown in Equation 4-2:
EQUATION 4-2:
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the Common
Mode Voltage (VCM) is below ground (VSS); see
Figure 2-16.
PD = VDD – VSS IQ + IOUT VDD – VOUT
This assumes that the device is sourcing the load
current, i.e. current flowing from the VDD supply into the
4.2.2
INTEGRATED EMI FILTER
I
×(VOUT - V
)
load. Use the term ( OUT
SS ) when the
device is sinking current. Note that this simple example
assumes a constant (DC) signal current flow.
The MCP6V51 has an integrated low-pass filter in its
inputs for the dedicated purpose of reducing any
electromagnetic or RF interference (EMI, RFI). The on-
chip filter is designed as a 2nd-order RC low-pass,
The thermal shutdown circuitry activates as soon as
the junction temperature reaches approximately
+175°C causing the amplifier’s output stage to be tri-
stated (high-impedance) effectively disabling any
output current flow. The amplifier will remain in this
disabled state until the junction temperature has cooled
down to approximately +160°C. At this point the
thermal shutdown circuitry will enable the output stage
of the MCP6V51 amplifier and the device will resume
normal operation.
which
sets a bandwidth limit of approximately
115 MHz and attenuates the high-frequency
interference. Performance results of the MCP6V51’s
EMI rejection ratio (EMIRR) under various conditions
can be seen in Figure 2-31 and Figure 2-33.
4.2.3
RAIL-TO-RAIL OUTPUT
The Output Voltage Range of the MCP6V51 zero-drift
op amps is typically VDD - 100 mV, and VSS + 50 mV
when RL = 10 kꢀ is connected to VDD/2 and
VDD = 45V. Refer to Figure 2-18, Figure 2-19 and
Figure 2-20 for more information.
If a fault condition persists, for example the amplifier’s
output (VOUT) is shorted causing excessive output
current, the thermal shutdown circuity may be triggered
again and the previously described cycle repeats. This
may continue until the fault condition is removed.
4.2.4
THERMAL SHUTDOWN
It should be noted that the thermal shutdown feature of
the MCP6V51 does not guarantee that the device will
remain undamaged when operated under stress
conditions during which the device is placed into the
shutdown mode.
Under certain operating conditions, the MCP6V51
amplifier can be subjected to a rise of its die
temperature above the specified maximum junction
temperature of 150°C. To control possible overheating
and damage, the MCP6V51 amplifier has internal
thermal shutdown circuitry. Especially when operating
with the maximum supply voltage of 45V, observe that
the ambient temperature and/or the amplifier’s output
current are such that the junction temperature remains
below the specified limit. To estimate the junction
temperature (TJ) consider these factors: the total power
dissipation of the device (PD) and the ambient
temperature at the device package (TA), and use
Equation 4-1 below.
4.3
Application Tips
4.3.1
INPUT OFFSET VOLTAGE OVER
TEMPERATURE
Table DC Electrical Specifications gives both the
linear and quadratic temperature coefficients (TC1 and
TC2) of input offset voltage. The input offset voltage, at
any temperature in the specified range, can be
calculated as follows:
EQUATION 4-1:
EQUATION 4-3:
VOSTA = VOS + TC1T + TC2T2
TJ = PD JA + TA
Where:
Where:
JA
=
the thermal resistance between the die
and the ambient environment, as
shown in Temperature
T
OS(TA)
VOS
=
=
=
=
=
TA – 25°C
V
Input offset voltage at TA
Input offset voltage at +25°C
Linear temperature coefficient
Quadratic temperature coefficient
Specifications
TC1
TC2
2018 Microchip Technology Inc.
DS20006136A-page 23
MCP6V51
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. These zero-drift op amps have a different
output impedance compared to standard linear op
amps, due to their unique topology.
4.3.2
DC GAIN PLOTS
Figure 2-8, Figure 2-9 and Figure 2-10 are
histograms of the reciprocals (in units of µV/V) of
CMRR, PSRR and AOL, respectively. They represent
the change in Input Offset Voltage (VOS) with a change
in Common Mode Input Voltage (VCM), Power Supply
Voltage (VDD) and Output Voltage (VOUT).
When driving a capacitive load with these op amps, a
series resistor at the output (RISO in Figure 4-8)
improves the feedback loop’s phase margin (stability)
by making the output load resistive at higher
frequencies. The bandwidth will be generally lower
than the bandwidth with no capacitive load.
The 1/AOL histogram is centered near 0 µV/V because
the measurements are dominated by the op amp’s
input noise. The negative values shown represent
noise and tester limitations, not unstable behavior.
Production tests make multiple VOS measurements,
which validates an op amp's stability; an unstable part
would show greater VOS variability or the output would
stick at one of the supply rails.
Figure 4-7 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
load capacitance (CL). The y-axis is the resistance
(RISO).
GN is the circuit’s noise gain. For non-inverting gains,
GN and the Signal Gain are equal. For inverting gains,
GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
4.3.3
OFFSET AT POWER-UP
When these parts power up, the input offset (VOS
)
starts at its uncorrected value (usually less than
±5 mV). Circuits with high DC gain may cause the
output to reach one of the two rails. In this case, the
time to a valid output is delayed by an output overdrive
time (tODR), in addition to the start-up time (tSTR).
1000
VDD = 45 V
RL = 10 kȍ
100
To avoid this extended start-up time, reducing the gain
is one method. Adding a capacitor across the feedback
resistor (RF) is another method.
10
GN:
1 V/V
10 V/V
100 V/V
4.3.4
SOURCE RESISTANCES
The input bias currents have two significant
components: switching glitches that dominate at room
temperature and below, and input ESD diode leakage
currents that dominate at +85°C and above.
1
10p
100p
1n
10n
100n
1μ
Normalized Load Capacitance; CL/GN (F)
FIGURE 4-7:
for Capacitive Loads.
Recommended RISO Values
Make the resistances seen by the inputs small and
equal. This minimizes the output offset voltage caused
by the input bias currents.
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify the RISO value until the
response is reasonable. Bench evaluation is helpful.
The inputs should see a resistance on the order of 10ꢀ
to 1 kꢀ at high frequencies (i.e., above 1 MHz). This
helps minimize the impact of switching glitches, which
are very fast, on overall performance. In some cases, it
may be necessary to add resistors in series with the
inputs to achieve this improvement in performance.
Small input resistances may be needed for high gains.
Without them, parasitic capacitances might cause
positive feedback and instability.
4.3.5
SOURCE CAPACITANCE
The capacitances seen by the two inputs should be
small. Large input capacitances and source
resistances, together with high gain, can lead to
instability.
4.3.6
CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
DS20006136A-page 24
2018 Microchip Technology Inc.
MCP6V51
CN and RN form a low-pass filter that affects the signal
at VP. This filter has a single real pole at 1/(2πRNCN).
4.3.7
STABILIZING OUTPUT LOADS
This family of zero-drift op amps has an output
impedance (Figure 2-28 and Figure 2-29) that has a
double zero when the gain is low. This can cause a
large phase shift in feedback networks that have low-
impedance near the part’s cross-over frequency. This
phase shift can cause stability problems.
The largest value of RF that should be used depends
on the noise gain (see GN in Section 4.3.6
“Capacitive Loads”), CG and the open-loop gain’s
phase shift. An approximate limit for RF is shown in
Equation 4-4.
Figure 4-8 shows that the load on the output is
(RL + RISO)||(RF + RG), where RISO is before the load.
This load needs to be large enough to maintain
stability; it is recommended to design for a total load of
10 kꢀ, or higher.
EQUATION 4-4:
3.5 pF
RF 10 k --------------- G N2
CG
Some applications may modify these values to reduce
either output loading or gain peaking (step-response
overshoot).
RISO
RG
RF
VOUT
-
At high gains, RN needs to be small, in order to prevent
positive feedback and oscillations. Large CN values
can also help.
RL
CL
+
U1
MCP6V51
Output Resistor, RISO
FIGURE 4-8:
Stabilizes Capacitive Loads
,
4.3.8 GAIN PEAKING
Figure 4-9 shows an op amp circuit that represents
noninverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage
and VM is the input). The CN and CG capacitances
represent the total capacitance at the input pins; they
include the op amp’s Common Mode Input
Capacitance (CCM), board parasitic capacitance and
any capacitor placed in parallel. The CFP capacitance
represents the parasitic capacitance coupling between
the output and the non-inverting input pins.
CN
CFP
RN
VP
U1
+
VOUT
MCP6V51
-
VM
RG
RF
CG
FIGURE 4-9:
Amplifier with Parasitic
Capacitance.
CG acts in parallel with RG (except for a gain of +1 V/
V), which causes an increase in gain at high
frequencies. CG also reduces the phase margin of the
feedback loop, which becomes less stable. This effect
can be reduced by either reducing CG or RF||RG.
2018 Microchip Technology Inc.
DS20006136A-page 25
MCP6V51
Typical thermojunctions have temperature-to-voltage
conversion coefficients of 1 to 100 µV/°C (sometimes
higher).
4.3.9
REDUCING UNDESIRED NOISE
AND SIGNALS
Reduce undesired noise and signals with:
Microchip’s AN1258 Application Note – “Op Amp
Precision Design: PCB Layout Techniques” (DS01258)
contains in-depth information on PCB layout
techniques that minimize thermojunction effects. It also
discusses other effects, such as crosstalk,
impedances, mechanical stresses and humidity.
• Low bandwidth signal filters:
- Minimize random analog noise
- Reduce interfering signals
• Good PCB layout techniques:
- Minimize crosstalk
- Minimize parasitic capacitances and
inductances that interact with fast switching
edges
4.3.11.2
Crosstalk
DC crosstalk causes offsets that appear as a larger
input offset voltage. Common causes include:
• Good power supply design:
• Common mode noise (remote sensors)
• Ground loops (current return paths)
• Power supply coupling
- Isolation from other parts
- Filtering of interference on supply line(s)
4.3.10
SUPPLY BYPASSING AND
FILTERING
Interference from the mains (usually 50 Hz or 60 Hz)
and other AC sources can also affect the DC
performance. Nonlinear distortion can convert these
signals to multiple tones, including a DC shift in voltage.
When the signal is sampled by an ADC, these AC
signals can also be aliased to DC, causing an apparent
shift in offset.
With this operational amplifier, the power supply pins
(only VDD for single supply) should have a low-ESR
ceramic bypass capacitor (i.e., 0.01 µF to 0.1 µF)
within 2 mm of the pins for good high-frequency
decoupling.
It is recommended to place a bulk capacitor (i.e., 1 µF
or larger) within 100 mm of the device to provide large,
slow currents. This bulk capacitor can be shared with
other low-noise analog parts.
To reduce interference:
- Keep traces and wires as short as possible
- Use shielding
- Use ground plane (at least a star ground)
- Place the input signal source near the DUT
- Use good PCB layout techniques
In some cases, high-frequency power supply noise
(e.g., switched-mode power supplies) may cause
undue intermodulation distortion, with a DC offset shift;
this noise needs to be filtered. Adding a small resistor
or ferrite bead into the supply connection can be
helpful.
- Use a separate power supply filter (bypass
capacitors) for these zero-drift op amps
4.3.11.3
Miscellaneous Effects
4.3.11
PCB DESIGN FOR DC PRECISION
Keep the resistances seen by the input pins as small
and as near to equal as possible, to minimize bias
current-related offsets.
In order to achieve DC precision on the order of ±1 µV,
many physical errors need to be minimized. The design
of the Printed Circuit Board (PCB), the wiring and the
thermal environment have a strong impact on the
precision achieved. A poor PCB design can easily be
more than 100 times worse than the MCP6V51 op
amps’ specifications.
Make the (trace) capacitances seen by the input pins
small and equal. This is helpful in minimizing switching
glitch-induced offset voltages.
Bending a coax cable with a radius that is too small
causes a small voltage drop to appear on the center
conductor (the triboelectric effect). Make sure the
bending radius is large enough to keep the conductors
and insulation in full contact.
4.3.11.1
PCB Layout
Any time two dissimilar metals are joined together, a
temperature-dependent voltage appears across the
junction (the Seebeck or thermojunction effect). This
effect is used in thermocouples to measure
temperature. The following are examples of
thermojunctions on a PCB:
Mechanical stresses can make some capacitor types
(such as some ceramics) output small voltages. Use
more appropriate capacitor types in the signal path and
minimize mechanical stresses and vibration.
Humidity can cause electrochemical potential voltages
to appear in a circuit. Proper PCB cleaning helps, as
does the use of encapsulants.
• Components (resistors, op amps, …) soldered to
a copper pad
• Wires mechanically attached to the PCB
• Jumpers
• Solder joints
• PCB vias
DS20006136A-page 26
2018 Microchip Technology Inc.
MCP6V51
4.4
Typical Applications
0.01C
100R
VDD
1 kꢀ
+5V
4.4.1
LOW-SIDE CURRENT SENSE
R
R
+
-
ADC
The common-mode input range of the MCP6V51
typically extend 0.3V below ground (VSS), which makes
this amplifier a good choice for Low-side current sense
application especially where operation on higher
supply voltages is required. One such example is
shown in Figure 4-10. Here, the load current (IL)
ranges from 0A to 1.5A, which results in an voltage
drop across the shunt resistor of 0 to 75 mV. The gain
on the MCP6V51 is set to 201 V/V, which gives an
output voltage range of about 0V to +15V.
0.2R
0.2R
U1
MCP6V51
-
R
R
+
FIGURE 4-11:
Simple Design.
Figure 4-13 shows a higher performance circuit for a
Wheatstone bridge signal conditioning design. This
example offers a symmetric, high impedance load to
the bridge with superior CMRR performance. It
maintains this high CMRR by driving the signal
differentially into the ADC.
40VDD
Load
MCP6V51
40VDD
U1
200
MCP6V51
IL
+
-
VOUT
VDD
RSHUNT
1 µF
0.05ꢀ
RG
100ꢀ
R
R
R
R
RF
20 k
3 k
10 nF
VDD
200
1 µF
20 kꢀ
ADC
CF
8.2 nF
200
3 k
FIGURE 4-10:
1.5A Max Load Current.
Low-Side Current Sense for
10 nF
20 k
1 µF
This circuit example can be adapted to a wide range of
similar applications:
- for VDD voltages from 4.5V up to 45V
200
- adjusting the shunt resistor and/or gain for
higher or lower load currents.
MCP6V51
Because the MCP6V51 has a very low offset drift and
virtually no 1/f noise, very small shunt resistor values
can be selected, which helps in mediating the heating
and size problems that may arise in such applications.
FIGURE 4-12:
Higher Performance Design.
4.4.2
WHEATSTONE BRIDGE
Many sensors are configured as Wheatstone bridges.
Strain gages and pressure sensors are two common
examples. These signals can be small and the
common mode noise large. Amplifier designs with high
differential gain are desirable.
Figure 4-11 shows how to interface to a Wheatstone
bridge with a minimum of components. Because the
circuit is not symmetric, the ADC input is single-ended
and there is a minimum of filtering; the CMRR is good
enough for moderate common mode noise.
2018 Microchip Technology Inc.
DS20006136A-page 27
MCP6V51
4.4.3
The ratiometric circuit in Figure 4-13 conditions a
two-wire RTD for applications with limited
RTD SENSOR
a
temperature range. U1 acts as a difference amplifier,
with a low-frequency pole. The sensor’s wiring
resistance (RW) is corrected in firmware. Failure (open)
of the RTD is detected by an out-of-range voltage.
VDD
RT
RN
34.8 kꢀ
10 nF
10.0 kꢀ
RF
RW
2 Mꢀ
+
U1
RRTD
MCP6V51
RG
10.0 kꢀ
-
100ꢀ
1 kꢀ
RF
2 Mꢀ
RW
100 nF
+5V
RB
4.99 kꢀ
10 nF
1.0 µF
+
-
ADC
FIGURE 4-13:
RTD Sensor.
DS20006136A-page 28
2018 Microchip Technology Inc.
MCP6V51
5.3
Application Notes
5.0
DESIGN AIDS
The following Microchip Application Notes are
available on the Microchip web site at www.microchip.
com/appnotes and are recommended as supplemental
reference resources.
Microchip provides the basic design aids needed for
the MCP6V51 op amp.
5.1
Microchip Advanced Part Selector
(MAPS)
• ADN003 Application Note – “Select the Right
Operational Amplifier for your Filtering Circuits”
(DS21821)
MAPS is a software tool that helps efficiently identify
Microchip devices that fit particular design
a
• AN722 Application Note – “Operational Amplifier
Topologies and DC Specifications” (DS00722)
requirement. Available at no cost from the Microchip
web site at www.microchip.com/maps, MAPS is an
overall selection tool for Microchip’s product portfolio
that includes Analog, Memory, MCUs and DSCs. Using
this tool, a customer can define a filter to sort features
for a parametric search of devices and export
side-by-side technical comparison reports. Helpful links
are also provided for data sheets, purchase and
sampling of Microchip parts.
• AN723 Application Note – “Operational Amplifier
AC Specifications and Applications” (DS00723)
• AN884 Application Note – “Driving Capacitive
Loads With Op Amps” (DS00884)
• AN990 Application Note – “Analog Sensor
Conditioning Circuits - An Overview” (DS00990)
• AN1177 Application Note – “Op Amp Precision
Design: DC Errors” (DS01177)
5.2
Analog Demonstration and
Evaluation Boards
• AN1228 Application Note – “Op Amp Precision
Design: Random Noise” (DS01228)
• AN1258 Application Note – “Op Amp Precision
Design: PCB Layout Techniques” (DS01258)
Microchip offers
a
broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help customers achieve faster time to
market. For a complete listing of these boards and their
corresponding user’s guides and technical information,
visit the Microchip web site at www.microchip.com/
analog tools.
Some boards that are especially useful are:
• MCP6V01 Thermocouple Auto-Zeroed Reference
Design (P/N MCP6V01RD-TCPL)
• MCP6XXX Amplifier Evaluation Board 1
(P/N DS51667)
• MCP6XXX Amplifier Evaluation Board 2
(P/N DS51668)
• MCP6XXX Amplifier Evaluation Board 3
(P/N DS51673)
• MCP6XXX Amplifier Evaluation Board 4
(P/N DS51681)
• Active Filter Demo Board Kit (P/N DS51614)
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board
(P/N SOIC8EV)
• 14-Pin SOIC/TSSOP/DIP Evaluation Board
(P/N SOIC14EV)
2018 Microchip Technology Inc.
DS20006136A-page 29
MCP6V51
NOTES:
DS20006136A-page 30
2018 Microchip Technology Inc.
MCP6V51
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
5-Lead SOT-23
Example
AADQY
32256
Example
8-Lead MSOP
6V51
832256
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2018 Microchip Technology Inc.
DS20006136A-page 31
MCP6V51
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.20 C 2X
D
e1
A
D
N
E/2
E1/2
E1
E
(DATUM D)
(DATUM A-B)
0.15 C D
2X
NOTE 1
1
2
e
B
NX b
0.20
C A-B D
TOP VIEW
A
A2
A1
A
0.20 C
SEATING PLANE
A
SEE SHEET 2
C
SIDE VIEW
Microchip Technology Drawing C04-091-OT Rev E Sheet 1 of 2
DS20006136A-page 32
2018 Microchip Technology Inc.
MCP6V51
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
c
T
L
L1
VIEW A-A
SHEET 1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
5
0.95 BSC
Outside lead pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
e1
A
A2
A1
E
E1
D
L
1.90 BSC
0.90
0.89
-
-
-
-
1.45
1.30
0.15
2.80 BSC
1.60 BSC
2.90 BSC
0.30
-
0.60
Footprint
Foot Angle
Lead Thickness
Lead Width
L1
0.60 REF
I
0°
0.08
0.20
-
-
-
10°
0.26
0.51
c
b
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-091-OT Rev E Sheet 2 of 2
2018 Microchip Technology Inc.
DS20006136A-page 33
MCP6V51
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X
SILK SCREEN
5
Y
Z
C
G
1
2
E
GX
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
0.95 BSC
2.80
MAX
Contact Pitch
E
C
Contact Pad Spacing
Contact Pad Width (X5)
Contact Pad Length (X5)
Distance Between Pads
Distance Between Pads
Overall Width
X
Y
G
GX
Z
0.60
1.10
1.70
0.35
3.90
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091B [OT]
DS20006136A-page 34
2018 Microchip Technology Inc.
MCP6V51
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2018 Microchip Technology Inc.
DS20006136A-page 35
MCP6V51
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20006136A-page 36
2018 Microchip Technology Inc.
MCP6V51
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2018 Microchip Technology Inc.
DS20006136A-page 37
MCP6V51
NOTES:
DS20006136A-page 38
2018 Microchip Technology Inc.
MCP6V51
APPENDIX A: REVISION HISTORY
Revision A (December 2018)
• Initial release of this document
2018 Microchip Technology Inc.
DS20006136A-page 39
MCP6V51
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
(1)
X
/XX
[X]
PART NO.
Device
Examples:
Temperature
Range
Package
Tape and Reel
Option
a)
MCP6V51T-E/OT: 5-Lead SOT-23 package,
Tape and Reel
b)
c)
MCP6V51-E/MS:
8-Lead MSOP package
MCP6V51T-E/MS: 8-Lead MSOP package,
Tape and Reel
Device:
MCP6V51: 45V, 2 MHz Zero-Drift Op Amp with EMI Filtering
Tape and Reel
Option:
Blank
T
=
=
Standard packaging (tube or tray)
Tape and Reel(1)
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
Temperature
Range:
E
=
-40C to +125C (Extended)
Package:
OT
MS
=
=
5-Lead Plastic Small Outline Transistor (SOT-23)
8-Lead Plastic Micro Small Outline Package
(MSOP)
2018 Microchip Technology Inc.
DS20006136A-page 40
MCP6V51
NOTES:
DS20006136A-page 41
2018 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-3968-4
== ISO/TS 16949 ==
2018 Microchip Technology Inc.
DS20006136A-page 42
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Australia - Sydney
Tel: 61-2-9868-6733
India - Bangalore
Tel: 91-80-3090-4444
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Beijing
Tel: 86-10-8569-7000
India - New Delhi
Tel: 91-11-4160-8631
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
China - Chengdu
Tel: 86-28-8665-5511
India - Pune
Tel: 91-20-4121-0141
Finland - Espoo
Tel: 358-9-4520-820
China - Chongqing
Tel: 86-23-8980-9588
Japan - Osaka
Tel: 81-6-6152-7160
Web Address:
www.microchip.com
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
China - Dongguan
Tel: 86-769-8702-9880
Japan - Tokyo
Tel: 81-3-6880- 3770
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Guangzhou
Tel: 86-20-8755-8029
Korea - Daegu
Tel: 82-53-744-4301
Germany - Garching
Tel: 49-8931-9700
China - Hangzhou
Tel: 86-571-8792-8115
Korea - Seoul
Tel: 82-2-554-7200
Germany - Haan
Tel: 49-2129-3766400
Austin, TX
Tel: 512-257-3370
China - Hong Kong SAR
Tel: 852-2943-5100
Malaysia - Kuala Lumpur
Tel: 60-3-7651-7906
Germany - Heilbronn
Tel: 49-7131-67-3636
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
China - Nanjing
Tel: 86-25-8473-2460
Malaysia - Penang
Tel: 60-4-227-8870
Germany - Karlsruhe
Tel: 49-721-625370
China - Qingdao
Philippines - Manila
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Tel: 86-532-8502-7355
Tel: 63-2-634-9065
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
China - Shanghai
Tel: 86-21-3326-8000
Singapore
Tel: 65-6334-8870
Germany - Rosenheim
Tel: 49-8031-354-560
China - Shenyang
Tel: 86-24-2334-2829
Taiwan - Hsin Chu
Tel: 886-3-577-8366
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Israel - Ra’anana
Tel: 972-9-744-7705
China - Shenzhen
Tel: 86-755-8864-2200
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
China - Suzhou
Tel: 86-186-6233-1526
Taiwan - Taipei
Tel: 886-2-2508-8600
Detroit
Novi, MI
Tel: 248-848-4000
China - Wuhan
Tel: 86-27-5980-5300
Thailand - Bangkok
Tel: 66-2-694-1351
Italy - Padova
Tel: 39-049-7625286
Houston, TX
Tel: 281-894-5983
China - Xian
Tel: 86-29-8833-7252
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
China - Xiamen
Tel: 86-592-2388138
Norway - Trondheim
Tel: 47-7288-4388
China - Zhuhai
Tel: 86-756-3210040
Poland - Warsaw
Tel: 48-22-3325737
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Raleigh, NC
Tel: 919-844-7510
Sweden - Gothenberg
Tel: 46-31-704-60-40
New York, NY
Tel: 631-435-6000
Sweden - Stockholm
Tel: 46-8-5090-4654
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS20006136A-page 43
2018 Microchip Technology Inc.
08/15/18
©2020 ICPDF网 联系我们和版权申明