MCP6V77-EMNY [MICROCHIP]
170 μA, 2 MHz Zero-Drift Op Amps;
| 型号： | MCP6V77-EMNY |
| 厂家： | 
MICROCHIP |
| 描述： | 170 μA, 2 MHz Zero-Drift Op Amps |
| 文件： | 总48页 (文件大小：1164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP6V76/6U/7/9
170 µA, 2 MHz Zero-Drift Op Amps
Features
Description
• High DC Precision:
The Microchip Technology Inc. MCP6V76/6U/7/9
family of operational amplifiers provides input offset
voltage correction for very low offset and offset drift.
These are low-power devices with a gain bandwidth
product of 2 MHz (typical). They are unity-gain stable,
have virtually no 1/f noise and have good Power Supply
Rejection Ratio (PSRR) and Common Mode Rejection
Ratio (CMRR). These products operate with a single
supply voltage as low as 2V, while drawing
170 µA/amplifier (typical) of quiescent current.
- VOS Drift: ±150 nV/°C (maximum)
- VOS: ±25 µV (maximum)
- AOL: 111 dB (minimum, VDD = 5.5V)
- PSRR: 110 dB (minimum, VDD = 5.5V)
- CMRR: 112 dB (minimum, VDD = 5.5V)
- Eni: 0.45 µVP-P (typical), f = 0.1 Hz to 10 Hz
- Eni: 0.15 µVP-P (typical), f = 0.01 Hz to 1 Hz
• Enhanced EMI Protection:
The MCP6V76/6U/7/9 family has enhanced EMI pro-
tection to minimize any electromagnetic interference
from external sources. This feature makes it well suited
for EMI sensitive applications such as power lines,
radio stations and mobile communications, etc.
- Electromagnetic Interference Rejection Ratio
(EMIRR) at 1.8 GHz: 96 dB
• Low Power and Supply Voltages:
- IQ: 170 µA/amplifier (typical)
- Wide Supply Voltage Range: 2V to 5.5V
• Small Packages:
The Microchip Technology Inc. MCP6V76/6U/7/9 op
amps are offered in single (MCP6V76 and
MCP6V76U), dual (MCP6V77) and quad (MCP6V79)
packages. They were designed using an advanced
CMOS process.
- Singles in SC70, SOT-23
- Duals in MSOP-8, 2x3 TDFN
- Quads in TSSOP-14
• Easy to Use:
- Rail-to-Rail Input/Output
Package Types
- Gain Bandwidth Product: 2 MHz (typical)
- Unity Gain Stable
MCP6V76
SOT-23
MCP6V77
MSOP
• Extended Temperature Range: -40°C to +125°C
VDD
VOUT
VSS
VDD
1
5
4
1
8
7
6
5
VOUTA
VOUTB
Typical Applications
2
3
4
2
3
VINA–
VINB
VINB
–
+
VINA+
VIN+
VIN–
• Portable Instrumentation
• Sensor Conditioning
VSS
• Temperature Measurement
• DC Offset Correction
• Medical Instrumentation
MCP6V76U
SC70, SOT-23
MCP6V77
2×3 TDFN *
VOUTA
VDD
1
8
VIN+
VSS
VDD
1
2
3
5
Design Aids
• FilterLab® Software
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
• Application Notes
VINA
–
+
VOUTB
2
3
4
7
6
5
EP
9
VINA
VINB
VINB
–
+
VIN–
VOUT
4
VSS
MCP6V79
TSSOP
Related Parts
V
V
V
V
V
1
14
13
12
11
10
9
VOUTA
OUTD
• MCP6V11/1U/2/4: Zero-Drift, Low Power
• MCP6V31/1U/2/4: Zero-Drift, Low Power
• MCP6V61/1U: Zero-Drift 1 MHz
–
2
3
4
5
6
7
VINA
VINA
–
+
IND
+
IND
VDD
SS
• MCP6V81/1U: Zero-Drift, 5 MHz
+
VINB
VINB
+
–
INC
• MCP6V91/1U: Zero-Drift, 10 MHz
VINC
VOUTC
–
VOUTB
8
* Includes Exposed Thermal Pad (EP); see Table 3-1.
2020 Microchip Technology Inc.
DS20006323B-page 1
MCP6V76/6U/7/9
Typical Application Circuit
R1
R3
VIN
VOUT
R2
R4
R5
C2
U1
MCP6XXX
VDD/2
R2
VDD/2
U2
MCP6V76
Offset Voltage Correction for Power Driver
DS20006323B-page 2
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
1.0
1.1
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD – VSS .................................................................................................................................................................6.5V
Current at Input Pins ..............................................................................................................................................±2 mA
Analog Inputs (VIN+ and VIN-) (Note 1) .....................................................................................VSS – 1.0V to VDD+1.0V
All Other Inputs and Outputs ......................................................................................................VSS – 0.3V to VDD+0.3V
Difference Input Voltage .................................................................................................................................|VDD – VSS
|
Output Short Circuit Current ...........................................................................................................................Continuous
Current at Output and Supply Pins ......................................................................................................................±30 mA
Storage Temperature .............................................................................................................................-65°C to +150°C
Maximum Junction Temperature .......................................................................................................................... +150°C
ESD protection on all pins (HBM, CDM, MM)
MCP6V76/6U 4 kV, 1.5 kV, 400V
MCP6V77/9 4 kV, 1.5 kV, 300V
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note 1: See Section 4.2.1, Rail-to-Rail Inputs.
1.2
Specifications
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2V to +5.5V, VSS = GND,
VCM = VDD/3,VOUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF (refer to Figures 1-4 and 1-5).
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Input Offset
Input Offset Voltage
VOS
TC1
-25
—
—
+25
µV
TA = +25°C
Input Offset Voltage Drift with
Temperature (Linear Temp. Co.)
-150
+150
nV/°C TA = -40 to +125°C,
(Note 1)
Input Offset Voltage Quadratic
Temp. Co.
TC2
—
—
-30
—
—
pV/°C2 TA = -40 to +125°C
Input Offset Voltage Aging
∆VOS
±0.75
µV
dB
408 hours Life Test at
+150°,
measured at +25°C
Power Supply Rejection Ratio
Input Bias Current and Impedance
Input Bias Current
PSRR
110
125
—
IB
IB
-50
—
±1
+50
—
pA
pA
nA
pA
pA
pA
Input Bias Current across
Temperature
+20
+0.2
±60
±50
±50
TA = +85°C
IB
0
+1.5
+250
—
TA = +125°C
Input Offset Current
IOS
IOS
IOS
-250
—
Input Offset Current across
Temperature
TA = +85°C
-800
+800
TA = +125°C
Note 1: For design guidance only; not tested.
2020 Microchip Technology Inc.
DS20006323B-page 3
MCP6V76/6U/7/9
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2V to +5.5V, VSS = GND,
VCM = VDD/3,VOUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF (refer to Figures 1-4 and 1-5).
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Common Mode Input Impedance
Differential Input Impedance
Common Mode
ZCM
—
—
1013||6
1013||6
—
—
Ω||pF
Ω||pF
ZDIFF
Common Mode
Input Voltage Range Low
VCML
—
—
—
VSS 0.2
V
V
Common Mode
Input Voltage Range High
VCMH VDD + 0.3
—
—
—
Common Mode Rejection Ratio
CMRR
CMRR
103
112
122
130
dB
dB
VDD = 2V,
VCM = -0.2V to 2.3V
VDD = 5.5V,
VCM = -0.2V to 5.8V
Open-Loop Gain
DC Open-Loop Gain (large signal)
AOL
AOL
96
132
137
—
—
dB
dB
VDD = 2V,
VOUT = 0.3V to 1.8V
111
VDD = 5.5V,
VOUT = 0.3V to 5.3V
Output
Minimum Output Voltage Swing
VOL
VOL
VSS
—
VSS + 35 VSS + 121
mV RL = 2 kΩ, G = +2,
0.5V input overdrive
VSS + 3.5
—
VDD
—
mV RL = 20 kΩ, G = +2,
0.5V input overdrive
Maximum Output Voltage Swing
Output Short Circuit Current
VOH VDD – 121 VDD – 45
mV RL = 2 kΩ, G = +2,
0.5V input overdrive
VOH
—
VDD – 4.5
mV RL = 20 kΩ, G = +2,
0.5V input overdrive
ISC
ISC
—
—
±9
—
—
mA VDD = 2V
±26
mA VDD = 5.5V
Power Supply
Supply Voltage
VDD
IQ
2
—
170
1.2
5.5
260
1.6
V
Quiescent Current per Amplifier
POR Trip Voltage
100
0.9
µA
V
IO = 0
VPOR
Note 1: For design guidance only; not tested.
DS20006323B-page 4
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
TABLE 1-2:
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2V to +5.5V, VSS = GND,
VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF (refer to Figure 1-4 and Figure 1-5).
Parameters
Sym. Min. Typ. Max. Units
Conditions
Amplifier AC Response
Gain Bandwidth Product
Slew Rate
GBWP
SR
—
—
—
2
—
—
—
MHz
V/µs
°
1.0
60
Phase Margin
PM
G = +1
Amplifier Noise Response
Input Noise Voltage
Eni
Eni
eni
ini
—
—
—
—
0.15
0.45
21
—
—
—
—
µVP-P f = 0.01 Hz to 1 Hz
µVP-P f = 0.1 Hz to 10 Hz
nV/√Hz f < 2 kHz
Input Noise Voltage Density
Input Noise Current Density
Amplifier Distortion (Note 1)
Intermodulation Distortion (AC)
Amplifier Step Response
Start Up Time
5
fA/√Hz
IMD
—
11
—
µVPK VCM tone = 100 mVPK at 1 kHz, GN = 1
tSTR
tSTL
—
—
200
15
—
—
µs
µs
G = +1, 0.1% VOUT settling (Note 2)
Offset Correction Settling Time
G = +1, VIN step of 2V,
VOS within 100 µV of its final value
Output Overdrive Recovery Time tODR
—
40
—
µs
G = -10, ±0.5V input overdrive to VDD/2,
VIN 50% point to VOUT 90% point (Note 3)
EMI Protection
EMI Rejection Ratio
EMIRR
—
—
—
—
75
89
96
98
—
—
—
—
dB
VIN = 0.1 VPK, f = 400 MHz
VIN = 0.1 VPK, f = 900 MHz
VIN = 0.1 VPK, f = 1800 MHz
VIN = 0.1 VPK, f = 2400 MHz
Note 1: These parameters were characterized using the circuit in Figure 1-6. In Figures 2-36 and 2-37, there is
an IMD tone at DC, a residual tone at 1 kHz and other IMD tones and clock tones.
2: High gains behave differently; see Section 4.3.2, Offset at Power Up.
3: tODR includes some uncertainty due to clock edge timing.
TABLE 1-3:
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2V to +5.5V, VSS = GND.
Parameters
Temperature Ranges
Sym.
Min.
Typ.
Max.
Units
Conditions
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
TA
TA
TA
-40
-40
-65
—
—
—
+125
+125
+150
°C
°C
°C
(Note 1)
Thermal Package Resistances
Thermal Resistance, 5L-SC-70
JA
JA
JA
JA
JA
—
—
—
—
—
209
201
53
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 8L-2x3 TDFN
Thermal Resistance, 8L-MSOP
Thermal Resistance, 14L-TSSOP
211
100
Note 1: Operation must not cause TJ to exceed Maximum Junction Temperature specification (+150°C).
2020 Microchip Technology Inc.
DS20006323B-page 5
MCP6V76/6U/7/9
1.3
Timing Diagrams
1.4
Test Circuits
The circuits used for most DC and AC tests are shown
in Figures 1-4 and 1-5. Lay out the bypass capacitors
as discussed in Section 4.3.9 “Supply Bypassing
and Filtering”. RN is equal to the parallel combination
of RF and RG to minimize bias current effects.
2V to 5.5V
2V
0V
VDD
tSTR
1.001(VDD/3)
0.999(VDD/3)
VOUT
VDD
1 µF
RN
VIN
FIGURE 1-1:
Amplifier Start Up.
RISO
CL
VOUT
MCP6V7X
VIN
RL
100 nF
RF
VDD/3
tSTL
VOS + 100 µV
OS – 100 µV
VL
RG
VOS
V
FIGURE 1-4:
AC and DC Test Circuit for
Most Noninverting Gain Conditions.
FIGURE 1-2:
Offset Correction Settling
Time.
VDD
1 µF
RN
VDD/3
VIN
RISO
CL
VOUT
MCP6V7X
tODR
RL
100 nF
RF
VIN
VDD
VL
RG
tODR
VOUT
VDD/2
FIGURE 1-5:
AC and DC Test Circuit for
Most Inverting Gain Conditions.
VSS
The circuit in Figure 1-6 tests the input’s dynamic
FIGURE 1-3:
Output Overdrive Recovery.
behavior (i.e., IMD, tSTR, tSTL and tODR). The
potentiometer balances the resistor network (VOUT
should equal VREF at DC). The op amp’s Common
mode input voltage is VCM = VIN/2. The error at the
input (VERR) appears at VOUT with a noise gain of
10 V/V.
11.0 kΩ 100 kΩ 500Ω
0.1%
0.1% 25 turn
VREF = VDD/3
VDD
RISO
0 Ω
1 µF
VOUT
VIN
100 nF
CL
30 pF
RL
open
MCP6V7X
VL
11.0 kΩ
100 kΩ 249Ω
1%
0.1%
0.1%
FIGURE 1-6:
Test Circuit for Dynamic
Input Behavior.
DS20006323B-page 6
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF.
2.1
DC Input Precision
8
6
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
28 Samples
TA = 25ºC
VDD = 5.5V
TA = +125°C
4
TA
TA
TA
=
=
=
+85°C
+25°C
- 40°C
2
VDD = 2V
0
-2
-4
-6
-8
Representative Part
VCM = VCML
0%
-2 -1.5 -1 -0.5 0 0.5
1 1.5 2 2.5 3 3.5 4
Input Offset Voltage (µV)
Power Supply Voltage (V)
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
Input Offset Voltage vs.
Power Supply Voltage with VCM = VCML
.
8
6
60%
50%
40%
30%
20%
10%
0%
28 Samples
TA = -40°C to +125°C
TA
TA
TA
=
=
=
- 40°C
+25°C
+85°C
4
2
VDD = 5.5V
TA = +125°C
VDD = 2V
0
-2
-4
-6
-8
Representative Part
VCM = VCMH
-12 -10 -8 -6 -4 -2
0
2
4
6
8 10 12
Input Offset Voltage Drift; TC1 (nV/°C)
Power Supply Voltage (V)
FIGURE 2-5:
Input Offset Voltage vs.
FIGURE 2-2:
Input Offset Voltage Drift.
Power Supply Voltage with VCM = VCMH
.
8
80%
70%
60%
50%
40%
30%
20%
10%
0%
Representative Part
VDD = 2.0V
28 Samples
6
4
TA = -40°C to +125°C
VDD = 5.5V
2
0
TA = +125°C
VDD = 2V
-2
-4
-6
-8
TA
TA
TA
=
=
=
+85°C
+25°C
-40°C
-200 -160 -120 -80 -40
Input Offset Voltage Quadratric Temp Co;
0
40
80 120
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Output Voltage (V)
TC2 (pV/°C2)
FIGURE 2-6:
Output Voltage with VDD = 2.0V.
Input Offset Voltage vs.
FIGURE 2-3:
Quadratic Temp. Co.
Input Offset Voltage
2020 Microchip Technology Inc.
DS20006323B-page 7
MCP6V76/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF.
8
160
6
TA
TA
TA
=
=
=
- 40°C
+25°C
+85°C
150
140
130
120
110
4
2
PSRR
TA = +125°C
0
-2
-4
-6
-8
CMRR @ VDD = 5.5V
@ VDD = 2V
Representative Part
VDD = 5.5V
-50
-25
0
25
50
75
100
125
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Ambient Temperature (°C)
FIGURE 2-7:
Input Offset Voltage vs.
FIGURE 2-10:
CMRR and PSRR vs.
Output Voltage with VDD = 5.5V.
Ambient Temperature.
8
170
160
150
140
VDD= 5.5V
TA = +125°C
6
TA
TA
TA
=
=
=
+85°C
+25°C
- 40°C
4
2
0
VDD= 2V
-2
-4
-6
-8
130
120
110
Representative Part
VDD = 2.0V
-50
-25
0
25
50
75
100 125
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
Ambient Temperature (°C)
Common Mode Input Voltage (V)
FIGURE 2-8:
Input Offset Voltage vs.
FIGURE 2-11:
DC Open-Loop Gain vs.
Common Mode Voltage with VDD = 2V.
Ambient Temperature.
8
Representative Part
VDD = 5.5V
6
4
TA = +125°C
TA
TA
TA
=
=
=
+85°C
+25°C
-40°C
2
0
-2
-4
-6
-8
Common Mode Input Voltage (V)
FIGURE 2-9:
Input Offset Voltage vs.
Common Mode Voltage with VDD = 5.5V.
DS20006323B-page 8
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF.
1m
1,000
100µ
10µ
1µ
800
600
400
200
0
-200
-400
-600
-800
-1,000
VDD = 5.5 V
TA = 85ºC
Input Offset Current
100n
10n
Input Bias Current
TA = +125°C
TA = +85°C
TA = +25°C
1n
TA = -40°C
100p
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Common Mode Voltage (V)
Input Voltage (V)
FIGURE 2-15:
Voltage (below VSS).
Input Bias Current vs. Input
FIGURE 2-12:
Currents vs. Common Mode Input Voltage with
TA = +85°C.
Input Bias and Offset
1000
VDD = 5.5 V
800
TA = 125ºC
600
400
Input Bias Current
200
0
-200
Input Offset Current
-400
-600
-800
-1000
Input Common Mode Voltage (V)
FIGURE 2-13:
Input Bias and Offset
Currents vs. Common Mode Input Voltage with
TA = +125°C.
1n
VDD = 5.5 V
Input Offset Current
Input Bias Current
100p
10p
1p
0.1p
Ambient Temperature (°C)
FIGURE 2-14:
Input Bias and Offset
Currents vs. Ambient Temperature with
VDD = +5.5V.
2020 Microchip Technology Inc.
DS20006323B-page 9
MCP6V76/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF.
2.2
Other DC Voltages and Currents
0.7
0.6
0.5
40
30
1 Wafer Lot
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
Upper (VCMH – VDD
)
20
0.4
0.3
0.2
0.1
10
0
-10
-20
-30
-40
0.0
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
-0.1
-0.2
-0.3
-0.4
-0.5
Lower (VCML – VSS
)
0
0.5
1
1.5
2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
-50
-25
0
25
50
75
100 125
Ambient Temperature (°C)
Power Supply Voltage (V)
FIGURE 2-16:
Input Common Mode
FIGURE 2-19:
Output Short Circuit Current
Voltage Headroom (Range) vs. Ambient
Temperature.
vs. Power Supply Voltage.
1000
200
180
160
140
120
100
80
60
40
20
0
VDD = 2V
100
10
1
VDD -VOH
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
VDD = 5.5V
VOL -VSS
0.1
1
10
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
Power Supply Voltage (V)
Output Current Magnitude (mA)
FIGURE 2-17:
Output Voltage Headroom
FIGURE 2-20:
Supply Current vs. Power
vs. Output Current.
Supply Voltage.
1.6
1.4
1.2
1
90
RL = 2 kΩ
80
VDD - VOH
70
60
50
40
30
VDD = 5.5V
0.8
VOL - VSS
0.6
800 Samples
0.4
20
1 Wafer Lot
VDD = 2V
10
0.2
0
VDD - VOH
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Ambient Temperature (°C)
FIGURE 2-18:
Output Voltage Headroom
FIGURE 2-21:
Power-On Reset Voltage vs.
vs. Ambient Temperature.
Ambient Temperature.
DS20006323B-page 10
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF.
2.3
Frequency Response
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
80
70
60
50
40
30
20
10
0
140
130
120
110
100
90
80
70
60
50
Representative Part
VDD = 5.5V
PM
CMRR
GBWP
PSRR-
VDD = 2V
PSRR+
40
30
10
100
1k
Frequency (Hz)
10k
100k
-50 -25
0
25 50 75 100 125
Ambient Temperature (°C)
FIGURE 2-22:
CMRR and PSRR vs.
FIGURE 2-25:
Gain Bandwidth Product
Frequency.
and Phase Margin vs. Ambient Temperature.
50
40
30
20
-60
3
2.5
2
90
80
70
60
50
40
30
PM
-90
Open-Loop Phase
-120
-150
-180
-210
-240
-270
1.5
1
Open-Loop Gain
VDD = 5.5V
VDD = 2V
10
0
GBWP
0
0.5
0
VDD = 2V
CL = 30 pF
-10
-20
-1
1
2
3
4
5
6
7
1.E+04
1.E+05
100k
1.E+06
1M
1.E+07
10M
10k
f (Hz)
Common Mode Input Voltage (V)
FIGURE 2-23:
Open-Loop Gain vs.
FIGURE 2-26:
Gain Bandwidth Product
Frequency with VDD = 2V.
and Phase Margin vs. Common Mode Input
Voltage.
50
40
30
-60
4
3.5
3
65
60
55
50
45
40
35
30
25
-90
Open-Loop Phase
VDD = 5.5V
-120
-150
-180
-210
-240
-270
PM
2.5
2
20
Open-Loop Gain
10
0
1.5
1
VDD = 2V
GBWP
VDD = 5.5V
-10
0.5
0
CL = 30 pF
-20
1.E+04
10k
0
1
2
3
4
5
6
1.E+05
100k
1.E+06
1M
1.E+07
10M
Output Voltage (V)
f (Hz)
FIGURE 2-24:
Open-Loop Gain vs.
FIGURE 2-27:
Gain Bandwidth Product
Frequency with VDD = 5.5V.
and Phase Margin vs. Output Voltage.
2020 Microchip Technology Inc.
DS20006323B-page 11
MCP6V76/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF.
100k
120
110
100
90
80
70
60
50
40
30
20
10
0
VDD = 2V
10k
1k
GN:
100
101 V/V
11 V/V
1 V/V
VPK = 100 mV
VDD = 5.5V
10
10k
100k
1M
10M
10M
100M
1G
10G
1k
Frequency (Hz)
Frequency (Hz)
FIGURE 2-28:
Closed-Loop Output
FIGURE 2-31:
EMIRR vs Frequency.
Impedance vs. Frequency with VDD = 2V.
10000
100k
120
100
80
VDD =5.5V
10000
10k
10010k
101000
110
60
40
20
0
EMIRR @ 2400 MHz
EMIRR @ 1800 MHz
EMIRR @ 900 MHz
EMIRR @ 400 MHz
GN:
101 V/V
11 V/V
1 V/V
VDD = 5.5V
1k
.10k
100k
1M
10M
0.01
0.10
1.00
10.00
Frequency (Hz)
RF Input Peak Voltage (Vp)
FIGURE 2-29:
Closed-Loop Output
FIGURE 2-32:
EMIRR vs RF Input Peak
Impedance vs. Frequency with VDD = 5.5V.
Voltage.
130
120
110
100
90
10
VDD = 5.5V
VDD = 2V
VDD = 5.5V
1
VDD = 2.0V
80
70
0.1
60
100000
10000000
1100k0
1010000k
100k
10100M000
10M
10k
100k
Frequency (Hz)
1M
1.E+06
1.E+04
1.E+05
Frequency (Hz)
FIGURE 2-30:
Maximum Output Voltage
FIGURE 2-33:
Channel-to-Channel
Swing vs. Frequency.
Separation vs. Frequency.
DS20006323B-page 12
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF.
2.4
Input Noise and Distortion
1000
1000
1.E+3
1m
VDD = 5.5V, green
VDD = 2V, blue
G = 11 V/V
VCM tone = 100 mVPK, f = 1 kHz
VDD = 2.0V
VDD = 5.5V
1.E+2
100µ
Residual
1 kHz tone
100
10
1
100
10
1
eni
(due to resistor
mismatch)
1.E1+01µ
1.E+10µ
DC tone
100n
1.E-1
ǻf = 64 Hz
ǻf = 2 Hz
Eni(0 Hz to f)
1.E10-2n
1
10
1.E+1
100
1.E+2
1k
1.E+3
10k
1.E+4
100k
1.E+5
1.E+0
1.E1+0 1.E10+1 11.E0+02 1.1Ek+3 1.1E0+k4 11.0E0+k5
Frequency (Hz)
Frequency (Hz)
FIGURE 2-34:
Input Noise Voltage Density
FIGURE 2-37:
Intermodulation Distortion
and Integrated Input Noise Voltage vs.
Frequency.
vs. Frequency with VDD Disturbance
(see Figure 1-6).
35
30
VDD = 2V
f < 2 kHz
NPBW = 10 Hz
VDD = 2.0V
25
20
VDD = 5.5V
15
NPBW = 1 Hz
10
5
0
-0.5 0 0.5
1
1.5
2 2.5 3 3.5 4 4.5 5 5.5 6
0
10 20 30 40 50 60 70 80 90 100
Common Mode Input Voltage (V)
Time (s)
FIGURE 2-35:
Input Noise Voltage Density
FIGURE 2-38:
Input Noise vs. Time with
vs. Input Common Mode Voltage.
1 Hz and 10 Hz Filters and VDD = 2V.
1.E+3
1m
VDD = 5.5V
G = 11 V/V
VCM tone = 100 mVPK, f = 1 kHz
VDD = 2.0V
VDD = 5.5V
1.E+2
100µ
NPBW = 10 Hz
Residual
1 kHz tone
(due to resistor
mismatch)
1.E1+01µ
1.E+10µ
DC tone
NPBW = 1 Hz
100n
1.E-1
ǻf = 64 Hz
ǻf = 2 Hz
0
10 20 30 40 50 60 70 80 90 100
Time (s)
1.E10-2n
1
10
1.E+1
100
1.E+2
1k
1.E+3
10k
1.E+4
100k
1.E+5
1.E+0
Frequency (Hz)
FIGURE 2-36:
Intermodulation Distortion
FIGURE 2-39:
Input Noise vs. Time with
vs. Frequency with VCM Disturbance (see
Figure 1-6).
1 Hz and 10 Hz Filters and VDD = 5.5V.
2020 Microchip Technology Inc.
DS20006323B-page 13
MCP6V76/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF.
2.5
Time Response
30
25
20
15
10
5
6
5
4
3
2
1
0
-1
6
5
4
3
2
1
0
VDD
VDD = 5.5V
G = +1 V/V
POR Trip Point
VDD = 5.5 V
G = +1 V/V
VOS
0
-5
0
2.5
5
7.5
10 12.5 15 17.5 20
0
1
2
3
4
5
6
7
8
9
10
Time (µs)
Time (ms)
FIGURE 2-40:
Input Offset Voltage vs.
FIGURE 2-43:
Noninverting Large Signal
Time at Power-Up.
Step Response.
6
5
VDD = 5.5 V
G = -1 V/V
VOUT
VIN
4
3
2
1
VDD = 5.5 V
G = +1 V/V
0
-1
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Time (5 µs/div)
Time (µs)
FIGURE 2-41:
The MCP6V76/6U/7/9
FIGURE 2-44:
Inverting Small Signal Step
Family Shows No Input Phase Reversal with
Overdrive.
Response.
6
5
4
3
2
1
0
VDD = 5.5 V
G = -1 V/V
VDD = 5.5V
G = +1 V/V
0
2.5
5
7.5
10 12.5 15 17.5 20
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Time (µs/div)
Time (µs)
FIGURE 2-45:
Response.
Inverting Large Signal Step
FIGURE 2-42:
Step Response.
Noninverting Small Signal
DS20006323B-page 14
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 20 kΩ to VL and CL = 30 pF.
2.0
1.8
Falling Edge, VDD = 5.5V
Rising Edge, VDD = 5.5V
1.6
1.4
1.2
1.0
0.8
Falling Edge, VDD = 2V
0.6
Rising Edge, VDD = 2V
0.4
0.2
0.0
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-46:
Slew Rate vs. Ambient
Temperature.
7
6
5
4
VDD = 5.5 V
G = -10 V/V
0.5V Overdrive
VOUT
GVIN
VOUT
3
2
GVIN
1
0
-1
Time (50 µs/div)
FIGURE 2-47:
Output Overdrive Recovery
vs. Time with G = -10 V/V.
1m
0.5V Input Overdrive
tODR, low
VDD = 2.0V
100µ
VDD = 5.5V
10µ
tODR, high
1µ
1
10
100
1000
Inverting Gain Magnitude (V/V)
FIGURE 2-48:
Output Overdrive Recovery
Time vs. Inverting Gain.
2020 Microchip Technology Inc.
DS20006323B-page 15
MCP6V76/6U/7/9
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
MCP6V76 MCP6V76U
MCP6V77
MCP6V79
Symbol
Description
SOT-23,
SOT-23
2×3 TDFN MSOP
TSSOP
SC-70
1
4
1
4
1
4
1
11
3
VOUT, VOUTA Output (Op Amp A)
2
2
VSS
Negative Power Supply
Noninverting Input (Op Amp A)
Inverting Input (Op Amp A)
Positive Power Supply
3
1
3
3
VIN+, VINA
VIN-, VINA
VDD
+
4
3
2
2
2
-
5
5
8
8
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
5
5
VINB
VINB
VOUTB
VOUTC
VINC
+
Noninverting Input (Op Amp B)
Inverting Input (Op Amp B)
Output (Op Amp B)
6
6
6
-
7
7
7
—
—
—
—
—
—
9
—
—
—
—
—
—
—
8
Output (Op Amp C)
9
-
Inverting Input (Op Amp C)
Noninverting Input (Op Amp C)
Noninverting Input (Op Amp D)
Inverting Input (Op Amp D)
Output (Op Amp D)
10
12
13
14
—
VINC
+
+
VIND
VIND
-
VOUTD
EP
Exposed Thermal Pad (EP); must be
connected to VSS
3.1
Analog Outputs
3.4
Exposed Thermal Pad (EP)
The analog output pins (VOUT) are low-impedance
voltage sources.
There is an internal connection between the exposed
thermal pad (EP) and the VSS pin; they must be
connected to the same potential on the printed circuit
board (PCB).
3.2
Analog Inputs
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (θJA).
The noninverting and inverting inputs (VIN+, VIN-, …)
are high-impedance CMOS inputs with low bias
currents.
3.3
Power Supply Pins
The positive power supply (VDD) is 2V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD
.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
DS20006323B-page 16
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
The low-pass filter reduces high-frequency content,
including harmonics of the chopping clock.
4.0
APPLICATIONS
The MCP6V76/6U/7/9 family of zero-drift op amps is
manufactured using Microchip’s state of the art CMOS
process. It is designed for applications with require-
ments for small packages and low power. Its low supply
voltage and low quiescent current make the
MCP6V76/6U/7/9 devices ideal for battery-powered
applications.
The output buffer drives external loads at the VOUT pin
(VREF is an internal reference voltage).
The oscillator runs at fOSC1 = 200 kHz. Its output is
divided by two to produce the chopping clock rate of
fCHOP = 100 kHz.
The internal POR part starts the part in a known good
state, protecting against power supply brown-outs.
4.1
Overview of Zero-Drift Operation
The digital control block controls switching and POR
events.
Figure 4-1 shows
a
simplified diagram of the
MCP6V76/6U/7/9 zero-drift op amp. This diagram will
be used to explain how slow voltage errors are reduced
in this architecture (much better VOS, ∆VOS/∆TA (TC1),
CMRR, PSRR, AOL and 1/f noise).
4.1.2
CHOPPING ACTION
Figure 4-2 shows the amplifier connections for the first
phase of the chopping clock and Figure 4-3 shows
them for the second phase. Its slow voltage errors
alternate in polarity, making the average error small.
VREF
Output
VOUT
VIN+
Buffer
VIN+
Main
VIN–
Amp.
NC
Main
VIN–
Amp.
NC
Low-Pass
Filter
Low-Pass
Filter
Aux.
Amp.
Chopper
Input
Switches
Chopper
Output
Switches
Aux.
Amp.
FIGURE 4-2:
First Chopping Clock Phase;
Equivalent Amplifier Diagram.
VIN+
Oscillator
Digital Control
POR
Main
VIN–
FIGURE 4-1:
Amp Functional Diagram.
Simplified Zero-Drift Op
Amp.
NC
4.1.1
BUILDING BLOCKS
Low-Pass
Filter
The Main amplifier is designed for high gain and
bandwidth, with a differential topology. Its main input
pair (+ and - pins at the top left) is used for the higher
frequency portion of the input signal. Its auxiliary input
pair (+ and - pins at the bottom left) is used for the low-
frequency portion of the input signal and corrects the
op amp’s input offset voltage. Both inputs are added
together internally.
Aux.
Amp.
The Auxiliary amplifier, chopper input switches and
chopper output switches provide a high DC gain to the
input signal. DC errors are modulated to higher
frequencies, while white noise is modulated to low
frequencies.
FIGURE 4-3:
Phase; Equivalent Amplifier Diagram.
Second Chopping Clock
2020 Microchip Technology Inc.
DS20006323B-page 17
MCP6V76/6U/7/9
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below VSS. They also
clamp any voltages well above VDD; their breakdown
voltage is high enough to allow normal operation, but
not low enough to protect against slow overvoltage
(beyond VDD) events. Very fast ESD events (that meet
the spec) are limited so that damage does not occur.
4.1.3
INTERMODULATION DISTORTION
(IMD)
These op amps will show intermodulation distortion
(IMD) products when an AC signal is present.
The signal and clock can be decomposed into sine
wave tones (Fourier series components). These tones
interact with the zero-drift circuitry’s nonlinear response
to produce IMD tones at sum and difference frequen-
cies. Each of the square wave clock’s harmonics has a
series of IMD tones centered on it. See Figures 2-36
and 2-37.
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs;
Figure 4-5 shows one approach to protecting these
inputs. D1 and D2 may be small signal silicon diodes,
Schottky diodes for lower clamping voltages or diode-
connected FETs for low leakage.
4.2
Other Functional Blocks
4.2.1
RAIL-TO-RAIL INPUTS
VDD
The input stage of the MCP6V76/6U/7/9 op amps uses
two differential CMOS input stages in parallel. One
U1
operates at low Common Mode Input Voltage (VCM
,
D1
MCP6V7X
which is approximately equal to VIN+ and VIN- in normal
operation) and the other at high VCM. With this
topology, the input operates with VCM up to VDD + 0.3V,
and down to VSS – 0.2V, at +25°C (see Figure 2-16).
The input offset voltage (VOS) is measured at
V1
D2
VOUT
V2
VCM = VSS – 0.2V and VDD + 0.3V to ensure proper
operation.
FIGURE 4-5:
Protecting the Analog Inputs
Against High Voltages.
4.2.1.1
Phase Reversal
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-41 shows an input voltage
exceeding both supplies with no phase inversion.
4.2.1.2
Input Voltage Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1 “Absolute Maximum
Ratings †”). This requirement is independent of the
current limits discussed later.
The ESD protection on the inputs can be depicted as
shown in Figure 4-4. This structure was chosen to
protect the input transistors against many (but not all)
overvoltage conditions and to minimize input bias
current (IB).
Bond
VDD
Pad
Bond
Pad
Bond
Pad
Input
Stage
VIN+
VIN–
Bond
Pad
VSS
FIGURE 4-4:
Simplified Analog Input ESD
Structures.
DS20006323B-page 18
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
4.2.1.3
Input Current Limits
4.3
Application Tips
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see Section 1.1 “Absolute Maxi-
mum Ratings †”). This requirement is independent of
the voltage limits discussed previously.
4.3.1
INPUT OFFSET VOLTAGE OVER
TEMPERATURE
Table 1-1 gives both the linear and quadratic
temperature coefficients (TC1 and TC2) of input offset
voltage. The input offset voltage, at any temperature in
the specified range, can be calculated as follows:
Figure 4-6 shows one approach to protecting these
inputs. The resistors R1 and R2 limit the possible
current in or out of the input pins (and into D1 and D2).
EQUATION 4-1:
The diode currents will dump onto VDD
.
VOSTA = VOS + TC1T + TC2T2
VDD
Where:
∆T
VOS(TA)
VOS
=
=
=
=
=
TA – 25°C
U1
D1
R1
R2
input offset voltage at TA
input offset voltage at +25°C
linear temperature coefficient
quadratic temperature coefficient
MCP6V7X
V1
V2
D2
VOUT
TC1
TC2
4.3.2
OFFSET AT POWER UP
VSS – min(V1, V2)
2 mA
max(V1, V2) – VDD
2 mA
min(R1, R2) >
min(R1, R2) >
When these parts power up, the input offset (VOS) starts
at its uncorrected value. Circuits with high DC gain can
cause the output to reach one of the two rails. In this
case, the time to a valid output is delayed by an output
overdrive time (like tODR) in addition to the start-up time
(like tSTR).
FIGURE 4-6:
Against High Currents.
Protecting the Analog Inputs
It can be simple to avoid this extra start-up time.
Reducing the gain is one method. Adding a capacitor
across the feedback resistor (RF) is another method.
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, the currents through
diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN-) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the Common
Mode Voltage (VCM) is below ground (VSS) (see
Figure 2-15).
4.2.2
The output voltage range of the MCP6V76/6U/7/9 zero-
drift op amps is DD – 5.9 mV (typical) and
RAIL-TO-RAIL OUTPUT
V
VSS + 4.5 mV (typical) when RL = 20 kΩ is connected to
VDD/2 and VDD = 5.5V. Refer to Figures 2-17 and 2-18
for more information.
This op amp is designed to drive light loads; use
another amplifier to buffer the output from heavy loads.
2020 Microchip Technology Inc.
DS20006323B-page 19
MCP6V76/6U/7/9
GN is the circuit’s noise gain. For noninverting gains,
GN and the Signal Gain are equal. For inverting gains,
GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
4.3.3
SOURCE RESISTANCES
The input bias currents have two significant
components: switching glitches that dominate at room
temperature and below and input ESD diode leakage
currents that dominate at +85°C and above.
10000
VDD = 5.5 V
RL = 20 kȍ
Make the resistances seen by the inputs small and
equal. This minimizes the output offset caused by the
input bias currents.
1000
100
The inputs should see a resistance on the order of 10Ω
to 1 kΩ at high frequencies (i.e., above 1 MHz). This
helps minimize the impact of switching glitches, which
are very fast, on overall performance. In some cases, it
may be necessary to add resistors in series with the
inputs to achieve this improvement in performance.
GN:
1 V/V
10 V/V
10
100 V/V
1
100p
1n
10n
100n
1µ
Normalized Load Capacitance; CL/¥GN (F)
Small input resistances may be needed for high gains.
Without them, parasitic capacitances might cause
positive feedback and instability.
FIGURE 4-8:
Recommended RISO Values
for Capacitive Loads.
4.3.4
SOURCE CAPACITANCE
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO's value until the
response is reasonable. Bench evaluation is helpful.
The capacitances seen by the two inputs should be
small. Large input capacitances and source resis-
tances, together with high gain, can lead to positive
feedback and instability.
4.3.6
STABILIZING OUTPUT LOADS
4.3.5
CAPACITIVE LOADS
This family of zero-drift op amps has an output
impedance (Figures 2-28 and 2-29) that has a double
zero when the gain is low. This can cause a large phase
shift in feedback networks that have low-impedance
near the part’s bandwidth. This large phase shift can
cause stability problems.
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. These zero-drift op amps have a different
output impedance than most op amps, due to their
unique topology.
Figure 4-9 shows that the load on the output is
(RL + RISO)||(RF + RG), where RISO is before the load
(like Figure 4-7). This load needs to be large enough to
maintain stability; it should be at least 10 kΩ.
When driving a capacitive load with these op amps, a
series resistor at the output (RISO in Figure 4-7)
improves the feedback loop’s phase margin (stability)
by making the output load resistive at higher
frequencies. The bandwidth will be generally lower
than the bandwidth with no capacitive load.
RG
RF
RISO
VOUT
RL
CL
U1
MCP6V7X
Output Load.
RISO
VOUT
FIGURE 4-9:
CL
U1
MCP6V7X
FIGURE 4-7:
Output Resistor, RISO,
Stabilizes Capacitive Loads.
Figure 4-8 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/√GN). The y-axis is
the resistance (RISO).
DS20006323B-page 20
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
4.3.7
GAIN PEAKING
4.3.8
REDUCING UNDESIRED NOISE
AND SIGNALS
Figure 4-10 shows an op amp circuit that represents
noninverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage
and VM is the input). The capacitances CN and CG
represent the total capacitance at the input pins; they
include the op amp’s Common Mode Input
Capacitance (CCM), board parasitic capacitance and
any capacitor placed in parallel. The capacitance CFP
represents the parasitic capacitance coupling the
output and noninverting input pins.
Reduce undesired noise and signals with:
• Low bandwidth signal filters:
- Minimize random analog noise
- Reduce interfering signals
• Good PCB layout techniques:
- Minimize crosstalk
- Minimize parasitic capacitances and
inductances that interact with fast switching
edges
• Good power supply design:
- Isolation from other parts
CN
CFP
RN
- Filtering of interference on supply line(s)
VP
4.3.9
SUPPLY BYPASSING AND
FILTERING
U1
MCP6V7X
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
of the pin for good high-frequency performance.
VM
VOUT
RG
RF
CG
These parts also need a bulk capacitor (i.e., 1 µF or
larger) within 100 mm to provide large, slow currents.
This bulk capacitor can be shared with other low-noise
analog parts.
FIGURE 4-10:
Capacitance.
Amplifier with Parasitic
CG acts in parallel with RG (except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
CG also reduces the phase margin of the feedback
loop, which becomes less stable. This effect can be
reduced by either reducing CG or RF||RG.
In some cases, high-frequency power supply noise
(e.g., switched mode power supplies) may cause
undue intermodulation distortion with a DC offset shift;
this noise needs to be filtered. Adding a resistor into the
supply connection can be helpful.
CN and RN form a low-pass filter that affects the signal
4.3.10
PCB DESIGN FOR DC PRECISION
at VP. This filter has a single real pole at 1/(2πRNCN).
The largest value of RF that should be used depends
on noise gain (see GN in Section 4.3.5 “Capacitive
Loads”), CG and the open-loop gain’s phase shift. An
approximate limit for RF is:
In order to achieve DC precision on the order of ±1 µV,
many physical errors need to be minimized. The design
of the Printed Circuit Board (PCB), the wiring and the
thermal environment have a strong impact on the
precision achieved. A poor PCB design can easily be
more than 100 times worse than the MCP6V76/6U/7/9
op amps’ minimum and maximum specifications.
EQUATION 4-2:
RF 10 k ------------- G2N
12 pF
CG
4.3.10.1
PCB Layout
Any time two dissimilar metals are joined together, a
temperature dependent voltage appears across the
junction (the Seebeck or thermojunction effect). This
effect is used in thermocouples to measure
temperature. The following are examples of
thermojunctions on a PCB:
Some applications may modify these values to reduce
either output loading or gain peaking (step response
overshoot).
At high gains, RN needs to be small in order to prevent
positive feedback and oscillations. Large CN values
can also help.
• Components (resistors, op amps, …) soldered to
a copper pad
• Wires mechanically attached to the PCB
• Jumpers
• Solder joints
• PCB vias
2020 Microchip Technology Inc.
DS20006323B-page 21
MCP6V76/6U/7/9
Typical thermojunctions have temperature to voltage
conversion coefficients of 1 to 100 µV/°C (sometimes
higher).
4.4
Typical Applications
4.4.1
WHEATSTONE BRIDGE
Microchip’s AN1258 (“Op Amp Precision Design: PCB
Layout Techniques”) contains in-depth information on
PCB layout techniques that minimize thermojunction
effects. It also discusses other effects, such as
crosstalk, impedances, mechanical stresses and
humidity.
Many sensors are configured as Wheatstone bridges.
Strain gauges and pressure sensors are two common
examples. These signals can be small and the
Common mode noise large. Amplifier designs with high
differential gain are desirable.
Figure 4-11 shows how to interface to a Wheatstone
bridge with a minimum of components. Because the
circuit is not symmetric, the ADC input is single-ended
and there is a minimum of filtering; the CMRR is good
enough for moderate Common mode noise.
4.3.10.2
Crosstalk
DC crosstalk causes offsets that appear as a larger
input offset voltage. Common causes include:
• Common mode noise (remote sensors)
• Ground loops (current return paths)
• Power supply coupling
0.01C
100R
VDD
1 kΩ
VDD
R
R
ADC
Interference from the mains (usually 50 Hz or 60 Hz)
and other AC sources can also affect the DC
performance. Nonlinear distortion can convert these
signals to multiple tones, including a DC shift in voltage.
When the signal is sampled by an ADC, these AC
signals can also be aliased to DC, causing an apparent
shift in offset.
0.2R
0.2R
U1
MCP6V76
R
R
FIGURE 4-11:
Simple Design.
To reduce interference:
4.4.2 RTD SENSOR
- Keep traces and wires as short as possible
- Use shielding
The ratiometric circuit in Figure 4-12 conditions a two-
wire RTD for applications with a limited temperature
range. U1 acts as a difference amplifier with a low-
frequency pole. The sensor’s wiring resistance (RW) is
corrected in firmware. Failure (open) of the RTD is
detected by an out-of-range voltage.
- Use ground plane (at least a star ground)
- Place the input signal source near to the DUT
- Use good PCB layout techniques
- Use a separate power supply filter (bypass
capacitors) for these zero-drift op amps
VDD
4.3.10.3
Miscellaneous Effects
RT
34.8 kΩ
RN
10.0 kΩ
Keep the resistances seen by the input pins as small
and as near to equal as possible to minimize bias-
current-related offsets.
10 nF
RF
2.00 MΩ
RW
Make the (trace) capacitances seen by the input pins
small and equal. This is helpful in minimizing switching
glitch-induced offset voltages.
U1
RRTD
100Ω
MCP6V76
Bending a coax cable with a radius that is too small
causes a small voltage drop to appear on the center
conductor (the triboelectric effect). Make sure the
bending radius is large enough to keep the conductors
and insulation in full contact.
1.00 kΩ
RG
RF
RW
10.0 kΩ 2.00 MΩ
100 nF
VDD
RB
4.99 kΩ
10 nF
1.0 µF
Mechanical stresses can make some capacitor types
(such as some ceramics) output small voltages. Use
more appropriate capacitor types in the signal path and
minimize mechanical stresses and vibration.
ADC
FIGURE 4-12:
RTD Sensor.
Humidity can cause electrochemical potential voltages
to appear in a circuit. Proper PCB cleaning helps, as
does the use of encapsulants.
DS20006323B-page 22
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
4.4.3
OFFSET VOLTAGE CORRECTION
Figure 4-13 shows MCP6V76 (U2) correcting the input
offset voltage of another op amp (U1). R2 and C2
integrate the offset error seen at U1’s input; the
integration needs to be slow enough to be stable (with
the feedback provided by R1 and R3). R4 and R5
attenuate the integrator’s output; this shifts the
integrator pole down in frequency.
R1
R2
R3
VIN
VOUT
R4
R5
C2
U1
MCP6XXX
VDD/2
R2
VDD/2
U2
MCP6V76
FIGURE 4-13:
Offset Correction.
4.4.4 PRECISION COMPARATOR
Use high gain before a comparator to improve the
latter’s performance. Do not use MCP6V76/6U/7/9 as
a comparator by itself; the VOS correction circuitry does
not operate properly without a feedback loop.
U1
VIN
MCP6V76
R1
R2
R3
R4
R5
VOUT
VDD/2
U2
MCP6541
FIGURE 4-14:
Precision Comparator.
2020 Microchip Technology Inc.
DS20006323B-page 23
MCP6V76/6U/7/9
5.3
Application Notes
5.0
DESIGN AIDS
The following Microchip Application Notes are
available on the Microchip web site at www.microchip.
com/appnotes and are recommended as supplemental
reference resources.
Microchip provides the basic design aids needed for
the MCP6V76/6U/7/9 family of op amps.
5.1
Microchip Advanced Part Selector
(MAPS)
ADN003: “Select the Right Operational Amplifier for
your Filtering Circuits”, DS21821
MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design require-
ment. Available at no cost from the Microchip web site
at www.microchip.com/maps, MAPS is an overall
selection tool for Microchip’s product portfolio that
includes Analog, Memory, MCUs and DSCs. Using this
tool, a customer can define a filter to sort features for a
parametric search of devices and export side-by-side
technical comparison reports. Helpful links are also
provided for data sheets, purchase and sampling of
Microchip parts.
AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
AN723: “Operational Amplifier AC Specifications and
Applications”, DS00723
AN884: “Driving Capacitive Loads With Op Amps”,
DS00884
AN990: “Analog Sensor Conditioning Circuits – An
Overview”, DS00990
AN1177: “Op Amp Precision Design: DC Errors”,
DS01177
5.2
Analog Demonstration and
Evaluation Boards
AN1228: “Op Amp Precision Design: Random Noise”,
DS01228
AN1258: “Op Amp Precision Design: PCB Layout
Techniques”, DS01258
Microchip offers
a
broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help customers achieve faster time to
market. For a complete listing of these boards and their
corresponding user’s guides and technical information,
These Application Notes and others are listed in the
design guide:
“Signal Chain Design Guide”, DS21825
visit
the
Microchip
web
site
at
www.microchip.com/analog tools.
Some boards that are especially useful are:
• MCP6V01 Thermocouple Auto-Zeroed Reference
Design (P/N MCP6V01RD-TCPL)
• MCP6XXX Amplifier Evaluation Board 2 (P/N
DS51668)
• MCP6XXX Amplifier Evaluation Board 3 (P/N
DS51673)
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board
(P/N SOIC8EV)
• 14-Pin SOIC/TSSOP/DIP Evaluation Board (P/N
SOIC14EV)
DS20006323B-page 24
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
5-Lead SC70 (MCP6V76U)
Example:
FV56
Device
MCP6V76UT-E/LTY
Code
FVNN
5-Lead SOT-23 (MCP6V76, MCP6V76U)
Example:
Device
Code
REBH0
03256
XXXXY
WWNNN
MCP6V76T-E/OT
MCP6V76UT-E/OT
REBHY
REBJY
8-Lead MSOP (3x3 mm) (MCP6V77)
Example
6V77
003256
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2020 Microchip Technology Inc.
DS20006323B-page 25
MCP6V76/6U/7/9
8-Lead TDFN (2x3x0.8 mm) (MCP6V77)
Example
Device
MCP6V77T-E/MNY
Code
DM8
DM8
003
25
Note:
Applies to 8-Lead 2x3 TDFN.
14-Lead TSSOP (4.4 mm) (MCP6V79)
Example
XXXXXXXX
YYWW
6V79E/ST
2003
256
NNN
DS20006323B-page 26
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
5-Lead Plastic Small Outline Transistor (LTY) [SC70]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
e
e
B
E
3
1
E1
2X
0.15 C
4
N
5X TIPS
0.30 C
NOTE 1
2X
0.15 C
5X b
0.10
C A B
TOP VIEW
c
A2
A
C
SEATING
PLANE
A1
L
SIDE VIEW
END VIEW
Microchip Technology Drawing C04-061-LTY Rev E Sheet 1 of 2
2020 Microchip Technology Inc.
DS20006323B-page 27
MCP6V76/6U/7/9
5-Lead Plastic Small Outline Transistor (LTY) [SC70]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
5
0.65 BSC
Overall Height
Standoff
Molded Package Thickness
Overall Length
A
A1
A2
D
E
0.80
0.00
0.80
-
-
-
1.10
0.10
1.00
2.00 BSC
2.10 BSC
Overall Width
Molded Package Width
Terminal Width
Terminal Length
E1
b
L
c
1.25 BSC
0.15
0.10
0.08
-
0.20
-
0.40
0.46
0.26
Lead Thickness
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-061-LTY Rev E Sheet 2 of 2
DS20006323B-page 28
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
5-Lead Plastic Small Outline Transistor (LTY) [SC70]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
Gx
SILK SCREEN
3
4
2
1
5
C
G
Y
X
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
0.65 BSC
2.20
MAX
Contact Pitch
E
C
Contact Pad Spacing
Contact Pad Width
Contact Pad Length
Distance Between Pads
Distance Between Pads
X
Y
G
Gx
0.45
0.95
1.25
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2061-LTY Rev E
2020 Microchip Technology Inc.
DS20006323B-page 29
MCP6V76/6U/7/9
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.20 C 2X
D
e1
A
D
N
E/2
E1/2
E1
E
(DATUM D)
(DATUM A-B)
0.15 C D
2X
NOTE 1
1
2
e
B
NX b
0.20
C A-B D
TOP VIEW
A
A2
A1
A
0.20 C
SEATING PLANE
A
SEE SHEET 2
C
SIDE VIEW
Microchip Technology Drawing C04-091-OT Rev F Sheet 1 of 2
DS20006323B-page 30
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
c
T
L
L1
VIEW A-A
SHEET 1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
5
0.95 BSC
Outside lead pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
e1
A
A2
A1
E
E1
D
L
1.90 BSC
0.90
0.89
-
-
-
-
1.45
1.30
0.15
2.80 BSC
1.60 BSC
2.90 BSC
0.30
-
0.60
Footprint
Foot Angle
Lead Thickness
Lead Width
L1
0.60 REF
I
0°
0.08
0.20
-
-
-
10°
0.26
0.51
c
b
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-091-OT Rev F Sheet 2 of 2
2020 Microchip Technology Inc.
DS20006323B-page 31
MCP6V76/6U/7/9
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X
SILK SCREEN
5
Y
Z
C
G
1
2
E
GX
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
0.95 BSC
2.80
MAX
Contact Pitch
E
C
Contact Pad Spacing
Contact Pad Width (X5)
Contact Pad Length (X5)
Distance Between Pads
Distance Between Pads
Overall Width
X
Y
G
GX
Z
0.60
1.10
1.70
0.35
3.90
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091-OT Rev F
DS20006323B-page 32
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2020 Microchip Technology Inc.
DS20006323B-page 33
MCP6V76/6U/7/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20006323B-page 34
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2020 Microchip Technology Inc.
DS20006323B-page 35
MCP6V76/6U/7/9
8-Lead Plastic Dual Flat, No Lead Package (MNY) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
E
N
(DATUM A)
(DATUM B)
NOTE 1
2X
0.15 C
2X
1
2
0.15 C
TOP VIEW
0.10 C
(A3)
C
A
SEATING
PLANE
8X
A1
L
0.08 C
C A B
SIDE VIEW
0.10
D2
1
2
0.10
C A B
NOTE 1
E2
K
N
8X b
0.10
0.05
C A B
C
e
BOTTOM VIEW
Microchip Technology Drawing No. C04-129-MNY Rev E Sheet 1 of 2
DS20006323B-page 36
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
8-Lead Plastic Dual Flat, No Lead Package (MNY) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Pins
Pitch
Overall Height
Standoff
Contact Thickness
Overall Length
Overall Width
Exposed Pad Length
Exposed Pad Width
Contact Width
Contact Length
N
8
e
0.50 BSC
0.75
A
A1
A3
D
0.70
0.00
0.80
0.05
0.02
0.20 REF
2.00 BSC
3.00 BSC
1.40
E
D2
E2
b
L
K
1.35
1.25
0.20
0.25
0.20
1.45
1.35
0.30
0.45
-
1.30
0.25
0.30
-
Contact-to-Exposed Pad
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04-129-MNY Rev E Sheet 2 of 2
2020 Microchip Technology Inc.
DS20006323B-page 37
MCP6V76/6U/7/9
8-Lead Plastic Dual Flat, No Lead Package (MNY) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X2
EV
8
ØV
C
Y2
EV
Y1
1
2
SILK SCREEN
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
MILLIMETERS
NOM
0.50 BSC
MIN
MAX
Contact Pitch
Optional Center Pad Width
Optional Center Pad Length
Contact Pad Spacing
X2
Y2
C
1.60
1.50
2.90
Contact Pad Width (X8)
Contact Pad Length (X8)
Thermal Via Diameter
Thermal Via Pitch
X1
Y1
V
0.25
0.85
0.30
1.00
EV
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing No. C04-129-MNY Rev. B
DS20006323B-page 38
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
E
N
E
2
E1
2
E1
2X 7 TIPS
0.20 C B A
1
2
e
TOP VIEW
A
A
C
A2
A
SEATING
PLANE
A1
14X
14X b
0.10 C
0.10
C B A
SIDE VIEW
SEE DETAIL B
VIEW A–A
Microchip Technology Drawing C04-087 Rev D Sheet 1 of 2
2020 Microchip Technology Inc.
DS20006323B-page 39
MCP6V76/6U/7/9
14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
(ș2)
R1
H
R2
c
L
ș1
(L1)
(ș3)
DETAIL B
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Terminals
Pitch
N
e
14
0.65 BSC
Overall Height
Standoff
Molded Package Thickness
Overall Length
Overall Width
A
A1
A2
D
–
–
–
1.00
5.00
1.20
0.15
1.05
5.10
0.05
0.80
4.90
E
6.40 BSC
Molded Package Width
Terminal Width
Terminal Thickness
Terminal Length
Footprint
Lead Bend Radius
Lead Bend Radius
Foot Angle
E1
b
4.30
0.19
0.09
0.45
4.40
–
–
0.60
4.50
0.30
0.20
0.75
c
L
L1
R1
R2
ș1
ș2
ș3
1.00 REF
0.09
0.09
0°
–
–
–
–
–
–
–
8°
–
Mold Draft Angle
Mold Draft Angle
12° REF
12° REF
–
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-087 Rev D Sheet 2 of 2
DS20006323B-page 40
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
G
SILK SCREEN
C
Y
X
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Contact Pitch
Contact Pad Spacing
Contact Pad Width (Xnn)
E
C
X
0.65 BSC
5.90
0.45
1.45
Contact Pad Length (Xnn)
Y
Contact Pad to Contact Pad (Xnn)
G
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2087 Rev D
2020 Microchip Technology Inc.
DS20006323B-page 41
MCP6V76/6U/7/9
NOTES:
DS20006323B-page 42
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
APPENDIX A: REVISION HISTORY
Revision B (April 2020)
• Updated Section 6.1 “Package Marking
Information” for 5-Lead SOT-23.
Revision A (March 2020)
• Original release of this document.
2020 Microchip Technology Inc.
DS20006323B-page 43
MCP6V76/6U/7/9
NOTES:
DS20006323B-page 44
2020 Microchip Technology Inc.
MCP6V76/6U/7/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
(1)
[X]
Examples:
PART NO.
–X
/XX
a)
MCP6V76T-E/OT: Tape and Reel,
Device Tape and Reel
Temperature
Range
Package
Extended temperature,
5LD SOT-23 package
a)
b)
MCP6V76UT-E/LTY: Tape and Reel,
Device:
MCP6V76T: Single Op Amp (Tape and Reel)
(SOT-23 only)
MCP6V76UT: Single Op Amp (Tape and Reel)
(SC-70, SOT-23)
Extended temperature,
5LD SC70 package
MCP6V76UT-E/OT: Tape and Reel,
Extended temperature,
5LD SOT-23 package
MCP6V77:
Dual Op Amp (MSOP, 2x3 TDFN)
MCP6V77T: Dual Op Amp (Tape and Reel) (MSOP,
2x3 TDFN)
a)
b)
MCP6V77-E/MS:
Extended temperature,
8LD MSOP package
MCP6V79:
Quad Op Amp (TSSOP)
MCP6V79T: Quad Op Amp (Tape and Reel) (TSSOP)
MCP6V77T-E/MS: Tape and Reel,
Extended temperature,
8LD MSOP package
MCP6V77T-E/MNY: Tape and Reel,
Temperature Range:
Package:
E
= -40°C to +125°C (Extended)
c)
Extended temperature,
8LD 2x3 TDFN package
LTY*
OT
=
Plastic Small Outline Transistor, 5-lead SC70
= Plastic Small Outline Transistor, 5-lead SOT-23
a)
b)
MCP6V79-E/ST:
Extended temperature,
14LD TSSOP package
MNY* = Plastic Dual Flat, No-Lead - 2×3×0.8 mm Body,
8-lead
MS
ST
= Plastic Micro Small Outline, 8-lead
= Plastic Thin Shrink Small Outline - 4.4 mm Body,
14-lead
MCP6V79T-E/ST: Tape and Reel,
Extended temperature,
14LD TSSOP package
*Y
=
Nickel palladium gold manufacturing designator.
Only available on the SC70 and TDFN packages.
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
2020 Microchip Technology Inc.
DS20006323B-page 45
MCP6V76/6U/7/9
NOTES:
DS20006323B-page 46
2020 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2020, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-5930-9
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2020 Microchip Technology Inc.
DS20006323B-page 47
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Australia - Sydney
Tel: 61-2-9868-6733
India - Bangalore
Tel: 91-80-3090-4444
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Beijing
Tel: 86-10-8569-7000
India - New Delhi
Tel: 91-11-4160-8631
Denmark - Copenhagen
Tel: 45-4485-5910
Fax: 45-4485-2829
China - Chengdu
Tel: 86-28-8665-5511
India - Pune
Tel: 91-20-4121-0141
Finland - Espoo
Tel: 358-9-4520-820
China - Chongqing
Tel: 86-23-8980-9588
Japan - Osaka
Tel: 81-6-6152-7160
Web Address:
www.microchip.com
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
China - Dongguan
Tel: 86-769-8702-9880
Japan - Tokyo
Tel: 81-3-6880- 3770
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Guangzhou
Tel: 86-20-8755-8029
Korea - Daegu
Tel: 82-53-744-4301
Germany - Garching
Tel: 49-8931-9700
China - Hangzhou
Tel: 86-571-8792-8115
Korea - Seoul
Tel: 82-2-554-7200
Germany - Haan
Tel: 49-2129-3766400
Austin, TX
Tel: 512-257-3370
China - Hong Kong SAR
Tel: 852-2943-5100
Malaysia - Kuala Lumpur
Tel: 60-3-7651-7906
Germany - Heilbronn
Tel: 49-7131-72400
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
China - Nanjing
Tel: 86-25-8473-2460
Malaysia - Penang
Tel: 60-4-227-8870
Germany - Karlsruhe
Tel: 49-721-625370
China - Qingdao
Philippines - Manila
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Tel: 86-532-8502-7355
Tel: 63-2-634-9065
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
China - Shanghai
Tel: 86-21-3326-8000
Singapore
Tel: 65-6334-8870
Germany - Rosenheim
Tel: 49-8031-354-560
China - Shenyang
Tel: 86-24-2334-2829
Taiwan - Hsin Chu
Tel: 886-3-577-8366
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Israel - Ra’anana
Tel: 972-9-744-7705
China - Shenzhen
Tel: 86-755-8864-2200
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
China - Suzhou
Tel: 86-186-6233-1526
Taiwan - Taipei
Tel: 886-2-2508-8600
Detroit
Novi, MI
Tel: 248-848-4000
China - Wuhan
Tel: 86-27-5980-5300
Thailand - Bangkok
Tel: 66-2-694-1351
Italy - Padova
Tel: 39-049-7625286
Houston, TX
Tel: 281-894-5983
China - Xian
Tel: 86-29-8833-7252
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
China - Xiamen
Tel: 86-592-2388138
Norway - Trondheim
Tel: 47-7288-4388
China - Zhuhai
Tel: 86-756-3210040
Poland - Warsaw
Tel: 48-22-3325737
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Raleigh, NC
Tel: 919-844-7510
Sweden - Gothenberg
Tel: 46-31-704-60-40
New York, NY
Tel: 631-435-6000
Sweden - Stockholm
Tel: 46-8-5090-4654
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS20006323B-page 48
2020 Microchip Technology Inc.
02/28/20
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