MIC33M656-SAYMP-TR [MICROCHIP]
Switching Regulator;
| 型号： | MIC33M656-SAYMP-TR |
| 厂家： | 
MICROCHIP |
| 描述： | Switching Regulator 开关 输出元件 |
| 文件： | 总46页 (文件大小：792K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MIC33M656
6A, Power Module Buck Converter
with HyperLight Load® and I2C Interface
The I2C interface allows programming the output
Features
voltage, between 0.6V and 1.28V with 5 mV resolution,
or between 0.6V and 3.84V with 10 mV and 20 mV
resolution. Three different default voltage options
(0.6V, 0.9V and 1.0V) are provided so that the applica-
tion can be started with a safe voltage level and then
moved to high-performance modes under I2C control.
• Input Voltage Range: 2.4V to 5.5V
• 6A Output Current
• Multiple Faults Indication through I2C
• I2C Programmable:
- Output voltage: 0.6V-1.28V, 5 mV resolution;
0.6V-3.84V, 10/20 mV resolution
An open-drain Power Good output facilitates output
voltage monitoring and sequencing. If set in shutdown
(EN = GND), the MIC33M656 typically draws 1.5 µA,
while the output is discharged through a 10pull-down
(if the output discharge feature is enabled).
- Slew rate: 0.2 ms/V-3.2 ms/V
- On time (switching frequency)
- High-side current limit: 3.5A-10A
- Enable delay: 0.2 ms-3 ms
The MIC33M656 pinout is compatible with the
MIC33M650, so that applications can be easily
converted.
- Output discharge when disabled (EN = GND)
• High Efficiency (up to 95%)
• Ultra-Fast Transient Response
The 2.4V to 5.5V input voltage range, low shutdown and
quiescent currents make the MIC33M656 ideal for
single-cell Li-ion battery-powered applications. The 100%
duty cycle capability provides low dropout operation,
extending operating range in portable systems.
• ±1.5% Output Voltage Accuracy Over
Line/Load/Temperature Range
• Safe Start-up with Pre-Biased Output
• Typical 1.5 µA Shutdown Supply Current
• Low Dropout (100% Duty Cycle) Operation
• I2C Speed, Up to 3.4 MHz
The MIC33M656 is available in a thermally efficient,
53-Lead, 6 mm x 10 mm x 3 mm B1QFN package, with
an operating junction temperature range from -40°C to
+125°C.
• Latch-Off Thermal Shutdown Protection
• Latch-Off Current Limit Protection
• Meets CISPR32 Class B Emissions
• Power Good (PG) Open-Drain Output
• Package: 53-Lead, 6 mm x 10 mm B1QFN
Applications
• Solid-State Drives (SSD)
• FPGAs, DSP and Low-Voltage ASIC Power
General Description
The Microchip MIC33M656 is an I2C programmable,
high-efficiency, low-voltage input, 6A current, synchro-
nous step-down regulator power module with
integrated inductor. The Constant-On-Time (COT) con-
trol architecture with HyperLight Load® mode provides
very high efficiency at light loads, while still having
ultra-fast transient response.
FIGURE 1:
CISPR32, Class B (VIN = 5V, VOUT = 1V,
OUT = 6A).
Radiated Emissions,
I
2019 Microchip Technology Inc.
DS20006256A-page 1
MIC33M656
Package Types
MIC33M656
53-Pin B1QFN*
6 mm x 10 mm
AUX_A
GND
47
48
49
50
51
52
27
26
25
24
23
22
21
20
OUT
OUT
OUT
EP_OUT
SDA
EN
PG
P
P
GND
GND
EP_P
GND
V
OUT
GND
A
SW
SW
SW
EP_SW
AUX_PV
IN
53
EP_PGND
*
Includes Exposed Thermal Pads (EP); see Table 3-1.
Typical Application
MIC33M656
SVIN
SW
OUT
VOUT
1.0V/6A
VIN
PVIN
2.4V to 5.5V
10 μF
Opt.
47 μF
47 μF
AUX_PVIN
PGND
EN
EN
VIN
VIN
2.4 kΩ
VIN
2.4 kΩ
AUX_AGND
AGND
100k
VOUT
PG
SDA
SCL
SDA
SCL
Power Good
Ordering Information
Default Status at Power-up
Output Voltage
Range/Step
High-Side
CurrentLimit
(typical)
Output
Pull-Down When
Disabled
Part Number
Output
TON[1:0]
(ns)
Soft Start
Speed
Overtemp
Latch-Off
Voltage
MIC33M656-HAYMP 1.0V
10A
10A
10A
[
[
[
10] – 130 ns 800 µs/V Latch-Off after
Yes
Yes
Yes
0.600V-1.280V/5 mV
0.600V-1.280V/5 mV
4 OT Cycles
MIC33M656-FAYMP
0.9V
10] – 130 ns 800 µs/V Latch-Off after
4 OT Cycles
MIC33M656-SAYMP 1.0 V
10] – 130 ns 800 µs/V Latch-Off after
0.600V-1.280V/10 mV
1.280V-3.840V/20 mV
4 OT Cycles
DS20006256A-page 2
2019 Microchip Technology Inc.
MIC33M656
Functional Block Diagram
SVIN
1 μF
10Ω
AUX_PVIN
10 μF
TON
ADJUST
PVIN
VIN
2.4V to 5.5V
MINIMUM
TOFF
2 x 0.1 μF
10 μF
UVLO
HSD
2.225V/2.072V
SW
EN
Control
Logic
OT
L1
0.47 μH
V
/6A
OUT
ꢀ165°C/ꢀ143°C
2 x 0.1 μF
PD
ZC
2x
47 μF
PVIN
LSD
RIPPLE
INJECTION
PGND
COMP
EA
SDA
SCL
I2C
CONTROL
AND
8-Bit
DAC
PD
REGISTERS
VIN
100k
AGND
VREF -9%
PG
PG
DELAY
2019 Microchip Technology Inc.
DS20006256A-page 3
MIC33M656
NOTES:
DS20006256A-page 4
2019 Microchip Technology Inc.
MIC33M656
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
SVIN, PVIN to AGND...................................................................................................................................... -0.3V to +6V
VSW to AGND ................................................................................................................................................ -0.3V to +6V
VEN to AGND................................................................................................................................................ -0.3V to PVIN
VPG to AGND................................................................................................................................................ -0.3V to PVIN
VSDA, VSCLto AGND .................................................................................................................................... -0.3V to PVIN
PVIN to SVIN.............................................................................................................................................. -0.3V to +0.3V
AGND to PGND ........................................................................................................................................... -0.3V to +0.3V
Junction Temperature .......................................................................................................................................... +150°C
Storage Temperature (TS)...................................................................................................................... -65°C to +150°C
Lead Temperature (soldering, 10s)...................................................................................................................... +260°C
ESD Rating (Note 1)
HBM................................................................................................................................................................. 2000V
CDM................................................................................................................................................................. 1500V
†
Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note 1: Devices are ESD-sensitive. Handling precautions recommended. Human body model, 1.5 k in series with
100 pF.
(1)
Operating Ratings
Supply Voltage (PVIN).................................................................................................................................. 2.4V to 5.5V
Enable Voltage (VEN) ...................................................................................................................................... 0V to PVIN
Power Good (PG) Pull-up Voltage (VPU_PG)................................................................................................... 0V to 5.5V
AUX_PVIN to PVIN .....................................................................................................................0V (shorted in operation)
AUX_AGND to AGND ...................................................................................................................0V (shorted in operation)
Maximum Output Current............................................................................................................................................. 6A
Junction Temperature (TJ) ..................................................................................................................... -40°C to +125°C
Note 1: The device is not ensured to function outside the operating range.
2019 Microchip Technology Inc.
DS20006256A-page 5
MIC33M656
(1,2)
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, PVIN = 5V; VOUT = 1.0V; COUT = 2 x 47 µF; TA = +25°C.
Boldface values indicate -40°C TJ +125°C.
Parameter
VIN Supply
Symbol
Min.
Typ.
Max.
Units
Conditions
Input Range
PVIN
2.4
—
5.5
V
V
Undervoltage Lockout
Threshold
UVLO
2.15
2.225
2.35
SVIN rising
SVIN falling
Undervoltage Lockout
Hysteresis
UVLO_H
—
153
—
V
Operating Supply Current
Shutdown Current
IIN0
—
—
60
100
µA
µA
VFB = 1.2V, non-switching
ISHDN
1.5
10
VEN = 0V, PVIN = SVIN = 5.5V,
VSW = VSDA= VSCL = 0V,
-40°C TJ +105°C
20
µA
VEN = 0V, PVIN = SVIN = 5.5V,
VSW = VSDA= VSCL = 0V,
-40°C TJ +125°C
Output Voltage
Output Accuracy
VOUT_ACC
VOUT_STEP
VOUT_STEP
-1.5
—
5
1.5
%
VOUT from 0.6V to 1.28V (includes
line and load regulation)
Output Voltage Step
(options HAYMP, FAYMP)
—
—
mV
mV
VOUT from 0.6V to 1.28V
Output Voltage Step
(option SAYMP)
—
—
—
10
20
—
—
—
VOUT from 0.6V to 1.28V
VOUT from 1.28V to 3.84V
Line Regulation
0.06
%
%
VOUT = 1.0V, VIN = 2.5 to 5.5V,
IOUT = 300 mA
Load Regulation
—
0.2
—
VOUT = 1.0V, IOUT = 0A to 6A
Enable Control
EN Logic Level High
EN Logic Level Low
EN Low Input Current
EN High Input Current
Enable Delay (Two Bits)
Enable Lockout Delay
VEN_H
VEN_L
IEN_L
1.2
—
—
—
—
—
—
V
V
VEN Rising, regulator enabled
VEN falling, regulator shutdown
VEN = 0V
0.4
500
500
0.01
0.01
nA
nA
IEN_H
VEN = 5.5V
0.15
0.85
1.70
2.55
0.25
0.4
1.20
2.35
3.5
ms
ms
ms
ms
EN_DELAY[1:0] = 00, default
EN_DELAY[1:0] = 01
EN_DELAY[1:0] = 10
EN_DELAY[1:0] = 11
1
2
3
Note 1: Specification for packaged product only.
2: Characterized in open loop.
DS20006256A-page 6
2019 Microchip Technology Inc.
MIC33M656
(1,2)
ELECTRICAL CHARACTERISTICS
(CONTINUED)
Electrical Specifications: Unless otherwise specified, PVIN = 5V; VOUT = 1.0V; COUT = 2 x 47 µF; TA = +25°C.
Boldface values indicate -40°C TJ +125°C.
Parameter
Internal DAC Slew Rate (Four Bits)
Slew Rate Time (time to 1V) TRISE
Symbol
Min.
Typ.
Max.
Units
Conditions
100
250
200
400
300
550
µs/V SLEW_RATE[3:0] = 0000
µs/V SLEW_RATE[3:0] = 0001
µs/V SLEW_RATE[3:0] = 0010
µs/V SLEW_RATE[3:0] = 0011, default
µs/V SLEW_RATE[3:0] = 0100
µs/V SLEW_RATE[3:0] = 0101
µs/V SLEW_RATE[3:0] = 0110
µs/V SLEW_RATE[3:0] = 0111
µs/V SLEW_RATE[3:0] = 1000
µs/V SLEW_RATE[3:0] = 1001
µs/V SLEW_RATE[3:0] = 1010
µs/V SLEW_RATE[3:0] = 1011
µs/V SLEW_RATE[3:0] = 1100
µs/V SLEW_RATE[3:0] = 1101
µs/V SLEW_RATE[3:0] = 1110
µs/V SLEW_RATE[3:0] = 1111
400
600
800
600
800
1000
1250
1450
1700
1900
2150
2350
2600
2800
3020
3250
3480
3710
750
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
3000
3200
950
1100
1300
1450
1650
1800
2000
2180
2350
2520
2690
TON Control/Switching Frequency (Two Bits)
Switching On Time
TON
—
—
—
—
—
260
180
130
105
1.6
—
—
—
—
—
ns
VOUT = 1V, TON[1:0] = 00
VOUT = 1V, TON[1:0] = 01
VOUT = 1V, TON[1:0] = 10
VOUT = 1V, TON[1:0] = 11
Switching Frequency
Maximum Duty Cycle
FREQ
MHz VOUT = 1V, TON[1:0] = 10,
IOUT = 3A
—
2.2
—
—
MHz VOUT = 3.3V, TON[1:0] = 10,
IOUT = 3A
DCMAX
—
100
%
Note 1: Specification for packaged product only.
2: Characterized in open loop.
2019 Microchip Technology Inc.
DS20006256A-page 7
MIC33M656
(1,2)
ELECTRICAL CHARACTERISTICS
(CONTINUED)
Electrical Specifications: Unless otherwise specified, PVIN = 5V; VOUT = 1.0V; COUT = 2 x 47 µF; TA = +25°C.
Boldface values indicate -40°C TJ +125°C.
Parameter
Symbol
Min.
Typ.
Max.
Units
Conditions
Short-Circuit Protection
High-Side MOSFET Forward
Current Limit
ILIM_HS
2.1
4.0
6.4
8.0
—
3.5
5.0
8.5
10.0
3.0
4.2
6.8
8.0
-3
4.9
6.5
10.6
12.0
—
A
ILIM[1:0] = 00
ILIM[1:0] = 01
ILIM[1:0] = 10
ILIM[1:0] = 11, default
ILIM[1:0] = 00
Low-Side MOSFET Forward
Current Limit
ILIM_LS
A
—
—
ILIM[1:0] = 01
—
—
ILIM[1:0] = 10
—
—
ILIM[1:0] = 11, default
Low-Side MOSFET Negative
Current Limit
ILIM_NEG
IZC_TH
HICCUP
—
-2
-4
A
A
N-Channel Zero-Crossing
Threshold
—
—
—
0.9
8
—
—
—
Current Limit Pulses before
Hiccup
Cycles
ms
Hiccup Period before Restart
Internal MOSFETs
1
High-Side On-Resistance
Low-Side On-Resistance
RDS-ON-HS
RDS-ON-LS
—
—
—
30
16
10
60
40
50
mΩ ISW = 1A
mΩ ISW = -1A
Output Discharge Resistance RDS-ON-DSC
Ω
VEN = 0V, VSW = 5.5V,
from VOUT to PGND
SW Leakage Current
Power Good (PG)
ILEAK_SW
—
1
10
µA
PVIN = 5.5V, VSW = 5.5V, VEN = 0V
PG Threshold
PG_TH
PG_HYS
87
—
—
—
—
91
4
95
—
%VOUT VOUT rising (good)
PG Hysteresis
%VOUT VOUT falling
PG Blanking Time
PG_BLANK
PG_LEAK
PG_SINKV
65
30
—
—
µs
PG Output Leakage Current
PG Sink Low Voltage
I2C Interface (SCL, SDA)
Low-Level Input Voltage
High-Level Input Voltage
High-Level Input Current
Low-Level Input Current
Logic 0 Output Voltage
SCL,SDA Pin Capacitance
SDA Pull-Down Resistance
—
nA
200
mV
VOUT = 0V, IPG = 10 mA
VIL
VIH
0
1.2
-1
—
—
0.4
5.5
1
V
V
SVIN = 5.5V
SVIN = 5.5V
II2C_H
II2C_L
0.01
0.01
—
µA
µA
V
-1
1
VOL
—
—
—
0.4
—
—
ISDA = 3 mA, ISCL = 3 mA
I2C_CAP
SDA_PD
0.7
80
pF
Ω
Note 1: Specification for packaged product only.
2: Characterized in open loop.
DS20006256A-page 8
2019 Microchip Technology Inc.
MIC33M656
(1,2)
ELECTRICAL CHARACTERISTICS
(CONTINUED)
Electrical Specifications: Unless otherwise specified, PVIN = 5V; VOUT = 1.0V; COUT = 2 x 47 µF; TA = +25°C.
Boldface values indicate -40°C TJ +125°C.
Parameter
Symbol
Min.
Typ.
Max.
Units
Conditions
I2C Interface Timing
Maximum SCL Clock
Frequency
SCL_CLOCK
—
—
—
100
400
3.4
—
—
—
kHz Standard mode
kHz Fast mode
MHz High-Speed mode
Thermal Shutdown
Thermal Shutdown
TSHDN
—
—
—
—
165
22
—
—
—
—
°C
°C
°C
—
TJ rising
TJ falling
TJ rising
Thermal Shutdown Hysteresis TSHDN_HYST
Thermal Warning Threshold
TThWrn
118
4
Thermal Latch-Off Soft Start
Cycles
TH_LATCH
Note 1: Specification for packaged product only.
2: Characterized in open loop.
TEMPERATURE SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, PVIN = 5V; VOUT = 1.0V; COUT = 2 x 47 µF; TA = +25°C.
Boldface values indicate -40°C TJ +125°C.
Parameters
Temperature Ranges
Sym.
Min.
Typ.
Max.
Units
Conditions
Junction Temperature
TJ
TA
40
—
—
+125
+150
°C
°C
Storage Temperature Range
Package Thermal Resistances
-65
Thermal Resistance,
JA
—
45
—
°C/W
53-Lead 6 mm x 10 mm x 3 mm B1QFN
2019 Microchip Technology Inc.
DS20006256A-page 9
MIC33M656
NOTES:
DS20006256A-page 10
2019 Microchip Technology Inc.
MIC33M656
2.0
TYPICAL CHARACTERISTIC CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VIN = PVIN = AUX_PVIN = 5V; VOUT = 1V; COUT = 2 x 47 µF; TA = +25°C.
61
80
VOUT = 1.0V
60
IOUT = 0 mA
75
HLL mode
59
70
58
VOUT = 3.3V
65
60
55
50
45
57
56
55
54
53
VOUT = 1.0V
-40 -25 -10
5
20
35
50
65
80
95 110 125
2.5
3
3.5
VIN (V)
4
4.5
5
Ambient Temperature (°C)
FIGURE 2-1:
Operating Supply Current vs.
FIGURE 2-4:
Operating Supply Current vs.
Input Voltage, Switching.
Temperature, Switching.
40
35
11
10
9
8
7
6
5
ILIM = 10A
HHiigghh-SSiiddeeOONn--RReessisistatanncece
30
25
20
15
10
5
ILIM = 8.5A
ILIM = 5A
Low-Side On-Resistance
Low Side ON-Resistance
ILIM = 3.5A
4
3
2
1
VIN = 5.0V
VOUT = 1V
0
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Ambient Temperature (°C)
Ambient Temperature (°C)
FIGURE 2-2:
High-Side Current Limits vs.
FIGURE 2-5:
RDS(on) vs. Temperature.
Temperature (VOUT = 1.0V), Closed Loop.
21
19
17
100.00
90.00
80.00
70.00
60.00
50.00
40.00
30.00
20.00
10.00
VIN = 3.3V
15
13
11
9
ILIM = 10A
ILIM = 8.5A
ILIM = 5A
VIN = 5.0V
7
5
VIN = 5.0V
3
ILIM = 3.5A
VOUT = 0.6V
VOUT = 3.3V
1
0.00
0.0001
-40 -25 -10
5
20
35
50
65
80
95 110 125
0.001
0.01
0.1
1
10
IOUT (A)
Ambient Temperature (°C)
FIGURE 2-6:
Efficiency vs. Load Current
FIGURE 2-3:
High-Side Current Limits vs.
(VOUT = 0.6V).
Temperature (VOUT = 3.3V), Closed Loop.
2019 Microchip Technology Inc.
DS20006256A-page 11
MIC33M656
Note: Unless otherwise indicated, VIN = PVIN = AUX_PVIN = 5V; VOUT = 1V; COUT = 2 x 47 µF; TA = +25°C.
100.00
90.00
80.00
70.00
60.00
50.00
40.00
30.00
20.00
10.00
0.00
0.06
0.04
0.02
0
FPWM mode
IOUT = 300 mA
VIN = 5.0V
VIN = 3.3V
VOUT = 0.6V
VOUT = 1.0V
VOUT = 3.3V
VOUT = 1V
0.0001
0.001
0.01
0.1
1
10
2.5
3
3.5
4
4.5
5
5.5
IOUT (A)
VIN (V)
FIGURE 2-7:
Efficiency vs. Load Current
FIGURE 2-10:
Line Regulation: Output
(VOUT = 1.0V).
Voltage Variation vs. Input Voltage.
100.00
90.00
80.00
70.00
60.00
50.00
40.00
30.00
20.00
10.00
0.00
FPWM mode
IN = 5V
0.14
0.12
0.1
V
VOUT = 0.6V
VOUT = 1.0V
VOUT = 2.5V
VOUT = 3.3V
VIN = 5.5V
VIN = 4.0V
0.08
0.06
0.04
0.02
0
VOUT = 3.3V
0
1
2
3
4
5
6
0.0001
0.001
0.01
0.1
1
10
IOUT (A)
IOUT (A)
FIGURE 2-8:
Efficiency vs. Load Current
FIGURE 2-11:
Load Regulation: VOUT
(VOUT = 3.3V).
Voltage Variation vs. IOUT
.
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
2.2
1.9
1.6
1.3
1
VOUT = 1V
VOUT = 0.6V
VIN = 5.0V
TON[1:0] = 11
TON[1:0] = 10
TON[1:0] = 11
TON[1:0] = 10
TON[1:0] = 01
TON[1:0] = 00
TON[1:0] = 01
TON[1:0] = 00
0.7
0
2
4
6
2.5
3
3.5
VIN (V)
4
4.5
5
IOUT (A)
FIGURE 2-9:
DCM/FPWM IOUT Threshold
FIGURE 2-12:
Switching Frequency vs.
vs. VIN.
IOUT (VOUT = 0.6V).
DS20006256A-page 12
2019 Microchip Technology Inc.
MIC33M656
Note: Unless otherwise indicated, VIN = PVIN = AUX_PVIN = 5V; VOUT = 1V; COUT = 2 x 47 µF; TA = +25°C.
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
VOUT = 1.0Vꢀ
VOUT = 1V
3.5
2.9
2.3
1.7
1.1
0.5
IOUTꢀ = 2.0A
VIN = 5.0V
TON[1:0] = 11
TON[1:0] = 11
TON[1:0] = 10
TON[1:0] = 10
TON[1:0] = 01
TON[1:0] = 01
TON[1:0] = 00
TON[1:0] = 00
2.5
3.5
4.5
5.5
0
2
4
6
VIN (V)
IOUT (A)
FIGURE 2-13:
Switching Frequency vs.
FIGURE 2-16:
Switching Frequency vs. VIN
IOUT (VOUT = 1.0V).
(VOUT = 1.0V).
VOUT = 3.3V
3.5
VOUT = 3.3V
3.5
IOUT = 2.0A
VIN = 5.0V
TON[1:0] = 11
TON[1:0] = 11
2.9
2.9
2.3
1.7
1.1
0.5
2.3 TON[1:0] = 10
TON[1:0] = 10
1.7
TON[1:0] = 01
TON[1:0] = 00
TON[1:0] = 01
TON[1:0] = 00
1.1
0.5
4
4.5
5
5.5
0
2
4
6
IOUT (A)
VIN (V)
FIGURE 2-14:
Switching Frequency vs.
FIGURE 2-17:
Switching Frequency vs. VIN
IOUT (VOUT = 3.3V).
(VOUT = 3.3V).
VOUT = 0.6V
3.5
IOUT = 2.0A
2.9
TON[1:0] = 11
2.3
1.7
TON[1:0] = 10
TON[1:0] = 01
1.1
TON[1:0] = 00
0.5
2.5
3.5
4.5
5.5
VIN (V)
FIGURE 2-15:
Switching Frequency vs. VIN
(VOUT = 0.6V).
2019 Microchip Technology Inc.
DS20006256A-page 13
MIC33M656
Note: Unless otherwise indicated, VIN = PVIN = AUX_PVIN = 5V; COUT = 2 x 47 µF; TON[1:0] = 11; ILIM[1:0] = 11;
VOUT = 1V; TA = +25°C.
EN
5V/div
VIN
5V/div
VOUT
500 mV/div
VOUT
500 mV/div
SW
5V/div
PG
5V/div
IO
2A/div
PG
5V/div
80 µs/div
2 ms/div
FIGURE 2-18:
VIN Turn-On (EN = PVIN).
FIGURE 2-21:
EN Turn-Off, RLOAD = 0.3.
9
,1
ꢀ9ꢁGLY
EN
2V/div
9
VOUT
500 mV/div
287
ꢀꢂꢂ P9ꢁGLY
3*
ꢀ9ꢁGLY
PG
5V/div
SW
5V/div
6:
ꢀ9ꢁGLY
1 ms/div
ꢃꢂꢂ VꢁGLY
FIGURE 2-19:
VIN Turn-Off (EN = PVIN)
,
FIGURE 2-22:
EN Turn-On into Pre-Biased
R
LOAD = 0.3.
Output (Vpre-bias = 0.8V).
EN
5V/div
EN
5V/div
VOUT
500 mV/div
VOUT
500 mV/div
PG
5V/div
PG
5V/div
SW
5V/div
IO
2A/div
2 ms/div
2 ms/div
FIGURE 2-20:
EN Turn-On, RLOAD = 0.3.
FIGURE 2-23:
Power-up into Short Circuit.
DS20006256A-page 14
2019 Microchip Technology Inc.
MIC33M656
Note: Unless otherwise indicated, VIN = PVIN = AUX_PVIN = 5V; COUT = 2 x 47 µF; TON[1:0] = 11; ILIM[1:0] = 11;
VOUT = 1V; TA = +25°C.
VIN
5V/div
VOUT
1V/div
VOUT
50 mV/div
AC coupled
IOUT
5A/div
SW 5V/div
PG
5V/div
IO
5A/div
SW
5V/div
1 µs/div
2 ms/div
FIGURE 2-24:
Output Current Limit
FIGURE 2-27:
Switching Waveforms –
Threshold.
IOUT = 6A.
Step from 0.5A to 6A
PG
5V/div
VOUT
1V/div
VOUT
100 mV/div
IO
10A/div
SW
5V/div
SW
5V/div
PG
5V/div
IO
5A/div
1 ms/div
80 µs/div
FIGURE 2-25:
Hiccup Mode Short-Circuit
FIGURE 2-28:
Load Transient Response.
Current Limit Response.
Step from 4.5V to 5.5V
VIN
5V/div
PG
5V/div
VIN
2V/div
VOUT
50 mV/div
AC coupled
VOUT, 10 mV/div
AC coupled
SW
5V/div
IO
IO
2A/div
50 mA/div
1 µs/div
1 ms/div
FIGURE 2-29:
Line Transient Response.
FIGURE 2-26:
Switching Waveforms –
IOUT = 50 mA, HLL.
2019 Microchip Technology Inc.
DS20006256A-page 15
MIC33M656
NOTES:
DS20006256A-page 16
2019 Microchip Technology Inc.
MIC33M656
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
Pin Number
2, 3, 4, 5, 23, 24,
PIN FUNCTION TABLE
Symbol
Description
Power Ground is the ground path for the MIC33M650 power module.
PGND
39, 40
1, 53
AUX_PVIN
SW
Auxiliary Power Input Voltage Pins: Connect externally to PVIN.
6, 7, 8, 9, 10, 11, 12,
13, 14, 15, 16, 17,
18, 19, 20, 21, 22
Switch Node Pins. SW connects to the internal MOSFETs and inductor.
Do not connect any external load to this point.
41, 42
PVIN
OUT
Power Supply Voltage Pins.
Output Side Connection Pins.
25, 26, 27, 28, 29,
30, 31, 32, 33, 34,
35, 36, 37, 38
43, 44
SVIN
Analog Voltage Input Pins: The power to the internal reference and
control sections of the MIC33M650. Internally connected to PVIN through
a 10 resistor.
46, 47
45
AUX_AGND
SCL
Auxiliary Analog Ground Pins: Connect externally to AGND
I2C Clock (Input) Pin: I2C serial bus clock input.
.
48
SDA
I2C Data (Input/Output) Pin: I2C serial bus data bidirectional pin.
49
EN
Enable (Input) Pin: Logic high enables the operation of the regulator. The
EN pin should not be left floating.
50
51
PG
Power Good (Output) Pin: This is an open-drain output that indicates
when the output voltage is higher than the 91% limit.
VOUT
Output Voltage Sense (Input) Pin: This pin is used to remotely sense the
output voltage. Connect VOUT as close to the output capacitor as possible
to sense the output voltage.
52
54
55
56
57
AGND
Analog Ground Pin: Internal signal ground for all low-power circuits.
Exposed Thermal Pad: Internally connected to OUT.
EP_OUT
EP_SW
EP_PGND
EP_PVIN
Exposed Thermal Pad: Internally connected to SW node.
Exposed Thermal Pad: Internally connected to PGND
.
Exposed Thermal Pad: Internally connected to PVIN.
3.1
Power Ground Pin (P
)
3.3
Input Voltage Pin (PV )
IN
GND
PGND is the ground path for the MIC33M656 buck
converter power stage. The PGND pin connects to the
sources of the low-side N-channel MOSFET, the nega-
tive terminals of the input capacitors and the negative
terminals of the output capacitors. The loop for the
Power Ground should be as small as possible and
separate from the Analog Ground (AGND) loop.
Input supply to the source of the internal high-side
P-channel MOSFET. The PVIN operating voltage range
is from 2.4V to 5.5V. An input capacitor between PVIN
and the Power Ground (PGND) pin is required and
placed as close as possible to the IC.
3.4
Analog Voltage Input Pin (SV )
IN
The power to the internal reference and control
sections of the MIC33M656. Internally connected to
PVIN through a 10 resistor.
3.2
Switch Node Pin (SW)
Switching node output pin which connects to the inter-
nal MOSFETs and inductor. This is a high-frequency
connection; therefore, traces should be kept as short
and as wide as practical.
2019 Microchip Technology Inc.
DS20006256A-page 17
MIC33M656
2
3.5
I C Clock Input Pin (SCL)
3.11 Auxiliary Analog Ground Pins
(AUX_A
)
GND
The SCL pin is the serial interface’s serial clock pin.
This pin is connected to the host controller SCL pin.
Connect these pins to AGND to make use of the internal
decoupling capacitor for SVIN pin filtering.
The MIC33M656 is a slave device, so its SCL pin is
only an input.
3.12 Auxiliary Input Voltage Pins
2
3.6
I C Data Input/Output Pin (SDA)
(AUX_PV )
IN
The SDA pin is the serial interface’s serial data pin.
This pin is connected to the host controller SDA pin.
The SDA pin has an open-drain N-channel driver.
Connect these pins to PVIN to make use of the internal
10 µF capacitor for PVIN filtering/decoupling.
3.13
P
Exposed Pad (EP_P
)
GND
GND
3.7
Enable Pin (EN)
Electrically connected to the PGND pins. Connect with
thermalviastothegroundplanetoensureadequateheat
sinking. See Section 8.0 “Packaging Information”.
Logic high enables operation of the regulator. Logic low
will shut down the device. In the OFF state, the supply
current of the device is greatly reduced (typically
1.5 µA). The EN pin should not be left open.
3.14 OUT Exposed Pad (EP_OUT)
Electrically connected to the OUT pins. Must be
externally connected to the output power connection.
3.8
Power Good Pin (PG)
This is an open-drain output that indicates when the
rising output voltage is higher than the 91% threshold.
There is a 4% hysteresis; therefore, PG will return low
when the output voltage falls below 87% of the target
regulation voltage.
3.15 SW Exposed Pad (EP_SW)
Electrically connected to the SW node.
3.16 PV Exposed Pad (EP_PV )
IN
IN
3.9
Output Voltage Sense Pin (V
)
OUT
Electrically connected to the PVIN pins. Must be
connected to the input power connection.
This pin is used to remotely sense the output voltage.
Connect to VOUT as close to the output capacitor as
possible to sense the output voltage. This pin also
provides the path to discharge the output through an
internal 10 resistor when the device is disabled.
3.10 Analog Ground Pin (A
)
GND
Internal signal ground for all low-power circuits.
Connect to ground plane. For best load regulation, the
connection path from AGND to the output capacitor
ground terminal should be free from parasitic voltage
drops.
DS20006256A-page 18
2019 Microchip Technology Inc.
MIC33M656
4.3
Enable (EN Pin)
4.0
4.1
FUNCTIONAL DESCRIPTION
Device Overview
When the EN pin is pulled low, the IC is in a shutdown
state with all internal circuits disabled and with the
Power Good (PG) output low. During shutdown, the
part typically consumes 1.5 µA. When the EN pin is
pulled high, the start-up sequence is initiated. There is
a programmable enable delay that is used to delay the
start of the output ramp. The enable delay timer can be
programmed to one of four time intervals of 0.25 ms,
1 ms, 2 ms or 3 ms in the CTRL1 register. Note that if
the 0 ms delay setting is chosen, there is an internal
delay of 250 µs before the part will start to switch in
order to bias up internal circuitry.
The MIC33M656 is a high-efficiency 6A peak current,
synchronous buck regulator with HyperLight Load
mode. The module integrates the inductor alongside
high-frequency, ripple dampening capacitors on the
input and output of the converter and decoupling
capacitor for the signal input. The Constant-On-Time
(COT) control architecture with automatic HyperLight
Load mode provides very high efficiency at light loads
and ultra-fast transient response.
The MIC33M656 output voltage is programmed
through the I2C interface, in the range of 0.6V to 1.28V,
with 5 mV resolution (options YMP, HAYMP and
FAYMP), or between 0.6V and 3.84V (option SAYMP).
The latter option has a 10 mV resolution, from 0.6V up
to 1.28V and a 20 mV resolution, from 1.28V to 3.84V.
2
4.4
I C Programming
The MIC33M656 behaves as an I2C slave, accessible
at 0x5B (7-bit addressing).
The I2C interface remains active and the MIC33M656
can be programmed whether the Enable pin is high or
low, as long as the input voltage is above the UVLO
threshold. This feature is useful in applications where a
housekeeping MCU preconfigures the MIC33M656
before enabling power delivery. The registers do not
get reset when the enable pin is low. The output voltage
can be programmed to a new value with I2C, regard-
less of the EN pin status. If the EN pin is high, the
output voltage will move to the newly programmed
value on-the-fly, with the programmed slew rate.
The 2.4V to 5.5V input voltage operating range makes
the device ideal for single-cell Li-ion battery-powered
applications. Automatic HyperLight Load mode
provides very high efficiency at light loads.
This device focuses on high output voltage accuracy.
Total output error is less than 1.5% over line, load and
temperature.
The MIC33M656 buck regulator uses an adaptive
Constant-On-Time control method. The adaptive on-time
control scheme is employed to obtain a nearly constant
switching frequency in Continuous Conduction mode.
Overcurrent protection is implemented by sensing the
current on both the low-side and high-side internal power
MOSFETs. The device includes an internal soft start func-
tion, which reduces the power supply input surge current
at start-up by controlling the output voltage rise time.
4.5
Power Good (PG)
The Power Good output is generally used for power
sequencing where the Power Good output is tied to the
enable output of another regulator. This technique
avoids all the regulators powering up at the same time,
causing large inrush current.
4.2
HyperLight Load Mode (HLL)
The Power Good output is an open-drain output. During
start-up, when the output voltage is rising, the Power
Good output goes high by means of an external pull-up
resistor when the output voltage reaches 91% of its set
value. The Power Good threshold has 4% hysteresis, so
the Power Good output stays high until the output voltage
falls below 87% of the set value. A built-in 65 µs blanking
time is incorporated to prevent nuisance tripping.
HLL is a power-saving switching mode. In HLL, the
switching frequency is not constant over the operation
current range. At light loads, the fixed on-time opera-
tion, coupled with low-side MOSFET diode emulation,
causes the switching frequency to decrease. This
reduces switching and drive losses, and increases
efficiency. The HLL switching mode can be disabled for
reduced output ripple and low noise by setting the
FPWM bit in the CTRL2 register.
The pull-up resistor from the PG pin can be connected
to VIN, VOUT or an external source that is less than or
equal to VIN. The PG pin can be connected to another
regulator’s enable pin for sequencing of the outputs.
The PG output is deasserted as soon as the Enable pin
is pulled low, or an input undervoltage condition or any
other Fault is detected.
2019 Microchip Technology Inc.
DS20006256A-page 19
MIC33M656
4.6
Output Soft Discharge Option
4.10 100% Duty Cycle Operation
To ensure a known output condition when the device is
turned off, then back on again, the output is actively
discharged to ground by means of an internal 10
resistor. The active discharge resistor can be enabled
or disabled through I2C in the CTRL2 register.
The MIC33M656 can deliver 100% duty cycle. To
achieve 100% duty cycle, the high-side switch is
latched on when the duty cycle reaches around 92%
and stays latched until the output voltage falls 4%
below its regulated value. This feature is especially
useful in battery-operated applications. It is recom-
mended that this feature is enabled together with the
highest TON setting, corresponding to the lowest
switching frequency (TON[1:0] = 00 in the CTRL1 reg-
ister). The high-side latch circuitry can be disabled by
setting the DIS_100PCT bit in the CTRL2 register to ‘1’.
4.7
Output Voltage Setting
The MIC33M656 output voltage has an 8-bit control DAC
that can be programmed from 0.6V to 1.28V, in 5 mV
increments, for part options HAYMP and FAYMP. Option
SAYMP can be programmed from 0.6V, up to 1.28V, with
10 mV resolution and from 1.28V up to 3.84V, with 20 mV
resolution. This can be programmed in the Output Voltage
Control (VOUT) register.
4.11 Switching Frequency
The switching frequency of the MIC33M656 is indirectly
set by programming the TON value. The equation
below provides an estimation for the resulting switching
frequency:
The output voltage sensing pin, VOUT, should be
connected exactly to the desired Point-of-Load (POL)
regulation, avoiding parasitic resistive drops.
4.8
Converter Stability/Output
Capacitor
EQUATION 4-2:
V
1
TON
OUT
fSW
=
-------------- ---------
The MIC33M656 utilizes an internal compensation
network and it is designed to provide stable operation
with output capacitors from 47 µF to 1000 µF. This
greatly simplifies the design where supplementary
output capacitance can be added without affecting
stability.
VIN
Equation 4-2 is valid only in Continuous Conduction
mode and for a loss-less converter. In practice, losses
will cause an increase of the switching frequency with
respect to the ideal case. As the load current increases,
losses will increase too and so will the switching
frequency.
4.9
Soft Start
Excess bulk capacitance on the output can cause
excessive input inrush current. The MIC33M656 inter-
nal soft start feature forces the output voltage to rise
gradually, keeping the inrush current at reasonable
levels. This is particularly important in battery-powered
applications. The ramp rate can be set in the CTRL2
register by means of the SLEW_RATE[3:0] bits (see
Register 7-2).
The on-time calculation is adaptive, in that the TON
value is modulated based on the input voltage, and on
the target output voltage, to stabilize the switching
frequency against their variations. Losses are not
accounted for.
The table below highlights the resulting On Time (TON
)
for typical output voltages:
When the enable pin goes high, the output voltage
starts to rise. Once the soft start period has finished,
the Power Good comparator is enabled and if the
output voltage is above 91% of the nominal regulation
voltage, then the Power Good output goes high.
TABLE 4-1:
ON-TIME CALCULATIONS
TON
VIN (V) VOUT (V) [00]
[01]
[10]
[11]
The output voltage soft start time is determined by the
soft start equation below. The Soft Start Time, tSS, can
be calculated using Equation 4-1.
5
0.6
1
140
260
520
740
930
380
110
180
340
490
610
270
100
130
200
260
310
170
80
105
150
190
220
130
1.8
2.5
3.3
1
EQUATION 4-1:
tSS = V
tRAMP
OUT
3.3
tSS = 1.0V 800s V
tSS = 800s = 0.8ms
Where:
V
=
=
1.0V
800 µs/V
OUT
t
RAMP
DS20006256A-page 20
2019 Microchip Technology Inc.
MIC33M656
4.12 Undervoltage Protection (UVLO)
4.14 Safe Start-up into a Pre-Biased
Output
Undervoltage protection ensures that the IC has
enough voltage to bias the internal circuitry properly
and provide sufficient gate drive for the power
MOSFETs. When the input voltage starts to rise, both
power MOSFETs are off and the Power Good output is
pulled low. The IC starts at approximately 2.225V typi-
cal and has a nominal 153 mV of hysteresis to prevent
chattering between the UVLO high and low states.
The MIC33M656 is designed for safe start-up into a
pre-biased output in forced PWM. This feature prevents
high negative inductor current flow in a pre-bias condition,
which can damage the IC. This is achieved by not allow-
ing forced PWM until the control loop commands eight
switching cycles. After eight cycles, the low-side negative
current limit is switched from 0A to -3A. The cycle counter
is reset to zero if the Enable pin is pulled low, or an input
undervoltage condition or any other Fault is detected.
4.13 Overtemperature Fault
The MIC33M656 monitors the die junction temperature
to keep the IC operating properly. If the IC junction
temperature exceeds +118°C, the warning flag,
“OT_WARN”, is set, but does not affect the operation
mode. It automatically resets if the junction temperature
drops below the temperature threshold. If the IC junction
temperature exceeds +165°C, both power MOSFETs
are immediately turned off. The IC is allowed to start
when the die temperature falls below +143°C.
4.15 Current Limiting
The MIC33M656 regulator uses both high-side and
low-side current sense for current limiting. When the
high-side current sense threshold is reached, the
high-side MOSFET is turned off and the low-side
MOSFET is turned on. The low-side MOSFET stays on
until the current falls to 80% of the high-side current
threshold value, then the high-side current can be turned
on again. If the overload condition lasts for more than
seven cycles, the MIC33M656 enters hiccup current lim-
iting and both MOSFETs are turned off. There is a 1 ms
cool-off period before the MOSFETs are allowed to be
turned on. If the regulator has another hiccup event
before it reaches the Power Good threshold on restart, it
will again turn off both MOSFETs and wait for 1 ms. If
this happens more than three times in a row, then the
part will enter the Latch-Off state, which will permanently
turn off both MOSFETs until the part is reset by toggling
the EN pin, recycling power or via an I2C command.
During the Fault condition, several changes will occur in
the STATUS Register. The OT bit will go high, indicating
the junction temperature reached +165°C, while the
OT_WARN automatically resets. If the controller is
enabled to restart after the first thermal shutdown event
(OT_LATCH bit in CTRL2 register is set), the SSD bit will
go low and the HICCUP bit will go high. Finally, the PG bit
in the FAULT register (address 0x03) will go low and the
PG pin will be pulled low until the output voltage has
restarted and is once again in regulation. The I2C inter-
face remains active and all the values stored in registers
are maintained. When the die temperature decreases
below the lower thermal shutdown threshold, and the
MIC33M656 resumes switching with the output voltage
going back in regulation, the global Power Good output is
pulled high, but the Overtemperature Fault bit, OT, is still
set to ‘1’. To clear the Fault, either recycle input power or
write a logic ‘0’ to the Overtemperature bit, OT, in the
FAULT register.
During a hiccup event, the HICCUP bit in the STATUS
Register will go high and the SSD bit will go low until the
output has recovered. The Power Good FAULT register
bit, PG, will also go low and the PG pin will be pulled low.
In latch-off, the LATCH_OFF status bit is set to ‘1’.
The high-side current limit can be programmed by
setting the ILIM[1:0] bits in the CTRL1 register. For max-
imum efficiency and current limit precision, the highest
current limit must be programmed together with a higher
TON setting (corresponding to a lower frequency).
During recovery from a thermal shutdown event, if the
regulator hits another thermal shutdown event before
Power Good can be achieved, the controller will again
reset. If this happens four times in a row, the part will be in
a Latch-Off state and the MOSFETs are permanently
latched off. The LATCH_OFF bit in the STATUS Register
will be set to ‘1’, which will latch off the MIC33M656. The
device can be restarted by toggling the enable input, by
recycling the input power or by software Enable Control
(EN_CON). This latch-off feature eliminates the thermal
stress on the MIC33M656 during a Fault event. The
OT_LATCH bit in the CTRL2 register can be set to ‘0’,
which will cause this latch-off to happen after the first over-
temperature event, instead of waiting for four consecutive
overtemperatures. This is a more conservative approach
to protect the part and is available to the user.
4.16 Thermal Considerations
Although the MIC33M656 is capable of delivering up to
6A under load, the package thermal resistance and the
device internal power dissipation may dictate some
limitations to the continuous output current.
As a reference, for VIN = 5V, VOUT = 1V, IOUT = 5A, the
DT100108 Evaluation Board application shows a
stable +40°C chip self-heating.
For VIN = 5V, VOUT = 3.3V, the same self-heating is
produced at about 4A.
If operated above the rated junction temperature,
electrical parameters may drift beyond characterized
specifications. The MIC33M656 is protected under all
circumstances by thermal shutdown.
2019 Microchip Technology Inc.
DS20006256A-page 21
MIC33M656
NOTES:
DS20006256A-page 22
2019 Microchip Technology Inc.
MIC33M656
The type of output capacitor is usually determined by its
Equivalent Series Resistance (ESR). Voltage and RMS
current capability are two other important factors to con-
sider when selecting the output capacitor. Recommended
capacitor types are ceramic, OS-CON and POSCAP. The
output capacitor ESR is usually the main cause of the out-
put ripple. The output capacitor ESR also affects the con-
trol loop from a stability point of view. The maximum value
of ESR is calculated using Equation 5-1.
5.0
5.1
APPLICATION INFORMATION
Power-up State
When power is first applied to the MIC33M656 and the
Enable pin is high, all I2C registers are loaded with their
default values and the device starts delivering power to
the output based on those default values. After the soft
start ramp has finished, these registers can be recon-
figured. These new settings are saved, even if the
Enable pin is pulled low. When the Enable pin is pulled
high again, the MIC33M656 is configured to the new
register settings, not the original default settings. To set
the I2C registers to their original settings, the input
power has to be recycled.
EQUATION 5-1:
V
OUTPP
ESR
---------------------------------
C
I
OUT
LPP
Where:
ΔV
=
=
Peak-to-Peak Output Voltage Ripple
Peak-to-Peak Inductor Current Ripple
When power is first applied to the MIC33M656 and the
Enable pin is low, all I2C registers can be configured.
When the Enable pin is pulled high, the regulator will
power up with the new I2C register settings. Again, these
register settings will not be lost when the Enable pin is
pulled low. If power is recycled, the register settings are
lost and they will have to be reprogrammed.
OUT(PP)
ΔI
L(PP)
The peak-to-peak inductor current ripple can be
calculated by using the formula in Equation 5-3.
EQUATION 5-2:
VOUT (VIN(MAX) – VOUT
VIN(MAX) fSW L
)
5.2
Output Voltage Sensing
IL(PP)
=
To achieve accurate output voltage regulation, the VOUT
pin (internal feedback divider top terminal) should be
Kelvin connected as close as possible to the point of reg-
ulation top terminal. Since both the internal reference and
the internal feedback divider’s bottom terminal refer to
AGND, it is important to minimize voltage drops between
AGND and the point of regulation return terminal (typically,
the ground terminal of the output capacitor which is
closest to the load).
Where:
L
=
0.47 µH
The total output ripple is a combination of the ESR and
output capacitance. The total ripple is calculated in
Equation 5-3.
EQUATION 5-3:
2
I
2
LPP
------------------------------------------
V
=
+
I
ESR
C
5.3
Digital Voltage Control (DVC)
OUTPP
LPP
C
f 8
OUT SW
OUT
When the buck converter is programmed to a lower volt-
age, the regulator is placed into forced PWM mode and
the Power Good monitor is blanked during the transition
time.
Where:
C
=
=
Output Capacitance Value
Switching Frequency
OUT
f
SW
The output capacitor RMS current is calculated in
Equation 5-4.
5.4
Output Capacitor Selection
The MIC33M656 utilizes an internal compensation
network and is designed to provide stable operation,
with output capacitors from 47 μF to 1000 μF. This
greatly simplifies the design, where supplementary
output capacitance can be added without affecting
stability.
EQUATION 5-4:
I
LPP
I
= ---------------------
12
C
OUTRMS
The power dissipated in the output capacitor is:
EQUATION 5-5:
2
P
= I
ESR
DISSCOUT
COUTRMS
COUT
2019 Microchip Technology Inc.
DS20006256A-page 23
MIC33M656
TABLE 5-1:
I2C BUS CONSTRAINTS
Standard Fast High-Speed
Mode Mode Mode
0 to 100 0 to 400 0 to 1700 0 to 3400
5.5
Input Capacitor Selection
The MIC33M656 integrates high-frequency input
bypass capacitors connected between PVIN and PGND
,
and an additional 10 µF, low-ESR ceramic capacitor for
input ripple smoothing, connected between PGND and
AUX_PVIN. Therefore, the connection between PVIN
and AUX_PVIN should have very low stray resistance
and inductance (i.e., many vias) to take advantage of
the internal 10 µF capacitor. While the internal 10 µF
capacitor can support the RMS ripple current, addi-
tional external input ceramic capacitors can be added
optionally to further attenuate the input voltage ripple
amplitude. The need for additional external input
capacitance also depends on the impedance of the
input supply distribution network.
Bit Rate
(kbits/s)
Max Cap
Load (pF)
400
1000
N/A
400
300
50
400
160
100
80
Rise Time
(ns)
Spike
Filtered (ns)
10
EQUATION 5-6:
V
CC – VOLmax
Rpmin = ----------------------------------------------
IOL
2
5.6
I C Bus Pull-ups Selection
Where:
The optimal pull-up resistors must be strong enough
such that the RC constant of the bus is not too large
(causing the line not to rise to a logical high before
being pulled low), but weak enough for the IC to drive
the line low (see Table 5-1).
V
=
=
=
Pull-up Reference Voltage (i.e., V )
IN
CC
V
(max)
0.4V
OL
I
3 mA
OL
DS20006256A-page 24
2019 Microchip Technology Inc.
MIC33M656
2
6.0
I C INTERFACE DESCRIPTION
The I2C bus is for 2-way, 2-line communication
between different ICs or modules. The two lines are: a
Serial Data line (SDA) and a Serial Clock line (SCL).
Both lines must be connected to a positive supply via a
pull-up resistor. Data transfer may be initiated only
when the bus is not busy. MIC33M656 is a slave only
device (i.e., it cannot generate a SCL signal and does
not have SCL clock stretching capability). Every data
transfer, to and from the MIC33M656, must be initiated
by a master device which drives the SCL line.
SDA
SCL
Change of data
allowed
Data line stable;
data valid
FIGURE 6-1:
6.1
Bit Transfer Diagram.
Start (Sr) condition. A low-to-high transition of the data
line while the clock is high is defined as the Stop
condition (P). Start and Stop conditions are always
generated by the master. The bus is considered to be
busy after the Start condition. The bus is considered to
be free again a certain time after the Stop condition.
The bus stays busy if a Repeated Start (Sr) is
generated instead of a Stop condition.
Bit Transfer
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the
high period of the clock pulse as changes in the data
line, at this time, will be interpreted as control signals.
6.2
Start and Stop Conditions
Both data and clock lines remain high when the bus is
not busy. A high-to-low transition of the data line, while
the clock is high, is defined as the Start (S) or Repeated
SDA
SDA
SCL
S
SCL
P
Stop Condition
Start Condition
START condition
FIGURE 6-2:
Start and Stop Conditions.
2019 Microchip Technology Inc.
DS20006256A-page 25
MIC33M656
means that the master will write information to a
selected slave. A ‘1’ in this position means that the
master will read information from the slave. When an
address is sent, each device in a system compares the
first seven bits after the Start condition with its address.
If they match, the device considers itself addressed by
the master as a slave-receiver or slave-transmitter,
depending on the R/W bit.
6.3
Device Address
The MIC33M656 device uses a fixed 7-bit address,
which is set in hardware. This address is ‘0x5B’.
6.4
Acknowledge
The number of data bytes transferred between the Start
and the Stop conditions, from transmitter to receiver, is
not limited. Each byte of eight bits is followed by one
Acknowledge bit. The Acknowledge bit is a high level
put on the bus by the transmitter, whereas the master
generates an extra Acknowledge related clock pulse.
The device that Acknowledges has to pull down the
SDA line during the Acknowledge clock pulse, so that
the SDA line is stable low during the high period of the
Acknowledge related clock pulse; setup and hold times
must be taken into account.
A command byte is a data byte which selects a register
on the device. The Least Significant six bits of the com-
mand byte determine the address of the register that
needs to be written.
The data to port are the 8-bit data that need to be written
to the selected register. This is followed by the
Acknowledge from the slave and then the Stop
condition.
The Write command is as follows and it is illustrated in
the timing diagram shown in Figure 6-3:
A slave receiver, which is addressed, must generate an
Acknowledge after the reception of each byte.
1. Send Start sequence.
Also, a master receiver must generate an Acknowledge
after the reception of each byte that has been clocked
out of the slave transmitter, except on the last received
byte. A master receiver must signal an end of data to
the transmitter by not generating an Acknowledge on
the last byte that has been clocked out of the slave
transmitter. In this event, the transmitter must leave the
data line high to enable the master to generate a Stop
condition.
2. Send 7-bit slave address.
3. Send the R/W bit – ‘0’ to indicate a write
operation.
4. Wait for Acknowledge from the slave.
5. Send the command byte containing the address
that needs to be written.
6. Wait for Acknowledge from the slave.
7. Receive the 8-bit data from the master and write
them to the slave register, indicated in Step 5,
starting from the MSB.
6.5
Bus Transactions
8. Acknowledge from the slave.
9. Send Stop sequence.
6.5.1
SINGLE WRITE
The first seven bits of the first byte make up the slave
address. The eighth bit is the LSb (Least Significant
bit). It determines the direction of the message (R/W).
A ‘0’ in the least significant position of the first byte
Note:
Writing to a non-existing register location
will have no effect.
1
2
3
4
5
6
7
8
9
SCL
Data to port
DATA 1
Slave address
Command byte
S
0
A
0
0
A
A
P
SDA
ACK from
Slave
START condition
R/W
ACK from
Slave
ACK from
Slave
DATA 1 VALID
Data out from port
FIGURE 6-3:
Single Write Timing Diagram.
DS20006256A-page 26
2019 Microchip Technology Inc.
MIC33M656
7. Send Start sequence again (Repeated Start
condition).
6.5.2
SINGLE READ
This reads a single byte from a device, from a
designated register. The register is specified through
the command byte.
8. Send the 7-bit slave address.
9. Send R/W bit – ‘1’ to indicate a read operation.
10. Wait for Acknowledge from the slave.
The Read command is as follows and it is illustrated in
the timing diagram of Figure 6-4 below.
11. Receive the 8-bit data from the slave starting
from MSB.
1. Send Start sequence.
12. Acknowledge from the master. On the received
byte, the master receiver issues a NACK in
place of an ACK to signal the end of the data
transfer.
2. Send 7-bit slave address.
3. Send the R/W bit – ‘0’ to indicate a write operation.
4. Wait for Acknowledge from the slave.
5. Send the register address that needs to be read.
6. Wait for Acknowledge from the slave.
13. Send Stop sequence.
Note:
Attempts to read from a non-existing
register location will return all zeros.
Slave address
Command byte
(cont.)
* * *
SDA
S
0
A
A
ACK from
Slave
START
condition
R/W
ACK from Slave
Slave address
Data from register
DATA (first byte)
(cont.)
* * *
Sr
1
A
A
P
(repeated)
START condition
STOP
condition
R/W
ACK from Slave
At this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
FIGURE 6-4:
Single Read Timing Diagram.
2019 Microchip Technology Inc.
DS20006256A-page 27
MIC33M656
NOTES:
DS20006256A-page 28
2019 Microchip Technology Inc.
MIC33M656
2
7.0
REGISTER MAP AND I C
PROGRAMMABILITY
The MIC33M656 internal registers are summarized in
the MIC33M656 Register Map.
TABLE 7-1:
Address
0x00
MIC33M656 REGISTER MAP
Register Name
Control Register (CTRL1)
TON[1:0]
ILIM[1:0]
Output Control Register (CTRL2)
OT_LATCH PULL_DN
EN_DELAY[1:0]
EN_INT
EN_CON
0x01
DIS_100PCT
FPWM
SLEW_RATE[3:0]
0x02
0x03
Output Voltage Register (VOUT)
VO[7:0]
Status and Fault Register (FAULT)
OT_WARN
EN_STAT BOOT_ERR
SSD
HICCUP
OT
LATCH_OFF
PG
REGISTER 7-1:
CTRL1: CONTROL REGISTER (ADDRESS 0x00)
R/W-V R/W-V R/W-V R/W-0 R/W-0
ILIM[1:0] EN_DELAY[1:0]
R/W-V
TON[1:0]
bit 7
R/W-0
R/W-0
EN_CON
bit 0
EN_INT
Legend:
V = Factory programmed POR value
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
bit 3-2
TON[1:0]: On Time
00 = Low frequency
01 = Medium frequency
10 = High frequency
11 = Very high frequency
ILIM[1:0]: High-Side Peak Current Limit
00 = 3.5A
01 = 5A
10 = 8.5A
11 = 10A
EN_DELAY[1:0]: Enable Delay
00 = 250 µs
01 = 1 ms
10 = 2 ms
11 = 3 ms
bit 1
bit 0
EN_INT: Enable Bit Register Control
0 = Register controlled
1 = Enable pin controlled
EN_CON: Enable Control
0 = Off
1 = On
2019 Microchip Technology Inc.
DS20006256A-page 29
MIC33M656
REGISTER 7-2:
CTRL2: OUTPUT CONTROL REGISTER (ADDRESS 0x01)
R/W-0
DIS_100PCT
bit 7
R/W-0
FPWM
R/W-V
R/W-V
R/W-V
R/W-V
R/W-V
R/W-V
bit 0
OT_LATCH
PULLDN
SLEW_RATE[3:0]
Legend:
V = Factory programmed POR value
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-0
DIS_100PCT: Disable 100% Duty Cycle
0 = 100% DC
1 = Disable 100% DC
FPWM: Force PWM
0 = HLL
1 = FPWM
OT_LATCH: Overtemperature Latch
0 = Latch off immediately
1 = Latch off after four OT cycles
PULLDN: Enable/Disable Regulator Pull-Down when Power-Down
0 = No pull-down
1 = Pull-down
SLEW_RATE[3:0]: Step Slew Rate Time in µs/V
0000 = 200
0001 = 400
0010 = 600
0011 = 800
0100 = 1000
0101 = 1200
0110 = 1400
0111 = 1600
1000 = 1800
1001 = 2000
1010 = 2200
1011 = 2400
1100 = 2600
1101 = 2800
1110 = 3000
1111 = 3200
DS20006256A-page 30
2019 Microchip Technology Inc.
MIC33M656
REGISTER 7-3:
VOUT: OUTPUT VOLTAGE CONTROL REGISTER (ADDRESS 0x02)
R/W-V R/W-V R/W-V R/W-V R/W-V R/W-V
VO[7:0]
R/W-V
R/W-V
bit 0
bit 7
Legend:
V = Factory programmed POR value
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
VO[7:0]: Output Voltage Control (HAYMP, FAYMP options)
For codes 0x00 to 0x76: 0.6V.
0x80 = 0.645
0x81 = 0.65V
0x82 = 0.655V
0x83 = 0.66V
0x84 = 0.665V
0x85 = 0.67V
0x86 = 0.675V
0x87 = 0.68V
0x88 = 0.685V
0x89 = 0.69V
0x8A = 0.695V
0x8B = 0.7V
0xA0 = 0.805V
0xA1 = 0.81V
0xA2 = 0.815V
0xA3 = 0.82V
0xA4 = 0.825V
0xA5 = 0.83V
0xA6 = 0.835V
0xA7 = 0.84V
0xA8 = 0.845V
0xA9 = 0.85V
0xAA = 0.855V
0xAB = 0.86V
0xAC = 0.865V
0xAD = 0.87V
0xAE = 0.875V
0xAF = 0.88V
0xB0 = 0.885V
0xB1 = 0.89V
0xB2 = 0.895V
0xB3 = 0.9V
0xC0 = 0.965
0xC1 = 0.97V
0xC2 = 0.975V
0xC3 = 0.98V
0xC4 = 0.985V
0xC5 = 0.99V
0xC6 = 0.995V
0xC7 = 1V
0xE0 = 1.125V
0xE1 = 1.13V
0xE2 = 1.135V
0xE3 = 1.14V
0xE4 = 1.145V
0xE5 = 1.15V
0xE6 = 1.155V
0xE7 = 1.16V
0xE8 = 1.165V
0xE9 = 1.17V
0xEA = 1.175V
0xEB = 1.18V
0xEC = 1.185V
0xED = 1.19V
0xEE = 1.195V
0xEF = 1.2V
0xC8 = 1.005V
0xC9 = 1.01V
0xCA = 1.015V
0xCB = 1.02V
0xCC = 1.025V
0xCD = 1.03V
0xCE = 1.035V
0xCF = 1.04V
0xD0 = 1.045V
0xD1 = 1.05V
0xD2 = 1.055V
0xD3 = 1.06V
0xD4 = 1.065V
0xD5 = 1.07V
0xD6 = 1.075V
0xD7 = 1.08V
0xD8 = 1.085V
0xD9 = 1.09V
0xDA = 1.095V
0xDB = 1.1V
0x8C = 0.705V
0x8D = 0.71V
0x8E = 0.715V
0x8F = 0.72V
0x90 = 0.725V
0x91 = 0.73V
0x92 = 0.735V
0x93 = 0.74V
0x94 = 0.745V
0x95 = 0.75V
0x96 = 0.755V
0x97 = 0.76V
0x98 = 0.765V
0x99 = 0.77V
0x9A = 0.775V
0x9B = 0.78V
0x9C = 0.785V
0x9D = 0.79V
0x9E = 0.795V
0x9F = 0.8V
0xF0 = 1.205V
0xF1 = 1.21V
0xF2 = 1.215V
0xF3 = 1.22V
0xF4 = 1.225V
0xF5 = 1.23V
0xF6 = 1.235V
0xF7 = 1.24V
0xF8 = 1.245V
0xF9 = 1.25V
0xFA = 1.255V
0xFB = 1.26V
0xFC = 1.265V
0xFD = 1.27V
0xFE = 1.275V
0xFF = 1.28V
0xB4 = 0.905V
0xB5 = 0.91V
0xB6 = 0.915V
0xB7 = 0.92V
0xB8 = 0.925V
0xB9 = 0.93V
0xBA = 0.935V
0xBB = 0.94V
0xBC = 0.945V
0xBD = 0.95V
0xBE = 0.955V
0xBF = 0.96V
0x77 = 0.6V
0x78 = 0.605V
0x79 = 0.61V
0x7A = 0.615V
0x7B = 0.62V
0x7C = 0.625V
0x7D = 0.63V
0x7E = 0.635V
0x7F = 0.64V
0xDC = 1.105V
0xDD = 1.11V
0xDE = 1.115V
0xDF = 1.12V
2019 Microchip Technology Inc.
DS20006256A-page 31
MIC33M656
REGISTER 7-3:
VOUT: OUTPUT VOLTAGE CONTROL REGISTER (ADDRESS 0x02) (CONTINUED)
bit 7-0
VO[7:0]: Output Voltage Control (SAYMP option)
For codes 0x00 to 0x3B: 0.6V.
0x40 = 0.65V 0x60 = 0.97V 0x80 = 1.3V
0xA0 = 1.94V 0xC0 = 2.58V 0xE0 = 3.22V
0xE1 = 3.24V
0x42 = 0.67V 0x62 = 0.99V 0x82 = 1.34V 0xA2 = 1.98V 0xC2 = 2.62V 0xE2 = 3.26V
0x43 = 0.68V 0x63 = 1V 0x83 = 1.36V 0xA3 = 2V 0xC3 = 2.64V 0xE3 = 3.28V
0x44 = 0.69V 0x64 = 1.01V 0x84 = 1.38V 0xA4 = 2.02V 0xC4 = 2.66V 0xE4 = 3.3V
0x45 = 0.7V 0x65 = 1.02V 0x85 = 1.4V 0xA5 = 2.04V 0xC5 = 2.68V 0xE5 = 3.32V
0x46 = 0.71V 0x66 = 1.03V 0x86 = 1.42V 0xA6 = 2.06V 0xC6 = 2.7V 0xE6 = 3.34V
0x47 = 0.72V 0x67 = 1.04V 0x87 = 1.44V 0xA7 = 2.08V 0xC7 = 2.72V 0xE7 = 3.36V
0x48 = 0.73V 0x68 = 1.05V 0x88 = 1.46V 0xA8 = 2.1V 0xC8 = 2.74V 0xE8 = 3.38V
0x41 = 0.66V 0x61 = 0.98V 0x81 = 1.32V 0xA1 = 1.96V 0xC1 = 2.6V
0x49 = 0.74V 0x69 = 1.06V 0x89 = 1.48V 0xA9 = 2.12V 0xC9 = 2.76V 0xE9 = 3.4V
0x4A = 0.75V 0x6A = 1.07V 0x8A = 1.5V 0xAA = 2.14V 0xCA = 2.78V 0xEA = 3.42V
0x4B = 0.76V 0x6B = 1.08V 0x8B = 1.52V 0xAB = 2.16V 0xCB = 2.8V 0xEB = 3.44V
0x4C = 0.77V 0x6C = 1.09V 0x8C = 1.54V 0xAC = 2.18V 0xCC = 2.82V 0xEC = 3.46V
0x4D = 0.78V 0x6D = 1.1V 0x8D = 1.56V 0xAD = 2.2V 0xCD = 2.84V 0xED = 3.48V
0x4E = 0.79V 0x6E = 1.11V 0x8E = 1.58V 0xAE = 2.22V 0xCE = 2.86V 0xEE = 3.5V
0x4F = 0.8V
0x50 = 0.81V 0x70 = 1.13V 0x90 = 1.62V 0xB0 = 2.26V 0xD0 = 2.9V
0x51 = 0.82V 0x71 = 1.14V 0x91 = 1.64V 0xB1 = 2.28V 0xD1 = 2.92V 0xF1 = 3.56V
0x52 = 0.83V 0x72 = 1.15V 0x92 = 1.66V 0xB2 = 2.3V 0xD2 = 2.94V 0xF2 = 3.58V
0x53 = 0.84V 0x73 = 1.16V 0x93 = 1.68V 0xB3 = 2.32V 0xD3 = 2.96V 0xF3 = 3.6V
0x54 = 0.85V 0x74 = 1.17V 0x94 = 1.7V 0xB4 = 2.34V 0xD4 = 2.98V 0xF4 = 3.62V
0x55 = 0.86V 0x75 = 1.18V 0x95 = 1.72V 0xB5 = 2.36V 0xD5 = 3V 0xF5 = 3.64V
0x56 = 0.87V 0x76 = 1.19V 0x96 = 1.74V 0xB6 = 2.38V 0xD6 = 3.02V 0xF6 = 3.66V
0x57 = 0.88V 0x77 = 1.2V 0x97 = 1.76V 0xB7 = 2.4V 0xD7 = 3.04V 0xF7 = 3.68V
0x58 = 0.89V 0x78 = 1.21V 0x98 = 1.78V 0xB8 = 2.42V 0xD8 = 3.06V 0xF8 = 3.7V
0x59 = 0.9V 0x79 = 1.22V 0x99 = 1.8V 0xB9 = 2.44V 0xD9 = 3.08V 0xF9 = 3.72V
0x6F = 1.12V 0x8F = 1.6V 0xAF = 2.24V 0xCF = 2.88V 0xEF = 3.52V
0xF0 = 3.54V
0x5A = 0.91V 0x7A = 1.23V 0x9A = 1.82V 0xBA = 2.46V 0xDA = 3.1V 0xFA = 3.74V
0x5B = 0.92V 0x7B = 1.24V 0x9B = 1.84V 0xBB = 2.48V 0xDB = 3.12V 0xFB = 3.76V
0x3B = 0.6V
0x3C = 0.61V 0x5C = 0.93V 0x7C = 1.25V 0x9C = 1.86V 0xBC = 2.5V 0xDC = 3.14V 0xFC = 3.78V
0x3D = 0.62V 0x5D = 0.94V 0x7D = 1.26V 0x9D = 1.88V 0xBD = 2.52V 0xDD = 3.16V 0xFD = 3.8V
0x3E = 0.63V 0x5E = 0.95V 0x7E = 1.27V 0x9E = 1.9V 0xBE = 2.54V 0xDE = 3.18V 0xFE = 3.82V
0x3F = 0.64V 0x5F = 0.96V 0x7F = 1.28V 0x9F = 1.92V 0xBF = 2.56V 0xDF = 3.2V 0xFF = 3.84V
DS20006256A-page 32
2019 Microchip Technology Inc.
MIC33M656
REGISTER 7-4:
FAULT: STATUS AND FAULT REGISTER (ADDRESS 0x03)
R-0
OT_WARN
bit 7
R-0
R-0
R-0
R-0
R-0
OT
R-0
R-0
PG
EN_STAT
BOOT_ERR
SSD
HICCUP
LATCH_OFF
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OT_WARN: Overtemperature Warning
0 = No Fault
1 = Fault
EN_STAT: Buck On/Off Control
0 = Off
1 = On
BOOT_ERR: Boot-up Error
0 = No Fault
1 = Fault
SSD: Soft Start Done
0 = Ramp not done
1 = Ramp done
HICCUP: Current Limit Hiccup
0 = Not in Hiccup mode
1 = In Hiccup mode
OT: Overtemperature
0 = No Fault
1 = Fault
LATCH_OFF: Overcurrent or Overtemperature Fault Latch-Off
0 = No Fault
1 = Fault (device is latched off)
PG: Power Good
0 = Power not good
1 = Power good
2019 Microchip Technology Inc.
DS20006256A-page 33
MIC33M656
NOTES:
DS20006256A-page 34
2019 Microchip Technology Inc.
MIC33M656
8.0
8.1
PACKAGING INFORMATION
Package Marking Information
53-Lead B1QFN
Example
XXXXX
MIC
33M656
XXXXXXXXX
XXXXXXXXX
FAY-TR
5256
WNNN
PIN 1
PIN 1
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2019 Microchip Technology Inc.
DS20006256A-page 35
MIC33M656
53-Lead Very Thick Plastic Quad Flat, No Lead Package (QDA) - 6x10x3.05 mm Body
[B1QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
53X
0.08 C
0.10 C
D
A
NOTE 1
B
E
53
1
2
(DATUM B)
(DATUM A)
2X
0.05 C
2X
TOP VIEW
0.05 C
A1
0.10
C A B
(A3)
D2
A
2X K6
D3
C
2X K1
SEATING
PLANE
D2
3X K2
20
27
SIDE VIEW
19
28
0.10
C A B
K5
E2
E3
E6
E5
K3
2
1
E4
46
K4
NOTE 1
53
47
D4
53X b
0.10
0.05
C A B
C
e
BOTTOM VIEW
Microchip Technology Drawing C04-1272 Rev B Sheet 1 of 2
DS20006256A-page 36
2019 Microchip Technology Inc.
MIC33M656
53-Lead Very Thick Plastic Quad Flat, No Lead Package (QDA) - 6x10x3.05 mm Body
[B1QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Length
N
53
0.50 BSC
3.00
e
A
2.95
0.00
3.05
0.05
A1
A3
D
D2
D3
D4
E
E2
E3
E4
E5
E6
K1
K2
K3
K4
K5
K6
b
0.02
0.203 REF
6.00 BSC
1.275
0.65
Exposed Pad Length
Exposed Pad Length
Exposed Pad Length
Overall Width
Exposed Pad Width
Exposed Pad Width
Exposed Pad Width
Exposed Pad Width
Exposed Pad Width
Package Edge to Exposed Pad
Package Edge to Exposed Pad
Exposed Pad to Exposed Pad
Exposed Pad to Exposed Pad
Exposed Pad to Exposed Pad
Exposed Pad to Exposed Pad
Terminal Width
1.225
0.60
0.55
1.325
0.70
0.65
0.60
10.00 BSC
4.525
1.625
0.50
0.65
6.623
0.90
4.475
1.575
0.45
0.60
6.573
0.85
0.85
1.90
0.45
0.45
0.45
0.20
0.45
4.575
1.675
0.55
0.70
6.673
0.95
0.95
2.00
0.55
0.55
0.55
0.30
0.55
0.90
1.95
0.50
0.50
0.50
0.25
0.50
Terminal Length
L
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-1272 Rev B Sheet 2 of 2
2019 Microchip Technology Inc.
DS20006256A-page 37
MIC33M656
53-Lead Very Thick Plastic Quad Flat, No Lead Package (QDA) - 6x10x3.05 mm Body
[B1QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
X4
G1
53
47
G2
1
2
46
G7
Y6
Y2
G3
ØV
Y5
C2
G4
Y4
Y3
G5
EV
19
28
Y1
20
27
G6
X1
SILK SCREEN
X3
E
Microchip Technology Drawing C04-3272 Rev B Sheet 1 of 2
DS20006256A-page 38
2019 Microchip Technology Inc.
MIC33M656
53-Lead Very Thick Plastic Quad Flat, No Lead Package (QDA) - 6x10x3.05 mm Body
[B1QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Contact Pitch
E
0.50 BSC
5.68
9.68
Contact Pad Spacing
Contact Pad Spacing
Contact Pad Width (X53)
C1
C2
X1
0.30
1.02
0.65
1.68
1.33
4.58
0.70
6.62
0.70
0.55
Contact Pad Length (X53)
Center Pad Width
Center Pad Length
Center Pad Width (X4)
Center Pad Length (X2)
Center Pad Width
Center Pad Length
Center Pad Length
Center Pad Length
Contact Pad to Center Pad (X2)
Contact Pad to Contact Pad (X48)
Contact Pad to Center Pad
Contact Pad to Center Pad
Contact Pad to Center Pad
Contact Pad to Center Pad
Contact Pad to Center Pad
Thermal Via Diameter
Thermal Via Pitch (X12)
Y1
X2
Y2
X3
Y3
X4
Y4
Y5
Y6
G1
G2
G3
G4
G5
G6
G7
V
0.45
0.20
0.45
0.45
0.20
0.20
0.30
0.33
1.20
EV
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
3. Thermal vias are centered within each exposed pad.
Microchip Technology Drawing C04-3272 Rev B Sheet 2 of 2
2019 Microchip Technology Inc.
DS20006256A-page 39
MIC33M656
NOTES:
DS20006256A-page 40
2019 Microchip Technology Inc.
MIC33M656
APPENDIX A: REVISION HISTORY
Revision A (September 2019)
• Initial release of this Data Sheet.
2019 Microchip Technology Inc.
DS20006256A-page 41
MIC33M656
NOTES:
DS20006256A-page 42
2019 Microchip Technology Inc.
MIC33M656
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
XX
X
PART NO.
Device
XX
Examples:
Package
Temperature
Range
Tape and Reel
Option
a) MIC33M656-FAYMP-TR: 0.9V Output, -40C to +125C
Temperature Range,
53-Lead B1QFN Package,
Tape and Reel
b) MIC33M656-HAYMP-TR: 1.0V Output, -40C to +125C
Temperature Range,
Device:
MIC33M656: 6A, Power Module Buck Converter with
HyperLight Load® and I2C Interface
53-Lead B1QFN Package,
Tape and Reel
c) MIC33M656-SAYMP-TR: 1.0V Output, -40C to +125C
Temperature Range,
Output Voltage FA = 0.9V
Option:
HA = 1.0V
53-Lead B1QFN Package,
Tape and Reel
SA = 1.0V, with 10 mV or 20 mV resolution
Junction
Temperature
Range:
Y
= -40C to +125C
Package:
MP = 53 Lead 6 mm x 10 mm x 3 mm Very Thick
Plastic Quad Flat, No Lead (B1QFN)
Note 1: Tape and Reel identifier only appears in the catalog
part number description. This identifier is used for
ordering purposes and is not printed on the device
package. Check with Microchip for package
Tape and Reel
Option:
TR = Tape and Reel(1)
availability with the Tape and Reel option.
2019 Microchip Technology Inc.
DS20006256A-page 43
MIC33M656
NOTES:
DS20006256A-page 44
2019 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-5073-3
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2019 Microchip Technology Inc.
DS20006256A-page 45
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
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Tel: 480-792-7200
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Technical Support:
http://www.microchip.com/
support
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Tel: 86-10-8569-7000
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DS20006256A-page 46
2019 Microchip Technology Inc.
05/14/19
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