MIC4606-1YTS-T5 [MICROCHIP]
IC GATE DRVR HALF-BRIDGE 16TSSOP;
| 型号： | MIC4606-1YTS-T5 |
| 厂家： | 
MICROCHIP |
| 描述： | IC GATE DRVR HALF-BRIDGE 16TSSOP 栅 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总40页 (文件大小：2588K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MIC4606
85V Full-Bridge MOSFET Drivers with Adaptive Dead Time and
Shoot-Through Protection
Features
General Description
• 5.5V to 16V Gate Drive Supply Voltage Range
• Advanced Adaptive Dead Time
• Intelligent Shoot-Through Protection
• MIC4606-1: 4 Independent TTL Inputs
• MIC4606-2: 2 PWM Inputs
The MIC4606 is an 85V full-bridge MOSFET driver that
features adaptive dead time and shoot-through
protection. The adaptive dead time circuitry actively
monitors both sides of the full-bridge to minimize the
time between high-side and low-side MOSFET
transitions, thus maximizing power efficiency. Anti
shoot-through circuitry prevents erroneous inputs and
noise from turning both MOSFETs of each side of the
bridge on at the same time.
• Enable Input for On/Off Control
• On-Chip Bootstrap Diodes
• Fast 35 ns Propagation Times
The MIC4606 also offers a wide 5.5V to 16V operating
supply range to maximize system efficiency. The low
5.5V operating voltage allows longer run times in
• Drives 1000 pF Load with 20 ns Rise and Fall
Times
• Low Power Consumption: 235 µA Total Quiescent
Current
battery-powered
applications. Additionally,
the
MIC4606’s adjustable gate drive sets the gate drive
voltage to VDD for optimal MOSFET RDS(ON), which
• Separate High- and Low-Side Undervoltage
Protection
minimizes power loss due to the MOSFET’s RDS(ON)
.
• –40°C to +125°C Junction Temperature Range
The MC4606-1 features four independent inputs while
the MIC4606-2 utilizes two PWM inputs, one for each
side of the H-bridge. The MIC4606-1 and MIC4606-2
are available in a 16-pin 4 mm x 4 mm QFN and a
16-pin 4 mm x 5 mm TSSOP package with an
operating temperature range of –40°C to +125°C.
Applications
• Full-Bridge Motor Drives
• Power Inverters
• High Voltage Step-Down Regulators
• Distributed Power Systems
• Stepper Motors
Typical Application Circuit
MIC4606
4x4 QFN
(12V Motor Drive Configuration)
12VDC
MIC5283
LDO
12V TO 3.3V
VDD
EN
AHB
J1
POWER
Q1
Q3
Q2
Q4
3.3VDC
MIC4606-1
FULL-BRIDGE
DRIVER
AHO
AHS
VDD
M
AHI
ALI
I/O
I/O
μC
DC MOTOR
12V 140mA
fS=20kHz
ALO
FWD
REV
I/O
I/O
BHI
BLI
I/O
I/O
VSS
BLO
VSS
BHS
BHB BHO
J2
COMMUNICATIONS
2018 Microchip Technology Inc.
DS20005604B-page 1
MIC4606
Package Types
MIC4606-1
16-Pin QFN
4 mm x 4 mm
MIC4606-2
16-Pin QFN
4 mm x 4 mm
NC
EN
1
2
12
11
NC
EN
1
2
12
11
AHB
BHB
AHB
BHB
AHO
AHS
BHO
BHS
3
4
10
9
AHO
AHS
BHO
BHS
3
4
10
9
EP
EP
MIC4606-1
16-pin TSSOP
4 mm x 5 mm
MIC4606-2
16-pin TSSOP
4 mm x 5 mm
1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BHB
BHO
BHB
EN
BPWM
NC
NC
APWM
NC
BHO
BHS
BLO
VSS
VDD
ALO
AHS
AHO
2
3
4
5
6
7
8
EN
BHI
BLI
ALI
AHI
NC
BHS
BLO
VSS
VDD
ALO
AHS
AHO
AHB
AHB
Note:
See Table 4-1 through Table 4-4 for pin descriptions.
DS20005604B-page 2
2018 Microchip Technology Inc.
MIC4606
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings † (Note 1)
Supply Voltage (VDD, VxHB – VxHS) ........................................................................................................... –0.3V to +18V
Input Voltage (VxLI, VxHI, VEN) ............................................................................................................–0.3V to VDD +0.3V
Voltage on xLO (VxLO) .......................................................................................................................–0.3V to VDD +0.3V
Voltage on xHO (VxHO) ..............................................................................................................VHS – 0.3V to VHB +0.3V
Voltage on xHS (Continuous)....................................................................................................................... –0.3V to 90V
Voltage on xHB .........................................................................................................................................................108V
Average Current in VDD to HB Diode................................................................................................................... 100 mA
ESD Protection On All Pins (Note 2)............................................................................................±1 kV HBM, ±200V MM
Operating Ratings ††
Supply Voltage (VDD) [decreasing VDD]................................................................................................... +5.25V to +16V
Supply Voltage (VDD) [increasing VDD] ...................................................................................................... +5.5V to +16V
Enable Voltage (VEN)........................................................................................................................................ 0V to VDD
Voltage on xHS .......................................................................................................................................... –0.3V to +85V
Voltage on xHS (100 ns repetitive transient).............................................................................................. –0.7V to +90V
HS Slew Rate........................................................................................................................................................50 V/ns
Voltage on xHB ............................................................................................................................................... VHS to VDD
and/or.................................................................................................................................. VDD –1V to VDD +85V
† Notice: Exceeding the absolute maximum ratings may damage the device.
†† Notice: The device is not guaranteed to function outside its operating ratings.
Note 1: “x” in front of a pin name refers to either A or B. (e.g. xHI can be either AHI or BHI).
2: Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5 kΩ in series
with 100 pF.
ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = VxHB = 12V; VEN = 5V; VSS = VxHS = 0V; No load on
xLO or xHO; TA = +25°C. Bold values indicate –40°C ≤ TJ ≤ +125°C. Note 1, Note 2.
Parameters
Symbol
Min.
Typ.
Max.
Units
Conditions
Supply Current
V
DD Quiescent Current
IDD
—
—
200
2.5
350
5
µA
µA
xLI = xHI = 0V
EN = 0V with xHS = floating;
VDD Shutdown Current
IDDSH
EN = 0V, xLI, xHI = 12V or
0V
—
—
—
40
0.35
35
100
0.5
75
VDD Operating Current
IDDO
IHB
fS = 20 kHz
mA
µA
Total xHB Quiescent
Current
xLI = xHI = 0V or xLI = 0V
and xHI =5V
Note 1: Specification for packaged product only.
2: x in front of a pin name refers to either A or B. (e.g. xHI can be either AHI or BHI).
3: VIL(MAX) = maximum positive voltage applied to the input which will be accepted by the device as a logic
low.
VIH(MIN) = minimum positive voltage applied to the input which will be accepted by the device as a logic
high.
4: xLI/xHI mode with inputs non-overlapping, assumes xHS low before xLI goes high and xLO low before xHI
goes high).
5: PWM mode (MIC4606-2) or LI/HI mode (MIC4606-1) with overlapping xLI/xHI inputs.
2018 Microchip Technology Inc.
DS20005604B-page 3
MIC4606
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, VDD = VxHB = 12V; VEN = 5V; VSS = VxHS = 0V; No load on
xLO or xHO; TA = +25°C. Bold values indicate –40°C ≤ TJ ≤ +125°C. Note 1, Note 2.
Parameters
Symbol
Min.
Typ.
Max.
400
Units
Conditions
fS = 20 kHz
xHS = VxHB = 90V
fS = 20 kHz
Total xHB Operating
Current
IHBO
—
30
μA
xHB to VSS Quiescent
Current
IHBS
—
—
0. 5
3
5
V
µA
µA
xHB to VSS Operating
Current
IHBSO
10
Input (TTL: xLI, xHI, EN) (Note 2, Note 3)
—
2.2
—
Low-Level Input Voltage
High-Level Input Voltage
Input Voltage Hysteresis
VIL
VIH
—
—
0.8
—
V
V
—
—
VHYS
0.1
300
150
—
V
—
100
50
500
250
kꢀ
kꢀ
xHI/xLI inputs
xPWM inputs
Input Pull-Down
Resistance
RI
Undervoltage Protection
—
—
—
—
V
DD Falling Threshold
VDDR
VDDH
VHBR
VHBH
4.0
4.4
0.25
4.4
4.9
V
V
V
V
VDD Threshold Hysteresis
—
—
xHB Falling Threshold
xHB Threshold Hysteresis
Bootstrap Diode
4.0
4.9
—
—
0.25
Low-Current Forward
Voltage
VDL
—
—
0.4
0.70
V
IVDD-xHB = 100 µA
High-Current Forward
Voltage
VDH
RD
0.7
3
1.0
5.0
V
IVDD-xHB = 50 mA
Dynamic Resistance
LO Gate Driver
—
ꢀ
IVDD-xHB = 50 mA
IxLO = 50 mA
Low-Level Output Voltage
VOLL
VOHL
—
—
0.3
0.5
0.6
1.0
V
V
IxLO = 50 mA,
VOHL = VDD - VxLO
High-Level Output Voltage
Peak Sink Current
IOHL
IOLL
—
—
1
1
—
—
A
A
VxLO = 0V
Peak Source Current
HO Gate Driver
VxLO = 12V
Low-Level Output Voltage
VOLH
—
0.3
0.6
V
IxHO = 50 mA
Note 1: Specification for packaged product only.
2: x in front of a pin name refers to either A or B. (e.g. xHI can be either AHI or BHI).
3: VIL(MAX) = maximum positive voltage applied to the input which will be accepted by the device as a logic
low.
VIH(MIN) = minimum positive voltage applied to the input which will be accepted by the device as a logic
high.
4: xLI/xHI mode with inputs non-overlapping, assumes xHS low before xLI goes high and xLO low before xHI
goes high).
5: PWM mode (MIC4606-2) or LI/HI mode (MIC4606-1) with overlapping xLI/xHI inputs.
DS20005604B-page 4
2018 Microchip Technology Inc.
MIC4606
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, VDD = VxHB = 12V; VEN = 5V; VSS = VxHS = 0V; No load on
xLO or xHO; TA = +25°C. Bold values indicate –40°C ≤ TJ ≤ +125°C. Note 1, Note 2.
Parameters
Symbol
Min.
Typ.
Max.
1.0
Units
Conditions
IxHO = 50 mA,
VOHH = VxHB - VxHO
VxHO = 0V
High-Level Output Voltage
VOHH
—
0.5
V
Peak Sink Current
IOHH
IOLH
—
—
1
1
—
—
A
A
Peak Source Current
VxLO = 12V
Switching Specifications (Note 4)
Lower Turn-Off
Propagation Delay
(xLI Falling to xLO Falling)
tLPHL
—
—
35
35
75
75
ns
ns
—
—
Upper Turn-Off
Propagation Delay
(xHI Falling to xHO
Falling)
tHPHL
Lower Turn-On
Propagation Delay
(xLI Rising to xLO Rising)
tLPLH
—
—
35
35
75
75
ns
ns
—
—
Upper Turn-On
Propagation Delay
(xHI Rising to xHO Rising)
tHPLH
tR/tF
tR/tF
Output Rise/Fall Time
—
—
20
—
—
ns
µs
CL = 1000 pF
CL = 0.1 µF
Output Rise/Fall Time (3V
to 9V)
0.8
Minimum Input Pulse
Width that Changes the
Output
tPW
—
50
—
ns
—
Switching Specifications (Note 5)
Delay from xPWM High
(or xLI Low) to xLO Low
tLOOFF
—
—
35
75
—
ns
V
—
—
xLO Output Voltage
Threshold for Low-Side
FET to be Considered Off
VLOOFF
1.9
Delay from xLO off to xHO
High
tHOON
—
—
35
35
75
75
ns
ns
—
—
Delay from xPWM Low (or
xHI Low) to xHO Low\
tHOOFF
Note 1: Specification for packaged product only.
2: x in front of a pin name refers to either A or B. (e.g. xHI can be either AHI or BHI).
3: VIL(MAX) = maximum positive voltage applied to the input which will be accepted by the device as a logic
low.
VIH(MIN) = minimum positive voltage applied to the input which will be accepted by the device as a logic
high.
4: xLI/xHI mode with inputs non-overlapping, assumes xHS low before xLI goes high and xLO low before xHI
goes high).
5: PWM mode (MIC4606-2) or LI/HI mode (MIC4606-1) with overlapping xLI/xHI inputs.
2018 Microchip Technology Inc.
DS20005604B-page 5
MIC4606
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, VDD = VxHB = 12V; VEN = 5V; VSS = VxHS = 0V; No load on
xLO or xHO; TA = +25°C. Bold values indicate –40°C ≤ TJ ≤ +125°C. Note 1, Note 2.
Parameters
Symbol
Min.
Typ.
Max.
Units
Conditions
Switch Node Voltage
Threshold Signaling xHO
is Off
VSWTH
1
2.2
4
V
—
—
Delay Between xHO FET
being considered Off to
xLO Turning On
tLOON
—
35
75
ns
For xHS Low/xLI High,
Delay from xPWM/xHI
Low to xLO High
tLOONHI
—
80
150
500
ns
ns
—
—
Force xLO On if VSWTH is
Not Detected
tSWTO
100
250
Note 1: Specification for packaged product only.
2: x in front of a pin name refers to either A or B. (e.g. xHI can be either AHI or BHI).
3: VIL(MAX) = maximum positive voltage applied to the input which will be accepted by the device as a logic
low.
VIH(MIN) = minimum positive voltage applied to the input which will be accepted by the device as a logic
high.
4: xLI/xHI mode with inputs non-overlapping, assumes xHS low before xLI goes high and xLO low before xHI
goes high).
5: PWM mode (MIC4606-2) or LI/HI mode (MIC4606-1) with overlapping xLI/xHI inputs.
DS20005604B-page 6
2018 Microchip Technology Inc.
MIC4606
TEMPERATURE SPECIFICATIONS (Note 1)
Parameters
Temperature Ranges
Sym.
Min.
Typ.
Max.
Units
Conditions
Storage Temperature Range
TS
TJ
–60
–40
—
—
+150
+125
°C
°C
—
—
Junction Operating Temperature
Package Thermal Resistances
Thermal Resistance, QFN-16Ld
Thermal Resistance, TSSOP-16Ld
JA
JA
—
—
51
—
—
°C/W
°C/W
—
—
97.5
Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable
junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the
maximum allowable power dissipation will cause the device operating junction temperature to exceed the
maximum +125°C rating. Sustained junction temperatures above +125°C can impact the device reliability.
2018 Microchip Technology Inc.
DS20005604B-page 7
MIC4606
2.0
2.1
TIMING DIAGRAMS
until xLI is pulled low (off) and xLO falls to < 1.9V. Delay
from xLI going low to xLO falling is tLOOFF and delay
Non-Overlapping LI/HI Input Mode
(MIC4606-1)
from xLO < 1.9V to xHO being on is tHOON
.
In LI/HI input mode, external xLI/xHI inputs are delayed
to the point that xHS is low before xLI is pulled high and
similarly xLO is low before xHI goes high
2.2V
(typ)
xHS
xHO goes high with a high signal on xHI after a typical
delay of 35 ns (tHPLH). xHI going low drives xHO low
also with typical delay of 35 ns (tHPHL).
tLOON
xHO
xLO
Likewise, xLI going high forces xLO high after typical
delay of 35 ns (tLPLH) and xLO follows low transition of
xLI after typical delay of 35 ns (tLPHL).
tHOON
tHOOFF
1.9V
(typ)
xHO and xLO output rise and fall times (tR/tF) are
typically 20 ns driving 1000 pF capacitive loads.
tLOOFF
All propagation delays are measured from the 50%
voltage level and rise/fall times are measured 10% to
90%.
xHI
xLI
xHS
FIGURE 2-2:
Separate Overlapping LI/HI
Input Mode (MIC4606-1).
tF
tR
xHO
xLO
xHI
2.3
PWM Input Mode (MIC4606-2)
tR
tF
A low xPWM signal applied to the MIC4606-2 causes
the xHO to go low, typically to 35 ns (tHOOFF) after the
xPWM input goes low. At this point, the switch node
xHS, falls (1-2).
tHPHL
tHPLH
tLPLH
tLPHL
When the xHS reaches 2.2V (VSWTH), the external
high-side MOSFET is deemed off and the xLO goes
high, typically within 35 ns (tLOON) (3-4). The xHS
falling below 2.2V sets a latch that can only be reset by
the xPWM going high. This design prevents ringing on
xHS from causing an indeterminate xLO state. Should
xHS never trip the aforementioned internal comparator
reference (2.2V), a falling xPWM edge delayed by
250 ns will set “HS latch” allowing xLO to go high. An
80 ns delay gated by xPWM going low may determine
the time to xLO going high for fast falling HS designs.
xPWM going high forces xLO low in typically 35 ns
(tLOOFF) (5-6).
xLI
FIGURE 2-1:
LI/HI Input Mode (MIC4606-1)
Separate Non-Overlapping
2.2
Overlapping LI/HI Input Mode
(MIC4606-1)
When xLI/xHI input high conditions overlap, xLO/xHO
output states are dominated by the first output to be
turned on. If xLI goes high (on) while xHO is high, xHO
stays high until xHI goes low. After a delay of tHOOFF
and when xHS < 2.2V, xLO goes high with a delay of
tLOON. If xHS never trip the aforementioned internal
comparator reference (2.2V), a falling xHI edge
delayed by a typical 250 ns will set “HS latch” allowing
xLO to go high.
When xLO reaches 1.9V (VLOOFF), the low-side
MOSFET is deemed off and xHO is allowed to go high.
The delay between these two points is typically 35 ns
(tHOON) (7-8).
xHO and xLO output rise and fall times (tR/tF) are
typically 20 ns driving 1000 pF capacitive loads.
Note: All propagation delays are measured from the
50% voltage level and rise/fall times are measured
10% to 90%.
If xHS falls very fast, xLO will be held low by a 35 ns
delay gated by HI going low. Conversely, xHI going
high (on) when xLO is high has no effect on outputs
DS20005604B-page 8
2018 Microchip Technology Inc.
MIC4606
tF
tR
2
xHO
xLO
tHOON
tR
4
6
7
(VLOOFF
)
tF
tLOOFF
tLOON
3
(VSWTH
)
xHS
1
5
xPWM
tHOOFF
FIGURE 2-3:
PWM Mode (MIC4606-2).
2018 Microchip Technology Inc.
DS20005604B-page 9
MIC4606
3.0
TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
80
275
250
225
200
175
150
125
FREQ = 20kHz
HS = 0V
HS = 0V
VHB = VDD
60
40
20
0
T = 25°C
T = 125°C
T = -40°C
T = 125°C
12
T = -40°C
T = 25°C
6
4
8
10
12
14
16
4
6
8
10
14
16
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 3-1:
V
Quiescent Current vs.
FIGURE 3-4:
V
Operating Current vs.
DD
HB
Input Voltage.
Input Voltage.
80
65
50
35
100
TAMB = 25°C
HS = 0V
80
60
40
20
0
T = -40°C
tHPHL
tLPHL
tLPLH
T = 25°C
tHPLH
T = 125°C
20
4
4
6
8
10
12
14
16
6
8
10
12
14
16
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 3-2:
Shutdown Current vs. Input
FIGURE 3-5:
Propagation Delay vs. Input
Voltage.
Voltage.
300
275
700
Freq = 20kHz
HS = 0V
600
500
400
300
200
100
0
VDD = 16V
250
225
200
175
150
125
100
T = 125°C
VDD = 12V
VDD = 5.5V
T = 25°C
T = -40°C
HS = 0V
-50
-25
0
25
50
75
100
125
4
6
8
10
12
14
16
TEMPERATURE (°C)
FIGURE 3-3:
V
Operating Current vs.
FIGURE 3-6:
V
Quiescent Current vs.
DD
DD
Input Voltage.
Temperature.
DS20005604B-page 10
2018 Microchip Technology Inc.
MIC4606
.
10
8
100
80
60
40
20
0
HS = 0V
ILO , IHO
HS = 0V
=
-50mA
VDD = 12V
VDD = 16V
VDD = 12V
VDD = 5.5V
6
4
VDD = 5.5V
VDD = 16V
2
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 3-7:
Shutdown Current vs.
FIGURE 3-10:
High Level Output
Temperature.
Resistance vs. Temperature.
10
700
FREQ = 20kHz
HS = 0V
HS = 0V
600
500
400
300
200
100
ILO , IHO
=
50mA
8
6
4
2
0
VDD = 16V
VDD = 12V
VDD = 5.5V
VDD = 12V
VDD = 16V
VDD = 5.5V
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 3-8:
V
Operating Current vs.
FIGURE 3-11:
Low Level Output
DD
Temperature.
Resistance vs. Temperature.
80
5
FREQ = 20kHz
HS = 0V
70
60
50
40
30
20
10
0
HS = 0V
4.8
4.6
4.4
4.2
4
VDD Rising
VHB = 16V
VHB Rising
VDD Falling
VHB Falling
VHB = 12V
VHB = 5.5V
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 3-9:
V
Operating Current vs.
FIGURE 3-12:
UVLO Thresholds vs.
HB
Temperature.
Temperature.
2018 Microchip Technology Inc.
DS20005604B-page 11
MIC4606
0.6
10
8
HS = 0V
VHB = VDD =12V
T = -40°C
HS = 0V
0.5
0.4
0.3
0.2
0.1
0
VHB Hysteresis
VDD Hysteresis
6
T = 25°C
4
T = 125°C
2
0
0
200
400
600
800
1000
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
FREQUENCY (kHz)
FIGURE 3-13:
UVLO Hysteresis vs.
FIGURE 3-16:
V
Operating Current vs.
DD
Temperature.
Frequency.
2.5
2
60
HS = 0V
MIC4606-1
VHB = VDD = 12V
VDD = VHB = 12V
HS = 0V
50
40
30
20
T = -40°C
tLPLH
1.5
1
tLPHL
T = 25°C
T = 125°C
tHPHL
0.5
tHPLH
0
0
200
400
600
800
1000
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
FREQUENCY (kHz)
FIGURE 3-17:
V
Operating Current vs.
FIGURE 3-14:
Propagation Delay vs.
HB
Frequency.
Temperature.
400
360
1000
MIC4606-2
HS = 0V
T = 25°C
VDD = VHB = 12V
HS = 0V
FORCE LO On
320
280
240
200
160
120
80
100
10
1
T = 125°C
T = -40°C
PWM to LO Low
PWM Low-to-LO High
40
PWM Low to HO Low
25 50 75 100
0.1
0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-50
-25
0
125
FORWARD VOLTAGE (V)
TEMPERATURE (°C)
FIGURE 3-18:
Characteristics.
Bootstrap Diode I–V
FIGURE 3-15:
Temperature.
Propagation Delay (PWM) vs.
DS20005604B-page 12
2018 Microchip Technology Inc.
MIC4606
100
10
HS = 0V
1
T = 125°C
0.1
T = 85°C
0.01
0.001
0.0001
T = 25°C
0
10 20 30 40 50 60 70 80 90 100
REVERSE VOLTAGE (V)
FIGURE 3-19:
Bootstrap Diode Reverse
Current.
2018 Microchip Technology Inc.
DS20005604B-page 13
MIC4606
4.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 4-1 through Table 4-4.
TABLE 4-1:
MIC4606-1 QFN PIN FUNCTION TABLE
MIC4606-1
Pin
Description
Number
4x4 QFN
1
NC
No Connect.
Phase A high-side bootstrap supply. An external bootstrap capacitor is required. Connect
the bootstrap capacitor between this pin and AHS. An on-chip bootstrap diode is
connected from VDD to AHB.
2
AHB
3
4
AHO
AHS
Phase A high-side drive output. Connect to the external high-side power MOSFET gate.
Phase A high-side drive reference connection. Connect to the external high-side power
MOSFET source terminal. Connect a bootstrap capacitor between this pin and AHB.
5
6
7
8
ALO
VDD
VSS
BLO
Phase A low-side drive output. Connect to the external low-side power MOSFET gate.
Input supply for gate drivers. Decouple this pin to VSS with a >1.0 µF capacitor.
Driver reference supply input. Connect to the power ground of the external circuitry.
Phase B low-side drive output. Connect to the external low-side power MOSFET gate.
Phase B high-side drive reference connection. Connect to the external high-side power
MOSFET source terminal. Connect a bootstrap capacitor between this pin and BHB.
9
BHS
BHO
10
Phase B high-side drive output. Connect to the external high-side power MOSFET gate.
Phase B high-side bootstrap supply. An external bootstrap capacitor is required. Connect
the bootstrap capacitor between this pin and BHS. An on-chip bootstrap diode is
connected from VDD to BHB.
11
12
BHB
EN
Enable input. A logic high on the enable pin results in normal operation. A logic low
disables all outputs and places the driver into a low current shutdown mode. Do not leave
this pin floating.
13
14
15
16
BHI
BLI
ALI
AHI
Phase B high-side drive input.
Phase B low-side drive input.
Phase A low-side drive input.
Phase A high-side drive input.
Exposed thermal pad. Connect to VSS. A connection to the ground plane is necessary for
optimum thermal performance.
EP
ePad
DS20005604B-page 14
2018 Microchip Technology Inc.
MIC4606
TABLE 4-2:
MIC4606-2 QFN PIN FUNCTION TABLE
MIC4606-2
Pin
Description
Number
4x4 QFN
1
NC
No Connect.
Phase A high-side bootstrap supply. An external bootstrap capacitor is required. Connect
the bootstrap capacitor between this pin and AHS. An on-chip bootstrap diode is
connected from VDD to AHB.
2
AHB
3
4
AHO
AHS
Phase A high-side drive output. Connect to the external high-side power MOSFET gate.
Phase A high-side drive reference connection. Connect to the external high-side power
MOSFET source terminal. Connect a bootstrap capacitor between this pin and AHB.
5
6
7
8
ALO
VDD
VSS
BLO
Phase A low-side drive output. Connect to the external low-side power MOSFET gate.
Input supply for gate drivers. Decouple this pin to VSS with a >1.0 µF capacitor.
Driver reference supply input. Connect to the power ground of the external circuitry.
Phase B low-side drive output. Connect to the external low-side power MOSFET gate.
Phase B high-side drive reference connection. Connect to the external high-side power
MOSFET source terminal. Connect a bootstrap capacitor between this pin and BHB.
9
BHS
BHO
10
Phase B high-side drive output. Connect to the external high-side power MOSFET gate.
Phase B high-side bootstrap supply. An external bootstrap capacitor is required. Connect
the bootstrap capacitor between this pin and BHS. An on-chip bootstrap diode is
connected from VDD to BHB.
11
12
BHB
EN
Enable input. A logic high on the enable pin results in normal operation. A logic low
disables all outputs and places the driver into a low current shutdown mode. Do not leave
this pin floating.
13
14
15
16
BPWM
NC
Phase B PWM input for single input signal drive.
No connect.
NC
No connect.
APWM
Phase A PWM input for single input signal drive.
Exposed thermal pad. Connect to VSS. A connection to the ground plane is necessary for
optimum thermal performance.
EP
ePad
2018 Microchip Technology Inc.
DS20005604B-page 15
MIC4606
TABLE 4-3:
Pin
MIC4606-1 TSSOP PIN FUNCTION TABLE
MIC4606-1
Description
Number 4x4 TSSOP
Phase B high-side bootstrap supply. An external bootstrap capacitor is required. Connect
the bootstrap capacitor between this pin and BHS. An on-chip bootstrap diode is
connected from VDD to BHB.
1
2
BHB
EN
Enable input. A logic high on the enable pin results in normal operation. A logic low
disables all outputs and places the driver into a low current shutdown mode. Do not leave
this pin floating.
3
4
5
6
7
BHI
BLI
ALI
AHI
NC
Phase B high-side drive input.
Phase B low-side drive input.
Phase A low-side drive input.
Phase A high-side drive input.
No Connect.
Phase A high-side bootstrap supply. An external bootstrap capacitor is required. Connect
the bootstrap capacitor between this pin and AHS. An on-chip bootstrap diode is
connected from VDD to AHB.
8
AHB
9
AHO
AHS
Phase A high-side drive output. Connect to the external high-side power MOSFET gate.
Phase A high-side drive reference connection. Connect to the external high-side power
MOSFET source terminal. Connect a bootstrap capacitor between this pin and AHB.
10
11
12
13
14
ALO
VDD
VSS
BLO
Phase A low-side drive output. Connect to the external low-side power MOSFET gate.
Input supply for gate drivers. Decouple this pin to VSS with a >1.0 µF capacitor.
Driver reference supply input. Connect to the power ground of the external circuitry.
Phase B low-side drive output. Connect to the external low-side power MOSFET gate.
Phase B high-side drive reference connection. Connect to the external high-side power
MOSFET source terminal. Connect a bootstrap capacitor between this pin and BHB.
15
16
BHS
BHO
Phase B high-side drive output. Connect to the external high-side power MOSFET gate.
DS20005604B-page 16
2018 Microchip Technology Inc.
MIC4606
TABLE 4-4:
Pin
MIC4606-2 TSSOP PIN FUNCTION TABLE
MIC4606-2
Description
Number 4x4 TSSOP
Phase B high-side bootstrap supply. An external bootstrap capacitor is required. Connect
the bootstrap capacitor between this pin and BHS. An on-chip bootstrap diode is
connected from VDD to BHB.
1
2
BHB
EN
Enable input. A logic high on the enable pin results in normal operation. A logic low
disables all outputs and places the driver into a low current shutdown mode. Do not leave
this pin floating.
3
4
5
6
7
BPWM
NC
Phase B PWM input for single input signal drive.
No connect.
NC
No connect.
APWM
NC
Phase A PWM input for single input signal drive.
No Connect.
Phase A high-side bootstrap supply. An external bootstrap capacitor is required. Connect
the bootstrap capacitor between this pin and AHS. An on-chip bootstrap diode is
connected from VDD to AHB.
8
AHB
9
AHO
AHS
Phase A high-side drive output. Connect to the external high-side power MOSFET gate.
Phase A high-side drive reference connection. Connect to the external high-side power
MOSFET source terminal. Connect a bootstrap capacitor between this pin and AHB.
10
11
12
13
14
ALO
VDD
VSS
BLO
Phase A low-side drive output. Connect to the external low-side power MOSFET gate.
Input supply for gate drivers. Decouple this pin to VSS with a >1.0 µF capacitor.
Driver reference supply input. Connect to the power ground of the external circuitry.
Phase B low-side drive output. Connect to the external low-side power MOSFET gate.
Phase B high-side drive reference connection. Connect to the external high-side power
MOSFET source terminal. Connect a bootstrap capacitor between this pin and BHB.
15
16
BHS
BHO
Phase B high-side drive output. Connect to the external high-side power MOSFET gate.
2018 Microchip Technology Inc.
DS20005604B-page 17
MIC4606
The latch is set by the quicker of either the falling edge
of xHS or xLI gated delay of 250 ns. The latch is
present to lockout xLO bounce due to ringing on xHS.
If xHS never adequately falls due to the absence of or
the presence of a very weak external pull-down on
xHS, the gated delay of 250 ns at xLI will set the latch
allowing xLO to transition high. This in turn allows the
xLI startup pulse to charge the bootstrap capacitor if the
load inductor current is very low and xHS is
uncontrolled. The latch is reset by the xLI falling edge.
5.0
FUNCTIONAL DIAGRAM
For xHO to be high, the xHI must be high and the xLO
must be low. xHO going high is delayed by xLO falling
below 1.9V. The xHI and xLI inputs must not rise at the
same time to prevent a glitch from occurring on the
output. A minimum 50 ns delay between both inputs is
recommended.
xLO is turned off very quickly on the xLI falling edge.
xLO going high is delayed by the longer of 35 ns delay
of xHO control signal going “off” or the RS latch being
set.
There is one external enable pin that controls both
phases.
VDD
xHB
*COMMON TO
BOTH PHASES
*
BIAS
REF
VDD
UVLO
HB
UVLO
xHO
EN
LEVEL
SHIFT
xHS
xLO
OR
-2
ONLY
EDGE
-1 HI
INPUT
LOGIC
(SEE DIAGRAM
BELOW)
S
R
-2 PWM
_
Q
-1 LI
-2 NC
-1
ONLY
FIGURE 5-1:
MIC4606 xPhase Top Level Block Diagram.
Æ HO
SECTION
AND INPUT
1.9V
LO
35ns
DELAY
HI
LI
R
Æ LO
SECTION
FF RESET
_
Q
250ns
DELAY
S
2.2V
HS
FIGURE 5-2:
Input Logic Block in Figure 5-1.
DS20005604B-page 18
2018 Microchip Technology Inc.
MIC4606
A high level applied to xLI pin causes VDD to be applied
to the gate of the external MOSFET. A low level on the
xLI pin grounds the gate of the external MOSFET.
6.0
FUNCTIONAL DESCRIPTION
The MIC4606 is a non-inverting, 85V full-bridge
MOSFET driver designed to independently drive all
four N-Channel MOSFETs in the bridge. The MIC4606
offers a wide 5.5V to 16V operating supply range with
either four independent TTL inputs (MIC4606-1) or two
PWM inputs, one for each phase (MIC4606-2). Refer to
Figure 5-1.
VDD
EXTERNAL
The drivers contain input buffers with hysteresis, three
independent UVLO circuits (two high side and one low
side), and four output drivers. The high-side output
drivers utilize a high-speed level-shifting circuit that is
referenced to its HS pin. Each phase has an internal
diode that is used by the bootstrap circuits to provide
the drive voltages for each of the two high-side outputs.
FET
LO
MIC4606
VSS
6.1
Startup and UVLO
The UVLO circuits force the driver’s outputs low until
the supply voltage exceeds the UVLO threshold. The
low-side UVLO circuit monitors the voltage between
the VDD and VSS pins. The high-side UVLO circuits
monitor the voltage between the xHB and xHS pins.
Hysteresis in the UVLO circuits prevent noise and finite
circuit impedance from causing chatter during turn-on.
FIGURE 6-1:
Diagram.
Low-Side Driver Block
6.5
High-Side Driver and Bootstrap
Circuit
6.2
Enable Inputs
A block diagram of the high-side driver and bootstrap
circuit is shown in Figure 6-2. This driver is designed to
drive a floating N-channel MOSFET, whose source
terminal is referenced to the HS pin.
There is one external enable pin that controls both
phases. A logic high on the enable pin (EN) allows for
startup of both phases and normal operation.
Conversely, when a logic low is applied on the enable
pin, both phases turn-off and the device enters a low
current shutdown mode. All outputs (xHO and xLO) are
pulled low when EN is low. Do not leave the EN pin
floating.
xHB
VDD
EXTERNAL
FET
CB
6.3
Input Stage
xHO
LEVEL
SHIFT
All input pins (xLI and xHI) are referenced to the VSS
pin. The MIC4606 has a TTL-compatible input range
and can be used with input signals with amplitude less
than the supply voltage. The threshold level is
independent of the VDD supply voltage and there is no
dependence between IVDD and the input signal
amplitude. This feature makes the MIC4606 an
excellent level translator that will drive high level gate
threshold MOSFETs from a low-voltage PWM IC.
MIC4606
xHS
FIGURE 6-2:
Bootstrap Circuit Block Diagram.
High-Side Driver and
A low-power, high-speed, level-shifting circuit isolates
the low side (VSS pin) referenced circuitry from the
high-side (xHS pin) referenced driver. Power to the
high-side driver and UVLO circuit is supplied by the
bootstrap capacitor (CB) while the voltage level of the
xHS pin is shifted high.
6.4
Low-Side Driver
A block diagram of the low-side driver is shown in
Figure 6-1. It drives a ground (VSS pin) referenced
N-channel MOSFET.
Low impedances in the driver allow the external
MOSFET to be turned on and off quickly. The rail-to-rail
drive capability of the output ensures high noise
immunity and a low RDS(ON) from the external
MOSFET.
The bootstrap circuit consists of an internal diode and
external capacitor, CB. In a typical application, such as
the motor driver shown in Figure 6-3 (only Phase A
illustrated), the AHS pin is at ground potential while the
2018 Microchip Technology Inc.
DS20005604B-page 19
MIC4606
low-side MOSFET is on. The internal diode allows
capacitor CB to charge up to VDD – VF during this time
(where VF is the forward voltage drop of the internal
diode). After the low-side MOSFET is turned off and the
AHO pin turns on, the voltage across capacitor CB is
applied to the gate of the high-side external MOSFET.
As the high-side MOSFET turns on, voltage on the
AHS pin rises with the source of the high-side MOSFET
until it reaches VIN. As the AHS and AHB pins rise, the
internal diode is reverse biased, preventing capacitor
CB from discharging.
VIN
CB
AHB
VDD
CVDD
AHI
Q1
AHO
LEVEL
SHIFT
M
PHASE
A
PHASE
B
AHS
ALO
ALI
Q2
PHASE A
MIC4606
VSS
FIGURE 6-3:
MIC4606 Motor Driver Example.
6.6
Programmable Gate Drive
1.1E-02
1E-02
The MIC4606 offers programmable gate drive, which
means the MOSFET gate drive (gate-to-source
voltage) equals the VDD voltage. This feature offers
designers flexibility in driving the MOSFETs. Different
MOSFETs require different VGS characteristics for
optimum RDS(ON) performance. Typically, the higher
the gate voltage (up to 16V), the lower the RDS(ON)
achieved. For example, a NTMSF4899NF MOSFET
can be driven to the ON state with a gate voltage of
5.5V but RDS(ON) is 5.2 mꢀ. If driven to 10V, RDS(ON) is
4.1 mꢀ—a decrease of 20%. In low-current
applications, the losses due to RDS(ON) are minimal,
but in battery-powered high-current motor drive
applications such as power tools, the difference in
RDS(ON) can cut into the efficiency budget, reducing run
time.
ID = 30A
TJ = 25°C
9E-03
8E-03
7E-03
6E-03
5E-03
4E-03
3E-03
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
VGS, GATE-TO-SOURCE VOLTAGE (V)
FIGURE 6-4:
MOSFET R
vs. V
.
GS
DS(ON)
DS20005604B-page 20
2018 Microchip Technology Inc.
MIC4606
7.0
7.1
APPLICATION INFORMATION
Adaptive Dead Time
EXTERNAL
FET
xHB
VDD
The door lock/unlock circuit diagram shown in
Figure 7-2 is used to illustrate the importance of the
adaptive dead time feature of the MIC4606. For each
phase, it is important that both MOSFETs are not
conducting at the same time or VIN will be shorted to
ground and current will “shoot through” the MOSFETs.
Excessive shoot-through causes higher power
dissipation in the MOSFETs, voltage spikes and
ringing. The high switching current and voltage ringing
generate conducted and radiated EMI.
CGD
RON
CB
xHO
RG
RG_FET
CGS
ROFF
MIC4606
xHS
Minimizing shoot-through can be done passively,
actively or through a combination of both. Passive
shoot-through protection can be achieved by
implementing delays between the high and low gate
drivers to prevent both MOSFETs from being on at the
same time. These delays can be adjusted for different
applications. Although simple, the disadvantage of this
approach is that it requires long delays to account for
process and temperature variations in the MOSFET
and MOSFET driver.
FIGURE 7-1:
External MOSFET.
MIC4606 Driving an
The internal gate resistance (RG_FET) and any external
damping resistor (RG) isolate the MOSFET’s gate from
the driver output. There is a delay between when the
driver output goes low and the MOSFET turns off. This
turn-off delay is usually specified in the MOSFET data
sheet. This delay increases when an external damping
resistor is used.
Adaptive dead time monitors voltages on the gate drive
outputs and switch node to determine when to switch
the MOSFETs on and off. This active approach adjusts
the delays to account for some of the variations, but it
too has its disadvantages. High currents and fast
switching voltages in the gate drive and return paths
can cause parasitic ringing to turn the MOSFETs back
on even while the gate driver output is low. Another
disadvantage is that the driver cannot monitor the gate
voltage inside the MOSFET. Figure 7-1 shows an
equivalent circuit of the high-side gate drive, including
parasitic.
12VDC
2.2μF
1μF
16V
MIC5283
LDO
VDD
12V TO 3.3V
EN
AHB
J1
POWER
Q1
Q2
3.3VDC
1μF
1μF
2.2μF
10V
MIC4606-1
FULL-BRIDGE
DRIVER
AHO
AHS
VDD
M
AHI
ALI
I/O
I/O
μC
DC MOTOR
12V 140mA
fS=20kHz
ALO
Unlock
Lock
I/O
I/O
BHI
BLI
I/O
I/O
VSS
BLO
VSS
BHS
BHB BHO
J2
COMMUNICATIONS
FIGURE 7-2:
Door Lock/Unlock Circuit.
2018 Microchip Technology Inc.
DS20005604B-page 21
MIC4606
Care must be taken to ensure that the input signal
pulse width is greater than the minimum specified pulse
width. An input signal that is less than the minimum
pulse width may result in no output pulse or an output
pulse whose width is significantly less than the input.
Æ HO
SECTION
AND INPUT
1.9V
LO
35ns
DELAY
HI
LI
The maximum duty cycle (ratio of high side on-time to
switching period) is determined by the time required for
the CB capacitor to charge during the off-time.
Adequate time must be allowed for the CB capacitor to
charge up before the high-side driver is turned back on.
R
S
Æ LO
SECTION
FF RESET
250ns
_
Q
DELAY
2.2V
HS
FIGURE 7-3:
Diagram.
Adaptive Dead-Time Logic
Although the adaptive dead time circuit in the MIC4606
prevents the driver from turning both MOSFETs on at
the same time, other factors outside of the anti
The MIC4606 uses a combination of active sensing
and passive delay to ensure that both MOSFETs are
not on at the same time. Figure 7-3 illustrates how the
adaptive dead time circuitry works.
shoot-through
circuit’s
control
can
cause
shoot-through. Other factors include ringing on the gate
drive node and capacitive coupling of the switching
node voltage on the gate of the low-side MOSFET.
For the MIC4606-2, a high level on the xPWM pin
causes /HI to go high and /LI to go low. This causes the
xLO pin to go low. The MIC4606 monitors the xLO pin
voltage and prevents the xHO pin from turning on until
the voltage on the xLO pin reaches the VLOOFF
threshold. After a short delay, the MIC4606 drives the
xHO pin high. Monitoring the xLO voltage eliminates
any excessive delay due to the MOSFET drivers
turn-off time and the short delay accounts for the
MOSFET turn-off delay as well as letting the xLO pin
voltage settle out. An external resistor between the xLO
output and the MOSFET may affect the performance of
the xLO pin monitoring circuit and is not recommended.
The scope photo in Figure 7-4 shows the dead time
(<20 ns) between the high and low-side MOSFET
transitions as the low-side driver switches off while the
high-side driver transitions from off to on.
A low on the xPWM pin causes /HI to go low and /LI to
go high. This causes the xHO pin to go low after a short
delay (tHOOFF). Before the xLO pin can go high, the
voltage on the switching node (xHS pin) must have
dropped to 2.2V. Monitoring the switch voltage instead
of the xHO pin voltage eliminates timing variations and
excessive delays due to the high side MOSFET
turn-off. The xLO driver turns on after a short delay
(tLOON). Once the xLO driver is turned on, it is latched
on until the xPWM signal goes high. This prevents any
ringing or oscillations on the switch node or xHS pin
from turning off the xLO driver. If the xPWM pin goes
low and the voltage on the xHS pin does not cross the
VSWTH threshold, the xLO pin will be forced high after
a short delay (tSWTO), insuring proper operation.
FIGURE 7-4:
(low) to HO (high).
Adaptive Dead Time LO
Table 7-1 contains truth tables for the MIC4606-1
(Independent TTL inputs) and Table 7-2 is for the
MIC4606-2 (PWM inputs) that details the “first on”
priority as well as the failsafe delay (tSWTO).
The internal logic circuits also insure a “first on” priority
at the inputs. If the xHO output is high, the xLI pin is
inhibited. A high signal or noise glitch on the xLI pin has
no effect on the xHO or xLO outputs until the xHI pin
goes low. Similarly, the xLO being high holds xHO low
until xLI and xLO are low.
TABLE 7-1:
MIC4606-1 TRUTH TABLE
xLI xHI xLO xHO
Comments
0
0
0
1
0
0
0
1
Both outputs off.
xHO will not go high until
xLO falls below 1.9V.
Fast propagation delay between the input and output
drive waveform is desirable. It improves overcurrent
protection by decreasing the response time between
the control signal and the MOSFET gate drive.
Minimizing propagation delay also minimizes phase
shift errors in power supplies with wide bandwidth
control loops.
xLO will be delayed an
extra 250 ns if xHS never
falls below 2.2V.
1
1
0
1
1
0
First ON stays on until
input of same goes low.
X
X
DS20005604B-page 22
2018 Microchip Technology Inc.
MIC4606
TABLE 7-2:
xPWM xLO
MIC4606-2 TRUTH TABLE
VIN
xHO
Comments
CB
VDD
DBST
AHB
CVDD
xLO will be delayed an
extra 250 ns if xHS never
falls below 2.2V.
RG
AHO
AHS
AHI
ALI
Level
0
1
1
0
0
Shift
RHS
VNEG
ꢀȍ
Phase
A
DCLAMP
xHO will not go high until
xLO falls below 1.9V.
1
ALO
M
RG
Phase
B
7.2
HS Pin Clamp
MIC4606
VSS
A resistor/diode clamp between the motor phase node
and the xHS pin is necessary to clamp large negative
glitches or pulses on the xHS pin.
FIGURE 7-5:
Negative HS Pin Voltage.
Figure 7-5 shows the Phase A section high-side and
low-side MOSFETs connected to one phase of the
motor. There is a brief period of time (dead time)
between switching to prevent both MOSFETs from
being on at the same time. When the high-side
MOSFET is conducting during the on-time state,
current flows into the motor. After the high-side
MOSFET turns off, but before the low-side MOSFET
turns on, current from the motor flows through the body
diode in parallel with the low-side MOSFET. Depending
upon the turn-on time of the body diode, the motor
current, and circuit parasitics, the initial negative
voltage on the switch node can be several volts or
more. The forward voltage drop of the body diode can
be several volts, depending on the body diode
characteristics and motor current.
7.3
Power Dissipation Considerations
Power dissipation in the driver can be separated into
three areas:
• Internal diode dissipation in the bootstrap circuit
• Internal driver dissipation
• Quiescent current dissipation used to supply the
internal logic and control functions.
7.4
Bootstrap Circuit Power
Dissipation
Power dissipation of the internal bootstrap diode
primarily comes from the average charging current of
the bootstrap capacitor (CB) multiplied by the forward
voltage drop of the diode. Secondary sources of diode
power dissipation are the reverse leakage current and
reverse recovery effects of the diode.
Even though the xHS pins are rated for negative
voltage, it is good practice to clamp the negative
voltage on the xHS pin with a resistor and diode to
prevent excessive negative voltage from damaging the
driver. Depending upon the application and amount of
negative voltage on the switch node, a 3ꢀ resistor is
recommended. If the xHS pin voltage exceeds 0.7V, a
diode between the xHS pin and ground is
recommended. The diode reverse voltage rating must
be greater than the high-voltage input supply (VIN).
Larger values of resistance can be used if necessary.
The average current drawn by repeated charging of the
high-side MOSFET is calculated by:
EQUATION 7-1:
IFAVE = QGATE fS
Adding a series resistor in the switch node limits the
peak high-side driver current during turn-off, which
affects the switching speed of the high-side driver. The
resistor in series with the HO pin may be reduced to
help compensate for the extra HS pin resistance.
Where:
QGATE Total gate charge at VHB
fS
Gate drive switching frequency
The average power dissipated by the forward voltage
drop of the diode equals:
EQUATION 7-2:
PDIODEfwd = IFAVE VF
Where:
VF
Diode forward voltage drop
2018 Microchip Technology Inc.
DS20005604B-page 23
MIC4606
There are two phases in the MIC4606. The power
dissipation for each of the bootstrap diodes must be
calculated and summed to obtain the total bootstrap
diode power dissipation for the package.
EXTERNAL
DIODE
CB
VIN
The value of VF should be taken at the peak current
through the diode; however, this current is difficult to
calculate because of differences in source
impedances. The peak current can either be measured
or the value of VF at the average current can be used,
which will yield a good approximation of diode power
dissipation.
xHB
VDD
xHO
HI
LI
LEVEL
SHIFT
xHS
xLO
The reverse leakage current of the internal bootstrap
diode is typically 3 µA at a reverse voltage of 85V at
125°C. Power dissipation due to reverse leakage is
typically much less than 1 mW and can be ignored.
An optional external bootstrap diode may be used
instead of the internal diode (Figure 7-6). An external
diode may be useful if high gate charge MOSFETs are
being driven and the power dissipation of the internal
diode is contributing to excessive die temperatures.
The voltage drop of the external diode must be less
than the internal diode for this option to work. The
reverse voltage across the diode will be equal to the
input voltage minus the VDD supply voltage. The above
equations can be used to calculate power dissipation in
the external diode; however, if the external diode has
significant reverse leakage current, the power
dissipated in that diode due to reverse leakage can be
calculated as:
MIC4606
VSS
FIGURE 7-6:
Optional Bootstrap Diode.
7.5
Gate Driver Power Dissipation
Power dissipation in the output driver stage is mainly
caused by charging and discharging the gate to source
and gate to drain capacitance of the external MOSFET.
Figure 7-7 shows a simplified equivalent circuit of the
MIC4606 driving an external high-side MOSFET.
EQUATION 7-3:
EXTERNAL
FET
xHB
VDD
PDIODErev = IR VREV 1 – D
CGD
RON
Where:
CB
xHO
RG
IR
VREV Diode reverse voltage
Duty cycle (tON x fS)
Reverse current flow at VREV and TJ
RG_FET
CGS
ROFF
D
MIC4606
The on-time is the time the high-side switch is
conducting. In most topologies, the diode is reverse
biased during the switching cycle off-time.
xHS
FIGURE 7-7:
MIC4606 Driving an
External High-Side MOSFET.
DS20005604B-page 24
2018 Microchip Technology Inc.
MIC4606
7.6
Dissipation During the External
MOSFET Turn-On
Energy from capacitor CB is used to charge up the input
capacitance of the MOSFET (CGD and CGS). The
energy delivered to the MOSFET is dissipated in the
three resistive components, RON, RG and RG_FET. RON
is the on resistance of the upper driver MOSFET in the
MIC4606. RG is the series resistor (if any) between the
driver and the MOSFET. RG_FET is the gate resistance
of the MOSFET. RG_FET is usually listed in the power
MOSFET’s specifications. The ESR of capacitor CB
and the resistance of the connecting etch can be
ignored since they are much less than RON and
RG_FET
.
The effective capacitances of CGD and CGS are difficult
to calculate because they vary non-linearly with ID,
VGS, and VDS. Fortunately, most power MOSFET
specifications include a typical graph of total gate
charge versus VGS. Figure 7-8 shows a typical gate
charge curve for an arbitrary power MOSFET. This
chart shows that for a gate voltage of 10V, the
MOSFET requires about 23.5 nC of charge. The
energy dissipated by the resistive components of the
gate drive circuit during turn-on is calculated as:
QG - TOTAL GATE CHARGE (nC)
FIGURE 7-8:
Typical Gate Charge vs.
V
.
GS
The same energy is dissipated by ROFF, RG, and
RG_FET when the driver IC turns the MOSFET off.
Assuming RON is approximately equal to ROFF, the total
energy and power dissipated by the resistive drive
elements is:
EQUATION 7-4:
EQUATION 7-7:
1
2
2
--
E = CISS VGS
EDRIVER = QG VGS
Where:
Where:
CISS Total gate capacitance of the MOSFET
EDRIVER Energy dissipated per switching
cycle
but
EQUATION 7-5:
and
EQUATION 7-8:
Q = C V
PDRIVER = QG VGS fS
Where:
so
PDRIVER Power dissipated per switching
cycle
EQUATION 7-6:
QG
Total gate charge at VGS
VGS
Gate-to-source voltage on the
MOSFET
1
2
--
E = QG VGS
fS
Switching frequency of the gate
drive circuit
The power dissipated in the driver equals the ratio of
RON and ROFF to the external resistive losses in RG
and RG_FET. Letting RON = ROFF, the power dissipated
in the driver due to driving the external MOSFET is:
2018 Microchip Technology Inc.
DS20005604B-page 25
MIC4606
EQUATION 7-9:
EQUATION 7-11:
RON
Pdisstotal = Pdisssupply + Pdissdrive + PDIODE
------------------------------------------------
RON + RG + RG_FET
Pdissdriver = PDRIVER
There are four MOSFETs driven by the MIC4606. The
power dissipation for each of the drivers must be
calculated and summed to obtain the total driver diode
power dissipation for the package.
The die temperature can be calculated after the total
power dissipation is known.
EQUATION 7-12:
In some cases, the high-side FET of one phase may be
pulsed at a frequency, fS, while the low-side FET of the
other phase is kept continuously on. since the
MOSFET gate is capacitive, there is no driver power if
the FET is not switched. The operation of each of the
four drivers must be considered to accurately calculate
power dissipation.
TJ = TA + PDISStotal JA
Where:
TA
TJ
Maximum ambient temperature
Junction temperature
PDISStotal Total power dissipation
θJA Thermal resistance from junction to
ambient air
7.7
Supply Current Power Dissipation
Power is dissipated in the input and control sections of
the MIC4606, even if there is no external load. Current
is still drawn from the VDD and HB pins for the internal
circuitry, the level shifting circuitry, and shoot-through
current in the output drivers. The VDD and HB currents
are proportional to operating frequency and the VDD
and VHB voltages. The typical characteristic graphs
show how supply current varies with switching
frequency and supply voltage.
7.9
Other Timing Considerations
Make sure the input signal pulse width is greater than
the minimum specified pulse width. An input signal that
is less than the minimum pulse width may result in no
output pulse or an output pulse whose width is
significantly less than the input.
The power dissipated by the MIC4606 due to supply
current is:
The maximum duty cycle (ratio of high side on-time to
switching period) is controlled by the minimum pulse
width of the low side and by the time required for the CB
capacitor to charge during the off-time. Adequate time
must be allowed for the CB capacitor to charge up
before the high-side driver is turned on.
EQUATION 7-10:
Pdisssupply = VDD IDD + VHB IHB
7.10 Decoupling and Bootstrap
Capacitor Selection
Decoupling capacitors are required for both the low
side (VDD) and high side (HB) supply pins. These
capacitors supply the charge necessary to drive the
external MOSFETs and also minimize the voltage
ripple on these pins. The capacitor from HB to HS has
two functions: it provides decoupling for the high-side
circuitry and also provides current to the high-side
circuit while the high-side external MOSFET is on.
Ceramic capacitors are recommended because of their
low impedance and small size. Z5U type ceramic
capacitor dielectrics are not recommended because of
the large change in capacitance over temperature and
voltage. A minimum value of 0.1 µF is required for CB
(HB to HS capacitors) and 1 µF for the VDD capacitor,
regardless of the MOSFETs being driven. Larger
MOSFETs may require larger capacitance values for
proper operation. The voltage rating of the capacitors
Values for IDD and IHB are found in the Electrical
Characteristics tables and the Typical Performance
Curves graphs.
7.8
Total Power Dissipation and
Thermal Considerations
Total power dissipation in the MIC4606 is equal to the
power dissipation caused by driving the external
MOSFETs, the supply currents and the internal
bootstrap diodes.
DS20005604B-page 26
2018 Microchip Technology Inc.
MIC4606
depends on the supply voltage, ambient temperature
and the voltage derating used for reliability. 25V rated
X5R or X7R ceramic capacitors are recommended for
most applications. The minimum capacitance value
should be increased if low voltage capacitors are used
because even good quality dielectric capacitors, such
as X5R, will lose 40% to 70% of their capacitance value
at the rated voltage.
7.11 DC Motor Applications
MIC4606 MOSFET drivers are widely used in DC
motor applications. They address both stepper and
brushed motors in full-bridge topologies. As shown in
Figure 7-9 and Figure 7-10, the driver switches the
MOSFETs at variable duty cycles that modulate the
voltage to control motor speed. The full-bridge topology
allows for bi-directional control.
Placement of the decoupling capacitors is critical. The
bypass capacitor for VDD should be placed as close as
possible between the VDD and VSS pins. The bypass
capacitor (CB) for the HB supply pin must be located as
close as possible between the HB and HS pins. The
etch connections must be short, wide, and direct. The
use of a ground plane to minimize connection
impedance is recommended. Refer to the section
Grounding, Component Placement and Circuit Layout
for more information.
The MIC4606’s 85V operating voltage offers ample
operating voltage margin to protect against voltage
spikes in the motor drive circuitry. It is good practice to
have at least twice the HV voltage of the motor supply.
The MIC4606’s 85V operating voltage allows sufficient
margin for 12V, 24V, and 40V motors.
The MIC4606 is offered in a small 4 mm x 4 mm QFN
16-lead package for applications that are space
constrained. The motor trend is to put the motor control
circuit inside the motor casing, which requires small
packaging because of the size of the motor.
The voltage on the bootstrap capacitor drops each time
it delivers charge to turn on the MOSFET. The voltage
drop depends on the gate charge required by the
MOSFET. Most MOSFET specifications specify gate
charge versus VGS voltage. Based on this information
and a recommended ∆VHB of less than 0.1V, the
minimum value of bootstrap capacitance is calculated
as:
The MIC4606 offers low UVLO threshold and
programmable gate drive, which allows for longer
operation time in battery operated motors such as
power hand tools.
EQUATION 7-13:
QGATE
----------------
CB
VHB
Where:
QGATE Total gate charge at VHB
∆VHB Voltage drop at the HB pin
If the high-side MOSFET is not switched but held in an
on state, the voltage in the bootstrap capacitor will drop
due to leakage current that flows from the HB pin to
ground. This current is specified in the Electrical
Characteristics table. In this case, the value of CB is
calculated as:
EQUATION 7-14:
IHBS tON
-------------------------
CB
VHB
Where:
IHBS Maximum HB pin leakage current
tON Maximum high-side FET on-time
The larger value of CB from Equation 7-13 or 7-14
should be used.
2018 Microchip Technology Inc.
DS20005604B-page 27
MIC4606
12VDC
5VDC
MIC2290
5V to12V
Boost
22μF
16V
MIC5283
LDO
12V to3.3V
VDD
EN
AHB
3.3VDC
MIC4606-1
FULL-BRIDGE
DRIVER
Q1
Q2
Q3
Q4
2.2μF
10V
AHO
AHS
VDD
I/O
AHI
ALI
I/O
I/O
μC
I/O
ALO
I/O
I/O
BHI
BLI
I/O
I/O
VSS
BLO
VSS
BHS
BHB BHO
M
12VDC
VDD
22μF
16V
EN
AHB
Q5
Q6
Q7
Q8
MIC4606-1
AHO
AHS
FULL-BRIDGE
DRIVER
AHI
ALI
ALO
BHI
BLI
VSS
BLO
BHS
BHB BHO
FIGURE 7-9:
Stepper Motor Driver.
DS20005604B-page 28
2018 Microchip Technology Inc.
MIC4606
MIC2290
5V TO 12V
Boost
5VDC
12VDC
HV
MIC5235
LDO
5V to 3.3V
VDD
3.3VDC
VCC
AHB
EN
MIC4606-1
C1
C2
N1
N3
N4
AHI
ALI
AHO
AHS
μC
M
BHI
BLI
N2
ALO
VSS
BLO
BHS
BHB BHO
FIGURE 7-10:
Full-Bridge DC Motor.
is used to power the line voltage. The Type II topology
switches at a higher frequency compared to the Type I
topology to maintain a small transformer size.
7.12 Power Inverter
Power inverters are used to supply AC loads from a DC
operated battery system, mainly during power failure.
The battery voltage can be 12 VDC, 24 VDC, or up to
36 VDC, depending on the power requirements. There
two popular conversion methods, Type I and Type II,
that convert the battery energy to AC line voltage
(110 VAC or 230 VAC).
Both types use a full bridge topology to invert DC to AC.
The MIC4606’s operating voltage offers enough of a
margin to address all of the available banks of batteries
commonly used in inverter applications. The 85V
operating voltage allows designers to increase the
bank of batteries up to 72V, if desired. The MIC4606
can sink as much as 1A, which is sufficient to drive the
MOSFET’s gate capacitance while switching the
MOSFET up to 50 kHz. This makes the MIC4606 an
ideal solution for single phase inverter applications.
BYPASS PATH
OUTPUT AC
INPUT AC
POWER SWITCHES FROM
INPUT AC TO DC/AC SUPPLY
DURING POWER OUTAGE
7.13 Grounding, Component
Placement and Circuit Layout
BATTERY
Nanosecond switching speeds and ampere peak
currents in and around the MIC4606 driver require
proper placement and trace routing of all components.
Improper placement may cause degraded noise
immunity, false switching, excessive ringing, or circuit
latch-up.
FIGURE 7-11:
Type I Inverter Topology.
As shown in Figure 7-11, Type I is a dual-stage
topology where line voltage is converted to DC through
a transformer to charge the storage batteries. When a
power failure is detected, the stored DC energy is
converted to AC through another transformer to drive
the AC loads connected to the inverter output. This
method is simplest to design but tends to be bulky and
expensive because it uses two transformers.
Figure 7-12 shows the critical current paths of the high
and low-side driver when their outputs go high and turn
on the external MOSFETs. It also helps demonstrate
the need for a low impedance ground plane. Charge
needed to turn-on the MOSFET gates comes from the
decoupling capacitors CVDD and CB. Current in the
low-side gate driver flows from CVDD through the
internal driver, into the MOSFET gate, and out the
Type II is a single-stage topology that uses only one
transformer to charge the bank of batteries to store the
energy. During a power outage, the same transformer
2018 Microchip Technology Inc.
DS20005604B-page 29
MIC4606
source. The return connection back to the decoupling
capacitor is made through the ground plane. Any
inductance or resistance in the ground return path
causes a voltage spike or ringing to appear on the
source of the MOSFET. This voltage works against the
gate drive voltage and can either slow down or turn off
the MOSFET during the period when it should be
turned on.
Figure 7-13 shows the critical current paths when the
driver outputs go low and turn off the external
MOSFETs. Short, low-impedance connections are
important during turn-off for the same reasons given in
the turn-on explanation. Current flowing through the
internal diode replenishes charge in the bootstrap
capacitor, CB.
LOW-SIDE DRIVE
TURN-OFF
Current in the high-side driver is sourced from
capacitor CB and flows into the xHB pin and out the
xHO pin, into the gate of the high side MOSFET. The
return path for the current is from the source of the
MOSFET and back to capacitor CB. The high-side
CURRENT PATH
xLO
VDD
xHB
CVDD
circuit return path usually does not have
a
low-impedance ground plane so the etch connections
in this critical path should be short and wide to minimize
parasitic inductance. As with the low-side circuit,
impedance between the MOSFET source and the
decoupling capacitor causes negative voltage
feedback that fights the turn-on of the MOSFET.
VSS
xLI
xHO
xHS
CB
LEVEL
SHIFT
xHI
It is important to note that capacitor CB must be placed
close to the xHB and xHS pins. This capacitor not only
provides all the energy for turn-on but it must also keep
xHB pin noise and ripple low for proper operation of the
high-side drive circuitry.
HIGH-SIDE DRIVE
TURN-OFF CURRENT
PATH
FIGURE 7-13:
Turn-Off Current Paths.
LOW-SIDE DRIVE TURN-
ON CURRENT PATH
xLO
VDD
xHB
CV
DD
GND
PLANE
VSS
xLI
GND
PLANE
xHO
xHS
LEVEL
SHIFT
CB
xHI
HIGH-SIDE DRIVE
TURN-ON CURRENT
PATH
FIGURE 7-12:
Turn-On Current Paths.
DS20005604B-page 30
2018 Microchip Technology Inc.
MIC4606
8.0
8.1
PACKAGING INFORMATION
Package Marking Information
16-lead QFN*
Example
XXXX
-XXXX
WNNN
4606
-1YML
1215
16-lead TSSOP*
Example
XXXX
-XXXX
4606
-1YTS
6943
WNNN
Legend: XX...X Product code or customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
e
3
)
●, ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle
mark).
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information. Package may or may not include
the corporate logo.
Underbar (_) and/or Overbar (⎯) symbol may not be to scale.
2018 Microchip Technology Inc.
DS20005604B-page 31
MIC4606
16-Lead QFN 4 mm x 4 mm Package Outline and Recommended Land Pattern
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
DS20005604B-page 32
2018 Microchip Technology Inc.
MIC4606
16-Lead TSSOP Package Outline and Recommended Land Pattern
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
2018 Microchip Technology Inc.
DS20005604B-page 33
MIC4606
NOTES:
DS20005604B-page 34
2018 Microchip Technology Inc.
MIC4606
APPENDIX A: REVISION HISTORY
Revision A (February 2017)
• Converted Micrel document MIC4606 to Micro-
chip data sheet template DS20005604A.
• Minor text changes throughout.
Revision B (January 2018)
• Replaced Figure 7-5 with the correct image.
2018 Microchip Technology Inc.
DS20005604B-page 35
MIC4606
NOTES:
DS20005604B-page 36
2018 Microchip Technology Inc.
MIC4606
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
Examples:
X
PART NO.
Device
-
-X
XX
XX
a)
b)
c)
d)
e)
f)
MIC4606-1YML:
85V Full-Bridge MOSFET
Driver with Adaptive
Junction
Temperature
Range
Input
Option
Package
Media
Type
Dead Time and Shoot-
Through Protection, Dual
Inputs, –40°C to +125°C
Junction Temperature
Range, 16-Pin QFN, 75/
Tube
Device:
MIC4606:
85V Full-Bridge MOSFET Drivers with
Adaptive Dead Time and Shoot-Through
Protection
MIC4606-1YML-T5:
MIC4606-1YML-TR:
MIC4606-1YTS-T5:
MIC4606-1YTS-TR
MIC4606-2YML-T5:
MIC4606-2YML-TR:
85V Full-Bridge MOSFET
Driver with Adaptive
Dead Time and Shoot-
Through Protection, Dual
Inputs, –40°C to +125°C
Input Option:
-1
-2
=
=
Dual inputs
Single PWM input
Junction
Temperature
Range:
Y
=
–40C to +125C (RoHS Compliant)
Junction
Temperature
Range, 16-Pin QFN, 500/
Reel
85V Full-Bridge MOSFET
Drivers with Adaptive
Dead Time and Shoot-
Through Protection, Dual
Inputs, –40°C to +125°C
Package:
ML
TS
=
=
16-Lead QFN
16-Lead TSSOP
Media Type
T5
TR
=
=
=
500/Reel
5000/Reel QFN (ML) Package
2500/Reel TSSOP (TS) Package
Junction
Temperature
Range, 16-Pin TSSOP,
5000/Reel
85V Full-Bridge MOSFET
Driver with Adaptive
Dead Time and Shoot-
Through Protection, Dual
Inputs, –40°C to +125°C
<blank>= 75/Tube QFN (-1YML) Package
Junction
Temperature
Range, 16-Pin TSSOP,
500/Reel
85V Full-Bridge MOSFET
Driver with Adaptive
Dead Time and Shoot-
Through Protection, Dual
Inputs, –40°C to +125°C
Junction
Temperature
Range, 16-Pin TSSOP,
2500/Reel
85V Full-Bridge MOSFET
Driver with Adaptive
Dead Time and Shoot-
Through Protection, Dual
Inputs, –40°C to +125°C
Junction
Temperature
Range, 16-Pin QFN, 500/
Reel
g)
85V Full-Bridge MOSFET
Driver with Adaptive
Dead Time and Shoot-
Through Protection, Sin-
gle PWM Input, –40°C to
+125°C Junction Tem-
perature Range, 16-Pin
QFN, 500/Reel.
2018 Microchip Technology Inc.
DS20005604B-page 37
MIC4606
NOTES:
DS20005604B-page 38
2018 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENAare trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ
CERTIFIEDꢀBYꢀDNVꢀ
© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-2518-2
== ISO/TSꢀ16949ꢀ==ꢀ
2018 Microchip Technology Inc.
DS20005604B-page 39
Worldwide Sales and Service
AMERICAS
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Corporate Office
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DS20005604B-page 40
2018 Microchip Technology Inc.
10/25/17
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