MIC7400YFL-TR_技术文档

MIC7400

Configurable PMIC, Five Channel Buck Regulator Plus One Boost

®

2

with HyperLight Load and I C Control

Features

General Description

• Input Voltage: 2.4V to 5.5V

The MIC7400 is a powerful, highly integrated,

configurable, power management IC (PMIC) featuring

five synchronous buck regulators, one boost regulator

and high-speed I²C interface with an internal

EEPROM.

• Five Independent Synchronous Bucks up to 3A

• One Independent Non-Synchronous Boost

200 mA

• 200 µA Quiescent Current (All Regulators On)

The device offers two distinct modes of operation—

“stand-by mode” and “normal mode”—intended to

provide an energy-optimized solution suitable for

portable handheld, and infotainment applications.

• 93% Peak Buck Efficiency, 85% Typical Efficiency

at 1 mA

• Dual Power Modes: Stand-by and Normal Mode

• I²C Interface up to 3.4 MHz

• I²C On-the-Fly EEPROM Programmability,

Featuring:

In normal mode, the programmable switching

converters can be configured to support a variety of

features, including start-up sequencing, timing,

soft-start ramp, output voltage levels, current-limit

levels and output discharge for each channel.

- Buck and Boost Output Voltage Scaling

- Power-on-Reset Threshold and Delay

- Power-Up Sequencing/Sequencing Delay

- Buck and Boost Current-Limit

In stand-by mode the PMIC can be configured in a low

power state by either disabling an output or by

changing the output voltage to another voltage level,

either lower or higher than normal-mode. In general, it's

assumed that the voltage in standby mode is lower than

the one in normal mode. Independent exit from

stand-by mode can be achieved either by I²C

communication or the external STBY pin.

- Buck and Boost Pull-Down when Disabled

- Individual ON, OFF, and Stand-by Modes

- Soft-Start and Global Power-Good Masking

• 23 µA Buck Typical Quiescent Current

• 70 µA Boost Typical Quiescent Current

• 1.5% Output Accuracy over

Temperature/Line/Load

The device has five synchronous buck regulators with

high-speed adaptive on-time control supporting even

the challenging ultra-fast transient requirement for

Core supplies. One boost regulator provides a flash

memory programming supply that delivers up to

200 mA of output current. The boost is equipped with

• 2.0 MHz Boost Switching Frequency

• 1.3 MHz Buck Operation in Continuous Mode

• Ultra-Fast Buck Transient Response

• 15 mm x 15 mm x 1.25 mm Solution Size

• Thermal Shutdown and Current-Limit Protection

an output disconnect switch that opens if

short-to-ground fault is detected.

a

• 36-Pin 4.5 mm x 4.5 mm x 0.85 mm FQFN

Package (0.4 mm Pitch)

An internal EEPROM enables a single-chip solution

across many platforms by allowing the designer to

customize the PMIC for their design. Modifications can

be made without the need to re-approve a new PMIC,

saving valuable design resources and time.

• –40°C to +125°C Junction Temperature Range

Applications

• Client and Enterprise Solid State Drives (SSD)

• Consumer and In-Vehicle Infotainment Devices

• Multimedia Devices

All switchers provide light load efficiency with

HyperLight Load^®mode for buck and PFM mode for

boost. An additional benefit of this proprietary

architecture is very low output ripple voltage throughout

the entire load range with the use of small output

capacitors. The MIC7400 is designed for use with a

small inductors (down to 0.47 µH for buck, 1.5 µH for

boost), and an output capacitor as small as 10 µF for

buck, enabling a total solution size of 15 mm x 15 mm

and less than 1 mm height.

• Portable Handheld Devices

• Security Cameras

• Gaming Machines

• Service Provider Gateways

 2017 Microchip Technology Inc.

DS20005887A-page 1

MIC7400

Typical Application Circuit

10μF

22μF

2.2μH

PVIN2

SW2 PGND2

OUT2

I_SNS

PVIN3

SW3

ZC

PVIN1

SYNC

BUCK2

10μF

I_SNS

ON-TIME

CONTROL

2.2μH

SW1

SYNC

BUCK1

SYNC

BUCK3

DAC

22μF

ZC

PGND3

OUT3

PGND1

OUT1

MIC7400

FAULT

BIASING

CIRCUIT

SEQUENCY

CONTROL

MONITOR

(OTP, OCP)

PVIN6

PVIN4

DAC ARRAY

AND

10μF

ANALOG

I_SNS

10μF

CONTROL

SOFT-START

I_SNS

ON-TIME

OSC

ON/OFF

PWM

CONTROL

2.2μH

STAND-BY

POWER

MANAGEMENT

CONTROL

DIGITAL

CONTROL

2.2μH

SW4

PVIN6O

SW6

SYNC

BUCK4

BOOST

I_SNS

DAC

22μF

PGND4

OUT4

ZC

DIG CTRL

DAC

ANALOG CTRL

PGND6

OUT6

SDA

SCL

I²C

INTERFACE

AVIN

UVLO

EEPROM

ANALOG CTRL

DIG CTRL

AND BG

AGND

SYNC

BUCK5

I_SNS

ZC

PG

POR

COMPARATOR

POR

VSLT

STBY

DIG CTRL

OUT5

SW5

PVIN5

PGND5

22μF

2.2μH

10μF

DS20005887A-page 2

 2017 Microchip Technology Inc.

MIC7400

Block Diagram

MIC7400

EEPROM

SDA

SCL

I²C INTERFACE

REGISTERS

PG

POR

(REFERENCED TO AVIN)

FAULT MONITOR

DAC ARRAY

VSLT

STBY

SEQUENCE

CONTROLLER

AVIN

INPUT LEVEL DETECT

UVLO

THERMAL

SENSOR

SLOW

OSC

VOTLAGE REFERENCE

AGND

PVIN1

SW1

PVIN2

I_SNS

ON-TIME

CONTROL

SW2

SYNC

BUCK

SYNC

BUCK

ZC

PGND1

OUT1

PGND2

OUT2

PVIN6

PVIN3

SW3

I_SNS

ON/OFF

I_SNS

PWM

ON-TIME

CONTROL

PVIN6O

SW6

BOOST

I_SNS

SYNC

BUCK

ZC

PGND6

OUT6

PGND3

OUT3

PVIN5

PVIN4

I_SNS

ON-TIME

CONTROL

ON-TIME

CONTROL

SW4

SYNC

BUCK

SYNC

BUCK

SW5

ZC

PGND4

OUT4

PGND5

OUT5

 2017 Microchip Technology Inc.

DS20005887A-page 3

MIC7400

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Supply Voltages (PV_IN[1-6])........................................................................................................................... –0.3V to +6V

Analog Supply Voltage (AV_IN) ...................................................................................................................... –0.3V to +6V

Buck Output Voltages (V_OUT[1-5])................................................................................................................. –0.3V to +6V

Boost Output Voltage (V_OUT6).................................................................................................................... –0.3V to +20V

Buck Switch Voltages (V_SW[1-5])................................................................................................................... –0.3V to +6V

Boost Switch Voltage (V_SW6) ..................................................................................................................... –0.3V to +20V

Power Good Voltage (V_PG) ......................................................................................................................... –0.3V to AV_IN

Power-On Reset Output (V_POR)................................................................................................................... –0.3V to +6V

POR Threshold Voltage (V_VSLT)................................................................................................................... –0.3V to +6V

Standby Voltage (V_STBY)..............................................................................................................................–0.3V to +6V

I²C IO (V_SDA, V_SCL)..................................................................................................................................... –0.3V to AV_IN

AGND to PGND[1-6] ................................................................................................................................. –0.3V to +0.3V

ESD Rating (Note 1).......................................................................................................................HBM: 2 kV; MM: 200V

Operating Ratings ‡

Input Voltage (PV_IN[1-6]) ............................................................................................................................+2.4V to +5.5V

Analog Input Voltage (AV_IN) ......................................................................................................................+2.4V to +5.5V

Buck Output Voltage Range (V_OUT[1-5]) ....................................................................................................+0.8V to +3.3V

Boost Output Voltage Range (V_OUT6) ...........................................................................................................+7V to +14V

Power Good Voltage (V_PG) .............................................................................................................................. 0V to AV_IN

Power-On Reset Output (V_POR)....................................................................................................................... 0V to AV_IN

POR Threshold Voltage (V_VSLT)....................................................................................................................... 0V to AV_IN

Standby Voltage (V_STBY).................................................................................................................................. 0V to AV_IN

I²C IO (V_SDA, V_SCL).......................................................................................................................................... 0V to AV_IN

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at those or any other conditions above those indicated

in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended

periods may affect device reliability. Specifications are for packaged product only.

‡ Notice: The device is not guaranteed to function outside its operating ratings.

Note 1: Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5 kΩ in series

with 100 pF.

DS20005887A-page 4

 2017 Microchip Technology Inc.

MIC7400

TABLE 1-1:

ELECTRICAL CHARACTERISTICS

Electrical Characteristics: V_IN= AV_IN= PV_IN(1-6)= 5.0V; V_OUT1= 1.8V; V_OUT2= 1.1V; V_OUT3= 1.8V; V_OUT4

=

1.05V; V_OUT5= 1.25V; V_OUT6= 12V. T_A= +25°C, unless otherwise noted. Bold values indicate –40°C ≤ T_J≤ +125°C.

Note 1

Parameter

Min.

Typ.

Max.

Units Conditions

Input Supply (V_IN)

Input Voltage Range (AV_IN, PV_IN[1-6]

)

2.4

—

5.5

V

—

Operating Quiescent Current into AV_IN

(Note 2, Note 3)

—

200

240

µA

V_IN= 5.0V; I_OUT= 0A

Operating Quiescent Current into PV_IN

(Note 2)

—

0.3

1.0

µA

V_IN= 5.0V; I_OUT= 0A

Undervoltage Lockout Threshold

Undervoltage Lockout Hysteresis

Standby Input (STBY)

Logic Level High

2.15

2.25

150

2.35

V

AV_INRising

—

mV

1.2

—

0.4

200

—

V

—

Logic Level Low

V

Bias Current into Pin

—

nA

µs

V_STBY= V_IN

Bias Current out of Pin

—

V_STBY= 0V

—

Rising/Falling Edge Reset Deglitch

100

POR Threshold Input (V_SLT

)

Logic Level High

1.2

—

Logic Level Low

0.4

200

—

Bias Current Into Pin

Bias Current Out of Pin

V_VSLT= V_IN

V_VSLT= 0V

Power-On-Reset (POR) Comparator

POR Upper Comparator Range

POR Lower Comparator Range

POR Upper Comparator Range

POR Lower Comparator Range

Power Reset Output (POR) and Timer

POR Delay

2.646

2.548

3.626

3.528

2.7

2.6

3.7

3.6

2.754

2.652

3.774

3.672

V

AV_INRising, V_VSLT= 0V

AV_INFalling, V_VSLT= 0V

AV_INRising, V_VSLT= V_IN

AV_INFalling, V_VSLT= V_IN

18

—

20

50

75

—

22

—

ms

µs

—

POR Deglitch Delay

AV_INFalling

POR Output Low Voltage

400

200

mV

nA

I_POR= 10 mA (sinking)

POR Leakage Current

V_POR= 5.5V

Global Power Good Output (PG)

Buck Power Good Threshold Voltage

Buck Hysteresis (Note 4)

87

—

91

4

95

—

%V_OUTV_OUT[1-5]Rising

%V_OUTV_OUT[1-5]Falling

%V_OUTV_OUT[6]Rising

Boost Power Good Threshold Voltage

Boost Hysteresis (Note 4)

87

—

91

95

380

75

—

mV

nA

µs

V_OUT[6]Falling

_PG= 10 mA (sinking)

V_PG= 5.5V

Power Good Output Low Voltage

Power Good Leakage Current

Power Good Deglitch Delay

Output Sequencing Delay (Note 4)

Thermal Protection

—

400

200

—

I

—

0.01

100

1

—

V_OUT[1-6]Falling

—

0.96

1.04

ms

Thermal Shutdown

—

160

20

—

°C

T_JRising

—

Thermal Hysteresis

 2017 Microchip Technology Inc.

DS20005887A-page 5

MIC7400

TABLE 1-1:

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Characteristics: V_IN= AV_IN= PV_IN(1-6)= 5.0V; V_OUT1= 1.8V; V_OUT2= 1.1V; V_OUT3= 1.8V; V_OUT4

=

1.05V; V_OUT5= 1.25V; V_OUT6= 12V. T_A= +25°C, unless otherwise noted. Bold values indicate –40°C ≤ T_J≤ +125°C.

Note 1

Parameter

Min.

Typ.

Max.

Units Conditions

Synchronous Buck (V_OUT1- V_OUT5

)

Buck Output Voltage Accuracy (OUT[1-5])

Typical Output Voltage 1 Accuracy

(Note 5)

–1.5

—

1.5

%

Includes Load, Line, and Reference

Typical Output Voltage 2 Accuracy

(Note 5)

–1.5

Includes Load, Line, and Reference

Typical Output Voltage 3 Accuracy

(Note 5)

Typical Output Voltage 4 Accuracy

(Note 5)

Typical Output Voltage 5 Accuracy

(Note 5)

Output Voltage 1 Accuracy (Note 5)

Output Voltage 2 Accuracy (Note 5)

Output Voltage 3 Accuracy (Note 5)

Output Voltage 4 Accuracy (Note 5)

Output Voltage 5 Accuracy (Note 5)

Load Regulation

–1

—

1

%

—

1

—

1

—

1

—

0.1

0.05

—

I_OUT= 10 mA to I_OUT(MAX)

V_IN= 3.3V to 5.0V

Line Regulation

Buck Soft-Start

Soft-Start (1-5) LSB (Note 4, Note 6)

Buck Internal MOSFETs

3.84

4.0

4.16

µs/step

—

High-Side On-Resistance

—

75

54

40

37

30

90

—

mꢀ

ꢀ

V

_IN= 3.3V; I_SW[1-5]= 200 mA

High-Side On-Resistance

V_IN= 5.0V; I_SW[1-5]= 200 mA

Low-Side On-Resistance

—

V

_IN= 3.3V; I_SW[1-5]= –200 mA

_IN= 5.0V; I_SW[1-5]= –200 mA

Low-Side On-Resistance

—

V

Output Pull-Down Resistance

Buck Controller Timing

200

V_SW[1-5]= 0V

Fixed On-Time (Note 7)

—

220

80

—

ns

V_IN= 3.3; V_OUT= 1.0V; I_OUT= 1.0A

Minimum OFF-Time

—

Buck Current-Limit (OUT1 - OUT5)

Buck 1 Current-Limit Threshold

Buck 2 Current-Limit Threshold

Buck 3 Current-Limit Threshold

Buck 4 Current-Limit Threshold

Buck 5 Current-Limit Threshold

3.075

4.88

4.1

6.1

4.1

5.125

7.32

A

See Table 4-3 for IPROG Settings

3.075

5.125

With Respect to Buck [x]

Current-Limit

Gross High-Side Current-Limit [1-5]

Zero Cross Threshold

—

150

0

—

%

mV

Zero crossing detector

DS20005887A-page 6

 2017 Microchip Technology Inc.

MIC7400

TABLE 1-1:

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Characteristics: V_IN= AV_IN= PV_IN(1-6)= 5.0V; V_OUT1= 1.8V; V_OUT2= 1.1V; V_OUT3= 1.8V; V_OUT4

=

1.05V; V_OUT5= 1.25V; V_OUT6= 12V. T_A= +25°C, unless otherwise noted. Bold values indicate –40°C ≤ T_J≤ +125°C.

Note 1

Parameter

Min.

–1.5

Typ.

Max.

1.5

Units Conditions

Boost (V_OUT6

)

Boost Output Voltage (V_OUT6

)

Typical Output Voltage Accuracy

(Note 5)

—

%

Includes Load, Line, and Reference

Output Voltage Accuracy (Note 5)

Load Regulation

–1

—

0.2

148

1

—

%

—

I_OUT6= 1.0 mA to 200 mA

Line Regulation

—

%

V_IN= 2.4V to 5.5V; I_OUT6= 10 mA

V_OUT6Discharge Current

111

185

mA

V_IN= 3.3V; V_OUT6= 12V

Boost Soft-Start Step Duration

Soft-Start 6 LSB (Note 4, Note 6)

Boost Internal MOSFETs

Low-Side On-Resistance

Boost Disconnect MOSFETs

Disconnect Switch On-Resistance

Disconnect Switch Current-Limit

Boost Switching Frequency

Switching Frequency (PWM Mode)

Minimum Duty Cycle

3.84

4.0

4.16

µs/step

—

160

140

—

mꢀ

V

_IN= 3.3V; I_SW1= –100 mA

_IN= 5.0V; I_SW1= –100 mA

V

—

90

5

—

mꢀ

I_PVIN6O= 100 mA; V_IN= 3.3V

A

—

1.92

35

2.0

40

85

2.08

45

MHz

%

—

Maximum Duty Cycle

80

90

%

Boost Current-Limit

NMOS Current-Limit Threshold

I²C Interface

—

2.24

—

A

—

I²C Interface (SCL, SDA)

Low Level Input Voltage

—

1.2

–200

—

0.4

—

V

—

High Level Input Voltage

Low Level Input Current

0.01

20

200

—

nA

ꢀ

High Level Input Current

SDA Pull-Down Resistance

SDA Logic 0 Output Voltage

CLK, DATA Pin Capacitance

I²C Interface Timing (Note 4)

—

0.4

—

V

I

_SDA= 3 mA

—

0.7

pF

—

100

400

3.4

kHz

MHz

Standard Mode

SCL Clock Frequency

Fast Mode

High Speed Mode (Note 4)

Note 1: Specifications are for packaged product only.

2: Tested in a non-switching configuration.

3: When all outputs are configured to the minimum programmable voltage.

4: Guaranteed by design.

5: Not tested in a closed loop configuration.

6: The soft-start time is calculated using the following equation: t_softstart= [(V_{OUT_PROGRAM}– 0.15)/0.05 +1) ×

t_RAMP

.

7: Buck frequency is calculated using the following equation f_SW= (V_OUT/V_IN) × (1/t_ON).

 2017 Microchip Technology Inc.

DS20005887A-page 7

MIC7400

TEMPERATURE SPECIFICATIONS (Note 1)

Parameters

Temperature Ranges

Sym.

Min.

Typ.

Max.

Units

Conditions

Junction Operating Temperature

Range

T_J

–40

—

+125

+150

°C

—

Ambient Storage Temperature Range

Package Thermal Resistance

Thermal Resistance FQFN-36Ld

T_S

_JA

—

30

—

°C/W

—

Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable

junction temperature and the thermal resistance from junction to air (i.e., T_A, T_J, _JA). Exceeding the

maximum allowable power dissipation will cause the device operating junction temperature to exceed the

maximum +125°C rating. Sustained junction temperatures above +125°C can impact the device reliability.

DS20005887A-page 8

 2017 Microchip Technology Inc.

MIC7400

2.0

TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

FIGURE 2-1:

Buck Efficiency (LDCR =

FIGURE 2-4:

Buck Efficiency (LDCR =

0 mΩ) vs. Output Current.

40 mΩ) vs. Output Current.

FIGURE 2-2:

Buck Efficiency (LDCR =

FIGURE 2-5:

Buck Efficiency (LDCR =

0 mΩ) vs. Output Current.

40 mΩ) vs. Output Current.

FIGURE 2-3:

Boost Efficiency (12V) vs.

FIGURE 2-6:

Output Voltage vs. Output

Output Current.

Current.

 2017 Microchip Technology Inc.

DS20005887A-page 9

MIC7400

FIGURE 2-7:

Buck Efficiency (LDCR =

FIGURE 2-10:

Buck Output Voltage (1.0V)

116 mΩ) vs. Output Current.

vs. Output Current.

FIGURE 2-11:

Regulator vs. Output Current.

Buck Output Voltage

FIGURE 2-8:

116 mΩ) vs. Output Current.

Buck Efficiency (LDCR =

FIGURE 2-12:

Buck Line Regulation vs.

FIGURE 2-9:

Output Voltage vs.

Input Voltage.

Temperature.

DS20005887A-page 10

 2017 Microchip Technology Inc.

MIC7400

FIGURE 2-13:

Output Current.

Dropout Output Voltage vs.

FIGURE 2-16:

Output Voltage.

Current-Limit Threshold vs.

Output Current-Limit vs.

Programmed Current-Limit

FIGURE 2-17:

Output Voltage.

FIGURE 2-14:

Current vs. Input Voltage.

V

Operating Supply

IN

FIGURE 2-18:

vs. Measured Current-Limit.

FIGURE 2-15:

vs. Input Voltage.

Buck 2 Switching Frequency

 2017 Microchip Technology Inc.

DS20005887A-page 11

MIC7400

V_IN= 3.3V

V_IN

(2V/div)

V_IN= 3.3V

V_IN

(2V/div)

V_OUT4

(1V/div)

V_OUT4= 1.05V/0.1A

V_OUT2= 1.1V/0.1A

V_OUT4= 1.05V/0.1A

V_OUT2= 1.1V/0.1A

V_OUT2

(1V/div)

V_OUT2

(1V/div)

V_OUT3= 1.8V/0.1A

V_OUT3

(1V/div)

V_OUT3

(1V/div)

V

_OUT3= 1.8V/0.1A

_OUT1= 1.8V/0.1A

V_OUT1= 1.8V/0.1A

V_OUT1

(1V/div)

V

_OUT5= 1.8V/0.1A

V_OUT5

(1V/div)

V_OUT5= 1.25V/0.1A

V_OUT5

(1V/div)

V_OUT6= 1.8V/0.1A

V_OUT6

(5V/div)

V_OUT6

(10V/div)

V

_OUT6= 12V/0.1A

V

(2V/di^Pv^G)

V

(2V/di^Pv^G)

Time (1.0ms/div)

FIGURE 2-19:

Hot Plug – Rising V .

FIGURE 2-21:

Unplug – Falling V .

IN

FIGURE 2-20:

POR Timing.

FIGURE 2-22:

STBY Delay.

DS20005887A-page 12

 2017 Microchip Technology Inc.

MIC7400

FIGURE 2-23:

Buck Soft-Start.

FIGURE 2-26:

POR Delay.

FIGURE 2-24:

Boost Soft-Start.

FIGURE 2-27:

Output Pull-Down

Resistance.

FIGURE 2-25:

Standard Delay.

FIGURE 2-28:

Buck 2 Load Transient –

10 mA to 1A.

 2017 Microchip Technology Inc.

DS20005887A-page 13

MIC7400

FIGURE 2-29:

10 mA to 3A.

Buck 4 Load Transient –

Buck 2 Load Transient –

Buck 4 Load Transient –

FIGURE 2-32:

10 mA to 0.2A.

Buck 2 Load Transient –

FIGURE 2-30:

200 mA to 1A.

FIGURE 2-33:

10 mA to 0.5A.

Buck 4 Load Transient –

FIGURE 2-31:

FIGURE 2-34:

Boost 6 Load Transient –

0.5A to 3A.

10 mA to 200 mA.

DS20005887A-page 14

 2017 Microchip Technology Inc.

MIC7400

FIGURE 2-35:

10 mA to 50 mA.

Boost 6 Load Transient –

Buck 4 Line Transient –

Boost 6 Line Transient –

FIGURE 2-38:

Cross Regulation.

FIGURE 2-39:

Waveforms.

Buck 2 PWM Switching

FIGURE 2-36:

3.3V to 5.0V.

FIGURE 2-40:

Buck 2 PFM Switching

FIGURE 2-37:

Waveforms.

3.3V to 5.0V.

 2017 Microchip Technology Inc.

DS20005887A-page 15

MIC7400

FIGURE 2-41:

Waveforms.

Buck 4 PWM Switching

Buck 4 PFM Switching

Boost 6 PWM Switching

FIGURE 2-44:

Waveforms.

Boost 6 PFM Switching

FIGURE 2-42:

Waveforms.

FIGURE 2-45:

– No Load.

Input Supply Inrush Current

FIGURE 2-43:

Waveforms.

DS20005887A-page 16

 2017 Microchip Technology Inc.

MIC7400

FIGURE 2-46:

Input Supply Inrush Current

FIGURE 2-48:

Rising Edge Trigger

– Loaded.

Standby.

FIGURE 2-47:

Falling Edge Trigger

Standby (DEFAULT).

 2017 Microchip Technology Inc.

DS20005887A-page 17

MIC7400

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

31

28

29

34

36 35

33 32

30

1

27

26

SW1

PVIN1

SW2

PVIN2

2

25

24

23

22

PVIN6

PVIN6O

SW6

OUT2

PVIN3

SW3

3

4

5

EP

6

7

PGND6

OUT6

PVIN5

PGND3

21

20

OUT3

PVIN4

SW4

8

9

19 SW5

18

10

12

14

15 16 17

11

13

FIGURE 3-1:

MIC7400 Pin Configuration.

TABLE 3-1:

PIN FUNCTION TABLE

Pin Number Pin Name

Description

Switch Pin 2 (Output): Inductor connection for the synchronous step-down regulator.

Connect the inductor between the output capacitor and the SW2 pin.

1

2

SW2

Power Supply Voltage 2 (Input): Input supply to the source of the internal high-side

P-channel MOSFET. An input capacitor between PVIN2 and the power ground PGND2

pin is required and should be placed as close as possible to the IC.

PVIN2

Output Voltage Sense 2 (Input): This pin is used to sense the output voltage. Connect

OUT2 as close to the output capacitor as possible to sense output voltage. Also

provides the path to discharge the output through an internal 90ꢀ resistor when

disabled. This pull-down feature is programmed through the PULLD[x] register.

3

OUT2

Power Supply Voltage 3 (Input): Input supply to the source of the internal high-side

P-channel MOSFET. An input capacitor between PVIN3 and the power ground PGND3

pin is required and should be placed as close as possible to the IC.

4

5

6

PVIN3

SW3

Switch Pin 3 (Output): Inductor connection for the synchronous step-down regulator.

Connect the inductor between the output capacitor and the SW3 pin.

Power Ground 3: The power ground for the synchronous buck converter power stage.

PGND3 The PGND pin connects to the sources of the internal low-side N-Channel MOSFET, the

negative terminals of input capacitors, and the negative terminals of output capacitors.

Output Voltage Sense 3 (Input): This pin is used to sense the output voltage. Connect

OUT3 as close to the output capacitor as possible to sense output voltage. Also

provides the path to discharge the output through an internal 90ꢀ resistor when

7

OUT3

disabled. This pull-down feature is programmed through the PULLD[x] register.

Power Supply Voltage 4 (Input): Input supply to the source of the internal high-side

8

9

PVIN4

SW4

P-channel MOSFET. An input capacitor between PVIN4 and the power ground PGND4

pin is required and to be placed as close as possible to the IC.

Switch Pin 4 (Output): Inductor connection for the synchronous step-down regulator.

Connect the inductor between the output capacitor and the SW4 pin.

DS20005887A-page 18

 2017 Microchip Technology Inc.

MIC7400

TABLE 3-1:

PIN FUNCTION TABLE (CONTINUED)

Pin Number Pin Name

Description

Power Ground 4: The power ground for the synchronous buck converter power stage.

10

11

PGND4 The PGND pin connects to the source of the internal low-side N-Channel MOSFET, the

negative terminals of input capacitors, and the negative terminals of output capacitors.

Output Voltage Sense 4 (Input): This pin is used to sense the output voltage. Connect

the OUT4 as close to the output capacitor as possible to sense output voltage. Also

provides the path to discharge the output through an internal 90ꢀ resistor when

OUT4

disabled. This pull-down feature is programmed through the PULLD[x] register.

Standby Reset (Input): Standby mode allows the total power consumption to be reduced

by either lowering a supply voltage or turning it off. The IC can be placed in standby

mode while operating in normal mode by a high-to-low transition (DEFAULT) on the

STBY input. When this occurs, the STBY_MODEB bit will be set to logic “0”. Either a

12

13

STBY

SDA

low-to-high transition on the STBY pin or an I²C write command to the STBY_MODEB

bit sets all of the regulators to their normal mode default settings. This pin can be driven

with either a digital signal or open collector output. Do not let this pin float. Connect to

ground or VIN. A pull-down resistor of 100 kꢀ or less can also be used. There are both

a high-to-low (DEFAULT) and low-to-high normal to standby trigger options available.

High-Speed Mode 3.4 MHz I²C Data (Input/Output): This is an open-drain, bidirectional

data pin. Data is read on the rising edge of the SCL and data is clocked out on the

falling edge of the SCL. External pull-up resistors are required.

Analog Ground: Internal signal ground for all low power circuits. Connect to ground

plane for best operation.

High-Speed Mode 3.4 MHz I²C Clock (Input): I²C serial clock line open-drain input.

14

15

AGND

SCL

External pull-up resistors are required.

Power-on-Reset (Output): This is an open-drain output that goes high after the POR

delay time elapses. The POR delay time starts as soon as the AVIN pin voltage rises

above the upper threshold set by the PORUP register. The POR output goes low

without delay when AVIN falls below the lower threshold set by the PORDN register.

16

17

POR

Output Voltage Sense 5 (Input): This pin is used to sense the output voltage. Connect

OUT5 as close to the output capacitor as possible to sense output voltage. Also

provides the path to discharge the output through an internal 90ꢀ resistor when

disabled. This pull-down feature is programmed through the PULLD[x] register.

OUT5

Power Ground 5: The power ground for the synchronous buck converter power stage.

18

19

20

PGND5 The PGND pin connects to the source of the internal low-side N-Channel MOSFET, the

negative terminals of input capacitors, and the negative terminals of output capacitors.

Switch Pin 5 (Output): Inductor connection for the synchronous step-down regulator.

Connect the inductor between the output capacitor and the SW5 pin.

SW5

Power Supply Voltage 5 (Input): Input supply to the source of the internal high-side

PVIN5

OUT6

P-channel MOSFET. An input capacitor between PVIN5 and the power ground PGND5

pin is required and should be placed as close as possible to the IC.

Output Voltage 6 Sense (Input): This pin is used to sense the output voltage. Connect

OUT6 as close to the output capacitor as possible to sense output voltage. Also

provides the path to discharge the output through an internal programmable current

source when disabled. This pull-down feature is programmed through the PULLD[x]

register.

21

Power Ground 6: The power ground for the boost converter power stage. The PGND

22

23

PGND6 pin connects to the source of the internal low-side N-Channel MOSFET, the negative

terminals of input capacitors, and the negative terminals of output capacitors.

Switch Pin 6 (Input): Inductor connection for the boost regulator. Connect the inductor

SW6

between the PVIN6O and SW6 pin.

 2017 Microchip Technology Inc.

DS20005887A-page 19

MIC7400

TABLE 3-1:

PIN FUNCTION TABLE (CONTINUED)

Pin Number Pin Name

Description

Power Supply Voltage 6 (Output): This pin is the output of the power disconnect switch

for the boost regulator. When the boost regulator is on, an internal switch provides a

current path for the boost inductor. In shutdown, an internal P-channel MOSFET is

24

PVIN6O turned off and disconnects the boost output from the input supply. This feature

eliminates current draw from the input supply during shutdown. An input capacitor

between PVIN6O and the power ground PGND6 pin is required and place as close as

possible to the IC.

25

26

PVIN6

Power Supply Voltage 6 (Input): Input supply to the internal disconnect switch.

Power Supply Voltage 1 (Input): Input supply to the source of the internal high-side

P-channel MOSFET. An input capacitor between PVIN1 and the power ground PGND1

pin is required and should be placed as close as possible to the IC.

PVIN1

Switch Pin 1 (Output): Inductor connection for the synchronous step-down regulator.

Connect the inductor between the output capacitor and the SW1 pin.

27

28

SW1

Power Ground 1: The power ground for the synchronous buck converter power stage.

PGND1 The PGND pin connects to the source of the internal low-side N-Channel MOSFET, the

negative terminals of input capacitors, and the negative terminals of output capacitors.

Output Voltage Sense 1 (Input): This pin is used to sense the output voltage remotely.

Connect OUT1 as close to output capacitor as possible to sense output voltage. This

feature also provides the path to discharge the output through an internal 90ꢀ resistor

when disabled. The pull-down feature is programmed through the PULLD[x] register.

29

30

31

32

OUT1

POR Selection Threshold (Input): A high on this pin sets the PORUP and PORDN

registers to their upper threshold limits and a low to their lower threshold limits. Do not

leave floating.

VSLT

AVIN

Analog Voltage Supply (Input): The start-up sequence begins as soon as the AVIN pin

voltage rises above the IC’s UVLO upper threshold. The outputs do not turn off until

AVIN pin voltage falls below the lower threshold limit. A 2.2 µF ceramic capacitor from

the AVIN pin to AGND pin must be placed next to the IC.

Analog Ground: Internal signal ground for all low power circuits. Connect directly to the

layer 2 ground plane. Layer 2 is the point where all the PGNDs and AGND are

connected. Do not connect PGND and AGND together on the top layer.

AGND

33

34

NC

No Connect. Must be left floating.

Global Power Good (Output): This is an open-drain output that is pulled high when all

the regulator power good flags are high. If an output falls below the power good

threshold or a thermal fault occurs, the global power good flag is pulled low. There is a

falling edge de-glitch time of 50 µs to prevent false triggering on output voltage

transients. A power good mask feature programmed through the PGOOD_MASK[x]

registers can be used to ignore a power good fault. When masked an individual power

good fault will not cause the global power good output to de-assert. Do not connect the

power good pull-up resistor to a voltage higher than AVIN.

35

PG

Power Ground 2: The power ground for the synchronous buck converter power stage.

36

PGND2 The PGND pin connects to the source of the internal low-side N-Channel MOSFET, the

negative terminals of input capacitors, and the negative terminals of output capacitors.

EP

ePAD

Exposed Pad: Must be connected to the GND plane for full output power to be realized.

DS20005887A-page 20

 2017 Microchip Technology Inc.

MIC7400

The MIC7400 has a current-mode boost regulator that

can deliver up to 200 mA of output current and only

consumes 70 µA of quiescent current. The 2.0 MHz

switching frequency allows small chip inductors to be

used. Programmable overcurrent sensing protects the

boost from overloads and an output disconnect switch

opens to protect against a short-circuit condition.

Soft-start is also programmable and controls both the

rising and falling output.

4.0

FUNCTIONAL DESCRIPTION

The MIC7400 is one of the industry’s most-advanced

PMIC designed for solid state drives (SSD) on the

market today. It is a multi-channel solution that offers

software-configurable soft-start, sequencing, and

digital voltage control (DVC) that minimizes PC board

area. These features usually require a pin for

programming. However, this approach makes the IC

larger by increasing pin count, and also increases BOM

cost due to the external components.

4.1

Programmable Buck Soft-Start

Control

The following is a complete list of programmable

features:

The MIC7400 soft-start feature forces the output

voltage to rise gradually, which limits the inrush current

during start-up. A slower output rise time will draw a

lower input surge current. The soft-start time is based

on the least significant bit (LSB) of an internal DAC and

the speed of the ramp rate, as shown in Figure 4-1.

This illustrates the soft-start waveform for all five

synchronous buck converters. The initial step starts at

150 mV and each subsequent step is 50 mV.

• Buck output voltage (0.8V – 3.3V/50 mV steps)

• Boost output voltage (7.0V – 14V/ 200 mV steps)

• Power-on-reset (2.25V – 4.25V/50 mV steps)

• Power-on-reset delay (5 ms – 160 ms/5 ms steps)

• Power-up sequencing (6 time slots)

• Power-up sequencing delay (0 ms – 7 ms/1 ms

steps)

• Soft-start (4 µs – 1024 µs per step)

• Buck current limit threshold

- (1.1A to 6.1A/0.5A steps)

• Boost current limit threshold

V_OUT

- (1.76A to 2.6A/0.12A steps)

• Boost pull-down (37 mA to 148 mA/37 mA steps)

• Buck pull-down (90ꢀ)

• Buck standby output voltage programmable

• Buck standby programmable standby current limit

• Boost standby output voltage programmable

50mV

• Boost standby programmable standby current

limit

t_RAMP

150mV

• Global power good masking

These features give the system designer the flexibility

to customize the MIC7400 for their application. For

example, V_OUT1current-limit can be programmed to

4.1A and V_OUT2can be set to 1.1A. These outputs can

be programmed to come up at the same time or 2.0 ms

apart. In addition, in power-saving standby mode, the

outputs can either be turned off or programmed to a

lower voltage. With this programmability, the MIC7400

can be used in multiple platforms.

TIME

t_SOFT-START

FIGURE 4-1:

Buck Soft-Start.

The output ramp rate (t_RAMP) is set by the soft-start

registers. Each output ramp rate can be individually set

from 4 µs to 1024 µs, see Table 4-1 for details.

The soft-start time t_SScan be calculated by

Equation 4-1:

The MIC7400 buck regulators are adaptive on-time

synchronous step-down DC-to-DC regulators. They

are designed to operate over a wide input voltage

range from 2.4V to 5.5V and provide a regulated output

voltage at up to 3.0A of output current. An adaptive

on-time control scheme is employed to obtain a

constant switching frequency and to simplify the control

compensation. The device includes an internal

soft-start function which reduces the power supply

input surge current at start-up by controlling the output

voltage rise time.

EQUATION 4-1:

V_OUT– 0.15V









---------------------------------

t_SS

=

 t_RAMP

50mV

Where:

t_SS= Output rise time.

V_OUT= Output voltage.

t_RAMP= Output dwell time.

 2017 Microchip Technology Inc.

DS20005887A-page 21

MIC7400

For example:

EQUATION 4-2:

V_OUT

1.8V – 0.15V









¨V_OUT

-------------------------------

t_SS

=

 8s

50mV

t_SS= 264s

50mV

Where:

V_OUT= 1.8V

t_RAMP= 8.0 µs

t_RAMP

V_{OUT_INIT}

Δt

TIME

TABLE 4-1:

—

BUCK OUTPUTS DEFAULT

SOFT-START TIME (DEFAULT)

FIGURE 4-3:

Buck DVC Control Ramp.

V_OUT

t_RAMP

t_SS

The ramp time is determined by Equation 4-3:

V_OUT1

V_OUT2

V_OUT3

V_OUT4

V_OUT5

1.8V

1.1V

8 µs

264 µs

152 µs

264 µs

144 µs

176 µs

EQUATION 4-3:

1.8V

V_OUT– V_{OUT_INIT}

1.05V

1.25V









---------------------------------------------

t =

 t_RAMP

50mV

Figure 4-2 shows the output of Buck 1 ramping up

cleanly, starting from 0.15V to its final 1.1V value.

Where:

V_{OUT_INIT}= Initial output voltage.

V_OUT= Final output voltage.

t_RAMP= Output dwell time.

When the regulator is programmed to a lower voltage,

then the output voltage ramps down at a rate

determined by the output ramp rate (t_RAMP), the output

capacitance and the external load. Small loads result in

slow output voltage decay and heavy loads cause the

decay to be controlled by the DAC ramp rate.

V_IN= 5.0V

V_OUT2= 1.1V

V_OUT2

(200mV/div)

I_OUT4= 500mA

t_SS= 203μs; DS = 152μs

In Figure 4-4, V_OUT1is switched to stand-by mode with

an I²C command and then switched back to normal

mode either by an I²C command or a low-to-high

transition of the STBY pin. In this case, the rise and fall

Time (40μs/div)

times are the same due to a 1A load on V_OUT1

.

FIGURE 4-2:

Buck Soft-Start.

DVC Rise/Fall – 64μs/Step

4.2

Buck Digital Voltage Control (DVC)

The output voltage has a 6-bit control DAC that can be

programmed from 0.8V to 3.3V in 50 mV increments. If

the output is programmed to a higher voltage, then the

output ramps up, as shown in Figure 4-3.

V_OUT1

STAND-BY

(500mV/div)

V_OUT1

WAKE-UP

(500mV/div)

Time (400μs/div)

DS20005887A-page 22

 2017 Microchip Technology Inc.

MIC7400

FIGURE 4-4:

Buck DVC Control Ramp.

EQUATION 4-4:

4.3

Programmable Boost Soft-Start

Control

t_SS= T1 + T2

V_OUT– 1.4V

The boost soft-start time is divided into two parts as

shown in Figure 4-5. T1 is a fixed 367 µs delay starting

from when the internal enable goes high. This delay

gives enough time for the disconnect switch to turn on

and bring the inductor voltage to V_INbefore the boost is

turned on. There is a 50 µs delay that is controlled by

the parasitic capacitance (C_GD) of the disconnect

switch before the output starts to rise.







------------------------------

T2 =

 t_RAMP



0.2V

12V – 1.4V







---------------------------

T2 =

 16s



0.2V

Where:

After the T1 period, the DAC output ramp starts, T2.

The total soft-start time, t_SS, is the sum of both periods.

Figure 4-6 displays the actual boost soft-start

waveform.

T1 = 367 µs

T2 = 848 µs

t_SS= 367 µs + 848 µs = 1.215 ms

V_OUT= Output voltage.

t

_RAMP= Output dwell time = 16 µs.

12V

4.4

Boost Digital Voltage Control

(DVC)

~ 50μs

t₁

~ V_IN

BOOST

12V

(PVIN6O)

The boost output control works the same way as the

buck, except that the voltage steps are 200 mV, see

Figure 4-7. When the boost is programmed to a lower

voltage the output ramps down at a rate determined by

the output ramp rate (t_RAMP), the output capacitance

and the external load. During both the ramp up and

down time, the power good output is blanked and if the

power good mask bit is set to “1”.

T2

T1

367μs

DAC

(INTERNAL)

EN6

(INTERNAL)

FIGURE 4-5:

Boost Soft-Start Ramp.

V_OUT

1.21ms

¨V_OUT

200mV

V_IN= 5.0V

V_OUT6= 12V

t_RAMP

V_OUT6

(2V/div)

I

_OUT6= 10mA

V_{OUT_INIT}

t_SS= 1.21ms

¨t

TIME

Time (200μs/div)

FIGURE 4-7:

Boost DVC Control Ramp.

FIGURE 4-6:

Boost Soft-Start.

The ramp time can be computed using the following

equation:

 2017 Microchip Technology Inc.

DS20005887A-page 23

MIC7400

EQUATION 4-5:

TABLE 4-3:

I_OUT(MAX)

BUCK CURRENT-LIMIT

REGISTER SETTINGS

V_OUT– V_{OUT_INIT}

I_PROG

BINARY

HEX









---------------------------------------------

t =

 t_RAMP

0.2V

0.5A

1.0A

1.5A

2.0A

2.5A

3.0A

1.1A

2.1A

3.1A

4.1A

5.1A

6.1A

1111

1101

1011

1001

0111

0101

F’h

D’h

B’h

9’h

7’h

5’h

Where:

V_{OUT_INIT}= Initial output voltage.

TABLE 4-2:

BOOST OUTPUT DEFAULT

SOFT-START TIME

The output can be turned back on by recycling the input

power or by software control. To clear the overcurrent

fault by software control, set the enable register bit to

“0” then clear the overcurrent fault by setting the fault

register bit to “0”. This will clear the overcurrent and

power good status registers. Now the output can be

re-enabled by setting the enable register bit to “1”.

—

V_OUT

t_RAMP

t_SS

V_OUT6

12V

16 µs

1.215 ms

4.5

Buck Current-Limit

The MIC7400 buck regulators have high-side

current-limiting that can be varied by a 4-bit code. If the

regulator remains in current-limit for more than seven

consecutive PWM cycles, the output is latched off, the

overcurrent status register bit is set to 1, the

power-good status register bit is set to 0 and the global

power good (PG) output pin is pulled low. An

overcurrent fault on one output will not disable the

remaining outputs. Table 4-3 shows the current-limit

register settings verses output current. The

current-limit register setting is set at twice the

maximum output current.

During start-up sequencing, once an overcurrent

condition is sensed, the fault register is set to “1” and

the start-up sequence will stop and no further outputs

will be enabled. See Figure 4-9 for default start-up

sequence.

4.6

Boost Current-Limit

The boost current-limit features cycle-by-cycle

protection. The duty cycle is cut immediately once the

current-limit is hit. When the boost current-limit is hit for

five consecutive cycles, the FAULT signal is asserted

and remains asserted with the boost converter keeping

on running until the boost is powered off.

This protects the boost in normal overload conditions,

but not in a short-to-ground case. For a short-circuit to

ground, the boost current-limit will not be able to limit

the inductor current. This short-circuit condition is

sensed by the current in the disconnect switch. When

the disconnect switch current limit is hit for four

consecutive master clock cycles (2 MHz), regardless if

the boost is switching or not, both the disconnect switch

and boost are latched off automatically and the FAULT

signal is asserted.

The output can be turned back on by recycling the input

power or by software control. To clear the overcurrent

fault by software control, set the enable register bit to

“0” then clear the overcurrent fault by setting the fault

register bit to “0”.

DS20005887A-page 24

 2017 Microchip Technology Inc.

MIC7400

through the initialization process. The DELAY register’s

STDEL bits set the delay between powering up each

regulator at initial power up.

4.7

Global Power Good Pin

The global power-good output indicates that all the

outputs are above the 91% limit after the power-up

sequence is completed. Once the power-up sequence

is complete, the global power good output stays high

unless an output falls below its power-good limit, a

thermal fault occurs, the input voltage drops below the

lower UVLO threshold or an output is turned OFF by

setting the enable register bit to “0” unless the

PGOOD_MASK[x] bit is set to “1” (Default).

The sequencing registers allow the outputs to come up

in any order. There are six time slots that an output can

be configured to power up in. Each time slot can be

programmed for up to six regulators to be turned on at

once or none at all.

Figure 4-9 shows an example of this feature. V_OUT4is

enabled in time slot 1. After a 1 ms delay, V_OUT2and

V_OUT3are enabled at the same time in time slot 2. The

1 ms is the standard delay for all of the outputs and can

be programmed from 0 ms to 7 ms in 1 ms steps. Next,

V_OUT1is powered up in time slot 3 and V_OUT5in time

slot 4. There are no regulators programmed for time

slot 5. Finally, V_OUT6is powered up in time slot 6. The

global power good output, V_PG, goes high as soon as

the last output reaches 91% of its final value.

A power-good mask bit can be used to control the

global power good output. The power-good mask

feature is programmed through the PGOOD_MASK[x]

registers and is used to ignore an individual

power-good fault. When masked, PGOOD_MASK[x]

bit is set to “1”, an individual power good fault will not

cause the global power good output to de-assert.

If all the PGOOD_MASK[x] bits are set to “1”, then the

power good output de-asserts as soon as the first

output starts to rise. The PGOOD_MASK[x] bit of the

last output must be set to “0” to have the PG output stay

low until the last output reaches 91% of its final value.

V_IN

V_IN= 3.3V

(2V/div)

V_OUT4

(1V/div)

V_OUT4= 1.05V/0.1A

V_OUT2= 1.1V/0.1A

The global power-good output is an open-drain output.

A pull-up resistor can be connected to V_INor V_OUT. Do

not connect the pull-up resistor to a voltage higher than

AV_IN.

V_OUT2

(1V/div)

V_OUT3= 1.8V/0.1A

V_OUT3

(1V/div)

4.8

Standard Delay

V_OUT1= 1.8V/0.1A

V_OUT1

(1V/div)

There is a programmable timer that is used to set the

standard delay time between each time slot. The timer

starts as soon as the previous time slot’s output power

good goes high. When the delay completes, the

regulators assigned to that time slot are enabled, see

Figure 4-8.

V

_OUT5= 1.8V/0.1A

V_OUT5

(1V/div)

V_OUT6= 1.8V/0.1A

V_OUT6

(5V/div)

V

(2V/di^Pv^G)

Time (1.0ms/div)

FIGURE 4-9:

Hot Plug – V Rising.

IN

V_OUT4

(500mV/div)

4.10 VSLT Pin

The power-on-reset threshold toggles between two

different ranges by driving the VSLT pin high or low.

The lower range of 2.25V to 3.25V is selected when the

VSLT pin is tied to ground. The upper range, 3.25V to

4.25V, is selected when the VSLT pin is tied to V_IN.

V_OUT2

(500mV/div)

4.11 Programmable Power-on-Reset

(POR) Delay

Time (400μs/div)

FIGURE 4-8:

Standard Delay Time.

The POR output pin provides the user with a way to let

the SOC know that the input power is failing. If the input

voltage falls below the power-on reset lower threshold

level, the POR output immediately goes low. The lower

threshold is set in the PORDN register and the upper

threshold uses PORUP register.

4.9

Power-Up Sequencing

When power is first applied to the MIC7400, all I²C

registers are loaded with their default values from the

EEPROM. There is about a 1.5 ms delay before the

first regulator is enabled while the MIC7400 goes

 2017 Microchip Technology Inc.

DS20005887A-page 25

MIC7400

The low-to-high POR transition can be delayed from

5 ms to 160 ms in 5 ms increments. This feature can be

used to signal the SOC that the power supplies are

stable. The PORDEL register sets the delay of the POR

pin. The POR delay starts as soon as the AVIN pin

voltage rises above the power-on reset upper threshold

limit. Figure 4-10 shows the POR operation.

4.13 Stand-By Mode

In stand-by mode, efficiency can be improved by

lowering the output voltage to the standby mode value

or turning an output off completely. There are two

registers used for setting the output voltage,

normal-mode register and stand-by mode register. The

default power-up voltages are set in the normal-mode

registers.

An I²C write command to the STBY_CTRL_REG

register or the STBY pin can be used to set the

MIC7400 into stand-by mode. Figure 4-12 shows an

I²C write command implementation. In stand-by mode,

the output can be programmed to a lower voltage or

turned completely off. When disabled, the output will be

soft-discharged to zero if the PULLD[1-6] register are

set to 1. If PULLD[x] = 0 the output drifts to PGND at a

rate determined by the load current and output

capacitance.

V_IN

(1V/div)

20ms

V_POR

(2V/div)

In stand-by, if an output is disabled, the global power

Time (10ms/div)

good

output

is

not

affected

when

the

FIGURE 4-10:

POR.

PGOOD_MASK[x] is set to logic 1. If the

PGOOD_MASK[x] is set to logic 0, then the global

power good flag is pulled low. In Figure 4-12, all the

PGOOD_MASK[x] bits are set to logic 1.

4.12 Power-Down Sequencing

When power is removed from V_IN, all the regulators try

to maintain the output voltage until the input voltage

falls below the UVLO limit of 2.35V as shown in

Figure 4-11.

V_SDA

(2V/div)

V

_IN= 3.3V

V_OUT4

V_IN

(2V/div)

(1V/div)

V_OUT4

(1V/div)

V_OUT4= 1.05V/0.1A

V_OUT2

(1V/div)

V

_OUT2= 1.1V/0.1A

V_OUT2

(1V/div)

V_OUT3

(1V/div)

V_OUT3

(1V/div)

V

_OUT3= 1.8V/0.1A

_OUT1= 1.8V/0.1A

V_OUT1

(1V/div)

V_OUT1

(1V/div)

V_OUT5= 1.25V/0.1A

V_OUT5

(1V/div)

V_OUT5

(1V/div)

V_OUT6

(10V/div)

V

_OUT6= 12V/0.1A

V_OUT6

(10V/div)

V

(2V/di^Pv^G)

V

(2V/di^Pv^G)

Time (1.0ms/div)

FIGURE 4-11:

Hot Unplug – V Falling.

IN

Time (1.0ms/div)

2

FIGURE 4-12:

I C Stand-by Mode.

DS20005887A-page 26

 2017 Microchip Technology Inc.

MIC7400

4.14 Resistive Discharge

Standby (STBY) – Wake-Up

To ensure a known output condition in stand-by mode,

the output is actively discharged to ground if the output

is disabled. Setting the buck pull down register field

PULLD[1-5] = 1 connects a 90ꢀ pull down resistor from

OUT[x] to PGND[x] when the MIC7400 is disabled. If

PULLD[x] = 0 the output drifts to PGND at a rate

determined by the load current and the output

capacitance value. The boost has a programmable

pull-down current level from 37 mA to 148 mA. In

Figure 4-13, the top trace shows the normal pull down

and the bottom trace is with the 90ꢀ pull-down.

V_STBY

(2V/div)

V_OUT4

(1V/div)

V_OUT2

(1V/div)

V_OUT3

(1V/div)

1k EXTERNAL

PULLDOWN

V_OUT1

(1V/div)

V_OUT5

(1V/div)

V_OUT5

(500mV/div)

90 INTERNAL

PULLDOWN

V_OUT6

(10V/div)

V_OUT5

(500mV/div)

V

(2V/di^Pv^G)

Time (200μs/div)

Time (10ms/div)

FIGURE 4-13:

Output Pull-Down

FIGURE 4-14:

STBY-to-NORMAL

Resistance.

Transition (DEFAULT).

4.15 STBY Pin

4.16 Safe Start-Up into a Pre-Biased

Output

A pin-selectable STBY input allows the MIC7400 to be

placed into standby or normal mode. In standby mode,

the individual regulator can be turned on or off or the

output voltage can be set to a different value. If the

regulators are turned off, standby mode cuts the

quiescent current by 23 µA for each buck regulator and

70 µA for the boost.

The MIC7400 is designed for safe start-up into a

pre-biased output. This prevents large negative

inductor currents that can cause the output voltage to

dip and excessive output voltage oscillations. A zero

crossing comparator is used to detect a negative

inductor current. If a negative inductor current is

detected, the low-side synchronous MOSFET

functions as a diode and is immediately turned off.

Figure 4-14 illustrates the STBY pin operation. A

low-to-high transition on the STBY pin switches the

output from standby mode to normal mode. There is a

100 µs STBY de-glitch time to eliminate nuisance

tripping then all the regulators are enabled at the same

time and ramp up with their programmed ramp rates. A

high-to-low transition on the STBY pin switches the

output from normal mode to standby mode.

Figure 4-15 shows a 1V output pre-bias at 0.5V at

start-up, see V_OUT4trace. The inductor current, trace

I_L4, is not allowed to go negative by more than 0.5A

before the low-side switch is turned off. This feature

prevents high negative inductor current flow in a

pre-bias condition which can damage the IC.

 2017 Microchip Technology Inc.

DS20005887A-page 27

MIC7400

4.18 Total Power Dissipation

The total power dissipation in the MIC7400 package is

equal to the sum of the power loss of each regulator:

EQUATION 4-8:

P_{D_TOTAL} SUMP_{D_SWITCHERS}



Once the total power dissipation is calculated, the IC

junction temperature can be estimated using

Equation 4-9:

FIGURE 4-15:

Pre-Biased Output Voltage.

4.17 Buck Regulator Power Dissipation

EQUATION 4-9:

The total power dissipation in a MIC7400 is a

combination of the five buck regulators and the boost

dissipation. The buck regulators (OUT1 to OUT5)

dissipation is approximately the switcher’s input power

minus the switcher’s output power and minus the

power loss in the inductor:

T

_JMAX T_A+ P_{D_TOTAL} _JA

Where:

T_J(MAX)= The maximum junction temperature.

T_A= The ambient temperature.

EQUATION 4-6:

θ_JA= The junction-to-ambient thermal resistance

of the package (30°C/W).

P_{D_BUCK} V_IN I_IN– V_OUT I_OUT– P_{L_LOSS}

Figure 4-16 shows the measured junction temperature

versus power dissipation of the MIC7400 evaluation

board. The actual junction temperature of the IC

depends upon many factors. The significant factors

influencing the die temperature rise are copper

thickness in the PCB, the surface area available for

convection heat transfer, air flow and power dissipation

from other components, including inductors, SOCs and

processor ICs. It is good engineering practice to

measure all power components temperature during the

final design review using a thermal couple or IR

thermometer, see the Thermal Measurements

sub-section for details.

While the boost power dissipation is estimated by

Equation 4-7:

EQUATION 4-7:

P_{D_BOOST} V_IN I_IN– V_OUT I_OUT– P_{L_LOSS}

– V_f I_OUT

Although the maximum output current for a single buck

regulator can be as much as 3A, the MIC7400 will

thermal limit and will not support this high output

current on all outputs at the same time.

DS20005887A-page 28

 2017 Microchip Technology Inc.

MIC7400

4.20 Overtemperature Fault

140

120

100

80

An overtemperature fault is triggered when the IC

junction temperature reaches 160°C. When this

occurs, both the overtemperature fault flag is set to “1”,

the global power good output is pulled low and all the

outputs are turned off. During the fault condition the I²C

interface remains active and all registers values are

maintained.

y = 30.866x + 24.869

60

When the die temperature decreases by 20°C the

overtemperature fault bit can be cleared. To clear the

fault, either recycle power or write a logic “0” to the over

temperature fault register. Once the fault bit is cleared,

the outputs power up to their default values and are

sequenced according to the time slot settings.

40

T_A= 25°C

20

0

1

2

3

4

POWER DISSIPATION (W)

4.21 Input Voltage “Hot Plug”

FIGURE 4-16:

Power Dissipation.

High voltage spikes of twice the input voltage can

appear on the MIC7400 PVIN pins if a battery pack is

hot-plugged to the input supply voltage connection as

shown in Figure 4-18 (Trace 1). These spikes are due

to the inductance of the wires to the battery and the

very low inductance and ESR of the ceramic input

capacitors. This problem can be solved by placing a

150 µF POS capacitor across the input terminals.

Figure 4-18 (Trace 2) shows that the high voltage spike

is greatly reduced to a value below the maximum

allowable input voltage rating.

4.19 Power Derating

The MIC7400 package has a 2W power dissipation

limit. To keep the IC junction temperature below a

125°C design limit, the output power has to be limited

above an ambient temperature of 65°C. Figure 4-17

shows the power dissipation derating curve.

140

120

100

80

60

40

20

0

0.5

1

1.5

2

2.5

POWER DISSIPATION (W)

FIGURE 4-17:

Power Derating Curve.

FIGURE 4-18:

Spike.

Hot Plug Input Voltage

The maximum power dissipation of the package can be

calculated by Equation 4-10:

4.22 Thermal Measurements

EQUATION 4-10:

Measuring the IC’s case temperature is recommended

to ensure it is within its operating limits. Although this

might seem like a very elementary task, it is easy to get

erroneous results. The most common mistake is to use

the standard thermal couple that comes with a thermal

meter. This thermal couple wire gauge is large

(typically 22 gauge) and behaves like a heatsink,

resulting in a lower case measurement.

T

_JMAX– T_A

-------------------------------

_DMAX

P

_JA

Where:

T_J(MAX)= The maximum junction temperature

(125°C).

T_A= The ambient temperature.

θ_JA= The junction-to-ambient thermal resistance

of the package (30°C/W).

 2017 Microchip Technology Inc.

DS20005887A-page 29

MIC7400

Two reliable methods of temperature measurement are

a

smaller thermal couple wire or an infrared

thermometer. If a thermal couple wire is used, it must

be constructed of 36 gauge wire or higher (smaller wire

size) to minimize the wire heat-sinking effect. In

addition, the thermal couple tip must be covered in

either thermal grease or thermal glue to make sure that

the thermal couple junction is making good contact with

the case of the IC. Omega brand thermal couple

(5SC-TT-K-36-36) is adequate for most applications.

Whenever possible, an infrared thermometer is

recommended. The measurement spot size of most

infrared thermometers is too large for an accurate

reading on a small form factor ICs. However, an IR

thermometer from Optris has a 1 mm spot size, which

makes it a good choice for measuring the hottest point

on the case. An optional stand makes it easy to hold the

beam on the IC for long periods of time.

DS20005887A-page 30

 2017 Microchip Technology Inc.

MIC7400

5.0

5.1

TIMING DIAGRAMS

Normal Power-Up Sequence for Outputs

The STDEL register sets the delay between powering up of each regulator at initial power-up (see power-up sequencing

in Figure 5-1). Once all the internal power good registers PGOOD[1-6] are all “1”, then the global PG pin goes high

without delay (see the Global Power Good Pin section for more information).

The PORDEL register sets the delay for the POR flag pin. The POR delay time starts as soon as the AV_INpin voltage

rises above the system UVLO upper threshold set by the PORUP register. The POR output goes low without delay if

AV_INfalls below the lower UVLO threshold set by the PORDN register.

POR UPPER

THRESHOLD

POR LOWER

THRESHOLD

2.7V

2.6V

2.35V

UVLO RISING

UVLO FALLING

2.3V

t_{POR_DELAY}

20ms

V_IN

BOOT-LOAD TIME

2ms

V_POR

t_DLY

1ms

t_SS

V_OUT1

t_DLY

1ms

t_SS

V_OUT2

t_DLY

1ms

t_SS

V_OUT3

t_DLY

1ms

t_SS

V_OUT4

t_DLY

1ms

t_SS

V_OUT5

t_SS

t_DLY

1ms

V_OUT6

V_PG

FIGURE 5-1:

MIC7400 Power-Up/Down.

 2017 Microchip Technology Inc.

DS20005887A-page 31

MIC7400

5.2

Standby (STBY) Pin (Wake-Up)

An I²C write command to the STBY_CTRL_REG register or the STBY pin can be used to set the MIC7400 into standby

mode. The standby (STBY) pin provides a hardware-specific manner in which to wake-up from stand-by mode and go

into normal mode. Figure 5-2 shows the STBY pin operation. A low-to-high transition on the STBY pin switches the

output from stand-by mode to normal mode.

There is a 100 µs STBY deglitch time to eliminate nuisance tripping, then all the regulators are enabled at the same time

and ramp up with their programmed ramp rates.

V

(DEFAU^SL^TT^BY)

0V

FORCES

03h BIT [6] = ‘1’

ALL CHANNELS ARE FORCED TO

ALL CHANNELS RETURN TO

THEIR DEFAULT STATE

THEIR STANDBY STATES

V_STBY

(INVP)

0V

t_SS

V_OUT1

0V

t_SS

V_OUT2

t_SS

V_OUT3

0V

t_SS

V_OUT4

t_SS

V_OUT5

t_SS

V_OUT6

0V

PG

POWER GOOD IS MASKED

PGOOD_MASK [1-6] = ‘1’

FIGURE 5-2:

MIC7400 STBY Function (DEFAULT).

DS20005887A-page 32

 2017 Microchip Technology Inc.

MIC7400

• If possible, place vias to the ground plane close to

the each input capacitor ground terminal, but not

in the way of the high di/dit current path.

6.0

PCB LAYOUT GUIDELINES

PCB layout is critical to achieve reliable, stable, and

efficient performance. A ground plane is required to

control EMI and minimize the inductance in power,

signal, and return paths.

• Use either X7R or X5R dielectric input capacitors.

Do not use Y5V or Z5U type capacitors.

• Do not replace the ceramic input capacitor with

any other type of capacitor. Any type of capacitor

can be placed in parallel with the input capacitor.

To minimize EMI and output noise, follow these layout

recommendations to ensure proper operation:

• In “Hot-Plug” applications, a Tantalum or

Electrolytic bypass capacitor must be used to limit

the over-voltage spike seen on the input supply

with power is suddenly applied.

6.1

General

• Most of the heat removed from the IC is due to the

exposed pad (EP) on the bottom of the IC

conducting heat into the internal ground planes

and the ground plane on the bottom side of the

board. Use at least 16 vias for the EP to ground

plane connection.

6.4

Inductor

• Keep the inductor connection to the switch node

(SW) short.

• Do not connect the PGND and AGND traces

together on the top layer. The single point

connection is made on the layer 2 ground plane.

• Do not route any digital lines underneath or close

to the inductor.

• To minimize noise, place a ground plane

underneath the inductor.

• Do not put a via directly in front of a high current

pin, SW, PGND, or PVIN. This will increase the

trace resistance and parasitic inductance.

6.5

Output Capacitor

• Do not place a via in between the input and output

capacitor ground connection. Put it to the inside of

the output capacitor and in the way of the high

di/dt current path.

• Use a wide trace to connect the output capacitor

ground terminal to the input capacitor ground

terminal.

• Route all power traces on the top layer.

• The OUT[1-6] trace should be separate from the

power trace and connected as close as possible

to the output capacitor. Sensing a long

high-current load trace can degrade the DC load

regulation.

• Place the input capacitors first and put them as

close as possible to the IC.

6.2

IC

• The 2.2 µF ceramic capacitor, which is connected

to the AVIN pin, must be located right at the IC.

The AVIN pin is very noise sensitive and

placement of the capacitor is very critical. Use

wide traces to connect to the AVIN and AGND

pins.

• The analog ground pin (AGND) must be

connected directly to the ground planes. Do not

route the SGND pin to the PGND Pad on the top

layer.

• Use wide traces to route the input and output

power lines.

• Use Layer 5 as an input voltage power plane.

• Layer 2 and the bottom layer (Layer 6) are ground

planes.

6.3

Input Capacitor

• A 10 µF X5R or X7R dielectrics ceramic capacitor

is recommended on each of the PVIN pins for

bypassing.

• Place the input capacitors on the same side of the

board and as close to the IC as possible.

• Keep both the PVIN pin and PGND connections

short.

 2017 Microchip Technology Inc.

DS20005887A-page 33

MIC7400

6.6

Proper Termination of Unused Pins

Many designs will not require all six DC/DC output voltages. In these cases, the unused pin must be connected to either

VIN or GND. The schematic in Figure 6-1 shows where to tie the unused pins and Table 6-1 summarizes the

connections.

VIN

+

C15

150μF

R7

0ȍ

PGND

R6

499kȍ

VIN

C1

2.2μF

R1

100kȍ

VSLT

PG

2

VSLT

26

29

VIN

PVIN2

PVIN1

VIN

C9

L2

OUT1

10μF

2.2μH

V_OUT2

1.1V/0.5A

1

3

SW2

27

28

SW1

C10

22μF

OUT2

PGND2

36

PGND

VIN

PGND1

MIC7400

4

PVIN3

25

PVIN6

VIN

C11

10μF

L3

2.2μH

V_OUT3

1.8V/0.5A

5

7

6

SW3

24

23

PVIN6O

SW6

C12

22μF

OUT3

PGND3

PGND

VIN

22

21

20

PGND6

OUT6

8

PVIN4

C13

10μF

L4

1.0μH

PVIN5

VIN

V_OUT4

1.05V/2.5A

9

11

10

SW4

C7

10μF

L5

C14

22μF

2.2μH

OUT4

PGND4

19

17

18

V_OUT5

SW5

OUT5

1.25V/1.0A

PGND

C8

22μF

VIN

PGND5

PGND

VIN

R4

100kȍ

VIN

TP14

R8

NF

R5

2kȍ

R3

2kȍ

4

3

SDA

CLK

VIN

2

1

NC

STAND-BY

POR

GND

PG

VSLT

FIGURE 6-1:

Connections for Unused Pins.

SUMMARIZATION OF UNUSED PIN CONNECTIONS

TABLE 6-1:

Unused

VIN

PGND

Boost

Buck

POR

PVIN6, PGIN6O, VOUT6

PVIN[x], VOUT[x}

—

PGND6, SW6

PGND[6], SW[x]

POR

DS20005887A-page 34

 2017 Microchip Technology Inc.

MIC7400

2

7.0

I C CONTROL REGISTER

The MIC7400 I²C Read/Write registers are detailed here. During normal operation, the configuration data can be saved

into non-volatile registers in EEPROM by addressing the chip and writing to SAVECONFIG key = 66’h. Saving CONFIG

data to EEPROM takes time so the external host should poll the MIC7400 and read the CONFIG bit[1] of EEPROM

Ready register 01’h to determine the end of programming.

All transactions start with a control byte sent from the I²C master device. The control byte begins with a START

condition, followed by a 7-bit slave address. The slave address is seven bits long followed by an eighth bit which is a

data direction bit (R/W), a “0” indicates a transmission (WRITE) and a “1” indicates a request for data (READ). A data

transfer is always terminated by a STOP condition that is generated by the master.

7.1

Serial Port Operation

7.1.1

EXTERNAL HOST INTERFACE

Bidirectional I²C port capable of Standard (up to 100 kbits/s), Fast (up to 400 kbits/s), Fast Plus (up to 1 Mbit/s) and High

Speed (up to 3.4 Mbit/s) as defined in the I²C-Bus Specification.

The MIC7400 acts as an I²C slave when addressed by the external host. The MIC7400 slave address uses a fixed 7-bit

code and is followed by an R/W bit which is part of the control word that is right after the start bit as shown in Figure 7-1

in the Device Address column.

The MIC7400 can receive multiple data bytes after a single address byte and automatically increments its register

pointer to block fill internal volatile memory. Byte data is latched after individual bytes are received so multi-byte transfers

could be corrupted if interrupted mid-stream.

No system clock is required by the digital core for I²C access from the external host (only the host SCL clock is

assumed).

In order to prevent spurious operation of the I²C, if a start bit is seen, then any partial communication is aborted and

new I²C data is allowed. Start bit is when SDA goes low when SCL is high. Stop bit is when SDA goes high when SCL

is high. Normal I²C exchange is shown in Figure 7-1.

FIGURE 7-1:

Read/Write Protocol.

 2017 Microchip Technology Inc.

DS20005887A-page 35

MIC7400

2

7.1.2

SPECIAL HOST I C COMMANDS

The following commands are all 2 byte communications:

• Byte1 = Device address with write bit set, LSB = 0.

• Byte2 = Special key.

Special keys include the following:

• SAVECONFIG Key = 66’h. Saves the shadow register configuration data into EEPROM registers 03’h through

23’h.

• RESET Key = 6A’h. Reloads only NORMAL mode voltage and current limit settings then enables the regulator to

NORMAL mode with no soft-start, no sequencing, and no delays. Then it clears the STANDBY register bit 6 in

register 03’h.

• RELOAD Key = 6B’h. Reloads all data from EEPROM into the shadow registers. No other actions are performed,

including soft-start, sequencing, and delay.

• REBOOT Key = 6C’h. Turns all regulators OFF, reloads EEPROM data into shadow registers, then re-sequences

the regulators with the programmed soft-start and sequence delays.

• SEQUENCE Key = 6D’h. Turns all regulators OFF, restarts the sequencer including soft-start and sequence

delays.

OBS: In order to use the Special Keys, FORCE_CLK_ON bit 2 of the Internal Clock control register (0x2F’h) must be

set to “1”. After the action has completed, the FORCE_CLK_ON bit can be cleared by writing “0”.

DS20005887A-page 36

 2017 Microchip Technology Inc.

MIC7400

8.0

8.1

REGISTER SETTINGS DESCRIPTIONS

Power Good Register (00’h)

This register indicates when the regulators 1 – 6 output voltage is above 91% of the target value. The MIC7400

deglitches the input signal for 50 µs in order to prevent false events. The global PG pin indicator is functional ‘AND’ of

all the power good indicators during sequencing. Once the power-up sequence is complete, the global power good

output stays high unless an output falls below its power-good limit, a thermal fault occurs, the input voltage drops below

the lower UVLO threshold or an output is turned OFF by setting the enable register bit to “0” if the PGOOD_MASK[x]

bit is set to “0”.

TABLE 8-1:

POWER GOOD STATUS REGISTER

PGOOD1-6_REG

Register Name

Power Good Status Register

0x00’h

Address

Field

—

Bit

R/W

Default

Description

Power Good indicator for Regulator 1

PGOOD1

PGOOD2

PGOOD3

PGOOD4

PGOOD5

PGOOD6

0

R

0

0 = Buck Not Valid

Power Good indicator for Regulator 2

0 = Buck Not Valid 1 = Buck Valid

Power Good indicator for Regulator 3

0 = Buck Not Valid 1 = Buck Valid

Power Good indicator for Regulator 4

0 = Buck Not Valid 1 = Buck Valid

Power Good indicator for Regulator 5

0 = Buck Not Valid 1 = Buck Valid

Power Good indicator for Regulator 6

0 = Boost Not Valid 1 = Boost Valid

1 = Buck Valid

1

2

3

4

5

R

0

Reserved

6

7

R/W

0

Not Used

—

8.2

EEPROM-Ready Register (01’h)

This register indicates the status of EEPROM to external I²C host.

The READY bit = 1 when the Trim and Configuration data have been loaded into core from EEPROM after reset, reboot

or reload and the chip is ready for operation. If the SAVE1 bit in register 04’h is read in as logic 1, the configuration

registers will not be loaded from the EEPROM memory and the READY bit will still get set indicating that any startup

procedure involving the EEPROM memory is complete. The READY bit will be set to 1 after loading or attempting to

load Trim and Configuration data from EEPROM into volatile memory. The Trim data will always be loaded and if SAVE1

bit in register 04’h is set to logic 0, Configuration data is also loaded. Regardless of the SAVE1 bit being set or not, after

the loading operation the READY bit is set to 1.

The CONFIG bit = 1 when the Configuration data have been saved to EEPROM after the SAVECONFIG Code is issued

from the Host. If CONFIG=1 before the SAVECONFIG code is issued, CONFIG will be cleared immediately and then

will be set to logic 1 again once all Configuration data is written to the EEPROM memory.

The EEPREAD and EEPWRITE bits indicate if an EEPROM read or write fault has occurred. These bits should be read

and cleared prior to reloading data from the EEPROM memory.

 2017 Microchip Technology Inc.

DS20005887A-page 37

MIC7400

TABLE 8-2:

EEPROM STATUS REGISTER

Register Name

STATUS_REG

—

EEPROM Status Register

0x01’h

Address

Field

Bit

R/W

Default

Description

Indicate ready for operation when the trim and configuration data

has been loaded.

READY

0

R

0

0 = Data not loaded

Indicate Configuration saved to EEPROM

0 = Configuration not saved 1 = Configuration saved

Not Used

1 = Chip ready

CONFIG

1

R

0

Reserved

2

3

4

5

R

0

—

R/W

Not Used

—

EEPROM Read

EEPROM Write

EEPREAD

EEPWRITE

6

7

R/W

0

0 = No Fault

1 = Fault

8.3

Fault Registers (02’h)

This register indicates the overcurrent flag for each regulator and one global overtemperature (OT). These register bits

are set by an overcurrent condition and reset by writing a logic “0” to each bit by the I²C host. The respective channel

must be restarted to enter normal functionality in order to successfully clear the over current fault.

If the fault condition persists, the bit will be set to logic “1” again immediately by the MIC7400 after it is written to logic

“0” by the host.

TABLE 8-3:

OVERCURRENT STATUS FAULT REGISTER

Register Name

FAULT_REG

Overcurrent Status Fault Register

Address

Field

—

0x02’h

Bit

R/W

Default

Description

Regulator 1 Overcurrent

REG1OC

REG2OC

REG3OC

REG4OC

REG5OC

0

R/W

0

0 = No Fault

Regulator 2 Overcurrent

0 = No Fault

Regulator 3 Overcurrent

0 = No Fault

Regulator 4 Overcurrent

0 = No Fault

Regulator 5 Overcurrent

0 = No Fault

Regulator 6 Overcurrent

0 = No Fault

1 = Fault

1

2

3

4

0

REG6OC

Reserved

OT

5

6

7

R/W

0

1 = Fault

—

Reserved

Overtemperature

0 = No Fault

1 = Fault

DS20005887A-page 38

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MIC7400

8.4

Standby Register (03’h)

This register controls standby mode operation. Global standby mode can either be enabled by I²C or by changing the

logic state of the STBY input pin. Global standby is controlled by the STBY_MODEB bit. When STBY_MODEB [6] = 1

then the regulators output voltages are set to their normal mode output voltage settings, (05’h – 0A’h) registers. When

STBY_MODEB [6] = 0 then regulators output voltages are set to the standby mode output voltage settings, (0B’h – 10’h)

registers. If STBY [1-6] register is set to logic “0”, then the output is shut off in standby mode.

The global power good flag is asserted when an output is disabled unless the power good mask bit (PGOOD_MASK[x])

is set to 1.

TABLE 8-4:

STANDBY REGISTER

STBY_CTRL_REG

Register Name

Standby Register

0x03’h

Address

Field

—

Bit

R/W

Default

Description

Regulator 1 Standby Voltage Control

STBY1

STBY2

STBY3

STBY4

STBY5

STBY6

0

R/W

1

0 = OFF

Regulator 2 Standby Voltage Control

0 = OFF 1 = ON

Regulator 3 Standby Voltage Control

0 = OFF 1 = ON

Regulator 4 Standby Voltage Control

0 = OFF 1 = ON

Regulator 5 Standby Voltage Control

0 = OFF 1 = ON

Regulator 6 Standby Voltage Control

0 = OFF 1 = ON

1 = ON

1

2

3

4

5

R/W

1

Global Standby Control

STBY_MODEB

SAVE1

6

7

R/W

1

0

0 = All regulators in Standby

1 = All regulators in Normal

Mode

Save Configuration

0 = Configuration Saved to

EEPROM

1 = Configuration Not Saved to

EEPROM

8.5

Enable/Disable Register (04’h)

This register controls the enable/disable of each DC/DC regulators. When EN(n) bit transitions from “0” to “1”, then the

regulator(n) is enabled with soft-start unless the STBY_MODEB register bit in register 03’h is set to logic “0”.

The configuration save bit “SAVE1” should be cleared by customer before saving configuration data to EEPROM. This

bit is used during power up to indicate via the Status register (00’h) that configuration data has previously been stored.

TABLE 8-5:

ENABLE REGISTER

EN_REG

Register Name

Enable Register

0x04’h

Address

Field

—

Bit

R/W

Default

Description

Regulator 1 ON/OFF Control bit

EN1

EN2

EN3

0

R/W

1

0 = OFF

Regulator 2 ON/OFF Control bit

0 = OFF 1 = ON

Regulator 3 ON/OFF Control

0 = OFF 1 = ON

1 = ON

1

2

R/W

1

 2017 Microchip Technology Inc.

DS20005887A-page 39

MIC7400

TABLE 8-5:

ENABLE REGISTER (CONTINUED)

Register Name

EN_REG

—

Enable Register

0x04’h

Address

Field

Bit

R/W

Default

Description

Regulator 4 ON/OFF Control

EN4

EN5

EN6

3

R/W

1

0 = OFF

Regulator 5 ON/OFF Control

0 = OFF 1 = ON

Regulator 6 ON/OFF Control

1 = ON

4

5

1

0 = OFF

1 = ON

—

Reserved

6

7

R/W

0

Not Used

—

8.6

Regulator Output Voltage Setting NORMAL Mode (05’h – 09’h)

One register for each regulator output (OUT1 – OUT5). Sets output voltage of regulator for NORMAL mode operation.

TABLE 8-6:

DVC REGISTERS FOR OUT[1 – 5]

OUT1-5_REG

Register

Name

DVC Registers for OUT[1-5]

OUT1 = 0x05’h; OUT2 = 0x06’h; OUT3 = 0x07’h

OUT4 = 0x08’h; OUT5 = 0x09’h

Address

Field

—

Bit

R/W

Default

Description

Output Voltage setting of OUT[1-5]

DVC from 3.3V to 0.8V in –50 mV steps

000000 = 3.30V 010000 = 2.50V 100000 = 1.70V 110000 = 0.90V

000001 = 3.25V 010001 = 2.45V 100001 = 1.65V 110001 = 0.85V

000010 = 3.20V 010010 = 2.40V 100010 = 1.60V 110010 = 0.80V

000011 = 3.15V 010011 = 2.35V 100011 = 1.55V 110011 = 0.80V

000100 = 3.10V 010100 = 2.30V 100100 = 1.50V 110100 = 0.80V

000101 = 3.05V 010101 = 2.25V 100101 = 1.45V 110101 = 0.80V

000110 = 3.00V 010110 = 2.20V 100110 = 1.40V 110110 = 0.80V

000111 = 2.95V 010111 = 2.15V 100111 = 1.35V 110111 = 0.80V

001000 = 2.90V 011000 = 2.10V 101000 = 1.30V 111000 = 0.80V

001001 = 2.85V 011001 = 2.05V 101001 = 1.25V 111001 = 0.80V

001010 = 2.80V 011010 = 2.00V 101010 = 1.20V 111010 = 0.80V

001011 = 2.75V 011011 = 1.95V 101011 = 1.15V 111011 = 0.80V

001100 = 2.70V 011100 = 1.90V 101100 = 1.10V 111100 = 0.80V

001101 = 2.65V 011101 = 1.85V 101101 = 1.05V 111101 = 0.80V

001110 = 2.60V 011110 = 1.80V 101110 = 1.00V 111110 = 0.80V

OUT1 = 011110

(1.8V)

OUT2 = 101100

(1.1V)

OUT3 = 011110

(1.8V)

OUT4 = 101101

(1.05V)

OUT[1-5]

5:0

R/W

OUT5 = 101001

(1.25V)

001111 = 2.55V

011111 = 1.75V

101111 = 0.95V

111111 = 0.80V

—

6

7

—

0

Not Used

—

DS20005887A-page 40

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MIC7400

8.7

Boost Regulator Output Voltage Setting NORMAL Mode (0A’h)

Sets output voltage of the boost regulator (OUT6) in NORMAL mode operation.

TABLE 8-7:

DVC REGISTERS FOR OUT6

OUT6_REG

Register Name

DVC Registers

0x0A’h

Address

Field

—

Bit

R/W

Default

Description

DVC from 14V to 7V in 200 mV decrements

000000 = 14.0V 010000 = 10.8V

100000 = 7.6V

100001 = 7.4V

100010 = 7.2V

100011 = 7.0V

100100 = 7.0V

100101 = 7.0V

100110 = 7.0V

100111 = 7.0V

101000 = 7.0V

101001 = 7.0V

101010 = 7.0V

101011 = 7.0V

101100 = 7.0V

101101 = 7.0V

101110 = 7.0V

101111 = 7.0V

110000 = 7.0V

000001 = 13.8V 010001 = 10.6V

000010 = 13.6V 010010 = 10.4V

000011 = 13.4V 010011 = 10.2V

000100 = 13.2V 010100 = 10.0V

110001 = 7.0V

110010 = 7.0V

110011 = 7.0V

110100 = 7.0V

110101 = 7.0V

110110 = 7.0V

110111 = 7.0V

111000 = 7.0V

111001 = 7.0V

111010 = 7.0V

111011 = 7.0V

111100 = 7.0V

111101 = 7.0V

111110 = 7.0V

111111 = 7.0V

000101 = 13.0V

000110 = 12.8V

000111 = 12.6V

001000 = 12.4V

001001 = 12.2V

001010 = 12.0V

001011 = 11.8V

001100 = 11.6V

001101 = 11.4V

001110 = 11.2V

001111 = 11.0V

010101 = 9.8V

010110 = 9.6V

010111 = 9.4V

011000 = 9.2V

011001 = 9.0V

011010 = 8.8V

011011 = 8.6V

011100 = 8.4V

011101 = 8.2V

011110 = 8.0V

011111 = 7.8V

001010

(12V)

OUT6

5:0

R/W

—

6

7

—

0

Not Used

—

 2017 Microchip Technology Inc.

DS20005887A-page 41

MIC7400

8.8

Regulator Voltage Setting STBY Mode (0B’h – 0F’h)

This register is used to sets the output voltage of regulators 1 – 5 in STBY mode operation.

TABLE 8-8:

STANDBY REGISTERS

STBY_OUT1-5_REG

Register

Name

Standby DVC Registers

OUT1 = 0x0B’h; OUT2 = 0x0C’h; OUT3 = 0x0D’h

OUT4 = 0x0E’h; OUT5 = 0x0F’h

Address

Field

—

Bit

R/W

Default

Description

Output Voltage setting of OUT[1-5]

DVC from 3.3V to 0.8V in –50 mV steps

000000 = 3.30V 010000 = 2.50V 100000 = 1.70V 110000 = 0.90V

000001 = 3.25V 010001 = 2.45V 100001 = 1.65V 110001 = 0.85V

000010 = 3.20V 010010 = 2.40V 100010 = 1.60V 110010 = 0.80V

000011 = 3.15V 010011 = 2.35V 100011 = 1.55V 110011 = 0.80V

000100 = 3.10V 010100 = 2.30V 100100 = 1.50V 110100 = 0.80V

000101 = 3.05V 010101 = 2.25V 100101 = 1.45V 110101 = 0.80V

000110 = 3.00V 010110 = 2.20V 100110 = 1.40V 110110 = 0.80V

000111 = 2.95V 010111 = 2.15V 100111 = 1.35V 110111 = 0.80V

001000 = 2.90V 011000 = 2.10V 101000 = 1.30V 111000 = 0.80V

001001 = 2.85V 011001 = 2.05V 101001 = 1.25V 111001 = 0.80V

001010 = 2.80V 011010 = 2.00V 101010 = 1.20V 111010 = 0.80V

001011 = 2.75V 011011 = 1.95V 101011 = 1.15V 111011 = 0.80V

001100 = 2.70V 011100 = 1.90V 101100 = 1.10V 111100 = 0.80V

001101 = 2.65V 011101 = 1.85V 101101 = 1.05V 111101 = 0.80V

OUT1 = 011110

(1.8V)

OUT2 = 101100

(1.1V)

OUT3 = 011110

(1.8V)

OUT4 = 101101

(1.05V)

SB_OUT

[1-5]

5:0

R/W

OUT5 = 101001

(1.25V)

001110 = 2.60V 011110 = 1.80V 101110 = 1.00V

001111 = 2.55V 011111 = 1.75V 101111 = 0.95V

111110 = 0.80V

111111 = 0.80V

—

6

7

—

0

Not Used

—

DS20005887A-page 42

 2017 Microchip Technology Inc.

MIC7400

8.9

Boost Regulator Output Voltage Setting STBY Mode (10’h)

Sets output voltage of the boost regulator (OUT6) for STBY mode operation.

TABLE 8-9:

STANDBY DVC REGISTER FOR OUT6

STBY_OUT6_REG

Register Name

DVC Registers

0x10’h

Address

Field

—

Bit

R/W

Default

Description

DVC from 14V to 7V in 200 mV decrements

000000 = 14.0V 010000 = 10.8V

100000 = 7.6V

100001 = 7.4V

100010 = 7.2V

100011 = 7.0V

100100 = 7.0V

100101 = 7.0V

100110 = 7.0V

100111 = 7.0V

101000 = 7.0V

101001 = 7.0V

101010 = 7.0V

101011 = 7.0V

101100 = 7.0V

101101 = 7.0V

101110 = 7.0V

101111 = 7.0V

110000 = 7.0V

000001 = 13.8V 010001 = 10.6V

000010 = 13.6V 010010 = 10.4V

000011 = 13.4V 010011 = 10.2V

000100 = 13.2V 010100 = 10.0V

110001 = 7.0V

110010 = 7.0V

110011 = 7.0V

110100 = 7.0V

110101 = 7.0V

110110 = 7.0V

110111 = 7.0V

111000 = 7.0V

111001 = 7.0V

111010 = 7.0V

111011 = 7.0V

111100 = 7.0V

111101 = 7.0V

111110 = 7.0V

111111 = 7.0V

000101 = 13.0V

000110 = 12.8V

000111 = 12.6V

001000 = 12.4V

001001 = 12.2V

001010 = 12.0V

001011 = 11.8V

001100 = 11.6V

001101 = 11.4V

001110 = 11.2V

001111 = 11.0V

010101 = 9.8V

010110 = 9.6V

010111 = 9.4V

011000 = 9.2V

011001 = 9.0V

011010 = 8.8V

011011 = 8.6V

011100 = 8.4V

011101 = 8.2V

011110 = 8.0V

011111 = 7.8V

001010

(12V)

SB_OUT6

5:0

R/W

—

6

7

—

0

Not Used

—

8.10 Sequence Register (11’h)

Each regulator can be assigned to start in any one of six sequencing slots (1 to 6). If starting in slot 1, the regulator starts

immediately. If starting in any other slot, the regulator must wait for the PGOOD = 1 flags of all regulators assigned to

the preceding slot and then wait for the specified delay time (register 17’h) i.e., all PGOODs in preceding state flag then

the delay timer is started and when delay completes the regulator is enabled.

Each regulator will delay its startup (after the appropriate preceding PGOOD flags) by the delay set in the Delay Register

(17’h), unless the regulator is assigned to sequence state 0.

If all default Enable bits = 0 the IC starts up, but no outputs are enabled.

Sequencing is only used during initial startup, and not used when outputs are enabled via I²C command. If outputs are

enabled via I²C, then soft-start is still active, but start-up delays (timed from preceding PGOODs) are not.

TABLE 8-10: SEQUENCE STATE 1 REGISTER

Register Name

Address

SEQ1_REG

Sequence Register

0x11’h

—

Field

Bit

R/W

Default

Description

1 = Regulator 1 will Start in

REG1SQ1

REG2SQ1

REG3SQ1

0

R/W

0

0 = No Start

Sequence State 1

1 = Regulator 2 will Start in

Sequence State 1

1

2

0

1 = Regulator 3 will Start in

Sequence State 1

 2017 Microchip Technology Inc.

DS20005887A-page 43

MIC7400

TABLE 8-10: SEQUENCE STATE 1 REGISTER (CONTINUED)

Register Name

Address

SEQ1_REG

Sequence Register

0x11’h

—

Field

Bit

R/W

Default

Description

1 = Regulator 4 will Start in

REG4SQ1

REG5SQ1

REG6SQ1

3

R/W

1

0 = No Start

Sequence State 1

1 = Regulator 5 will Start in

Sequence State 1

4

5

0

1 = Regulator 6 will Start in

Sequence State 1

—

6

7

R/W

0

Reserved

TABLE 8-11: SEQUENCE STATE 2 REGISTER

Register Name

Address

SEQ2_REG

Sequence Register

0x12’h

—

Field

Bit

R/W

Default

Description

1 = Regulator 1 will Start in

REG1SQ2

REG2SQ2

REG3SQ2

REG4SQ2

REG5SQ2

REG6SQ2

0

R/W

0

0 = No Start

Sequence State 2

1 = Regulator 2 will Start in

Sequence State 2

1

2

3

4

5

1

0

1 = Regulator 3 will Start in

Sequence State 2

1 = Regulator 4 will Start in

Sequence State 2

1 = Regulator 5 will Start in

Sequence State 2

1 = Regulator 6 will Start in

Sequence State 2

—

6

7

R/W

0

Reserved

TABLE 8-12: SEQUENCE STATE 3 REGISTER

Register Name

Address

SEQ3_REG

Sequence Register

0x13’h

—

Field

Bit

R/W

Default

Description

1 = Regulator 1 will Start in

REG1SQ3

REG2SQ3

REG3SQ3

REG4SQ3

REG5SQ3

REG6SQ3

0

R/W

1

0 = No Start

Sequence State 3

1 = Regulator 2 will Start in

Sequence State 3

1

2

3

4

5

0

1 = Regulator 3 will Start in

Sequence State 3

1 = Regulator 4 will Start in

Sequence State 3

1 = Regulator 5 will Start in

Sequence State 3

1 = Regulator 6 will Start in

Sequence State 3

DS20005887A-page 44

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MIC7400

TABLE 8-12: SEQUENCE STATE 3 REGISTER (CONTINUED)

Register Name

Address

SEQ3_REG

Sequence Register

0x13’h

—

Field

Bit

R/W

Default

Description

—

6

7

R/W

0

Reserved

TABLE 8-13: SEQUENCE STATE 4 REGISTER

Register Name

Address

SEQ4_REG

Sequence Register

0x14’h

—

Field

Bit

R/W

Default

Description

1 = Regulator 1 will Start in

Sequence State 4

REG1SQ4

REG2SQ4

REG3SQ4

REG4SQ4

REG5SQ4

REG6SQ4

0

R/W

0

0 = No Start

1 = Regulator 2 will Start in

Sequence State 4

1

2

3

4

5

0

1

0

1 = Regulator 3 will Start in

Sequence State 4

1 = Regulator 4 will Start in

Sequence State 4

1 = Regulator 5 will Start in

Sequence State 4

1 = Regulator 6 will Start in

Sequence State 4

—

6

7

R/W

0

Reserved

TABLE 8-14: SEQUENCE STATE 5 REGISTER

Register Name

Address

SEQ5_REG

Sequence Register

0x15’h

—

Field

Bit

R/W

Default

Description

1 = Regulator 1 will Start in

REG1SQ5

REG2SQ5

REG3SQ5

REG4SQ5

REG5SQ5

REG6SQ5

0

R/W

0

0 = No Start

Sequence State 5

1 = Regulator 2 will Start in

Sequence State 5

1

2

3

4

5

0

1 = Regulator 3 will Start in

Sequence State 5

1 = Regulator 4 will Start in

Sequence State 5

1 = Regulator 5 will Start in

Sequence State 5

1 = Regulator 6 will Start in

Sequence State 5

—

6

7

R/W

0

Reserved

 2017 Microchip Technology Inc.

DS20005887A-page 45

MIC7400

TABLE 8-15: SEQUENCE STATE 6 REGISTER

Register Name

Address

SEQ6_REG

Sequence Register

0x16’h

—

Field

Bit

R/W

Default

Description

1 = Regulator 1 will Start in

REG1SQ6

REG2SQ6

REG3SQ6

REG4SQ6

REG5SQ6

REG6SQ6

0

R/W

0

0 = No Start

Sequence State 6

1 = Regulator 2 will Start in

Sequence State 6

1

2

3

4

5

0

1

1 = Regulator 3 will Start in

Sequence State 6

1 = Regulator 4 will Start in

Sequence State 6

1 = Regulator 5 will Start in

Sequence State 6

1 = Regulator 6 will Start in

Sequence State 6

—

6

7

R/W

0

Reserved

8.11 Delay Register (17’h)

The STDEL register sets the delay between powering up of each regulator at initial power up (see Figure 5-1). Once all

the internal power good registers PGOOD[1-6] are all “1”, then the global PG pin goes high without delay.

The PORDEL register sets the delay for the POR flag pin. The POR delay time starts as soon as AVIN pin voltage rises

above the system UVLO upper threshold set by the PORUP register (21’h). The POR output goes low without delay if

AVIN falls below the lower UVLO threshold set by the PORDN register (22’h).

TABLE 8-16: DELAY REGISTER

Register Name

Address

DELAY_CNTL_REG

—

Delay Register

0x17’h

Field

Bit

R/W

Default

Description

Delay Time from 0 ms to 7 ms in 1 ms increment

001

(1 ms)

STDEL

2:0

7:3

R/W

000 = 0 ms

001 = 1 ms

010 = 2 ms

011 = 3 ms

100 = 4 ms

101 = 5 ms

110 = 6 ms

111 = 7 ms

Delay Time from 5 ms to 160 ms in 5 ms increment

00000 = 5ms

00001 = 10ms

00010 = 15ms

00011 = 20ms

00100 = 25ms

00101 = 30ms

00110 = 35ms

00111 = 40ms

01000 = 45ms

01001 = 50ms

01010 = 55ms

01011 = 60ms

01100 = 65ms

01101 = 70ms

01110 = 75ms

01111 = 80ms

10000 = 85ms

10001 = 90ms

10010 = 95ms

10011 = 100ms

11000 = 125ms

11001 = 130ms

11010 = 135ms

11011 = 140ms

00011

(20 ms)

PORDEL

R/W

10100 = 105ms 11100 = 145ms

10101 = 110ms

10110 = 115ms

10111 = 120ms

11101 = 150ms

11110 = 155ms

11111 = 160ms

DS20005887A-page 46

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MIC7400

8.12 Soft-Start Registers (18’h – 1A’h)

When regulator(n) is turned on from either the Enable Register (04’h) in NORMAL mode or from the Standby Register

(03’h) in STANDBY mode, the three REG(n)SS soft-start bits are used to control both the rising and falling ramp rate of

the outputs.

In NORMAL mode, the outputs are stepped from the current regulator voltage settings to a newly programmed regulator

voltage setting or to the default value.

On power-up, the regulator voltage output is set to the lowest possible voltage setting, which is 3F’h. The voltage

regulator will change by one step or increment at a time. The amount of time between each step is controlled by the

soft-start registers. Table 8-17 details the amount of time for each encoded soft-start value.

TABLE 8-17: SOFT-START REGISTER SPEED SETTINGS

Register

R/W

Default

Description

Soft-Start Time from 4 µs to 512 µs

SS_SPEED = 0

R/W

000

000 = 4 µs

001 = 8 µs

010 = 16 µs

011 = 32 µs

100 = 64 µs

110 = 256 µs

111 = 512 µs

101 = 128 µs

Soft-Start Time from 8 µs to 1024 µs

SS_SPEED = 1

R/W

000

000 = 8 µs

010 = 32 µs

011 = 64 µs

100 = 128 µs

110 = 512 µs

001 = 16 µs

101 = 256 µs 111 = 1024 µs

TABLE 8-18: SOFT-START REGISTER OUT1 AND OUT2

Register Name

Address

SS1-2_REG

Soft-Start Register for V_OUT1and V_OUT2

—

0x18’h

Field

Bit

R/W

Default

Description

001

(8 µs)

REG1SS

2:0

R/W

OUT1 Soft-Start Time. See Table 8-17 for Soft-Start settings.

001

(8 µs)

REG2SS

—

5:3

6

R/W

OUT2 Soft-Start Time. See Table 8-17 for Soft-Start settings.

Reserved

0

Sets the speed of the clock to slow or fast for different clock divi-

sion, see Table 8-17. 0 = Slow speed; 1 = Fast speed.

SS_SPEED

7

0

TABLE 8-19: SOFT-START REGISTER OUT3 AND OUT4

Register Name

Address

SS3-4_REG

Soft-Start Register for V_OUT3and V_OUT4

—

0x19’h

Field

Bit

R/W

Default

Description

001

(8 µs)

REG3SS

REG4SS

2:0

R/W

OUT3 Soft-Start Time. See Table 8-17 for Soft-Start settings.

OUT4 Soft-Start Time. See Table 8-17 for Soft-Start settings.

001

(8 µs)

5:3

—

6

7

R/W

0

Reserved

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DS20005887A-page 47

MIC7400

TABLE 8-20: SOFT-START REGISTER OUT5 AND OUT6

Register Name

Address

SS5-6_REG

Soft-Start Register for V_OUT5and V_OUT6

—

0x1A’h

Field

Bit

R/W

Default

Description

001

(8 µs)

REG5SS

REG6SS

2:0

R/W

OUT5 Soft-Start Time. See Table 8-17 for Soft-Start settings.

OUT6 Soft-Start Time. See Table 8-17 for Soft-Start settings.

010

(16 µs)

5:3

—

6

7

R/W

0

Reserved

8.13 Current-Limit (Normal Mode) Registers (1B’h – 1D’h)

This register is used to set the current limit for each DC/DC regulator in normal mode operation.

TABLE 8-21: CURRENT-LIMIT REGISTER I

AND I

OUT2

OUT1

Register Name

Address

ILIMIT_1-2_REG

—

Current-Limit Register for V_OUT1and V_OUT2

0x1B’h

Field

Bit

R/W

Default

Description

Normal current-limit for regulator 1 from 8.6A to 1.1A in 0.5A dec-

rements

0000 = 8.6A

0001 = 8.1A

0010 = 7.6A

0011 = 7.1A

0100 = 6.6A

0101 = 6.1A

0110 = 5.6A

0111 = 5.1A

1000 = 4.6A

1001 = 4.1A

1010 = 3.6A

1011 = 3.1A

1100 = 2.6 A

1101 = 2.1A

1110 = 1.6A

1111 = 1.1A

1001

(4.1A)

REG1CL

REG2CL

3:0

R/W

Normal current-limit for regulator 2 from 8.6A to 1.1A in 0.5A dec-

rements

0000 = 8.6A

0001 = 8.1A

0010 = 7.6A

0011 = 7.1A

0100 = 6.6A

0101 = 6.1A

0110 = 5.6A

0111 = 5.1A

1000 = 4.6A

1001 = 4.1A

1010 = 3.6A

1011 = 3.1A

1100 = 2.6 A

1101 = 2.1A

1110 = 1.6A

1111 = 1.1A

1001

(4.1A)

7:4

R/W

TABLE 8-22: CURRENT-LIMIT REGISTER I

AND I

OUT4

OUT3

Register Name

Address

ILIMIT_3-4_REG

—

Current-Limit Register for V_OUT3and V_OUT4

0x1C’h

Field

Bit

R/W

Default

Description

Normal current-limit for regulator 3 from 8.6A to 1.1A in 0.5A dec-

rements

0000 = 8.6A

0001 = 8.1A

0010 = 7.6A

0011 = 7.1A

0100 = 6.6A

0101 = 6.1A

0110 = 5.6A

0111 = 5.1A

1000 = 4.6A

1001 = 4.1A

1010 = 3.6A

1011 = 3.1A

1100 = 2.6 A

1101 = 2.1A

1110 = 1.6A

1111 = 1.1A

1001

(4.1A)

REG3CL

3:0

R/W

Normal current-limit for regulator 4 from 8.6A to 1.1A in 0.5A dec-

rements

0000 = 8.6A

0001 = 8.1A

0010 = 7.6A

0011 = 7.1A

0100 = 6.6A

0101 = 6.1A

0110 = 5.6A

0111 = 5.1A

1000 = 4.6A

1001 = 4.1A

1010 = 3.6A

1011 = 3.1A

1100 = 2.6 A

1101 = 2.1A

1110 = 1.6A

1111 = 1.1A

0101

(6.1A)

REG4CL

7:4

R/W

DS20005887A-page 48

 2017 Microchip Technology Inc.

MIC7400

TABLE 8-23: CURRENT-LIMIT REGISTER I

AND I

OUT6

OUT5

Register Name

Address

ILIMIT_5-6_REG

—

Current-Limit Register for V_OUT5and V_OUT6

0x1D’h

Field

Bit

R/W

Default

Description

Normal current-limit for regulator 5 from 8.6A to 1.1A in 0.5A dec-

rements

0000 = 8.6A

0001 = 8.1A

0010 = 7.6A

0011 = 7.1A

0100 = 6.6A

0101 = 6.1A

0110 = 5.6A

0111 = 5.1A

1000 = 4.6A

1001 = 4.1A

1010 = 3.6A

1011 = 3.1A

1100 = 2.6 A

1101 = 2.1A

1110 = 1.6A

1111 = 1.1A

1001

(4.1A)

REG5CL

3:0

R/W

Current-limit from 2.6A to 1.78A in 0.12A decrements

011

(2.24A)

REG6CL

—

6:4

7

R/W

000 = 2.6A

010 = 2.36A

011 = 2.24A

100 = 2.12A

101 = 2.00A

110 = 1.88A

111 = 1.76A

001 = 2.48A

0

0 = Current-Limit On

1 = Current-Limit Off

8.14 Current-Limit (STBY Mode) Registers (1E’h – 20’h)

This register is used to set the current-limit for each DC/DC regulator when in standby (STBY) mode operation.

TABLE 8-24: STANDBY CURRENT-LIMIT REGISTER I AND I

OUT1

OUT2

Register Name

Address

STBY_ILIMIT_1-2_REG

—

Standby Current-Limit Register for V_OUT1and V_OUT2

0x1E’h

Field

Bit

R/W

Default

Description

Standby current-limit for regulator 1 from 8.6A to 1.1A in 0.5A dec-

rements

0000 = 8.6A

0001 = 8.1A

0010 = 7.6A

0011 = 7.1A

0100 = 6.6A

0101 = 6.1A

0110 = 5.6A

0111 = 5.1A

1000 = 4.6A

1001 = 4.1A

1010 = 3.6A

1011 = 3.1A

1100 = 2.6 A

1101 = 2.1A

1110 = 1.6A

1111 = 1.1A

1001

(4.1A)

SB1CL

SB2CL

3:0

R/W

Standby current-limit for regulator 2 from 8.6A to 1.1A in 0.5A dec-

rements

0000 = 8.6A

0001 = 8.1A

0010 = 7.6A

0011 = 7.1A

0100 = 6.6A

0101 = 6.1A

0110 = 5.6A

0111 = 5.1A

1000 = 4.6A

1001 = 4.1A

1010 = 3.6A

1011 = 3.1A

1100 = 2.6 A

1101 = 2.1A

1110 = 1.6A

1111 = 1.1A

1001

(4.1A)

7:4

R/W

TABLE 8-25: STANDBY CURRENT-LIMIT REGISTER I

AND I

OUT4

OUT3

Register Name

Address

STBY_ILIMIT_3-4_REG

—

Standby Current-Limit Register for V_OUT3and V_OUT4

0x1F’h

Field

Bit

R/W

Default

Description

Standby current-limit for regulator 3 from 8.6A to 1.1A in 0.5A

decrements

0000 = 8.6A

0001 = 8.1A

0010 = 7.6A

0011 = 7.1A

0100 = 6.6A

0101 = 6.1A

0110 = 5.6A

0111 = 5.1A

1000 = 4.6A

1001 = 4.1A

1010 = 3.6A

1011 = 3.1A

1100 = 2.6 A

1101 = 2.1A

1110 = 1.6A

1111 = 1.1A

1001

(4.1A)

SB3CL

3:0

R/W

 2017 Microchip Technology Inc.

DS20005887A-page 49

MIC7400

TABLE 8-25: STANDBY CURRENT-LIMIT REGISTER I

AND I

(CONTINUED)

OUT3

OUT4

Register Name

Address

STBY_ILIMIT_3-4_REG

—

Standby Current-Limit Register for V_OUT3and V_OUT4

0x1F’h

Field

Bit

R/W

Default

Description

Standby current-limit for regulator 4 from 8.6A to 1.1A in 0.5A

decrements

0000 = 8.6A

0001 = 8.1A

0010 = 7.6A

0011 = 7.1A

0100 = 6.6A

0101 = 6.1A

0110 = 5.6A

0111 = 5.1A

1000 = 4.6A

1001 = 4.1A

1010 = 3.6A

1011 = 3.1A

1100 = 2.6 A

1101 = 2.1A

1110 = 1.6A

1111 = 1.1A

0101

(6.1A)

SB4CL

7:4

R/W

TABLE 8-26: STANDBY CURRENT-LIMIT REGISTER I

AND I

OUT6

OUT5

Register Name

Address

STBY_ILIMIT_5-6_REG

—

Standby Current-Limit Register for V_OUT5and V_OUT6

0x20’h

Field

Bit

R/W

Default

Description

Standby current-limit for regulator 5 from 8.6A to 1.1A in 0.5A dec-

rements

0000 = 8.6A

0001 = 8.1A

0010 = 7.6A

0011 = 7.1A

0100 = 6.6A

0101 = 6.1A

0110 = 5.6A

0111 = 5.1A

1000 = 4.6A

1001 = 4.1A

1010 = 3.6A

1011 = 3.1A

1100 = 2.6 A

1101 = 2.1A

1110 = 1.6A

1111 = 1.1A

1001

(4.1A)

SB5CL

3:0

R/W

Current-limit from 2.6A to 1.78A in 0.12A decrements

011

(2.24A)

SB6CL

—

6:4

7

R/W

000 = 2.6A

010 = 2.36A

011 = 2.24A

100 = 2.12A

101 = 2.00A

110 = 1.88A

111 = 1.76A

001 = 2.48A

0

0 = Current-Limit On

1 = Current-Limit Off

8.15 Power-on-Reset (POR) Threshold Voltage Setting Register (21’h and 22’h)

This register is used to set the rising and falling threshold of power-on-reset (POR) comparator. The POR threshold

voltage setting is based on the logic level of the VSLT pin in addition to the register bits. Refer to Table 8-16 for POR

time delay settings.

TABLE 8-27: RISING AND FALLING POWER-ON-RESET THRESHOLD VOLTAGE SETTINGS

Rising and Falling Power-On-Reset Threshold Voltage

Condition

—

Setting

Bit

R/W

Default

Description

3.3V to 2.3V in 50 mV decrements

00000 = 3.25V 01000 = 2.85V 10000 = 2.45V 11000 = 2.25V

00001 = 3.20V 01001 = 2.80V 10001 = 2.40V 11001 = 2.25V

00010 = 3.15V 01010 = 2.75V 10010 = 2.35V 11010 = 2.25V

VSCLT = 0

4:0

R/W

00000 00011 = 3.10V 01011 = 2.70V 10011 = 2.30V 11011 = 2.25V

00100 = 3.05V 01100 = 2.65V 10100 = 2.25V 11100 = 2.25V

00101 = 3.00V 01101 = 2.60V 10101 = 2.25V 11101 = 2.25V

00110 = 2.95V 01110 = 2.55V 10110 = 2.25V 11110 = 2.25V

00111 = 2.90V 01111 = 2.50V 10111 = 2.25V 11111 = 2.25V

DS20005887A-page 50

 2017 Microchip Technology Inc.

MIC7400

TABLE 8-27: RISING AND FALLING POWER-ON-RESET THRESHOLD VOLTAGE SETTINGS

Rising and Falling Power-On-Reset Threshold Voltage

Setting

Condition

—

Bit

R/W

Default

Description

4.3V to 3.3V in 50 mV decrements

00000 = 4.25V 01000 = 3.85V 10000 = 3.45V 11000 = 3.25V

00001 = 4.20V 01001 = 3.80V 10001 = 3.40V 11001 = 3.25V

00010 = 4.15V 01010 = 3.75V 10010 = 3.35V 11010 = 3.25V

VSCLT = 1

4:0

R/W

00000 00011 = 4.10V 01011 = 3.70V 10011 = 3.30V 11011 = 3.25V

00100 = 4.05V 01100 = 3.65V 10100 = 3.25V 11100 = 3.25V

00101 = 4.00V 01101 = 3.60V 10101 = 3.25V 11101 = 3.25V

00110 = 3.95V 01110 = 3.55V 10110 = 3.25V 11110 = 3.25V

00111 = 3.90V 01111 = 3.50V 10111 = 3.25V 11111 = 3.25V

The three most significant bits [7:5] in registers 21’h and 22’h are used to mask the output voltage power-good flag after

the start-up sequenced is finished.

TABLE 8-28: POWER-ON-RESET RISING THRESHOLD VOLTAGE SETTING REGISTER (21’H)

Register Name

Address

PORUP_REG

—

Power-on-Reset Rising Threshold

0x21’h

Field

Bit

R/W

Default

Description

PORUP

4:0

R/W

01011

See Table 8-27

PGOOD_MASK

1

5

6

7

R/W

1

0 = Do not mask PGOOD1

1 = Mask PGOOD1

1 = Mask PGOOD2

1 = Mask PGOOD3

PGOOD_MASK

2

0 = Do not mask PGOOD2

0 = Do not mask PGOOD3

PGOOD_MASK

3

TABLE 8-29: POWER-ON-RESET FALLING THRESHOLD VOLTAGE SETTING REGISTER (22’H)

Register Name

Address

PORDN_REG

—

Power-on-Reset Falling Threshold

0x22’h

Field

Bit

R/W

Default

Description

PORDN

4:0

R/W

01101

See Table 8-27

PGOOD_MASK

4

5

6

7

R/W

1

0 = Do not mask PGOOD4

1 = Mask PGOOD4

1 = Mask PGOOD5

1 = Mask PGOOD6

PGOOD_MASK

5

0 = Do not mask PGOOD5

0 = Do not mask PGOOD6

PGOOD_MASK

6

 2017 Microchip Technology Inc.

DS20005887A-page 51

MIC7400

8.16 Pull-Down When Disabled Register (23’h)

This register is used to set the preference of enabling/disabling a pull-down FET when the DC/DC regulators are

disabled. The pull-down value for buck regulators 1 through 5 is 90ꢀ. The pull-down current value for the boost regulator

6 is programmable.

TABLE 8-30: PULL-DOWN WHEN DISABLED REGISTER

Register Name

Address

PULLDN1-6_REG

—

Pull-Down When Disabled Register

0x23’h

Field

Bit

R/W

Default

Description

Enable/Disable the pull-down on Regulator 1 when power down.

0 = No Pull-Down; 1 = Pull-Down

PULLD1

PULLD2

PULLD3

PULLD4

PULLD5

PULLD6C

PULLD6

0

R/W

0

Enable/Disable the pull-down on Regulator 2 when power down.

0 = No Pull-Down; 1 = Pull-Down

1

2

R/W

Enable/Disable the pull-down on Regulator 3 when power down.

0 = No Pull-Down; 1 = Pull-Down

0

Enable/Disable the pull-down on Regulator 4 when power down.

0 = No Pull-Down; 1 = Pull-Down

3

0

Enable/Disable the pull-down on Regulator 5 when power down.

0 = No Pull-Down; 1 = Pull-Down

4

0

Sets Boost Pull-Down Current Level

00 = 148 mA; 01 = 111 mA; 10 = 74 mA; 11 = 37 mA

6:5

7

00

0

Enable/Disable the pull-down on Regulator 6 when power down.

0 = No Pull-Down; 1 = Pull-Down

8.17 Internal Clock Control Register

This register houses the Force_CLK_ON bit 2 used when sending the special commands keys. Bit 2 of this register is

used to set the PMIC clock to permanently be enabled in order to execute the new command. This bit should be cleared

after the command has been executed in order to save power (the internal clock logic will shut down the clock

automatically when not needed).

TABLE 8-31: INTERNAL CLOCK CONTROL REGISTER

Register Name

Address

Force Clock Register

—

Internal Clock Control Register

0x2F’h

Field

Bit

R/W

Default

Description

—

0

1

R/W

0

Reserved

0=No action.

FORCE_-

CLK_ON

2

R/W

0

1= Force the internal clock to keep running and not be turned off

by the power down logic.

—

3

4

5

6

7

R/W

0

Reserved

DS20005887A-page 52

 2017 Microchip Technology Inc.

MIC7400

9.0

9.1

PACKAGING INFORMATION

Package Marking Information

36-Pin FQFN*

(Configurable)

Example

36-Pin FQFN*

(Configured)

Example

XXXX

NNN

7400

102

Legend: XX...X Product code or customer-specific information

Y

Year code (last digit of calendar year)

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC^®designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

*

e

3

)

●, ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle

mark).

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information. Package may or may not include

the corporate logo.

Underbar (_) and/or Overbar (⎯) symbol may not be to scale.

 2017 Microchip Technology Inc.

DS20005887A-page 53

MIC7400

36-Lead 4.5 mm x 4.5 mm FQFN Package Outline and Recommended Land Pattern

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging.

DS20005887A-page 54

 2017 Microchip Technology Inc.

MIC7400

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging.

 2017 Microchip Technology Inc.

DS20005887A-page 55

MIC7400

NOTES:

DS20005887A-page 56

 2017 Microchip Technology Inc.

MIC7400

APPENDIX A: REVISION HISTORY

Revision A (November 2017)

• Converted Micrel document MIC7400 to Micro-

chip data sheet DS20005887A.

• Minor text changes throughout.

 2017 Microchip Technology Inc.

DS20005887A-page 57

MIC7400

NOTES:

DS20005887A-page 58

 2017 Microchip Technology Inc.

MIC7400

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.

Examples:

PART NO.

Device

–XXXX

X

XX

–XX

a) MIC7400YFL-T5: Configurable PMIC, Five Chan-

nel Buck Regulator Plus One

Output

Voltages

Junction Temp. Package Media Type

Range

Boost with HyperLight Load and

I C Control, 1.8V, 1.1V, 1.8V,

2

1.05V, 1.25V, 12V Output Volt-

ages, –40°C to +125°C Temp.

Range, 36-Lead FQFN, 500/

Reel

Device:

MIC7400:

Configurable PMIC, Five Channel Buck

Regulator Plus One Boost with HyperLight

Load and I C Control

®

2

Output Voltages: <blank>= 1.8V, 1.1V, 1.8V, 1.05V, 1.25V, 12V

b) MIC7400-

XXXXYFL-TR:

Configurable PMIC, Five Chan-

nel Buck Regulator Plus One

Boost with HyperLight Load and

XXXX

=

Configurable (Contact Marketing for Options)

2

I C Control, Configurable Output

Junction

Temperature

Range:

Y

=

–40°C to +125°C

Voltages, –40°C to +125°C

Temp. Range, 36-Lead FQFN,

5,000/Reel

c) MIC7400YFL:

Configurable PMIC, Five Chan-

nel Buck Regulator Plus One

Boost with HyperLight Load and

Package:

FL

=

36-Lead 4.5 mm x 4.5 mm FQFN

2

Media Type:

<blank>= 1/Tube

T5

TR

I C Control, 1.8V, 1.1V, 1.8V,

=

500/Reel

5,000/Reel

1.05V, 1.25V, 12V Output Volt-

ages, –40°C to +125°C Temp.

Range, 36-Lead FQFN, 1/Tube

d) MIC7400-

XXXXYFL-T5:

Configurable PMIC, Five Chan-

nel Buck Regulator Plus One

Boost with HyperLight Load and

2

I C Control, Configurable Output

Voltages, –40°C to +125°C

Temp. Range, 36-Lead FQFN,

500/Reel

Note 1:

Tape and Reel identifier only appears in the

catalog part number description. This identifier is

used for ordering purposes and is not printed on

the device package. Check with your Microchip

Sales Office for package availability with the

Tape and Reel option.

 2017 Microchip Technology Inc.

DS20005887A-page 59

MIC7400

NOTES:

DS20005887A-page 60

 2017 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR,

AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,

CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,

KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,

maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,

OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip

Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST

Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered

trademarks of Microchip Technology Incorporated in the U.S.A.

and other countries.

ClockWorks, The Embedded Control Solutions Company,

EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,

mTouch, Precision Edge, and Quiet-Wire are registered

trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,

CodeGuard, CryptoAuthentication, CryptoCompanion,

CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average

Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial

Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,

KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,

MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,

PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple

Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,

SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,

USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and

ZENAare trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

Silicon Storage Technology is a registered trademark of Microchip

Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip Technology

Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ

CERTIFIEDꢀBYꢀDNVꢀ

ISBN: 978-1-5224-2382-9

== ISO/TSꢀ16949ꢀ==ꢀ

 2017 Microchip Technology Inc.

DS20005887A-page 61

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Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

Hong Kong

Tel: 852-2943-5100

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

Finland - Espoo

Tel: 358-9-4520-820

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Web Address:

www.microchip.com

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Beijing

Tel: 86-10-8569-7000

Fax: 86-10-8528-2104

France - Saint Cloud

Tel: 33-1-30-60-70-00

India - Pune

Tel: 91-20-3019-1500

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Germany - Garching

Tel: 49-8931-9700

Germany - Haan

Austin, TX

Tel: 512-257-3370

Japan - Osaka

Tel: 81-6-6152-7160

Fax: 81-6-6152-9310

Boston

Tel: 49-2129-3766400

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Japan - Tokyo

Tel: 81-3-6880- 3770

Fax: 81-3-6880-3771

Germany - Heilbronn

Tel: 49-7131-67-3636

China - Dongguan

Tel: 86-769-8702-9880

Germany - Karlsruhe

Tel: 49-721-625370

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

China - Guangzhou

Tel: 86-20-8755-8029

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

China - Hangzhou

Tel: 86-571-8792-8115

Fax: 86-571-8792-8116

Korea - Seoul

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Germany - Rosenheim

Tel: 49-8031-354-560

China - Hong Kong SAR

Tel: 852-2943-5100

Fax: 852-2401-3431

Israel - Ra’anana

Tel: 972-9-744-7705

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Detroit

Novi, MI

Tel: 248-848-4000

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Houston, TX

Tel: 281-894-5983

Italy - Padova

Tel: 39-049-7625286

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

Tel: 317-536-2380

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

China - Shanghai

Tel: 86-21-3326-8000

Fax: 86-21-3326-8021

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Norway - Trondheim

Tel: 47-7289-7561

Los Angeles

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Tel: 951-273-7800

Poland - Warsaw

Tel: 48-22-3325737

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Romania - Bucharest

Tel: 40-21-407-87-50

China - Shenzhen

Tel: 86-755-8864-2200

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Raleigh, NC

Tel: 919-844-7510

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Taipei

Tel: 886-2-2508-8600

Fax: 886-2-2508-0102

New York, NY

Tel: 631-435-6000

Sweden - Gothenberg

Tel: 46-31-704-60-40

San Jose, CA

Tel: 408-735-9110

Tel: 408-436-4270

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Sweden - Stockholm

Tel: 46-8-5090-4654

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

DS20005887A-page 62

 2017 Microchip Technology Inc.

11/07/16


型号：	MIC7400YFL-TR
厂家：	MICROCHIP
描述：	IC REG BUCK BOOST PROG SYNC
文件：	总62页 (文件大小：3088K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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