MXT577FNS740M000TA [MICROCHIP]

LVDS Output Clock Oscillator;
MXT577FNS740M000TA
型号: MXT577FNS740M000TA
厂家: MICROCHIP    MICROCHIP
描述:

LVDS Output Clock Oscillator

文件: 总24页 (文件大小:742K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
MXT57  
Low Jitter, Temperature Compensated Crystal Oscillator  
Features  
General Description  
• Output Frequency 2.5 MHz to 850 MHz  
The MXT57 product line is a family of ultra-low jitter,  
industry standard TCXO that are designed to maximize  
performance in networking, storage, server, and  
telecommunications equipment.  
• Phase Noise as Low as 190 fs (F0 = 156.25 MHz,  
Integration Bandwidth 1.875 MHz to 20 MHz)  
• Ultra-Low Spurs (–100 dBc or Greater Typical)  
• ±2.5 ppm over Voltage and Temperature  
The MXT57 is available in a 5 mm x 7 mm LLGA  
package. These devices are capable of ±2.5 ppm total  
stability across the –40°C to +85°C operating  
temperature range, using proven assembly methods  
that improve long term reliability and minimize aging  
drift compared to traditional TCXO assembly  
processes.  
• Supports CMOS, LVPECL, LVDS, and HCSL  
Outputs  
• 2.375V to 3.63V Supply Voltage  
• Output Enable Option: Can be Ordered on Pin 1  
or Pin 2  
• Industry-Standard and Space-Saving 5.0 mm x  
7.0 mm 6-Lead Package  
As a custom ASIC with programmable output format  
and OE options, these TCXOs can be configured to be  
footprint-compatible with any standard 6-pin TCXO  
available today. Standard options and frequencies are  
available.  
• –40°C to +85°C Operating Temperature Range  
• Pb-Free and RoHS Compliant  
• Analog TCXO, No Phase Bumps during  
Temperature Transitions  
Please visit http://clockworks.microchip.com/timing to  
select a combination of options to customize your  
product, print a specific data sheet, and order samples.  
• Short Production Lead Time  
Applications  
• 10/40/100G Ethernet  
Functional Block Diagram  
• SONET-Optical Communications  
• PCIe Gen 3/4/5  
VDD  
6
• Fibre Channel/SAS  
• CPRI/OBSAI, XAUI and Backplane SERDES  
VDD Power Rail Regulation  
5 - /Q  
4 - Q  
Analog  
TCXO  
÷
PLL  
OTP MEMORY  
Pin 1  
or 2  
3
VSS  
OE  
2018 Microchip Technology Inc.  
DS20006037A-page 1  
MXT57  
Package Types  
MXT57 Pinout  
Enable Pin 1 Option  
MXT57 Pinout  
Enable Pin 2 Option  
OE  
NC  
1
2
3
6
5
4
VDD  
/Q  
NC  
OE  
1
2
3
6
5
4
VDD  
/Q  
GND  
Q
GND  
Q
DS20006037A-page 2  
2018 Microchip Technology Inc.  
MXT57  
1.0  
ELECTRICAL CHARACTERISTICS  
Absolute Maximum Ratings †  
Supply Voltage......................................................................................................................................... –0.3V to + 4.0V  
Input Voltage......................................................................................................................................–0.3V to VDD +0.3V  
ESD Protection (HBM)...............................................................................................................................................4 kV  
ESD Protection (MM) ................................................................................................................................................400V  
ESD Protection (CDM)............................................................................................................................................1.5 kV  
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.  
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated  
in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended  
periods may affect device reliability.  
TABLE 1-1:  
ELECTRICAL CHARACTERISTICS  
Electrical Characteristics: VDD = 2.375V to 3.63V, TA = –40°C to +85°C with output terminated per output logic  
type.  
Parameters  
Sym.  
Min.  
Typ.  
Max.  
Units  
Conditions  
Supply Voltage  
(Note 1)  
VDD  
2.375  
3.63  
V
120  
95  
130  
Output enabled LVCMOS (no load).  
LVPECL  
Supply Current  
IDD  
90  
100  
mA  
LVDS  
95  
105  
HCSL  
60  
Output disabled (Tri-state)  
A = ±5  
B = ±2.5  
A = ±8  
B = ±5  
Frequency  
Stability  
Inclusive of initial accuracy, temperature  
drift, aging, shock and vibration.  
f  
ppm  
ms  
V
From 90% VDD to valid clock output,  
Start-up Time  
tSU  
20  
T = +25°C  
VIH  
VIL  
2
VDD+0.3  
0.8  
Input logic-high  
Input logic-low  
Input Logic  
Levels  
–0.3  
Enable Active  
High Option  
(Note 2)  
50  
50  
kΩ  
kΩ  
Pull-up resistor on Pin 1 or 2  
Enable Active  
Low Option  
(Note 3)  
Pull-down resistor on Pin 1 or 2  
LVCMOS  
Frequency  
f0  
2.5  
250  
MHz  
450  
110  
12 kHz to 20 MHz @ 156.25 MHz  
1.875 MHz to 5 MHz @ 156.25 MHz  
Integrated Phase  
Noise (Random)  
ϕj  
fsRMS  
Output High  
Voltage  
VOH  
VOL  
VDD – 0.8  
V
RL = 50ꢀ  
Output Low  
Voltage  
0.6  
mV  
Single-ended  
Output Rise/Fall  
Time  
tr/tf  
100  
45  
500  
55  
ps  
%
Duty Cycle  
LVPECL  
SYM  
Frequency  
f0  
2.5  
850  
MHz  
480  
100  
12 kHz to 20 MHz @ 200 MHz  
1.875 MHz to 20 MHz @ 200 MHz  
Integrated Phase  
Noise (Random)  
ϕj  
fsRMS  
2018 Microchip Technology Inc.  
DS20006037A-page 3  
MXT57  
TABLE 1-1:  
ELECTRICAL CHARACTERISTICS (CONTINUED)  
Electrical Characteristics: VDD = 2.375V to 3.63V, TA = –40°C to +85°C with output terminated per output logic  
type.  
Parameters  
Sym.  
Min.  
Typ.  
Max.  
Units  
Conditions  
Output High  
Voltage  
VDD  
1.01  
VOH  
VDD–1.35  
VDD–0.8  
V
RL = 50ꢀ  
Output Low  
Voltage  
VDD  
1.78  
VOL  
VDD–2.0  
0.65  
VDD–1.6  
0.95  
mV  
mV  
Single-ended  
Output  
Differential  
Voltage  
VOD  
0.77  
Output Rise/Fall  
Time  
tr/tf  
85  
45  
350  
55  
ps  
%
Duty Cycle  
LVDS  
SYM  
Frequency  
f0  
2.5  
850  
MHz  
430  
100  
12 kHz to 20 MHz @ 200 MHz  
Integrated Phase  
Noise (Random)  
ϕj  
fsRMS  
1.875 MHz to 20 MHz @ 200 MHz  
Output High  
Voltage  
VOH  
VOL  
1.248  
0.898  
1.375  
1.025  
1.602  
1.252  
V
Output Low  
Voltage  
mV  
Output  
Differential  
Voltage  
VOD  
247  
350  
1.2  
454  
mV  
mV  
Common Mode  
Output Voltage  
VCM  
1.125  
1.375  
Output Rise/Fall  
Time  
tr/tf  
100  
45  
400  
55  
ps  
%
Duty Cycle  
HCSL  
SYM  
Frequency  
f0  
2.5  
850  
MHz  
450  
110  
12 kHz to 20 MHz @ 100 MHz  
1.875 MHz to 20 MHz @ 100 MHz  
Integrated Phase  
Noise (Random)  
ϕj  
fsRMS  
Output High  
Voltage  
VOH  
VOL  
660  
700  
0
850  
27  
mV  
Output Low  
Voltage  
–150  
mV  
mV  
Output  
Differential  
Voltage  
200  
250  
250  
300  
20% to 80%  
VOD  
RL = 50ꢀ  
Common Mode  
Output Voltage  
VCM  
48  
52  
mV  
Differential  
Output Rise/Fall  
Time  
tr/tf  
150  
48  
300  
450  
52  
ps  
%
Duty Cycle  
SYM  
Note 1: VDD Pin should have basic VDD filtering as shown in Figure Something.  
2: Output is enabled if pad floated (not connected) or pulled high; output tri-stated if pulled low.  
3: Output is enabled if pad floated (not connected) or pulled low; output tri-stated if pulled high.  
DS20006037A-page 4  
2018 Microchip Technology Inc.  
MXT57  
TEMPERATURE SPECIFICATIONS (Note 1)  
Parameters  
Temperature Ranges  
Sym.  
Min.  
Typ.  
Max.  
Units  
Conditions  
Operating Temperature Range  
Maximum Junction Temperature  
Storage Temperature Range  
Soldering Temperature  
TA  
TJ  
TS  
–40  
+85  
°C  
°C  
°C  
°C  
+125  
+125  
+260  
–65  
10 sec. max.  
Package Thermal Resistance  
Thermal Resistance from Junction to  
Ambient, LGA-6Ld  
JA  
53  
°C/W  
Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable  
junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the  
maximum allowable power dissipation will cause the device operating junction temperature to exceed the  
maximum +125°C rating. Sustained junction temperatures above +125°C can impact the device reliability.  
2018 Microchip Technology Inc.  
DS20006037A-page 5  
MXT57  
2.0  
PIN DESCRIPTIONS  
The descriptions of the pins are listed in Table 2-1 and Table 2-2.  
TABLE 2-1:  
Pin Number  
PIN FUNCTION TABLE (ENABLE PIN 1 OPTION)  
Pin Name  
Pin Type  
Description  
Output Enable.  
1
OE  
I
Active-High and Active-Low options.  
Do not connect, leave floating.  
Power supply ground.  
Clock output +.  
2
3
4
5
6
DNC  
GND  
Q
NC  
Ground  
O
/Q  
O
Clock output –.  
VDD  
Power  
Power supply.  
TABLE 2-2:  
PIN FUNCTION TABLE (ENABLE PIN 2 OPTION)  
Pin Number  
Pin Name  
Pin Type  
Description  
Do not connect, leave floating.  
1
DNC  
NC  
Output Enable.  
Active-High and Active-Low options.  
2
OE  
I
3
4
5
6
GND  
Q
Ground  
O
Power supply ground.  
Clock output +.  
Clock output –.  
Power supply.  
/Q  
O
VDD  
Power  
DS20006037A-page 6  
2018 Microchip Technology Inc.  
MXT57  
3.0  
PERFORMANCE CHARACTERISTICS  
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of  
samples and are provided for informational purposes only. The performance characteristics listed herein  
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified  
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.  
FIGURE 3-1:  
LVCMOS Output 125 MHz 1.875 MHz to 20 MHz, 154 fs.  
FIGURE 3-2:  
LVCMOS Output 125 MHz 12 kHz to 20 MHz, 412 fs.  
2018 Microchip Technology Inc.  
DS20006037A-page 7  
MXT57  
FIGURE 3-3:  
LVPECL Output 200 MHz 1.875 MHz to 20 MHz 169 fs.  
FIGURE 3-4:  
LVPECL Output 200 MHz 12 kHz to 20 MHz, 428 fs.  
DS20006037A-page 8  
2018 Microchip Technology Inc.  
MXT57  
FIGURE 3-5:  
HCSL Output 156.25 MHz 1.875 MHz to 20 MHz, 191 fs.  
FIGURE 3-6:  
HCSL Output 156.25 MHz 12 kHz to 20 MHz, 449 fs.  
2018 Microchip Technology Inc.  
DS20006037A-page 9  
MXT57  
3XDBA125nd 5-X573A6LOLArqenconir urnBurnin
3-MXT573DBA-125M and 5-MXT573ABA-156.25M 6L MOLGA Frequency Monitor During Burn-In +85°C, 3.3V  
2
1.5  
1
20,000 hrs.  
Readout  
10,000 hrs.  
Extrapolated  
0.5  
0
-0.5  
-1  
-1.5  
-2  
200  
OPERATING HOURS  
20,000  
FIGURE 3-7:  
Aging.  
DS20006037A-page 10  
2018 Microchip Technology Inc.  
MXT57  
4.0  
OUTPUT WAVEFORM  
Output Voltage Swing  
Refer to Table 4-1  
FIGURE 4-1:  
Output Waveform: LVPECL, LVDS, HCSL, LVCMOS.  
TABLE 4-1:  
OUTPUT VOLTAGE SWING  
Output Logic Protocol  
Output Swing (Peak-to-Peak, Typical)  
LVCMOS  
LVPECL  
LVDS  
VOH – 3V, VOL + 3V  
770 mV  
350 mV  
HCSL  
700 mV  
2018 Microchip Technology Inc.  
DS20006037A-page 11  
MXT57  
5.0  
SOLDER REFLOW PROFILE  
FIGURE 5-1:  
Solder Reflow Profile.  
TABLE 5-1:  
SOLDER REFLOW  
Refer to JSTD-020C  
Ramp-Up Rate (200°C to Peak Temp.)  
Preheat Time 150°C to 200°C  
Time Maintained above 217°C  
Peak Temperature  
3°C/sec. max.  
60 to 180 sec.  
60 to 150 sec.  
255°C to 260°C  
20 to 40 sec.  
Time within 5°C of Actual Peak  
Ramp-Down Rate  
6°C/sec. max.  
8 minutes max.  
Time 25°C to Peak Temperature  
DS20006037A-page 12  
2018 Microchip Technology Inc.  
MXT57  
6.0  
ENVIRONMENTAL SPECIFICATIONS  
TABLE 6-1:  
ENVIRONMENTAL SPECIFICATIONS  
Parameter  
Specification  
Thermal Shock  
MIL-STD-883, Method 1011, Condition A  
MIL-STD-883, Method 1004  
Moisture Resistance  
Mechanical Shock  
Mechanical Vibration  
Resistance to Soldering Heat  
Hazardous Substance  
Solderability  
MIL-STD-883, Method 2022, Condition C  
MIL-STD-883, Method 2007, Condition B  
J-STD-020C, Table 5-2 Pb-free Devices (Except 2 Cycles Max)  
Pb-Free/RoHS/Green Compliant  
JESD22-B102-D Method 2 (Preconditioning E)  
MIL-STD-883, Method 2004, Test Condition D  
MIL-STD-883, Method 1014, Condition C  
Terminal Strength  
Gross Leak  
Fine Leak  
MIL-STD-883, Method 1014, Condition A2, R1 = 2x10–8 ATM CC/S  
Solvent Resistance  
MIL-STD-202, Method 215  
2018 Microchip Technology Inc.  
DS20006037A-page 13  
MXT57  
7.0  
7.1  
PACKAGING INFORMATION  
Package Marking Information  
Example  
6-Lead LGA*  
XXXXXXX  
WNNN<cr>  
XXXXXXXX  
MXT573A  
6035<cr>  
BA200M00  
Legend: XX...X Product code, customer-specific information, or frequency in MHz   
without printed decimal point  
Y
YY  
WW  
NNN  
Year code (last digit of calendar year)  
Year code (last 2 digits of calendar year)  
Week code (week of January 1 is week ‘01’)  
Alphanumeric traceability code  
e
3
Pb-free JEDEC® designator for Matte Tin (Sn)  
*
This package is Pb-free. The Pb-free JEDEC designator ( )  
e3  
can be found on the outer packaging for this package.  
, , Pin one index is identified by a dot, delta up, or delta down (triangle  
mark).  
Note: In the event the full Microchip part number cannot be marked on one line, it will  
be carried over to the next line, thus limiting the number of available  
characters for customer-specific information. Package may or may not include  
the corporate logo.  
Underbar (_) and/or Overbar () symbol may not be to scale.  
DS20006037A-page 14  
2018 Microchip Technology Inc.  
MXT57  
6-Lead 7.0 mm x 5.0 mm LLGA Package Outline and Recommended Land Pattern  
6-Lead Low Profile Land Grid Array [APA] - 7x5 mm Body (LLGA)  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
D
A
B
E
N
(DATUM A)  
(DATUM B)  
NOTE 1  
2X  
0.10 C  
2X  
1
2
TOP VIEW  
0.10 C  
A1  
C
A2  
A
SEATING  
PLANE  
SIDE VIEW  
0.07 C  
1
2
E1  
L
N
L1  
6X b  
0.10  
0.05  
C A B  
C
e
BOTTOM VIEW  
Microchip Technology Drawing C04-1071A Sheet 1 of 2  
2018 Microchip Technology Inc.  
DS20006037A-page 15  
MXT57  
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DS20006037A-page 16  
2018 Microchip Technology Inc.  
MXT57  
6-Lead Low Profile Land Grid Array [APA] - 7x5 mm Body (LLGA)  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
X
6
G1  
Y
C
G2  
1
2
E
SILK SCREEN  
RECOMMENDED LAND PATTERN  
Units  
MILLIMETERS  
Dimension Limits  
MIN  
NOM  
2.54 BSC  
3.93  
MAX  
Contact Pitch  
E
C
Contact Pad Spacing  
Contact Pad Width (X6)  
Contact Pad Length (X6)  
Contact to Contact (X4)  
Contact to Contact (X3)  
X
Y
G1  
G2  
1.60  
1.53  
0.94  
2.40  
Notes:  
1. Dimensioning and tolerancing per ASME Y14.5M  
BSC: Basic Dimension. Theoretically exact value shown without tolerances.  
Microchip Technology Drawing C04-3071A  
2018 Microchip Technology Inc.  
DS20006037A-page 17  
MXT57  
NOTES:  
DS20006037A-page 18  
2018 Microchip Technology Inc.  
MXT57  
APPENDIX A: REVISION HISTORY  
Revision A (May 2018)  
• Initial creation of MXT57 Microchip data sheet  
DS20006037A.  
2018 Microchip Technology Inc.  
DS20006037A-page 19  
MXT57  
NOTES:  
DS20006037A-page 20  
2018 Microchip Technology Inc.  
MXT57  
PRODUCT IDENTIFICATION SYSTEM  
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.  
Examples:  
X
XX  
X
PART NO.  
Device  
XXXMXXX  
XX  
a) MXT573ABFMXT57, 3A Crystal Frequency code, OE  
100M000TA  
Crystal  
Frequency  
Enable Pin  
Option  
Output Logic  
Type  
Output  
Frequency  
Shipping  
Pin 1, PECL (Active-Low), 100 MHz,   
43/Tube.  
b) MXT574DBCMXT57, 4D Crystal Frequency code, OE  
33M5000RA  
Pin 1, CMOS (Active-High), 33.5 MHz,  
1,000/Reel.  
Device:  
MXT57:  
Low Jitter, Temperature Compensated  
Crystal Oscillator (6-Lead 7x5 LLGA)  
c) MXT575CNUMXT57, 5C Crystal Frequency code, OE  
740M250TA  
Pin 2, HCSL (Active-High), 740.25 MHz,  
43/Tube,  
Crystal Frequency:  
Enable Pin Option:  
5A (Example Only) = Selected by ClockWorks Configura-  
tor; Dependent on the ordered out-  
put frequency.  
d) MXT577FNNMXT57, 7F Crystal Frequency code, OE  
3M300000RA Pin 2, CMOS (Active-Low), 3.3 MHz,  
1,000/Reel.  
B
N
=
=
Pin 1  
Pin 2  
Note 1:  
Tape and Reel identifier only appears in the  
catalog part number description. This  
identifier is used for ordering purposes and  
is not printed on the device package. Check  
with your Microchip Sales Office for package  
availability with the Tape and Reel option.  
Output Logic Type:  
(For Enable Pin 1)  
A
B
C
D
F
G
H
J
=
=
=
=
=
=
=
=
PECL (Active-High)  
LVDS (Active-High)  
CMOS (Active-High)  
HCSL (Active-High)  
PECL (Active-Low)  
LVDS (Active-Low)  
CMOS (Active-Low)  
HCSL (Active-Low)  
Output Logic Type:  
(For Enable Pin 2)  
R
S
T
U
L
M
N
P
=
=
=
=
=
=
=
=
PECL (Active-High)  
LVDS (Active-High)  
CMOS (Active-High)  
HCSL (Active-High)  
PECL (Active-Low)  
LVDS (Active-Low)  
CMOS (Active-Low)  
HCSL (Active-Low)  
Output Frequency:  
Shipping:  
xxxMxxx  
=
2.5 MHz to 850 MHz  
TA =  
43/Tube  
RA = 1,000/Reel  
Please visit http://clockworks.microchip.com/timing to select a combination of  
options to customize your product, print a specific data sheet and order samples.  
2018 Microchip Technology Inc.  
DS20006037A-page 21  
MXT57  
NOTES:  
DS20006037A-page 22  
2018 Microchip Technology Inc.  
Note the following details of the code protection feature on Microchip devices:  
Microchip products meet the specification contained in their particular Microchip Data Sheet.  
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the  
intended manner and under normal conditions.  
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our  
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data  
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.  
Microchip is willing to work with the customer who is concerned about the integrity of their code.  
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not  
mean that we are guaranteeing the product as “unbreakable.”  
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our  
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts  
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.  
Information contained in this publication regarding device  
applications and the like is provided only for your convenience  
and may be superseded by updates. It is your responsibility to  
ensure that your application meets with your specifications.  
MICROCHIP MAKES NO REPRESENTATIONS OR  
WARRANTIES OF ANY KIND WHETHER EXPRESS OR  
IMPLIED, WRITTEN OR ORAL, STATUTORY OR  
OTHERWISE, RELATED TO THE INFORMATION,  
INCLUDING BUT NOT LIMITED TO ITS CONDITION,  
QUALITY, PERFORMANCE, MERCHANTABILITY OR  
FITNESS FOR PURPOSE. Microchip disclaims all liability  
arising from this information and its use. Use of Microchip  
devices in life support and/or safety applications is entirely at  
the buyer’s risk, and the buyer agrees to defend, indemnify and  
hold harmless Microchip from any and all damages, claims,  
suits, or expenses resulting from such use. No licenses are  
conveyed, implicitly or otherwise, under any Microchip  
intellectual property rights unless otherwise stated.  
Trademarks  
The Microchip name and logo, the Microchip logo, AnyRate, AVR,  
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,  
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,  
KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,  
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,  
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip  
Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST  
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered  
trademarks of Microchip Technology Incorporated in the U.S.A.  
and other countries.  
ClockWorks, The Embedded Control Solutions Company,  
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,  
mTouch, Precision Edge, and Quiet-Wire are registered  
trademarks of Microchip Technology Incorporated in the U.S.A.  
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any  
Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,  
CodeGuard, CryptoAuthentication, CryptoCompanion,  
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average  
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial  
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,  
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,  
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,  
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,  
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple  
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,  
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,  
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and  
ZENAare trademarks of Microchip Technology Incorporated in the  
U.S.A. and other countries.  
SQTP is a service mark of Microchip Technology Incorporated in  
the U.S.A.  
Microchip received ISO/TS-16949:2009 certification for its worldwide  
headquarters, design and wafer fabrication facilities in Chandler and  
Tempe, Arizona; Gresham, Oregon and design centers in California  
and India. The Company’s quality system processes and procedures  
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping  
devices, Serial EEPROMs, microperipherals, nonvolatile memory and  
analog products. In addition, Microchip’s quality system for the design  
and manufacture of development systems is ISO 9001:2000 certified.  
Silicon Storage Technology is a registered trademark of Microchip  
Technology Inc. in other countries.  
GestIC is a registered trademark of Microchip Technology  
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology  
Inc., in other countries.  
All other trademarks mentioned herein are property of their  
respective companies.  
QUALITYMANAGEMENTꢀꢀSYSTEMꢀ  
CERTIFIEDBYDNVꢀ  
© 2018, Microchip Technology Incorporated, All Rights Reserved.  
ISBN: 978-1-5224-3134-3  
== ISO/TS16949==ꢀ  
2018 Microchip Technology Inc.  
DS20006037A-page 23  
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DS20006037A-page 24  
2018 Microchip Technology Inc.  
10/25/17  

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