PAC1932T-I/J6CX [MICROCHIP]
Single/Multi-Channel DC Power/Energy Monitor with Accumulator;
| 型号： | PAC1932T-I/J6CX |
| 厂家： | 
MICROCHIP |
| 描述： | Single/Multi-Channel DC Power/Energy Monitor with Accumulator |
| 文件： | 总64页 (文件大小：1181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PAC1931/2/3/4
Single/Multi-Channel DC Power/Energy Monitor
with Accumulator
Features
Applications
• High-Side Current Monitor with One, Two, Three
or Four Channels
• Embedded Computing
• Networking
- 100 mV full-scale range for current sense
voltage,16-bit resolution
• FPGA Systems
• Automotive
- Selectable bidirectional current sense
capability, -100 mV to +100 mV range, 16-bit
two’s complement (signed) data format
• Low Voltage/High Power – AI, GPU
• Industrial
®
• Linux Applications
- External sense resistor sets full scale current
range
• Notebook and Tablet Computing
• Cloud, Linux and Server Computing
• Optical Networking Modules
- Very low input current simplifies routing
• Wide Bus Voltage Range for Voltage Monitor
- 0V to 32V input common-mode voltage
Computing Platform Support
• Windows® 10 Driver
• Linux Driver
- 16-bit resolution for voltage measurements;
14 bits are used for power calculations
• Real Time Auto-Calibration of Offset and Gain
Errors for Voltage and Current, No User
Adjustment Required
• Python™ Script
• 1% Power Measurement Accuracy over a Wide
Dynamic Range
Description
The PAC1931/2/3/4 are one, two, three and
four-channel power and energy monitoring devices. A
high-voltage multiplexer sequentially connects the
inputs to a bus voltage monitor and current sense
amplifier that feed high-resolution ADCs. Digital
circuitry performs power calculations and energy
accumulation.
• On-Chip Accumulation of 28-bit Power Results for
Energy Measurement
- 48-bit power accumulator register for
recording accumulated power data
- 24-bit Accumulator Count
-
User programmable sampling rates of 8, 64,
256 and 1024 samples per second
This enables energy monitoring with integration
periods from 1 ms up to 36 hours or longer. Bus
voltage, sense resistor voltage and accumulated
proportional power are stored in registers for retrieval
by the system master or Embedded Controller.
- 17 minutes of power data accumulation
minimum at 1024 S/s
-
Over 36 hours of power data accumulation
minimum at 8 S/s
• 2.7V to 5.5V Supply Operation
The sampling rate and energy integration period can be
controlled over SMBus or I2C. Active channel selection,
one-shot measurements and other controls are also
configurable by SMBus or I2C.
- Separate VDD I/O pin for digital I/O
- 1.62-5.5V capable SMBus and digital I/O
-
SMBus 3.0 and I2C Fast Mode Plus (1 Mb/S)
• SMBus Address – 16 Options, set with Resistor
• No Input Filters Required
The PAC1931/2/3/4 device family uses real time
calibration to minimize offset and gain errors. No input
filters are required for this device.
• ALERT Features that can be Enabled:
- ALERT on accumulator overflow
- ALERT on Conversion Complete
• 4 × 4 × 0.5 mm UQFN Package
• 2.225 × 2.17 mm WLCSP Package
2017-2019 Microchip Technology Inc.
DS20005850E-page 1
PAC1931/2/3/4
Package Types
PAC1932/3/4 – Top View
PAC1931/2/3/4 – Top View
2.225 × 2.17 mm WLCSP
4 × 4 × 0.5 mm UQFN*
1
2
3
4
A
B
SENSE2+
SENSE2-
SENSE1-
VDD I/O
SENSE1+
PWRDN
VDD
1
12
11
10
9
SLOW/ALERT
SENSE1-
SENSE1+
2
3
4
VDD
Exposed pad
GND
GND
SENSE4+
SENSE4-
SM_CLK
C
D
SENSE3-
SENSE3+
ADDRSEL
SENSE4-
SLOW/ALERT
SENSE4+
SM_CLK
SM_DATA
*Includes Exposed Thermal Pad; see Table 3-1.
Device Block Diagram
VDD GND
SENSE 1+
VBUS1
VBUS
VBUS
Buffer/
Divider
16-bit
ADC
Sense1+
Sense1-
Registers
SENSE 1-
SENSE 2+
VDD I/O
Calculation
and
Calibration
VSENSE
Registers
Differential
VSENSE
Amplifier
VBUS2
16-bit
ADC
Sense2+
Sense2-
SENSE 2-
SENSE 3+
VPOWER
Registers
VBUS3
SM_CLK
Accumulator
Registers
Accumlator
Sense3+
Sense3-
SM_DATA
SLOW/ALERT
SENSE 3-
SENSE 4+
VBUS4
ADC/MUX Clocking &
Control
Control
Registers
PWRDN
Sense4+
Sense4-
SENSE 4-
High
Voltage
MUX
Resistor
Decoder
ADDRSEL
Note:
For PAC1931, channels 2, 3 and 4 are inactive.
For PAC1932, channels 3 and 4 are inactive.
For PAC1933, channel 4 is inactive.
DS20005850E-page 2
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
1.0
1.1
ELECTRICAL CHARACTERISTICS
Electrical Specifications
(†)
Absolute Maximum Ratings
VDD pin............................................................................................................................................................-0.3 to 6.0V
Voltage on SENSE- and SENSE+ pins............................................................................................................-0.3 to 40V
Voltage on any other pin to GND .........................................................................................................GND -0.3 to +6.0V
Voltage between Sense pins (|(SENSE+ – SENSE-)|)..........................................................................................500 mV
Input current to any pin except VDD ....................................................................................................................±100 mA
Output short-circuit current..............................................................................................................................Continuous
Junction to Ambient (J-A)...................................................................................................................................+78°C/W
Operating Ambient Temperature Range .....................................................................................................-40 to +150°C
Storage Temperature Range.......................................................................................................................-55 to +150°C
ESD Rating – all pins – HBM...................................................................................................................................4000V
ESD Rating – all pins – CDM ..................................................................................................................................2000V
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended
periods may affect device reliability.
ESD Protection Diagram
(Floating ESD rail)
SLOW/
ALERT
VDD I/O
GND
ADDRSEL
VDD
SM_DATA
SM_CLK
PWRDN
CLAMP
CIRCUIT
SENSE3+
SENSE3-
SENSE4+
SENSE4-
SENSE1+
SENSE1-
SENSE2+
SENSE2-
(~40v breakdown)
This diagram represents the ESD protection circuitry
on the PAC1934. The SENSE pins are allowed to be at
32V if VDD is at zero. The back-to-back diodes between
the Sense+ and Sense- pins have 1 kΩ resistors in
series with them.
For PAC1931, PAC1932 and PAC1933, some of the
SENSE pins are not electrically connected inside.
These unconnected pins should be grounded.
2017-2019 Microchip Technology Inc.
DS20005850E-page 3
PAC1931/2/3/4
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics: Unless otherwise specified, maximum values are at TA = -40°C to +85°C,
VDD = 2.7V to 5.5V, VDD I/O= 1.62V to 5.5V, VBUS = 0V to 32V; typical values are at TA = +25°C
VDD = VDD I/O = 3.3V, VBUS = 32V, VSENSE = (SENSE+ – SENSE-) = 0V
Characteristic
Symbol
Min.
Typ.
Max.
Unit
Conditions
Power Supply
VDD Range
VDD
VDD I/O
IDD
2.7
1.62
—
—
—
5.5
5.5
V
V
VDD I/O Range
VDD Pin Active
Current
585
675
µA 1024 Samples/s
All IDD specifications are the same
for PAC1931/2/3/4
VDD Pin Active
Current
IDD SLOW
VDD_RISE_MIN
VDD_RISE
—
—
—
16
—
—
—
µA 4 channels enabled, 8 Samples/s
Minimum VDD Rise
Rate
0.05
1000
V/ms 0 to 5V in 100 ms
V/ms 0 to 5V in 5 µs
Maximum VDD Rise
Rate
V
DD Sleep Current
IDD_SLEEP
—
—
5
—
—
µA Sleep State
VDD Power-Down
Current
IDD_PWRDN
0.1
µA Power-Down State
V
DD I/O Current
IDD I/O
—
—
—
2
µA All States
Analog Input Characteristics
VBUS Voltage Range
VBUS
–0.2V
32
V
Common-mode range for SENSE+
and SENSE- pins, referenced to
ground (negative range not tested
in production)
VSENSE Differential
Input Voltage Range
VSENSE_DIF
–100
–7
—
0
100
7
mV
SENSE+, SENSE-Pin ISENSE +, SENSE-
I
µA VSENSE+ = VSENSE- = 32V
(Input current is the combined
current for the two pins)
Input Current
SENSE+, SENSE-Pin ISENSE +, SENSE-
Input current
I
–1
—
0
1
1
µA VSENSE+ = 6V, VSENSE- = 5.9V
VBUS, VSENSE Input
RTRACE
—
k
Trace Resistance
(allowable trace
resistance without
measurement error)
VSENSE Measurement Accuracy
VSENSE Gain
Accuracy
VSENSE_
—
—
±0.2
±1
±0.9
±0.1
%
%
At +25°C
typical, -40 to +85°C
GAIN_ERR
VSENSE Offset
Accuracy, referenced
to input
VBUS_
±0.012
±0.012
mV At +25°C
mV typical, -40 to +85°C
OFFSET_ERR
VSENSE – Unidirectional Currents
VSENSE
ADC Resolution
VSENSE_RES
VSENSE_FSR
VSENSE_LSB
—
0
—
—
16
100
—
Bits Straight Binary for unidirectional
currents
VSENSE
Full Scale Range
mV Unidirectional currents
VSENSE LSB Step
Size
—
1.5
µV Unidirectional currents
DS20005850E-page 4
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
TABLE 1-1:
DC CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise specified, maximum values are at TA = -40°C to +85°C,
VDD = 2.7V to 5.5V, VDD I/O= 1.62V to 5.5V, VBUS = 0V to 32V; typical values are at TA = +25°C
VDD = VDD I/O = 3.3V, VBUS = 32V, VSENSE = (SENSE+ – SENSE-) = 0V
Characteristic
Symbol
Min.
Typ.
Max.
Unit
Conditions
VSENSE – Bidirectional Currents
VSENSE
ADC Resolution
VSENSE_RES
VSENSE_FSR
VSENSE_LSB
—
-100
—
—
—
3
16
100
—
bits 16-bit two’s complement (signed)
mV Bidirectional currents
VSENSE
Full Scale Range
V
SENSE LSB Step
Size
VBUS Measurement Accuracy
µV Bidirectional currents
VBUS Gain Accuracy
VBUS_GAIN_ERR
—
—
±0.02
±0.2
±0.5
—
%
%
At +25°C
typical, -40 to +85°C
VBUS Offset Accuracy,
referenced to input
VBUS_
±1
±2
LSB At +25°C
LSB typical, -40 to +85°C
OFFSET_ERR
VBUS – Unipolar Voltages
VBUS
ADC Resolution
VBUS_RES
VBUS_FSR
VBUS_LSB
—
0
—
—
16
32
—
bits Straight Binary for unidirectional
currents
V
BUS Unipolar
Full-Scale Range
BUS LSB Step Size
V
Unipolar voltage
V
—
488
µV FSR = 32V, 16-bit resolution
VBUS – Bipolar Voltages
VBUS ADC Resolution
VBUS_RES
VBUS_FSR
VBUS_LSB
—
–32
—
—
—
16
32
—
bits 16-bit two's complement (signed)
numbers are reported for VBUS
measurement result
VBUS Bipolar
Full-Scale Range
V
Mathematical scaling.
Physics limits the negative input
voltage to -0.2V
VBUS LSB Step Size
976
µV Bipolar voltages
Power Accumulator Accuracy
Accumulator Error
Accumulator Error
Accumulator Error
Accumulator Error
Accumulator Error
—
—
—
—
—
0.2
0.2
1
—
—
—
—
—
%
%
%
%
%
VSENSE = 97 mV
VSENSE = 10 mV
VSENSE = 1 mV
VSENSE = 100 µV
VSENSE = 50 µV
ACC_Err
ACC_Err
ACC_Err
ACC_Err
ACC_Err
3
5
Active Mode Timing
Pull-Up Voltage
Range
VPULLUP
tINT_T
1.62
—
—
14.25
3
5.5
—
V
Pull-up voltage for I2C/SMBus pins
and digital I/O pins. Set by VDD I/O.
Time to First
Communications
ms
ms
Transition From Sleep tSLEEP_TO_ACTIVE
State to Start of
—
—
Conversion Cycle
Digital I/O Pins (SM_CLK, SM_DATA, SLOW/ALERT, PWRDN)
Input High Voltage
VIH
VDD I/O
x 0.7
—
—
V
V
Input Low Voltage
VIL
—
—
VDD I/O
x 0.3
2017-2019 Microchip Technology Inc.
DS20005850E-page 5
PAC1931/2/3/4
TABLE 1-1:
DC CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise specified, maximum values are at TA = -40°C to +85°C,
VDD = 2.7V to 5.5V, VDD I/O= 1.62V to 5.5V, VBUS = 0V to 32V; typical values are at TA = +25°C
VDD = VDD I/O = 3.3V, VBUS = 32V, VSENSE = (SENSE+ – SENSE-) = 0V
Characteristic
Symbol
Min.
Typ.
Max.
Unit
Conditions
Output Low Voltage
VOL
—
—
0.4
V
Sinking 8 mA for the ALERT pin
and 20 mA for the SMCLK pin
Leakage Current
ILEAK
–1
—
+1
µA
DS20005850E-page 6
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
TABLE 1-2:
SMBUS MODULE SPECIFICATIONS
Electrical Characteristics: Unless otherwise specified, maximum values are at TA = -40°C to +85°C,
VDD = 2.7V to 5.5V, VBUS = 0V to 32V; Typical values are at TA = +25°C, VDD = 3.3V, VBUS = 32V,
VSENSE = (SENSE+ – SENSE-) = 0V, VDD I/O = 1.62V to 5.5V
Characteristic
Sym.
Min.
Typ.
Max.
Units
Conditions
SMBus Interface
Input Capacitance
SMBus Timing
Clock Frequency
CIN
—
4
10
1
pF
Not tested in production
fSMB
.010
—
MHz No minimum if Time-Out is not
enabled
Spike Suppression
tSP
0
—
—
50
—
ns
Bus Free Time Stop to
Start
tBUF
0.5
µs
Per SMBus 3.0
Per SMBus 3.0
Hold Time after
Repeated Start
Condition
tHD:STA
0.26
0.26
—
—
—
—
µs
Repeated Start
Condition Setup Time
tSU:STA
µs
Per SMBus 3.0
Per SMBus 3.0
Setup Time: Stop
Setup Time: Start
Data Hold Time
tSU:STO
tSU:STA
tHD:DAT
tSU:DAT
tLOW
0.26
0.26
0
—
—
—
—
—
—
—
—
—
—
—
µs
µs
µs
ns
µs
µs
ns
ns
pF
—
Data Setup Time
Clock Low Period
Clock High Period
Clock/Data Fall Time
Clock/Data Rise Time
Capacitive Load
50
—
Per SMBus 3.0 (Note)
0.5
0.26
—
—
Per SMBus 3.0
tHIGH
50
tFALL
120
120
550
Not tested in production
Not tested in production
tRISE
—
CLOAD
—
Per bus line,
CLOAD not tested in production
SLOW Pin Pulse Width SLOWpw
—
100
—
µs
Pulses narrower than 100 µS
may not be detected
Note:
A device must internally provide a hold time of at least 300 ns for the SM_DATA signal (with respect to the
VIH(min) of the SM_CLK signal) to bridge the undefined region of the falling edge of SM_CLK.
TLOW
THIGH
THD:STA
TSU:STO
TRISE
TFALL
TSU:DA
SMCLK
THD:DAT
TSU:STA
THD:STA
T
SMDATA
TBUF
S
S
P
P
S - Start Condition
P - Stop Condition
FIGURE 1-1:
SMBus Timing.
2017-2019 Microchip Technology Inc.
DS20005850E-page 7
PAC1931/2/3/4
2.0
TYPICAL OPERATING CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, maximum values are at TA = -40°C to +85°C, VDD = 2.7V to 5.5V, VBUS = 0V to 32V;
typical values are at TA = +25°C, VDD = 3.3V, VBUS = 3.3V, VSENSE = (SENSE+ – SENSE-) = 0V, VDD I/O = 1.62 to 5.5V.
10
5
25
20
15
10
5
o
o
3.3vDC -40 C
3.3vDC 25 C
o
3.3vDC 0 C
o
3.3vDC 25 C
o
3.3vDC 85 C
o
3.3vDC 125 C
0
0
-5
5
-10
-15
-10
10uV
100uV
1mV
10mV
100mV
1uV
10uV
0.1mV
1mV
10mV
100mV
Sense Input Voltage
Sense Input Voltage
FIGURE 2-1:
VSENSE Error vs. VSENSE
FIGURE 2-4:
VSENSE Error vs. VSENSE
Input Voltage.
Input Voltage and Temperature.
0.025%
o
o
CM3.3v 3.3vDC 25 C
CM3.3v 3.3vDC 25 C
0.025%
0.0125%
0
0.0125%
0
0.0125%
-0.025%
-0.0125%
-0.025%
-1mV
-0.5mV
0
0.5mV
1mV
-80 -60 -40 -20
0
20 40 60 80
Sense Input Voltage
Sense Input Voltage (mV)
FIGURE 2-2:
V
SENSE Error vs. VSENSE
FIGURE 2-5:
VSENSE Error vs. VSENSE
Input Voltage Bidirectional Mode.
Input Voltage Bidirectional Mode (Zoom View).
0.05%
0.05%
0
0.025%
0
-0.05%
o
o
CM1v 3.3vDC 25 C
Ch1 3.3vDC -40 C
o
o
CM3v 3.3vDC 25 C
Ch1 3.3vDC 0 C
o
o
-0.025%
-0.1%
CM5v 3.3vDC 25 C
Ch1 3.3vDC 25 C
o
o
CM16v 3.3vDC 25 C
Ch1 3.3vDC 85 C
o
o
Ch1 3.3vDC 125 C
-0.15%
CM32v 3.3vDC 25 C
-0.05%
0
20mV
40mV
Sense Input Voltage
60mV
80mV
100mV
0
20mV
40mV
60mV
80mV
100mV
Sense Input Voltage
FIGURE 2-3:
VSENSE Error vs. VSENSE
FIGURE 2-6:
VSENSE Error vs. VSENSE
Input Voltage vs. Temperature.
and Common Mode.
DS20005850E-page 8
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
Note: Unless otherwise indicated, maximum values are at TA = -40°C to +85°C, VDD = 2.7V to 5.5V, VBUS = 0V to 32V;
typical values are at TA = +25°C, VDD = 3.3V, VBUS = 3.3V, VSENSE = (SENSE+ – SENSE-) = 0V, VDD I/O = 1.62 to 5.5V.
25
20
15
10
5
25
20
15
10
5
o
o
3.3vDC -40 C
3.3vDC 25 C
o
3.3vDC 0 C
o
3.3vDC 25 C
o
3.3vDC 85 C
o
3.3vDC 125 C
0
0
1mV
10mV
0.1V
Input Voltage
1V
10V
1mV
10mV
0.1V
Input Voltage
1V
10V
FIGURE 2-7:
VBUS Error vs. VBUS Input
FIGURE 2-10:
VBUS Error vs. VBUS Input
Voltage.
Voltage vs. Temperature.
2%
1%
0
2%
1%
o
3.3vDC 25 C
0
o
3.3vDC -40 C
o
3.3vDC 0 C
o
3.3vDC 25 C
-1%
-1%
-2%
o
3.3vDC 85 C
o
3.3vDC 125 C
-2%
10mV
100mV
1V
10V
10mV
100mV
1V
10V
32V
Input Voltage
Input Voltage
FIGURE 2-8:
VBUS Error vs. VBUS Input
FIGURE 2-11:
VBUS Error vs. VBUS Input
Voltage (Zoom View).
Voltage vs. Temperature (Zoom View).
0.1%
0
o
0.05%
0
3.3vDC 25 C
-0.2%
-0.4%
o
3.3vDC -40 C
o
-0.05%
-0.1%
3.3vDC 0 C
o
-0.6%
3.3vDC 25 C
o
3.3vDC 85 C
o
3.3vDC 125 C
-0.8%
0
5
10
15
20
25
30
-0.5v
0v
0.5v
1v
Input Voltage
Input Voltage
FIGURE 2-9:
Voltage.
VBUS Error vs. VBUS Input
FIGURE 2-12:
Voltage vs. Temperature (Bipolar Voltage Mode).
VBUS Error vs. VBUS Input
2017-2019 Microchip Technology Inc.
DS20005850E-page 9
PAC1931/2/3/4
Note: Unless otherwise indicated, maximum values are at TA = -40°C to +85°C, VDD = 2.7V to 5.5V, VBUS = 0V to 32V;
typical values are at TA = +25°C, VDD = 3.3V, VBUS = 3.3V, VSENSE = (SENSE+ – SENSE-) = 0V, VDD I/O = 1.62 to 5.5V.
o
3.3vDC -40 C
0
-0.2
-0.4
-0.6
-0.8
-1
o
0.2%
0.1%
0
3.3vDC 0 C
o
3.3vDC 25 C
o
3.3vDC 85 C
o
3.3vDC 125 C
-0.1%
-0.2%
-40
0
25
55
85
125
0v
5v
10v
15v
20v
25v
30v
o
Input Voltage
Temperature ( C)
FIGURE 2-13:
VBUS Error vs. VBUS Input
FIGURE 2-16:
Input Offset for VBUS
Voltage vs. Temperature.
Measurements vs. Temperature.
0
-0.2
-0.4
-0.6
-0.8
-1
-40
0
25
55
85
125
o
Temperature ( C)
FIGURE 2-14:
BUS (LSBs, 8X Average Results, Total
Population 5,000 devices).
Zero Input Histogram for
FIGURE 2-17:
Measurements vs. Temperature.
Input Offset for VSENSE
V
70
VIO=1.6v VDD=2.6v
60
50
40
30
20
10
0
VIO=5.5v VDD=5.5v
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
SMBUS Output Voltage (VOL)
FIGURE 2-18:
vs. VOL
I2C/SMBus Drive Current
FIGURE 2-15:
VSENSE (LSBs, 8X Average Results, Total
Population 5,000 Devices).
Zero Input Histogram for
.
DS20005850E-page 10
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
Note: Unless otherwise indicated, maximum values are at TA = -40°C to +85°C, VDD = 2.7V to 5.5V, VBUS = 0V to 32V;
typical values are at TA = +25°C, VDD = 3.3V, VBUS = 3.3V, VSENSE = (SENSE+ – SENSE-) = 0V, VDD I/O = 1.62 to 5.5V.
640
2.6v
2.7v
3.3v
620
5.0v
5.5v
600
5.6v
580
560
540
520
-40
0
25
55
85
125
o
Temperature ( C)
FIGURE 2-19:
IDD vs. Temperature and
FIGURE 2-22:
IDD vs.Temperature, VDD,
Supply at 1024 Samples/Second.
and Sample Rate.
60
30
2.6v
2.6v
2.7v
2.7v
3.3v
5.0v
5.5v
25
50
40
30
20
10
3.3v
5.0v
5.5v
5.6v
20
5.6v
15
10
5
0
-40
0
25
55
85
125
-40
0
25
55
85
125
o
o
Temperature ( C)
Temperature ( C)
FIGURE 2-20:
IDD in SLOW Mode vs.
FIGURE 2-23:
IDD in SLEEP Mode vs.
Temperature and VDD
.
Temperature and VDD.
12
0.15
0.1
0.05
0
VDD 2.6v/VIO 1.7v
2.6v
2.7v
3.3v
5.0v
5.5v
5.6v
VDD 5.6v/VIO 1.7v
VDD 2.6v/VIO 5.6v
VDD 5.6v/VIO 5.6v
10
8
6
4
2
0
-40
0
25
55
85
125
-40
0
25
55
85
125
o
o
Temperature ( C)
Temperature ( C)
FIGURE 2-21:
IDD for VDD I/O Pin vs.
FIGURE 2-24:
IDD in Power Down Mode
Temperature and VDD
.
vs. Temperature and VDD.
2017-2019 Microchip Technology Inc.
DS20005850E-page 11
PAC1931/2/3/4
Note: Unless otherwise indicated, maximum values are at TA = -40°C to +85°C, VDD = 2.7V to 5.5V, VBUS = 0V to 32V;
typical values are at TA = +25°C, VDD = 3.3V, VBUS = 3.3V, VSENSE = (SENSE+ – SENSE-) = 0V, VDD I/O = 1.62 to 5.5V.
2
1.5
1
0.03
0.025
0.02
0.015
0.01
0.005
0
0v CM
1v CM
5v CM
16v CM
32v CM
0v CM
1v CM
5v CM
16v CM
32v CM
0.5
0
-0.5
-40
0
25
55
85
125
-40
0
25
55
85
125
o
o
Temperature ( C)
Temperature ( C)
FIGURE 2-25:
VSENSE Input Current –
FIGURE 2-28:
VSENSE Input Leakage
Active Mode, 1024 Samples/Second.
Current vs. VDD and Temperature.
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0v
1v
5v
16v
32v
-40
0
25
55
85
125
o
Temperature ( C)
FIGURE 2-26:
VBUS Input Leakage Current
FIGURE 2-29:
Clock Frequency Error
vs. VDD and Temperature.
-40°C to +85°C. Total Population 200 Devices.
2.5
0v
1v
5v
2
16v
32v
1.5
1
0.5
0
-40
0
25
55
85
125
o
Temperature ( C)
FIGURE 2-27:
VBUS Input Current – Active
FIGURE 2-30:
Clock Frequency Error at
Mode, 1024 Samples/Second.
30°C. Total Population 11,189 Devices.
DS20005850E-page 12
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
Figure 2-31 shows the equivalent circuitry for the input
channels of the PAC193X devices. ESD protection
diodes include two 40V breakdown diodes. Input
leakage current is very low (no DC bias current). The
switched capacitor sampling circuits shown as a switch
with equivalent series resistance and sampling
capacitor. The switches work at 1024 samples per
second (SPS) maximum, independent of sampling rate
(at 8 SPS, the device is sleeping in between samples).
Input impedance for each input is about 32 MΩ.
6 kΩ
VSENSE-
1 kΩ
6 kΩ
1
30 pF
1
1 kΩ
30 pF
29 kΩ
VSENSE+
1.2 pF
40V
40V
1
1
VSS/GND
FIGURE 2-31:
Equivalent Input Circuits for PAC193X Devices.
2017-2019 Microchip Technology Inc.
DS20005850E-page 13
PAC1931/2/3/4
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN DESCRIPTIONS
QFN
WLCSP16
Symbol
Pin Type
Description
1
C3
SLOW/ALERT
Digital I/O pin
Voltage range is set by V I/O pin. Default function is
DD
SLOW, may be programmed to function as ALERT pin
(Open Collector when functioning as ALERT, requires pull-up
resistor to V I/O).
DD
2
3
4
5
6
A4
B4
C4
D4
C2
V
Power for IC
Positive power supply voltage
Ground for the IC
DD
GND
Ground pin
SM_CLK
SM_DATA
ADDRSEL
SENSE3-
SENSE3+
SENSE4-
SENSE4+
SENSE1+
SENSE1-
SENSE2+
SENSE2-
SMBus clock input
SMBus data I/O
Analog I/O pin
32V analog pin
32V analog pin
32V analog pin
32V analog pin
32V analog pin
32V analog pin
32V analog pin
32V analog pin
Clock Input pin
Open drain requires pull-up resistor to V I/O
DD
Address selection for the SMBus Slave address
0-32V range, connect to load side of sense resistor
0-32V range, connect to supply side of sense resistor
0-32V range, connect to load side of sense resistor
0-32V range, connect to supply side of sense resistor
0-32V range, connect to supply side of sense resistor
0-32V range, connect to load side of sense resistor
0-32V range, connect to supply side of sense resistor
0-32V range, connect to load side of sense resistor
Digital power reference level for digital I/O
(1)
(2)
7
C1
D1
D2
D3
(1)
8
(1)
(2)
(2)
(2)
9
(1)
10
11
12
13
14
15
A3
A2
2)
(
(
A1
B1
2)
B2
B3
—
V
I/O
Sets V
IH
reference for digital
I/O
DD
16
17
PWRDN
EP
Digital input pin
Voltage range is set by V I/O pin. Active low puts the
DD
device in power-down state (all circuitry is powered down
including SMBus).
N/C
The Exposed pad is not electrically connected
Note 1: For PAC1932, pins 7,8,9,10 are not connected inside and should be grounded.
For PAC1933, pins 9 and 10 are not connected inside and should be grounded.
2: For PAC1931, solder balls on A1, B1, C1, D1, D2, and D3 are present but the channels are disabled internally and
should be grounded. For PAC1932, solder balls on C1, D1, D2, and D3 are present but the channels are disabled
internally and should be grounded. For PAC1933, solder balls on D2 and D3 are present but the channels are disabled
internally and should be grounded.
3.1
SenseN+/SenseN– (N=1,2,3,4)
3.5
Positive Power Supply Voltage
(V
)
DD
These two pins form the differential input for measuring
voltage across a sense resistor in the application. The
positive input (SenseN+) also acts as the input pin for
bus voltage.
Power supply input pin for the device. 2.7-5.5V range,
bypass with 100 nF ceramic capacitor to ground near
the IC.
3.2
Ground (GND)
3.6
Digital Power Reference Voltage
(V
)
DD I/O
System ground.
Connect this pin to the power supply voltage for the
digital controller driving the SMBus pins and digital
input pins for the device, 1.62V-5.5V. Bypass with
100 nF ceramic capacitor to ground near the IC. This
pin does not supply power, instead it acts as the VIH
reference.
3.3
SMBus Data (SM_DATA)
This is the bi-directional SMBus data pin. This pin is
open drain, and requires a pull-up resistor to VDD I/O.
3.4
SMBus Clock (SM_CLK)
This is the SMBus clock input pin.
DS20005850E-page 14
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
3.7
Address Selection (ADDR_SEL)
Connect a resistor from this pin to ground to select
SMBus address.
3.8
Enable Pin (PWRDN)
Power down input pin for the device, active low.
3.9
SLOW/ALERT
In default mode, if this pin is forced high, sampling rate
is forced to eight samples/second. When it is forced
low, the sampling rate is 1024 samples/second unless
a different sample rate has been programmed.This pin
may be programmed to act as the ALERT pin, in
ALERT mode the pin needs a pull-up resistor to VDD
I/O.
3.10 Exposed Thermal Pad Pin (EP)
The Exposed pad is not electrically connected. It is
recommended that you connect it to ground.
2017-2019 Microchip Technology Inc.
DS20005850E-page 15
PAC1931/2/3/4
V
SENSE are converted to digital results by a 16-bit ADC,
4.0
GENERAL DESCRIPTION
and the digital results are multiplied to give VPOWER
.
The PAC1934 is a four-channel, bidirectional, high-side
current-sensing device with precision voltage
measurement capabilities, DSP for power calculation
and a power accumulator. PAC1931, PAC1932 and
PAC1933 are one, two and three-channel versions of
the PAC1934. These devices measure the voltage
The VPOWER results are accumulated on-chip, which
enables energy measurement over the accumulation
period.
The PAC1931/2/3/4 has an I2C/SMBus interface for
digital control and reading results. It also has digital
supply reference VDD I/O that is to be connected to the
same supply as the digital master for the I2C/SMBUS,
enabling digital I/O voltages as low as 1.62V.
developed across an external sense resistor (VSENSE
)
to represent the high-side current of a battery or
voltage regulator. The PAC1931/2/3/4 also measures
the SENSE+ pin voltages (VBUS). Both VBUS and
A system diagram is shown in Figure 4-1.
Sense
Resistors
VSOURCE 0V – 32V
VSOURCE 0V – 32V
VSOURCE 0V – 32V
Load
Load
Load
VSOURCE 0V – 32V
Load
1.62V to 5.5V
Digital Supply
2.7V to 5.5V
VDD I/O
VDD
PAC193X
System
Master
SM_CLK
SM_DATA
SLOW
ADDRSEL
GND
PWRDN
Note:
VDD and VDD I/O may be connected together.
FIGURE 4-1:
PAC1931/2/3/4 System Diagram.
DS20005850E-page 16
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
VDD GND
SENSE 1+
VBUS1
VBUS
VBUS
Buffer/
Divider
16-bit
ADC
Sense1+
Sense1-
Registers
SENSE 1-
SENSE 2+
VDD I/O
Calculation
and
Calibration
VSENSE
Registers
Differential
VSENSE
Amplifier
VBUS2
16-bit
ADC
Sense2+
Sense2-
SENSE 2-
SENSE 3+
VPOWER
Registers
VBUS3
SM_CLK
Accumulator
Registers
Accumlator
Sense3+
Sense3-
SM_DATA
SLOW/ALERT
SENSE 3-
SENSE 4+
VBUS4
ADC/MUX Clocking &
Control
Control
Registers
PWRDN
Sense4+
Sense4-
SENSE 4-
High
Voltage
MUX
Resistor
Decoder
ADDRSEL
FIGURE 4-2:
PAC1931/2/3/4 Functional Block Diagram.
FIGURE 4-3:
PCB Pattern for Sense
Resistor.
Figure 4-3 shows the recommended PCB pattern for
sense resistor with wide metal for the high-current path.
The drawing shows metal, solder paste openings and
resistor outline. VSOURCE connects to the +terminal of the
high-current path, and the load connects to the -terminal
of the high-current path. Sense+ and Sense- have a
Kelvin connection to the current sense resistor to ensure
that no metal with high current is included in the VSENSE
measurement path. Sense+ and Sense- are shown as a
differential pair, route them as a differential pair to the
Sense inputs at the chip. The input pins allow for a typical
VSENSE trace resistance of 1 k, which allows the routing
flexibility far away from the chip itself on the board.
2017-2019 Microchip Technology Inc.
DS20005850E-page 17
PAC1931/2/3/4
data conversion and power integration is not
interrupted and will continue as determined by the
settings in the Control register.
4.1
Detailed Description
A high-voltage multiplexer connects the input pins to
the VBUS and VSENSE amplifiers. The amplifier outputs
are sampled simultaneously for each channel,
converted by 16 bit ADCs and processed for gain and
offset error correction. After each conversion, VBUS
Changes written to the control and configuration
registers take effect 1 mS after a REFRESH command
is sent. Any new commands written within this 1 mS
window will be ignored and NACKed to indicate that
they are ignored.
and VSENSE are multiplied together to give VPOWER
.
An internal oscillator and digital control signals control
the two ADCs and the mux. The mux sequentially
connects each channel’s amplifiers to the ADC inputs.
The values for VBUS and VSENSE measurement results
and Power calculation results respond to the
REFRESH command in the same fashion as the
accumulators and accumulator count. The readable
registers will be stable within 1 mS from sending the
REFRESH command and may be read by the master
at any time. The internal values continue to be
updated according to the sampling plan determined by
the settings in the Control register. The results that are
sent to the readable registers for VBUS, VSENSE and
Power are the values from the most recent complete
conversion cycle. See Register 6-1 REFRESH
Command (Address 00h).
The PAC1931/2/3/4 measures the source-side voltage,
VBUS, and the voltage VSENSE across an external
current sense resistor, RSENSE
.
4.1.1
INITIAL OPERATION AND ACTIVE
STATE
After POR and a start-up sequence, the device is in
the Active state and begins sampling the inputs
sequentially. Voltage and current are sampled for all
active channels and power is calculated and
accumulated. All active channels are sampled at 1024
samples/second by default. Sample rates of 256, 64 or
eight samples/second may be programmed over I2C
or SMBus. If the SLOW pin is asserted the sample rate
is eight samples per second. For sampling rates lower
than 1024 samples/second, the device is in Sleep
mode for a portion of the conversion cycle, which
results in lower power dissipation. If fewer than four
channels are active, power is also reduced.
4.1.3
REFRESH_G COMMAND
The REFRESH_G is identical in every respect to the
REFRESH command, but it is used with the I2C
General Call address (0000 000). This allows the
system to issue a REFRESH command to all of the
PAC1931/2/3/4 devices in the system with a single
command. Then the data from this REFRESH_G
command may be read device-by-device to capture a
snapshot of the system power and energy for all
devices. See Register 6-12 REFRESH_G Command
(Address 1Eh). Note that the REFRESH_G command
can also be used with a valid Slave address but in this
case only the device with this Slave address will
receive the command. In other words it has the same
properties as the REFRESH command with the
possibility of being compatible with the I2C General
Call address.
To read accumulator data and reset the accumulators,
the REFRESH command is used. To read the voltage,
current, power and accumulator data without resetting
the accumulators, the REFRESH_V command is
used. Changes to the Control register (01h) are
activated by sending either REFRESH or
REFRESH_V. When a new value is written to the
Control register (01h), the new values take effect at
the end of the next round-robin sampling cycle
following the next REFRESH or REFRESH_V
command.
4.1.4
REFRESH_V COMMAND
If the user wants to read VSENSE and VBUS results, the
most recent Power calculation, and/or the accumulator
values and count without resetting the accumulators,
the REFRESH_V command may be sent. Sending the
REFRESH_V command and waiting 1 mS ensures that
4.1.2
REFRESH COMMAND
The master sends the REFRESH command after
changing the Control register and/or before reading
accumulator data from the device. The master controls
the accumulation period in this manner.
the VSENSE
,
VBUS
,
Power, accumulator and
accumulator count values will be stable when read by
the master. The sampling of the inputs, data conversion
and power integration are not interrupted and will
continue as determined by the settings in the Control
register. The data in these readable registers will
remain stable until the next REFRESH or REFRESH_V
command. The internal accumulator values and
accumulator count are unaffected by the REFRESH_V
command.
The readable registers for the VBUS, VSENSE, Power,
accumulator outputs and accumulator count are
updated by the REFRESH command and the values
will be static until the next REFRESH command.
These readable registers will be stable within 1 mS
from sending the REFRESH command, and may be
read by the master at any time up until the next
REFRESH command is sent. The internal accumulator
values and accumulator count will be reset by the
REFRESH command, but the sampling of the inputs,
DS20005850E-page 18
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
Note that the REFRESH_V command may also be
used to activate changes to the Control register, just
like the REFRESH command, except with the
REFRESH_V command changes to the Control
register will be enacted without resetting the
new sample rate to take effect and for all the sample
rate related registers (like CTRL_ACT) to show their
updated values.
If one of these lower sample rates is used, power
dissipation is reduced. The round-robin sampling and
conversion cycle is exactly the same, but the device
goes into the sleep state between conversion cycles.
See Section 2.0 “Typical Operating Curves”.
accumulators
or
accumulator
count.
See
Register 6-13 REFRESH_V Command (Address
1Fh).
If the SLOW pin is pulled high, the device will sample
at eight samples/second. No matter what the
programmed sample rate, this new SLOW sample rate
will take effect on the next conversion cycle (if a
round-robin conversion cycle is in process when the
SLOW pin goes high, that conversion cycle will
complete before the SLOW sample rate takes effect.)
4.1.5
SLEEP STATE
The SLEEP state is a lower power state than the
Active state. While in this state, the device will draw a
supply current of ISLEEP from the VDD pin. The device
automatically goes to this state between conversion
cycles when sampling rates lower than 1,024
samples/second are selected, or if fewer than four
channels are active. All digital states and data are
retained in the SLEEP state. The device can also be
put in the Sleep state by setting the SLEEP bit
followed by a REFRESH or REFRESH_V command,
and sampling will resume when the SLEEP bit is
cleared followed by a REFRESH of REFRESH_V
command. The device does not go into SLEEP state
based on any other condition such as static conditions
on the SMBus pins. If SMBus Timeout is enabled, it is
supported in SLEEP mode or ACTIVE mode.
If the device is programmed for Single Shot mode, and
the SLOW pin is asserted, the first sampling will begin
within 125 ms after the SLOW pin is asserted.
If the device is in the Sleep state, asserting the SLOW
pin will not cause sampling to start.
Whenever the SLOW pin changes state, a limited
REFRESH or REFRESH_V command may be
executed by the chip hardware (default is REFRESH).
Like any other REFRESH command, this resets the
accumulators and accumulator count for a REFRESH
command, and updates the readable registers for
either REFRESH or REFRESH_V. These are limited
REFRESH commands because no programmed
changes to the Control or Status registers take effect
(Control and Status registers means registers 01h,
1Ch, 1Dh, and 20h-26h). The readable registers are
stable with the new values within 1 ms of the SLOW
pin transition.
4.1.6
POWER-DOWN STATE
The Power-Down state is entered by pulling the
PWRDN pin low. In this state, all circuits on the chip
including the SMBus pins are inactive, and the device
is in a state of minimum power dissipation.
In the Power-Down state, no data is retained in the
chip (neither register configuration nor measurement
data). When the PWRDN pin is pulled high,
integration, measurement and accumulation will begin
using the default register settings, as described in
Section 4.1.1 “Initial Operation and Active State”.
The first measurement data may be requested by a
REFRESH or REFRESH_V command 20 ms after the
PWRDN pin is pulled high.
The Slow register enables selection of REFRESH or
REFRESH_V on the SLOW pin transitions, which
allows this function to be disabled for either edge, and
also tracks both the state of the SLOW pin and
transitions on the SLOW pin. See Register 6-14,
SLOW (Address 20h).
This is the default functionality of the SLOW pin, but it
may be reconfigured to function as an ALERT pin (see
paragraph Section 4.4 “Alert Functionality”). If the
SLOW pin is configured to serve as an ALERT pin, the
slower sampling rate of eight samples/second is only
available by programming the Control register 01h.
4.1.7
PROGRAMMING THE SAMPLE
RATE AND THE SLOW PIN
The default sampling rate after power-up is 1024
samples/second. Sampling rates of 256, 64 or 8
samples/second may be programmed in the
Register 6-2 CTRL Register (Address 01h). Any time
a new sample rate is programmed, it does not take
effect until
a
REFRESH, REFRESH_G, or
REFRESH_V command is received. When any of
these REFRESH commands are received, any
round-robin sampling cycle in progress will complete
before the new sampling rate takes effect. For
example, if the user is sampling at 8 SPS and program
a new sample rate, it may take up to 125 mS for the
2017-2019 Microchip Technology Inc.
DS20005850E-page 19
PAC1931/2/3/4
4.2
Conversion Cycles
4.4
Alert Functionality
A
conversion cycle for the device consists of
The Alert functionality can serve two purposes: to
notify the system that a conversion cycle for all active
channels is complete, or to notify the system that the
accumulator or accumulator count has overflowed.
analog-to-digital conversion being complete for all
channels (including the real-time calibration that is part
of each conversion cycle). Immediately following the
data conversion, the power results are calculated for
that channel and the power value is added to the
accumulator. Averaged values for VSENSE and VBUS
are also updated internally as part of each conversion
cycle.
4.4.1
USING THE ALERT FUNCTION
To use the ALERT function, configure the SLOW pin to
function as ALERT using Register 6-2 CTRL Register
(Address 01h). For this configuration, the ALERT pin
must have a pull-up to VDD I/O (it will function as an
open drain output). If a pull-up resistor is attached to
the pin for Alert functionality, the device will power up
in Slow mode. Any of the four sample rates can be
programmed using Register 6-2 CTRL Register
(Address 01h).
Data conversion and processing is performed for each
active channel in sequential fashion until all active
channels have been converted, completing the
conversion cycle for the device. The sequential
sampling of each channel, along with the calculation
time and any sleep time needed to set the overall
sampling rate, is referred to as a round-robin sampling
period.
The Alert function for Accumulator Overflow can also
be used without reconfiguring the SLOW pin, by
monitoring the OVF bit in Register 6-2 CTRL Register
(Address 01h).
4.3
Conversion Cycle Controls
4.3.1
REDUCING THE NUMBER OF
CHANNELS TO BE SAMPLED
4.4.2
ALERT AFTER COMPLETE
CONVERSION
Program Register 6-10 CHANNEL_DIS and SMBus
(Address 1Ch) to reduce the number of channels that
are active. The sample rate is unaffected, but power
dissipation is reduced very slightly if some channels
are disabled. Any or all channels may be disabled; if
all channels are disabled, the device goes into Sleep
mode. When a channel is disabled due to register
programming in the PAC1934, or due to factory
programming on the PAC1931, PAC1932 and
PAC1933, the auto-incrementing pointer will skip
these channels by default (see Section 5.5
“Auto-Incrementing Pointer”).
Register 6-2 has an ALERT_CC bit that can be used
to enable the ALERT_CC function. If this bit is set, the
ALERT pin will go low for 5 μS after each complete
conversion cycle is complete.
4.4.3
ALERT ON ACCUMULATOR
OVERFLOW
If the ALERT function is enabled, and any of the
accumulators or the accumulator count overflow, the
ALERT pin may be used to notify the system. To
enable this trigger for the ALERT pin, bit 1 in the
Register 6-2 CTRL Register (Address 01h) must be
set. Note that the OVF bit in the Register 6-2 CTRL
Register (Address 01h) will be set when these
overflows occur.
4.3.2
SINGLE SHOT MODE
The Control register also allows the device to operate
in Single Shot mode. In Single Shot mode, all active
channels will sample and convert once, followed by
results being calculated. The accumulator and
accumulator count operate the same as for continuous
conversion mode, accumulating each single shot
power calculation and incrementing the accumulator
count. The conversion cycle will start when the
4.4.4
CLEARING ALERT AND OVF
When the Alert function has been tripped by
accumulator or accumulator count overflow, it will
remain asserted until a REFRESH command is
received. REFRESH_G will also clear the OVF bit and
the Alert function, but REFRESH_V will not.
REFRESH
command
(or
REFRESH_V
or
REFRESH_G) is sent.
After the single shot measurements and calculations
are complete, the device will go into Sleep mode. A
REFRESH, REFRESH_G or REFRESH_V command
may be sent to read the data. The user needs to wait
3 ms after the REFRESH command before
commanding another Single Shot conversion by
means of sending one of the REFRESH commands.
This is because a 1 ms delay is required between
REFRESH commands, and coming out of Sleep
requires 2 ms.
DS20005850E-page 20
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
4.5
Voltage Measurement
4.7
Selecting R
Values
SENSE
The VBUS voltage for each channel is measured by the
SENSE+ pin for each channel. high-voltage
RSENSE can easily be calculated if you know the
maximum current you want to sense, as shown in
Equation 4-2.
A
multiplexer is connected to each SENSE+ pin, and the
multiplexer sequentially connects each SENSE+ input
to an ADC for conversion. The result is stored in a
16-bit VBUS results register and the 14 MSBs are
multiplied by the VSENSE number for the VPOWER
results value. The VPOWER results are accumulated in
the accumulator.
Consider that you may need to select a value for IMax
that includes current peaks well beyond your nominal
current.
EQUATION 4-2:
CALCULATING RSENSE
FSR
Rsense = -------------
IMax
Full-Scale Voltage (FSV) is 32V by default. The device
may be programmed for bipolar VBUS measurements.
in this bipolar mode, the mathematical range for
negative VBUS numbers is -32V, the actual range is
limited to about -200mV due to physical factors. This
bipolar capability for VBUS enables accurate offset
measurement and correction. For bipolar operation,
the 16-bit VBUS result is a two’s complement (signed)
number.
Where:
FSR
RSENSE
IMax
=
=
=
Full Scale VSENSE voltage input
External RSENSE resistor value
Maximum current to measure
Full-Scale Current (FSC) can be calculated from
Equation 4-3.
The measured voltage at SENSE+ can be calculated
using Equation 4-1.
EQUATION 4-3:
FULL-SCALE CURRENT
EQUATION 4-1:
BUS VOLTAGE
100 mV
FSC = ----------------------
VBUS
R
VSource = 32V ----------------------------------
SENSE
Denominator
Where:
Where:
VSOURCE
FSC
=
=
Full-scale current
=
=
The measured voltage on the
SENSE+ pin
RSENSE
External sense resistor value
VBUS
The value read from the VBUS
results registers
The actual current through RSENSE can then be
calculated using Equation 4-4.
Denominator
=
=
216 for unipolar measurements
215 for bipolar measurements
EQUATION 4-4:
SENSE CURRENT
V
SENSE
ISENSE = FSC ----------------------------------
Denominator
4.6
Current Measurement
Where:
The PAC1931/2/3/4 device family includes high-side
current sensing circuits. These circuits measure the
voltage (VSENSE) induced across a fixed external
current sense resistor (RSENSE) and store the voltage
as a 16-bit number in the VSENSE Results registers.
ISENSE
FSC
=
=
Actual bus current
Full-scale current value (from
Equation 4-3)
The PAC1931/2/3/4 current sensing operates with a
Full-Scale Range (FSR) of 100 mV in unidirectional
mode (default).
VSENSE
=
The value read from the
VSENSE results registers
216 for unipolar measurements
Denominator
=
=
When sensing unidirectional currents (the default
mode), the ADC results are presented in straight binary
format. For bidirectional current sensing, the ADC
results are in two’s complement (signed) format. For
bipolar current measurements, the range is ±100 mV,
but use FSR = 100 mV in the equations that follow. For
best accuracy on current values near zero, it is
recommended to use the bidirectional current mode
and 8x average current results.
2
15 for bipolar measurements
2017-2019 Microchip Technology Inc.
DS20005850E-page 21
PAC1931/2/3/4
4.8
ADC Measurements, Offset, and
8x Averaging
The PAC1931/2/3/4 is primarily desired for energy
measurements where many power readings are
accumulated. This is inherently an averaging process.
Individual voltage and current measurements can also
benefit from averaging to reduce noise and offset.
Averaged values are internally calculated for VBUS and
VSENSE, with a rolling average of the most recent eight
values present in the VBUSn_AVG (Register 6-7) and
VSENSEn_AVG (Register 6-6) registers. The average
is updated internally after every conversion cycle. The
readable registers are updated with REFRESH,
REFRESH_V, or REFRESH_G commands like all the
other readable results registers. These averaged
results may be used for the most accurate, lowest
noise and lowest offset measurements.
FIGURE 4-4:
Illustration of the Four
Permute Combinations that the ADC Cycles
through and the Resulting Low Average Offset.
Each Bin Represents One Code.
The ADC channels use a special offset canceling
technique. If the user observes the unaveraged results
for near-zero values of VBUS and VSENSE, they may
observe a cyclical pattern of offset variation. The user
may think this is noise, but in fact it is due to internal
circuitry switching through different permutations of
offset cancellation circuitry. This small variation in
unaveraged offset is canceled in the 8x averaged
result. It is also canceled in the Power Accumulator
results. The overall effect is offset that is consistently
very close to zero LSB over supply and temperature
variations.
Results from both the VBUS and VSENSE ADCs are 17b
two's complement (signed) internally. There is an
additional bit of resolution that is not accessible from the
results register. The NEG_PWR (Address 1Dh) register
determines whether the conversion results are reported
in the readable registers as unipolar or bipolar numbers.
Using bipolar numbers can give more accurate results
for very small numbers that may actually be negative for
some readings, in addition to measuring bidirectional
currents(charging/discharging)andvoltagesthatcandip
below ground.
The offset canceling technique is illustrated in
Figure 4-4. It is very difficult to accurately observe, as
it is a challenge to read the data from every conversion
cycle. The effect of capturing data points at a rate that
does not correspond exactly to the internal sampling
rate of the PAC1931/2/3/4 can make these
permutations appear less periodic and deterministic
than they are inside the chip. The data conversion uses
one of the permute positions 1-4 for each input on each
conversion, cycling through all four permutations in four
conversions. When averaged the Permute Enabled
result shown below is realized, evenly distributed
around zero.
Averaged values are also calculated for VBUS and
VSENSE. A rolling average of the most recent eight
values is present in the VBUSn_AVG (Register 6-7)
and VSENSEn_AVG (Register 6-6) registers. These
registers require eight conversion cycles after POR
before they represent an accurate value, they are
updated after every conversion cycle. The readable
registers are updated with REFRESH, REFRESH_V
or REFRESH_G commands like all the other readable
results registers.
DS20005850E-page 22
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
accumulation period, T. In this equation, T must be
known from a system clock time stamp or other
accurate indicator of the total accumulation period.
4.9
Power and Energy
The Full-Scale Range for Power depends on the
external sense resistor used, as shown in
Equation 4-5.
EQUATION 4-8:
ENERGY CALCULATION
EQUATION 4-5:
POWER FSR
CALCULATION
Vaccum
Energy = ---------------------------------- P w r F S R -------------------------
Denominator AccCount
T
PowerFSR = 100 mV RSENSE 32V
= 3.2V2 RSENSE
Where:
Denominator
=
=
228 (unipolar mode)
227 (bipolar mode)
Where:
RSENSE
=
=
=
External RSENSE resistor value
Full-Scale VSENSE voltage input
Full-Scale VBUS voltage input
EQUATION 4-9:
ENERGY CALCULATION
Vaccum PwrFSR
100 mV
32V
Energy = ---------------------------------- --------------------------
Denominator
f
s
The device implements Power measurements by
multiplying VBUS and the VSENSE to give a result
VPOWER. VPOWER values are used to calculate
Proportional Power as shown in Equation 4-6. The
Proportional Power is the fractional portion of Power
FSR measured in one sample. Bipolar mode is where
VBUS is bipolar mode, VBUS is bidirectional mode, or
both VBUS and VSENSE are bipolar/bidirectional.
Where:
Denominator
=
=
228 (unipolar mode)
27 (bipolar mode)
2
Equation 4-9 shows how to calculate energy using the
accumulated power and the sampling rate, fs.
EQUATION 4-6:
PROPORTIONAL POWER
CALCULATION
Vpower
PPROP = ----------------------------------
Denominator
Where:
Denominator
=
=
2
28 (unipolar mode)
227 (bipolar mode)
To calculate the actual power from the Proportional
Power, multiply by the Power FSR as shown in
Equation 4-7. This Actual Power number is the power
measured in one sample.
EQUATION 4-7:
POWER CALCULATION
Pactual = PowerFSR PPROP
These VPOWER results are digitally accumulated on
chip, and stored in the VACCUM registers.
The energy calculation Equations 4-8 and 4-9 use a
different denominator term depending on unipolar or
bipolar mode. Bipolar mode for energy applies when
bipolar/bidirectional mode is used for VBUS and/or
VSENSE. Equation 4-8 shows how to realize this using
the Accumulator results, Accumulator count and the
2017-2019 Microchip Technology Inc.
DS20005850E-page 23
PAC1931/2/3/4
4.9.1
ADDITIONAL ACCUMULATOR
INFORMATION
not all be full-scale numbers; this is especially true if
VBUS is not 32V. If VBUS is a lower number, the
maximum number of full-scale samples that can be
accumulated is scaled by 32V/VBUS. This limitation can
limit the accumulation period before overflow to 17
minutes at 1024 samples/second, or 36 hours at eight
samples/second, if most values are near full-scale. The
Accumulator Count limit described above will still limit
The math for the Power calculation and accumulation
inside the chip is always done in two's complement
math, no matter what the user sets the output registers
to show. VBUS and VSENSE are 17-bit two's
complement (signed) numbers internally. VPOWER is
the product of VSENSE multiplied by the 14 MSBs of
VBUS, and this is a 31 bit two's complement result
(signed) internally. In some cases this results in a
Power result that is not identical to the product of the
VBUS results register multiplied by the VSENSE register.
However, the Power result from the Power results
register is more accurate than the product of the VBUS
register multiplied by the VSENSE register in these
cases, as explained below.
the total number of samples to 224
.
If VSENSE and VBUS are both programmed to be
unsigned (unipolar) in register NEG_PWR (Address
1Dh), 16b without sign are exported to VBUS and
VSENSE results registers.
If VBUS is programmed to be signed (bipolar) in
Register 6-11 NEG_PWR (Address 1Dh), the
corresponding data is truncated to 16-bit two's
complement (signed) for the readable results register.
If VSENSE is programmed to be signed (bipolar) in
register NEG_PWR (Address 1Dh), the corresponding
results register value is truncated to 16-bit two's
complement (signed), but the power calculation uses
17-bit two's complement (signed). Therefore,
a
mismatch is possible between an externally calculated
power value (VBUS times VSENSE) and the actual power
value calculated internally to the chip. The internally
calculated (and accumulated) value is more accurate
than the externally calculated value in every case.
The continuous power integration periods (also called
the energy accumulation period) can range from ~1ms
to many hours, depending on the number of samples
per second selected via SMBus. The number of
samples is limited by the size of the Accumulator Count
register to 16,777,216 (224). This count corresponds to
about 273 minutes at 1024 samples/second, or 582
hours at eight samples/second. This Accumulator
Count can overflow, and it will not reset when it
overflows.
When the accumulation registers reach their maximum
value, this is called accumulator overflow. The
accumulator outputs remain at their maximum value;
they do not roll over. The user can calculate the
worst-case time to roll over and read them at or before
that time or use the built in Alert functions to detect
rollover and read them at that time.
Worst-case accumulator overflow time can be
calculated assuming that every measurement that is
accumulated is a full-scale number. Since the power
numbers are 28 bits, and the accumulator is 48 bits, 220
samples can be accumulated before overflow if they
are all full-scale values. For most applications, they will
DS20005850E-page 24
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
NOTES:
2017-2019 Microchip Technology Inc.
DS20005850E-page 25
PAC1931/2/3/4
2
5.1.5
SMBUS DATA BYTES
5.0
SMBUS AND I C
COMMUNICATIONS
PROTOCOL
All SMBus data bytes are sent most significant bit first
and composed of eight bits of information.
The PAC1931/2/3/4 communicates over a two-wire bus
with
controller using SMBus or I2C serial
communication protocol. A detailed timing diagram is
TABLE 5-1:
ADDRESS SELECT
RESISTOR
a
Resistor (1%)
SMBus Address
shown in Figure 1-1.
0 (Tie to GND)
499
0010_000(r/w)
0010_001(r/w)
0010_010(r/w)
0010_011(r/w)
0010_100(r/w)
0010_101(r/w)
0010_110(r/w)
0010_111(r/w)
0011_000(r/w)
0011_001(r/w)
0011_010(r/w)
0011_011(r/w)
0011_100(r/w)
0011_101(r/w)
0011_110(r/w)
0011_111(r/w)
Stretching of the SMCLK signal is supported; however,
the PAC1931/2/3/4 will not stretch the clock signal.
806
2
1,270
5.1
I C/SMBus Addressing and
Control Bits
2,050
3,240
5.1.1
SMBUS ADDRESS AND RD/WR BIT
5,230
The SMBus Address Byte consists of the 7-bit slave
address followed by a 1-bit RD / WR indicator. If this
RD / WR bit is a logic ‘0’, the SMBus master is writing
data to the slave device. If this RD / WR bit is a logic
‘1’, the SMBus master is reading data from the slave
device.
The PAC1931/2/3/4 I2C/SMBus address is determined
by a single pull-down resistor connected between
ground and the ADDRSEL pin as shown in Table 5-1.
The chip translates the resistor value into an address
on power-up, and the value is latched until another
power-up event takes place. The address cannot be
changed on the fly.
8,450
13,300
21,500
34,000
54,900
88,700
140,000
226,000
Tie to VDD
5.1.2
SMBUS START BIT
The SMBus Start bit is defined as a transition of the
SMBus data line from a logic ‘1’ state to a logic ‘0’ state
while the SMBus Clock line is in a logic ‘1’ state.
5.1.3
SMBUS ACK AND NACK BITS
The SMBus slave will ACK (acknowledge) all data
bytes that it receives. This is done by the slave device
pulling the SMBus data line low after the eighth bit of
each byte that is transmitted.
5.1.4
SMBUS STOP BIT
The SMBus Stop bit is defined as a transition of the
SMBus data line from a logic ‘0’ state to a logic ‘1’ state
while the SMBus clock line is in a logic ‘1’ state. When
the PAC1931/2/3/4 detects an SMBus Stop bit, and it
has been communicating with the SMBus protocol, it
will reset its slave interface and prepare to receive
further communications.
DS20005850E-page 26
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
2
5.2
SMBus Time-Out
5.4
I C/SMBus Protocols
The PAC1931/2/3/4 can support the SMBus Time-Out
functionality. This functionality is disabled by default,
and can be enabled by writing to the Timeout bit (see
Register 6-10 CHANNEL_DIS and SMBus (Address
1Ch).
The PAC1931/2/3/4 supports Write Byte, Read Byte,
Block Read, Send Byte and Receive Byte as valid
protocols.
It will not respond to the Alert Response Address
protocol. It will respond to the I2C General Call
Address.
If Time-Out is enabled and the clock is held at logic ‘0’
for tTIMEOUT = 25-43 ms, the device will time-out and
reset the SMBus interface. Communication is restored
with a start condition.
All of the protocol charts listed below use the
convention in Table 5-2.
TABLE 5-2:
PROTOCOL FORMAT
2
5.3
SMBus and I C Compatibility
Data Sent to Device
Data Sent to the Master
The PAC1931/2/3/4 is compatible with SMBus 3.0
1 MHz class and I2C Fast-mode Plus. The major
differences between SMBus and I2C devices are
highlighted here. For more information, refer to the
SMBus 3.0 and I2C specifications.
# of bits sent
# of bits sent
5.5
Auto-Incrementing Pointer
The PAC1931/2/3/4 has an auto-incrementing address
pointer. The pointer has two loops for auto-incrementing,
a read loop and a write loop.
1. If Time-Out function is enabled, the minimum
frequency for SMBus communications is
10 kHz. If Time-Out function is disabled (default
condition), then there is no minimum frequency
for SMBus communications.
The read loop includes all of the readable registers,
including all of the configuration and Control registers,
the results registers, and the Product ID, Manufacturer
ID and Revision ID registers.
2. If SMBus Time-Out is enabled in Register 6-10:
CHANNEL_DIS and SMBus (Address 1Ch),the
SMBus slave protocol will reset if the clock is
held at a logic ‘0’ for tTIMEOUT. I2C does not have
a time-out, this is the default condition.
The write loop includes only the writable control and
configuration registers.
Neither loop includes the REFRESH commands.
3. I2C devices do not support the Alert Response
Address functionality (which is optional for
SMBus).The PAC1931/2/3/4 does not support
the Alert Response Address functionality;
instead, the ALERT is a GPIO pin that may be
monitored by the master or Embedded
Controller.
The read loop will skip inactive channels, if some
channels have been disabled. This automatic channel
skipping feature can be disabled by setting the No Skip
bit in Register 6-10: CHANNEL_DIS and SMBus
(Address 1Ch).
If the user elects to read disabled channels, they will
return FFh and the register address will by NACKed.
4. I2C devices support Block Read and Block Write
differently. I2C protocol allows for unlimited
number of bytes to be sent in either direction.
The SMBus protocol for Block Read and Block
Write requires that an additional data byte
indicating number of bytes to read/write is
transmitted. PAC1931/2/3/4 devices support the
I2C protocol for Block Read by default (no byte
count information is sent). If the Byte Count bit is
set (see Register 6-10: CHANNEL_DIS and
SMBus (Address 1Ch), it will be sent as the first
data byte in response to the Block Read
command, per SMBus protocol.
See Figure 5-1 for a graphic representation.
2017-2019 Microchip Technology Inc.
DS20005850E-page 27
PAC1931/2/3/4
App Read Loop
App Write Loop
Channels ON or
(Channels OFF and
Skip OFF)
Channels 1 & 4 OFF
and Skip ON
Channels OFF and
Skip ON
Don’t care if Channels
ON or OFF
REFRESH
CTRL
REFRESH
CTRL
REFRESH
CTRL
REFRESH
CTRL
0x00
W
1 byte
0x01 R/W 1 byte
ACC_COUNT
VPOWER1_ACC
VPOWER2_ACC
VPOWER3_ACC
VPOWER4_ACC
VBUS1
ACC_COUNT
VPOWER1_ACC
VPOWER2_ACC
VPOWER3_ACC
VPOWER4_ACC
VBUS1
ACC_COUNT
VPOWER1_ACC
VPOWER2_ACC
VPOWER3_ACC
VPOWER4_ACC
VBUS1
ACC_COUNT
VPOWER1_ACC
VPOWER2_ACC
VPOWER3_ACC
VPOWER4_ACC
VBUS1
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
R
R
R
R
R
R
R
R
R
R
3 bytes
6 bytes
6 bytes
6 bytes
6 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
4 bytes
4 bytes
4 bytes
4 bytes
VBUS2
VBUS2
VBUS2
VBUS2
VBUS3
VBUS3
VBUS3
VBUS3
VBUS4
VBUS4
VBUS4
VBUS4
VSENSE1
VSENSE1
VSENSE1
VSENSE1
VSENSE2
VSENSE2
VSENSE2
VSENSE2
0x0C R
0x0D R
VSENSE3
VSENSE3
VSENSE3
VSENSE3
VSENSE4
VSENSE4
VSENSE4
VSENSE4
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
R
R
R
R
R
R
R
R
R
R
R
R
R
VBUS1_AVG
VBUS2_AVG
VBUS3_AVG
VBUS4_AVG
VSENSE1_AVG
VSENSE2_AVG
VSENSE3_AVG
VSENSE4_AVG
VPOWER1
VBUS1_AVG
VBUS2_AVG
VBUS3_AVG
VBUS4_AVG
VSENSE1_AVG
VSENSE2_AVG
VSENSE3_AVG
VSENSE4_AVG
VPOWER1
VBUS1_AVG
VBUS2_AVG
VBUS3_AVG
VBUS4_AVG
VSENSE1_AVG
VSENSE2_AVG
VSENSE3_AVG
VSENSE4_AVG
VPOWER1
VBUS1_AVG
VBUS2_AVG
VBUS3_AVG
VBUS4_AVG
VSENSE1_AVG
VSENSE2_AVG
VSENSE3_AVG
VSENSE4_AVG
VPOWER1
VPOWER2
VPOWER2
VPOWER2
VPOWER2
VPOWER3
VPOWER3
VPOWER3
VPOWER3
VPOWER4
VPOWER4
VPOWER4
VPOWER4
CHANNEL_DIS
NEG_PWR
CHANNEL_DIS
NEG_PWR
CHANNEL_DIS
NEG_PWR
CHANNEL_DIS
NEG_PWR
0x1C R/W 1 byte
0x1D R/W 1 byte
REFRESH_G
REFRESH_V
SLOW
REFRESH_G
REFRESH_V
SLOW
REFRESH_G
REFRESH_V
SLOW
REFRESH_G
REFRESH_V
SLOW
0x1E
0x1F
W
W
1 byte
1 byte
0x20 R/W 1 byte
CTRL_ACT
CTRL_ACT
CTRL_ACT
CTRL_ACT
0x21
0x22
0x23
0x24
0x25
0x26
R
R
R
R
R
R
1 byte
1 byte
1 byte
1 byte
1 byte
1 byte
CHANNEL_DIS_ACT
NEG_PWR_ACT
CTRL_LAT
CHANNEL_DIS_ACT
NEG_PWR_ACT
CTRL_LAT
CHANNEL_DIS_ACT
NEG_PWR_ACT
CTRL_LAT
CHANNEL_DIS_ACT
NEG_PWR_ACT
CTRL_LAT
CHANNEL_DIS_LAT
NEG_PWR_LAT
CHANNEL_DIS_LAT
NEG_PWR_LAT
CHANNEL_DIS_LAT
NEG_PWR_LAT
CHANNEL_DIS_LAT
NEG_PWR_LAT
PID
MID
REV
PID
MID
REV
PID
MID
REV
PID
MID
REV
0xFD R
0xFE R
0xFF R
1 byte
1 byte
1 byte
FIGURE 5-1:
READ and WRITE Auto Incrementing Loops.
Figure 5-1 shows how the auto-incrementing READ
loop works with SKIP option on and off, for reading. It
also shows how the WRITE loop works with the
REFRESH,
commands.
REFRESH_V,
and
REFRESH_G
DS20005850E-page 28
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
2
5.6
I C/SMBus Commands
5.6.1
REFRESH AND REFRESH_V
REFRESH and REFRESH_V commands are sent
using the Send byte command, the Slave Address and
the desired command (00h for REFRESH or 1Fh for
REFRESH_V. See Table 5-3.
TABLE 5-3:
START
REFRESH AND REFRESH_V COMMANDS
REFRESH or
REFRESH_V
Command
Slave Address
WR
ACK
ACK
STOP
1 0
YYYY_YYY
0
0
00h or 1Fh
0
0 1
Just as the REFRESH command is sent using a Send
Byte command with the slave address, and the
REFRESH command (00h), the REFRESH_G
command is sent using Send Byte with the General
Call address (0000 000) and the REFRESH_G
command (1Eh).
5.6.2
GENERAL CALL ADDRESS
RESPONSE
When the master sends the General Call address, the
PAC1931/2/3/4 will be able to execute the REFRESH
command by means of a second version of the
REFRESH command called REFRESH_G (see
Register 6-12 REFRESH_G Command (Address
1Eh)).
Table 5-4 shows the response to the General Call
command for REFRESH_G.
TABLE 5-4:
START
GENERAL CALL RESPONSE
General Call
WR
REFRESH_G
Command
ACK
ACK
STOP
Address
1 0
0000_000
0
0
1Eh
0
0 1
5.6.3
WRITE BYTE
The Write Byte is used to write one byte of data to the
registers, as shown in Table 5-5.
TABLE 5-5:
START
WRITE BYTE PROTOCOL
Slave
Register
Address
Register
Data
WR
ACK
ACK
ACK
STOP
0 1
Address
1 0
YYYY_YYY
0
0
XXh
0
XXh
0
2017-2019 Microchip Technology Inc.
DS20005850E-page 29
PAC1931/2/3/4
5.6.4
READ BYTE
The Read Byte protocol is used to read one byte of data
from the registers, as shown in Table 5-6.
If an invalid register address is specified, the slave will
ACK its address but NACK (not acknowledge) the
register address.
The master will NACK the data received from the slave
by holding the SMBus data line high after the eighth
data bit has been sent.
TABLE 5-6:
READ BYTE PROTOCOL
Slave
Address
Register
Address
START
WR
ACK
ACK
START Slave Address RD
ACK Register Data NACK
STOP
1 0
YYYY_YYY
0
0
XXh
0
1 0
YYYY_YYY
1
0
XXh
1
0 1
5.6.5
SEND BYTE
The Send Byte protocol is used to set the internal
address register pointer to the correct address location.
No data is transferred during the Send Byte protocol,
as shown in Table 5-7.
TABLE 5-7:
START
SEND BYTE PROTOCOL
Slave Address
WR
ACK
Register Address
ACK
STOP
0 1
1 0
YYYY_YYY
0
0
XXh
0
If the master wishes to continue clocking and read the
next register, the master will ACK after the register
data, instead of sending NACK followed by STOP.
5.6.6
RECEIVE BYTE
The Receive Byte protocol is used to read data from a
register when the internal register address pointer is
known to be at the right location (e.g., set via Send
Byte). This is shown in Table 5-8.
If some channels are deactivated, their data registers
will be skipped by the auto-incrementing pointer.
Alternatively, you may set bit 0 in Register 6-10
CHANNEL_DIS and SMBus (Address 1Ch) and the
pointer will not skip the addresses associated with the
inactive channels. The measurement data for these
inactive channels will read FFh.
When an ACK is received after the REGISTER DATA,
then the address pointer automatically increments.
When a NACK is received after the REGISTER DATA,
then the address pointer stays at the same position.
TABLE 5-8:
START
RECEIVE BYTE PROTOCOL
Slave Address
RD
ACK
Register Data
NACK
STOP
1 0
YYYY_YYY
1
0
XXh
1
0 1
DS20005850E-page 30
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
5.6.7
BLOCK READ – I2C VERSION
Block Read is used to read multiple data bytes from a
register that contains more than one byte of data, or
from a group of contiguous registers, as shown in
Table 5-9. The PAC1931/2/3/4 supports I2C Block
Read by default, but the SMBus format can also be
supported (see Table 5-10).
If an invalid register address is specified, the slave will
ACK its address but NACK the register address.
The master will NACK the data received from the slave
by holding the SMBus data line high after the 8th data
bit has been sent.
TABLE 5-9:
BLOCK READ PROTOCOL I2C VERSION (DEFAULT)
Register
Address
Register
Data
START Slave Address
WR
ACK
ACK
START Slave Address
RD
ACK
1 0
ACK
0
YYYY_YYY
Register Data
XXh
0
0
XXh
ACK
0
0
1 0
ACK
0
YYYY_YYY
1
0
NACK
1
XXh
Register
Data
Register
Data
Register
Data
ACK
0
STOP
XXh
XXh
XXh
0 1
5.6.8
BLOCK READ – SMBUS VERSION
PAC1931/2/3/4 can also support the SMBus version of
Block Read. If the Byte Count bit is set, Block Read will
result in the device sending the Byte Count data before
the first data byte. This protocol is shown in Table 5-10.
Also see Section 4.3 “Conversion Cycle Controls”
above and Register 6-10 CHANNEL_DIS and SMBus
(Address 1Ch).
TABLE 5-10: BLOCK READ PROTOCOL SMBUS VERSION (MUST SET BYTE COUNT BIT)
Register
Address
START Slave Address
WR
ACK
ACK
START Slave Address
RD
ACK
Byte Count
XXh = N
STOP
1 0
ACK
0
YYYY_YYY
Register Data
XXh
0
0
XXh
0
1 0
ACK
0
YYYY_YYY
1
0
NACK
1
Register
Data
Register
Data
Register
Data
ACK
0
ACK
XXh
0
XXh
XXh
0 1
2017-2019 Microchip Technology Inc.
DS20005850E-page 31
PAC1931/2/3/4
6.0
REGISTERS IN HEXADECIMAL
ORDER
The registers shown in Table 6-1 are accessible
through the SMBus. In the individual register tables that
follow, an entry of ‘—’ indicates that the bit is not used
and will always read ‘0’.
Data represented by the data registers are ensured to
be synchronized and stable 1 ms after any of the
REFRESH commands are sent. Immediately after the
REFRESH commands are sent, the data bytes will be
changing dynamically until 1 ms has elapsed. When
new data is written to a Control register, and the master
reads it back, this new data will be read back even if no
REFRESH command has been sent to cause the new
data to take effect.
Note:
The letter N or n is used to represent
1,2,3,4 in the register and bit names
below, in sections that describe registers
that are grouped for all four channels.
Note:
For PAC1931, channels 2, 3 and 4 do not
contain valid data and will read FF. Also,
for PAC1932, channels 3 and 4 do not
contain valid data and will read FF. The
auto-incrementing pointer will skip these
channels by default (see Section 5.5
“Auto-Incrementing Pointer”). The
same applies to channel
PAC1933.
4 for the
TABLE 6-1:
REGISTER SET IN HEXADECIMAL ORDER
Register
Number
POR
Value
Description
Type Bytes
Register 6-1
REFRESH Command (Address 00h)
Send Byte for REFRESH command SEND
0
1
3
6
6
6
6
00h
Register 6-2
CTRL Register (Address 01h)
Configuration controls and status
Accumulator count for all channels
Accumulator output for channel 1
Accumulator output for channel 2
Accumulator output for channel 3
Accumulator output for channel 4
R/W
00h
Register 6-3
ACC_COUNT Register (Address 02h)
Block
Read
000000h
Note 1
Note 1
Note 1
Note 1
Register 6-4
Block
Read
VPOWERN Accumulator Registers:
VPOWER1_ACC(03h), VPOWER2_ACC
(04h), VPOWER3_ACC (05h),
VPOWER4_ACC (06h)
Block
Read
Block
Read
Block
Read
Note 1: The VPOWERN Accumulator Registers, 03h-06h, have a POR value that is all zeros: 6 bytes 000000000000h.
DS20005850E-page 32
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
TABLE 6-1:
REGISTER SET IN HEXADECIMAL ORDER (CONTINUED)
Register
Number
POR
Value
Description
Type Bytes
Register 6-5
VBUSN Result Registers VBUS1 (07h),
VBUS2 (08h), VBUS3 (09h),VBUS4 (0Ah )
VBUS measurement for channel 1
Block
Read
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
4
4
1
0000h
VBUS measurement for channel 2
Block
Read
0000h
V
BUS measurement for channel 3
BUS measurement for channel 4
Block
Read
0000h
V
Block
Read
0000h
Register 6-6
VSENSE measurement for channel 1 Block
Read
0000h
VSENSEn Result Registers: VSENSE1
(0Bh), VSENSE2 (0Ch), VSENSE3 (0Dh),
VSENSE4 (0Eh)
VSENSE measurement for channel 2 Block
Read
0000h
VSENSE measurement for channel 3 Block
Read
0000h
VSENSE measurement for channel 4 Block
Read
0000h
Register 6-7
VBUSN_AVG Result Registers
VBUS1_AVG (0Fh), VBUS2_AVG (10h),
VBUS3_AVG (11h), VBUS4_AVG (12h)
Rolling average of eight most recent Block
0000h
VBUS1 measurements
Rolling average of eight most recent Block
BUS2 measurements Read
Rolling average of eight most recent Block
BUS3 measurements Read
Rolling average of eight most recent Block
VBUS4 measurements Read
Rolling average of eight most recent Block
VSENSE1 measurements Read
Rolling average of eight most recent Block
SENSE2 measurements Read
Rolling average of eight most recent Block
VSENSE3 measurements Read
Rolling average of eight most recent Block
Read
0000h
V
0000h
V
0000h
Register 6-8
0000h
VSENSEn AVG Result Register
VSENSE1_AVG (13h), VSENSE2_AVG
(14h), VSENSE3_AVG(15h),
VSENSE4_AVG (16h)
0000h
V
0000h
0000h
VSENSE4 measurements
Read
Register 6-9
VSENSE x VBUS for Channel 1
VSENSE x VBUS for Channel 2
VSENSE x VBUS for Channel 3
Block
Read
00000000h
00000000h
00000000h
00000000h
VPOWERN Result Register: VPOWER1
(17h), VPOWER2 (18h), VPOWER3 (19h),
VPOWER4 (1Ah)
Block
Read
Block
Read
VSENSE x VBUS for Channel 4
Block
Read
Register 6-10
CHANNEL_DIS and SMBus (Address 1Ch)
Disable selected channels,
activate SMBus functionality,
pointer increment
R/W
PAC1931: 70h
PAC1932: 30h
PAC1933: 10h
PAC1934: 00h
Register 6-11
NEG_PWR (Address 1Dh)
Configuration control for
enabling bidirectional current and
bipolar voltage measurements
R/W
1
00h
Note 1: The VPOWERN Accumulator Registers, 03h-06h, have a POR value that is all zeros: 6 bytes 000000000000h.
2017-2019 Microchip Technology Inc.
DS20005850E-page 33
PAC1931/2/3/4
TABLE 6-1:
REGISTER SET IN HEXADECIMAL ORDER (CONTINUED)
Register
Number
POR
Value
Description
Type Bytes
Register 6-12
REFRESH_G Command (Address 1Eh)
REFRESH response to
General Call Address
SEND
SEND
0
0
N/A
Register 6-13
REFRESH_V Command (Address 1Fh)
Refreshes VBUS and VSENSE data
only,
N/A
no accumulator reset
Register 6-14
SLOW (Address 20h)
Status and control for
SLOW pin functions
R/W
R
1
1
1
1
1
1
1
1
1
1
15h
00h
00h
00h
00h
00h
00h
Register 6-15
CTRL_ACT Register (Address 21h)
Currently active value of 01h
(Control)
Register 6-16
Channel DIS_ACT (Address 22h)
Currently active value of
1Ch (CHANNEL_DIS and SMBus)
R
Register 6-17
NEG_PWR_ACT (Address 23h)
Currently active value of
1Dh(NEG_PWR)
R
Register 6-18
CTRL_LAT Register (Address 24h)
Latched image of 21h (CTRL_ACT)
R
Register 6-19
Channel DIS_LAT (Address 25h)
Latched image of
22h (Channel DIS_ACT)
R
Register 6-20
NEG_PWR _LAT (Address 26h)
Latched image of
23h (NEG_PWR_ACT)
R
Register 6-21
Product ID Register (Address FDh)
Stores the Product ID
Stores the Manufacturer ID
Stores the revision
R
See register
details
Register 6-22
Manufacturer ID Register (Address FEh)
R
5Dh
Register 6-23
R
03h
Revision ID Register (Address FFh)
Note 1: The VPOWERN Accumulator Registers, 03h-06h, have a POR value that is all zeros: 6 bytes 000000000000h.
DS20005850E-page 34
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
6.1
Detailed Register Information
REGISTER 6-1:
SEND
REFRESH COMMAND (ADDRESS 00H)
SEND SEND SEND SEND
No Data in this command, Send Byte only
SEND
SEND
SEND
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
This command is a SEND Byte, does not contain any data. When it is sent to the device, the REFRESH
command is executed. The accumulator data, accumulator count, VBUS, and VSENSE measurements
are all refreshed and the accumulators are reset. The master can read the accumulator data and
accumulator count anytime 1 ms after the REFRESH command is sent, and anytime after than up until
the next REFRESH command is sent. (The master can read VBUS and VSENSE data in the same time
period. The accumulator results, accumulator count, VBUS and VSENSE data can be refreshed with the
REFRESH_V command without resetting the accumulators, see Register 6-7).
REGISTER 6-2:
RW-0
CTRL REGISTER (ADDRESS 01H)
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
R-0
OVF
bit 0
Sample_Rate[1:0]
bit 7
SLEEP
SING
ALERT_PIN ALERT_CC OVF ALERT
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-1
bit 7-6
Write to these bits to change settings from default value.
Sample_Rate[1:0]: determines sample rate in Normal mode (if SLOW pin is not asserted).
00b= 1024 samples/s
01b= 256 samples/s
10b= 64 samples/s
11b= 8 samples/s
bit 5
SLEEP: setting this bit to 1, followed by the REFRESH or REFRESH_V command, puts the device in
SLEEP mode. All programmed, readable, and measured digital data is stable in this mode. Clearing the
SLEEP bit and sending a REFRESH or REFRESH_V command causes the device become active and
start converting in the mode specified by the Control registers (unless the SLOW pin is asserted, in
which case it will start converting at an 8 Hz rate). The SLEEP bit has higher priority than the SING bit
or the SLOW pin, if the SLEEP bit is set the device goes into SLEEP mode not matter how the SING
bit or the SLOW pin are set.
0= Active mode
1= SLEEP mode, no data conversion
2017-2019 Microchip Technology Inc.
DS20005850E-page 35
PAC1931/2/3/4
REGISTER 6-2:
CTRL REGISTER (ADDRESS 01H) (CONTINUED)
bit 4 SING: setting this bit to 1puts the device in Single-shot mode. After writing this bit and sending a
REFRESH command, the device resets the accumulators and performs one conversion cycle for any
and all active channels, then returns to sleep mode. Another REFRESH command, without changing
this bit, will perform another single-shot command. When the bit is cleared, sending a REFRESH
command resets the accumulators and causes the device to start converting in the sequential scan
mode for active channels. A REFRESH_V command may be used instead of REFRESH to move in and
out of Single Shot mode without resetting the accumulators and accumulator count.
0= Sequential scan mode
1= Single-shot mode
bit 3
ALERT_PIN: setting this bit to 1causes the SLOW pin to function as an ALERT pin (active low output
pin). If this bit is set to 1, the ALERT pin can be triggered by conversion complete if bit 2 is set.
If this bit is set to 1, and the Overflow ALERT enable bit is set to 1, the ALERT pin will be triggered by
accumulator or accumulator count overflow (see bit 1and bit 0descriptions directly below).
Note that bit 3 only determines the functionality of this pin, SLOW or ALERT, it does not influence the
ALERT functionality. If there is a pull-up resistor connected to the pin for ALERT functionality, the device
will initially power-up in SLOW mode. Once bit 3 is set to enable ALERT functionality, the conversion
rate will change to either the default or programmed value.
0= Disable the ALERT pin function
1= Enable the ALERT pin function
bit 2
ALERT_CC: setting this bit to 1causes the ALERT pin to be asserted for 5 μS at the end of each
conversion cycle.
0= No ALERT on Conversion Cycle Complete
1= ALERT function asserted for 5 μS on each completion of the conversion cycle
Note:
If this bit and the OVF ALERT bit are set, OVF ALERT dominates. EOC alerts will not be
seen on the ALERT pin if OVF ALERT = 1.
bit 1
OVF ALERT: Overflow ALERT enable. If this bit is set and any of the accumulators or the accumulator
counter overflow, the ALERT function will be triggered. This will be reflected in bit 0 of this register, and
if bit 3 is set to 1, the ALERT pin will be triggered (sent low).
The ALERT function is cleared by REFRESH or REFRESH_G.
0= no ALERT if accumulator or accumulator counter overflow has occurred.
1= ALERT pin triggered if accumulator or accumulator counter has overflowed
If this bit and the ALERT_CC bit are set, OVF ALERT dominates. EOC alerts will not be seen on the
ALERT pin if OVF ALERT =1.
bit 0
OVF: Overflow indication status bit, this bit will be set to 1if any of the accumulators or the accumulator
counter overflows.This bit is by cleared REFRESH or REFRESH_G. These commands also clear the
ALERT function.
0= no accumulator or accumulator counter overflow has occurred
1= accumulator or accumulator counter has overflowed
DS20005850E-page 36
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
REGISTER 6-3:
R-0
ACC_COUNT REGISTER (ADDRESS 02h)
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
bit 16
ACC_COUNT[23:16]
bit 23
R-0
R-0
R-0
R-0
ACC_COUNT[15:8]
bit 15
R-0
bit 8
R-0
R-0
R-0
ACC_COUNT[7:0]
bit0
bit 7
bit0
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 23-0
ACC_COUNT[23:0]: contain the count for each time a power result has been summed in the
accumulator
2017-2019 Microchip Technology Inc.
DS20005850E-page 37
PAC1931/2/3/4
REGISTER 6-4:
VPOWERN ACCUMULATOR REGISTERS: VPOWER1_ACC(03h),
VPOWER2_ACC (04h), VPOWER3_ACC (05h), VPOWER4_ACC (06h)
R-0
bit 47
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0 R-0
VPOWERn[47:40]
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
bit 40
R-0
bit 32
R-0
bit 24
R-0
bit 16
R-0
R-0
VPOWERn[39:32]
bit 39
R-0
R-0
R-0
VPOWERn[31:24]
bit 31
R-0
R-0
R-0
VPOWERn[23:16]
bit 23
R-0
R-0
R-0
R-0
VPOWERn[15:8]
bit 15
R-0
bit 8
bit 0
R-0
R-0
R-0
VPOWERn[7:0]
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 47-0
VPOWERn_ACC[47:0]: contain the accumulated sum of VPOWER samples, where n = 1 to 4,
depending on device. These are 48 bit unsigned numbers unless either VBUS or VSENSE are configured
to have a bipolar range. In that case they will be 48-bit two's complement (signed) numbers.
Note that power is always calculated and accumulated using signed numbers for VBUS and VSENSE, but
if both VBUS and VSENSE are in the default unipolar mode, power is reported as an unsigned number.
This can lead to very small discrepancies between a manual comparison of the product of VBUS and
VSENSE and the results that the chip calculates and accumulates for VPOWER. The digital math in the
chip uses more bits than the reported results for VBUS and VSENSE, so the results registers for VPOWER
and Accumulated Power will in some cases have a more accurate number than calculations using the
results registers for VSENSE and VBUS will provide.
DS20005850E-page 38
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
REGISTER 6-5:
VBUSN RESULT REGISTERS VBUS1 (07h), VBUS2 (08h), VBUS3 (09h),VBUS4
(0Ah)
R-0
bit 15
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
VBUSn[15:8]
bit 8
bit 0
R-0
R-0
R-0
VBUSn[7:0]
R-0
R-0
R-0
R-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
VBUSn[15:0]: contain the most recent digitized value of a VBUS sample, where n = 1 to 4, depending
on device. These are 16 bit unsigned numbers unless VBUS is configured to have a bipolar range. In
that case they will be 16-bit two's complement (signed) numbers.
REGISTER 6-6:
VSENSEn RESULT REGISTERS: VSENSE1 (0Bh), VSENSE2 (0Ch), VSENSE3
(0Dh), VSENSE4 (0Eh)
R-0
bit 15
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
VSENSEn[15:8]
bit 8
bit 0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
VSENSEn[7:0]
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
VSENSEn[15:0]: contain the most recent digitized value of VSENSE samples, where n = 1 to 4,
depending on device. These are 16 bit unsigned numbers unless VSENSE is configured to have a bipolar
range. In that case they will be 16-bit two's complement (signed) numbers.
2017-2019 Microchip Technology Inc.
DS20005850E-page 39
PAC1931/2/3/4
REGISTER 6-7:
VBUSN_AVG RESULT REGISTERS VBUS1_AVG (0FH), VBUS2_AVG (10H),
VBUS3_AVG (11H), VBUS4_AVG (12H)
R-0
bit 15
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
VBUSn_AVG[15:8]
bit 8
bit 0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
VBUSn_AVG[7:0]
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
VBUSn_AVG[15:0]: contain a rolling average of the eight most recent VBUS measurements. They have
the same format as the values in the VBUS registers.
REGISTER 6-8:
VSENSEn AVG RESULT REGISTER VSENSE1_AVG (13H), VSENSE2_AVG (14H),
VSENSE3_AVG(15H), VSENSE4_AVG (16H)
R-0
bit 15
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
VSENSEn_AVG[15:8]
bit 8
bit 0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
VSENSEn_AVG[7:0]
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
VSENSEn_AVG[15:0]: contain a rolling average of the eight most recent VSENSE results.
They have the same format as the values in the VSENSE registers.
DS20005850E-page 40
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
REGISTER 6-9:
VPOWERN RESULT REGISTER: VPOWER1 (17H), VPOWER2 (18H), VPOWER3
(19H), VPOWER4 (1AH)
R-0
bit 31
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
bit 24
R-0
bit 16
VPOWERn[27:20]
R-0
R-0
VPOWERn[19:12]
bit 23
R-0
R-0
R-0
R-0
VPOWERn[11:4]
bit 15
R-0
bit 8
bit 0
R-0
U
U
U
U
VPOWERn[3:0]
—
—
—
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-4
VPOWERn[27:0]: these registers contain the product of VBUS (14 MSBs) and VSENSE which
represents Proportional Power for each channel.These are 28 bit unsigned numbers unless either VBUS
or VSENSE are configured to have a bipolar range. In that case they will be 28-bit two's complement
(signed) numbers.These are the numbers that are accumulated in the accumulators.
Note that power is always calculated using signed numbers for VBUS and VSENSE, but if both VBUS and
VSENSE are in the default unipolar mode, power is reported as an unsigned number. This can lead to
very small discrepancies between a manual comparison of the product of VBUS and VSENSE and the
results that the chip calculates for VPOWER.The digital math in the chip uses more bits than the reported
results for VBUS and VSENSE, so the results registers for VPOWER and Accumulated Power will in some
cases have a more accurate number than calculations using the results registers for VSENSE and VBUS
will provide.
bit 3-0
Not used at this time, always reads ‘0’
2017-2019 Microchip Technology Inc.
DS20005850E-page 41
PAC1931/2/3/4
REGISTER 6-10: CHANNEL_DIS AND SMBUS (ADDRESS 1CH)
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
U
CH1_OFF
CH2_OFF
CH3_OFF
CH4_OFF
TIMEOUT
BYTE
COUNT
—
NO SKIP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-4
CHn_OFF[7:4]: allows one or more channels to be inactive during the conversion cycle. These settings
apply for normal continuous round-robin conversion cycles or Single-Shot mode, if Single-Shot mode
is selected. Note that if a channel is set to inactive, the auto incrementing address pointer will skip
addresses associated with that channel unless the Pointer Skipping bit 1in this register is set.
Changes to bits 7-4 do not take effect until a REFRESH, REFRESH_V, or REFRESH_G command are
sent.
Changes to bits 3-1 take place as soon as a new value is written, they are not gated by a REFRESH
command like most other control bits.
bit 7
bit 6
0= CH1 ON. Channel 1 active during conversion cycle
1= CH1 OFF. Channel 1 inactive during conversion cycle
0= CH2 ON. Channel 2 active during conversion cycle
1= CH2 OFF. Channel 2 inactive during conversion cycle (for PAC1931, this bit is set to ‘1’ with factory
trim. Although you can program this bit to a ‘1’ for PAC1931, you will not be able to read the data from
this channel).
bit 5
bit 4
bit 3
0= CH3 ON. Channel 3 active during conversion cycle
1= CH3 OFF. Channel 3 inactive during conversion cycle (for PAC1931 and PAC1932, this bit is set to
‘1’ with factory trim. Although you can program this bit to a ‘1’ for PAC1931 and PAC1932, you will not
be able to read the data from this channel).
0= CH4 ON. Channel 4 active during conversion cycle
1= CH4 OFF. Channel 4 inactive during conversion cycle (for PAC1931, PAC1932 and PAC1933, this
bit is set to ‘1’ with factory trim. Although you can program this bit to a ‘1’ for PAC1931, PAC1932 and
PAC1933, you will not be able to read the data from this channel).
TIMEOUT: Timeout enable bit. The SMBus timeout is disabled by default, and is enabled by setting this
bit.
0= No SMBus timeout feature
1= SMBus timeout feature is available
bit 2
BYTE COUNT: causes Byte Count data to be included in the response to the SMBus Block Read
command for each register read. This functionality is disabled by default, and Block Read corresponds
to I2C protocol.
0= No Byte Count in response to a Block Readcommand
1= Data in response to a Block Readcommand includes the Byte Count data
NO SKIP: controls the auto-incrementing of the address pointer for channels that are inactive
0= The auto-incrementing pointer will skip over addresses used by/for channels that are inactive
bit 1
bit 0
1= The auto-incrementing pointer will not skip over addresses used by/for channels that are inactive.
With this setting, these channels that are disabled will read 0xFFif read.
Unimplemented bits always read ‘0’
DS20005850E-page 42
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
REGISTER 6-11: NEG_PWR (ADDRESS 1DH)
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
CH4_BIDV
bit 0
CH1_BIDI
CH2_BIDI
CH3_BIDI
CH4 BIDI
CH1_BIDV
CH2_BIDV
CH3_BIDV
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-4
CHn_BIDI[7:4]: these control bits allow the user to enable bidirectional current measurements for any
channel, which will result in the VSENSE voltage measurement data being in 16-bit two's complement
(signed) format. If the channel is enabled for negative current measurements, the full scale range for
VSENSE is -100 mV to +100 mV.
If these bits are enabled for any channel, that channel’s power numbers are also capable of reporting
bidirectional numbers in two’s complement format.
bit 3-0
CHn_BIDI[3:0]: these control bits allow the user to enable bidirectional/bipolar voltage measurements
for any channel, which will result in the VBUS voltage measurement data being in 16 bit two’s
complement format.
If the channel is enabled for negative voltage measurements, the full scale range for VBUS is +32V to
-32V. Note that this range is the digital FSR, the VBUS input will not give accurate measurements if taken
more than 200 mV below ground.
If these bits are enabled for any channel, that channel’s power numbers are also capable of reporting
bidirectional numbers in two’s complement format.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0= Channel 1 VSENSE ADC converts 0 to +100 mV range with 16-bit straight binary output
1= Channel 1 VSENSE ADC converts -100 mV to +100 mV range with 16-bit two’s complement output
0= Channel 2 VSENSE ADC converts 0 to +100 mV range with 16 bit straight binary output
1= Channel 2 VSENSE ADC converts -100 mV to +100 mV range with 16 bit two’s complement output
0= Channel 3 VSENSE ADC converts 0 to +100 mV range with 16-bit straight binary output
1= Channel 3 VSENSE ADC converts -100 mV to +100 mV range with 16-bit two’s complement output
0= Channel 4 VSENSE ADC converts 0 to +100 mV range with 16-bit straight binary output
1= Channel 4 VSENSE ADC converts -100 mV to +100 mV range with 16 bit two’s complement output
0= Channel 1 VBUS ADC converts 0 to +32V range with 16-bit straight binary output
1= Channel 1 VBUS ADC converts -32V to +32 range with 16-bit two’s complement output
0= Channel 2 VBUS ADC converts 0 to +32V range with 16-bit straight binary output
1= Channel 2 VBUS ADC converts -32V to +32V range with 16-bit two’s complement output
0= Channel 3 VBUS ADC converts 0 to +32V range with 16-bit straight binary output
1= Channel 3 VBUS ADC converts -32V to +32V range with 16-bit two’s complement output
0= Channel 4 VBUS ADC converts 0 to +32V range with 16-bit straight binary output
1= Channel 4 VBUS ADC converts -32V to +32V range with 16-bit two’s complement output
2017-2019 Microchip Technology Inc.
DS20005850E-page 43
PAC1931/2/3/4
REGISTER 6-12: REFRESH_G COMMAND (ADDRESS 1EH)
SEND
SEND
SEND
SEND
SEND
SEND
SEND
SEND
No Data in this command, Send Byte only
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
This command is a SEND Byte, does not contain any data. It is exactly like the REFRESH command
but is intended for use with the General Callcommand.
When it is sent to the device, the REFRESH command is executed and the readable accumulator data,
readable accumulator count, VBUS, and VSENSE measurements are all refreshed and the internal
accumulators values or accumulator count are reset, exactly like the REFRESH command. The master
can read the updated data 1 ms after the REFRESH_G command is sent, and anytime after than up
until the next REFRESH, REFRESH_G, or REFRESH_V command is sent.
REGISTER 6-13: REFRESH_V COMMAND (ADDRESS 1FH)
SEND
SEND
SEND
SEND
SEND
SEND
SEND
SEND
No Data in this command, Send Byte only
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
This command is a SEND Byte, does not contain any data. When it is sent to the device, the
REFRESH_V command is executed.
It is similar to the REFRESH command except the accumulators and accumulator count are not reset.
The readable accumulator data, readable accumulator count, VBUS, and VSENSE measurements are all
refreshed without affecting the internal accumulators values or accumulator count. The master can read
the updated data 1 ms after the REFRESH_V command is sent, and anytime after than up until the next
REFRESH, REFRESH_G, or REFRESH_V command is sent.
DS20005850E-page 44
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
REGISTER 6-14: SLOW (ADDRESS 20H)
R-0
SLOW
bit 7
R-0
R-0
RW-1
RW-0
RW-1
RW-0
RW-1
POR
bit 0
SLOW-LH
SLOW_HL
R_RISE
R_V_RISE
R_FALL
R_V_FALL
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
This register tracks the state of the SLOW pin, tracks transitions on the SLOW pin, and controls the type of limited
REFRESH command (if any) that occurs on a SLOW pin transition. This allows software to monitor the state of the
SLOW pin and its transitions over I2C even though the SLOW pin is asynchronous to the I2C pins and may have a
different controller. All of the bits in this register are updated in real time, they do not require a REFRESH signal to be
updated.
Note that if a REFRESH and REFRESH_V are both enabled for a certain SLOW pin transition, REFRESH will be
executed (REFRESH wins over REFRESH_V).
On a transition of the SLOW pin, a limited REFRESH function is executed. These limited REFRESH and REFRESH_V
functions update all of the readable results registers. For the limited REFRESH function only, it also reset the
accumulators and accumulator count. These are called limited REFRESH and limited REFRESH_V functions because
there is no activation of any pending changes to the Control registers.
If the SLOW pin is configured to act as an ALERT pin, all of these bits are always 0. The bits are not cleared when
read, see the details on each bit for clearing information.
SLOW Control and Status Bits
bit 7 = 0
bit 7 = 1
The SLOW pin is pulled low externally
The SLOW pin is pulled high externally
bit 6 = 0
bit 6 = 1
The SLOW pin has not transitioned low to high since the last REFRESH command
The SLOW pin has transitioned low to high since the last REFRESH command
The bit is reset to 0 by a REFRESH or REFRESH_G command
bit 5 = 0
bit 5 = 1
The SLOW pin has not transitioned high to low since the last REFRESH command
The SLOW pin has transitioned high to low since the last REFRESH command
The bit is reset to 0 by a REFRESH or REFRESH_G command
bit 4 = 0
bit 4 = 1
Disables a limited REFRESH function to take place on the rising edge of the SLOW pin
Enables a limited REFRESH function to take place on the rising edge of the SLOW pin
The bit is not reset automatically, it must be written to be changed.
bit 3 = 0
bit 3 = 1
Disables a limited REFRESH_V function to take place on the rising edge of the SLOW pin
Enables a limited REFRESH_V function to take place on the rising edge of the SLOW pin
The bit is not reset automatically, it must be written to be changed
bit 2 = 0
bit 2 = 1
Disables a limited REFRESH function to take place on the falling edge of the SLOW pin
Enables a limited REFRESH function to take place on the falling edge of the SLOW pin
The bit is not reset automatically, it must be written to be changed
bit 1 = 0
bit 1 = 1
Disables a limited REFRESH_V function to take place on the falling edge of the SLOW pin
Enables a limited REFRESH_V function to take place on the falling edge of the SLOW pin
The bit is not reset automatically, it must be written to be changed
POR Status Bit
The POR bit is a POR flag, for the purpose of enabling the system designer can clear it after POR, and then monitor
it to detect if the device was powered cycled or somehow reset since the POR. If the reset is detected in this manner,
any non-default programming can be reprogrammed.
bit 0 = 0
bit 0 = 1
This bit has been cleared over I2C since the last POR occurred
This bit has the POR default value of 1, and has not been cleared since the last reset occurred
This bit is only reset by POR
2017-2019 Microchip Technology Inc.
DS20005850E-page 45
PAC1931/2/3/4
REGISTER 6-15: CTRL_ACT REGISTER (ADDRESS 21H)
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
OVF
bit 0
Sample_Rate[1:0]
bit 7
SLEEP
SING
ALERT_PIN ALERT_CC OVF ALERT
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
This register contains an image of the Control register, 01h. The bits in this register reflect the current active value of
these settings, whereas the values in register 01h may have been programmed but not activated by one of the
REFRESH commands. This register allows the software to determine the actual active setting.
This register is valid when the Results registers are valid, 1 ms after a REFRESH/_V/_G command (in most cases).
However, if the users program a conversion rate change followed by REFRESH, the new conversion rate will not
become effective until the current conversion cycle is complete. For example, if the old sample rate was 8 Hz, it will
take up to 125 mS before the conversion cycle (and the CTRL_ACT register) are updated. This delay can be variable,
depending on where we are in the conversion cycle when the REFRESH command is sent.
bit 7-6
Sample_Rate[1:0]: shows the value that is currently active since the most recent REFRESH function
was received for programmed sample rate in Normal mode (that is, if SLOW pin is not asserted)
00b= 1024 samples/s
01b= 256 samples/s
10b= 64 samples/s
11b= 8 samples/s
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SLEEP: shows the value that is currently active since the most recent REFRESH function was received
for the SLEEP bit.
0= ACTIVE mode
1= SLEEP mode, no data conversion
SING: shows the value that is currently active since the most recent REFRESH function was received
for the single shot select bit, SING.
0= Sequential scan mode
1= Single-shot mode
ALERT_PIN: shows the value that is currently active since the most recent REFRESH function was
received for the ALERT_PIN bit.
0= Disable the ALERT pin function
1= Enable the ALERT pin function
ALERT_CC: shows the value that is currently active since the most recent REFRESH function was
received for the ALERT_CC bit.
0= No ALERT on Conversion Cycle Complete
1= ALERT function asserted for 5 μS on each completion of the conversion cycle
OVF ALERT: shows the value that is currently active since the most recent REFRESH function was
received for the OVF ALERT bit.
0= No ALERT if accumulator or accumulator counter overflow has occurred
1= ALERT pin triggered if accumulator or accumulator counter has overflowed
OVF: shows the value that is currently active since the most recent REFRESH function was received
for the OVF bit.
0= No accumulator or accumulator counter overflow has occurred
1= Accumulator or accumulator counter has overflowed
DS20005850E-page 46
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
REGISTER 6-16: CHANNEL DIS_ACT (ADDRESS 22H)
R-0
R-0
R-0
R-0
U
U
U
U
—
CH1_OFF
CH2_OFF
CH3_OFF
CH4_OFF
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
This register contains an image of the Channel Disable bits in register 1Ch.The bits in this register reflect the value
that was activated by the most recent REFRESH function, and is currently active. Whereas the values in register 1Ch
may have been programmed but not activated by one of the REFRESH commands, register 22h allows software to
determine the actual active setting. This register is valid when the Results registers are valid, 1 ms after a
REFRESH/_V/_G command.
bit 7-4
bit 7
CHn_OFF[7:4]: shows the value that is currently active for these bits.
0= CH1 ON. Channel 1 active during conversion cycle
1= CH1 OFF. Channel 1 inactive during conversion cycle
0= CH2 ON. Channel 2 active during conversion cycle
1= CH2 OFF. Channel 2 inactive during conversion cycle
0= CH3 ON. Channel 3 active during conversion cycle
1= CH3 OFF. Channel 3 inactive during conversion cycle
0= CH4 ON. Channel 4 active during conversion cycle
1= CH4 OFF. Channel 4 inactive during conversion cycle
Not used, always reads ‘0’
bit 6
bit 5
bit 4
bit 3-0
REGISTER 6-17: NEG_PWR_ACT (ADDRESS 23H)
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CH4_BIDV
bit 0
CH1_BIDI
CH2_BIDI
CH3_BIDI
CH4 BIDI
CH1_BIDV
CH2_BIDV
CH3_BIDV
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
This register contains an image of the NEG_PWR register, 1Dh.The bits in this register reflect the current active value
of these settings, whereas the values in register 1Dh may have been programmed but not activated by one of the
REFRESH commands. This register allows software to determine the actual active setting. This register is valid when
the Results registers are valid, 1 ms after a REFRESH/_V/_G command.
bit 7-4
bit 3-0
bit 7
CH1_BIDI[7:4]: these bits show the current active value of the corresponding bits in Register 6-11,
NEG_PWR (Address 1Dh).
CH1_BIDV[3:0]: these bits show the current active value of the corresponding bits in Register 6-11,
NEG_PWR (Address 1Dh).
0= Channel 1 VSENSE ADC converts 0 to +100 mV range with 16-bit straight binary output
1= Channel 1 VSENSE ADC converts -100 mV to +100 mV range with 16-bit two’s complement output
0= Channel 2 VSENSE ADC converts 0 to +100 mV range with 16-bit straight binary output
1= Channel 2 VSENSE ADC converts -100 mV to +100 mV range with 16-bit two’s complement output
0= Channel 3 VSENSE ADC converts 0 to +100 mV range with 16-bit straight binary output
1= Channel 3 VSENSE ADC converts -100 mV to +100 mV range with 16-bit two’s complement output
0= Channel 4 VSENSE ADC converts 0 to +100 mV range with 16-bit straight binary output
1= Channel 4 VSENSE ADC converts -100 mV to +100 mV range with 16-bit two’s complement output
bit 6
bit 5
bit 4
2017-2019 Microchip Technology Inc.
DS20005850E-page 47
PAC1931/2/3/4
REGISTER 6-17: NEG_PWR_ACT (ADDRESS 23H) (CONTINUED)
bit 3
bit 2
bit 1
bit 0
0= Channel 1 VBUS ADC converts 0 to +32V range with 16-bit straight binary output
1= Channel 1 VBUS ADC converts -32V to +32V range with 16-bit two’s complement output
0= Channel 2 VBUS ADC converts 0 to +32V range with 16-bit straight binary output
1= Channel 2 VBUS ADC converts -32V to +32V range with 16-bit two’s complement output
0= Channel 3 VBUS ADC converts 0 to +32V range with 16-bit straight binary output
1= Channel 3 VBUS ADC converts -32V to +32V range with 16-bit two’s complement output
0= Channel 4 VBUS ADC converts 0 to +32V range with 16-bit straight binary output
1= Channel 4 VBUS ADC converts -32V to +32V range with 16-bit two’s complement output
REGISTER 6-18: CTRL_LAT REGISTER (ADDRESS 24H)
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
OVF
bit 0
Sample_Rate[1:0]
bit 7
SLEEP
SING
ALERT_PIN ALERT_CC OVF ALERT
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
This register contains an image of the Register 6-15 CTRL_ACT Register (Address 21h). The bits in this register
reflect the value of these settings that was active before the most recent REFRESH command (including REFRESH_V
and/or REFRESH_G). The values in register 01h may have been programmed but not activated by one of the
REFRESH commands, and the values in 21h are currently active. This register allows software to determine the actual
active setting that was active prior to the most recent REFRESH command and therefore corresponds to the dataset
that is held in the readable registers. This register is valid when the Results registers are valid, 1 ms after a
REFRESH/_V/_G command.
bit 7-6
Sample_Rate[1:0]: shows the value of these settings that was latched prior to the most recent
REFRESH command (including REFRESH_V and/or REFRESH_G)
00b= 1024 samples/s
01b= 256 samples/s
10b= 64 samples/s
11b= 8 samples/s
bit 5
bit 4
bit 3
bit 2
SLEEP: shows the value of these settings that was latched prior to the most recent REFRESH
command (including REFRESH_V and/or REFRESH_G).
0= Active mode
1= SLEEP mode, no data conversion
SING: shows the value of these settings that was latched prior to the most recent REFRESH command
(including REFRESH_V and/or REFRESH_G).
0= Sequential scan mode
1= Single-shot mode
ALERT_PIN: the value of these settings that was latched prior to the most recent REFRESH command
(including REFRESH_V and/or REFRESH_G).
0= Disable the ALERT pin function
1= Enable the ALERT pin function
ALERT_CC: shows the value of these settings that was latched prior to the most recent REFRESH
command (including REFRESH_V and/or REFRESH_G) for the ALERT_CC bit.
0= No ALERT on Conversion Cycle Complete
1= ALERT function asserted for 5 μS on each completion of the conversion cycle
DS20005850E-page 48
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
REGISTER 6-18: CTRL_LAT REGISTER (ADDRESS 24H) (CONTINUED)
bit 1
OVF ALERT: shows the value of these settings that was latched prior to the most recent REFRESH
command (including REFRESH_V and/or REFRESH_G) for the OVF_ALERT bit.
0= No ALERT if accumulator or accumulator counter overflow has occurred
1= ALERT pin triggered if accumulator or accumulator counter has overflowed
bit 0
OVF: shows the value of these settings that was latched prior to the most recent REFRESH command
(including REFRESH_V and/or REFRESH_G) for the OVF bit.
0= No accumulator or accumulator counter overflow has occurred
1= Accumulator or accumulator counter has overflowed
REGISTER 6-19: CHANNEL DIS_LAT (ADDRESS 25H)
R-0
R-0
R-0
R-0
U
U
U
U
—
CH1_OFF
CH2_OFF
CH3_OFF
CH4_OFF
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
This register contains an image of the Register 6-16 Channel DIS_ACT (Address 22h).The bits in this register reflect
the value of these settings that was active before the most recent REFRESH command (including REFRESH_V and/or
REFRESH_G). The values in register 1Ch may have been programmed but not activated by one of the REFRESH
commands, and the values in 22h are currently active. This register allows software to determine the actual active
setting that was active prior to the most recent REFRESH command and therefore corresponds to the dataset that is
held in the readable registers. This register is valid when the Results registers are valid, 1 ms after a REFRESH/_V/_G
command.
bit 7-4
CHn_OFF[7:4]: the value of these settings that was latched prior to the most recent REFRESH
command (including REFRESH_V and/or REFRESH_G).
bit 7
0= CH1 ON. Channel 1 active during conversion cycle
1= CH1 OFF. Channel 1 inactive during conversion cycle
bit 6
0= CH2 ON. Channel 2 active during conversion cycle
1= CH2 OFF. Channel 2 inactive during conversion cycle
bit 5
0= CH3 ON. Channel 3 active during conversion cycle
1= CH3 OFF. Channel 3 inactive during conversion cycle
bit 4
0= CH4 ON. Channel 4 active during conversion cycle
1= CH4 OFF. Channel 4 inactive during conversion cycle
bit 3-0
Not used, always read ‘0’
2017-2019 Microchip Technology Inc.
DS20005850E-page 49
PAC1931/2/3/4
REGISTER 6-20: NEG_PWR _LAT (ADDRESS 26H)
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CH4_BIDV
bit 0
CH1_BIDI
CH2_BIDI
CH3_BIDI
CH4 BIDI
CH1_BIDV
CH2_BIDV
CH3_BIDV
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
This register contains an image of the Register 6-17 NEG_PWR_ACT (Address 23h).The bits in this register reflect
the value of these settings that was active before the most recent REFRESH command (including REFRESH_V and/or
REFRESH_G). The values in register 1Dh may have been programmed but not activated by one of the REFRESH
commands, and the values in 23h are currently active. This register allows software to determine the actual active
setting that was active prior to the most recent REFRESH command and therefore corresponds to the dataset that is
held in the readable registers. This register is valid when the Results registers are valid, 1 ms after a REFRESH/_V/_G
command.
bit 7-4
bit 3-0
bit 7
CHn_BIDI[7:4]: the value of these settings that was latched prior to the most recent REFRESH
command (including REFRESH_V and/or REFRESH_G).
CHn_BIDV[3:0]: the value of these settings that was latched prior to the most recent REFRESH
command (including REFRESH_V and/or REFRESH_G).
0= Channel 1 VSENSE ADC converts 0 to +100mV range with 16-bit straight binary output
1= Channel 1 VSENSE ADC converts -100mV to +100mV range with 16 bit two’s complement output
0= Channel 2 VSENSE ADC converts 0 to +100mV range with 16-bit straight binary output
1= Channel 2 VSENSE ADC converts -100mV to +100mV range with 16-bit two’s complement output
0= Channel 3 VSENSE ADC converts 0 to +100mV range with 16-bit straight binary output
1= Channel 3 VSENSE ADC converts -100mV to +100mV range with 16-bit two’s complement output
0= Channel 4 VSENSE ADC converts 0 to +100mV range with 16-bit straight binary output
1= Channel 4 VSENSE ADC converts -100mV to +100mV range with 16-bit two’s complement output
0= Channel 1 VBUS ADC converts 0 to +32V range with 16-bit straight binary output
1= Channel 1 VBUS ADC converts -32V to +32V range with 16-bit two’s complement output
0= Channel 2 VBUS ADC converts 0 to +32V range with 16-bit straight binary output
1= Channel 2 VBUS ADC converts -32V to +32V range with 16-bit two’s complement output
0= Channel 3 VBUS ADC converts 0 to +32V range with 16-bit straight binary output
1= Channel 3 VBUS ADC converts -32V to +32V range with 16-bit two’s complement output
0= Channel 4 VBUS ADC converts 0 to +32V range with 16-bit straight binary output
1= Channel 4 VBUS ADC converts -32V to +32V range with 16-bit two’s complement output
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS20005850E-page 50
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
REGISTER 6-21: PRODUCT ID REGISTER (ADDRESS FDh)
R-0
R-1
R-0
R-1
R-1
R-0
R-1
R-1
PID[7:0]
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
PID[7:0]: contain the Product ID for the PAC1931/2/3/4.
0101_1000for PAC1931
0101_1001for PAC1932
0101_1010for PAC1933
0101_1011for PAC1934 (Default shown in table directly above)
REGISTER 6-22: MANUFACTURER ID REGISTER (ADDRESS FEh)
R-0
R-1
R-0
R-1
R-1
R-1
R-0
R-1
MID[7:0]
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
MID[7:0]: the Manufacturer ID register identifies Microchip as the manufacturer of the PAC1931/2/3/4
This value is 5Dh.
REGISTER 6-23: REVISION ID REGISTER (ADDRESS FFh)
R-0
R-0
R-0
R-0
R-0
R-0
R-1
R-1
RID[7:0]
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writeable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
RID[7:0]: the Revision register identifies the die revision
This register reads 03h.
2017-2019 Microchip Technology Inc.
DS20005850E-page 51
PAC1931/2/3/4
7.0
PACKAGE DESCRIPTION
7.1
Package Marking Information
UQFN
PAC1932/3/4
Example
PAC
1932
JQ^
e3
929256
WLCSP-16
PAC1931/2/3/4
Example
934
925
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS20005850E-page 52
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
E
N
NOTE 1
1
2
(DATUM B)
(DATUM A)
2X
0.20 C
2X
TOP VIEW
0.20 C
0.10 C
A1
C
A
SEATING
PLANE
16X
(A3)
0.08 C
C A B
SIDE VIEW
0.10
D2
0.10
C A B
E2
2
1
e
2
NOTE 1
K
N
L
16X b
0.10
C A B
e
BOTTOM VIEW
Microchip Technology Drawing C04-257A Sheet 1 of 2
2017-2019 Microchip Technology Inc.
DS20005850E-page 53
PAC1931/2/3/4
16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Pins
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Width
Exposed Pad Width
Overall Length
Exposed Pad Length
Terminal Width
Terminal Length
N
16
0.65 BSC
0.50
e
A
A1
A3
E
E2
D
D2
b
L
0.45
0.00
0.55
0.05
0.02
0.127 REF
4.00 BSC
2.60
4.00 BSC
2.60
2.50
2.70
2.50
0.25
0.30
0.20
2.70
0.35
0.50
-
0.30
0.40
-
Terminal-to-Exposed-Pad
K
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-257A Sheet 2 of 2
DS20005850E-page 54
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body
[UQFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
16
1
2
C2 Y2
Y1
X1
E
SILK SCREEN
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
MILLIMETERS
NOM
0.65 BSC
MIN
MAX
Contact Pitch
Optional Center Pad Width
Optional Center Pad Length
Contact Pad Spacing
Contact Pad Spacing
Contact Pad Width (X16)
Contact Pad Length (X16)
X2
Y2
C1
C2
X1
Y1
2.70
2.70
4.00
4.00
0.35
0.80
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2257A
2017-2019 Microchip Technology Inc.
DS20005850E-page 55
PAC1931/2/3/4
ꢁꢂꢃ%DOOꢄ:DIHUꢄ/HYHOꢄ&KLSꢄ6FDOHꢄ3DFNDJHꢄꢅ&6ꢆꢄꢄꢃꢄꢇꢈꢇꢇꢉ[ꢇꢈꢁꢊꢄPPꢄ%RG\ꢄ>:/&63@
3$&ꢁꢋꢌꢍ
1RWHꢀ )RUꢆWKHꢆPRVWꢆFXUUHQWꢆSDFNDJHꢆGUDZLQJVꢍꢆSOHDVHꢆVHHꢆWKHꢆ0LFURFKLSꢆ3DFNDJLQJꢆ6SHFLILFDWLRQꢆORFDWHGꢆDW
KWWSꢎꢏꢏZZZꢁPLFURFKLSꢁFRPꢏSDFNDJLQJ
'
$
%
(
ꢂ
ꢈ
ꢌ
ꢉ
127(ꢆꢂ
$
%
&
'
ꢅ'$780ꢆ%ꢇ
ꢅ'$780ꢆ$ꢇ
ꢈ;
ꢀꢁꢀꢂꢀ &
ꢈ;
ꢀꢁꢀꢂꢀ &
723ꢆ9,(:
6,'(ꢆ9,(:
$ꢂ
$ꢈ
&
$
6($7,1*
3/$1(
ꢂꢋ;
ꢀꢁꢀꢄꢀ &
ꢂ
ꢈ
ꢌ
ꢉ
ꢂꢋ;ꢆE
ꢀꢁꢀꢃ
ꢀꢁꢀꢄ
& $ %
&
'
&
%
$
H(
ꢈ
H(
H'
ꢈ
H'
%27720ꢆ9,(:
0LFURFKLSꢆ7HFKQRORJ\ꢆ'UDZLQJꢆꢆ&ꢀꢉꢊꢋꢀꢌꢋꢊꢀꢂꢆ5HYꢁꢆ%ꢆ6KHHWꢆꢂꢆRIꢆꢈ
DS20005850E-page 56
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
ꢁꢂꢃ%DOOꢄ:DIHUꢄ/HYHOꢄ&KLSꢄ6FDOHꢄ3DFNDJHꢄꢅ&6ꢆꢄꢄꢃꢄꢇꢈꢇꢇꢉ[ꢇꢈꢁꢊꢄPPꢄ%RG\ꢄ>:/&63@
3$&ꢁꢋꢌꢍ
1RWHꢀ )RUꢆWKHꢆPRVWꢆFXUUHQWꢆSDFNDJHꢆGUDZLQJVꢍꢆSOHDVHꢆVHHꢆWKHꢆ0LFURFKLSꢆ3DFNDJLQJꢆ6SHFLILFDWLRQꢆORFDWHGꢆDW
KWWSꢎꢏꢏZZZꢁPLFURFKLSꢁFRPꢏSDFNDJLQJ
8QLWV
'LPHQVLRQꢆ/LPLWV
0,//,0(7(56
120
0,1
0$;
%XPSꢆ3LWFK
%XPSꢆ3LWFK
/HQJWK
H'
H(
'
(
$
$ꢂ
$ꢈ
E
ꢀꢁꢄꢀꢆ%6&
ꢀꢁꢄꢀꢆ%6&
ꢈꢁꢈꢈꢄꢆ%6&
ꢈꢁꢂꢃꢀꢆ%6&
ꢀꢁꢋꢉꢂ
:LGWK
2YHUDOOꢆ+HLJKW
%XPSꢆ+HLJKW
'LHꢆ7KLFNQHVV
%XPSꢆ'LDPHWHU
ꢀꢁꢋꢀꢂ
ꢀꢁꢂꢐꢃ
ꢀꢁꢌꢋꢌ
ꢀꢁꢈꢐꢃ
ꢀꢁꢋꢃꢐ
ꢀꢁꢈꢄꢃ
ꢀꢁꢉꢂꢌ
ꢀꢁꢌꢄꢃ
ꢊ
ꢀꢁꢌꢑꢑ
ꢀꢁꢌꢈꢃ
Notes:
ꢂꢁ 7RSVLGHꢆ$ꢂꢆLQGLFDWRUꢆLVꢆDQꢆHQJUDYHGꢆILJXUHꢁ
ꢈꢁ 8QGHUꢊILOOꢆLVꢆUHFRPPHQGHGꢆIRUꢆEHVWꢆVROGHUꢆMRLQWꢆUHOLDELOLW\ꢁ
ꢌꢁ 6ROGHUꢆGLDPHWHUꢆDWꢆLQWHUIDFHꢆWRꢆSDFNDJHꢆERG\ꢆLVꢆꢌꢀꢀPꢆꢅQRPLQDOꢇꢁ
ꢉꢁ 'LPHQVLRQLQJꢆDQGꢆWROHUDQFLQJꢆSHUꢆ$60(ꢆ<ꢂꢉꢁꢄ0
%6&ꢎꢆ%DVLFꢆ'LPHQVLRQꢁꢆ7KHRUHWLFDOO\ꢆH[DFWꢆYDOXHꢆVKRZQꢆZLWKRXWꢆWROHUDQFHVꢁ
5()ꢎꢆ5HIHUHQFHꢆ'LPHQVLRQꢍꢆXVXDOO\ꢆZLWKRXWꢆWROHUDQFHꢍꢆIRUꢆLQIRUPDWLRQꢆSXUSRVHVꢆRQO\ꢁ
0LFURFKLSꢆ7HFKQRORJ\ꢆ'UDZLQJꢆꢆ&ꢀꢉꢊꢋꢀꢌꢋꢊꢀꢂꢆ5HYꢁꢆ%ꢆ6KHHWꢆꢈꢆRIꢆꢈ
2017-2019 Microchip Technology Inc.
DS20005850E-page 57
PAC1931/2/3/4
ꢁꢂꢃ%DOOꢄ:DIHUꢄ/HYHOꢄ&KLSꢄ6FDOHꢄ3DFNDJHꢄꢅ&6ꢆꢄꢄꢃꢄꢇꢈꢇꢇꢉ[ꢇꢈꢁꢊꢄPPꢄ%RG\ꢄ>:/&63@
3$&ꢁꢋꢌꢍ
1RWHꢀ )RUꢆWKHꢆPRVWꢆFXUUHQWꢆSDFNDJHꢆGUDZLQJVꢍꢆSOHDVHꢆVHHꢆWKHꢆ0LFURFKLSꢆ3DFNDJLQJꢆ6SHFLILFDWLRQꢆORFDWHGꢆDW
KWWSꢎꢏꢏZZZꢁPLFURFKLSꢁFRPꢏSDFNDJLQJ
'ꢂ
H'
$
H(
%
(ꢂ
*ꢈ
&
'
ꢂ
ꢈ
ꢌ
ꢉ
;ꢂ
6,/.ꢆ6&5((1
*ꢂ
5(&200(1'('ꢆ/$1'ꢆ3$77(51
8QLWV
'LPHQVLRQꢆ/LPLWV
0,//,0(7(56
0,1
120
ꢀꢁꢄꢀꢆ%6&
ꢀꢁꢄꢀꢆ%6&
ꢂꢁꢄꢀꢆ%6&
ꢂꢁꢄꢀꢆ%6&
ꢀꢁꢈꢄ
0$;
&RQWDFWꢆ3LWFK
&RQWDFWꢆ3LWFK
2YHUDOOꢆ3LWFK
2YHUDOOꢆ3LWFK
6SDFHꢆ%HWZHHQꢆ&RQWDFWV
6SDFHꢆ%HWZHHQꢆ&RQWDFWV
&RQWDFWꢆ'LDPHWHU
H'
H(
'ꢂ
(ꢂ
*ꢂ
*ꢈ
;ꢂ
ꢀꢁꢈꢄ
ꢀꢁꢈꢄ
1RWHVꢎ
ꢂꢁ 'LPHQVLRQLQJꢆDQGꢆWROHUDQFLQJꢆSHUꢆ$60(ꢆ<ꢂꢉꢁꢄ0
%6&ꢎꢆ%DVLFꢆ'LPHQVLRQꢁꢆ7KHRUHWLFDOO\ꢆH[DFWꢆYDOXHꢆVKRZQꢆZLWKRXWꢆWROHUDQFHVꢁ
ꢈꢁ )RUꢆEHVWꢆVROGHULQJꢆUHVXOWVꢍꢆWKHUPDOꢆYLDVꢍꢆLIꢆXVHGꢍꢆVKRXOGꢆEHꢆILOOHGꢆRUꢆWHQWHGꢆWRꢆDYRLGꢆVROGHUꢆORVVꢆGXULQJ
UHIORZꢆSURFHVV
0LFURFKLSꢆ7HFKQRORJ\ꢆ'UDZLQJꢆ&ꢀꢉꢊꢑꢀꢌꢋꢆ5HYꢁꢆ%
DS20005850E-page 58
2017-2019 Microchip Technology Inc.
PAC1931/2/3/4
APPENDIX A: REVISION HISTORY
Revision E (August 2019)
The following is the list of modifications:
1. Added the PAC1931 Single-Channel DC
Power/Energy Monitor with Accumulator and
related information throughout the Data Sheet.
Revision D (May 2019)
The following is the list of modifications:
1. Added the WLCSP package.
2. Updated Table 1-1.
3. Replaced Figure 2-22.
4. Updated
Register 6-10,
Register 6-14,
Register 6-16, and Register 6-19.
Revision C (June 2018)
The following is the list of modifications:
1. Added the entire PAC1932/3/4 device family.
2. Added UQFN package.
3. Updated Table 1-1.
4. Updated Section 2.0 “Typical Operating
Curves”.
5. Updated Section 3.0 “Pin Descriptions”.
6. Updated Register 6-10.
7. Updated Register 6-15.
8. Updated Register 6-21.
9. Updated Section 7.0 “Package Description”.
10. Updated Product Identification System.
11. Fixed minor typographical errors.
Revision B (November 2017)
The following is the list of modifications:
1. Updated Section 4.5 “Voltage Measurement”,
Section 4.6
“Current
Measurement”,
Section 4.7 “Selecting RSENSE Values” and
Section 4.9 “Power and Energy”.
2. Updated Register 6-10.
3. Fixed minor typographical errors.
Revision A (September 2017)
• Initial Release for Advance Data Sheet.
2017-2019 Microchip Technology Inc.
DS20005850E-page 59
PAC1931/2/3/4
NOTES:
2017-2019 Microchip Technology Inc.
DS20005850E-page 60
PAC1931/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
-X
/XXX
Example:
a) PAC1932T-I/JQ:
16-Lead 4 mm × 4 mm UQFN,
shipped in a 3,300 piece Tape and Reel
Tape and
Reel
Temperature
Range
Package
b) PAC1933T-I/JQ:
c) PAC1934T-I/JQ:
16-Lead 4 mm × 4 mm UQFN,
shipped in a 3,300 piece Tape and Reel
Device:
PAC1931/2/3/4: Single/Multi-Channel DC Power/Energy
Monitor with Accumulator
16-Lead 4 mm × 4 mm UQFN,
shipped in a 3,300 piece Tape and Reel
a) PAC1934T-I/J6CX: 16-lead 2.225 mm x 2.17 mm WLCSP,
shipped in a 5,000 piece Tape and Reel
Tape and Reel:
T
I
= Tape and Reel
b) PAC1933T-I/J6CX: 16-lead 2.225 mm x 2.17 mm WLCSP,
shipped in a 5,000 piece Tape and Reel
Temperature
Range:
= -40C to +85C (Industrial)
c) PAC1932T-I/J6CX: 16-lead 2.225 mm x 2.17 mm WLCSP,
shipped in a 5,000 piece Tape and Reel
d) PAC1931T-I/J6CX: 16-lead 2.225 mm x 2.17 mm WLCSP,
shipped in a 5,000 piece Tape and Reel
Package:
JQ
= 16-Lead Ultra Thin Plastic Quad Flat, No Lead
Package, 4 mm × 4 mm × 0.5 mm Body (UQFN)
Note 1:
Tape and Reel identifier only appears in the catalog
part number description. This identifier is used for
ordering purposes and is not printed on the device
package. Check with your Microchip Sales Office for
package availability with the Tape and Reel option.
J6CX = 16-Ball Wafer Level Chip Scale Package,
2.225 mm × 2.17 mm (WLCSP)
2017-2019 Microchip Technology Inc.
DS20005850E-page 61
PAC1931/2/3/4
NOTES:
DS20005850E-page 62
2017-2019 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-4949-2
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2017-2019 Microchip Technology Inc.
DS20005850E-page 63
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Australia - Sydney
Tel: 61-2-9868-6733
India - Bangalore
Tel: 91-80-3090-4444
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Beijing
Tel: 86-10-8569-7000
India - New Delhi
Tel: 91-11-4160-8631
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
China - Chengdu
Tel: 86-28-8665-5511
India - Pune
Tel: 91-20-4121-0141
Finland - Espoo
Tel: 358-9-4520-820
China - Chongqing
Tel: 86-23-8980-9588
Japan - Osaka
Tel: 81-6-6152-7160
Web Address:
www.microchip.com
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
China - Dongguan
Tel: 86-769-8702-9880
Japan - Tokyo
Tel: 81-3-6880- 3770
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Guangzhou
Tel: 86-20-8755-8029
Korea - Daegu
Tel: 82-53-744-4301
Germany - Garching
Tel: 49-8931-9700
China - Hangzhou
Tel: 86-571-8792-8115
Korea - Seoul
Tel: 82-2-554-7200
Germany - Haan
Tel: 49-2129-3766400
Austin, TX
Tel: 512-257-3370
China - Hong Kong SAR
Tel: 852-2943-5100
Malaysia - Kuala Lumpur
Tel: 60-3-7651-7906
Germany - Heilbronn
Tel: 49-7131-72400
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
China - Nanjing
Tel: 86-25-8473-2460
Malaysia - Penang
Tel: 60-4-227-8870
Germany - Karlsruhe
Tel: 49-721-625370
China - Qingdao
Philippines - Manila
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Tel: 86-532-8502-7355
Tel: 63-2-634-9065
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
China - Shanghai
Tel: 86-21-3326-8000
Singapore
Tel: 65-6334-8870
Germany - Rosenheim
Tel: 49-8031-354-560
China - Shenyang
Tel: 86-24-2334-2829
Taiwan - Hsin Chu
Tel: 886-3-577-8366
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Israel - Ra’anana
Tel: 972-9-744-7705
China - Shenzhen
Tel: 86-755-8864-2200
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
China - Suzhou
Tel: 86-186-6233-1526
Taiwan - Taipei
Tel: 886-2-2508-8600
Detroit
Novi, MI
Tel: 248-848-4000
China - Wuhan
Tel: 86-27-5980-5300
Thailand - Bangkok
Tel: 66-2-694-1351
Italy - Padova
Tel: 39-049-7625286
Houston, TX
Tel: 281-894-5983
China - Xian
Tel: 86-29-8833-7252
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
China - Xiamen
Tel: 86-592-2388138
Norway - Trondheim
Tel: 47-7288-4388
China - Zhuhai
Tel: 86-756-3210040
Poland - Warsaw
Tel: 48-22-3325737
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Raleigh, NC
Tel: 919-844-7510
Sweden - Gothenberg
Tel: 46-31-704-60-40
New York, NY
Tel: 631-435-6000
Sweden - Stockholm
Tel: 46-8-5090-4654
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS20005850E-page 64
2017-2019 Microchip Technology Inc.
05/14/19
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明