PCX7410VGU400L_技术文档

Features

• 22.8 SPECint95 (estimated), 17SPECfp95 at 500 MHz (estimated)

• 917MIPS at 500 MHz

• Selectable Bus Clock (14 CPU Bus Dividers Up To 9x)

• Seven Selectable Core-to-L2 Frequency Divisors

• Selectable 603 Interface Voltage Below 3.3V (1.8V, 2.5V)

• Selectable L2 interface of 1.8V or 2.5V

• P_DTypical 5.3W at 500 MHz, Full Operating Conditions

• Nap, Doze and Sleep Modes for Power Saving

• Superscalar (Four Instructions fetched per Clock Cycle)

• 4 GB Direct Addressing Range

PowerPC 7410

RISC

Microprocessor

Preliminary

Specification

β-site

• Virtual Memory: 4 hexabytes (2⁵²)

• 64-bit Data and 32-bit Address Bus Interface

• 32 KB Instruction and Data Cache

• Eight Independent Execution Units and Three Register Files

• Write-back and Write-through Operations

• f_INTMax = 450 MHz (500 MHz to be confirmed)

• f_BUSMax = 133 MHz

Description

The PC7410 is the second microprocessor that uses the fourth (G4) full implementa-

tion of the PowerPC^™Reduced Instruction Set Computer (RISC) architecture. It is

fully JTAG-compliant.

The PC7410 maintains some of the characteristics of G3 microprocessors:

PC7410

•

The design is superscalar, capable of issuing three instructions per clock cycle

into eight independent execution units

The microprocessor provides four software controllable power-saving modes and

a thermal assist unit management

The microprocessor has separate 32-Kbyte, physically-addressed instruction and

data caches with dedicated L2 cache interface with on-chip L2 tags

In addition, the PC7410 integrates full hardware-based multiprocessing capability,

including a 5-state cache coherency protocol (4 MESI states plus a fifth state for

shared intervention) and an implementation of the new AltiVec^™technology instruc-

tion set.

New features have been developed to make latency equal for double-precision and

single-precision floating-point operations involving multiplication. Additionally, in mem-

ory subsystem (MSS) bandwidth, the PC7410 offers an optional, high-bandwidth MPX

bus interface.

Unlike the PC7400, the PC7410 does not support the 3.3V I/O on the L2 cache

interface.

Rev. 2141B–HIREL–01/03

1

Screening

•

CBGA Upscreenings Based on Atmel Standards

•

Full Military Temperature Range (T_j= -55°C, +125°C),

Industrial Temperature Range (T_j= -40°C, +110°C)

•

CI-CGA Package Versions, HiTCE (TBC)

GS suffix

CI±CGA 360

Ceramic Ball Grid Array

with Solder Column Interposer (SCI)

G suffix

CBGA 360

Ceramic Ball Grid Array

GH suffix

HITCE 360

Ceramic Ball Grid Array

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PC7410

2141B–HIREL–01/03

PC7410

Block Diagram

Figure 1. PC7410 Microprocessor Block Diagram

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General Parameters

Table 1 provides a summary of the general parameters of the PC7410.

Table 1. Device Parameters

Parameter

Technology

Die size

Description

0.18 µm CMOS, six-layer metal

6.32 mm x 8.26 mm (52 mm²)

10.5 million

Transistor count

Logic design

Packages

Fully-static

Surface-mount, ceramic 360-ball or -column grid array

(CBGA/CI-CGA)

Core power supply

I/O power supply

1.8V ± 100 mV dc or 1.5V ± 50 mV dc (nominal; see Table 4 for

Recommended Operating Conditions)

1.8V ± 100 mV dc or

2.5V ± 100 mV dc (input thresholds are configuration pin selectable) or

3.3V ± 100 mV (603 bus only) ⁽¹⁾

Note:

1. 3.3V I/O bus not supported for 1.5V core power supply processor version.

Features

This section summarizes features of the PC7410’s implementation of the PowerPC

architecture. Major features of the PC7410 are as follows:

•

Branch Processing Unit

–

Four instructions fetched per clock

One branch processed per cycle (plus resolving two speculations)

Up to one speculative stream in execution, one additional speculative

stream in fetch

–

512-entry branch history table (BHT) for dynamic prediction

64-entry, 4-way set associative branch target instruction cache (BTIC) for

eliminating branch delay slots

•

Dispatch Unit

–

Full hardware detection of dependencies (resolved in the execution units)

Dispatch two instructions to eight independent units (system, branch,

load/store, fixed-point unit 1, fixed-point unit 2, floating-point, AltiVec

permute, AltiVec ALU)

–

Serialization control (predispatch, postdispatch, execution serialization)

•

Decode

–

Register file access

Forwarding control

Partial instruction decode

Completion

–

8-entry completion buffer

Instruction tracking and peak completion of two instructions per cycle

Completion of instructions in program order while supporting out-of-order

instruction execution, completion serialization and all instruction flow

changes

•

Fixed-point Units (FXUs) that Share 32 GPRs for Integer Operands

Fixed-point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical

–

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PC7410

2141B–HIREL–01/03

PC7410

–

Fixed-point unit 2 (FXU2) — shift, rotate, arithmetic, logical

Single-cycle arithmetic, shifts, rotates, logical

Multiply and divide support (multi-cycle)

Early out multiply

•

Three-stage Floating-point Unit and a 32-entry FPR File

–

Support for IEEE-754 standard single- and double-precision floating-point

arithmetic

–

Three-cycle latency, one-cycle throughput (single or double precision)

Hardware support for divide

Hardware support for denormalized numbers

Time deterministic non-IEEE mode

•

System Unit

–

Executes CR logical instructions and miscellaneous system instructions

Special register transfer instructions

AltiVec Unit

–

Full 128-bit data paths

Two dispatchable units: vector permute unit and vector ALU unit

Contains its own 32-entry 128-bit vector register file (VRF) with six renames

The vector ALU unit is further sub-divided into the vector simple integer unit

(VSIU), the vector complex integer unit (VCIU) and the vector floating-point

unit (VFPU).

–

Fully pipelined

•

Load/Store Unit

–

One-cycle load or store cache access (byte, half-word, word, double-word)

Two-cycle load latency with one-cycle throughput

Effective address generation

Hits under misses (multiple outstanding misses)

Single-cycle unaligned access within double-word boundary

Alignment, zero padding, sign extend for integer register file

Floating-point internal format conversion (alignment, normalization)

Sequencing for load/store multiples and string operations

Store gathering

Executes the cache and TLB instructions

Big- and little-endian byte addressing supported

Misaligned little-endian supported

Supports FXU, FPU, and AltiVec load/store traffic

Complete support for all four architecture AltiVec DST streams

•

Level 1 (L1) Cache Structure

–

32K 32-byte line, 8-way set associative instruction cache (iL1)

32K 32-byte line, 8-way set associative data cache (dL1)

Single-cycle cache access

Pseudo least-recently-used (LRU) replacement

Data cache supports AltiVec LRU and transient instructions algorithm

Copy-back or write-through data cache (on a page-per-page basis)

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2141B–HIREL–01/03

–

Supports all PowerPC memory coherency modes

Non-blocking instruction and data cache

Separate copy of data cache tags for efficient snooping

No snooping of instruction cache except for ICBI instruction

•

Level 2 (L2) Cache Interface

–

Internal L2 cache controller and tags; external data SRAMs

512K, 1M and 2-Mbyte 2-way set associative L2 cache support

Copyback or write-through data cache (on a page basis or for all L2)

32-byte (512K), 64-byte (1M), or 128-byte (2M) sectored line size

Supports pipelined (register-register) synchronous burst SRAMs and

pipelined (register-register) late-write synchronous burst SRAMs

–

Supports direct mapped mode for 256K, 512K, 1M or 2 Mbytes of SRAM

(either all, half or none of L2 SRAM must be configured as direct mapped.

Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4

supported

–

64-bit data bus which also support 32-bits bus mode

Selectable interface voltages of 1.8V and 2.5V

•

Memory Management Unit

–

128 entry, 2-way set associative instruction TLB

128 entry, 2-way set associative data TLB

Hardware reload for TLBs

Four instruction BATs and four data BATs

Virtual memory support for up to four petabytes (2⁵²) of virtual memory

Real memory support for up to four gigabytes (2³²) of physical memory

Snooped and invalidated for TLBI instructions

•

Efficient Data Flow

–

All data buses between VRF, load/store unit, dL1, iL1, L2 and the bus are

128 bits wide

–

dL1 is fully pipelined to provide 128 bits per cycle to/from the VRF

L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s

Up to eight outstanding out-of-order cache misses between dL1 and L2/bus

Up to seven outstanding out-of-order transactions on the bus

Load folding to fold new dL1 misses into older outstanding load and store

misses to the same line

–

Store miss merging for multiple store misses to the same line. Only

coherency action taken (i.e., address only) for store misses merged to all 32

bytes of a cache line (no data tenure needed).

–

Two-entry finished store queue and four-entry completed store queue

between load/store unit and dL1

Separate additional queues for efficient buffering of outbound data (castouts,

write throughs, etc.) from dL1 and L2

•

Bus Interface

–

MPX bus extension to 60X processor interface

Mode-compatible with 60x processor interface

32-bit address bus

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2141B–HIREL–01/03

PC7410

–

64-bit data bus

Bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x,

6.5x, 7x, 7.5x, 8x, 9x supported

–

Selectable interface voltages of 1.8V, 2.5V and 3.3V

•

Power Management

–

Low-power design with thermal requirements very similar to PC740 and

PC750

–

Low voltage 1.8V or 1.5V processor core

Selectable interface voltages of 1.8V can reduce power in output buffers

Three static power saving modes: doze, nap, and sleep

Dynamic power management

•

Testability

–

LSSD scan design

IEEE 1149.1 JTAG interface

Array built-in self test (ABIST) – factory test only

Redundancy on L1 data arrays and L2 tag arrays

Reliability and Serviceability

Parity checking on 60x and L2 cache buses

–

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2141B–HIREL–01/03

Signal Description

Figure 2. PC7410 Microprocessor Signal Groups

L2OV_DD

GND

L2AV_DD

L2ADDR[0:18]

L2DATA[0:63]

L2DP[0:7]

BR

1

19

64

8

13

49

1

L2 Cache

Address/Data

Address

Arbitration

BG

ABB/AMON[0]

TS

1

Address

Start

L2CE

L2WE

1

A[0:31]

AP[0:3]

TT[0:4]

TBST

1

32

4

L2CLKOUTA,

L2CLKOUTB

Address

Bus

L2 Cache

Clock/Control

2

L2SYNC_OUT

L2SYNC_IN

L2ZZ

1

5

1

INT

TSIZ[0:2]

GBL

3

SMI

Transfer

Attribute

MCP

1

SRESET

HRESET

CKSTP_IN

CKSTP_OUT

HIT

WT

1

Interrupts

Reset

CI

PCX7410

1

CHK

1

AACK

1

Address

Termination

SHDO, SHD1

RSRV

2

1

4

1

5

3

ARTRY

DBG

1

TBEN

1

Processor

Status

Control

EMODE

QREQ

Data

Arbitration

DBWO, DTI(0)

DBB, DMON(0)

D[0:63]

DP[0:7]

DTI(2)

TA

1

QACK

1

DRDY

64

8

SYSCLK

PLL_CFG[0:3]

CLK_OUT

JTAG:COP

Factory Test

Data

Transfer

Clock

Control

1

Test Interface

LSSD_MODE

1

Data

Termination

DTI1

L1_TSTCLK,

L2_TSTCLK

1

BVSEL

TEA

I/O Voltage

Selection

1

L2VSEL

12

20

1

OV_DD

V_DD

AV_DD

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PC7410

2141B–HIREL–01/03

PC7410

Detailed Specification

Scope

This drawing describes the specific requirements for the microprocessor PC7410 in

compliance with Atmel-Grenoble standard screening.

Applicable

Documents

1. MIL-STD-883: Test methods and procedures for electronics

2. MIL-PRF-38535: Appendix A: General specifications for microcircuits

Requirements

General

The microcircuits are in accordance with the applicable documents and as specified

herein.

Design and Construction

Terminal Connections

Depending on the package, the terminal connections are as shown in Table 16, Table 4

and Figure 2.

Absolute Maximum

Ratings

Table 2. Absolute Maximum Ratings⁽¹⁾

Symbol

V_DD

Characteristic

Value

Unit

V

Core supply voltage

PLL supply voltage

L2 DLL supply voltage

60x bus supply voltage

L2 bus supply voltage

-0.3 to 2.1⁽⁴⁾

AV_DD

L2AV_DD

OV_DD

L2OV_DD

V_IN

-0.3 to 2.1⁽⁴⁾

V

-0.3 to 2.1⁽⁴⁾

V

-0.3 to 3.465⁽³⁾⁽⁶⁾

-0.3 to 2.6⁽³⁾

V

Processor bus input voltage

L2 bus input voltage

-0.3 to OVDD + 0,2V⁽²⁾⁽⁵⁾

-0.3 to L2OVDD + 0,2V⁽²⁾⁽⁵⁾

-0.3 to OVDD + 0,2V

-55 to 150

V

V_IN

V

JTAG signal input voltage

V_IN

V

T_STG

Storage temperature range

Rework temperature

°C

260

Notes: 1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only. Stresses

beyond those listed may affect device reliability or cause permanent damage to the device.

2. Caution: V_INmust not exceed OV_DDor L2OV_DDby more than 0.2V at any time including during power-on reset.

3. Caution: L2OV_DD/OV_DDmust not exceed V_DD/AV_DD/L2AV_DDby more than 2.0V at any time including during power-on reset;

this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

4. Caution: V_DD/AV_DD/L2AV_DDmust not exceed L2OV_DD/OV_DDby more than 0.4V at any time including during power-on reset;

this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

5. V_INmay overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 3.

6. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support 3.3V OV_DDand have a maximum value OV_DD

of -0.3 to 2.6V.

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2141B–HIREL–01/03

Figure 3. Overshoot/Undershoot Voltage

(L2)OV_DD+ 20%

(L2)OV_DD+ 5%

(L2)OV_DD

V_IH

V_IL

GND

GND - 0.3V

GND - 0.7V

Not to exceed

10% of t_SYSCLK

The PC7410 provides several I/O voltages to support both compatibility with existing

systems and migration to future systems. The PC7410 “core” voltage must always be

provided at nominal voltage (see Table 4 for actual recommended core voltage). Volt-

age to the L2 I/Os and processor interface I/Os are provided through separate sets of

supply pins and may be provided at the voltages shown in Table 3. The input voltage

threshold for each bus is selected by sampling the state of the voltage select pins at the

negation of the signal HRESET. The output voltage will swing from GND to the maxi-

mum voltage applied to the OV_DDor L2OV_DDpower pins.

Table 3. Input Threshold Voltage Setting

Processor Bus Input

BVSEL Signal Threshold is Relative to:

L2 Bus Input Threshold

is Relative to:

L2VSEL Signal

0⁽¹⁾

1.8V

0

1.8

HRESET⁽¹⁾⁽²⁾

1^(1)(4)(5)

2.5V

HRESET

1

2.5

3.3V⁽⁷⁾

2.5

HRESET⁽⁶⁾

HRESET

Not supported

Notes: 1. Caution: The input threshold selection must agree with the OV_DD/L2OV_DDvoltages

supplied.

2. To select the 2.5V threshold option, L2VSEL/BVSEL should be tied to HRESET so

that the two signals change state together. This is the preferred method for selecting

this mode operation.

3. Default voltage setting if left unconnected (internal pull-up).

4. Default voltage setting if left unconnected (internal pulled-up). PC7410RXnnnLE

(Rev 1.4) and later only. Previous revisions do not support 3.3V OV_DD, the default

voltage setting if left unconnected is 2.5V.

5. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support 3.3V

OV_DD, having BVSEL = 1 selects the 2.5V threshold.

6. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support BVSEL

= HRESET.

7. The XPC7410RXnnnNE does not support the default OV_DDsetting of 3.3V. The

BVSEL input must be tie either low or HRESET.

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PC7410

2141B–HIREL–01/03

PC7410

Recommended

Operating Conditions

Table 4. Recommended Operating Conditions⁽¹⁾

Recommended

Unit

Symbol

Characteristic

Value

V_DD

Core supply voltage

1.8 ± 100 mV

V

or 1.5 ± 50 mV

AV_DD

PLL supply voltage

1.8 ± 100 mV

or 1.5 ± 50 mV

V

L2AV_DD

L2 DLL supply voltage

1.8 ± 100 mV

or 1.5 ± 50 mV

OV_DD

Processor bus supply voltage see note ⁽³⁾

BVSEL = 0

1.8 ± 100 mV

2.5 ± 100 mV

3.3 ± 165 mV

1.8 ± 100 mV

2.5 ± 100 mV

GND to OV_DD

GND to L2OV_DD

GND to OV_DD

-55 to 125

V

BVSEL = HRESET

BVSEL = 1 or = HRESET

L2VSEL = 0

(2)(3)

OV_DD

L2OV_DD

V_IN

V

L2 bus supply voltage

Input voltage

V

L2VSEL = 1⁽²⁾or L2VSEL = HRESET

V

Processor bus

V

V_IN

L2 Bus

V

V_IN

JTAG Signals

V

T_j

Die-junction temperature

°C

Notes: 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not

guaranteed.

2. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support 3.3V OV_DDand have a recommended OV_DD

value of 2.5V ±100 mV for BVSEL = 1.

3. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support BVSEL = HRESET.

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2141B–HIREL–01/03

Thermal Characteristics

Package Characteristics

Table 5. Package Thermal Characteristics CBGA

Value

Symbol

R_θJA

Characteristic

PC7410 CBGA

Unit

°C/W

Junction-to-ambient thermal resistance, natural convection, single-layer (1s) board⁽¹⁾⁽²⁾

Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board⁽¹⁾⁽³⁾

Junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board⁽¹⁾⁽³⁾

Junction-to-ambient thermal resistance, 400 ft/min airflow, single-layer (1s) board

Junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board⁽¹⁾⁽³⁾

Junction-to-ambient thermal resistance, 400 ft/min airflow, four-layer (2s2p) board

Junction-to-board thermal resistance⁽⁴⁾

24

17

R_θJMA

R_θJB

18

16

14

°C/W

13

8

°C/W

R_θJC

Junction-to-case thermal resistance⁽⁵⁾

< 0.1

Notes: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) tempera-

ture, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1) with the calculated case temperature. The actual value of R_θJCfor the part is less than 0.1°C/W.

See “Thermal Management Information” on page 14 for more details about thermal management.

The board designer can choose between several commercially available heat sink types to place on the PC7410. For

exposed-die packaging technology as in Table 5, the intrinsic conduction thermal resistance paths are shown in Figure 4.

Package Thermal

Table 6 provides the package thermal characteristics for the PC7410, HiTCE.

Characteristics for HiTCE

Table 6. Package Thermal Characteristics for HiTCE Package

Value

Characteristic

Symbol

PC7410 HiTCE

Unit

Junction-to-bottom of balls⁽¹⁾

Rθ_J

TBD

°C/W

Note:

1. Simulation, no convection air flow.

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PC7410

2141B–HIREL–01/03

PC7410

Internal Package Conduction

Resistance

Figure 4 depicts the primary heat transfer path for a package with an attached heat sink

mounted on a printed circuit board.

Heat generated on the active side of the chip is conducted through the silicon, then

through the heat sink attach material (or thermal interface material) and finally to the

heat sink where it is removed by forced-air convection.

Since the silicon thermal resistance is quite small, for a first-order analysis the tempera-

ture drop in the silicon may be neglected. Thus, the heat sink attach material and the

heat sink conduction/convective thermal resistances are the dominant terms.

Figure 4. C4 Package with Heat Sink Mounted on a Printed Circuit Board

External Resistance

Radiation

Convection

Heat Sink

Thermal Interface Material

Die Junction

Die/Package

Package/Leads

Internal Resistance

Printed Circuit Board

Radiation

Convection

External Resistance

Thermal Management

Assistance

The PC7410 incorporates a thermal management assist unit (TAU) composed of a ther-

mal sensor, digital-to-analog converter, comparator, control logic and dedicated special-

purpose registers (SPRs). More information on the use of this feature is given in the

MPC RISC Microprocessor User’s Manual from Motorola.

Table 7. Thermal Sensor Specifications at V_DD= AV_DD= L2V_DD= 1.8V ± 100 mV or

1.5V ± 50mV, -55°C ≤ Tj ≤ 125°C

Characteristic

Min

0

Max

Unit

°C

Temperature range⁽¹⁾

Comparator settling time⁽²⁾

Resolution⁽³⁾

127

20

4

µs

°C

Accuracy

-12

+12

°C

Notes: 1. The temperature is the junction temperature of the die. The thermal assist unit’s raw

output does not indicate an absolute temperature, but it must be interpreted by soft-

ware to derive the absolute junction temperature. For information about the use and

calibration of the TAU, see Motorola application note, “Programming the Thermal

Assist Unit in the MPC750 Microprocessor”.

2. The comparator settling time value must be converted into the number of CPU clocks

that need to be written into the THRM3 SPR.

3. The resolution is guaranteed by design and characterization.

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Thermal Management

Information

This section provides thermal management information for the ceramic ball grid array

(CBGA) package for air-cooled applications. Proper thermal control design is primarily

dependent upon the system-level design – the heat sink, airflow and thermal interface

material. To reduce the die-junction temperature, heat sinks may be attached to the

package by several methods: adhesive, spring clip to holes in the printed-circuit board

or package and mounting clip and screw assembly; see Figure 5. This spring force

should not exceed 5.5 pounds of force. Ultimately, the final selection of an appropriate

heat sink depends on many factors such as thermal performance at a given air velocity,

spatial volume, mass, attachment method, assembly and cost.

Figure 5. CBGA Package Cross-section with Heat Sink Options

Heat Sink

Heat Sink Clip

Adhesive or

Thermal Interface Material

Option

Printed-Circuit Board

Adhesives and Thermal

Interface Materials

A thermal interface material is recommended at the package lid-to-heat sink interface to

minimize the thermal contact resistance. For those applications where the heat sink is

attached by spring clip mechanism, Figure 6 shows the thermal performance of three

thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint

and a joint with thermal grease as a function of contact pressure. As shown, the perfor-

mance of these thermal interface materials improves with increasing contact pressure.

The use of thermal grease significantly reduces the interface thermal resistance. That is,

the bare joint results in a thermal resistance approximately seven times greater than the

thermal grease joint.

Heat sinks are attached to the package by means of a spring clip to holes in the printed-

circuit board (see Figure 5). This spring force should not exceed 5.5 pounds of force.

Therefore, synthetic grease offers the best thermal performance, considering the low

interface pressure.

The board designer can choose between several types of thermal interface. Heat sink

adhesive materials should be selected based upon high conductivity, yet must have

adequate mechanical strength to meet equipment shock/vibration requirements.

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PC7410

2141B–HIREL–01/03

PC7410

Figure 6. Thermal Performance of Different Thermal Interface Materials

Silicone Sheet (0.006 inch)

Bare Joint

Floroether Oil Sheet (0.007 inch)

Graphite/Oil Sheet (0.005 inch)

Synthetic Grease

2

1.5

1

0.5

0

10

20

30

40

50

60

70

80

Contact Pressure (psi)

Heat Sink Selection Example

For preliminary heat sink sizing, the die-junction temperature can be expressed as

follows:

T_j= T_a+ T_r+ (θ_jc+ θ_int+ θ_sa) × P_d

where:

T_j= die-junction temperature

T_a= inlet cabinet ambient temperature

T_r= air temperature rise within the computer cabinet

θ_jc= junction-to-case thermal resistance

θ_int= adhesive or interface material thermal resistance

θ_sa= heat sink base-to-ambient thermal resistance

P_d= power dissipated by the device

During operation, the die-junction temperatures (T_j) should be maintained less than the

value specified in Table 4. The temperature of the air cooling the component greatly

depends upon the ambient inlet air temperature and the air temperature rise within the

electronic cabinet. An electronic cabinet inlet-air temperature (T_a) may range from 30°C

to 40°C. The air temperature rise within a cabinet (T_r) may be in the range of 5°C to

10°C. The thermal resistance of the thermal interface material (θ_int) is typically about

1°C/W. Assuming a T_aof 30°C, a T_rof 5°C, a CBGA package θ_jc= 0.03, and a power

consumption (P_d) of 5.0 watts, the following expression for T_jis obtained:

T_j= 30°C + 5°C + (0.03°C ⁄ W + 1.0°C ⁄ W + θ_sa) × 5W

15

2141B–HIREL–01/03

For a Thermally heat sink #2328B, the heat sink-to-ambient thermal resistance (θ_sa) ver-

sus airflow velocity is shown in Figure 7.

Figure 7. Thermalloy #2328B Heat Sink-to-ambient Thermal Resistance vs. Airflow

Velocity

8

Thermalloy #2328B Pin-fin Heat Sink

7

(25 x28 x 15 mm)

6

5

4

3

2

1

0

0.5

1

1.5

2

2.5

3

3.5

Approach Air Velocity (m/s)

Assuming an air velocity of 0.5 m/s, the effective R_sais 7°C/W, thus

T_j= 30°C + 5°C + (0.03°C ⁄ W + 1.0°C ⁄ W + 7°C ⁄ W) × 5W ,

resulting in a die-junction temperature of approximately 75°C which is well within the

maximum operating temperature of the component.

Other heat sinks offered by Chip Coolers, IERC, Thermalloy, Wakefield Engineering and

Aavid Engineering offer different heat sink-to-ambient thermal resistances and may or

may not need air flow.

Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances

are a common figure of merit used for comparing the thermal performance of various

microelectronic packaging technologies, one should exercise caution when only using

this metric in determining thermal management because no single parameter can ade-

quately describe three-dimensional heat flow. The final die-junction operating

temperature is not only a function of the component-level thermal resistance, but of the

system-level design and its operating conditions. In addition to the component's power

consumption, a number of factors affect the final operating die-junction temperature –

airflow, board population (local heat flux of adjacent components), heat sink efficiency,

heat sink attach, heat sink placement, next-level interconnect technology, system air

temperature rise, altitude, etc.

16

PC7410

2141B–HIREL–01/03

PC7410

Due to the complexity and the many variations of system-level boundary conditions for

today's microelectronic equipment, the combined effects of the heat transfer mecha-

nisms (radiation, convection and conduction) may vary widely. For these reasons, it is

recommended to use conjugate heat transfer models for the board, as well as system-

level designs.

To expedite system-level thermal analysis, several “compact” thermal-package models

are available within FLOTHERM^®. These are available upon request.

Power Consideration

Power Management

The PC7410 provides four power modes, selectable by setting the appropriate control

bits in the MSR and HIDO registers. The four power modes are:

•

Full-power: This is the default power state of the PC7410. The PC7410 is fully

powered and the internal functional units are operating at the full processor clock

speed. If the dynamic power management mode is enabled, functional units that are

idle will automatically enter a low-power state without affecting performance,

software execution or external hardware.

•

Doze: All the functional units of the PC7410 are disabled except for the time

base/decrementer registers and the bus snooping logic. When the processor is in

doze mode, an external asynchronous interrupt, a system management interrupt, a

decrementer exception, a hard or soft reset or machine check brings the PC7410

into the full-power state. The PC7410 in doze mode maintains the PLL in a fully

powered state and locked to the system external clock input (SYSCLK) so a

transition to the full-power state takes only a few processor clock cycles.

•

Nap: The nap mode further reduces power consumption by disabling bus snooping,

leaving only the time base register and the PLL in a powered state. The PC7410

returns to the full-power state upon receipt of an external asynchronous interrupt, a

system management interrupt, a decrementer exception, a hard or soft reset or a

machine check input (MCP). A return to full-power state from a nap state takes only

a few processor clock cycles. When the processor is in nap mode, if QACK is

negated, the processor is put in doze mode to support snooping.

Sleep: Sleep mode minimizes power consumption by disabling all internal functional

units, after which external system logic may disable the PLL and SYSCLK.

Returning the PC7410 to the full-power state requires the enabling of the PLL and

SYSCLK, followed by the assertion of an external asynchronous interrupt, a system

management interrupt, a hard or soft reset or a machine check input (MCP) signal

after the time required to relock the PLL.

17

2141B–HIREL–01/03

Power Dissipation

Table 8. Power Consumption for PC7410 (1.8V)

Processor (CPU) Frequency

400 MHz 450 MHz

1.5V 1.8V

Power Mode

Core power supply

Full-On Mode

Typical⁽¹⁾⁽³⁾

500 MHz

1.8 V

Unit

1.5V

1.8V

2.92

6.6

4.2

3.29

7.43

4.7

5.3

W

Maximum^(1)(2)(4)(5)

9.5

10.7

11.9

Doze Mode

Maximum^(1)(2)(5)

Nap Mode

3.6

1.35

1.3

4.3

4.1

1.5

4.8

1.5

5.3

1.65

1.6

W

Maximum^(1)(2)(5)

1.35

1.3

Sleep Mode

Maximum^(1)(2)(5)

1.45

Sleep Mode - PLL and DLL Disabled

Typical⁽¹⁾⁽³⁾

600

1.1

600

1.1

600

1.1

600

1.1

600

1.1

mW

W

Maximum^(1)(2)(5)

Notes: 1. These values apply for all valid processor bus and L2 bus ratios. The values do not

include I/O supply power (OV_DDand L2OV_DD) or PLL/DLL supply power (AV_DDand

L2AV_DD). OV_DDand L2OV_DDpower is system dependent, but is typically <10% of V_DD

power. Worst case power consumption for AV_DD= 15 mW and L2AV_DD= 15 mW.

2. Maximum power is measured at 105°C, at V_DD= 1.8V or 1.5Vwhile running an

entirely cache-resident, contrived sequence of instructions which keep the execution

units, including AltiVec, maximally busy.

3. Typical power is an average value measured at 65°C, V_DD= 1.8V or 1.5V,

OV_DD= L2OV_DD= 2.5V in a system while running a codec application that is AltiVec

intensive.

4. These values include the use of AltiVec. Without AltiVec operation, estimate a 25%

decrease.

5. Power consumption derating at low temperatures to be defined after device

characterization.

18

PC7410

2141B–HIREL–01/03

PC7410

Electrical

Characteristics

Static Characteristics

Table 9. DC Electrical Specifications (see Table 4 for Recommended Operating Conditions)

NominalBus

Symbol

V_IH

Characteristic

Voltage⁽¹⁾

1.8

2.5

3.3

1.8

2.5

3.3

1.8

2.5

3.3

1.8

2.5

3.3

1.8

2.5

3.3

1.8

2.5

3.3

1.8

2.5

3.3

1.8

2.5

3.3

Min

Max

Unit

Input high voltage

0.65 x (L2)OV_DD

(L2)OV_DD+ 0.2

V

(all inputs except SYSCLK)^(2)(3)(8)

V_IH

1.7

(L2)OV_DD+ 0.2

V_IH

2.0

OV_DD+ 0.3

V_IL

Input low voltage

-0.3

0.35 x (L2)OV_DD

V

(all inputs except SYSCLK)⁽⁸⁾

V_IL

-0.3

0.2 x (L2)OV_DD

V_IL

-0.3

0.8

CV_IH

CV_IL

I_IN

SYSCLK input high voltage⁽²⁾⁽⁸⁾

SYSCLK input low voltage⁽⁸⁾

Input leakage current,

1.5

OV_DD+ 0.2

2.0

OV_DD+ 0.2

2.4

OV_DD+ 0.3

-0.3

0.2

0.4

20

35

70

20

35

70

–

V

-0.3

–

µA

V

(2)(3)(6)(7)

V_IN= L2OV_DD/OV_DD

I_IN

–

I_IN

–

High-Z (off-state) leakage current,

I_TSI

–

(2)(3)(5)(7)

V_IN= L2OV_DD/OV_DD

I_TSI

–

I_TSI

–

Output high voltage, I_OH= -6 mA⁽⁸⁾

V_OH

V_OL

C_IN

(L2)OV_DD- 0.45

1.7

2.4

–

Output low voltage, I_OL= 6 mA⁽⁸⁾

0.45

0.4

6.0

V

–

Capacitance, V_IN= 0V, f = 1 MHz^(3)(4)(7)

–

pF

Notes: 1. Nominal voltages; see Table 4 for recommended operating conditions.

2. For processor bus signals, the reference is OV_DDwhile L2OV_DDis the reference for the L2 bus signals.

3. Excludes factory test signals.

4. Capacitance is periodically sampled rather than 100% tested.

5. The leakage is measured for nominal OV_DDand L2OV_DD, or both OV_DDand L2OV_DDmust vary in the same direction (for

example, both OV_DDand L2OV_DDvary by either +5% or –5%).

6. Measured at max OV_DD/L2OV_DD

7. Excludes IEEE 1149.1 boundary scan (JTAG) signals.

19

2141B–HIREL–01/03

8. For JTAG support: all signals controlled by BVSEL and L2VSEL will see V_IL/V_IH/V_OL/V_OH/CV_IH/CV_ILDC limits of 1.8V mode

while either the EXTEST or CLAMP instruction is loaded into the IEEE 1149.1 instruction register by the UpdateIR TAP state

until a different instruction is loaded into the instruction register by either another UpdateIR or a Test-Logic-Reset TAP state.

If only TSRT is asserted to the part, and then a SAMPLE instruction is executed, there is no way to control or predict what

the DC voltage limits are. If HRESET is asserted before executing a SAMPLE instruction, the DC voltage limits will be con-

trolled by the BVSEL/L2VSEL settings during HRESET. Anytime HRESET is not asserted (i.e., just asserting TRST), the

voltage mode is not known until either EXTEST or CLAMP is executed, at which time the voltage level will be at the DC lim-

its of 1.8V.

Dynamic Characteristics After fabrication, parts are sorted by maximum processor core frequency as shown in

“Clock AC Specifications” and tested for conformance to the AC specifications for that

frequency. These specifications are for valid processor core frequencies. The processor

core frequency is determined by the bus (SYSCLK) frequency and the settings of the

PLL_CFG[0:3] signals. Parts are sold by maximum processor core frequency.

Clock AC Specifications

Table 10 provides the clock AC timing specifications as defined in Figure 8.

Table 10. Clock AC Timing Specifications (See Table 4 for Recommended Operating Conditions)

Maximum Processor Core Frequency

400 MHz

450 MHz

500 MHz

Symbol

Characteristic

Min

Max

400

800

133

30

Min

Max

450

900

133

30

Min

Max

500

1000

133

30

Unit

MHz

ns

(1)

f_CORE

Processor frequency

VCO frequency

350

700

33

350

700

33

350

700

33

(1)

f_VCO

(1)

f_SYSCLK

t_SYSCLK

SYSCLK frequency

SYSCLK cycle time

SYSCLK rise and fall time

7.5

(2)

(3)

t

_KR& t_KF

1.0

1

ns

0.5

ns

(4)

_KHKL/t_SYSCLK

SYSCLK duty cycle measured at OV_DD/2

SYSCLK jitter⁽⁵⁾

40

60

40

60

40

60

%

±150

100

±150

100

±150

100

ps

Internal PLL relock time⁽⁶⁾

µs

Notes: 1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus) fre-

quency, CPU (core) frequency and PLL (VCO) frequency do not exceed their respective maximum or minimum operating

frequencies. Refer to the PLL_CFG[0:3] signal description in “Clock Selection” on page 40 for valid PLL_CFG[0:3] settings

2. Rise and fall times for the SYSCLK input measured from 0.4V to 2.4V when OV_DD= 3.3V nominal.

3. Rise and fall times for the SYSCLK input measured from 0.2V to 1.2V when OV_DD= 1.8V or 2.5V nominal.

4. Timing is guaranteed by design and characterization.

5. This represents total input jitter, short-term and long-term combined, and is guaranteed by design.

6. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for

PLL lock after a stable V_DDand SYSCLK are reached during the power-on reset sequence. This specification also applies

when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held

asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.

20

PC7410

2141B–HIREL–01/03

PC7410

Figure 8. SYSCLK Input Timing Diagram

t_KR

t_KF

t_SYSCLK

t_KHKL

CVIH

CVIL

SYSCLK

VM

Note:

VM = Midpoint Voltage (OV_DD/2)

Processor Bus AC

Specifications

Table 11 provides the processor AC timing specifications for the PC7410 as defined in

Figure 10 and Figure 11. Timing specifications for the L2 bus are provided in “L2 Bus

AC Specifications” on page 27.

Table 11. Processor Bus AC Timing Specifications⁽¹⁾at V_DD= AV_DD= 1.8V ± 100 mV;

-55°C ≤ T_j≤ 125°C, OV_DD= 1.8V ± 100 mV

400, 450, 500 MHz

Symbol⁽²⁾

Parameter

Min

8

Max

Unit

t_SYSCLK

ns

(3)(4)(5)(6)

t_MVRH

t_MXRH

t_IVKH

Mode select input setup to HRESET

HRESET to mode select input hold

Input Setup

(2)(3)(5)

0

1.0

0

ns

t_IXKH

Input Hold

ns

Output Valid Times:⁽⁷⁾⁽⁸⁾

TS

ns

t_KHTSV

t_KHARV

t_KHOV

3.0

2.3

3.0

ARTRY/SHD0/SHD1

All Other Outputs

Output Hold Times:^(7)(12)

TS

ns

t_KHTSX

t_KHARX

t_KHOX

0.5

ARTRY/SHD0/SHD1

All Other Outputs

(11)

t_KHOE

t_KHOZ

SYSCLK to Output Enable

0.5

ns

SYSCLK to Output High Impedance (all except ABB/AMON[0], ARTRY/SHD,

DBB/DMON[0]), SHD0, SHD1)

3.5

(5)(9)(11)

t_KHABPZ

SYSCLK to ABB/AMON[0], DBB/DMON[0] High Impedance after precharge

Maximum Delay to ARTRY/SHD0/SHD1 Precharge

1.0

1

t_SYSCLK

(5)(10)(11)

t_KHARP

t_KHARPZ

SYSCLK to ARTRY/SHD0/SHD1 High Impedance After Precharge

2

Notes: 1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input

SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the sig-

nal in question. All output timings assume a purely resistive 50 Ω load (see Figure 10). Input and output timings are

measured at the pin; time-of-flight delays must be added for trace lengths, vias and connectors in the system.

2. The symbology used for timing specifications herein follows the pattern of

t_{(signal)(state)(reference)(state)}for inputs and t_{(reference)(state)(signal)(state)}for outputs. For example, t_IVKHsymbolizes the time input sig-

nals (I) reach the valid state (V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And

t_KHOVsymbolizes the time from SYSCLK (K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time

can be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) - note the position

of the reference and its state for inputs -and output hold time can be read as the time from the rising edge (KH) until the out-

put went invalid (OX).

3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 11).

21

2141B–HIREL–01/03

4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of

255 bus clocks after the PLL re-lock time during the power-on reset sequence.

5. t_SYSCLKis the period of the external clock (SYSCLK) in nanoseconds(ns). The numbers given in the table must be multiplied

by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.

6. Mode select signals are BVSEL, EMODE, L2VSEL, PLL_CFG[0:3]

7. All other output signals are composed of the following - A[0:31], AP[0:3], TT[0:4], TBST, TSIZ[0:2], GBL, WT, CI, DH[0:31],

DL[0:31], DP[0:7], BR, CKSTP_OUT, DRDY, HIT, QREQ, RSRV.

8. Output valid time is measured from 2.4V to 0.8V which may be longer than the time required to discharge from Vdd to 0.8V.

9. According to the 60x bus protocol, ABB and DBB are driven only by the currently active bus master. They are asserted low

then precharged high before returning to high-Z as shown in Figure 9. The nominal precharge width for ABB or DBB is 0.5 x

t_SYSCLK, i.e., less than the minimum t_SYSCLKperiod, to ensure that another master asserting ABB, or DBB on the following

clock will not contend with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid

time is tested for precharge.The high-Z behavior is guaranteed by design.

10. According to the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately fol-

lowing AACK. Bus contention is not an issue since any master asserting ARTRY will be driving it low. Any master asserting

it low in the first clock following AACK will then go to high-Z for one clock before precharging it high during the second cycle

after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 t_SYSCLK; i.e., it should be high-Z as shown in

Figure 9 before the first opportunity for another master to assert ARTRY. Output valid and output hold timing are tested for

the signal asserted. Output valid time is tested for precharge. The high-Z behavior is guaranteed by design.

11. Guaranteed by design and not tested.

12. Output hold time characteristics can be altered by the use of the L2_TSTCK pin during system reset, similar to L2 output

hold being altered by the use of bits [14-15] in the L2CR register. Information on the operation of the L2_TSTCLK will be

included in future revisions of this specification.

22

PC7410

2141B–HIREL–01/03

PC7410

Figure 9. Input/Output Timing Diagram

VM

SYSCLK

t_IVKH

t_IXKH

All Inputs

t_KHOX

t_KHOV

All Outputs

(except TS, ABB,

ARTRY, DBB)

t_KHOE

t_KHOZ

All Outputs

(except TS, ABB,

ARTRY, DBB)

t_KHABPZ

t_KHTSV

t_KHTSX

TS,

t_KHTSV

ABB/AMON[0],

DBB/DMON[0]

t_KHARPZ

t_KHARP

t_KHARX

t_KHARV

ARTRY,

t_KHARV

SHD0,

SHD1

VM = Midpont Voltage (OVDD/2)

Figure 10. AC Test Load for the 60x Interface

Output

Z0 = 50Ω

RL = 50Ω

OV_DD/2

Figure 11. Mode Input Timing Diagram

VM

HRESET

t_MVRH

t_MXRH

MODE SIGNALS

where VM = Midpoint Voltage (OV_DD/2)

23

2141B–HIREL–01/03

L2 Clock AC Specifications

The L2CLK frequency is programmed by the L2 configuration register (L2CR[4:6]) core-

to-L2 divisor ratio. See Table 18 for example core and L2 frequencies at various divi-

sors. Table 12 provides the potential range of L2CLK output AC timing specifications as

defined in Figure 12.

The L2SYNC_OUT signal is intended to be routed halfway out to the SRAMs and then

returned to the L2SYNC_IN input of the PC7410 to synchronize L2CLKOUT at the

SRAM with the processor’s internal clock. L2CLKOUT at the SRAM can be offset for-

ward or backward in time by shortening or lengthening the routing of L2SYNC_OUT to

L2SYNC_IN. See Motorola Application Note AN179/D "PowerPC Backside L2 Timing

Analysis for the PCB Design Engineer."

The minimum L2CLK frequency of Table 12 is specified by the maximum delay of the

internal DLL. The variable-tap DLL introduces up to a full clock period delay in the

L2CLKOUTA, L2CLKOUTB and L2SYNC_OUT signals so that the returning

L2SYNC_IN signal is phase aligned with the next core clock (divided by the L2 divisor

ratio). Do not choose a core-to-L2 divisor which results in an L2 frequency below this

minimum, or the L2CLKOUT signals provided for SRAM clocking will not be phase

aligned with the PC7410 core clock at the SRAMs.

The maximum L2CLK frequency shown in Table 12 is the core frequency divided by

one. Very few L2 SRAM designs will be able to operate in this mode. Most designs will

select a greater core-to-L2 divisor to provide a longer L2CLK period for read and write

access to the L2 SRAMs. The maximum L2CLK frequency for any application of the

PC7410 will be a function of the AC timings of the PC7410, the AC timings for the

SRAM, bus loading and printed circuit board trace length.

Atmel is similarly limited by system constraints and cannot perform tests of the L2 inter-

face on a socketed part on a functional tester at the maximum frequencies of Table 12.

Therefore, functional operation and AC timing information are tested at core-to-L2 divi-

sors of 2 or greater.

L2 input and output signals are latched or enabled respectively by the internal L2CLK

(which is SYSCLK multiplied up to the core frequency and divided down to the L2CLK

frequency). In other words, the AC timings of Table 13 are entirely independent of

L2SYNC_IN. In a closed loop system, where L2SYNC_IN is driven through the board

trace by L2SYNC_OUT, L2SYNC_IN only controls the output phase of L2CLKOUTA

and L2CLKOUTB which are used to latch or enable data at the SRAMs. However, since

in a closed loop system L2SYNC_IN is held in phase alignment with the internal L2CLK,

the signals of Table 13 are referenced to this signal rather than the not-externally-visible

internal L2CLK. During manufacturing test, these times are actually measured relative to

SYSCLK.

24

PC7410

2141B–HIREL–01/03

PC7410

Table 12. L2CLK Output AC Timing Specifications at Recommended Operating Conditions (See Table 4)

400 MHz 450 MHz 500 MHz

Min Min Min Max

Symbol

Parameter

Max

400

7.5

Max

400

7.5

Unit

MHz

ns

(1)(4)

f_L2CLK

t_L2CLK

_CHCL/t_L2CLK

L2CLK frequency

L2CLK cycle time

L2CLK duty cycle

Internal DLL-relock time⁽³⁾

DLL capture window⁽⁵⁾

133

2.5

133

2.5

133

2.5

400

7.5

(2)

t

50

%

640

-

L2CLK

ns

0

-

10

50

0

-

10

50

0

-

10

50

t_L2CSKW

L2CLKOUT output-to-output

skew⁽⁶⁾

ps

L2CLKOUT output jitter⁽⁶⁾

-

±150

-

±150

-

±150

ps

Notes: 1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, and L2SYNC_OUT pins. The L2CLK frequency to core frequency set-

tings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective maximum

or minimum operating frequencies. The maximum L2LCK frequency will be system-dependent. L2CLK_OUTA and

L2CLK_OUTB must have equal loading.

2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.

3. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to

compute the actual time duration in nanoseconds. Re-lock timing is guaranteed by design and characterization.

4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. This adds more delay to each tap of the DLL.

5. Allowable skew between L2SYNC_OUT and L2SYNC_IN.

6. Guaranteed by design and not tested. This output jitter number represents the maximum delay of one tap forward or one tap

back from the current DLL tap as the phase comparator seeks to minimize the phase difference between L2SYNC_IN and

the internal L2CLK. This number must be comprehended in the L2 timing analysis. The input jitter on SYSCLK affects

L2CLKOUT and the L2 address/data/control signals equally and therefore is already comprehended in the AC timing and

does not have to be considered in the L2 timing analysis.

25

2141B–HIREL–01/03

Figure 12. L2CLK_OUT Output Timing Diagram

L2 Single-Ended Clock Mode

t_L2CLK

t_CHCL

t_L2CR

t_L2CF

L2CLK_OUTA

L2CLK_OUTB

L2SYNC_OUT

VM

t_L2CSKW

VM

L2 Differential Clock Mode

t_L2CLK

t_CHCL

L2CLK_OUTB

L2CLK_OUTA

VM

L2SYNC_OUT

Note:

VM = Midpoint Voltage (L2OV_DD/2)

26

PC7410

2141B–HIREL–01/03

PC7410

L2 Bus AC Specifications

Table 13 provides the L2 bus interface AC timing specifications for the PC7410 as

defined in Figure 13 and Figure 14 for the loading conditions described in Figure 15.

Table 13. L2 Bus Interface AC Timing Specifications at V_DD= AV_DD= L2AV_DD= 1.8V ± 100mV or 1.5V ± 50mV ;

-55°C ≤ T_j≤ 125°C, L2OV_DD= 2.5V ± 100mV or L2OV_DD= 1.8V ± 100mV

400, 450, 500 MHz

Symbol

Parameter

Min

Max

Unit

ns

(1)

t

_L2CR& t_L2CF

L2SYNC_IN rise and fall time

1.0

Setup Times

ns

(2)

t_DVL2CH

Data and parity

1.5

Input Hold Times

Data and parity

ns

(2)

t_DXL2CH

0.0

(3)(4)

t_L2CHOV

Valid Times

All outputs when L2CR[14:15] = 00

All outputs when L2CR[14:15] = 01

All outputs when L2CR[14:15] = 10

All outputs when L2CR[14:15] = 11

2.5

2.9

3.5

(3)

t_L2CHOX

Output Hold Times

ns

All outputs when L2CR[14:15] = 00

All outputs when L2CR[14:15] = 01

All outputs when L2CR[14:15] = 10

All outputs when L2CR[14:15] = 11

0.4

0.8

1.2

1.6

t_L2CHOZ

L2SYNC_IN to high impedance

All outputs when L2CR[14:15] = 00

All outputs when L2CR[14:15] = 01

All outputs when L2CR[14:15] = 10

All outputs when L2CR[14:15] = 11

2.0

2.5

3.0

3.5

Notes: 1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OV_DD

.

2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of

the input L2SYNC_IN (see Figure 13). Input timings are measured at the pins.

3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint of the sig-

nal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50 Ω load (see

Figure 15).

4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous burst

RAMs, L2CR[14:15] = 00 is recommended. For pipelined late-write synchronous burst SRAMs, L2CR[14:15] = 10 is

recommended.

Figure 13. L2 Bus Input Timing Diagram

t_L2CR

t_L2CF

VM

L2SYNC_IN

t_DVL2CH

t_DXL2CH

L2 Data and Data

Parity Inputs

Note:

VM = Midpoint Voltage (L2OV_DD/2)

27

2141B–HIREL–01/03

Figure 14. L2 Bus Output Timing Diagram

VM

L2SYNC_IN

t_L2CHOV

t_L2CHOX

All Outputs

t_L2CHOZ

L2DATA BUS

Note:

VM = Midpoint Voltage (L2OV_DD/2)

Figure 15. AC Test Load for the L2 Interface

Output

Z0 = 50Ω

L2OV_DD/2

RL = 50Ω

28

PC7410

2141B–HIREL–01/03

PC7410

IEEE 1149.1 AC Timing

Specifications

Table 14 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure

16, Figure 17, Figure 18 and Figure 19.

Table 14. JTAG AC Timing Specifications (Independent of SYSCLK) ⁽¹⁾at Recom-

mended Operating Conditions (see Table 4)

Symbol

f_TCLK

Parameter

Min

0

Max

Unit

MHz

ns

TCK frequency of operation

TCK cycle time

33.3

t _TCLK

t_JHJL

30

15

0

TCK clock pulse width measured at OVDD/2

TCK rise and fall times

TRST assert time

ns

t

_JR& t_JF

2

ns

(2)

t_TRST

25

ns

Input Setup Times:

Boundary-scan data

TMS, TDI

ns

(3)

t_DVJH

t_IVJH

4

0

Input Hold Times:

Boundary-scan data

TMS, TDI

ns

t_DXJH

t_IXJH

20

25

Valid Times:

Boundary-scan data

TDO

(4)

t_JLDV

t_JLOV

4

20

25

TCK to output high impedance:

Boundary-scan data

TDO

(4)(5)

(5)

t_JLDZ

t_JLOZ

3

19

9

Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK

to the midpoint of the signal in question. The output timings are measured at the pins.

All output timings assume a purely resistive 50 Ω load (see Figure 16). Time-of-flight

delays must be added for trace lengths, vias and connectors in the system.

2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes

only.

3. Non-JTAG signal input timing with respect to TCK.

4. Non-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization

Figure 16. Alternate AC Test Load for the JTAG Interface

Output

Z0 = 50Ω

OV_DD/2

RL = 50Ω

Figure 17. JTAG Clock Input Timing Diagram

t_JR

t_JF

VM

TCLK

t_JHJL

t_TCLK

Note:

VM = Midpoint Voltage (OV_DD/2)

29

2141B–HIREL–01/03

Figure 18. TRST Timing Diagram

t_TRST

VM

TRST

Note:

VM = Midpoint Voltage (OV_DD/2)

Figure 19. Boundary-scan Timing Diagram

TCK

VM

t_DVJH

Boundary

t_DXJH

Data Inputs

Input Data

Valid

t_JLDV

t_JLDX

Boundary

Data Outputs

Output Data Valid

t_JLDZ

Output Data Valid

Boundary

Data Outputs

Note:

VM = Midpoint Voltage (OV_DD/2)

Figure 20. Test Access Port Timing Diagram

VM

TCK

t_IVJH

t_IXJH

TDI, TMS

Input Data

Valid

t_JLOV

t_JLOX

Output Data Valid

TDO

t_JLOZ

Output Data Valid

TDO

Note:

VM = Midpoint Voltage (OV_DD/2)

30

PC7410

2141B–HIREL–01/03

PC7410

Preparation for

Delivery

Handling

MOS devices must be handled with certain precautions to avoid damage due to accu-

mulation of static charge. Input protection devices have been designed in the chip to

minimize the effect of static buildup. However, the following handling practices are

recommended:

•

Devices should be handled on benches with conductive and grounded surfaces.

Ground test equipment, tools and operator.

Do not handle devices by the leads.

Store devices in conductive foam or carriers.

Avoid use of plastic, rubber or silk in MOS areas.

Maintain relative humidity above 50% if practical.

For CI-CGA packages, use specific tray to take care of the highest height of the

package compared with the normal CBGA.

Package Mechanical Data

Parameters

The package parameters are as provided in the following list. The package type is

25x25 mm, 360-lead CBGA, HiTCE and CI-CGA.

Table 15. Package Parameters

Parameter

Package outline

25 mm x 25 mm

Interconnects

360 (19 x 19 ball array minus one)

1.27 mm (50 mil)

Pitch

Minimum module height

Maximum module height

Ball or column diameter

2.65 mm (CBGA, HiTCE), 3.65 mm (CI-CGA)

3.20 mm (CBGA), 3.24 mm (HiTCE), 4.20 mm (CI-CGA)

0.89 mm (35 mil)

The following remarks apply to Figure 26 and Figure 27:

•

Dimensions and tolerancing are as per ASME Y14.5M-1994.

All dimensions are in millimeters.

Top side A1 corner index is a metallized feature with various shapes. Bottom side

A1 corner is designated with a ball missing from the array.

•

Dimension B is the maximum solder ball diameter measured parallel to datum A.

D2 and E2 define the area occupied by the die and underfill. Actual size of this area

may be smaller than shown. D3 and E3 are the minimum clearance from the

package edge to the chip capacitors.

31

2141B–HIREL–01/03

Pin Assignment

BGA360 Package

Figure 21, Figure 22, Figure 23 and Figure 24 show top views of the packages available

for the PC7410. Note that these drawings are not to scale.

Figure 21. Top View of 360-Ball CBGA and 360-Pin CI-CGA Packages

Pin A1 Index

Figure 22. Top View of 360-pin CBGA and CI-CGA Packages

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

32

PC7410

2141B–HIREL–01/03

PC7410

Figure 23. Cross-section of 360-ball CBGA and HiTCE Package

View

Substrate Assembly

Die

Encapsulant

Figure 24. Cross-section of 360-column CI-CGA Package

View

Substrate Assembly

Die

Encapsulant

Table 16. Pinout Listing for the PC7410, 360-ball CBGA and CI-CGA packages

Signal Name

Pin Number

Active

I/O

I/F Select⁽¹⁾

A[0:31]

A13, D2, H11, C1, B13, F2, C13, E5, D13, G7, F12, G3, G6,

H2, E2, L3, G5, L4, G4, J4, H7, E1, G2, F3, J7, M3, H3, J2,

J6, K3, K2, L2

High

I/O

BVSEL

AACK

N3

L7

Low

Input

BVSEL

ABB⁽¹²⁾

AMON[0]⁽¹²⁾

Output

AP[0:3]

C4, C5, C6, C7

High

Low

I/O

BVSEL

Vdd

ARTRY

AV_DD

L6

A8

H1

E7

W1

K11

C2

B8

D7

E3

K5

BG

Low

High

Low

High

Low

Input

Output

Input

BVSEL

N/A

BR

BVSEL^{(1)(3)(8)(9)(14)}

CHK^(4)(8)(9)

CI

Input

BVSEL

I/O

CKSTP_IN

CKSTP_OUT

CLK_OUT

Input

Output

DBB⁽¹²⁾

DMON[0]⁽¹²⁾

DBG

K1

Low

Input

BVSEL

33

2141B–HIREL–01/03

Table 16. Pinout Listing for the PC7410, 360-ball CBGA and CI-CGA packages (Continued)

Signal Name

Pin Number

Active

I/O

I/F Select⁽¹⁾

DH[0:31]

W12, W11, V11, T9, W10, U9, U10, M11, M9, P8, W7, P9,

W9, R10, W6, V7, V6, U8, V9, T7, U7, R7, U6, W5, U5, W4,

P7, V5, V4, W3, U4, R5

High

I/O

BVSEL

DL[0:31]

M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11, V13, U12,

P12, T13, W13, U13, V10, W8, T11, U11, V12, V8, T1, P1,

V1, U1, N1, R2, V3, U3, W2

High

I/O

BVSEL

DP[0:7]

L1, P2, M2, V2, M1, N2, T3, R1

High

Low

I/O

BVSEL

DRDY^(6)(8)(13)

K9

D1

Output

Input

DBWO

DTI[0]

DTI[1:2]^(10)(13)

EMODE^(7)(10)

GBL

H6, G1

A3

High

Low

Input

I/O

BVSEL

N/A

B1

GND

D10, D14, D16, D4, D6, E12, E8, F4, F6, F10, F14, F16, G9,

G11, H5, H8, H10, H12, H15, J9, J11, K4, K6, K8, K10, K12,

K14, K16, L9, L11, M5, M8, M10, M12, M15, N9, N11, P4,

P6, P10, P14, P16, R8, R12, T4, T6, T10, T14, T16

HIT⁽⁶⁾⁽⁸⁾

B5

Low

High

Output

Input

BVSEL

L2VSEL

HRESET

B6

INT

C11

F8

Input

L1_TSTCLK⁽²⁾

L2ADDR[0:16]

Input

L17, L18, L19, M19, K18, K17, K15, J19, J18, J17, J16, H18,

H17, J14, J13, H19, G18

Output

L2ADDR[17:18]⁽⁸⁾

L2AV_DD

K19, W19

L13

High

Output

L2VSEL

Vdd

L2CE

P17

Low

High

Output

I/O

L2VSEL

L2CLKOUTA

L2CLKOUTB

L2DATA[0:63]

N15

L16

U14, R13, W14, W15, V15, U15, W16, V16, W17, V17, U17,

W18, V18, U18, V19, U19, T18, T17, R19, R18, R17, R15,

P19, P18, P13, N14, N13, N19, N17, M17, M13, M18, H13,

G19, G16, G15, G14, G13, F19, F18, F13, E19, E18, E17,

E15, D19, D18, D17, C18, C17, B19, B18, B17, A18, A17,

A16, B16, C16, A14, A15, C15, B14, C14, E13

L2DP[0:7]

V14, U16, T19, N18, H14, F17, C19, B15

High

I/O

L2VSEL

N/A

(11)

L2OV_DD

D15, E14, E16, H16, J15, L15, M16, K13, P15, R14, R16,

T15, F15

L2SYNC_IN

L14

M14

F7

High

Input

Output

Input

L2VSEL

BVSEL

N/A

L2SYNC_OUT

L2_TSTCLK⁽²⁾

L2VSEL^{(1)(3)(8)(9)(14)}

A19

Input

34

PC7410

2141B–HIREL–01/03

PC7410

Table 16. Pinout Listing for the PC7410, 360-ball CBGA and CI-CGA packages (Continued)

Signal Name

L2WE

Pin Number

Active

Low

I/O

I/F Select⁽¹⁾

L2VSEL

BVSEL

N/A

N16

G17

F9

Output

Input

L2ZZ

High

Low

LSSD_MODE⁽²⁾

MCP

B11

Low

Input

OV_DD

D5, D8, D12, E4, E6, E9, E11, F5, H4, J5, L5, M4, P5, R4,

R6, R9, R11, T5, T8, T12

PLL_CFG[0:3]

QACK

QREQ

RSRV

SHD0⁽⁸⁾

SHD1⁽⁵⁾⁽⁸⁾

SMI

A4, A5, A6, A7

High

Low

Input

Output

I/O

BVSEL

N/A

B2

J3

D3

B3

B4

I/O

A12

Input

Output

Input

Output

Input

I/O

SRESET

SYSCLK

TA

E10

H9

F1

Low

High

Low

High

Low

High

Low

High

Low

TBEN

TBST

A2

A11

TCK

B10

TDI⁽⁹⁾

B7

TDO

D9

TEA

J1

TMS⁽⁹⁾

TRST^(9)(14)

TS

C8

A10

K7

TSIZ[0:2]

TT[0:4]

WT

A9, B9, C9

Output

I/O

C10, D11, B12, C12, F11

C3

I/O

V_DD

G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12

Notes: 1. OV_DDsupplies power to the processor bus, JTAG and all control signals except the L2 cache controls (L2CE, L2WE, and

L2ZZ); L2OV_DDsupplies power to the L2 cache interface (L2ADDR[0:18], L2ASPARE, L2DATA[0:63], L2DP[0:7] and

L2SYNC_OUT) and the L2 control signals and V_DDsupplies power to the processor core and the PLL and DLL (after filtering

to become AV_DDand L2AV_DDrespectively). These columns serve as a reference for the nominal voltage supported on a

given signal as selected by the BVSEL/L2VSEL pin configurations of Table 3 and the voltage supplied. For actual recom-

mended value of V_INor supply voltages, see Table 4.

2. These are test signals for factory use only and must be pulled up to OV_DDfor normal machine operation.

3. To allow for future I/O voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OV_DD

(selects 2.5V), GND (selects 1.8V), or to HRESET (selects 2.5V). The PC7410 Both the 60x processor bus and the L2 bus

only support the 1.8 and 2.5 options (see Table 3). the default selection if BVSEL and/or L2VSEL is left unconnected is 2.5V

4. Connect to HRESET to trigger post power-on-reset (por) internal memory test.

35

2141B–HIREL–01/03

5. Ignored in 60x bus mode.

6. Unused output in 60x bus mode.

7. Deasserted (pulled high) at HRESET for 60x bus mode.

8. Uses one of 9 existing no-connects in PC750’s 360-ball BGA package.

9. Internal pull-up on die.

10. Reuses PC750’s DRTRY, DBDIS and TLBISYNC pins (DTI1, DTI2 and EMODE respectively).

11. The VOLTDET pin position on the PC750 360-ball CBGA package is now an L2OV_DDpin on the PC7410 packages.

12. Output only for PC7410, was I/O for PC750.

13. Enhanced mode only.

14. To overcome the internal pull-up resistance and ensure this input will recognize a low signal, a pull-down resistance less

than 250Ω should be used.

36

PC7410

2141B–HIREL–01/03

PC7410

Figure 25. Mechanical Dimensions and Bottom Surface Nomenclature of the 360-ball CBGA Package

2X

0.2

B

2X

150 µm

D

PIN A1

INDEX

A

360 X

0.15

A

2

1

C6

A3

A4

C5

C1

0.35

A

1

2

1

E

E2

E4

C4

C2

1

2X

C3

2

0.2

C

D4

D2

D3

E

3

TOP VIEW

D1

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19

W

V

U

T

R

P

N

M

L

K

J

A2

A1

A

E1

H

G

F

K

E

D

C

B

A

K

GND : C1.2 C2.2 C3.2 C4.2 C5.2 C6.2

C1.1, C2.1 : L2OVDD

G

0.3

T

E F

B

360X

C3.1, C6.1 : OVDD

T

0.15

C4.1, C5.1 : OVDD

BOTTOM VIEW

Parameter

Min

2.62

0.8

Max

3.20

1.00

1.30

0.6

Parameter

Min

Max

A

D3

D4

E

2.75

–

A1

A2

A3

A4

B

6.32

1.10

–

25.00 BASIC

22.86 BASIC

12.6 typ

E1

E2

E3

E4

G

0.82

0.9

0.93

3.00

–

D

25.00 BASIC

22.86 BASIC

10 typ

8.26

D1

D2

1.27 BASIC

37

2141B–HIREL–01/03

Figure 26. Mechanical Dimensions and Bottom Surface Nomenclature of the 360-ball HiTCE Package

2X

0.2

2X

0.2

D

B

PIN A1

INDEX

A

360

X

0.15

A

2

1

C6

A3

A4

C5

C1

0.35

A

1

2

1

E

E2

E4

C4

C2

1

2X

C3

2

0.2

C

D4

D2

D3

E

3

TOP VIEW

D1

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19

W

V

U

T

R

P

N

M

L

K

J

A2

A1

A

E1

H

G

F

K

E

D

C

B

A

K

GND : C1.2 C2.2 C3.2 C4.2 C5.2 C6.2

C1.1, C2.1 : L2OVDD

G

0.3

T

E F

B

360X

C3.1, C6.1 : OVDD

T

0.15

C4.1, C5.1 : OVDD

BOTTOM VIEW

Parameter

Min

2.62

0.8

Max

3.24

1.00

1.30

0.6

Parameter

Min

Max

A

D3

D4

E

2.75

–

A1

A2

A3

A4

B

6.32

1.10

–

25.00 BASIC

22.86 BASIC

12.6 typ

E1

E2

E3

E4

G

0.82

0.9

0.93

3.00

–

D

25.00 BASIC

22.86 BASIC

10 typ

8.26

D1

D2

1.27 BASIC

38

PC7410

2141B–HIREL–01/03

PC7410

Figure 27. Mechanical Dimensions and Bottom Surface Nomenclature of the 360-column CI-CGA Package

2X

0.2

B

2X

0.2

D

PIN A1

INDEX

A

360 X

0.15

A

2

1

C6

A3

A4

C5

C1

0.35

A

1

2

1

E

E2

E4

C4

C2

1

2X

C3

2

0.2

C

D4

D2

D3

E3

TOP VIEW

D1

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19

W

V

U

T

R

P

N

M

L

A2

A1

A

K

J

E1

H

G

F

K

E

D

C

B

A

GND : C1.2 C2.2 C3.2 C4.2 C5.2 C6.2

C1.1, C2.1 : L2OVDD

K

G

0.3

T

E F

C3.1, C6.1 : OVDD

B

360X

T

0.15

C4.1, C5.1 : OVDD

Parameter

Min

3.4

Max

4.20

1.695

1.30

0.6

Parameter

Min

Max

A

D3

D4

E

2.75

–

A1

A2

A3

A4

B

1.545

1.10

–

6.32

25.00 BASIC

22.86 BASIC

E1

E2

E3

E4

G

0.82

0.9

–

15

–

0.93

3.00

D

25.00 BASIC

22.86 BASIC

8.26

D1

D2

1.27 BASIC

–

13

39

2141B–HIREL–01/03

Clock Selection

The PC7410’s PLL is configured by the PLL_CFG[0:3] signals. For a given SYSCLK

(bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency

of operation. The PLL configuration for the PC7410 is shown in Table 17 for example

frequencies. In this example, shaded cells represent settings that, for a given SYSCLK

frequency, result in core and/or VCO frequencies that do not comply with the minimum

and maximum core frequencies listed in Table 11.

Table 17. PC7410 Microprocessor PLL Configuration^{(1)(2)(3)(4)(5)}

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus-to-

Core

Multiplier

Core-to-

VCO

Multiplier

PLL_CFG

[0:3]

Bus

33.3 MHz

Bus

50 MHz

Bus

66.6 MHz

Bus

75 MHz

Bus

83.3 MHz

Bus

100 MHz

Bus

133 MHz

0100

0110

1000

1110

1010

0111

1011

1001

1101

0101

0010

0001

2x

2.5x

3x

2x

400 (800)

465 (930)

3.5x

4x

350 (700)

400 (800)

450 (900)

500 (1000)

4.5x

5x

375 (750)

416 (833)

458 (916)

500 (1000)

375 (750)

412 (825)

450 (900)

488 (967)

5.5x

6x

366 (733)

400 (800)

433 (866)

466 (933)

6.5x

7x

350 (700)

375 (750)

7.5x

500

(1000)

1100

0000

0011

1111

8x

9x

2x

400 (800)

450 (900)

PLL off/bypass

PLL off

PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied

PLL off, no core clocking occurs

Notes: 1. PLL_CFG[0:3] settings not listed are reserved.

2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO

frequencies which are not useful, not supported, or not tested for by the PC7410; see “Clock AC Specifications” on page 20

for valid SYSCLK, core, and VCO frequencies.

3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode

is set for 1:1 mode operation. This mode is intended for factory use and third- party emulator tool development only.

Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.

4. In PLL-off mode, no clocking occurs inside the PC7410 regardless of the SYSCLK input.

5. PLL-off mode should not be used during chip power-up sequencing.

40

PC7410

2141B–HIREL–01/03

PC7410

The PC7410 generates the clock for the external L2 synchronous data SRAMs by divid-

ing the core clock frequency of the PC7410. The divided-down clock is then phase-

adjusted by an on-chip delay-lock-loop (DLL) circuit and should be routed from the

PC74107410 to the external RAMs. A separate clock output, L2SYNC_OUT is sent out

half the distance to the SRAMs and then returned as an input to the DLL on pin

L2SYNC_IN so that the rising-edge of the clock as seen at the external RAMs can be

aligned to the clocking of the internal latches in the L2 bus interface.

The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of

the L2CR register. Generally, the divisor must be chosen according to the frequency

supported by the external RAMs, the frequency of the MPC7410 core, and the phase

adjustment range that the L2 DLL supports. Table 18 shows various example L2 clock

frequencies that can be obtained for a given set of core frequencies. The minimum L2

frequency target is 133 MHz. Sample core-to-L2 frequencies for the MPC7410 is shown

in Table 18. In this example, shaded cells represent settings that, for a given core fre-

quency, result in L2 frequencies that do not comply with the minimum and maximum L2

frequencies listed in Table 14.

Table 18. Sample Core-to-L2 Frequencies

Core Frequency in MHz

÷1

350

366

400

–

÷1.5

233

244

266

288

300

311

333

÷2

÷2.5

140

147

160

173

180

186

200

÷3

–

÷3.5

–

÷4

–

350

366

400

433

450

466

500

175

183

200

216

225

233

250

–

133

144

150

155

166

–

133

143

–

Note:

The core and L2 frequencies are for reference only. Some examples may represent core

or L2 frequencies which are not useful, not supported or not tested for by the PC7410;

see “L2 Clock AC Specifications” on page 24 for valid L2CLK frequencies. The

L2CR[L2SL] bit should be set for L2CLK frequencies less than 150 MHz.

System Design

Information

PLL Power Supply

Filtering

The AV_DDand L2AV_DDpower signals are provided on the PC7410 to provide power to

the clock generation phase-locked loop and L2 cache delay-locked loop, respectively.

To ensure stability of the internal clock, the power supplied to the AV_DDinput signal

should be filtered of any noise in the 500 kHz to 10 MHz resonant frequency range of

the PLL. A circuit similar to the one shown in Figure 28 using surface mount capacitors

with minimum effective series inductance (ESL) is recommended.

The circuit should be placed as close as possible to the AV_DDpin to minimize noise cou-

pled from nearby circuits. An identical but separate circuit should be placed as close as

possible to the L2AV_DDpin. It is often possible to route directly from the capacitors to the

AV_DDpin, which is on the periphery of the 360-ball CBGA footprint without the induc-

tance of vias. The L2AV_DDpin may be more difficult to route but is proportionately less

critical.

41

2141B–HIREL–01/03

Figure 28. PLL Power Supply Filter Circuit

Low ESL surface mount capacitor

10Ω

V_DD

AV_DD(or L2AV_DD)

2.2 µF

GND

Power Supply Voltage

Sequency

The notes in Table 2 contain cautions about the sequencing of the external bus voltages

and core voltage of the PC7410 (when they are different). These cautions are necessary

for the long term reliability of the part. If they are violated, the electrostatic discharge

(ESD) protection diodes will be forward-biased and excessive current can flow through

these diodes. If the system power supply design does not control the voltage sequenc-

ing, one or both of the circuits of Figure 29 can be added to meet these requirements.

The MUR420 Schottky diodes of Figure 29 control the maximum potential difference

between the external bus and core power supplies on power-up and the 1N5820 diodes

regulate the maximum potential difference on power-down.

Figure 29. Example Voltage Sequencing Circuits

2.5V

1.8V

MUR420

1N5820

Decoupling

Recommendations

Due to the PC7410’s dynamic power management feature, large address and data

buses and high operating frequencies, the PC7410 can generate transient power surges

and high frequency noise in its power supply, especially while driving large capacitive

loads. This noise must be prevented from reaching other components in the PC7410

system and the PC7410 itself requires a clean, tightly regulated source of power. There-

fore, it is recommended that the system designer place at least one decoupling

capacitor at each V_DD, OV_DD, and L2OV_DDpin of the PC7410. It is also recommended

that these decoupling capacitors receive their power from separate V_DD, (L2)OV_DD, and

GND power planes in the PCB, utilizing short traces to minimize inductance.

These capacitors should have a value of 0.01 µF or 0.1 µF. Only ceramic SMT (surface

mount technology) capacitors should be used to minimize lead inductance, preferably

0508 or 0603 orientations where connections are made along the length of the part.

Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital

Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to previous rec-

ommendations for decoupling PowerPC microprocessors, multiple small capacitors of

equal value are recommended over using multiple values of capacitance.

42

PC7410

2141B–HIREL–01/03

PC7410

In addition, it is recommended that there be several bulk storage capacitors distributed

around the PCB, feeding the V_DD, L2OV_DD, and OV_DDplanes to enable quick recharging

of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent

series resistance) rating to ensure the quick response time necessary. They should also

be connected to the power and ground planes through two vias to minimize inductance.

Suggested bulk capacitors are 100 - 330 µF (AVX TPS tantalum or Sanyo OSCON).

Connection

Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an

appropriate signal level. Unused active low inputs should be tied to OV_DD. Unused

active high inputs should be connected to GND. All NC (no-connect) signals must

remain unconnected.

Power and ground connections must be made to all external V_DD, OV_DD, L2OV_DD, and

GND pins of the PC7410.

See “L2 Clock AC Specifications” on page 24 for a discussion of the L2SYNC_OUT and

L2SYNC_IN signals.

Output Buffer DC

Impedance

The PC7410 60x and L2 I/O drivers are characterized over process, voltage and tem-

perature. To measure Z₀, an external resistor is connected from the chip pad to OV_DDor

GND. Then the value of each resistor is varied until the pad voltage is OV_DD/2 (see Fig-

ure 30).

The output impedance is the average of two components, the resistances of the pull-up

and pull-down devices. When data is held low, SW2 is closed (SW1 is open), and R_Nis

trimmed until the voltage at the pad equals OV_DD/2. R_Nthen becomes the resistance of

the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and R_Pis

trimmed until the voltage at the pad equals OV_DD/2. R_Pthen becomes the resistance of

the pull-up devices. R_Pand R_Nare designed to be close to each other in value. Then Z₀

= (R_P+ R_N)/2.

Figure 30. Driver Impedance Measurement

OV_DD

RN

SW2

Pad

Data

SW1

RP

OGND

43

2141B–HIREL–01/03

Table 19 summarizes the signal impedance results. The impedance increases with junc-

tion temperature and is relatively unaffected by bus voltage.

Table 19. Impedance Characteristics with V_DD= 1.8V, OV_DD= 1.8V or 2.5V,

T_j= -55°C to 125°C

Impedance

Processor bus

41.5 - 54.3

L2 Bus

42.7 - 54.1

39.3 - 50

Symbol

Unit

R_N

R_P

Z₀

Ohms

37.3 - 55.3

Pull-up Resistor

Requirements

The PC7410 requires pull-up resistors (1 kΩ – 5 kΩ) on several control pins of the bus

interface to maintain the control signals in the negated state after they have been

actively negated and released by the PC7410 or other bus masters. These pins are: TS,

AACK, ARTRY, SHDO, SHD1, TEA, and TA.

Three test pins also require pull-up resistors (100Ω-1 kΩ). These pins are L1_TSTCLK,

L2_TSTCLK, and LSSD_MODE. These signals are for factory use only and must be

pulled up to OV_DDfor normal machine operation.

In addition, CKSTP_OUT is an open-drain style output that requires a pull-up resistor

(1 kΩ–5 kΩ) if it is used by the system.

During inactive periods on the bus, the address and transfer attributes may not be

driven by any master and may, therefore, float in the high-impedance state for relatively

long periods of time. Since the PC7410 must continually monitor these signals for

snooping, this float condition may cause excessive power draw by the input receivers on

the PC7410 or by other receivers in the system. It is recommended that these signals be

pulled up through weak (10 kΩ) pull-up resistors by the system, or that they may be oth-

erwise driven by the system during inactive periods of the bus. The snooped address

and transfer attribute inputs are: A[0:31], AP[0:3], TT[0:4], TBST, CI, WT, and GBL.

In systems where GBL is not connected and other devices may be asserting TS for a

snoopable transaction while not driving GBL to the processor, we recommend that a

strong (1 kΩ) pull-up resistor be used on GBL.

The data bus input receivers are normally turned off when no read operation is in

progress and, therefore, do not require pull-up resistors on the bus. Other data bus

receivers in the system, however, may require pull-ups, or that those signals be other-

wise driven by the system during inactive periods by the system. The data bus signals

are: DH[0:31], DL[0:31], and DP[0:7].

If address or data parity is not used by the system, and the respective parity checking is

disabled through HID0, the input receivers for those pins are disabled, and those pins

do not require pull-up resistors and should be left unconnected by the system. If parity

checking is disabled through HID0, and parity generation is not required by the PC7410

(note the PC7410 always generates parity), then all parity pins may be left unconnected

by the system.

The L2 interface does not normally require pull-up resistors.

44

PC7410

2141B–HIREL–01/03

PC7410

JTAG Configuration

Signals

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal

is optional in the IEEE 1149.1 specification, but is provided on all processors that imple-

ment the PowerPC architecture. While it is possible to force the TAP controller to the

reset state using only the TCK and TMS signals, more reliable power-on reset perfor-

mance will be obtained if the TRST signal is asserted during power-on reset.

Because the JTAG interface is also used for accessing the common on-chip processor

(COP) function, simply tying TRST to HRESET is not practical.

The COP function of these processors allows a remote computer system (typically, a PC

with dedicated hardware and debugging software) to access and control the internal

operations of the processor. The COP interface connects primarily through the JTAG

port of the processor, with some additional status monitoring signals. The COP port

requires the ability to independently assert HRESET or TRST in order to fully control the

processor. If the target system has independent reset sources, such as voltage moni-

tors, watchdog timers, power supply failures, or push-button switches, then the COP

reset signals must be merged into these signals with logic.

The arrangement shown in Figure 31 allows the COP port to independently assert

HRESET or TRST, while ensuring that the target can drive HRESET as well. If the JTAG

interface and COP header will not be used, TRST should be tied to HRESET through a

0Ω isolation resistor so that it is asserted when the system reset signal (HRESET) is

asserted ensuring that the JTAG scan chain is initialized during power-on. While Motor-

ola recommends that the COP header be designed into the system as shown in Figure

31, if this is not possible, the isolation resistor will allow future access to TRST in the

case where a JTAG interface may need to be wired onto the system in debug situations.

The COP header shown in Figure 31 adds many benefits — breakpoints, watchpoints,

register and memory examination/modification, and other standard debugger features

are possible through this interface — and can be as inexpensive as an unpopulated

footprint for a header to be added when needed.

The COP interface has a standard header for connection to the target system, based on

the 0.025" square-post 0.100" centered header assembly (often called a Berg header).

The connector typically has pin 14 removed as a connector key.

There is no standardized way to number the COP header shown in Figure 31; conse-

quently, many different pin numbers have been observed from emulator vendors. Some

are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-

bottom, while still others number the pins counter clockwise from pin 1 (as with an IC).

Regardless of the numbering, the signal placement recommended in Figure 31 is com-

mon to all known emulators.

The QACK signal shown in Figure 31 is usually connected to the PCI bridge chip in a

system and is an input to the PC7410 informing it that it can go into the quiescent state.

Under normal operation this occurs during a low-power mode selection. In order for

COP to work, the PC7410 must see this signal asserted (pulled down). While shown on

the COP header, not all emulator products drive this signal. If the product does not, a

pull-down resistor can be populated to assert this signal. Additionally, some emulator

products implement open-drain type outputs and can only drive QACK asserted; for

these tools, a pull-up resistor can be implemented to ensure this signal is deasserted

when it is not being driven by the tool. Note that the pull-up and pull-down resistors on

the QACK signal are mutually exclusive and it is never necessary to populate both in a

system. To preserve correct power-down operation, QACK should be merged via logic

so that it also can be driven by the PCI bridge.

45

2141B–HIREL–01/03

Figure 31. COP Connector Diagram

SRESET

From Target

Board Sources

(if any)

SRESET

HRESET

QACK

10 kΩ

HRESET

13

11

OV

DD

SRESET

OV

DD

OV

5

0 Ω

TRST

1

3

2

4

TRST

4

VDD_SENSE

6

OV

DD

10 kΩ

2 kΩ

5

7

6

8

1

5

DD

CHKSTP_OUT

15

10 kΩ

9

10

12

OV

DD

Key

14

11

10 kΩ

2

DD

KEY

13

15

CHKSTP_IN

TMS

No pin

CHKSTP_IN

TMS

8

9

1

3

7

2

16

TDO

TDI

TDO

COP Connector

Physical Pin Out

TDI

TCK

QACK

10

12

16

NC

3

OV

2 kΩ

DD

4

10 kΩ

Notes: 1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the

PC7410. Connect pin 5 of the COP header to OV_DDwith a 10 kΩ pull-up resistor.

2. Key location; pin 14 is not physically present on the COP header.

3. Component not populated. Populate only if debug tool does not drive QACK.

4. Populate only if debug tool uses an open-drain type output and does not actively

deassert QACK.

5. If the JTAG interface is implemented, connect HRESET from the target source to

TRST from the COP header though an AND gate to TRST of the part. If the JTAG

interface is not implemented, connect HRESET from the target source to TRST of the

part through a 0Ω isolation resistor.

46

PC7410

2141B–HIREL–01/03

PC7410

Table 20. COP Pin Definitions

Pins

Signal

TDO

Connection

TDO

Special Notes

1

2

3

4

QACK

TDI

QACK

TDI

Add 2K pull-down to ground. Must be merged with on-board QACK, if any.

TRST

Add 2K pull-down to ground. Must be merged with on-board TRST if any.

See Figure 31.

5

6

7

8

RUN/STOP

VDD_SENSE

TCK

No Connect

VDD

Used on 604e; leave no-connect for all other processors.

Add 2K pull-up to OV_DD(for short circuit limiting protection only).

TCK

CKSTP_IN

Optional. Add 10K pull-up to OV_DD. Used on several emulator products. Useful for

checkstopping the processor from a logic analyzer of other external trigger.

9

TMS

10

11

12

13

14

15

16

N/A

SRESET

N/A

SRESET

HRESET

Merge with on-board SRESET, if any.

HRESET

N/A

Merge with on-board HRESET.

Key location; pin should be removed.

CKSTP_OUT

Ground

CKSTP_OUT

Digital Ground

Add 10K pull-up to OV_DD.

Boundary scan testing is enabled through the JTAG interface signals. (BSDL descrip-

tions of the PC7410 are available on the Internet at

www.mot.com/PowerPC/teksupport.) The TRST signal is optional in the IEEE 1149.1

specification but is provided on all PowerPC implementations. While it is possible to

force the TAP controller to the reset state using only the TCK and TMS signals, more

reliable power-on reset performance will be obtained if the TRST signal is asserted dur-

ing power-on reset. Since the JTAG interface is also used for accessing the common

on-chip processor (COP) function of PowerPC processors, simply tying TRST to

HRESET is not practical.

The common on-chip processor (COP) function of PowerPC processors allows a remote

computer system (typically a PC with dedicated hardware and debugging software) to

access and control the internal operations of the processor. The COP interface con-

nects primarily through the JTAG port of the processor with some additional status

monitoring signals. The COP port requires the ability to independently assert HRESET

or TRST in order to fully control the processor. If the target system has independent

reset sources, such as voltage monitors, watchdog timers, power supply failures or

push-button switches, then the COP reset signals must be merged into these signals

with logic.

The arrangement shown in Figure 31 allows the COP to independently assert HRESET

or TRST, while ensuring that the target can drive HRESET as well. The pull-down resis-

tor on TRST ensures that the JTAG scan chain is initialized during power-on if a JTAG

interface cable is not attached; if it is attached, it is responsible for driving TRST when

needed.

47

2141B–HIREL–01/03

The COP header shown in Figure 31 adds many benefits – breakpoints, watchpoints,

register and memory examination/modification and other standard debugger features

are possible through this interface – and can be as inexpensive as an unpopulated foot-

print for a header to be added when needed.

The COP interface has a standard header for connection to the target system, based on

the 0.025” square-post 0.100” centered header assembly (often called a “Berg” header).

The connector typically has pin 14 removed as a connector key, as shown in Figure 31.

48

PC7410

2141B–HIREL–01/03

PC7410

Definitions

Datasheet Status

Description

Table 21. Datasheet Status

Datasheet Status

Validity

Objective specification

This datasheet contains target and goal

specifications for discussion with customer and

application validation.

Before design phase

Target specification

This datasheet contains target or goal

specifications for product development.

Valid during the design phase

Preliminary specification

α-site

This datasheet contains preliminary data.

Additional data may be published later; could

include simulation results.

Valid before characterization phase

Preliminary specification β-site

Product specification

Limiting Values

This datasheet also contains characterization

results.

Valid before the industrialization phase

Valid for production purposes

This datasheet contains final product

specification.

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the

limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at

any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values

for extended periods may affect device reliability.

Application Information

Where application information is given, it is advisory and does not form part of the specification.

Life Support

Applications

These products are not designed for use in life support appliances, devices or systems

where malfunction of these products can reasonably be expected to result in personal

injury. Atmel customers using or selling these products for use in such applications do

so at their own risk and agree to fully indemnify Atmel for any damages resulting from

such improper use or sale.

49

2141B–HIREL–01/03

Ordering Information

PC (X) 7410

V

GS

U

400

L

x

(1)

Revision Level

Rev. E

Prefix

Prototype

(1)

Application modifier

L: 1.8V ± 100 mV

Type

N: 1.5V ± 50 mV (400 MHz only)

(1)

Max Internal Processor Speed

400 MHz

450 MHz

(1)

Temperature Range: T

V: -40°C, +110°C

M: -55°C, +125°C

j

500 MHz (TBC)

(1)

Package

G: CBGA

GS: CI-CBGA

GH: HITCE

(1)

Screening Level

U: Upscreening

Note:

1. For availability of the different versions, contact your local Atmel sales office.

50

PC7410

2141B–HIREL–01/03

Atmel Headquarters

Atmel Operations

Corporate Headquarters

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San Jose, CA 95131

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e-mail

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Web Site

http://www.atmel.com

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does

not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted

by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical

components in life support devices or systems.

ATMEL^®is the registered trademark of Atmel Corporation.

PowerPC is the trademark of IBM Corporation.

Other terms and product names may be the trademark of others.

Printed on recycled paper.

2141B–HIREL–01/03

0M


型号：	PCX7410VGU400L
厂家：	MICROCHIP
描述：	RISC Microprocessor, 32-Bit, 400MHz, CMOS, CBGA360, 外围集成电路
文件：	总51页 (文件大小：926K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCX7410VGU400L [MICROCHIP]

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