PD69101ILQ-TR#N/A_技术文档

PD69101

Datasheet

1-Port PSE PoE Controller

August 2019

1-Port PSE PoE Controller

Contents

1 Revision History ............................................................................................................................. 1

1.1 Revision 3.0 ........................................................................................................................................ 1

1.2 Revision 2.0 ........................................................................................................................................ 1

1.3 Revision 1.9 ........................................................................................................................................ 1

1.4 Revision 1.8 ........................................................................................................................................ 1

1.5 Revision 1.7 ........................................................................................................................................ 1

1.6 Revision 1.6 ........................................................................................................................................ 1

1.7 Revision 1.5 ........................................................................................................................................ 1

1.8 Revision 1.4 ........................................................................................................................................ 2

1.9 Revision 1.3 ........................................................................................................................................ 2

1.10 Revision 1.2 ...................................................................................................................................... 2

1.11 Revision 1.1 ...................................................................................................................................... 2

1.12 Revision 1.0 ...................................................................................................................................... 2

2 Product Overview .......................................................................................................................... 3

2.1 Features .............................................................................................................................................. 3

2.2 Typical 2-Pairs Application .................................................................................................................. 4

3 Functional Descriptions ................................................................................................................. 5

3.1 Logic Main Control Module ................................................................................................................ 5

3.1.1 Line Detection Generator ........................................................................................................................ 6

3.1.2 Classification Generator .......................................................................................................................... 6

3.1.3 Current Limiter ........................................................................................................................................ 6

3.1.4 Main MOSFET .......................................................................................................................................... 6

3.1.5 Analog-to-Digital Converter (ADC) .......................................................................................................... 6

3.1.6 Power on Reset (POR) ............................................................................................................................. 6

3.1.7 Voltage Regulator .................................................................................................................................... 6

3.1.8 CLK ........................................................................................................................................................... 6

3.2 Application Information ..................................................................................................................... 6

3.2.1 Line Detection ......................................................................................................................................... 7

3.2.2 Legacy (Capacitor) Detection .................................................................................................................. 7

3.2.3 Classification ............................................................................................................................................ 7

3.2.4 Port Start Up ............................................................................................................................................ 7

3.2.5 Over-Load Detection and Port Shut Down .............................................................................................. 7

3.2.6 Disconnect Detection .............................................................................................................................. 8

3.2.7 Over-Temperature Protection ................................................................................................................. 8

3.2.8 V MAIN Out-of-Range Protection ............................................................................................................ 8

3.2.9 Serial Communication: Monitoring Mode ............................................................................................... 8

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1-Port PSE PoE Controller

4 Electrical Specifications ................................................................................................................ 11

4.1 Dynamic Characteristics ................................................................................................................... 12

4.2 Absolute Maximum Ratings .............................................................................................................. 13

4.3 Moisture Sensitivity .......................................................................................................................... 14

4.4 Power Dissipation Information ......................................................................................................... 14

5 Pin Descriptions ........................................................................................................................... 15

5.1 CURRENT_SET and AF/AT ................................................................................................................. 17

5.2 Mode of Operation Coding ............................................................................................................... 17

5.3 LED I/Os Behavior ............................................................................................................................. 17

6 Package Specifications ................................................................................................................. 19

6.1 RoHS and Solder Reflow Information ............................................................................................... 20

6.2 Thermal Specifications ..................................................................................................................... 21

6.3 Tape and Reel—Packaging Information ........................................................................................... 22

7 Ordering Information ................................................................................................................... 24

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1

Revision History

The revision history describes the changes that were implemented in the document. The changes are

listed by revision, starting with the most current publication.

1.1

Revision 3.0

Revision 3.0 was published in August 2019. The following is a summary of changes in revision 3.0 of this

document.

Changed package marking of figure PD69101 Pinout (see page 15).

Part marking is updated. For more information, see the Ordering Information (see page 24) section.

1.2

Revision 2.0

Revision 2.0 was published in March 2018. The following is a summary of changes in revision 2.0 of this

document.

Document format was updated.

MSL level was updated from 1 to 3.

4-pair application was removed.

Tape and Reel—Packaging Information section was added. For more information, see Tape and

Reel—Packaging Information (see page 22).

Part marking is updated. For more information, see the Ordering Information (see page 24) section.

1.3

1.4

Revision 1.9

Revision 1.9 was published in March 2014. The following is a summary of changes in revision 1.9 of this

document.

TETA JB was added.

A typo in the ESD parameter was corrected.

Vmain out-of-range information was corrected.

Revision 1.8

Revision 1.8 was published in October 2013. In revision 1.8 of this document, the extended input voltage

range was updated to 32 V–57 V.

1.5

1.6

1.7

Revision 1.7

Revision 1.7 was published in July 2013. In revision 1.7 of this document, TETA JC data was added.

Revision 1.6

Revision 1.6 was published in July 2013. In revision 1.6 of this document, the IC marking was updated.

Revision 1.5

Revision 1.5 was published in December 2010. In revision 1.5 of this document, parameters were

updated.

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1.8

Revision 1.4

Revision 1.4 was published in September 2010. In revision 1.4 of this document, parameters were

updated.

1.9

Revision 1.3

Revision 1.3 was published in June 2010. In revision 1.3 of this document, parameters were updated.

1.10

Revision 1.2

Revision 1.2 was published in June 2010. In revision 1.2 of this document, the package drawing was

updated.

1.11

1.12

Revision 1.1

Revision 1.1 was published in March 2010. In revision 1.1 of this document, the wave forms and

functionality were updated according to evaluation results.

Revision 1.0

Revision 1.0 was published in March 2010. It was the first publication of this document.

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2

Product Overview

Microsemi's PD69101 device is a single-port, mixed-signal, high-voltage Power over Ethernet (PoE)

driver. Utilized in Ethernet switches, it enables network devices to share power and data over the same

cable. It enables detection of IEEE 802.3af-2003-compliant powered devices (PDs) and IEEE 802.3at high-

power devices, ensuring safe power feeding and disconnection of ports, with full digital control and a

minimum of external components. A “plug-and-play” device, the PD69101 executes all real-time

functions as specified in the IEEE 802.3af-2003 (AF) and IEEE 802.3at high-power (AT) standards,

including load detection, AF and AT classification, and multiple classification attempts (MCA).

Integrating power, analog, and state-of-the-art logic, the PD69101 fits into a single 24-pin plastic QFN

package. The chip includes built-in internal thermal protection, and two LEDs provide port state and

port type (AF/AT) indication.

The PD69101:

Is designed to detect and disable disconnected ports, utilizing DC disconnection methods as

specified in the AF and IEEE 802.3ar-2009 standards.

Is a low-power device using an internal 0.34 Ω MOSFET and an external 0.5 Ω sense resistor.

Can optionally detect legacy/pre-standard PD devices.

Provides over-load, under-load, over-voltage, over-temperature, and short-circuiting PD protection.

Supports supply voltages ranging from 32 V to 57 VDC with no need for additional power supply

sources.

2.1

Features

The PD69101 device has the following key features.

Fully AF and AT compliant

Includes two-event classification

Supports pre-standard PD detection

Supports Cisco device detection

Single DC voltage input (32 V–57 VDC)

Supports two pairs

VMAIN out-of-range protection

Wide temperature range: –40 °C to 85 °C

Over-temperature protection

Low thermal dissipation (0.5 Ω sense resistor)

Includes on/off command pin

2× direct LEDs drive

Continuous port monitoring and system data

Configurable load current setting

Configurable AT/AF modes

Configurable standard and legacy detection mode

Power soft-start mechanism

On-chip thermal protection

Voltage monitoring and protection

Built-in 3.3 VDC regulator

Internal power-on reset

RoHS compliant

Low Rdson FET: 0.3 Ω

MSL3

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2.2

Typical 2-Pairs Application

This typical application illustrates a simple plug-and-play PoE solution for a single Ethernet port switch

or hub.

POS and NEG signals should be connected to the switch RJ45 jack. AF and AT modes of operations are

set through AF/AT and current-set pins (DGND or DVDD).

Figure 1 • Typical 2-Pair Application

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3

Functional Descriptions

The PD69101 device has two major sections: a digital section that controls and monitors the logical PoE

functions (state machines, timings, and so on) and an analog section that performs the front-end analog

PoE functionality.

The following illustration shows the internal functional blocks of the PD69101 device.

Figure 2 • PD69101 Internal Block Diagram

3.1

Logic Main Control Module

The logic main control block includes the digital timing mechanisms and state machines, synchronizing

and activating the PoE functions, such as the following.

Real-time protection (RTP)

Start-up macro (DVDT)

Load signature detection (RES DET)

Classification macro (CLASS)

Voltage and current monitoring registers (VMC)

LEDs stream out control indications

ADC interfacing

Direct digital signals with analog block

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3.1.1

3.1.2

3.1.3

Line Detection Generator

Upon request from the main control module, four different voltage levels are generated by the line

detection generator, ensuring robust AF/AT line detection functionality.

Classification Generator

Upon request from the main control module, the state machine applies a regulated class event and

mark event voltage to the ports, as required by the IEEE standard.

Current Limiter

This circuit continuously monitors the current of powered ports and limits the current to a specific

value, according to pre-defined limits as set by AF/AT and current_set pins. In cases where the current

exceeds this specific level, the system starts measuring the elapsed time. If this time period is greater

than a preset threshold, the port is disconnected.

3.1.4

3.1.5

Main MOSFET

Main power switching FET, used to control PoE current into the load.

Analog-to-Digital Converter (ADC)

A 10-bit analog-to-digital converter, used to convert analog signals into digital registers for the logic

control module.

3.1.6

3.1.7

Power on Reset (POR)

This circuit monitors the internal 3.3 VDC levels. If this voltage drops below specific thresholds, a reset

signal is generated and the PD69101s are reset.

Voltage Regulator

The voltage regulator generates 3.3 VDC and 5 VDC for the internal circuitry. These voltages are derived

from the Vmain supply.

3.1.8

CLK

CLK is an internal 8 MHz clock oscillator.

3.2

Application Information

The PD69101 performs IEEE 802.3af and IEEE 802.3at functionality as well as legacy (capacitor) and

Cisco PD detection, in addition to protections such as short circuit and dV/dT protection upon startup.

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3.2.1

Line Detection

The line detection feature detects a valid AF or AT load, as specified in the AF/AT standard. The resistor

value should range from 19K Ω to 26.5K Ω. Line detection is based on four different voltage levels

generated over the PD (the load), as shown in the following illustration.

Figure 3 • Typical PoE Voltage Timing Diagram

3.2.2

3.2.3

Legacy (Capacitor) Detection

In cases where pin 24 is set to 0, the PD69101's detection mechanism is configured to detect and power

up legacy PDs, as well as AF/AT-compliant. This mechanism also detects and powers up Cisco legacy PDs.

Classification

The classification process takes place right after the resistor detection, when the resistor detection has

completed successfully. The main goal of the classification process is to detect the PD class, as specified

in the IEEE 802.3AF and AT standards. In AF mode, the classification mechanism is based on a single

voltage level (single class event). In AT mode, the classification mechanism is based on two voltage

levels (dual class event) as defined in IEEE 802.3at-2009. In AT mode, when the PD is class 0–3, the

PD69101 generates a single class event. When the PD is class 4, the PD69101 generates two class

events.

3.2.4

3.2.5

Port Start Up

Upon a successful detection and classification process, power is applied to the load through a controlled

start-up mechanism. During this period, current is limited to 425 mA for a typical duration of 65 mS,

which enables the PD load to charge and enter a steady state power condition.

Over-Load Detection and Port Shut Down

After power up, the PD69101 automatically initializes its internal protection mechanisms to monitor and

disconnect power from the load in cases where extreme conditions (such as over-current or short port

terminal scenarios) occur, as specified in the IEEE 802.3AF/AT standard.

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3.2.6

3.2.7

Disconnect Detection

The PD69101 supports the DC disconnect function as per the IEEE 802.3AF/AT standard. This mechanism

continuously monitors the load current and disconnects power in cases where the load current is below

7.5 mA (typical) for more than 322 mS.

Over-Temperature Protection

The PD69101 has internal temperature sensors that continuously monitor junction temperature and

disconnect load power when the junction temperature exceeds 200 °C. This mechanism protects the

device from extreme events such as high ambient temperature or other thermo-mechanical failures that

may damage the PD69101.

3.2.8

3.2.9

V MAIN Out-of-Range Protection

The PD69101 automatically disconnects port power when Vmain exceeds 57.5 VDC ±0.5 VDC. This is an

extremely valuable feature that protects the load if the main power source is faulty or damaged.

Serial Communication: Monitoring Mode

When MODE0 and MODE1 input pins are configured to serial monitoring mode (01), the PD69101

continuously and repeatedly transmits out the content of nine internal registers.

Data out stream is transmitted through LED1 (pin 14)

Clock out stream is transmitted through LED0 (pin 13)

Data stream is shifted out with a 1 MHz clock (1 µsec)

Total transaction packet length is 116 µsec

The transmission is repeated every 1 µsec

Between transactions, the clock is held low while the data stream out is stable high/low.

Note: To exploit LED1 and LED0 to communicate and monitor transmissions, use a 1K Ω pull-up resistor

to the DVDD.

The following table lists the stream out data transmits of 116 bits, starting from MSB to LSB.

Table 1 • Serial Monitoring Mode

MSB

LSB

Internal

1

Internal

2

Internal

3

Internal

4

VPORT

10 bits

VMAIN

10 bits

IPORT

Port Status

0

13 bits

10 bits

23 bits

16 bits

13 bits

5 bits

78 internal signals used for internal tests

Port voltage

Vmain

Port current

Real-time port

measurement

voltage

measurement

status indication

measurement

LSB= 58 mV

LSB= 238 µA

I= Decimal ×

238 µA

For more

LSB= 58 mV

information, see

Port Status Coding

(see page 9).

V= Decimal ×

58 mV

V= Decimal ×

58 mV

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The following table lists the port status coding.

Table 2 • Port Status Coding

Binary MSB to LSB

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01100

01011

01101

01110

01111

10000

10001

10010

10011

10100

Decimal Value

Description

0

PoE idle state

1

2

3

Searching phase

Res detection phase

Back off phase

4

5

6

7

Class phase

8

9

Wait for start up

10

12

11

13

14

15

16

17

18

19

20

Cap detection

Start up

Ongoing

UDL

Overload or short circuit

Vmain out of range

Figure 4 • Data Stream Out

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Figure 5 • Multi-Packet Idle Time (Between Packets)

Figure 6 • Data/Clock Typical Timing

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4

Electrical Specifications

Unless otherwise specified, the following specifications apply to the operating ambient temperature

(TAMB): –40 °C to 85 °C.

Table 3 • Power Supply

Parameter

Symbol

Test Conditions/

Comment

Min.

32

Typ.

55

Max.

57

Unit

VDC

mA

Input voltage

VMAIN

Supports full IEEE 802.3

functionality

Power supply current at operating

mode

VMAIN = 55 V

10

Table 4 • Digital I/O

Parameter

Symbol

Test Conditions/

Comment

Min.

2.2

Typ.

0.6

Max.

Unit

Input logic, high threshold

Input logic, low threshold

Input hysteresis voltage

Input high current

VIH

VIL

VDC

µA

0.8

10

0.4

–10

2.4

IIH

Input low current

IIL

10

µA

Output high voltage

Output low voltage

VOH

VOL

For IOH = –1 mA

IOH = 1 mA

VDC

0.4

Table 5 • PoE Load Currents

Parameter

Symbol

Test Conditions

/Comment

Min.

1.18

Typ.

1.2

Max.

1.28

Unit

A

AT, high limit mode

AT_LIM_HIGH

RSENSE = 0.5 Ω 1%,

(high current level, for future

use)

connected at

Port_Sense pin

AT, medium limit

mode

AT_LIM_MID

847

874

919

mA

(medium current level, for

future use)

AT, low limit mode

AF, limit mode

AT_LIM_LOW

AF_LIM

706

410

722

425

767

448

mA

Table 6 • Main Power Switching FET

Parameter

Symbol

Typ.

0.3

Unit

Ω

On resistance

RDSON

Internal thermal protection threshold

200

°C

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Table 7 • LED0 and LED1 Drivers

Parameter

Symbol

Typ.

3

Max.

5

Unit

mA

Current sink

ISINK (from Vmain to AGND)

4.1

Dynamic Characteristics

The PD69101 device utilizes three current level thresholds (IMIN, ICUT, and ILIM) and three timers (TMIN, TCUT,

and TLIM).

Loads that consume ILIM current for more than TLIM are labeled as "short circuit state" and shut down.

Loads that dissipate more than ICUT for longer than TCUT are labeled as overloads and are shut down.

If output power is below IMIN for more than TMIN, the PD is labeled as "no load" and is shut down.

Automatic recovery from overload and no load conditions is attempted every TOVLREC periods (typically

one second). Output power is limited to ILIM, which is a maximum peak current allowed at the port.

Table 8 • IEEE 802.3 AF Mode Parameters

Parameter

Symbol

Conditions

Min.

Typ.

1

Max.

Unit

sec

Automatic

TUDLREC value, measured from port shutdown point

(can be modified through control port)

recovery from no

load shutdown

Cutoff timer

accuracy

Typical accuracy of Tcut

2

ms

mA

W

Inrush current

IInrsh

For t = 50 ms,

400

10

450

375

15.4

Cload = 180 μF (max)

Output current

operating range

IPORT

PPORT

Continuous operation after startup period

Output power

available

Continuous operation after startup period, at port

output

0.57

operating range

Off-mode current

IMIN1

IMIN2

Must disconnect for T greater than TUVL

0

5

mA

May or may not disconnect when T is greater than

7.5

10

TUVL

PD power

TPMDO

Buffer period to handle transitions

300

400

ms

maintenance

request drop-out

time limit

Over-load current

detection range

ICUT

Time limited to TOVL

350

50

400

75

mA

ms

µs

Over-load time

limit

TOVL

TRISE

Turn-on rise time

From 10% to 90% of Vport (specified for PD load

consisting of 100 μF capacitor in parallel to 200 Ω)

15

Turn-off time

TOFF

From Vport to 2.8 VDC

500

ms

Time maintain

TMPS

DC modulation time for DC disconnect

49

power signature

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Table 9 • IEEE 802.3 AT Mode Parameters

Parameter

Symbol

Conditions

Min.

Typ.

1

Max.

Unit

sec

Automatic recovery from

no load shutdown

TUDLREC value, measured from port

shutdown point (can be modified through

control port)

Cutoff timer accuracy

Inrush current

Typical accuracy of Tcut

2

ms

IInrsh

IPORT

For t = 50 ms, Cload = 180 μF (max)

Continuous operation after startup period

400

10

450

725

mA

Output current operating

range

Output power available

operating range

PPORT

Continuous operation after startup

period, at port output

0.57

36.25

W

Off-mode current

IMIN1

IMIN2

Must disconnect for T greater than TUVL

0

5

mA

May or may not disconnect when T is

7.5

10

greater than

TUVL

PD power maintenance

request drop-out time

limit

TPMDO

Buffer period to handle transitions

Time limited to TOVL

300

400

ms

Over-load current

detection range

ICUT

600

75

mA

Over-load time limit

Turn-on rise time

TOVL

TRISE

50

15

ms

µs

From 10% to 90% of Vport (specified for PD

load consisting of 100 μF capacitor in

parallel to 200 Ω).

Turn-off time

TOFF

From Vport to 2.8 VDC

500

ms

Time maintain power

signature

TMPS

DC modulation time for DC disconnect

49

4.2

Absolute Maximum Ratings

The following table lists the absolute maximum ratings for the PD69101. Exceeding these ratings can

cause damage to the device. Pin Port_Sense is ESD sensitive and passes 500 V HBM. All voltages are with

respect to ground. Currents are marked positive when flowing into a specified terminal and marked

negative when flowing out of a specified terminal.

Table 10 • Absolute Maximum Ratings

Parameter

Rating

Supply input voltage (VMAIN)

Port_Neg pin, LED0, LED1

Port_Sense pin

–0.3 VDC to 74 VDC

–0.3 VDC to 3.6 VDC

–0.3 VDC to 0.3 VDC

–0.3 V to 5.5 V

QGND, AGND pins

VAUX5

All other pins

–0.3 VDC to 3.6 VDC

–40 °C to 85 °C

Operating ambient temperature range

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Parameter

Rating

Maximum operating junction temperature

Storage temperature range

150 °C

–65 °C to 150 °C

±2 KV (HBM)

ESD protection at all I/O pins

4.3

4.4

Moisture Sensitivity

This device is rated moisture sensitivity level 3 or better as specified in the joint IPC and JEDEC standard

IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard.

Power Dissipation Information

Table 11 • Power Dissipation

Parameter

Value

2

Rsense power dissipation

0.5 Ω × IPORT

0.3 Ω × IPORT

Rds_ON power dissipation

Pport_AF = 15.4 W

PRsense = 51 mW (320 mA)

31 mW (320 mA)

PRds_ON

Pport_AT = 30 W

PRsense = 180 mW (600 mA)

108 mW (600 mA)

PRds_ON

Typical PD69101 self power dissipation (including internal regulations)

Typical PD69101 2-pairs AF application power dissipation

Typical PD69101 2-pairs AT application power dissipation

0.5 W (50 VDC)

0.5 W + 51 mW + 31 mW = 0.582 W

0.5 W + 180 mW + 108 mW = 0.788 W

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Pin Descriptions

The following illustration shows the device pin diagram from the top and bottom views.

Figure 7 • PD69101 Pinout

The following table lists the pin descriptions for the PD69101 device.

Table 12 • Pin Descriptions

Number

0

Name

Type

Description

Exposed PAD

Analog

ground

Exposed pad; metal plate on the IC bottom side connected to analog

ground.

A high-quality ground plane (about 500 mil. inch over 500 mil. inch)

should be deployed around this pin whenever possible.

1

2

CURRENT_SET

AF/AT

Digital input

Power in

User input to set AF/AT and maximum current limit.

Use pull-up resistors to DVDD or pull-down resistors to DGND to set the

mode of operation as shown in the CURRENT_SET and AF/AT Pins (see

page 17) table.

3

DVDD

Regulated input voltage (3.3 V) for internal digital circuitry.

Should be externally connected to pin 4.

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Number

Name

Type

Description

4

VAUX3P3

Power in

Voltage regulation in, 3.3 VDC.

Connect to pin 5.

A 4.7 µF capacitor to AGND is recommended.

5

6

DRV_VAUX3P3

VAUX5

Power out

Power

Internal voltage regulator out, 3.3 VDC.

Should be externally connected to pin 4.

Regulated 5 VDC voltage filter.

A 1 µF capacitor to AGND is recommended.

7

8

AGND

Power

Analog ground.

V_MAIN

Supply voltage for the internal analog circuit. Place a low-ESR bypass

capacitor with low impedance trace as close as possible to AGND and this

pin (not less than 1 µF).

9

PORT_NEG

PORT_SENSE

QGND

Analog I/O

Analog input

Power

Negative output of the port.

10

11

12

13

14

Sense resistor port input (connected to 0.5, 1% Ω resistor to GND).

Quiet analog ground; used for sensitive analog cells.

Resistor reference. Connect 30.1K 1% resistor to QGND.

I_REF

Analog I/O

LED0

Open-drain I

/O

Port status direct LED indications. For details, see the 2-Pair Behavior (see

page 17) table. This is a high-voltage, open-drain, active low (SINK)

output pin.

LED1

Connection to LED and Vmain through a ~18.2K Ω (~3 mA) resistor is

recommended.

15

16

17

N/C

Analog I/O

Test pin (for production use only); keep open (not connected).

N/C

TRIM

Analog input

Digital I/O

Zapping input for IC production trimming.

Should be connected to DVDD.

18

SYNC

Synchronization open-drain I/O pin between master and slave.

In 2-pair mode (switch), this pin should be pulled down to DGND through

a 4.7K Ω resistor.

19

20

21

22

DGND

Digital I/O

Digital input

Test I/O

Digital ground.

RESET_N

MODE 0

MODE 1

Reset input/on-off command (active low).

Configuration input pins.

Used to set mode of operation and test mode at production. Typically

connected to DGND.

For details, see the Configuration Coding (see page 17) table.

23

24

Master/Slave

Digital input

If connected to DVDD (3.3 VDC): master mode.

If connected to GND: slave mode.

STD_DET

/LEGACY

User input pin to set the chip mode of operation.

1: DVDD= IEEE 802.3af-compliant resistor detection only.

0: DGND= IEEE 802.3AF/AT detection and legacy (non-standard) line

detection.

Note: 0= Connect to DGND, 1= connect to DVDD.

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1-Port PSE PoE Controller

5.1

CURRENT_SET and AF/AT

These pins determine the typical PD load output current as listed in the following table.

Table 13 • CURRENT_SET and AF/AT Pins

AT/AF Pin

Current_Set Pin

Max. Current

ICUT [mA]

Typical ILIM

[mA]

IEEE 802.3

0

1

0

1

350

600

720

1000

425

722

874

1200

AF mode (standard)

AT mode (standard)

AT mode (high power)

AT mode (extra high power)

5.2

Mode of Operation Coding

The following table lists the mode of operation coding options related to pins 21 and 22.

Table 14 • Configuration Coding

Mode

0

Mode

1

Mode

Description

0

1

Normal operation

mode

Standard operation PoE mode.

LED0 and LED1 outputs are used for direct LED drive as described in the

following section.

Serial monitoring

mode

Standard operation PoE mode.

LED0 and LED1 are used to continuously stream out internal logic signals for

PoE monitoring.

1

0

1

Test mode

Internal IC test mode; used in production only.

5.3

LED I/Os Behavior

The following tables list the LED I/Os behavior related to pins 13 and 14 in 2-pair application. In both

application types, the LED pin is a high-voltage open-drain output pin and an active low (sink) pin. That

is, LED is “ON” when the I/O is pulled low.

Table 15 • 2-Pair Behavior

Status Indications

LED0

ON

LED1

OFF

ON

Notes

AF mode—port ON

Useful for bi-color LED connected from LED0 to LED1.

AT mode (class AT was detected)—port ON

AF mode—over-load or short

ON

Blink

1 Hz

OFF

Blinking continues for ~2 sec.

AT mode—over-load or short

Blink

1 Hz

Blink

1 Hz

Vmain voltage is out of range or IC over-

temperature

Blink

4 Hz

OFF

Blinking continues as long as over-voltage or over-

temperature state exists.

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1-Port PSE PoE Controller

Status Indications

LED0

OFF

LED1

ON

Notes

AF mode—port OFF

AT mode—port OFF

Useful for bi-color LED connected from LED0 to LED1.

OFF

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1-Port PSE PoE Controller

6

Package Specifications

This section provides the package drawing, RoHS and solder reflow information, and thermal

specifications for the PD69101 device.

The PD69101 package is a 4 mm × 5 mm, 24-pin QFN, as shown in the following illustration.

Figure 8 • QFN Package

Dimensions do not include protrusions; these shall not exceed 0.155 mm (0.006”) on any side. Lead

dimension shall not include solder coverage.

The following table lists the dimensions for the QFN package.

Table 16 • Package Dimensions

Dimension

Millimeters

Inches

Min.

Max.

0.039

0.002

A

0.80

1.00

0.05

0.031

A1

A3

K

0.00

0

0.20 REF

0.20 MIN

0.50 BSC

0.30

0.008 REF

0.008 MIN

0.02 BSC

0.012

e

L

0.50

0.30

2.75

3.75

0.02

b

0.18

0.007

0.012

0.108

0.148

D2

E2

2.50

0.098

3.50

0.138

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1-Port PSE PoE Controller

Dimension

Millimeters

4.00 BSC

Inches

D

E

0.158 BSC

0.197 BSC

5.00 BSC

6.1

RoHS and Solder Reflow Information

The PD69101 device is rated RoHS 6/6. The package is lead(Pb)-free, with a 100% matte tin finish. The

package peak temperature for solder reflow (40 seconds maximum exposure) is 260 °C (0 °C, –5 °C).

The following table lists the classification reflow profile information.

Table 17 • Classification Reflow Profiles

Profile Feature

Pb-Free Assembly

3 °C/second max.

Average ramp-up rate (TSmax to Tp)

Preheat:

150 °C

Temperature minimum (TSmin)

Temperature maximum (TSmax)

200 °C

60 seconds–180 seconds

Time (TSmin to TSmax)

Time maintained above:

217 °C

Temperature (TL)

60 seconds–150 seconds

Time (tL)

Peak/classification temperature

Time within 5 °C of actual peak temperature (tp)

Ramp-down rate

See the figure Classification Reflow Profile Diagram (see page 21).

20 seconds–40 seconds

6 °C/second max.

8 minutes max.

Time 25 °C to peak temperature

Note: All temperatures refer to the top-side of the package, measured on the package body surface.

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1-Port PSE PoE Controller

The following illustration shows the classification reflow profile of the PD69101 device.

Figure 9 • Classification Reflow Profile Diagram

Note: Exceeding these ratings can damage the device.

6.2

Thermal Specifications

The following table lists the thermal specifications for the PD69101 device.

Table 18 • Thermal Specifications

Parameter

Value

Typical thermal resistance: junction to ambient

Typical thermal resistance: junction to case

Typical thermal resistance: junction to board

25 °C/W

4 °C/W

2 °C/W

The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All

specifications assume no ambient airflow.

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1-Port PSE PoE Controller

6.3

Tape and Reel—Packaging Information

The following section provides the tape and reel packaging information. The following illustration shows

the tape specification.

Figure 10 • Tape Specification

The following table lists the tape mechanical data.

Table 19 • Tape Mechanical Data

Dimension

A0

Millimeters

4.25 ±0.10

5.40 ±0.10

1.20 ±0.10

-

B0

K0

K1

Pitch

Width

8.00 ±0.10

12.00 ±0.30

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1-Port PSE PoE Controller

The following illustration shows the reel specification.

Figure 11 • Reel Specification

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1-Port PSE PoE Controller

7

Ordering Information

The following table lists the ordering information for the PD69101 device.

Table 20 • Ordering Information

Part Number

Package

Packaging Type

Tape and reel

Temperature

Part Marking

PD69101ILQ-TR

Plastic 24-pin

– 40 °C to 85 °C

MSC

69101

ZZ e3¹

QFN: 4 mm × 5 mm

YYWWNNN²

1. ZZ e3: ZZ = Random character with no meaning and e3 = 2nd level interconnect.

2. YY = Year, WW = Week, NNN = Trace Code.

Microsemi Proprietary and Confidential. PD-000308061 PD69101 Datasheet Revision 3.0

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1-Port PSE PoE Controller

Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services

for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The

products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with

mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and

complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data

and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any

products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the

entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights,

licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this

document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products

and services at any time without notice.

Microsemi Headquarters

One Enterprise, Aliso Viejo,

CA 92656 USA

Within the USA: +1 (800) 713-4113

Outside the USA: +1 (949) 380-6100

Sales: +1 (949) 380-6136

Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of semiconductor and system

solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened

analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time

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service marks are the property of their respective owners.

PD-000308061

Microsemi Proprietary and Confidential. PD-000308061 PD69101 Datasheet Revision 3.0

25


型号：	PD69101ILQ-TR#N/A
厂家：	MICROCHIP
描述：	Switching Controller 开关
文件：	总28页 (文件大小：1256K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PD69101ILQ-TR#N/A [MICROCHIP]

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