PD69208MILQ-TR-LE_技术文档

PD69208T4/PD69204T4/

PD69208M

PoE PSE Manager

Introduction

Microchip's PD69208T4, PD69204T4, and PD69208M Power over Ethernet (PoE) manager ICs integrate power,

analog, and state-of-the-art logic into a single 8 mm × 8 mm, 56-pin, plastic QFN package. The device is used in

conjunction with a Microchip PSE controller or an Ethernet switch processor from a supported third-party vendor to

provide an IEEE^®802.3af/at/bt or Power over HDBase (PoH) Power Sourcing Equipment (PSE) solution.

Typical PoE Application

The following figure shows the typical PoE application of Microchip Generation 6 devices.

Figure 1.ꢀTypical PoE Application with Microchip Controller

System Bulk

Capacitor

5V

3.3V

VMAIN

VAUX5

VAUX3P3

VMAIN

Isola�on

VDDA VDD

PORT_NEG0

PD69210

PD69220

PD69200

PoE Controller

Required for

IEC62368-1 Ed.2

MOSI

SCK

MOSI

PD69208T4

PD69204T4

PD69208M

PoE Manager

UART/I²C

To Host

SCK

xCS

P_SYSTEM>250W

xCS

VMAIN

MISO

PORT_NEG7

MISO

(PD69208T4/M)

PORT_NEG3

(PD69204T4)

VSSA VSS

Required for

IEC62368-1 Ed.2

Power

Supply

Monitoring

PGD<0:3>

IREF

P_SYSTEM>250W

F

AGND

DGND

Consult Microchip AN3361 Designing an IEEE 802.3af/at/bt PoE System Based on PD692x0/PD69208.

DS00003428C-page 1

Datasheet

PD69208T4/PD69204T4/PD69208M

PoE Manager Features

•

Drives 2-pair or 4-pair power ports

Single DC voltage input

Built-in 3.3 V and 5 V regulators

Over-temperature protection and thermal monitoring

Low-power dissipation

Industrial temperature range: –40 °C to 85 °C

MSL3, RoHS compliant

Table 1.ꢀDevice-Specific Features

Feature

PD69208T4

PD69204T4

PD69208M

Ports per IC

8

4

8

PSE type supported

Maximum output power

4

3

95 W

60 W

Chipset Features

•

Complies with IEEE 802.3af/at/bt

•

Supports pre-standard PD detection

LED stream support

Supports Power over HDBaseT (POH)

Cascade up to 12 PoE devices for 48 logical ports

Advance system power management

Configurable load current setting

Field upgradable

Emergency power management supporting 16

configurable power banks

Any combination of PD69208T4, PD69204T4, and

PD69208M, and any combination of 2-pair and 4-

pair in the same system is possible and supported.

•

Continuous port monitoring and status

Supports Fast and Perpetual PoE

Applications

•

PoE switches/routers/midspans

Industrial automation

•

PoE for LED lighting

Video recorders (NVR/DVR)

DS00003428C-page 2

Datasheet

PD69208T4/PD69204T4/PD69208M

Table of Contents

Introduction.....................................................................................................................................................1

Typical PoE Application...........................................................................................................................1

PoE Manager Features...........................................................................................................................2

Chipset Features.....................................................................................................................................2

Applications.............................................................................................................................................2

1. Functional Descriptions...........................................................................................................................5

1.1. Digital Block Module.....................................................................................................................5

1.2. PD Detection Generator...............................................................................................................5

1.3. Classification Generator...............................................................................................................5

1.4. Current Limiter..............................................................................................................................6

1.5. Main Power MOSFET.................................................................................................................. 6

1.6. 10-Bit ADC................................................................................................................................... 6

1.7. Power on Reset............................................................................................................................6

1.8. Voltage Regulator.........................................................................................................................6

1.9. Oscillator...................................................................................................................................... 6

1.10. SPI Communication......................................................................................................................6

2. Electrical Specifications.......................................................................................................................... 7

2.1. Absolute Maximum Ratings..........................................................................................................7

2.2. Recommended Operating Conditions.......................................................................................... 7

2.3. Immunity.......................................................................................................................................7

2.4. Device Electrical Specifications....................................................................................................8

2.5. Port Real-Time Protection............................................................................................................ 8

2.6. Port Current Monitoring................................................................................................................9

2.7. Port Voltage Monitoring..............................................................................................................10

2.8. Main Voltage Monitoring.............................................................................................................10

2.9. Temperature Monitoring............................................................................................................. 10

2.10. Digital Interface...........................................................................................................................11

2.11. Detection.................................................................................................................................... 11

2.12. Classification.............................................................................................................................. 12

3. Pins....................................................................................................................................................... 13

3.1. Pin Diagrams..............................................................................................................................13

3.2. Pin Descriptions......................................................................................................................... 14

4. Application Information..........................................................................................................................16

4.1. Connection Check......................................................................................................................16

4.2. PD Detection.............................................................................................................................. 16

4.3. Legacy Detection........................................................................................................................16

4.4. Classification.............................................................................................................................. 16

4.5. Port Start-Up.............................................................................................................................. 16

4.6. Over-Load Detection and Port Shut-Down.................................................................................17

4.7. Disconnect Detection................................................................................................................. 17

4.8. IC Thermal Monitoring................................................................................................................17

4.9. Over-Temperature Protection.....................................................................................................17

DS00003428C-page 3

Datasheet

PD69208T4/PD69204T4/PD69208M

4.10. V_MAINOut-of-Range Protection.................................................................................................. 17

4.11. 2-Pair and 4-Pair Ports...............................................................................................................17

4.12. Port Power Limit.........................................................................................................................17

4.13. Port Matrix Control..................................................................................................................... 18

4.14. Power Good Interrupt.................................................................................................................18

4.15. Power Sequencing..................................................................................................................... 18

4.16. Ground....................................................................................................................................... 18

4.17. Voltage Regulator.......................................................................................................................19

4.18. SPI Communication....................................................................................................................19

5. Package Information............................................................................................................................. 21

5.1. Package Outline Drawing...........................................................................................................21

5.2. Thermal Specifications...............................................................................................................22

5.3. Recommended PCB Layout.......................................................................................................23

5.4. Recommended Solder Reflow Information.................................................................................26

5.5. Tape and Reel Specification.......................................................................................................28

5.6. Reference Documents................................................................................................................29

6. Ordering Information............................................................................................................................. 30

7. Revision History.................................................................................................................................... 31

The Microchip Website.................................................................................................................................32

Product Change Notification Service............................................................................................................32

Customer Support........................................................................................................................................ 32

Microchip Devices Code Protection Feature................................................................................................32

Legal Notice................................................................................................................................................. 33

Trademarks.................................................................................................................................................. 33

Quality Management System....................................................................................................................... 34

Worldwide Sales and Service.......................................................................................................................35

DS00003428C-page 4

Datasheet

PD69208T4/PD69204T4/PD69208M

Functional Descriptions

1.

Functional Descriptions

The following figure shows the functional blocks of the PD69208T4, PD69204T4, and PD69208M.

Figure 1-1.ꢀPSE Manager Block Diagram

1.1

Digital Block Module

The logic main control block includes digital timing mechanisms and state machines that synchronize and activate

PoE functions.

•

Real-Time Protection

Start-Up Macro

Load Signature Detection

Classification

Voltage and Current Monitoring

ADC interfacing

Direct digital signals with analog block

SPI communication block

Registers

1.2

1.3

PD Detection Generator

On request from the controller to the main control module, the PD detection generator generates four different

voltage levels to ensure a robust AF/AT/BT PD detection functionality.

Classification Generator

On request from the PD692x0 controller to the main control module, state machine applies a regulated class event

and mark event voltage to ports, as required by IEEE standards.

DS00003428C-page 5

Datasheet

PD69208T4/PD69204T4/PD69208M

Functional Descriptions

1.4

Current Limiter

This circuit continuously monitors the current of powered ports and limits the current to a pre-defined value set by

AF/AT/BT/PoH. When the current value exceeds this specific value, the system starts measuring the elapsed timing.

If this interval is greater than a preset threshold, the port is disconnected.

1.5

1.6

Main Power MOSFET

The main power switching FET is used to control PoE current into the load.

10-Bit ADC

A 10-bit analog to digital converter (ADC) is used to convert analog signals into digital registers for the logic control

module.

1.7

Power on Reset

Power on Reset (PoR) monitors the internal 3.3 V and 5 V DC levels. If this voltage drops below the specific

thresholds, a reset signal is generated and the manager is reset.

1.8

Voltage Regulator

The voltage regulator generates 3.3 V and 5 V for internal circuitry.

1.9

Oscillator

The manager’s clock (CLK) is an internal 8 MHz clock oscillator.

1.10

SPI Communication

The managers use SPI communication in SPI slave mode to communicate with the MCU. Each manager has an

address determined by ADDR0-ADDR3 pins. Addresses 0–11 are supported. The frequency between controller and

manager ICs is 1 MHz.

DS00003428C-page 6

Datasheet

PD69208T4/PD69204T4/PD69208M

Electrical Specifications

2.

Electrical Specifications

This section describes the electrical specifications of the PD69208T4, PD69204T4, and PD69208M devices.

2.1

Absolute Maximum Ratings

PoE performance is not guaranteed when exceeding the recommended rating. Exposure to any stress in the range

between the recommended rating, as listed in the following table, and the absolute maximum rating should be limited

to a short time. Exceeding these ratings may impact long-term operating reliability.

Table 2-1.ꢀAbsolute Maximum Ratings

Parameters

Min

Max

Units

1,2

Supply input voltage (V_MAIN

PORT_NEG[0.7]pins

V_AUX5

)

–0.3

72

V

V_MAIN+0.5

6

V_AUX3P3,DV_DD

4

Digital pins: MISO, MOSI, SCK, CS_N, ADDR[3:0], –0.3

PGD[3:0], RESET_N, TRIM

DV_DD+0.3 and <4.0

Absolute maximum junction temperature

Lead soldering temperature (40 s, reflow)

150

260

150

°C

Storage temperature

–65

1. Power sequence requirement: V_MAIN> V_AUX5> V_AUX3P3= TRIM, DVDD.

2. EPAD is connected by copper plane on PCB to AGND. AGND is ground for IC.

Note: DRV_VAUX5 and IREF are output pins and should not apply voltage or current. DRV_VAUX5 can be left open

when not used.

2.2

Recommended Operating Conditions

Table 2-2.ꢀOperating Conditions

Symbol

Parameter

Conditions

Min Typ Max Units

Maximum junction operating

temperature

125 °C

V_MAIN

Main supply voltage Supports full IEEE 802.3af/at/bt

functionality

44

57

V

2.3

Immunity

Table 2-3.ꢀImmunity

Symbol

Parameter

Conditions

HBM¹

Min

Typ

Max

Units

V

ESD

ESD rating

–2000

–500

–1

+2000

+500

1

CDM²

V

Surge

Lightning surge³

EN61000 4-5

kV

DS00003428C-page 7

Datasheet

PD69208T4/PD69204T4/PD69208M

Electrical Specifications

1. ESD HBM complies with JESD22 Class 2 standard.

2. ESD CDM complies with JESD22 Class 1 standard.

3. System-level common mode 10/700 µs according to IEC61000-4-5.

2.4

Device Electrical Specifications

If not specified under conditions, the Min and Max ratings stated in the following table apply to the entire specified

operating ratings of the device. Typ values stated are either by design or by production testing at 25 °C ambient.

Table 2-4.ꢀElectrical Specifications

Symbol

V_PORT

V_TH

Parameter

Conditions

Min

Typ

Max Units

Port output

V_MAIN–V_{PORT_NEGx}

0

57

V

POR threshold

Internal or external 3.3 V supply

8

V

I_MAIN

Main power supply current at

operating mode. V_MAIN= 55 V

14

mA

V_AUX5

5 V output voltage

V_AUX5–AGND

4.5

3

5

5.5

3.6

5

V

V_AUX3P3

I_AUX3P3

Internal 3.3 V output voltage

V_AUX3P3–AGND

Without external NPN

3.3

V

3.3 V output current for application

use

mA

With external NPN transistor on

V_AUX5

30

V_{AUX3P3_IN}3.3 V input voltage

V_AUX3P3–AGND

DV_DD–DGND

3

3.3

3.6

V

DV_DD

Digital 3.3 V input voltage

POR_TP

POR_HYS

R_{CH_ON}

PPWR

Power-on reset DVDD trip point

Power-on reset DVDD hysteresis

Total channel resistance

DV_DD–DGND

2.575 2.775 2.975 V

POR_TP–DGND

R_{ds_on}+ R_sense+ R_bonding

>90 W

0.2

0.25 0.3

V

0.34

2

Ω

%

Port power accuracy

2.5

Port Real-Time Protection

Table 2-5.ꢀPort Real-Time Protection

Symbol Parameter

Conditions

Min Typ Max Units

15 µs

T_RISE

Turn-on rise time

From 10% to 90% of the voltage

difference at the VPORT_NEGx in

POWER_ON state from the beginning of

POWER_UP

I_INRUSHOutput current in POWER_UP state CLOAD ≤ 180 µF¹

T_INRUSHInrush time

400 425 450 mA

65 ms

DS00003428C-page 8

Datasheet

PD69208T4/PD69204T4/PD69208M

Electrical Specifications

...........continued

Symbol Parameter

Conditions

Min Typ Max Units

I_PORT

Output operating current

802.3af

10

360 mA

620 mA

560 mA

692 mA

794 mA

948 mA

mA

802.3at

802.3bt class 5

802.3bt class 6

802.3bt class 7

802.3bt class 8

802.3af

I_CUT

Overload current

375

645

589

709

825

980

64

802.3at

mA

802.3bt class 5

802.3bt class 6

802.3bt class 7

802.3bt class 8/PoH²

mA

T_CUT

I_LIM

Overload time limit

Port current limit

62

66

ms

802.3af

400 425 450 mA

670 720 770 mA

790 850 892 mA

1020 1150 1300 mA

802.3bt class 1–3

802.3at, 802.3bt class 4–6

802.3bt class 7–8/PoH

V_MAIN–V_{PORT_NEGx}<30 V

2 pairs

T_LIM

I_UDL

Port current limit time

1

6

2

3

9

3

ms

mA

DC disconnect under-load current

7.5

2.5

4 pairs IEEE 802.3bt (for each pair-set)

T_MPDOPD maintain power signature

dropout time limit

322 324 326 ms

T_MPS

PD maintain power

Signature time for validity

Turn off time

802.3bt PSE Type 1, 2

802.3bt PSE Type 3, 4

From V_MAINto 2.8 V

46

3

48

4

50

5

ms

T_OFF

500 ms

1. Can be overridden by communication command.

2. The power port is limited to the maximum of 100 W according to UL’s LPS requirements (Port Power = I_PORT

V_MAIN).

×

2.6

Port Current Monitoring

Table 2-6.ꢀPort Current Monitoring

Symbol

Conditions

Typ

10

Max

Units

Bits

µA

Resolution

LSB

Reported as 14 bits

122.07

16

Measurement period

mS

DS00003428C-page 9

Datasheet

PD69208T4/PD69204T4/PD69208M

Electrical Specifications

...........continued

Symbol

Conditions

Typ

Max

9

Units

%

Accuracy

50 mA < I_PORT< 150 mA

150 mA < I_PORT< 350 mA

4.5

3.5

3.0

1.5

%

I_PORT> 350 mA (PD69208M)

350 mA < I_PORT< 600 mA (PD6920xT4)

600 mA < I_PORT< 800 mA (PD6920xT4)

I_PORT> 800 mA (PD6920xT4)

%

2.7

Port Voltage Monitoring

Table 2-7.ꢀPort Voltage Monitoring

Symbol

Conditions

Typ

10

Max

Units

Resolution

LSB

Bits

mV

ms

%

58.6

3

Measurement period

Accuracy

3.3

2.8

Main Voltage Monitoring

Table 2-8.ꢀMain Voltage Monitoring

Symbol

Conditions

Typ

Max

Units

Bits

mV

ms

%

Resolution

10

58.6

3

LSB

Measurement period

Accuracy (PD69208T4-PD69204T4)

42 V < V_MAIN< 50 V

50 V < V_MAIN< 57 V

50 V < V_MAIN< 57 V¹

42 V < V_MAIN< 50 V

50 V < V_MAIN< 57 V

2.1

1.5

0.6

3.0

2.2

%

Accuracy (PD69208M)

1. 0 °C–70 °C

%

2.9

Temperature Monitoring

Table 2-9.ꢀTemperature Monitoring

Symbol

Resolution

LSB

Conditions

Min

Typ

8

Max

Units

Bits

°C

Temperature = (DATA x 1.9384)–277

1.9384

DS00003428C-page 10

Datasheet

PD69208T4/PD69204T4/PD69208M

Electrical Specifications

...........continued

Symbol

Conditions

Min

Typ

Max

Units

ms

Measurement period

Accuracy

3

–3

3

°C

2.10

Digital Interface

Table 2-10.ꢀDigital Interface

Symbol Parameter

Conditions

Min Typ Max Units

V_IH

V_IL

Hyst

I_IH

Input logic high voltage

RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3],

ADDR[0..3]

2.2

V

Input logic low voltage

RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3],

ADDR[0..3]

0.8

V

Input logic hysteresis voltage RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3],

ADDR[0..3]

0.4 0.6 0.8

V

Input logic high current

Input logic low current

Output logic high voltage

RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3], –10

ADDR[0..3]

10

µA

V

I_IL

RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3], –10

ADDR[0..3]

V_OH

RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3],

2.4

ADDR[0..3]

I_OH= –1 mA

V_OL

Output logic low voltage

RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3],

0.4

V

ADDR[0..3]

I_OH= 1 mA

2.11

Detection

Table 2-11.ꢀDetection

Symbol Parameter

Conditions

Min Typ Max Units

V_OC

Pre-detection voltage, open-circuit

V_MAIN–V_{PORT_NEGx}, open port

7.8

V

voltage

V_VALID

Detection voltage

V_MAIN–V_{PORT_NEGx}, for IEEE 802.3

compliant signature resistance

(RSIG <33 K)

9.3

V

I_SC

Short circuit current

V_MAIN–V_{PORT_NEGx}= 0 V

388 408 µA

R_{SIG_LOW}Minimum valid detection resistance

R_{SIG_HIGH}Maximum valid detection resistance

15

19

33

kΩ

26.5

DS00003428C-page 11

Datasheet

PD69208T4/PD69204T4/PD69208M

Electrical Specifications

2.12

Classification

Table 2-12.ꢀClassification

Symbol

V_CLASS

V_MARK

Parameter

Conditions

Min Typ Max Units

Class event output voltage

Mark event output voltage

V_MAIN–V_{PORT_NEGx}; 0 mA ≤ I_PORT≤ 50 mA

V_MAIN–V_{PORT_NEGx}; 0.1 mA ≤ I_PORT≤ 5 mA

V_MAIN–V_{PORT_NEGx}= 0 V

15.5 18 20.5 V

7

8.5 10

V

I_{CLASS_LIM}Class event current limitation

I_{MARK_ LIM}Mark event current limitation

51 70 100 mA

V_MAIN–V_{PORT_NEGx}= 0 V

Classification current thresholds Class 0

0

5

mA

Class 1

Class 2

Class 3

Class 4

Class Error

8

13

21

31

45

16

25

35

51

100 mA

DS00003428C-page 12

Datasheet

PD69208T4/PD69204T4/PD69208M

Pins

3.

Pins

This section provides pin diagrams and pin descriptions for the PD69208T4, PD69204T4, and PD69208M devices.

3.1

Pin Diagrams

Figure 3-1.ꢀPin Diagram Top View

DS00003428C-page 13

Datasheet

PD69208T4/PD69204T4/PD69208M

Pins

3.2

Pin Descriptions

The following table describes the functional pins of the PD69208T4, PD69208M, and PD69204T4 Managers.

Table 3-1.ꢀPin Descriptions

Designator

Type

Description

EPAD

Exposed PAD. Connect to analog ground. GND

must have sufficient copper mass on bottom or

top layer to ensure adequate thermal

performance.

1,18,45

2

N.C.

TST

N/A

Not connected. Leave floating.

Digital input

Test pin for production use only. Connect to

DGND.

3,4

VPORT_NEG0

RESERVED

Analog I/O

N/A

Negative port 0 output.

5,8,11,

14,16,

26,27,

29,32,

35,38

Reserved pin. Do not connect externally.

6,7

VPORT_NEG1

VPORT_NEG2

VPORT_NEG3

AGND

Analog I/O

Power

Negative port 1 output.

Negative port 2 output.

Negative port 3 output.

Analog ground.

9,10

12,13

15,21,28

17

VMAIN

Power

Main high voltage supply voltage. A low ESR 1 µF

(or higher) bypass capacitor, connected to AGND,

should be placed as close as possible to this pin

through low resistance traces.

19

20

22

23

DRV_VAUX5

VAUX5

Power

Driven outputs for 5 V external regulation; if

internal regulation is used, connect to pin 20. If an

external NPN is used to regulate the voltage,

connect this pin to Base and connect 4.7 µF

capacitor between this pin and AGND.

Powered by regulated 5 V. Connect 4.7 µF or

higher capacitor between this pin and AGND. If an

external NPN is used to regulate the voltage,

connect this pin to the emitter. The collector

should be connected to V_MAIN

.

VAUX3P3

Powered by regulated 3.3 V. A 4.7 µF or higher

filtering capacitor should be connected between

this pin and AGND. When an external 3.3 V

regulator is used, connect it to this pin to supply

the chip.

VAUX3P3_INT

Connected to V_AUX3P3(pin 22) if internal 3.3 V

regulator is used. Leave unconnected (Floating) if

external 3.3 V regulator is used.

DS00003428C-page 14

Datasheet

PD69208T4/PD69204T4/PD69208M

Pins

...........continued

Designator

Type

Description

24

IREF

Analog input

Reference resistor pin. Connect a 28.7 kΩ 1%

resistor to AGND. Use 0.1% resistor in BT/PoH

applications.

25

TRIM

Test input

Test input pin. Keep connected to V_AUX3P3

.

30,31

VPORT_NEG4

Analog I/O

PD69208M/T4: Negative port 4 output.

PD69204T4: Not connected, leave floating.

33,34

36,37

39,40

VPORT_NEG5

VPORT_NEG6

VPORT_NEG7

Analog I/O

PD69208M/T4: Negative port 5 output.

PD69204T4: Not connected, leave floating.

PD69208M/T4: Negative port 6 output.

PD69204T4: Not connected, leave floating.

PD69208M/T4: Negative port 7 output.

PD69204T4: Not connected, leave floating.

41

42

43

PGD1

DGND

DVDD

Digital input

Power

Power good input from the system power supply.

Digital ground.

Power in

Regulated 3.3 V for digital circuitry. Connect

voltage from pin V_AUX3P3or from external power

supply source if used. A 1 µF or higher filtering

capacitor should be connected between this pin

and DGND.

44

RESET_N

Digital input

Reset input - active low (0 = reset). An external 10

kΩ pull-up resistor should be connected between

this pin and DV_DD

.

46

47

48

49

50

51

52

53

54

55

56

PGD2

PGD3

ADDR0

ADDR1

ADDR2

ADDR3

CS_N

SCK

Digital input

Digital output

Digital input

Power good input from the system power supply.

SPI address bit 0 to set chip address.

SPI address bit 1 to set chip address.

SPI address bit 2 to set chip address.

SPI address bit 3 to set chip address.

SPI bus, chip select.

SPI bus, serial clock input.

MOSI

SPI bus, master data out/slave in.

MISO

SPI bus, master data in/slave out.

PGD0

Power good input from the system power supply.

An adequate ground plane on a bottom or top layer is required for adequate thermal performance. See AN3361

Designing an IEEE 802.3af/802.3at/802.3bt-Compliant PD69208 48-Port PoE System for additional details.

DS00003428C-page 15

Datasheet

PD69208T4/PD69204T4/PD69208M

Application Information

4.

Application Information

This section describes the application information of the PD69208T4, PD69204T4, and PD69208M devices.

4.1

Connection Check

An additional PD construction detection phase named, connection check, is done to detect which PD configuration is

connected (single-signature or dual-signature) per the IEEE 802.3bt standard.

4.2

PD Detection

The PD detection feature detects a valid IEEE 802.3af, IEEE 802.3at, or IEEE802.3bt. The PD detection is done

based on four different voltage levels to ensure robust detection, as shown in the Typical IEEE 802.3bt Port PoE

Voltage Diagram.

4.3

4.4

Legacy Detection

When legacy detection is enabled, the PD detection mechanism detects and powers up the legacy and pre-standard

PDs as well as IEEE 802.3af, IEEE 802.3at and IEEE 802.3bt standard compliant PDs (Classes 0–8).

Classification

The classification process takes place immediately after PD detection is successfully completed. The goal of the

classification process is to detect PD class as specified in IEEE 802.3 standards.

In IEEE 802.3af mode, the classification mechanism is based on a single voltage level (single event). In IEEE 802.3at

and IEEE 802.3bt modes, the classification mechanism is based on two voltage levels (multiple events) as defined in

IEEE 802.3-2015 Clause 33 and IEEE 802.3bt. In PoH mode, the classification mechanism is based on three events

classification as defined in HDBaseT standard.

Figure 4-1.ꢀTypical IEEE 802.3bt Port PoE Voltage Diagram

4.5

Port Start-Up

Upon a successful detection and classification process, power is applied to the load through a controlled start-up

mechanism.

DS00003428C-page 16

Datasheet

PD69208T4/PD69204T4/PD69208M

Application Information

During this period, inrush current is limited to ILIM for a duration of TLIM (as specified in the table Port Real-Time

Protection), which allows PD load to charge and allows a steady state of power condition.

4.6

4.7

4.8

Over-Load Detection and Port Shut-Down

After power-up, the PSE manager automatically initializes its internal protection mechanisms. These mechanisms are

used to monitor and disconnect power from the PD when extreme conditions occur. These conditions include over-

current or short ports terminals scenarios.

Disconnect Detection

The managers support the DC disconnect function as per IEEE 802.3 standards. This mechanism continuously

monitors load current and disconnects power according to IUDL, TMPDO, and TMPS parameters as specified in Port

Real-Time Protection.

IC Thermal Monitoring

The managers contains a thermal sensor that is sampled by the controller so that the manager die temperature is

monitored at all times. To protect the PSE manager from damage, the system ports are disconnected before damage

can occur.

A temperature alarm threshold can be set by the controller to send interrupt indication by the xINT_OUT pin before

ports are disconnected. The temperature can be read and monitored by the host as well if required.

4.9

Over-Temperature Protection

In addition to the die thermal sensor, there are thermal sensors on each MOSFET that continuously monitors each

port main MOSFETs junction temperature, and shuts down the port load power when the temperature exceeds the

threshold.

4.10

4.11

V_MAINOut-of-Range Protection

The system automatically disconnects ports power when V_MAINexceeds the pre-configured over-voltage and under-

voltage thresholds.

2-Pair and 4-Pair Ports

Operation modes include the following:

•

PoE Type 1/2 class 0–4 (up to 30 W)

PoE Type 3 class 0–4 2-Pair and class 5–6 4-Pair (up to 60 W)

PoE Type 4 class 7/8 4-Pair (75 W/90 W)

POH Mode: 4-Pair (up to 95 W)

Note: For more information about 4-Pair operation modes and power, see Microchip AN3361.

4.12

Port Power Limit

Port power limit (PPL) is used to configure port power limit. When a port exceeds the power limit, it gets disconnected

automatically.

DS00003428C-page 17

Datasheet

PD69208T4/PD69204T4/PD69208M

Application Information

4.13

4.14

Port Matrix Control

Port matrix control enables layout designers to ascribe each physical port in the system to a logical port if required.

Power Good Interrupt

Interrupt from power supply directly to the manager. For systems comprising more than a single power supply, in

case one power supply fails, a port shutdown mechanism is executed to maintain operation and prevent the collapse

of other power supplies.

When a function is used, PGD0, PGD1, PGD2, and PGD3 should be connected to the main power supplies status

indication pin. Any change of at least 1 µs on these lines triggers a pre-defined disconnection matrix. This matrix is

defined by the PSE controller system power parameters. The port shutdown function reacts within 2 µs to any power

good event.

4.15

Power Sequencing

Figure 4-2.ꢀPower Sequencing

For proper operation, ensure that V_MAINis always the highest voltage connected to the IC.

With an external 5 V and/or 3.3 V supply:

•

V_aux5pin voltage should never be above V_MAINpin voltage.

V_aux3p3pin voltage should never be above V_aux5pin voltage.

The maximum 3.3 V slew rate is 100 ms.

Td1: V_MAINshould be raised before or at the same time as 5 V.

Td2: 5 V should be raised before or at the same time as 3.3 V.

Td3: 3.3 V should be dropped before or at the same time as 5 V.

Td4: 5 V should be dropped before or at the same time as V_MAIN

.

For details about PD69208 5 V and 3.3 V power supply connection options, see AN3361 Designing an IEEE^®

802.3af/at/bt PoE System Based on PD692x0/PD69208.

4.16

Ground

The digital ground and analog ground should be tied together on the board.

DS00003428C-page 18

Datasheet

PD69208T4/PD69204T4/PD69208M

Application Information

4.17

Voltage Regulator

The voltage regulator generates 3.3 V and 5 V for internal circuitry. These voltages are derived from V_MAINsupply. To

use the internal voltage regulator connect:

•

V_AUX5to DRV_VAUX5

V_AUX3P3to VAUX3P3_INT

There are three options to reduce the managers’ power dissipation by regulating voltage outside the chip.

•

Use an external NPN transistor to regulate the 5 V. In this setup, the configuration of regulators pins should be

as follows.

– DRV_VAUX5 is connected to NPN BASE

– V_AUX5is connected to NPN EMITTER (Connect Collector to V_MAIN

)

– V_AUX3P3is connected to VAUX3P3_INT

•

Supply the manager with an external 5 V voltage regulator. In this setup, regulators pins configuration should be

as follows.

– V_AUX3P3is connected to VAUX3P3_INT

– DRV_VAUX5 is not connected (left open)

– V_AUX5is connected to external 5 V

Supply the manager with an external 3.3 V voltage regulator. In this setup, regulators pins configuration should

be as follows.

– V_AUX5is connected to DRV_VAUX5

– VAUX3P3_INT is not connected (left open)

– V_AUX3P3is connected to external 3.3 V

4.18

SPI Communication

The following table lists the SPI communication packet structure.

Table 4-1.ꢀSPI Communication—Packet Structure

Control Byte

Selects Manager

According to

Address

R/W Bit

Internal

Address

Register Number of Words

Data Written to IC

(Read Access Only) (Write Access Only)

Read from IC (Read

Access Only)

8 bits

R(0)/W(1)

8 bits

16 bits

4.18.1 SPI Addressing

The manager operates in the 8-bit address and 16-bit data. It responds to SPI transaction if the first SPI byte (IC

address byte bits[7:1]) complies with the following.

Table 4-2.ꢀManager SPI Addressing

3 Bits (bit 7:5)

4 Bits (bit 4:1)

1 Bit (bit 0)

000

Address Input Pin

Read/Write

4.18.2 Broadcast

A broadcast command is intended to instruct all connected manager ICs to perform a specific operation.

The broadcast command is a write command with the standard packet structure. In a broadcast read operation, the

read data is not valid and the read operation has no impact.

DS00003428C-page 19

Datasheet

PD69208T4/PD69204T4/PD69208M

Application Information

Table 4-3.ꢀManager Broadcast

3 Bits (bit 7:5)

4 Bits (bit 4:1)

0000

1 Bit (bit 0)

001

Write

Figure 4-3.ꢀSPI Timing Diagram

Table 4-4.ꢀSPI Timing Diagram Description

Name Min Delay

Max Delay

Description

D1

D2

D3

910 ns

45%

SPI clock period

SPI duty cycle

55%

340 ns

SPI_CS setup to SPI clock positive edge (delay after SPI_CS active

signal)

D4

D5

340 ns

SPI_CS hold to SPI clock positive edge (delay before SPI_CS

inactive signal)

2 SPI clock cycles

Delay between last SCK in SPI1 frame and first SCK at adjacent

SPI1 frame

D6

1 SPI clock cycle

340 ns

Between byte 0 (IC address) and byte 1 (address)

Between byte 1 (address) and byte 2 (data)

Between byte 2 (MS data byte) and byte 3 (LS data byte)

MOSI setup time

D7

D8

D9

D10

D11

D12

D13

D14

D15

340 ns

MOSI hold time

700 ns

MISO tri-state to valid data from clock positive edge

MISO valid data to tri-state from SPI_CS positive edge

SPI_CS width (Delay SPI1 frame to adjacent SPI1 frame)

Filtered glitch width

1 SPI clock cycle

60 ns

D3 + D11 + 24

SPI clock

cycles

MISO tri-state from SPI_CS negative edge to valid data

D16

D17

200 ns

MISO setup to SCK positive edge

MISO hold to SCK positive edge

DS00003428C-page 20

Datasheet

PD69208T4/PD69204T4/PD69208M

Package Information

5.

Package Information

This section describes the package of the PD69208T4, PD69204T4, and PD69208M devices.

5.1

Package Outline Drawing

The following figure shows the package drawing of the PD69208T4, PD69204T4, and PD69208M package.

Figure 5-1.ꢀPD69208T4 Package Drawing (56 Pin QFN 8 mm × 8 mm)

The following table lists the dimensions and measurements of the PD69208T4 package.

Table 5-1.ꢀPackage Outline Dimensions and Measurements

Dimension

Millimeters

Min

Inches

Min

Max

1.00

0.05

Max

A

0.80

0.031

0.039

0.002

A1

A3

K

0.00

0

0.20 REF

0.20 MIN

0.50 BSC

0.30

0.008 REF

0.008 MIN

0.02 BSC

0.012

e

L

0.50

0.30

6.75

0.02

b

0.18

0.007

0.012

0.267

D2

E2

D

6.50

0.256

6.50

0.256

8.00 BSC

0.315 BSC

E

Note: Dimensions do not include protrusions; they should not exceed 0.155 mm (0.006 in.) on any side. Lead

dimension should not include solder coverage. Dimensions are in millimeters and inches for reference.

DS00003428C-page 21

Datasheet

PD69208T4/PD69204T4/PD69208M

Package Information

5.2

Thermal Specifications

The following tables list the thermal specifications the PD69208T4, PD69204T4, and PD69208M.

Table 5-2.ꢀThermal Specifications

Thermal Resistance

Typ

19.0

0.05

Units

°C/W

Notes

θ_JA

Junction-to-ambient thermal resistance.

Ψ_JT

Junction-to-top thermal characterization parameter. A

thermal metric derived from the difference in junction

temperature (TJ) and package top temperature (TT)

divided by total heating power (PH).

θ_JC(top)

4.9

°C/W

Junction-to-case thermal resistance with heat flow through

package top.

θ_JB

15.2

Junction-to-board thermal resistance.

Note: All parameters are as per JEDEC JESD-51.

DS00003428C-page 22

Datasheet

PD69208T4/PD69204T4/PD69208M

Package Information

5.3

Recommended PCB Layout

The following figures show the recommended PCB layout for a PD69208T4, PD69204T4, and PD69208M 56-pin

QFN 8 mm × 8 mm package. Units are in mm (mils).

Figure 5-2.ꢀTop-Copper Layer

DS00003428C-page 23

Datasheet

PD69208T4/PD69204T4/PD69208M

Package Information

Figure 5-3.ꢀTop-Solder Paste Layer

0.2797[11.0118]

0.6209[24.4449]

1.9200[75.5906]

2.2700[89.3701]

3.8900[153.1496]

4.2100[165.7480]

6.1300[241.3386]

7.0203[276.3898]

8.2797[325.5906]

DS00003428C-page 24

Datasheet

PD69208T4/PD69204T4/PD69208M

Package Information

Figure 5-4.ꢀSolder Mask

Figure 5-5.ꢀBOT and Internal Layers Copper Plane

DS00003428C-page 25

Datasheet

PD69208T4/PD69204T4/PD69208M

Package Information

Figure 5-6.ꢀTop-Layer Pin Geometry

0.8048[31.6850]

0.7523[29.6181]

0.6209[24.4449]

0.0254[1.0000]

0.0356[1.4016]

Paste

Metal

Mask

Note: The contract manufacturer has latitude to modify the solder paste stencil for manufacturability reasons. The

solder paste stencil covers 65% to 80% of the thermal pad and should not allow solder to be applied to the thermal

vias under the QFN package using any method they deem appropriate. Any design should be subject to system

validation and qualification prior to commitment to mass production of field deployment. Use a 5 mil stencil.

5.4

Recommended Solder Reflow Information

RoHS 6/6

Pb-free 100% Matte Tin Finish

Package Peak Temperature for Solder Reflow (40 s maximum exposure)—260 °C (0 °C, –5 °C)

DS00003428C-page 26

Datasheet

PD69208T4/PD69204T4/PD69208M

Package Information

Table 5-3.ꢀClassification Reflow Profiles

Profile Feature

Sn-Pb Eutectic Assembly

Pb-Free Assembly

Average ramp-up rate (TS_maxto Tp)

Preheat

3 °C/second max

Temperature min (TS_min

)

100 °C

150 °C

Temperature max (TS_max

)

150 °C

200 °C

Time (ts_minto ts_max

)

60 s to 120 s

60 s to 180 s

Time Maintained

Temperature (T_L)

Time (t_L)

183 °C

217 °C

60 s to 150 s

Peak classification temperature (TP)

210 °C to 235 °C

10 s to 30 s

240 °C to 255 °C

20 s to 40 s

Time within 5 °C of actual peak temperature

(tp)

Ramp-down rate

6 °C/second max

6 minutes max

6 °C/second max

8 minutes max

Time 25 °C to peak temperature

Figure 5-7.ꢀClassification Reflow Profiles

Table 5-4.ꢀPb-Free Process—Package Classification Reflow Temperatures

Package Thickness

Volume <350 mm³

Volume 350–2000 mm³

Volume >2000 mm³

Less than 1.6 mm¹

1.6 mm to 2.5 mm¹

260 + 0 °C

250 + 0 °C

260 + 0 °C

250 + 0 °C

245 + 0 °C

260 + 0 °C

245 + 0 °C

Greater than or equal to

2.5 mm¹

1. Tolerance: The device manufacturer or supplier should assure process compatibility up to and including the

stated classification temperature, meaning that the Peak reflow temperature is +0 °C. For example, 260 °C to

0 °C, at the rated MSL value.

Note: Exceeding the ratings that are mentioned in the preceding table might cause damage to the device.

DS00003428C-page 27

Datasheet

PD69208T4/PD69204T4/PD69208M

Package Information

5.5

Tape and Reel Specification

This section provides the tape and reel specifications.

Figure 5-8.ꢀTape and Reel Pin-1 Orientation

Figure 5-9.ꢀTape Specifications

Table 5-5.ꢀTape Mechanical Data

Dimension

A0

Value (mm)

8.35 ±0.10

1.40 ±0.10

N/A

B0

K0

K1

Pitch

Width

12.00 ±0.10

16.00 ±0.30

DS00003428C-page 28

Datasheet

PD69208T4/PD69204T4/PD69208M

Package Information

Figure 5-10.ꢀReel Specifications

Table 5-6.ꢀReel Mechanical Data

Dimensions

Tape size

A max.

B max.

C

Value (mm)

16.00 ±0.3

330

Value (inch)

0.630 ±0.012

13

1.5

0.059

13.0 ±0.20

20.2

0.512 ±0.008

0.795

D min.

N min.

G

50

1.968

16.4+2.0/–0.0

29

0.724 to 0.645

1.142

T max.

Base quantity: 2000 pieces

5.6

Reference Documents

•

IEEE Std 802.3-2018 Clause 33 Power over Ethernet over 2-Pair and Clause 145 Power over Ethernet

PD692x0_Serial Communication Protocol User Guide

Microchip AN3361 Designing an IEEE 802.3af/802.3at/802.3bt-Compliant PD69208 48-Port PoE System

AN3378 Surge Protection Application Note 8-Port PSE PoE Manager PD69208T4/M/4T4

PD692x0+PD69208M/208T4/204T4 Implementing Perpetual PoE (PPoE) and Fast PoE

PD69210, PD69220 & PD39210 PoE PSE Controller Data Sheet

PD69200 PoE PSE Controller Data Sheet

DS00003428C-page 29

Datasheet

PD69208T4/PD69204T4/PD69208M

Ordering Information

6.

Ordering Information

The following table lists the part ordering information for the manager ICs.

Table 6-1.ꢀOrdering Information

Part Number

Package

Packaging Type

Temperature

Part Marking

Microsemi Logo

PD69208T4

L E e4¹

PD69208T4ILQ-TR-LE

Plastic QFN

8 mm × 8 mm

(56 lead)

Tape and Reel

–40 °C to 85 °C

YYWWNNN²

PD69204T4ILQ-TR-LE

PD69208MILQ-TR-LE

Plastic QFN

8 mm × 8 mm

(56 lead)

Tape and Reel

–40 °C to 85 °C

Microsemi Logo

PD69204T4

L E e4¹

YYWWNNN²

Plastic QFN

8 mm × 8 mm

(56 lead)

Microsemi Logo

PD69208M

L E e4¹

YYWWNNN²

1. L= FAB code; E= V2R4; and e4= second-level interconnect.

2. YY= Year; WW= Week; and NNN= Trace code.

Note: The package meets RoHS, Pb-free of the European Council to minimize the environmental impact of electrical

equipment.

The following table lists the manufacturing and ordering part numbers of the manager devices.

Table 6-2.ꢀManufacturing and Ordering Part Numbers

Ordering Part Number

PD69208T4ILQ-TR-LE

PD69204T4ILQ-TR-LE

PD69208MILQ-TR-LE

Manufacturing Part Number

PD69208T4ILQ-TR-LE

PD69204T4ILQ-TR-LE

PD69208MILQ-TR-LE

DS00003428C-page 30

Datasheet

PD69208T4/PD69204T4/PD69208M

Revision History

7.

Revision History

Revision

Date

Section

Description

C

11/2020

Power Sequencing

•

Updated text.

Ordering Information

Typical PoE Application

Updated "5 mm x 5 mm" to "8 mm x 8 mm".

Updated block diagram.

B

7/2020

Recommended PCB

Layout

Updated all five diagrams.

Main Voltage Monitoring

•

Corrected error to align with actual system

performance.

Port Current Monitoring

Indicated which conditions are for PD69208M or

PD6920xT4.

A

4/2020

This is the initial issue of this document. The

PD69208T4, PD69204T4, and PD69208M PoE PSE

managers were previously described in the following

documents:

•

PD69208T4 and PD69210 Datasheet (Revision 3