PIC10F220I/OT_技术文档

PIC10F220/222

Data Sheet

High-Performance Microcontrollers

with 8-bit A/D

DS41270E

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

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OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

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conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable

Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The

Embedded Control Solutions Company are registered

trademarks of Microchip Technology Incorporated in the

U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,

MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select

Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,

WiperLock and ZENA are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS41270E-page ii

PIC10F220/222

6-Pin, 8-Bit Flash Microcontrollers

Device Included In This Data Sheet:

Low-Power Features/CMOS Technology:

• PIC10F220

• PIC10F222

• Operating Current:

- < 175 μA @ 2V, 4 MHz

• Standby Current:

High-Performance RISC CPU:

- 100 nA @ 2V, typical

• Low-Power, High-Speed Flash Technology:

- 100,000 Flash endurance

- > 40-year retention

• Only 33 Single-Word Instructions to Learn

• All Single-Cycle Instructions Except for Program

Branches which are Two-Cycle

• Fully Static Design

• 12-bit Wide Instructions

• Wide Operating Voltage Range: 2.0V to 5.5V

• Wide Temperature Range:

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

• 2-Level Deep Hardware Stack

• Direct, Indirect and Relative Addressing modes

for Data and Instructions

• 8-bit Wide Data Path

• 8 Special Function Hardware Registers

• Operating Speed:

Peripheral Features:

- 500 ns instruction cycle with 8 MHz internal

clock

• 4 I/O Pins:

- 3 I/O pins with individual direction control

- 1 input only pin

- 1 μs instruction cycle with 4 MHz internal

clock

- High current sink/source for direct LED drive

- Wake-on-change

Special Microcontroller Features:

- Weak pull-ups

• 4 or 8 MHz Precision Internal Oscillator:

- Factory calibrated to ±1%

• 8-bit Real-Time Clock/Counter (TMR0) with 8-bit

Programmable Prescaler

• In-Circuit Serial Programming™ (ICSP™)

• In-Circuit Debugging (ICD) Support

• Power-On Reset (POR)

• Analog-to-Digital (A/D) Converter:

- 8-bit resolution

- 2 external input channels

- 1 internal input channel dedicated

• Short Device Reset Timer, DRT (1.125 ms typical)

• Watchdog Timer (WDT) with Dedicated On-Chip

RC Oscillator for Reliable Operation

• Programmable Code Protection

• Multiplexed MCLR Input Pin

• Internal Weak Pull-Ups on I/O Pins

• Power-Saving Sleep mode

• Wake-up from Sleep on Pin Change

Program Memory

Flash (words)

Data Memory

Timers

8-bit

Device

I/O

8-Bit A/D (ch)

SRAM (bytes)

PIC10F220

PIC10F222

256

512

16

23

4

1

2

DS41270E-page 1

PIC10F220/222

6-Lead SOT-23 Pin Diagram

1

2

6

5

GP0/AN0/ICSPDAT

GP3/MCLR/VPP

VDD

VSS

3

4

GP1/AN1/ICSPCLK

GP2/T0CKI/FOSC4

8-Lead DIP Pin Diagram

GP3/MCLR/VPP

VSS

1

N/C

VDD

8

7

6

5

2

3

4

N/C

GP2/T0CKI/FOSC4

GP1/AN1/ICSPCLK

GP0/AN0/ICSPDAT

8-Lead DFN Pin Diagram

N/C

VDD

8

1

GP3/MCLR/VPP

VSS

7

6

5

2

3

4

GP2/T0CKI/FOSC4

GP1/AN1/ICSPCLK

N/C

GP0/AN0/ICSPDAT

DS41270E-page 2

PIC10F220/222

Table of Contents

1.0 General Description...................................................................................................................................................................... 5

2.0 Device Varieties .......................................................................................................................................................................... 7

3.0 Architectural Overview ................................................................................................................................................................. 9

4.0 Memory Organization................................................................................................................................................................. 13

5.0 I/O Port....................................................................................................................................................................................... 21

6.0 TMR0 Module and TMR0 Register............................................................................................................................................. 25

7.0 Analog-to-Digital (A/D) converter ............................................................................................................................................... 29

8.0 Special Features Of The CPU.................................................................................................................................................... 33

9.0 Instruction Set Summary............................................................................................................................................................ 43

10.0 Electrical Characteristics............................................................................................................................................................ 51

11.0 Development Support................................................................................................................................................................. 61

12.0 DC and AC Characteristics Graphs and Charts......................................................................................................................... 69

13.0 Packaging Information................................................................................................................................................................ 73

Index .................................................................................................................................................................................................... 79

The Microchip Web Site....................................................................................................................................................................... 81

Customer Change Notification Service ................................................................................................................................................ 81

Customer Support................................................................................................................................................................................ 81

Reader Response................................................................................................................................................................................ 82

Product Identification System .............................................................................................................................................................. 83

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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

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An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

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DS41270E-page 3

PIC10F220/222

NOTES:

DS41270E-page 4

PIC10F220/222

1.1

Applications

1.0

GENERAL DESCRIPTION

The PIC10F220/222 devices fit in applications ranging

from personal care appliances and security systems to

low-power remote transmitters/receivers. The Flash

technology makes customizing application programs

(transmitter codes, appliance settings, receiver fre-

quencies, etc.) extremely fast and convenient. The

small footprint packages, for through hole or surface

mounting, make these microcontrollers well suited for

applications with space limitations. Low-cost, low-

power, high-performance, ease-of-use and I/O flexibil-

ity make the PIC10F220/222 devices very versatile,

even in areas where no microcontroller use has been

considered before (e.g., timer functions, logic and

PLDs in larger systems and coprocessor applications).

The PIC10F220/222 devices from Microchip

Technology are low-cost, high-performance, 8-bit, fully-

static Flash-based CMOS microcontrollers. They

employ a RISC architecture with only 33 single-word/

single-cycle instructions. All instructions are single-

cycle (1 μs) except for program branches, which take

two cycles. The PIC10F220/222 devices deliver perfor-

mance in an order of magnitude higher than their com-

petitors in the same price category. The 12-bit wide

instructions are highly symmetrical, resulting in a

typical 2:1 code compression over other 8-bit

microcontrollers in its class. The easy-to-use and easy

to remember instruction set reduces development time

significantly.

The PIC10F220/222 products are equipped with spe-

cial features that reduce system cost and power

requirements. The Power-on Reset (POR) and Device

Reset Timer (DRT) eliminates the need for the external

Reset circuitry. INTOSC Internal Oscillator mode is pro-

vided, thereby, preserving the limited number of I/O

available. Power-Saving Sleep mode, Watchdog Timer

and code protection features improve system cost,

power and reliability.

The PIC10F220/222 devices are available in cost-

effective Flash, which is suitable for production in any

volume. The customer can take full advantage of

Microchip’s price leadership in Flash programmable

microcontrollers while benefiting from the Flash

programmable flexibility.

The PIC10F220/222 products are supported by a full-

featured macro assembler, a software simulator, an in-

circuit debugger,

a

‘C’ compiler,

a

low-cost

development programmer and a full featured program-

mer. All the tools are supported on IBM^®PC and

compatible machines.

TABLE 1-1:

PIC10F220/222 DEVICES^{(1), (2)}

PIC10F220

PIC10F222

Clock

Maximum Frequency of Operation (MHz)

Flash Program Memory

Data Memory (bytes)

Timer Module(s)

8

256

16

8

512

23

Memory

Peripherals

Features

TMR0

Yes

2

TMR0

Yes

2

Wake-up from Sleep on pin change

Analog inputs

I/O Pins

3

Input Only Pins

1

Internal Pull-ups

Yes

33

Yes

33

In-Circuit Serial Programming™

Number of instructions

Packages

6-pin SOT-23,

8-pin DIP, DFN

6-pin SOT-23,

8-pin DIP, DFN

Note 1: The PIC10F220/222 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O

current capability and precision internal oscillator.

2: The PIC10F220/222 devices use serial programming with data pin GP0 and clock pin GP1.

DS41270E-page 5

PIC10F220/222

NOTES:

DS41270E-page 6

PIC10F220/222

2.0

DEVICE VARIETIES

A variety of packaging options are available. Depend-

ing on application and production requirements, the

proper device option can be selected using the

information in this section. When placing orders, please

use the PIC10F220/222 Product Identification System

at the back of this data sheet to specify the correct part

number.

2.1

Quick Turn Programming (QTP)

Devices

Microchip offers a QTP programming service for

factory production orders. This service is made

available for users who choose not to program

medium-to-high quantity units and whose code

patterns have stabilized. The devices are identical to

the Flash devices but with all Flash locations and fuse

options already programmed by the factory. Certain

code and prototype verification procedures do apply

before production shipments are available. Please

contact your local Microchip Technology sales office for

more details.

2.2

Serialized Quick Turn

Programming^SM(SQTP^SM) Devices

Microchip offers a unique programming service, where

a few user-defined locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or

sequential.

Serial programming allows each device to have a

unique number, which can serve as an entry-code,

password or ID number.

DS41270E-page 7

PIC10F220/222

NOTES:

DS41270E-page 8

PIC10F220/222

The PIC10F220/222 devices contain an 8-bit ALU and

working register. The ALU is a general purpose arith-

metic unit. It performs arithmetic and Boolean functions

between data in the working register and any register

file.

3.0

ARCHITECTURAL OVERVIEW

The high performance of the PIC10F220/222 devices

can be attributed to a number of architectural features

commonly found in RISC microprocessors. To begin

with, the PIC10F220/222 devices use a Harvard archi-

tecture in which program and data are accessed on

separate buses. This improves bandwidth over tradi-

tional von Neumann architectures where program and

data are fetched on the same bus. Separating program

and data memory further allows instructions to be sized

differently than the 8-bit wide data word. Instruction

opcodes are 12 bits wide, making it possible to have all

single-word instructions. A 12-bit wide program mem-

ory access bus fetches a 12-bit instruction in a single

cycle. A two-stage pipeline overlaps fetch and execu-

tion of instructions. Consequently, all instructions (33)

execute in a single cycle (1 μs @ 4 MHz or 500 ns @

8 MHz) except for program branches.

The ALU is 8-bits wide and capable of addition, sub-

traction, shift and logical operations. Unless otherwise

mentioned, arithmetic operations are two’s comple-

ment in nature. In two-operand instructions, one oper-

and is typically the W (working) register. The other

operand is either a file register or an immediate

constant. In single operand instructions, the operand is

either the W register or a file register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC) and

Zero (Z) bits in the STATUS register. The C and DC bits

operate as a borrow and digit borrow out bit, respec-

tively, in subtraction. See the SUBWF and ADDWF

instructions for examples.

The table below lists program memory (Flash) and data

memory (RAM) for the PIC10F220/222 devices.

Memory

Device

A simplified block diagram is shown in Figure 3-1 with

the corresponding device pins described in Table 3-1.

Program

Data

PIC10F220

PIC10F222

256 x 12

512 x 12

16 x 8

23 x 8

The PIC10F220/222 devices can directly or indirectly

address its register files and data memory. All Special

Function Registers (SFR), including the PC, are

mapped in the data memory. The PIC10F220/222

devices have a highly orthogonal (symmetrical) instruc-

tion set that makes it possible to carry out any opera-

tion, on any register, using any addressing mode. This

symmetrical nature and lack of “special optimal situa-

tions” make programming with the PIC10F220/222

devices simple, yet efficient. In addition, the learning

curve is reduced significantly.

DS41270E-page 9

PIC10F220/222

FIGURE 3-1:

BLOCK DIAGRAM

9-10

8

GPIO

Data Bus

Program Counter

Flash

512 x 12 or

256 x 12

Program

Memory

GP0/AN0/ICSPDAT

GP1/AN1/ICSPCLK

GP2/T0CKI/FOSC4

GP3/MCLR/VPP

RAM

23 or 16

bytes

STACK1

STACK2

File

Registers

Program

Bus

12

RAM Addr

9

Addr MUX

Instruction Reg

Indirect

Addr

5

Direct Addr

5-7

FSR Reg

STATUS Reg

8

3

MUX

Device Reset

Timer

Instruction

Decode &

Control

Power-on

Reset

ALU

AN0

AN1

8

Watchdog

Timer

ADC

Timing

Generation

W Reg

Internal RC

Clock

Timer0

Absolute

Voltage

MCLR

VDD, VSS

Reference

TABLE 3-1:

PINOUT DESCRIPTION

Input

Function

Output

Type

Name

Description

Type

GP0/AN0/ICSPDAT

GP0

TTL

CMOS Bidirectional I/O pin. Can be software programmed for internal weak

pull-up and wake-up from Sleep on pin change.

AN0

ICSPDAT

GP1

AN

ST

—

Analog Input

CMOS In-Circuit programming data

GP1/AN1/ICSPCLK

TTL

CMOS Bidirectional I/O pin. Can be software programmed for internal weak

pull-up and wake-up from Sleep on pin change.

AN1

ICSPCLK

GP2

AN

ST

—

Analog Input

In-Circuit programming clock

GP2/T0CKI/FOSC4

GP3/MCLR/VPP

TTL

ST

CMOS Bidirectional I/O pin

Clock input to TMR0

CMOS Oscillator/4 output

T0CKI

FOSC4

GP3

—

TTL

—

Input pin. Can be software programmed for internal weak pull-up and

wake-up from Sleep on pin change.

MCLR

ST

—

Master Clear (Reset). When configured as MCLR, this pin is an

active-low Reset to the device. Voltage on MCLR/VPP must not

exceed VDD during normal device operation or the device will enter

Programming mode.

VPP

VDD

VSS

HV

P

—

Programming voltage input

VDD

VSS

Positive supply for logic and I/O pins

Ground reference for logic and I/O pins

P

Legend:

I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,

ST = Schmitt Trigger input, AN = Analog Input

DS41270E-page 10

PIC10F220/222

3.1

Clocking Scheme/Instruction

Cycle

3.2

Instruction Flow/Pipelining

An instruction cycle consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle,

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the PC to change (e.g., GOTO) then two cycles

are required to complete the instruction (Example 3-1).

The clock is internally divided by four to generate four

non-overlapping quadrature clocks, namely Q1, Q2,

Q3 and Q4. Internally, the PC is incremented every Q1,

and the instruction is fetched from program memory

and latched into the Instruction Register (IR) in Q4. It is

decoded and executed during Q1 through Q4. The

clocks and instruction execution flow is shown in

Figure 3-2 and Example 3-1.

A fetch cycle begins with the PC incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the Instruction Register in cycle Q1. This instruc-

tion is then decoded and executed during the Q2, Q3

and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-2:

CLOCK/INSTRUCTION CYCLE

Q2

Q3

Q4

Q2

Q3

Q4

Q2

Q3

Q4

Q1

OSC1

Q1

Q2

Q3

Q4

PC

Internal

phase

clock

PC

PC + 1

PC + 2

Fetch INST (PC)

Execute INST (PC - 1)

Fetch INST (PC + 1)

Execute INST (PC)

Fetch INST (PC + 2)

Execute INST (PC + 1)

EXAMPLE 3-1:

INSTRUCTION PIPELINE FLOW

1. MOVLW 03H

2. MOVWF GPIO

3. CALL SUB_1

Fetch 1

Execute 1

Fetch 2

Execute 2

Fetch 3

Execute 3

Fetch 4

4. BSF

GPIO, BIT1

Flush

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction

is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

DS41270E-page 11

PIC10F220/222

NOTES:

DS41270E-page 12

PIC10F220/222

4.2

Program Memory Organization for

the PIC10F222

4.0

MEMORY ORGANIZATION

The PIC10F220/222 memories are organized into pro-

gram memory and data memory. Data memory banks

are accessed using the File Select Register (FSR).

The PIC10F222 devices have a 10-bit Program

Counter (PC) capable of addressing a 1024 x 12

program memory space.

4.1

Program Memory Organization for

the PIC10F220

Only the first 512 x 12 (0000h-01FFh) for the Mem-

High are physically implemented (see Figure 4-2).

Accessing a location above these boundaries will

cause a wrap-around within the first 512 x 12 space

(PIC10F222). The effective Reset vector is at 0000h,

(see Figure 4-2). Location 01FFh (PIC10F222) con-

tains the internal clock oscillator calibration value.

This value should never be overwritten.

The PIC10F220 devices have a 9-bit Program Counter

(PC) capable of addressing a 512 x 12 program

memory space.

Only the first 256 x 12 (0000h-00FFh) for the

PIC10F220 are physically implemented (see

Figure 4-1). Accessing

a location above these

boundaries will cause a wrap-around within the first

256 x 12 space (PIC10F220). The effective Reset

vector is at 0000h, (see Figure 4-1). Location 00FFh

(PIC10F220) contains the internal clock oscillator

calibration value. This value should never be

overwritten.

FIGURE 4-2:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC10F222

<9:0>

PC<8:0>

10

CALL, RETLW

Stack Level 1

Stack Level 2

FIGURE 4-1:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC10F220

(1)

Reset Vector

0000h

<8:0>

PC<7:0>

9

CALL, RETLW

On-chip Program

Memory

Stack Level 1

Stack Level 2

(1)

Reset Vector

0000h

On-chip Program

Memory

512 Words

01FFh

0200h

02FFh

256 Word

00FFh

0100h

Note 1: Address 0000h becomes the effective

Reset vector. Location 01FFh contains the

MOVLW XXinternal oscillator calibration

value.

01FFh

Note 1: Address 0000h becomes the

effective Reset vector. Location 00FFh

contains the MOVLW XXinternal oscillator

calibration value.

DS41270E-page 13

PIC10F220/222

FIGURE 4-4:

PIC10F222 REGISTER

FILE MAP

4.3

Data Memory Organization

Data memory is composed of registers or bytes of

RAM. Therefore, data memory for a device is specified

by its register file. The register file is divided into two

functional groups: Special Function Registers (SFR)

and General Purpose Registers (GPR).

File Address

(1)

INDF

00h

01h

02h

03h

04h

05h

06h

07h

TMR0

PCL

The Special Function Registers include the TMR0 reg-

ister, the Program Counter (PCL), the STATUS register,

the I/O register (GPIO) and the File Select Register

(FSR). In addition, Special Function Registers are used

to control the I/O port configuration and prescaler

options.

STATUS

FSR

OSCCAL

GPIO

ADCON0

ADRES

The General Purpose Registers are used for data and

control information under command of the instructions.

08h

09h

For the PIC10F220, the register file is composed of 9

Special Function Registers and 16 General Purpose

Registers (Figure 4-3, Figure 4-4).

General

Purpose

Registers

For the PIC10F222, the register file is composed of 9

Special Function Registers and 23 General Purpose

Registers (Figure 4-4).

1Fh

4.3.1

GENERAL PURPOSE REGISTER

FILE

Note 1: Not a physical register. See Section 4.9

“Indirect Data Addressing; INDF and

FSR Registers”.

The General Purpose Register file is accessed, either

directly or indirectly, through the File Select Register

(FSR). See Section 4.9 “Indirect Data Addressing;

INDF and FSR Registers”.

4.3.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral functions to control the

operation of the device (Table 4-1).

FIGURE 4-3:

PIC10F220 REGISTER

FILE MAP

File Address

The Special Function Registers can be classified into

two sets. The Special Function Registers associated

with the “core” functions are described in this section.

Those related to the operation of the peripheral

features are described in the section for each

peripheral feature.

(1)

INDF

00h

01h

02h

03h

04h

05h

06h

07h

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

ADCON0

ADRES

08h

09h

(2)

Unimplemented

0Fh

10h

General

Purpose

Registers

1Fh

Note 1: Not a physical register. See Section 4.9

“Indirect Data Addressing; INDF and

FSR Registers”.

2: Unimplemented, read as 00h.

DS41270E-page 14

PIC10F220/222

TABLE 4-1:

SPECIAL FUNCTION REGISTER (SFR) SUMMARY

Value on

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Power-On

Reset

Page #

(2)

00h

01h

02h

INDF

Uses contents of FSR to address data memory (not a physical register)

8-Bit Real-Time Clock/Counter

xxxx xxxx

1111 1111

20

25

19

TMR0

(1)

PCL

Low Order 8 Bits of PC

(3)

03h

04h

05h

06h

STATUS

FSR

GPWUF

—

TO

PD

Z

DC

C

0--1 1xxx

111x xxxx

1111 1110

---- xxxx

15

20

18

21

Indirect Data Memory Address Pointer

OSCCAL

GPIO

CAL6

—

CAL5

—

CAL4

—

CAL3

—

CAL2

GP3

CAL1

GP2

CAL0

GP1

FOSC4

GP0

07h

08h

N/A

ADCON0

ADRES

ANS1

ANS0

—

CHS1

CHS0 GO/DONE ADON

11-- 1100

xxxx xxxx

---- 1111

30

31

23

Result of Analog-to-Digital Conversion

TRISGPIO

OPTION

—

I/O Control Register

PSA PS2

N/A

GPWU GPPU

T0CS

T0SE

PS1

PS0

1111 1111

17

Legend:

– = unimplemented, read as ‘0’, x= unknown, u= unchanged, q= value depends on condition.

Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.7 “Program Counter” for an

explanation of how to access these bits.

2: Other (non Power-up) Resets include external Reset through MCLR, Watchdog Timer and wake-up on pin change

Reset.

3: See Table 8-1 for other Reset specific values.

4.4

STATUS Register

This register contains the arithmetic status of the ALU,

the Reset status and the page preselect bit.

The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUSwill clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu(where u= unchanged).

Therefore, it is recommended that only BCF, BSF and

MOVWFinstructions be used to alter the STATUS regis-

ter. These instructions do not affect the Z, DC or C bits

from the STATUS register. For other instructions, which

do affect Status bits, see Instruction Set Summary.

DS41270E-page 15

PIC10F220/222

REGISTER 4-1:

STATUS REGISTER (ADDRESS: 03h)

R/W-0

GPWUF

bit 7

R/W-0

—

R/W-0

—

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC

R/W-x

C

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

GPWUF: GPIO Reset bit

1= Reset due to wake-up from Sleep on pin change

0= After power-up or other Reset

bit 6

bit 5

bit 4

Reserved: Do not use. Use of this bit may affect upward compatibility with future products.

TO: Time-out bit

1= After power-up, CLRWDTinstruction or SLEEPinstruction

0= A WDT time-out occurred

bit 3

bit 2

bit 1

PD: Power-down bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit carry/borrow bit (for ADDWFand SUBWFinstructions)

ADDWF:

1= A carry to the 4th low-order bit of the result occurred

0= A carry to the 4th low-order bit of the result did not occur

SUBWF:

1= A borrow from the 4th low-order bit of the result did not occur

0= A borrow from the 4th low-order bit of the result occurred

bit 0

C: Carry/borrow bit (for ADDWF, SUBWFand RRF, RLFinstructions)

ADDWF:

SUBWF:

RRFor RLF:

1= A carry occurred

1= A borrow did not occur Load bit with LSb or MSb, respectively

0= A carry did not occur 0= A borrow occurred

DS41270E-page 16

PIC10F220/222

4.5

OPTION Register

Note:

If TRIS bit is set to ‘0’, the wake-up on

change and pull-up functions are disabled

for that pin (i.e., note that TRIS overrides

Option control of GPPU and GPWU).

The OPTION register is a 8-bit wide, write-only register,

which contains various control bits to configure the

Timer0/WDT prescaler and Timer0.

The OPTION register is not memory mapped and is

therefore only addressable by executing the OPTION

instruction, the contents of the W register will be trans-

ferred to the OPTION register. A Reset sets the

OPTION<7:0> bits.

If the T0CS bit is set to ‘1’, it will override

the TRIS function on the T0CKI pin.

REGISTER 4-2:

OPTION REGISTER

W-1

GPWU

bit 7

W-1

GPPU

W-1

PSA

W-1

PS2

W-1

PS1

W-1

PS0

T0CS

T0SE

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

GPWU: Enable Wake-up On Pin Change bit (GP0, GP1, GP3)

1= Disabled

0= Enabled

GPPU: Enable Weak Pull-ups bit (GP0, GP1, GP3)

1= Disabled

0= Enabled

T0CS: Timer0 Clock Source Select bit

1= Transition on T0CKI pin (overrides TRIS on the T0CKI pin)

0= Transition on internal instruction cycle clock, FOSC/4

T0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on the T0CKI pin

0= Increment on low-to-high transition on the T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler assigned to the WDT

0= Prescaler assigned to Timer0

PS<2:0>: Prescaler Rate Select bits

Bit Value Timer0 Rate WDT Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

DS41270E-page 17

PIC10F220/222

4.6

OSCCAL Register

The Oscillator Calibration (OSCCAL) register is used to

calibrate the internal precision 4/8 MHz oscillator. It

contains seven bits for calibration.

Note:

Erasing the device will also erase the pre-

programmed internal calibration value for

the internal oscillator. The calibration

value must be read prior to erasing the

part so it can be reprogrammed correctly

later.

After you move in the calibration constant, do not

change the value. See Section 8.2.2 “Internal 4/8 MHz

Oscillator”.

REGISTER 4-3:

OSCCAL – OSCILLATOR CALIBRATION REGISTER (ADDRESS: 05h)

R/W-1

CAL6

R/W-1

CAL5

R/W-1

CAL4

R/W-1

CAL3

R/W-1

CAL2

R/W-1

CAL1

R/W-1

CAL0

R/W-0

FOSC4

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-1

CAL<6:0>: Oscillator Calibration bits

0111111= Maximum frequency

•

0000001

0000000= Center frequency

1111111

•

1000000= Minimum frequency

bit 0

FOSC4: INTOSC/4 Output Enable bit⁽¹⁾

1= INTOSC/4 output onto GP2

0= GP2/T0CKI applied to GP2

Note 1: Overrides GP2/T0CKI control registers when enabled.

DS41270E-page 18

PIC10F220/222

4.7.1

EFFECTS OF RESET

4.7

Program Counter

The PC is set upon a Reset, which means that the PC

addresses the last location in program memory (i.e.,

the oscillator calibration instruction). After executing

MOVLW XX, the PC will roll over to location 0000h and

begin executing user code.

As a program instruction is executed, the Program

Counter (PC) will contain the address of the next

program instruction to be executed. The PC value is

increased by one every instruction cycle, unless an

instruction changes the PC.

For a GOTOinstruction, bits 8:0 of the PC are provided

by the GOTO instruction word. The PC Latch (PCL) is

mapped to PC<7:0>.

4.8

Stack

The PIC10F220 device has a 2-deep, 8-bit wide

hardware PUSH/POP stack.

For a CALLinstruction or any instruction where the PCL

is the destination, bits 7:0 of the PC again are provided

by the instruction word. However, PC<8> does not

come from the instruction word, but is always cleared

(Figure 4-5).

The PIC10F222 device has a 2-deep, 9-bit wide

hardware PUSH/POP stack.

A CALLinstruction will PUSH the current value of stack

1 into stack 2 and then PUSH the current PC value,

incremented by one, into stack level 1. If more than two

sequential CALL’s are executed, only the most recent

two return addresses are stored.

Instructions where the PCL is the destination or Modify

PCL instructions, include MOVWF PC, ADDWF PCand

BSF PC, 5.

Note:

Because PC<8> is cleared in the CALL

instruction or any Modify PCL instruction,

all subroutine calls or computed jumps are

limited to the first 256 locations of any

program memory page (512 words long).

A RETLWinstruction will POP the contents of stack level

1 into the PC and then copy stack level 2 contents into

level 1. If more than two sequential RETLW’s are exe-

cuted, the stack will be filled with the address

previously stored in level 2.

Note 1: The W register will be loaded with the lit-

eral value specified in the instruction. This

is particularly useful for the implementa-

tion of data look-up tables within the

program memory.

FIGURE 4-5:

LOADING OF PC

BRANCH INSTRUCTIONS

GOTOInstruction

8 7

0

2: There are no Status bits to indicate stack

PC

PCL

overflows or stack underflow conditions.

3: There are no instructions mnemonics

called PUSH or POP. These are actions

that occur from the execution of the CALL

and RETLWinstructions.

Instruction Word

CALLor Modify PCLInstruction

8 7

0

PC

PCL

Instruction Word

Reset to ‘0’

DS41270E-page 19

PIC10F220/222

EXAMPLE 4-1:

HOW TO CLEAR RAM

USING INDIRECT

ADDRESSING

4.9

Indirect Data Addressing; INDF

and FSR Registers

The INDF register is not a physical register. Addressing

INDF actually addresses the register whose address is

contained in the FSR register (FSR is a pointer). This is

indirect addressing.

MOVLW

MOVWF

0x10

;initialize pointer

;to RAM

FSR

INDF

;clear INDF

;register

INCF

BTFSC

GOTO

FSR,F

FSR,4

;all done?

;NO, clear next

4.9.1

INDIRECT ADDRESSING

• Register file 09 contains the value 10h

• Register file 0A contains the value 0Ah

• Load the value 09 into the FSR register

CONTINUE

:

;YES, continue

• A read of the INDF register will return the value

of 10h

The FSR is a 5-bit wide register. It is used in conjunc-

tion with the INDF register to indirectly address the data

memory area.

• Increment the value of the FSR register by one

(FSR = 0A)

• A read of the INDR register now will return the

value of 0Ah.

The FSR<4:0> bits are used to select data memory

addresses 00h to 1Fh.

Reading INDF itself indirectly (FSR = 0) will produce

00h. Writing to the INDF register indirectly results in a

no-operation (although Status bits may be affected).

Note:

Do not use banking. FSR <7:5> are

unimplemented and read as ‘1’s.

A simple program to clear RAM locations 10h-1Fh

using Indirect addressing is shown in Example 4-1.

FIGURE 4-6:

DIRECT/INDIRECT ADDRESSING

Direct Addressing

Indirect Addressing

4

(opcode)

0

(FSR)

0

4

Location Select

00h

Data

Memory

0Fh

10h

(1)

1Fh

Bank 0

Note 1: For register map detail, see Section 4.3 “Data Memory Organization”.

DS41270E-page 20

PIC10F220/222

The TRIS registers are “write-only” and are set (output

drivers disabled) upon Reset.

5.0

I/O PORT

As with any other register, the I/O register(s) can be

written and read under program control. However, read

instructions (e.g., MOVF GPIO, W) always read the I/O

pins independent of the pin’s Input/Output modes. On

Reset, all I/O ports are defined as input (inputs are at

high-impedance) since the I/O control registers are all

set.

5.3

I/O Interfacing

The equivalent circuit for an I/O port pin is shown in

Figure 5-1. All port pins, except GP3, which is input

only, may be used for both input and output operations.

For input operations, these ports are non-latching. Any

input must be present until read by an input instruction

(e.g., MOVF GPIO, W). The outputs are latched and

remain unchanged until the output latch is rewritten. To

use a port pin as output, the corresponding direction

control bit in TRIS must be cleared (= 0). For use as an

input, the corresponding TRIS bit must be set. Any I/O

pin (except GP3) can be programmed individually as

input or output.

5.1

GPIO

GPIO is an 8-bit I/O register. Only the low-order 4 bits

are used (GP<3:0>). Bits 7 through 4 are unimple-

mented and read as ‘0’s. Please note that GP3 is an

input only pin. Pins GP0, GP1 and GP3 can be config-

ured with weak pull-ups and also for wake-up on

change. The wake-up on change and weak pull-up

functions are not individually pin selectable. If GP3/

MCLR is configured as MCLR, a weak pull-up can be

enabled via the Configuration Word. Configuring GP3

as MCLR disables the wake-up on change function for

this pin.

FIGURE 5-1:

EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

Data

Bus

D

Q

Data

VDD

P

VDD

(1)

WR

Port

Latch

5.2

TRIS Registers

CK

The Output Driver Control register is loaded with the

contents of the W register by executing the TRIS f

instruction. A ‘1’ from a TRIS register bit puts the corre-

sponding output driver in a High-Impedance mode. A

‘0’ puts the contents of the output data latch on the

selected pins, enabling the output buffer. The excep-

tions are GP3, which is input only, and the GP2/T0CKI/

FOSC4 pin, which may be controlled by various

registers. See Table 5-1.

N

I/O

W

Reg

D

Q

TRIS

Latch

VSS VSS

TRIS ‘f’

CK

Reset

(2)

Note:

A read of the ports reads the pins, not the

output data latches. That is, if an output

driver on a pin is enabled and driven high,

but the external system is holding it low, a

read of the port will indicate that the pin is

low.

RD Port

Note 1: I/O pins have protection diodes to VDD and

VSS.

2: See Table 3-1 for buffer type.

TABLE 5-1:

ORDER OF PRECEDENCE FOR PIN FUNCTIONS

Priority

GP0

GP1

GP2

GP3

1

2

3

AN0

TRIS GPIO

—

AN1

TRIS GPIO

—

FOSC4

T0CKI

MCLR

—

TRIS GPIO

—

TABLE 5-2:

REQUIREMENTS TO MAKE PINS AVAILABLE IN DIGITAL MODE

Bit

GP0

GP1

GP2

GP3

FOSC4

T0CS

—

0

—

0

—

0

ANS1

—

ANS0

—

MCLRE

—

Legend:

— = Condition of bit will have no effect on the setting of the pin to Digital mode.

DS41270E-page 21

PIC10F220/222

FIGURE 5-2:

BLOCK DIAGRAM OF GP0

FIGURE 5-3:

BLOCK DIAGRAM OF GP2

AND GP1

(1)

Data

Bus

D

I/O Pin

Q

GPPU

Data

Latch

WR

Port

FOSC4

CK

OSCCAL<0>

Data

W

Reg

Bus

D

Q

D

Q

Data

Latch

TRIS

Latch

(1)

I/O Pin

WR

Port

TRIS ‘f’

CK

W

Reg

Reset

T0CS

D

Q

TRIS

Latch

TRIS ‘f’

CK

RD Port

Reset

T0CKI

Analog Enable

Note 1: I/O pins have protection diodes to VDD and

VSS.

RD Port

FIGURE 5-4:

BLOCK DIAGRAM OF GP3

Q

D

GPPU

CK

MCLRE

Reset

Mis-Match

(1)

ADC

I/O Pin

Note 1: I/O pins have protection diodes to VDD and

VSS.

Data Bus

RD Port

Q

D

CK

Mis-match

Note 1: GP3/MCLR pin has a protection diode to VSS

only.

DS41270E-page 22

PIC10F220/222

TABLE 5-3:

SUMMARY OF PORT REGISTERS

Value on

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3 Bit 2 Bit 1 Bit 0

Power-On

Reset

All Other Resets

N/A

TRISGPIO

—

I/O Control Registers

---- 1111

1111 1111

N/A

OPTION

STATUS

GPIO

GPWU

GPWUF

—

GPPU T0CS T0SE PSA

PS2

Z

PS1 PS0 1111 1111

(1)

03h

—

TO

—

PD

DC

C

0001 1xxx

q00q quuu

06h

GP3

GP2 GP1 GP0 ---- xxxx

---- uuuu

Legend:

Shaded cells not used by PORT registers, read as ‘0’, – = unimplemented, read as ‘0’, x= unknown, u= unchanged,

q= depends on condition.

Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

EXAMPLE 5-1:

I/O PORT READ-MODIFY-

WRITE INSTRUCTIONS

5.4

I/O Programming Considerations

5.4.1

BIDIRECTIONAL I/O PORTS

;Initial GPIO Settings

;GPIO<3:2> Inputs

;GPIO<1:0> Outputs

;

Some instructions operate internally as read followed

by write operations. The BCFand BSFinstructions, for

example, read the entire port into the CPU, execute the

bit operation and re-write the result. Caution must be

used when these instructions are applied to a port

where one or more pins are used as input/outputs. For

example, a BSFoperation on bit 2 of GPIO will cause

all eight bits of GPIO to be read into the CPU, bit 2 to

be set and the GPIO value to be written to the output

latches. If another bit of GPIO is used as a bidirectional

I/O pin (say bit 0) and it is defined as an input at this

time, the input signal present on the pin itself would be

read into the CPU and rewritten to the data latch of this

particular pin, overwriting the previous content. As long

as the pin stays in the Input mode, no problem occurs.

However, if bit 0 is switched into Output mode later on,

the content of the data latch may now be unknown.

;

GPIO latch

GPIO pins

----------

---- pp11

----------

GPIO, 1 ;---- pp01

GPIO, 0 ;---- pp10

BCF

MOVLW 007h;

TRIS

GPIO

;---- pp10

---- pp11

;

Note:

The user may have expected the pin values to

be ---- pp00. The second BCFcaused GP1

to be latched as the pin value (High).

5.4.2

SUCCESSIVE OPERATIONS ON I/O

PORTS

The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be

valid at the beginning of the instruction cycle (Figure 5-5).

Therefore, care must be exercised if a write followed by

a read operation is carried out on the same I/O port. The

sequence of instructions should allow the pin voltage to

stabilize (load dependent) before the next instruction

causes that file to be read into the CPU. Otherwise, the

previous state of that pin may be read into the CPU rather

than the new state. When in doubt, it is better to separate

these instructions with a NOP or another instruction not

accessing this I/O port.

Example 5-1 shows the effect of two sequential

Read-Modify-Write instructions (e.g., BCF, BSF, etc.)

on an I/O port.

A pin actively outputting a high or a low should not be

driven from external devices at the same time in order

to change the level on this pin (“wired-or”, “wired-and”).

The resulting high output currents may damage the

chip.

FIGURE 5-5:

SUCCESSIVE I/O OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC + 3

PC

PC + 1

PC + 2

This example shows a write to GPIO followed

by a read from GPIO.

Instruction

Fetched

MOVWFGPIO

MOVFGPIO, W

NOP

Data setup time = (0.25 TCY – TPD)

where: TCY = instruction cycle

TPD = propagation delay

GP<2:0>

Port pin

written here

Port pin

sampled here

Therefore, at higher clock frequencies, a

write followed by a read may be problematic.

Instruction

Executed

MOVWF GPIO

(Write to GPIO)

MOVF GPIO,W

(Read GPIO)

NOP

DS41270E-page 23

PIC10F220/222

NOTES:

DS41270E-page 24

PIC10F220/222

Counter mode is selected by setting the T0CS bit

(OPTION<5>). In this mode, Timer0 will increment

either on every rising or falling edge of pin T0CKI. The

T0SE bit (OPTION<4>) determines the source edge.

Clearing the T0SE bit selects the rising edge. Restric-

tions on the external clock input are discussed in detail

in Section 6.1 “Using Timer0 With An External

Clock”.

6.0

TMR0 MODULE AND TMR0

REGISTER

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select:

- Edge select for external clock

The prescaler may be used by either the Timer0

module or the Watchdog Timer, but not both. The

prescaler assignment is controlled in software by the

control bit PSA (OPTION<3>). Clearing the PSA bit will

assign the prescaler to Timer0. The prescaler is not

readable or writable. When the prescaler is assigned to

the Timer0 module, prescale values of 1:2, 1:4, 1:256

are selectable. Section 6.2 “Prescaler” details the

operation of the prescaler.

Figure 6-1 is a simplified block diagram of the Timer0

module.

Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In Timer mode, the Timer0 module will

increment every instruction cycle (without prescaler). If

TMR0 register is written, the increment is inhibited for

the following two cycles (Figure 6-2 and Figure 6-3).

The user can work around this by writing an adjusted

value to the TMR0 register.

A summary of registers associated with the Timer0

module is found in Table 6-1.

FIGURE 6-1:

TIMER0 BLOCK DIAGRAM

Data Bus

GP2/T0CKI

FOSC/4

0

1

PSOUT

8

1

0

Sync with

Internal

Clocks

TMR0 Reg

Programmable

PSOUT

Sync

(2)

Prescaler

(2 TCY delay)

T0SE

3

(1)

PS2, PS1, PS0

PSA

(1)

T0CS

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer (Figure 6-5).

FIGURE 6-2:

TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

PC

(Program

Counter)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC-1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6

Instruction

Fetch

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

NT0 + 1

T0

T0 + 1

T0 + 2

NT0

NT0 + 2

Timer0

Instruction

Executed

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 2

Write TMR0

executed

DS41270E-page 25

PIC10F220/222

FIGURE 6-3:

TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

PC

(Program

Counter)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC-1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Instruction

Fetch

T0

T0 + 1

NT0

NT0 + 1

Timer0

Instruction

Executed

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 2

Write TMR0

executed

TABLE 6-1:

REGISTERS ASSOCIATED WITH TIMER0

Value on

Power-On

Reset

Value on

All Other

Resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

01h

TMR0

Timer0 – 8-Bit Real-Time Clock/Counter

GPWU GPPU T0CS T0SE PSA

xxxx xxxx

1111 1111

---- 1111

uuuu uuuu

1111 1111

---- 1111

N/A

OPTION

TRISGPIO

PS2

PS1

PS0

(1)

N/A

—

I/O Control Register

—

Legend:

Shaded cells not used by Timer0, – = unimplemented, x = unknown, u= unchanged.

Note 1: The TRIS of the T0CKI pin is overridden when T0CS = 1

6.1.1

EXTERNAL CLOCK

SYNCHRONIZATION

6.1

Using Timer0 With An External

Clock

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks (Figure 6-4).

Therefore, it is necessary for T0CKI to be high for at

least 2TOSC (and a small RC delay of 2Tt0H) and low

for at least 2TOSC (and a small RC delay of 2Tt0H).

Refer to the electrical specification of the desired

device.

When an external clock input is used for Timer0, it must

meet certain requirements. The external clock require-

ment is due to internal phase clock (TOSC) synchroniza-

tion. Also, there is a delay in the actual incrementing of

Timer0 after synchronization.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple counter-type

prescaler, so that the prescaler output is symmetrical.

For the external clock to meet the sampling require-

ment, the ripple counter must be taken into account.

Therefore, it is necessary for T0CKI to have a period of

at least 4TOSC (and a small RC delay of 4Tt0H) divided

by the prescaler value. The only requirement on T0CKI

high and low time is that they do not violate the

minimum pulse width requirement of Tt0H. Refer to

parameters 40, 41 and 42 in the electrical specification

of the desired device.

DS41270E-page 26

PIC10F220/222

6.1.2

TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0 mod-

ule is actually incremented. Figure 6-4 shows the delay

from the external clock edge to the timer incrementing.

FIGURE 6-4:

TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Small pulse

misses sampling

External Clock Input or

Prescaler Output⁽²⁾

(1)

External Clock/Prescaler

Output After Sampling

(3)

Increment Timer0 (Q4)

Timer0

T0

T0 + 1

T0 + 2

Note 1: Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC. (Duration of Q = TOSC).

Therefore, the error in measuring the interval between two edges on Timer0 input = ±4TOSC max.

2: External clock if no prescaler selected; prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

6.2

Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module or as a postscaler for the Watchdog

Timer (WDT), respectively (see Section 8.6 “Watch-

dog Timer (WDT)”). For simplicity, this counter is

being referred to as “prescaler” throughout this data

sheet.

Note:

The prescaler may be used by either the

Timer0 module or the WDT, but not both.

Thus, a prescaler assignment for the

Timer0 module means that there is no

prescaler for the WDT and vice-versa.

The PSA and PS<2:0> bits (OPTION<3:0>) determine

prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF 1,

MOVWF 1, BSF 1,x, etc.) will clear the prescaler.

When assigned to WDT, a CLRWDTinstruction will clear

the prescaler along with the WDT. The prescaler is

neither readable nor writable. On a Reset, the

prescaler contains all ‘0’s.

DS41270E-page 27

PIC10F220/222

To change prescaler from the WDT to the Timer0

module, use the sequence shown in Example 6-2. This

sequence must be used even if the WDT is disabled. A

CLRWDT instruction should be executed before

switching the prescaler.

6.2.1

SWITCHING PRESCALER

ASSIGNMENT

The prescaler assignment is fully under software

control (i.e., it can be changed “on-the-fly” during pro-

gram execution). To avoid an unintended device Reset,

the following instruction sequence (Example 6-1) must

be executed when changing the prescaler assignment

from Timer0 to the WDT.

EXAMPLE 6-2:

CHANGING PRESCALER

(WDT→TIMER0)

CLRWDT

;Clear WDT and

;prescaler

EXAMPLE 6-1:

CHANGING PRESCALER

(TIMER0 → WDT)

;Clear WDT

;Clear TMR0 & Prescaler

MOVLW ‘xxxx0xxx’ ;Select TMR0, new

;prescale value and

;clock source

CLRWDT

CLRF

TMR0

OPTION

MOVLW ‘00xx1111’b;These 3 lines (5, 6, 7)

OPTION

;are required only if

;desired

CLRWDT

;PS<2:0> are 000 or 001

MOVLW ‘00xx1xxx’b;Set Postscaler to

OPTION

;desired WDT rate

FIGURE 6-5:

BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

TCY (= FOSC/4)

Data Bus

8

0

1

GP2/T0CKI⁽²⁾

M

U

X

1

0

M

U

X

Sync

2

Cycles

TMR0 Reg

T0SE⁽¹⁾

T0CS⁽¹⁾

PSA⁽¹⁾

0

1

8-bit Prescaler

M

U

X

8

Watchdog

Timer

PS<2:0>⁽¹⁾

8-to-1 MUX

PSA⁽¹⁾

1

0

WDT Enable bit

MUX

PSA⁽¹⁾

WDT

Time-Out

Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.

2: T0CKI is shared with pin GP2 on the PIC10F220/222.

DS41270E-page 28

PIC10F220/222

7.0

ANALOG-TO-DIGITAL (A/D)

CONVERTER

Note:

The A/D Converter module consumes

power when the ADON bit is set even

when no channels are selected as analog

inputs. For low-power applications, it is

recommended that the ADON bit be

cleared when the A/D Converter is not in

use.

The A/D converter allows conversion of an analog

signal into an 8-bit digital signal.

7.1

Clock Divisors

The A/D Converter has a single clock source setting,

INTOSC/4. The A/D Converter requires 13 TAD periods

to complete a conversion. The divisor values do not

affect the number of TAD periods required to perform a

conversion. The divisor values determine the length of

the TAD period.

7.5

The GO/DONE bit

The GO/DONE bit is used to determine the status of a

conversion, to start a conversion and to manually halt a

conversion in process. Setting the GO/DONE bit starts

a conversion. When the conversion is complete, the A/

D Converter module clears the GO/DONE bit. A con-

version can be terminated by manually clearing the

GO/DONE bit while a conversion is in process. Manual

termination of a conversion may result in a partially

converted result in ADRES.

Note:

Due to the fixed clock divisor, a conversion

will complete in 13 CPU instruction cycles.

7.2

Voltage Reference

Due to the nature of the design, there is no external

voltage reference allowed for the A/D Converter.

The A/D Converter reference voltage will always be

VDD.

The GO/DONE bit is cleared when the device enters

Sleep, stopping the current conversion. The A/D Con-

verter does not have a dedicated oscillator, it runs off of

the system clock.

7.3

Analog Mode Selection

The GO/DONE bit cannot be set when ADON is clear.

The ANS<1:0> bits are used to configure pins for ana-

log input. Upon any Reset ANS<1:0> defaults to 11.

This configures pins AN0 and AN1 as analog inputs.

Pins configured as analog inputs are not available for

digital output. Users should not change the ANS bits

while a conversion is in process. ANS bits are active

regardless of the condition of ADON.

7.6

Sleep

This A/D Converter does not have a dedicated A/D

Converter clock and therefore no conversion in Sleep

is possible. If a conversion is underway and a Sleep

command is executed, the GO/DONE and ADON bit

will be cleared. This will stop any conversion in process

and power-down the A/D Converter module to con-

serve power. Due to the nature of the conversion pro-

cess, the ADRES may contain a partial conversion. At

least 1 bit must have been converted prior to Sleep to

have partial conversion data in ADRES. The CHS bits

are reset to their default condition and CHS<1:0> = 11.

7.4

A/D Converter Channel Selection

The CHS bits are used to select the analog channel to

be sampled by the A/D Converter. The CHS bits

should not be changed during a conversion. To

acquire an analog signal, the CHS selection must

match one of the pin(s) selected by the ANS bits. The

Internal Absolute Voltage Reference can be selected

regardless of the condition of the ANS bits. All channel

selection information will be lost when the device

enters Sleep.

For accurate conversions, TAD must meet the following:

• 500 ns < TAD < 50 μs

• TAD = 1/(FOSC/divisor)

TABLE 7-1:

EFFECTS OF SLEEP AND WAKE ON ADCON0

ANS1

ANS0

CHS1

CHS0

GO/DONE

ADON

Prior to Sleep

Entering Sleep

Wake

x

1

x

1

0

1

0

1

0

x

Unchanged

1

x

Unchanged

1

DS41270E-page 29

PIC10F220/222

7.7

Analog Conversion Result

Register

7.8

Internal Absolute Voltage

Reference

The ADRES register contains the results of the last

conversion. These results are present during the sam-

pling period of the next analog conversion process.

After the sampling period is over, ADRES is cleared (=

0). A ‘leading one’ is then right shifted into the ADRES

to serve as an internal conversion complete bit. As

each bit weight, starting with the MSb, is converted, the

leading one is shifted right and the converted bit is

stuffed into ADRES. After a total of 9 right shifts of the

‘leading one’ have taken place, the conversion is com-

plete; the ‘leading one’ has been shifted out and the

GO/DONE bit is cleared.

The function of the Internal Absolute Voltage Refer-

ence is to provide a constant voltage for conversion

across the devices VDD supply range. The A/D Con-

verter is ratiometric with the conversion reference

voltage being VDD. Converting a constant voltage of

0.6V (typical) will result in a result based on the voltage

applied to VDD of the device. The result of conversion

of this reference across the VDD range can be

approximated by: Conversion Result = 0.6V/(VDD/256)

Note:

The actual value of the Absolute Voltage

Reference varies with temperature and

part-to-part variation. The conversion is

also susceptible to analog noise on the

VDD pin and noise generated by the sink-

ing or sourcing of current on the I/O pins.

If the GO/DONE bit is cleared in software during a con-

version, the conversion stops. The data in ADRES is

the partial conversion result. This data is valid for the bit

weights that have been converted. The position of the

‘leading one’ determines the number of bits that have

been converted. The bits that were not converted

before the GO/DONE was cleared are unrecoverable.

REGISTER 7-1:

ADCON0: A/D CONVERTER 0 REGISTER

R/W-1

ANS1

R/W-1

ANS0

U-0

—

U-0

—

R/W-1

CHS1

R/W-1

CHS0

R/W-0

ADON

GO/DONE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

ANS1: ADC Analog Input Pin Select bit

1= GP1/AN1 configured for analog input

0= GP1/AN1 configured as digital I/O

(1), (2)

ANS0: ADC Analog Input Pin Select bit

1= GP0/AN0 configured as an analog input

0= GP0/AN0 configured as digital I/O

bit 5-4

bit 3-2

Unimplemented: Read as ‘0’

(3)

CHS<1:0>: ADC Channel Select bits

00= Channel 00 (GP0/AN0)

01= Channel 01 (GP1/AN1)

1X= 0.6V absolute Voltage reference

(4)

bit 1

bit 0

GO/DONE: ADC Conversion Status bit

1= ADC conversion in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically cleared

by hardware when the ADC is done converting.

0= ADC conversion completed/not in progress. Manually clearing this bit while a conversion is in process

terminates the current conversion.

ADON: ADC Enable bit

1= ADC module is operating

0= ADC module is shut-off and consumes no power

Note 1: When the ANS bits are set, the channel(s) selected are automatically forced into analog mode regardless of the pin

function previously defined.

2:

The ANS<1:0> bits are active regardless of the condition of ADON

3: CHS<1:0> bits default to 11after any Reset.

4: If the ADON bit is clear, the GO/DONE bit cannot be set.

DS41270E-page 30

PIC10F220/222

REGISTER 7-2:

ADRES: ANALOG CONVERSION RESULT REGISTER

R-X

ADRES7

bit 7

R-X

ADRES6

ADRES5

ADRES4

ADRES3

ADRES2

ADRES1

ADRES0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

ADRES<7:0>

DS41270E-page 31

PIC10F220/222

After the analog input channel is selected (or changed),

an A/D acquisition must be done before the conversion

can be started. To calculate the minimum acquisition

time, Equation 7-1 may be used. This equation

assumes that 1/2 LSb error is used (256 steps for the

ADC). The 1/2 LSb error is the maximum error allowed

for the ADC to meet its specified resolution.

7.9

A/D Acquisition Requirements

For the ADC to meet its specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The Analog

Input model is shown in Figure 7-1. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge the

capacitor CHOLD. The sampling switch (RSS) impedance

varies over the device voltage (VDD), see Figure 7-1.

The maximum recommended impedance for analog

sources is 10 kΩ. As the source impedance is

decreased, the acquisition time may be decreased.

EQUATION 7-1:

ACQUISITION TIME EXAMPLE

Assumptions:

Temperature = 50°C and external impedance of 10 kΩ 5.0V VDD

Tacq

=

Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

TAMP + TC + TCOFF

2 μs + TC + [(Temperature - 25°C)(0.05 μs/°C)]

Solving for Tc:

Therefore:

Tc

=

CHOLD (RIC + RSS + RS) In(1/512)

-25pF (l kΩ + 7 kΩ + 10 kΩ ) In(0.00196)

2.81 μs

Tacq

=

2 μs + 2.81 μs + [(50°C-25°C)(0.0 5μs/°C)]

6.06 μs

Note 1: The charge holding capacitor (CHOLD) is not discharged after each conversion.

2: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin

leakage specification.

FIGURE 7-1:

ANALOG INPUT MODULE

VDD

Sampling

Switch

VT = 0.6V

ANx

SS

RIC ≤ 1k

Rss

Rs

CPIN

5 pF

VA

I LEAKAGE

± 500 nA

CHOLD = 25 pF

VSS/VREF-

VT = 0.6V

6V

5V

RSS

Legend:

CPIN

VT

ILEAKAGE

= Input Capacitance

= Threshold Voltage

= Leakage current at the pin due

to various junctions

VDD 4V

3V

2V

RIC

SS

CHOLD

= Interconnect Resistance

= Sampling Switch

= Sample/Hold Capacitance

5 6 7 8 9 1011

Sampling Switch

(kΩ)

DS41270E-page 32

PIC10F220/222

The PIC10F220/222 devices have a Watchdog Timer,

which can be shut off only through Configuration bit

WDTE. It runs off of its own RC oscillator for added reli-

ability. When using DRT, there is an 1.125 ms (typical)

delay only on VDD power-up. With this timer on-chip,

most applications need no external Reset circuitry.

8.0

SPECIAL FEATURES OF THE

CPU

What sets a microcontroller apart from other proces-

sors are special circuits that deal with the needs of real-

time applications. The PIC10F220/222 microcontrol-

lers have a host of such features intended to maximize

system reliability, minimize cost through elimination of

external components, provide power-saving operating

modes and offer code protection. These features are:

The Sleep mode is designed to offer a very low current

Power-Down mode. The user can wake-up from Sleep

through a change on input pins or through a Watchdog

Timer time-out.

• Reset:

8.1

Configuration Bits

- Power-on Reset (POR)

- Device Reset Timer (DRT)

- Watchdog Timer (WDT)

- Wake-up from Sleep on pin change

• Sleep

The PIC10F220/222 Configuration Words consist of 12

bits. Configuration bits can be programmed to select

various device configurations. One bit is the Watchdog

Timer enable bit, one bit is the MCLR enable bit and

one bit is for code protection (see Register 8-1).

• Code Protection

• ID Locations

• In-Circuit Serial Programming™

• Clock Out

REGISTER 8-1:

CONFIG: CONFIGURATION WORD⁽¹⁾

—

MCLRE

CP

WDTE MCPU IOSCFS

bit 0

bit 11

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 11-5 Unimplemented: Read as ‘0’

bit 4

bit 3

bit 2

bit 1

MCLRE: GP3/MCLR Pin Function Select bit

1= GP3/MCLR pin function is MCLR

0= GP3/MCLR pin function is digital I/O, MCLR internally tied to VDD

CP: Code Protection bit

1= Code protection off

0= Code protection on

WDTE: Watchdog Timer Enable bit

1= WDT enabled

0= WDT disabled

MCPU: Master Clear Pull-up Enable bit⁽²⁾

1= Pull-up disabled

0= Pull-up enabled

bit 0

IOSCFS: Internal Oscillator Frequency Select bit

1= 8 MHz

0= 4 MHz

Note 1: Refer to the “PIC10F220/222 Memory Programming Specification” (DS41266), to determine how to

access the Configuration Word. The Configuration Word is not user addressable during device operation.

2: MCLRE must be a ‘1’ to enable this selection.

DS41270E-page 33

PIC10F220/222

8.2

Oscillator Configurations

8.3

Reset

The device differentiates between various kinds of

Reset:

8.2.1

OSCILLATOR TYPES

The PIC10F220/222 devices are offered with internal

oscillator mode only.

• Power-on Reset (POR)

• MCLR Reset during normal operation

• MCLR Reset during Sleep

• INTOSC: Internal 4/8 MHz Oscillator

• WDT Time-out Reset during normal operation

• WDT Time-out Reset during Sleep

• Wake-up from Sleep on pin change

8.2.2

INTERNAL 4/8 MHz OSCILLATOR

The internal oscillator provides a 4/8 MHz (nominal)

system clock (see Section 10.0 “Electrical Charac-

teristics” for information on variation over voltage and

temperature).

Some registers are not reset in any way, they are

unknown on POR and unchanged in any other Reset.

Most other registers are reset to “Reset state” on

Power-on Reset (POR), MCLR, WDT or Wake-up on

pin change Reset during normal operation. They are

not affected by a WDT Reset during Sleep or MCLR

Reset during Sleep, since these Resets are viewed as

resumption of normal operation. The exceptions to this

are TO, PD and GPWUF bits. They are set or cleared

differently in different Reset situations. These bits are

used in software to determine the nature of Reset. See

Table 8-1 for a full description of Reset states of all

registers.

In addition, a calibration instruction is programmed into

the last address of memory, which contains the calibra-

tion value for the internal oscillator. This location is

always uncode protected, regardless of the code-pro-

tect settings. This value is programmed as a MOVLW XX

instruction where XX is the calibration value and is

placed at the Reset vector. This will load the W register

with the calibration value upon Reset and the PC will

then roll over to the users program at address 0x000.

The user then has the option of writing the value to the

OSCCAL Register (05h) or ignoring it.

OSCCAL, when written to with the calibration value, will

“trim” the internal oscillator to remove process variation

from the oscillator frequency.

Note:

Erasing the device will also erase the pre-

programmed internal calibration value for

the internal oscillator. The calibration

value must be read prior to erasing the

part so it can be reprogrammed correctly

later.

TABLE 8-1:

RESET CONDITIONS FOR REGISTERS – PIC10F220/222

Register

Address

Power-on Reset

MCLR Reset, WDT Time-out, Wake-up On Pin Change,

(1)

W

—

qqqq qqqu

INDF

TMR0

PC

00h

01h

02h

xxxx xxxx

1111 1111

uuuu uuuu

1111 1111

STATUS

FSR

03h

04h

05h

06h

07h

08h

—

0--1 1xxx

111x xxxx

1111 1110

---- xxxx

11-- 1100

xxxx xxxx

1111 1111

---- 1111

q00q quuu

111u uuuu

uuuu uuuu

---- uuuu

11-- 1100

uuuu uuuu

1111 1111

---- 1111

OSCCAL

GPIO

ADCON0

ADRES

OPTION

TRIS

—

Legend:

u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’, q= value depends on condition.

Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XXinstruction at top of memory.

DS41270E-page 34

PIC10F220/222

TABLE 8-2:

RESET CONDITION FOR SPECIAL REGISTERS

STATUS Addr: 03h

PCL Addr: 02h

1111 1111

Power-on Reset

0--1 1xxx

MCLR Reset during normal operation

0--u uuuu

MCLR Reset during Sleep

0--1 0uuu

0--0 0uuu

0--0 uuuu

1--1 0uuu

1111 1111

WDT Reset during Sleep

WDT Reset normal operation

Wake-up from Sleep on pin change

Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’.

The Power-on Reset circuit and the Device Reset

Timer (see Section 8.5 “Device Reset Timer (DRT)”)

circuit are closely related. On power-up, the Reset latch

is set and the DRT is reset. The DRT timer begins

counting once it detects MCLR to be high. After the

time-out period, which is typically 1.125 ms, it will reset

the Reset latch and thus end the on-chip Reset signal.

8.3.1

MCLR ENABLE

This Configuration bit, when unprogrammed (left in the

‘1’ state), enables the external MCLR function. When

programmed, the MCLR function is tied to the internal

VDD and the pin is assigned to be a I/O. See Figure 8-1.

FIGURE 8-1:

MCLR SELECT

A power-up example where MCLR is held low is shown

in Figure 8-3. VDD is allowed to rise and stabilize before

bringing MCLR high. The chip will actually come out of

Reset TDRT msec after MCLR goes high.

GPWU

Weak Pull-up

In Figure 8-4, the on-chip Power-on Reset feature is

being used (MCLR and VDD are tied together or the pin

is programmed to be GP3). The VDD is stable before

the Start-up timer times out and there is no problem in

getting a proper Reset. However, Figure 8-5 depicts a

problem situation where VDD rises too slowly. The time

between when the DRT senses that MCLR is high and

when MCLR and VDD actually reach their full value, is

too long. In this situation, when the start-up timer times

out, VDD has not reached the VDD (min) value and the

chip may not function correctly. For such situations, we

recommend that external RC circuits be used to

achieve longer POR delay times (Figure 8-4).

GP3/MCLR/VPP

Internal MCLR

MCLRE

8.4

Power-on Reset (POR)

The PIC10F220/222 devices incorporate an on-chip

Power-on Reset (POR) circuitry, which provides an

internal chip Reset for most power-up situations.

The on-chip POR circuit holds the chip in Reset until

VDD has reached a high enough level for proper oper-

ation. To take advantage of the internal POR, program

the GP3/MCLR/VPP pin as MCLR and tie through a

resistor to VDD, or program the pin as GP3. An internal

weak pull-up resistor is implemented using a transistor

(refer to Table 10-1 for the pull-up resistor ranges). This

will eliminate external RC components usually needed

to create a Power-on Reset.

Note:

When the devices start normal operation

(exit the Reset condition), device operat-

ing parameters (voltage, frequency, tem-

perature, etc.) must be met to ensure

proper operation. If these conditions are

not met, the device must be held in Reset

until the operating conditions are met.

When the devices start normal operation (exit the

Reset condition), device operating parameters (volt-

age, frequency, temperature,...) must be met to ensure

operation. If these conditions are not met, the devices

must be held in Reset until the operating parameters

are met.

For additional information on design considerations

related to the use of PIC10F220/222 devices with their

short device Reset timer, refer to Application Notes

AN522, “Power-Up Considerations” (DS00522) and

AN607, “Power-up Trouble Shooting” (DS00607).

A simplified block diagram of the on-chip Power-on

Reset circuit is shown in Figure 8-2.

DS41270E-page 35

PIC10F220/222

FIGURE 8-2:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

VDD

Power-up

Detect

POR (Power-on

Reset)

GP3/MCLR/VPP

MCLR Reset

S

R

Q

MCLRE

WDT Reset

WDT Time-out

Start-up Timer

1.125 ms

CHIP Reset

Pin Change

Sleep

Wake-up on pin Change Reset

FIGURE 8-3:

TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)

VDD

MCLR

Internal POR

TDRT

DRT Time-out

Internal Reset

FIGURE 8-4:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE

TIME

VDD

MCLR

Internal POR

TDRT

DRT Time-out

Internal Reset

DS41270E-page 36

PIC10F220/222

FIGURE 8-5:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE

TIME

V1

VDD

MCLR

Internal POR

TDRT

DRT Time-out

Internal Reset

Note:

When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final

value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.

DS41270E-page 37

PIC10F220/222

8.6.1

WDT PERIOD

8.5

Device Reset Timer (DRT)

The WDT has a nominal time-out period of 18 ms, (with

no prescaler). If a longer time-out period is desired, a

prescaler with a division ratio of up to 1:128 can be

assigned to the WDT (under software control) by writ-

ing to the OPTION register. Thus, a time-out period of

a nominal 2.3 seconds can be realized. These periods

vary with temperature, VDD and part-to-part process

variations (see DC specs).

On the PIC10F220/222 devices, the DRT runs any time

the device is powered up.

The DRT operates on an internal oscillator. The pro-

cessor is kept in Reset as long as the DRT is active.

The DRT delay allows VDD to rise above VDD min. and

for the oscillator to stabilize.

The on-chip DRT keeps the devices in a Reset condi-

tion for approximately 1.125 ms after MCLR has

reached a logic high (VIH MCLR) level. Programming

GP3/MCLR/VPP as MCLR and using an external RC

network connected to the MCLR input is not required in

most cases. This allows savings in cost-sensitive and/

or space restricted applications, as well as allowing the

use of the GP3/MCLR/VPP pin as a general purpose

input.

Under worst-case conditions (VDD = Min., Temperature

= Max., max. WDT prescaler), it may take several

seconds before a WDT time-out occurs.

8.6.2

WDT PROGRAMMING

CONSIDERATIONS

The CLRWDT instruction clears the WDT and the

postscaler, if assigned to the WDT, and prevents it from

timing out and generating a device Reset.

The Device Reset Time delays will vary from chip-to-

chip due to VDD, temperature and process variation.

See AC parameters for details.

The SLEEP instruction resets the WDT and the

postscaler, if assigned to the WDT. This gives the

maximum Sleep time before a WDT wake-up Reset.

Reset sources are POR, MCLR, WDT time-out and

wake-up on pin change. See Section 8.9.2 “Wake-up

from Sleep”, Notes 1, 2 and 3.

TABLE 8-3:

DRT (DEVICE RESET TIMER

PERIOD)

POR Reset

Subsequent Resets

1.125 ms (typical)

10 μs (typical)

8.6

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip

RC oscillator, which does not require any external

components. This RC oscillator is separate from the

internal 4/8 MHz oscillator. This means that the WDT

will run even if the main processor clock has been

stopped, for example, by execution of a SLEEPinstruc-

tion. During normal operation or Sleep, a WDT Reset or

wake-up Reset, generates a device Reset.

The TO bit (STATUS<4>) will be cleared upon a

Watchdog Timer Reset.

The WDT can be permanently disabled by program-

ming the configuration WDTE as a ‘0’ (see Section 8.1

“Configuration Bits”). Refer to the PIC10F220/222

Programming Specification to determine how to access

the Configuration Word.

DS41270E-page 38

PIC10F220/222

FIGURE 8-6:

WATCHDOG TIMER BLOCK DIAGRAM

From Timer0 Clock Source

(Figure 6-5)

0

M

U

X

Postscaler

8-to-1 MUX

1

Watchdog

Timer

3

PS<2:0>

PSA

WDT Enable

Configuration

(Figure 6-4)

To Timer0

PSA

Bit

0

1

MUX

WDT Time-out

Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.

TABLE 8-4:

Address

SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Value on

All Other

Resets

Name

Bit 7

Bit 6

Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On

Reset

N/A

OPTION

GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: Shaded boxes = Not used by Watchdog Timer, – = unimplemented, read as ‘0’, u= unchanged.

8.7

Time-out Sequence, Power-down

and Wake-up from Sleep Status

Bits (TO/PD/GPWUF/CWUF)

The TO, PD and GPWUF bits in the STATUS register

can be tested to determine if a Reset condition has

been caused by a Power-up condition, a MCLR,

Watchdog Timer (WDT) Reset or wake-up on pin

change.

TABLE 8-5:

GPWUF

TO/PD/GPWUF STATUS AFTER RESET

TO

PD

Reset Caused By

WDT wake-up from Sleep

0

u

WDT time-out (not from Sleep)

0

1

0

1

MCLR wake-up from Sleep

Power-up

0

1

u

1

u

0

MCLR not during Sleep

Wake-up from Sleep on pin change

Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’, q= value depends on condition.

Note 1: The TO, PD and GPWUF bits maintain their status (u) until a Reset occurs. A low-pulse on the MCLR

input does not change the TO, PD or GPWUF Status bits.

DS41270E-page 39

PIC10F220/222

FIGURE 8-9:

BROWN-OUT

8.8

Reset on Brown-out

PROTECTION CIRCUIT 3

A Brown-out is a condition where device power (VDD)

dips below its minimum value, but not to zero, and then

recovers. The device should be reset in the event of a

Brown-out.

VDD

MCP809

VDD

Bypass

Capacitor

VSS

VDD

To reset PIC10F220/222 devices when a Brown-out

occurs, external Brown-out protection circuits may be

built, as shown in Figure 8-7 and Figure 8-8.

RST

(2)

MCLR

PIC10F22X

FIGURE 8-7:

BROWN-OUT

PROTECTION CIRCUIT 1

Note 1: This Brown-out Protection circuit employs

Microchip Technology’s MCP809 micro-

controller supervisor. There are 7 different

trip point selections to accommodate 5V to

3V systems.

VDD

33k

2: Pin must be configured as MCLR.

PIC10F22X

Q1

(2)

MCLR

10k

(1)

8.9

Power-down Mode (Sleep)

40k

A device may be powered down (Sleep) and later

powered up (wake-up from Sleep).

Note 1: This circuit will activate Reset when VDD goes

below Vz + 0.7V (where Vz = Zener voltage).

2: Pin must be configured as MCLR.

8.9.1

SLEEP

The Power-Down mode is entered by executing a

SLEEPinstruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the TO bit (STATUS<4>) is set, the PD

bit (STATUS<3>) is cleared and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, driving low or high-impedance).

FIGURE 8-8:

BROWN-OUT

PROTECTION CIRCUIT 2

VDD

R1

R2

Note:

A Reset generated by a WDT time-out

does not drive the MCLR pin low.

PIC10F22X

Q1

(2)

MCLR

For lowest current consumption while powered down,

the T0CKI input should be at VDD or VSS and the GP3/

MCLR/VPP pin must be at a logic high level if MCLR is

enabled.

(1)

40k

Note 1: This brown-out circuit is less expensive,

although less accurate. Transistor Q1 turns

off when VDD is below a certain level such

that:

R1

= 0.7V

VDD •

R1 + R2

2: Pin must be configured as MCLR.

DS41270E-page 40

PIC10F220/222

8.9.2

WAKE-UP FROM SLEEP

8.12 In-Circuit Serial Programming™

The device can wake-up from Sleep through one of the

following events:

The PIC10F220/222 microcontrollers can be serially

programmed while in the end application circuit. This is

simply done with two lines for clock and data, and three

other lines for power, ground and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware, or a custom

firmware, to be programmed.

1. An external Reset input on GP3/MCLR/VPP pin,

when configured as MCLR.

2. A Watchdog Timer Time-out Reset (if WDT was

enabled).

3. A change on input pin GP0, GP1 or GP3 when

wake-up on change is enabled.

These events cause a device Reset. The TO, PD

GPWUF bits can be used to determine the cause of a

device Reset. The TO bit is cleared if a WDT time-out

occurred (and caused wake-up). The PD bit, which is

set on power-up, is cleared when SLEEP is invoked.

The GPWUF bit indicates a change in state while in

Sleep at pins GP0, GP1 or GP3 (since the last file or bit

operation on GP port).

The devices are placed into a Program/Verify mode by

holding the GP1 and GP0 pins low while raising the

MCLR (VPP) pin from VIL to VIHH (see programming

specification). GP1 becomes the programming clock

and GP0 becomes the programming data. Both GP1

and GP0 are Schmitt Trigger inputs in this mode.

After Reset, a 6-bit command is then supplied to the

device. Depending on the command, 16 bits of program

data are then supplied to or from the device, depending

if the command was a Load or a Read. For complete

details of serial programming, please refer to the

PIC10F220/222 Programming Specifications.

Caution: Right before entering Sleep, read the

input pins. When in Sleep, wake up

occurs when the values at the pins

change from the state they were in at the

last reading. If a wake-up on change

occurs and the pins are not read before

re-entering Sleep, a wake-up will occur

immediately even if no pins change

while in Sleep mode.

A typical In-Circuit Serial Programming connection is

shown in Figure 8-10.

FIGURE 8-10:

TYPICAL IN-CIRCUIT

SERIAL

PROGRAMMING™

CONNECTION

Note:

The WDT is cleared when the device

wakes from Sleep, regardless of the wake-

up source.

To Normal

Connections

External

Connector

Signals

PIC10F22X

8.10 Program Verification/Code

Protection

+5V

0V

VDD

If the Code Protection bit has not been programmed,

the on-chip program memory can be read out for

verification purposes.

VSS

VPP

MCLR/VPP

GP1

GP0

CLK

The first 64 locations and the last location (Reset

Vector) can be read, regardless of the code protection

bit setting.

Data I/O

VDD

8.11 ID Locations

Four memory locations are designated as ID locations

where the user can store checksum or other code

identification numbers. These locations are not

accessible during normal execution, but are readable

and writable during program/verify.

To Normal

Connections

Use only the lower 4 bits of the ID locations and always

program the upper 8 bits as ‘1’s.

DS41270E-page 41

PIC10F220/222

NOTES:

DS41270E-page 42

PIC10F220/222

All instructions are executed within a single instruction

cycle, unless a conditional test is true or the program

counter is changed as a result of an instruction. In this

case, the execution takes two instruction cycles. One

instruction cycle consists of four oscillator periods.

Thus, for an oscillator frequency of 4 MHz, the normal

instruction execution time is 1 μs. If a conditional test is

true or the program counter is changed as a result of an

instruction, the instruction execution time is 2 μs.

9.0

INSTRUCTION SET SUMMARY

The PIC16 instruction set is highly orthogonal and is

comprised of three basic categories.

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations

Each PIC16 instruction is a 12-bit word divided into an

opcode, which specifies the instruction type, and one

or more operands which further specify the operation

of the instruction. The formats for each of the catego-

ries is presented in Figure 9-1, while the various

opcode fields are summarized in Table 9-1.

Figure 9-1 shows the three general formats that the

instructions can have. All examples in the figure use

the following format to represent a hexadecimal

number:

‘0xhhh’

For byte-oriented instructions, ‘f’ represents a file reg-

ister designator and ‘d’ represents a destination desig-

nator. The file register designator specifies which file

register is to be used by the instruction.

where ‘h’ signifies a hexadecimal digit.

FIGURE 9-1:

GENERAL FORMAT FOR

INSTRUCTIONS

The destination designator specifies where the result of

the operation is to be placed. If ‘d’ is ‘0’, the result is

placed in the W register. If ‘d’ is ‘1’, the result is placed

in the file register specified in the instruction.

Byte-oriented file register operations

11

6

5

d

4

0

OPCODE

f (FILE #)

For bit-oriented instructions, ‘b’ represents a bit field

designator which selects the number of the bit affected

by the operation, while ‘f’ represents the number of the

file in which the bit is located.

d = 0for destination W

d = 1for destination f

f = 5-bit file register address

Bit-oriented file register operations

11 8 7

b (BIT #)

For literal and control operations, ‘k’ represents an

8 or 9-bit constant or literal value.

5

4

0

OPCODE

f (FILE #)

b = 3-bit address

f = 5-bit file register address

TABLE 9-1:

OPCODE FIELD

DESCRIPTIONS

Literal and control operations (except GOTO)

11

Field

Description

f

W

b

Register file address (0x00 to 0x7F)

Working register (accumulator)

8

7

0

OPCODE

k (literal)

Bit address within an 8-bit file register

Literal field, constant data or label

k = 8-bit immediate value

k

x

Don’t care location (= 0or 1)

Literal and control operations – GOTOinstruction

11

The assembler will generate code with x = 0. It is the

recommended form of use for compatibility with all

Microchip software tools.

9

8

0

OPCODE

k (literal)

d

Destination select;

d= 0(store result in W)

d= 1(store result in file register ‘f’)

Default is d= 1

k = 9-bit immediate value

label

TOS

PC

Label name

Top-of-Stack

Program Counter

Watchdog Timer counter

Time-out bit

WDT

TO

PD

Power-down bit

dest

Destination, either the W register or the specified

register file location

[

(

]

)

Options

Contents

→

Assigned to

< >

∈

Register bit field

In the set of

italics

User defined term (font is courier)

DS41270E-page 43

PIC10F220/222

TABLE 9-2:

INSTRUCTION SET SUMMARY

Description

12-Bit Opcode

MSb LSb

Mnemonic,

Operands

Status

Affected

Cycles

Notes

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

f, d

f

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate left f through Carry

Rotate right f through Carry

Subtract W from f

Swap f

1

0001 11df ffff C,DC,Z

1,2,4

2,4

4

0001 01df ffff

0000 011f ffff

0000 0100 0000

0010 01df ffff

0000 11df ffff

0010 11df ffff

0010 10df ffff

0011 11df ffff

0001 00df ffff

0010 00df ffff

0000 001f ffff

0000 0000 0000

0011 01df ffff

0011 00df ffff

Z

None

Z

None

Z

–

f, d

f

1

2,4

1,4

1⁽²⁾

1

1⁽²⁾

1

Z

None

C

–

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

2,4

1,2,4

2,4

C

0000 10df ffff C,DC,Z

0011 10df ffff

0001 10df ffff

None

Z

Exclusive OR W with f

2,4

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1

0100 bbbf ffff

None

2,4

0101 bbbf ffff

0110 bbbf ffff

0111 bbbf ffff

1⁽²⁾

LITERAL AND CONTROL OPERATIONS

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

OPTION

RETLW

SLEEP

TRIS

k

–

k

–

f

AND literal with W

Call subroutine

1

2

1

2

1

2

1

1110 kkkk kkkk

1001 kkkk kkkk

0000 0000 0100 TO, PD

101k kkkk kkkk

1101 kkkk kkkk

1100 kkkk kkkk

0000 0000 0010

1000 kkkk kkkk

Z

None

1

Clear Watchdog Timer

Unconditional branch

Inclusive OR Literal with W

Move Literal to W

Load OPTION register

Return, place Literal in W

Go into standby mode

Load TRIS register

None

Z

None

0000 0000 0011 TO, PD

0000 0000 0fff

1111 kkkk kkkk

None

Z

3

XORLW

k

Exclusive OR Literal to W

Note 1: The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for

GOTO. See Section 4.7 “Program Counter”.

2: When an I/O register is modified as a function of itself (e.g., MOVF PORTB, 1), the value used will be that

value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and

is driven low by an external device, the data will be written back with a ‘0’.

3: The instruction TRIS f, where f = 6 causes the contents of the W register to be written to the tri-state

latches of PORTB. A ‘1’ forces the pin to a high-impedance state and disables the output buffers.

4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be

cleared (if assigned to TMR0).

DS41270E-page 44

PIC10F220/222

9.1

Instruction Description

ADDWF

Add W and f

BCF

Bit Clear f

Syntax:

[ label ] ADDWF f,d

Syntax:

[ label ] BCF f,b

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operation:

(W) + (f) → (destination)

Operation:

0 → (f<b>)

Status Affected: C, DC, Z

Status Affected: None

Description:

Add the contents of the W register

Description:

Bit ‘b’ in register ‘f’ is cleared.

and register ‘f’. If ‘d’ is ‘0’, the result

is stored in the W register. If ‘d’ is

‘1’, the result is stored back in

register ‘f’.

ANDLW

AND literal with W

BSF

Bit Set f

Syntax:

Operands:

[ label ] ANDLW

0 ≤ k ≤ 255

k

Syntax:

[ label ] BSF f,b

Operands:

0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operation:

(W).AND. (k) → (W)

Operation:

1 → (f<b>)

Status Affected:

Description:

Z

Status Affected: None

The contents of the W register are

AND’ed with the eight-bit literal ‘k’.

The result is placed in the W

register.

Description: Bit ‘b’ in register ‘f’ is set.

BTFSC

Bit Test f, Skip if Clear

ANDWF

AND W with f

Syntax:

[ label ] BTFSC f,b

Syntax:

[ label ] ANDWF f,d

Operands:

0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

skip if (f<b>) = 0

Operation:

(W) AND (f) → (destination)

Status Affected: None

Status Affected: Z

Description: If bit ‘b’ in register ‘f’ is ‘0’, then the

Description: The contents of the W register are

next instruction is skipped.

AND’ed with register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W register.

If ‘d’ is ‘1’, the result is stored back

in register ‘f’.

If bit ‘b’ is ‘0’, then the next instruc-

tion fetched during the current

instruction execution is discarded,

and a NOPis executed instead,

making this a two-cycle instruction.

DS41270E-page 45

PIC10F220/222

CLRW

Clear W

BTFSS

Bit Test f, Skip if Set

Syntax:

[ label ] CLRW

None

Syntax:

[ label ] BTFSS f,b

Operands:

Operation:

Operands:

0 ≤ f ≤ 31

0 ≤ b < 7

00h → (W);

1 → Z

Operation:

skip if (f<b>) = 1

Status Affected:

Description:

Z

Status Affected: None

The W register is cleared. Zero bit

(Z) is set.

Description:

If bit ‘b’ in register ‘f’ is ‘1’, then the

next instruction is skipped.

If bit ‘b’ is ‘1’, then the next instruc-

tion fetched during the current

instruction execution, is discarded

and a NOPis executed instead,

making this a two-cycle instruction.

CLRWDT

Syntax:

Clear Watchdog Timer

[ label ] CLRWDT k

None

CALL

Subroutine Call

Syntax:

[ label ] CALL

0 ≤ k ≤ 255

k

Operands:

Operation:

Operands:

Operation:

00h → WDT;

0 → WDT prescaler (if assigned);

(PC) + 1→ Top of Stack;

k → PC<7:0>;

1 → TO;

1 → PD

(Status<6:5>) → PC<10:9>;

0 → PC<8>

Status Affected: TO, PD

Status Affected: None

Description:

The CLRWDTinstruction resets the

Description:

Subroutine call. First, return

WDT. It also resets the prescaler, if

the prescaler is assigned to the

WDT and not Timer0. Status bits

TO and PD are set.

address (PC + 1) is pushed onto

the stack. The eight-bit immediate

address is loaded into PC bits

<7:0>. The upper bits PC<10:9>

are loaded from STATUS<6:5>,

PC<8> is cleared. CALLis a two-

cycle instruction.

CLRF

Clear f

COMF

Complement f

Syntax:

[ label ] CLRF

0 ≤ f ≤ 31

f

Syntax:

Operands:

[ label ] COMF f,d

Operands:

Operation:

0 ≤ f ≤ 31

d ∈ [0,1]

00h → (f);

1 → Z

Operation:

(f) → (dest)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

The contents of register ‘f’ are

cleared and the Z bit is set.

The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the

result is stored in the W register. If

‘d’ is ‘1’, the result is stored back in

register ‘f’.

DS41270E-page 46

PIC10F220/222

DECF

Decrement f

INCF

Increment f

Syntax:

Operands:

[ label ] DECF f,d

Syntax:

Operands:

[ label ] INCF f,d

0 ≤ f ≤ 31

d ∈ [0,1]

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

(f) – 1 → (dest)

Operation:

(f) + 1 → (dest)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

INCFSZ

Syntax:

Increment f, Skip if 0

DECFSZ

Syntax:

Decrement f, Skip if 0

[ label ] INCFSZ f,d

[ label ] DECFSZ f,d

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

(f) + 1 → (dest), skip if result = 0

Operation:

(f) – 1 → d; skip if result = 0

Status Affected: None

Description:

The contents of register ‘f’ are

Description:

The contents of register ‘f’ are dec-

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

remented. If ‘d’ is ‘0’, the result is

placed in the W register. If ‘d’ is ‘1’,

the result is placed back in register

‘f’.

If the result is ‘0’, then the next

instruction, which is already

fetched, is discarded and a NOPis

executed instead making it a two-

cycle instruction.

If the result is ‘0’, the next instruc-

tion, which is already fetched, is

discarded and a NOPis executed

instead making it a two-cycle

instruction.

IORLW

Inclusive OR literal with W

[ label ] IORLW k

0 ≤ k ≤ 255

GOTO

Unconditional Branch

[ label ] GOTO k

0 ≤ k ≤ 511

Syntax:

Operands:

Operation:

Status Affected:

Description:

Operands:

Operation:

(W) .OR. (k) → (W)

Z

k → PC<8:0>;

STATUS<6:5> → PC<10:9>

Status Affected: None

The contents of the W register are

OR’ed with the eight-bit literal ‘k’.

The result is placed in the W

register.

Description: GOTOis an unconditional branch.

The 9-bit immediate value is

loaded into PC bits <8:0>. The

upper bits of PC are loaded from

STATUS<6:5>. GOTOis a two-

cycle instruction.

DS41270E-page 47

PIC10F220/222

IORWF

Inclusive OR W with f

MOVWF

Syntax:

Move W to f

[ label ] MOVWF

0 ≤ f ≤ 31

Syntax:

[ label ] IORWF f,d

f

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

Operation:

(W) → (f)

Operation:

(W).OR. (f) → (dest)

Status Affected: None

Status Affected:

Description:

Z

Description:

Move data from the W register to

register ‘f’.

Inclusive OR the W register with

register ‘f’. If ‘d’ is ‘0’, the result is

placed in the W register. If ‘d’ is ‘1’,

the result is placed back in register

‘f’.

MOVF

Move f

NOP

No Operation

[ label ] NOP

None

Syntax:

Operands:

[ label ] MOVF f,d

Syntax:

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

Operation:

No operation

Operation:

(f) → (dest)

Status Affected: None

Status Affected:

Description:

Z

Description:

No operation.

The contents of register ‘f’ are

moved to destination ‘d’. If ‘d’ is ‘0’,

destination is the W register. If ‘d’

is ‘1’, the destination is file register

‘f’. ‘d’ = 1is useful as a test of a file

register, since status flag Z is

affected.

MOVLW

Syntax:

Move Literal to W

[ label ] MOVLW k

0 ≤ k ≤ 255

OPTION

Syntax:

Load OPTION Register

[ label ] OPTION

None

Operands:

Operation:

Operands:

Operation:

(W) → OPTION

k → (W)

Status Affected: None

Description: The content of the W register is

Description:

The eight-bit literal ‘k’ is loaded

into the W register. The “don’t

loaded into the OPTION register.

cares” will assembled as ‘0’s.

DS41270E-page 48

PIC10F220/222

RETLW

Return with Literal in W

SLEEP

Enter SLEEP Mode

Syntax:

[ label ] RETLW

0 ≤ k ≤ 255

k

Syntax:

[label]

SLEEP

Operands:

Operation:

Operands:

Operation:

None

k → (W);

TOS → PC

00h → WDT;

0→ WDT prescaler;

1→ TO;

Status Affected: None

0→ PD

Description:

The W register is loaded with the

eight-bit literal ‘k’. The program

counter is loaded from the top of

the stack (the return address). This

is a two-cycle instruction.

Status Affected: TO, PD, RBWUF

Description:

Time-out Status bit (TO) is set. The

Power-down Status bit (PD) is

cleared.

RBWUF is unaffected.

The WDT and its prescaler are

cleared.

The processor is put into Sleep

mode with the oscillator stopped.

See section on Sleep for more

details.

RLF

Rotate Left f through Carry

SUBWF

Subtract W from f

Syntax:

Operands:

[ label ]

RLF f,d

Syntax:

[label] SUBWF f,d

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

See description below

C

Operation:

(f) – (W) → (dest)

Status Affected:

Description:

Status Affected: C, DC, Z

The contents of register ‘f’ are

rotated one bit to the left through

the Carry Flag. If ‘d’ is ‘0’, the

result is placed in the W register. If

‘d’ is ‘1’, the result is stored back in

register ‘f’.

Description:

Subtract (2’s complement method)

the W register from register ‘f’. If ‘d’

is ‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

register ‘f’

C

RRF

Rotate Right f through Carry

SWAPF

Syntax:

Swap Nibbles in f

Syntax:

Operands:

[ label ] RRF f,d

[label] SWAPF f,d

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

See description below

C

Operation:

(f<3:0>) → (dest<7:4>);

(f<7:4>) → (dest<3:0>)

Status Affected:

Description:

Status Affected: None

The contents of register ‘f’ are

rotated one bit to the right through

the Carry Flag. If ‘d’ is ‘0’, the

result is placed in the W register. If

‘d’ is ‘1’, the result is placed back

in register ‘f’.

Description: The upper and lower nibbles of

register ‘f’ are exchanged. If ‘d’ is

‘0’, the result is placed in W

register. If ‘d’ is ‘1’, the result is

placed in register ‘f’.

register ‘f’

C

DS41270E-page 49

PIC10F220/222

TRIS

Load TRIS Register

Syntax:

[ label ] TRIS

f

Operands:

Operation:

f = 6

(W) → TRIS register f

Status Affected: None

Description:

TRIS register ‘f’ (f = 6 or 7) is

loaded with the contents of the W

register

XORLW

Exclusive OR literal with W

Syntax:

[label] XORLW k

0 ≤ k ≤ 255

Operands:

Operation:

(W) .XOR. k → (W)

Z

Status Affected:

Description:

The contents of the W register are

XOR’ed with the eight-bit literal ‘k’.

The result is placed in the W

register.

XORWF

Syntax:

Exclusive OR W with f

[ label ] XORWF f,d

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

(W) .XOR. (f) → (dest)

Status Affected:

Description:

Z

Exclusive OR the contents of the

W register with register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

DS41270E-page 50

PIC10F220/222

10.0 ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

Ambient temperature under bias.............................................................................................................-40°C to +125°C

Storage temperature ...............................................................................................................................-65°C to +150°C

Voltage on VDD with respect to VSS ..................................................................................................................0 to +6.5V

Voltage on MCLR with respect to VSS.............................................................................................................0 to +13.5V

Voltage on all other pins with respect to VSS .................................................................................. -0.3V to (VDD + 0.3V)

Total power dissipation⁽¹⁾.....................................................................................................................................800 mW

Max. current out of VSS pin .....................................................................................................................................80 mA

Max. current into VDD pin........................................................................................................................................80 mA

Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................................±20 mA

Output clamp current, IOK (VO < 0 or VO > VDD) ..............................................................................................................±20 mA

Max. output current sunk by any I/O pin .................................................................................................................25 mA

Max. output current sourced by any I/O pin............................................................................................................25 mA

Max. output current sourced by I/O port .................................................................................................................75 mA

Max. output current sunk by I/O port ......................................................................................................................75 mA

Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} .. + ∑(VOL x

IOL)

^†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above

those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions

for extended periods may affect device reliability.

DS41270E-page 51

PIC10F220/222

FIGURE 10-1:

6.0

VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C

5.5

5.0

4.5

4.0

3.5

VDD

(Volts)

3.0

2.5

2.0

8

0

4

10

20

25

Frequency (MHz)

DS41270E-page 52

PIC10F220/222

10.1 DC Characteristics: PIC10F220/222 (Industrial)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40×C ≤ TA ≤ +85°C (industrial)

DC CHARACTERISTICS

Param

Sym

No.

(1)

Characteristic

Min Typ

Max Units

Conditions

D001

D002

D003

VDD Supply Voltage

2.0

5.5

—

V

See Figure 10-1

(2)

VDR RAM Data Retention Voltage

1.5*

—

Device in Sleep mode

VPOR VDD Start Voltage

Vss

—

to ensure Power-on Reset

D004

D010

SVDD VDD Rise Rate

to ensure Power-on Reset

(3)

0.05*

—

V/ms

IDD

IPD

Supply Current

—

175

0.625

250

275

1.1

400

1.5

μA

mA

μA

VDD = 2.0V, Fosc = 4 MHz

VDD = 5.0V, Fosc = 4 MHz

VDD = 2.0V, Fosc = 8 MHz

VDD = 5.0V, Fosc = 8 MHz

0.800

mA

(4)

Power-down Current

D020

D022

—

0.1

1

1.2

2.4

μA

VDD = 2.0V

VDD = 5.0V

(4)

IWDT WDT Current

—

1.0

7

3

16

μA

VDD = 2.0V

VDD = 5.0V

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only

and is not tested.

2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, bus

rate, internal code execution pattern and temperature also have an impact on the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

All I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that the device is in Sleep mode.

4: Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD

or VSS. The peripheral current is the sum of the base IPD and the additional current consumed when the peripheral is

enabled.

DS41270E-page 53

PIC10F220/222

10.2 DC Characteristics: PIC10F220/222 (Extended)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40×C £ TA £ +125×C (extended)

DC CHARACTERISTICS

Param

Sym

No.

(1)

Characteristic

Supply Voltage

Min

Typ

Max

Units

Conditions

D001

D002

D003

VDD

VDR

2.0

1.5*

—

5.5

—

V

See Figure 10-1

(2)

RAM Data Retention Voltage

Device in Sleep mode

VPOR

VDD Start Voltage

Vss

—

to ensure Power-on Reset

(3)

IDD

Supply Current

D010

—

175

0.625

250

275

1.1

400

1.5

μA

mA

μA

VDD = 2.0V, Fosc = 4 MHz

VDD = 5.0V, Fosc = 4 MHz

VDD = 2.0V, Fosc = 8 MHz

VDD = 5.0V, Fosc = 8 MHz

0.800

mA

(4)

IPD

Power-down Current

D020

D022

—

0.1

1

9

15

μA

VDD = 2.0V

VDD = 5.0V

(4)

IWDT

WDT Current

—

1.0

7

18

22