PIC12C509T-04E_技术文档

PIC12C5XX

8-Pin, 8-Bit CMOS Microcontrollers

Devices included in this Data Sheet:

Peripheral Features:

• PIC12C508 • PIC12C508A

• PIC12C509 • PIC12C509A

• PIC12CR509A

•

PIC12CE518

PIC12CE519

• 8-bit real time clock/counter (TMR0) with 8-bit

programmable prescaler

• Power-On Reset (POR)

• Device Reset Timer (DRT)

Note: Throughout this data sheet PIC12C5XX

refers to the PIC12C508, PIC12C509,

PIC12C508A, PIC12C509A,

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

PIC12CR509A, PIC12CE518 and

PIC12CE519. PIC12CE5XX refers to

PIC12CE518 and PIC12CE519.

• Programmable code-protection

• 1,000,000 erase/write cycle EEPROM data

memory

• EEPROM data retention > 40 years

• Power saving SLEEP mode

High-Performance RISC CPU:

• Only 33 single word instructions to learn

• Wake-up from SLEEP on pin change

• Internal weak pull-ups on I/O pins

• Internal pull-up on MCLR pin

• All instructions are single cycle (1 µs) except for

program branches which are two-cycle

• Operating speed: DC - 4 MHz clock input

DC - 1 µs instruction cycle

• Selectable oscillator options:

- INTRC: Internal 4 MHz RC oscillator

- EXTRC: External low-cost RC oscillator

Memory

Device

EPROM

ROM

RAM EEPROM

- XT:

- LP:

Standard crystal/resonator

Program

Data

Power saving, low frequency crystal

PIC12C508

512 x 12

1024 x 12

512 x 12

1024 x 12

25

41

25

41

PIC12C508A

PIC12C509

CMOS Technology:

• Low power, high speed CMOS EPROM/ROM

technology

PIC12C509A

PIC12CE518

PIC12CE519

PIC12CR509A

16

• Fully static design

• Wide operating voltage range

1024 x 12

• Wide temperature range:

- Commercial: 0°C to +70°C

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

• 12-bit wide instructions

• 8-bit wide data path

• Seven special function hardware registers

• Two-level deep hardware stack

• Low power consumption

- < 2 mA @ 5V, 4 MHz

- 15 µA typical @ 3V, 32 KHz

- < 1 µA typical standby current

• Direct, indirect and relative addressing modes for

data and instructions

• Internal 4 MHz RC oscillator with programmable

calibration

• In-circuit serial programming

1999 Microchip Technology Inc.

DS40139E-page 1

PIC12C5XX

Pin Diagram - PIC12C508/509

PDIP, 208 mil SOIC, Windowed Ceramic Side Brazed

VSS

VDD

1

2

3

4

8

7

6

5

GP0

GP5/OSC1/CLKIN

GP4/OSC2

GP1

GP3/MCLR/VPP

GP2/T0CKI

Pin Diagram - PIC12C508A/509A,

PIC12CE518/519

PDIP, 150 & 208 mil SOIC, Windowed CERDIP

VSS

VDD

1

2

3

4

8

7

6

5

GP0

GP5/OSC1/CLKIN

GP4/OSC2

GP1

GP3/MCLR/VPP

GP2/T0CKI

Pin Diagram - PIC12CR509A

PDIP, 150 & 208 mil SOIC

VSS

VDD

1

8

7

6

5

GP0

GP5/OSC1/CLKIN

GP4/OSC2

2

3

4

GP1

GP3/MCLR/VPP

GP2/T0CKI

Device Differences

Device

Oscillator

Process

Technology

(Microns)

Voltage

Range

2

Oscillator

Calibration

(Bits)

PIC12C508A

PIC12LC508A

PIC12C508

3.0-5.5

2.5-5.5

3.0-5.5

2.5-5.5

3.0-5.5

2.5-5.5

3.0-5.5

2.5-5.5

See Note 1

6

4

6

4

6

0.7

0.9

0.7

0.9

0.7

See Note 1

PIC12C509A

PIC12LC509A

PIC12C509

See Note 1

PIC12CR509A

PIC12CE518

PIC12LCE518

PIC12CE519

PIC12LCE519

See Note 1

-

Note 1: If you change from the PIC12C50X to the PIC12C50XA or to the PIC12CR50XA, please verify

oscillator characteristics in your application.

Note 2: See Section 7.2.5 for OSCCAL implementation differences.

DS40139E-page 2

1999 Microchip Technology Inc.

PIC12C5XX

TABLE OF CONTENTS

1.0 General Description............................................................................................................................................... 4

2.0 PIC12C5XX Device Varieties ................................................................................................................................ 7

3.0 Architectural Overview........................................................................................................................................... 9

4.0 Memory Organization .......................................................................................................................................... 13

5.0 I/O Port ................................................................................................................................................................ 21

6.0 Timer0 Module and TMR0 Register .................................................................................................................... 25

7.0 EEPROM Peripheral Operation........................................................................................................................... 29

8.0 Special Features of the CPU............................................................................................................................... 35

9.0 Instruction Set Summary ..................................................................................................................................... 47

10.0 Development Support.......................................................................................................................................... 59

11.0 Electrical Characteristics - PIC12C508/PIC12C509............................................................................................ 65

12.0 DC and AC Characteristics - PIC12C508/PIC12C509 ........................................................................................ 75

13.0 Electrical Characteristics PIC12C508A/PIC12C509A/PIC12LC508A/PIC12LC509A/PIC12CR509A/

PIC12CE518/PIC12CE519/

PIC12LCE518/PIC12LCE519/PIC12LCR509A................................................................................................... 79

14.0 DC and AC Characteristics

PIC12C508A/PIC12C509A/PIC12LC508A/PIC12LC509A/PIC12CE518/PIC12CE519/PIC12CR509A/

PIC12LCE518/PIC12LCE519/ PIC12LCR509A.................................................................................................. 93

15.0 Packaging Information......................................................................................................................................... 99

Index ........................................................................................................................................................................... 105

PIC12C5XX Product Identification System ................................................................................................................ 109

Sales and Support: ..................................................................................................................................................... 109

To Our Valued Customers

Most Current Data Sheet

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner

of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of doc-

ument DS30000.

Errata

An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and rec-

ommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The

errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

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• The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277

When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet

(include literature number) you are using.

Corrections to this Data Sheet

We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time

to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any

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We appreciate your assistance in making this a better document.

1999 Microchip Technology Inc.

DS40139E-page 3

PIC12C5XX

1.1

Applications

1.0

GENERAL DESCRIPTION

The PIC12C5XX from Microchip Technology is a fam-

ily of low-cost, high performance, 8-bit, fully static,

EEPROM/EPROM/ROM-based CMOS microcontrol-

lers. It employs a RISC architecture with only 33 sin-

gle word/single cycle instructions. All instructions are

single cycle (1 µs) except for program branches

which take two cycles. The PIC12C5XX delivers per-

formance an order of magnitude higher than its com-

petitors in the same price category. The 12-bit wide

instructions are highly symmetrical resulting in 2:1

code compression over other 8-bit microcontrollers in

its class. The easy to use and easy to remember

instruction set reduces development time signifi-

cantly.

The PIC12C5XX series fits perfectly in applications

ranging from personal care appliances and security

systems to low-power remote transmitters/receivers.

The EPROM technology makes customizing applica-

tion programs (transmitter codes, appliance settings,

receiver frequencies, etc.) extremely fast and conve-

nient, while the EEPROM data memory technology

allows for the changing of calibration factors and secu-

rity codes. The small footprint packages, for through

hole or surface mounting, make this microcontroller

series perfect for applications with space limitations.

Low-cost, low-power, high performance, ease of use

and I/O flexibility make the PIC12C5XX series very ver-

satile even in areas where no microcontroller use has

been considered before (e.g., timer functions, replace-

ment of “glue” logic and PLD’s in larger systems, copro-

cessor applications).

The PIC12C5XX products are equipped with special

features that reduce system cost and power require-

ments. The Power-On Reset (POR) and Device Reset

Timer (DRT) eliminate the need for external reset cir-

cuitry. There are four oscillator configurations to choose

from, including INTRC internal oscillator mode and the

power-saving LP (Low Power) oscillator mode. Power

saving SLEEP mode, Watchdog Timer and code

protection features also improve system cost, power

and reliability.

The PIC12C5XX are available in the cost-effective

One-Time-Programmable (OTP) versions which are

suitable for production in any volume. The customer

can take full advantage of Microchip’s price leadership

in OTP microcontrollers while benefiting from the OTP’s

flexibility.

The PIC12C5XX products are supported by a full-fea-

tured macro assembler, a software simulator, an in-cir-

cuit emulator, a ‘C’ compiler, fuzzy logic support tools,

a low-cost development programmer, and a full fea-

tured programmer. All the tools are supported on IBM

PC and compatible machines.

DS40139E-page 4

1999 Microchip Technology Inc.

PIC12C5XX

TABLE 1-1:

PIC12CXXX & PIC12CEXXX FAMILY OF DEVICES

PIC12C508(A) PIC12C509(A) PIC12CR509A PIC12CE518 PIC12CE519 PIC12C671 PIC12C672 PIC12CE673 PIC12CE674

Maximum

4

10

Frequency

of Operation

(MHz)

Clock

EPROM

Program

Memory

512 x 12

1024 x 12

(ROM)

512 x 12

25

1024 x 12

1024 x 14

128

2048 x 14 1024 x 14

2048 x 14

128

Memory

RAM Data

Memory

(bytes)

25

41

128

EEPROM

Data Memory

(bytes)

—

16

—

16

Timer

Module(s)

TMR0

—

TMR0

—

TMR0

—

TMR0

—

TMR0

—

TMR0

4

TMR0

4

TMR0

4

TMR0

4

Peripherals

A/D Con-

verter (8-bit)

Channels

Wake-up

from SLEEP

on pin

Yes

—

Yes

—

Yes

—

Yes

4

Yes

4

Yes

4

Yes

4

change

Interrupt

Sources

I/O Pins

5

Features

Input Pins

1

Internal

Pull-ups

Yes

In-Circuit

Serial

Programming

Yes

33

Yes

33

—

Yes

33

Yes

33

Yes

35

Yes

35

Yes

35

Yes

35

Number of

Instructions

33

Packages

8-pin DIP,

JW, SOIC

8-pin DIP,

JW, SOIC

8-pin DIP,

SOIC

8-pin DIP,

JW, SOIC

8-pin DIP,

JW, SOIC

8-pin DIP,

JW, SOIC

8-pin DIP, 8-pin DIP,

JW, SOIC JW

8-pin DIP,

JW

All PIC12CXXX & PIC12CEXXX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O

current capability.

All PIC12CXXX & PIC12CEXXX devices use serial programming with data pin GP0 and clock pin GP1.

1999 Microchip Technology Inc.

DS40139E-page 5

PIC12C5XX

NOTES:

DS40139E-page 6

1999 Microchip Technology Inc.

PIC12C5XX

2.3

Quick-Turnaround-Production (QTP)

Devices

2.0

PIC12C5XX DEVICE VARIETIES

A

variety of packaging options are available.

Depending on application and production

Microchip offers

a QTP Programming Service for

requirements, the proper device option can be

selected using the information in this section. When

placing orders, please use the PIC12C5XX Product

Identification System at the back of this data sheet to

specify the correct part number.

factory production orders. This service is made

available for users who choose not to program a

medium to high quantity of units and whose code

patterns have stabilized. The devices are identical to

the OTP devices but with all EPROM locations and fuse

options already programmed by the factory. Certain

code and prototype verification procedures do apply

before production shipments are available. Please con-

tact your local Microchip Technology sales office for

more details.

2.1

UV Erasable Devices

The UV erasable version, offered in ceramic side

brazed package, is optimal for prototype development

and pilot programs.

The UV erasable version can be erased and

reprogrammed to any of the configuration modes.

2.4

Serialized Quick-Turnaround

Production (SQTP^SM) Devices

Note: Please note that erasing the device will

also erase the pre-programmed internal

calibration value for the internal oscillator.

The calibration value must be saved prior

to erasing the part.

Microchip offers a unique programming service where

few user-defined locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or

sequential.

a

Microchip’s PICSTART PLUS and PRO MATE pro-

grammers all support programming of the PIC12C5XX.

Third party programmers also are available; refer to the

Microchip Third Party Guide for a list of sources.

Serial programming allows each device to have a

unique number which can serve as an entry-code,

password or ID number.

2.5

Read Only Memory (ROM) Device

2.2

One-Time-Programmable (OTP)

Devices

Microchip offers masked ROM to give the customer a

low cost option for high volume, mature products.

The availability of OTP devices is especially useful for

customers who need the flexibility for frequent code

updates or small volume applications.

The OTP devices, packaged in plastic packages permit

the user to program them once. In addition to the

program memory, the configuration bits must also be

programmed.

1999 Microchip Technology Inc.

DS40139E-page 7

PIC12C5XX

NOTES:

DS40139E-page 8

1999 Microchip Technology Inc.

PIC12C5XX

The PIC12C5XX device contains an 8-bit ALU and

3.0

ARCHITECTURAL OVERVIEW

working register. The ALU is

a general purpose

The high performance of the PIC12C5XX family can

be attributed to a number of architectural features

commonly found in RISC microprocessors. To begin

with, the PIC12C5XX uses a Harvard architecture in

which program and data are accessed on separate

buses. This improves bandwidth over traditional von

Neumann architecture where program and data are

fetched on the same bus. Separating program and

data memory further allows instructions to be sized

differently than the 8-bit wide data word. Instruction

opcodes are 12-bits wide making it possible to have all

arithmetic unit. It performs arithmetic and Boolean

functions between data in the working register and any

register file.

The ALU is 8-bits wide and capable of addition,

subtraction, shift and logical operations. Unless

otherwise mentioned, arithmetic operations are two's

complement in nature. In two-operand instructions,

typically one operand is the W (working) register. The

other operand is either a file register or an immediate

constant. In single operand instructions, the operand is

either the W register or a file register.

single word instructions.

A 12-bit wide program

memory access bus fetches a 12-bit instruction in a

single cycle. A two-stage pipeline overlaps fetch and

execution of instructions. Consequently, all instructions

(33) execute in a single cycle (1µs @ 4MHz) except for

program branches.

The W register is an 8-bit working register used for

ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC),

and Zero (Z) bits in the STATUS register. The C and

DC bits operate as a borrow and digit borrow out bit,

respectively, in subtraction. See the SUBWFand ADDWF

instructions for examples.

The table below lists program memory (EPROM), data

memory (RAM), ROM memory, and non-volatile

(EEPROM) for each device.

A simplified block diagram is shown in Figure 3-1, with

the corresponding device pins described in Table 3-1.

Memory

ROM RAM EEPROM

Device

EPROM

Program Program

Data

PIC12C508

512 x 12

1024 x 12

512 x 12

1024 x 12

512 x 12

1024 x 12

25

41

PIC12C509

PIC12C508A

PIC12C509A

PIC12CR509A

PIC12CE518

PIC12CE519

25

41

25 x 8

41 x 8

16 x 8

The PIC12C5XX can directly or indirectly address its

register files and data memory. All special function

registers including the program counter are mapped in

the data memory. The PIC12C5XX has

a highly

orthogonal (symmetrical) instruction set that makes it

possible to carry out any operation on any register

using any addressing mode. This symmetrical nature

and lack of ‘special optimal situations’ make

programming with the PIC12C5XX simple yet efficient.

In addition, the learning curve is reduced significantly.

1999 Microchip Technology Inc.

DS40139E-page 9

PIC12C5XX

FIGURE 3-1: PIC12C5XX BLOCK DIAGRAM

12

8

GPIO

Data Bus

Program Counter

ROM/EPROM

GP0

GP1

512 x 12 or

1024 x 12

RAM

GP2/T0CKI

GP3/MCLR/VPP

GP4/OSC2

GP5/OSC1/CLKIN

Program

STACK1

Memory

25 x 8 or

STACK2

File

Registers

Program

12

RAM Addr

Bus

9

Addr MUX

Instruction reg

Indirect

Addr

5

16 X 8

EEPROM

Data

Memory

PIC12CE5XX

Only

Direct Addr

5-7

FSR reg

STATUS reg

8

3

MUX

Device Reset

Timer

Instruction

Decode &

Control

ALU

Power-on

Reset

8

Timing

Generation

Watchdog

Timer

OSC1/CLKIN

OSC2

W reg

Internal RC

OSC

Timer0

MCLR

VDD, VSS

DS40139E-page 10

1999 Microchip Technology Inc.

PIC12C5XX

TABLE 3-1:

Name

PIC12C5XX PINOUT DESCRIPTION

DIP

SOIC

Pin #

I/O/P

Type

Buffer

Type

Description

Pin #

GP0

7

I/O

TTL/ST Bi-directional I/O port/ serial programming data. Can

be software programmed for internal weak pull-up and

wake-up from SLEEP on pin change. This buffer is a

Schmitt Trigger input when used in serial programming

mode.

GP1

6

I/O

TTL/ST Bi-directional I/O port/ serial programming clock. Can

be software programmed for internal weak pull-up and

wake-up from SLEEP on pin change. This buffer is a

Schmitt Trigger input when used in serial programming

mode.

GP2/T0CKI

5

4

5

4

I/O

I

ST

Bi-directional I/O port. Can be configured as T0CKI.

GP3/MCLR/VPP

TTL/ST Input port/master clear (reset) input/programming volt-

age input. When configured as MCLR, this pin is an

active low reset to the device. Voltage on MCLR/VPP

must not exceed VDD during normal device operation

or the device will enter programming mode. Can be

software programmed for internal weak pull-up and

wake-up from SLEEP on pin change. Weak pull-up

always on if configured as MCLR. ST when in MCLR

mode.

GP4/OSC2

3

2

3

2

I/O

TTL

Bi-directional I/O port/oscillator crystal output. Con-

nections to crystal or resonator in crystal oscillator

mode (XT and LP modes only, GPIO in other modes).

GP5/OSC1/CLKIN

TTL/ST Bidirectional IO port/oscillator crystal input/external

clock source input (GPIO in Internal RC mode only,

OSC1 in all other oscillator modes). TTL input when

GPIO, ST input in external RC oscillator mode.

VDD

1

P

—

Positive supply for logic and I/O pins

Ground reference for logic and I/O pins

VSS

8

P

Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input,

ST = Schmitt Trigger input

1999 Microchip Technology Inc.

DS40139E-page 11

PIC12C5XX

3.1

Clocking Scheme/Instruction Cycle

3.2

Instruction Flow/Pipelining

The clock input (OSC1/CLKIN pin) is internally divided

by four to generate four non-overlapping quadrature

clocks namely Q1, Q2, Q3 and Q4. Internally, the

program counter is incremented every Q1, and the

instruction is fetched from program memory and

latched into instruction register in Q4. It is decoded

and executed during the following Q1 through Q4. The

clocks and instruction execution flow is shown in

Figure 3-2 and Example 3-1.

An Instruction Cycle consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO)

then two cycles are required to complete the

instruction (Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is

latched into the Instruction Register (IR) in cycle Q1.

This instruction is then decoded and executed during

the Q2, Q3, and Q4 cycles. Data memory is read

during Q2 (operand read) and written during Q4

(destination write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

Q2

Q3

Q4

Q2

Q3

Q4

Q2

Q3

Q4

Q1

OSC1

Q1

Q2

Q3

Q4

PC

Internal

phase

clock

PC

PC+1

PC+2

Fetch INST (PC)

Execute INST (PC-1)

Fetch INST (PC+1)

Execute INST (PC)

Fetch INST (PC+2)

Execute INST (PC+1)

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 03H

2. MOVWF GPIO

3. CALL SUB_1

Fetch 1

Execute 1

Fetch 2

Execute 2

Fetch 3

Execute 3

Fetch 4

4. BSF

GPIO, BIT1

Flush

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch

instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

DS40139E-page 12

1999 Microchip Technology Inc.

PIC12C5XX

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK

4.0

MEMORY ORGANIZATION

PIC12C5XX memory is organized into program mem-

ory and data memory. For devices with more than 512

bytes of program memory, a paging scheme is used.

Program memory pages are accessed using one STA-

TUS register bit. For the PIC12C509, PIC12C509A,

PICCR509A and PIC12CE519 with a data memory

register file of more than 32 registers, a banking

scheme is used. Data memory banks are accessed

using the File Select Register (FSR).

PC<11:0>

12

CALL, RETLW

Stack Level 1

Stack Level 2

Reset Vector (note 1)

0000h

4.1

Program Memory Organization

On-chip Program

Memory

The PIC12C5XX devices have

a

12-bit Program

Counter (PC) capable of addressing

program memory space.

a

2K 12

x

512 Word

01FFh

0200h

Only the first 512

x 12 (0000h-01FFh) for the

PIC12C508, PIC12C508A and PIC12CE518 and 1K x

12 (0000h-03FFh) for the PIC12C509, PIC12C509A,

PIC12CR509A, and PIC12CE519 are physically

On-chip Program

Memory

implemented. Refer to Figure 4-1. Accessing

a

location above these boundaries will cause a wrap-

around within the first 512 x 12 space (PIC12C508,

PIC12C508A and PIC12CE518) or 1K x 12 space

(PIC12C509, PIC12C509A, PIC12CR509A and

PIC12CE519). The effective reset vector is at 000h,

(see Figure 4-1). Location 01FFh (PIC12C508,

PIC12C508A and PIC12CE518) or location 03FFh

(PIC12C509, PIC12C509A, PIC12CR509A and

PIC12CE519) contains the internal clock oscillator

calibration value. This value should never be

overwritten.

1024 Word

03FFh

0400h

7FFh

Note 1: Address 0000h becomes the

effective reset vector. Location

01FFh (PIC12C508, PIC12C508A,

PIC12CE518) or location 03FFh

(PIC12C509, PIC12C509A,

PIC12CR509A, PIC12CE519) con-

tains the MOVLW XXINTERNAL RC

oscillator calibration value.

1999 Microchip Technology Inc.

DS40139E-page 13

PIC12C5XX

4.2

Data Memory Organization

FIGURE 4-2: PIC12C508, PIC12C508A AND

PIC12CE518 REGISTER FILE

MAP

Data memory is composed of registers, or bytes of

RAM. Therefore, data memory for a device is specified

by its register file. The register file is divided into two

functional groups: special function registers and

general purpose registers.

File Address

INDF⁽¹⁾

00h

TMR0

PCL

01h

02h

03h

04h

05h

06h

07h

The special function registers include the TMR0

register, the Program Counter (PC), the Status

Register, the I/O registers (ports), and the File Select

Register (FSR). In addition, special purpose registers

are used to control the I/O port configuration and

prescaler options.

STATUS

FSR

OSCCAL

GPIO

The general purpose registers are used for data and

control information under command of the instructions.

For the PIC12C508, PIC12C508A and PIC12CE518,

the register file is composed of 7 special function

registers and 25 general purpose registers (Figure 4-

2).

General

Purpose

Registers

For the PIC12C509, PIC12C509A, PIC12CR509A,

and PIC12CE519 the register file is composed of 7

special function registers, 25 general purpose

registers, and 16 general purpose registers that may

be addressed using a banking scheme (Figure 4-3).

1Fh

Note 1: Not a physical register. See Section 4.8

4.2.1

GENERAL PURPOSE REGISTER FILE

The general purpose register file is accessed either

directly or indirectly through the file select register FSR

(Section 4.8).

FIGURE 4-3: PIC12C509, PIC12C509A, PIC12CR509A AND PIC12CE519 REGISTER FILE MAP

FSR<6:5>

File Address

00h

00

01

INDF⁽¹⁾

TMR0

PCL

20h

01h

02h

03h

04h

05h

Addresses map

back to

addresses

in Bank 0.

STATUS

FSR

OSCCAL

GPIO

06h

07h

General

Purpose

Registers

2Fh

0Fh

10h

1Fh

30h

General

Purpose

Registers

General

Purpose

Registers

3Fh

Bank 0

Bank 1

Note 1: Not a physical register. See Section 4.8

DS40139E-page 14

1999 Microchip Technology Inc.

PIC12C5XX

4.2.2

SPECIAL FUNCTION REGISTERS

The special registers can be classified into two sets.

The special function registers associated with the

“core” functions are described in this section. Those

related to the operation of the peripheral features are

described in the section for each peripheral feature.

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral functions to control

the operation of the device (Table 4-1).

TABLE 4-1:

SPECIAL FUNCTION REGISTER (SFR) SUMMARY

Value on

All Other

Resets⁽²⁾

Value on

Power-On

Reset

Address

Name

TRIS

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1 Bit 0

--11 1111

N/A

—

Contains control bits to configure Timer0, Timer0/WDT

prescaler, wake-up on change, and weak pull-ups

1111 1111

xxxx xxxx

1111 1111

uuuu uuuu

1111 1111

N/A

00h

01h

02h

03h

OPTION

INDF

Uses contents of FSR to address data memory (not a physical register)

8-bit real-time clock/counter

TMR0

PCL

(1)

Low order 8 bits of PC

0001 1xxx q00q quuu⁽³⁾

STATUS

GPWUF

—

PA0

TO

PD

Z

DC

C

FSR

(PIC12C508/

PIC12C508A/

PIC12C518)

04h

Indirect data memory address pointer

111x xxxx

111u uuuu

FSR

(PIC12C509/

PIC12C509A/

PIC12CR509A/

PIC12CE519)

04h

05h

110x xxxx

0111 ----

11uu uuuu

uuuu ----

OSCCAL

(PIC12C508/

PIC12C509)

CAL3

CAL2

CAL1

CAL0

—

OSCCAL

(PIC12C508A/

PIC12C509A/

PIC12CE518/

PIC12CE519/

PIC12CR509A)

1000 00--

uuuu uu--

05h

CAL5

CAL4

CAL3

CAL2

CAL1

CAL0

GPIO

(PIC12C508/

PIC12C509/

PIC12C508A/

PIC12C509A/

PIC12CR509A)

--xx xxxx

11xx xxxx

--uu uuuu

11uu uuuu

06h

—

GP5

GP4

GP3

GP2

GP1

GP0

GPIO

(PIC12CE518/

PIC12CE519)

SCL

SDA

Legend: Shaded boxes = unimplemented or unused, —= unimplemented, read as ’0’ (if applicable)

x= unknown, u= unchanged, q= see the tables in Section 8.7 for possible values.

Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.6

for an explanation of how to access these bits.

2: Other (non power-up) resets include external reset through MCLR, watchdog timer and wake-up on pin change reset.

3: If reset was due to wake-up on pin change then bit 7 = 1. All other resets will cause bit 7 = 0.

1999 Microchip Technology Inc.

DS40139E-page 15

PIC12C5XX

For example, CLRF STATUSwill clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu(where u= unchanged).

4.3

STATUS Register

This register contains the arithmetic status of the ALU,

the RESET status, and the page preselect bit for

program memories larger than 512 words.

It is recommended, therefore, that only BCF, BSF and

MOVWF instructions be used to alter the STATUS

register because these instructions do not affect the Z,

DC or C bits from the STATUS register. For other

instructions, which do affect STATUS bits, see

Instruction Set Summary.

The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to

the device logic. Furthermore, the TO and PD bits are

not writable. Therefore, the result of an instruction with

the STATUS register as destination may be different

than intended.

FIGURE 4-4: STATUS REGISTER (ADDRESS:03h)

R/W-0

GPWUF

R/W-0

—

R/W-0

PA0

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC

R/W-x

C

R = Readable bit

W = Writable bit

- n = Value at POR reset

bit7

6

5

4

3

2

1

bit0

bit 7:

GPWUF: GPIO reset bit

1 = Reset due to wake-up from SLEEP on pin change

0 = After power up or other reset

bit 6:

bit 5:

Unimplemented

PA0: Program page preselect bits

1 = Page 1 (200h - 3FFh) - PIC12C509, PIC12C509A, PIC12CR509A and PIC12CE519

0 = Page 0 (000h - 1FFh) - PIC12C5XX

Each page is 512 bytes.

Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program

page preselect is not recommended since this may affect upward compatibility with future products.

bit 4:

bit 3:

bit 2:

bit 1:

TO: Time-out bit

1 = After power-up, CLRWDTinstruction, or SLEEPinstruction

0 = A WDT time-out occurred

PD: Power-down bit

1 = After power-up or by the CLRWDTinstruction

0 = By execution of the SLEEPinstruction

Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

DC: Digit carry/borrow bit (for ADDWFand SUBWFinstructions)

ADDWF

1 = A carry from the 4th low order bit of the result occurred

0 = A carry from the 4th low order bit of the result did not occur

SUBWF

1 = A borrow from the 4th low order bit of the result did not occur

0 = A borrow from the 4th low order bit of the result occurred

bit 0:

C: Carry/borrow bit (for ADDWF, SUBWFand RRF, RLFinstructions)

ADDWF

SUBWF

RRF or RLF

1 = A carry occurred

0 = A carry did not occur

1 = A borrow did not occur

0 = A borrow occurred

Load bit with LSB or MSB, respectively

DS40139E-page 16

1999 Microchip Technology Inc.

PIC12C5XX

4.4

OPTION Register

Note: If TRIS bit is set to ‘0’, the wake-up on

change and pull-up functions are disabled

for that pin; i.e., note that TRIS overrides

OPTION control of GPPU and GPWU.

The OPTION register is

register which contains various control bits to

configure the Timer0/WDT prescaler and Timer0.

a

8-bit wide, write-only

Note: If the T0CS bit is set to ‘1’, GP2 is forced to

By executing the OPTION instruction, the contents of

the W register will be transferred to the OPTION

register. A RESET sets the OPTION<7:0> bits.

be an input even if TRIS GP2 = ‘0’.

FIGURE 4-5: OPTION REGISTER

W-1

GPPU

6

W-1

T0CS

5

W-1

T0SE

4

W-1

PSA

3

W-1

PS2

2

W-1

PS1

1

W-1

PS0

GPWU

W

U

= Writable bit

= Unimplemented bit

bit7

bit0

- n = Value at POR reset

Reference Table 4-1 for

other resets.

bit 7:

bit 6:

bit 5:

bit 4:

bit 3:

GPWU: Enable wake-up on pin change (GP0, GP1, GP3)

1 = Disabled

0 = Enabled

GPPU: Enable weak pull-ups (GP0, GP1, GP3)

1 = Disabled

0 = Enabled

T0CS: Timer0 clock source select bit

1 = Transition on T0CKI pin

0 = Transition on internal instruction cycle clock, Fosc/4

T0SE: Timer0 source edge select bit

1 = Increment on high to low transition on the T0CKI pin

0 = Increment on low to high transition on the T0CKI pin

PSA: Prescaler assignment bit

1 = Prescaler assigned to the WDT

0 = Prescaler assigned to Timer0

bit 2-0: PS2:PS0: Prescaler rate select bits

Bit Value

Timer0 Rate WDT Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1999 Microchip Technology Inc.

DS40139E-page 17

PIC12C5XX

4.5

OSCCAL Register

The Oscillator Calibration (OSCCAL) register is used to

calibrate the internal 4 MHz oscillator. It contains four to

six bits for calibration. Increasing the cal value

increases the frequency. See Section 7.2.5 for more

information on the internal oscillator.

FIGURE 4-6: OSCCAL REGISTER (ADDRESS 05h) FOR PIC12C508 AND PIC12C509

R/W-0

CAL3

R/W-1

CAL2

R/W-1

CAL1

R/W-1

CAL0

R/W-0

U-0

—

R

W

U

= Readable bit

= Writable bit

= Unimplemented bit,

read as ‘0’

bit7

bit0

- n = Value at POR reset

bit 7-4: CAL<3:0>: Calibration

bit 3-0: Unimplemented: Read as ’0’

FIGURE 4-7: OSCCAL REGISTER (ADDRESS 05h) FOR PIC12C508A/C509A/CR509A/12CE518/

12CE519

R/W-1

CAL5

R/W-0

CAL4

R/W-0

CAL3

R/W-0

CAL2

R/W-0

CAL1

R/W-0

CAL0

U-0

—

U-0

—

R

W

U

= Readable bit

= Writable bit

= Unimplemented bit,

read as ‘0’

bit7

bit0

- n = Value at POR reset

bit 7-2: CAL<5:0>: Calibration

bit 1-0: Unimplemented: Read as ’0’

DS40139E-page 18

1999 Microchip Technology Inc.

PIC12C5XX

4.6.1

EFFECTS OF RESET

4.6

Program Counter

The Program Counter is set upon a RESET, which

means that the PC addresses the last location in the

last page i.e., the oscillator calibration instruction. After

executing MOVLW XX, the PC will roll over to location

00h, and begin executing user code.

As a program instruction is executed, the Program

Counter (PC) will contain the address of the next

program instruction to be executed. The PC value is

increased by one every instruction cycle, unless an

instruction changes the PC.

The STATUS register page preselect bits are cleared

upon a RESET, which means that page 0 is pre-

selected.

For a GOTOinstruction, bits 8:0 of the PC are provided

by the GOTOinstruction word. The PC Latch (PCL) is

mapped to PC<7:0>. Bit 5 of the STATUS register

provides page information to bit 9 of the PC (Figure 4-

8).

Therefore, upon a RESET, a GOTO instruction will

automatically cause the program to jump to page 0

until the value of the page bits is altered.

For a CALL instruction, or any instruction where the

PCL is the destination, bits 7:0 of the PC again are

provided by the instruction word. However, PC<8>

does not come from the instruction word, but is always

cleared (Figure 4-8).

4.7

Stack

PIC12C5XX devices have

hardware push/pop stack.

a 12-bit wide L.I.F.O.

Instructions where the PCL is the destination, or

Modify PCL instructions, include MOVWF PC, ADDWF

PC,and BSF PC,5.

A CALLinstruction will push the current value of stack

1 into stack 2 and then push the current program

counter value, incremented by one, into stack level 1. If

more than two sequential CALL’s are executed, only

the most recent two return addresses are stored.

Note: Because PC<8> is cleared in the CALL

instruction, or any Modify PCL instruction,

all subroutine calls or computed jumps are

limited to the first 256 locations of any pro-

gram memory page (512 words long).

A RETLWinstruction will pop the contents of stack level

1 into the program counter and then copy stack level 2

contents into level 1. If more than two sequential

RETLW’s are executed, the stack will be filled with the

address previously stored in level 2. Note that the

W register will be loaded with the literal value specified

in the instruction. This is particularly useful for the

implementation of data look-up tables within the

program memory.

FIGURE 4-8: LOADING OF PC

BRANCH INSTRUCTIONS -

PIC12C5XX

GOTO Instruction

11

10

9

8

7

0

Upon any reset, the contents of the stack remain

unchanged, however the program counter (PCL) will

also be reset to 0.

PC

PCL

Instruction Word

0

Note 1: There are no STATUS bits to indicate

stack overflows or stack underflow condi-

tions.

PA0

7

Note 2: There are no instructions mnemonics

called PUSH or POP. These are actions

that occur from the execution of the CALL

and RETLWinstructions.

STATUS

CALL or Modify PCL Instruction

11

10

9

8

7

0

PC

PCL

Instruction Word

Reset to ‘0’

PA0

7

0

STATUS

1999 Microchip Technology Inc.

DS40139E-page 19

PIC12C5XX

4.8

Indirect Data Addressing; INDF and

FSR Registers

EXAMPLE 4-2: HOW TO CLEAR RAM

USING INDIRECT

ADDRESSING

The INDF register is not

a physical register.

movlw

movwf

clrf

incf

btfsc

goto

0x10

;initialize pointer

Addressing INDF actually addresses the register

whose address is contained in the FSR register (FSR

is a pointer). This is indirect addressing.

FSR

;

to RAM

FSR,F

FSR,4

;inc pointer

;all done?

;NO, clear next

EXAMPLE 4-1: INDIRECT ADDRESSING

• Register file 07 contains the value 10h

• Register file 08 contains the value 0Ah

• Load the value 07 into the FSR register

• A read of the INDF register will return the value

of 10h

CONTINUE

:

;YES, continue

The FSR is

a 5-bit wide register. It is used in

conjunction with the INDF register to indirectly address

the data memory area.

• Increment the value of the FSR register by one

(FSR = 08)

The FSR<4:0> bits are used to select data memory

addresses 00h to 1Fh.

• A read of the INDR register now will return the

value of 0Ah.

PIC12C508/PIC12C508A/PIC12CE518:

use banking. FSR<7:5> are unimplemented and read

as '1's.

Does not

Reading INDF itself indirectly (FSR = 0) will produce

00h. Writing to the INDF register indirectly results in a

no-operation (although STATUS bits may be affected).

PIC12C509/PIC12C509A/PIC12CR509A/

PIC12CE519: Uses FSR<5>. Selects between bank 0

and bank 1. FSR<7:6> is unimplemented, read as '1’ .

A simple program to clear RAM locations 10h-1Fh

using indirect addressing is shown in Example 4-2.

FIGURE 4-9: DIRECT/INDIRECT ADDRESSING

Direct Addressing

Indirect Addressing

(FSR)

4

(opcode)

0

5

(FSR)

0

6

4

5

6

bank select location select

location select

bank

00

01

00h

Addresses

map back to

addresses

in Bank 0.

Data

Memory⁽¹⁾

0Fh

10h

1Fh

Bank 0

3Fh

Bank 1⁽²⁾

Note 1: For register map detail see Section 4.2.

Note 2: PIC12C509, PIC12C509A, PIC12CR509A, PIC12CE519.

DS40139E-page 20

1999 Microchip Technology Inc.

PIC12C5XX

5.3

I/O Interfacing

5.0

I/O PORT

As with any other register, the I/O register can be

written and read under program control. However, read

instructions (e.g., MOVF GPIO,W) always read the I/O

pins independent of the pin’s input/output modes. On

RESET, all I/O ports are defined as input (inputs are at

hi-impedance) since the I/O control registers are all

set. See Section 7.0 for SCL and SDA description for

PIC12CE5XX.

The equivalent circuit for an I/O port pin is shown in

Figure 5-1. All port pins, except GP3 which is input

only, may be used for both input and output operations.

For input operations these ports are non-latching. Any

input must be present until read by an input instruction

(e.g., MOVF GPIO,W). The outputs are latched and

remain unchanged until the output latch is rewritten. To

use a port pin as output, the corresponding direction

control bit in TRIS must be cleared (= 0). For use as an

input, the corresponding TRIS bit must be set. Any I/O

pin (except GP3) can be programmed individually as

input or output.

5.1

GPIO

GPIO is an 8-bit I/O register. Only the low order 6 bits

are used (GP5:GP0). Bits 7 and 6 are unimplemented

and read as '0's. Please note that GP3 is an input only

pin. The configuration word can set several I/O’s to

alternate functions. When acting as alternate functions

the pins will read as ‘0’ during port read. Pins GP0,

GP1, and GP3 can be configured with weak pull-ups

and also with wake-up on change. The wake-up on

change and weak pull-up functions are not pin

selectable. If pin 4 is configured as MCLR, weak pull-

up is always on and wake-up on change for this pin is

not enabled.

FIGURE 5-1: EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

Data

Bus

D

Q

Data

Latch

VDD

WR

Port

CK

P

N

I/O

pin^(1,3)

W

Reg

5.2

TRIS Register

D

Q

The output driver control register is loaded with the

contents of the W register by executing the TRIS f

instruction. A '1' from a TRIS register bit puts the

corresponding output driver in a hi-impedance mode.

A '0' puts the contents of the output data latch on the

selected pins, enabling the output buffer. The

exceptions are GP3 which is input only and GP2 which

may be controlled by the option register, see Figure 4-

5.

TRIS

Latch

VSS

TRIS ‘f’

CK

Reset

(2)

Note:

A read of the ports reads the pins, not the

output data latches. That is, if an output

driver on a pin is enabled and driven high,

but the external system is holding it low, a

read of the port will indicate that the pin is

low.

RD Port

Note 1: I/O pins have protection diodes to VDD

and VSS.

Note 2: See Table 3-1 for buffer type.

Note 3: See Section 7.0 for SCL and SDA

The TRIS registers are “write-only” and are set (output

drivers disabled) upon RESET.

description for PIC12CE5XX

1999 Microchip Technology Inc.

DS40139E-page 21

PIC12C5XX

TABLE 5-1:

SUMMARY OF PORT REGISTERS

Value on

Power-On

Reset

Value on

All Other Resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3 Bit 2 Bit 1 Bit 0

N/A

03H

TRIS

—

--11 1111

1111 1111

0001 1xxx

--11 1111

1111 1111

OPTION

GPWU

GPPU

T0CS

PAO

T0SE

TO

PSA

PD

PS2

Z

PS1

DC

PS0

C

(1)

STATUS

GPWUF

—

q00q quuu

GPIO

(PIC12C508/

PIC12C509/

PIC12C508A/

PIC12C509A/

PIC12CR509A)

--xx xxxx

11xx xxxx

--uu uuuu

11uu uuuu

06h

—

GP5

GP4

GP3

GP2

GP1

GP0

GPIO

(PIC12CE518/

PIC12CE519)

SCL

SDA

Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0', x= unknown, u= unchanged,

q = see tables in Section 8.7 for possible values.

Note 1: If reset was due to wake-up on change, then bit 7 = 1. All other resets will cause bit 7 = 0.

5.4

I/O Programming Considerations

EXAMPLE 5-1: READ-MODIFY-WRITE

INSTRUCTIONS ON AN

I/O PORT

5.4.1

BI-DIRECTIONAL I/O PORTS

;Initial GPIO Settings

Some instructions operate internally as read followed

by write operations. The BCFand BSFinstructions, for

example, read the entire port into the CPU, execute

the bit operation and re-write the result. Caution must

be used when these instructions are applied to a port

where one or more pins are used as input/outputs. For

example, a BSF operation on bit5 of GPIO will cause

all eight bits of GPIO to be read into the CPU, bit5 to

be set and the GPIO value to be written to the output

latches. If another bit of GPIO is used as a bi-

directional I/O pin (say bit0) and it is defined as an

input at this time, the input signal present on the pin

itself would be read into the CPU and rewritten to the

data latch of this particular pin, overwriting the

previous content. As long as the pin stays in the input

mode, no problem occurs. However, if bit0 is switched

into output mode later on, the content of the data latch

may now be unknown.

;

GPIO<5:3> Inputs

GPIO<2:0> Outputs

GPIO latch GPIO pins

---------- ----------

BCF

MOVLW 007h

TRIS GPIO

GPIO, 5

GPIO, 4

;--01 -ppp

;--10 -ppp

;

--11 pppp

;--10 -ppp

--11 pppp

;

;Note that the user may have expected the pin

;values to be --00 pppp. The 2nd BCF caused

;GP5 to be latched as the pin value (High).

5.4.2

SUCCESSIVE OPERATIONS ON I/O

PORTS

The actual write to an I/O port happens at the end of

an instruction cycle, whereas for reading, the data

must be valid at the beginning of the instruction cycle

(Figure 5-2). Therefore, care must be exercised if a

write followed by a read operation is carried out on the

same I/O port. The sequence of instructions should

allow the pin voltage to stabilize (load dependent)

before the next instruction, which causes that file to be

read into the CPU, is executed. Otherwise, the

previous state of that pin may be read into the CPU

rather than the new state. When in doubt, it is better to

separate these instructions with a NOP or another

instruction not accessing this I/O port.

Example 5-1 shows the effect of two sequential read-

modify-write instructions (e.g., BCF, BSF, etc.) on an

I/O port.

A pin actively outputting a high or a low should not be

driven from external devices at the same time in order

to change the level on this pin (“wired-or”, “wired-

and”). The resulting high output currents may damage

the chip.

DS40139E-page 22

1999 Microchip Technology Inc.

PIC12C5XX

FIGURE 5-2: SUCCESSIVE I/O OPERATION

Q4

Q3

Q1 Q2

PC

MOVWF GPIO

Q1 Q2

PC + 3

NOP

PC + 1

PC + 2

NOP

This example shows a write to GPIO followed

by a read from GPIO.

Instruction

fetched

MOVF GPIO,W

Data setup time = (0.25 TCY – TPD)

where: TCY = instruction cycle.

TPD = propagation delay

GP5:GP0

Port pin

written here

Port pin

sampled here

Therefore, at higher clock frequencies, a

write followed by a read may be problematic.

Instruction

executed

MOVWF GPIO

(Write to

MOVF GPIO,W

(Read

NOP

GPIO)

1999 Microchip Technology Inc.

DS40139E-page 23

PIC12C5XX

NOTES:

DS40139E-page 24

1999 Microchip Technology Inc.

PIC12C5XX

Counter mode is selected by setting the T0CS bit

(OPTION<5>). In this mode, Timer0 will increment

either on every rising or falling edge of pin T0CKI. The

T0SE bit (OPTION<4>) determines the source edge.

Clearing the T0SE bit selects the rising edge.

Restrictions on the external clock input are discussed

in detail in Section 6.1.

6.0

TIMER0 MODULE AND

TMR0 REGISTER

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

- Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

- Edge select for external clock

The prescaler may be used by either the Timer0

module or the Watchdog Timer, but not both. The

prescaler assignment is controlled in software by the

control bit PSA (OPTION<3>). Clearing the PSA bit

will assign the prescaler to Timer0. The prescaler is

not readable or writable. When the prescaler is

assigned to the Timer0 module, prescale values of 1:2,

1:4,..., 1:256 are selectable. Section 6.2 details the

operation of the prescaler.

Figure 6-1 is a simplified block diagram of the Timer0

module.

Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In timer mode, the Timer0 module will

increment every instruction cycle (without prescaler). If

TMR0 register is written, the increment is inhibited for

the following two instruction cycles (Figure 6-2 and

Figure 6-3). The user can work around this by writing

an adjusted value to the TMR0 register.

A summary of registers associated with the Timer0

module is found in Table 6-1.

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

Data bus

GP2/T0CKI

FOSC/4

0

1

PSout

8

1

0

Sync with

Internal

Clocks

TMR0 reg

Programmable

Prescaler⁽²⁾

PSout

Sync

(2 TCY delay)

T0SE

3

PS2, PS1, PS0⁽¹⁾

PSA⁽¹⁾

T0CS⁽¹⁾

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer (Figure 6-5).

1999 Microchip Technology Inc.

DS40139E-page 25

PIC12C5XX

FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

PC

(Program

Counter)

Instruction

Fetch

T0

T0+1

T0+2

NT0

NT0+1

NT0+2

Timer0

Instruction

Executed

Read TMR0

reads NT0 + 1

Write TMR0

executed

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 2

FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

(Program

Counter)

PC-1

PC

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

MOVWF TMR0

Instruction

Fetch

T0

T0+1

NT0

NT0+1

T0

Timer0

Instruction

Execute

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 1

Write TMR0

executed

TABLE 6-1:

Address

REGISTERS ASSOCIATED WITH TIMER0

Value on

Power-On

Reset

Value on

All Other

Resets

Name

TMR0

Bit 7

Timer0 - 8-bit real-time clock/counter

GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

GP5 GP4 GP3 GP2 GP1 GP0

Bit 6

Bit 5

Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

01h

N/A

xxxx xxxx uuuu uuuu

OPTION

TRIS

—

--11 1111 --11 1111

Legend: Shaded cells not used by Timer0, -= unimplemented, x = unknown, u= unchanged,

DS40139E-page 26

1999 Microchip Technology Inc.

PIC12C5XX

When a prescaler is used, the external clock input is

divided by the asynchronous ripple counter-type

prescaler so that the prescaler output is symmetrical.

For the external clock to meet the sampling

requirement, the ripple counter must be taken into

account. Therefore, it is necessary for T0CKI to have a

period of at least 4TOSC (and a small RC delay of

40 ns) divided by the prescaler value. The only

requirement on T0CKI high and low time is that they

do not violate the minimum pulse width requirement of

10 ns. Refer to parameters 40, 41 and 42 in the

electrical specification of the desired device.

6.1

Using Timer0 with an External Clock

When an external clock input is used for Timer0, it

must meet certain requirements. The external clock

requirement is due to internal phase clock (TOSC)

synchronization. Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

6.1.1

EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is

accomplished by sampling the prescaler output on the

Q2 and Q4 cycles of the internal phase clocks

(Figure 6-4). Therefore, it is necessary for T0CKI to be

high for at least 2TOSC (and a small RC delay of 20 ns)

and low for at least 2TOSC (and a small RC delay of

20 ns). Refer to the electrical specification of the

desired device.

6.1.2

TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0

module is actually incremented. Figure 6-4 shows the

delay from the external clock edge to the timer

incrementing.

6.1.3

OPTION REGISTER EFFECT ON GP2 TRIS

If the option register is set to read TIMER0 from the pin,

the port is forced to an input regardless of the TRIS reg-

ister setting.

FIGURE 6-4: TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Small pulse

External Clock Input or

misses sampling

Prescaler Output (2)

(1)

External Clock/Prescaler

Output After Sampling

(3)

Increment Timer0 (Q4)

Timer0

T0

T0 + 1

T0 + 2

Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).

Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.

2: External clock if no prescaler selected, Prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

1999 Microchip Technology Inc.

DS40139E-page 27

PIC12C5XX

6.2

Prescaler

EXAMPLE 6-1: CHANGING PRESCALER

(TIMER0→WDT)

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer (WDT), respectively (Section 8.6). For simplicity,

this counter is being referred to as “prescaler”

throughout this data sheet. Note that the prescaler

may be used by either the Timer0 module or the WDT,

but not both. Thus, a prescaler assignment for the

Timer0 module means that there is no prescaler for

the WDT, and vice-versa.

1.CLRWDT

2.CLRF

;Clear WDT

;Clear TMR0 & Prescaler

3.MOVLW '00xx1111’b ;These 3 lines (5, 6, 7)

TMR0

4.OPTION

;

are required only if

desired

5.CLRWDT

;PS<2:0> are 000 or 001

6.MOVLW '00xx1xxx’b ;Set Postscaler to

7.OPTION desired WDT rate

;

To change prescaler from the WDT to the Timer0

module, use the sequence shown in Example 6-2. This

sequence must be used even if the WDT is disabled. A

CLRWDT instruction should be executed before

switching the prescaler.

The PSA and PS2:PS0 bits (OPTION<3:0>)

determine prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF 1,

MOVWF 1, BSF 1,x, etc.) will clear the prescaler.

When assigned to WDT, a CLRWDT instruction will

clear the prescaler along with the WDT. The prescaler

is neither readable nor writable. On a RESET, the

prescaler contains all '0's.

EXAMPLE 6-2: CHANGING PRESCALER

(WDT→TIMER0)

CLRWDT

MOVLW

;Clear WDT and

;prescaler

'xxxx0xxx'

;Select TMR0, new

;prescale value and

;clock source

6.2.1

SWITCHING PRESCALER ASSIGNMENT

OPTION

The prescaler assignment is fully under software control

(i.e., it can be changed “on the fly” during program

execution). To avoid an unintended device RESET, the

following instruction sequence (Example 6-1) must be

executed when changing the prescaler assignment from

Timer0 to the WDT.

FIGURE 6-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

TCY ( = Fosc/4)

Data Bus

8

0

GP2/T0CKI

M

U

X

1

M

U

X

Sync

2

Cycles

1

TMR0 reg

0

T0SE

T0CS

PSA

0

1

8-bit Prescaler

M

U

X

8

Watchdog

Timer

8 - to - 1MUX

PS2:PS0

PSA

1

0

WDT Enable bit

MUX

PSA

WDT

Time-Out

Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.

DS40139E-page 28

1999 Microchip Technology Inc.

PIC12C5XX

Namely, to avoid code overhead in modifying the TRIS

register, both SDA and SCL are always outputs. To

read data from the EEPROM peripheral requires out-

putting a ‘1’ on SDA placing it in high-Z state, where

only the internal 100K pull-up is active on the SDA line.

7.0

EEPROM PERIPHERAL

OPERATION

This section applies to PIC12CE518 and

PIC12CE519 only.

The PIC12CE518 and PIC12CE519 each have 16

bytes of EEPROM data memory. The EEPROM mem-

ory has an endurance of 1,000,000 erase/write cycles

and a data retention of greater than 40 years. The

EEPROM data memory supports a bi-directional 2-wire

bus and data transmission protocol. These two-wires

are serial data (SDA) and serial clock (SCL), that are

mapped to bit6 and bit7, respectively, of the GPIO reg-

ister (SFR 06h). Unlike the GP0-GP5 that are con-

nected to the I/O pins, SDA and SCL are only

connected to the internal EEPROM peripheral. For

most applications, all that is required is calls to the fol-

lowing functions:

SDA:

Built-in 100K (typical) pull-up to VDD

Open-drain (pull-down only)

Always an output

Outputs a ‘1’ on reset

SCL:

Full CMOS output

Always an output

Outputs a ‘1’ on reset

The following example requires:

• Code Space: 77 words

• RAM Space: 5 bytes (4 are overlayable)

• Stack Levels:1 (The call to the function itself. The

functions do not call any lower level functions.)

;

Byte_Write: Byte write routine

Inputs:EEPROM Address

EEPROM Data

EEADDR

EEDATA

if OK, else

• Timing:

Outputs:

Return 01 in

return 00 in

W

- WRITE_BYTE takes 328 cycles

- READ_CURRENT takes 212 cycles

- READ_RANDOM takes 416 cycles.

• IO Pins: 0 (No external IO pins are used)

;

Read_Current: Read EEPROM at address

currently held by EE device.

;

Inputs:NONE

Outputs:

EEPROM Data

Return 01 in

return 00 in

EEDATA

if OK, else

W

This code must reside in the lower half of a page. The

code achieves it’s small size without additional calls

through the use of a sequencing table. The table is a

list of procedures that must be called in order. The

table uses an ADDWF PCL,F instruction, effectively a

computed goto, to sequence to the next procedure.

However the ADDWF PCL,F instruction yields an 8 bit

address, forcing the code to reside in the first 256

addresses of a page.

;

Read_Random: Read EEPROM byte at supplied

address

;

Inputs:EEPROM Address

EEADDR

EEDATA

if OK,

Outputs:

EEPROM Data

Return 01 in

W

else return 00 in

W

The code for these functions is available on our website

www.microchip.com. The code will be accessed by

either including the source code FL51XINC.ASM or by

linking FLASH5IX.ASM.

It is very important to check the return codes when

using these calls, and retry the operation if unsuccess-

ful. Unsuccessful return codes occur when the EE data

memory is busy with the previous write, which can take

up to 4 mS.

7.0.1

SERIAL DATA

SDA is a bi-directional pin used to transfer addresses

and data into and data out of the device.

For normal data transfer SDA is allowed to change only

during SCL low. Changes during SCL high are

reserved for indicating the START and STOP condi-

tions.

The EEPROM interface is a 2-wire bus protocol con-

sisting of data (SDA) and a clock (SCL). Although

these lines are mapped into the GPIO register, they are

not accessible as external pins; only to the internal

EEPROM peripheral. SDA and SCL operation is also

slightly different than GPO-GP5 as listed below.

1999 Microchip Technology Inc.

DS40139E-page 29

PIC12C5XX

Figure 7-1: Block diagram of GPIO6 (SDA line)

VDD

reset

To 24L00 SDA

Pad

D

EN

write

GPIO

ck

Q

databus

Output Latch

Q

D

Schmitt Trigger

EN

ck

Input Latch

ltchpin

Read

GPIO

Figure 7-2: Block diagram of GPIO7 (SCL line)

VDD

To 24LC00 SCL

Pad

D

EN

write

GPIO

ck

Q

databus

Q

D

Schmitt Trigger

EN

ck

ltchpin

Read

GPIO

DS40139E-page 30

1999 Microchip Technology Inc.

PIC12C5XX

7.0.2

SERIAL CLOCK

7.1.4

DATA VALID (D)

This SCL input is used to synchronize the data transfer

from and to the device.

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

7.1

BUS CHARACTERISTICS

The data on the line must be changed during the LOW

period of the clock signal. There is one bit of data per

clock pulse.

The following bus protocol is to be used with the

EEPROM data memory.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited.

• Data transfer may be initiated only when the bus

is not busy.

During data transfer, the data line must remain stable

whenever the clock line is HIGH. Changes in the data

line while the clock line is HIGH will be interpreted as a

START or STOP condition.

7.1.5

ACKNOWLEDGE

Accordingly, the following bus conditions have been

defined (Figure 7-3).

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this acknowledge bit.

7.1.1

Both data and clock lines remain HIGH.

7.1.2 START DATA TRANSFER (B)

BUS NOT BUSY (A)

Note: Acknowledge bits are not generated if an

internal programming cycle is in progress.

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an acknowledge bit on the last

byte that has been clocked out of the slave. In this case,

the slave must leave the data line HIGH to enable the

master to generate the STOP condition (Figure 7-4).

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

7.1.3

STOP DATA TRANSFER (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

1999 Microchip Technology Inc.

DS40139E-page 31

PIC12C5XX

FIGURE 7-3: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(C)

(D)

(C)

(A)

SCL

SDA

START

CONDITION

STOP

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

FIGURE 7-4: ACKNOWLEDGE TIMING

Acknowledge

Bit

1

2

3

4

5

6

7

8

9

1

2

3

SCL

SDA

Data from transmitter

Receiver must release the SDA line at this point

so the Transmitter can continue sending data.

Transmitter must release the SDA line at this point

allowing the Receiver to pull the SDA line low to

acknowledge the previous eight bits of data.

7.2

Device Addressing

FIGURE 7-5: CONTROL BYTE FORMAT

Read/Write Bit

After generating a START condition, the bus master

transmits a control byte consisting of a slave address

and a Read/Write bit that indicates what type of opera-

tion is to be performed. The slave address consists of

a 4-bit device code (1010) followed by three don’t care

bits.

Device Select

Don’t Care

Bits

S

1

0

1

0

X

X R/W ACK

The last bit of the control byte determines the operation

to be performed. When set to a one a read operation is

selected, and when set to a zero a write operation is

selected. (Figure 7-5). The bus is monitored for its cor-

responding slave address all the time. It generates an

acknowledge bit if the slave address was true and it is

not in a programming mode.

Slave Address

Start Bit

Acknowledge Bit

DS40139E-page 32

1999 Microchip Technology Inc.

PIC12C5XX

7.3

WRITE OPERATIONS

7.4

ACKNOWLEDGE POLLING

7.3.1

BYTE WRITE

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the master, the device ini-

tiates the internally timed write cycle. ACK polling can

be initiated immediately. This involves the master send-

ing a start condition followed by the control byte for a

write command (R/W = 0). If the device is still busy with

the write cycle, then no ACK will be returned. If no ACK

is returned, then the start bit and control byte must be

re-sent. If the cycle is complete, then the device will

return the ACK and the master can then proceed with

the next read or write command. See Figure 7-6 for

flow diagram.

Following the start signal from the master, the device

code (4 bits), the don’t care bits (3 bits), and the R/W

bit (which is a logic low) are placed onto the bus by the

master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will follow

after it has generated an acknowledge bit during the

ninth clock cycle. Therefore, the next byte transmitted

by the master is the word address and will be written

into the address pointer. Only the lower four address

bits are used by the device, and the upper four bits are

don’t cares. The address byte is acknowledgeable and

the master device will then transmit the data word to be

written into the addressed memory location. The mem-

ory acknowledges again and the master generates a

stop condition. This initiates the internal write cycle,

and during this time will not generate acknowledge sig-

nals (Figure 7-7). After a byte write command, the inter-

nal address counter will not be incremented and will

point to the same address location that was just written.

If a stop bit is transmitted to the device at any point in

the write command sequence before the entire

sequence is complete, then the command will abort

and no data will be written. If more than 8 data bits are

transmitted before the stop bit is sent, then the device

will clear the previously loaded byte and begin loading

the data buffer again. If more than one data byte is

transmitted to the device and a stop bit is sent before a

full eight data bits have been transmitted, then the write

command will abort and no data will be written. The

EEPROM memory employs a VCC threshold detector

circuit which disables the internal erase/write logic if the

VCC is below minimum VDD.

FIGURE 7-6: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Byte write operations must be preceded and immedi-

ately followed by a bus not busy bus cycle where both

SDA and SCL are held high.

Did Device

NO

Acknowledge

(ACK = 0)?

YES

FIGURE 7-7: BYTE WRITE

S

T

A

R

T

S

T

O

P

BUS ACTIVITY

MASTER

CONTROL

BYTE

WORD

ADDRESS

DATA

SDA LINE

P

S

1

0

1

0

X

0

X

A

C

K

A

C

K

A

C

K

BUS ACTIVITY

X = Don’t Care Bit

1999 Microchip Technology Inc.

DS40139E-page 33

PIC12C5XX

device as part of a write operation. After the word

address is sent, the master generates a start condition

following the acknowledge. This terminates the write

operation, but not before the internal address pointer is

set. Then the master issues the control byte again but

with the R/W bit set to a one. It will then issue an

acknowledge and transmits the eight bit data word. The

master will not acknowledge the transfer but does gen-

erate a stop condition and the device discontinues

transmission (Figure 7-9). After this command, the

internal address counter will point to the address loca-

tion following the one that was just read.

7.5

READ OPERATIONS

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one. There are three basic types

of read operations: current address read, random read,

and sequential read.

7.5.1

CURRENT ADDRESS READ

It contains an address counter that maintains the

address of the last word accessed, internally incre-

mented by one. Therefore, if the previous read access

was to address n, the next current address read opera-

tion would access data from address n + 1. Upon

receipt of the slave address with the R/W bit set to one,

the device issues an acknowledge and transmits the

eight bit data word. The master will not acknowledge

the transfer but does generate a stop condition and the

device discontinues transmission (Figure 7-8).

7.5.3

SEQUENTIAL READ

Sequential reads are initiated in the same way as a ran-

dom read except that after the device transmits the first

data byte, the master issues an acknowledge as

opposed to a stop condition in a random read. This

directs the device to transmit the next sequentially

addressed 8-bit word (Figure 7-10).

7.5.2

RANDOM READ

To provide sequential reads, it contains an internal

address pointer which is incremented by one at the

completion of each read operation. This address

pointer allows the entire memory contents to be serially

read during one operation.

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, first the word address must

be set. This is done by sending the word address to the

FIGURE 7-8: CURRENT ADDRESS READ

S

T

S

BUS ACTIVITY

A

CONTROL

BYTE

T

MASTER

R

O

P

T

SDA LINE

S

1

0

1 0 X X X 1

P

A

C

K

N

O

BUS ACTIVITY

DATA

A

C

K

X = Don’t Care Bit

FIGURE 7-9: RANDOM READ

S

T

A

R

T

S

T

A

R

T

S

T

O

P

BUS ACTIVITY

MASTER

CONTROL

BYTE

WORD

ADDRESS (n)

CONTROL

BYTE

X

X X X

P

S

1

0

1 0 X X X 0

S

1 0 1 0 X X X 1

SDA LINE

A

C

K

A

C

K

A

C

K

N

O

DATA (n)

BUS ACTIVITY

A

C

K

X = Don’t Care Bit

FIGURE 7-10: SEQUENTIAL READ

S

T

O

P

BUS ACTIVITY

MASTER

CONTROL

BYTE

DATA n

DATA n + 1

DATA n + 2

DATA n + X

SDA LINE

P

A

C

K

A

C

K

A

C

K

A

C

K

N

O

BUS ACTIVITY

A

C

K

DS40139E-page 34

1999 Microchip Technology Inc.

PIC12C5XX

The PIC12C5XX has a Watchdog Timer which can be

shut off only through configuration bit WDTE. It runs

off of its own RC oscillator for added reliability. If using

XT or LP selectable oscillator options, there is always

an 18 ms (nominal) delay provided by the Device

Reset Timer (DRT), intended to keep the chip in reset

until the crystal oscillator is stable. If using INTRC or

EXTRC there is an 18 ms delay only on VDD power-up.

With this timer on-chip, most applications need no

external reset circuitry.

8.0

SPECIAL FEATURES OF THE

CPU

What sets

a

microcontroller apart from other

processors are special circuits to deal with the needs

of real-time applications. The PIC12C5XX family of

microcontrollers has a host of such features intended

to maximize system reliability, minimize cost through

elimination of external components, provide power

saving operating modes and offer code protection.

These features are:

The SLEEP mode is designed to offer a very low

current power-down mode. The user can wake-up

from SLEEP through a change on input pins or

through a Watchdog Timer time-out. Several oscillator

options are also made available to allow the part to fit

the application, including an internal 4 MHz oscillator.

The EXTRC oscillator option saves system cost while

• Oscillator selection

• Reset

- Power-On Reset (POR)

- Device Reset Timer (DRT)

- Wake-up from SLEEP on pin change

• Watchdog Timer (WDT)

• SLEEP

the LP crystal option saves power.

A set of

configuration bits are used to select various options.

• Code protection

8.1

Configuration Bits

• ID locations

• In-circuit Serial Programming

The PIC12C5XX configuration word consists of 12

bits. Configuration bits can be programmed to select

various device configurations. Two bits are for the

selection of the oscillator type, one bit is the Watchdog

Timer enable bit, and one bit is the MCLR enable bit.

FIGURE 8-1:

CONFIGURATION WORD FOR PIC12C5XX

—

9

—

8

—

7

—

6

—

5

MCLRE CP

WDTE FOSC1 FOSC0

bit0

Register: CONFIG

Address⁽¹⁾

FFFh

:

bit11

10

4

3

2

1

bit 11-5: Unimplemented

bit 4:

bit 3:

bit 2:

MCLRE: MCLR enable bit.

1 = MCLR pin enabled

0 = MCLR tied to VDD, (Internally)

CP: Code protection bit.

1 = Code protection off

0 = Code protection on

WDTE: Watchdog timer enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator selection bits

11 = EXTRC - external RC oscillator

10 = INTRC - internal RC oscillator

01 = XT oscillator

00 = LP oscillator

Note 1: Refer to the PIC12C5XX Programming Specifications to determine how to access the

configuration word. This register is not user addressable during device operation.

1999 Microchip Technology Inc.

DS40139E-page 35

PIC12C5XX

8.2

Oscillator Configurations

OSCILLATOR TYPES

TABLE 8-1:

CAPACITOR SELECTION

FOR CERAMIC RESONATORS

- PIC12C5XX

8.2.1

The PIC12C5XX can be operated in four different

oscillator modes. The user can program two

configuration bits (FOSC1:FOSC0) to select one of

these four modes:

Osc

Type

Resonator Cap. Range Cap. Range

Freq

C1

C2

XT

4.0 MHz

30 pF

These values are for design guidance only. Since

each resonator has its own characteristics, the user

should consult the resonator manufacturer for

appropriate values of external components.

• LP:

• XT:

Low Power Crystal

Crystal/Resonator

• INTRC: Internal 4 MHz Oscillator

• EXTRC: External Resistor/Capacitor

TABLE 8-2:

CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR -

PIC12C5XX

8.2.2

CRYSTAL OSCILLATOR / CERAMIC

RESONATORS

Osc

Resonator Cap.Range Cap. Range

In XT or LP modes, a crystal or ceramic resonator is

connected to the GP5/OSC1/CLKIN and GP4/OSC2

pins to establish oscillation (Figure 8-2). The

PIC12C5XX oscillator design requires the use of a

parallel cut crystal. Use of a series cut crystal may give

Type

Freq

C1

C2

(1)

LP

XT

32 kHz

15 pF

200 kHz

1 MHz

4 MHz

47-68 pF

15 pF

47-68 pF

15 pF

a

frequency out of the crystal manufacturers

Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is

recommended.

specifications. When in XT or LP modes, the device

can have an external clock source drive the GP5/

OSC1/CLKIN pin (Figure 8-3).

These values are for design guidance only. Rs may

be required to avoid overdriving crystals with low

drive level specification. Since each crystal has its

own characteristics, the user should consult the crys-

tal manufacturer for appropriate values of external

components.

FIGURE 8-2: CRYSTAL OPERATION (OR

CERAMIC RESONATOR) (XT

OR LP OSC

CONFIGURATION)

C1⁽¹⁾

OSC1

PIC12C5XX

SLEEP

XTAL

RF⁽³⁾

To internal

logic

OSC2

RS⁽²⁾

C2⁽¹⁾

Note 1: See Capacitor Selection tables for

recommended values of C1 and C2.

2: A series resistor (RS) may be required for

AT strip cut crystals.

3: RF approximate value = 10 MΩ.

FIGURE 8-3: EXTERNAL CLOCK INPUT

OPERATION (XT OR LP OSC

CONFIGURATION)

OSC1

PIC12C5XX

OSC2

Clock from

ext. system

Open

DS40139E-page 36

1999 Microchip Technology Inc.

PIC12C5XX

8.2.3

EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

8.2.4

EXTERNAL RC OSCILLATOR

For timing insensitive applications, the RC device

option offers additional cost savings. The RC oscillator

frequency is a function of the supply voltage, the

resistor (Rext) and capacitor (Cext) values, and the

operating temperature. In addition to this, the oscillator

frequency will vary from unit to unit due to normal

process parameter variation. Furthermore, the

difference in lead frame capacitance between package

types will also affect the oscillation frequency,

especially for low Cext values. The user also needs to

take into account variation due to tolerance of external

R and C components used.

Either a prepackaged oscillator or a simple oscillator

circuit with TTL gates can be used as an external

crystal oscillator circuit. Prepackaged oscillators

provide a wide operating range and better stability. A

well-designed crystal oscillator will provide good

performance with TTL gates. Two types of crystal

oscillator circuits can be used: one with parallel

resonance, or one with series resonance.

Figure 8-4 shows implementation of

a

parallel

resonant oscillator circuit. The circuit is designed to

use the fundamental frequency of the crystal. The

74AS04 inverter performs the 180-degree phase shift

that a parallel oscillator requires. The 4.7 kΩ resistor

provides the negative feedback for stability. The 10 kΩ

potentiometers bias the 74AS04 in the linear region.

This circuit could be used for external oscillator

designs.

Figure 8-6 shows how the R/C combination is

connected to the PIC12C5XX. For Rext values below

2.2 kΩ, the oscillator operation may become unstable,

or stop completely. For very high Rext values

(e.g., 1 MΩ) the oscillator becomes sensitive to noise,

humidity and leakage. Thus, we recommend keeping

Rext between 3 kΩ and 100 kΩ.

FIGURE 8-4: EXTERNAL PARALLEL

RESONANT CRYSTAL

Although the oscillator will operate with no external

capacitor (Cext = 0 pF), we recommend using values

above 20 pF for noise and stability reasons. With no or

small external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or

package lead frame capacitance.

OSCILLATOR CIRCUIT

+5V

To Other

Devices

10k

74AS04

4.7k

PIC12C5XX

74AS04

CLKIN

The Electrical Specifications sections show RC

frequency variation from part to part due to normal

process variation. The variation is larger for larger R

(since leakage current variation will affect RC

frequency more for large R) and for smaller C (since

variation of input capacitance will affect RC frequency

more).

10k

XTAL

10k

Also, see the Electrical Specifications sections for

variation of oscillator frequency due to VDD for given

Rext/Cext values as well as frequency variation due to

operating temperature for given R, C, and VDD values.

20 pF

Figure 8-5 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental

frequency of the crystal. The inverter performs a 180-

degree phase shift in a series resonant oscillator

circuit. The 330 Ω resistors provide the negative

feedback to bias the inverters in their linear region.

FIGURE 8-6: EXTERNAL RC OSCILLATOR

MODE

VDD

Rext

Internal

FIGURE 8-5: EXTERNAL SERIES

RESONANT CRYSTAL

clock

OSC1

N

OSCILLATOR CIRCUIT

To Other

Devices

Cext

VSS

PIC12C5XX

330

PIC12C5XX

74AS04

CLKIN

0.1 µF

XTAL

1999 Microchip Technology Inc.

DS40139E-page 37

PIC12C5XX

8.2.5

INTERNAL 4 MHz RC OSCILLATOR

Some registers are not reset in any way; they are

unknown on POR and unchanged in any other reset.

Most other registers are reset to “reset state” on power-

on reset (POR), MCLR, WDT or wake-up on pin

change reset during normal operation. They are not

affected by a WDT reset during SLEEP or MCLR reset

during SLEEP, since these resets are viewed as

resumption of normal operation. The exceptions to this

are TO, PD, and GPWUF bits. They are set or cleared

differently in different reset situations. These bits are

used in software to determine the nature of reset. See

Table 8-3 for a full description of reset states of all

registers.

The internal RC oscillator provides a fixed 4 MHz (nom-

inal) system clock at VDD = 5V and 25°C, see “Electri-

cal Specifications” section for information on variation

over voltage and temperature.

In addition, a calibration instruction is programmed into

the top of memory which contains the calibration value

for the internal RC oscillator. This location is never code

protected regardless of the code protect settings. This

value is programmed as a MOVLW XXinstruction where

XX is the calibration value, and is placed at the reset

vector. This will load the W register with the calibration

value upon reset and the PC will then roll over to the

users program at address 0x000. The user then has the

option of writing the value to the OSCCAL Register

(05h) or ignoring it.

OSCCAL, when written to with the calibration value, will

“trim” the internal oscillator to remove process variation

from the oscillator frequency. .

Note: Please note that erasing the device will

also erase the pre-programmed internal

calibration value for the internal oscillator.

The calibration value must be read prior to

erasing the part. so it can be repro-

grammed correctly later.

For the PIC12C508A, PIC12C509A, PIC12CE518,

PIC12CE519, and PIC12CR509A, bits <7:2>, CAL5-

CAL0 are used for calibration. Adjusting CAL5-0 from

000000 to 111111 yields a higher clock speed. Note

that bits 1 and 0 of OSCCAL are unimplemented and

should be written as 0 when modifying OSCCAL for

compatibility with future devices.

For the PIC12C508 and PIC12C509, the upper 4 bits of

the register are used. Writing a larger value in this loca-

tion yields a higher clock speed.

8.3

RESET

The device differentiates between various kinds of

reset:

a) Power on reset (POR)

b) MCLR reset during normal operation

c) MCLR reset during SLEEP

d) WDT time-out reset during normal operation

e) WDT time-out reset during SLEEP

f) Wake-up from SLEEP on pin change

DS40139E-page 38

1999 Microchip Technology Inc.

PIC12C5XX

TABLE 8-3:

RESET CONDITIONS FOR REGISTERS

MCLR Reset

WDT time-out

Register

Address

Power-on Reset

Wake-up on Pin Change

(1)

—

W (PIC12C508/509)

qqqq xxxx

qqqq uuuu

(1)

W (PIC12C508A/509A/

PIC12CE518/519/

PIC12CE509A)

qqqq qqxx

qqqq qquu

INDF

TMR0

PC

00h

01h

02h

03h

xxxx xxxx

1111 1111

0001 1xxx

uuuu uuuu

1111 1111

(2,3)

STATUS

q00q quuu

FSR (PIC12C508/

PIC12C508A/

04h

111x xxxx

111u uuuu

PIC12CE518)

FSR (PIC12C509/

PIC12C509A/

04h

110x xxxx

11uu uuuu

PIC12CE519/

PIC12CR509A)

OSCCAL

(PIC12C508/509)

05h

0111 ----

1000 00--

uuuu ----

uuuu uu--

OSCCAL

(PIC12C508A/509A/

PIC12CE518/512/

PIC12CR509A)

GPIO

06h

--xx xxxx

--uu uuuu

(PIC12C508/PIC12C509/

PIC12C508A/

PIC12C509A/

PIC12CR509A)

GPIO

(PIC12CE518/

PIC12CE519)

11xx xxxx

1111 1111

--11 1111

11uu uuuu

1111 1111

--11 1111

OPTION

TRIS

—

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.

Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XXinstruction at top of memory.

Note 2: See Table 8-7 for reset value for specific conditions

Note 3: If reset was due to wake-up on pin change, then bit 7 = 1. All other resets will cause bit 7 = 0.

TABLE 8-4:

RESET CONDITION FOR SPECIAL REGISTERS

STATUS Addr: 03h

PCL Addr: 02h

Power on reset

0001 1xxx

1111 1111

MCLR reset during normal operation

MCLR reset during SLEEP

000u uuuu

0001 0uuu

0000 0uuu

0000 uuuu

1001 0uuu

WDT reset during SLEEP

WDT reset normal operation

Wake-up from SLEEP on pin change

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’.

1999 Microchip Technology Inc.

DS40139E-page 39

PIC12C5XX

8.3.1

MCLR ENABLE

The Power-On Reset circuit and the Device Reset

Timer (Section 8.5) circuit are closely related. On

power-up, the reset latch is set and the DRT is reset.

The DRT timer begins counting once it detects MCLR

to be high. After the time-out period, which is typically

18 ms, it will reset the reset latch and thus end the on-

chip reset signal.

This configuration bit when unprogrammed (left in the

‘1’ state) enables the external MCLR function. When

programmed, the MCLR function is tied to the internal

VDD, and the pin is assigned to be a GPIO. See

Figure 8-7. When pin GP3/MCLR/VPP is configured as

MCLR, the internal pull-up is always on.

A power-up example where MCLR is held low is

shown in Figure 8-9. VDD is allowed to rise and

stabilize before bringing MCLR high. The chip will

actually come out of reset TDRT msec after MCLR

goes high.

FIGURE 8-7: MCLR SELECT

MCLRE

In Figure 8-10, the on-chip Power-On Reset feature is

being used (MCLR and VDD are tied together or the

pin is programmed to be GP3.). The VDD is stable

before the start-up timer times out and there is no

problem in getting a proper reset. However, Figure 8-

11 depicts a problem situation where VDD rises too

slowly. The time between when the DRT senses that

MCLR is high and when MCLR (and VDD) actually

reach their full value, is too long. In this situation, when

the start-up timer times out, VDD has not reached the

VDD (min) value and the chip is, therefore, not

guaranteed to function correctly. For such situations,

we recommend that external RC circuits be used to

achieve longer POR delay times (Figure 8-10).

WEAK

PULL-UP

INTERNAL MCLR

GP3/MCLR/VPP

8.4

Power-On Reset (POR)

The PIC12C5XX family incorporates on-chip Power-

On Reset (POR) circuitry which provides an internal

chip reset for most power-up situations.

The on-chip POR circuit holds the chip in reset until

VDD has reached a high enough level for proper opera-

tion. To take advantage of the internal POR, program

the GP3/MCLR/VPP pin as MCLR and tie through a

resistor to VDD or program the pin as GP3. An internal

weak pull-up resistor is implemented using a transistor.

Refer to Table 11-1 for the pull-up resistor ranges. This

will eliminate external RC components usually needed

to create a Power-on Reset. A maximum rise time for

VDD is specified. See Electrical Specifications for

details.

Note: When the device starts normal operation

(exits the reset condition), device operating

parameters (voltage, frequency, tempera-

ture, etc.) must be meet to ensure opera-

tion. If these conditions are not met, the

device must be held in reset until the oper-

ating conditions are met.

For additional information refer to Application Notes

“Power-Up Considerations” - AN522 and “Power-up

Trouble Shooting” - AN607.

When the device starts normal operation (exits the

reset condition), device operating parameters (voltage,

frequency, temperature, ...) must be met to ensure

operation. If these conditions are not met, the device

must be held in reset until the operating parameters are

met.

A simplified block diagram of the on-chip Power-On

Reset circuit is shown in Figure 8-8.

DS40139E-page 40

1999 Microchip Technology Inc.

PIC12C5XX

FIGURE 8-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Power-Up

Detect

Pin Change

SLEEP

POR (Power-On Reset)

VDD

Wake-up on

pin change

GP3/MCLR/VPP

WDT Time-out

MCLRE

RESET

S

R

Q

8-bit Asynch

On-Chip

DRT OSC

Ripple Counter

(Start-Up Timer)

CHIP RESET

FIGURE 8-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)

VDD

MCLR

INTERNAL POR

TDRT

DRT TIME-OUT

INTERNAL RESET

FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME

VDD

MCLR

INTERNAL POR

TDRT

DRT TIME-OUT

INTERNAL RESET

1999 Microchip Technology Inc.

DS40139E-page 41

PIC12C5XX

FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME

V1

VDD

MCLR

INTERNAL POR

TDRT

DRT TIME-OUT

INTERNAL RESET

When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In

this example, the chip will reset properly if, and only if, V1 ≥ VDD min.

8.5

Device Reset Timer (DRT)

8.6

Watchdog Timer (WDT)

In the PIC12C5XX, DRT runs from RESET and varies

based on oscillator selection (see Table 8-5.)

The Watchdog Timer (WDT) is a free running on-chip

RC oscillator which does not require any external

components. This RC oscillator is separate from the

external RC oscillator of the GP5/OSC1/CLKIN pin

and the internal 4 MHz oscillator. That means that the

WDT will run even if the main processor clock has

been stopped, for example, by execution of a SLEEP

instruction. During normal operation or SLEEP, a WDT

reset or wake-up reset generates a device RESET.

The DRT operates on an internal RC oscillator. The

processor is kept in RESET as long as the DRT is

active. The DRT delay allows VDD to rise above VDD

min., and for the oscillator to stabilize.

Oscillator circuits based on crystals or ceramic

resonators require a certain time after power-up to

establish a stable oscillation. The on-chip DRT keeps

the device in a RESET condition for approximately 18

ms after MCLR has reached a logic high (VIHMCLR)

level. Thus, programming GP3/MCLR/VPP as MCLR

and using an external RC network connected to the

MCLR input is not required in most cases, allowing for

savings in cost-sensitive and/or space restricted

applications, as well as allowing the use of the GP3/

MCLR/VPP pin as a general purpose input.

The TO bit (STATUS<4>) will be cleared upon a

Watchdog Timer reset.

The WDT can be permanently disabled by

programming the configuration bit WDTE as a ’0’

(Section 8.1). Refer to the PIC12C5XX Programming

Specifications to determine how to access the

configuration word.

TABLE 8-5:

DRT (DEVICE RESET TIMER

PERIOD)

The Device Reset time delay will vary from chip to chip

due to VDD, temperature, and process variation. See

AC parameters for details.

Oscillator

Configuration

Subsequent

POR Reset

Resets

The DRT will also be triggered upon a Watchdog

Timer time-out. This is particularly important for

applications using the WDT to wake from SLEEP

mode automatically.

IntRC &

ExtRC

18 ms (typical) 300 µs (typical)

XT & LP

18 ms (typical)

DS40139E-page 42

1999 Microchip Technology Inc.

PIC12C5XX

8.6.1

WDT PERIOD

8.6.2

WDT PROGRAMMING CONSIDERATIONS

The WDT has a nominal time-out period of 18 ms,

(with no prescaler). If a longer time-out period is

desired, a prescaler with a division ratio of up to 1:128

can be assigned to the WDT (under software control)

by writing to the OPTION register. Thus, a time-out

period of a nominal 2.3 seconds can be realized.

These periods vary with temperature, VDD and part-to-

part process variations (see DC specs).

The CLRWDT instruction clears the WDT and the

postscaler, if assigned to the WDT, and prevents it

from timing out and generating a device RESET.

The SLEEP instruction resets the WDT and the

postscaler, if assigned to the WDT. This gives the

maximum SLEEP time before a WDT wake-up reset.

Under worst case conditions (VDD = Min., Temperature

= Max., max. WDT prescaler), it may take several

seconds before a WDT time-out occurs.

FIGURE 8-12: WATCHDOG TIMER BLOCK DIAGRAM

From Timer0 Clock Source

(Figure 8-5)

0

M

Postscaler

1

Watchdog

Timer

U

X

8 - to - 1 MUX

PS2:PS0

PSA

WDT Enable

Configuration Bit

To Timer0 (Figure 8-4)

1

0

PSA

MUX

Note: T0CS, T0SE, PSA, PS2:PS0

are bits in the OPTION register.

WDT

Time-out

TABLE 8-6:

SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Value on

Power-On

Reset

Value on

All Other

Resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1 Bit 0

PS1 PS0

N/A

OPTION

GPWU

GPPU

T0CS

T0SE

PSA

PS2

1111 1111

Legend: Shaded boxes = Not used by Watchdog Timer, —= unimplemented, read as ’0’, u= unchanged

1999 Microchip Technology Inc.

DS40139E-page 43

PIC12C5XX

8.7

Time-Out Sequence, Power Down,

and Wake-up from SLEEP Status Bits

(TO/PD/GPWUF)

FIGURE 8-14: BROWN-OUT PROTECTION

CIRCUIT 2

VDD

The TO, PD, and GPWUF bits in the STATUS register

can be tested to determine if a RESET condition has

been caused by a power-up condition, a MCLR or

Watchdog Timer (WDT) reset.

VDD

R1

Q1

MCLR

TABLE 8-7:

TO/PD/GPWUF STATUS

AFTER RESET

R2

40k*

PIC12C5XX

GPWUF TO PD

RESET caused by

WDT wake-up from

0

1

0

u

0

SLEEP

WDT time-out (not from

SLEEP)

This brown-out circuit is less expensive, although

less accurate. Transistor Q1 turns off when VDD

is below a certain level such that:

MCLR wake-up from

SLEEP

R1

= 0.7V

0

1

u

1

u

0

Power-up

VDD •

R1 + R2

MCLR not during SLEEP

*Refer to Figure 8-7 and Table 11-1 for internal

weak pull-up on MCLR.

Wake-up from SLEEP on

pin change

Legend: u = unchanged

Note 1: The TO, PD, and GPWUF bits maintain

their status (u) until a reset occurs. A low-

pulse on the MCLR input does not change

the TO, PD, and GPWUF status bits.

FIGURE 8-15: BROWN-OUT PROTECTION

CIRCUIT 3

VDD

8.8

Reset on Brown-Out

MCP809

VDD

bypass

capacitor

Vss

A brown-out is a condition where device power (VDD)

dips below its minimum value, but not to zero, and then

recovers. The device should be reset in the event of a

brown-out.

VDD

RST

MCLR

PIC12C5XX

To reset PIC12C5XX devices when

a brown-out

occurs, external brown-out protection circuits may be

This brown-out protection circuit employs

Microchip Technology’s MCP809 microcontroller

supervisor. The MCP8XX and MCP1XX family of

supervisors provide push-pull and open collector

outputs with both high and low active reset pins.

There are 7 different trip point selections to

accomodate 5V and 3V systems.

built, as shown in Figure 8-13

Figure 8-15

, Figure 8-14 and

FIGURE 8-13: BROWN-OUT PROTECTION

CIRCUIT 1

VDD

33k

Q1

10k

MCLR

40k*

PIC12C5XX

This circuit will activate reset when VDD goes below

Vz + 0.7V (where Vz = Zener voltage).

*Refer to Figure 8-7 and Table 11-1 for internal

weak pull-up on MCLR.

DS40139E-page 44

1999 Microchip Technology Inc.

PIC12C5XX

8.9

Power-Down Mode (SLEEP)

8.10

Program Verification/Code Protection

A device may be powered down (SLEEP) and later

powered up (Wake-up from SLEEP).

If the code protection bit has not been programmed,

the on-chip program memory can be read out for

verification purposes.

8.9.1

SLEEP

The first 64 locations can be read by the PIC12C5XX

regardless of the code protection bit setting.

The Power-Down mode is entered by executing a

SLEEPinstruction.

The last memory location cannot be read if code pro-

tection is enabled on the PIC12C508/509.

If enabled, the Watchdog Timer will be cleared but

keeps running, the TO bit (STATUS<4>) is set, the PD

bit (STATUS<3>) is cleared and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, driving low, or hi-impedance).

The last memory location can be read regardless of the

code protection bit setting on the PIC12C508A/509A/

CR509A/CE518/CE519.

8.11

ID Locations

It should be noted that a RESET generated by a WDT

time-out does not drive the MCLR pin low.

Four memory locations are designated as ID locations

where the user can store checksum or other code-

identification numbers. These locations are not

accessible during normal execution but are readable

and writable during program/verify.

For lowest current consumption while powered down,

the T0CKI input should be at VDD or VSS and the GP3/

MCLR/VPP pin must be at a logic high level (VIHMC) if

MCLR is enabled.

Use only the lower 4 bits of the ID locations and

always program the upper 8 bits as ’0’s.

8.9.2

WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of

the following events:

1. An external reset input on GP3/MCLR/VPP pin,

when configured as MCLR.

2. A Watchdog Timer time-out reset (if WDT was

enabled).

3. A change on input pin GP0, GP1, or GP3/

MCLR/VPP when wake-up on change is

enabled.

These events cause a device reset. The TO, PD, and

GPWUF bits can be used to determine the cause of

device reset. The TO bit is cleared if a WDT time-out

occurred (and caused wake-up). The PD bit, which is

set on power-up, is cleared when SLEEP is invoked.

The GPWUF bit indicates a change in state while in

SLEEP at pins GP0, GP1, or GP3 (since the last time

there was a file or bit operation on GP port).

Caution: Right before entering SLEEP, read the

input pins. When in SLEEP, wake up

occurs when the values at the pins change

from the state they were in at the last

reading. If a wake-up on change occurs

and the pins are not read before

reentering SLEEP, a wake up will occur

immediately even if no pins change while

in SLEEP mode.

The WDT is cleared when the device wakes from

sleep, regardless of the wake-up source.

1999 Microchip Technology Inc.

DS40139E-page 45

PIC12C5XX

8.12

In-Circuit Serial Programming

FIGURE 8-16: TYPICAL IN-CIRCUIT SERIAL

PROGRAMMING

The PIC12C5XX microcontrollers with EPROM pro-

gram memory can be serially programmed while in the

end application circuit. This is simply done with two

lines for clock and data, and three other lines for power,

ground, and the programming voltage. This allows cus-

tomers to manufacture boards with unprogrammed

devices, and then program the microcontroller just

before shipping the product. This also allows the most

recent firmware or a custom firmware to be pro-

grammed.

CONNECTION

To Normal

Connections

External

Connector

Signals

PIC12C5XX

+5V

0V

VDD

VSS

VPP

MCLR/VPP

The device is placed into a program/verify mode by

holding the GP1 and GP0 pins low while raising the

MCLR (VPP) pin from VIL to VIHH (see programming

specification). GP1 becomes the programming clock

and GP0 becomes the programming data. Both GP1

and GP0 are Schmitt Trigger inputs in this mode.

GP1

GP0

CLK

Data I/O

VDD

After reset, a 6-bit command is then supplied to the

device. Depending on the command, 14-bits of pro-

gram data are then supplied to or from the device,

depending if the command was a load or a read. For

complete details of serial programming, please refer to

the PIC12C5XX Programming Specifications.

To Normal

Connections

A typical in-circuit serial programming connection is

shown in Figure 8-16.

DS40139E-page 46

1999 Microchip Technology Inc.

PIC12C5XX

All instructions are executed within a single instruction

cycle, unless a conditional test is true or the program

counter is changed as a result of an instruction. In this

case, the execution takes two instruction cycles. One

instruction cycle consists of four oscillator periods.

Thus, for an oscillator frequency of 4 MHz, the normal

instruction execution time is 1 µs. If a conditional test is

true or the program counter is changed as a result of

an instruction, the instruction execution time is 2 µs.

9.0

INSTRUCTION SET SUMMARY

Each PIC12C5XX instruction is a 12-bit word divided

into an OPCODE, which specifies the instruction type,

and one or more operands which further specify the

operation of the instruction. The PIC12C5XX

instruction set summary in Table 9-2 groups the

instructions into byte-oriented, bit-oriented, and literal

and control operations. Table 9-1 shows the opcode

field descriptions.

Figure 9-1 shows the three general formats that the

instructions can have. All examples in the figure use the

following format to represent a hexadecimal number:

For byte-oriented instructions, ’f’ represents a file

register designator and ’d’ represents a destination

designator. The file register designator is used to

specify which one of the 32 file registers is to be used

by the instruction.

0xhhh

where ’h’ signifies a hexadecimal digit.

The destination designator specifies where the result

of the operation is to be placed. If ’d’ is ’0’, the result is

placed in the W register. If ’d’ is ’1’, the result is placed

in the file register specified in the instruction.

FIGURE 9-1: GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented file register operations

11

6

5

4

0

For bit-oriented instructions, ’b’ represents a bit field

designator which selects the number of the bit affected

by the operation, while ’f’ represents the number of the

file in which the bit is located.

OPCODE

d

f (FILE #)

d = 0 for destination W

d = 1 for destination f

f = 5-bit file register address

Bit-oriented file register operations

11 8 7

b (BIT #)

For literal and control operations, ’k’ represents an

8 or 9-bit constant or literal value.

5

4

0

TABLE 9-1:

OPCODE FIELD

DESCRIPTIONS

OPCODE

f (FILE #)

b = 3-bit bit address

f = 5-bit file register address

Field

Description

f

W

b

k

Register file address (0x00 to 0x7F)

Working register (accumulator)

Literal and control operations (except GOTO)

11

8

7

0

Bit address within an 8-bit file register

Literal field, constant data or label

OPCODE

k (literal)

k = 8-bit immediate value

Don’t care location (= 0 or 1)

The assembler will generate code with x = 0. It is

the recommended form of use for compatibility

with all Microchip software tools.

Literal and control operations - GOTOinstruction

11 0

x

d

9

8

OPCODE

k (literal)

Destination select;

d = 0 (store result in W)

d = 1 (store result in file register ’f’)

Default is d = 1

k = 9-bit immediate value

label Label name

TOS

PC

Top of Stack

Program Counter

Watchdog Timer Counter

Time-Out bit

WDT

TO

PD

Power-Down bit

Destination, either the W register or the specified

register file location

dest

[ ]

( )

→

Options

Contents

Assigned to

< >

Register bit field

In the set of

italics

User defined term (font is courier)

1999 Microchip Technology Inc.

DS40139E-page 47

PIC12C5XX

TABLE 9-2:

INSTRUCTION SET SUMMARY

12-Bit Opcode

Mnemonic,

Operands

Status

Description

Cycles MSb

LSb Affected Notes

1

0001 11df ffff

C,DC,Z 1,2,4

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate left f through Carry

Rotate right f through Carry

Subtract W from f

Swap f

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

f,d

f

0001 01df ffff

0000 011f ffff

0000 0100 0000

0010 01df ffff

0000 11df ffff

Z

2,4

4

–

Z

f, d

f

Z

None

Z

None

Z

None

C

2,4

1,4

1(2) 0010 11df ffff

0010 10df ffff

1(2) 0011 11df ffff

1

0001 00df ffff

0010 00df ffff

0000 001f ffff

0000 0000 0000

0011 01df ffff

0011 00df ffff

0000 10df ffff

0011 10df ffff

0001 10df ffff

–

2,4

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

C

C,DC,Z 1,2,4

None

Z

2,4

Exclusive OR W with f

BIT-ORIENTED FILE REGISTER OPERATIONS

1

0100 bbbf ffff

0101 bbbf ffff

None

2,4

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

BCF

BSF

BTFSC

BTFSS

f, b

1 (2) 0110 bbbf ffff

1 (2) 0111 bbbf ffff

LITERAL AND CONTROL OPERATIONS

1

2

1

2

1

2

1

1110 kkkk kkkk

1001 kkkk kkkk

0000 0000 0100

101k kkkk kkkk

1101 kkkk kkkk

1100 kkkk kkkk

0000 0000 0010

1000 kkkk kkkk

0000 0000 0011

0000 0000 0fff

1111 kkkk kkkk

Z

AND literal with W

Call subroutine

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

OPTION

RETLW

SLEEP

TRIS

k

–

k

–

f

None

TO, PD

None

Z

None

TO, PD

None

Z

1

3

Clear Watchdog Timer

Unconditional branch

Inclusive OR Literal with W

Move Literal to W

Load OPTION register

Return, place Literal in W

Go into standby mode

Load TRIS register

Exclusive OR Literal to W

XORLW

k

Note 1: The 9th bit of the program counter will be forced to a ’0’ by any instruction that writes to the PC except for GOTO.

(Section 4.6)

2: When an I/O register is modified as a function of itself (e.g. MOVF GPIO, 1), the value used will be that value

present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven

low by an external device, the data will be written back with a ’0’.

3: The instruction TRIS f, where f = 6 causes the contents of the W register to be written to the tristate latches of

GPIO. A ’1’ forces the pin to a hi-impedance state and disables the output buffers.

4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared

(if assigned to TMR0).

DS40139E-page 48

1999 Microchip Technology Inc.

PIC12C5XX

ADDWF

Syntax:

Add W and f

[ label ] ADDWF f,d

0 ≤ f ≤ 31

ANDWF

Syntax:

AND W with f

[ label ] ANDWF f,d

Operands:

0 ≤ f ≤ 31

d

[0,1]

d

[0,1]

Operation:

(W) + (f) → (dest)

Operation:

(W) .AND. (f) → (dest)

Status Affected: C, DC, Z

Status Affected:

Encoding:

Z

0001

11df

ffff

0001

01df

ffff

Encoding:

Add the contents of the W register and

register ’f’. If ’d’ is 0 the result is stored

in the W register. If ’d’ is ’1’ the result is

stored back in register ’f’.

The contents of the W register are

AND’ed with register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is

'1' the result is stored back in register 'f'.

Description:

Words:

1

Words:

1

Cycles:

Example:

Cycles:

Example:

ADDWF

FSR,

0

ANDWF

FSR,

1

Before Instruction

0x17

W

=

0x17

W

=

FSR = 0xC2

After Instruction

W

=

0xD9

W

=

0x17

FSR = 0xC2

FSR = 0x02

ANDLW

And literal with W

[ label ] ANDLW

0 ≤ k ≤ 255

BCF

Bit Clear f

Syntax:

k

Syntax:

Operands:

[ label ] BCF f,b

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 ≤ f ≤ 31

0 ≤ b ≤ 7

(W).AND. (k) → (W)

Operation:

0 → (f<b>)

Z

Status Affected: None

1110

kkkk

0100

bbbf

ffff

Encoding:

Description:

Words:

The contents of the W register are

AND’ed with the eight-bit literal 'k'. The

result is placed in the W register.

Bit 'b' in register 'f' is cleared.

1

Words:

1

Cycles:

Example:

BCF

FLAG_REG,

7

Example:

ANDLW

0x5F

Before Instruction

FLAG_REG = 0xC7

Before Instruction

0xA3

W

=

After Instruction

FLAG_REG = 0x47

After Instruction

0x03

W

=

1999 Microchip Technology Inc.

DS40139E-page 49

PIC12C5XX

BSF

Bit Set f

BTFSS

Bit Test f, Skip if Set

Syntax:

Operands:

[ label ] BSF f,b

Syntax:

[ label ] BTFSS f,b

0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operands:

0 ≤ f ≤ 31

0 ≤ b < 7

Operation:

1 → (f<b>)

Operation:

skip if (f<b>) = 1

Status Affected: None

0101

bbbf

ffff

0111

bbbf

ffff

Encoding:

Description:

Words:

Encoding:

Bit ’b’ in register ’f’ is set.

If bit ’b’ in register ’f’ is ’1’ then the next

instruction is skipped.

Description:

1

If bit ’b’ is ’1’, then the next instruction

fetched during the current instruction

execution, is discarded and an NOP is

executed instead, making this a 2 cycle

instruction.

Cycles:

BSF

FLAG_REG,

7

Example:

Before Instruction

FLAG_REG = 0x0A

Words:

1

After Instruction

FLAG_REG = 0x8A

Cycles:

Example:

1(2)

HERE

FALSE GOTO

TRUE

BTFSS FLAG,1

PROCESS_CODE

•

BTFSC

Bit Test f, Skip if Clear

•

Syntax:

[ label ] BTFSC f,b

Operands:

0 ≤ f ≤ 31

0 ≤ b ≤ 7

Before Instruction

PC

=

address (HERE)

After Instruction

If FLAG<1>

PC

Operation:

skip if (f<b>) = 0

=

0,

Status Affected: None

address (FALSE);

1,

address (TRUE)

bbbf

ffff

if FLAG<1>

PC

Encoding:

0110

If bit ’b’ in register ’f’ is 0 then the next

instruction is skipped.

Description:

If bit ’b’ is 0 then the next instruction

fetched during the current instruction

execution is discarded, and an NOP is

executed instead, making this a 2 cycle

instruction.

Words:

1

Cycles:

Example:

1(2)

HERE

FALSE

TRUE

BTFSC

GOTO

•

FLAG,1

PROCESS_CODE

Before Instruction

PC

=

address (HERE)

After Instruction

if FLAG<1>

PC

=

0,

address (TRUE);

1,

address(FALSE)

if FLAG<1>

PC

DS40139E-page 50

1999 Microchip Technology Inc.

PIC12C5XX

CALL

Subroutine Call

[ label ] CALL

0 ≤ k ≤ 255

CLRW

Clear W

Syntax:

k

Syntax:

[ label ] CLRW

None

Operands:

Operation:

Operands:

Operation:

(PC) + 1→ Top of Stack;

k → PC<7:0>;

00h → (W);

1 → Z

(STATUS<6:5>) → PC<10:9>;

0 → PC<8>

Status Affected:

Encoding:

Z

0000

0100

0000

Status Affected: None

The W register is cleared. Zero bit (Z)

is set.

Description:

1001

kkkk

Encoding:

Subroutine call. First, return address

(PC+1) is pushed onto the stack. The

eight bit immediate address is loaded

into PC bits <7:0>. The upper bits

PC<10:9> are loaded from STA-

TUS<6:5>, PC<8> is cleared. CALLis

a two cycle instruction.

Description:

Words:

1

Cycles:

Example:

1

CLRW

Before Instruction

0x5A

W

=

After Instruction

Words:

1

2

W

=

0x00

Cycles:

Example:

Z

=

1

HERE

CALL

THERE

Before Instruction

PC address (HERE)

CLRWDT

Clear Watchdog Timer

[ label ] CLRWDT

None

=

Syntax:

After Instruction

PC address (THERE)

TOS = + 1)

=

Operands:

Operation:

address (HERE

00h → WDT;

0 → WDT prescaler (if assigned);

1 → TO;

1 → PD

CLRF

Clear f

Syntax:

[ label ] CLRF

0 ≤ f ≤ 31

f

Status Affected: TO, PD

Operands:

Operation:

0000

0100

Encoding:

00h → (f);

1 → Z

The CLRWDTinstruction resets the

WDT. It also resets the prescaler, if the

prescaler is assigned to the WDT and

not Timer0. Status bits TO and PD are

set.

Description:

Status Affected:

Encoding:

Z

0000

011f

ffff

The contents of register ’f’ are cleared

and the Z bit is set.

Description:

Words:

1

Cycles:

Example:

1

Words:

1

CLRWDT

Cycles:

Example:

Before Instruction

CLRF

FLAG_REG

WDT counter

=

?

Before Instruction

FLAG_REG

After Instruction

WDT counter

=

0x5A

0x00

After Instruction

WDT prescale =

0

1

FLAG_REG

Z

=

0x00

1

TO

PD

=

1999 Microchip Technology Inc.

DS40139E-page 51

PIC12C5XX

COMF

Complement f

[ label ] COMF f,d

0 ≤ f ≤ 31

DECFSZ

Syntax:

Decrement f, Skip if 0

[ label ] DECFSZ f,d

0 ≤ f ≤ 31

Syntax:

Operands:

d

[0,1]

d

[0,1]

Operation:

(f) → (dest)

Operation:

(f) – 1 → d; skip if result = 0

Status Affected:

Encoding:

Z

Status Affected: None

0010

01df

ffff

0010

11df

ffff

Encoding:

The contents of register ’f’ are comple-

mented. If ’d’ is 0 the result is stored in

the W register. If ’d’ is 1 the result is

stored back in register ’f’.

The contents of register ’f’ are decre-

mented. If ’d’ is 0 the result is placed in

the W register. If ’d’ is 1 the result is

placed back in register ’f’.

Description:

If the result is 0, the next instruction,

which is already fetched, is discarded

and an NOP is executed instead mak-

ing it a two cycle instruction.

Words:

1

Cycles:

Example:

COMF

REG1,0

Words:

1

Before Instruction

REG1

=

0x13

Cycles:

Example:

1(2)

After Instruction

HERE

DECFSZ

GOTO

CNT,

LOOP

1

REG1

=

W

=

0xEC

CONTINUE

•

DECF

Decrement f

[ label ] DECF f,d

0 ≤ f ≤ 31

Before Instruction

PC

=

address (HERE)

Syntax:

After Instruction

Operands:

CNT

if CNT

PC

if CNT

PC

=

≠

=

CNT - 1;

0,

address (CONTINUE);

0,

d

[0,1]

Operation:

(f) – 1 → (dest)

Status Affected:

Encoding:

Z

address (HERE+1)

0000

11df

ffff

Decrement register ’f’. If ’d’ is 0 the

result is stored in the W register. If ’d’ is

1 the result is stored back in register ’f’.

Description:

GOTO

Unconditional Branch

Syntax:

[ label ] GOTO

0 ≤ k ≤ 511

k

Words:

1

Operands:

Cycles:

Example:

Operation:

k → PC<8:0>;

STATUS<6:5> → PC<10:9>

DECF

CNT,

1

Before Instruction

Status Affected: None

CNT

=

0x01

0

101k

kkkk

Encoding:

Z

=

GOTOis an unconditional branch. The

9-bit immediate value is loaded into PC

bits <8:0>. The upper bits of PC are

loaded from STATUS<6:5>. GOTOis a

two cycle instruction.

Description:

After Instruction

CNT

=

0x00

1

Z

=

Words:

1

Cycles:

Example:

2

GOTO THERE

After Instruction

PC

=

address (THERE)

DS40139E-page 52

1999 Microchip Technology Inc.

PIC12C5XX

INCF

Increment f

IORLW

Inclusive OR literal with W

Syntax:

Operands:

[ label ] INCF f,d

Syntax:

[ label ] IORLW k

0 ≤ f ≤ 31

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 ≤ k ≤ 255

d

[0,1]

(W) .OR. (k) → (W)

Operation:

(f) + 1 → (dest)

Z

Status Affected:

Encoding:

Z

1101

kkkk

0010

10df

ffff

The contents of the W register are

OR’ed with the eight bit literal 'k'. The

result is placed in the W register.

The contents of register ’f’ are incre-

mented. If ’d’ is 0 the result is placed in

the W register. If ’d’ is 1 the result is

placed back in register ’f’.

Description:

Words:

1

Cycles:

Example:

Words:

1

IORLW

0x35

Cycles:

Example:

Before Instruction

0x9A

INCF

CNT,

1

W

=

Before Instruction

After Instruction

CNT

=

0xFF

0

W

=

0xBF

Z

=

Z

=

0

After Instruction

CNT

Z

=

0x00

1

IORWF

Inclusive OR W with f

[ label ] IORWF f,d

0 ≤ f ≤ 31

Syntax:

Operands:

INCFSZ

Increment f, Skip if 0

[ label ] INCFSZ f,d

0 ≤ f ≤ 31

d

[0,1]

Syntax:

Operation:

(W).OR. (f) → (dest)

Operands:

Status Affected:

Encoding:

Z

d

[0,1]

0001

00df

ffff

Operation:

(f) + 1 → (dest), skip if result = 0

Inclusive OR the W register with regis-

ter 'f'. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Description:

Status Affected: None

0011

11df

ffff

Encoding:

The contents of register ’f’ are incre-

mented. If ’d’ is 0 the result is placed in

the W register. If ’d’ is 1 the result is

placed back in register ’f’.

Description:

Words:

1

Cycles:

Example:

If the result is 0, then the next instruc-

tion, which is already fetched, is dis-

carded and an NOP is executed

instead making it a two cycle instruc-

tion.

IORWF

RESULT, 0

Before Instruction

RESULT

W

=

0x13

=

0x91

After Instruction

Words:

1

RESULT

=

0x13

0x93

0

Cycles:

Example:

1(2)

W

Z

HERE

INCFSZ

GOTO

CNT,

LOOP

1

CONTINUE

•

Before Instruction

PC

=

address (HERE)

After Instruction

CNT

if CNT

PC

if CNT

PC

=

≠

=

CNT + 1;

0,

address (CONTINUE);

0,

address (HERE +1)

1999 Microchip Technology Inc.

DS40139E-page 53

PIC12C5XX

MOVF

Move f

MOVWF

Syntax:

Move W to f

[ label ] MOVWF

0 ≤ f ≤ 31

Syntax:

Operands:

[ label ] MOVF f,d

f

0 ≤ f ≤ 31

Operands:

Operation:

d

[0,1]

(W) → (f)

Operation:

(f) → (dest)

Status Affected: None

Status Affected:

Encoding:

Z

0000

001f

ffff

Encoding:

0010

00df

ffff

Move data from the W register to regis-

Description:

ter 'f'.

The contents of register ’f’ is moved to

destination ’d’. If ’d’ is 0, destination is

the W register. If ’d’ is 1, the destination

is file register ’f’. ’d’ is 1 is useful to test

a file register since status flag Z is

affected.

Description:

Words:

1

Cycles:

Example:

MOVWF

TEMP_REG

Before Instruction

TEMP_REG

Words:

1

=

0xFF

0x4F

Cycles:

Example:

W

MOVF

FSR,

0

After Instruction

TEMP_REG

W

=

0x4F

After Instruction

W

=

value in FSR register

NOP

No Operation

[ label ] NOP

None

MOVLW

Move Literal to W

[ label ] MOVLW

0 ≤ k ≤ 255

Syntax:

k

Operands:

Operation:

Operands:

Operation:

No operation

k → (W)

Status Affected: None

0000

Status Affected: None

Encoding:

Description:

Words:

1100

kkkk

Encoding:

No operation.

The eight bit literal ’k’ is loaded into the

W register. The don’t cares will assem-

ble as 0s.

Description:

1

Cycles:

1

NOP

Example:

Words:

1

Cycles:

Example:

MOVLW

0x5A

After Instruction

W

=

0x5A

DS40139E-page 54

1999 Microchip Technology Inc.

PIC12C5XX

OPTION

Syntax:

Load OPTION Register

[ label ] OPTION

None

RLF

Rotate Left f through Carry

[ label ] RLF f,d

0 ≤ f ≤ 31

Syntax:

Operands:

Operation:

d

[0,1]

(W) → OPTION

Status Affected: None

Operation:

See description below

C

0000

0010

Encoding:

Status Affected:

Encoding:

The content of the W register is loaded

into the OPTION register.

Description:

0011

01df

ffff

The contents of register ’f’ are rotated

one bit to the left through the Carry

Flag. If ’d’ is 0 the result is placed in the

W register. If ’d’ is 1 the result is stored

back in register ’f’.

Description:

Words:

Cycles:

Example

1

OPTION

Before Instruction

register ’f’

C

W

=

0x07

After Instruction

OPTION

Words:

1

=

Cycles:

Example:

1

RLF

REG1,0

RETLW

Return with Literal in W

Before Instruction

Syntax:

[ label ] RETLW

k

REG1

C

=

1110 0110

0

Operands:

Operation:

0 ≤ k ≤ 255

After Instruction

k → (W);

TOS → PC

REG1

W

C

=

1110 0110

1100 1100

1

Status Affected: None

1000

kkkk

Encoding:

The W register is loaded with the eight

bit literal ’k’. The program counter is

loaded from the top of the stack (the

return address). This is a two cycle

instruction.

Description:

RRF

Rotate Right f through Carry

[ label ] RRF f,d

0 ≤ f ≤ 31

Syntax:

Operands:

d

[0,1]

Words:

1

2

Operation:

See description below

C

Cycles:

Example:

Status Affected:

Encoding:

CALL TABLE ;W contains

;table offset

;value.

0011

00df

ffff

The contents of register ’f’ are rotated

one bit to the right through the Carry

Flag. If ’d’ is 0 the result is placed in the

W register. If ’d’ is 1 the result is placed

back in register ’f’.

Description:

•

;W now has table

;value.

•

TABLE

ADDWF PC

;W = offset

RETLW k1

RETLW k2

;Begin table

;

register ’f’

C

•

Words:

1

•

Cycles:

Example:

1

RETLW kn

; End of table

RRF

REG1,0

Before Instruction

W

=

0x07

Before Instruction

REG1

C

=

1110 0110

0

After Instruction

value of k8

W

=

After Instruction

REG1

W

C

=

1110 0110

0111 0011

0

1999 Microchip Technology Inc.

DS40139E-page 55

PIC12C5XX

SLEEP

Enter SLEEP Mode

SUBWF

Subtract W from f

Syntax:

[label]

None

[label] SUBWF f,d

SLEEP

Operands:

0 ≤ f ≤ 31

Operands:

Operation:

d

[0,1]

00h → WDT;

0 → WDT prescaler;

1 → TO;

Operation:

(f) – (W) → (dest)

Status Affected: C, DC, Z

0 → PD

0000

10df

ffff

Encoding:

Status Affected: TO, PD, GPWUF

Subtract (2’s complement method) the

W register from register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is

1 the result is stored back in register 'f'.

Description:

0000

0011

Encoding:

Time-out status bit (TO) is set. The

power down status bit (PD) is cleared.

Description:

Words:

1

GPWUF is unaffected.

The WDT and its prescaler are

cleared.

Cycles:

SUBWF

REG1, 1

Example 1:

The processor is put into SLEEP mode

with the oscillator stopped. See sec-

tion on SLEEP for more details.

Before Instruction

REG1

W

C

=

3

2

?

Words:

1

Cycles:

Example:

1

After Instruction

SLEEP

REG1

=

1

2

1

W

C

; result is positive

Example 2:

Before Instruction

REG1

W

C

=

2

?

After Instruction

REG1

W

C

=

0

2

1

; result is zero

Example 3:

Before Instruction

REG1

W

C

=

1

2

?

After Instruction

REG1

W

C

=

FF

2

0

; result is negative

DS40139E-page 56

1999 Microchip Technology Inc.

PIC12C5XX

SWAPF

Syntax:

Swap Nibbles in f

[ label ] SWAPF f,d

0 ≤ f ≤ 31

XORLW

Exclusive OR literal with W

Syntax:

[label] XORLW

k

Operands:

0 ≤ k ≤ 255

d

[0,1]

Operation:

(W) .XOR. k → (W)

Operation:

(f<3:0>) → (dest<7:4>);

(f<7:4>) → (dest<3:0>)

Status Affected:

Encoding:

Z

1111

kkkk

Status Affected: None

The contents of the W register are

XOR’ed with the eight bit literal 'k'. The

result is placed in the W register.

Description:

0011

10df

ffff

Encoding:

The upper and lower nibbles of register

’f’ are exchanged. If ’d’ is 0 the result is

placed in W register. If ’d’ is 1 the result

is placed in register ’f’.

Description:

Words:

1

Cycles:

Example:

1

Words:

Cycles:

Example

1

XORLW 0xAF

Before Instruction

0xB5

W

=

SWAPF

REG1,

0

After Instruction

Before Instruction

REG1

W

=

0x1A

=

0xA5

After Instruction

REG1

W

=

0xA5

0X5A

XORWF

Exclusive OR W with f

[ label ] XORWF f,d

0 ≤ f ≤ 31

Syntax:

Operands:

TRIS

Load TRIS Register

d

[0,1]

Syntax:

[ label ] TRIS

f = 6

f

Operation:

(W) .XOR. (f) → (dest)

Operands:

Operation:

Status Affected:

Encoding:

Z

(W) → TRIS register f

0001

10df

ffff

Status Affected: None

Exclusive OR the contents of the W

register with register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is

1 the result is stored back in register 'f'.

Description:

0000

0fff

Encoding:

TRIS register ’f’ (f = 6) is loaded with the

contents of the W register

Description:

Words:

Cycles:

Example

1

Words:

Cycles:

Example

1

TRIS

GPIO

REG,1

XORWF

Before Instruction

W

=

0XA5

REG

=

0xAF

0xB5

W

=

After Instruction

TRIS

=

After Instruction

REG

W

=

0x1A

0xB5

Note: f = 6 for PIC12C5XX only.

1999 Microchip Technology Inc.

DS40139E-page 57

PIC12C5XX

NOTES:

DS40139E-page 58

1999 Microchip Technology Inc.

PIC12C5XX

10.3

ICEPIC: Low-Cost PICmicro

In-Circuit Emulator

10.0 DEVELOPMENT SUPPORT

10.1

Development Tools

ICEPIC is a low-cost in-circuit emulator solution for the

Microchip PIC12CXXX, PIC16C5X and PIC16CXXX

families of 8-bit OTP microcontrollers.

The PICmicro microcontrollers are supported with a

full range of hardware and software development tools:

• MPLAB™-ICE Real-Time In-Circuit Emulator

ICEPIC is designed to operate on PC-compatible

machines ranging from 386 through Pentium based

machines under Windows 3.x, Windows 95, or Win-

dows NT environment. ICEPIC features real time, non-

intrusive emulation.

• ICEPIC Low-Cost PIC16C5X and PIC16CXXX

In-Circuit Emulator

• PRO MATE II Universal Programmer

• PICSTART Plus Entry-Level Prototype

Programmer

10.4

PRO MATE II: Universal Programmer

• SIMICE

The PRO MATE II Universal Programmer is a full-fea-

tured programmer capable of operating in stand-alone

mode as well as PC-hosted mode. PRO MATE II is CE

compliant.

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• PICDEM-3 Low-Cost Demonstration Board

• MPASM Assembler

The PRO MATE II has programmable VDD and VPP

supplies which allows it to verify programmed memory

at VDD min and VDD max for maximum reliability. It has

an LCD display for displaying error messages, keys to

enter commands and a modular detachable socket

assembly to support various package types. In stand-

alone mode the PRO MATE II can read, verify or pro-

• MPLAB SIM Software Simulator

• MPLAB-C17 (C Compiler)

• Fuzzy Logic Development System

(fuzzyTECH −MP)

®

• KEELOQ Evaluation Kits and Programmer

10.2

MPLAB-ICE: High Performance

Universal In-Circuit Emulator with

MPLAB IDE

gram

PIC12CXXX,

PIC14C000,

PIC16C5X,

PIC16CXXX and PIC17CXX devices. It can also set

configuration and code-protect bits in this mode.

10.5

PICSTART Plus Entry Level

Development System

The MPLAB-ICE Universal In-Circuit Emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for

PICmicro microcontrollers (MCUs). MPLAB-ICE is

supplied with the MPLAB Integrated Development

Environment (IDE), which allows editing, “make” and

download, and source debugging from a single envi-

ronment.

The PICSTART programmer is an easy-to-use, low-

cost prototype programmer. It connects to the PC via

one of the COM (RS-232) ports. MPLAB Integrated

Development Environment software makes using the

programmer simple and efficient. PICSTART Plus is not

recommended for production programming.

Interchangeable processor modules allow the system

to be easily reconfigured for emulation of different pro-

cessors. The universal architecture of the MPLAB-ICE

allows expansion to support all new Microchip micro-

controllers.

PICSTART Plus supports all PIC12CXXX, PIC14C000,

PIC16C5X, PIC16CXXX and PIC17CXX devices with

up to 40 pins. Larger pin count devices such as the

PIC16C923, PIC16C924 and PIC17C756 may be sup-

ported with an adapter socket. PICSTART Plus is CE

compliant.

The MPLAB-ICE Emulator System has been designed

as a real-time emulation system with advanced fea-

tures that are generally found on more expensive devel-

opment tools. The PC compatible 386 (and higher)

machine platform and Microsoft Windows 3.x or

Windows 95 environment were chosen to best make

these features available to you, the end user.

MPLAB-ICE

is

available

in

two

versions.

MPLAB-ICE 1000 is a basic, low-cost emulator system

with simple trace capabilities. It shares processor mod-

ules with the MPLAB-ICE 2000. This is a full-featured

emulator system with enhanced trace, trigger, and data

monitoring features. Both systems will operate across

the entire operating speed range of the PICmicro

MCU.

1999 Microchip Technology Inc.

DS40139E-page 59

PIC12C5XX

10.6

SIMICE Entry-Level Hardware

Simulator

10.8

PICDEM-2 Low-Cost PIC16CXX

Demonstration Board

SIMICE is an entry-level hardware development sys-

tem designed to operate in a PC-based environment

with Microchip’s simulator MPLAB™-SIM. Both SIM-

ICE and MPLAB-SIM run under Microchip Technol-

ogy’s MPLAB Integrated Development Environment

(IDE) software. Specifically, SIMICE provides hardware

simulation for Microchip’s PIC12C5XX, PIC12CE5XX,

and PIC16C5X families of PICmicro 8-bit microcon-

trollers. SIMICE works in conjunction with MPLAB-SIM

to provide non-real-time I/O port emulation. SIMICE

enables a developer to run simulator code for driving

the target system. In addition, the target system can

provide input to the simulator code. This capability

allows for simple and interactive debugging without

having to manually generate MPLAB-SIM stimulus

files. SIMICE is a valuable debugging tool for entry-

level system development.

The PICDEM-2 is a simple demonstration board that

supports the PIC16C62, PIC16C64, PIC16C65,

PIC16C73 and PIC16C74 microcontrollers. All the

necessary hardware and software is included to

run the basic demonstration programs. The user

can program the sample microcontrollers provided

with the PICDEM-2 board, on a PRO MATE II pro-

grammer or PICSTART-Plus, and easily test firmware.

The MPLAB-ICE emulator may also be used with the

PICDEM-2 board to test firmware. Additional prototype

area has been provided to the user for adding addi-

tional hardware and connecting it to the microcontroller

socket(s). Some of the features include a RS-232 inter-

face, push-button switches, a potentiometer for simu-

lated analog input, a Serial EEPROM to demonstrate

2

usage of the I C bus and separate headers for connec-

tion to an LCD module and a keypad.

10.7

PICDEM-1 Low-Cost PICmicro

Demonstration Board

10.9

PICDEM-3 Low-Cost PIC16CXXX

Demonstration Board

The PICDEM-1 is a simple board which demonstrates

the capabilities of several of Microchip’s microcontrol-

lers. The microcontrollers supported are: PIC16C5X

(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,

PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and

PIC17C44. All necessary hardware and software is

included to run basic demo programs. The users can

program the sample microcontrollers provided with

The PICDEM-3 is a simple demonstration board that

supports the PIC16C923 and PIC16C924 in the PLCC

package. It will also support future 44-pin PLCC

microcontrollers with a LCD Module. All the neces-

sary hardware and software is included to run the

basic demonstration programs. The user can pro-

gram the sample microcontrollers provided with

the PICDEM-3 board, on a PRO MATE II program-

mer or PICSTART Plus with an adapter socket, and

easily test firmware. The MPLAB-ICE emulator may

also be used with the PICDEM-3 board to test firm-

ware. Additional prototype area has been provided to

the user for adding hardware and connecting it to the

microcontroller socket(s). Some of the features include

an RS-232 interface, push-button switches, a potenti-

ometer for simulated analog input, a thermistor and

separate headers for connection to an external LCD

module and a keypad. Also provided on the PICDEM-3

board is an LCD panel, with 4 commons and 12 seg-

ments, that is capable of displaying time, temperature

and day of the week. The PICDEM-3 provides an addi-

tional RS-232 interface and Windows 3.1 software for

showing the demultiplexed LCD signals on a PC. A sim-

ple serial interface allows the user to construct a hard-

ware demultiplexer for the LCD signals.

the PICDEM-1 board, on

a PRO MATE II or

PICSTART-Plus programmer, and easily test firm-

ware. The user can also connect the PICDEM-1

board to the MPLAB-ICE emulator and download the

firmware to the emulator for testing. Additional proto-

type area is available for the user to build some addi-

tional hardware and connect it to the microcontroller

socket(s). Some of the features include an RS-232

interface, a potentiometer for simulated analog input,

push-button switches and eight LEDs connected to

PORTB.

DS40139E-page 60

1999 Microchip Technology Inc.

PIC12C5XX

10.10 MPLAB Integrated Development

Environment Software

10.12 Software Simulator (MPLAB-SIM)

The MPLAB-SIM Software Simulator allows code

development in a PC host environment. It allows the

user to simulate the PICmicro series microcontrollers

on an instruction level. On any given instruction, the

user may examine or modify any of the data areas or

provide external stimulus to any of the pins. The input/

output radix can be set by the user and the execution

can be performed in; single step, execute until break, or

in a trace mode.

The MPLAB IDE Software brings an ease of software

development previously unseen in the 8-bit microcon-

troller market. MPLAB is a windows based application

which contains:

• A full featured editor

• Three operating modes

- editor

- emulator

MPLAB-SIM fully supports symbolic debugging using

MPLAB-C17 and MPASM. The Software Simulator

offers the low cost flexibility to develop and debug code

outside of the laboratory environment making it an

excellent multi-project software development tool.

- simulator

• A project manager

• Customizable tool bar and key mapping

• A status bar with project information

• Extensive on-line help

MPLAB allows you to:

10.13 MPLAB-C17 Compiler

• Edit your source files (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PICmicro tools (automatically updates all

project information)

• Debug using:

- source files

The MPLAB-C17 Code Development System is a

complete ANSI ‘C’ compiler and integrated develop-

ment environment for Microchip’s PIC17CXXX family of

microcontrollers. The compiler provides powerful inte-

gration capabilities and ease of use not found with

other compilers.

- absolute listing file

For easier source level debugging, the compiler pro-

vides symbol information that is compatible with the

MPLAB IDE memory display.

The ability to use MPLAB with Microchip’s simulator

allows a consistent platform and the ability to easily

switch from the low cost simulator to the full featured

emulator with minimal retraining due to development

tools.

10.14 Fuzzy Logic Development System

(fuzzyTECH-MP)

10.11 Assembler (MPASM)

fuzzyTECH-MP fuzzy logic development tool is avail-

able in two versions - a low cost introductory version,

MP Explorer, for designers to gain a comprehensive

working knowledge of fuzzy logic system design; and a

full-featured version, fuzzyTECH-MP, Edition for imple-

menting more complex systems.

The MPASM Universal Macro Assembler is a PC-

hosted symbolic assembler. It supports all microcon-

troller series including the PIC12C5XX, PIC14000,

PIC16C5X, PIC16CXXX, and PIC17CXX families.

MPASM offers full featured Macro capabilities, condi-

tional assembly, and several source and listing formats.

It generates various object code formats to support

Microchip's development tools as well as third party

programmers.

Both versions include Microchip’s fuzzyLAB demon-

stration board for hands-on experience with fuzzy logic

systems implementation.

10.15 SEEVAL Evaluation and

Programming System

MPASM allows full symbolic debugging from MPLAB-

ICE, Microchip’s Universal Emulator System.

The SEEVAL SEEPROM Designer’s Kit supports all

Microchip 2-wire and 3-wire Serial EEPROMs. The kit

includes everything necessary to read, write, erase or

program special features of any Microchip SEEPROM

product including Smart Serials and secure serials.

The Total Endurance Disk is included to aid in trade-

off analysis and reliability calculations. The total kit can

significantly reduce time-to-market and result in an

optimized system.

MPASM has the following features to assist in develop-

ing software for specific use applications.

• Provides translation of Assembler source code to

object code for all Microchip microcontrollers.

• Macro assembly capability.

• Produces all the files (Object, Listing, Symbol, and

special) required for symbolic debug with

Microchip’s emulator systems.

• Supports Hex (default), Decimal and Octal source

and listing formats.

MPASM provides a rich directive language to support

programming of the PICmicro . Directives are helpful

in making the development of your assemble source

code shorter and more maintainable.

1999 Microchip Technology Inc.

DS40139E-page 61

PIC12C5XX

10.16 KEELOQ Evaluation and

Programming Tools

KEELOQ evaluation and programming tools support

Microchips HCS Secure Data Products. The HCS eval-

uation kit includes an LCD display to show changing

codes, a decoder to decode transmissions, and a pro-

gramming interface to program test transmitters.

DS40139E-page 62

1999 Microchip Technology Inc.

PIC12C5XX

TABLE 10-1: DEVELOPMENT TOOLS FROM MICROCHIP

y

z

u

f

t s u c o r d o r a l P t u m E

o l s e T a o r f t o w S

s e r m a m r g o P r

d s a r B o m e o D

1999 Microchip Technology Inc.

DS40139E-page 63

PIC12C5XX

NOTES:

DS40139E-page 64

1999 Microchip Technology Inc.

PIC12C5XX

11.0 ELECTRICAL CHARACTERISTICS - PIC12C508/PIC12C509

Absolute Maximum Ratings†

Ambient Temperature under bias........................................................................................................... –40°C to +125°C

Storage Temperature ............................................................................................................................. –65°C to +150°C

Voltage on VDD with respect to VSS .................................................................................................................0 to +7.5 V

Voltage on MCLR with respect to VSS...............................................................................................................0 to +14 V

Voltage on all other pins with respect to VSS ............................................................................... –0.6 V to (VDD + 0.6 V)

(1)

Total Power Dissipation ....................................................................................................................................700 mW

Max. Current out of VSS pin ..................................................................................................................................200 mA

Max. Current into VDD pin .....................................................................................................................................150 mA

Input Clamp Current, IIK (VI < 0 or VI > VDD).................................................................................................................... ±20 mA

Output Clamp Current, IOK (VO < 0 or VO > VDD)............................................................................................................. ±20 mA

Max. Output Current sunk by any I/O pin................................................................................................................25 mA

Max. Output Current sourced by any I/O pin...........................................................................................................25 mA

Max. Output Current sourced by I/O port (GPIO) .................................................................................................100 mA

Max. Output Current sunk by I/O port (GPIO )......................................................................................................100 mA

Note 1: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)

†

NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

1999 Microchip Technology Inc.

DS40139E-page 65

PIC12C5XX

11.1

DC CHARACTERISTICS:

PIC12C508/509 (Commercial, Industrial, Extended)

Standard Operating Conditions (unless otherwise specified)

DC Characteristics

Power Supply Pins

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Parm

No.

(1)

Characteristic

Sym Min

Max Units

Conditions

Typ

D001 Supply Voltage

VDD

2.5

3.0

5.5

V

FOSC = DC to 4 MHz (Commercial/

Industrial)

FOSC = DC to 4 MHz (Extended)

V

D002 RAM Data Retention

VDR

1.5*

Device in SLEEP mode

(2)

Voltage

D003 VDD Start Voltage to

VPOR

VSS

V

See section on Power-on Reset for details

ensure Power-on Reset

D004 VDD Rise Rate to ensure SVDD 0.05

V/ms See section on Power-on Reset for details

Power-on Reset

*

(3)

Supply Current

(4)

D010

IDD

—

.78

1.1

10

14

2.4

27

mA

µA

XT and EXTRC options

FOSC = 4 MHz, VDD = 5.5V

D010C

D010A

INTRC Option

FOSC = 4 MHz, VDD = 5.5V

LP OPTION, Commercial Temperature

FOSC = 32 kHz, VDD = 3.0V, WDT disabled

LP OPTION, Industrial Temperature

FOSC = 32 kHz, VDD = 3.0V, WDT disabled

LP OPTION, Extended Temperature

FOSC = 32 kHz, VDD = 3.0V, WDT disabled

35

(5)

Power-Down Current

D020

D021

D021B

IPD

—

0.25

2

4

5

18

µA

VDD = 3.0V, Commercial WDT disabled

VDD = 3.0V, Industrial WDT disabled

VDD = 3.0V, Extended WDT disabled

D022

∆IWDT

—

3.75

8

9

14

µA

VDD = 3.0V, Commercial

VDD = 3.0V, Industrial

VDD = 3.0V, Extended

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design

guidance only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as

bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an

impact on the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: IR = VDD/2Rext (mA) with Rext in kOhm.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current

is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or

VSS.

DS40139E-page 66

1999 Microchip Technology Inc.

PIC12C5XX

11.2

DC CHARACTERISTICS:

PIC12C508/509 (Commercial, Industrial, Extended)

Standard Operating Conditions (unless otherwise specified)

Operating temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

DC CHARACTERISTICS

Operating voltage VDD range as described in DC spec Section 11.1 and

Section 11.2.

Param

No.

Characteristic

Sym

Min

Typ† Max Units

Conditions

Input Low Voltage

I/O ports

VIL

-

D030

D031

with TTL buffer

VSS

-

0.8V

V

4.5 < VDD ≤ 5.5V

otherwise

0.15VDD

with Schmitt Trigger buffer

VSS

D032 MCLR, GP2/T0CKI (in EXTRC mode)

D033

(1)

OSC1 (EXTRC)

D033 OSC1 (in XT and LP)

Input High Voltage

I/O ports

VSS

-

0.3VDD

V

Note1

VIH

-

D040

with TTL buffer

VSS

2.0V

0.25VDD+

0.8V

VDD

V

4.5 ≤ VDD ≤ 5.5V

otherwise

D040A

D041

with Schmitt Trigger buffer

0.85VDD

0.7VDD

0.85VDD

50

-

VDD

400

V

For entire VDD range

Note1

D042 MCLR/GP2/T0CKI

D042A OSC1 (XT and LP)

D043 OSC1 (in EXTRC mode)

D070 GPIO weak pull-up current

IPUR

IIL

250

µA VDD = 5V, VPIN = VSS

For VDD ≤5.5V

(2, 3)

Input Leakage Current

D060 I/O ports

-1

0.5

+1

µA Vss ≤ VPIN ≤ VDD,

Pin at hi-impedance

(2)

D061 MCLR, GP2/T0CKI

D063 OSC1

20

130

0.5

250

+5

µA

VPIN = VSS + 0.25V

VPIN = VDD

-3

-

0.5

+3

µA Vss ≤ VPIN ≤ VDD,

XT and LP options

Output Low Voltage

D080 I/O ports/CLKOUT

Output High Voltage

(3)

VOL

-

0.6

-

V

IOL = 8.7 mA, VDD = 4.5V

IOH = -5.4 mA, VDD = 4.5V

D090

VOH VDD - 0.7

I/O ports/CLKOUT

Capacitive Loading Specs on

Output Pins

D100 OSC2 pin

COSC2

CIO

-

15

50

pF In XT and LP modes when

external clock is used to drive

OSC1.

pF

D101 All I/O pins

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that

the PIC12C5XX be driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is defined as coming out of the pin.

1999 Microchip Technology Inc.

DS40139E-page 67

PIC12C5XX

TABLE 11-1: PULL-UP RESISTOR RANGES - PIC12C508/C509

VDD (Volts)

Temperature (°C)

Min

Typ

Max

Units

GP0/GP1

2.5

–40

25

38K

42K

50K

15K

18K

19K

22K

42K

48K

49K

55K

17K

20K

22K

24K

63K

20K

23K

25K

28K

Ω

85

125

–40

25

5.5

85

125

GP3

2.5

5.5

–40

25

285K

343K

368K

431K

247K

288K

306K

351K

346K

414K

457K

504K

292K

341K

371K

407K

417K

532K

593K

360K

437K

448K

500K

Ω

85

125

–40

25

85

125

*

These parameters are characterized but not tested.

DS40139E-page 68

1999 Microchip Technology Inc.

PIC12C5XX

11.3

Timing Parameter Symbology and Load Conditions - PIC12C508/C509

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase subscripts (pp) and their meanings:

pp

T

Time

2

to

mc

osc

os

MCLR

ck

cy

drt

io

CLKOUT

cycle time

device reset timer

I/O port

oscillator

OSC1

t0

T0CKI

wdt

watchdog timer

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (Hi-impedance)

Low

Valid

L

Hi-impedance

FIGURE 11-1: LOAD CONDITIONS - PIC12C508/C509

CL = 50 pF for all pins except OSC2

CL

15 pF for OSC2 in XT or LP

modes when external clock

is used to drive OSC1

VSS

1999 Microchip Technology Inc.

DS40139E-page 69

PIC12C5XX

11.4

Timing Diagrams and Specifications

FIGURE 11-2: EXTERNAL CLOCK TIMING - PIC12C508/C509

Q4

Q3

Q4

4

Q1

Q2

OSC1

1

3

4

2

TABLE 11-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC12C508/C509

AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial),

–40°C ≤ TA ≤ +85°C (industrial),

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 11.1

Parameter

Sym

(1)

Characteristic

Min

Max Units

Conditions

Typ

No.

External CLKIN Frequency⁽²⁾

FOSC

DC

—

4

MHz XT osc mode

kHz LP osc mode

DC

200

Oscillator Frequency⁽²⁾

External CLKIN Period⁽²⁾

Oscillator Period⁽²⁾

0.1

DC

250

5

—

4

200

—

MHz XT osc mode

kHz LP osc mode

ns EXTRC osc mode

ns XT osc mode

ms LP osc mode

ns EXTRC osc mode

ns XT osc mode

ms LP osc mode

—

1

TOSC

—

250

5

—

10,000

—

Instruction Cycle Time⁽³⁾

2

3

Tcy

—

4/FOSC

—

TosL, TosH Clock in (OSC1) Low or High Time

TosR, TosF Clock in (OSC1) Rise or Fall Time

These parameters are characterized but not tested.

50*

2*

—

ns XT oscillator

ms LP oscillator

ns XT oscillator

ns LP oscillator

4

—

25*

50*

—

*

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

2: All specified values are based on characterization data for that particular oscillator type under standard oper-

ating conditions with the device executing code. Exceeding these specified limits may result in an unstable

oscillator operation and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruction cycle period (TCY) equals four times the input oscillator time base period.

DS40139E-page 70

1999 Microchip Technology Inc.

PIC12C5XX

TABLE 11-3: CALIBRATED INTERNAL RC FREQUENCIES - PIC12C508/C509

AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial),

–40°C ≤ TA ≤ +85°C (industrial),

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 10.1

Parameter

Sym

(1)

Characteristic

Min*

Max* Units

Conditions

MHz VDD = 5.0V

MHz VDD = 2.5V

Typ

No.

Internal Calibrated RC Frequency

3.58

4.00

4.32

Internal Calibrated RC Frequency

3.50

—

4.26

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

FIGURE 11-3: I/O TIMING - PIC12C508/C509

Q1

Q2

Q3

Q4

OSC1

I/O Pin

(input)

17

18

19

I/O Pin

(output)

New Value

Old Value

20, 21

Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

1999 Microchip Technology Inc.

DS40139E-page 71

PIC12C5XX

TABLE 11-4: TIMING REQUIREMENTS - PIC12C508/C509

AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 11.1

Parameter

(1)

No.

Sym

TosH2ioV

TosH2ioI

Characteristic

Min

—

Typ

Max

100*

—

Units

ns

(3)

—

17

OSC1↑ (Q1 cycle) to Port out valid

OSC1↑ (Q2 cycle) to Port input invalid

TBD

ns

18

(I/O in hold time)

TioV2osH

Port input valid to OSC1↑

TBD

—

ns

19

(I/O in setup time)

(2, 3)

TioR

TioF

—

10

25**

ns

20

21

Port output rise time

(2, 3)

Port output fall time

*

These parameters are characterized but not tested.

** These parameters are design targets and are not tested. No characterization data available at this time.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

2: Measurements are taken in EXTRC mode.

3: See Figure 11-1 for loading conditions.

FIGURE 11-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC12C508/C509

VDD

MCLR

30

Internal

POR

32

DRT

Timeout

(Note 2)

Internal

RESET

Watchdog

Timer

RESET

31

34

I/O pin

(Note 1)

Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.

2: Runs in MCLR or WDT reset only in XT and LP modes.

DS40139E-page 72

1999 Microchip Technology Inc.

PIC12C5XX

TABLE 11-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC12C508/C509

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 11.1

Parameter

No.

(1)

Sym Characteristic

Min Typ

Max Units

Conditions

30

31

TmcL MCLR Pulse Width (low)

2000*

9*

—

ns VDD = 5 V

Twdt Watchdog Timer Time-out Period

(No Prescaler)

18*

30*

ms VDD = 5 V (Commercial)

(2)

32

34

TDRT Device Reset Timer Period

9*

—

18*

—

30*

ms VDD = 5 V (Commercial)

TioZ I/O Hi-impedance from MCLR Low

2000*

ns

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

Note 2: See Table 11-6.

TABLE 11-6: DRT (DEVICE RESET TIMER PERIOD - PIC12C508/C509)

Oscillator Configuration

POR Reset

Subsequent Resets

IntRC & ExtRC

XT & LP

18 ms (typical)

300 µs (typical)

18 ms (typical)

1999 Microchip Technology Inc.

DS40139E-page 73

PIC12C5XX

FIGURE 11-5: TIMER0 CLOCK TIMINGS - PIC12C508/C509

T0CKI

40

41

42

TABLE 11-7: TIMER0 CLOCK REQUIREMENTS - PIC12C508/C509

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 11.1.

Parameter

(1)

Sym Characteristic

Min

Typ

Max Units Conditions

No.

40

Tt0H T0CKI High Pulse Width - No Prescaler

- With Prescaler

0.5 TCY + 20*

10*

—

ns

41

42

Tt0L T0CKI Low Pulse Width - No Prescaler

- With Prescaler

0.5 TCY + 20*

10*

Tt0P T0CKI Period

20 or TCY + 40*

Whichever is greater.

N = Prescale Value

(1, 2, 4,..., 256)

N

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

DS40139E-page 74

1999 Microchip Technology Inc.

PIC12C5XX

12.0 DC AND AC CHARACTERISTICS - PIC12C508/PIC12C509

The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables

the data presented are outside specified operating range (e.g., outside specified VDD range). This is for information

only and devices will operate properly only within the specified range.

The data presented in this section is a statistical summary of data collected on units from different lots over a period of

time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean – 3σ)

respectively, where σ is standard deviation.

FIGURE 12-1: CALIBRATED INTERNAL RC

FREQUENCY RANGE VS.

FIGURE 12-2: CALIBRATED INTERNAL RC

FREQUENCY RANGE VS.

TEMPERATURE (VDD = 2.5V)

TEMPERATURE (VDD = 5.0V)

4.50

4.40

4.50

4.40

4.30

4.20

4.10

4.30

4.20

4.10

Max.

4.00

Max.

4.00

3.90

3.80

3.90

3.80

3.70

Min.

3.70

3.60

3.50

Min.

3.50

-40

25

85

125

-40

25

85

125

Temperature (Deg.C)

1999 Microchip Technology Inc.

DS40139E-page 75

PIC12C5XX

TABLE 12-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C

Oscillator

Frequency

VDD = 2.5V

VDD = 5.5V

External RC

Internal RC

XT

4 MHz

32 KHz

250 µA*

420 µA

251 µA

15 µA

780 µA*

1.1 mA

780 µA

37 µA

LP

*Does not include current through external R&C.

FIGURE 12-3: WDT TIMER TIME-OUT

PERIOD VS. VDD

FIGURE 12-4: SHORT DRT PERIOD VS. VDD

1000

50

45

40

900

800

700

600

35

30

Max +125°C

500

25

Max +85°C

400

20

Typ +25°C

300

Typ +25°C

15

200

10

MIn –40°C

100

2

3

4

5

6

7

5

2

3

4

5

6

7

VDD (Volts)

DS40139E-page 76

1999 Microchip Technology Inc.

PIC12C5XX

FIGURE 12-5: IOH vs. VOH, VDD = 2.5 V

FIGURE 12-7: IOL vs. VOL, VDD = 2.5 V

25

20

15

10

0

-1

-2

Max –40°C

Typ +25°C

-3

-4

Min +85°C

-5

Min +125°C

5

0

-6

-7

500m

1.0

1.5

2.0

2.5

VOH (Volts)

0

250.0m

500.0m

1.0

VOL (Volts)

FIGURE 12-6: IOH vs. VOH, VDD = 5.5 V

FIGURE 12-8: IOL vs. VOL, VDD = 5.5 V

0

50

-5

Max –40°C

40

30

20

10

-10

Typ +25°C

Min +85°C

-15

-20

Min +125°C

-25

-30

3.5

4.0

4.5

5.0

5.5

0

VOH (Volts)

250.0m

500.0m

750.0m

1.0

VOL (Volts)

1999 Microchip Technology Inc.

DS40139E-page 77

PIC12C5XX

NOTES:

DS40139E-page 78

1999 Microchip Technology Inc.

PIC12C5XX

13.0 ELECTRICAL CHARACTERISTICS - PIC12C508A/PIC12C509A/

PIC12LC508A/PIC12LC509A/PIC12CR509A/PIC12CE518/PIC12CE519/

PIC12LCE518/PIC12LCE519/PIC12LCR509A

Absolute Maximum Ratings†

Ambient Temperature under bias........................................................................................................... –40°C to +125°C

Storage Temperature ............................................................................................................................. –65°C to +150°C

Voltage on VDD with respect to VSS .................................................................................................................0 to +7.0 V

Voltage on MCLR with respect to VSS...............................................................................................................0 to +14 V

Voltage on all other pins with respect to VSS ............................................................................... –0.3 V to (VDD + 0.3 V)