PIC12CE673-10E/JM [MICROCHIP]
8-Pin, 8-Bit CMOS Microcontroller with A/D Converter; 8引脚， 8位CMOS微控制器与A / D转换器
| 型号： | PIC12CE673-10E/JM |
| 厂家： | 
MICROCHIP |
| 描述： | 8-Pin, 8-Bit CMOS Microcontroller with A/D Converter |
| 文件： | 总129页 (文件大小：1827K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC12C67X
8-Pin, 8-Bit CMOS Microcontroller with A/D Converter
and EEPROM Data Memory
Devices Included in this Data Sheet:
Pin Diagrams:
PDIP, SOIC, Windowed CERDIP
• PIC12C671
• PIC12C672
• PIC12CE673
• PIC12CE674
VDD
1
VSS
8
7
6
5
GP5/OSC1/CLKIN
GP4/OSC2/AN3/
CLKOUT
GP3/MCLR/VPP
GP0/AN0
2
3
GP1/AN1/VREF
GP2/T0CKI/AN2/
INT
4
Note: Throughout this data sheet PIC12C67X
refers to the PIC12C671, PIC12C672,
PIC12CE673 and PIC12CE674.
PIC12CE67X refers to PIC12CE673 and
PIC12CE674.
PDIP, Windowed CERDIP
VSS
VDD
1
2
3
4
8
7
6
5
High-Performance RISC CPU:
GP0/AN0
GP5/OSC1/CLKIN
GP4/OSC2/AN3/
CLKOUT
GP1/AN1/VREF
GP2/T0CKI/AN2/
INT
• Only 35 single word instructions to learn
GP3/MCLR/VPP
• All instructions are single cycle (400 ns) except for
program branches which are two-cycle
• Operating speed: DC - 10 MHz clock input
DC - 400 ns instruction cycle
Special Microcontroller Features:
• In-Circuit Serial Programming (ICSP™)
Memory
• Internal 4 MHz oscillator with programmable calibration
Device
Data
RAM
Data
EEPROM
• Selectable clockout
• Power-on Reset (POR)
Program
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
PIC12C671
PIC12C672
1024 x 14
2048 x 14
128 x 8
128 x 8
128 x 8
128 x 8
—
—
PIC12CE673 1024 x 14
PIC12CE674 2048 x 14
16 x 8
16 x 8
• 14-bit wide instructions
• 8-bit wide data path
• Interrupt capability
• Special function hardware registers
• 8-level deep hardware stack
• Power saving SLEEP mode
• Interrupt-on-pin change (GP0, GP1, GP3)
• Internal pull-ups on I/O pins (GP0, GP1, GP3)
• Internal pull-up on MCLR pin
• Selectable oscillator options:
- INTRC: Precision internal 4 MHz oscillator
- EXTRC: External low-cost RC oscillator
• Direct, indirect and relative addressing modes for
data and instructions
Peripheral Features:
- XT:
- HS:
- LP:
Standard crystal/resonator
High speed crystal/resonator
Power saving, low frequency crystal
• Four-channel, 8-bit A/D converter
• 8-bit real time clock/counter (TMR0) with 8-bit
programmable prescaler
CMOS Technology:
• 1,000,000 erase/write cycle EEPROM data
memory
• EEPROM data retention > 40 years
• Low-power, high-speed CMOS EPROM/EEPROM
technology
• Fully static design
• Wide operating voltage range 2.5V to 5.5V
• Commercial, Industrial and Extended
temperature ranges
• Low power consumption
< 2 mA @ 5V, 4 MHz
15 µA typical @ 3V, 32 kHz
< 1 µA typical standby current
1999 Microchip Technology Inc.
DS30561B-page 1
PIC12C67X
Table of Contents
1.0 General Description ...................................................................................................................................................................... 3
2.0 PIC12C67X Device Varieties ........................................................................................................................................................ 5
3.0 Architectural Overview .................................................................................................................................................................. 7
4.0 Memory Organization.................................................................................................................................................................. 11
5.0 I/O Port........................................................................................................................................................................................ 25
6.0 EEPROM Peripheral Operation .................................................................................................................................................. 33
7.0 Timer0 Module ............................................................................................................................................................................ 39
8.0 Analog-to-Digital Converter (A/D) Module................................................................................................................................... 45
9.0 Special Features of the CPU....................................................................................................................................................... 53
10.0 Instruction Set Summary............................................................................................................................................................. 69
11.0 Development Support ................................................................................................................................................................. 83
12.0 Electrical Specifications .............................................................................................................................................................. 89
13.0 DC and AC Characteristics....................................................................................................................................................... 109
14.0 Packaging Information .............................................................................................................................................................. 115
Appendix A:Compatibility ................................................................................................................................................................... 119
Appendix B:Code for Accessing EEPROM Data Memory ................................................................................................................. 119
Index .................................................................................................................................................................................................. 121
On-Line Support................................................................................................................................................................................. 125
Reader Response .............................................................................................................................................................................. 126
PIC12C67X Product Identification System ........................................................................................................................................ 127
To Our Valued Customers
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Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revi-
sion of silicon and revision of document to which it applies.
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Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure
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DS30561B-page 2
1999 Microchip Technology Inc.
PIC12C67X
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software
lock-up.
1.0
GENERAL DESCRIPTION
The PIC12C67X devices are low-cost, high-perfor-
mance, CMOS, fully-static, 8-bit microcontrollers with
integrated analog-to-digital (A/D) converter and
EEPROM data memory (EEPROM on PIC12CE67X
versions only).
A UV erasable windowed package version is ideal for
code development, while the cost-effective One-Time-
Programmable (OTP) version is suitable for production
in any volume. The customer can take full advantage of
Microchip’s price leadership in OTP microcontrollers,
while benefiting from the OTP’s flexibility.
All PICmicro® microcontrollers employ an advanced
RISC architecture. The PIC12C67X microcontrollers
have enhanced core features, eight-level deep stack,
and multiple internal and external interrupt sources.
The separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two stage instruction
pipeline allows all instructions to execute in a single
cycle, except for program branches, which require two
cycles. A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set gives
some of the architectural innovations used to achieve a
very high performance.
1.1
Applications
The PIC12C67X series fits perfectly in applications
ranging from personal care appliances and security
systems to low-power remote transmitters/receivers.
The EPROM technology makes customizing applica-
tion programs (transmitter codes, appliance settings,
receiver frequencies, etc.) extremely fast and conve-
nient, while the EEPROM data memory (PIC12CE67X
only) technology allows for the changing of calibration
factors and security codes. The small footprint pack-
ages, for through hole or surface mounting, make this
microcontroller series perfect for applications with
space limitations. Low-cost, low-power, high perfor-
mance, ease of use and I/O flexibility make the
PIC12C67X series very versatile even in areas where
no microcontroller use has been considered before
(i.e., timer functions, replacement of "glue" logic and
PLD’s in larger systems, coprocessor applications).
PIC12C67X microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
The PIC12C67X devices have 128 bytes of RAM, 16
bytes of EEPROM data memory (PIC12CE67X only), 5
I/O pins and 1 input pin. In addition a timer/counter is
available. Also a 4-channel, high-speed, 8-bit A/D is
provided. The 8-bit resolution is ideally suited for appli-
cations requiring low-cost analog interface, (i.e.,
thermostat control, pressure sensing, etc.)
1.2
Family and Upward Compatibility
The PIC12C67X products are compatible with other
members of the 14-bit PIC16CXXX families.
The PIC12C67X devices have special features to
reduce external components, thus reducing cost,
enhancing system reliability and reducing power con-
sumption. The Power-On Reset (POR), Power-up
Timer (PWRT), and Oscillator Start-up Timer (OST)
eliminate the need for external reset circuitry. There are
five oscillator configurations to choose from, including
INTRC precision internal oscillator mode and the
power-saving LP (Low Power) oscillator mode. Power-
saving SLEEP mode, Watchdog Timer and code
protection features improve system cost, power and
reliability. The SLEEP (power-down) feature provides a
power-saving mode. The user can wake-up the chip
from SLEEP through several external and internal
interrupts and resets.
1.3
Development Support
The PIC12C67X devices are supported by a full-
featured macro assembler, a software simulator, an in-
circuit emulator, a low-cost development programmer
and a full-featured programmer. A “C” compiler and
fuzzy logic support tools are also available.
1999 Microchip Technology Inc.
DS30561B-page 3
PIC12C67X
TABLE 1-1:
PIC12C67X & PIC12CE67X FAMILY OF DEVICES
PIC12C671 PIC12LC671 PIC12C672 PIC12LC672 PIC12CE673 PIC12LCE673 PIC12CE674 PIC12LCE674
Maximum
10
10
10
10
10
10
10
10
Frequency
of Operation
(MHz)
Clock
EPROM
Program
Memory
1024 x 14
128
1024 x 14
128
2048 x 14
128
2048 x 14
128
1024 x 14
128
1024 x 14
128
2048 x 14
128
2048 x 14
128
Memory
RAM Data
Memory
(bytes)
EEPROM
Data Memory
(bytes)
—
—
—
—
16
16
16
16
Timer
Module(s)
TMR0
4
TMR0
4
TMR0
4
TMR0
4
TMR0
4
TMR0
4
TMR0
4
TMR0
4
Peripherals
A/D Con-
verter (8-bit)
Channels
Wake-up
from SLEEP
on pin
Yes
4
Yes
4
Yes
4
Yes
4
Yes
4
Yes
4
Yes
4
Yes
4
change
Interrupt
Sources
I/O Pins
5
5
5
5
5
5
5
5
Features
Input Pins
1
1
1
1
1
1
1
1
Internal
Pull-ups
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
In-Circuit
Serial
Programming
Yes
35
Yes
35
Yes
35
Yes
35
Yes
35
Yes
35
Yes
35
Yes
35
Number of
Instructions
Voltage
3.0V - 5.5V 2.5V - 5.5V
3.0V - 5.5V 2.5V - 5.5V
3.0V - 5.5V 2.5V - 5.5V
3.0V - 5.5V 2.5V - 5.5V
Range (Volts)
Packages
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW
8-pin DIP,
JW
8-pin DIP,
JW
8-pin DIP,
JW
All PIC12C67X devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
All PIC12C67X devices use serial programming with data pin GP0 and clock pin GP1.
DS30561B-page 4
1999 Microchip Technology Inc.
PIC12C67X
2.3
Quick-Turn-Programming (QTP)
Devices
2.0
PIC12C67X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC12C67X Product Iden-
tification System section at the end of this data sheet.
When placing orders, please use that page of the data
sheet to specify the correct part number.
Microchip offers a QTP Programming Service for fac-
tory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabi-
lized. The devices are identical to the OTP devices, but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before produc-
tion shipments are available. Please contact your local
Microchip Technology sales office for more details.
For example, the PIC12C67X device “type” is indicated
in the device number:
1. C, as in PIC12C671. These devices have
EPROM type memory and operate over the
standard voltage range.
2.4
Serialized Quick-Turn Programming
(SQTPSM) Devices
2. LC, as in PIC12LC671. These devices have
EPROM type memory and operate over an
extended voltage range.
Microchip offers a unique programming service where
a few user-defined locations in each device are pro-
grammed with different serial numbers. The serial num-
bers may be random, pseudo-random, or sequential.
3. CE, as in PIC12CE674. These devices have
EPROM type memory, EEPROM data memory
and operate over the standard voltage range.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password, or ID number.
4. LCE, as in PIC12LCE674. These devices have
EPROM type memory, EEPROM data memory
and operate over an extended voltage range.
2.1
UV Erasable Devices
The UV erasable version, offered in windowed pack-
age, is optimal for prototype development and pilot pro-
grams.
The UV erasable version can be erased and repro-
grammed to any of the configuration modes.
Microchip's PICSTART Plus and PRO MATE pro-
grammers both support the PIC12C67X. Third party
programmers also are available; refer to the Microchip
Third Party Guide for a list of sources.
Note: Please note that erasing the device will
also erase the pre-programmed internal
calibration value for the internal oscillator.
The calibration value must be saved prior
to erasing the part.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications.
The OTP devices, packaged in plastic packages, per-
mit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
1999 Microchip Technology Inc.
DS30561B-page 5
PIC12C67X
NOTES:
DS30561B-page 6
1999 Microchip Technology Inc.
PIC12C67X
The PIC12C67X can directly or indirectly address its
register files or data memory. All special function regis-
ters, including the program counter, are mapped in the
data memory. The PIC12C67X has an orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC12C67X simple yet efficient. In addition, the learn-
ing curve is reduced significantly.
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC12C67X family can be
attributed to a number of architectural features com-
monly found in RISC microprocessors. To begin with,
the PIC12C67X uses a Harvard architecture, in which
program and data are accessed from separate memo-
ries using separate buses. This improves bandwidth
over traditional von Neumann architecture in which pro-
gram and data are fetched from the same memory
using the same bus. Separating program and data
buses also allow instructions to be sized differently than
the 8-bit wide data word. Instruction opcodes are 14-
bits wide making it possible to have all single word
instructions. A 14-bit wide program memory access
bus fetches a 14-bit instruction in a single instruction
cycle. A two-stage pipeline overlaps fetch and execu-
tion of instructions (Example 3-1). Consequently, all
instructions (35) execute in a single cycle (400 ns @ 10
MHz) except for program branches.
PIC12C67X devices contain an 8-bit ALU and working
register. The ALU is a general purpose arithmetic unit.
It performs arithmetic and Boolean functions between
the data in the working register and any register file.
The ALU is 8-bits wide and capable of addition, sub-
traction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two's comple-
ment in nature. In two-operand instructions, typically
one operand is the working register (W register). The
other operand is a file register or an immediate con-
stant. In single operand instructions, the operand is
either the W register or a file register.
The table below lists program memory (EPROM), data
memory (RAM), and non-volatile memory (EEPROM)
for each PIC12C67X device.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
EEPROM
Data
Memory
Program RAM Data
Device
Memory
Memory
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow bit and a digit borrow out bit,
respectively, in subtraction. See the SUBLWand SUBWF
instructions for examples.
PIC12C671
PIC12C672
PIC12CE673
PIC12CE674
1K x 14
2K x 14
1K x 14
2K x 14
128 x 8
128 x 8
128 x 8
128 x 8
—
—
16x8
16x8
1999 Microchip Technology Inc.
DS30561B-page 7
PIC12C67X
FIGURE 3-1: PIC12C67X BLOCK DIAGRAM
Device
Program Memory
Data Memory (RAM)
Non-Volatile Memory (EEPROM)
PIC12C671
PIC12C672
PIC12CE673
PIC12CE674
1K x 14
2K x 14
1K x 14
2K x 14
128 x 8
128 x 8
128 x 8
128 x 8
—
—
16 x 8
16 x 8
13
8
GPIO
Data Bus
Program Counter
GP0/AN0
GP1/AN1/VREF
GP2/T0CKI/AN2/INT
GP3/MCLR/VPP
GP4/OSC2/AN3/CLKOUT
EPROM
Program
Memory
RAM
8 Level Stack
(13 bit)
128 bytes
File
Registers
GP5/OSC1/CLKIN
Program
Bus
14
RAM Addr (1)
9
Addr MUX
Instruction reg
Indirect
Addr
7
Direct Addr
8
16x8
EEPROM
Data
FSR reg
PIC12CE673
PIC12CE674
Memory
STATUS reg
8
3
MUX
Power-up
Timer
Instruction
Decode &
Control
Oscillator
Start-up Timer
ALU
Watchdog
Timer
8
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
Power-on
Reset
W reg
Internal
4 MHz Clock
Timer0
MCLR
VDD, VSS
A/D
Note 1: Higher order bits are from the STATUS Register.
DS30561B-page 8
1999 Microchip Technology Inc.
PIC12C67X
TABLE 3-1:
Name
PIC12C67X PINOUT DESCRIPTION
I/O/P Buffer
DIP Pin #
Description
Type
Type
GP0/AN0
7
6
I/O
TTL/ST Bi-directional I/O port/serial programming data/analog input 0.
Can be software programmed for internal weak pull-up and
interrupt-on-pin change. This buffer is a Schmitt Trigger input
when used in serial programming mode.
GP1/AN1/VREF
I/O
TTL/ST Bi-directional I/O port/serial programming clock/analog input 1/
voltage reference. Can be software programmed for internal
weak pull-up and interrupt-on-pin change. This buffer is a
Schmitt Trigger input when used in serial programming mode.
GP2/T0CKI/AN2/INT
GP3/MCLR/VPP
5
4
I/O
I
ST
Bi-directional I/O port/analog input 2. Can be configured as
T0CKI or external interrupt.
TTL/ST Input port/master clear (reset) input/programming voltage
input. When configured as MCLR, this pin is an active low
reset to the device. Voltage on MCLR/VPP must not exceed
VDD during normal device operation. Can be software pro-
grammed for internal weak pull-up and interrupt-on-pin
change. Weak pull-up always on if configured as MCLR . This
buffer is Schmitt Trigger when in MCLR mode.
GP4/OSC2/AN3/CLKOUT
GP5/OSC1/CLKIN
3
2
I/O
I/O
TTL
Bi-directional I/O port/oscillator crystal output/analog input 3.
Connections to crystal or resonator in crystal oscillator mode
(HS, XT and LP modes only, GPIO in other modes). In EXTRC
and INTRC modes, the pin output can be configured to CLK-
OUT, which has 1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
TTL/ST Bi-directional IO port/oscillator crystal input/external clock
source input (GPIO in INTRC mode only, OSC1 in all other
oscillator modes). Schmitt trigger input for EXTRC oscillator
mode.
VDD
1
P
—
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
VSS
8
P
Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input,
ST = Schmitt Trigger input.
1999 Microchip Technology Inc.
DS30561B-page 9
PIC12C67X
3.1
Clocking Scheme/Instruction Cycle
3.2
Instruction Flow/Pipelining
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, and the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 3-2.
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute
are pipelined such that fetch takes one instruction
cycle, while decode and execute takes another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the program counter to change
(i.e., GOTO), then two cycles are required to complete
the instruction (Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is
latched into the “Instruction Register" (IR) in cycle
Q1. This instruction is then decoded and executed
during the Q2, Q3, and Q4 cycles. Data memory is
read during Q2 (operand read) and written during Q4
(destination write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
PC
PC+1
PC+2
OSC2/CLKOUT
(EXTRC and
INTRC modes)
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
2. MOVWF GPIO
3. CALL SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
GPIO, BIT3 (Forced NOP)
Flush
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetched
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS30561B-page 10
1999 Microchip Technology Inc.
PIC12C67X
4.2
Data Memory Organization
4.0
MEMORY ORGANIZATION
The data memory is partitioned into two banks, which
contain the General Purpose Registers and the Special
Function Registers. Bit RP0 is the bank select bit.
4.1
Program Memory Organization
The PIC12C67X has a 13-bit program counter capable
of addressing an 8K x 14 program memory space.
RP0 (STATUS<5>) = 1 → Bank 1
RP0 (STATUS<5>) = 0 → Bank 0
For the PIC12C671 and the PIC12CE673, the first 1K x
14 (0000h-03FFh) is implemented.
Each Bank extends up to 7Fh (128 bytes). The lower
locations of each Bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers implemented as
static RAM. Both Bank 0 and Bank 1 contain Special
Function Registers. Some "high use" Special Function
Registers from Bank 0 are mirrored in Bank 1 for code
reduction and quicker access.
For the PIC12C672 and the PIC12CE674, the first 2K
x 14 (0000h-07FFh) is implemented. Accessing a loca-
tion above the physically implemented address will
cause a wraparound. The reset vector is at 0000h and
the interrupt vector is at 0004h.
FIGURE 4-1: PIC12C67X PROGRAM
MEMORY MAP AND STACK
Also note that F0h through FFh on the PIC12C67X is
mapped into Bank 0 registers 70h-7Fh as common
RAM.
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
4.2.1
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly or indi-
rectly through the File Select Register FSR
(Section 4.5).
Stack Level 1
Stack Level 8
Reset Vector
0000h
Peripheral
Interrupt Vector
0004h
0005h
On-Chip Program
Memory
03FFh
0400h
(PIC12C672 and
PIC12CE674 only)
07FFh
0800h
1FFFh
1999 Microchip Technology Inc.
DS30561B-page 11
PIC12C67X
4.2.2
SPECIAL FUNCTION REGISTERS
FIGURE 4-2: PIC12C67X REGISTER FILE
MAP
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
File
Address
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
INDF(1)
TMR0
PCL
INDF(1)
OPTION
PCL
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
The Special Function Registers can be classified into
two sets (core and peripheral). Those registers associ-
ated with the “core” functions are described in this sec-
tion, and those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
STATUS
FSR
STATUS
FSR
GPIO
TRIS
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
PCON
OSCCAL
ADRES
ADCON0
ADCON1
A0h
General
Purpose
Register
BFh
C0h
General
Purpose
Register
EFh
F0h
70h
7Fh
Mapped
in Bank 0
FFh
Bank 0
Bank 1
Unimplemented data memory locations, read
as ’0’.
Note 1: Not a physical register.
DS30561B-page 12
1999 Microchip Technology Inc.
PIC12C67X
TABLE 4-1:
PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY
Value on
Power-on
Reset
Value on
all other
Resets(3)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0
00h(1)
01h
INDF
TMR0
PCL
STATUS
FSR
GPIO
—
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
11xx xxxx 11uu uuuu
02h(1)
03h(1)
04h(1)
05h
Program Counter's (PC) Least Significant Byte
IRP(4)
RP1(4)
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
SCL(5)
SDA(5)
GP5
GP4
GP3
GP2
GP1
GP0
06h
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
07h
—
08h
—
09h
—
0Ah(1,2) PCLATH
—
—
T0IE
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
0000 000x 0000 000u
-0-- ---- -0-- ----
0Bh(1)
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
INTCON
GIE
—
PEIE
ADIF
INTE
—
GPIE
—
T0IF
—
INTF
—
GPIF
—
PIR1
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
A/D Result Register
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADRES
ADCON0
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
ADCS1
ADCS0
reserved
CHS1
CHS0
GO/DONE reserved
ADON
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC12C67X; always maintain these bits clear.
5: The SCL (GP7) and SDA (GP6) bits are unimplemented on the PIC12C671/672 and read as ’0’.
1999 Microchip Technology Inc.
DS30561B-page 13
PIC12C67X
TABLE 4-1:
PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY (CONT.)
Value on
Power-on
Reset
Value on
all other
Resets(3)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 1
80h(1)
81h
INDF
OPTION
PCL
STATUS
FSR
TRIS
—
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
GPPU
Program Counter’s (PC) Least Significant Byte
IRP(4) RP1(4)
RP0 TO
Indirect data memory address pointer
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
82h(1)
83h(1)
84h(1)
85h
PD
Z
DC
C
—
—
GPIO Data Direction Register
86h
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
87h
—
88h
—
89h
—
8Ah(1,2) PCLATH
—
—
T0IE
—
Write Buffer for the upper 5 bits of the PC
---0 0000 ---0 0000
0000 000x 0000 000u
-0-- ---- -0-- ----
8Bh(1)
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
INTCON
GIE
—
PEIE
ADIE
INTE
—
GPIE
—
T0IF
—
INTF
—
GPIF
—
PIE1
—
Unimplemented
—
—
—
PCON
—
—
—
—
—
POR
—
—
—
---- --0- ---- --u-
0111 00-- uuuu uu--
OSCCAL
CAL3
CAL2
CAL1
CAL0
CALFST
CALSLW
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADCON1
—
—
—
—
PCFG2
PCFG1
PCFG0
---- -000 ---- -000
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC12C67X; always maintain these bits clear.
5: The SCL (GP7) and SDA (GP6) bits are unimplemented on the PIC12C671/672 and read as ’0’.
DS30561B-page 14
1999 Microchip Technology Inc.
PIC12C67X
4.2.2.1
STATUS REGISTER
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS Register, because these instructions do not
affect the Z, C or DC bits from the STATUS Register.
For other instructions, not affecting any status bits, see
the "Instruction Set Summary."
The STATUS Register, shown in Register 4-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS Register can be the destination for any
instruction, as with any other register. If the STATUS
Register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS Register as destination may be different than
intended.
Note 1: Bits IRP and RP1 (STATUS<7:6>) are not
used by the PIC12C67X and should be
maintained clear. Use of these bits as
general purpose R/W bits is NOT recom-
mended, since this may affect upward
compatibility with future products.
2: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS Register
as 000u u1uu(where u= unchanged).
REGISTER 4-1:
STATUS REGISTER (ADDRESS 03h, 83h)
Reserved Reserved R/W-0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
IRP
bit7
RP1
RP0
R
= Readable bit
W = Writable bit
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing)
1= Bank 2, 3 (100h - 1FFh)
0= Bank 0, 1 (00h - FFh)
The IRP bit is reserved; always maintain this bit clear.
bit 6-5: RP<1:0>: Register Bank Select bits (used for direct addressing)
11= Bank 3 (180h - 1FFh)
10= Bank 2 (100h - 17Fh)
01= Bank 1 (80h - FFh)
00= Bank 0 (00h - 7Fh)
Each bank is 128 bytes. The RP1 bit is reserved; always maintain this bit clear.
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions) (for borrow the polarity is reversed)
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1= A carry-out from the most significant bit of the result occurred
0= No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the sec-
ond operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
1999 Microchip Technology Inc.
DS30561B-page 15
PIC12C67X
4.2.2.2
OPTION REGISTER
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer by setting bit PSA
(OPTION<3>).
The OPTION Register is a readable and writable regis-
ter, which contains various control bits to configure the
TMR0/WDT prescaler, the External INT Interrupt,
TMR0 and the weak pull-ups on GPIO.
REGISTER 4-2:
OPTION REGISTER (ADDRESS 81h)
R/W-1
GPPU
R/W-1
INTEDG
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
R
= Readable bit
W = Writable bit
U
bit7
bit0
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
GPPU: Weak Pull-up Enable
1= Weak pull-ups disabled
0= Weak pull-ups enabled (GP0, GP1, GP3)
INTEDG: Interrupt Edge
1= Interrupt on rising edge of GP2/T0CKI/AN2/INT pin
0= Interrupt on falling edge of GP2/T0CKI/AN2/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on GP2/T0CKI/AN2/INT pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on GP2/T0CKI/AN2/INT pin
0= Increment on low-to-high transition on GP2/T0CKI/AN2/INT pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
bit 2-0: PS<2:0>: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
DS30561B-page 16
1999 Microchip Technology Inc.
PIC12C67X
4.2.2.3
INTCON REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
The INTCON Register is a readable and writable regis-
ter, which contains various enable and flag bits for the
TMR0 Register overflow, GPIO port change and exter-
nal GP2/INT pin interrupts.
REGISTER 4-3:
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
GPIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
GPIF
R
= Readable bit
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
GIE: Global Interrupt Enable bit
1= Enables all un-masked interrupts
0= Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1= Enables all un-masked peripheral interrupts
0= Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
INTE: INT External Interrupt Enable bit
1= Enables the external interrupt on GP2/INT/T0CKI/AN2 pin
0= Disables the external interrupt on GP2/INT/T0CKI/AN2 pin
GPIE: GPIO Interrupt on Change Enable bit
1= Enables the GPIO Interrupt on Change
0= Disables the GPIO Interrupt on Change
T0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: INT External Interrupt Flag bit
1= The external interrupt on GP2/INT/T0CKI/AN2 pin occurred (must be cleared in software)
0= The external interrupt on GP2/INT/T0CKI/AN2 pin did not occur
GPIF: GPIO Interrupt on Change Flag bit
1= GP0, GP1 or GP3 pins changed state (must be cleared in software)
0= Neither GP0, GP1 nor GP3 pins have changed state
1999 Microchip Technology Inc.
DS30561B-page 17
PIC12C67X
4.2.2.4
PIE1 REGISTER
Note: Bit PEIE (INTCON<6>) must be set to
This register contains the individual enable bits for the
Peripheral interrupts.
enable any peripheral interrupt.
REGISTER 4-4:
PIE1 REGISTER (ADDRESS 8Ch)
U-0
R/W-0
ADIE
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
R
= Readable bit
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
bit 6:
Unimplemented: Read as ’0’
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
bit 5-0: Unimplemented: Read as ’0’
DS30561B-page 18
1999 Microchip Technology Inc.
PIC12C67X
4.2.2.5
PIR1 REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
This register contains the individual flag bits for the
Peripheral interrupts.
REGISTER 4-5:
PIR1 REGISTER (ADDRESS 0Ch)
U-0
R/W-0
ADIF
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
R
= Readable bit
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
bit 6:
Unimplemented: Read as ’0’
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared in software)
0= The A/D conversion is not complete
bit 5-0: Unimplemented: Read as ’0’
1999 Microchip Technology Inc.
DS30561B-page 19
PIC12C67X
4.2.2.6
PCON REGISTER
The Power Control (PCON) Register contains a flag bit
to allow differentiation between a Power-on Reset
(POR), an external MCLR Reset and a WDT Reset.
REGISTER 4-6:
PCON REGISTER (ADDRESS 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
—
—
—
—
—
—
POR
—
R
= Readable bit
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-2: Unimplemented: Read as ’0’
bit 1:
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
Unimplemented: Read as ’0’
DS30561B-page 20
1999 Microchip Technology Inc.
PIC12C67X
4.2.2.7
OSCCAL REGISTER
The Oscillator Calibration (OSCCAL) Register is used
to calibrate the internal 4 MHz oscillator. It contains four
bits for fine calibration and two other bits to either
increase or decrease frequency.
REGISTER 4-7:
OSCCAL REGISTER (ADDRESS 8Fh)
R/W-0
CAL3
R/W-1
CAL2
R/W-1
CAL1
R/W-1
CAL0
R/W-0
R/W-0
U-0
U-0
CALFST CALSLW
—
—
R
= Readable bit
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-4: CAL<3:0>: Fine Calibration
bit 3:
CALFST: Calibration Fast
1= Increase frequency
0= No change
bit 2:
CALSLW: Calibration Slow
1= Decrease frequency
0= No change
bit 1-0: Unimplemented: Read as ’0’
Note: If CALFST = 1 and CALSLW = 1, CALFST has precedence.
1999 Microchip Technology Inc.
DS30561B-page 21
PIC12C67X
4.3.2
STACK
4.3
PCL and PCLATH
The Program Counter (PC) is 13-bits wide. The low
byte comes from the PCL Register, which is a readable
and writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.
On any reset, the PC is cleared. Figure 4-3 shows the
two situations for the loading of the PC. The upper
example in the figure shows how the PC is loaded on a
write to PCL (PCLATH<4:0> → PCH). The lower exam-
ple in the figure shows how the PC is loaded during a
CALLor GOTOinstruction (PCLATH<4:3> → PCH).
The PIC12C67X family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the stack pointer is
not readable or writable. The PC is PUSHed onto the
stack when a CALLinstruction is executed or an inter-
rupt causes a branch. The stack is POPed in the event
of a RETURN, RETLWor a RETFIEinstruction execu-
tion. PCLATH is not affected by a PUSH or POP oper-
ation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
FIGURE 4-3: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
Instruction with
PCL as
Destination
Note 1: There are no status bits to indicate stack
PC
overflow or stack underflow conditions.
8
PCLATH<4:0>
PCLATH
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW, and RETFIE
instructions, or the vectoring to an inter-
rupt address.
5
ALU result
PCH
12 11 10
PCL
8
7
0
GOTO, CALL
PC
4.4
Program Memory Paging
PCLATH<4:3>
PCLATH
11
The PIC12C67X ignores both paging bits
PCLATH<4:3>, which are used to access program
memory when more than one page is available. The
use of PCLATH<4:3> as general purpose read/write
bits for the PIC12C67X is not recommended since this
may affect upward compatibility with future products.
2
Opcode <10:0>
4.3.1
COMPUTED GOTO
A Computed GOTO is accomplished by adding an off-
set to the program counter (ADDWF PCL). When doing
a table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
DS30561B-page 22
1999 Microchip Technology Inc.
PIC12C67X
4.5
Indirect Addressing, INDF and FSR
Registers
EXAMPLE 4-1: INDIRECT ADDRESSING
movlw 0x20
movwf FSR
;initialize pointer
;to RAM
The INDF Register is not a physical register. Address-
ing the INDF Register will cause indirect addressing.
NEXT
clrf
incf
INDF
;clear INDF register
FSR,F ;inc pointer
Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF Register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF Register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR Register and the IRP bit
(STATUS<7>), as shown in Figure 4-4. However, IRP is
not used in the PIC12C67X.
btfss FSR,4 ;all done?
goto
NEXT
;no clear next
;yes continue
CONTINUE
:
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-1.
FIGURE 4-4: DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
(1)
(1)
from opcode
7
RP1 RP0
6
0
0
IRP
FSR register
bank select
180h
location select
bank select
location select
00
01
10
11
00h
not used
Data
Memory
7Fh
1FFh
Bank 0
Bank 1 Bank 2
Bank 3
For register file map detail see Figure 4-2.
Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.
1999 Microchip Technology Inc.
DS30561B-page 23
PIC12C67X
NOTES:
DS30561B-page 24
1999 Microchip Technology Inc.
PIC12C67X
5.3
I/O Interfacing
5.0
I/O PORT
The equivalent circuit for an I/O port pin is shown in
Figure 5-1 through Figure 5-5. All port pins, except
GP3, which is input only, may be used for both input
and output operations. For input operations, these
ports are non-latching. Any input must be present until
read by an input instruction (i.e., MOVF GPIO,W). The
outputs are latched and remain unchanged until the
output latch is rewritten. To use a port pin as output,
the corresponding direction control bit in TRIS must be
cleared (= 0). For use as an input, the corresponding
TRIS bit must be set. Any I/O pin (except GP3) can be
programmed individually as input or output.
As with any other register, the I/O register can be
written and read under program control. However, read
instructions (i.e., MOVF GPIO,W) always read the I/O
pins independent of the pin’s input/output modes. On
RESET, all I/O ports are defined as input (inputs are at
hi-impedance), since the I/O control registers are all
set.
5.1
GPIO
GPIO is an 8-bit I/O register. Only the low order 6 bits
are used (GP<5:0>). Bits 6 and 7 (SDA and SCL,
respectively) are used by the EEPROM peripheral on
the PIC12CE673/674. Refer to Section 6.0 and
Appendix B for use of SDA and SCL. Please note that
GP3 is an input only pin. The configuration word can
set several I/O’s to alternate functions. When acting as
alternate functions, the pins will read as ‘0’ during port
read. Pins GP0, GP1 and GP3 can be configured with
weak pull-ups and also with interrupt-on-change. The
interrupt on change and weak pull-up functions are not
pin selectable. If pin 4, (GP3), is configured as MCLR,
a weak pull-up is always on. Interrupt-on-change for
this pin is not set and GP3 will read as '0'. Interrupt-on-
change is enabled by setting bit GPIE, INTCON<3>.
Note that external oscillator use overrides the GPIO
functions on GP4 and GP5.
Port pins GP6 (SDA) and GP7 (SCL) are used for the
serial EEPROM interface on the PIC12CE673/674.
These port pins are not available externally on the
package. Users should avoid writing to pins GP6
(SDA) and GP7 (SCL) when not communicating with
the serial EEPROM memory. Please see Section 6.0,
EEPROM Peripheral Operation, for information on
serial EEPROM communication.
Note:
On a Power-on Reset, GP0, GP1, GP2
and GP4 are configured as analog inputs
and read as '0'.
5.2
TRIS Register
This register controls the data direction for GPIO. A '1'
from a TRIS Register bit puts the corresponding output
driver in a hi-impedance mode. A '0' puts the contents
of the output data latch on the selected pins, enabling
the output buffer. The exceptions are GP3, which is
input only and its TRIS bit will always read as '1', while
GP6 and GP7 TRIS bits will read as ’0’.
Note:
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
Upon reset, the TRIS Register is all '1's, making all
pins inputs.
TRIS for pins GP4 and GP5 is forced to a ’1’ where
appropriate. Writes to TRIS <5:4> will have an effect
in EXTRC and INTRC oscillator modes only. When
GP4 is configured as CLKOUT, changes to TRIS<4>
will have no effect.
1999 Microchip Technology Inc.
DS30561B-page 25
PIC12C67X
FIGURE 5-1: BLOCK DIAGRAM OF GP0/AN0 AND GP1/AN1/VREF PIN
GPPU
Data Bus
D
Q
Q
VDD
P
VDD
P
VDD
WR PORT
CK
I/O Pin
Data Latch
N
D
Q
Q
VSS
VSS
WR TRIS
CK
TRIS Latch
Analog
Input
TTL
Input
Buffer
Mode
RD TRIS
Q
D
EN
RD PORT
(1)
(1)
GP0/INT and GP1/INT
To A/D Converter
Note 1: Wake-up on pin change interrupts for GP0 and GP1.
DS30561B-page 26
1999 Microchip Technology Inc.
PIC12C67X
FIGURE 5-2: BLOCK DIAGRAM OF GP2/T0CKI/AN2/INT PIN
Data Bus
D
Q
Q
VDD
P
VDD
WR PORT
CK
I/O Pin
Data Latch
N
D
Q
Q
VSS
VSS
WR TRIS
CK
TRIS Latch
Analog
Input
Mode
Schmitt Trigger
Input Buffer
RD TRIS
Q
D
EN
RD PORT
TMR0 Clock Input
GP2/INT
To A/D Converter
1999 Microchip Technology Inc.
DS30561B-page 27
PIC12C67X
FIGURE 5-3: BLOCK DIAGRAM OF GP3/MCLR/VPP PIN
VDD
GPPU
P
MCLREN
Input Pin
VSS
MCLR
Schmitt Trigger
Input Buffer
Program Mode
HV Detect
TTL Input
Buffer
Data Bus
Q
D
EN
RD PORT
RD TRIS
GP3/INT
VSS
(1)
Note 1: Wake-up on pin change interrupt for GP3.
DS30561B-page 28
1999 Microchip Technology Inc.
PIC12C67X
FIGURE 5-4: BLOCK DIAGRAM OF GP4/OSC2/AN3/CLKOUT PIN
INTRC or EXTRC w/ CLKOUT
CLKOUT (FOSC/4)
1
0
From OSC1 Oscillator
Data Bus
Circuit
D
Q
VDD
VDD
WR PORT
CK
Q
P
I/O Pin
Data Latch
N
VSS
VSS
INTRC/
EXTRC
D
Q
Q
INTRC or EXTRC
w/o CLKOUT
WR TRIS
CK
TRIS Latch
Analog
Input
Mode
TTL
Input Buffer
RD TRIS
Q
D
EN
RD PORT
To A/D Converter
1999 Microchip Technology Inc.
DS30561B-page 29
PIC12C67X
FIGURE 5-5: BLOCK DIAGRAM OF GP5/OSC1/CLKIN PIN
To OSC2
Oscillator
Circuit
Data Bus
D
Q
Q
VDD
VDD
WR PORT
EN
P
Data Latch
I/O Pin
N
D
Q
Q
WR TRIS
VSS
VSS
INTRC
EN
TRIS Latch
INTRC
TTL
Input Buffer
RD TRIS
Q
D
EN
RD PORT
DS30561B-page 30
1999 Microchip Technology Inc.
PIC12C67X
TABLE 5-1:
SUMMARY OF PORT REGISTERS
Value on
Power-on
Reset
Value on
all other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2 Bit 1 Bit 0
85h
81h
03h
05h
TRIS
—
—
GPIO Data Direction Register
--11 1111
1111 1111
0001 1xxx
11xx xxxx
--11 1111
1111 1111
000q quuu
11uu uuuu
OPTION
STATUS
GPIO
GPPU
IRP(1)
INTEDG
RP1(1)
T0CS
RP0
T0SE
TO
PSA
PD
PS2
Z
PS1
DC
PS0
C
(2)
(2)
GP5
GP4
GP3
GP2
GP1 GP0
SCL
SDA
Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0', x= unknown, u= unchanged,
q = see tables in Section 9.4 for possible values.
Note 1: The IRP and RP1 bits are reserved on the PIC12C67X; always maintain these bits clear.
2: The SCL and SDA bits are unimplemented on the PIC12C671 and PIC12C672.
Example 5-1 shows the effect of two sequential read-
modify-write instructions on an I/O port.
5.4
I/O Programming Considerations
5.4.1
BI-DIRECTIONAL I/O PORTS
EXAMPLE 5-1: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
Any instruction which writes, operates internally as a
read followed by a write operation. The BCFand BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result back
to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSFoperation on bit5
of GPIO will cause all eight bits of GPIO to be read into
the CPU. Then the BSF operation takes place on bit5
and GPIO is written to the output latches. If another bit
of GPIO is used as a bi-directional I/O pin (i.e., bit0) and
it is defined as an input at this time, the input signal
present on the pin itself would be read into the CPU and
rewritten to the data latch of this particular pin, overwrit-
ing the previous content. As long as the pin stays in the
input mode, no problem occurs. However, if bit0 is
switched to an output, the content of the data latch may
now be unknown.
;Initial GPIO Settings
; GPIO<5:3> Inputs
; GPIO<2:0> Outputs
;
;
;
GPIO latch GPIO pins
---------- ----------
BCF
BCF
MOVLW 007h
TRIS GPIO
GPIO, 5
GPIO, 4
;--01 -ppp
;--10 -ppp
;
--11 pppp
--11 pppp
;--10 -ppp
--10 pppp
;
;Note that the user may have expected the pin
;values to be --00 pppp. The 2nd BCF caused
;GP5 to be latched as the pin value (High).
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.
Reading the port register reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(i.e., BCF, BSF, etc.) on a port, the value of the port
pins is read, the desired operation is done to this value,
and this value is then written to the port latch.
1999 Microchip Technology Inc.
DS30561B-page 31
PIC12C67X
NOTES:
DS30561B-page 32
1999 Microchip Technology Inc.
PIC12C67X
6.1
Bus Characteristics
6.0
EEPROM PERIPHERAL
OPERATION
The following bus protocol is to be used with the
EEPROM data memory. In this section, the term “proces-
sor” is used to denote the portion of the PIC12C67X that
interfaces to the EEPROM via software.
The PIC12CE673 and PIC12CE674 each have 16
bytes of EEPROM data memory. The EEPROM mem-
ory has an endurance of 1,000,000 erase/write cycles
and a data retention of greater than 40 years. The
EEPROM data memory supports a bi-directional 2-wire
bus and data transmission protocol. These two-wires
are serial data (SDA) and serial clock (SCL), that are
mapped to bit6 and bit7, respectively, of the GPIO reg-
ister (SFR 06h). Unlike the GP0-GP5 that are con-
nected to the I/O pins, SDA and SCL are only
connected to the internal EEPROM peripheral. For
most applications, all that is required is calls to the
following functions:
• Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as a
START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 6-3).
6.1.1
BUS NOT BUSY (A)
; Byte_Write: Byte write routine
Both data and clock lines remain HIGH.
;
;
;
Inputs:EEPROM Address
EEPROM Data
EEADDR
EEDATA
6.1.2
START DATA TRANSFER (B)
Outputs:
Return 01 in W if OK, else
return 00 in W
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
;
; Read_Current: Read EEPROM at address
currently held by EE device.
;
;
;
Inputs:NONE
Outputs:
6.1.3
STOP DATA TRANSFER (C)
EEPROM Data
EEDATA
Return 01 in W if OK, else
return 00 in W
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
;
; Read_Random: Read EEPROM byte at supplied
address
;
;
;
6.1.4
DATA VALID (D)
Inputs:EEPROM Address
Outputs: EEPROM Data
EEADDR
EEDATA
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
Return 01 in W if OK,
else return 00 in W
The code for these functions is available on our web
site (www.microchip.com). The code will be accessed
by either including the source code FL67XINC.ASM or
by linking FLASH67X.ASM. FLASH67X.INC provides
external definition to the calling program.
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the available data
EEPROM space.
6.0.1
SERIAL DATA
SDA is a bi-directional pin used to transfer addresses
and data into and data out of the device.
For normal data transfer, SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
6.0.2
SERIAL CLOCK
This SCL signal is used to synchronize the data trans-
fer from and to the EEPROM.
1999 Microchip Technology Inc.
DS30561B-page 33
PIC12C67X
6.1.5
ACKNOWLEDGE
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. The processor must signal an end of data to
the EEPROM by not generating an acknowledge bit on
the last byte that has been clocked out of the EEPROM.
In this case, the EEPROM must leave the data line
HIGH to enable the processor to generate the STOP
condition (Figure 6-4).
The EEPROM, when addressed, will generate an
acknowledge after the reception of each byte. The pro-
cessor must generate an extra clock pulse which is
associated with this acknowledge bit.
Note: Acknowledge bits are not generated if an
internal programming cycle is in progress.
FIGURE 6-1: BLOCK DIAGRAM OF GPIO6 (SDA LINE)
VDD
Reset
To EEPROM SDA
Pad
D
P
Write
GPIO
CK
Q
Data Bus
Output Latch
Q
D
Schmitt Trigger
CK
Input Latch
ltchpin
Read
GPIO
FIGURE 6-2: BLOCK DIAGRAM OF GPIO7 (SCL LINE)
VDD
To EEPROM SCL
Pad
D
P
N
Write
GPIO
CK
Q
Data Bus
Output Latch
Q
D
Schmitt Trigger
CK
ltchpin
Read
GPIO
DS30561B-page 34
1999 Microchip Technology Inc.
PIC12C67X
FIGURE 6-3: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(C)
(D)
(C)
(A)
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
FIGURE 6-4: ACKNOWLEDGE TIMING
Acknowledge
Bit
1
2
3
4
5
6
7
8
9
1
2
3
SCL
SDA
Data from transmitter
Data from transmitter
Receiver must release the SDA line at this
point so the Transmitter can continue
sending data.
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
6.2
Device Addressing
FIGURE 6-5: CONTROL BYTE FORMAT
After generating a START condition, the processor
transmits a control byte consisting of a EEPROM
address and a Read/Write bit that indicates what type
of operation is to be performed. The EEPROM address
consists of a 4-bit device code (1010) followed by three
don’t care bits.
Read/Write Bit
Device Select
Bits
Don’t Care
Bits
S
1
0
1
0
X
X
X
R/W ACK
The last bit of the control byte determines the operation
to be performed. When set to a one, a read operation
is selected, and when set to a zero, a write operation is
selected (Figure 6-5). The bus is monitored for its cor-
responding EEPROM address all the time. It generates
an acknowledge bit if the EEPROM address was true
and it is not in a programming mode.
EEPROM Address
Start Condition
Acknowledge Condition
1999 Microchip Technology Inc.
DS30561B-page 35
PIC12C67X
6.3
Write Operations
6.4
Acknowledge Polling
Since the EEPROM will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the processor, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the proces-
sor sending a start condition followed by the control
byte for a write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, then the start bit and control byte
must be re-sent. If the cycle is complete, then the
device will return the ACK and the processor can then
proceed with the next read or write command. (See
Figure 6-6 for flow diagram.)
6.3.1
BYTE WRITE
Following the start signal from the processor, the
device code (4 bits), the don’t care bits (3 bits), and the
R/W bit (which is a logic low) are placed onto the bus
by the processor. This indicates to the addressed
EEPROM that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the processor is the word address and will be written
into the address pointer. Only the lower four address
bits are used by the device, and the upper four bits are
don’t cares. If the address byte is acknowledged, the
processor will then transmit the data word to be written
into the addressed memory location. The memory
acknowledges again and the processor generates a
stop condition. This initiates the internal write cycle,
and during this time will not generate acknowledge sig-
nals. After a byte write command, the internal address
counter will not be incremented and will point to the
same address location that was just written. If a stop bit
sequence is transmitted to the device at any point in the
write command sequence before the entire sequence
is complete, then the command will abort and no data
will be written. If more than 8 data bits are transmitted
before the stop bit sequence is sent, then the device will
clear the previously loaded byte and begin loading the
data buffer again. If more than one data byte is trans-
mitted to the device and a stop bit is sent before a full
eight data bits have been transmitted, then the write
command will abort and no data will be written. The
EEPROM memory employs a VCC threshold detector
circuit, which disables the internal erase/write logic if
the VCC is below minimum VDD. Byte write operations
must be preceded and immediately followed by a bus
not busy bus cycle where both SDA and SCL are held
high. (See Figure 6-7 for Byte Write operation.)
FIGURE 6-6: ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did EEPROM
NO
Acknowledge
(ACK = 0)?
YES
Next
Operation
FIGURE 6-7: BYTE WRITE
S
T
A
R
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS
DATA
T
SDA LINE
ACTIVITY
P
S
1
0
1
0
X
X
X
0
X
X
X
X
A
C
K
A
C
K
A
C
K
X = Don’t Care Bit
DS30561B-page 36
1999 Microchip Technology Inc.
PIC12C67X
address is sent, the processor generates a start condi-
tion following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then the processor issues the control
byte again, but with the R/W bit set to a one. The
EEPROM will then issue an acknowledge and trans-
mits the 8-bit data word. The processor will not
acknowledge the transfer, but does generate a stop
condition and the EEPROM discontinues transmission
(Figure 6-9). After this command, the internal address
counter will point to the address location following the
one that was just read.
6.5
Read Operations
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
EEPROM address is set to one. There are three basic
types of read operations; current address read, random
read and sequential read.
6.5.1
CURRENT ADDRESS READ
The EEPROM contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n, the next current address read
operation would access data from address n + 1. Upon
receipt of the EEPROM address with the R/W bit set to
one, the EEPROM issues an acknowledge and trans-
mits the 8-bit data word. The processor will not
acknowledge the transfer, but does generate a stop
condition and the EEPROM discontinues transmission
(Figure 6-8).
6.5.3
SEQUENTIAL READ
Sequential reads are initiated in the same way as a ran-
dom read, except that after the device transmits the first
data byte, the processor issues an acknowledge as
opposed to a stop condition in a random read. This
directs the EEPROM to transmit the next sequentially
addressed 8-bit word (Figure 6-10).
6.5.2
RANDOM READ
To provide sequential reads, the EEPROM contains an
internal address pointer, which is incremented by one
at the completion of each read operation. This address
pointer allows the entire memory contents to be serially
read during one operation.
Random read operations allow the processor to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
EEPROM as part of a write operation. After the word
FIGURE 6-8: CURRENT ADDRESS READ
S
T
A
R
S
T
O
P
CONTROL
BYTE
T
SDA LINE
ACTIVITY
S 1 0 1 0 X X X 1
P
A
C
K
N
O
DATA
A
C
K
X = Don’t Care Bit
FIGURE 6-9: RANDOM READ
S
T
A
R
T
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS (n)
CONTROL
BYTE
X X X X
P
S 1 0 1 0 X X X 0
S 1 0 1 0 X X X 1
SDA LINE
ACTIVITY
A
C
K
A
C
K
A
C
K
N
O
DATA (n)
A
C
K
X = Don’t Care Bit
FIGURE 6-10: SEQUENTIAL READ
S
T
O
P
CONTROL
DATA n
BYTE
DATA n + 1
DATA n + 2
DATA n + X
SDA LINE
ACTIVITY
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
1999 Microchip Technology Inc.
DS30561B-page 37
PIC12C67X
NOTES:
DS30561B-page 38
1999 Microchip Technology Inc.
PIC12C67X
(OPTION<4>). Clearing bit T0SE selects the rising
edge. Restrictions on the external clock input are dis-
cussed in detail in Section 7.2.
7.0
TIMER0 MODULE
The Timer0 module timer/counter has the following fea-
tures:
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The pres-
caler assignment is controlled in software by control bit
PSA (OPTION<3>). Clearing bit PSA will assign the
prescaler to the Timer0 module. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4, ...,
1:256 are selectable. Section 7.3 details the operation
of the prescaler.
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0
module.
7.1
Timer0 Interrupt
Timer mode is selected by clearing bit T0CS
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
the TMR0 register is written, the increment is inhibited
for the following two instruction cycles (Figure 7-2 and
Figure 7-3). The user can work around this by writing
an adjusted value to the TMR0 register.
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt ser-
vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP, since the timer is shut off during SLEEP. See
Figure 7-4 for Timer0 interrupt timing.
Counter mode is selected by setting bit T0CS
(OPTION<5>). In counter mode, Timer0 will increment
either on every rising or falling edge of pin RA4/T0CKI.
The incrementing edge is determined by the bit T0SE
FIGURE 7-1: TIMER0 BLOCK DIAGRAM
Data Bus
FOSC/4
0
1
8
1
0
Sync with
Internal
clocks
TMR0
Programmable
Prescaler
GP2/TOCKI/
AN2/INT
(2 TCY delay)
TOSE
3
Set interrupt
flag bit T0IF
on overflow
PS<2:0>
PSA
TOCS
Note 1: TOCS, TOSE, PSA, PS<2:0> (OPTION<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram).
FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
Instruction
Fetch
MOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,W
MOVWF TMR0
T0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
TMR0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0 Read TMR0 Read TMR0
reads NT0 reads NT0 reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
1999 Microchip Technology Inc.
DS30561B-page 39
PIC12C67X
FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
MOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,W
MOVWF TMR0
Instruction
Fetch
T0
T0+1
NT0+1
NT0
TMR0
Instruction
Execute
Read TMR0
reads NT0
Read TMR0 Read TMR0 Read TMR0
reads NT0 reads NT0 reads NT0
Read TMR0
reads NT0 + 1
Write TMR0
executed
FIGURE 7-4: TIMER0 INTERRUPT TIMING
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
OSC1
CLKOUT(3)
Timer0
FEh
FFh
00h
01h
02h
1
1
T0IF bit
(INTCON<2>)
Interrupt Latency(2)
GIE bit
(INTCON<7>)
INSTRUCTION
FLOW
PC
PC
PC +1
PC +1
0004h
0005h
Instruction
fetched
Inst (PC)
Inst (PC+1)
Inst (0004h)
Inst (0005h)
Inst (0004h)
Instruction
executed
Inst (PC-1)
Dummy cycle
Dummy cycle
Inst (PC)
Note 1: Interrupt flag bit T0IF is sampled here (every Q1).
2: Interrupt latency = 3TCY where TCY = instruction cycle time.
3: CLKOUT is available only in the INTRC and EXTRC oscillator modes.
DS30561B-page 40
1999 Microchip Technology Inc.
PIC12C67X
caler, so that the prescaler output is symmetrical. For
the external clock to meet the sampling requirement,
the ripple-counter must be taken into account. There-
fore, it is necessary for T0CKI to have a period of at
least 4TOSC (and a small RC delay of 40 ns) divided by
the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the mini-
mum pulse width requirement of 10 ns. Refer to param-
eters 40, 41 and 42 in the electrical specification of the
desired device.
7.2
Using Timer0 with an External Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
7.2.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
used as the clock source. The synchronization of
T0CKI with the internal phase clocks is accomplished
by sampling the prescaler output on the Q2 and Q4
cycles of the internal phase clocks (Figure 7-5). There-
fore, it is necessary for T0CKI to be high for at least
2TOSC (and a small RC delay of 20 ns) and low for at
least 2TOSC (and a small RC delay of 20 ns). Refer to
the electrical specification of the desired device.
7.2.2
TMR0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0 mod-
ule is actually incremented. Figure 7-5 shows the delay
from the external clock edge to the timer incrementing.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type pres-
FIGURE 7-5: TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small pulse
misses sampling
External Clock Input or
Prescaler output(2)
(1)
(3)
External Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC. (Duration of Q = TOSC). Therefore, the error
in measuring the interval between two edges on Timer0 input = ±4TOSC max.
2: External clock if no prescaler selected; prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
1999 Microchip Technology Inc.
DS30561B-page 41
PIC12C67X
The PSA and PS<2:0> bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
7.3
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 7-6). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available which is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer, and
vice-versa.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (i.e., CLRF 1, MOVWF 1,
BSF 1,x...., etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The pres-
caler is not readable or writable.
FIGURE 7-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
8
CLKOUT (= FOSC/4)
M
U
X
1
0
0
1
M
U
X
GP2/T0CKI/
AN2/INT
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
Set flag bit T0IF
on Overflow
PSA
0
1
8-bit Prescaler
M
U
X
Watchdog
Timer
8
8 - to - 1MUX
PS<2:0>
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS<2:0> are (OPTION<5:0>).
DS30561B-page 42
1999 Microchip Technology Inc.
PIC12C67X
7.3.1
SWITCHING PRESCALER ASSIGNMENT
To change prescaler from the WDT to the Timer0 mod-
ule, use the sequence shown in Example 7-2.
The prescaler assignment is fully under software con-
trol, (i.e., it can be changed “on-the-fly” during program
execution).
EXAMPLE 7-2: CHANGING PRESCALER
(WDT→TIMER0)
Note: To avoid an unintended device RESET, the
following instruction sequence (shown in
Example 7-1) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must
be followed even if the WDT is disabled.
CLRWDT
;Clear WDT and
;prescaler
STATUS, RP0 ;Bank 1
b’xxxx0xxx’ ;Select TMR0, new
;prescale value and
OPTION_REG ;clock source
STATUS, RP0 ;Bank 0
BSF
MOVLW
MOVWF
BCF
EXAMPLE 7-1: CHANGING PRESCALER
(TIMER0→WDT)
BCF
STATUS, RP0 ;Bank 0
CLRF
BSF
TMR0
;Clear TMR0 & Prescaler
STATUS, RP0 ;Bank 1
CLRWDT
;Clears WDT
MOVLW b’xxxx1xxx’ ;Select new prescale
MOVWF OPTION_REG ;value & WDT
STATUS, RP0 ;Bank 0
BCF
TABLE 7-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
Value on
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
01h
TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
0000 000x 0000 000u
1111 1111 1111 1111
0Bh/8Bh INTCON
GIE
OPTION GPPU INTEDG
TRIS
PEIE
T0IE
T0CS
TRIS5
INTE
T0SE
TRIS4
GPIE
PSA
T0IF
PS2
INTF
PS1
GPIF
PS0
81h
85h
—
—
TRIS3
TRIS2
TRIS1
TRIS0 --11 1111 --11 1111
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by Timer0.
1999 Microchip Technology Inc.
DS30561B-page 43
PIC12C67X
NOTES:
DS30561B-page 44
1999 Microchip Technology Inc.
PIC12C67X
The ADCON0 Register, shown in Figure 8-1, controls
the operation of the A/D module. The ADCON1 Regis-
ter, shown in Figure 8-2, configures the functions of the
port pins. The port pins can be configured as analog
inputs (GP1 can also be a voltage reference) or as dig-
ital I/O.
8.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-To-Digital (A/D) converter module has four
analog inputs.
The A/D allows conversion of an analog input signal to
a corresponding 8-bit digital number (refer to Applica-
tion Note AN546 for use of A/D Converter). The output
of the sample and hold is the input into the converter,
which generates the result via successive approxima-
tion. The analog reference voltage is software select-
able to either the device’s positive supply voltage (VDD)
or the voltage level on the GP1/AN1/VREF pin. The A/D
converter has a unique feature of being able to operate
while the device is in SLEEP mode.
Note 1: If the port pins are configured as analog
inputs (reset condition), reading the port
(MOVF GPIO,W) results in reading '0's.
2: Changing ADCON1 Register can cause
the GPIF and INTF flags to be set in the
INTCON Register.
These interrupts
should be disabled prior to modifying
ADCON1.
The A/D module has three registers. These registers
are:
• A/D Result Register (ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
REGISTER 8-1:
ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0 R/W-0
R/W-0
ADCS1 ADCS0 reserved CHS1
CHS0 GO/DONE reserved ADON
bit0
R =Readable bit
W = Writable bit
bit7
U =Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-6: ADCS<1:0>: A/D Conversion Clock Select bits
00= FOSC/2
01= FOSC/8
10= FOSC/32
11= FRC (clock derived from an RC oscillation)
bit 5:
Reserved
bit 4-3: CHS<1:0>: Analog Channel Select bits
00= channel 0, (GP0/AN0)
01= channel 1, (GP1/AN1)
10= channel 2, (GP2/AN2)
11= channel 3, (GP4/AN3)
bit 2:
GO/DONE: A/D Conversion Status bit
If ADON = 1
1= A/D conversion in progress (setting this bit starts the A/D conversion)
0= A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D conversion
is complete)
bit 1:
bit 0:
Reserved
ADON: A/D on bit
1= A/D converter module is operating
0= A/D converter module is shut off and consumes no operating current
1999 Microchip Technology Inc.
DS30561B-page 45
PIC12C67X
REGISTER 8-2:
ADCON1 REGISTER (ADDRESS 9Fh)
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
PCFG2
PCFG1
PCFG0
R =Readable bit
W = Writable bit
bit7
bit0
U =Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1-0: PCFG<2:0>: A/D Port Configuration Control bits
PCFG<2:0>
GP4
GP2
GP1
GP0
VREF
000(1)
001
010
011
100
101
110
111
A
A
A
A
VDD
A
D
D
D
D
D
D
A
A
A
D
D
D
D
VREF
A
A
A
A
A
A
A
D
GP1
VDD
GP1
VDD
GP1
VDD
VDD
VREF
A
VREF
D
D
A = Analog input
D = Digital I/O
Note 1: Value on reset.
2: Any instruction that reads a pin configured as an analog input will read a '0'.
DS30561B-page 46
1999 Microchip Technology Inc.
PIC12C67X
The ADRES Register contains the result of the A/D
conversion. When the A/D conversion is complete, the
result is loaded into the ADRES register, the GO/DONE
bit (ADCON0<2>) is cleared, and A/D interrupt flag bit
ADIF (PIE1<6>) is set. The block diagrams of the A/D
module are shown in Figure 8-1.
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine sample time, see Section 8.1. After
this acquisition time has elapsed, the A/D conversion
can be started. The following steps should be followed
for doing an A/D conversion:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result Register (ADRES), clear bit
ADIF if required.
1. Configure the A/D module:
7. For the next conversion, go to step 1, step 2 or
step 3 as required. The A/D conversion time per
bit is defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
• Configure analog pins / voltage reference /
and digital I/O (ADCON1 and TRIS)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
FIGURE 8-1: A/D BLOCK DIAGRAM
CHS<1:0>
11
GP4/AN3
VIN
10
(Input voltage)
GP2/AN2
01
A/D
Converter
GP1/AN1/VREF
00
GP0/AN0
VDD
VREF
(Reference
voltage)
PCFG<2:0>
1999 Microchip Technology Inc.
DS30561B-page 47
PIC12C67X
8.1
A/D Sampling Requirements
Note 1: The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 8-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
Figure 8-2. The maximum recommended imped-
ance for analog sources is 10 kΩ. After the analog
input channel is selected (changed), this acquisition
must be done before the conversion can be started.
2: The charge holding capacitor (CHOLD) is
not discharged after each conversion.
3: The maximum recommended impedance
for analog sources is 10 kΩ. This is
required to meet the pin leakage specifi-
cation.
4: After a conversion has completed, a
2.0 TAD delay must complete before
acquisition can begin again. During this
time, the holding capacitor is not con-
nected to the selected A/D input channel.
To calculate the minimum acquisition time, Equation 8-1
may be used. This equation assumes that 1/2 LSb error
is used (512 steps for the A/D). The 1/2 LSb error is the
maximum error allowed for the A/D to meet its specified
resolution.
EXAMPLE 8-1: CALCULATING THE
MINIMUM REQUIRED
SAMPLE TIME
EQUATION 8-1:
A/D MINIMUM CHARGING
TIME
TACQ = Internal Amplifier Settling Time +
Holding Capacitor Charging Time +
Temperature Coefficient
(-Tc/CHOLD(RIC + RSS + RS))
VHOLD = (VREF - (VREF/512)) • (1 - e
)
or
TACQ = 5 µs + Tc + [(Temp - 25°C)(0.05 µs/°C)]
Tc = -(51.2 pF)(1 kΩ + RSS + RS) ln(1/511)
TC =
-CHOLD (RIC + RSS + RS) ln(1/512)
-51.2 pF (1 kΩ + 7 kΩ + 10 kΩ) ln(0.0020)
-51.2 pF (18 kΩ) ln(0.0020)
-0.921 µs (-6.2146)
Example 8-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following system assumptions.
Rs = 10 kΩ
1/2 LSb error
5.724 µs
VDD = 5V → Rss = 7 kΩ
Temp (system max.) = 50°C
VHOLD = 0 @ t = 0
TACQ = 5 µs + 5.724 µs + [(50°C - 25°C)(0.05 µs/°C)]
10.724 µs + 1.25 µs
11.974 µs
FIGURE 8-2: ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
RAx
SS
RIC ≤ 1k
Rss
Rs
CHOLD
= DAC capacitance
= 51.2 pF
CPIN
5 pF
VA
I leakage
± 500 nA
VT = 0.6V
VSS
Legend: CPIN
VT
= input capacitance
= threshold voltage
6V
5V
VDD 4V
3V
I leakage = leakage current at the pin due to
various junctions
2V
RIC
SS
= interconnect resistance
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
5 6 7 8 9 10 11
Sampling Switch
( kΩ )
DS30561B-page 48
1999 Microchip Technology Inc.
PIC12C67X
8.2
Selecting the A/D Conversion Clock
8.3
Configuring Analog Port Pins
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.5 TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selected. The four possible options for TAD are:
The ADCON1 and TRIS Registers control the opera-
tion of the A/D port pins. The port pins that are desired
as analog inputs must have their corresponding TRIS
bits set (input). If the TRIS bit is cleared (output), the
digital output level (VOH or VOL) will be converted.
• 2TOSC
The A/D operation is independent of the state of the
CHS<2:0> bits and the TRIS bits.
• 8TOSC
• 32TOSC
• Internal ADC RC oscillator
Note 1: When reading the port register, all pins
configured as analog input channel will
read as cleared (a low level). Pins config-
ured as digital inputs, will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs. If the minimum TAD time of 1.6 µs can not be
obtained, TAD should be ≤8 µs for preferred operation.
Table 8-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
2: Analog levels on any pin that is defined as
a digital input (including the AN<3:0>
pins) may cause the input buffer to con-
sume current that is out of the devices
specification.
TABLE 8-1:
TAD vs. DEVICE OPERATING FREQUENCIES
Device Frequency
AD Clock Source (TAD)
ADCS<1:0>
Operation
2TOSC
4 MHz
1.25 MHz
1.6 µs
333.33 kHz
500 ns(2)
00
01
10
11
6 µs
24 µs(3)
96 µs(3)
2 - 6 µs(1)
8TOSC
2.0 µs
6.4 µs
25.6 µs(3)
2 - 6 µs(1,4)
32TOSC
8.0 µs
Internal ADC RC Oscillator(5)
2 - 6 µs(1,4)
Note 1: The RC source has a typical TAD time of 4 µs.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: While in RC mode, with device frequency above 1 MHz, conversion accuracy is out of specification.
5: For extended voltage devices (LC), please refer to Electrical Specifications section.
1999 Microchip Technology Inc.
DS30561B-page 49
PIC12C67X
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRES register will
NOT be updated with the partially completed A/D con-
version sample. That is, the ADRES register will con-
tinue to contain the value of the last completed
conversion (or the last value written to the ADRES reg-
ister). After the A/D conversion is aborted, a 2TAD wait
is required before the next acquisition is started. After
this 2TAD wait, an acquisition is automatically started on
the selected channel.
8.4
A/D Conversions
Example 8-2 shows how to perform an A/D conversion.
The GPIO pins are configured as analog inputs. The
analog reference (VREF) is the device VDD. The A/D
interrupt is enabled and the A/D conversion clock is
FRC. The conversion is performed on the GP0 channel.
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
EXAMPLE 8-2: DOING AN A/D CONVERSION
BSF
CLRF
BSF
STATUS, RP0
ADCON1
; Select Page 1
; Configure A/D inputs
; Enable A/D interrupts
; Select Page 0
; RC Clock, A/D is on, Channel 0 is selected
;
; Clear A/D interrupt flag bit
; Enable peripheral interrupts
; Enable all interrupts
PIE1,
ADIE
BCF
STATUS, RP0
0xC1
ADCON0
MOVLW
MOVWF
BCF
BSF
BSF
PIR1,
ADIF
INTCON, PEIE
INTCON, GIE
;
;
;
;
Ensure that the required sampling time for the selected input channel has elapsed.
Then the conversion may be started.
BSF
:
ADCON0, GO
; Start A/D Conversion
; The ADIF bit will be set and the GO/DONE bit
:
;
is cleared upon completion of the A/D Conversion.
DS30561B-page 50
1999 Microchip Technology Inc.
PIC12C67X
8.5
A/D Operation During Sleep
8.7
Effects of a Reset
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS<1:0> = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared,
and the result loaded into the ADRES Register. If the
A/D interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off, and any
conversion is aborted. The value that is in the ADRES
register is not modified for a Reset. The ADRES regis-
ter will contain unknown data after a Power-on Reset.
8.8
Connection Considerations
If the input voltage exceeds the rail values (VSS or VDD)
by greater than 0.2V, then the accuracy of the conver-
sion is out of specification.
Note: For the PIC12C67X, care must be taken
when using the GP4 pin in A/D conversions
due to its proximity to the OSC1 pin.
When the A/D clock source is another clock option (not
RC), a SLEEPinstruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
An external RC filter is sometimes added for anti-
aliasing of the input signal. The R component should be
selected to ensure that the total source impedance is
kept under the 10 kΩ recommended specification. Any
external components connected (via hi-impedance) to
an analog input pin (capacitor, zener diode, etc.) should
have very little leakage current at the pin.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS<1:0> = 11). To perform an A/D
conversion in SLEEP, the GO/DONE bit
must be set, followed by the SLEEP
instruction.
8.9
Transfer Function
The ideal transfer function of the A/D converter is as fol-
lows: the first transition occurs when the analog input
voltage (VAIN) is 1 LSb (or Analog VREF / 256)
(Figure 8-3).
8.6
A/D Accuracy/Error
FIGURE 8-3: A/D TRANSFER FUNCTION
The overall accuracy of the A/D is less than ± 1 LSb for
VDD = 5V ± 10% and the analog VREF = VDD. This over-
all accuracy includes offset error, full scale error, and
integral error. The A/D converter is monotonic over the
full VDD range. The resolution and accuracy may be
less when either the analog reference (VDD) is less than
5.0V or when the analog reference (VREF) is less than
VDD.
FFh
FEh
The maximum pin leakage current is specified in the
Device Data Sheet electrical specification, parameter
#D060.
04h
03h
02h
01h
00h
In systems where the device frequency is low, use of
the A/D RC clock is preferred. At moderate to high fre-
quencies, TAD should be derived from the device oscil-
lator. TAD must not violate the minimum and should be
≤8 µs for preferred operation. This is because TAD,
when derived from TOSC, is kept away from on-chip
phase clock transitions. This reduces, to a large extent,
the effects of digital switching noise. This is not possible
with the RC derived clock. The loss of accuracy due to
digital switching noise can be significant if many I/O
pins are active.
Analog input voltage
In systems where the device will enter SLEEP mode
after the start of the A/D conversion, the RC clock
source selection is required. In this mode, the digital
noise from the modules in SLEEP are stopped. This
method gives high accuracy.
1999 Microchip Technology Inc.
DS30561B-page 51
PIC12C67X
FIGURE 8-4: FLOWCHART OF A/D OPERATION
ADON = 0
Yes
ADON = 0?
No
Acquire
Selected Channel
Yes
GO = 0?
No
Yes
Yes
Start of A/D
Conversion Delayed
1 Instruction Cycle
Finish Conversion
SLEEP
Instruction?
A/D Clock
= RC?
GO = 0
ADIF = 1
No
No
Yes
Yes
Abort Conversion
GO = 0
Wake-up
From Sleep?
Finish Conversion
Device in
SLEEP?
Wait 2 TAD
GO = 0
ADIF = 1
ADIF = 0
No
No
SLEEP
Power-down A/D
Finish Conversion
Stay in Sleep
Power-down A/D
Wait 2 TAD
GO = 0
ADIF = 1
Wait 2 TAD
TABLE 8-2:
SUMMARY OF A/D REGISTERS
Value on
Power-on
Reset
Value on
all other
Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Bh/8Bh INTCON
GIE
PEIE
T0IE
INTE GPIE
T0IF
INTF
GPIF
0000 000x 0000 000u
-0-- ---- -0-- ----
PIR1
—
ADIF
—
—
—
—
—
—
—
—
0Ch
8Ch
1Eh
1Fh
9Fh
05h
85h
PIE1
—
ADIE
—
—
—
—
-0-- ---- -0-- ----
xxxx xxxx uuuu uuuu
ADRES
A/D Result Register
ADCON0
ADCON1
ADCS1 ADCS0 reserved CHS1 CHS0 GO/DONE reserved ADON 0000 0000 0000 0000
—
—
—
—
—
PCFG2
PCFG1 PCFG0 ---- -000 ---- -000
(2)
(2)
11xx xxxx 11uu uuuu
--11 1111 --11 1111
GPIO
TRIS
SCL
—
SDA
—
GP5
GP4
GP3
GP2
GP1
GP0
TRIS5 TRIS4 TRIS3
TRIS2
TRIS1
TRIS0
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: These registers can be addressed from either bank.
2: The SCL (GP7) and SDA (GP6) bits are unimplemented on the PIC12C671/672 and read as ’0’.
DS30561B-page 52
1999 Microchip Technology Inc.
PIC12C67X
the chip in reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only,
designed to keep the part in reset while the power sup-
ply stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
9.0
SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other proces-
sors are special circuits to deal with the needs of real-
time applications. The PIC12C67X family has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external compo-
nents, provide power saving operating modes and offer
code protection. These are:
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The INTRC/EXTRC oscillator option saves system
cost, while the LP crystal option saves power. A set of
configuration bits are used to select various options.
• Oscillator selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
• Interrupts
9.1
Configuration Bits
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h-
3FFFh), which can be accessed only during
programming.
• In-circuit serial programming
The PIC12C67X has a Watchdog Timer, which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
REGISTER 9-1:
CONFIGURATION WORD
CP1 CP0 CP1 CP0 CP1 CP0 MCLRE CP1
bit13
CP0 PWRTE WDTE FOSC2 FOSC1 FOSC0
bit0
Register: CONFIG
Address 2007h
(1)
bit 13-8, CP<1:0>: Code Protection bit pairs
6-5: 11= Code protection off
10= Locations 400h through 7FEh code protected (do not use for PIC12C671 and PIC12CE673)
01= Locations 200h through 7FEh code protected
00= All memory is code protected
bit 7:
bit 4:
bit 3:
MCLRE: Master Clear Reset Enable bit
1 = Master Clear Enabled
0 = Master Clear Disabled
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0: FOSC<2:0>: Oscillator Selection bits
111= EXTRC, Clockout on OSC2
110= EXTRC, OSC2 is I/O
101= INTRC, Clockout on OSC2
100= INTRC, OSC2 is I/O
011= Invalid Selection
010= HS Oscillator
001= XT Oscillator
000= LP Oscillator
Note 1: All of the CP<1:0> pairs have to be given the same value to enable the code protection scheme listed.
1999 Microchip Technology Inc.
DS30561B-page 53
PIC12C67X
9.2
Oscillator Configurations
OSCILLATOR TYPES
TABLE 9-1:
CAPACITOR SELECTION
FOR CERAMIC RESONATORS
- PIC12C67X
9.2.1
The PIC12C67X can be operated in seven different
oscillator modes. The user can program three
configuration bits (FOSC<2:0>) to select one of these
seven modes:
Osc
Type
Resonator Cap. Range Cap. Range
Freq
C1
C2
XT
455 kHz
2.0 MHz
4.0 MHz
22-100 pF
15-68 pF
15-68 pF
22-100 pF
15-68 pF
15-68 pF
• LP:
• HS:
• XT:
Low Power Crystal
High Speed Crystal/Resonator
Crystal/Resonator
HS
4.0 MHz
8.0 MHz
10.0 MHz
15-68 pF
10-68 pF
10-22 pF
15-68 pF
10-68 pF
10-22 pF
• INTRC*: Internal 4 MHz Oscillator
• EXTRC*: External Resistor/Capacitor
These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for
appropriate values of external components.
*Can be configured to support CLKOUT
9.2.2
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
TABLE 9-2:
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
- PIC12C67X
In XT, HS or LP modes, a crystal or ceramic resonator
is connected to the GP5/OSC1/CLKIN and GP4/OSC2
pins to establish oscillation (Figure 9-1). The
PIC12C67X oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may give
Osc
Type
Resonator Cap. Range Cap. Range
Freq
C1
C2
LP
32 kHz(1)
100 kHz
200 kHz
15 pF
15-30 pF
15-30 pF
15 pF
30-47 pF
15-82 pF
a
frequency out of the crystal manufacturers
specifications. When in XT, HS or LP modes, the
device can have an external clock source drive the
GP5/OSC1/CLKIN pin (Figure 9-2).
XT
100 kHz
200 kHz
455 kHz
1 MHz
2 MHz
4 MHz
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-47 pF
200-300 pF
100-200 pF
15-100 pF
15-30 pF
15-30 pF
15-47 pF
FIGURE 9-1: CRYSTAL OPERATION
(OR CERAMIC RESONATOR)
(XT, HS OR LP OSC
CONFIGURATION)
HS
4 MHz
8 MHz
10 MHz
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
(1)
C1
OSC1
PIC12C67X
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is
SLEEP
recommended.
XTAL
(3)
RF
To internal
logic
These values are for design guidance only. Rs may
be required in HS mode, as well as XT mode, to
avoid overdriving crystals with low drive level specifi-
cation. Since each crystal has its own characteris-
tics, the user should consult the crystal manufacturer
for appropriate values of external components.
OSC2
(2)
RS
(1)
C2
Note 1: See Capacitor Selection tables for
recommended values of C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the oscillator mode selected
(approx. value = 10 MΩ).
FIGURE 9-2: EXTERNAL CLOCK INPUT
OPERATION (XT, HS OR LP
OSC CONFIGURATION)
OSC1
OSC2
Clock from
ext. system
PIC12C67X
Open
DS30561B-page 54
1999 Microchip Technology Inc.
PIC12C67X
9.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
9.2.4
EXTERNAL RC OSCILLATOR
For timing insensitive applications, the RC device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (REXT) and capacitor (CEXT) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low CEXT values. The user also needs to
take into account variation due to tolerance of external
R and C components used.
Either a pre-packaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external
crystal oscillator circuit. Pre-packaged oscillators
provide a wide operating range and better stability. A
well-designed crystal oscillator will provide good
performance with TTL gates. Two types of crystal
oscillator circuits can be used; one with parallel
resonance or one with series resonance.
Figure 9-3 shows implementation of
a
parallel
resonant oscillator circuit. The circuit is designed to
use the fundamental frequency of the crystal. The
74AS04 inverter performs the 180-degree phase shift
that a parallel oscillator requires. The 4.7 kΩ resistor
provides the negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
This circuit could be used for external oscillator
designs.
Figure 9-5 shows how the R/C combination is
connected to the PIC12C67X. For REXT values below
2.2 kΩ, the oscillator operation may become unstable
or stop completely. For very high REXT values
(i.e., 1 MΩ), the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend keeping
REXT between 3 kΩ and 100 kΩ.
FIGURE 9-3: EXTERNAL PARALLEL
RESONANT CRYSTAL
Although the oscillator will operate with no external
capacitor (CEXT = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
PIC12C67X
4.7k
74AS04
CLKIN
The variation is larger for larger R (since leakage
current variation will affect RC frequency more for
large R) and for smaller C (since variation of input
capacitance will affect RC frequency more).
10k
XTAL
FIGURE 9-5: EXTERNAL RC OSCILLATOR
MODE
10k
VDD
20 pF
20 pF
REXT
Internal
clock
OSC1
N
Figure 9-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180-
degree phase shift in a series resonant oscillator
circuit. The 330 Ω resistors provide the negative
feedback to bias the inverters in their linear region.
CEXT
VSS
PIC12C67X
OSC2/CLKOUT
FOSC/4
FIGURE 9-4: EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
To Other
Devices
330
330
74AS04
74AS04
74AS04
PIC12C67X
CLKIN
0.1 µF
XTAL
1999 Microchip Technology Inc.
DS30561B-page 55
PIC12C67X
9.2.5
INTERNAL 4 MHz RC OSCILLATOR
9.3
Reset
The PIC12C67X differentiates between various kinds
of reset:
The internal RC oscillator provides a fixed 4 MHz (nom-
inal) system clock at VDD = 5V and 25°C. See
Section 13.0 for information on variation over voltage
and temperature.
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during SLEEP
• WDT Reset (normal operation)
In addition, a calibration instruction is programmed into
the last address of the program memory which contains
the calibration value for the internal RC oscillator. This
value is programmed as a RETLW XXinstruction where
XX is the calibration value. In order to retrieve the cali-
bration value, issue a CALL YYinstruction where YY is
the last location in program memory (03FFh for the
PIC12C671 and the PIC12CE673, 07FFh for the
PIC12C672 and the PIC12CE674). Control will be
returned to the user’s program with the calibration
value loaded into the W register. The program should
then perform a MOVWF OSCCALinstruction to load the
value into the internal RC oscillator trim register.
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), MCLR Reset, WDT
Reset, and MCLR Reset during SLEEP. They are not
affected by a WDT Wake-up, which is viewed as the
resumption of normal operation. The TO and PD bits
are set or cleared differently in different reset situations,
as indicated in Table 9-5. These bits are used in
software to determine the nature of the reset. See
Table 9-6 for a full description of reset states of all
registers.
OSCCAL, when written to with the calibration value, will
“trim” the internal oscillator to remove process variation
from the oscillator frequency. Bits <7:4>, CAL<3:0> are
used for fine calibration, while bit 3, CALFST, and bit 2,
CALSLW, are used for more coarse adjustment. Adjust-
ing CAL<3:0> from 0000 to 1111 yields a higher clock
speed. Set CALFST = 1 for greater increase in fre-
quency or set CALSLW = 1 for greater decrease in fre-
quency. Note that bits 1 and 0 of OSCCAL are
unimplemented and should be written as 0 when mod-
ifying OSCCAL for compatibility with future devices.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 9-6.
The PIC12C67X has a MCLR noise filter in the MCLR
reset path. The filter will detect and ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
When MCLR is asserted, the state of the OSC1/CLKIN
and CLKOUT/OSC2 pins are as follows:
Note: Please note that erasing the device will
also erase the pre-programmed internal
calibration value for the internal oscillator.
The calibration value must be saved prior
to erasing the part.
TABLE 9-3:
CLKIN/CLKOUT PIN STATES
WHEN MCLR ASSERTED
Oscillator Mode OSC1/CLKIN Pin OSC2/CLKout Pin
EXTRC, CLKOUT OSC1 pin is
on OSC2
OSC2 pin is driven
low
tristated and
driven by external
circuit
9.2.6
CLKOUT
The PIC12C67X can be configured to provide a clock
out signal (CLKOUT) on pin 3 when the configuration
word address (2007h) is programmed with FOSC2,
FOSC1, and FOSC0, equal to 101 for INTRC or 111 for
EXTRC. The oscillator frequency, divided by 4, can be
used for test purposes or to synchronize other logic.
EXTRC, OSC2 is OSC1 pin is
OSC2 pin is
tristate input
I/O
tristated and
driven by external
circuit
INTRC, CLKOUT OSC1 pin is
OSC2 pin is driven
low
on OSC2
tristate input
INTRC, OSC2 is
I/O
OSC1 pin is
tristate input
OSC2 pin is
tristate input
DS30561B-page 56
1999 Microchip Technology Inc.
PIC12C67X
FIGURE 9-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Weak
Pull-up
GP3/MCLR/VPP Pin
MCLRE
INTERNAL MCLR
WDT
Module
SLEEP
WDT Time-out
VDD rise
detect
Power-on Reset
VDD
S
OST/PWRT
OST
Chip_Reset
10-bit Ripple-counter
R
Q
OSC1/
CLKIN
Pin
PWRT
(1)
On-chip
RC OSC
10-bit Ripple-counter
Enable PWRT
Enable OST
See Table 9-4 for time-out situations.
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
1999 Microchip Technology Inc.
DS30561B-page 57
PIC12C67X
9.4.3
OSCILLATOR START-UP TIMER (OST)
9.4
Power-on Reset (POR), Power-up
Timer (PWRT) and Oscillator Start-up
Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal oscil-
lator or resonator has started and stabilized.
9.4.1
POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in reset until
VDD has reached a high enough level for proper opera-
tion. To take advantage of the POR, just tie the MCLR
pin through a resistor to VDD. This will eliminate exter-
nal RC components usually needed to create a Power-
on Reset. A maximum rise time for VDD is specified.
See Electrical Specifications for details.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
9.4.4
TIME-OUT SEQUENCE
On power-up, the Time-out Sequence is as follows:
first, PWRT time-out is invoked after the POR time
delay has expired; then, OST is activated. The total
time-out will vary, based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 9-7, Figure 9-8, and Figure 9-9 depict time-out
sequences on power-up.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
For additional information, refer to Application Note
AN607, "Power-up Trouble Shooting."
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 9-9). This is useful for testing purposes or to
synchronize more than one PIC12C67X device operat-
ing in parallel.
9.4.2
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only, from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in reset as long as the PWRT is active. The
PWRT’s time delay allows VDD to rise to an acceptable
level. A configuration bit is provided to enable/disable
the PWRT.
9.4.5
POWER CONTROL (PCON)/STATUS
REGISTER
The Power Control/Status Register, PCON (address
8Eh), has one bit. See Register 4-6 for register.
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation. See
Table 11-4.
Bit1 is POR (Power-on Reset). It is cleared on a Power-
on Reset and is unaffected otherwise. The user sets
this bit following a Power-on Reset. On subsequent
resets, if POR is ‘0’, it will indicate that a Power-on
Reset must have occurred.
TABLE 9-4:
TIME-OUT IN VARIOUS SITUATIONS
Oscillator Configuration
Power-up
Wake-up from SLEEP
PWRTE = 0 PWRTE = 1
XT, HS, LP
72 ms + 1024TOSC
1024TOSC
1024TOSC
INTRC, EXTRC
72 ms
—
—
TABLE 9-5:
STATUS/PCON BITS AND THEIR SIGNIFICANCE
PD
POR
TO
0
0
0
1
1
1
1
1
0
x
0
0
u
1
1
x
0
u
0
u
0
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Legend: u= unchanged, x= unknown.
DS30561B-page 58
1999 Microchip Technology Inc.
PIC12C67X
TABLE 9-6:
RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Condition
Power-on Reset
000h
0001 1xxx
000u uuuu
0001 0uuu
0000 uuuu
uuu0 0uuu
uuu1 0uuu
---- --0-
---- --u-
---- --u-
---- --u-
---- --u-
---- --u-
MCLR Reset during normal operation
MCLR Reset during SLEEP
000h
000h
WDT Reset during normal operation
WDT Wake-up from SLEEP
000h
PC + 1
PC + 1(1)
Interrupt wake-up from SLEEP
Legend: u= unchanged, x= unknown, -= unimplemented bit read as ’0’.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
TABLE 9-7:
Register
INITIALIZATION CON\DITIONS FOR ALL REGISTERS
Power-on Reset
MCLR Resets
WDT Reset
Wake-up via
WDT or Interrupt
W
xxxx xxxx
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
11xx xxxx
uuuu uuuu
0000 0000
uuuu uuuu
0000 0000
000q quuu(3)
uuuu uuuu
11uu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
PC + 1(2)
INDF
TMR0
PCL
STATUS
FSR
uuuq quuu(3)
uuuu uuuu
11uu uuuu
GPIO
PIC12CE67X
GPIO
--xx xxxx
--uu uuuu
--uu uuuu
PIC12C67X
PCLATH
INTCON
PIR1
---0 0000
0000 000x
-0-- ----
0000 0000
1111 1111
--11 1111
-0-- ----
---- --0-
0111 00--
---- -000
---0 0000
0000 000u
-0-- ----
0000 0000
1111 1111
--11 1111
-0-- ----
---- --u-
uuuu uu--
---- -000
---u uuuu
uuuu uqqq(1)
-q-- ----(4)
uuuu uquu(5)
uuuu uuuu
--uu uuuu
-u-- ----
---- --u-
uuuu uu--
---- -uuu
ADCON0
OPTION
TRIS
PIE1
PCON
OSCCAL
ADCON1
Legend:
u
= unchanged,
x = unknown, -= unimplemented bit, read as ’0’, q= value depends on condition.
Note 1: One or more bits in INTCON and PIR1 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
3: See Table 9-5 for reset value for specific condition.
4: If wake-up was due to A/D completing then bit 6 = 1, all other interrupts generating a wake-up will cause bit 6 = u.
5: If wake-up was due to A/D completing then bit 3 = 0, all other interrupts generating a wake-up will cause bit 3 = u.
1999 Microchip Technology Inc.
DS30561B-page 59
PIC12C67X
FIGURE 9-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 9-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30561B-page 60
1999 Microchip Technology Inc.
PIC12C67X
FIGURE 9-10: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
FIGURE 9-11: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
VDD
33k
VDD
10k
D
R
MCLR
R1
4.3k
PIC12C67X
MCLR
PIC12C67X
C
Note 1: This circuit will activate reset when VDD goes
Note 1: External Power-on Reset circuit is required only
if VDD power-up slope is too slow. The diode D
helps discharge the capacitor quickly when VDD
powers down.
below (Vz + 0.7V), where Vz = Zener voltage.
2: Resistors should be adjusted for the character-
istics of the transistor.
2: R < 40 kΩ is recommended to make sure that
voltage drop across R does not violate the
device’s electrical specification.
FIGURE 9-12: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
3: R1 = 100Ω to 1 kΩ will limit any current flowing
into MCLR from external capacitor C, in the
event of MCLR/VPP pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
VDD
VDD
R1
Q1
MCLR
R2
4.3k
PIC12C67X
Note 1: This brown-out circuit is less expensive,
albeit less accurate. Transistor Q1 turns off
when VDD is below a certain level such that:
R1
= 0.7V
VDD •
R1 + R2
2: Resistors should be adjusted for the charac-
teristics of the transistor.
1999 Microchip Technology Inc.
DS30561B-page 61
PIC12C67X
The “return-from-interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
9.5
Interrupts
There are four sources of interrupt:
Interrupt Sources
The GP2/INT, GPIO port change interrupt and the
TMR0 overflow interrupt flags are contained in the
INTCON register.
TMR0 Overflow Interrupt
External Interrupt GP2/INT pin
GPIO Port Change Interrupts (pins GP0, GP1, GP3)
A/D Interrupt
The peripheral interrupt flag ADIF, is contained in the
Special Function Register PIR1. The corresponding
interrupt enable bit is contained in Special Function
Register PIE1, and the peripheral interrupt enable bit is
contained in Special Function Register INTCON.
The Interrupt Control Register (INTCON) records indi-
vidual interrupt requests in flag bits. It also has individ-
ual and global interrupt enable bits.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid repeated interrupts.
Note: Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>),
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt flag bits are set,
regardless of the status of their corresponding mask bit
or the GIE bit. The GIE bit is cleared on reset.
For external interrupt events, such as GPIO change
interrupt, the interrupt latency will be three or four
instruction cycles. The exact latency depends on when
the interrupt event occurs (Figure 9-14). The latency is
the same for one or two cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit or the GIE bit.
FIGURE 9-13: INTERRUPT LOGIC
Wake-up
(If in SLEEP mode)
T0IF
T0IE
INTF
INTE
Interrupt to CPU
GPIF
GPIE
PEIE
ADIF
ADIE
GIE
DS30561B-page 62
1999 Microchip Technology Inc.
PIC12C67X
FIGURE 9-14: INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT
3
4
INT pin
1
1
Interrupt Latency
INTF flag
(INTCON<1>)
5
2
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
0004h
PC
PC+1
PC+1
0005h
Instruction
Inst (PC+1)
—
Inst (0004h)
Inst (PC)
Inst (0005h)
Inst (0004h)
fetched
Instruction
executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC-1)
Note
1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4 TCY where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTRC and EXTRC oscillator modes.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
1999 Microchip Technology Inc.
DS30561B-page 63
PIC12C67X
9.5.1
TMR0 INTERRUPT
9.6
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt (i.e., W register and STATUS
register). This will have to be implemented in software.
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>) (Section 7.0). The flag bit T0IF
(INTCON<2>) will be set, regardless of the state of the
enable bits. If used, this flag must be cleared in software.
Example 9-1 shows the storing and restoring of the
STATUS and W registers. The register, W_TEMP, must
be defined in both banks and must be defined at the
same offset from the bank base address (i.e., if
W_TEMP is defined at 0x20 in bank 0, it must also be
defined at 0xA0 in bank 1).
9.5.2
INT INTERRUPT
External interrupt on GP2/INT pin is edge triggered;
either rising if bit INTEDG (OPTION<6>) is set, or fall-
ing, if the INTEDG bit is clear. When a valid edge
appears on the GP2/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 9.8 for details on SLEEP mode.
Example 9-2 shows the saving and restoring of STA-
TUS and W using RAM locations 0x70 - 0x7F.
W_TEMP is defined at 0x70 and STATUS_TEMP is
defined at 0x71.
The example:
a) Stores the W register.
b) Stores the STATUS register in bank 0.
c) Executes the ISR code.
d) Restores the STATUS register (and bank select
bit).
e) Restores the W register.
f) Returns from interrupt.
9.5.3
GPIO INTCON CHANGE
An input change on GP3, GP1 or GP0 sets flag bit GPIF
(INTCON<0>). The interrupt can be enabled/disabled by
setting/clearing enable bit GPIE (INTCON<3>)
(Section 5.1) . This flag bit GPIF (INTCON<0>) will be
set, regardless of the state of the enable bits. If used, this
flag must be cleared in software.
EXAMPLE 9-1: SAVING STATUS AND W REGISTERS USING GENERAL PURPOSE RAM
(0x20 - 0x6F)
MOVWF
SWAPF
BCF
MOVWF
:
W_TEMP
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;Change to bank zero, regardless of current bank
;Save status to bank zero STATUS_TEMP register
STATUS,W
STATUS,RP0
STATUS_TEMP
:(ISR)
:
SWAPF
STATUS_TEMP,W
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
;Return from interrupt
MOVWF
SWAPF
SWAPF
RETFIE
STATUS
W_TEMP,F
W_TEMP,W
EXAMPLE 9-2: SAVING STATUS AND W REGISTERS USING SHARED RAM (0x70 - 0x7F)
MOVWF
MOVF
MOVWF
:
W_TEMP
STATUS,W
STATUS_TEMP
;Copy W to TEMP register (bank independent)
;Move STATUS register into W
;Save contents of STATUS register
:(ISR)
:
MOVF
MOVWF
SWAPF
SWAPF
RETFIE
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
;Retrieve copy of STATUS register
;Restore pre-isr STATUS register contents
;
;Restore pre-isr W register contents
;Return from interrupt
DS30561B-page 64
1999 Microchip Technology Inc.
PIC12C67X
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out early and generating a premature
device RESET condition.
9.7
Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip RC
oscillator, which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEPinstruction. Dur-
ing normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The WDT can be permanently
disabled by clearing configuration bit WDTE
(Section 9.1).
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
9.7.2
WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., and
max. WDT prescaler), it may take several seconds
before a WDT time-out occurs.
Note: When the prescaler is assigned to the
WDT, always execute a CLRWDTinstruction
before changing the prescale value, other-
wise a WDT reset may occur.
9.7.1
WDT PERIOD
See Example 7-1 and Example 7-2 for changing pres-
caler between WDT and Timer0.
The WDT has a nominal time-out period of 18 ms (with
no prescaler). The time-out periods vary with tempera-
DD
ture, V and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
FIGURE 9-15: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 7-5)
0
Postscaler
8
M
1
U
WDT Timer
X
8 - to - 1 MUX
PS<2:0>
PSA
WDT
Enable Bit
To TMR0 (Figure 7-5)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS<2:0> are bits in the OPTION register.
TABLE 9-8:
Address
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
PWRTE WDTE FOSC2 FOSC1 FOSC0
T0SE PSA PS2 PS1 PS0
Bit 3
Bit 2
Bit 1
Bit 0
Config. bits(1)
OPTION
2007h
81h
MCLRE
GPPU
CP1
CP0
INTEDG T0CS
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 9-1 for operation of these bits. Not all CP0 and CP1 bits are shown.
1999 Microchip Technology Inc.
DS30561B-page 65
PIC12C67X
Other peripherals can not generate interrupts since
during SLEEP, no on-chip Q clocks are present.
9.8
Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOPafter the SLEEPinstruction.
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D, and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input, if enabled, should also be at VDD or VSS
for lowest current consumption. The contribution from
on-chip pull-ups on GPIO should be considered.
9.8.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
The MCLR pin, if enabled, must be at a logic high level
(VIHMC).
• If the interrupt occurs before the the execution of
a SLEEPinstruction, the SLEEPinstruction will
complete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
9.8.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
• If the interrupt occurs during or after the execu-
tion of a SLEEPinstruction, the device will imme-
diately wake-up from sleep . The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
1. External reset input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. GP2/INT interrupt, interrupt GPIO port change
or some Peripheral Interrupts.
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up, is cleared when SLEEPis invoked. The TO
bit is cleared if a WDT time-out occurred (and caused
wake-up).
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDTinstruc-
tion should be executed before a SLEEPinstruction.
The following peripheral interrupt can wake the device
from SLEEP:
1. A/D conversion (when A/D clock source is RC).
DS30561B-page 66
1999 Microchip Technology Inc.
PIC12C67X
FIGURE 9-16: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKOUT(4)
GPIO pin
GPIF flag
(INTCON<0>)
Interrupt Latency
(Note 3)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
Inst(PC - 1)
fetched
Instruction
executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(0004h)
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for INTRC and EXTRC osc mode.
3: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will
continue in-line.
4: CLKOUT is not available in XT, HS or LP osc modes, but shown here for timing reference.
After reset, and if the device is placed into program-
ming/verify mode, the program counter (PC) is at loca-
tion 00h. A 6-bit command is then supplied to the
device. Depending on the command, 14-bits of pro-
gram data are then supplied to or from the device,
depending if the command was a load or a read. For
complete details of serial programming, please refer to
the PIC12C67X Programming Specifications.
9.9
Program Verification/Code Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
Note: Microchip does not recommend code pro-
tecting windowed devices.
9.10
ID Locations
FIGURE 9-17: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
Four memory locations (2000h - 2003h) are designated
as ID locations, where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during program/verify. It is recom-
mended that only the 4 least significant bits of the ID
location are used.
CONNECTION
To Normal
Connections
External
Connector
Signals
PIC12C67X
9.11
In-Circuit Serial Programming
+5V
0V
VDD
PIC12C67X microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming volt-
age. This allows customers to manufacture boards with
unprogrammed devices, and then program the micro-
controller just before shipping the product. This also
allows the most recent firmware or a custom firmware
to be programmed.
VSS
VPP
MCLR/VPP
GP1
GP0
CLK
Data I/O
VDD
To Normal
Connections
The device is placed into a program/verify mode by
holding the GP1 and GP0 pins low, while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). GP1 (clock) becomes the programming
clock and GP0 (data) becomes the programming data.
Both GP0 and GP1 are Schmitt Trigger inputs in this
mode.
1999 Microchip Technology Inc.
DS30561B-page 67
PIC12C67X
NOTES:
DS30561B-page 68
1999 Microchip Technology Inc.
PIC12C67X
The instruction set is highly orthogonal and is grouped
into three basic categories:
10.0 INSTRUCTION SET SUMMARY
Each PIC12C67X instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC12C67X instruc-
tion set summary in Table 10-2 lists byte-oriented, bit-
oriented, and literal and control operations. Table 10-
1 shows the opcode field descriptions.
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.
For byte-oriented instructions, ’f’ represents a file reg-
ister designator and ’d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ’d’ is zero, the result is
placed in the W register. If ’d’ is one, the result is placed
in the file register specified in the instruction.
Table 10-2 lists the instructions recognized by the
MPASM assembler.
For bit-oriented instructions, ’b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ’f’ represents the number of the
file in which the bit is located.
Figure 10-1 shows the three general formats that the
instructions can have.
Note: To maintain upward compatibility with
future PIC12C67X products, do not use the
OPTIONand TRISinstructions.
For literal and control operations, ’k’ represents an
eight or eleven bit constant or literal value.
All examples use the following format to represent a
hexadecimal number:
TABLE 10-1: OPCODE FIELD
DESCRIPTIONS
0xhh
Field
Description
where h signifies a hexadecimal digit.
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
FIGURE 10-1: GENERAL FORMAT FOR
INSTRUCTIONS
Bit address within an 8-bit file register
Literal field, constant data or label
Byte-oriented file register operations
13
8
7
6
0
0
Don’t care location (= 0 or 1)
OPCODE
d
f (FILE #)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
Bit-oriented file register operations
13 10 9
7 6
label Label name
TOS Top of Stack
PC Program Counter
OPCODE
b (BIT #)
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
PCLATH
Program Counter High Latch
GIE Global Interrupt Enable bit
WDT Watchdog Timer/Counter
TO Time-out bit
Literal and control operations
General
13
8
7
0
0
OPCODE
k (literal)
PD Power-down bit
dest Destination either the W register or the specified
k = 8-bit immediate value
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
register file location
[ ] Options
Contents
( )
→
k (literal)
Assigned to
Register bit field
In the set of
< >
User defined term (font is courier)
italics
1999 Microchip Technology Inc.
DS30561B-page 69
PIC12C67X
10.1.3 PCL AS SOURCE OR DESTINATION
10.1
Special Function Registers as
Source/Destination
Read, write or read-modify-write on PCL may have the
following results:
The PIC12C67X’s orthogonal instruction set allows
read and write of all file registers, including special
function registers. There are some special situations
the user should be aware of:
Read PC:
PCL → dest
Write PCL:
PCLATH → PCH;
8-bit destination value → PCL
10.1.1 STATUS AS DESTINATION
Read-Modify-Write: PCL→ ALU operand
PCLATH → PCH;
If an instruction writes to STATUS, the Z, C and DC bits
may be set or cleared as a result of the instruction and
overwrite the original data bits written. For example,
executing CLRF STATUS will clear register STATUS,
and then set the Z bit leaving 0000 0100bin the reg-
ister.
8-bit result → PCL
Where PCH = program counter high byte (not an
addressable register), PCLATH = Program counter
high holding latch, dest = destination, WREG or f.
10.1.4 BIT MANIPULATION
10.1.2 TRIS AS DESTINATION
All bit manipulation instructions are done by first read-
ing the entire register, operating on the selected bit and
writing the result back (read-modify-write). The user
should keep this in mind when operating on special
function registers, such as ports.
Bit 3 of the TRIS register always reads as a '1' since
GP3 is an input only pin. This fact can affect some read-
modify-write operations on the TRIS register.
DS30561B-page 70
1999 Microchip Technology Inc.
PIC12C67X
TABLE 10-2: INSTRUCTION SET SUMMARY
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
Status
Affected
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d Add W and f
f, d AND W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111 dfff ffff C,DC,Z
1,2
1,2
2
0101 dfff ffff
0001 lfff ffff
0001 0000 0011
1001 dfff ffff
0011 dfff ffff
1011 dfff ffff
1010 dfff ffff
1111 dfff ffff
0100 dfff ffff
1000 dfff ffff
0000 lfff ffff
0000 0xx0 0000
1101 dfff ffff
1100 dfff ffff
Z
Z
Z
Z
Z
f
-
Clear f
Clear W
f, d Complement f
f, d Decrement f
f, d Decrement f, Skip if 0
f, d Increment f
f, d Increment f, Skip if 0
f, d Inclusive OR W with f
f, d Move f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
DECFSZ
INCF
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
1,2
f
-
Move W to f
No Operation
f, d Rotate Left f through Carry
f, d Rotate Right f through Carry
f, d Subtract W from f
f, d Swap nibbles in f
f, d Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
0010 dfff ffff C,DC,Z
1110 dfff ffff
0110 dfff ffff Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b Bit Clear f
f, b Bit Set f
f, b Bit Test f, Skip if Clear
f, b Bit Test f, Skip if Set
1
1
01
01
00bb bfff ffff
01bb bfff ffff
10bb bfff ffff
11bb bfff ffff
1,2
1,2
3
1 (2) 01
1 (2) 01
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x kkkk kkkk C,DC,Z
1001 kkkk kkkk
0kkk kkkk kkkk
Z
0000 0110 0100 TO,PD
1kkk kkkk kkkk
Inclusive OR literal with W
Move literal to W
1000 kkkk kkkk
00xx kkkk kkkk
0000 0000 1001
01xx kkkk kkkk
0000 0000 1000
Z
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
0000 0110 0011 TO,PD
110x kkkk kkkk C,DC,Z
1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( i.e., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
1999 Microchip Technology Inc.
DS30561B-page 71
PIC12C67X
10.2
Instruction Descriptions
ADDLW
Add Literal and W
[ label ] ADDLW
0 ≤ k ≤ 255
ANDLW
And Literal with W
[ label ] ANDLW
0 ≤ k ≤ 255
Syntax:
k
Syntax:
k
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
Operation:
Status Affected:
Encoding:
Description:
(W) + k → (W)
C, DC, Z
(W) .AND. (k) → (W)
Z
11
111x
kkkk
kkkk
11
1001
kkkk
kkkk
The contents of the W register are
added to the eight bit literal ’k’ and
the result is placed in the W regis-
ter.
The contents of W register are
AND’ed with the eight bit literal 'k'.
The result is placed in the W reg-
ister.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
ADDLW
0x15
ANDLW
0x5F
Before Instruction
Before Instruction
W
=
0x10
0x25
W
=
0xA3
0x03
After Instruction
After Instruction
W
=
W
=
ADDWF
Syntax:
Add W and f
ANDWF
Syntax:
AND W with f
[ label ] ADDWF f,d
[ label ] ANDWF f,d
Operands:
0 ≤ f ≤ 127
Operands:
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(W) + (f) → (dest)
Operation:
(W) .AND. (f) → (dest)
Status Affected:
Encoding:
C, DC, Z
Status Affected:
Encoding:
Z
00
0111
dfff
ffff
00
0101
dfff
ffff
Description:
Add the contents of the W register
with register ’f’. If ’d’ is 0, the result
is stored in the W register. If ’d’ is
1, the result is stored back in reg-
ister ’f’.
Description:
AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W register. If 'd' is 1, the result
is stored back in register 'f'.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
ANDWF
FSR,
1
ADDWF
FSR,
0
Before Instruction
Before Instruction
W
=
0x17
0xC2
W
=
0x17
0xC2
FSR =
FSR =
After Instruction
After Instruction
W
=
0x17
0x02
W
=
0xD9
0xC2
FSR =
FSR =
DS30561B-page 72
1999 Microchip Technology Inc.
PIC12C67X
BCF
Bit Clear f
BTFSC
Bit Test, Skip if Clear
Syntax:
Operands:
[ label ] BCF f,b
Syntax:
[ label ] BTFSC f,b
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
Status Affected:
Encoding:
Description:
Words:
0 → (f<b>)
Operation:
skip if (f<b>) = 0
None
None
Status Affected:
Encoding:
01
00bb
bfff
ffff
01
10bb
bfff
ffff
Bit ’b’ in register ’f’ is cleared.
Description:
If bit ’b’ in register ’f’ is ’0’, then the
next instruction is skipped.
If bit ’b’ is ’0’, then the next instruc-
tion fetched during the current
instruction execution is discarded,
and a NOPis executed instead,
making this a 2 cycle instruction.
1
1
Cycles:
BCF
FLAG_REG, 7
Example
Before Instruction
FLAG_REG = 0xC7
Words:
Cycles:
Example
1
After Instruction
1(2)
FLAG_REG = 0x47
HERE
FALSE
TRUE
BTFSC
GOTO
•
•
•
FLAG,1
PROCESS_CO
DE
Before Instruction
PC
=
address HERE
After Instruction
if FLAG<1> = 0,
PC =
address TRUE
if FLAG<1>=1,
PC =
address FALSE
BSF
Bit Set f
Syntax:
Operands:
[ label ] BSF f,b
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
Status Affected:
Encoding:
Description:
Words:
1 → (f<b>)
None
01
01bb
bfff
ffff
Bit ’b’ in register ’f’ is set.
1
1
Cycles:
BSF
FLAG_REG,
7
Example
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
1999 Microchip Technology Inc.
DS30561B-page 73
PIC12C67X
CLRF
Clear f
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] CLRF
0 ≤ f ≤ 127
f
Syntax:
[ label ] BTFSS f,b
Operands:
Operation:
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
00h → (f)
1 → Z
Operation:
skip if (f<b>) = 1
None
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
00
0001
1fff
ffff
01
11bb
bfff
ffff
Description:
The contents of register ’f’ are
cleared and the Z bit is set.
Description:
If bit ’b’ in register ’f’ is ’1’, then the
next instruction is skipped.
If bit ’b’ is ’1’, then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a NOPis executed instead,
making this a 2 cycle instruction.
Words:
Cycles:
Example
1
1
CLRF
FLAG_REG
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
Words:
Cycles:
Example
1
=
0x5A
1(2)
=
=
0x00
1
HERE
FALSE
TRUE
BTFSS
GOTO
•
•
•
FLAG,1
PROCESS_CO
DE
Z
Before Instruction
PC
=
address HERE
After Instruction
if FLAG<1> = 0,
PC =
address FALSE
if FLAG<1> = 1,
PC =
address TRUE
CLRW
Clear W
CALL
Call Subroutine
[ label ] CALL k
0 ≤ k ≤ 2047
Syntax:
[ label ] CLRW
None
Syntax:
Operands:
Operation:
Operands:
Operation:
00h → (W)
1 → Z
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Status Affected:
Encoding:
Z
00
0001
0000
0011
Status Affected:
Encoding:
None
Description:
W register is cleared. Zero bit (Z)
is set.
10
0kkk
kkkk
kkkk
Description:
Call Subroutine. First, return
Words:
Cycles:
Example
1
address (PC+1) is pushed onto
the stack. The eleven bit immedi-
ate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALLis
a two cycle instruction.
1
CLRW
Before Instruction
W
=
0x5A
After Instruction
Words:
Cycles:
Example
1
2
W
Z
=
=
0x00
1
HERE
CALL
THER
E
Before Instruction
PC
=
Address HERE
After Instruction
PC
= Address THERE
TOS = Address HERE+1
DS30561B-page 74
1999 Microchip Technology Inc.
PIC12C67X
CLRWDT
Syntax:
Clear Watchdog Timer
[ label ] CLRWDT
None
DECF
Decrement f
Syntax:
Operands:
[ label ] DECF f,d
Operands:
Operation:
0 ≤ f ≤ 127
d
[0,1]
00h → WDT
0 → WDT prescaler,
1 → TO
Operation:
(f) - 1 → (dest)
Status Affected:
Encoding:
Z
1 → PD
00
0011
dfff
ffff
Status Affected:
Encoding:
TO, PD
Description:
Decrement register ’f’. If ’d’ is 0,
the result is stored in the W regis-
ter. If ’d’ is 1, the result is stored
back in register ’f’.
00
0000
0110
0100
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT. Status bits
TO and PD are set.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
DECF
CNT,
1
1
Before Instruction
CNT
CLRWDT
=
=
0x01
0
Before Instruction
Z
WDT counter
=
=
?
After Instruction
CNT
After Instruction
=
=
0x00
1
WDT counter
0x00
Z
WDT prescaler=
0
1
1
TO
PD
=
=
COMF
Complement f
[ label ] COMF f,d
0 ≤ f ≤ 127
DECFSZ
Syntax:
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0 ≤ f ≤ 127
Syntax:
Operands:
Operands:
d
[0,1]
d
[0,1]
Operation:
(f) → (dest)
Operation:
(f) - 1 → (dest); skip if result = 0
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
None
00
1001
dfff
ffff
00
1011
dfff
ffff
Description:
The contents of register ’f’ are
complemented. If ’d’ is 0, the
result is stored in W. If ’d’ is 1, the
result is stored back in register ’f’.
Description:
The contents of register ’f’ are
decremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded. A NOPis executed
instead making it a two cycle
instruction.
Words:
Cycles:
Example
1
1
COMF
REG1,0
Before Instruction
REG1
=
0x13
Words:
Cycles:
Example
1
After Instruction
REG1
=
=
0x13
0xEC
1(2)
W
HERE
DECFSZ
GOTO
CNT, 1
LOOP
CONTINUE •
•
•
Before Instruction
PC
=
address HERE
After Instruction
CNT
if CNT =
PC
if CNT ≠
PC
=
CNT - 1
0,
address CONTINUE
0,
=
=
address HERE+1
1999 Microchip Technology Inc.
DS30561B-page 75
PIC12C67X
GOTO
Unconditional Branch
INCFSZ
Syntax:
Increment f, Skip if 0
[ label ] INCFSZ f,d
0 ≤ f ≤ 127
Syntax:
[ label ] GOTO k
Operands:
Operation:
0 ≤ k ≤ 2047
Operands:
d
[0,1]
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Operation:
(f) + 1 → (dest), skip if result = 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
10
1kkk
kkkk
kkkk
00
1111
dfff
ffff
Description:
GOTOis an unconditional branch.
The eleven bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTOis a two
cycle instruction.
Description:
The contents of register ’f’ are
incremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded. A NOPis executed
instead making it a two cycle
instruction.
Words:
Cycles:
Example
1
2
GOTO THERE
Words:
Cycles:
Example
1
After Instruction
1(2)
PC
=
Address THERE
HERE
INCFSZ
GOTO
CNT,
LOOP
1
CONTINUE •
•
•
Before Instruction
PC
=
address HERE
After Instruction
CNT
if CNT=
=
CNT + 1
0,
PC
if CNT≠
=
address CONTINUE
0,
PC
=
address HERE +1
INCF
Increment f
IORLW
Inclusive OR Literal with W
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
Operands:
[ label ] INCF f,d
Syntax:
0 ≤ f ≤ 127
d
[0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operation:
(f) + 1 → (dest)
(W) .OR. k → (W)
Z
Status Affected:
Encoding:
Z
00
1010
dfff
ffff
11
1000
kkkk
kkkk
Description:
The contents of register ’f’ are
incremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
The contents of the W register are
OR’ed with the eight bit literal 'k'.
The result is placed in the W reg-
ister.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
IORLW
0x35
INCF
CNT,
1
Before Instruction
Before Instruction
CNT
W
=
0x9A
=
=
0xFF
0
After Instruction
Z
W
Z
=
=
0xBF
1
After Instruction
CNT
=
=
0x00
1
Z
DS30561B-page 76
1999 Microchip Technology Inc.
PIC12C67X
IORWF
Inclusive OR W with f
[ label ] IORWF f,d
0 ≤ f ≤ 127
MOVF
Move f
Syntax:
Syntax:
Operands:
[ label ] MOVF f,d
Operands:
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(W) .OR. (f) → (dest)
Operation:
(f) → (dest)
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
Z
00
0100
dfff
ffff
00
1000
dfff
ffff
Description:
Inclusive OR the W register with
register ’f’. If ’d’ is 0, the result is
placed in the W register. If ’d’ is 1,
the result is placed back in regis-
ter ’f’.
Description:
The contents of register f are
moved to a destination dependant
upon the status of d. If d = 0, des-
tination is W register. If d = 1, the
destination is file register f itself.
d = 1 is useful to test a file register
since status flag Z is affected.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
IORWF
RESULT, 0
Before Instruction
MOVF
FSR,
0
RESULT =
0x13
0x91
After Instruction
W
=
W = value in FSR register
= 1
After Instruction
Z
RESULT =
0x13
0x93
1
W
Z
=
=
MOVWF
Move W to f
[ label ] MOVWF
0 ≤ f ≤ 127
(W) → (f)
MOVLW
Move Literal to W
[ label ] MOVLW k
0 ≤ k ≤ 255
Syntax:
f
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
Operation:
Status Affected:
Encoding:
Description:
k → (W)
None
None
00
0000
1fff
ffff
11
00xx
kkkk
kkkk
Move data from W register to reg-
ister 'f'.
The eight bit literal ’k’ is loaded
into W register. The don’t cares
will assemble as 0’s.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
MOVWF
OPTION
Before Instruction
MOVLW
0x5A
OPTION =
0xFF
0x4F
W
=
After Instruction
After Instruction
W
=
0x5A
OPTION =
0x4F
0x4F
W
=
1999 Microchip Technology Inc.
DS30561B-page 77
PIC12C67X
NOP
No Operation
RETFIE
Return from Interrupt
[ label ] RETFIE
None
Syntax:
[ label ] NOP
None
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Operands:
Operation:
No operation
None
TOS → PC,
1 → GIE
Status Affected:
Encoding:
None
00
0000
0xx0
0000
00
0000
0000
1001
No operation.
Description:
Return from Interrupt. Stack is
POPed and Top of Stack (TOS) is
loaded in the PC. Interrupts are
enabled by setting Global Inter-
rupt Enable bit, GIE
(INTCON<7>). This is a two cycle
instruction.
1
Cycles:
1
NOP
Example
Words:
Cycles:
Example
1
2
RETFIE
After Interrupt
PC
=
TOS
1
GIE =
OPTION
Syntax:
Load Option Register
[ label ] OPTION
None
RETLW
Return with Literal in W
[ label ] RETLW k
0 ≤ k ≤ 255
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
Operation:
(W) → OPTION
None
k → (W);
TOS → PC
Status Affected:
Encoding:
None
00
0000
0110
0010
11
01xx
kkkk
kkkk
The contents of the W register are
loaded in the OPTION register.
This instruction is supported for
code compatibility with PIC16C5X
products. Since OPTION is a read-
able/writable register, the user can
directly address it.
Description:
The W register is loaded with the
eight bit literal ’k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two cycle instruction.
Words:
Cycles:
Example
1
2
Words:
Cycles:
Example
1
1
CALL TABLE;W contains
table
To maintain upward compatibility
with future PIC12C67X products,
do not use this instruction.
;offset value
TABLE
•
•
•
;W now has table value
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2
;
•
•
•
RETLW kn ; End of table
Before Instruction
W
=
0x07
After Instruction
W
=
value of k8
DS30561B-page 78
1999 Microchip Technology Inc.
PIC12C67X
RETURN
Return from Subroutine
[ label ] RETURN
None
RRF
Rotate Right f through Carry
[ label ] RRF f,d
0 ≤ f ≤ 127
Syntax:
Syntax:
Operands:
Operands:
Operation:
Status Affected:
Encoding:
Description:
d
[0,1]
TOS → PC
Operation:
See description below
C
None
Status Affected:
Encoding:
00
0000
0000
1000
00
1100
dfff
ffff
Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two cycle
instruction.
Description:
The contents of register ’f’ are
rotated one bit to the right through
the Carry Flag. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
Words:
Cycles:
Example
1
2
C
Register f
RETURN
Words:
Cycles:
Example
1
1
After Interrupt
PC
=
TOS
RRF
REG1,
0
Before Instruction
REG1
=
=
1110 0110
0
C
After Instruction
REG1
=
=
=
1110 0110
0111 0011
0
W
C
RLF
Rotate Left f through Carry
SLEEP
Syntax:
Operands:
[ label ]
RLF f,d
Syntax:
[ label ]
SLEEP
0 ≤ f ≤ 127
Operands:
Operation:
None
d
[0,1]
00h → WDT,
0 → WDT prescaler,
1 → TO,
Operation:
See description below
C
Status Affected:
Encoding:
0 → PD
00
1101
dfff
ffff
Status Affected:
Encoding:
TO, PD
Description:
The contents of register ’f’ are
rotated one bit to the left through
the Carry Flag. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is stored back in reg-
ister ’f’.
00
0000
0110
0011
Description:
The power-down status bit, PD is
cleared. Time-out status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
C
Register f
Words:
Cycles:
Example
1
1
Words:
1
Cycles:
Example:
1
RLF
REG1,0
SLEEP
Before Instruction
REG1
=
=
1110 0110
0
C
After Instruction
REG1
=
=
=
1110 0110
1100 1100
1
W
C
1999 Microchip Technology Inc.
DS30561B-page 79
PIC12C67X
SUBLW
Subtract W from Literal
SUBWF
Subtract W from f
Syntax:
[ label ]
Syntax:
[ label ]
SUBLW k
SUBWF f,d
Operands:
Operation:
0 ≤ k ≤ 255
Operands:
Operation:
0 ≤ f ≤ 127
[0,1]
d
k - (W) → (W)
(f) - (W) → (dest)
Status
Affected:
C, DC, Z
Status
Affected:
C, DC, Z
Encoding:
11
110x
kkkk
kkkk
Encoding:
00
0010
dfff
ffff
Description:
The W register is subtracted (2’s
complement method) from the eight
bit literal 'k'. The result is placed in
the W register.
Description:
Subtract (2’s complement method) W
register from register 'f'. If 'd' is 0, the
result is stored in the W register. If 'd'
is 1, the result is stored back in regis-
ter 'f'.
Words:
1
1
Cycles:
Words:
1
1
Example 1:
SUBLW
0x02
Cycles:
Before Instruction
Example 1:
SUBWF
REG1,1
W
C
=
=
1
?
Before Instruction
REG1
W
C
=
=
=
3
2
?
After Instruction
W
C
=
=
1
1; result is positive
After Instruction
Example 2:
Example 3:
Before Instruction
REG1
W
C
=
=
=
1
2
W
C
=
=
2
?
1; result is positive
Example 2:
Before Instruction
After Instruction
REG1
W
C
=
=
=
2
2
?
W
C
=
=
0
1; result is zero
Before Instruction
After Instruction
W
C
=
=
3
?
REG1
W
C
=
=
=
0
2
After Instruction
1; result is zero
W
C
=
=
0xFF
0; result is nega-
Example 3:
Before Instruction
REG1
W
C
=
=
=
1
2
?
tive
After Instruction
REG1
W
C
=
=
=
0xFF
2
0; result is negative
DS30561B-page 80
1999 Microchip Technology Inc.
PIC12C67X
SWAPF
Syntax:
Swap Nibbles in f
[ label ] SWAPF f,d
0 ≤ f ≤ 127
XORLW
Exclusive OR Literal with W
Syntax:
[ label ]
XORLW k
Operands:
Operands:
0 ≤ k ≤ 255
d
[0,1]
Operation:
(W) .XOR. k → (W)
Operation:
(f<3:0>) → (dest<7:4>),
(f<7:4>) → (dest<3:0>)
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
None
11
1010 kkkk kkkk
00
1110
dfff
ffff
Description:
The contents of the W register
are XOR’ed with the eight bit lit-
eral 'k'. The result is placed in the
W register.
Description:
The upper and lower nibbles of
register ’f’ are exchanged. If ’d’ is
0, the result is placed in W regis-
ter. If ’d’ is 1, the result is placed in
register ’f’.
Words:
1
1
Cycles:
Example:
Words:
Cycles:
Example
1
1
XORLW
0xAF
Before Instruction
SWAPF
REG,
0
W
=
0xB5
0x1A
Before Instruction
REG1
After Instruction
=
0xA5
W
=
After Instruction
REG1
W
=
=
0xA5
0x5A
XORWF
Syntax:
Exclusive OR W with f
[ label ] XORWF f,d
0 ≤ f ≤ 127
TRIS
Load TRIS Register
Syntax:
[ label ] TRIS
f
Operands:
Operands:
Operation:
Status Affected:
Encoding:
Description:
5 ≤ f ≤ 7
d
[0,1]
(W) → TRIS register f;
Operation:
(W) .XOR. (f) → (dest)
None
Status Affected:
Encoding:
Z
00
0000 0110
0fff
00
0110
dfff
ffff
The instruction is supported for
code compatibility with the
PIC16C5X products. Since TRIS
registers are readable and writ-
able, the user can directly address
them.
Description:
Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0, the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
REG
XORWF
1
To maintain upward compatibility
with future PIC12C67X products,
do not use this instruction.
Before Instruction
REG
W
=
=
0xAF
0xB5
After Instruction
REG
W
=
=
0x1A
0xB5
1999 Microchip Technology Inc.
DS30561B-page 81
PIC12C67X
NOTES:
DS30561B-page 82
1999 Microchip Technology Inc.
PIC12C67X
MPLAB allows you to:
11.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASM Assembler
- absolute listing file
- object code
- MPLAB-C17 and MPLAB-C18 C Compilers
- MPLINK/MPLIB Linker/Librarian
• Simulators
The ability to use MPLAB with Microchip’s simulator,
MPLAB-SIM, allows a consistent platform and the abil-
ity to easily switch from the cost-effective simulator to
the full featured emulator with minimal retraining.
- MPLAB-SIM Software Simulator
• Emulators
- MPLAB-ICE Real-Time In-Circuit Emulator
- PICMASTER®/PICMASTER-CE In-Circuit
11.2
MPASM Assembler
Emulator
MPASM is a full featured universal macro assembler for
all PICmicro MCU’s. It can produce absolute code
directly in the form of HEX files for device program-
mers, or it can generate relocatable objects for
MPLINK.
- ICEPIC™
• In-Circuit Debugger
- MPLAB-ICD for PIC16F877
• Device Programmers
MPASM has a command line interface and a Windows
shell and can be used as a standalone application on a
Windows 3.x or greater system. MPASM generates
relocatable object files, Intel standard HEX files, MAP
files to detail memory usage and symbol reference, an
absolute LST file which contains source lines and gen-
erated machine code, and a COD file for MPLAB
debugging.
- PRO MATE II Universal Programmer
- PICSTART Plus Entry-Level Prototype
Programmer
• Low-Cost Demonstration Boards
- SIMICE
- PICDEM-1
- PICDEM-2
- PICDEM-3
MPASM features include:
- PICDEM-17
- SEEVAL
• MPASM and MPLINK are integrated into MPLAB
projects.
- KEELOQ
• MPASM allows user defined macros to be created
for streamlined assembly.
11.1
MPLAB Integrated Development
Environment Software
• MPASM allows conditional assembly for multi pur-
pose source files.
• MPASM directives allow complete control over the
assembly process.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a Windows -based applica-
tion which contains:
11.3
MPLAB-C17 and MPLAB-C18
C Compilers
• Multiple functionality
- editor
The MPLAB-C17 and MPLAB-C18 Code Development
Systems are complete ANSI ‘C’ compilers and inte-
grated development environments for Microchip’s
PIC17CXXX and PIC18CXXX family of microcontrol-
lers, respectively. These compilers provide powerful
integration capabilities and ease of use not found with
other compilers.
- simulator
- programmer (sold separately)
- emulator (sold separately)
• A full featured editor
• A project manager
• Customizable tool bar and key mapping
• A status bar
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• On-line help
1999 Microchip Technology Inc.
DS30561B-page 83
PIC12C67X
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different pro-
cessors. The universal architecture of the MPLAB-ICE
allows expansion to support new PICmicro microcon-
trollers.
11.4
MPLINK/MPLIB Linker/Librarian
MPLINK is a relocatable linker for MPASM and
MPLAB-C17 and MPLAB-C18. It can link relocatable
objects from assembly or C source files along with pre-
compiled libraries using directives from a linker script.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced fea-
tures that are generally found on more expensive devel-
opment tools. The PC platform and Microsoft® Windows
3.x/95/98 environment were chosen to best make these
features available to you, the end user.
MPLIB is a librarian for pre-compiled code to be used
with MPLINK. When a routine from a library is called
from another source file, only the modules that contains
that routine will be linked in with the application. This
allows large libraries to be used efficiently in many dif-
ferent applications. MPLIB manages the creation and
modification of library files.
MPLAB-ICE 2000 is a full-featured emulator system
with enhanced trace, trigger, and data monitoring fea-
tures. Both systems use the same processor modules
and will operate across the full operating speed range
of the PICmicro MCU.
MPLINK features include:
• MPLINK works with MPASM and MPLAB-C17
and MPLAB-C18.
• MPLINK allows all memory areas to be defined as
sections to provide link-time flexibility.
11.7
PICMASTER/PICMASTER CE
The PICMASTER system from Microchip Technology is
a full-featured, professional quality emulator system.
This flexible in-circuit emulator provides a high-quality,
universal platform for emulating Microchip 8-bit
PICmicro microcontrollers (MCUs). PICMASTER sys-
tems are sold worldwide, with a CE compliant model
available for European Union (EU) countries.
MPLIB features include:
• MPLIB makes linking easier because single librar-
ies can be included instead of many smaller files.
• MPLIB helps keep code maintainable by grouping
related modules together.
• MPLIB commands allow libraries to be created
and modules to be added, listed, replaced,
deleted, or extracted.
11.8
ICEPIC
ICEPIC is a low-cost in-circuit emulation solution for the
Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X, and PIC16CXXX families of 8-bit one-time-
programmable (OTP) microcontrollers. The modular
system can support different subsets of PIC16C5X or
PIC16CXXX products through the use of
interchangeable personality modules or daughter
boards. The emulator is capable of emulating without
target application circuitry being present.
11.5
MPLAB-SIM Software Simulator
The MPLAB-SIM Software Simulator allows code
development in a PC host environment by simulating
the PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file or user-defined key press to any of the pins. The
execution can be performed in single step, execute until
break, or trace mode.
11.9
MPLAB-ICD In-Circuit Debugger
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPLAB-C18 and MPASM. The Soft-
ware Simulator offers the flexibility to develop and
debug code outside of the laboratory environment mak-
ing it an excellent multi-project software development
tool.
Microchip’s In-Circuit Debugger, MPLAB-ICD, is a pow-
erful, low-cost run-time development tool. This tool is
based on the flash PIC16F877 and can be used to
develop for this and other PICmicro microcontrollers
from the PIC16CXXX family. MPLAB-ICD utilizes the
In-Circuit Debugging capability built into the
PIC16F87X. This feature, along with Microchip’s In-Cir-
cuit Serial Programming protocol, offers cost-effective
in-circuit flash programming and debugging from the
graphical user interface of the MPLAB Integrated
Development Environment. This enables a designer to
develop and debug source code by watching variables,
single-stepping and setting break points. Running at
full speed enables testing hardware in real-time. The
MPLAB-ICD is also a programmer for the flash
PIC16F87X family.
11.6
MPLAB-ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers (MCUs). Software control of
MPLAB-ICE is provided by the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
DS30561B-page 84
1999 Microchip Technology Inc.
PIC12C67X
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and download the
firmware to the emulator for testing. Additional proto-
type area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
11.10 PRO MATE II Universal Programmer
The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for instructions and error messages,
keys to enter commands and a modular detachable
socket assembly to support various package types. In
stand-alone mode the PRO MATE II can read, verify or
program PICmicro devices. It can also set code-protect
bits in this mode.
11.14 PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-Plus, and easily test firmware.
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connec-
tion to an LCD module and a keypad.
11.11 PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient.
PICSTART Plus supports all PICmicro devices with up
to 40 pins. Larger pin count devices such as the
PIC16C92X, and PIC17C76X may be supported with
an adapter socket. PICSTART Plus is CE compliant.
11.12 SIMICE Entry-Level
Hardware Simulator
SIMICE is an entry-level hardware development sys-
tem designed to operate in a PC-based environment
with Microchip’s simulator MPLAB-SIM. Both SIMICE
and MPLAB-SIM run under Microchip Technology’s
MPLAB Integrated Development Environment (IDE)
software. Specifically, SIMICE provides hardware sim-
ulation for Microchip’s PIC12C5XX, PIC12CE5XX, and
PIC16C5X families of PICmicro 8-bit microcontrollers.
SIMICE works in conjunction with MPLAB-SIM to pro-
vide non-real-time I/O port emulation. SIMICE enables
a developer to run simulator code for driving the target
system. In addition, the target system can provide input
to the simulator code. This capability allows for simple
and interactive debugging without having to manually
generate MPLAB-SIM stimulus files. SIMICE is a valu-
able debugging tool for entry-level system develop-
ment.
11.15 PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an addi-
tional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
11.13 PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
1999 Microchip Technology Inc.
DS30561B-page 85
PIC12C67X
11.16 PICDEM-17
The PICDEM-17 is an evaluation board that demon-
strates the capabilities of several Microchip microcon-
trollers,
including
PIC17C752,
PIC17C756,
PIC17C762, and PIC17C766. All necessary hardware
is included to run basic demo programs, which are sup-
plied on a 3.5-inch disk. A programmed sample is
included, and the user may erase it and program it with
the other sample programs using the PRO MATE II or
PICSTART Plus device programmers and easily debug
and test the sample code. In addition, PICDEM-17 sup-
ports down-loading of programs to and executing out of
external FLASH memory on board. The PICDEM-17 is
also usable with the MPLAB-ICE or PICMASTER emu-
lator, and all of the sample programs can be run and
modified using either emulator. Additionally, a gener-
ous prototype area is available for user hardware.
11.17 SEEVAL Evaluation and Programming
System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in trade-
off analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
11.18 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS eval-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
DS30561B-page 86
1999 Microchip Technology Inc.
PIC12C67X
TABLE 11-1: DEVELOPMENT TOOLS FROM MICROCHIP
0
2 5 P 1 C M
X X X C R M F
X
H C S X X
X X C 9 3
C 5 X 2 X /
C 4 X 2 X /
2 X X 1 8 C I C P
X X 7 1 7 C I C P
X 4 C 7 C 1 P I
X X 9 1 6 C I C P
X 8 X 6 1 F C I P
X 8 C 6 C 1 P I
X X 7 1 6 C I C P
X 7 C 6 C 1 P I
X 2 6 F 6 C 1 P I
X X C 6 X C 1 P I
X 6 C 6 C 1 P I
X 5 C 6 C 1 P I
0
4 0 1 0 C I P
X X C 2 X C 1 P I
l s o o T e w f a t o r S s o t r a l
E m r u g g b e e u D s r e m m r a g o P r
s
K l a i t E d v n a s d r a B o o m D e
1999 Microchip Technology Inc.
DS30561B-page 87
PIC12C67X
NOTES:
DS30561B-page 88
1999 Microchip Technology Inc.
PIC12C67X
12.0 ELECTRICAL SPECIFICATIONS FOR PIC12C67X
Absolute Maximum Ratings †
Ambient temperature under bias...............................................................................................................–40° to +125°C
Storage temperature ............................................................................................................................. –65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR)................................................... –0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.0V
Voltage on MCLR with respect to VSS (Note 2)..................................................................................................0 to +14V
Total power dissipation (Note 1)...........................................................................................................................700 mW
Maximum current out of VSS pin ...........................................................................................................................200 mA
Maximum current into VDD pin ..............................................................................................................................150 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. ± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by GPIO pins combined...................................................................................................100 mA
Maximum current sourced by GPIO pins combined..............................................................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1999 Microchip Technology Inc.
DS30561B-page 89
PIC12C67X
FIGURE 12-1: PIC12C67X VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA < 0°C, +70°C <TA ≤ +125°C
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
FIGURE 12-2: PIC12C67X VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +70°C
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
DS30561B-page 90
1999 Microchip Technology Inc.
PIC12C67X
FIGURE 12-3: PIC12LC67X VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +85°C
6.0
5.5
5.0
4.5
4.0
3.5
3.0
VDD
(Volts)
2.5
2.0
20
0
4
10
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
1999 Microchip Technology Inc.
DS30561B-page 91
PIC12C67X
12.1
DC Characteristics:
PIC12C671/672 (Commercial, Industrial, Extended)
PIC12CE673/674 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise specified)
DC CHARACTERISTICS
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Typ(1)
Parm
No.
Characteristic
Sym Min
Max Units
Conditions
D001
D002
Supply Voltage
VDD
VDR
3.0
5.5
V
V
RAM Data Retention
Voltage(2)
1.5*
Device in SLEEP mode
D003
D004
VDD Start Voltage to ensure VPOR
Power-on Reset
VSS
V
See section on Power-on Reset for details
VDD Rise Rate to ensure
Power-on Reset
SVDD 0.05*
V/ms See section on Power-on Reset for details
Supply Current(3)
D010
IDD
—
—
—
—
—
—
1.2
1.2
2.2
19
2.5
2.5
8
mA FOSC = 4MHz, VDD = 3.0V
XT and EXTRC mode (Note 4)
mA FOSC = 4MHz, VDD = 3.0V
INTRC mode (Note 6)
mA FOSC = 10MHz, VDD = 5.5V
HS mode
µA FOSC = 32kHz, VDD = 3.0V, WDT disabled
LP mode, Commercial Temperature
µA FOSC = 32kHz, VDD = 3.0V, WDT disabled
LP mode, Industrial Temperature
µA FOSC = 32kHz, VDD = 3.0V, WDT disabled
LP mode, Extended Temperature
D010C
D010A
29
37
60
19
32
Power-down Current(5)
Watchdog Timer Current
D020
D021
D021B
IPD
—
—
—
—
—
—
0.25
0.25
2
0.5
0.8
3
6
7
14
8
9
16
µA VDD = 3.0V, Commercial, WDT disabled
µA VDD = 3.0V, Industrial, WDT disabled
µA VDD = 3.0V, Extended, WDT disabled
µA VDD = 5.5V, Commercial, WDT disabled
µA VDD = 5.5V, Industrial, WDT disabled
µA VDD = 5.5V, Extended, WDT disabled
D022
D028
∆IWDT
∆IEE
—
—
—
2.2
2.2
4
5
6
11
µA VDD = 3.0V, Commercial
µA VDD = 3.0V, Industrial
µA VDD = 3.0V, Extended
Supply Current(3)
During read/write to
EEPROM peripheral
—
0.1
0.2
mA FOSC = 4MHz, VDD = 5.5V, SCL = 400kHz
For PIC12CE673/674 only
*
These parameters are characterized but not tested.
Note 1: Data in Typical ("Typ") column is based on characterization results at 25°C. This data is for design guidance only and is not
tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator
type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD,
MCLR = VDD; WDT disabled.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.
4: For EXTRC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the
formula:
Ir = VDD/2REXT (mA) with REXT in kOhm.
5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the
part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
6: INTRC calibration value is for 4MHz nominal at 5V, 25°C.
DS30561B-page 92
1999 Microchip Technology Inc.
PIC12C67X
Standard Operating Conditions (unless otherwise specified)
DC CHARACTERISTICS
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Typ(1)
Parm
No.
Characteristic
Sym Min
Max Units
Conditions
LP Oscillator Operating
Frequency
INTRC/EXTRC Oscillator
Operating Frequency
XT Oscillator Operating
Frequency
FOSC
0
—
0
200 kHz All temperatures
4(6)
4
MHz All temperatures
MHz All temperatures
MHz All temperatures
HS Oscillator Operating
Frequency
0
10
*
These parameters are characterized but not tested.
Note 1: Data in Typical ("Typ") column is based on characterization results at 25°C. This data is for design guidance only and is not
tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator
type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD,
MCLR = VDD; WDT disabled.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.
4: For EXTRC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the
formula:
Ir = VDD/2REXT (mA) with REXT in kOhm.
5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the
part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
6: INTRC calibration value is for 4MHz nominal at 5V, 25°C.
1999 Microchip Technology Inc.
DS30561B-page 93
PIC12C67X
12.2
DC Characteristics:
PIC12LC671/672 (Commercial, Industrial)
PIC12LCE673/674 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating temperature 0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
DC CHARACTERISTICS
Param
No.
Characteristic
Sym Min Typ† Max Units
Conditions
D001
D002
Supply Voltage
RAM Data Retention
Voltage(2)
VDD
VDR
2.5
5.5
V
V
1.5*
VSS
Device in SLEEP mode
See section on Power-on Reset for details
D003
D004
VDD Start Voltage to
ensure Power-on Reset
VPOR
V
VDD Rise Rate to ensure SVDD 0.05*
V/ms See section on Power-on Reset for details
Power-on Reset
Supply Current(3)
D010
IDD
—
—
—
0.4
0.4
15
2.1
2.1
33
mA FOSC = 4MHz, VDD = 2.5V
XT and EXTRC mode (Note 4)
mA FOSC = 4MHz, VDD = 2.5V
INTRC mode (Note 6)
µA FOSC = 32kHz, VDD = 2.5V, WDT disabled
LP mode, Industrial Temperature
D010C
D010A
Power-down Current(5)
D020
D021
D021B
IPD
—
—
0.2
0.2
5
6
µA VDD = 2.5V, Commercial
µA VDD = 2.5V, Industrial
Watchdog Timer Current ∆IWDT
—
2.0
2.0
4
6
µA VDD = 2.5V, Commercial
µA VDD = 2.5V, Industrial
LP Oscillator Operating FOSC
Frequency
INTRC/EXTRC Oscillator
Operating Frequency
XT Oscillator Operating
Frequency
0
—
0
200 kHz All temperatures
4(6)
MHz All temperatures
MHz All temperatures
MHz All temperatures
4
HS Oscillator Operating
Frequency
0
10
*
These parameters are characterized but not tested.
Note 1: Data in Typical ("Typ") column is based on characterization results at 25°C. This data is for design guidance only and is not
tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator
type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD,
MCLR = VDD; WDT disabled.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.
4: For EXTRC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the
formula:
Ir = VDD/2REXT (mA) with REXT in kOhm.
5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the
part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
6: INTRC calibration value is for 4MHz nominal at 5V, 25°C.
DS30561B-page 94
1999 Microchip Technology Inc.
PIC12C67X
12.3
DC CHARACTERISTICS:
PIC12C671/672 (Commercial, Industrial, Extended)
PIC12CE673/674 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise specified)
Operating temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
DC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 12.1 and
Section 12.2.
Param
No.
Characteristic
Sym
Min
Typ† Max Units
Conditions
Input Low Voltage
I/O ports
VIL
D030
D031
with TTL buffer
VSS
VSS
VSS
VSS
0.8V
V
V
V
V
For 4.5V ≤ VDD ≤ 5.5V
—
—
—
—
0.15VDD
0.2VDD
0.2VDD
otherwise
with Schmitt Trigger buffer
D032 MCLR, GP2/T0CKI/AN2/INT
(in EXTRC mode)
D033 OSC1 (in EXTRC mode)
VSS
VSS
0.2VDD
0.3VDD
Note 1
Note 1
—
—
D033 OSC1 (in XT, HS, and LP)
Input High Voltage
I/O ports
V
VIH
—
—
—
—
—
—
—
D040
D040A
D041
with TTL buffer
2.0V
0.25VDD + 0.8V
0.8VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
4.5V ≤ VDD ≤ 5.5V
otherwise
with Schmitt Trigger buffer
For entire VDD range
D042 MCLR, GP2/T0CKI/AN2/INT
D042A OSC1 (XT, HS, and LP)
D043 OSC1 (in EXTRC mode)
Input Leakage Current (Notes 2, 3)
D060 I/O ports
0.8VDD
0.7VDD
Note 1
0.9VDD
IIL
+1
µA VSS ≤ VPIN ≤ VDD, Pin at
hi-impedance
—
—
D061 GP3/MCLR (Note 5)
D061A GP3 (Note 6)
D062 GP2/T0CKI
+30
+5
µA VSS ≤ VPIN ≤ VDD
µA VSS ≤ VPIN ≤ VDD
µA VSS ≤ VPIN ≤ VDD
—
—
—
—
+5
+5
D063 OSC1
µA VSS ≤ VPIN ≤ VDD, XT, HS, and
LP osc configuration
D070 GPIO weak pull-up current (Note 4)
MCLR pull-up current
IPUR
50
250
400
30
µA VDD = 5V, VPIN = VSS
µA VDD = 5V, VPIN = VSS
—
—
—
Output Low Voltage
D080 I/O ports
VOL
0.6
0.6
0.6
0.6
V
V
V
V
IOL = 8.5 mA, VDD = 4.5V,
–40°C to +85°C
—
—
—
—
—
—
—
—
D080A
IOL = 7.0 mA, VDD = 4.5V,
–40°C to +125°C
D083 OSC2/CLKOUT
D083A
IOL = 1.6 mA, VDD = 4.5V,
–40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
–40°C to +125°C
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C67X
be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: Does not include GP3. For GP3 see parameters D061 and D061A.
5: This spec. applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal pull-up
enabled.
6: This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit
is higher than the standard I/O logic.
1999 Microchip Technology Inc.
DS30561B-page 95
PIC12C67X
Standard Operating Conditions (unless otherwise specified)
Operating temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
DC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 12.1 and
Section 12.2.
Param
No.
Characteristic
Output High Voltage
Sym
Min
Typ† Max Units
Conditions
D090 I/O ports (Note 3)
VOH
VDD - 0.7
VDD - 0.7
VDD - 0.7
VDD - 0.7
V
V
V
V
IOH = -3.0 mA, VDD = 4.5V,
–40°C to +85°C
—
—
—
—
—
—
—
—
D090A
IOH = -2.5 mA, VDD = 4.5V,
–40°C to +125°C
D092 OSC2/CLKOUT
D092A
IOH = 1.3 mA, VDD = 4.5V,
–40°C to +85°C
IOH = 1.0 mA, VDD = 4.5V,
–40°C to +125°C
Capacitive Loading Specs on
Output Pins
D100 OSC2 pin
COSC2
15
50
pF In XT and LP modes when
—
—
—
—
external clock is used to drive
OSC1.
D101 All I/O pins
CIO
pF
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C67X
be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: Does not include GP3. For GP3 see parameters D061 and D061A.
5: This spec. applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal pull-up
enabled.
6: This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit
is higher than the standard I/O logic.
DS30561B-page 96
1999 Microchip Technology Inc.
PIC12C67X
12.4
DC CHARACTERISTICS:
PIC12LC671/672 (Commercial, Industrial)
PIC12LCE673/674 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
DC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 12.1 and
Section 12.2.
Param
No.
Characteristic
Sym
Min
Typ† Max
Units
Conditions
Input Low Voltage
I/O ports
VIL
D030
with TTL buffer
VSS
VSS
VSS
VSS
—
—
—
—
0.8V
V
V
V
V
For 4.5V ≤ VDD ≤ 5.5V
0.15VDD
0.2VDD
0.2VDD
otherwise
D031
D032
with Schmitt Trigger buffer
MCLR, GP2/T0CKI/AN2/INT
(in EXTRC mode)
D033
D033
OSC1 (in EXTRC mode)
OSC1 (in XT, HS, and LP)
Input High Voltage
I/O ports
VSS
VSS
—
—
0.2VDD
0.3VDD
V
V
Note 1
Note 1
VIH
—
—
—
—
—
—
—
D040
D040A
D041
D042
with TTL buffer
2.0V
0.25VDD + 0.8V
0.8VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
4.5V ≤ VDD ≤ 5.5V
otherwise
with Schmitt Trigger buffer
MCLR, GP2/T0CKI/AN2/INT
For entire VDD range
0.8VDD
D042A OSC1 (XT, HS, and LP)
0.7VDD
Note 1
D043
D060
D061
OSC1 (in EXTRC mode)
Input Leakage Current (Notes 2, 3)
I/O ports
0.9VDD
IIL
—
—
+1
µA Vss ≤ VPIN ≤ VDD, Pin at
hi-impedance
GP3/MCLR (Note 5)
+30
+5
µA Vss ≤ VPIN ≤ VDD
D061A GP3 (Note 6)
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD
D062
D063
GP2/T0CKI
OSC1
—
—
—
—
+5
+5
µA Vss ≤ VPIN ≤ VDD, XT, HS and
LP osc configuration
D070
GPIO weak pull-up current (Note 4)
MCLR pull-up current
Output Low Voltage
I/O ports
IPUR
50
—
250
—
400
30
µA VDD = 5V, VPIN = VSS
µA VDD = 5V, VPIN = VSS
—
D080
D080A
D083
D083A
†
VOL
—
—
—
—
—
—
—
—
0.6
0.6
0.6
0.6
V
V
V
V
IOL = 8.5 mA, VDD = 4.5V,
–40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
–40°C to +125°C
OSC2/CLKOUT
IOL = TBD, VDD = 4.5V,
–40°C to +85°C
IOL = TBD, VDD = 4.5V,
–40°C to +125°C
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C67X
be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent nor-
mal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: Does not include GP3. For GP3 see parameters D061 and D061A.
5: This spec. applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal pull-up
enabled.
6: This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit is
higher than the standard I/O logic.
1999 Microchip Technology Inc.
DS30561B-page 97
PIC12C67X
Standard Operating Conditions (unless otherwise specified)
Operating temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
DC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 12.1 and
Section 12.2.
Param
No.
Characteristic
Sym
Min
Typ† Max
Units
Conditions
Output High Voltage
D090
I/O ports (Note 3)
VOH
VDD - 0.7
VDD - 0.7
VDD - 0.7
VDD - 0.7
—
—
—
—
—
—
—
—
V
V
V
V
IOH = -3.0 mA, VDD = 4.5V,
–40°C to +85°C
D090A
D092
IOH = -2.5 mA, VDD = 4.5V,
–40°C to +125°C
IOH = TBD, VDD = 4.5V,
–40°C to +85°C
OSC2/CLKOUT
D092A
IOH = TBD, VDD = 4.5V,
–40°C to +125°C
Capacitive Loading Specs on
Output Pins
D100
OSC2 pin
COSC2
CIO
—
—
—
—
15
50
pF In XT and LP modes when
external clock is used to drive
OSC1.
pF
D101
†
All I/O pins
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C67X
be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent nor-
mal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: Does not include GP3. For GP3 see parameters D061 and D061A.
5: This spec. applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal pull-up
enabled.
6: This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit is
higher than the standard I/O logic.
DS30561B-page 98
1999 Microchip Technology Inc.
PIC12C67X
12.5
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
2. TppS
T
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
ST
DAT
STA
Hold
SU
Setup
DATA input hold
START condition
STO
STOP condition
FIGURE 12-4: LOAD CONDITIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
1999 Microchip Technology Inc.
DS30561B-page 99
PIC12C67X
12.6
Timing Diagrams and Specifications
FIGURE 12-5: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
4
Q1
OSC1
1
3
4
3
2
CLKOUT
TABLE 12-1: CLOCK TIMING REQUIREMENTS
Parameter Sym Characteristic
No.
Min Typ†
Max
Units Conditions
FOSC External CLKIN Frequency
DC
DC
DC
DC
DC
.455
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
4
MHz XT and EXTRC osc mode
MHz HS osc mode (PIC12CE67X-04)
MHz HS osc mode (PIC12CE67X-10)
kHz LP osc mode
(Note 1)
10
200
4
Oscillator Frequency
(Note 1)
MHz EXTRC osc mode
4
MHz XT osc mode
4
MHz HS osc mode (PIC12CE67X-04)
MHz HS osc mode (PIC12CE67X-10)
kHz LP osc mode
4
10
200
—
—
—
—
—
5
1
TOSC External CLKIN Period
250
250
100
5
ns
ns
ns
µs
ns
ns
ns
ns
µs
ns
ns
µs
ns
ns
ns
ns
XT and EXTRC osc mode
HS osc mode (PIC12CE67X-04)
HS osc mode (PIC12CE67X-10)
LP osc mode
(Note 1)
Oscillator Period
(Note 1)
250
250
250
100
5
EXTRC osc mode
XT osc mode
10,000
250
250
—
HS osc mode (PIC12CE67X-04)
HS osc mode (PIC12CE67X-10)
LP osc mode
2
3
TCY Instruction Cycle Time (Note 1) 400
DC
—
TCY = 4/FOSC
TosL, External Clock in (OSC1) High
TosH or Low Time
50
2.5
10
—
XT oscillator
—
LP oscillator
—
HS oscillator
4
TosR, External Clock in (OSC1) Rise
TosF or Fall Time
25
XT oscillator
—
50
LP oscillator
—
15
HS oscillator
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based
on characterization data for that particular oscillator type under standard operating conditions with the device exe-
cuting code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than
expected current consumption. All devices are tested to operate at "min." values with an external clock applied to
the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC2 is discon-
nected (has no loading) for the PIC12C67X.
DS30561B-page 100
1999 Microchip Technology Inc.
PIC12C67X
TABLE 12-2: CALIBRATED INTERNAL RC FREQUENCIES -PIC12C671, PIC12C672, PIC12CE673,
PIC12CE674, PIC12LC671,
PIC12LC672, PIC12LCE673,
PIC12LCE674
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial),
–40°C ≤ TA ≤ +85°C (industrial),
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1
Parameter
Sym
Typ(1)
Characteristic
Min*
Max* Units
Conditions
MHz VDD = 5.0V
MHz VDD = 2.5V
No.
Internal Calibrated RC Frequency
3.65
4.00
4.28
4.31
Internal Calibrated RC Frequency
3.55
4.00
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
1999 Microchip Technology Inc.
DS30561B-page 101
PIC12C67X
FIGURE 12-6: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
14
12
18
19
16
I/O Pin
(input)
15
17
I/O Pin
new value
old value
(output)
20, 21
Note: Refer to Figure 12-4 for load conditions.
TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS
Param Sym
No.
Characteristic
Min
Typ†
Max
Units Conditions
10*
11*
12*
13*
14*
15*
16*
17*
18*
18A*
TosH2ckL OSC1↑ to CLKOUT↓
TosH2ckH OSC1↑ to CLKOUT↑
—
—
—
—
—
75
75
35
35
—
—
—
50
—
—
200
200
100
100
ns Note 1
ns Note 1
ns Note 1
ns Note 1
TckR
TckF
CLKOUT rise time
CLKOUT fall time
TckL2ioV CLKOUT ↓ to Port out valid
0.5TCY + 20 ns Note 1
TioV2ckH Port in valid before CLKOUT ↑
TckH2ioI Port in hold after CLKOUT ↑
TOSC + 200
—
—
ns Note 1
0
ns Note 1
TosH2ioV OSC1↑ (Q1 cycle) to Port out valid
TosH2ioI OSC1↑ (Q2 cycle) to Port PIC12C67X
—
150
—
ns
ns
ns
100
200
input invalid (I/O in hold
time)
PIC12LC67X
—
19*
TioV2osH Port input valid to OSC1↑ (I/O in setup
0
—
—
ns
time)
20*
20A*
21*
TioR
TioF
Port output rise time
Port output fall time
PIC12C67X
PIC12LC67X
PIC12C67X
PIC12LC67X
—
—
10
—
10
—
—
—
40
80
40
80
—
—
ns
ns
ns
ns
ns
ns
—
21A*
22††*
23††*
—
Tinp
Trbp
GP2/INT pin high or low time
TCY
TCY
GP0/GP1/GP3 change INT high or low
time
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
†† These parameters are asynchronous events not related to any internal clock edge.
Note 1: Measurements are taken in EXTRC and INTRC modes where CLKOUT output is 4 x TOSC.
DS30561B-page 102
1999 Microchip Technology Inc.
PIC12C67X
FIGURE 12-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Timeout
32
OSC
Timeout
Internal
RESET
Watchdog
Timer
RESET
36
34
31
34
I/O Pins
TABLE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
Parameter
No.
Sym Characteristic
Min
Typ†
Max Units
Conditions
30
TmcL MCLR Pulse Width (low)
2
—
—
µs VDD = 5V, –40°C to +125°C
ms VDD = 5V, –40°C to +125°C
31*
Twdt
Watchdog Timer Time-out Period
7
18
33
(No Prescaler)
32
33*
34
Tost
Oscillation Start-up Timer Period
—
28
—
1024TOSC
—
—
TOSC = OSC1 period
Tpwrt Power up Timer Period
72
—
132
2.1
ms VDD = 5V, –40°C to +125°C
µs
TIOZ I/O Hi-impedance from MCLR
Low or Watchdog Timer Reset
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
1999 Microchip Technology Inc.
DS30561B-page 103
PIC12C67X
FIGURE 12-8: TIMER0 CLOCK TIMINGS
GP2/T0CKI
41
40
42
TMR0
Note: Refer to Figure 12-4 for load conditions.
TABLE 12-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max Units
Conditions
40*
41*
42*
Tt0H
T0CKI High Pulse Width No Prescaler
0.5TCY + 20
10
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Must also meet
parameter 42
With Prescaler
Tt0L
Tt0P
T0CKI Low Pulse Width
T0CKI Period
No Prescaler
With Prescaler
No Prescaler
0.5TCY + 20
10
Must also meet
parameter 42
TCY + 40
With Prescaler Greater of:
20 or TCY + 40
N = prescale
value (2, 4,...,
256)
N
48
*
TCKE2tmr1 Delay from external clock edge to timer
increment
2TOSC
—
7Tos
c
—
These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
TABLE 12-6: GPIO PULL-UP RESISTOR RANGES
VDD (Volts)
Temperature (°C)
Min
Typ
Max
Units
GP0/GP1
2.5
–40
25
38K
42K
42K
50K
15K
18K
19K
22K
42K
48K
49K
55K
17K
20K
22K
24K
63K
63K
63K
63K
20K
23K
25K
28K
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
85
125
–40
25
5.5
85
125
GP3
2.5
5.5
–40
25
285K
343K
368K
431K
247K
288K
306K
351K
346K
414K
457K
504K
292K
341K
371K
407K
417K
532K
532K
593K
360K
437K
448K
500K
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
85
125
–40
25
85
125
*
These parameters are characterized but not tested.
DS30561B-page 104
1999 Microchip Technology Inc.
PIC12C67X
TABLE 12-7: A/D CONVERTER CHARACTERISTICS:
PIC12C671/672-04/PIC12CE673/674-04 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC12C671/672-10/PIC12CE673/674-10 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC12LC671/672-04/PIC12LCE673/674-04 (COMMERCIAL, INDUSTRIAL)
Param Sym Characteristic
No.
Min
Typ†
Max
Units
Conditions
A01
A02
A03
NR
EABS Total absolute error
EIL Integral linearity error
Resolution
—
—
—
—
—
—
8-bits
< ±1
< ±1
bit
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
LSb
LSb
LSb
LSb
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A04
A05
A06
EDL Differential linearity error
EFS Full scale error
—
—
—
—
—
—
< ±1
< ±1
< ±1
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
EOFF Offset error
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10
A20
—
Monotonicity
—
guaranteed
(Note 3)
—
—
V
VSS ≤ VAIN ≤ VREF
VREF Reference voltage
VAIN Analog input voltage
2.5V
—
VDD + 0.3
A25
A30
VSS - 0.3
—
—
VREF + 0.3
V
ZAIN Recommended impedance of
—
10.0
kΩ
analog voltage source
A40
A50
IAD A/D conversion
current (VDD)
PIC12C67X
—
—
180
90
—
—
µA Average current con-
sumption when A/D is on.
(Note 1)
PIC12LC67X
µA
IREF VREF input current (Note 2)
10
—
1000
µA During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD, see Section 8.1.
—
—
10
µA During A/D Conversion
cycle
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec
includes any such leakage from the A/D module.
2: VREF current is from GP1 pin or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes.
1999 Microchip Technology Inc.
DS30561B-page 105
PIC12C67X
FIGURE 12-9: A/D CONVERSION TIMING
BSF ADCON0, GO
1 TCY
(TOSC/2)(1)
134
131
130
Q4
132
A/D CLK
7
6
5
4
3
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 12-8: A/D CONVERSION REQUIREMENTS
Param Sym Characteristic
No.
Min
Typ†
Max Units
Conditions
130
TAD
A/D clock period
PIC12C67X
PIC12LC67X
PIC12C67X
PIC12LC67X
1.6
2.0
2.0
3.0
11
—
—
—
—
µs TOSC based, VREF ≥ 3.0V
µs TOSC based, VREF full range
µs A/D RC Mode
4.0
6.0
—
6.0
9.0
11
µs A/D RC Mode
131
132
TCNV Conversion time (not including S/H
TAD
time) (Note 1)
TACQ Acquisition time
Note 2
5*
20
—
—
—
µs
µs The minimum time is the
amplifier setting time. This
may be used if the "new"
input voltage has not
changed by more than 1 LSb
(i.e., 20.0 mV @ 5.12V) from
the last sampled voltage (as
stated on CHOLD).
134
135
TGO Q4 to A/D clock start
—
TOSC/2 §
—
—
—
If the A/D clock source is
selected as RC, a time of
TCY is added before the A/D
clock starts. This allows the
SLEEPinstruction to be exe-
cuted.
TSWC Switching from convert → sample time 1.5 §
—
TAD
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
§
This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 8.1 for min. conditions.
DS30561B-page 106
1999 Microchip Technology Inc.
PIC12C67X
TABLE 12-9: EEPROM MEMORY BUS TIMING REQUIREMENTS - PIC12CE673/674 ONLY.
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0°C ≤ TA ≤ +70°C, Vcc = 3.0V to 5.5V (commercial)
–40°C ≤ TA ≤ +85°C, Vcc = 3.0V to 5.5V (industrial)
–40°C ≤ TA ≤ +125°C, Vcc = 4.5V to 5.5V (extended)
Operating Voltage VDD range is described in Section 12.1
Parameter
Symbol
Min
Max
Units
Conditions
Clock frequency
FCLK
—
—
—
100
100
400
kHz
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Clock high time
Clock low time
THIGH
TLOW
TR
4000
4000
600
—
—
—
ns
ns
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
4700
4700
1300
—
—
—
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
SDA and SCL rise time
(Note 1)
—
—
—
1000
1000
300
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
SDA and SCL fall time
TF
—
300
ns
ns
(Note 1)
START condition hold time
THD:STA
4000
4000
600
—
—
—
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
START condition setup time
TSU:STA
4700
4700
600
—
—
—
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Data input hold time
Data input setup time
THD:DAT
TSU:DAT
0
—
ns
ns
(Note 2)
250
250
100
—
—
—
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
STOP condition setup time
TSU:STO
TAA
4000
4000
600
—
—
—
ns
ns
ns
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Output valid from clock
(Note 2)
—
—
—
3500
3500
900
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Bus free time: Time the bus must
be free before a new transmis-
sion can start
TBUF
4700
4700
1300
—
—
—
4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Output fall time from VIH
minimum to VIL maximum
TOF
TSP
TWC
20+0.1
CB
250
ns
ns
(Note 1), CB ≤ 100 pF
Input filter spike suppression
(SDA and SCL pins)
—
50
(Notes 1, 3)
Write cycle time
Endurance
—
4
ms
1M
—
cycles 25°C, VCC = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (min-
imum 300 ns) of the falling edge of SCL and avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific applica-
tion, please consult the Total Endurance Model which can be obtained on Microchip’s website.
1999 Microchip Technology Inc.
DS30561B-page 107
PIC12C67X
NOTES:
DS30561B-page 108
1999 Microchip Technology Inc.
PIC12C67X
13.0 DC AND AC CHARACTERISTICS - PIC12C671/PIC12C672/PIC12LC671/
PIC12LC672/PIC12CE673/PIC12CE674/PIC12LCE673/PIC12LCE674
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables
the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only
and devices will operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean – 3σ)
respectively, where σ is standard deviation.
FIGURE 13-1: CALIBRATED INTERNAL RC
FREQUENCY RANGE VS.
FIGURE 13-2: CALIBRATED INTERNAL RC
FREQUENCY RANGE VS.
TEMPERATURE (VDD = 5.0V)
(INTERNAL RC IS
TEMPERATURE (VDD = 2.5V)
(INTERNAL RC IS
CALIBRATED TO 25°C, 5.0V)
CALIBRATED TO 25°C, 5.0V)
4.50
4.40
4.30
4.50
4.40
4.30
Max.
4.20
4.20
Max.
4.10
4.00
4.10
4.00
3.90
3.80
3.70
3.60
3.90
3.80
Min.
3.70
3.60
3.50
Min
.
3.50
-40
0
25
85
125
-40
0
25
85
125
Temperature (Deg.C)
Temperature (Deg.C)
1999 Microchip Technology Inc.
DS30561B-page 109
PIC12C67X
TABLE 13-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C
Oscillator
External RC
Frequency
VDD = 2.5V
VDD = 5.5V
4 MHz
4 MHz
4 MHz
32 kHz
400 µA*
400 µA
400 µA
15 µA
900 µA*
900 µA
900 µA
60 µA
Internal RC
XT
LP
*Does not include current through external R&C.
FIGURE 13-3: WDT TIMER TIME-OUT
FIGURE 13-4: IOH vs. VOH, VDD = 2.5 V
PERIOD vs. VDD
-0
55
50
45
-1
-2
-3
-4
40
Min +125°C
Min +85°C
-5
35
Max +125°C
-6
Typ +25°C
30
Max +85°C
-7
-8
25
20
-9
Typ +25°C
Max -40°C
-10
15
.5 .75 1.0 1.25 1.5 1.75 2.0 2.25 2.5
MIn –40°C
VOH (Volts)
10
0
2.5
3.5
4.5
5.5
6.5
VDD (Volts)
DS30561B-page 110
1999 Microchip Technology Inc.
PIC12C67X
FIGURE 13-5: IOH vs. VOH, VDD = 3.5 V
FIGURE 13-7: IOL vs. VOL, VDD = 2.5 V
35
0
30
-5
Max -40°C
Typ +25°C
Min +125°C
25
20
-10
Min +85°C
Typ +25°C
-15
15
10
Max -40°C
Min +85°C
-20
Min +125°C
-25
1.5
2.0
2.5
3.5
3.0
5
0
VOH (Volts)
0
0.25
0.5
0.75
1.0
FIGURE 13-6: IOH vs. VOH, VDD = 5.5 V
VOL (Volts)
0
FIGURE 13-8: IOL vs. VOL, VDD = 3.5 V
-5
-10
-15
-20
45
Max -40°C
40
35
30
25
-25
-30
Typ +25°C
-35
-40
20
15
3.5
4.0
4.5
5.0
5.5
Min +85°C
VOH (Volts)
Min +125°C
10
0
0
0.25
0.5
0.75
1.0
VOL (Volts)
1999 Microchip Technology Inc.
DS30561B-page 111
PIC12C67X
FIGURE 13-9: IOL vs. VOL, VDD = 5.5 V
FIGURE 13-10: VTH (INPUT THRESHOLD
VOLTAGE) OF GPIO PINS
vs. VDD
55
1.8
Max -40°C
50
45
40
Max (-40 to 125)
1.6
1.4
Typ (25)
1.2
35
30
Typ +25°C
Min (-40 to 125)
1.0
0.8
0.6
0
25
20
15
Min +85°C
2.5
3.5
4.5
VDD (Volts)
5.5
Min +125°C
10
0
0
0.25
0.5
0.75
1.0
VOL (Volts)
DS30561B-page 112
1999 Microchip Technology Inc.
PIC12C67X
FIGURE 13-11: VIL, VIH OF NMCLR AND T0CKI vs. VDD
3.5
VIH Max (-40 to 125)
VIH Typ (25)
3.0
2.5
VIH Min (-40 to 125)
2.0
1.5
VIL Max (-40 to 125)
VIL Typ (25)
VIL Min (-40 to 125)
1.0
0.5
2.5
3.5
4.5
VDD (Volts)
5.5
1999 Microchip Technology Inc.
DS30561B-page 113
PIC12C67X
NOTES:
DS30561B-page 114
1999 Microchip Technology Inc.
PIC12C67X
14.0 PACKAGING INFORMATION
14.1
Package Marking Information
8-Lead PDIP (300 mil)
Example
12CE674
MMMMMMMM
XXXXXCDE
04/PSAZ
AABB
9925
8-Lead SOIC (208 mil)
Example
MMMMMMM
XXXXXXX
AABBCDE
12C671
04I/SM
9924SAZ
Example
8-Lead Windowed Ceramic Side Brazed (300 mil)
JW
MM
CE674
MMMMMM
Legend: MM...M Microchip part number information
XX...X Customer specific information*
AA
BB
C
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
O = Outside Vendor
C = 5” Line
S = 6” Line
H = 8” Line
D
E
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
1999 Microchip Technology Inc.
DS30561B-page 115
PIC12C67X
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
eB
α
β
5
10
15
5
10
15
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS30561B-page 116
1999 Microchip Technology Inc.
PIC12C67X
8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC)
E
E1
p
D
2
n
1
B
α
c
A2
A
φ
A1
L
β
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
8
8
1.27
1.97
1.88
0.13
7.95
5.28
5.21
0.64
4
.050
.075
.074
.005
.313
.208
.205
.025
4
Overall Height
A
.070
.080
1.78
2.03
Molded Package Thickness
Standoff
A2
A1
E
.069
.002
.300
.078
.010
.325
.212
.210
.030
8
1.75
0.05
7.62
5.11
5.13
0.51
0
1.98
0.25
8.26
5.38
5.33
0.76
8
Overall Width
Molded Package Width
Overall Length
E1
D
.201
.202
.020
0
Foot Length
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.014
0
.009
.017
12
.010
.020
15
0.20
0.36
0
0.23
0.43
12
0.25
0.51
15
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
β
0
12
15
0
12
15
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
Drawing No. C04-056
1999 Microchip Technology Inc.
DS30561B-page 117
PIC12C67X
8-Lead Ceramic Side Brazed Dual In-line with Window (JW) – 300 mil
E1
W
T
D
2
1
n
U
A
A2
L
A1
c
B1
p
eB
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.100
.165
.123
.035
.290
.520
.140
.010
.055
.018
.310
.166
.450
.270
2.54
Top to Seating Plane
A
.145
.103
.025
.280
.510
.130
.008
.050
.016
.296
.161
.440
.260
.185
3.68
2.62
4.19
3.12
0.89
7.37
13.21
3.56
0.25
1.40
0.46
7.87
4.22
11.43
6.86
4.70
Top of Body to Seating Plane
Standoff
A2
A1
E1
D
.143
.045
.300
.530
.150
.012
.060
.020
.324
.171
.460
.280
3.63
1.14
7.62
13.46
3.81
0.30
1.52
0.51
8.23
4.34
11.68
7.11
0.64
7.11
12.95
3.30
0.20
1.27
0.41
7.52
4.09
11.18
6.60
Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Window Diameter
Lid Length
L
c
B1
B
eB
W
T
Lid Width
U
*Controlling Parameter
JEDC Equivalent: MS-015
Drawing No. C04-083
DS30561B-page 118
1999 Microchip Technology Inc.
PIC12C67X
APPENDIX A:COMPATIBILITY
APPENDIX B:CODE FOR
ACCESSING EEPROM
DATA MEMORY
To convert code written for PIC16C5X to PIC12C67X,
the user should take the following steps:
1. Remove any program memory page select
Please refer to our web site at www.microchip.com for
code availability.
operations (PA2, PA1, PA0 bits) for CALL, GOTO.
2. Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
3. Eliminate any data memory page switching.
Redefine data variables to reallocate them.
4. Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
5. Change reset vector to 0000h.
1999 Microchip Technology Inc.
DS30561B-page 119
PIC12C67X
NOTES:
DS30561B-page 120
1999 Microchip Technology Inc.
PIC12C67X
INDEX
C
C bit .................................................................................... 15
CAL0 bit.............................................................................. 21
CAL1 bit.............................................................................. 21
CAL2 bit.............................................................................. 21
CAL3 bit.............................................................................. 21
CALFST bit......................................................................... 21
CALL Instruction ................................................................. 74
CALSLW bit ........................................................................ 21
Carry bit ................................................................................ 7
Clocking Scheme................................................................ 10
CLRF Instruction................................................................. 74
CLRW Instruction................................................................ 74
CLRWDT Instruction........................................................... 75
Code Examples
Changing Prescaler (Timer0 to WDT) ........................ 43
Changing Prescaler (WDT to Timer0) ........................ 43
Indirect Addressing..................................................... 23
Code Protection............................................................ 53, 67
COMF Instruction................................................................ 75
Computed GOTO................................................................ 22
Configuration Bits ............................................................... 53
A
A/D
Accuracy/Error ............................................................ 51
ADCON0 Register....................................................... 45
ADIF bit....................................................................... 47
Analog Input Model Block Diagram............................. 48
Analog-to-Digital Converter......................................... 45
Configuring Analog Port Pins...................................... 49
Configuring the Interrupt ............................................. 47
Configuring the Module............................................... 47
Connection Considerations......................................... 51
Conversion Clock........................................................ 49
Conversions................................................................ 50
Converter Characteristics ......................................... 105
Delays......................................................................... 48
Effects of a Reset........................................................ 51
Equations.................................................................... 48
Flowchart of A/D Operation......................................... 52
GO/DONE bit .............................................................. 47
Internal Sampling Switch (Rss) Impedence................ 48
Operation During Sleep .............................................. 51
Sampling Requirements.............................................. 48
Sampling Time............................................................ 48
Source Impedence...................................................... 48
Time Delays................................................................ 48
Transfer Function........................................................ 51
Absolute Maximum Ratings ................................................ 89
ADDLW Instruction ............................................................. 72
ADDWF Instruction ............................................................. 72
ADIE bit............................................................................... 18
ADIF bit............................................................................... 19
ADRES Register ..................................................... 13, 45, 47
ALU ....................................................................................... 7
ANDLW Instruction ............................................................. 72
ANDWF Instruction ............................................................. 72
Application Notes
D
DC and AC Characteristics............................................... 109
DC bit.................................................................................. 15
DC Characteristics
PIC12C671/672, PIC12CE673/674............................ 92
PIC12LC671/672, PIC12LCE673/674........................ 94
DECF Instruction ................................................................ 75
DECFSZ Instruction............................................................ 75
Development Support..................................................... 3, 83
Digit Carry bit........................................................................ 7
Direct Addressing ............................................................... 23
E
EEPROM Peripheral Operation.......................................... 33
Electrical Characteristics - PIC12C67X .............................. 89
Errata.................................................................................... 2
External Brown-out Protection Circuit................................. 61
External Power-on Reset Circuit......................................... 61
AN546......................................................................... 45
AN556......................................................................... 22
Architecture
F
Harvard ......................................................................... 7
Overview....................................................................... 7
von Neumann................................................................ 7
Assembler
Family of Devices ................................................................. 4
Features ............................................................................... 1
FSR Register.......................................................... 13, 14, 23
MPASM Assembler..................................................... 83
G
B
General Description.............................................................. 3
GIE bit................................................................................. 62
GOTO Instruction................................................................ 76
GPIF bit .............................................................................. 64
GPIO............................................................................. 25, 59
GPIO Register .................................................................... 13
GPPU bit............................................................................. 16
BCF Instruction ................................................................... 73
Bit Manipulation .................................................................. 70
Block Diagrams
Analog Input Model..................................................... 48
On-Chip Reset Circuit................................................. 57
Timer0......................................................................... 39
Timer0/WDT Prescaler ............................................... 42
Watchdog Timer.......................................................... 65
BSF Instruction ................................................................... 73
BTFSC Instruction............................................................... 73
BTFSS Instruction............................................................... 74
1999 Microchip Technology Inc.
DS30561B-page 121
PIC12C67X
I
K
I/O Interfacing......................................................................25
I/O Ports..............................................................................25
I/O Programming Considerations........................................31
ID Locations ........................................................................53
INCF Instruction ..................................................................76
INCFSZ Instruction..............................................................76
In-Circuit Serial Programming....................................... 53, 67
INDF Register ............................................................... 14, 23
Indirect Addressing .............................................................23
Initialization Conditions for All Registers.............................59
Instruction Cycle..................................................................10
Instruction Flow/Pipelining ..................................................10
Instruction Format ...............................................................69
Instruction Set
KeeLoq Evaluation and Programming Tools ................... 86
L
Loading of PC..................................................................... 22
M
MCLR............................................................................ 56, 59
Memory
Data Memory .............................................................. 11
Program Memory........................................................ 11
Register File Map - PIC12CE67X............................... 12
MOVF Instruction................................................................ 77
MOVLW Instruction............................................................. 77
MOVWF Instruction ............................................................ 77
MPLAB Integrated Development Environment Software.... 83
ADDLW .......................................................................72
ADDWF.......................................................................72
ANDLW .......................................................................72
ANDWF.......................................................................72
BCF.............................................................................73
BSF.............................................................................73
BTFSC ........................................................................73
BTFSS ........................................................................74
CALL ...........................................................................74
CLRF...........................................................................74
CLRW .........................................................................74
CLRWDT.....................................................................75
COMF .........................................................................75
DECF ..........................................................................75
DECFSZ......................................................................75
GOTO .........................................................................76
INCF............................................................................76
INCFSZ.......................................................................76
IORLW ........................................................................76
IORWF ........................................................................77
MOVF..........................................................................77
MOVLW ......................................................................77
MOVWF ......................................................................77
NOP ............................................................................78
OPTION ......................................................................78
RETFIE .......................................................................78
RETLW .......................................................................78
RETURN .....................................................................79
RLF .............................................................................79
RRF.............................................................................79
SLEEP ........................................................................79
SUBLW .......................................................................80
SUBWF.......................................................................80
SWAPF .......................................................................81
TRIS............................................................................81
XORLW.......................................................................81
XORWF.......................................................................81
Section ........................................................................69
INTCON Register................................................................17
INTEDG bit..........................................................................16
Internal Sampling Switch (Rss) Impedence ........................48
Interrupts.............................................................................53
A/D..............................................................................62
GP2/INT ......................................................................62
GPIO Port ...................................................................62
Section ........................................................................62
TMR0 ..........................................................................64
TMR0 Overflow ...........................................................62
IORLW Instruction...............................................................76
IORWF Instruction...............................................................77
IRP bit .................................................................................15
N
NOP Instruction .................................................................. 78
O
Opcode ............................................................................... 69
OPTION Instruction ............................................................ 78
OPTION Register................................................................ 16
Orthogonal............................................................................ 7
OSC selection..................................................................... 53
OSCCAL Register............................................................... 21
Oscillator
EXTRC ....................................................................... 58
HS............................................................................... 58
INTRC......................................................................... 58
LP ............................................................................... 58
XT ............................................................................... 58
Oscillator Configurations..................................................... 54
Oscillator Types
EXTRC ....................................................................... 54
HS............................................................................... 54
INTRC......................................................................... 54
LP ............................................................................... 54
XT ............................................................................... 54
P
Package Marking Information........................................... 115
Packaging Information...................................................... 115
Paging, Program Memory................................................... 22
PCL..................................................................................... 70
PCL Register .......................................................... 13, 14, 22
PCLATH.............................................................................. 59
PCLATH Register ................................................... 13, 14, 22
PCON Register............................................................. 20, 58
PD bit............................................................................ 15, 56
PICDEM-1 Low-Cost PICmicro Demo Board ..................... 85
PICDEM-2 Low-Cost PIC16CXX Demo Board................... 85
PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 85
PICSTART Plus Entry Level Development System......... 85
PIE1 Register...................................................................... 18
Pinout Description - PIC12CE67X........................................ 9
PIR1 Register ..................................................................... 19
POP .................................................................................... 22
POR.................................................................................... 58
Oscillator Start-up Timer (OST)............................ 53, 58
Power Control Register (PCON)................................. 58
Power-on Reset (POR)................................... 53, 58, 59
Power-up Timer (PWRT)...................................... 53, 58
Power-Up-Timer (PWRT) ........................................... 58
Time-out Sequence .................................................... 58
Time-out Sequence on Power-up............................... 60
TO............................................................................... 56
Power.................................................................................. 56
DS30561B-page 122
1999 Microchip Technology Inc.
PIC12C67X
Power-down Mode (SLEEP)............................................... 66
Prescaler, Switching Between Timer0 and WDT ................ 43
PRO MATE II Universal Programmer .............................. 85
Program Branches................................................................ 7
Program Memory
Paging......................................................................... 22
Program Verification ........................................................... 67
PS0 bit ................................................................................ 16
PS1 bit ................................................................................ 16
PS2 bit ................................................................................ 16
PSA bit ................................................................................ 16
PUSH .................................................................................. 22
T
T0CS bit.............................................................................. 16
TAD ..................................................................................... 49
Timer0
RTCC.......................................................................... 59
Timers
Timer0
Block Diagram.................................................... 39
External Clock .................................................... 41
External Clock Timing......................................... 41
Increment Delay ................................................. 41
Interrupt .............................................................. 39
Interrupt Timing .................................................. 40
Prescaler ............................................................ 42
Prescaler Block Diagram.................................... 42
Section ............................................................... 39
Switching Prescaler Assignment ........................ 43
Synchronization.................................................. 41
T0CKI ................................................................. 41
T0IF .................................................................... 64
Timing................................................................. 39
TMR0 Interrupt ................................................... 64
Timing Diagrams
A/D Conversion ........................................................ 106
CLKOUT and I/O ...................................................... 102
External Clock Timing............................................... 100
Time-out Sequence .................................................... 60
Timer0 ........................................................................ 39
Timer0 Interrupt Timing .............................................. 40
Timer0 with External Clock......................................... 41
Wake-up from Sleep via Interrupt............................... 67
TO bit.................................................................................. 15
TOSE bit............................................................................. 16
TRIS Instruction.................................................................. 81
TRIS Register ......................................................... 14, 25, 31
Two’s Complement............................................................... 7
R
RC Oscillator....................................................................... 55
Read Modify Write .............................................................. 31
Read-Modify-Write .............................................................. 31
Register File........................................................................ 11
Registers
Map
PIC12C67X......................................................... 12
Reset Conditions......................................................... 59
Reset............................................................................. 53, 56
Reset Conditions for Special Registers .............................. 59
RETFIE Instruction.............................................................. 78
RETLW Instruction.............................................................. 78
RETURN Instruction ........................................................... 79
RLF Instruction.................................................................... 79
RP0 bit .......................................................................... 11, 15
RP1 bit ................................................................................ 15
RRF Instruction................................................................... 79
S
SEEVAL Evaluation and Programming System............... 86
Services
One-Time-Programmable (OTP) .................................. 5
Quick-Turnaround-Production (QTP)............................ 5
Serialized Quick-Turnaround Production (SQTP)......... 5
SFR..................................................................................... 70
SFR As Source/Destination ................................................ 70
SLEEP .......................................................................... 53, 56
SLEEP Instruction............................................................... 79
Software Simulator (MPLAB-SIM) ...................................... 84
Special Features of the CPU .............................................. 53
Special Function Register
PIC12C67X................................................................. 13
Special Function Registers ................................................. 70
Special Function Registers, Section ................................... 12
Stack................................................................................... 22
Overflows.................................................................... 22
Underflow.................................................................... 22
STATUS Register ............................................................... 15
SUBLW Instruction.............................................................. 80
SUBWF Instruction ............................................................. 80
SWAPF Instruction.............................................................. 81
U
UV Erasable Devices............................................................ 5
W
W Register
ALU............................................................................... 7
Wake-up from SLEEP......................................................... 66
Watchdog Timer (WDT).................................... 53, 56, 59, 65
WDT ................................................................................... 59
Block Diagram ............................................................ 65
Period ......................................................................... 65
Programming Considerations..................................... 65
Timeout....................................................................... 59
WWW, On-Line Support ....................................................... 2
X
XORLW Instruction............................................................. 81
XORWF Instruction............................................................. 81
Z
Z bit..................................................................................... 15
Zero bit ................................................................................. 7
1999 Microchip Technology Inc.
DS30561B-page 123
PIC12C67X
NOTES:
DS30561B-page 124
1999 Microchip Technology Inc.
PIC12C67X
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip’s development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
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Explorer. Files are also available for FTP download
from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-786-7302 for the rest of the world.
981103
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
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The file transfer site is available by using an FTP ser-
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ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
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ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
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available for consideration is:
Trademarks: The Microchip name, logo, PIC, PICmicro,
PICSTART, PICMASTER, PRO MATE and MPLAB are
registered trademarks of Microchip Technology Incorpo-
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fuzzyLAB are trademarks and SQTP is a service mark of
Microchip in the U.S.A.
• Latest Microchip Press Releases
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All other trademarks mentioned herein are the property of
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• Job Postings
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tems, technical information and more
• Listing of seminars and events
1999 Microchip Technology Inc.
DS30561B-page 125
PIC12C67X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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FAX: (______) _________ - _________
Application (optional):
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Literature Number:
DS30561B
Device:
PIC12C67X
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
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8. How would you improve our software, systems, and silicon products?
DS30561B-page 126
1999 Microchip Technology Inc.
PIC12C67X
PIC12C67X PRODUCT IDENTIFICATION SYSTEM
Examples
PART NO. -XX X /XX XXX
Pattern:
Special Requirements
a)
b)
c)
d)
e)
f)
PIC12CE673-04/P
Commercial Temp.,
PDIP Package, 4 MHz,
normal VDD limits
Package:
P
JW
SM
=
=
=
300 mil PDIP
300 mil Windowed Ceramic Side Brazed
208 mil SOIC
PIC12CE673-04I/P
Industrial Temp., PDIP
package,4 MHz,normal
VDD limits
Temperature
Range:
-
=
=
=
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
I
E
Frequency
Range:
04
10
=
=
4 MHz/200 kHz
10 MHz
PIC12CE673-10I/P
Industrial Temp.,
PDIP package, 10 MHz,
normal VDD limits
Device
PIC12CE673
PIC12C671-04/P
PIC12CE674
Commercial Temp.,
PDIP Package, 4 MHz,
normal VDD limits
PIC12LCE673
PIC12LCE674
PIC12C671
PIC12C672
PIC12C671-04I/SM
Industrial Temp., SOIC
package,4 MHz,normal
VDD limits
PIC12C671T (Tape & reel for SOIC only)
PIC12C672T (Tape & reel for SOIC only)
PIC12LC671
PIC12LC672
PIC12LC671T (Tape & reel for SOIC only)
PIC12LC672T (Tape & reel for SOIC only)
PIC12C671-04I/P
Industrial Temp.,
PDIP package, 4 MHz,
normal VDD limits
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement
of each oscillator type (including LC devices).
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
1999 Microchip Technology Inc.
DS30561B-page 127
®
Note the following details of the code protection feature on PICmicro MCUs.
•
•
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
•
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Tech-
nology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
2002 Microchip Technology Inc.
M
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Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699 Fax: 905-673-6509
India
Microchip Technology Inc.
India Liaison Office
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
01/18/02
2002 Microchip Technology Inc.
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