PIC12F629T-I/SNVAO [MICROCHIP]
RISC Microcontroller, 8-Bit, FLASH, 20MHz, CMOS, PDSO8;
| 型号： | PIC12F629T-I/SNVAO |
| 厂家： | 
MICROCHIP |
| 描述： | RISC Microcontroller, 8-Bit, FLASH, 20MHz, CMOS, PDSO8 时钟 微控制器 光电二极管 外围集成电路 装置 |
| 文件： | 总136页 (文件大小：1423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC12F629/675
Data Sheet
8-Pin, Flash-Based 8-Bit
CMOS Microcontrollers
2010 Microchip Technology Inc.
DS41190G
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
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OTHERWISE, RELATED TO THE INFORMATION,
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
32
PIC logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-160-4
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS41190G-page 2
2010 Microchip Technology Inc.
PIC12F629/675
8-Pin Flash-Based 8-Bit CMOS Microcontroller
High-Performance RISC CPU:
Low-Power Features:
• Only 35 Instructions to Learn
- All single-cycle instructions except branches
• Operating Speed:
• Standby Current:
- 1 nA @ 2.0V, typical
• Operating Current:
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instruction cycle
• Interrupt Capability
- 8.5 A @ 32 kHz, 2.0V, typical
- 100 A @ 1 MHz, 2.0V, typical
• Watchdog Timer Current
- 300 nA @ 2.0V, typical
• Timer1 Oscillator Current:
- 4 A @ 32 kHz, 2.0V, typical
• 8-Level Deep Hardware Stack
• Direct, Indirect, and Relative Addressing modes
Special Microcontroller Features:
Peripheral Features:
• Internal and External Oscillator Options
- Precision Internal 4 MHz oscillator factory
calibrated to ±1%
• 6 I/O Pins with Individual Direction Control
• High Current Sink/Source for Direct LED Drive
• Analog Comparator module with:
- One analog comparator
- External Oscillator support for crystals and
resonators
- 5 s wake-up from Sleep, 3.0V, typical
• Power-Saving Sleep mode
- Programmable on-chip comparator voltage
reference (CVREF) module
• Wide Operating Voltage Range – 2.0V to 5.5V
• Industrial and Extended Temperature Range
• Low-Power Power-on Reset (POR)
- Programmable input multiplexing from device
inputs
- Comparator output is externally accessible
• Analog-to-Digital Converter module (PIC12F675):
- 10-bit resolution
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Brown-out Detect (BOD)
- Programmable 4-channel input
- Voltage reference input
• Watchdog Timer (WDT) with Independent
Oscillator for Reliable Operation
• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
• Multiplexed MCLR/Input Pin
• Interrupt-on-Pin Change
• Enhanced Timer1:
• Individual Programmable Weak Pull-ups
• Programmable Code Protection
• High Endurance Flash/EEPROM Cell
- 100,000 write Flash endurance
- 1,000,000 write EEPROM endurance
- Flash/Data EEPROM Retention: > 40 years
- 16-bit timer/counter with prescaler
- External Gate Input mode
- Option to use OSC1 and OSC2 in LP mode
as Timer1 oscillator, if INTOSC mode
selected
• In-Circuit Serial ProgrammingTM (ICSPTM) via
two pins
Program
Memory
Data Memory
10-bit A/D
(ch)
Timers
8/16-bit
Device
I/O
Comparators
Flash
(words)
SRAM
(bytes)
EEPROM
(bytes)
PIC12F629
PIC12F675
1024
1024
64
64
128
128
6
6
—
4
1
1
1/1
1/1
* 8-bit, 8-pin devices protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and
foreign patents and applications may be issued or pending.
2010 Microchip Technology Inc.
DS41190G-page 3
PIC12F629/675
Pin Diagrams
8-pin PDIP, SOIC, DFN-S, DFN
VSS
1
2
8
7
VDD
GP0/CIN+/ICSPDAT
GP5/T1CKI/OSC1/CLKIN
GP4/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
GP1/CIN-/ICSPCLK
3
4
6
5
GP2/T0CKI/INT/COUT
1
2
3
4
8
7
6
5
VDD
VSS
GP5/T1CKI/OSC1/CLKIN
GP0/AN0/CIN+/ICSPDAT
GP4/AN3/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
GP1/AN1/CIN-/VREF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT
DS41190G-page 4
2010 Microchip Technology Inc.
PIC12F629/675
Table of Contents
1.0 Device Overview......................................................................................................................................................................... 7
2.0 Memory Organization.................................................................................................................................................................. 9
3.0 GPIO Port ................................................................................................................................................................................. 21
4.0 Timer0 Module.......................................................................................................................................................................... 29
5.0 Timer1 Module with Gate Control ............................................................................................................................................. 32
6.0 Comparator Module .................................................................................................................................................................. 37
7.0 Analog-to-Digital Converter (A/D) Module (PIC12F675 only) ................................................................................................... 43
8.0 Data EEPROM Memory ............................................................................................................................................................ 49
9.0 Special Features of the CPU .................................................................................................................................................... 53
10.0 Instruction Set Summary ........................................................................................................................................................... 71
11.0 Development Support ............................................................................................................................................................... 81
12.0 Electrical Specifications ............................................................................................................................................................ 85
13.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 107
14.0 Packaging Information ............................................................................................................................................................ 117
Appendix A: Data Sheet Revision History ......................................................................................................................................... 127
Appendix B: Device Differences ....................................................................................................................................................... 127
Appendix C: Device Migrations ......................................................................................................................................................... 128
®
Appendix D: Migrating from other PIC Devices .............................................................................................................................. 128
Index ................................................................................................................................................................................................. 129
On-Line Support ................................................................................................................................................................................ 133
Systems Information and Upgrade Hot Line ..................................................................................................................................... 133
Reader Response ............................................................................................................................................................................. 134
Product Identification System ........................................................................................................................................................... 135
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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2010 Microchip Technology Inc.
DS41190G-page 5
PIC12F629/675
NOTES:
DS41190G-page 6
2010 Microchip Technology Inc.
PIC12F629/675
Sheet, and is highly recommended reading for a better
understanding of the device architecture and operation
of the peripheral modules.
1.0
DEVICE OVERVIEW
This document contains device specific information for
the PIC12F629/675. Additional information may be
found in the PIC® Mid-Range Reference Manual
(DS33023), which may be obtained from your local
Microchip Sales Representative or downloaded from
the Microchip web site. The Reference Manual should
be considered a complementary document to this Data
The PIC12F629 and PIC12F675 devices are covered
by this Data Sheet. They are identical, except the
PIC12F675 has a 10-bit A/D converter. They come in
8-pin PDIP, SOIC, MLF-S and DFN packages.
Figure 1-1 shows a block diagram of the PIC12F629/
675 devices. Table 1-1 shows the pinout description.
FIGURE 1-1:
PIC12F629/675 BLOCK DIAGRAM
13
8
Data Bus
Program Counter
Flash
GP0/AN0/CIN+
Program
Memory
GP1/AN1/CIN-/VREF
GP2/AN2/T0CKI/INT/COUT
GP3/MCLR/VPP
GP4/AN3/T1G/OSC2/CLKOUT
GP5/T1CKI/OSC1/CLKIN
RAM
File
Registers
8-Level Stack
(13-bit)
1K x 14
64 x 8
Program
Bus
14
RAM
Addr(1)
9
Addr MUX
Instruction Reg
7
Indirect
Addr
Direct Addr
8
FSR Reg
STATUS Reg
Internal
4 MHz
8
Oscillator
3
MUX
Instruction
Decode &
Control
Power-up
Timer
ALU
Timing
Generation
Oscillator
Start-up Timer
8
OSC1/CLKIN
OSC2/CLKOUT
Power-on
Reset
W Reg
VDD, VSS
Watchdog
Timer
Brown-out
Detect
T1G
T1CKI
Timer0
Timer1
T0CKI
Analog
Comparator
Analog to Digital Converter
EEDATA
and reference
(PIC12F675 only)
128 bytes
DATA
8
EEPROM
EEADDR
CIN- CIN+ COUT
VREF
AN0 AN1 AN2 AN3
Note 1: Higher order bits are from STATUS register.
2010 Microchip Technology Inc.
DS41190G-page 7
PIC12F629/675
TABLE 1-1:
PIC12F629/675 PINOUT DESCRIPTION
Input
Type
Output
Type
Name
Function
Description
GP0/AN0/CIN+/ICSPDAT
GP0
TTL
CMOS Bidirectional I/O w/ programmable pull-up and
interrupt-on-change
AN0
CIN+
AN
AN
A/D Channel 0 input
Comparator input
ICSPDAT
GP1
TTL
TTL
CMOS Serial programming I/O
GP1/AN1/CIN-/VREF/
ICSPCLK
CMOS Bidirectional I/O w/ programmable pull-up and
interrupt-on-change
AN1
CIN-
AN
AN
AN
ST
ST
A/D Channel 1 input
Comparator input
VREF
External voltage reference
Serial programming clock
ICSPCLK
GP2
GP2/AN2/T0CKI/INT/COUT
CMOS Bidirectional I/O w/ programmable pull-up and
interrupt-on-change
AN2
T0CKI
INT
AN
ST
ST
A/D Channel 2 input
TMR0 clock input
External interrupt
COUT
CMOS Comparator output
GP3/MCLR/VPP
GP3
TTL
Input port w/ interrupt-on-change
MCLR
VPP
ST
HV
Master Clear
Programming voltage
GP4/AN3/T1G/OSC2/
CLKOUT
GP4
TTL
CMOS Bidirectional I/O w/ programmable pull-up and
interrupt-on-change
AN3
AN
ST
A/D Channel 3 input
TMR1 gate
T1G
OSC2
XTAL
Crystal/resonator
CLKOUT
CMOS FOSC/4 output
GP5/T1CKI/OSC1/CLKIN
GP5
TTL
CMOS Bidirectional I/O w/ programmable pull-up and
interrupt-on-change
T1CKI
OSC1
CLKIN
VSS
ST
TMR1 clock
XTAL
ST
Crystal/resonator
External clock input/RC oscillator connection
Ground reference
VSS
VDD
Power
Power
VDD
Positive supply
Legend: Shade = PIC12F675 only
TTL = TTL input buffer, ST = Schmitt Trigger input buffer
DS41190G-page 8
2010 Microchip Technology Inc.
PIC12F629/675
2.2
Data Memory Organization
2.0
2.1
MEMORY ORGANIZATION
Program Memory Organization
The data memory (see Figure 2-2) is partitioned into
two banks, which contain the General Purpose
Registers and the Special Function Registers. The
Special Function Registers are located in the first 32
locations of each bank. Register locations 20h-5Fh are
General Purpose Registers, implemented as static
RAM and are mapped across both banks. All other
RAM is unimplemented and returns ‘0’ when read. RP0
(STATUS<5>) is the bank select bit.
The PIC12F629/675 devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. Only the first 1K x 14 (0000h-03FFh)
for the PIC12F629/675 devices is physically imple-
mented. Accessing a location above these boundaries
will cause a wrap-around within the first 1K x 14 space.
The Reset vector is at 0000h and the interrupt vector is
at 0004h (see Figure 2-1).
• RP0 = 0Bank 0 is selected
• RP0 = 1Bank 1 is selected
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
DSTEMP/675
Note: The IRP and RP1 bits STATUS<7:6> are
reserved and should always be maintained
as ‘0’s.
PC<12:0>
2.2.1
GENERAL PURPOSE REGISTER
FILE
CALL, RETURN
RETFIE, RETLW
13
The register file is organized as 64 x 8 in the
PIC12F629/675 devices. Each register is accessed,
either directly or indirectly, through the File Select
Register FSR (see Section 2.4 “Indirect Addressing,
INDF and FSR Registers”).
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
000h
Interrupt Vector
0004
0005
On-chip Program
Memory
03FFh
0400h
1FFFh
2010 Microchip Technology Inc.
DS41190G-page 9
PIC12F629/675
2.2.2
SPECIAL FUNCTION REGISTERS
FIGURE 2-2:
DATA MEMORY MAP OF
THE PIC12F629/675
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
registers are static RAM.
File
File
Address
Address
(1)
(1)
Indirect addr.
TMR0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
Indirect addr.
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
OPTION_REG
PCL
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
PCL
STATUS
FSR
STATUS
FSR
GPIO
TRISIO
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
TMR1L
TMR1H
T1CON
PCON
OSCCAL
WPU
IOC
CMCON
VRCON
EEDATA
EEADR
EECON1
(1)
EECON2
(2)
(2)
(2)
ADRESH
ADCON0
ADRESL
(2)
ANSEL
General
Purpose
Registers
accesses
20h-5Fh
64 Bytes
5Fh
60h
DFh
E0h
7Fh
FFh
Bank 0
Bank 1
Unimplemented data memory locations, read as ‘0’.
1: Not a physical register.
2: PIC12F675 only.
DS41190G-page 10
2010 Microchip Technology Inc.
PIC12F629/675
TABLE 2-1:
Address
SPECIAL FUNCTION REGISTERS SUMMARY
Value on
POR, BOD
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 0
00h
01h
02h
03h
INDF(1)
TMR0
Addressing this Location uses Contents of FSR to Address Data Memory
Timer0 Module’s Register
0000 0000 20,61
xxxx xxxx
0000 0000
0001 1xxx
29
19
14
PCL
Program Counter’s (PC) Least Significant Byte
IRP(2)
RP1(2)
RP0
TO
PD
Z
DC
C
STATUS
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
--xx xxxx
—
20
21
—
—
—
—
19
15
17
—
32
32
GPIO
—
—
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
PCLATH
—
—
T0IE
—
Write Buffer for Upper 5 bits of Program Counter
---0 0000
0000 0000
00-- 0--0
—
INTCON
PIR1
GIE
PEIE
ADIF
INTE
—
GPIE
CMIF
T0IF
—
INTF
—
GPIF
EEIF
TMR1IF
—
Unimplemented
TMR1L
TMR1H
Holding Register for the Least Significant Byte of the 16-bit Timer1
Holding Register for the Most Significant Byte of the 16-bit Timer1
xxxx xxxx
xxxx xxxx
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
T1CON
—
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON -000 0000
35
—
—
—
—
—
—
—
—
38
—
—
—
—
44
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CMCON
—
—
-0-0 0000
COUT
CINV
CIS
CM2
CM1
CM0
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
ADRESH(3)
ADCON0(3)
Most Significant 8 bits of the Left Shifted A/D Result or 2 bits of the Right Shifted Result
ADFM VCFG CHS1 CHS0 GO/DONE
xxxx xxxx
—
—
ADON
00-- 0000 45,61
Legend: — = unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,
shaded = unimplemented
Note 1: This is not a physical register.
2: These bits are reserved and should always be maintained as ‘0’.
3: PIC12F675 only.
2010 Microchip Technology Inc.
DS41190G-page 11
PIC12F629/675
TABLE 2-1:
Address
SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED)
Value on
POR, BOD
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 1
80h
81h
82h
83h
INDF(1)
Addressing this Location uses Contents of FSR to Address Data Memory
0000 0000 20,61
1111 1111 14,31
OPTION_REG
PCL
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
DC
PS0
C
Program Counter’s (PC) Least Significant Byte
0000 0000
0001 1xxx
19
14
IRP(2)
RP1(2)
STATUS
RP0
Indirect Data Memory Address Pointer
TO
PD
Z
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
FSR
TRISIO
—
xxxx xxxx
20
21
—
—
—
—
19
15
16
—
18
—
18
—
—
—
—
21
23
—
—
42
—
—
TRISIO5
TRISIO4
TRISIO3
TRISIO2
TRISIO1
TRISIO0 --11 1111
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
PCLATH
INTCON
PIE1
—
—
—
T0IE
—
Write Buffer for Upper 5 bits of Program Counter
---0 0000
GIE
PEIE
ADIE
INTE
—
GPIE
CMIE
T0IF
—
INTF
—
GPIF
0000 0000
EEIE
TMR1IE
00-- 0--0
Unimplemented
—
—
PCON
—
—
—
—
—
—
POR
—
BOD
—
---- --0x
Unimplemented
CAL5
—
OSCCAL
—
CAL4
CAL3
CAL2
CAL1
CAL0
1000 00--
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
WPU
IOC
—
—
—
WPU5
IOC5
WPU4
IOC4
—
WPU2
IOC2
WPU1
IOC1
WPU0
IOC0
--11 -111
--00 0000
—
—
IOC3
Unimplemented
Unimplemented
VREN
—
—
VRCON
—
—
0-0- 0000
VRR
VR3
VR2
VR1
WR
VR0
RD
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
EEDATA
Data EEPROM Data Register
0000 0000
-000 0000
---- x000
---- ----
xxxx xxxx
49
49
50
50
44
EEADR
—
—
Data EEPROM Address Register
EECON1
EECON2(1)
ADRESL(3)
ANSEL(3)
—
—
—
WRERR
WREN
EEPROM Control Register 2
Least Significant 2 bits of the Left Shifted A/D Result of 8 bits or the Right Shifted Result
ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1
—
ANS0
-000 1111 46,61
Legend: — = unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,
shaded = unimplemented
Note 1: This is not a physical register.
2: These bits are reserved and should always be maintained as ‘0’.
3: PIC12F675 only.
DS41190G-page 12
2010 Microchip Technology Inc.
PIC12F629/675
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
2.2.2.1
STATUS Register
The STATUS register, shown in Register 2-1, contains:
• the arithmetic status of the ALU
• the Reset status
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not affect-
ing any Status bits, see the “Instruction Set Summary”.
• the bank select bits for data memory (SRAM)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: Bits IRP and RP1 (STATUS<7:6>) are not
used by the PIC12F629/675 and should
be maintained as clear. Use of these bits
is not recommended, since this may affect
upward compatibility with future products.
2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1:
Reserved
IRP
STATUS: STATUS REGISTER (ADDRESS: 03h OR 83h)
Reserved
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
IRP: This bit is reserved and should be maintained as ‘0’
RP1: This bit is reserved and should be maintained as ‘0’
RP0: Register Bank Select bit (used for direct addressing)
0= Bank 0 (00h - 7Fh)
1= Bank 1 (80h - FFh)
bit 4
bit 3
bit 2
bit 1
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT Time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)
For borrow, the polarity is reversed.
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note:
For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the
source register.
2010 Microchip Technology Inc.
DS41190G-page 13
PIC12F629/675
2.2.2.2
OPTION Register
Note: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT by
setting PSA bit to ‘1’ (OPTION<3>). See
Section 4.4 “Prescaler”.
The OPTION register is a readable and writable
register, which contains various control bits to
configure:
• TMR0/WDT prescaler
• External GP2/INT interrupt
• TMR0
• Weak pull-ups on GPIO
REGISTER 2-2:
R/W-1
OPTION_REG: OPTION REGISTER (ADDRESS: 81h)
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
GPPU
INTEDG
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
GPPU: GPIO Pull-up Enable bit
1= GPIO pull-ups are disabled
0= GPIO pull-ups are enabled by individual PORT latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of GP2/INT pin
0= Interrupt on falling edge of GP2/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on GP2/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on GP2/T0CKI pin
0= Increment on low-to-high transition on GP2/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the TIMER0 module
PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
DS41190G-page 14
2010 Microchip Technology Inc.
PIC12F629/675
2.2.2.3
INTCON Register
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, GPIO port change and
external GP2/INT pin interrupts.
REGISTER 2-3:
INTCON: INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
GPIE
R/W-0
T0IF
R/W-0
INTF
R/W-0
GPIF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
GIE: Global Interrupt Enable bit
1= Enables all unmasked interrupts
0= Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
INTE: GP2/INT External Interrupt Enable bit
1= Enables the GP2/INT external interrupt
0= Disables the GP2/INT external interrupt
GPIE: Port Change Interrupt Enable bit(1)
1= Enables the GPIO port change interrupt
0= Disables the GPIO port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit(2)
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: GP2/INT External Interrupt Flag bit
1= The GP2/INT external interrupt occurred (must be cleared in software)
0= The GP2/INT external interrupt did not occur
GPIF: Port Change Interrupt Flag bit
1= When at least one of the GP5:GP0 pins changed state (must be cleared in software)
0= None of the GP5:GP0 pins have changed state
Note 1: IOC register must also be enabled to enable an interrupt-on-change.
2: T0IF bit is set when TIMER0 rolls over. TIMER0 is unchanged on Reset and should be initialized before
clearing T0IF bit.
2010 Microchip Technology Inc.
DS41190G-page 15
PIC12F629/675
2.2.2.4
PIE1 Register
The PIE1 register contains the interrupt enable bits, as
shown in Register 2-4.
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
REGISTER 2-4:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
R/W-0
EEIE
R/W-0
ADIE
U-0
U-0
R/W-0
CMIE
U-0
U-0
R/W-0
—
—
—
—
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
EEIE: EE Write Complete Interrupt Enable bit
1= Enables the EE write complete interrupt
0= Disables the EE write complete interrupt
ADIE: A/D Converter Interrupt Enable bit (PIC12F675 only)
1= Enables the A/D converter interrupt
0= Disables the A/D converter interrupt
bit 5-4
bit 3
Unimplemented: Read as ‘0’
CMIE: Comparator Interrupt Enable bit
1= Enables the comparator interrupt
0= Disables the comparator interrupt
bit 2-1
bit 0
Unimplemented: Read as ‘0’
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
DS41190G-page 16
2010 Microchip Technology Inc.
PIC12F629/675
2.2.2.5
PIR1 Register
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-5.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
REGISTER 2-5:
PIR1: PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch)
R/W-0
EEIF
R/W-0
ADIF
U-0
—
U-0
—
R/W-0
CMIF
U-0
—
U-0
—
R/W-0
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
EEIF: EEPROM Write Operation Interrupt Flag bit
1= The write operation completed (must be cleared in software)
0= The write operation has not completed or has not been started
ADIF: A/D Converter Interrupt Flag bit (PIC12F675 only)
1= The A/D conversion is complete (must be cleared in software)
0= The A/D conversion is not complete
bit 5-4
bit 3
Unimplemented: Read as ‘0’
CMIF: Comparator Interrupt Flag bit
1= Comparator input has changed (must be cleared in software)
0= Comparator input has not changed
bit 2-1
bit 0
Unimplemented: Read as ‘0’
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
2010 Microchip Technology Inc.
DS41190G-page 17
PIC12F629/675
2.2.2.6
PCON Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
• Power-on Reset (POR)
• Brown-out Detect (BOD)
• Watchdog Timer Reset (WDT)
• External MCLR Reset
The PCON Register bits are shown in Register 2-6.
REGISTER 2-6:
PCON: POWER CONTROL REGISTER (ADDRESS: 8Eh)
U-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
POR
R/W-x
BOD
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-2
bit 1
Unimplemented: Read as ‘0’
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOD: Brown-out Detect Status bit
1= No Brown-out Detect occurred
0= A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs)
2.2.2.7
OSCCAL Register
The Oscillator Calibration register (OSCCAL) is used to
calibrate the internal 4 MHz oscillator. It contains 6 bits
to adjust the frequency up or down to achieve 4 MHz.
The OSCCAL register bits are shown in Register 2-7.
REGISTER 2-7:
OSCCAL: OSCILLATOR CALIBRATION REGISTER (ADDRESS: 90h)
R/W-1
R/W-0
CAL4
R/W-0
CAL3
R/W-0
CAL2
R/W-0
CAL1
R/W-0
CAL0
U-0
—
U-0
—
CAL5
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-2
CAL5:CAL0: 6-bit Signed Oscillator Calibration bits
111111= Maximum frequency
100000= Center frequency
000000= Minimum frequency
bit 1-0
Unimplemented: Read as ‘0’
DS41190G-page 18
2010 Microchip Technology Inc.
PIC12F629/675
2.3.2
STACK
2.3
PCL and PCLATH
The PIC12F629/675 family has an 8-level deep x 13-bit
wide hardware stack (see Figure 2-1). The stack space
is not part of either program or data space and the
Stack Pointer is not readable or writable. The PC is
PUSHed onto the stack when a CALL instruction is
executed, or an interrupt causes a branch. The stack is
POPed in the event of a RETURN, RETLWor a RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The Program Counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.
On any Reset, the PC is cleared. Figure 2-3 shows the
two situations for the loading of the PC. The upper
example in Figure 2-3 shows how the PC is loaded on
a write to PCL (PCLATH<4:0> PCH). The lower
example in Figure 2-3 shows how the PC is loaded
during a CALL or GOTO instruction (PCLATH<4:3>
PCH).
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
FIGURE 2-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
Note 1: There are no Status bits to indicate Stack
Overflow or Stack Underflow conditions.
12
8
7
0
Instruction with
PCL as
Destination
PC
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.
8
PCLATH<4:0>
PCLATH
5
ALU result
PCH
12 11 10
PC
PCL
8
7
0
GOTO, CALL
PCLATH<4:3>
PCLATH
11
2
Opcode <10:0>
2.3.1
COMPUTED GOTO
A computed GOTOis accomplished by adding an offset
to the PC (ADDWF PCL). When performing a table read
using a computed GOTO method, care should be
exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to the
Application Note, “Implementing
a Table Read”
(AN556).
2010 Microchip Technology Inc.
DS41190G-page 19
PIC12F629/675
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 2-1.
2.4
Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
EXAMPLE 2-1:
INDIRECT ADDRESSING
MOVLW
MOVWF
CLRF
INCF
BTFSS
GOTO
0x20
FSR
INDF
FSR
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 2-2.
NEXT
FSR,4 ;all done?
NEXT ;no clear next
;yes continue
CONTINUE
FIGURE 2-2:
DIRECT/INDIRECT ADDRESSING PIC12F629/675
Direct Addressing
From Opcode
Indirect Addressing
(1)
(1)
7
RP1
RP0
6
0
0
IRP
FSR Register
Bank Select
180h
Location Select
Bank Select Location Select
00
01
10
11
00h
Data
Not Used
Memory
7Fh
1FFh
Bank 0
Bank 1
Bank 2
Bank 3
For memory map detail see Figure 2-2.
Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.
DS41190G-page 20
2010 Microchip Technology Inc.
PIC12F629/675
register are maintained set when using them as analog
inputs. I/O pins configured as analog inputs always
read ‘0’.
3.0
GPIO PORT
There are as many as six general purpose I/O pins
available. Depending on which peripherals are
enabled, some or all of the pins may not be available as
general purpose I/O. In general, when a peripheral is
enabled, the associated pin may not be used as a
general purpose I/O pin.
Note: The ANSEL (9Fh) and CMCON (19h)
registers (9Fh) must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’. The ANSEL register is defined for
the PIC12F675.
Note: Additional information on I/O ports may be
found in the PIC® Mid-Range Reference
Manual, (DS33023).
EXAMPLE 3-1:
INITIALIZING GPIO
BCF
STATUS,RP0
GPIO
07h
CMCON
STATUS,RP0
ANSEL
0Ch
;Bank 0
;Init GPIO
;Set GP<2:0> to
;digital IO
;Bank 1
;Digital I/O
;Set GP<3:2> as inputs
;and set GP<5:4,1:0>
;as outputs
3.1
GPIO and the TRISIO Registers
CLRF
MOVLW
MOVWF
BSF
CLRF
MOVLW
MOVWF
GPIO is an 6-bit wide, bidirectional port. The
corresponding data direction register is TRISIO.
Setting a TRISIO bit (= 1) will make the corresponding
GPIO pin an input (i.e., put the corresponding output
driver in a High-Impedance mode). Clearing a TRISIO
bit (= 0) will make the corresponding GPIO pin an
output (i.e., put the contents of the output latch on the
selected pin). The exception is GP3, which is input-only
and its TRISIO bit will always read as ‘1’. Example 3-1
shows how to initialize GPIO.
TRISIO
3.2
Additional Pin Functions
Every GPIO pin on the PIC12F629/675 has an
interrupt-on-change option and every GPIO pin, except
GP3, has a weak pull-up option. The next two sections
describe these functions.
Reading the GPIO register reads the status of the pins,
whereas writing to it will write to the PORT latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified, and then written to the
PORT data latch. GP3 reads ‘0’ when MCLREN = 1.
3.2.1
WEAK PULL-UP
Each of the GPIO pins, except GP3, has an individually
configurable weak internal pull-up. Control bits WPUx
enable or disable each pull-up. Refer to Register 3-3.
Each weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset by the GPPU bit
(OPTION<7>).
The TRISIO register controls the direction of the
GP pins, even when they are being used as analog
inputs. The user must ensure the bits in the TRISIO
REGISTER 3-1:
GPIO: GPIO REGISTER (ADDRESS: 05h)
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
—
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
GPIO<5:0>: General Purpose I/O pin
1= Port pin is >VIH
0= Port pin is <VIL
2010 Microchip Technology Inc.
DS41190G-page 21
PIC12F629/675
REGISTER 3-2:
TRISIO: GPIO TRI-STATE REGISTER (ADDRESS: 85h)
U-0
U-0
—
R/W-1
R/W-1
R-1
R/W-1
R/W-1
R/W-1
TRISIO5
TRISIO4
TRISIO3
TRISIO2
TRISIO1
TRISIO0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
TRISIO<5:0>: General Purpose I/O Tri-State Control bit
1= GPIO pin configured as an input (tri-stated)
0= GPIO pin configured as an output
Note:
TRISIO<3> always reads ‘1’.
REGISTER 3-3:
WPU: WEAK PULL-UP REGISTER (ADDRESS: 95h)
U-0
—
U-0
—
R/W-1
WPU5
R/W-1
WPU4
U-0
—
R/W-1
WPU2
R/W-1
WPU1
R/W-1
WPU0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
WPU<5:4>: Weak Pull-up Register bit
1= Pull-up enabled
0= Pull-up disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
WPU<2:0>: Weak Pull-up Register bit
1= Pull-up enabled
0= Pull-up disabled
Note 1: Global GPPU must be enabled for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISIO = 0).
DS41190G-page 22
2010 Microchip Technology Inc.
PIC12F629/675
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
3.2.2
INTERRUPT-ON-CHANGE
Each of the GPIO pins is individually configurable as an
interrupt-on-change pin. Control bits IOC enable or
disable the interrupt function for each pin. Refer to
Register 3-4. The interrupt-on-change is disabled on a
Power-on Reset.
a) Any read or write of GPIO. This will end the
mismatch condition.
b) Clear the flag bit GPIF.
A mismatch condition will continue to set flag bit GPIF.
Reading GPIO will end the mismatch condition and
allow flag bit GPIF to be cleared.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
GPIO. The ‘mismatch’ outputs of the last read are OR’d
together to set, the GP Port Change Interrupt flag bit
(GPIF) in the INTCON register.
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF inter-
rupt flag may not get set.
REGISTER 3-4:
IOC: INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h)
U-0
—
U-0
—
R/W-0
IOC5
R/W-0
IOC4
R/W-0
IOC3
R/W-0
IOC2
R/W-0
IOC1
R/W-0
IOC0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
IOC<5:0>: Interrupt-on-Change GPIO Control bits
1= Interrupt-on-change enabled
0= Interrupt-on-change disabled
Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.
2010 Microchip Technology Inc.
DS41190G-page 23
PIC12F629/675
FIGURE 3-1:
BLOCK DIAGRAM OF GP0
AND GP1 PINS
Analog
Input Mode
3.3
Pin Descriptions and Diagrams
Each GPIO pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the comparator or the A/D, refer to the
appropriate section in this Data Sheet.
Data Bus
D
Q
Q
VDD
WR
WPU
CK
Weak
3.3.1
GP0/AN0/CIN+
GPPU
RD
WPU
Figure 3-1 shows the diagram for this pin. The GP0 pin
is configurable to function as one of the following:
VDD
• a general purpose I/O
D
Q
Q
• an analog input for the A/D (PIC12F675 only)
• an analog input to the comparator
WR
PORT
CK
I/O pin
3.3.2
GP1/AN1/CIN-/VREF
D
Q
Q
Figure 3-1 shows the diagram for this pin. The GP1 pin
is configurable to function as one of the following:
WR
TRISIO
CK
VSS
Analog
Input Mode
• as a general purpose I/O
RD
TRISIO
• an analog input for the A/D (PIC12F675 only)
• an analog input to the comparator
RD
PORT
• a voltage reference input for the A/D (PIC12F675
only)
D
Q
Q
Q
Q
D
CK
WR
IOC
EN
RD
IOC
D
EN
Interrupt-on-Change
RD PORT
To Comparator
To A/D Converter
DS41190G-page 24
2010 Microchip Technology Inc.
PIC12F629/675
3.3.3
GP2/AN2/T0CKI/INT/COUT
3.3.4
GP3/MCLR/VPP
Figure 3-2 shows the diagram for this pin. The GP2 pin
is configurable to function as one of the following:
Figure 3-3 shows the diagram for this pin. The GP3 pin
is configurable to function as one of the following:
• a general purpose I/O
• a general purpose input
• as Master Clear Reset
• an analog input for the A/D (PIC12F675 only)
• the clock input for TMR0
FIGURE 3-3:
BLOCK DIAGRAM OF GP3
• an external edge triggered interrupt
• a digital output from the comparator
Data Bus
MCLRE
I/O pin
Reset
FIGURE 3-2:
BLOCK DIAGRAM OF GP2
RD
TRISIO
VSS
Analog
Input Mode
Data Bus
D
MCLRE
VSS
Q
Q
VDD
RD
PORT
WR
CK
Weak
WPU
D
Q
Q
Q
Q
D
CK
WR
IOC
GPPU
Analog
RD
WPU
EN
COUT
Input
RD
IOC
Enable
Mode
D
VDD
D
Q
Q
EN
WR
PORT
CK
Interrupt-on-Change
COUT
1
0
RD PORT
I/O pin
D
Q
Q
WR
TRISIO
CK
VSS
Analog
Input Mode
RD
TRISIO
RD
PORT
D
Q
Q
Q
D
D
CK
WR
IOC
EN
RD
IOC
Q
EN
Interrupt-on-Change
RD PORT
To TMR0
To INT
To A/D Converter
2010 Microchip Technology Inc.
DS41190G-page 25
PIC12F629/675
3.3.5
GP4/AN3/T1G/OSC2/CLKOUT
3.3.6
GP5/T1CKI/OSC1/CLKIN
Figure 3-4 shows the diagram for this pin. The GP4 pin
is configurable to function as one of the following:
Figure 3-5 shows the diagram for this pin. The GP5 pin
is configurable to function as one of the following:
• a general purpose I/O
• a general purpose I/O
• a TMR1 clock input
• a crystal/resonator connection
• a clock input
• an analog input for the A/D (PIC12F675 only)
• a TMR1 gate input
• a crystal/resonator connection
• a clock output
FIGURE 3-5:
BLOCK DIAGRAM OF GP5
FIGURE 3-4:
BLOCK DIAGRAM OF GP4
INTOSC
Mode
Analog
TMR1LPEN(1)
VDD
Input Mode
CLK
Data Bus
D
Modes(1)
VDD
Q
Q
Data Bus
D
Q
Q
WR
CK
Weak
WR
WPU
CK
WPU
Weak
GPPU
RD
GPPU
RD
WPU
WPU
Oscillator
Circuit
Oscillator
Circuit
OSC1
OSC2
VDD
VDD
D
Q
Q
CLKOUT
Enable
WR
PORT
CK
FOSC/4
1
0
D
Q
Q
I/O pin
I/O pin
WR
CK
D
Q
Q
PORT
CLKOUT
Enable
WR
TRISIO
CK
VSS
VSS
D
Q
Q
INTOSC
Mode
INTOSC/
RC/EC(2)
RD
TRISIO
WR
TRISIO
CK
CLKOUT
Enable
(2)
RD
PORT
RD
TRISIO
Analog
Input Mode
D
Q
Q
RD
PORT
Q
Q
D
CK
WR
IOC
D
Q
Q
EN
Q
D
D
RD
IOC
CK
WR
IOC
EN
D
RD
IOC
EN
Q
Interrupt-on-Change
EN
Interrupt-on-Change
RD PORT
RD PORT
To TMR1 or CLKGEN
To TMR1 T1G
To A/D Converter
Note 1: Timer1 LP Oscillator enabled
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
2: When using Timer1 with LP oscillator, the Schmitt
Trigger is by-passed.
2: With CLKOUT option.
DS41190G-page 26
2010 Microchip Technology Inc.
PIC12F629/675
TABLE 3-2:
SUMMARY OF REGISTERS ASSOCIATED WITH GPIO
Value on
POR,
Value on all
other
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOD
Resets
05h
GPIO
INTCON
—
GIE
—
—
PEIE
COUT
INTEDG
—
GP5
T0IE
—
GP4
INTE
CINV
T0SE
GP3
GPIE
CIS
GP2
T0IF
CM2
PS2
GP1
INTF
CM1
PS1
GP0
GPIF
CM0
PS0
--xx xxxx
0000 0000
-0-0 0000
1111 1111
--uu uuuu
0000 000u
-0-0 0000
1111 1111
--11 1111
--11 -111
--00 0000
-000 1111
0Bh/8Bh
19h
CMCON
OPTION_REG
TRISIO
WPU
81h
GPPU
—
T0CS
PSA
85h
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111
95h
—
—
WPU5
IOC5
WPU4
IOC4
—
WPU2
IOC2
WPU1
IOC1
WPU0
IOC0
--11 -111
--00 0000
-000 1111
96h
IOC
—
—
IOC3
ANS3
9Fh
ANSEL
—
ADCS2
ADCS1
ADCS0
ANS2
ANS1
ANS0
Legend: x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by GPIO.
2010 Microchip Technology Inc.
DS41190G-page 27
PIC12F629/675
NOTES:
DS41190G-page 28
2010 Microchip Technology Inc.
PIC12F629/675
Counter mode is selected by setting the T0CS bit
(OPTION_REG<5>). In this mode, the Timer0 module
will increment either on every rising or falling edge of
pin GP2/T0CKI. The incrementing edge is determined
4.0
TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
by
the
source
edge
(T0SE)
control
bit
• 8-bit timer/counter
(OPTION_REG<4>). Clearing the T0SE bit selects the
rising edge.
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Note: Counter mode has specific external clock
requirements. Additional information on
these requirements is available in the PIC®
Mid-Range
(DS33023).
Reference
Manual,
Figure 4-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
4.2
Timer0 Interrupt
Note: Additional information on the Timer0
module is available in the PIC® Mid-Range
Reference Manual, (DS33023).
A Timer0 interrupt is generated when the TMR0
register timer/counter overflows from FFh to 00h. This
overflow sets the T0IF bit. The interrupt can be masked
by clearing the T0IE bit (INTCON<5>). The T0IF bit
(INTCON<2>) must be cleared in software by the
Timer0 module Interrupt Service Routine before re-
enabling this interrupt. The Timer0 interrupt cannot
wake the processor from Sleep since the timer is shut-
off during Sleep.
4.1
Timer0 Operation
Timer mode is selected by clearing the T0CS bit
(OPTION_REG<5>). In Timer mode, the Timer0
module will increment every instruction cycle (without
prescaler). If TMR0 is written, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
FIGURE 4-1:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
CLKOUT
(= FOSC/4)
Data Bus
0
1
8
1
SYNC 2
Cycles
TMR0
T0CKI
pin
0
0
1
Set Flag bit T0IF
on Overflow
T0CS
T0SE
8-bit
Prescaler
PSA
8
PSA
1
0
PS0 - PS2
WDT
Time-out
Watchdog
Timer
PSA
WDTE
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
2010 Microchip Technology Inc.
DS41190G-page 29
PIC12F629/675
a small RC delay of 20 ns) and low for at least 2TOSC
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
4.3
Using Timer0 with an External
Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2TOSC (and
Note: The ANSEL (9Fh) and CMCON (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
The ANSEL register is defined for the
PIC12F675.
REGISTER 4-1:
R/W-1
OPTION_REG: OPTION REGISTER (ADDRESS: 81h)
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
GPPU
INTEDG
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
GPPU: GPIO Pull-up Enable bit
1= GPIO pull-ups are disabled
0= GPIO pull-ups are enabled by individual PORT latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of GP2/INT pin
0= Interrupt on falling edge of GP2/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on GP2/T0CK pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on GP2/T0CKI pin
0= Increment on low-to-high transition on GP2/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the TIMER0 module
PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
DS41190G-page 30
2010 Microchip Technology Inc.
PIC12F629/675
EXAMPLE 4-1:
CHANGING PRESCALER
(TIMER0WDT)
4.4
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. For simplicity, this counter will be referred to as
“prescaler” throughout this Data Sheet. The prescaler
assignment is controlled in software by the control bit
PSA (OPTION_REG<3>). Clearing the PSA bit will
assign the prescaler to Timer0. Prescale values are
selectable via the PS2:PS0 bits (OPTION_REG<2:0>).
BCF
STATUS,RP0 ;Bank 0
CLRWDT
CLRF
;Clear WDT
;Clear TMR0 and
; prescaler
TMR0
BSF
STATUS,RP0 ;Bank 1
MOVLW
MOVWF
CLRWDT
b’00101111’ ;Required if desired
OPTION_REG ; PS2:PS0 is
; 000 or 001
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing
to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1, x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer.
;
MOVLW
MOVWF
BCF
b’00101xxx’ ;Set postscaler to
OPTION_REG ; desired WDT rate
STATUS,RP0 ;Bank 0
4.4.1
SWITCHING PRESCALER
ASSIGNMENT
To change prescaler from the WDT to the TMR0
module, use the sequence shown in Example 4-2. This
precaution must be taken even if the WDT is disabled.
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution). To avoid an unintended device
Reset, the following instruction sequence (Example 4-
1) must be executed when changing the prescaler
assignment from Timer0 to WDT.
EXAMPLE 4-2:
CHANGING PRESCALER
(WDTTIMER0)
CLRWDT
;Clear WDT and
; postscaler
BSF
STATUS,RP0 ;Bank 1
MOVLW
b’xxxx0xxx’ ;Select TMR0,
; prescale, and
; clock source
;
MOVWF
BCF
OPTION_REG
STATUS,RP0 ;Bank 0
TABLE 4-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
all other
Resets
Value on
POR, BOD
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h
TMR0
Timer0 Module Register
GIE PEIE T0IE
GPPU INTEDG T0CS
xxxx xxxx uuuu uuuu
0000 0000 0000 000u
0Bh/8Bh INTCON
INTE
T0SE
GPIE
PSA
T0IF
PS2
INTF
PS1
GPIF
PS0
81h
85h
OPTION_REG
TRISIO
1111 1111 1111 1111
—
—
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
Legend: — = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown.
Shaded cells are not used by the Timer0 module.
2010 Microchip Technology Inc.
DS41190G-page 31
PIC12F629/675
The Timer1 Control register (T1CON), shown in
Register 5.1, is used to enable/disable Timer1 and
select the various features of the Timer1 module.
5.0
TIMER1 MODULE WITH GATE
CONTROL
The PIC12F629/675 devices have a 16-bit timer.
Figure 5-1 shows the basic block diagram of the Timer1
module. Timer1 has the following features:
Note: Additional information on timer modules is
available in the PIC® Mid-Range Refer-
ence Manual, (DS33023).
• 16-bit timer/counter (TMR1H:TMR1L)
• Readable and writable
• Internal or external clock selection
• Synchronous or asynchronous operation
• Interrupt on overflow from FFFFh to 0000h
• Wake-up upon overflow (Asynchronous mode)
• Optional external enable input (T1G)
• Optional LP oscillator
FIGURE 5-1:
TIMER1 BLOCK DIAGRAM
TMR1ON
TMR1GE
T1G
TMR1ON
TMR1GE
Set Flag bit
TMR1IF on
Overflow
TMR1
Synchronized
Clock Input
0
TMR1L
TMR1H
1
LP Oscillator
T1SYNC
OSC1
OSC2
1
0
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
2
Sleep Input
T1CKPS<1:0>
INTOSC
w/o CLKOUT
TMR1CS
T1OSCEN
LP
DS41190G-page 32
2010 Microchip Technology Inc.
PIC12F629/675
5.1
Timer1 Modes of Operation
5.2
Timer1 Interrupt
Timer1 can operate in one of three modes:
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit (PIR1<0>) is set. To
enable the interrupt on rollover, you must set these bits:
• 16-bit timer with prescaler
• 16-bit synchronous counter
• 16-bit asynchronous counter
• Timer1 interrupt Enable bit (PIE1<0>)
• PEIE bit (INTCON<6>)
In Timer mode, Timer1 is incremented on every
instruction cycle. In Counter mode, Timer1 is
incremented on the rising edge of the external clock
input T1CKI. In addition, the Counter mode clock can
be synchronized to the microcontroller system clock
or run asynchronously.
• GIE bit (INTCON<7>).
The interrupt is cleared by clearing the TMR1IF in the
Interrupt Service Routine.
Note: The TMR1H:TTMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
In counter and timer modules, the counter/timer clock
can be gated by the T1G input.
If an external clock oscillator is needed (and the
microcontroller is using the INTOSC w/o CLKOUT),
Timer1 can use the LP oscillator as a clock source.
5.3
Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4, or 8
divisions of the clock input. The T1CKPS bits
(T1CON<5:4>) control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write
to TMR1H or TMR1L.
Note: In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge.
FIGURE 5-2:
TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the
clock.
2010 Microchip Technology Inc.
DS41190G-page 33
PIC12F629/675
REGISTER 5-1:
T1CON: TIMER1 CONTROL REGISTER (ADDRESS: 10h)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TMR1GE
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
Unimplemented: Read as ‘0’
TMR1GE: Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1= Timer1 is on if T1G pin is low
0= Timer1 is on
bit 5-4
bit 3
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale Value
10= 1:4 Prescale Value
01= 1:2 Prescale Value
00= 1:1 Prescale Value
T1OSCEN: LP Oscillator Enable Control bit
If INTOSC without CLKOUT oscillator is active:
1= LP oscillator is enabled for Timer1 clock
0= LP oscillator is off
Else:
This bit is ignored
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from T1OSO/T1CKI pin (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
DS41190G-page 34
2010 Microchip Technology Inc.
PIC12F629/675
5.4
Timer1 Operation in
5.5
Timer1 Oscillator
Asynchronous Counter Mode
A crystal oscillator circuit is built-in between pins OSC1
(input) and OSC2 (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The
oscillator is a low-power oscillator rated up to 37 kHz. It
will continue to run during Sleep. It is primarily intended
for a 32 kHz crystal. Table 9-2 shows the capacitor
selection for the Timer1 oscillator.
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer
(Section 5.4.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer1 can use this mode only when
the system clock is derived from the internal oscillator.
As with the system LP oscillator, the user must provide
a software time delay to ensure proper oscillator
start-up.
Note: The ANSEL (9Fh) and CMCON (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
The ANSEL register is defined for the
PIC12F675.
While enabled, TRISIO4 and TRISIO5 are set. GP4
and GP5 read ‘0’ and TRISIO4 and TRISIO5 are read
‘1’.
Note: The oscillator requires a start-up and stabi-
lization time before use. Thus, T1OSCEN
should be set and a suitable delay
observed prior to enabling Timer1.
5.4.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L, while the timer is running
from an external asynchronous clock, will ensure a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself, poses certain problems, since
the timer may overflow between the reads.
5.6
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To setup the timer to wake the device:
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the timer register.
• Timer1 must be on (T1CON<0>)
• TMR1IE bit (PIE1<0>) must be set
• PEIE bit (INTCON<6>) must be set
Reading the 16-bit value requires some care.
Examples 12-2 and 12-3 in the PIC® Mid-Range MCU
Family Reference Manual (DS33023) show how to
read and write Timer1 when it is running in
Asynchronous mode.
The device will wake-up on an overflow. If the GIE bit
(INTCON<7>) is set, the device will wake-up and jump
to the Interrupt Service Routine on an overflow.
TABLE 5-1:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
Value on
POR, BOD
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
0Bh/8Bh INTCON GIE
PEIE
ADIF
T0IE
—
INTE
—
GPIE
CMIF
T0IF
—
INTF
—
GPIF 0000 0000 0000 000u
TMR1IF 00-- 0--0 00-- 0--0
xxxx xxxx uuuu uuuu
0Ch
0Eh
0Fh
10h
8Ch
PIR1
EEIF
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
T1CON
PIE1
—
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu
ADIE CMIE TMR1IE 00-- 0--0 00-- 0--0
EEIE
—
—
—
—
Legend: x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
2010 Microchip Technology Inc.
DS41190G-page 35
PIC12F629/675
NOTES:
DS41190G-page 36
2010 Microchip Technology Inc.
PIC12F629/675
The Comparator Control Register (CMCON), shown
in Register 6-1, contains the bits to control the
comparator.
6.0
COMPARATOR MODULE
The PIC12F629/675 devices have one analog
comparator. The inputs to the comparator are
multiplexed with the GP0 and GP1 pins. There is an
on-chip Comparator Voltage Reference that can also
be applied to an input of the comparator. In addition,
GP2 can be configured as the comparator output.
REGISTER 6-1:
CMCON: COMPARATOR CONTROL REGISTER (ADDRESS: 19h)
U-0
—
R-0
U-0
—
R/W-0
CINV
R/W-0
CIS
R/W-0
CM2
R/W-0
CM1
R/W-0
CM0
COUT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
COUT: Comparator Output bit
When CINV = 0:
1= VIN+ > VIN-
0= VIN+ < VIN-
When CINV = 1:
1= VIN+ < VIN-
0= VIN+ > VIN-
bit 5
bit 4
Unimplemented: Read as ‘0’
CINV: Comparator Output Inversion bit
1= Output inverted
0= Output not inverted
bit 3
CIS: Comparator Input Switch bit
When CM2:CM0 = 110or 101:
1= VIN- connects to CIN+
0= VIN- connects to CIN-
bit 2-0
CM2:CM0: Comparator Mode bits
Figure 6-2 shows the Comparator modes and CM2:CM0 bit settings
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TABLE 6-1:
OUTPUT STATE VS. INPUT
CONDITIONS
6.1
Comparator Operation
A single comparator is shown in Figure 6-1, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 6-1 represent
the uncertainty due to input offsets and response time.
Input Conditions
CINV
COUT
VIN- > VIN+
VIN- < VIN+
VIN- > VIN+
VIN- < VIN+
0
0
1
1
0
1
1
0
FIGURE 6-1:
SINGLE COMPARATOR
Note: To use CIN+ and CIN- pins as analog
inputs, the appropriate bits must be
programmed in the CMCON (19h) register.
VIN+
VIN-
+
Output
The polarity of the comparator output can be inverted
by setting the CINV bit (CMCON<4>). Clearing CINV
results in a non-inverted output. A complete table
showing the output state versus input conditions and
the polarity bit is shown in Table 6-1.
–
VIN-
VIN+
Output
Note:
CINV bit (CMCON<4>) is clear.
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6.2
Comparator Configuration
There are eight modes of operation for the comparator.
The CMCON register, shown in Register 6-1, is used to
select the mode. Figure 6-2 shows the eight possible
modes. The TRISIO register controls the data direction
of the comparator pins for each mode. If the
Comparator mode is changed, the comparator output
level may not be valid for a specified period of time.
Refer to the specifications in Section 12.0 “Electri-
cal Specifications”.
Note: Comparator interrupts should be disabled
during a Comparator mode change. Other-
wise, a false interrupt may occur.
FIGURE 6-2:
COMPARATOR I/O OPERATING MODES
Comparator Reset (POR Default Value - low power)
Comparator Off (Lowest power)
CM2:CM0 = 111
CM2:CM0 = 000
GP1/CIN-
GP0/CIN+
A
A
GP1/CIN-
GP0/CIN+
D
D
Off (Read as ‘0’)
Off (Read as ‘0’)
GP2/COUT
D
GP2/COUT
D
Comparator without Output
Comparator w/o Output and with Internal Reference
CM2:CM0 = 010
CM2:CM0 = 100
GP1/CIN-
GP0/CIN+
A
A
GP1/CIN-
GP0/CIN+
A
D
COUT
COUT
GP2/COUT
D
GP2/COUT
D
From CVREF Module
Comparator with Output and Internal Reference
Multiplexed Input with Internal Reference and Output
CM2:CM0 = 011
CM2:CM0 = 101
GP1/CIN-
GP0/CIN+
A
D
GP1/CIN-
GP0/CIN+
A
A
CIS = 0
CIS = 1
COUT
COUT
GP2/COUT
D
GP2/COUT
D
From CVREF Module
From CVREF Module
Comparator with Output
Multiplexed Input with Internal Reference
CM2:CM0 = 001
CM2:CM0 = 110
GP1/CIN-
GP0/CIN+
A
A
GP1/CIN-
GP0/CIN+
A
A
CIS = 0
CIS = 1
COUT
COUT
GP2/COUT
D
GP2/COUT
D
From CVREF Module
A = Analog Input, ports always reads ‘0’
D = Digital Input
CIS = Comparator Input Switch (CMCON<3>)
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range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
6.3
Analog Input Connection
Considerations
maximum
source
impedance
of
10 k
is
A simplified circuit for an analog input is shown in
Figure 6-3. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
FIGURE 6-3:
ANALOG INPUT MODE
VDD
VT = 0.6V
RIC
Rs < 10K
AIN
Leakage
±500 nA
CPIN
5 pF
VA
VT = 0.6V
Vss
Legend:
CPIN
VT
= Input Capacitance
= Threshold Voltage
ILEAKAGE
RIC
= Leakage Current at the pin due to Various Junctions
= Interconnect Resistance
RS
= Source Impedance
VA
= Analog Voltage
The TRISIO<2> bit functions as an output enable/
disable for the GP2 pin while the comparator is in an
Output mode.
6.4
Comparator Output
The comparator output, COUT, is read through the
CMCON register. This bit is read-only. The comparator
output may also be directly output to the GP2 pin in
three of the eight possible modes, as shown in
Figure 6-2. When in one of these modes, the output on
GP2 is asynchronous to the internal clock. Figure 6-4
shows the comparator output block diagram.
Note 1: When reading the GPIO register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
TTL input specification.
2: Analog levels on any pin that is defined as
a digital input, may cause the input buffer
to consume more current than is
specified.
FIGURE 6-4:
MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM
GP0/CIN+
GP1/CIN-
CVREF
To GP2/T0CKI pin
To Data Bus
RD CMCON
Q
Q
D
EN
CINV
CM2:CM0
Set CMIF bit
D
RD CMCON
EN
Reset
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The following equations determine the output voltages:
6.5
Comparator Reference
VRR = 1 (low range): CVREF = (VR3:VR0 / 24) x VDD
The comparator module also allows the selection of an
internally generated voltage reference for one of the
comparator inputs. The internal reference signal is
used for four of the eight Comparator modes. The
VRCON register, Register 6-2, controls the voltage
reference module shown in Figure 6-5.
VRR = 0 (high range): CVREF = (VDD / 4) + (VR3:VR0 x
VDD / 32)
6.5.2
VOLTAGE REFERENCE
ACCURACY/ERROR
6.5.1
CONFIGURING THE VOLTAGE
REFERENCE
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 6-5) keep CVREF from approaching VSS or
VDD. The Voltage Reference is VDD derived and there-
fore, the CVREF output changes with fluctuations in
VDD. The tested absolute accuracy of the Comparator
Voltage Reference can be found in Section 12.0
“Electrical Specifications”.
The voltage reference can output 32 distinct voltage
levels, 16 in a high range and 16 in a low range.
FIGURE 6-5:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
8R
R
R
R
R
VDD
VRR
8R
16-1 Analog
MUX
VREN
CVREF to
Comparator
Input
VR3:VR0
While the comparator is enabled during Sleep, an inter-
rupt will wake-up the device. If the device wakes up
from Sleep, the contents of the CMCON and VRCON
registers are not affected.
6.6
Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is ensured to have a valid level. If
the internal reference is changed, the maximum delay
of the internal voltage reference must be considered
when using the comparator outputs. Otherwise, the
maximum delay of the comparators should be used
(Table 12-7).
6.8
Effects of a Reset
A device Reset forces the CMCON and VRCON
registers to their Reset states. This forces the
comparator module to be in the Comparator Reset
mode, CM2:CM0 = 000and the voltage reference to its
off state. Thus, all potential inputs are analog inputs
with the comparator and voltage reference disabled to
consume the smallest current possible.
6.7
Operation During Sleep
Both the comparator and voltage reference, if enabled
before entering Sleep mode, remain active during
Sleep. This results in higher Sleep currents than shown
in the power-down specifications. The additional cur-
rent consumed by the comparator and the voltage ref-
erence is shown separately in the specifications. To
minimize power consumption while in Sleep mode, turn
off the comparator, CM2:CM0 = 111, and voltage refer-
ence, VRCON<7> = 0.
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REGISTER 6-2:
R/W-0
VRCON: VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)
U-0
—
R/W-0
VRR
R/W-0
—
R/W-0
VR3
R/W-0
VR2
R/W-0
VR1
R/W-0
VR0
VREN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
VREN: CVREF Enable bit
1= CVREF circuit powered on
0= CVREF circuit powered down, no IDD drain
bit 6
bit 5
Unimplemented: Read as ‘0’
VRR: CVREF Range Selection bit
1= Low range
0= High range
bit 4
Unimplemented: Read as ‘0’
bit 3-0
VR3:VR0: CVREF value selection 0 VR [3:0] 15
When VRR = 1: CVREF = (VR3:VR0 / 24) * VDD
When VRR = 0: CVREF = VDD/4 + (VR3:VR0 / 32) * VDD
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
6.9
Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of the comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<6>, to
determine the actual change that has occurred. The
CMIF bit, PIR1<3>, is the comparator interrupt flag.
This bit must be reset in software by clearing it to ‘0’.
Since it is also possible to write a ‘1’ to this register, a
simulated interrupt may be initiated.
a) Any read or write of CMCON. This will end the
mismatch condition.
b) Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition, and
allow flag bit CMIF to be cleared.
Note: If a change in the CMCON register (COUT)
should occur when a read operation is
being executed (start of the Q2 cycle), then
the CMIF (PIR1<3>) interrupt flag may not
get set.
The CMIE bit (PIE1<3>) and the PEIE bit (INT-
CON<6>) must be set to enable the interrupt. In addi-
tion, the GIE bit must also be set. If any of these bits are
cleared, the interrupt is not enabled, though the CMIF
bit will still be set if an interrupt condition occurs.
TABLE 6-2:
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Value on
Value on
POR, BOD
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
0Bh/8Bh
0Ch
INTCON
PIR1
GIE
EEIF
—
PEIE
ADIF
COUT
ADIE
—
T0IE
—
INTE
—
GPIE
CMIF
CIS
T0IF
—
INTF
—
GPIF
0000 0000 0000 000u
TMR1IF 00-- 0--0 00-- 0--0
CM0
TMR1IE 00-- 0--0 00-- 0--0
19h
CMCON
PIE1
—
CINV
—
CM2
—
CM1
—
-0-0 0000 -0-0 0000
8Ch
EEIE
—
—
CMIE
85h
TRISIO
VRCON
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
VRR VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000
99h
VREN
—
—
Legend:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the comparator module.
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circuit. The output of the sample and hold is connected
to the input of the converter. The converter generates a
binary result via successive approximation and stores
the result in a 10-bit register. The voltage reference
used in the conversion is software selectable to either
VDD or a voltage applied by the VREF pin. Figure 7-1
shows the block diagram of the A/D on the PIC12F675.
7.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
(PIC12F675 ONLY)
The Analog-to-Digital converter (A/D) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. The PIC12F675 has four
analog inputs, multiplexed into one sample and hold
FIGURE 7-1:
A/D BLOCK DIAGRAM
VDD
VCFG = 0
VCFG = 1
VREF
GP0/AN0
GP1/AN1/VREF
GP2/AN2
ADC
10
GO/DONE
GP4/AN3
ADFM
CHS1:CHS0
10
ADON
ADRESH ADRESL
VSS
controls the voltage reference selection. If VCFG is set,
then the voltage on the VREF pin is the reference;
otherwise, VDD is the reference.
7.1
A/D Configuration and Operation
There are two registers available to control the
functionality of the A/D module:
7.1.4
CONVERSION CLOCK
1. ADCON0 (Register 7-1)
2. ANSEL (Register 7-2)
The A/D conversion cycle requires 11 TAD. The source
of the conversion clock is software selectable via the
ADCS bits (ANSEL<6:4>). There are seven possible
clock options:
7.1.1
ANALOG PORT PINS
The ANS3:ANS0 bits (ANSEL<3:0>) and the TRISIO
bits control the operation of the A/D port pins. Set the
corresponding TRISIO bits to set the pin output driver
to its high-impedance state. Likewise, set the
corresponding ANS bit to disable the digital input
buffer.
• FOSC/2
• FOSC/4
• FOSC/8
• FOSC/16
• FOSC/32
Note: Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
• FOSC/64
• FRC (dedicated internal RC oscillator)
For correct conversion, the A/D conversion clock
(1/TAD) must be selected to ensure a minimum TAD of
1.6 s. Table 7-1 shows a few TAD calculations for
selected frequencies.
7.1.2
CHANNEL SELECTION
There are four analog channels on the PIC12F675,
AN0 through AN3. The CHS1:CHS0 bits
(ADCON0<3:2>) control which channel is connected to
the sample and hold circuit.
7.1.3
VOLTAGE REFERENCE
There are two options for the voltage reference to the
A/D converter: either VDD is used, or an analog voltage
applied to VREF is used. The VCFG bit (ADCON0<6>)
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TABLE 7-1:
TAD vs. DEVICE OPERATING FREQUENCIES
Device Frequency
A/D Clock Source (TAD)
Operation
2 TOSC
ADCS2:ADCS0
20 MHz
100 ns(2)
200 ns(2)
400 ns(2)
800 ns(2)
1.6 s
5 MHz
4 MHz
500 ns(2)
1.0 s(2)
2.0 s
1.25 MHz
1.6 s
3.2 s
000
100
001
101
010
110
x11
400 ns(2)
800 ns(2)
1.6 s
4 TOSC
8 TOSC
6.4 s
16 TOSC
32 TOSC
64 TOSC
A/D RC
3.2 s
6.4 s
12.8 s(3)
2 - 6 s(1,4)
4.0 s
12.8 s(3)
25.6 s(3)
51.2 s(3)
2 - 6 s(1,4)
8.0 s(3)
16.0 s(3)
2 - 6 s(1,4)
3.2 s
2 - 6 s(1,4)
Legend:Shaded cells are outside of recommended range.
Note 1: The A/D RC source has a typical TAD time of 4 s for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the
conversion will be performed during Sleep.
previous conversion. After an aborted conversion, a
2 TAD delay is required before another acquisition can
be initiated. Following the delay, an input acquisition is
automatically started on the selected channel.
7.1.5
STARTING A CONVERSION
The A/D conversion is initiated by setting the
GO/DONE bit (ADCON0<1>). When the conversion is
complete, the A/D module:
Note: The GO/DONE bit should not be set in the
• Clears the GO/DONE bit
same instruction that turns on the A/D.
• Sets the ADIF flag (PIR1<6>)
• Generates an interrupt (if enabled)
7.1.6
CONVERSION OUTPUT
If the conversion must be aborted, the GO/DONE bit
can be cleared in software. The ADRESH:ADRESL
registers will not be updated with the partially complete
The A/D conversion can be supplied in two formats: left
or right shifted. The ADFM bit (ADCON0<7>) controls
the output format. Figure 7-2 shows the output formats.
A/D
conversion
sample.
Instead,
the
ADRESH:ADRESL registers will retain the value of the
FIGURE 7-2:
10-BIT A/D RESULT FORMAT
ADRESH
ADRESL
LSB
(ADFM = 0)
MSB
Bit 7
Bit 0
Bit 7
Bit 0
10-bit A/D Result
Unimplemented: Read as ‘0’
(ADFM = 1)
MSB
LSB
Bit 0
Bit 7
Bit 0
Bit 7
Unimplemented: Read as ‘0’
10-bit A/D Result
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REGISTER 7-1:
R/W-0
ADCON0: A/D CONTROL REGISTER (ADDRESS: 1Fh)
R/W-0
VCFG
U-0
—
U-0
—
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
ADON
ADFM
GO/DONE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
ADFM: A/D Result Formed Select bit
1= Right justified
0= Left justified
VCFG: Voltage Reference bit
1= VREF pin
0= VDD
bit 5-4
bit 3-2
Unimplemented: Read as ‘0’
CHS1:CHS0: Analog Channel Select bits
00= Channel 00 (AN0)
01= Channel 01 (AN1)
10= Channel 02 (AN2)
11= Channel 03 (AN3)
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
1= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0= A/D conversion completed/not in progress
ADON: A/D Conversion Status bit
1= A/D converter module is operating
0= A/D converter is shut-off and consumes no operating current
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REGISTER 7-2:
ANSEL: ANALOG SELECT REGISTER (ADDRESS: 9Fh)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-1
ANS3
R/W-1
ANS2
R/W-1
ANS1
R/W-1
ANS0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-4
ADCS<2:0>: A/D Conversion Clock Select bits
000= Fosc/2
001= Fosc/8
010= Fosc/32
x11= FRC (clock derived from a dedicated internal oscillator = 500 kHz max)
100= Fosc/4
101= Fosc/16
110= Fosc/64
bit 3-0
ANS3:ANS0: Analog Select bits
(Between analog or digital function on pins AN<3:0>, respectively.)
1= Analog input; pin is assigned as analog input(1)
0= Digital I/O; pin is assigned to port or special function
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and inter-
rupt-on-change. The corresponding TRISIO bit must be set to Input mode in order to allow external control
of the voltage on the pin.
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is decreased, the acquisition time may be decreased.
After the analog input channel is selected (changed),
this acquisition must be done before the conversion
can be started.
7.2
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 7-3. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
Figure 7-3. The maximum recommended imped-
ance for analog sources is 10 k. As the impedance
To calculate the minimum acquisition time,
Equation 7-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D).
The 1/2 LSb error is the maximum error allowed for
the A/D to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the PIC® Mid-Range Reference Manual (DS33023).
EQUATION 7-1:
ACQUISITION TIME
TACQ
= Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
= TAMP + TC + TCOFF
= 2s + TC + [(Temperature -25°C)(0.05s/°C)]
= CHOLD (RIC + RSS + RS) In(1/2047)
= - 120pF (1k + 7k + 10k) In(0.0004885)
= 16.47s
= 2s + 16.47s + [(50°C -25C)(0.05s/C)
= 19.72s
TC
TACQ
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
FIGURE 7-3:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC 1K
RSS
RS
CHOLD
CPIN
5 pF
= DAC capacitance
= 120 pF
VA
I LEAKAGE
± 500 nA
VT = 0.6V
VSS
Legend: CPIN
= input capacitance
= threshold voltage
6V
5V
VT
I LEAKAGE = leakage current at the pin due to
VDD 4V
3V
various junctions
= interconnect resistance
= sampling switch
2V
RIC
SS
CHOLD
= sample/hold capacitance (from DAC)
5 6 7 8 9 1011
Sampling Switch
(k)
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When the A/D clock source is something other than
RC, a SLEEPinstruction causes the present conversion
to be aborted, and the A/D module is turned off. The
ADON bit remains set.
7.3
A/D Operation During Sleep
The A/D converter module can operate during Sleep.
This requires the A/D clock source to be set to the
internal RC oscillator. When the RC clock source is
selected, the A/D waits one instruction before starting
the conversion. This allows the SLEEPinstruction to be
executed, thus eliminating much of the switching noise
from the conversion. When the conversion is complete,
the GO/DONE bit is cleared, and the result is loaded
into the ADRESH:ADRESL registers. If the A/D
interrupt is enabled, the device awakens from Sleep. If
the A/D interrupt is not enabled, the A/D module is
turned off, although the ADON bit remains set.
7.4
Effects of Reset
A device Reset forces all registers to their Reset state.
Thus the A/D module is turned off and any pending
conversion is aborted. The ADRESH:ADRESL
registers are unchanged.
TABLE 7-2:
SUMMARY OF A/D REGISTERS
Value on
POR,
BOD
Value on
all other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
05h
GPIO
—
—
GPIO5
T0IE
—
GPIO4
INTE
—
GPIO3
GPIE
CMIF
GPIO2
T0IF
—
GPIO1
INTF
—
GPIO0 --xx xxxx --uu uuuu
GPIF 0000 0000 0000 000u
TMR1IF 00-- 0--0 00-- 0--0
0Bh, 8Bh INTCON
GIE
EEIF
PEIE
ADIF
0Ch
1Eh
1Fh
85h
8Ch
9Eh
9Fh
PIR1
ADRESH Most Significant 8 bits of the Left Shifted A/D result or 2 bits of the Right Shifted Result
xxxx xxxx uuuu uuuu
00-- 0000 00-- 0000
ADCON0
TRISIO
PIE1
ADFM
—
VCFG
—
—
—
CHS1
CHS0
GO
ADON
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
CMIE TMR1IE 00-- 0--0 00-- 0--0
EEIE
ADIE
—
—
—
—
ADRESL Least Significant 2 bits of the Left Shifted A/D Result or 8 bits of the Right Shifted Result
ANSEL ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0
xxxx xxxx uuuu uuuu
-000 1111 -000 1111
—
Legend: x= unknown, u= unchanged, -= unimplemented read as ‘0’. Shaded cells are not used for A/D converter module.
DS41190G-page 48
2010 Microchip Technology Inc.
PIC12F629/675
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write). The EEPROM
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The write
time will vary with voltage and temperature as well as
from chip to chip. Please refer to AC Specifications for
exact limits.
8.0
DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during normal operation (full VDD range). This memory
is not directly mapped in the register file space.
Instead, it is indirectly addressed through the Special
Function Registers. There are four SFRs used to read
and write this memory:
• EECON1
When the data memory is code-protected, the CPU
may continue to read and write the data EEPROM
memory. The device programmer can no longer access
this memory.
• EECON2 (not a physically implemented register)
• EEDATA
• EEADR
Additional information on the data EEPROM is
available in the PIC® Mid-Range Reference Manual,
(DS33023).
EEDATA holds the 8-bit data for read/write, and
EEADR holds the address of the EEPROM location
being accessed. PIC12F629/675 devices have 128
bytes of data EEPROM with an address range from 0h
to 7Fh.
REGISTER 8-1:
R/W-0
EEDAT: EEPROM DATA REGISTER (ADDRESS: 9Ah)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EEDAT7
bit 7
EEDAT6
EEDAT5
EEDAT4
EEDAT3
EEDAT2
EEDAT1
EEDAT0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
EEDATn: Byte value to write to or read from data EEPROM
REGISTER 8-2:
EEADR: EEPROM ADDRESS REGISTER (ADDRESS: 9Bh)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EADR6
EADR5
EADR4
EADR3
EADR2
EADR1
EADR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
Unimplemented: Should be set to ‘0’
EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation
bit 6-0
2010 Microchip Technology Inc.
DS41190G-page 49
PIC12F629/675
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
8.1
EEADR
The EEADR register can address up to a maximum of
128 bytes of data EEPROM. Only seven of the eight
bits in the register (EEADR<6:0>) are required. The
MSb (bit 7) is ignored.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset during normal
operation. In these situations, following Reset, the user
can check the WRERR bit, clear it, and rewrite the
location. The data and address will be cleared,
therefore, the EEDATA and EEADR registers will need
to be re-initialized.
The upper bit should always be ‘0’ to remain upward
compatible with devices that have more data EEPROM
memory.
8.2
EECON1 and EECON2 Registers
EECON1 is the control register with four low-order bits
physically implemented. The upper four bits are non-
implemented and read as ‘0’s.
Interrupt flag bit EEIF in the PIR1 register is set when
write is complete. This bit must be cleared in software.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the data EEPROM write sequence.
REGISTER 8-3:
EECON1: EEPROM CONTROL REGISTER (ADDRESS: 9Ch)
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
WRERR
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-4
bit 3
Unimplemented: Read as ‘0’
WRERR: EEPROM Error Flag bit
1= A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during normal
operation or BOD detect)
0= The write operation completed
bit 2
bit 1
WREN: EEPROM Write Enable bit
1= Allows write cycles
0= Inhibits write to the data EEPROM
WR: Write Control bit
1= Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only
be set, not cleared, in software.)
0= Write cycle to the data EEPROM is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only
be set, not cleared, in software).
0= Does not initiate an EEPROM read
DS41190G-page 50
2010 Microchip Technology Inc.
PIC12F629/675
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
8.3
Reading the EEPROM Data
Memory
To read a data memory location, the user must write
the address to the EEADR register and then set
control bit RD (EECON1<0>), as shown in
Example 8-1. The data is available, in the very next
cycle, in the EEDATA register. Therefore, it can be
read in the next instruction. EEDATA holds this value
until another read, or until it is written to by the user
(during a write operation).
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit
(PIR<7>) register must be cleared by software.
8.5
Write Verify
Depending on the application, good programming
practice may dictate that the value written to the data
EEPROM should be verified (see Example 8-3) to the
desired value to be written.
EXAMPLE 8-1:
DATA EEPROM READ
BSF
STATUS,RP0
;Bank 1
;
;Address to read
;EE Read
;Move data to W
MOVLW CONFIG_ADDR
MOVWF EEADR
EXAMPLE 8-3:
WRITE VERIFY
BSF
MOVF
EECON1,RD
EEDATA,W
BCF
:
STATUS,RP0
;Bank 0
;Any code
BSF
MOVF
STATUS,RP0
EEDATA,W
;Bank 1 READ
8.4
Writing to the EEPROM Data
Memory
;EEDATA not changed
;from previous write
;YES, Read the
BSF
EECON1,RD
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte, as
shown in Example 8-2.
;value written
XORWF EEDATA,W
BTFSS STATUS,Z
;Is data the same
;No, handle error
;Yes, continue
GOTO
:
WRITE_ERR
EXAMPLE 8-2:
DATA EEPROM WRITE
8.5.1
USING THE DATA EEPROM
high-endurance, byte
BSF
BSF
BCF
STATUS,RP0
EECON1,WREN
INTCON,GIE
;Bank 1
;Enable write
;Disable INTs
;Unlock write
;
;
;
The data EEPROM is
a
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated
often). Frequently changing values will typically be
updated more often than specifications D120 or
D120A. If this is not the case, an array refresh must be
performed. For this reason, variables that change
infrequently (such as constants, IDs, calibration, etc.)
should be stored in Flash program memory.
MOVLW 55h
MOVWF EECON2
MOVLW AAh
MOVWF EECON2
BSF
BSF
EECON1,WR
INTCON,GIE
;Start the write
;Enable INTS
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will
prevent the data from being written into the EEPROM.
8.6
Protection Against Spurious Write
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up Timer (72 ms duration) prevents
EEPROM write.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
The write initiate sequence and the WREN bit together
help prevent an accidental write during:
• brown-out
• power glitch
• software malfunction
2010 Microchip Technology Inc.
DS41190G-page 51
PIC12F629/675
8.7
Data EEPROM Operation During
Code Protect
Data memory can be code protected by programming
the CPD bit to ‘0’.
When the data memory is code protected, the CPU is
able to read and write data to the data EEPROM. It is
recommended to code protect the program memory
when code protecting data memory. This prevents
anyone from programming zeroes over the existing
code (which will execute as NOPs) to reach an added
routine, programmed in unused program memory,
which outputs the contents of data memory.
Programming unused locations to ‘0’ will also help
prevent data memory code protection from becoming
breached.
TABLE 8-1:
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Value on all
other
Resets
Value on
POR, BOD
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Ch
9Ah
9Bh
9Ch
9Dh
PIR1
EEIF
ADIF
—
—
CMIF
—
—
TMR1IF 00-- 0--0 00-- 0--0
0000 0000 0000 0000
EEDATA
EEADR
EEPROM Data Register
—
—
EEPROM Address Register
-000 0000 -000 0000
EECON1
EECON2
—
—
—
WRERR WREN
WR
RD
---- x000 ---- q000
---- ---- ---- ----
(1)
EEPROM Control Register 2
Legend: x= unknown, u= unchanged, - = unimplemented read as ‘0’, q= value depends upon condition.
Shaded cells are not used by data EEPROM module.
Note 1: EECON2 is not a physical register.
DS41190G-page 52
2010 Microchip Technology Inc.
PIC12F629/675
The PIC12F629/675 has a Watchdog Timer that is
controlled by Configuration bits. It runs off its own RC
oscillator for added reliability. There are two timers that
offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), intended to keep the
chip in Reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only,
designed to keep the part in Reset while the power
supply stabilizes. There is also circuitry to reset the
device if a brown-out occurs, which can provide at least
a 72 ms Reset. With these three functions on-chip,
most applications need no external Reset circuitry.
9.0
SPECIAL FEATURES OF THE
CPU
Certain special circuits that deal with the needs of real
time applications are what sets a microcontroller apart
from other processors. The PIC12F629/675 family has
a host of such features intended to:
• maximize system reliability
• minimize cost through elimination of external
components
• provide power saving operating modes and offer
code protection
These features are:
The Sleep mode is designed to offer a very low current
Power-down mode. The user can wake-up from Sleep
through:
• Oscillator selection
• Reset
• External Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Detect (BOD)
• Interrupts
• Watchdog Timer wake-up
• An interrupt
Several oscillator options are also made available to
allow the part to fit the application. The INTOSC option
saves system cost while the LP crystal option saves
power. A set of Configuration bits are used to select
various options (see Register 9.2).
• Watchdog Timer (WDT)
• Sleep
• Code protection
• ID Locations
• In-Circuit Serial Programming
2010 Microchip Technology Inc.
DS41190G-page 53
PIC12F629/675
9.1
Configuration Bits
Note:
Address 2007h is beyond the user program
memory space. It belongs to the special con-
figuration memory space (2000h-3FFFh),
which can be accessed only during program-
ming. See PIC12F629/675 Programming
Specification for more information.
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’) to select various
device configurations, as shown in Register 9.2. These
bits are mapped in program memory location 2007h.
REGISTER 9-1:
CONFIG: CONFIGURATION WORD (ADDRESS: 2007h)
R/P-1 R/P-1
U-0
U-0
U-0
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
BG1
BG0
—
—
—
CPD
CP
BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0
bit 0
bit 13
Legend:
P = Programmed using ICSP™
R = Readable bit
Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
-n = Value at POR
0 = bit is cleared
x = bit is unknown
(1)
bit 13-12
BG1:BG0: Bandgap Calibration bits for BOD and POR voltage
00= Lowest bandgap voltage
11= Highest bandgap voltage
bit 11-9
bit 8
Unimplemented: Read as ‘0’
(2)
CPD: Data Code Protection bit
1= Data memory code protection is disabled
0= Data memory code protection is enabled
(3)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
CP: Code Protection bit
1= Program Memory code protection is disabled
0= Program Memory code protection is enabled
(4)
BODEN: Brown-out Detect Enable bit
1= BOD enabled
0= BOD disabled
(5)
MCLRE: GP3/MCLR Pin Function Select bit
1= GP3/MCLR pin function is MCLR
0= GP3/MCLR pin function is digital I/O, MCLR internally tied to VDD
PWRTE: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
FOSC2:FOSC0: Oscillator Selection bits
111= RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN
110= RC oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN
101= INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN
100= INTOSC oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN
011= EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN
010= HS oscillator: High speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
001= XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
000= LP oscillator: Low-power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
Note 1: The Bandgap Calibration bits are factory programmed and must be read and saved prior to erasing the device as spec-
ified in the PIC12F629/675 Programming Specification. These bits are reflected in an export of the Configuration Word.
Microchip Development Tools maintain all Calibration bits to factory settings.
2: The entire data EEPROM will be erased when the code protection is turned off.
3: The entire program memory will be erased, including OSCCAL value, when the code protection is turned off.
4: Enabling Brown-out Detect does not automatically enable Power-up Timer.
5: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
DS41190G-page 54
2010 Microchip Technology Inc.
PIC12F629/675
FIGURE 9-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT, EC,
OR LP OSC
9.2
Oscillator Configurations
9.2.1
OSCILLATOR TYPES
CONFIGURATION)
The PIC12F629/675 can be operated in eight different
oscillator option modes. The user can program three
Configuration bits (FOSC2 through FOSC0) to select
one of these eight modes:
Clock from
External System
OSC1
PIC12F629/675
OSC2(1)
• LP
• XT
• HS
• RC
Low-Power Crystal
Open
Crystal/Resonator
High-Speed Crystal/Resonator
External Resistor/Capacitor (2 modes)
Note 1: Functions as GP4 in EC Osc mode.
• INTOSC Internal Oscillator (2 modes)
• EC External Clock In
TABLE 9-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Note: Additional information on oscillator config-
urations is available in the PIC® Mid-
Range Reference Manual, (DS33023).
Ranges Characterized:
Mode
Freq.
OSC1(C1)
OSC2(C2)
9.2.2
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
XT
455 kHz
2.0 MHz
4.0 MHz
68-100 pF
15-68 pF
15-68 pF
68-100 pF
15-68 pF
15-68 pF
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1 and OSC2 pins to establish
oscillation (see Figure 9-1). The PIC12F629/675
oscillator design requires the use of a parallel cut
crystal. Use of a series cut crystal may yield a
frequency outside of the crystal manufacturers
specifications. When in XT, LP or HS modes, the
device can have an external clock source to drive the
OSC1 pin (see Figure 9-2).
HS
8.0 MHz
16.0 MHz
10-68 pF
10-22 pF
10-68 pF
10-22 pF
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time. These values are for design
guidance only. Since each resonator has
its own characteristics, the user should
consult the resonator manufacturer for
appropriate values of external
FIGURE 9-1:
CRYSTAL OPERATION (OR
CERAMIC RESONATOR)
HS, XT OR LP OSC
components.
TABLE 9-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
CONFIGURATION
OSC1
Mode
Freq.
OSC1(C1)
OSC2(C2)
To Internal
Logic
C1(1)
LP
32 kHz
68-100 pF
68-100 pF
XTAL
XT
HS
100 kHz
2 MHz
4 MHz
68-150 pF
15-30 pF
15-30 pF
150-200 pF
15-30 pF
15-30 pF
Sleep
RF(3)
OSC2
RS(2)
C2(1)
PIC12F629/675
8 MHz
10 MHz
20 MHz
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
Note 1: See Table 9-1 and Table 9-2 for recommended
values of C1 and C2.
2: A series resistor may be required for AT strip cut
crystals.
3: RF varies with the Oscillator mode selected
(Approx. value = 10 M
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time. These values are for design
guidance only. Rs may be required in HS
mode as well as XT mode to avoid
overdriving crystals with low drive level
specification. Since each crystal has its
own characteristics, the user should
consult the crystal manufacturer for
appropriate values of external
components.
2010 Microchip Technology Inc.
DS41190G-page 55
PIC12F629/675
9.2.3
EXTERNAL CLOCK IN
9.2.5
INTERNAL 4 MHZ OSCILLATOR
For applications where a clock is already available
elsewhere, users may directly drive the PIC12F629/
675 provided that this external clock source meets the
AC/DC timing requirements listed in Section 12.0
“Electrical Specifications”. Figure 9-2 shows how
an external clock circuit should be configured.
When calibrated, the internal oscillator provides a fixed
4
MHz (nominal) system clock. See Electrical
Specifications, Section 12.0 “Electrical Specifica-
tions”, for information on variation over voltage and
temperature.
Two options are available for this Oscillator mode
which allow GP4 to be used as a general purpose I/O
or to output FOSC/4.
9.2.4
RC OSCILLATOR
For applications where precise timing is not a
requirement, the RC oscillator option is available. The
operation and functionality of the RC oscillator is
dependent upon a number of variables. The RC
oscillator frequency is a function of:
9.2.5.1
Calibrating the Internal Oscillator
A calibration instruction is programmed into the last
location of program memory. This instruction is a
RETLW XX, where the literal is the calibration value.
The literal is placed in the OSCCAL register to set the
calibration of the internal oscillator. Example 9-1
demonstrates how to calibrate the internal oscillator.
For best operation, decouple (with capacitance) VDD
and VSS as close to the device as possible.
• Supply voltage
• Resistor (REXT) and capacitor (CEXT) values
• Operating temperature.
The oscillator frequency will vary from unit to unit due
to normal process parameter variation. The difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to account for the
tolerance of the external R and C components.
Figure 9-3 shows how the R/C combination is
connected.
Note: Erasing the device will also erase the pre-
programmed internal calibration value for
the internal oscillator. The calibration value
must be saved prior to erasing part as
specified in the PIC12F629/675 Program-
ming specification. Microchip Develop-
ment Tools maintain all Calibration bits to
factory settings.
Two options are available for this Oscillator mode
which allow GP4 to be used as a general purpose I/O
or to output FOSC/4.
EXAMPLE 9-1:
CALIBRATING THE
INTERNAL OSCILLATOR
FIGURE 9-3:
RC OSCILLATOR MODE
BSF
CALL
MOVWF OSCCAL
BCF
STATUS, RP0
3FFh
;Bank 1
;Get the cal value
;Calibrate
VDD
PIC12F629/675
STATUS, RP0
;Bank 0
REXT
GP5/OSC1/
CLKIN
Internal
Clock
9.2.6
CLKOUT
CEXT
VSS
The PIC12F629/675 devices can be configured to
provide a clock out signal in the INTOSC and RC
oscillator modes. When configured, the oscillator
frequency divided by four (FOSC/4) is output on the
GP4/OSC2/CLKOUT pin. FOSC/4 can be used for test
purposes or to synchronize other logic.
FOSC/4
GP4/OSC2/CLKOUT
DS41190G-page 56
2010 Microchip Technology Inc.
PIC12F629/675
They are not affected by a WDT wake-up, since this is
viewed as the resumption of normal operation. TO and
PD bits are set or cleared differently in different Reset
situations as indicated in Table 9-4. These bits are
used in software to determine the nature of the Reset.
See Table 9-7 for a full description of Reset states of all
registers.
9.3
Reset
The PIC12F629/675 differentiates between various
kinds of Reset:
a) Power-on Reset (POR)
b) WDT Reset during normal operation
c) WDT Reset during Sleep
A simplified block diagram of the on-chip Reset Circuit
is shown in Figure 9-4.
d) MCLR Reset during normal operation
e) MCLR Reset during Sleep
f) Brown-out Detect (BOD)
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Table 12-4 in Electrical
Specifications Section for pulse-width specification.
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:
• Power-on Reset
• MCLR Reset
• WDT Reset
• WDT Reset during Sleep
• Brown-out Detect (BOD) Reset
FIGURE 9-4:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/
VPP pin
SLEEP
WDT
WDT
Module
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Detect
S
R
Q
Q
BODEN
OST/PWRT
OST
10-bit Ripple Counter
Chip_Reset
OSC1/
CLKIN
pin
PWRT
10-bit Ripple Counter
On-chip(1)
RC OSC
Enable PWRT
Enable OST
See Table 9-3 for time-out situations.
Note 1: This is a separate oscillator from the INTOSC/EC oscillator.
2010 Microchip Technology Inc.
DS41190G-page 57
PIC12F629/675
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting”.
9.3.1
MCLR
PIC12F629/675 devices have a noise filter in the
MCLR Reset path. The filter will detect and ignore
small pulses.
9.3.3
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal)
time-out on power-up only, from POR or Brown-out
Detect. The Power-up Timer operates on an internal
RC oscillator. The chip is kept in Reset as long as
PWRT is active. The PWRT delay allows the VDD to
rise to an acceptable level. A Configuration bit, PWRTE
can disable (if set) or enable (if cleared or
programmed) the Power-up Timer. The Power-up
Timer should always be enabled when Brown-out
Detect is enabled.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from previous devices of this family.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to VDD. The use of an RC
network, as shown in Figure 9-5, is suggested.
The Power-up Time delay will vary from chip to chip
and due to:
An internal MCLR option is enabled by setting the
MCLRE bit in the Configuration Word. When enabled,
MCLR is internally tied to VDD. No internal pull-up
option is available for the MCLR pin.
• VDD variation
• Temperature variation
• Process variation.
FIGURE 9-5:
RECOMMENDED MCLR
CIRCUIT
See DC parameters for details (Section 12.0 “Electri-
cal Specifications”).
VDD
R1
9.3.4
OSCILLATOR START-UP TIMER
(OST)
PIC12F629/675
1 kor greater
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
MCLR
C1
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
Sleep.
0.1 f
(optional, not critical)
9.3.2
POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper
operation. To take advantage of the POR, simply tie the
MCLR pin through a resistor to VDD. This will eliminate
external RC components usually needed to create
Power-on Reset. A maximum rise time for VDD is
required. See Electrical Specifications for details (see
Section 12.0 “Electrical Specifications”). If the BOD
is enabled, the maximum rise time specification does
not apply. The BOD circuitry will keep the device in
Reset until VDD reaches VBOD (see Section 9.3.5
“Brown-Out Detect (BOD)”).
Note: The POR circuit does not produce an
internal Reset when VDD declines.
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
DS41190G-page 58
2010 Microchip Technology Inc.
PIC12F629/675
On any Reset (Power-on, Brown-out, Watchdog, etc.),
the chip will remain in Reset until VDD rises above
BVDD (see Figure 9-6). The Power-up Timer will now
be invoked, if enabled, and will keep the chip in Reset
an additional 72 ms.
9.3.5
BROWN-OUT DETECT (BOD)
The PIC12F629/675 members have on-chip Brown-out
Detect circuitry. A Configuration bit, BODEN, can
disable (if clear/programmed) or enable (if set) the
Brown-out Detect circuitry. If VDD falls below VBOD for
greater than parameter (TBOD) in Table 12-4 (see
Section 12.0 “Electrical Specifications”), the
Brown-out situation will reset the device. This will occur
regardless of VDD slew-rate. A Reset is not guaranteed
to occur if VDD falls below VBOD for less than parameter
(TBOD).
Note: A Brown-out Detect does not enable the
Power-up Timer if the PWRTE bit in the
Configuration Word is set.
If VDD drops below BVDD while the Power-up Timer is
running, the chip will go back into a Brown-out Detect
and the Power-up Timer will be re-initialized. Once VDD
rises above BVDD, the Power-up Timer will execute a
72 ms Reset.
FIGURE 9-6:
BROWN-OUT SITUATIONS
VDD
VBOD
Internal
Reset
72 ms(1)
VDD
VBOD
Internal
Reset
<72 ms
72 ms(1)
VDD
VBOD
Internal
Reset
72 ms(1)
Note 1: 72 ms delay only if PWRTE bit is programmed to ‘0’.
9.3.6
TIME-OUT SEQUENCE
9.3.7
POWER CONTROL (PCON) STATUS
REGISTER
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired.
Then, OST is activated. The total time-out will vary
based on oscillator configuration and PWRTE bit
status. For example, in EC mode with PWRTE bit
erased (PWRT disabled), there will be no time-out at
all. Figure 9-7, Figure 9-8 and Figure 9-9 depict time-
out sequences.
The power CONTROL/STATUS register, PCON
(address 8Eh) has two bits.
Bit 0 is BOD (Brown-out). BOD is unknown on Power-
on Reset. It must then be set by the user and checked
on subsequent Resets to see if BOD = 0, indicating that
a brown-out has occurred. The BOD Status bit is a
“don’t care” and is not necessarily predictable if the
brown-out circuit is disabled (by setting BODEN bit = 0
in the Configuration Word).
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 9-8). This is useful for testing purposes or
to synchronize more than one PIC12F629/675 device
operating in parallel.
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset must have occurred (i.e., VDD may
have gone too low).
Table 9-6 shows the Reset conditions for some special
registers, while Table 9-7 shows the Reset conditions
for all the registers.
2010 Microchip Technology Inc.
DS41190G-page 59
PIC12F629/675
TABLE 9-3:
TIME-OUT IN VARIOUS SITUATIONS
Power-up
Brown-out Detect
Wake-up
Oscillator Configuration
from Sleep
PWRTE = 0
PWRTE = 1
PWRTE = 0
PWRTE = 1
XT, HS, LP
TPWRT +
1024•TOSC
1024•TOSC
TPWRT +
1024•TOSC
1024•TOSC
1024•TOSC
—
RC, EC, INTOSC
TPWRT
—
TPWRT
—
TABLE 9-4:
POR
STATUS/PCON BITS AND THEIR SIGNIFICANCE
BOD
TO
PD
0
1
u
u
u
0
u
u
1
1
0
0
1
1
u
0
Power-on Reset
Brown-out Detect
WDT Reset
WDT Wake-up
u
u
u
u
u
1
u
0
MCLR Reset during normal operation
MCLR Reset during Sleep
Legend: u = unchanged, x = unknown
TABLE 9-5: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Address Name
Value on all
other
Value on
POR, BOD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Resets(1)
03h
8Eh
STATUS
PCON
IRP
—
RP1
—
RPO
—
TO
—
PD
—
Z
DC
C
0001 1xxx 000q quuu
—
POR
BOD ---- --0x ---- --uq
Legend:u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’, q= value depends on condition.
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during
normal operation.
TABLE 9-6:
INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Condition
Power-on Reset
000h
000h
0001 1xxx
000u uuuu
---- --0x
---- --uu
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Reset
000h
000h
0001 0uuu
0000 uuuu
uuu0 0uuu
0001 1uuu
uuu1 0uuu
---- --uu
---- --uu
---- --uu
---- --10
---- --uu
WDT Wake-up
PC + 1
Brown-out Detect
000h
PC + 1(1)
Interrupt Wake-up from Sleep
Legend:u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and global enable bit GIE is set, the PC is loaded with the
interrupt vector (0004h) after execution of PC + 1.
DS41190G-page 60
2010 Microchip Technology Inc.
PIC12F629/675
TABLE 9-7:
Register
INITIALIZATION CONDITION FOR REGISTERS
• MCLR Reset during
• Wake-up from Sleep
through interrupt
• Wake-up from Sleep
through WDT Time-out
normal operation
Power-on
Reset
Address
• MCLR Reset during Sleep
• WDT Reset
• Brown-out Detect(1)
W
—
00h/80h
01h
xxxx xxxx
—
uuuu uuuu
—
uuuu uuuu
—
INDF
TMR0
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
--xx xxxx
---0 0000
0000 0000
00-- 0--0
-000 0000
-0-0 0000
xxxx xxxx
00-- 0000
1111 1111
--11 1111
00-- 0--0
---- --0x
1000 00--
--11 -111
--00 0000
0-0- 0000
0000 0000
-000 0000
---- x000
---- ----
xxxx xxxx
-000 1111
uuuu uuuu
0000 0000
000q quuu(4)
uuuu uuuu
--uu uuuu
---0 0000
0000 000u
00-- 0--0
-uuu uuuu
-0-0 0000
uuuu uuuu
00-- 0000
1111 1111
--11 1111
00-- 0--0
---- --uu(1,6)
1000 00--
--11 -111
--00 0000
0-0- 0000
0000 0000
-000 0000
---- q000
---- ----
uuuu uuuu
-000 1111
uuuu uuuu
PC + 1(3)
PCL
02h/82h
03h/83h
04h/84h
05h
STATUS
FSR
uuuq quuu(4)
uuuu uuuu
--uu uuuu
---u uuuu
uuuu uuqq(2)
qq-- q--q(2,5)
-uuu uuuu
-u-u uuuu
uuuu uuuu
uu-- uuuu
uuuu uuuu
--uu uuuu
uu-- u--u
---- --uu
uuuu uu--
uuuu uuuu
--uu uuuu
u-u- uuuu
uuuu uuuu
-uuu uuuu
---- uuuu
---- ----
uuuu uuuu
-uuu uuuu
GPIO
PCLATH
INTCON
PIR1
0Ah/8Ah
0Bh/8Bh
0Ch
T1CON
CMCON
ADRESH
ADCON0
OPTION_REG
TRISIO
PIE1
10h
19h
1Eh
1Fh
81h
85h
8Ch
PCON
8Eh
OSCCAL
WPU
90h
95h
IOC
96h
VRCON
EEDATA
EEADR
EECON1
EECON2
ADRESL
ANSEL
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’, q= value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
4: See Table 9-6 for Reset value for specific condition.
5: If wake-up was due to data EEPROM write completing, Bit 7 = 1; A/D conversion completing, Bit 6 = 1;
Comparator input changing, bit 3 = 1; or Timer1 rolling over, bit 0 = 1. All other interrupts generating a
wake-up will cause these bits to = u.
6: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
2010 Microchip Technology Inc.
DS41190G-page 61
PIC12F629/675
FIGURE 9-7:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
OST Time-out
Internal Reset
TOST
FIGURE 9-8:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
OST Time-out
Internal Reset
TOST
FIGURE 9-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
OST Time-out
Internal Reset
TOST
DS41190G-page 62
2010 Microchip Technology Inc.
PIC12F629/675
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
9.4
Interrupts
The PIC12F629/675 has 7 sources of interrupt:
• External Interrupt GP2/INT
• TMR0 Overflow Interrupt
• GPIO Change Interrupts
• Comparator Interrupt
Note 1: Individual interrupt flag bits are set,
regardless of the status of their
corresponding mask bit or the GIE bit.
• A/D Interrupt (PIC12F675 only)
• TMR1 Overflow Interrupt
• EEPROM Data Write Interrupt
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts which were
ignored are still pending to be serviced
when the GIE bit is set again.
The Interrupt Control register (INTCON) and Peripheral
Interrupt register (PIR) record individual interrupt
requests in flag bits. The INTCON register also has
individual and Global Interrupt Enable (GIE) bits.
A Global Interrupt Enable bit, GIE (INTCON<7>)
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register and PIE register. GIE is cleared on
Reset.
The return from interrupt instruction, RETFIE, exits
interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the
INTCON register:
• INT pin interrupt
• GP port change interrupt
• TMR0 overflow interrupt
The peripheral interrupt flags are contained in the
special register PIR1. The corresponding interrupt
enable bit is contained in special register PIE1.
The following interrupt flags are contained in the PIR
register:
• EEPROM data write interrupt
• A/D interrupt
• Comparator interrupt
• Timer1 overflow interrupt
When an interrupt is serviced:
• The GIE is cleared to disable any further interrupt
• The return address is pushed onto the stack
• The PC is loaded with 0004h
Once in the Interrupt Service Routine, the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in
software before re-enabling interrupts to avoid GP2/
INT recursive interrupts.
For external interrupt events, such as the INT pin, or
GP port change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 9-11). The latency is the same for one or two-
cycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
2010 Microchip Technology Inc.
DS41190G-page 63
PIC12F629/675
FIGURE 9-10:
INTERRUPT LOGIC
IOC-GP0
IOC0
IOC-GP1
IOC1
IOC-GP2
IOC2
IOC-GP3
IOC3
IOC-GP4
IOC4
IOC-GP5
IOC5
T0IF
T0IE
Wake-up (If in Sleep mode)
Interrupt to CPU
INTF
INTE
TMR1IF
TMR1IE
GPIF
GPIE
CMIF
CMIE
PEIE
GIE
(1)
ADIF
ADIE
EEIF
EEIE
Note 1: PIC12F675 only.
DS41190G-page 64
2010 Microchip Technology Inc.
PIC12F629/675
9.4.1
GP2/INT INTERRUPT
9.4.3
GPIO INTERRUPT
External interrupt on GP2/INT pin is edge-triggered;
either rising if INTEDG bit (OPTION<6>) is set, of
falling, if INTEDG bit is clear. When a valid edge
appears on the GP2/INT pin, the INTF bit (INT-
CON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The GP2/INT
interrupt can wake-up the processor from Sleep if the
INTE bit was set prior to going into Sleep. The status of
the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up. See
Section 9.7 “Power-Down Mode (Sleep)” for details
on Sleep and Figure 9-13 for timing of wake-up from
Sleep through GP2/INT interrupt.
An input change on GPIO change sets the GPIF
(INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the GPIE (INTCON<3>)
bit. Plus individual pins can be configured through the
IOC register.
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF
interrupt flag may not get set.
9.4.4
COMPARATOR INTERRUPT
See Section 6.9 “Comparator Interrupts” for
description of comparator interrupt.
9.4.5
A/D CONVERTER INTERRUPT
Note: The ANSEL (9Fh) and CMCON (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
The ANSEL register is defined for the
PIC12F675.
After a conversion is complete, the ADIF flag (PIR<6>)
is set. The interrupt can be enabled/disabled by setting
or clearing ADIE (PIE<6>).
See Section 7.0 “Analog-to-Digital Converter (A/D)
Module (PIC12F675 only)” for operation of the A/D
converter interrupt.
9.4.2
TMR0 INTERRUPT
An overflow (FFh 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be enabled/disabled by setting/clearing T0IE
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 4.0 “Timer0 Module”.
FIGURE 9-11:
INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT
3
4
INT pin
1
1
Interrupt Latency
INTF Flag
(INTCON<1>)
5
2
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC + 1
—
0004h
0005h
PC
PC + 1
Instruction
Fetched
Inst (PC+1)
Inst (0004h)
Inst (PC)
Inst (0005h)
Inst (0004h)
Instruction
Executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC - 1)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC Oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
2010 Microchip Technology Inc.
DS41190G-page 65
PIC12F629/675
TABLE 9-8:
SUMMARY OF INTERRUPT REGISTERS
Value on all
other
Resets
Value on
POR, BOD
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh INTCON
GIE
EEIF
EEIE
PEIE
ADIF
ADIE
T0IE
—
INTE
—
GPIE
CMIF
CMIE
T0IF
—
INTF
—
GPIF
0000 0000 0000 000u
0Ch
8Ch
PIR1
PIE1
TMR1IF 00-- 0--0 00-- 0--0
TMR1IE 00-- 0--0 00-- 0--0
—
—
—
—
Legend: x= unknown, u= unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the interrupt module.
9.5
Context Saving During Interrupts
9.6
Watchdog Timer (WDT)
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W register and
STATUS register). This must be implemented in
software.
The Watchdog Timer is a free running, on-chip RC
oscillator, which requires no external components. This
RC oscillator is separate from the external RC oscillator
of the CLKIN pin and INTOSC. That means that the
WDT will run, even if the clock on the OSC1 and OSC2
pins of the device has been stopped (for example, by
execution of a SLEEP instruction). During normal
operation, a WDT Time-out generates a device Reset.
If the device is in Sleep mode, a WDT Time-out causes
the device to wake-up and continue with normal
operation. The WDT can be permanently disabled by
programming the Configuration bit WDTE as clear
(Section 9.1 “Configuration Bits”).
Example 9-2 stores and restores the STATUS and W
registers. The user register, W_TEMP, must be defined
in both banks and must be defined at the same offset
from the bank base address (i.e., W_TEMP is defined
at 0x20 in Bank 0 and it must also be defined at 0xA0
in Bank 1). The user register, STATUS_TEMP, must be
defined in Bank 0. The Example 9-2:
• Stores the W register
9.6.1
WDT PERIOD
• Stores the STATUS register in Bank 0
• Executes the ISR code
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with
temperature, VDD and process variations from part to
part (see DC specs). If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT under software control by
writing to the OPTION register. Thus, time-out periods
up to 2.3 seconds can be realized.
• Restores the STATUS (and bank select bit
register)
• Restores the W register
EXAMPLE 9-2:
SAVING THE STATUS AND
W REGISTERS IN RAM
;copy W to temp register,
could be in either bank
;swap status to be saved into W
;change to bank 0 regardless of
current bank
MOVWF W_TEMP
The CLRWDTand SLEEPinstructions clear the WDT
and the prescaler, if assigned to the WDT, and prevent
it from timing out and generating a device Reset.
SWAPF STATUS,W
BCF
STATUS,RP0
MOVWF STATUS_TEMP ;save status to bank 0 register
:
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer Time-out.
:(ISR)
:
SWAPF STATUS_TEMP,W;swap STATUS_TEMP register into
W, sets bank to original state
;move W into STATUS register
;swap W_TEMP
9.6.2
WDT PROGRAMMING
CONSIDERATIONS
MOVWF STATUS
SWAPF W_TEMP,F
SWAPF W_TEMP,W
;swap W_TEMP into W
It should also be taken in account that under worst-
case conditions (i.e., VDD = Min., Temperature = Max.,
Max. WDT prescaler) it may take several seconds
before a WDT Time-out occurs.
DS41190G-page 66
2010 Microchip Technology Inc.
PIC12F629/675
FIGURE 9-12:
WATCHDOG TIMER BLOCK DIAGRAM
CLKOUT
(= FOSC/4)
Data Bus
0
8
1
0
SYNC 2
Cycles
1
TMR0
T0CKI
pin
0
Set Flag bit T0IF
on Overflow
T0CS
T0SE
8-bit
Prescaler
PSA
1
8
PSA
1
0
PS0 - PS2
WDT
Time-out
Watchdog
Timer
PSA
WDTE
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
TABLE 9-9:
SUMMARY OF WATCHDOG TIMER REGISTERS
Value on all
other
Resets
Value on
POR, BOD
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
81h
OPTION_REG GPPU INTEDG T0CS
Config. bits CP
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
2007h
BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0 uuuu uuuu uuuu uuuu
Legend: u= Unchanged, shaded cells are not used by the Watchdog Timer.
2010 Microchip Technology Inc.
DS41190G-page 67
PIC12F629/675
The first event will cause a device Reset. The two latter
events are considered a continuation of program exe-
cution. The TO and PD bits in the STATUS register can
be used to determine the cause of device Reset. The
PD bit, which is set on power-up, is cleared when Sleep
is invoked. TO bit is cleared if WDT Wake-up occurred.
9.7
Power-Down Mode (Sleep)
The Power-down mode is entered by executing a
SLEEPinstruction.
If the Watchdog Timer is enabled:
• WDT will be cleared but keeps running
• PD bit in the STATUS register is cleared
• TO bit is set
When the SLEEP instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the correspond-
ing interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEPinstruction, then branches to the interrupt
address (0004h). In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have an NOPafter the SLEEPinstruction.
• Oscillator driver is turned off
• I/O ports maintain the status they had before
Sleep was executed (driving high, low, or
high-impedance).
For lowest current consumption in this mode, all I/O
pins should be either at VDD, or VSS, with no external
circuitry drawing current from the I/O pin and the com-
parators and CVREF should be disabled. I/O pins that
are high-impedance inputs should be pulled high or low
externally to avoid switching currents caused by float-
ing inputs. The T0CKI input should also be at VDD or
VSS for lowest current consumption. The contribution
from on-chip pull-ups on GPIO should be considered.
Note: If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from Sleep. The
SLEEPinstruction is completely executed.
The MCLR pin must be at a logic high level (VIHMC).
Note: It should be noted that a Reset generated
by a WDT Time-out does not drive MCLR
pin low.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
9.7.1
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the
following events:
1. External Reset input on MCLR pin
2. Watchdog Timer Wake-up (if WDT was enabled)
3. Interrupt from GP2/INT pin, GPIO change, or a
peripheral interrupt.
FIGURE 9-13:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
(2)
TOST
INTF flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
Sleep
INSTRUCTION FLOW
PC
PC
PC + 1
PC + 2
PC + 2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = Sleep
Inst(PC - 1)
Fetched
Instruction
Executed
Dummy cycle
Dummy cycle
Sleep
Inst(PC + 1)
Inst(0004h)
Note 1: XT, HS or LP Oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale). Approximately 1 s delay will be there for RC Osc mode. See Section 12 for wake-up from
Sleep delay in INTOSC mode.
3: GIE = 1assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
4: CLKOUT is not available in XT, HS, LP or EC Osc modes, but shown here for timing reference.
DS41190G-page 68
2010 Microchip Technology Inc.
PIC12F629/675
FIGURE 9-14:
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
9.8
Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
To Normal
Note: The entire data EEPROM and Flash
program memory will be erased when the
code protection is turned off. The INTOSC
calibration data is also erased. See
PIC12F629/675 Programming Specifica-
tion for more information.
Connections
External
Connector
Signals
PIC12F629/675
+5V
0V
VDD
VSS
VPP
GP3/MCLR/VPP
9.9
ID Locations
GP1
GP0
CLK
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during Program/Verify. Only the
Least Significant 7 bits of the ID locations are used.
Data I/O
VDD
To Normal
Connections
9.10 In-Circuit Serial Programming
The PIC12F629/675 microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for:
9.11 In-Circuit Debugger
Since in-circuit debugging requires the loss of clock,
data and MCLR pins, MPLAB® ICD 2 development with
an 8-pin device is not practical. A special 14-pin
PIC12F675-ICD device is used with MPLAB ICD 2 to
provide separate clock, data and MCLR pins and frees
all normally available pins to the user.
• power
• ground
• programming voltage
This allows customers to manufacture boards with
unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
This special ICD device is mounted on the top of the
header and its signals are routed to the MPLAB ICD 2
connector. On the bottom of the header is an 8-pin
socket that plugs into the user’s target via the 8-pin
stand-off connector.
The device is placed into a Program/Verify mode by
holding the GP0 and GP1 pins low, while raising the
MCLR (VPP) pin from VIL to VIHH (see Programming
Specification). GP0 becomes the programming data
and GP1 becomes the programming clock. Both GP0
and GP1 are Schmitt Trigger inputs in this mode.
When the ICD pin on the PIC12F675-ICD device is
held low, the In-Circuit Debugger functionality is
enabled. This function allows simple debugging
functions when used with MPLAB ICD 2. When the
microcontroller has this feature enabled, some of the
resources are not available for general use. Table 9-10
shows which features are consumed by the
background debugger:
After Reset, to place the device into Programming/
Verify mode, the PC is at location 00h. A 6-bit
command is then supplied to the device. Depending on
the command, 14-bits of program data are then
supplied to or from the device, depending on whether
the command was a load or a read. For complete
details of serial programming, please refer to the
Programming Specifications.
TABLE 9-10: DEBUGGER RESOURCES
I/O pins
Stack
ICDCLK, ICDDATA
1 level
Program Memory
Address 0h must be NOP
A typical In-Circuit Serial Programming connection is
shown in Figure 9-14.
300h-3FEh
For more information, see 8-Pin MPLAB ICD 2 Header
Information Sheet (DS51292) available on Microchip’s
web site (www.microchip.com).
2010 Microchip Technology Inc.
DS41190G-page 69
PIC12F629/675
NOTES:
DS41190G-page 70
2010 Microchip Technology Inc.
PIC12F629/675
For example, a CLRF GPIOinstruction will read GPIO,
clear all the data bits, then write the result back to
GPIO. This example would have the unintended result
that the condition that sets the GPIF flag would be
cleared.
10.0 INSTRUCTION SET SUMMARY
The PIC12F629/675 instruction set is highly orthogonal
and is comprised of three basic categories:
• Byte-oriented operations
• Bit-oriented operations
TABLE 10-1: OPCODE FIELD
DESCRIPTIONS
• Literal and control operations
Each PIC12F629/675 instruction is a 14-bit word
divided into an opcode, which specifies the instruction
type, and one or more operands, which further specify
the operation of the instruction. The formats for each of
the categories is presented in Figure 10-1, while the
various opcode fields are summarized in Table 10-1.
Field
Description
f
Register file address (0x00 to 0x7F)
Working register (accumulator)
W
b
k
Bit address within an 8-bit file register
Literal field, constant data or label
Table 10-2 lists the instructions recognized by the
MPASMTM assembler. A complete description of
each instruction is also available in the PIC® Mid-
Range Reference Manual (DS33023).
x
Don’t care location (= 0or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC
TO
PD
Program Counter
Time-out bit
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
Power-down bit
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the
operation, while ‘f’ represents the address of the file in
which the bit is located.
FIGURE 10-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8
7
6
0
For literal and control operations, ‘k’ represents an 8-
bit or 11-bit constant, or literal value.
OPCODE
d
f (FILE #)
d = 0for destination W
d = 1for destination f
One instruction cycle consists of four oscillator periods;
for an oscillator frequency of 4 MHz, this gives a normal
instruction execution time of 1 s. All instructions are
executed within a single instruction cycle, unless a
conditional test is true, or the program counter is
changed as a result of an instruction. When this occurs,
the execution takes two instruction cycles, with the
second cycle executed as a NOP.
f = 7-bit file register address
Bit-oriented file register operations
13 10 9
b (BIT #)
7
6
0
OPCODE
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Note: To maintain upward compatibility with
future products, do not use the OPTION
and TRISIOinstructions.
Literal and control operations
General
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
13
8
7
0
0
OPCODE
k (literal)
k = 8-bit immediate value
10.1 Read-Modify-Write Operations
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
k (literal)
2010 Microchip Technology Inc.
DS41190G-page 71
PIC12F629/675
TABLE 10-2: PIC12F629/675 INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Description
Operands
Status
Affected
Cycles
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00 0111 dfff ffff C,DC,Z
1,2
1,2
2
00 0101 dfff ffff
00 0001 lfff ffff
00 0001 0xxx xxxx
00 1001 dfff ffff
00 0011 dfff ffff
00 1011 dfff ffff
00 1010 dfff ffff
00 1111 dfff ffff
00 0100 dfff ffff
00 1000 dfff ffff
00 0000 lfff ffff
00 0000 0xx0 0000
00 1101 dfff ffff
00 1100 dfff ffff
Z
Z
Z
Z
Z
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
DECFSZ
INCF
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
Move W to f
No Operation
-
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
00 0010 dfff ffff C,DC,Z
00 1110 dfff ffff
00 0110 dfff ffff
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01 00bb bfff ffff
1,2
1,2
3
01 01bb bfff ffff
01 10bb bfff ffff
01 11bb bfff ffff
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11 111x kkkk kkkk C,DC,Z
11 1001 kkkk kkkk
10 0kkk kkkk kkkk
00 0000 0110 0100
10 1kkk kkkk kkkk
11 1000 kkkk kkkk
11 00xx kkkk kkkk
00 0000 0000 1001
11 01xx kkkk kkkk
00 0000 0000 1000
00 0000 0110 0011
Z
TO,PD
Z
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
TO,PD
11 110x kkkk kkkk C,DC,Z
11 1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PIC® Mid-Range MCU Family Ref-
erence Manual (DS33023).
DS41190G-page 72
2010 Microchip Technology Inc.
PIC12F629/675
10.2 Instruction Descriptions
ADDLW
Add Literal and W
BCF
Bit Clear f
Syntax:
[label] ADDLW
0 k 255
k
Syntax:
[label] BCF f,b
Operands:
Operation:
Status Affected:
Description:
Operands:
0 f 127
0 b 7
(W) + k (W)
C, DC, Z
Operation:
0 (f<b>)
Status Affected:
Description:
None
The contents of the W register
are added to the eight-bit literal ‘k’
and the result is placed in the W
register.
Bit ‘b’ in register ‘f’ is cleared.
BSF
Bit Set f
ADDWF
Add W and f
Syntax:
[label] BSF f,b
Syntax:
[label] ADDWF f,d
Operands:
0 f 127
0 b 7
Operands:
0 f 127
d
Operation:
1 (f<b>)
Operation:
(W) + (f) (destination)
Status Affected:
Description:
None
Status Affected: C, DC, Z
Bit ‘b’ in register ‘f’ is set.
Description:
Add the contents of the W register
with register ‘f’. If ‘d’ is 0, the
result is stored in the W register. If
‘d’ is 1, the result is stored back in
register ‘f’.
BTFSS
Bit Test f, Skip if Set
ANDLW
AND Literal with W
Syntax:
[label] BTFSS f,b
Syntax:
[label] ANDLW
0 k 255
k
Operands:
0 f 127
0 b < 7
Operands:
Operation:
Status Affected:
Description:
(W) .AND. (k) (W)
Operation:
skip if (f<b>) = 1
Z
Status Affected: None
The contents of W register are
AND’ed with the eight-bit literal
‘k’. The result is placed in the W
register.
Description: If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next
instruction is discarded and a NOP
is executed instead, making this a
2TCY instruction.
ANDWF
AND W with f
Syntax:
[label] ANDWF f,d
Operands:
0 f 127
d
Operation:
(W) .AND. (f) (destination)
Status Affected:
Description:
Z
AND the W register with register
‘f’. If ‘d’ is 0, the result is stored in
the W register. If ‘d’ is 1, the result
is stored back in register ‘f’.
2010 Microchip Technology Inc.
DS41190G-page 73
PIC12F629/675
BTFSC
Bit Test, Skip if Clear
CLRWDT
Clear Watchdog Timer
Syntax:
[label] BTFSC f,b
Syntax:
[ label ] CLRWDT
Operands:
0 f 127
0 b 7
Operands:
Operation:
None
00h WDT
0 WDT prescaler,
1 TO
Operation:
skip if (f<b>) = 0
Status Affected: None
1 PD
Description:
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
Status Affected: TO, PD
If bit ‘b’, in register ‘f’, is ‘0’, the
next instruction is discarded, and
a NOPis executed instead, making
this a 2TCY instruction.
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT.
Status bits TO and PD are set.
CALL
Call Subroutine
COMF
Complement f
Syntax:
[ label ] CALL k
0 k 2047
Syntax:
[ label ] COMF f,d
Operands:
Operation:
Operands:
0 f 127
d [0,1]
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Operation:
(f) (destination)
Status Affected:
Description:
Z
Status Affected: None
The contents of register ‘f’ are
complemented. If ‘d’ is 0, the
result is stored in W. If ‘d’ is 1, the
result is stored back in register ‘f’.
Description:
Call Subroutine. First, return
address (PC + 1) is pushed onto
the stack. The eleven-bit immedi-
ate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALLis
a two-cycle instruction.
DECF
Decrement f
CLRF
Clear f
Syntax:
[label] DECF f,d
Syntax:
[label] CLRF
0 f 127
f
Operands:
0 f 127
d [0,1]
Operands:
Operation:
00h (f)
1 Z
Operation:
(f) - 1 (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Decrement register ‘f’. If ‘d’ is 0,
the result is stored in the W
register. If ‘d’ is 1, the result is
stored back in register ‘f’.
The contents of register ‘f’ are
cleared and the Z bit is set.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
Operation:
None
00h (W)
1 Z
Status Affected:
Description:
Z
W register is cleared. Zero bit (Z)
is set.
DS41190G-page 74
2010 Microchip Technology Inc.
PIC12F629/675
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ] INCFSZ f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
Operation:
(f) + 1 (destination),
skip if result = 0
skip if result = 0
Status Affected: None
Status Affected: None
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is 0, the result
is placed in the W register. If ‘d’ is
1, the result is placed back in
register ‘f’.
incremented. If ‘d’ is 0, the result
is placed in the W register. If ‘d’ is
1, the result is placed back in
register ‘f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
then a NOPis executed instead,
making it a 2TCY instruction.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
a NOPis executed instead, making
it a 2TCY instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR Literal with W
Syntax:
[ label ] GOTO k
0 k 2047
Syntax:
[ label ] IORLW k
0 k 255
Operands:
Operation:
Operands:
Operation:
Status Affected:
Description:
k PC<10:0>
PCLATH<4:3> PC<12:11>
(W) .OR. k (W)
Z
Status Affected: None
The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
Description:
GOTOis an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTOis a two-
cycle instruction.
IORWF
Inclusive OR W with f
INCF
Increment f
Syntax:
[ label ] IORWF f,d
Syntax:
[ label ] INCF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(W) .OR. (f) (destination)
Operation:
(f) + 1 (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Inclusive OR the W register with
register ‘f’. If ‘d’ is 0, the result is
placed in the W register. If ‘d’ is 1,
the result is placed back in
register ‘f’.
The contents of register ‘f’ are
incremented. If ‘d’ is 0, the result
is placed in the W register. If ‘d’ is
1, the result is placed back in
register ‘f’.
2010 Microchip Technology Inc.
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PIC12F629/675
MOVWF
Move W to f
[ label ] MOVWF
0 f 127
(W) (f)
MOVF
Move f
Syntax:
f
Syntax:
Operands:
[ label ] MOVF f,d
Operands:
Operation:
Status Affected:
Description:
0 f 127
d [0,1]
Operation:
(f) (dest)
None
Status Affected:
Description:
Z
Move data from W register to
register ‘f’.
The contents of register f is
moved to a destination dependent
upon the status of d. If d = 0,
the destination is W register. If d =
1, the destination is file register f
itself. d = 1is useful to test a file
register since status flag Z is
affected.
Words:
1
Cycles:
Example:
1
MOVWF OPTION
Before Instruction
OPTION = 0xFF
W
=
0x4F
Words:
1
1
After Instruction
OPTION = 0x4F
W
Cycles:
Example:
=
0x4F
MOVF
FSR, 0
After Instruction
W
=
value in FSR
register
Z
=
1
NOP
No Operation
MOVLW
Syntax:
Move literal to W
Syntax:
[ label ] NOP
[ label ] MOVLW k
0 k 255
Operands:
Operation:
Status Affected:
Description:
Words:
None
Operands:
Operation:
No operation
k (W)
None
Status Affected: None
No operation.
Description:
The eight-bit literal ‘k’ is loaded into
W register. The “don’t cares” will
assemble as ‘0’s.
1
Cycles:
1
NOP
Example:
Words:
1
1
Cycles:
Example:
MOVLW
0x5A
After Instruction
W
=
0x5A
DS41190G-page 76
2010 Microchip Technology Inc.
PIC12F629/675
RETFIE
Return from Interrupt
[ label ] RETFIE
None
RETLW
Return with literal in W
[ label ] RETLW k
0 k 255
Syntax:
Syntax:
Operands:
Operation:
Operands:
Operation:
TOS PC,
1 GIE
k (W);
TOS PC
Status Affected:
Description:
None
Status Affected:
Description:
None
Return from Interrupt. Stack is
POPed and Top-of-Stack (TOS) is
loaded in the PC. Interrupts are
enabled by setting Global
Interrupt Enable bit, GIE
The W register is loaded with the
eight-bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
(INTCON<7>). This is a two-cycle
instruction.
Words:
1
2
Cycles:
Example:
Words:
1
CALL TABLE;W contains
table
Cycles:
Example:
2
;offset value
RETFIE
•
•
•
;W now has table value
TABLE
After Interrupt
PC = TOS
GIE =
1
ADDWF PCL;W = offset
RETLW k1 ;Begin table
RETLW k2
;
•
•
•
RETLW kn ; End of table
Before Instruction
W
=
0x07
After Instruction
W
=
value of k8
RETURN
Return from Subroutine
Syntax:
[ label ] RETURN
None
Operands:
Operation:
TOS PC
Status Affected: None
Description: Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
2010 Microchip Technology Inc.
DS41190G-page 77
PIC12F629/675
SUBLW
Subtract W from Literal
RLF
Rotate Left f through Carry
Syntax:
[ label ] SUBLW k
0 k 255
Syntax:
[ label ] RLF f,d
Operands:
Operation:
Operands:
0 f 127
d [0,1]
k - (W) W)
Status Affected: C, DC, Z
Operation:
See description below
C
Description:
The W register is subtracted (2’s
Status Affected:
Description:
complement method) from the
eight-bit literal ‘k’. The result is
placed in the W register.
The contents of register ‘f’ are rotated
one bit to the left through the Carry
Flag. If ‘d’ is 0, the result is placed in
the W register. If ‘d’ is 1, the result is
stored back in register ‘f’.
C
Register f
SUBWF
Subtract W from f
Syntax:
[ label ] SUBWF f,d
Operands:
0 f 127
d [0,1]
RRF
Rotate Right f through Carry
Syntax:
[ label ] RRF f,d
Operation:
(f) - (W) destination)
Operands:
0 f 127
d [0,1]
Status
Affected:
C, DC, Z
Operation:
See description below
C
Description:
Subtract (2’s complement method)
W register from register ‘f’. If ‘d’ is
0, the result is stored in the W
register. If ‘d’ is 1, the result is
stored back in register ‘f’.
Status Affected:
Description:
The contents of register ‘f’ are
rotated one bit to the right through
the Carry Flag. If ‘d’ is 0, the result
is placed in the W register. If ‘d’ is
1, the result is placed back in
register ‘f’.
SWAPF
Swap Nibbles in f
C
Register f
Syntax:
[ label ] SWAPF f,d
Operands:
0 f 127
d [0,1]
Operation:
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
SLEEP
Syntax:
[ label ] SLEEP
None
Status Affected: None
Operands:
Operation:
Description: The upper and lower nibbles of
00h WDT,
0 WDT prescaler,
1 TO,
register ‘f’ are exchanged. If ‘d’ is
0, the result is placed in the W
register. If ‘d’ is 1, the result is
placed in register ‘f’.
0 PD
Status Affected:
Description:
TO, PD
The power-down Status bit, PD is
cleared. Time-out Status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
The processor is put into Sleep
mode with the oscillator stopped.
DS41190G-page 78
2010 Microchip Technology Inc.
PIC12F629/675
XORLW
Exclusive OR Literal with W
XORWF
Exclusive OR W with f
Syntax:
[label] XORLW k
0 k 255
Syntax:
[label] XORWF f,d
Operands:
Operation:
Status Affected:
Description:
Operands:
0 f 127
d [0,1]
(W) .XOR. k W)
Z
Operation:
(W) .XOR. (f) destination)
Status Affected:
Description:
Z
The contents of the W register
are XOR’ed with the eight-bit
literal ‘k’. The result is placed in
the W register.
Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
0, the result is stored in the W
register. If ‘d’ is 1, the result is
stored back in register ‘f’.
2010 Microchip Technology Inc.
DS41190G-page 79
PIC12F629/675
NOTES:
DS41190G-page 80
2010 Microchip Technology Inc.
PIC12F629/675
11.1 MPLAB Integrated Development
Environment Software
11.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• A single graphical interface to all debugging tools
- Simulator
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- HI-TECH C for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Customizable data windows with direct edit of
contents
• Simulators
• High-level source code debugging
• Mouse over variable inspection
- MPLAB SIM Software Simulator
• Emulators
• Drag and drop variables from source to watch
windows
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
2010 Microchip Technology Inc.
DS41190G-page 81
PIC12F629/675
11.2 MPLAB C Compilers for Various
Device Families
11.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
11.3 HI-TECH C for Various Device
Families
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
11.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple
platforms.
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
11.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• MPLAB IDE compatibility
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
DS41190G-page 82
2010 Microchip Technology Inc.
PIC12F629/675
11.7 MPLAB SIM Software Simulator
11.9 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip’s most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcon-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a high-
speed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
11.10 PICkit 3 In-Circuit Debugger/
Programmer and
11.8 MPLAB REAL ICE In-Circuit
Emulator System
PICkit 3 Debug Express
The MPLAB PICkit
programming of
3
allows debugging and
and Flash
dsPIC®
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
PIC®
microcontrollers at a most affordable price point using
the powerful graphical user interface of the MPLAB
Integrated Development Environment (IDE). The
MPLAB PICkit 3 is connected to the design engineer’s
PC using a full speed USB interface and can be
connected to the target via an Microchip debug (RJ-11)
connector (compatible with MPLAB ICD 3 and MPLAB
REAL ICE). The connector uses two device I/O pins
and the reset line to implement in-circuit debugging and
In-Circuit Serial Programming™.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers signifi-
cant advantages over competitive emulators including
low-cost, full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, a rugge-
dized probe interface and long (up to three meters) inter-
connection cables.
2010 Microchip Technology Inc.
DS41190G-page 83
PIC12F629/675
11.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
11.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
Development Environment (IDE) the PICkit™
2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
11.12 MPLAB PM3 Device Programmer
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS41190G-page 84
2010 Microchip Technology Inc.
PIC12F629/675
12.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings†
Ambient temperature under bias........................................................................................................... -40 to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on VDD with respect to VSS ..................................................................................................... -0.3 to +6.5V
Voltage on MCLR with respect to Vss ..................................................................................................-0.3 to +13.5V
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ...............................................................................................................................800 mW
Maximum current out of VSS pin ..................................................................................................................... 300 mA
Maximum current into VDD pin ........................................................................................................................ 250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)20 mA
Output clamp current, IOK (Vo < 0 or Vo >VDD)20 mA
Maximum output current sunk by any I/O pin....................................................................................................25 mA
Maximum output current sourced by any I/O pin .............................................................................................. 25 mA
Maximum current sunk by all GPIO ................................................................................................................ 125 mA
Maximum current sourced all GPIO................................................................................................................ 125 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL).
† NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin, rather than
pulling this pin directly to VSS.
2010 Microchip Technology Inc.
DS41190G-page 85
PIC12F629/675
FIGURE 12-1:
PIC12F629/675 WITH A/D DISABLED VOLTAGE-FREQUENCY GRAPH,
-40°C TA +125°C
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
VDD
(Volts)
0
4
8
10
12
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 12-2:
PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH,
-40°C TA +125°C
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
VDD
(Volts)
0
4
8
10
12
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
DS41190G-page 86
2010 Microchip Technology Inc.
PIC12F629/675
FIGURE 12-3:
PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH,
0°C TA +125°C
5.5
5.0
4.5
4.0
3.5
3.0
VDD
(Volts)
2.5
2.2
2.0
0
4
8
10
12
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2010 Microchip Technology Inc.
DS41190G-page 87
PIC12F629/675
12.1 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Sym
Characteristic
Min Typ† Max Units
Conditions
VDD
Supply Voltage
FOSC < = 4 MHz:
D001
2.0
2.2
2.5
3.0
4.5
—
—
—
—
—
5.5
5.5
5.5
5.5
5.5
V
V
V
V
V
PIC12F629/675 with A/D off
D001A
D001B
D001C
D001D
PIC12F675 with A/D on, 0°C to +125°C
PIC12F675 with A/D on, -40°C to +125°C
4 MHZ < FOSC < = 10 MHz
D002
VDR
RAM Data Retention
Voltage(1)
1.5*
—
—
V
Device in Sleep mode
D003
VPOR
VDD Start Voltage to
ensure internal Power-on
Reset signal
—
VSS
—
V
See section on Power-on Reset for details
D004
D005
SVDD
VDD Rise Rate to ensure 0.05*
internal Power-on Reset
signal
—
—
—
V/ms See section on Power-on Reset for details
VBOD
—
2.1
V
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
DS41190G-page 88
2010 Microchip Technology Inc.
PIC12F629/675
12.2 DC Characteristics: PIC12F629/675-I (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40C TA +85C for industrial
Conditions
Note
Param
No.
Device Characteristics
Supply Current (IDD)
Min Typ† Max Units
VDD
D010
D011
D012
D013
D014
D015
D016
D017
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9
16
28
A
A
A
A
A
A
A
A
mA
A
A
A
A
A
A
A
A
mA
A
A
A
mA
mA
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
4.5
5.0
FOSC = 32 kHz
LP Oscillator Mode
18
35
54
110
190
330
220
370
0.6
70
150
280
450
280
650
1.4
FOSC = 1 MHz
XT Oscillator Mode
FOSC = 4 MHz
XT Oscillator Mode
110
250
390
250
470
850
450
700
1.1
FOSC = 1 MHz
EC Oscillator Mode
140
260
180
320
580
340
500
0.8
180
320
580
2.1
2.4
FOSC = 4 MHz
EC Oscillator Mode
FOSC = 4 MHz
INTOSC Mode
250
450
800
2.95
3.0
FOSC = 4 MHz
EXTRC Mode
FOSC = 20 MHz
HS Oscillator Mode
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have
an impact on the current consumption.
2010 Microchip Technology Inc.
DS41190G-page 89
PIC12F629/675
12.3 DC Characteristics: PIC12F629/675-I (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40C TA +85C for industrial
Conditions
Param
No.
Device Characteristics
Min
Typ†
Max Units
VDD
Note
D020
Power-down Base Current
(IPD)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.99
1.2
2.9
0.3
1.8
8.4
58
700
770
995
1.5
3.5
17
nA
nA
nA
A
A
A
A
A
A
A
A
A
A
A
A
A
A
nA
A
2.0
3.0
5.0
2.0
3.0
5.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
3.0
5.0
WDT, BOD, Comparators, VREF,
and T1OSC disabled
D021
WDT Current(1)
D022
D023
70
BOD Current(1)
109
3.3
6.1
11.5
58
130
6.5
8.5
16
Comparator Current(1)
D024
D025
D026
70
CVREF Current(1)
T1 OSC Current(1)
A/D Current(1)
85
100
160
6.5
7.0
10.5
775
138
4.0
4.6
6.0
1.2
0.0022 1.0
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
DS41190G-page 90
2010 Microchip Technology Inc.
PIC12F629/675
12.4 DC Characteristics: PIC12F629/675-E (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40C TA +125C for extended
Conditions
Note
Param
No.
Device Characteristics
Supply Current (IDD)
Min Typ† Max Units
VDD
D010E
D011E
D012E
D013E
D014E
D015E
D016E
D017E
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9
16
28
A
A
A
A
A
A
A
A
mA
A
A
A
A
A
A
A
A
mA
A
A
A
mA
mA
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
4.5
5.0
FOSC = 32 kHz
LP Oscillator Mode
18
35
54
110
190
330
220
370
0.6
70
150
280
450
280
650
1.4
FOSC = 1 MHz
XT Oscillator Mode
FOSC = 4 MHz
XT Oscillator Mode
110
250
390
250
470
850
450
780
1.1
FOSC = 1 MHz
EC Oscillator Mode
140
260
180
320
580
340
500
0.8
180
320
580
2.1
2.4
FOSC = 4 MHz
EC Oscillator Mode
FOSC = 4 MHz
INTOSC Mode
250
450
800
2.95
3.0
FOSC = 4 MHz
EXTRC Mode
FOSC = 20 MHz
HS Oscillator Mode
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have
an impact on the current consumption.
2010 Microchip Technology Inc.
DS41190G-page 91
PIC12F629/675
12.5 DC Characteristics: PIC12F629/675-E (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40C TA +125C for extended
Conditions
Param
No.
Device Characteristics
Min
Typ†
Max Units
VDD
Note
D020E Power-down Base Current
(IPD)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.00099 3.5
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
2.0
3.0
5.0
2.0
3.0
5.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
3.0
5.0
WDT, BOD, Comparators, VREF,
and T1OSC disabled
0.0012
0.0029
0.3
4.0
8.0
6.0
9.0
20
D021E
WDT Current(1)
1.8
8.4
D022E
D023E
58
70
BOD Current(1)
109
3.3
130
10
Comparator Current(1)
6.1
13
11.5
58
24
D024E
D025E
D026E
70
CVREF Current(1)
T1 OSC Current(1)
A/D Current(1)
85
100
165
10
138
4.0
4.6
12
6.0
20
0.0012
0.0022
6.0
8.5
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
DS41190G-page 92
2010 Microchip Technology Inc.
PIC12F629/675
12.6 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
Input Low Voltage
I/O ports
VIL
—
—
—
—
—
—
D030
D030A
D031
D032
D033
D033A
with TTL buffer
VSS
VSS
VSS
VSS
VSS
VSS
0.8
V
V
V
V
V
V
4.5V VDD 5.5V
Otherwise
0.15 VDD
0.2 VDD
0.2 VDD
0.3
with Schmitt Trigger buffer
MCLR, OSC1 (RC mode)
OSC1 (XT and LP modes)
OSC1 (HS mode)
Entire range
(Note 1)
(Note 1)
0.3 VDD
Input High Voltage
I/O ports
—
VIH
—
—
D040
D040A
with TTL buffer
2.0
VDD
VDD
V
V
4.5V VDD 5.5V
otherwise
(0.25 VDD+0.8)
—
—
D041
with Schmitt Trigger buffer
MCLR
0.8 VDD
0.8 VDD
1.6
VDD
VDD
VDD
VDD
VDD
400*
entire range
D042
V
V
V
V
—
D043
OSC1 (XT and LP modes)
OSC1 (HS mode)
OSC1 (RC mode)
(Note 1)
(Note 1)
—
D043A
D043B
0.7 VDD
0.9 VDD
50*
—
D070 IPUR GPIO Weak Pull-up Current
250
A VDD = 5.0V, VPIN = VSS
Input Leakage Current(3)
—
D060
IIL
I/O ports
01
1
A VSS VPIN VDD,
Pin at high-impedance
—
—
—
—
D060A
D060B
D061
Analog inputs
VREF
01
01
01
01
1
1
5
5
A VSS VPIN VDD
A VSS VPIN VDD
A VSS VPIN VDD
MCLR(2)
D063
OSC1
A VSS VPIN VDD, XT, HS and
LP osc configuration
Output Low Voltage
—
—
—
—
D080 VOL I/O ports
D083 OSC2/CLKOUT (RC mode)
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 4.5V (Ind.)
IOL = 1.6 mA, VDD = 4.5V (Ind.)
IOL = 1.2 mA, VDD = 4.5V (Ext.)
Output High Voltage
D090 VOH I/O ports
D092 OSC2/CLKOUT (RC mode)
—
—
—
—
VDD - 0.7
VDD - 0.7
V
V
IOH = -3.0 mA, VDD = 4.5V (Ind.)
IOH = -1.3 mA, VDD = 4.5V (Ind.)
IOH = -1.0 mA, VDD = 4.5V (Ext.)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use
an external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
2010 Microchip Technology Inc.
DS41190G-page 93
PIC12F629/675
12.7 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) (Cont.)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
Sym
No.
Characteristic
Min
Typ†
Max Units
Conditions
Capacitive Loading Specs
on Output Pins
D100
D101
COSC2 OSC2 pin
—
—
—
—
15*
50*
pF In XT, HS and LP modes when
external clock is used to drive
OSC1
CIO
All I/O pins
pF
Data EEPROM Memory
Byte Endurance
Byte Endurance
D120
D120A
D121
ED
ED
100K
10K
1M
100K
—
—
—
E/W -40C TA +85°C
E/W +85°C TA +125°C
VDRW VDD for Read/Write
VMIN
5.5
V
Using EECON to read/write
VMIN = Minimum operating
voltage
D122
D123
TDEW Erase/Write cycle time
TRETD Characteristic Retention
—
5
6
ms
40
—
—
Year Provided no other specifications
are violated
D124
TREF
Number of Total Erase/Write
Cycles before Refresh(1)
1M
10M
—
E/W -40C TA +85°C
Program Flash Memory
Cell Endurance
D130
D130A
D131
EP
10K
1K
100K
10K
—
—
—
E/W -40C TA +85°C
E/W +85°C TA +125°C
ED
Cell Endurance
VPR
VDD for Read
VMIN
5.5
V
VMIN = Minimum operating
voltage
D132
D133
D134
VPEW VDD for Erase/Write
TPEW Erase/Write cycle time
TRETD Characteristic Retention
4.5
—
—
2
5.5
2.5
—
V
ms
40
—
Year Provided no other specifications
are violated
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: See Section 8.5.1 “Using the Data EEPROM” for additional information.
DS41190G-page 94
2010 Microchip Technology Inc.
PIC12F629/675
12.8 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
T
Time
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (High-Impedance)
Low
Valid
L
High-Impedance
FIGURE 12-4:
LOAD CONDITIONS
Load Condition 1
Load Condition 2
VDD/2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464
CL = 50 pF for all pins
15 pF for OSC2 output
2010 Microchip Technology Inc.
DS41190G-page 95
PIC12F629/675
12.9 AC CHARACTERISTICS: PIC12F629/675 (INDUSTRIAL, EXTENDED)
FIGURE 12-5:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
4
Q1
OSC1
1
3
4
3
2
CLKOUT
TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
Sym
Characteristic
Min Typ†
Max
Units
Conditions
No.
FOSC External CLKIN Frequency(1) DC
—
—
—
—
—
4
37
4
kHz LP Osc mode
MHz XT mode
DC
DC
DC
20
20
37
—
4
MHz HS mode
MHz EC mode
Oscillator Frequency(1)
5
kHz LP Osc mode
MHz INTOSC mode
MHz RC Osc mode
MHz XT Osc mode
MHz HS Osc mode
—
DC
0.1
1
—
—
—
4
20
1
TOSC
External CLKIN Period(1)
Oscillator Period(1)
27
50
—
—
—
—
200
—
s LP Osc mode
ns HS Osc mode
ns EC Osc mode
ns XT Osc mode
s LP Osc mode
ns INTOSC mode
ns RC Osc mode
ns XT Osc mode
ns HS Osc mode
50
250
27
—
250
—
250
250
50
—
—
10,000
1,000
—
Instruction Cycle Time(1)
200
TCY
—
DC
—
ns TCY = 4/FOSC
2
3
TCY
TosL, External CLKIN (OSC1) High 2*
s LP oscillator, TOSC L/H duty cycle
TosH External CLKIN Low
20*
—
—
ns HS oscillator, TOSC L/H duty
cycle
100 *
—
—
—
—
—
—
ns XT oscillator, TOSC L/H duty cycle
ns LP oscillator
4
TosR, External CLKIN Rise
TosF External CLKIN Fall
50*
25*
15*
—
ns XT oscillator
—
ns HS oscillator
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to OSC1 pin. When an external clock input is used, the ‘max’ cycle time limit is “DC” (no clock)
for all devices.
DS41190G-page 96
2010 Microchip Technology Inc.
PIC12F629/675
TABLE 12-2:
Param
PRECISION INTERNAL OSCILLATOR PARAMETERS
Freq.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
No.
Tolerance
1
2
3.96
3.92
4.00
4.00
4.04
4.08
MHz VDD = 3.5V, 25C
MHz 2.5V VDD 5.5V
0C TA +85C
FOSC
F10
Internal Calibrated
INTOSC Frequency
5
3.80
4.00
4.20
MHz 2.0V VDD 5.5V
-40C TA +85C (IND)
-40C TA +125C (EXT)
s VDD = 2.0V, -40C to +85C
s VDD = 3.0V, -40C to +85C
s VDD = 5.0V, -40C to +85C
—
—
—
—
—
—
6
4
3
8
6
5
TIOSCST
F14
Oscillator Wake-up from
Sleep start-up time*
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
2010 Microchip Technology Inc.
DS41190G-page 97
PIC12F629/675
FIGURE 12-6:
CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
22
23
CLKOUT
13
12
19
18
14
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS
Param
Sym
Characteristic
Min
Typ†
Max
Units Conditions
No.
10
11
12
13
14
15
TosH2ckL OSC1 to CLOUT
TosH2ckH OSC1 to CLOUT
—
—
—
—
—
75
75
35
35
—
—
200
200
100
100
20
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
TckR
TckF
CLKOUT rise time
CLKOUT fall time
TckL2ioV CLKOUT to Port out valid
TioV2ckH Port in valid before CLKOUT
TOSC + 200
ns
—
16
17
TckH2ioI
Port in hold after CLKOUT
0
—
—
50
—
—
—
150 *
300
—
ns
ns
ns
ns
(Note 1)
TosH2ioV OSC1 (Q1 cycle) to Port out valid
—
18
19
TosH2ioI OSC1 (Q2 cycle) to Port input
100
invalid (I/O in hold time)
TioV2osH Port input valid to OSC1
0
—
—
ns
(I/O in setup time)
20
21
22
23
TioR
TioF
Tinp
Trbp
Port output rise time
—
—
10
10
—
—
40
40
—
—
ns
ns
ns
ns
Port output fall time
INT pin high or low time
GPIO change INT high or low time
25
TCY
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4xTOSC.
DS41190G-page 98
2010 Microchip Technology Inc.
PIC12F629/675
FIGURE 12-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O Pins
FIGURE 12-8:
BROWN-OUT DETECT TIMING AND CHARACTERISTICS
VDD
BVDD
(Device not in Brown-out Detect)
(Device in Brown-out Detect)
35
Reset (due to BOD)
(1)
72 ms time-out
Note 1: 72 ms delay only if PWRTE bit in Configuration Word is programmed to ‘0’.
2010 Microchip Technology Inc.
DS41190G-page 99
PIC12F629/675
TABLE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT DETECT REQUIREMENTS
Param
No.
Sym
TMCL
Characteristic
Min
Typ†
Max Units
Conditions
30
2
TBD
—
TBD
—
s VDD = 5V, -40°C to +85°C
MCLR Pulse Width (low)
TBD
ms Extended temperature
31
TWDT
TOST
Watchdog Timer Time-out
Period
(No Prescaler)
10
10
17
17
25
30
ms VDD = 5V, -40°C to +85°C
ms Extended temperature
32
Oscillation Start-up Timer
Period
—
1024TOSC
—
—
TOSC = OSC1 period
33*
TPWRT Power-up Timer Period
28*
TBD
72
TBD
132*
TBD
ms VDD = 5V, -40°C to +85°C
ms Extended Temperature
34
TIOZ
I/O High-impedance from
MCLR Low or Watchdog Timer
Reset
—
—
2.0
s
BVDD
TBOD
Brown-out Detect Voltage
Brown-out Hysteresis
2.025
TBD
100*
—
—
—
2.175
—
V
—
35
*
Brown-out Detect Pulse Width
—
s VDD BVDD (D005)
These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
DS41190G-page 100
2010 Microchip Technology Inc.
PIC12F629/675
FIGURE 12-9:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
45
46
48
47
TMR0 or
TMR1
TABLE 12-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
Sym
Characteristic
Min
Typ† Max Units
Conditions
No.
40*
Tt0H
T0CKI High Pulse Width
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
10
0.5 TCY + 20
10
41*
42*
Tt0L
Tt0P
T0CKI Low Pulse Width
T0CKI Period
Greater of:
20 or TCY + 40
N
ns N = prescale value
(2, 4, ..., 256)
45*
46*
47*
Tt1H
Tt1L
T1CKI High Time Synchronous, No Prescaler
0.5 TCY + 20
15
—
—
—
—
ns
ns
Synchronous,
with Prescaler
Asynchronous
30
0.5 TCY + 20
15
—
—
—
—
—
—
ns
ns
ns
T1CKI Low Time Synchronous, No Prescaler
Synchronous,
with Prescaler
Asynchronous
30
—
—
—
—
ns
Tt1P
Ft1
T1CKI Input
Period
Synchronous
Greater of:
30 or TCY + 40
N
ns N = prescale value
(1, 2, 4, 8)
Asynchronous
60
—
—
—
ns
Timer1 oscillator input frequency range
DC
200*
kHz
(oscillator enabled by setting bit T1OSCEN)
48
TCKEZtmr1 Delay from external clock edge to timer increment
2 TOSC*
—
7
—
TOSC*
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
2010 Microchip Technology Inc.
DS41190G-page 101
PIC12F629/675
TABLE 12-6: COMPARATOR SPECIFICATIONS
Standard Operating Conditions
-40°C to +125°C (unless otherwise stated)
Comparator Specifications
Sym Characteristics
Min
Typ
Max
Units
Comments
VOS
Input Offset Voltage
—
0
5.0
—
10
VDD - 1.5
—
mV
V
VCM
CMRR
TRT
Input Common Mode Voltage
Common Mode Rejection Ratio
Response Time(1)
+55*
—
—
db
ns
s
150
—
400*
TMC2COV Comparator Mode Change to
Output Valid
—
10*
*
These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from
VSS to VDD - 1.5V.
TABLE 12-7: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS
Standard Operating Conditions
Voltage Reference Specifications
-40°C to +125°C (unless otherwise stated)
Sym
Characteristics
Resolution
Min
Typ
Max
Units
Comments
—
—
VDD/24*
VDD/32
—
—
LSb Low Range (VRR = 1)
LSb High Range (VRR = 0)
Absolute Accuracy
—
—
—
—
1/2
1/2*
LSb Low Range (VRR = 1)
LSb High Range (VRR = 0)
Unit Resistor Value (R)
Settling Time(1)
—
—
2k*
—
—
10*
s
*
These parameters are characterized but not tested.
Note 1: Settling time measured while VRR = 1and VR<3:0> transitions from 0000to 1111.
DS41190G-page 102
2010 Microchip Technology Inc.
PIC12F629/675
TABLE 12-8: PIC12F675 A/D CONVERTER CHARACTERISTICS:
Param
No.
Sym
NR
Characteristic
Min
Typ†
Max
Units
Conditions
A01
Resolution
—
—
—
—
10 bits
bit
A02
EABS Total Absolute
Error*
1
LSb VREF = 5.0V
A03
A04
EIL
Integral Error
—
—
—
—
1
1
LSb VREF = 5.0V
EDL
Differential Error
LSb No missing codes to 10 bits
VREF = 5.0V
A05
A06
A07
A10
EFS
Full Scale Range
2.2*
—
—
—
5.5*
1
V
EOFF Offset Error
LSb VREF = 5.0V
LSb VREF = 5.0V
EGN
—
Gain Error
—
—
1
(3)
guaranteed
Monotonicity
—
—
—
V
VSS VAIN VREF+
A20
A20A
VREF Reference Voltage
2.0
2.5
—
—
VDD + 0.3
Absolute minimum to ensure 10-bit
accuracy
A21
A25
A30
VREF Reference V High
(VDD or VREF)
VSS
VSS
—
—
—
—
VDD
VREF
10
V
V
VAIN Analog Input
Voltage
ZAIN Recommended
Impedance of
Analog Voltage
Source
k
A50
IREF
VREF Input
Current(2)
10
—
—
—
1000
10
A During VAIN acquisition.
Based on differential of VHOLD to VAIN.
A During A/D conversion cycle.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: When A/D is off, it will not consume any current other than leakage current. The power-down current spec
includes any such leakage from the A/D module.
2: VREF current is from External VREF or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2010 Microchip Technology Inc.
DS41190G-page 103
PIC12F629/675
FIGURE 12-10:
PIC12F675 A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
134
Q4
1 TCY
(1)
(TOSC/2)
131
130
A/D CLK
9
8
7
6
3
2
1
0
A/D DATA
ADRES
NEW_DATA
1 TCY
OLD_DATA
ADIF
GO
DONE
SAMPLING STOPPED
132
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 12-9: PIC12F675 A/D CONVERSION REQUIREMENTS
Param
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
No.
130
TAD
A/D Clock Period
1.6
—
—
—
—
s TOSC based, VREF 3.0V
s TOSC based, VREF full range
3.0*
130
TAD
A/D Internal RC
Oscillator Period
ADCS<1:0> = 11(RC mode)
s At VDD = 2.5V
3.0*
2.0*
—
6.0
4.0
11
9.0*
6.0*
—
s At VDD = 5.0V
131
132
TCNV Conversion Time
(not including
TAD Set GO bit to new data in A/D result
register
Acquisition Time)(1)
TACQ Acquisition Time
(Note 2)
11.5
—
—
—
s
5*
s The minimum time is the amplifier
settling time. This may be used if the
“new” input voltage has not changed
by more than 1 LSb (i.e., 4.1 mV @
4.096V) from the last sampled
voltage (as stored on CHOLD).
134
TGO
Q4 to A/D Clock
Start
—
TOSC/2
—
—
If the A/D clock source is selected as
RC, a time of TCY is added before
the A/D clock starts. This allows the
SLEEPinstruction to be executed.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 7.1 “A/D Configuration and Operation” for minimum conditions.
DS41190G-page 104
2010 Microchip Technology Inc.
PIC12F629/675
FIGURE 12-11:
PIC12F675 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
134
(1)
(TOSC/2 + TCY)
1 TCY
131
Q4
130
A/D CLK
9
8
7
3
2
1
0
6
A/D DATA
NEW_DATA
1 TCY
OLD_DATA
ADRES
ADIF
GO
DONE
SAMPLING STOPPED
132
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 12-10: PIC12F675 A/D CONVERSION REQUIREMENTS (SLEEP MODE)
Param
Sym
Characteristic
Min
Typ†
Max Units
Conditions
No.
130
TAD
A/D Clock Period
1.6
—
—
—
—
s VREF 3.0V
s VREF full range
ADCS<1:0> = 11(RC mode)
s At VDD = 2.5V
3.0*
130
TAD
A/D Internal RC
Oscillator Period
3.0*
2.0*
—
6.0
4.0
11
9.0*
6.0*
—
s At VDD = 5.0V
131
132
TCNV
TACQ
Conversion Time
(not including
TAD
Acquisition Time)(1)
Acquisition Time
(Note 2)
11.5
—
—
—
s
5*
s The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1 LSb (i.e.,
4.1 mV @ 4.096V) from the last
sampled voltage (as stored on
CHOLD).
134
TGO
Q4 to A/D Clock
Start
—
TOSC/2 + TCY
—
—
If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEPinstruction to be
executed.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 7.1 “A/D Configuration and Operation” for minimum conditions.
2010 Microchip Technology Inc.
DS41190G-page 105
PIC12F629/675
NOTES:
DS41190G-page 106
2010 Microchip Technology Inc.
PIC12F629/675
13.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period
of time and matrix samples. “Typical” represents the mean of the distribution at 25°C. “Max” or “min” represents
(mean + 3) or (mean - 3) respectively, where is standard deviation, over the whole temperature range.
FIGURE 13-1:
TYPICAL IPD vs. VDD OVER TEMP (-40°C TO +25°C)
Typical Baseline IPD
6.0E-09
5.0E-09
4.0E-09
3.0E-09
2.0E-09
1.0E-09
0.0E+00
-40
0
25
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
FIGURE 13-2:
TYPICAL IPD vs. VDD OVER TEMP (+85°C)
Typical Baseline IPD
3.5E-07
3.0E-07
2.5E-07
2.0E-07
1.5E-07
1.0E-07
5.0E-08
0.0E+00
85
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2010 Microchip Technology Inc.
DS41190G-page 107
PIC12F629/675
FIGURE 13-3:
TYPICAL IPD vs. VDD OVER TEMP (+125°C)
Typical Baseline IPD
4.0E-06
3.5E-06
3.0E-06
2.5E-06
2.0E-06
1.5E-06
1.0E-06
5.0E-07
0.0E+00
125
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 13-4:
MAXIMUM IPD vs. VDD OVER TEMP (-40°C TO +25°C)
Maximum Baseline IPD
1.0E-07
9.0E-08
8.0E-08
7.0E-08
6.0E-08
5.0E-08
4.0E-08
3.0E-08
2.0E-08
1.0E-08
0.0E+00
-40
0
25
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
DS41190G-page 108
2010 Microchip Technology Inc.
PIC12F629/675
FIGURE 13-5:
MAXIMUM IPD vs. VDD OVER TEMP (+85°C)
Maximum Baseline IPD
9.0E-07
8.0E-07
7.0E-07
6.0E-07
5.0E-07
4.0E-07
3.0E-07
2.0E-07
1.0E-07
0.0E+00
85
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 13-6:
MAXIMUM IPD vs. VDD OVER TEMP (+125°C)
Maximum Baseline IPD
9.0E-06
8.0E-06
7.0E-06
6.0E-06
5.0E-06
4.0E-06
3.0E-06
2.0E-06
1.0E-06
0.0E+00
125
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2010 Microchip Technology Inc.
DS41190G-page 109
PIC12F629/675
FIGURE 13-7:
TYPICAL IPD WITH BOD ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)
Typical BOD IPD
130
120
110
100
90
-40
0
25
85
125
80
70
60
50
3
3.5
4
4.5
5
5.5
V
DD
(V)
FIGURE 13-8:
TYPICAL IPD WITH CMP ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)
Typical Comparator IPD
1.8E-05
1.6E-05
1.4E-05
1.2E-05
1.0E-05
8.0E-06
6.0E-06
4.0E-06
2.0E-06
0.0E+00
-40
0
25
85
125
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
(V)
DD
DS41190G-page 110
2010 Microchip Technology Inc.
PIC12F629/675
FIGURE 13-9:
TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (-40°C TO +25°C)
Typical A/D IPD
5.0E-09
4.5E-09
4.0E-09
3.5E-09
3.0E-09
2.5E-09
2.0E-09
1.5E-09
1.0E-09
5.0E-10
0.0E+00
-40
0
25
2
2.5
3
3.5
4
4.5
5
5.5
V
(V)
DD
FIGURE 13-10:
TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+85°C)
Typical A/D IPD
3.5E-07
3.0E-07
2.5E-07
2.0E-07
1.5E-07
1.0E-07
5.0E-08
0.0E+00
85
2
2.5
3
3.5
4
4.5
5
5.5
V
DD
(V)
2010 Microchip Technology Inc.
DS41190G-page 111
PIC12F629/675
FIGURE 13-11:
TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+125°C)
Typical A/D IPD
3.5E-06
3.0E-06
2.5E-06
2.0E-06
1.5E-06
1.0E-06
5.0E-07
0.0E+00
125
2
2.5
3
3.5
4
4.5
5
5.5
V
(V)
DD
FIGURE 13-12:
TYPICAL IPD WITH T1 OSC ENABLED vs. VDD OVER TEMP (-40°C TO +125°C),
32 kHZ, C1 AND C2=50 pF)
Typical T1 IPD
1.20E-05
1.00E-05
8.00E-06
6.00E-06
4.00E-06
2.00E-06
0.00E+00
-40
0
25
85
125
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
(V)
DD
DS41190G-page 112
2010 Microchip Technology Inc.
PIC12F629/675
FIGURE 13-13:
TYPICAL IPD WITH CVREF ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)
Typical CVREF IPD
160
140
120
100
80
-40
0
25
85
125
60
40
2
2.5
3
3.5
4
4.5
5
5.5
V
(V)
DD
FIGURE 13-14:
TYPICAL IPD WITH WDT ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)
Typical WDT IPD
16
14
12
10
8
-40
0
25
85
125
6
4
2
0
2
2.5
3
3.5
4
4.5
5
5.5
V
(V)
DD
2010 Microchip Technology Inc.
DS41190G-page 113
PIC12F629/675
FIGURE 13-15:
MAXIMUM AND MINIMUMINTOSC FREQ vs. TEMPERATURE WITH 0.1F AND
0.01F DECOUPLING (VDD = 3.5V)
Internal Oscillator
Frequency vs Temperature
4.20E+06
4.15E+06
4.10E+06
4.05E+06
4.00E+06
3.95E+06
3.90E+06
3.85E+06
3.80E+06
-3sigma
average
+3sigma
-40°C
0°C
25°C
85°C
125°C
Temperature (°C)
FIGURE 13-16:
MAXIMUM AND MINIMUMINTOSC FREQ vs. VDD WITH 0.1F AND 0.01F
DECOUPLING (+25°C)
Internal Oscillator
Frequency vs VDD
4.20E+06
4.15E+06
4.10E+06
4.05E+06
4.00E+06
3.95E+06
3.90E+06
3.85E+06
3.80E+06
-3sigma
average
+3sigma
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
VDD (V)
DS41190G-page 114
2010 Microchip Technology Inc.
PIC12F629/675
FIGURE 13-17:
TYPICAL WDT PERIOD vs. VDD (-40C TO +125C)
WDT Time-out
50
45
40
35
30
25
20
15
10
5
-40
0
25
85
125
0
2
2.5
3
3.5
4
4.5
5
5.5
V
(V)
DD
2010 Microchip Technology Inc.
DS41190G-page 115
PIC12F629/675
NOTES:
DS41190G-page 116
2010 Microchip Technology Inc.
PIC12F629/675
14.0 PACKAGING INFORMATION
14.1 Package Marking Information
8-Lead PDIP (Skinny DIP)
Example
12F629-I
XXXXXXXX
XXXXXNNN
YYWW
/017
e3
0215
8-Lead SOIC
Example
12F629-E
XXXXXXXX
XXXXYYWW
NNN
/0215
e3
017
8-Lead DFN-S
Example
XXXXXXX
XXXXXXX
XXYYWW
NNN
12F629
-E/021
0215
017
e
3
Example
8-Lead DFN (4x4 mm)
XXXXXX
XXXXXX
XXXX
0610
e
3
XXXXXX
YYWW
NNN
017
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2010 Microchip Technology Inc.
DS41190G-page 117
PIC12F629/675
14.2 Package Details
The following sections give the technical details of the packages.
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DS41190G-page 118
2010 Microchip Technology Inc.
PIC12F629/675
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢞꢖꢄꢈꢈꢆꢟꢎꢊꢈꢋꢐꢃꢆꢑꢞꢜꢒꢆꢓꢆꢜꢄꢠꢠꢘꢡꢢꢆꢔꢣꢤꢕꢆꢖꢖꢆꢗꢘꢅꢙꢆꢚꢞꢟꢏꢥꢛ
ꢜꢘꢊꢃꢝ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
D
e
N
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E1
NOTE 1
1
2
3
α
h
b
h
c
φ
A2
A
L
A1
L1
β
6ꢄꢃ&!
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7:ꢔ
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ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅꢙꢍꢃꢌ4ꢄꢈ!!
ꢐ&ꢆꢄ#ꢋ%%ꢅꢅꢏ
ꢗ
M
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ꢕꢁꢀꢕ
M
M
M
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ꢗꢀ
.
: ꢈꢉꢆꢇꢇꢅ>ꢃ#&ꢍ
?ꢁꢕꢕꢅ1ꢐ,
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅ9ꢈꢄꢑ&ꢍ
,ꢍꢆ'%ꢈꢉꢅ@ꢋꢓ&ꢃꢋꢄꢆꢇA
3ꢋꢋ&ꢅ9ꢈꢄꢑ&ꢍ
.ꢀ
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ꢍ
-ꢁꢛꢕꢅ1ꢐ,
ꢖꢁꢛꢕꢅ1ꢐ,
ꢕꢁꢎꢘ
ꢕꢁꢖꢕ
M
M
ꢕꢁꢘꢕ
ꢀꢁꢎꢜ
9
3ꢋꢋ&ꢓꢉꢃꢄ&
3ꢋꢋ&ꢅꢗꢄꢑꢇꢈ
9ꢈꢆ#ꢅꢙꢍꢃꢌ4ꢄꢈ!!
9ꢈꢆ#ꢅ>ꢃ#&ꢍ
ꢔꢋꢇ#ꢅꢒꢉꢆ%&ꢅꢗꢄꢑꢇꢈꢅꢙꢋꢓ
ꢔꢋꢇ#ꢅꢒꢉꢆ%&ꢅꢗꢄꢑꢇꢈꢅ1ꢋ&&ꢋ'
9ꢀ
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ꢀꢁꢕꢖꢅꢝ.3
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ꢘꢟ
ꢀꢘꢟ
ꢜꢘꢊꢃꢉꢝ
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢏꢅꢐꢃꢑꢄꢃ%ꢃꢌꢆꢄ&ꢅ,ꢍꢆꢉꢆꢌ&ꢈꢉꢃ!&ꢃꢌꢁ
-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢒꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢔꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢕꢁꢀꢘꢅ''ꢅꢓꢈꢉꢅ!ꢃ#ꢈꢁ
ꢖꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕꢘꢜ1
2010 Microchip Technology Inc.
DS41190G-page 119
PIC12F629/675
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢞꢖꢄꢈꢈꢆꢟꢎꢊꢈꢋꢐꢃꢆꢑꢞꢜꢒꢆꢓꢆꢜꢄꢠꢠꢘꢡꢢꢆꢔꢣꢤꢕꢆꢖꢖꢆꢗꢘꢅꢙꢆꢚꢞꢟꢏꢥꢛ
ꢜꢘꢊꢃꢝ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
DS41190G-page 120
2010 Microchip Technology Inc.
PIC12F629/675
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢦꢈꢄꢊꢢꢆꢜꢘꢆꢂꢃꢄꢅꢆꢇꢄꢌꢧꢄꢨꢃꢆꢑꢩꢦꢒꢆꢓꢆꢪꢫꢬꢆꢖꢖꢆꢗꢘꢅꢙꢆꢚꢍꢦꢜꢁꢞꢛ
ꢜꢘꢊꢃꢝ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
ꢅ
e
D
L
b
N
N
K
E
E2
EXPOSED PAD
NOTE 1
NOTE 1
1
2
1
2
D2
BOTTOM VIEW
TOP VIEW
A
A3
A1
NOTE 2
6ꢄꢃ&!
ꢔꢚ99ꢚꢔ.ꢙ.ꢝꢐ
ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢅ9ꢃ'ꢃ&!
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ꢂꢃ&ꢌꢍ
: ꢈꢉꢆꢇꢇꢅ8ꢈꢃꢑꢍ&
ꢐ&ꢆꢄ#ꢋ%%ꢅ
,ꢋꢄ&ꢆꢌ&ꢅꢙꢍꢃꢌ4ꢄꢈ!!
: ꢈꢉꢆꢇꢇꢅ9ꢈꢄꢑ&ꢍ
: ꢈꢉꢆꢇꢇꢅ>ꢃ#&ꢍ
7
ꢈ
ꢗ
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ꢀꢁꢕꢕ
ꢕꢁꢕꢘ
ꢕꢁꢕꢀ
ꢕꢁꢎꢕꢅꢝ.3
ꢘꢁꢕꢕꢅ1ꢐ,
?ꢁꢕꢕꢅ1ꢐ,
ꢖꢁꢕꢕ
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.
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.$ꢓꢋ!ꢈ#ꢅꢂꢆ#ꢅ>ꢃ#&ꢍ
,ꢋꢄ&ꢆꢌ&ꢅ>ꢃ#&ꢍ
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9
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ꢖꢁꢀꢕ
ꢎꢁꢖꢕ
ꢕꢁꢖ<
ꢕꢁꢜꢘ
M
ꢕꢁ?ꢕ
M
ꢜꢘꢊꢃꢉꢝ
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢂꢆꢌ4ꢆꢑꢈꢅ'ꢆꢊꢅꢍꢆ ꢈꢅꢋꢄꢈꢅꢋꢉꢅ'ꢋꢉꢈꢅꢈ$ꢓꢋ!ꢈ#ꢅ&ꢃꢈꢅ)ꢆꢉ!ꢅꢆ&ꢅꢈꢄ#!ꢁ
-ꢁ ꢂꢆꢌ4ꢆꢑꢈꢅꢃ!ꢅ!ꢆ*ꢅ!ꢃꢄꢑ"ꢇꢆ&ꢈ#ꢁ
ꢖꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢀꢎꢎ1
2010 Microchip Technology Inc.
DS41190G-page 121
PIC12F629/675
ꢜꢘꢊꢃꢝ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
DS41190G-page 122
2010 Microchip Technology Inc.
PIC12F629/675
8-Lead Plastic Dual Flat, No Lead Package (MD) 4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 1 of 2
2010 Microchip Technology Inc.
DS41190G-page 123
PIC12F629/675
8-Lead Plastic Dual Flat, No Lead Package (MD) 4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 2 of 2
DS41190G-page 124
2010 Microchip Technology Inc.
PIC12F629/675
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢦꢈꢄꢊꢢꢆꢜꢘꢆꢂꢃꢄꢅꢆꢇꢄꢌꢧꢄꢨꢃꢆꢑꢩDꢒꢆꢓꢆꢭꢫꢭꢫꢕꢣꢤꢆꢖꢖꢆꢗꢘꢅꢙꢆꢚꢍꢦꢜꢛ
ꢜꢘꢊꢃꢝ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
2010 Microchip Technology Inc.
DS41190G-page 125
PIC12F629/675
NOTES:
DS41190G-page 126
2010 Microchip Technology Inc.
PIC12F629/675
APPENDIX A: DATA SHEET
REVISION HISTORY
APPENDIX B: DEVICE
DIFFERENCES
The differences between the PIC12F629/675 devices
listed in this data sheet are shown in Table B-1.
Revision A
This is a new data sheet.
TABLE B-1:
Feature
A/D
DEVICE DIFFERENCES
PIC12F629 PIC12F675
Revision B
Added characterization graphs.
Updated specifications.
No
Yes
Added notes to indicate Microchip programmers
maintain all Calibration bits to factory settings and the
PIC12F675 ANSEL register must be initialized to
configure pins as digital I/O.
Updated MLF-S package name to DFN-S.
Revision C
Revision D (01/2007)
Updated Package Drawings; Replace PICmicro with
PIC; Revised Product ID example (b).
Revision E (03/2007)
Replaced Package Drawings (Rev. AM); Replaced
Development Support Section.
Revision F (09/2009)
Updated Registers to new format; Added information to
the “Package Marking Information” (8-Lead DFN) and
“Package Details” sections (8-Lead Dual Flat, No Lead
Package (MD) 4X4X0.9 mm Body (DFN)); Added Land
Patterns for SOIC (SN) and DFN-S (MF) packages;
Updated Register 3-2; Added MD Package to the
Product identification System chapter; Other minor
corrections.
Revision G (03/2010)
Updated the Instruction Set Summary section, adding
pages 76 and 77.
2010 Microchip Technology Inc.
DS41190G-page 127
PIC12F629/675
APPENDIX C: DEVICE MIGRATIONS
APPENDIX D: MIGRATING FROM
OTHER PIC®
This section is intended to describe the functional and
electrical specification differences when migrating
between functionally similar devices (such as from a
PIC16C74A to a PIC16C74B).
DEVICES
This discusses some of the issues in migrating from
other PIC devices to the PIC12F6XX family of devices.
Not Applicable
D.1
PIC12C67X to PIC12F6XX
TABLE 1:
Feature
FEATURE COMPARISON
PIC12C67X PIC12F6XX
Max Operating Speed
Max Program Memory
A/D Resolution
10 MHz
2048 bytes
8-bit
20 MHz
1024 bytes
10-bit
Data EEPROM
16 bytes
5
64 bytes
8
Oscillator Modes
Brown-out Detect
Internal Pull-ups
Interrupt-on-change
Comparator
N
Y
GP0/1/3
GP0/1/3
N
GP0/1/2/4/5
GP0/1/2/3/4/5
Y
Note: This device has been designed to perform
to the parameters of its data sheet. It has
been tested to an electrical specification
designed to determine its conformance
with these parameters. Due to process
differences in the manufacture of this
device, this device may have different
performance characteristics than its earlier
version. These differences may cause this
device to perform differently in your
application than the earlier version of this
device.
Note: The user should verify that the device
oscillator starts and performs as expected.
Adjusting the loading capacitor values and/
or the oscillator mode may be required.
DS41190G-page 128
2010 Microchip Technology Inc.
PIC12F629/675
Interrupts .................................................................... 42
Operation.................................................................... 38
Operation During SLEEP............................................ 41
Output......................................................................... 40
Reference................................................................... 41
Response Time .......................................................... 41
Comparator Specifications................................................ 102
Comparator Voltage Reference Specifications................. 102
Configuration Bits ............................................................... 54
Configuring the Voltage Reference..................................... 41
Crystal Operation................................................................ 55
Customer Change Notification Service............................. 133
Customer Notification Service .......................................... 133
Customer Support............................................................. 133
INDEX
A
A/D...................................................................................... 43
Acquisition Requirements ........................................... 47
Block Diagram............................................................. 43
Calculating Acquisition Time....................................... 47
Configuration and Operation....................................... 43
Effects of a RESET..................................................... 48
Internal Sampling Switch (Rss) Impedance................ 47
Operation During SLEEP............................................ 48
PIC12F675 Converter Characteristics ...................... 103
Source Impedance...................................................... 47
Summary of Registers ................................................ 48
Absolute Maximum Ratings ................................................ 85
AC Characteristics
D
Data EEPROM Memory
Industrial and Extended .............................................. 96
ADCON0
Associated Registers/Bits........................................... 52
Code Protection.......................................................... 52
EEADR Register......................................................... 49
EECON1 Register ...................................................... 49
EECON2 Register ...................................................... 49
EEDATA Register....................................................... 49
Data Memory Organization................................................... 9
DC Characteristics
A/D Control register (ADDRESS
1Fh) .................................................................... 45
Additional Pin Functions ..................................................... 21
Interrupt-on-Change.................................................... 23
Weak Pull-up............................................................... 21
Analog Input Connection Considerations............................ 40
Analog-to-Digital Converter. See A/D
Extended and Industrial.............................................. 93
Industrial..................................................................... 88
Development Support......................................................... 81
Device Differences............................................................ 127
Device Migrations ............................................................. 128
Device Overview................................................................... 7
Assembler
MPASM Assembler..................................................... 82
B
Block Diagram
TMR0/WDT Prescaler................................................. 29
Block Diagrams
E
Analog Input Mode...................................................... 40
Analog Input Model..................................................... 47
Comparator Output ..................................................... 40
Comparator Voltage Reference .................................. 41
GP0 and GP1 Pins...................................................... 24
GP2............................................................................. 25
GP3............................................................................. 25
GP4............................................................................. 26
GP5............................................................................. 26
On-Chip Reset Circuit................................................. 57
RC Oscillator Mode..................................................... 56
Timer1......................................................................... 32
Watchdog Timer.......................................................... 67
Brown-out
EEADR — EEPROM Address Register (ADDRESS
9Bh)............................................................................ 49
EECON1 — EEPROM Control register (Address
9Ch)............................................................................ 50
EEPROM Data Memory
Reading ...................................................................... 51
Spurious Write............................................................ 51
Write Verify................................................................. 51
Writing ........................................................................ 51
Electrical Specifications...................................................... 85
Errata.................................................................................... 5
F
Firmware Instructions ......................................................... 71
Associated Registers .................................................. 60
Brown-out Detect (BOD)..................................................... 59
Brown-out Detect Timing and Characteristics..................... 99
G
General Purpose Register File ............................................. 9
GPIO
Associated Registers.................................................. 27
GPIO — GPIO register (ADDRESS
C
C Compilers
MPLAB C18 ................................................................ 82
Calibrated Internal RC Frequencies.................................... 97
CLKOUT ............................................................................. 56
Code Examples
05H)............................................................................ 21
GPIO Port........................................................................... 21
GPIO, TRISIO Registers..................................................... 21
I
Changing Prescaler .................................................... 31
Data EEPROM Read .................................................. 51
Data EEPROM Write .................................................. 51
Initializing GPIO .......................................................... 21
Saving STATUS and W Registers in RAM ................. 66
Write Verify ................................................................. 51
Code Protection .................................................................. 69
Comparator......................................................................... 37
Associated Registers .................................................. 42
Configuration............................................................... 39
Effects of a RESET..................................................... 41
I/O Operating Modes................................................... 39
ID Locations........................................................................ 69
In-Circuit Debugger............................................................. 69
In-Circuit Serial Programming............................................. 69
Indirect Addressing, INDF and FSR Registers ................... 20
Instruction Format............................................................... 71
Instruction Set..................................................................... 71
ADDLW....................................................................... 73
ADDWF ...................................................................... 73
ANDLW....................................................................... 73
ANDWF ...................................................................... 73
MOVF ......................................................................... 76
2010 Microchip Technology Inc.
DS41190G-page 129
PIC12F629/675
BCF.............................................................................73
BSF.............................................................................73
BTFSC ........................................................................74
BTFSS ........................................................................73
CALL...........................................................................74
CLRF...........................................................................74
CLRW .........................................................................74
CLRWDT.....................................................................74
COMF .........................................................................74
DECF ..........................................................................74
DECFSZ......................................................................75
GOTO .........................................................................75
INCF............................................................................75
INCFSZ.......................................................................75
IORLW ........................................................................75
IORWF........................................................................75
MOVLW ......................................................................76
MOVWF ......................................................................76
NOP ............................................................................76
RETFIE .......................................................................77
RETLW .......................................................................77
RETURN.....................................................................77
RLF .............................................................................78
RRF.............................................................................78
SLEEP ........................................................................78
SUBLW .......................................................................78
SUBWF.......................................................................78
SWAPF .......................................................................78
XORLW.......................................................................79
XORWF.......................................................................79
Summary Table...........................................................72
Internal 4 MHz Oscillator.....................................................56
Internal Sampling Switch (Rss) Impedance ........................47
Internet Address................................................................133
Interrupts.............................................................................63
A/D Converter .............................................................65
Comparator.................................................................65
Context Saving............................................................66
GP2/INT......................................................................65
GPIO...........................................................................65
Summary of Registers ................................................66
TMR0 ..........................................................................65
IOC — INTERRUPT-ON-CHANGE GPIO register
Stack........................................................................... 19
Pin Descriptions and Diagrams .......................................... 24
Pinout Descriptions
PIC12F629 ................................................................... 8
PIC12F675 ................................................................... 8
Power Control/Status Register (PCON).............................. 59
Power-Down Mode (SLEEP) .............................................. 68
Power-on Reset (POR)....................................................... 58
Power-up Timer (PWRT) .................................................... 58
Prescaler............................................................................. 31
Switching Prescaler Assignment ................................ 31
Program Memory Organization............................................. 9
Programming, Device Instructions...................................... 71
R
RC Oscillator....................................................................... 56
Reader Response............................................................. 134
READ-MODIFY-WRITE OPERATIONS ............................. 71
Registers
ANSEL (Analog Select) .............................................. 46
CONFIG (Configuration Word) ................................... 54
EEADR (EEPROM Address) ...................................... 50
EECON1 (EEPROM Control) ..................................... 51
EEDAT (EEPROM Data)............................................ 49
INTCON (Interrupt Control)......................................... 15
IOCB (Interrupt-on-Change GPIO)............................. 24
Maps
PIC12F629 ......................................................... 10
PIC12F675 ......................................................... 10
OPTION_REG (Option).................................. 14, 30, 31
OSCCAL (Oscillator Calibration) ................................ 18
PCON (Power Control) ............................................... 18
PIE1 (Peripheral Interrupt Enable 1)........................... 16
PIR1 (Peripheral Interrupt 1)....................................... 17
STATUS ..................................................................... 14
T1CON (Timer1 Control) ............................................ 34
VRCON (Voltage Reference Control)......................... 42
WPU (Weak Pull-up)................................................... 23
RESET................................................................................ 57
Revision History................................................................ 127
S
Software Simulator (MPLAB SIM) ...................................... 83
Special Features of the CPU .............................................. 53
Special Function Registers................................................. 10
Special Functions Registers Summary............................... 11
STATUS — STATUS Register (ADDRESS
(ADDRESS 96h) .................................................................23
M
MCLR..................................................................................58
Memory Organization
03h or 83h) ................................................................. 13
T
Data EEPROM Memory..............................................49
Microchip Internet Web Site..............................................133
Migrating from other PICmicro Devices ............................128
MPLAB ASM30 Assembler, Linker, Librarian .....................82
MPLAB Integrated Development Environment Software ....81
MPLAB PM3 Device Programmer.......................................84
MPLAB REAL ICE In-Circuit Emulator System...................83
MPLINK Object Linker/MPLIB Object Librarian ..................82
Time-out Sequence ............................................................ 59
Timer0................................................................................. 29
Associated Registers.................................................. 31
External Clock............................................................. 30
Interrupt ...................................................................... 29
Operation.................................................................... 29
T0CKI ......................................................................... 30
Timer1
O
Associated Registers.................................................. 35
Asynchronous Counter Mode..................................... 35
Reading and Writing........................................... 35
Interrupt ...................................................................... 33
Modes of Operations .................................................. 33
Operation During SLEEP............................................ 35
Oscillator..................................................................... 35
Prescaler .................................................................... 33
Timer1 Module with Gate Control....................................... 32
Timing Diagrams
OPCODE Field Descriptions...............................................71
Oscillator Configurations.....................................................55
Oscillator Start-up Timer (OST) ..........................................58
P
Packaging .........................................................................117
Details.......................................................................118
Marking .....................................................................117
PCL and PCLATH...............................................................19
Computed GOTO........................................................19
DS41190G-page 130
2010 Microchip Technology Inc.
PIC12F629/675
CLKOUT and I/O......................................................... 98
External Clock............................................................. 96
INT Pin Interrupt.......................................................... 65
PIC12F675 A/D Conversion (Normal Mode)............. 104
PIC12F675 A/D Conversion Timing
(SLEEP Mode).......................................................... 105
RESET, Watchdog Timer, Oscillator Start-up Timer
and Power-up Timer .................................................. 99
Time-out Sequence on Power-up (MCLR not Tied to
VDD)/
Case 1 ................................................................ 62
Case 2 ................................................................ 62
Time-out Sequence on Power-up
(MCLR Tied to VDD).................................................... 62
Timer0 and Timer1 External Clock ........................... 101
Timer1 Incrementing Edge.......................................... 33
Timing Parameter Symbology............................................. 95
TRISIO — GPIO Tri-state REGISTER (Address
85H) ............................................................................ 22
V
Voltage Reference Accuracy/Error ..................................... 41
W
Watchdog Timer
Summary of Registers ................................................ 67
Watchdog Timer (WDT)...................................................... 66
WPU — Weak pull-up Register (ADDRESS
95h)............................................................................. 22
WWW Address.................................................................. 133
WWW, On-Line Support ....................................................... 5
2010 Microchip Technology Inc.
DS41190G-page 131
PIC12F629/675
NOTES:
DS41190G-page 132
2010 Microchip Technology Inc.
PIC12F629/675
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
2010 Microchip Technology Inc.
DS41190G-page 133
PIC12F629/675
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
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Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
PIC12F629/675
DS41190G
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41190G-page 134
2010 Microchip Technology Inc.
PIC12F629/675
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
PIC12F629 - E/P 301 = Extended Temp., PDIP
package, 20 MHz, QTP pattern #301.
PIC12F675 - I/SN = Industrial temp., SOIC
package, 20 MHz.
b)
Device:
PIC12F6XX: Standard VDD range
PIC12F6XXT: (Tape and Reel)
Temperature
Range:
I
E
=
=
-40C to +85C (Industrial)
-40C to +125C (Extended)
Package:
P
=
=
=
=
PDIP
SN
MF
MD
SOIC (Gull wing, 3.90 mm body)
MLF-S
8-Lead Plastic Dual Flat, No Lead (4X4) (DFN)
Pattern:
3-Digit Pattern Code for QTP (blank otherwise)
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type.
2010 Microchip Technology Inc.
DS41190G-page 135
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
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Technical Support:
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Web Address:
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Kokomo
Kokomo, IN
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Fax: 765-864-8387
China - Shenzhen
Tel: 86-755-8203-2660
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Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
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Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
China - Xian
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Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
01/05/10
DS41190G-page 136
2010 Microchip Technology Inc.
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