PIC12F635TE/STQTP [MICROCHIP]
8/14-PIN FLASH-BASED, 8-BIT CMOS MICROCONTROLLERS WITH NANOWATT TECHNOLOGY; 8月14日-PIN基于闪存的8位CMOS采用纳瓦技术的微控制器
| 型号： | PIC12F635TE/STQTP |
| 厂家： | 
MICROCHIP |
| 描述： | 8/14-PIN FLASH-BASED, 8-BIT CMOS MICROCONTROLLERS WITH NANOWATT TECHNOLOGY |
| 文件： | 总196页 (文件大小：3306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC12F635/PIC16F636/639
Data Sheet
8/14-Pin Flash-Based,
8-Bit CMOS Microcontrollers
with nanoWatt Technology
*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U. S. Patent No. 5,847,450. Additional U.S. and
foreign patents and applications may be issued or pending.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK,
MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel and Total
Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2005, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS41232B-page ii
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
8/14-Pin Flash-Based, 8-Bit CMOS Microcontrollers
With nanoWatt Technology
High-Performance RISC CPU:
Peripheral Features:
• Only 35 instructions to learn:
- All single-cycle instructions except branches
• Operating speed:
• 6/12 I/O pins with individual direction control:
- High-current source/sink for direct LED drive
- Interrupt-on-pin change
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instruction cycle
• Interrupt capability
• 8-level deep hardware stack
• Direct, Indirect and Relative Addressing modes
- Individually programmable weak pull-ups/
pull-downs
- Ultra Low-Power Wake-up
• Analog comparator module with:
- Up to two analog comparators
- Programmable on-chip voltage reference
(CVREF) module (% of VDD)
Special Microcontroller Features:
• Precision Internal Oscillator:
- Factory calibrated to ±1%
- Comparator inputs and outputs externally
accessible
- Software selectable frequency range of
8 MHz to 31 kHz
• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
- Software tunable
• Enhanced Timer1:
- Two-Speed Start-up mode
- 16-bit timer/counter with prescaler
- External Gate Input mode
- Crystal fail detect for critical applications
• Clock mode switching for low power operation
• Power-saving Sleep mode
• Wide operating voltage range (2.0V-5.5V)
• Industrial and Extended Temperature range
• Power-on Reset (POR)
- Option to use OSC1 and OSC2 in LP mode
as Timer1 oscillator if INTOSC mode
selected
• KEELOQ® compatible hardware Cryptographic
module
• In-Circuit Serial ProgrammingTM (ICSPTM) via
two pins
• Wake-up Reset (WUR)
• Independent weak pull-up/pull-down resistors
• Programmable Low-Voltage Detect (PLVD)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
Low Frequency Analog Front-End Features
(PIC16F639 only):
• Brown-out Detect (BOD) with software control
option
• Enhanced Low-Current Watchdog Timer (WDT)
with on-chip oscillator (software selectable
nominal 268 seconds with full prescaler) with
software enable
• Three input pins for 125 kHz LF input signals
• High input detection sensitivity (3 mVPP, typical)
• Demodulated data, Carrier clock or RSSI output
selection
• Input carrier frequency: 125 kHz, typical
• Input modulation frequency: 4 kHz, maximum
• Multiplexed Master Clear with pull-up/input pin
• Programmable code protection (program and
data independent)
• 8 internal configuration registers
• Bidirectional transponder communication
(LF talk back)
• High-Endurance Flash/EEPROM cell:
- 100,000 write Flash endurance
- 1,000,000 write EEPROM endurance
- Flash/Data EEPROM Retention: > 40 years
• Programmable antenna tuning capacitance
(up to 63 pF, 1 pF/step)
• Low standby current: 5 μA (with 3 channels
enabled), typical
• Low operating current: 15 μA (with 3 channels
enabled), typical
Low Power Features:
• Serial Peripheral Interface (SPI™) with internal
MCU and external devices
• Supports Battery Back-up mode and batteryless
operation with external circuits
• Standby Current:
- 1 nA @ 2.0V, typical
• Operating Current:
- 8.5 μA @ 32 kHz, 2.0V, typical
- 100 μA @ 1 MHz, 2.0V, typical
• Watchdog Timer Current:
- 1 μA @ 2.0V, typical
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 1
PIC12F635/PIC16F636/639
Program Memory
Flash (words)
Data Memory
LowFrequency
Analog
Device
I/O
Comparators
SRAM (bytes)
EEPROM (bytes)
Front-End
PIC12F635
PIC16F636
PIC16F639
1024
2048
2048
64
128
256
256
6
1
2
2
N
N
Y
128
128
12
12
Pin Diagrams
8-Pin PDIP, SOIC, DFN-S
8
1
2
VDD
VSS
7
GP5/T1CKI/OSC1/CLKIN
GP4/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
GP0/C1IN+/ICSPDAT/ULPWU
GP1/C1IN-/ICSPCLK
3
4
6
5
GP2/T0CKI/INT/C1OUT
14-Pin PDIP, SOIC, TSSOP
VDD
1
2
3
4
5
6
7
VSS
14
13
12
11
10
9
RA5/T1CKI/OSC1/CLKIN
RA4/T1G/OSC2/CLKOUT
RA0/C1IN+/ICSPDAT/ULPWU
RA1/C1IN-/VREF/ICSPCLK
RA3/MCLR/VPP
RC5
RC4/C2OUT
RC3
RA2/T0CKI/INT/C1OUT
RC0/C2IN+
RC1/C2IN-
RC2
8
20-Pin SSOP
VDD
RA5/T1CKI/OSC1/CLKIN
RA4/T1G/OSC2/CLKOUT
RA3/MCLR/VPP
VSS
1
2
3
4
5
6
7
8
9
10
20
19
18
RA0/C1IN+/ICSPDAT/ULPWU
RA1/C1IN-/VREF/ICSPCLK
RA2/TOCKI/INT/C1OUT
RC0/C2IN+
17
16
RC5
RC4/C2OUT
RC1/C2IN-/CS
15
14
13
12
11
RC3/LFDATA/RSSI/CCLK/SDIO
RC2/SCLK/ALERT
(3)
(4)
VDDT
VSST
LCZ
LCY
LCCOM
LCX
Note 1: Any references to PORTA, RAn, TRISA and TRISAn refer to GPIO, GPn, TRISIO and TRISIOn, respectively.
2: Additional information on I/O ports may be found in the “PICmicro® Mid-Range MCU Family Reference
Manual” (DS33023).
3: VDDT is the supply voltage of the Analog Front-End section (PIC16F639 only). VDDT is treated as VDD in
this document unless otherwise stated.
4: VSST is the ground reference voltage of the Analog Front-End section (PIC16F639 only). VSST is treated
as VSS in this document unless otherwise stated.
DS41232B-page 2
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Memory Organization................................................................................................................................................................. 11
3.0 Clock Sources ............................................................................................................................................................................ 29
4.0 I/O Ports ..................................................................................................................................................................................... 39
5.0 Timer0 Module ........................................................................................................................................................................... 53
6.0 Timer1 Module with Gate Control............................................................................................................................................... 56
7.0 Comparator Module.................................................................................................................................................................... 61
8.0 Programmable Low-Voltage Detect (PLVD) Module.................................................................................................................. 71
9.0 Data EEPROM Memory ............................................................................................................................................................. 73
10.0 KeeLoq Compatible Cryptographic Module................................................................................................................................ 77
11.0 Analog Front-End (AFE) Functional Description (PIC16F639 Only) .......................................................................................... 79
12.0 Special Features of the CPU.................................................................................................................................................... 111
13.0 Instruction Set Summary.......................................................................................................................................................... 131
14.0 Development Support............................................................................................................................................................... 141
15.0 Electrical Specifications............................................................................................................................................................ 147
16.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 173
17.0 Packaging Information.............................................................................................................................................................. 175
On-Line Support
185
Systems Information and Upgrade Hot Line ..................................................................................................................................... 185
Reader Response............................................................................................................................................................................. 186
Appendix A: Data Sheet Revision History......................................................................................................................................... 187
Appendix B: Product Identification System....................................................................................................................................... 193
Worldwide Sales and Service ........................................................................................................................................................... 194
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 3
PIC12F635/PIC16F636/639
NOTES:
DS41232B-page 4
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
The PIC12F635/PIC16F636/639 devices are covered
by this data sheet. Figure 1-1 shows a block diagram of
the PIC12F635/PIC16F636/639 devices. Table 1-1
shows the pinout description.
1.0
DEVICE OVERVIEW
This document contains device specific information for
the PIC12F635/PIC16F636/639 devices. Additional
information may be found in the “PICmicro® Mid-Range
MCU Family Reference Manual” (DS33023), which may
be obtained from your local Microchip Sales
Representative or downloaded from the Microchip web
site. The reference manual should be considered a
complementary document to this data sheet and is
highly recommended reading for a better understanding
of the device architecture and operation of the peripheral
modules.
FIGURE 1-1:
PIC12F635 BLOCK DIAGRAM
Configuration
13
8
GPIO
Data Bus
Program Counter
GP0/C1IN+/ICSPDAT/ULPWU
GP1/C1IN-/ICSPCLK
Flash
1K x 14
Program
Memory
GP2/T0CKI/INT/C1OUT
GP3/MCLR/VPP
RAM
64 bytes
8-level Stack
(13-bit)
GP4/T1G/OSC2/CLKOUT
GP5/T1CKI/OSC1/CLKIN
File
Registers
Program
Bus
14
RAM Addr
9
Addr MUX
Instruction reg
Indirect
Addr
7
Direct Addr
8
FSR reg
Status reg
8
3
Power-up
Timer
MUX
Instruction
Decode and
Control
Oscillator
Start-up Timer
ALU
Power-on
Reset
OSC1/CLKIN
8
Timing
Generation
Watchdog
Timer
W reg
Brown-out
Detect
OSC2/CLKOUT
Programmable
8 MHz
Internal
Oscillator Oscillator
31 kHz
Internal
Low-Voltage Detect
Wake-up
Reset
T1G
VDD VSS
MCLR
T1CKI
Timer0
Timer1
T0CKI
Cryptographic
Module
1 Analog
Comparator
and Reference
EEDAT
128 bytes
Data
EEPROM
EEADDR
C1IN- C1IN+ C1OUT
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 5
PIC12F635/PIC16F636/639
FIGURE 1-2:
PIC16F636 BLOCK DIAGRAM
Configuration
13
8
Data Bus
PORTA
Program Counter
RA0/C1IN+/ICSPDAT/ULPWU
RA1/C1IN-/VREF/ICSPCLK
RA2/T0CKI/INT/C1OUT
RA3/MCLR/VPP
Flash
2K x 14
Program
Memory
RAM
128
bytes
8-level Stack
(13-bit)
RA4/T1G/OSC2/CLKOUT
RA5/T1CKI/OSC1/CLKIN
File
Registers
Program
Bus
14
RAM Addr
9
Addr MUX
Instruction reg
PORTC
Indirect
Addr
7
Direct Addr
8
RC0/C2IN+
RC1/C2IN-
RC2
FSR reg
RC3
Status reg
8
RC4/C2OUT
RC5
3
Power-up
Timer
MUX
Oscillator
Instruction
Decode and
Control
Start-up Timer
ALU
Power-on
Reset
8
Watchdog
Timer
OSC1/CLKIN
W reg
Timing
Generation
Brown-out
Detect
OSC2/CLKOUT
Programmable
Low-Voltage Detect
8 MHz
Internal
Oscillator Oscillator
31 kHz
Internal
Wake-up
Reset
T1CKI T1G
VDD
VSS
MCLR
Timer0
Timer1
T0CKI
2 Analog Comparators
and Reference
Cryptographic
Module
EEDAT
256 bytes
Data
EEPROM
EEADDR
C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT
DS41232B-page 6
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 1-3:
PIC16F639 BLOCK DIAGRAM
Configuration
13
8
PORTA
Data Bus
Program Counter
RA0/C1IN+/ICSPDAT/ULPWU
RA1/C1IN-/VREF/ICSPCLK
RA2/T0CKI/INT/C1OUT
RA3/MCLR/VPP
Flash
2K x 14
Program
Memory
RAM
128
8-level Stack
(13-bit)
bytes
RA4/T1G/OSC2/CLKOUT
RA5/T1CKI/OSC1/CLKIN
File
Registers
Program
Bus
14
RAM Addr (1)
9
Addr MUX
Instruction reg
PORTC
Indirect
Addr
7
Direct Addr
RC0/C2IN+
8
RC1/C2IN-/CS
FSR reg
RC2/SCLK/ALERT
RC3/LFDATA/RSSI/CCLK/SDIO
RC4/C2OUT
Status reg
8
RC5
3
MUX
Power-up
Timer
Oscillator
Instruction
Decode and
Control
Start-up Timer
ALU
Power-on
Reset
8
Watchdog
Timer
OSC1/CLKIN
W reg
Timing
Generation
VDDT
VSST
Brown-out
Detect
125 kHz
Analog Front-End
(AFE)
OSC2/CLKOUT
Programmable
Low-voltage Detect
LCCOM
8 MHz
Internal
31 kHz
Internal
Wake-up
Reset
T1CKI T1G
Oscillator Oscillator
LCX LCY LCZ
VDD VSS
MCLR
Timer0
Timer1
T0CKI
2 Analog
Comparators
and Reference
EEDAT
256 bytes
DATA
KEELOQ Module
EEPROM
EEADDR
C1IN- C1IN+ C1OUTC2IN-
C2IN+ C2OUT
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 7
PIC12F635/PIC16F636/639
TABLE 1-1:
PIC12F635 PINOUT DESCRIPTIONS
Input Output
Name
Function
Description
Type
Type
VDD
VDD
GP5
D
—
Power supply for microcontroller.
GP5/T1CKI/OSC1/CLKIN
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up/pull-down.
T1CKI
OSC1
CLKIN
GP4
ST
XTAL
ST
—
—
—
Timer1 clock.
XTAL connection.
TOSC reference clock.
GP4/T1G/OSC2/CLKOUT
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individually enabled pull-up/pull-down.
T1G
OSC2
CLKOUT
GP3
ST
—
—
Timer1 gate.
XTAL XTAL connection.
—
CMOS TOSC/4 reference clock.
GP3/MCLR/VPP
TTL
—
—
—
General purpose input. Individually controlled
interrupt-on-change.
MCLR
ST
Master Clear Reset. Pull-up enabled when configured as
MCLR.
VPP
HV
ST
Programming voltage.
GP2/T0CKI/INT/C1OUT
GP2
CMOS General purpose I/O. Individually controlled
interrupt-on-change. Individually enabled
pull-up/pull-down.
T0CKI
INT
ST
ST
—
—
—
External clock for Timer0.
External interrupt.
C1OUT
GP1
CMOS Comparator 1 output.
GP1/C1IN-/ICSPCLK
TTL
CMOS General purpose I/O. Individually controlled
interrupt-on-change. Individually enabled
pull-up/pull-down.
C1IN-
ICSPCLK
GP0
AN
ST
—
—
—
Comparator 1 input – negative.
Serial programming clock.
GP0/C1IN+/ICSPDAT/ULPWU
TTL
General purpose I/O. Individually controlled
interrupt-on-change. Individually enabled
pull-up/pull-down.
Selectable Ultra Low-Power Wake-up pin.
C1IN+
AN
—
Comparator 1 input – positive.
ICSPDAT TTL
CMOS Serial programming data I/O.
ULPWU
VSS
AN
D
—
—
Ultra Low-Power Wake-up input.
VSS
Ground reference for microcontroller.
Legend: AN = Analog input or output
HV = High Voltage
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
XTAL = Crystal
D = Direct
TTL = TTL compatible input
DS41232B-page 8
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
TABLE 1-2:
PIC16F636 PINOUT DESCRIPTIONS
Input Output
Name
Function
Description
Type
Type
VDD
VDD
RA5
D
—
Power supply for microcontroller.
RA5/T1CKI/OSC1/CLKIN
TTL
CMOS General purpose I/O. Individually controlled
interrupt-on-change. Individually enabled pull-up/pull-down.
T1CKI
OSC1
CLKIN
RA4
ST
XTAL
ST
—
—
—
Timer1 clock.
XTAL connection.
TOSC reference clock.
RA4/T1G/OSC2/CLKOUT
RA3/MCLR/VPP
TTL
CMOS General purpose I/O. Individually controlled
interrupt-on-change. Individually enabled pull-up/pull-down.
T1G
OSC2
CLKOUT
RA3
ST
—
—
Timer1 gate.
XTAL XTAL connection.
—
CMOS TOSC/4 reference clock.
TTL
—
—
—
General purpose input. Individually controlled
interrupt-on-change.
MCLR
ST
Master Clear Reset. Pull-up enabled when
configured as MCLR.
VPP
RC5
HV
TTL
TTL
—
Programming voltage.
RC5
CMOS General purpose I/O.
CMOS General purpose I/O.
CMOS Comparator 2 output.
CMOS General purpose I/O.
CMOS General purpose I/O.
CMOS General purpose I/O.
RC4/C2OUT
RC4
C2OUT
RC3
RC3
TTL
TTL
TTL
AN
RC2
RC2
RC1/C2IN-
RC1
C2IN-
RC0
—
Comparator 1 input – negative.
RC0/C2IN+
TTL
AN
CMOS General purpose I/O.
C2IN+
RA2
—
Comparator 1 input – positive.
RA2/T0CKI/INT/C1OUT
ST
CMOS General purpose I/O. Individually controlled
interrupt-on-change. Individually enabled pull-up/pull-down.
T0CKI
INT
ST
ST
—
—
—
External clock for Timer0.
External interrupt.
C1OUT
RA1
CMOS Comparator 1 output.
RA1/C1IN-/VREF/ICSPCLK
RA0/C1IN+/ICSPDAT/ULPWU
TTL
CMOS General purpose I/O. Individually controlled
interrupt-on-change. Individually enabled pull-up/pull-down.
C1IN-
ICSPCLK
RA0
AN
ST
—
—
—
Comparator 1 input – negative.
Serial programming clock.
TTL
General purpose I/O. Individually controlled
interrupt-on-change. Individually enabled pull-up/pull-down.
Selectable Ultra Low-Power Wake-up pin.
C1IN+
AN
—
Comparator 1 input – positive.
ICSPDAT TTL
CMOS Serial programming data I/O.
ULPWU
VSS
AN
D
—
—
Ultra Low-Power Wake-up input.
VSS
Ground reference for microcontroller.
Legend: AN = Analog input or output
HV = High Voltage
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
XTAL = Crystal
D = Direct
TTL = TTL compatible input
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 9
PIC12F635/PIC16F636/639
TABLE 1-3:
PIC16F639 PINOUT DESCRIPTIONS
Input
Type
Output
Type
Name
Function
Description
VDD
VDD
RA5
D
—
Power supply for microcontroller
RA5/T1CKI/OSC1/CLKIN
TTL
CMOS
General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up/pull-down.
T1CKI
OSC1
CLKIN
RA4
ST
XTAL
ST
—
—
Timer1 clock
XTAL connection
TOSC/4 reference clock
—
TTL
CMOS
General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up/pull-down.
RA4/T1G/OSC2/CLKOUT
RA3/MCLR/VPP
ST
—
Timer1 gate
T1G
OSC2
CLKOUT
RA3
—
—
XTAL
XTAL connection
CMOS
TOSC reference clock
TTL
General purpose input. Individually controlled interrupt-on-change.
—
Master Clear Reset. Pull-up enabled when configured as MCLR.
MCLR
VPP
ST
HV
TTL
TTL
—
—
—
Programming voltage
RC5
RC5
CMOS
CMOS
CMOS
CMOS
CMOS
General purpose I/O
RC4/C2OUT
RC4
General purpose I/O
C2OUT
RC3
Comparator2 output
RC3/LFDATA/RSSI/CCLK/SDIO
TTL
—
General purpose I/O
LFDATA
RSSI
Digital output representation of analog input signal to LC pins.
—
Current Received signal strength indicator. Analog current that is proportional
to input amplitude.
CCLK
SDIO
VDDT
—
TTL
D
—
CMOS
—
Carrier clock output
Input/Output for SPI communication
VDDT
Power supply for Analog Front-End. In this document, VDDT is treated
the same as VDD, unless otherwise stated.
LCZ
LCZ
LCY
AN
AN
AN
AN
D
—
—
—
—
—
125 kHz analog Z channel input
125 kHz analog Y channel input
125 kHz analog X channel input
Common reference for analog inputs
LCY
LCX
LCX
LCCOM
VSST
LCCOM
VSST
Ground reference for Analog Front-End. In this document, VSST is
treated the same as VSS, unless otherwise stated.
RC2
SCLK
ALERT
RC1
TTL
TTL
—
CMOS
—
General purpose I/O
RC2/SCLK/ALERT
RC1/C2IN-/CS
Digital clock input for SPI communication
Output with internal pull-up resistor for AFE error signal
General purpose I/O
OD
TTL
AN
CMOS
—
C2IN-
Comparator1 input - negative
Chip select input for SPI communication with internal pull-up resistor
TTL
—
CS
RC0
RC0/C2IN+
TTL
AN
ST
CMOS
—
General purpose I/O
C2IN+
RA2
Comparator1 input - positive
RA2/T0CKI/INT/C1OUT
CMOS
General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up/pull-down.
T0CKI
INT
ST
ST
—
—
External clock for Timer0
External Interrupt
—
C1OUT
RA1
CMOS
CMOS
Comparator1 output
RA1/C1IN-/VREF/ICSPCLK
TTL
General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up/pull-down.
C1IN-
ICSPCLK
RA0
AN
ST
—
—
—
Comparator1 input – negative
Serial Programming Clock
RA0/C1IN+/ICSPDAT/ULPWU
TTL
General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up/pull-down. Selectable Ultra Low-Power
Wake-up pin.
C1IN+
ICSPDAT
ULPWU
VSS
AN
TTL
AN
D
—
CMOS
—
Comparator1 input – positive
Serial Programming Data IO
Ultra Low-Power Wake-up input
Ground reference for microcontroller
VSS
—
Legend:
AN = Analog input or output
HV = High Voltage
TTL = TTL compatible input
CMOS = CMOS compatible input or output
D
OD
=
=
Direct
Direct
ST
= Schmitt Trigger input with CMOS levels
= Crystal
XTAL
DS41232B-page 10
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 2-1: PROGRAM MEMORY MAP AND
STACK OF THE PIC12F635
2.0
2.1
MEMORY ORGANIZATION
Program Memory Organization
PC<12:0>
CALL, RETURN
RETFIE, RETLW
The PIC12F635/PIC16F636/639 devices have a 13-bit
program counter capable of addressing an 8K x 14
program memory space. Only the first 1K x 14
(0000h-03FFh, for the PIC12F635) and 2K x 14
(0000h-07FFh, for the PIC16F636/639) is physically
implemented. Accessing a location above these
boundaries will cause a wrap around within the first
2K x 14 space. The Reset vector is at 0000h and the
interrupt vector is at 0004h (see Figure 2-1).
13
Stack Level 1
Stack Level 8
Reset Vector
0000h
2.2
Data Memory Organization
Interrupt Vector
0004h
0005h
The data memory (see Figure 2-2) is partitioned into
two banks, which contain the General Purpose
Registers (GPR) and the Special Function Registers
(SFR). The Special Function Registers are located in
the first 32 locations of each bank. Register locations
20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are GPRs,
implemented as static RAM for the PIC16F636/639.
For the PIC12F635, register locations 40h through 7Fh
are GPRs implemented as static RAM. Register
locations F0h-FFh in Bank 1 point to addresses 70h-
7Fh in Bank 0. All other RAM is unimplemented and
returns ‘0’ when read. RP0 (STATUS<5>) is the bank
select bit.
On-chip Program
Memory
03FFh
0400h
Access 0-3FFh
1FFFh
FIGURE 2-2: PROGRAM MEMORY MAP AND
STACK OF THE PIC16F636/639
PC<12:0>
TABLE 2-1:
BANK SELECTION
CALL, RETURN
RETFIE, RETLW
13
RP0
0
RP1
0
Bank
0
1
2
3
Stack Level 1
Stack Level 8
1
0
0
1
1
1
Reset Vector
0000h
0004h
0005h
Interrupt Vector
On-chip Program
Memory
07FFh
0800h
Access 0-7FFh
1FFFh
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 11
PIC12F635/PIC16F636/639
2.2.1
GENERAL PURPOSE REGISTER
The register file is organized as 64 x 8 for the
PIC12F635 and 128 x 8 for the PIC16F636/639. Each
register is accessed, either directly or indirectly,
through the File Select Register, FSR (see Section 2.4
“Indirect Addressing, INDF and FSR Registers”).
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral functions for controlling
the desired operation of the device (see Figure 2-1).
These registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
DS41232B-page 12
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 2-3:
PIC12F635 SPECIAL FUNCTION REGISTERS
File File
Address Address
Indirect addr.(1) 00h Indirect addr.(1) 80h
OPTION_REG 81h
File
Address
File
Address
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
TMR0
PCL
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
PCL
STATUS
FSR
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
STATUS
FSR
GPIO
TRISIO
Accesses
00h-0Bh
Accesses
80h-8Bh
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
TMR1L
TMR1H
T1CON
PCON
OSCCON
OSCTUNE
CRCON
CRDAT0(2)
CRDAT1(2)
CRDAT2(2)
CRDAT3(2)
LVDCON
WPUDA
IOCA
WDA
WDTCON
CMCON0
CMCON1
VRCON
EEDAT
EEADR
EECON1
EECON2(1)
3Fh
40h
General
Purpose
Register
64 Bytes
EFh
F0h
FFh
16Fh
170h
17Fh
1EFh
1F0h
1FFh
Accesses
70h-7Fh
Accesses
70h-7Fh
Accesses
Bank 0
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
®
2: CRDAT<3:0> are KEELOQ hardware peripheral related registers and require the execution of the
“KEELOQ® Encoder License Agreement” regarding implementation of the module and access to related
registers. The “KEELOQ® Encoder License Agreement” may be accessed through the Microchip web site
located at www.microchip.com/KEELOQ or by contacting your local Microchip Sales Representative.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 13
PIC12F635/PIC16F636/639
FIGURE 2-4:
PIC16F636/639 SPECIAL FUNCTION REGISTERS
File
Address
File
Address
File
Address
File
Address
Indirect addr.(1) 00h
Indirect addr. (1) 80h
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
TMR0
PCL
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
OPTION_REG 81h
PCL
STATUS
FSR
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
STATUS
FSR
PORTA
TRISA
Accesses
00h-0Bh
Accesses
80h-8Bh
PORTC
TRISC
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
TMR1L
TMR1H
T1CON
PCON
OSCCON
OSCTUNE
CRCON
CRDAT0(2)
CRDAT1(2)
CRDAT2(2)
CRDAT3(2)
LVDCON
WPUDA
IOCA
WDA
WDTCON
CMCON0
CMCON1
VRCON
EEDAT
EEADR
EECON1
EECON2(1)
General
Purpose
Register
32 Bytes
General
Purpose
Register
96 Bytes
BFh
C0h
EFh
16Fh
170h
17Fh
1EFh
1F0h
1FFh
F0h
FFh
Accesses
70h-7Fh
Accesses
70h-7Fh
Accesses
Bank 0
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
2: CRDAT<3:0> are KEELOQ hardware peripheral related registers and require the execution of the “KEELOQ
®
Encoder License Agreement” regarding implementation of the module and access to related registers. The
®
“KEELOQ Encoder License Agreement” may be accessed through the Microchip web site located at
www.microchip.com/KEELOQ or by contacting your local Microchip Sales Representative.
DS41232B-page 14
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
TABLE 2-2:
PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Value on
Value on
Addr Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR/BOD/ all other
(1)
WUR
Resets
Bank 0
00h INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
01h TMR0
02h PCL
Timer0 Module Register
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--xx xx00 --uu uu00
Program Counter’s (PC) Least Significant Byte
03h STATUS
04h FSR
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
05h GPIO
—
—
GP5
GP4
GP3
GP2
GP1
GP0
06h
07h
08h
09h
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
0Ah PCLATH
0Bh INTCON
0Ch PIR1
—
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000 ---0 0000
0000 0000 0000 0000
(2)
GIE
EEIF
PEIE
LVDIF
T0IE
CRIF
INTE
—
RAIE
C1IF
T0IF
INTF
—
RAIF
OSFIF
TMR1IF 000- 00-0 000- 00-0
0Dh
0Eh TMR1L
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1
10h T1CON
—
Unimplemented
—
—
Holding Register for the Least Significant Byte of the 16-bit TMR1
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
11h
12h
13h
14h
15h
16h
17h
—
—
—
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
18h WDTCON
19h CMCON0
1Ah CMCON1
—
—
—
—
C1OUT
—
—
—
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000
C1INV
—
CIS
—
CM2
—
CM1
CM0
-0-0 0000 -0-0 0000
T1GSS CMSYNC ---- --10 ---- --10
1Bh
—
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
1Ch
1Dh
1Eh
1Fh
Legend:
— = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,
shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set
again if the mismatch exists.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 15
PIC12F635/PIC16F636/639
TABLE 2-3:
PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Value on
Value on
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR/BOD/ all other
(1)
WUR
Resets
Bank 1
80h INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
81h OPTION_REG RAPU INTEDG
T0CS
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO PD
Indirect Data Memory Address Pointer
T0SE
PSA
PS2
PS1
PS0
C
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
82h PCL
83h STATUS
84h FSR
Z
DC
85h TRISIO
—
—
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
86h
87h
88h
89h
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
8Ah PCLATH
8Bh INTCON
8Ch PIE1
—
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000 ---0 0000
0000 0000 0000 0000
(3)
GIE
EEIE
PEIE
LVDIE
T0IE
CRIE
INTE
—
RAIE
C1IE
T0IF
INTF
—
RAIF
OSFIE
TMR1IE 000- 00-0 000- 00-0
8Dh
—
Unimplemented
—
—
8Eh PCON
—
—
—
—
IRCF2
—
ULPWUE SBODEN WUR
—
POR
LTS
BOD
SCS
--01 q-qq --0u u-uu
-110 q000 -110 x000
8Fh OSCCON
90h OSCTUNE
IRCF1
—
IRCF0
TUN4
OSTS
TUN3
HTS
TUN2
TUN1
TUN0 ---0 0000 ---u uuuu
91h
92h
93h
—
—
—
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
94h LVDCON
—
—
—
—
—
—
—
—
IRVST
LVDEN
—
—
LVDL2
LVDL1
LVDL0 --00 -000 --00 -000
(2)
95h WPUDA
96h IOCA
WPUDA5 WPUDA4
WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111
IOCA5
WDA5
IOCA4
WDA4
IOCA3
—
IOCA2
WDA2
IOCA1
WDA1
IOCA0 --00 0000 --00 0000
WDA0 --11 -111 --11 -111
(2)
97h WDA
9Bh
—
Unimplemented
VREN
—
—
99h VRCON
9Ah EEDAT
9Bh EEADR
9Ch EECON1
9Dh EECON2
—
VRR
—
VR3
VR2
VR1
VR0
0-0- 0000 0-0- 0000
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000
EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000
—
—
—
—
WRERR WREN
WR
RD
---- x000 ---- q000
---- ---- ---- ----
EEPROM Control Register 2 (not a physical register)
Unimplemented
9Eh
—
—
—
—
—
—
9Fh
Unimplemented
Legend:
— = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,
shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: GP3 pull-up is enabled when pin is configured as MCLR in the Configuration Word register.
3: MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset, but will set
again if the mismatch exists.
DS41232B-page 16
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
TABLE 2-4:
PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Value on
Value on
Addr Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR/BOD/ all other
(1)
WUR
Resets
Bank 0
00h INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
01h TMR0
02h PCL
Timer0 Module Register
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuxx
--xx xx00 --uu uu00
Program Counter’s (PC) Least Significant Byte
03h STATUS
04h FSR
IRP
RP1
RP0
TO
PD
Z
DC
RA1
RC1
C
Indirect Data Memory Address Pointer
05h PORTA
—
—
RA5
RC5
RA4
RC4
RA3
RC3
RA2
RC2
RA0
RC0
06h
—
Unimplemented
—
—
07h PORTC
—
—
--xx xx00 --uu uu00
08h
09h
—
—
Unimplemented
Unimplemented
—
—
—
—
0Ah PCLATH
0Bh INTCON
0Ch PIR1
—
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000 ---0 0000
0000 0000 0000 0000
(2)
GIE
EEIF
PEIE
LVDIF
T0IE
CRIF
INTE
C2IF
RAIE
C1IF
T0IF
INTF
—
RAIF
OSFIF
TMR1IF 0000 00-0 0000 00-0
0Dh
0Eh TMR1L
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1
10h T1CON
—
Unimplemented
—
—
Holding Register for the Least Significant Byte of the 16-bit TMR1
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
11h
12h
13h
14h
15h
16h
17h
—
—
—
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
18h WDTCON
19h CMCON0 C2OUT C1OUT
1Ah CMCON1
—
—
—
C2INV
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000
C1INV
—
CIS
—
CM2
—
CM1
CM0
0000 0000 0000 0000
—
—
T1GSS C2SYNC ---- --10 ---- --10
1Bh
—
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
1Ch
1Dh
1Eh
1Fh
Legend:
— = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,
shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set
again if the mismatch exists.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 17
PIC12F635/PIC16F636/639
TABLE 2-5:
PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Value on
Value on
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR/BOD/ all other
(1)
WUR
Resets
Bank 1
80h INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
81h OPTION_REG RAPU INTEDG
T0CS
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO PD
Indirect Data Memory Address Pointer
T0SE
PSA
PS2
PS1
PS0
C
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
82h PCL
83h STATUS
84h FSR
Z
DC
85h TRISA
—
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
86h
—
Unimplemented
—
—
87h TRISC
—
—
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111
88h
89h
—
Unimplemented
Unimplemented
—
—
—
—
—
8Ah PCLATH
8Bh INTCON
8Ch PIE1
—
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000 ---0 0000
0000 0000 0000 0000
(3)
GIE
EEIE
PEIE
LVDIE
T0IE
CRIE
INTE
C2IE
RAIE
C1IE
T0IF
INTF
—
RAIF
OSFIE
TMR1IE 0000 00-0 0000 00-0
8Dh
—
Unimplemented
—
—
8Eh PCON
—
—
—
—
IRCF2
—
ULPWUE SBODEN WUR
—
POR
LTS
BOD
SCS
--01 q-qq --0u u-uu
-110 q000 -110 x000
8Fh OSCCON
90h OSCTUNE
IRCF1
—
IRCF0
TUN4
OSTS
TUN3
HTS
TUN2
TUN1
TUN0 ---0 0000 ---u uuuu
91h
92h
93h
—
—
—
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
94h LVDCON
—
—
—
—
—
—
—
—
IRVST
LVDEN
—
—
LVDL2
LVDL1
LVDL0 --00 -000 --00 -000
(2)
95h WPUDA
96h IOCA
WPUDA5 WPUDA4
WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111
IOCA5
WDA5
IOCA4
WDA4
IOCA3
—
IOCA2
WDA2
IOCA1
WDA1
IOCA0 --00 0000 --00 0000
WDA0 --11 -111 --11 -111
(2)
97h WDA
9Bh
—
Unimplemented
VREN
—
—
99h VRCON
9Ah EEDAT
9Bh EEADR
9Ch EECON1
9Dh EECON2
—
VRR
—
VR3
VR2
VR1
VR0
0-0- 0000 0-0- 0000
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000
EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000
—
—
—
—
WRERR WREN
WR
RD
---- x000 ---- q000
---- ---- ---- ----
EEPROM Control Register 2 (not a physical register)
Unimplemented
9Eh
—
—
—
—
—
—
9Fh
Unimplemented
Legend:
— = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,
shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: RA3 pull-up is enabled when pin is configured as MCLR in the Configuration Word register.
3: MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set
again if the mismatch exists.
DS41232B-page 18
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
TABLE 2-6:
PIC12F635/PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Value on
POR/BOD/
WUR
Value on
all other
Resets
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
Bank 2
10Ch
10Dh
10Eh
10Fh
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
GO/DONE ENC/DEC
—
—
—
—
—
—
—
—
110h CRCON
111h CRDAT0
112h CRDAT1
113h CRDAT2
114h CRDAT3
—
—
—
—
CRREG1 CRREG0 00-- --00 00-- --00
0000 0000 0000 0000
(2)
(2)
(2)
(2)
Cryptographic Data Register 0
Cryptographic Data Register 1
Cryptographic Data Register 2
Cryptographic Data Register 3
Unimplemented
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
115h
—
—
—
—
—
—
116h
Unimplemented
Legend:
— = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,
shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2:
CRDAT<3:0> are KEELOQ® hardware peripheral related registers and require the execution of the “KEELOQ Encoder License Agreement”
regarding implementation of the module and access to related registers. The “KEELOQ Encoder License Agreement” may be accessed
through the Microchip web site located at www.microchip.com/KEELOQ or by contacting your local Microchip Sales Representative.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 19
PIC12F635/PIC16F636/639
For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the Status register as
000u u1uu(where u= unchanged).
2.2.2.1
Status Register
The Status register, shown in Register 2-1, contains:
• the arithmetic status of the ALU
• the Reset status
It is recommended, therefore, that only BCF, BSF, SWAPF
and MOVWF instructions are used to alter the Status
register, because these instructions do not affect any
Status bits. For other instructions not affecting any Status
bits, see Section 13.0 “Instruction Set Summary”.
• the bank select bits for data memory (SRAM)
The Status register can be the destination for any
instruction, like any other register. If the Status register is
the destination for an instruction that affects the Z, DC or
C bits, then the write to these three bits is disabled.
These bits are set or cleared according to the device
logic. Furthermore, the TO and PD bits are not writable.
Therefore, the result of an instruction with the Status
register as destination may be different than intended.
Note 1: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1:
STATUS – STATUS REGISTER (ADDRESS: 03h OR 83h)
R/W-0
IRP
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 7
bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1= Bank 2, 3 (100h-1FFh)
0= Bank 0, 1 (00h-FFh)
bit 6-5
RP<1:0>: Register Bank Select bits (used for direct addressing)
11= Bank 3 (180h-1FFh)
10= Bank 2 (100h-17Fh)
01= Bank 1 (80h-FFh)
00= Bank 0 (00h-7Fh)
Each bank is 128 bytes.
bit 4
bit 3
bit 2
bit 1
TO: Time-out bit
1= After power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWFinstructions)
For Borrow, the polarity is reversed.
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note:
For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high-order or low-order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS41232B-page 20
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
2.2.2.2
Option Register
Note:
To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT by
The Option register is a readable and writable register
which contains various control bits to configure:
setting
the
PSA
bit
to
‘1’
• TMR0/WDT prescaler
• External RA2/INT interrupt
• TMR0
(OPTION_REG<3>). See Section 5.4
“Prescaler”.
• Weak pull-up/pull-downs on PORTA
REGISTER 2-2:
OPTION_REG – OPTION REGISTER (ADDRESS: 81h)
R/W-1
RAPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
RAPU: PORTA Pull-up/Pull-down Enable bit
1= PORTA pull-ups/pull-downs are disabled
0= PORTA pull-ups/pull-downs are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RA2/INT pin
0= Interrupt on falling edge of RA2/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on RA2/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on RA2/T0CKI pin
0= Increment on low-to-high transition on RA2/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
‘1’ = Bit is set
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 21
PIC12F635/PIC16F636/639
2.2.2.3
INTCON Register
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
The INTCON register is a readable and writable
register which contains the various enable and flag bits
for TMR0 register overflow, PORTA change and
external RA2/INT pin interrupts.
REGISTER 2-3:
INTCON – INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RAIE(1)
R/W-0
T0IF(2)
R/W-0
INTF
R/W-0
RAIF(3)
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
GIE: Global Interrupt Enable bit
1= Enables all unmasked interrupts
0= Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
INTE: RA2/INT External Interrupt Enable bit
1= Enables the RA2/INT external interrupt
0= Disables the RA2/INT external interrupt
RAIE: PORTA Change Interrupt Enable bit(1)
1= Enables the PORTA change interrupt
0= Disables the PORTA change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit(2)
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: RA2/INT External Interrupt Flag bit
1= The RA2/INT external interrupt occurred (must be cleared in software)
0= The RA2/INT external interrupt did not occur
RAIF: PORTA Change Interrupt Flag bit(3)
1= When at least one of the PORTA <5:0> pins changed state (must be cleared in software)
0= None of the PORTA <5:0> pins have changed state
Note 1: IOCA register must also be enabled.
2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should
be initialized before clearing the T0IF bit.
3: MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will
be cleared upon Reset but will set again if the mismatch exists.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS41232B-page 22
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
2.2.2.4
PIE1 Register
The PIE1 register contains the interrupt enable bits, as
shown in Register 2-4.
Note:
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
REGISTER 2-4:
PIE1 — PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
R/W-0
EEIE
R/W-0
LVDIE
R/W-0
CRIE
R/W-0
C2IE(1)
R/W-0
C1IE
R/W-0
OSFIE
U-0
—
R/W-0
TMR1IE
bit 0
bit 7
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
EEIE: EE Write Complete Interrupt Enable bit
1= Enables the EE write complete interrupt
0= Disables the EE write complete interrupt
LVDIE: Low-Voltage Detect Interrupt Enable bit
1= Enables the LVD interrupt
0= Disables the LVD interrupt
CRIE: Cryptographic Interrupt Enable bit
1= Enables the cryptographic interrupt
0= Disables the cryptographic interrupt
C2IE: Comparator 2 Interrupt Enable bit(1)
1= Enables the Comparator 2 interrupt
0= Disables the Comparator 2 interrupt
C1IE: Comparator 1 Interrupt Enable bit
1= Enables the Comparator 1 interrupt
0= Disables the Comparator 1 interrupt
OSFIE: Oscillator Fail Interrupt Enable bit
1= Enables the oscillator fail interrupt
0= Disables the oscillator fail interrupt
bit 1
bit 0
Unimplemented: Read as ‘0’
TMR1IE: Timer1 Interrupt Enable bit
1= Enables the Timer1 interrupt
0= Disables the Timer1 interrupt
Note 1: PIC16F636/639 only.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 23
PIC12F635/PIC16F636/639
2.2.2.5
PIR1 Register
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-5.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
REGISTER 2-5:
PIR1 – PERIPHERAL INTERRUPT REQUEST REGISTER 1 (ADDRESS: 0Ch)
R/W-0
EEIF
R/W-0
LVDIF
R/W-0
CRIF
R/W-0
C2IF(1)
R/W-0
C1IF
R/W-0
OSFIF
U-0
—
R/W-0
TMR1IF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
EEIF: EEPROM Write Operation Interrupt Flag bit
1= The write operation completed (must be cleared in software)
0= The write operation has not completed or has not been started
LVDIF: Low-Voltage Detect Interrupt Flag bit
1= The supply voltage has crossed selected LVD voltage (must be cleared in software)
0= The supply voltage has not crossed selected LVD voltage
CRIF: Cryptographic Interrupt Flag bit
1= The Cryptographic module has completed an operation (must be cleared in software)
0= The Cryptographic module has not completed an operation or is Idle
C2IF: Comparator 2 Interrupt Flag bit(1)
1= Comparator output (C2OUT bit) has changed (must be cleared in software)
0= Comparator output (C2OUT bit) has not changed
C1IF: Comparator 1 Interrupt Flag bit
1= Comparator output (C1OUT bit) has changed (must be cleared in software)
0= Comparator output (C1OUT bit) has not changed
OSFIF: Oscillator Fail Interrupt Flag bit
1= System oscillator failed, clock input has changed INTOSC (must be cleared in software)
0= System clock operating
bit 1
bit 0
Unimplemented: Read as ‘0’
TMR1IF: Timer1 Interrupt Flag bit
1= Timer1 rolled over (must be cleared in software)
0= Timer1 has not rolled over
Note 1: PIC16F636/639 only.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS41232B-page 24
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
The PCON register also controls the Ultra Low-Power
Wake-up and software enable of the BOD.
2.2.2.6
PCON Register
The Power Control (PCON) register (see Table 12-3)
contains flag bits to differentiate between a:
The PCON register bits are shown in Register 2-6.
• Power-on Reset (POR)
• Wake-up Reset (WUR)
• Brown-out Detect (BOD)
• Watchdog Timer Reset (WDT)
• External MCLR Reset
REGISTER 2-6:
PCON – POWER CONTROL REGISTER (ADDRESS: 8Eh)
U-0
—
U-0
—
R/W-0
ULPWUE SBODEN(1)
R/W-1
R/W-x
WUR
U-0
—
R/W-0
POR
R/W-x
BOD
bit 7
bit 0
bit 7-6
bit 5
Unimplemented: Read as ‘0’
ULPWUE: Ultra Low-Power Wake-up Enable bit
1= Ultra Low-Power Wake-up enabled
0= Ultra Low-Power Wake-up disabled
bit 4
bit 3
SBODEN: Software BOD Enable bit(1)
1= BOD enabled
0= BOD disabled
WUR: Wake-up Reset Status bit
1= No Wake-up Reset occurred
0= A Wake-up Reset occurred (must be set in software after a Power-on Reset occurs)
bit 2
bit 1
Unimplemented: Read as ‘0’
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOD: Brown-out Detect Status bit
1= No Brown-out Detect occurred
0= A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs)
Note 1: BODEN<1:0> = 01in the Configuration Word register for SBODEN to control the
Brown-out Detect module.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 25
PIC12F635/PIC16F636/639
2.3.1
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL). When
performing a table read using a computed GOTO
method, care should be exercised if the table location
crosses a PCL memory boundary (each 256-byte
block). Refer to the Application Note AN556,
“Implementing a Table Read” (DS00556).
COMPUTED GOTO
2.3
PCL and PCLATH
The Program Counter (PC) is 13 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.
On any Reset, the PC is cleared. Figure 2-5 shows the
two situations for the loading of the PC. The upper
example in Figure 2-5 shows how the PC is loaded on a
write to PCL (PCLATH<4:0> → PCH). The lower
example in Figure 2-5 shows how the PC is loaded
during a CALL or GOTO instruction (PCLATH<4:3> →
PCH).
2.3.2
STACK
The PIC12F635/PIC16F636/639 family has an 8-
level x 13-bit wide hardware stack (see Figure 2-1).
The stack space is not part of either program or data
space and the Stack Pointer is not readable or writable.
The PC is PUSHed onto the stack when a CALL
instruction is executed or an interrupt causes a branch.
The stack is POPed in the event of a RETURN, RETLW
or a RETFIE instruction execution. PCLATH is not
affected by a PUSH or POP operation.
FIGURE 2-5:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
Instruction with
12
8
7
0
PCL as
Destination
PC
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
8
PCLATH<4:0>
PCLATH
5
ALU Result
PCH
12 11 10
PC
PCL
Note 1: There are no Status bits to indicate stack
overflow or stack underflow conditions.
8
7
0
GOTO, CALL
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLWand RETFIEinstructions
or the vectoring to an interrupt address.
PCLATH<4:3>
PCLATH
11
2
Opcode<10:0>
DS41232B-page 26
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 2-1.
2.4
Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
EXAMPLE 2-1:
INDIRECT ADDRESSING
MOVLW 0x20
MOVWF FSR
CLRF INDF
INCF FSR
;initialize pointer
;to RAM
;clear INDF register
;INC POINTER
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR and the IRP bit
(STATUS<7>), as shown in Figure 2-6.
NEXT
BTFSS FSR,4 ;all done?
GOTO
NEXT
;no clear next
;yes continue
CONTINUE
FIGURE 2-6:
DIRECT/INDIRECT ADDRESSING PIC12F635/PIC16F636/639
Direct Addressing
From Opcode
Indirect Addressing
7
6
0
0
IRP
File Select Register
RP1 RP0
Bank Select
180h
Location Select
Bank Select
Location Select
00h
00
01
10
11
Data
Memory
7Fh
1FFh
Bank 0
Bank 1
Bank 2
Bank 3
Note: For memory map detail, see Figure 2-2.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 27
PIC12F635/PIC16F636/639
NOTES:
DS41232B-page 28
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
The PIC12F635/PIC16F636/639 can be configured in
one of eight clock modes.
3.0
3.1
CLOCK SOURCES
Overview
1. EC – External clock with I/O on RA4.
2. LP – Low gain crystal or Ceramic Resonator
The PIC12F635/PIC16F636/639 has a wide variety of
clock sources and selection features to allow it to be
used in a wide range of applications, while maximizing
performance and minimizing power consumption.
Oscillator mode.
3. XT – Medium gain crystal or Ceramic Resonator
Oscillator mode.
4. HS – High gain crystal or Ceramic Resonator
mode.
Figure 3-1 illustrates
PIC12F635/PIC16F636/639 clock sources.
a
block diagram of the
5. RC – External Resistor-Capacitor (RC) with
FOSC/4 output on RA4.
Clock sources can be configured from external oscillators,
quartz crystal resonators, ceramic resonators and
Resistor-Capacitor (RC) circuits. In addition, the system
clock source can be configured from one of two internal
oscillators, with a choice of speeds selectable via
software. Additional clock features include:
6. RCIO – External Resistor-Capacitor (RC) with I/O
on RA4.
7. INTOSC – Internal oscillator with FOSC/4 output
on RA4 and I/O on RA5.
8. INTOSCIO – Internal oscillator with I/O on RA4
and RA5.
• Selectable system clock source between external
or internal via software.
• Two-Speed Clock Start-up mode, which
minimizes latency between external oscillator
start-up and code execution.
• Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch to the
internal oscillator.
Clock source modes are configured by the FOSC<2:0>
bits in the Configuration Word register (see
Section 12.0 “Special Features of the CPU”). The
internal clock can be generated by two oscillators. The
HFINTOSC is a high-frequency calibrated oscillator. The
LFINTOSC is a low-frequency uncalibrated oscillator.
FIGURE 3-1:
PIC12F635/PIC16F636/639 CLOCK SOURCE BLOCK DIAGRAM
FOSC<2:0>
(Configuration Word)
External Oscillator
SCS
(OSCCON<0>)
OSC2
OSC1
Sleep
LP, XT, HS, RC, RCIO, EC
IRCF<2:0>
(OSCCON<6:4>)
System Clock
(CPU and Peripherals)
8 MHz
111
110
101
Internal Oscillator
4 MHz
2 MHz
1 MHz
HFINTOSC(1)
8 MHz
100
011
010
001
000
500 kHz
250 kHz
125 kHz
31 kHz
LFINTOSC(2)
31 kHz
Power-up Timer (PWRT)
Watchdog Timer (WDT)
Fail-Safe Clock Monitor (FSCM)
Note 1: HFINTOSC = High-Frequency Calibrated Internal Oscillator.
2: LFINTOSC = Low-Frequency Internal Oscillator is not calibrated.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 29
PIC12F635/PIC16F636/639
3.2
Clock Source Modes
3.3
External Clock Modes
Clock source modes can be classified as external or
internal.
3.3.1
OSCILLATOR START-UP TIMER (OST)
If the PIC12F635/PIC16F636/639 is configured for LP,
XT or HS modes, the Oscillator Start-up Timer (OST)
counts 1024 oscillations from the OSC1 pin following a
Power-on Reset (POR) and the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and
is providing a stable system clock to the PIC12F635/
PIC16F636/639.
External clock modes rely on external circuitry for the
clock source. Examples are oscillator modules (EC
mode), quartz crystal resonators or ceramic resonators
(LP, XT and HS modes) and Resistor-Capacitor (RC
mode) circuits.
Internal clock sources are contained internally within
PIC12F635/PIC16F636/639. The device has two inter-
nal oscillators: the 8 MHz High-Frequency Internal
Oscillator (HFINTOSC) and 31 kHz Low-Frequency
Internal Oscillator (LFINTOSC).
The system clock can be selected between external or
internal clock sources via the System Clock Selection
(SCS) bit (see Section 3.5 “Clock Switching”).
When switching between clock sources, a delay is
required to allow the new clock to stabilize. Table 3-1
shows oscillator delay examples.
In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Clock Start-
up mode can be selected (see Section 3.6 “Two-Speed
Clock Start-up Mode”).
TABLE 3-1:
OSCILLATOR DELAY EXAMPLES
Switch From
Switch To
Frequency
Oscillator Delay
LFINTOSC
HFINTOSC
31 kHz
125 kHz-8 MHz
Sleep/POR
5 μs-10 μs (approx.)
Sleep/POR
LFINTOSC (31 kHz)
Sleep/POR
EC, RC
EC, RC
DC – 20 MHz
DC – 20 MHz
31 kHz-20 MHz
125 kHz-8 MHz
CPU Start-up
LP, XT, HS
HFINTOSC
1024 Clock Cycles (OST)
LFINTOSC (31 kHz)
1 μs (approx.)
DS41232B-page 30
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
3.3.2
EC MODE
FIGURE 3-3:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
The External Clock (EC) mode allows an externally
generated logic level as the system clock source.
When operating in this mode, an external clock source
is connected to the OSC1 pin and the RA5 pin is
available for general purpose I/O. Figure 3-2 shows the
pin connections for EC mode.
PIC12F635/PIC16F636/639
OSC1
To Internal
Logic
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC12F635/PIC16F636/639
design is fully static, stopping the external clock input
will have the effect of halting the device while leaving all
data intact. Upon restarting the external clock, the
device will resume operation as if no time had elapsed.
C1
Quartz
Crystal
(2)
RF
Sleep
OSC2
(1)
RS
C2
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level.
2: The value of RF varies with the Oscillator
mode selected (typically between 2 MΩ to
10 MΩ).
FIGURE 3-2:
EXTERNAL CLOCK (EC)
MODE OPERATION
OSC1/CLKIN
Clock from
Note 1: Quartz
crystal
characteristics
vary
Ext. System
PIC12F635/PIC16F636/639
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
I/O (OSC2)
RA4
3.3.3
LP, XT, HS MODES
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
the OSC1 and OSC2 pins (Figure 3-1). The mode
selects a low, medium or high gain setting of the
internal inverter-amplifier to support various resonator
types and speed.
FIGURE 3-4:
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
LP Oscillator mode selects the lowest gain setting of
the internal inverter-amplifier. LP mode current
consumption is the least of the three modes. This mode
is best suited to drive resonators with a low drive level
specification, for example, tuning fork type crystals.
PIC12F635/PIC16F636/639
OSC1
To Internal
Logic
C1
C2
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is better suited to drive resonators with a
medium drive level specification, for example, low-
frequency AT-cut quartz crystal resonators.
(3)
(2)
Sleep
RP
RF
OSC2
(1)
RS
Ceramic
Resonator
HS Oscillator mode selects the highest gain setting of
the internal inverter-amplifier. HS mode current
consumption is the highest of the three modes. This
mode is better suited for resonators that require a high
drive setting, for example, high-frequency AT-cut
quartz crystal resonators or ceramic resonators.
Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator
mode selected (typically between 2 MΩ to
10 MΩ).
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation (typical value 1 MΩ).
Figure 3-3 and Figure 3-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 31
PIC12F635/PIC16F636/639
3.3.4
EXTERNAL RC MODES
3.4
Internal Clock Modes
The External Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required. There are two modes, RC and RCIO.
The PIC12F635/PIC16F636/639 has two independent,
internal oscillators that can be configured or selected
as the system clock source.
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
8 MHz. The frequency of the HFINTOSC can be
user adjusted ±12% via software using the
OSCTUNE register (Register 3-1).
In RC mode, the RC circuit connects to the OSC1 pin.
The OSC2/CLKOUT pin outputs the RC oscillator
frequency divided by 4. This signal may be used to
provide a clock for external circuitry, synchronization,
calibration, test or other application requirements.
Figure 3-5 shows the RC mode connections.
2. The LFINTOSC (Low-Frequency Internal
Oscillator) is uncalibrated and operates at
approximately 31 kHz.
The system clock speed can be selected via software
using the Internal Oscillator Frequency Select (IRCF)
bits.
FIGURE 3-5:
RC MODE
VDD
The system clock can be selected between external or
internal clock sources via the System Clock Selection
(SCS) bit (see Section 3.5 “Clock Switching”).
REXT
Internal
Clock
OSC1
CEXT
VSS
3.4.1
LFINTOSC AND LFINTOSCIO
MODES
PIC12F635/PIC16F636/639
OSC2/CLKOUT
The LFINTOSC and LFINTOSCIO modes configure
the internal oscillators as the system clock source
when the device is programmed using the oscillator
selection (FOSC) bits in the Configuration Word
register (Register 12-1).
FOSC/4
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
In RCIO mode, the RC circuit is connected to the OSC1
pin. The OSC2 pin becomes an additional general
purpose I/O pin. The I/O pin becomes bit 4 of PORTA
(RA4). Figure 3-6 shows the RCIO mode connections.
In LFINTOSC mode, the OSC1 pin is available for
general purpose I/O. The OSC2/CLKOUT pin outputs
the selected internal oscillator frequency divided by 4.
The CLKOUT signal may be used to provide a clock for
external circuitry, synchronization, calibration, test or
other application requirements.
FIGURE 3-6:
RCIO MODE
VDD
In LFINTOSCIO mode, the OSC1 and OSC2 pins are
REXT
available for general purpose I/O.
Internal
Clock
OSC1
3.4.2
HFINTOSC
CEXT
The High-Frequency Internal Oscillator (HFINTOSC) is
a factory calibrated 8 MHz internal clock source. The
frequency of the HFINTOSC can be altered
approximately ±12% via software using the OSCTUNE
register (Register 3-1).
PIC12F635/PIC16F636/639
I/O (OSC2)
VSS
RA4
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 3-1). One of seven
frequencies can be selected via software using the
IRCF bits (see Section 3.4.4 “Frequency Select Bits
(IRCF)”).
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT)
values and the operating temperature. In addition to
this, the oscillator frequency will vary from unit to unit
due to normal threshold voltage. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency or for low
CEXT values. The user also needs to take into account
variation due to tolerance of external RC components
used.
The HFINTOSC is enabled by selecting any frequency
between 8 MHz and 125 kHz (IRCF ≠ 000) as the
system clock source (SCS = 1), or when Two-Speed
Start-up is enabled (IESO = 1and IRCF ≠ 000).
The HF Internal Oscillator (HTS) bit (OSCCON<2>)
indicates whether the HFINTOSC is stable or not.
DS41232B-page 32
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
When the OSCTUNE register is modified, the
HFINTOSC frequency will begin shifting to the new
frequency. The HFINTOSC clock will stabilize within
1 ms. Code execution continues during this shift. There
is no indication that the shift has occurred.
3.4.2.1
OSCTUNE Register
The HFINTOSC is factory calibrated but can be
adjusted in software by writing to the OSCTUNE
register (Register 3-1).
The OSCTUNE register has a tuning range of
approximately ±12%. The default value of the
OSCTUNE register is ‘0’. The value is a 5-bit two’s
complement number. Due to process variation, the
monotonicity and frequency step cannot be specified.
OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
Monitor (FSCM) and peripherals, are not affected by
the change in frequency.
REGISTER 3-1:
OSCTUNE – OSCILLATOR TUNING REGISTER (ADDRESS: 90h)
U-0
—
U-0
—
U-0
—
R/W-0
TUN4
R/W-0
TUN3
R/W-0
TUN2
R/W-0
TUN1
R/W-0
TUN0
bit 7
bit 0
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
TUN<4:0>: Frequency Tuning bits
01111= Maximum frequency
01110=
•
•
•
00001=
00000= Oscillator module is running at the calibrated frequency.
11111=
•
•
•
10000= Minimum frequency
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 33
PIC12F635/PIC16F636/639
3.4.3
LFINTOSC
3.4.5
HFINTOSC AND LFINTOSC CLOCK
SWITCH TIMING
The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated (approximate) 31 kHz internal clock
source.
When switching between the LFINTOSC and the
HFINTOSC, the new oscillator may already be shut
down to save power. If this is the case, there is a 10 μs
delay after the IRCF bits are modified before the
frequency selection takes place. The LTS/HTS bits will
reflect the current active status of the LFINTOSC and
the HFINTOSC oscillators. The timing of a frequency
selection is as follows:
The output of the LFINTOSC connects to a postscaler
and multiplexer (see Figure 3-1). 31 kHz can be
selected via software using the IRCF bits (see
Section 3.4.4 “Frequency Select Bits (IRCF)”). The
LFINTOSC is also the clock source for the Power-up
Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe
Clock Monitor (FSCM).
1. IRCF bits are modified.
2. If the new clock is shut down, a 10 μs clock start-
The LFINTOSC is enabled by selecting 31 kHz
(IRCF = 000) as the system clock source (SCS = 1), or
when any of the following are enabled:
up delay is started.
3. Clock switch circuitry waits for a falling edge of
the current clock.
• Two-Speed Start-up (IESO = 1and IRCF = 000)
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
4. CLKOUT is held low and the clock switch
circuitry waits for a rising edge in the new clock.
5. CLKOUT is now connected with the new clock.
HTS/LTS bits are updated as required.
• Fail-Safe Clock Monitor (FSCM)
The LF Internal Oscillator (LTS) bit (OSCCON<1>)
indicates whether the LFINTOSC is stable or not.
6. Clock switch is complete.
If the internal oscillator speed selected is between
8 MHz and 125 kHz, there is no start-up delay before
the new frequency is selected. This is because the old
and the new frequencies are derived from the
HFINTOSC via the postscaler and multiplexer.
3.4.4
FREQUENCY SELECT BITS (IRCF)
The output of the 8 MHz HFINTOSC and 31 kHz
LFINTOSC connects to a postscaler and multiplexer
(see Figure 3-1). The Internal Oscillator Frequency
Select bits, IRCF<2:0> (OSCCON<6:4>), select the
frequency output of the internal oscillators. One of eight
frequencies can be selected via software:
Note:
Care must be taken to ensure a valid
voltage or frequency selection is chosen.
See voltage vs. frequency diagrams
(Figure 15-2, Figure 15-3 and Figure 15-4)
for more detail.
• 8 MHz
• 4 MHz (Default after Reset)
• 2 MHz
• 1 MHz
• 500 kHz
• 250 kHz
• 125 kHz
• 31 kHz
Note:
Following any Reset, the IRCF bits are set
to ‘110’ and the frequency selection is set
to 4 MHz. The user can modify the IRCF
bits to select a different frequency.
DS41232B-page 34
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
When the PIC12F635/PIC16F636/639 is configured for
LP, XT or HS modes, the Oscillator Start-up Timer
3.5
Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bit.
(OST) is enabled (see Section 3.3.1 “Oscillator Start-
up Timer (OST)”). The OST timer will suspend
program execution until 1024 oscillations are counted.
Two-Speed Start-up mode minimizes the delay in code
execution by operating from the internal oscillator as
the OST is counting. When the OST count reaches
1024 and the OSTS bit (OSCCON<3>) is set, program
execution switches to the external oscillator.
3.5.1
SYSTEM CLOCK SELECT (SCS) BIT
The System Clock Select (SCS) bit (OSCCON<0>)
selects the system clock source that is used for the
CPU and peripherals.
When SCS = 0, the system clock source is determined
by configuration of the FOSC<2:0> bits in the
Configuration Word register (Register 12-1).
3.6.1
TWO-SPEED START-UP MODE
CONFIGURATION
Two-Speed Start-up mode is configured by the
following settings:
When SCS = 1, the system clock source is chosen by
the internal oscillator frequency selected by the IRCF
bits. After a Reset, SCS is always cleared.
• IESO = 1(CONFIG<10>) Internal/External
Switchover bit.
• SCS = 0.
• FOSC configured for LP, XT or HS mode.
• Two-Speed Start-up mode is entered after:
• Power-on Reset (POR) and, if enabled, after
PWRT has expired, or
Note:
Any automatic clock switch, which may
occur from Two-Speed Start-up or Fail-
Safe Clock Monitor, does not update the
SCS bit. The user can monitor the OSTS
(OSCCON<3>) to determine the current
system clock source.
• Wake-up from Sleep.
3.5.2
OSCILLATOR START-UP TIME-OUT
STATUS BIT
If the external clock oscillator is configured to be
anything other than LP, XT or HS mode, then Two-
Speed Start-up is disabled. This is because the external
clock oscillator does not require any stabilization time
after POR or an exit from Sleep.
The Oscillator Start-up Time-out Status (OSTS) bit
(OSCCON<3>) indicates whether the system clock is
running from the external clock source, as defined by
the FOSC bits, or from the internal clock source. In
particular, OSTS indicates that the Oscillator Start-up
Timer (OST) has timed out for LP, XT or HS modes.
3.6.2
TWO-SPEED START-UP
SEQUENCE
The Two-Speed Start-up sequence is listed below.
1. Wake-up from Power-on Reset or Sleep.
3.6
Two-Speed Clock Start-up Mode
2. Instructions begin execution by the internal
oscillator at the frequency set in the IRCF bits
(OSCCON<6:4>).
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up time
from the time spent awake and can reduce the overall
power consumption of the device.
3. OST enabled to count 1024 clock cycles.
4. OST timed out, wait for falling edge of the
internal oscillator.
5. OSTS is set.
This mode allows the application to wake-up from
Sleep, perform a few instructions using the INTOSC as
the clock source and go back to Sleep without waiting
for the primary oscillator to become stable.
6. System clock held low until the next falling edge
of new clock (LP, XT or HS mode).
7. System clock is switched to external clock
source.
Note:
Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit (OSCCON<3>) to remain
clear.
3.6.3
CHECKING EXTERNAL/INTERNAL
CLOCK STATUS
Checking the state of the OSTS bit (OSCCON<3>) will
confirm if the PIC12F635/PIC16F636/639 is running
from the external clock source, as defined by the FOSC
bits in the Configuration Word register (Register 12-1)
or the internal oscillator.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 35
PIC12F635/PIC16F636/639
FIGURE 3-7:
TWO-SPEED START-UP
Q1 Q2 Q3 Q4
Q1
Q2
Q3
Q4
Q1
INTOSC
TOST
OSC1
0
1
1022 1023
OSC2
Program Counter
PC
PC + 1
PC + 2
System Clock
The frequency of the internal oscillator will depend upon
the value contained in the IRCF bits (OSCCON<6:4>).
Upon entering the Fail-Safe condition, the OSTS bit
(OSCCON<3>) is automatically cleared to reflect that
the internal oscillator is active and the WDT is cleared.
The SCS bit (OSCCON<0>) is not updated. Enabling
FSCM does not affect the LTS bit.
3.7
Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) is designed to
allow the device to continue to operate in the event of
an oscillator failure. The FSCM can detect oscillator
failure at any point after the device has exited a Reset
or Sleep condition and the Oscillator Start-up Timer
(OST) has expired.
The FSCM sample clock is generated by dividing the
LFINTOSC clock by 64. This will allow enough time
between FSCM sample clocks for a system clock edge
to occur. Figure 3-8 shows the FSCM block diagram.
FIGURE 3-8:
FSCM BLOCK DIAGRAM
Clock Monitor
Latch (CM)
On the rising edge of the sample clock, the monitoring
latch (CM = 0) will be cleared. On a falling edge of the
primary system clock, the monitoring latch will be set
(CM = 1). In the event that a falling edge of the sample
clock occurs and the monitoring latch is not set, a clock
failure has been detected. The assigned internal
oscillator is enabled when FSCM is enabled, as
reflected by the IRCF.
(edge-triggered)
Primary
Clock
S
Q
LFINTOSC
Oscillator
÷ 64
C
Q
31 kHz
(~32 μs)
488 Hz
(~2 ms)
Clock
Failure
Detected
Note 1: Two-Speed Start-up is automatically
enabled when the Fail-Safe Clock
Monitor mode is enabled.
2: Primary clocks with a frequency of
≤ ~488 Hz will be considered failed by
FSCM. A slow starting oscillator can
cause an FCSM interrupt.
The FSCM function is enabled by setting the FCMEN
bit in the Configuration Word register (Register 12-1). It
is applicable to all external clock options (LP, XT, HS,
EC, RC or I/O modes).
In the event of an external clock failure, the FSCM will
set the OSFIF bit (PIR1<2>) and generate an oscillator
fail interrupt if the OSFIE bit (PIE1<2>) is set. The
device will then switch the system clock to the internal
oscillator. The system clock will continue to come from
the internal oscillator unless the external clock recovers
and the Fail-Safe condition is exited.
DS41232B-page 36
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
The Fail-Safe condition must be cleared before the
OSFIF flag can be cleared.
3.7.1
FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared after a Reset, the
execution of a SLEEPinstruction, or a modification of the
SCS bit. While in Fail-Safe condition, the PIC12F635/
PIC16F636/639 uses the internal oscillator as the
system clock source. The IRCF bits (OSCCON<6:4>)
can be modified to adjust the internal oscillator
frequency without exiting the Fail-Safe condition.
FIGURE 3-9:
Sample Clock
FSCM TIMING DIAGRAM
Oscillator
Failure
System
Clock
Output
CM Output
(Q)
Failure
Detected
OSCFIF
CM Test
CM Test
CM Test
Note:
The system clock is normally at a much higher frequency than the sample clock. The relative
frequencies in this example have been chosen for clarity.
3.7.2
RESET OR WAKE-UP FROM SLEEP
Note:
Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit (OSCCON<3>) to verify the
oscillator start-up and system clock
switchover has successfully completed.
The FSCM is designed to detect oscillator failure at any
point after the device has exited a Reset or Sleep
condition and the Oscillator Start-up Timer (OST) has
expired. If the external clock is EC or RC mode,
monitoring will begin immediately following these
events.
For LP, XT or HS mode, the external oscillator may
require a start-up time considerably longer than the
FSCM sample clock time or a false clock failure may be
detected (see Figure 3-9). To prevent this, the internal
oscillator is automatically configured as the system
clock and functions until the external clock is stable (the
OST has timed out). This is identical to Two-Speed
Start-up mode. Once the external oscillator is stable,
the LFINTOSC returns to its role as the FSCM source.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 37
PIC12F635/PIC16F636/639
REGISTER 3-2:
OSCCON – OSCILLATOR CONTROL REGISTER (ADDRESS: 8Fh)
U-0
—
R/W-1
IRCF2
R/W-1
IRCF1
R/W-0
IRCF0
R-1
OSTS(1)
R-0
R-0
LTS
R/W-0
SCS
HTS
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IRCF<2:0>: Nominal Internal Oscillator Frequency Select bits
000= 31 kHz
001= 125 kHz
010= 250 kHz
011= 500 kHz
100= 1 MHz
101= 2 MHz
110= 4 MHz
111= 8 MHz
bit 3
bit 2
bit 1
bit 0
OSTS: Oscillator Start-up Time-out Status bit(1)
1= Device is running from the external system clock defined by FOSC<2:0>
0= Device is running from the internal system clock (HFINTOSC or LFINTOSC)
HTS: HFINTOSC (High Frequency – 8 MHz to 125 kHz) Status bit
1= HFINTOSC is stable
0= HFINTOSC is not stable
LTS: LFINTOSC (Low Frequency – 31 kHz) Stable bit
1= LFINTOSC is stable
0= LFINTOSC is not stable
SCS: System Clock Select bit
1= Internal oscillator is used for system clock
0= Clock source defined by FOSC<2:0>
Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator
mode or Fail-Safe mode is enabled.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
TABLE 3-2:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Value on:
POR, BOD,
WUR
Value on
all other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Ch
8Ch
8Fh
90h
PIR1
EEIF
EEIE
—
LVDIF
LVDIE
CRIF
CRIE
C2IF
C2IE
C1IF
C1IE
OSFIF
OSFIE
HTS
—
—
TMR1IF 0000 00-0 0000 00-0
TMR1IE 0000 00-0 0000 00-0
PIE1
OSCCON
OSCTUNE
CONFIG
IRCF2 IRCF1 IRCF0
OSTS
TUN3
LTS
TUN1
SCS
-110 x000 -110 x000
—
—
—
TUN4
TUN2
TUN0 ---0 0000 ---u uuuu
(1)
2007h
CPD
CP
MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0
—
—
Legend:
x= unknown, u= unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Note 1: See Register 12-1 for operation of all Configuration Word register bits.
DS41232B-page 38
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
4.2
Additional Pin Functions
4.0
I/O PORTS
Every PORTA pin on the PIC12F635/PIC16F636/639
has an interrupt-on-change option and a weak pull-up/
pull-down option. RA0 has an Ultra Low-Power Wake-
up option. The next three sections describe these
functions.
There are as many as twelve general purpose I/O pins
available. Depending on which peripherals are
enabled, some or all of the pins may not be available as
general purpose I/O. In general, when a peripheral is
enabled, the associated pin may not be used as a
general purpose I/O pin.
4.2.1
WEAK PULL-UP/PULL-DOWN
Each of the PORTA pins, except RA3, has an internal
weak pull-up and pull-down. The WDA bits select either
a pull-up or pull-down for an individual port bit.
Individual control bits can turn on the pull-up or pull-
down. These pull-ups/pull-downs are automatically
turned off when the port pin is configured as an output,
as an alternate function or on a Power-on Reset,
setting the RAPU bit (OPTION_REG<7>). A weak pull-
up on RA3 is enabled when configured as MCLR in the
Configuration Word register and disabled when high
voltage is detected, to reduce current consumption
through RA3, while in Programming mode.
4.1
PORTA and the TRISA Registers
PORTA is
a 6-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register 4-4). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., put the
corresponding output driver in a High-impedance
mode). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., put the
contents of the output latch on the selected pin). The
exception is RA3, which is input only and its TRIS bit will
always read as ‘1’. Example 4-1 shows how to initialize
PORTA.
Note:
PORTA = GPIO
TRISA = TRISIO
Reading the PORTA register (Register 4-3) reads the
status of the pins, whereas writing to it will write to the
port latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the port data latch. RA3 reads ‘0’ when MCLRE = 1.
The TRISA register controls the direction of the
PORTA pins, even when they are being used as analog
inputs. The user must ensure the bits in the TRISA
register are maintained set when using them as analog
inputs. I/O pins configured as analog inputs always
read ‘0’.
Note:
The CMCON0 (19h) register must be
initialized to configure an analog channel
as a digital input. Pins configured as
analog inputs will read ‘0’.
EXAMPLE 4-1:
INITIALIZING PORTA
BCF
STATUS,RP0
;Bank 0
BCF
CLRF
STATUS,RP1
PORTA
;
;Init PORTA
;Set RA<2:0> to
;digital I/O
;Bank 1
MOVLW 07h
MOVWF CMCON0
BSF
BCF
STATUS,RP0
STATUS,RP1
;
MOVLW 0Ch
MOVWF TRISA
;Set RA<3:2> as inputs
;and set RA<5:4,1:0>
;as outputs
;Bank 0
BCF
BCF
STATUS,RP0
STATUS,RP1
;
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 39
PIC12F635/PIC16F636/639
REGISTER 4-1:
WDA – WEAK PULL-UP/PULL-DOWN REGISTER (ADDRESS: 97h)
U-0
—
U-0
—
R/W-1
WDA5
R/W-1
WDA4
U-0
—
R/W-1
WDA2
R/W-1
WDA1
R/W-1
WDA0
bit 7
bit 0
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
WDA<5:4>: Pull-up/Pull-down Selection bits
1= Pull-up selected
0= Pull-down selected
bit 3
Unimplemented: Read as ‘0’
bit 2-0
WDA<2:0>: Pull-up/Pull-down Selection bits
1= Pull-up selected
0= Pull-down selected
Note 1: The weak pull-up/pull-down device is enabled only when the global RAPU bit is
enabled, the pin is in Input mode (TRIS = 1), the individual WDA bit is enabled
(WDA = 1) and the pin is not configured as an analog input or clock function.
2: RA3 pull-up is enabled when the pin is configured as MCLR in the Configuration
Word register and the device is not in Programming mode.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
REGISTER 4-2:
WPUDA – WEAK PULL-UP/PULL-DOWN DIRECTION REGISTER (ADDRESS: 95h)
U-0
—
U-0
—
R/W-1
R/W-1
U-0
—
R/W-1
R/W-1
R/W-1
WPUDA5(3) WPUDA4(3)
WPUDA2 WPUDA1 WPUDA0
bit 0
bit 7
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
WPUDA<5:4>: Pull-up/Pull-down Direction Selection bits(3)
1= Pull-up/pull-down enabled
0= Pull-up/pull-down disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
WPUDA<2:0>: Pull-up/Pull-down Direction Selection bits
1= Pull-up/pull-down enabled
0= Pull-up/pull-down disabled
Note 1: The weak pull-up/pull-down direction device is enabled only when the global RAPU bit
is enabled, the pin is in Input mode (TRIS = 1), the individual WPUDA bit is enabled
(WPUDA = 1) and the pin is not configured as an analog input or clock function.
2: RA3 pull-up is enabled when the pin is configured as MCLR in the Configuration
Word register and the device is not in Programming mode.
3: WPUDA5 bit can be written if INTOSC is enabled and T1OSC is disabled;
otherwise, the bit can not be written and reads as ‘1’. WPUDA4 bit can be written
if not configured as OSC2; otherwise, the bit can not be written and reads as ‘1’.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS41232B-page 40
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
REGISTER 4-3:
PORTA – PORTA REGISTER (ADDRESS: 05h)
U-0
—
U-0
—
R/W-x
RA5
R/W-x
RA4
R-x
R/W-x
RA2
R/W-0
RA1
R/W-0
RA0
RA3
bit 7
bit 0
bit 7-6:
bit 5-0:
Unimplemented: Read as ‘0’
RA<5:0>: PORTA I/O pins
1= Port pin is > VIH
0= Port pin is < VIL
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
REGISTER 4-4:
TRISA – PORTA TRI-STATE REGISTER (ADDRESS: 85h)
U-0
—
U-0
—
R/W-1
R/W-1
R-1
R/W-1
R/W-1
R/W-1
TRISA5(2) TRISA4(2) TRISA3(1) TRISA2 TRISA1
TRISA0
bit 7
bit 0
bit 7-6:
bit 5-0:
Unimplemented: Read as ‘0’
TRISA<5:0>: PORTA Tri-State Control bits(1,2)
1= PORTA pin configured as an input (tri-stated)
0= PORTA pin configured as an output
Note 1: TRISA<3> always reads ‘1’.
2: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 41
PIC12F635/PIC16F636/639
A mismatch condition will continue to set flag bit RAIF.
Reading PORTA will end the mismatch condition and
allow flag bit RAIF to be cleared. The latch holding the
last read value is not affected by a MCLR nor BOD
Reset. After these Resets, the RAIF flag will continue
to be set if a mismatch is present.
4.2.2
INTERRUPT-ON-CHANGE
Each of the PORTA pins is individually configurable as
an interrupt-on-change pin. Control bits, IOCAx, enable
or disable the interrupt function for each pin. Refer to
Register 4-5. The interrupt-on-change is disabled on a
Power-on Reset.
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTA Change Interrupt Flag
bit (RAIF) in the INTCON register (Register 2-3).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, clears the
interrupt by:
a) Any read or write of PORTA. This will end the
mismatch condition, then
b) Clear the flag bit RAIF.
REGISTER 4-5:
IOCA – INTERRUPT-ON-CHANGE PORTA REGISTER (ADDRESS: 96h)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
IOCA2
R/W-0
IOCA1
R/W-0
IOCA0
IOCA5(2) IOCA4(2) IOCA3(3)
bit 7
bit 0
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
IOCA<5:0>: Interrupt-on-change PORTA Control bits(2,3)
1= Interrupt-on-change enabled(1)
0= Interrupt-on-change disabled
Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be
recognized.
2: IOCA<5:4> always reads ‘0’ in XT, HS and LP Oscillator modes.
3: IOCA<3> is ignored when WUR is enabled and the device is in Sleep mode.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS41232B-page 42
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
4.2.3
ULTRA LOW-POWER WAKE-UP
EXAMPLE 4-2:
ULTRA LOW-POWER
WAKE-UP INITIALIZATION
The Ultra Low-Power Wake-up (ULPWU) on RA0 allows
a slow falling voltage to generate an interrupt-on-change
on RA0 without excess current consumption. The mode
is selected by setting the ULPWUE bit (PCON<5>). This
enables a small current sink which can be used to
discharge a capacitor on RA0.
BCF
BCF
BSF
MOVLW
MOVWF
BSF
BCF
BCF
STATUS,RP0
;Bank 0
STATUS,RP1
PORTA,0
;
;Set RA0 data latch
;Turn off
H’7’
CMCON0
; comparators
;Bank 1
;
;Output high to
; charge capacitor
STATUS,RP0
STATUS,RP1
TRISA,0
To use this feature, the RA0 pin is configured to output
‘1’ to charge the capacitor, interrupt-on-change for RA0
is enabled and RA0 is configured as an input. The
ULPWUE bit is set to begin the discharge and a SLEEP
instruction is performed. When the voltage on RA0 drops
below VIL, an interrupt will be generated which will cause
the device to wake-up. Depending on the state of the
GIE bit (INTCON<7>), the device will either jump to the
interrupt vector (0004h) or execute the next instruction
when the interrupt event occurs. See Section 4.2.2
“Interrupt-on-change” and Section 12.9.3 “PORTA
Interrupt” for more information.
CALL
BSF
BSF
CapDelay
PCON,ULPWUE ;Enable ULP Wake-up
IOCA,0
TRISA,0
;Select RA0 IOC
;RA0 to input
B’10001000’ ;Enable interrupt
BSF
MOVLW
MOVWF
SLEEP
INTCON
; and clear flag
;Wait for IOC
This feature provides a low power technique for
periodically waking up the device from Sleep. The time-
out is dependent on the discharge time of the RC circuit
on RA0. See Example 4-2 for initializing the Ultra Low
Power Wake-up module.
The series resistor provides overcurrent protection for the
RA0 pin and can allow for software calibration of the time-
out (see Figure 4-1). A timer can be used to measure the
charge time and discharge time of the capacitor. The
charge time can then be adjusted to provide the desired
interrupt delay. This technique will compensate for the
affects of temperature, voltage and component accuracy.
The Ultra Low-Power Wake-up peripheral can also be
configured as a simple Programmable Low-Voltage
Detect or temperature sensor.
Note:
For more information, refer to the
Application Note AN879, “Using the
Microchip Ultra Low-Power Wake-up
Module” (DS00879).
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 43
PIC12F635/PIC16F636/639
4.2.4
PIN DESCRIPTIONS AND
DIAGRAMS
4.2.4.1
RA0/C1IN+/ICSPDAT/ULPWU
Figure 4-2 shows the diagram for this pin. The RA0 pin
is configurable to function as one of the following:
Each PORTA pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions,
such as the comparator, refer to the appropriate section
in this data sheet.
• a general purpose I/O
• an analog input to the comparator
• In-Circuit Serial Programming™ data
• an analog input for the Ultra Low-Power Wake-up
FIGURE 4-1:
BLOCK DIAGRAM OF RA0
Analog
Input Mode(1)
VDD
Data Bus
D
Q
Q
Weak
CK
WR
WPUDA
RAPU
RD
Weak
WPUDA
D
Q
Q
CK
WR
WDA
VDD
RD
WDA
D
Q
Q
I/O pin
WR
CK
PORTA
–
+
VSS
VT
D
Q
Q
WR
TRISA
CK
IULP
0
1
RD
TRISA
Analog
Input Mode(1)
VSS
ULPWUE
RD
PORTA
D
Q
Q
Q
D
D
CK
WR
IOCA
Q3
EN
RD
IOCA
Interrupt-on-
Change
Q
EN
RD PORTA
Note 1: Comparator mode determines Analog Input mode.
DS41232B-page 44
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
4.2.4.2
RA1/C1IN-/VREF/ICSPCLK
4.2.4.3
RA2/T0CKI/INT/C1OUT
Figure 4-2 shows the diagram for this pin. The RA1 pin
is configurable to function as one of the following:
Figure 4-3 shows the diagram for this pin. The RA2 pin
is configurable to function as one of the following:
• a general purpose I/O
• a general purpose I/O
• an analog input to the comparator
• In-Circuit Serial Programming clock
• the clock input for TMR0
• an external edge-triggered interrupt
• a digital output from the comparator
FIGURE 4-2:
BLOCK DIAGRAM OF RA1
FIGURE 4-3:
BLOCK DIAGRAM OF RA2
Analog
Input Mode(1)
Data Bus
D
Q
Q
Data Bus
D
VDD
Q
Q
WR
CK
WPUDA
VDD
WR
CK
WPUDA
Weak
Weak
RAPU
RD
RAPU
RD
WPUDA
WPUDA
Weak
Weak
D
Q
Q
D
Q
Q
VSS
WR
WDA
CK
VSS
WR
CK
WDA
RD
RD
WDA
WDA
VDD
D
Q
Q
C1OUT
VDD
D
Q
Q
Enable
WR
PORTA
CK
WR
PORTA
CK
C1OUT
1
0
I/O pin
D
Q
Q
I/O pin
D
Q
Q
WR
TRISA
CK
VSS
WR
TRISA
CK
VSS
Analog
Input Mode(1)
RD
TRISA
RD
TRISA
RD
PORTA
RD
PORTA
D
Q
Q
D
Q
Q
Q
Q
D
CK
WR
IOCA
Q
Q
D
CK
WR
IOCA
Q3
EN
RD
IOCA
EN
Q3
D
RD
IOCA
D
EN
Interrupt-on-
change
EN
Interrupt-on-
change
RD PORTA
RD PORTA
To Comparator
To TMR0
To INT
Note 1: Comparator mode determines Analog Input mode.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 45
PIC12F635/PIC16F636/639
4.2.4.4
RA3/MCLR/VPP
Figure 4-4 shows the diagram for this pin. The RA3 pin
is configurable to function as one of the following:
• a general purpose input
• as Master Clear Reset with weak pull-up
• a high-voltage detect for Program mode entry
FIGURE 4-4:
BLOCK DIAGRAM OF RA3
VDD
Weak
MCLRE
Program
Mode
HV Detect
Reset
MCLRE
Data Bus
Input
pin
RD
TRISA
VSS
MCLRE
RD
VSS
Q3
PORTA
D
Q
Q
Q
Q
D
CK
WR
IOCA
EN
RD
IOCA
D
EN
RD PORTA
Interrupt-on-
change
WURE
Sleep
DS41232B-page 46
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
4.2.4.5
RA4/T1G/OSC2/CLKOUT
4.2.4.6
RA5/T1CKI/OSC1/CLKIN
Figure 4-5 shows the diagram for this pin. The RA4 pin
is configurable to function as one of the following:
Figure 4-6 shows the diagram for this pin. The RA5 pin
is configurable to function as one of the following:
• a general purpose I/O
• a TMR1 gate input
• a crystal/resonator connection
• a clock output
• a general purpose I/O
• a TMR1 clock input
• a crystal/resonator connection
• a clock input
FIGURE 4-5:
BLOCK DIAGRAM OF RA4
FIGURE 4-6:
BLOCK DIAGRAM OF RA5
Data Bus
D
Data Bus
D
CLK(1) Modes
VDD
CLK(1) Modes
VDD
Q
Q
Q
Q
WR
WR
CK
CK
WPUDA
WPUDA
Weak
Weak
RAPU
RAPU
RD
RD
WPUDA
WPUDA
Weak
Weak
D
Q
Q
D
Q
Q
VSS
VSS
WR
WR
WDA
CK
CK
WDA
Oscillator
Circuit
RD
WDA
RD
WDA
Oscillator
Circuit
OSC1
VDD
CLKOUT
Enable
OSC2
VDD
D
Q
Q
Fosc/4
1
0
WR
PORTA
CK
D
Q
Q
WR
PORTA
CK
I/O pin
I/O pin
CLKOUT
Enable
D
Q
Q
VSS
WR
TRISA
CK
D
Q
Q
VSS
INTOSC/
RC/EC(2)
WR
TRISA
INTOSC
Mode
CK
RD
TRISA
CLKOUT
Enable
(2)
RD
TRISA
RD
PORTA
XTAL
D
Q
Q
RD
PORTA
Q
Q
D
CK
WR
IOCA
D
Q
Q
Q3
EN
Q
Q
D
CK
WR
IOCA
RD
IOCA
EN
Q3
D
RD
IOCA
D
EN
Interrupt-on-
change
EN
Interrupt-on-
change
RD PORTA
RD PORTA
T1G To Timer1
T1G To Timer1
Note 1: Oscillator modes are XT, HS, LP and LPTMR1.
Note 1: Oscillator modes are XT, HS, LP, LPTMR1 and
CLKOUT Enable.
2: When using Timer1 with LP oscillator, the
Schmitt Trigger is bypassed.
2: With CLKOUT option.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 47
PIC12F635/PIC16F636/639
TABLE 4-1:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on:
POR, BOD, all other
WUR Resets
Value on
Add
r
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
05h PORTA
—
—
RA5
T0IE
RA4
RA3
RA2
T0IF
RA1
RA0
--xx xx00 --uu uu00
0Bh/ INTCON
8Bh
GIE
PEIE
INTE
RAIE
INTF
RAIF 0000 0000 0000 0000
0Eh TMR1L
0Fh TMR1H
10h T1CON
1Ah CMCON1
19h CMCON0
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
—
—
—
—
—
—
T1GSS C2SYNC ---- --10 ---- --10
C2OUT C1OUT
C2INV
T0CS
C1INV
T0SE
CIS
PSA
CM2
PS2
CM1
PS1
CM0
PS0
0000 0000 0000 0000
1111 1111 1111 1111
81h OPTION_REG RAPU INTEDG
85h TRISA
95h WPUDA
96h IOCA
97h WDA
—
—
—
—
—
—
—
—
TRISA5 TRISA4
WPUDA5 WPUDA4
TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
—
IOCA3
—
WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111
IOCA5
WDA5
IOCA4
WDA4
IOCA2
WDA2
IOCA1
WDA1
IOCA0 --00 0000 --00 0000
WDA0 --11 -111 --11 -111
Legend:
x= unknown, u= unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
DS41232B-page 48
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 4-7:
BLOCK DIAGRAM OF RC0
AND RC1
4.3
PORTC
PORTC is a general purpose I/O port consisting of 6
bidirectional pins. The pins can be configured for either
digital I/O or analog input to comparator. For specific
information about individual functions, refer to the
appropriate section in this data sheet.
Data Bus
VDD
D
Q
Q
WR
PORTC
CK
Note:
The CMCON0 (19h) register must be ini-
tialized to configure an analog channel as
a digital input. Pins configured as analog
inputs will read ‘0’.
I/O pin
D
Q
Q
WR
TRISC
CK
VSS
Analog Input
EXAMPLE 4-3:
INITIALIZING PORTC
Mode
BCF
BCF
CLRF
MOVLW
MOVWF
BSF
BCF
MOVLW
MOVWF
STATUS,RP0
STATUS,RP1
PORTC
;Bank 0
;
;Init PORTC
;Set RC<4,1:0> to
;digital I/O
;Bank 1
RD
TRISC
07h
RD
PORTC
CMCON0
STATUS,RP0
STATUS,RP1
0Ch
To Comparators
;Set RC<3:2> as inputs
;and set RC<5:4,1:0>
;as outputs
TRISC
4.3.3
RC2
BCF
BCF
STATUS,RP0
STATUS,RP1
;Bank 0
;
The RC2 pin is configurable to function as a general
purpose I/O.
4.3.1
RC0/C2IN+
4.3.4
RC3
The RC0 pin is configurable to function as one of the
following:
The RC3 pin is configurable to function as a general
purpose I/O.
• a general purpose I/O
• an analog input to the comparator
4.3.5
RC5
4.3.2
RC1/C2IN-
The RC5 pin is configurable to function as a general
purpose I/O.
The RC1 pin is configurable to function as one of the
following:
FIGURE 4-8:
BLOCK DIAGRAM OF
RC2, RC3 AND RC5
• a general purpose I/O
• an analog input to the comparator
Data Bus
VDD
D
CK
Q
Q
WR
PORTC
I/O pin
D
Q
Q
WR
TRISC
CK
VSS
RD
TRISC
RD
PORTC
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 49
PIC12F635/PIC16F636/639
4.3.6
RC4/C2OUT
The RC4 pin is configurable to function as one of the
following:
• a general purpose I/O
• a digital output from the comparator
FIGURE 4-9:
BLOCK DIAGRAM OF RC4
C2OUT Enable
C2OUT
Data Bus
VDD
D
Q
Q
WR
PORTC
CK
1
0
I/O pin
D
Q
Q
WR
TRISC
CK
VSS
RD
TRISC
RD
PORTC
DS41232B-page 50
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
REGISTER 4-6:
PORTC – PORTC REGISTER (ADDRESS: 07h)
U-0
—
U-0
—
R/W-x
RC5
R/W-x
RC4
R/W-x
RC3
R/W-x
RC2
R/W-0
RC1
R/W-0
RC0
bit 7
bit 0
bit 7-6:
bit 5-0:
Unimplemented: Read as ‘0’
RC<5:0>: PORTC General Purpose I/O Pin bits
1= Port pin is > VIH
0= Port pin is < VIL
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
REGISTER 4-7:
TRISC – PORTC TRI-STATE REGISTER (ADDRESS: 87h)
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
bit 7
bit 0
bit 7-6:
bit 5-0:
Unimplemented: Read as ‘0’
TRISC<5:0>: PORTC Tri-State Control bit
1= PORTC pin configured as an input (tri-stated)
0= PORTC pin configured as an output
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
TABLE 4-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on:
POR, BOD,
WUR
Value on
all other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
07h
PORTC
—
—
RC5
RC4
RC3
CIS
RC2
CM2
RC1
CM1
RC0
CM0
--xx xx00 --uu uu00
0000 0000 0000 0000
19h
CMCON0 C2OUT C1OUT C2INV
TRISC
x= unknown, u= unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.
C1INV
87h
—
—
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111
Legend:
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 51
PIC12F635/PIC16F636/639
NOTES:
DS41232B-page 52
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
Counter mode is selected by setting the T0CS bit
(OPTION_REG<5>). In this mode, the Timer0 module
will increment either on every rising or falling edge of
pin RA2/T0CKI. The incrementing edge is determined
5.0
TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
by
the
source
edge
(T0SE)
control
bit
• 8-bit timer/counter
(OPTION_REG<4>). Clearing the T0SE bit selects the
rising edge.
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Note:
Counter mode has specific external clock
requirements. Additional information on
these requirements is available in the
“PICmicro® Mid-Range MCU Family
Reference Manual” (DS33023).
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
Note:
Additional information on the Timer0
module is available in the “PICmicro® Mid-
Range MCU Family Reference Manual”
(DS33023).
5.2
Timer0 Interrupt
A Timer0 interrupt is generated when the TMR0
register timer/counter overflows from FFh to 00h. This
overflow sets the T0IF bit (INTCON<2>). The interrupt
can be masked by clearing the T0IE bit (INTCON<5>).
The T0IF bit must be cleared in software by the Timer0
module Interrupt Service Routine before re-enabling
this interrupt. The Timer0 interrupt cannot wake the
processor from Sleep since the timer is shut off during
Sleep.
5.1
Timer0 Operation
Timer mode is selected by clearing the T0CS bit
(OPTION_REG<5>). In Timer mode, the Timer0
module will increment every instruction cycle (without
prescaler). If TMR0 is written, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
FIGURE 5-1:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
CLKOUT
(= FOSC/4)
Data Bus
0
1
8
1
SYNC/2
Cycles
TMR0
T0CKI
pin
0
0
1
Set Flag bit T0IF
on Overflow
T0CS
T0SE
8-bit
Prescaler
PSA
8
PSA
WDTE
SWDTEN
1
PS<2:0>
WDT
Time-out
16-bit
Prescaler
0
16
Watchdog
Timer
LFINTOSC
PSA
WDTPS<3:0>
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the Option register, WDTPS<3:0> are bits in the WDTCON register.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 53
PIC12F635/PIC16F636/639
5.3
Using Timer0 with an External
Clock
When no prescaler is used, the external clock input is the
same as the prescaler output. The synchronization of
T0CKI, with the internal phase clocks, is accomplished
by sampling the prescaler output on the Q2 and Q4
cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2 TOSC (and a
small RC delay of 20 ns) and low for at least 2 TOSC (and
a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
Note:
The CMCON0 (19h) register must be ini-
tialized to configure an analog channel as
a digital input. Pins configured as analog
inputs will read ‘0’.
REGISTER 5-1:
OPTION_REG – OPTION REGISTER (ADDRESS: 81h)
R/W-1
RAPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
RAPU: PORTA Pull-up Enable bit
1= PORTA pull-ups are disabled
0= PORTA pull-ups are enabled by individual values in the WPUDA register
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RA2/T0CKI/INT/C1OUT pin
0= Interrupt on falling edge of RA2/T0CKI/INT/C1OUT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on RA2/T0CKI/INT/C1OUT pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on RA2/T0CKI/INT/C1OUT pin
0= Increment on low-to-high transition on RA2/T0CKI/INT/C1OUT pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate(1)
000
001
010
011
100
101
110
111
1 : 2
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Note 1: A dedicated 16-bit WDT postscaler is available for the PIC12F635/PIC16F636/639.
See Section 12.11 “Watchdog Timer (WDT)” for more information.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS41232B-page 54
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
EXAMPLE 5-1:
CHANGING PRESCALER
(TIMER0 → WDT)
5.4
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. For simplicity, this counter will be referred to as
“prescaler” throughout this data sheet. The prescaler
assignment is controlled in software by the control bit,
PSA (OPTION_REG<3>). Clearing the PSA bit will
assign the prescaler to Timer0. Prescale values are
selectable via the PS<2:0> bits (OPTION_REG<2:0>).
BCF
STATUS,RP0
;Bank 0
;
BCF
STATUS,RP1
CLRWDT
CLRF
;Clear WDT
;Clear TMR0 and
; prescaler
;Bank 1
;
;Required if desired
; PS2:PS0 is
; 000 or 001
;
TMR0
BSF
BCF
STATUS,RP0
STATUS,RP1
MOVLW
MOVWF
CLRWDT
b’00101111’
OPTION_REG
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing
to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,
x....etc.) will clear the prescaler. When assigned to
WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer.
MOVLW
MOVWF
BCF
b’00101xxx’
OPTION_REG
STATUS,RP0
STATUS,RP1
;Set postscaler to
; desired WDT rate
;Bank 0
BCF
;
5.4.1
SWITCHING PRESCALER
ASSIGNMENT
To change prescaler from the WDT to the TMR0
module, use the sequence shown in Example 5-2. This
precaution must be taken even if the WDT is disabled.
The prescaler assignment is fully under software control
(i.e., it can be changed “on the fly” during program
execution). To avoid an unintended device Reset, the
following instruction sequence (Example 5-1 and
Example 5-2) must be executed when changing the
prescaler assignment from Timer0 to WDT.
EXAMPLE 5-2:
CHANGING PRESCALER
(WDT → TIMER0)
CLRWDT
;Clear WDT and
;prescaler
;Bank 1
BSF
BCF
STATUS,RP0
STATUS,RP1
;
MOVLW
b’xxxx0xxx’
;Select TMR0,
;prescale, and
;clock source
MOVWF
BCF
BCF
OPTION_REG
STATUS,RP0
STATUS,RP1
;
;Bank 0
;
TABLE 5-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
Bit 0 POR, BOD,
WUR
Value on
all other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
01h
TMR0
Timer0 Module Register
GIE PEIE T0IE
OPTION_REG RAPU INTEDG T0CS
TRISA
— = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the Timer0 module.
xxxx xxxx uuuu uuuu
0Bh/8Bh INTCON
INTE
RAIE
PSA
T0IF
PS2
INTF
PS1
RAIF 0000 0000 0000 0000
81h
T0SE
PS0
1111 1111 1111 1111
85h
—
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
Legend:
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 55
PIC12F635/PIC16F636/639
NOTES:
DS41232B-page 56
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
The Timer1 Control register (T1CON), shown in
Register 6-1, is used to enable/disable Timer1 and
select the various features of the Timer1 module.
6.0
TIMER1 MODULE WITH GATE
CONTROL
The PIC12F635/PIC16F636/639 has a 16-bit timer.
Figure 6-1 shows the basic block diagram of the Timer1
module. Timer1 has the following features:
Note:
Additional information on timer modules is
available in the “PICmicro® Mid-Range
MCU
Family
Reference
Manual”
• 16-bit timer/counter (TMR1H:TMR1L)
• Readable and writable
(DS33023).
• Internal or external clock selection
• Synchronous or asynchronous operation
• Interrupt on overflow from FFFFh to 0000h
• Wake-up upon overflow (Asynchronous mode)
• Optional external enable input:
- Selectable gate source: T1G or C2 output
(T1GSS)
- Selectable gate polarity (T1GINV)
• Optional LP oscillator
FIGURE 6-1:
TIMER1 ON THE PIC12F635/PIC16F636/639 BLOCK DIAGRAM
TMR1ON
TMR1GE
T1GINV
TMR1ON
TMR1GE
Set Flag bit
To C2 Comparator Module
TMR1 Clock
TMR1IF on
Overflow
(1)
TMR1
Synchronized
Clock Input
0
TMR1L
TMR1H
1
Oscillator
(3)
T1SYNC
OSC1/T1CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
0
OSC2/T1G
2
Sleep Input
T1CKPS<1:0>
INTOSC
No CLKOUT
TMR1CS
T1OSCEN
1
0
(2)
C2OUT
T1GSS
Note 1: Timer1 increments on the rising edge.
2: C2OUT for PIC16F636/639, C1OUT for PIC12F635.
3: ST Buffer is low-power type when using LP oscillator, or high-speed type when using T1CKI.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 57
PIC12F635/PIC16F636/639
6.1
Timer1 Modes of Operation
6.3
Timer1 Prescaler
Timer1 can operate in one of three modes:
Timer1 has four prescaler options, allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits
(T1CON<5:4>) control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write
to TMR1H or TMR1L.
• 16-bit timer with prescaler
• 16-bit synchronous counter
• 16-bit asynchronous counter
In Timer mode, Timer1 is incremented on every
instruction cycle. In Counter mode, Timer1 is incremented
on the rising edge of the external clock input T1CKI. In
addition, the Counter mode clock can be synchronized to
the microcontroller system clock or run asynchronously.
6.4
Timer1 Gate
Timer1 gate source is software configurable to be the
T1G pin or the output of Comparator 2. This allows the
device to directly time external events using T1G or
analog events using Comparator 2. See CMCON1
(Register 7-2) for selecting the Timer1 gate source.
This feature can simplify the software for many other
applications.
In Counter and Timer modules, the counter/timer clock
can be gated by the Timer1 gate, which can be selected
as either the T1G pin or the Comparator 2 output.
If an external clock oscillator is needed (and the
microcontroller is using the INTOSC w/o CLKOUT),
Timer1 can use the LP oscillator as a clock source.
Note:
TMR1GE bit (T1CON<6>) must be set to
use either T1G or C2OUT as the Timer1
gate source. See Register 7-2 for more
information on selecting the Timer1 gate
source.
Note:
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge.
6.2
Timer1 Interrupt
Timer1 gate can be inverted using the T1GINV bit
(T1CON<7>), whether it originates from the T1G pin or
Comparator 2 output. This configures Timer1 to
measure either the active-high or active-low time
between events.
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit (PIR1<0>) is set. To
enable the interrupt on rollover, you must set these bits:
• Timer1 interrupt enable bit (PIE1<0>)
• PEIE bit (INTCON<6>)
• GIE bit (INTCON<7>).
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
Note:
The TMR1H:TTMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
FIGURE 6-2:
TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of
the clock.
DS41232B-page 58
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
REGISTER 6-1:
T1CON – TIMER1 CONTROL REGISTER (ADDRESS: 10h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
R/W-0
R/W-0
bit 7
bit 0
bit 7
bit 6
T1GINV: Timer1 Gate Invert bit(1)
1= Timer1 gate is inverted
0= Timer1 gate is not inverted
TMR1GE: Timer1 Gate Enable bit(2)
If TMR1ON = 0:
This bit is ignored.
If TMR1ON = 1:
1= Timer1 is on if Timer1 gate is not active
0= Timer1 is on
bit 5-4
bit 3
T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
T1OSCEN: LP Oscillator Enable Control bit
If INTOSC without CLKOUT oscillator is active:
1= LP oscillator is enabled for Timer1 clock
0= LP oscillator is off
Else:
This bit is ignored.
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from T1CKI pin (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.
2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the
T1GSS bit (CMCON1<1>), as a Timer1 gate source.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 59
PIC12F635/PIC16F636/639
6.5
Timer1 Operation in
6.6
Timer1 Oscillator
Asynchronous Counter Mode
A crystal oscillator circuit is built-in between pins OSC1
(input) and OSC2 (amplifier output). It is enabled by
setting control bit, T1OSCEN (T1CON<3>). The
oscillator is a low-power oscillator rated up to 31 kHz. It
will continue to run during Sleep. It is primarily intended
for a 32 kHz crystal. Table 3-1 shows the capacitor
selection for the Timer1 oscillator.
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up the
processor. However, special precautions in software are
needed to read/write the timer (see Section 6.5.1
“Reading and Writing Timer1 in Asynchronous
Counter Mode”).
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer1 can use this mode only when
the primary system clock is derived from the internal
oscillator. As with the system LP oscillator, the user
must provide a software time delay to ensure proper
oscillator start-up.
Note:
The CMCON0 (19h) register must be
initialized to configure an analog channel
as a digital input. Pins configured as
analog inputs will read ‘0’.
TRISA5 and TRISA4 bits are set when the Timer1
oscillator is enabled. RA5 and RA4 bits read as ‘0’ and
TRISA5 and TRISA4 bits read as ‘1’.
6.5.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Note:
The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1.
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
6.7
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when set up in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers
while the register is incrementing. This may produce an
unpredictable value in the timer register.
• Timer1 must be on (T1CON<0>)
• TMR1IE bit (PIE1<0>) must be set
• PEIE bit (INTCON<6>) must be set
Reading the 16-bit value requires some care.
Examples in the “PICmicro® Mid-Range MCU Family
Reference Manual” (DS33023) show how to read and
write Timer1 when it is running in Asynchronous mode.
The device will wake-up on an overflow. If the GIE bit
(INTCON<7>) is set, the device will wake-up and jump
to the Interrupt Service Routine (0004h) on an overflow.
If the GIE bit is clear, execution will continue with the
next instruction.
TABLE 6-1:
REGISTERS ASSOCIATED WITH TIMER1
Value on
POR, BOD,
WUR
Value on
all other
Resets
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh/
8Bh
INTCON
PIR1
GIE
PEIE
T0IE
INTE
C2IF
RAIE
C1IF
T0IF
INTF
—
RAIF
0000 0000 0000 0000
0Ch
0Eh
0Fh
10h
1Ah
EEIF
LVDIF
CRIF
OSFIF
TMR1IF 0000 00-0 0000 00-0
xxxx xxxx uuuu uuuu
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
CMCON
1
—
—
—
—
—
—
T1GSS C2SYNC ---- --10 ---- --10
8Ch
PIE1
EEIE
LVDIE
CRIE
C2IE
C1IE
OSFIE
—
TMR1IE 0000 00-0 0000 00-0
Legend:
x= unknown, u= unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
DS41232B-page 60
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
The CMCON0 register (Register 7-1) controls the
comparator input and output multiplexers. A block
diagram of the various comparator configurations is
shown in Figure 7-4.
7.0
COMPARATOR MODULE
The comparator module contains two analog
comparators. The inputs to the comparators are
multiplexed with I/O port pins RA0, RA1, RC0 and RC1,
while the outputs are multiplexed to pins RA2 and RC4.
An on-chip Comparator Voltage Reference (CVREF)
can also be applied to the inputs of the comparators.
Note:
The PIC12F635 has only 1 comparator.
The comparator on the PIC12F635
behaves like comparator
PIC16F636/639.
2
of the
REGISTER 7-1:
CMCON0 – COMPARATOR CONTROL 0 REGISTER (ADDRESS: 19h)
R-0
R-0
R/W-0
R/W-0
R/W-0
CIS
R/W-0
CM2
R/W-0
CM1
R/W-0
CM0
bit 0
C2OUT(1) C1OUT(2) C2INV(1) C1INV(2)
bit 7
bit 7
C2OUT: Comparator 2 Output bit(1)
When C2INV = 0:
1= C2 VIN+ > C2 VIN-
0= C2 VIN+ < C2 VIN-
When C2INV = 1:
1= C2 VIN+ < C2 VIN-
0= C2 VIN+ > C2 VIN-
bit 6
C1OUT: Comparator 1 Output bit(2)
When C1INV = 0:
1= C1 VIN+ > C1 VIN-
0= C1 VIN+ < C1 VIN-
When C1INV = 1:
1= C1 VIN+ < C1 VIN-
0= C1 VIN+ > C1 VIN-
bit 5
bit 4
bit 3
C2INV: Comparator 2 Output Inversion bit(1)
1= C2 output inverted
0= C2 output not inverted
C1INV: Comparator 1 Output Inversion bit(2)
1= C1 output inverted
0= C1 output not inverted
CIS: Comparator Input Switch bit
When CM<2:0> = 010:
1= C1 VIN- connects to RA0
C2 VIN- connects to RC0
0= C1 VIN- connects to RA1
C2 VIN- connects to RC1
When CM<2:0> = 001:
1= C1 VIN- connects to RA0
0= C1 VIN- connects to RA1
bit 2-0
CM<2:0>: Comparator Mode bits
Figure 7-4 shows the Comparator modes and CM<2:0> bit settings.
Note 1: PIC16F636/639 only. Reads as ‘0’ for PIC12F635.
2: PIC12F635 bit names are COUT and CINV.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 61
PIC12F635/PIC16F636/639
FIGURE 7-1:
SINGLE COMPARATOR
7.1
Comparator Operation
A single comparator is shown in Figure 7-1 along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 7-1 represent
the uncertainty due to input offsets and response time.
VIN+
VIN-
+
Output
–
VIN-
VIN+
Note:
To use CIN+ and CIN- pins as analog
inputs, the appropriate bits must be
programmed in the CMCON0 (19h)
register.
Output
The polarity of the comparator output can be inverted
by setting the CxINV bits (CMCON0<5:4>). Clearing
CxINV results in a non-inverted output. A complete
table showing the output state versus input conditions
and the polarity bit is shown in Table 7-1.
7.2
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 7-2. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum source impedance of 10 kΩ is recommended
for the analog sources. Any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current.
TABLE 7-1:
OUTPUT STATE VS. INPUT
CONDITIONS
Input Conditions
CINV
CxOUT
VIN- > VIN+
VIN- < VIN+
VIN- > VIN+
VIN- < VIN+
0
0
1
1
0
1
1
0
Note 1: When reading the Port register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert as analog inputs according to the
input specification.
2: Analog levels on any pin defined as a
digital input may cause the input buffer to
consume more current than is specified.
FIGURE 7-2:
ANALOG INPUT MODEL
VDD
VT = 0.6V
RIC
Rs < 10 kΩ
AIN
ILEAKAGE
±500 nA
CPIN
5 pF
VA
VT = 0.6V
Vss
Legend:
CPIN
VT
= Input Capacitance
= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
RS
VA
= Interconnect Resistance
= Source Impedance
= Analog Voltage
DS41232B-page 62
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
7.3
Comparator Configuration
There are eight modes of operation for the comparators.
The CMCON0 register is used to select these modes.
Figure 7-3 and Figure 7-4 show the eight possible
modes. The TRISA and TRISC registers control the data
direction of the comparator output pins for each mode. If
the Comparator mode is changed, the comparator
output level may not be valid for the specified mode
change delay shown in Section 15.0 “Electrical
Specifications”.
Note:
Comparator interrupts should be disabled
during Comparator mode change.
Otherwise, a false interrupt may occur.
a
FIGURE 7-3:
COMPARATOR I/O OPERATING MODES FOR PIC12F635
Comparator Off (Lowest Power)(1)
Comparator Reset (POR Default Value – Low Power)
CM<2:0> = 000
CM<2:0> = 111
GP1/CIN-
GP0/CIN+
A
A
GP1/CIN-
GP0/CIN+
D
D
Off (Read as ‘0’)
Off (Read as ‘0’)
GP2/C1OUT
D
GP2/C1OUT
D
Comparator without Output
Comparator w/o Output and with Internal Reference
CM<2:0> = 010
CM<2:0> = 100
GP1/CIN-
GP0/CIN+
A
A
GP1/CIN-
GP0/CIN+
A
D
C1OUT
C1OUT
GP2/C1OUT
D
GP2/C1OUT
D
From CVREF Module
Comparator with Output and Internal Reference
Multiplexed Input with Internal Reference and Output
CM<2:0> = 011
CM<2:0> = 101
GP1/CIN-
GP0/CIN+
A
D
GP1/CIN-
GP0/CIN+
A
A
CIS = 0
CIS = 1
C1OUT
C1OUT
GP2/C1OUT
D
GP2/C1OUT
D
From CVREF Module
From CVREF Module
Comparator with Output
Multiplexed Input with Internal Reference
CM<2:0> = 001
CM<2:0> = 110
GP1/CIN-
GP0/CIN+
A
A
GP1/CIN-
GP0/CIN+
A
A
CIS = 0
CIS = 1
C1OUT
C1OUT
GP2/C1OUT
D
GP2/C1OUT
D
From CVREF Module
Legend: A = Analog Input, ports always read ‘0’
CIS = Comparator Input Switch (CMCON0<3>)
D = Digital Input
Note 1: Lowest power statement assures valid digital stats on GPO, GP1 and GP2.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 63
PIC12F635/PIC16F636/639
FIGURE 7-4:
COMPARATOR I/O OPERATING MODES FOR PIC16F636/639
Comparator Reset (POR Default Value)
CM<2:0> = 000
Comparators Off (Lowest Power)(1)
CM<2:0> = 111
A
D
VIN-
VIN-
RA1
RA0
RA1
RA0
Off (Read as ‘0’)
Off (Read as ‘0’)
Off (Read as ‘0’)
Off (Read as ‘0’)
C1
C2
C1
C2
VIN+
VIN+
A
D
A
A
D
D
VIN-
VIN-
RC1
RC0
RC1
RC0
VIN+
VIN+
Four Inputs Multiplexed to Two Comparators
Two Independent Comparators
CM<2:0> = 010
CM<2:0> = 100
A
A
VIN-
RA1
RA1
RA0
CIS = 0
CIS = 1
VIN-
A
C1OUT
C2OUT
C1
C2
VIN+
A
RA0
C1OUT
C2OUT
C1
C2
VIN+
A
A
RC1
RC0
VIN-
CIS = 0
CIS = 1
A
A
VIN-
RC1
RC0
VIN+
VIN+
From CVREF Module
Two Common Reference Comparators
CM<2:0> = 011
Two Common Reference Comparators with Outputs
CM<2:0> = 110
A
A
VIN-
VIN-
RA1
RA0
RA1
C1OUT
C2OUT
C1OUT
C2OUT
C1
C2
C1
C2
VIN+
VIN+
D
D
RA2/C1OUT
A
A
A
A
VIN-
VIN-
RC1
RC0
RC1
RC0
VIN+
VIN+
RC4/C2OUT
One Independent Comparator
CM<2:0> = 101
Three Inputs Multiplexed to Two Comparators
CM<2:0> = 001
D
VIN-
A
RA1
RA0
RA1
CIS = 0
CIS = 1
VIN-
Off (Read as ‘0’)
C1
C2
VIN+
D
A
RA0
C1OUT
C2OUT
C1
C2
VIN+
A
A
VIN-
A
A
VIN-
RC1
RC0
RC1
RC0
C2OUT
VIN+
VIN+
A = Analog Input, ports always read ‘0’
CIS = Comparator Input Switch (CMCON0<3>)
Legend:
D = Digital Input
DS41232B-page 64
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 7-5:
PIC12F635 COMPARATOR C1 OUTPUT BLOCK DIAGRAM
C1INV
C1SYNC
To TMR1
0
To C1OUT pin
1
Q
Q
D
TMR1
Clock Source
EN
(1)
To Data Bus
D
EN
RD CMCON
Set C2IF bit
Q
D
RD CMCON
EN
CL
Reset
Note 1: Comparator 1 output is latched on falling edge of T1 clock source.
FIGURE 7-6:
PIC16F636/639 COMPARATOR C1 OUTPUT BLOCK DIAGRAM
C1INV
To C1OUT pin
To Data Bus
Q
D
EN
RD CMCON
Set C1IF bit
Q
D
RD CMCON
EN
CL
NRESET
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 65
PIC12F635/PIC16F636/639
FIGURE 7-7:
PIC16F636/639 COMPARATOR C2 OUTPUT BLOCK DIAGRAM
C2INV
C2SYNC
To TMR1
0
To C2OUT pin
1
Q
Q
D
TMR1
Clock Source
EN
(1)
To Data Bus
D
EN
RD CMCON
Set C2IF bit
Q
D
RD CMCON
EN
CL
Reset
Note 1: Comparator 2 output is latched on falling edge of T1 clock source.
REGISTER 7-2:
CMCON1 – COMPARATOR CONTROL 1 REGISTER (ADDRESS: 1Ah)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
(1)
—
—
—
—
—
—
T1GSS
C2SYNC
bit 7
bit 0
bit 7-2:
bit 1
Unimplemented: Read as ‘0’
T1GSS: Timer1 Gate Source Select bit
1= Timer1 gate source is T1G pin (RA4 must be configured as digital input)
0= Timer1 gate source is Comparator 2 output
(2)
bit 0
C2SYNC: Comparator 2 Synchronize bit
1= C2 output synchronized with falling edge of Timer1 clock
0= C2 output not synchronized with Timer1 clock
Note 1: C2SYNC is C1SYNC in PIC12F635.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS41232B-page 66
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
The CxIE bits (PIE1<4:3>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupts. In
addition, the GIE bit must also be set. If any of these
bits are cleared, the interrupt is not enabled, though the
CxIF bits will still be set if an interrupt condition occurs.
7.4
Comparator Outputs
The comparator outputs are read through the
CMCON0 register. These bits are read-only. The
comparator outputs may also be directly output to the
RA2 and RC4 I/O pins. When enabled, multiplexers in
the output path of the RA2 and RC4 pins will switch
and the output of each pin will be the unsynchronized
output of the comparator. The uncertainty of each of
the comparators is related to the input offset voltage
and the response time given in the specifications.
Figure 7-5 and Figure 7-6 show the output block
diagrams for Comparator 1 and 2.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON0. This will end the
mismatch condition.
b) Clear flag bits CxIF.
A mismatch condition will continue to set flag bits CxIF.
Reading CMCON0 will end the mismatch condition and
allow flag bits CxIF to be cleared.
The TRIS bits will still function as an output enable/
disable for the RA2 and RC4 pins while in this mode.
Note:
If a change in the CMCON0 register
(CxOUT) should occur when a read
operation is being executed (start of the
Q2 cycle), then the CxIF (PIR1<4:3>)
interrupt flags may not get set.
The polarity of the comparator outputs can be changed
using the C1INV and C2INV bits (CMCON0<5:4>).
Timer1 gate source can be configured to use the T1G
pin or Comparator 2 output as selected by the T1GSS bit
(CMCON1<1>). This feature can be used to time the
duration or interval of analog events. The output of
Comparator 2 can also be synchronized with Timer1 by
setting the C2SYNC bit (CMCON1<0>). When enabled,
the output of Comparator 2 is latched on the falling edge
of the Timer1 clock source. If a prescaler is used with
Timer1, Comparator 2 is latched after the prescaler. To
prevent a race condition, the Comparator 2 output is
latched on the falling edge of the Timer1 clock source
and Timer1 increments on the rising edge of its clock
source. See Figure 7-6, Comparator C2 Output Block
Diagram and Figure 5-1, Timer1 on the PIC12F635/
PIC16F636/639 Block Diagram for more information.
It is recommended to synchronize Comparator 2 with
Timer1 by setting the C2SYNC bit when Comparator 2
is used as the Timer1 gate source. This ensures Timer1
does not miss an increment if Comparator 2 changes
during an increment.
7.5
Comparator Interrupts
The comparator interrupt flags are set whenever there
is a change in the output value of its respective
comparator. Software will need to maintain information
about the status of the output bits, as read from
CMCON0<7:6>, to determine the actual change that
has occurred. The CxIF bits (PIR1<4:3>) are the
Comparator Interrupt Flags. These bits must be reset in
software by clearing them to ‘0’. Since it is also possible
to write a ‘1’ to this register, a simulated interrupt may
be initiated.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 67
PIC12F635/PIC16F636/639
EQUATION 7-1:
7.6
Comparator Reference
The comparator module also allows the selection of an
internally generated voltage reference for one of the
comparator inputs. The VRCON register (Register 7-3)
controls the voltage reference module shown in
Figure 7-8.
VRR = 1 (low range): CVREF = (VR<3:0>/24) x VDD
VRR = 0 (high range):
CVREF = (VDD/4) + (VR<3:0> x VDD/32)
7.6.2
VOLTAGE REFERENCE
ACCURACY/ERROR
7.6.1
CONFIGURING THE VOLTAGE
REFERENCE
The voltage reference is VDD derived and therefore, the
CVREF output changes with fluctuations in VDD. The
tested absolute accuracy of the comparator voltage
reference can be found in Section 15.0 “Electrical
Specifications”.
The voltage reference can output 32 distinct voltage
levels, 16 in a high range and 16 in a low range.
The following equation determines the output voltages:
FIGURE 7-8:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
8R
R
R
R
R
VDD
VRR
8R
16-1 Analog
MUX
VREN
CVREF to
Comparator
Input
VR<3:0>
DS41232B-page 68
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
While the comparator is enabled during Sleep, an
interrupt will wake-up the device. If the GIE bit
7.7
Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is ensured to have a valid level. If
the internal reference is changed, the maximum delay
of the internal voltage reference must be considered
when using the comparator outputs. Otherwise, the
maximum delay of the comparators should be used
(Table 15-7).
(INTCON<7>) is set, the device will jump to the
interrupt vector (0004h) and if clear, continues
execution with the next instruction. If the device wakes
up from Sleep, the contents of the CMCON0, CMCON1
and VRCON registers are not affected.
7.9
Effects of a Reset
A device Reset forces the CMCON0, CMCON1 and
VRCON registers to their Reset states. This forces the
comparator module to be in the Comparator Reset
mode, CM<2:0> = 000and the voltage reference to its
OFF state. Thus, all potential inputs are analog inputs
with the comparator and voltage reference disabled to
consume the smallest current possible.
7.8
Operation During Sleep
The comparators and voltage reference, if enabled
before entering Sleep mode, remain active during
Sleep. This results in higher Sleep currents than shown
in the power-down specifications. The additional
current consumed by the comparator and the voltage
reference is shown separately in the specifications. To
minimize power consumption while in Sleep mode, turn
off the comparator, CM<2:0> = 111 and voltage
reference, VRCON<7> = 0.
REGISTER 7-3:
VRCON – VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)
R/W-0
VREN
U-0
—
R/W-0
VRR
R/W-0
—
R/W-0
VR3
R/W-0
VR2
R/W-0
VR1
R/W-0
VR0
bit 7
bit 0
bit 7
VREN: CVREF Enable bit
1= CVREF circuit powered on
0= CVREF circuit powered down, no IDD drain and CVREF = VSS
bit 6
bit 5
Unimplemented: Read as ‘0’
VRR: CVREF Range Selection bit
1= Low range
0= High range
bit 4
Unimplemented: Read as ‘0’
bit 3-0
VR<3:0>: CVREF Value Selection bits 0 ≤ VR<3:0> ≤ 15
When VRR = 1:
CVREF = (VR<3:0>/24) * VDD
When VRR = 0:
CVREF = VDD/4 + (VR<3:0>/32) * VDD
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 69
PIC12F635/PIC16F636/639
NOTES:
DS41232B-page 70
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
8.1
Voltage Trip Points
8.0
PROGRAMMABLE
LOW-VOLTAGE DETECT
(PLVD) MODULE
The PIC12F635/PIC16F636/639 device supports eight
internal PLVD trip points. See Register 8-1 for available
PLVD trip point voltages.
The Programmable Low-Voltage Detect module is an
interrupt driven supply level detection. The voltage
detection monitors the internal power supply.
REGISTER 8-1:
LVDCON – LOW-VOLTAGE DETECT CONTROL REGISTER (ADDRESS: 94h)
U-0
—
U-0
—
R-0
R/W-0
U-0
—
R/W-1
LVDL2
R/W-0
LVDL1
R/W-0
LVDL0
IRVST
LVDEN
bit 7
bit 0
bit 7-6
bit 5
Unimplemented: Read as ‘0’
IRVST: Internal Reference Voltage Stable Status Flag bit
1= Indicates that the PLVD is stable and PLVD interrupt is reliable
0= Indicates that the PLVD is not stable and PLVD interrupt should not be enabled
bit 4
LVDEN: Low-Voltage Detect Power Enable bit
1= Enables PLVD, powers up PLVD circuit and supporting reference circuitry
0= Disables PLVD, powers down PLVD and supporting circuitry
bit 3
Unimplemented: Read as ‘0’
bit 2-0
LVDL<2:0>: Low-Voltage Detection Limit bits (nominal values)
111= 4.5V
110= 4.2V
101= 4.0V
100= 2.3V (default)
011= 2.2V
010= 2.1V
001= 2.0V
000= 1.9V(1)
Note 1: Not tested and below minimum VDD.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
TABLE 8-1:
REGISTERS ASSOCIATED WITH PROGRAMMABLE LOW-VOLTAGE DETECT
Value on
POR, BOD,
WUR
Value on
all other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
94h
LVDCON
—
—
IRVST LVDEN
—
LVDL2 LVDL1 LVDL0 --00 -000 --00 -000
0Bh/8Bh INTCON
GIE
PEIE
LVDIF
LVDIE
T0IE
CRIF
CRIE
INTE
C2IF
RAIE
C1IF
C1IE
T0IF
INTF
—
RAIF
0000 0000 0000 0000
0Ch
PIR1
PIE1
EEIF
EEIE
OSFIF
OSFIE
TMR1IF 0000 00-0 0000 00-0
TMR1IE 0000 00-0 0000 00-0
(1)
8Ch
C2IE
—
Legend:
x= unknown, u= unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the comparator or
comparator voltage reference module.
Note 1: PIC16F636/639 only.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 71
PIC12F635/PIC16F636/639
NOTES:
DS41232B-page 72
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
9.0
DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during normal operation (full VDD range). This memory
is not directly mapped in the register file space.
Instead, it is indirectly addressed through the Special
Function Registers. There are four SFRs used to read
and write this memory:
writes the new data (erase before write). The EEPROM
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The write
time will vary with voltage and temperature as well as
from chip-to-chip. Please refer to A/C specifications in
Section 15.0 “Electrical Specifications” for exact
limits.
• EECON1
• EECON2 (not a physically implemented register)
When the data memory is code-protected, the CPU
may continue to read and write the data EEPROM
memory. The device programmer can no longer access
the data EEPROM data and will read zeroes.
• EEDAT
• EEADR
EEDAT holds the 8-bit data for read/write and EEADR
holds the address of the EEPROM location being
accessed. PIC16F636/639 has 256 bytes of data
EEPROM and the PIC12F635 has 64 bytes.
Additional information on the data EEPROM is
available in the “PICmicro® Mid-Range MCU Family
Reference Manual” (DS33023).
REGISTER 9-1:
EEDAT – EEPROM DATA REGISTER (ADDRESS: 9Ah)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EEDAT7
EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0
bit 0
bit 7
bit 7-0
EEDATn: Byte Value to Write to or Read From Data EEPROM bits
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
REGISTER 9-2:
EEADR – EEPROM ADDRESS REGISTER (ADDRESS: 9Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EEADR7(1) EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0
R/W-0
R/W-0
bit 7
bit 0
bit 7-0
EEADR: Specifies 1 of 256 Locations for EEPROM Read/Write Operation bits
Note 1: PIC16F636/639 only. Read as ‘0’ on PIC12F635.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 73
PIC12F635/PIC16F636/639
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset during normal
operation. In these situations, following Reset, the user
can check the WRERR bit, clear it and rewrite the
location. The data and address will be cleared.
Therefore, the EEDAT and EEADR registers will need
to be re-initialized.
9.1
EECON1 AND EECON2 Registers
EECON1 is the control register with four low-order bits
physically implemented. The upper four bits are non-
implemented and read as ‘0’s.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
Interrupt flag, EEIF bit (PIR1<7>), is set when write is
complete. This bit must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the data EEPROM write sequence.
Note:
The EECON1, EEDAT and EEADR
registers should not be modified during a
data EEPROM write (WR bit = 1).
REGISTER 9-3:
EECON1 – EEPROM CONTROL 1 REGISTER (ADDRESS: 9Ch)
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
WRERR
bit 7
bit 0
bit 7-4
bit 3
Unimplemented: Read as ‘0’
WRERR: EEPROM Error Flag bit
1= A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during
normal operation or BOD detect)
0= The write operation completed
bit 2
bit 1
WREN: EEPROM Write Enable bit
1= Allows write cycles
0= Inhibits write to the data EEPROM
WR: Write Control bit
1= Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit
can only be set, not cleared, in software.)
0= Write cycle to the data EEPROM is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit
can only be set, not cleared, in software.)
0= Does not initiate an EEPROM read
Legend:
S = Bit can only be set
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS41232B-page 74
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
9.2
Reading the EEPROM Data
Memory
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1<0>), as shown in Example 9-1. The data
is available, in the very next cycle, in the EEDAT
register. Therefore, it can be read in the next
instruction. EEDAT holds this value until another read,
or until it is written to by the user (during a write
operation).
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit
(PIR1<7>) must be cleared by software.
9.4
Write Verify
Depending on the application, good programming
practice may dictate that the value written to the data
EEPROM should be verified (see Example 9-3) to the
desired value to be written.
EXAMPLE 9-1:
DATA EEPROM READ
BSF
BCF
STATUS,RP0
STATUS,RP1
;Bank 1
;
;
;Address to read
;EE Read
;Move data to W
MOVLW
MOVWF
BSF
CONFIG_ADDR
EEADR
EECON1,RD
EEDAT,W
EXAMPLE 9-3:
WRITE VERIFY
BSF
STATUS,RP0 ;Bank 1
MOVF
BCF
MOVF
STATUS,RP1
EEDAT,W
;
;EEDAT not changed
;from previous write
;YES, Read the
;value written
9.3
Writing to the EEPROM Data
Memory
BSF
EECON1,RD
XORWF EEDAT,W
BTFSS STATUS,Z
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDAT register. Then the user must follow a
specific sequence to initiate the write for each byte, as
shown in Example 9-2.
;Is data the same
;No, handle error
;Yes, continue
GOTO
:
WRITE_ERR
9.4.1
USING THE DATA EEPROM
high-endurance, byte
EXAMPLE 9-2:
DATA EEPROM WRITE
The data EEPROM is
a
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
STATUS,RP0
STATUS,RP1
EECON1,WREN
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON,GIE
;Bank 1
;
;Enable write
;Disable INTs
;Unlock write
;
;
;
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated often).
The maximum endurance for any EEPROM cell is
specified as D120. D124 specifies a maximum number
of writes to any EEPROM location before a refresh is
required of infrequently changing memory locations.
;Start the write
;Enable INTS
9.4.2
EEPROM ENDURANCE
BSF
As an example, hypothetically, a data EEPROM is
64 bytes long and has an endurance of 1M writes. It
also has a refresh parameter of 10M writes. If every
memory location in the cell were written the maximum
number of times, the data EEPROM would fail after
64M write cycles. If every memory location, save 1,
were written the maximum number of times, the data
EEPROM would fail after 63M write cycles, but the one
remaining location could fail after 10M cycles. If proper
refreshes occurred, then the lone memory location
would have to be refreshed 6 times for the data to
remain correct.
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will
prevent the data from being written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 75
PIC12F635/PIC16F636/639
9.5
Protection Against Spurious Write
9.6
Data EEPROM Operation During
Code Protection
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up Timer (nominal 64 ms duration) prevents
EEPROM write.
Data memory can be code-protected by programming
the CPD bit in the Configuration Word (Register 12-1)
to ‘0’.
When the data memory is code-protected, the CPU is
able to read and write data to the data EEPROM. It is
recommended to code-protect the program memory
when code-protecting data memory. This prevents
anyone from programming zeroes over the existing
code (which will execute as NOPs) to reach an added
routine, programmed in unused program memory,
which outputs the contents of data memory.
Programming unused locations in program memory to
‘0’ will also help prevent data memory code protection
from becoming breached.
The write initiate sequence and the WREN bit together
help prevent an accidental write during:
• Brown-out
• Power glitch
• Software malfunction
TABLE 9-1:
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Value on
POR, BOD,
WUR
Value on
all other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh/8Bh INTCON
GIE
EEIF
EEIE
PEIE
LVDIF
LVDIE
T0IE
CRIF
CRIE
INTE
RAIE
C1IF
C1IE
T0IF
INTF
—
RAIF 0000 0000 0000 0000
TMR1IF 0000 00-0 0000 00-0
TMR1IE 0000 00-0 0000 00-0
(1)
0Ch
PIR1
C2IF
C2IE
OSFIF
OSFIE
(1)
8Ch
PIE1
—
9Ah
EEDAT
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000
(1)
9Bh
EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000
9Ch
EECON1
—
—
—
—
WRERR WREN
WR
RD
---- x000 ---- q000
---- ---- ---- ----
9Dh
EECON2 EEPROM Control Register 2 (not a physical register)
Legend:
x= unknown, u= unchanged, — = unimplemented read as ‘0’, q= value depends upon condition.
Shaded cells are not used by the data EEPROM module.
Note 1: PIC16F636/639 only.
DS41232B-page 76
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
®
10.0 KEELOQ COMPATIBLE
CRYPTOGRAPHIC MODULE
To obtain information regarding the implementation of
the KEELOQ module, Microchip Technology requires
®
the execution of the “KEELOQ Encoder License
Agreement”.
®
The “KEELOQ Encoder License Agreement” may be
accessed through the Microchip web site located at
www.microchip.com/KEELOQ. Further information may
be obtained by contacting your local Microchip Sales
Representative.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 77
PIC12F635/PIC16F636/639
NOTES:
DS41232B-page 78
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
11.2 Modulation Circuit
11.0 ANALOG FRONT-END (AFE)
FUNCTIONAL DESCRIPTION
(PIC16F639 ONLY)
The modulation circuit consists of a modulation
transistor (FET), internal tuning capacitors and external
LC antenna components. The modulation transistor
The PIC16F639 device consists of the PIC16F636
device and low frequency (LF) Analog Front-End
(AFE), with the AFE section containing three analog-
input channels for signal detection and LF talk-back.
This section describes the Analog Front-End (AFE) in
detail.
and the internal tuning capacitors are connected
between the LC input pin and LCCOM pin. Each LC
input has its own modulation transistor.
When the modulation transistor turns on, its low Turn-on
Resistance (RM) clamps the induced LC antenna
voltage. The coil voltage is minimized when the
modulation transistor turns-on and maximized when the
modulation transistor turns-off. The modulation
transistor’s low Turn-on Resistance (RM) results in a
high modulation depth.
The PIC16F639 device can detect a 125 kHz input
signal as low as 1 mVpp and transmit data by using
internal LF talk-back modulation or via an external
transmitter. The PIC16F639 can also be used for
various bidirectional communication applications.
Figure 11-3 and Figure 11-4 show application examples
of the device.
The LF talk-back is achieved by turning on and off the
modulation transistor.
The modulation data comes from the microcontroller
section via the digital SPI interface as “Clamp On”,
“Clamp Off” commands. Only those inputs that are
enabled will execute the clamp command. A basic
block diagram of the modulation circuit is shown in
Figure 11-1 and Figure 11-2.
Each analog input channel has internal tuning
capacitance, sensitivity control circuits, an input signal
strength limiter and an LF talk-back modulation
transistor. An Automatic Gain Control (AGC) loop is
used for all three input channel gains. The output of
each channel is OR'd and fed into a demodulator. The
digital output is passed to the LFDATA pin. Figure 11-1
shows the block diagram of the AFE and Figure 11-2
shows the LC input path.
The modulation FET is also shorted momentarily after
Soft Reset and Inactivity timer time-out.
11.3 Tuning Capacitor
There are a total of eight Configuration registers. Six of
them are used for AFE operation options, one for
column parity bits and one for status indication of AFE
operation. Each register has 9 bits including one row
parity bit. These registers are readable and writable by
SPI (Serial Protocol Interface) commands except for
the Status register, which is read-only.
Each channel has internal tuning capacitors for external
antenna tuning. The capacitor values are programmed
by the Configuration registers up to 63 pF, 1 pF per step.
Note:
The user can control the tuning capacitor
by programming the AFE Configuration
registers.
11.1 RF Limiter
11.4 Variable Attenuator
The RF Limiter limits LC pin input voltage by de-Q’ing
the attached LC resonant circuit. The absolute voltage
limit is defined by the silicon process’s maximum
allowed input voltage (see Section 15.0 “Electrical
Specifications”). The limiter begins de-Q’ing the
external LC antenna when the input voltage exceeds
VDE_Q, progressively de-Q’ing harder to reduce the
antenna input voltage.
The variable attenuator is used to attenuate, via AGC
control, the input signal voltage to avoid saturating the
amplifiers and demodulators.
Note:
The variable attenuator function is
accomplished by the device itself. The
user cannot control its function.
The signal levels from all 3 channels are combined
such that the limiter attenuates all 3 channels
uniformly, in respect to the channel with the strongest
signal.
11.5 Sensitivity Control
The sensitivity of each channel can be reduced by the
channel’s Configuration register sensitivity setting.
This is used to desensitize the channel from optimum.
Note:
The user can desensitize the channel
sensitivity by programming the AFE
Configuration registers.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 79
PIC12F635/PIC16F636/639
11.6 AGC Control
11.10 Demodulator
The AGC controls the variable attenuator to limit the
internal signal voltage to avoid saturation of internal
amplifiers and demodulators (Refer to Section 11.4
“Variable Attenuator”).
The Demodulator consists of a full-wave rectifier, low
pass filter, peak detector and Data Slicer that detects
the envelope of the input signal.
11.11 Data Slicer
The signal levels from all 3 channels are combined
such that AGC attenuates all 3 channels uniformly in
respect to the channel with the strongest signal.
The Data Slicer consists of a reference generator and
comparator. The Data Slicer compares the input with
the reference voltage. The reference voltage comes
from the minimum modulation depth requirement
setting and input peak voltage. The data from all 3
channels are OR’d together and sent to the output
enable filter.
Note:
The AGC control function is accomplished
by the device itself. The user cannot
control its function.
11.7 Fixed Gain Amplifiers 1 and 2
FGA1 and FGA2 provides a maximum two-stage gain
of 40 dB.
11.12 Output Enable Filter
The Output Enable Filter enables the LFDATA output
once the incoming signal meets the wake-up sequence
requirements (see Section 11.15 “Configurable
Output Enable Filter”).
Note:
The user cannot control the gain of these
two amplifiers.
11.8 Auto Channel Selection
11.13 RSSI (Received Signal Strength
Indicator)
The Auto Channel Selection feature is enabled if the
Auto Channel Select bit AUTOCHSEL<8> in Configu-
ration Register 5 (Register 11-6) is set, and disabled if
the bit is cleared. When this feature is active (i.e.,
AUTOCHSE <8> = 1), the control circuit checks the
demodulator output of each input channel immediately
after the AGC settling time (TSTAB). If the output is high,
it allows this channel to pass data, otherwise it is
blocked.
The RSSI provides a current which is proportional to the
input signal amplitude (see Section 11.31.3 “Received
Signal Strength Indicator (RSSI) Output”).
11.14 Analog Front-End Timers
The AFE has an internal 32 kHz RC oscillator. The
oscillator is used in several timers:
The status of this operation is monitored by AFE Status
Register 7 bits <8:6> (Register 11-8). These bits indicate
the current status of the channel selection activity, and
automatically updates for every Soft Reset period. The
auto channel selection function resets after each Soft
Reset (or after Inactivity timer time-out). Therefore, the
blocked channels are reenabled after Soft Reset.
• Inactivity timer
• Alarm timer
• Pulse Width timer
• Period timer
• AGC settling timer
11.14.1 RC OSCILLATOR
This feature can make the output signal cleaner by
blocking any channel that was not high at the end of
TAGC. This function works only for demodulated data
output, and is not applied for carrier clock or RSSI
output.
The RC oscillator is low power, 32 kHz ± 10% over
temperature and voltage variations.
11.9 Carrier Clock Detector
The Detector senses the input carrier cycles. The
output of the Detector switches digitally at the signal
carrier frequency. Carrier clock output is available
when the output is selected by the DATOUT bit in the
AFE Configuration Register 1 (Register 11-2).
DS41232B-page 80
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
The timer is reset when the:
11.14.2 INACTIVITY TIMER
• CS pin is low (any SPI command).
• Output enable filter is disabled.
The Inactivity Timer is used to automatically return the
AFE to Standby mode, if there is no input signal. The
time-out period is approximately 16 ms (TINACT), based
on the 32 kHz internal clock.
• LFDATA pin is enabled (signal passed output
enable filter).
The purpose of the Inactivity Timer is to minimize AFE
current draw by automatically returning the AFE to the
lower current Standby mode, if there is no input signal
for approximately 16 ms.
The timer starts when:
• Receiving a LF signal.
The timer causes a low output on the ALERT pin when:
The timer is reset when:
• Output enable filter is enabled and modulated
input signal is present for TALARM, but does not
pass the output enable filter requirement.
• An amplitude change in LF input signal, either
high-to-low or low-to-high
• CS pin is low (any SPI™ command)
Note:
The Alarm timer is disabled if the output
enable filter is disabled.
• Timer-related Soft Reset
The timer starts when:
11.14.4 PULSE WIDTH TIMER
• AFE receives any LF signal
The timer causes an AFE Soft Reset when:
The Pulse Width Timer is used to verify that the
received output enable sequence meets both the
minimum TOEH and minimum TOEL requirements.
• A previously received LF signal does not change
either high-to-low or low-to-high for TINACT
11.14.5 PERIOD TIMER
The Soft Reset returns the AFE to Standby mode where
most of the analog circuits, such as the AGC,
demodulator and RC oscillator, are powered down. This
returns the AFE to the lower Standby Current mode.
The Period Timer is used to verify that the received
output enable sequence meets the maximum TOET
requirement.
11.14.6 AGC SETTLING TIMER (TAGC)
11.14.3 ALARM TIMER
This timer is used to keep the output enable filter in
Reset while the AGC settles on the input signal. The
time-out period is approximately 3.5 ms. At end of this
time (TAGC), the input should remain high (TPAGC),
otherwise the counting is aborted and a Soft Reset is
issued. See Figure 11-6 for details.
The Alarm Timer is used to notify the MCU that the AFE
is receiving LF signal that does not pass the output
enable filter requirement. The time-out period is
approximately 32 ms (TALARM) in the presence of
continuing noise.
The Alarm Timer time-out occurs if there is an input
signal for longer than 32 ms that does not meet the
output enable filter requirements. The Alarm Timer
time-out causes:
Note 1: The AFE needs continuous and
uninterrupted high input signal during
AGC settling time (TAGC). Any absence of
signal during this time may reset the timer
and a new input signal is needed for AGC
settling time, or may result in improper
AGC gain settings which will produce
invalid output.
a) The ALERT pin to go low.
b) The ALARM bit to set in the AFE Status
Configuration 7 register (Register 11-8).
The MCU is informed of the Alarm timer time-out by
monitoring the ALERT pin. If the Alarm timer time-out
occurs, the MCU can take appropriate actions such as
lowering channel sensitivity or disabling channels. If
the noise source is ignored, the AFE can return to a
lower standby current draw state.
2: The rest of the AFE section wakes up if any
of these input channels receive the AGC
settling time correctly. AFE Status Register
7 bits <4:2> (Register 11-8) indicate which
input channels have waken up the AFE
first. Valid input signal on multiple input pins
can cause more than one channel's
indicator bit to be set.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 81
PIC12F635/PIC16F636/639
FIGURE 11-1:
FUNCTIONAL BLOCK DIAGRAM – ANALOG FRONT-END
÷ 64
AGC
LCX
Detector
WAKEX
Tune X
RF
Lim
Sensitivity
Control X
Mod
A
÷ 64
LCCOM
WAKEY
AGC
LCY
Σ
Detector
WAKEZ
Tune Y
RF
Lim
Sensitivity
Control Y
Mod
A
LCCOM
÷ 64
AGC
LCZ
Detector
Tune Z
RF
Lim
Sensitivity
Control Z
Watchdog
Mod
A
B
Modulation
Depth
To Sensitivity X
32 kHZ
Oscillator
AGC
Timer
Output Enable
Filter
LCCOM
To Sensitivity Y
To Sensitivity Z
AGC Preserve
Command Decoder/Controller
To Modulation
Transistors
To Tuning Cap X
To Tuning Cap Y
To Tuning Cap Z
Configuration
Registers
RSSI
SCLK/ALERT
CS
LFDATA/RSSI/
CCLK/SDIO
VSST
VDDT
MCU
DS41232B-page 82
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 11-2:
LC INPUT PATH
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 83
PIC12F635/PIC16F636/639
FIGURE 11-3:
BIDIRECTIONAL PASSIVE KEYLESS ENTRY (PKE) SYSTEM APPLICATION EXAMPLE
d
e
s
t
e
p
d
y
o
r
C
c
n
E
e
s
)
n
F
o
H
p
U
s
(
e
R
LED
LED
UHF
Transmitter
UHF
Receiver
Ant. X
Ant. Y
Ant. Z
d
n
a
H
m
k
m
5
o
2
C
1
F
(
L
PIC16F639
)
z
MCU
(PIC16F636)
LF
+
Transmitter/
Receiver
3 Input
Analog Front-End
Base Station
Transponder
FIGURE 11-4:
PASSIVE KEYLESS ENTRY (PKE) TRANSPONDER CONFIGURATION EXAMPLE
+3V
315 MHz
VDD
VSS
1
20
19
18
+3V
+3V
S0
S3
2
S1
S4
3
S2
S5
4
17
16
RF Circuitry
LED
Data
5
(UHF TX)
RFEN
CS
6
15
14
13
12
11
LFDATA/RSSI/CCLK/SDIO
SCLK/ALERT
VSST
LCCOM
LCZ
7
+3V
VDDT
LCX
LCY
8
9
10
air-core
coil
ferrite-core
coil
ferrite-core
coil
DS41232B-page 84
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
11.15 Configurable Output Enable Filter
The purpose of this filter is to enable the LFDATA output
and wake the microcontroller only after receiving a
specific sequence of pulses on the LC input pins.
Therefore, it prevents the AFE from waking up the
microcontroller due to noise or unwanted input signals.
The circuit compares the timing of the demodulated
header waveform with a pre-defined value, and enables
the demodulated LFDATA output when a match occurs.
The output enable filter consists of a high (TOEH) and
low duration (TOEL) of a pulse immediately after the
AGC settling gap time. The selection of high and low
times further implies a max period time. The output
enable high and low times are determined by SPI
interface programming. Figure 11-5 and Figure 11-6
show the output enable filter waveforms.
There should be no missing cycles during TOEH.
Missing cycles may result in failing the output enable
condition.
FIGURE 11-5:
OUTPUT ENABLE FILTER TIMING
Required Output Enable Sequence
Data Packet
Start bit
TSTAB
(TAGC + TPAGC)
Demodulator
Output
TGAP
t ≥ TOEH
t ≥ TOEL
AGC
Gap Pulse
AFE Wake-up
and AGC Stabilization
LFDATA output is enabled
on this rising edge
t
≤ TOET
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 85
PIC12F635/PIC16F636/639
FIGURE 11-6:
OUTPUT ENABLE FILTER TIMING EXAMPLE (DETAILED)
Start bit
LFDATA Output
LF Coil Input
3.5 ms
TPAGC
TGAP
Gap
Pulse
Low
t ≥ TOEL
t ≥ TE
Current
Standby
Mode
(need
“high”)
TAGC
(AGC settling time)
t ≥ TOEH
t ≤ TOET
TSTAB
(AFE Stabilization)
Filter
starts
Filter is passed and
LFDATA is enabled
Legend:
TAGC = AGC stabilization time
TE = Time element of pulse
TGAP = AGC stabilization gap
TOEH = Minimum output enable filter high time
TOEL = Minimum output enable filter low time
TOET = Maximum output enable filter period
TPAGC = High time after TAGC
TSTAB = TAGC + TPAGC
DS41232B-page 86
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
If the filter resets due to a long high (TOEH > TOET), the
high-pulse timer will not begin timing again until after a
gap of TE and another low-to-high transition occurs on
TABLE 11-1: TYPICAL OUTPUT ENABLE
FILTER TIMING
OEH
OEL
TOEH
(ms)
TOEL
(ms)
TOET
the demodulator output.
<1:0>
<1:0>
(ms)
Disabling the output enable filter disables the TOEH and
TOEL requirement and the AFE passes all received LF
data. See Figure 11-10, Figure 11-11 and Figure 11-12
for examples.
01
01
01
01
00
01
10
11
1
1
1
1
1
1
2
4
3
3
4
6
When viewed from an application perspective, from the
pin input, the actual output enable filter timing must fac-
tor in the analog delays in the input path (such as
demodulator charge and discharge times).
10
10
10
10
00
01
10
11
2
2
2
2
1
1
2
4
4
4
5
8
• TOEH - TDR + TDF
• TOEL + TDR - TDF
The output enable filter starts immediately after TGAP,
the gap after AGC stabilization period.
11
11
11
11
00
01
10
11
4
4
4
4
1
1
2
4
6
6
11.16 Input Sensitivity Control
8
10
The AFE is designed to have typical input sensitivity of
3 mVPP. This means any input signal with amplitude
greater than 3 mVPP can be detected. The AFE’s internal
AGC loop regulates the detecting signal amplitude when
the input level is greater than approximately 20 mVPP.
This signal amplitude is called “AGC-active level”. The
AGC loop regulates the input voltage so that the input
signal amplitude range will be kept within the linear range
of the detection circuits without saturation. The AGC
Active Status bit (AGCACT<5>) in the AFE Status
Register 7 (Register 11-8) is set if the AGC loop
regulates the input voltage.
00
XX
Filter Disabled
Note 1: Typical at room temperature and
VDD = 3.0V, 32 kHz oscillator.
TOEH is measured from the rising edge of the demodulator
output to the first falling edge. The pulse width must fall
within TOEH ≤ t ≤ TOET.
TOEL is measured from the falling edge of the
demodulator output to the rising edge of the next pulse.
The pulse width must fall within TOEL ≤ t ≤ TOET.
Table 11-2 shows the input sensitivity comparison when
the AGCSIG option is used. When AGCSIG option bit is
set, the demodulated output is available only when the
AGC loop is active (see Table 11-1). The AFE has also
input sensitivity reduction options per each channel. The
Configuration Register 3 (Register 11-4), Configuration
Register 4 (Register 11-5) and Configuration Register 5
(Register 11-6) have the option to reduce the channel
gains from 0 dB to approximately -30 dB.
TOET is measured from rising edge to the next rising
edge (i.e., the sum of TOEH and TOEL). The pulse width
must be t ≤ TOET. If the Configuration Register 0
(Register 11-1), OEL<8:7> is set to ‘00’, then TOEH
must not exceed TOET and TOEL must not exceed
TINACT.
The filter will reset, requiring a complete new successive
high and low period to enable LFDATA, under the
following conditions.
• The received high is not greater than the
configured minimum TOEH value.
• During TOEH, a loss of signal > 56 μs. A loss of
signal < 56 μs may or may not cause a filter
Reset.
• The received low is not greater than the
configured minimum TOEL value.
• The received sequence exceeds the maximum
TOET value:
- TOEH + TOEL > TOET
- or TOEH > TOET
- or TOEL > TOET
• A Soft Reset SPI command is received.
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Preliminary
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TABLE 11-2: INPUT SENSITIVITY VS. MODULATED SIGNAL STRENGTH SETTING (AGCSIG <7>)
Input
Sensitivity
(Typical)
AGCSIG<7>
(Config. Register 5)
Description
0
Disabled – the AFE passes signal of any amplitude level it is capable of
detecting (demodulated data and carrier clock).
3.0 mVPP
1
Enabled – No output until AGC Status = 1(i.e., VPEAK ≈ 20 mVPP)
(demodulated data and carrier clock).
20 mVPP
• Provides the best signal to noise ratio.
11.17 Input Channels (Enable/Disable)
11.19 AGC Preserve
Each channel can be individually enabled or disabled
by programming bits in Configuration Register 0<3:1>
(Register 11-1).
The AGC preserve feature allows the AFE to preserve
the AGC value during the AGC settling time (TAGC) and
apply the value to the data slicing circuit for the following
data streams instead of using a new tracking value. This
feature is useful to demodulate the input signal correctly
when the input has random amplitude variations at a
given time period. This feature is enabled when the AFE
receives an AGC Preserve On command and disabled
if it receives an AGC Preserve Off command. Once the
AGC Preserve On command is received, the AFE
acquires a new AGC value during each AGC settling
time and preserves the value until a Soft Reset or an
AGC Preserve Off command is issued. Therefore, it
does not need to issue another AGC Preserve On
command. An AGC Preserve Off command is needed to
The purpose of having an option to disable a particular
channel is to minimize current draw by powering down
as much circuitry as possible, if the channel is not
needed for operation. The exact circuits disabled when
an input is disabled are amplifiers, detector, full-wave
rectifier, data slicer, and modulation FET. However, the
RF input limiter remains active to protect the silicon
from excessive antenna input voltages.
11.18 AGC Amplifier
The circuit automatically amplifies input signal voltage
levels to an acceptable level for the data slicer. Fast
attack and slow release by nature, the AGC tracks the
carrier signal level and not the modulated data bits.
disable
Section 11.32.2.5 “AGC Preserve On Command”
and Section 11.32.2.6 “AGC Preserve Off
Command” for AGC Preserve commands).
the
AGC
preserve
feature
(see
The AGC inherently tracks the strongest of the three
antenna input signals. The AGC requires an AGC
stabilization time (TAGC).
The AGC will attempt to regulate a channel’s peak
signal voltage into the data slicer to a desired regulated
AGC voltage – reducing the input path’s gain as the
signal level attempts to increase above regulated AGC
voltage, and allowing full amplification on signal levels
below the regulated AGC voltage.
The AGC has two modes of operation:
1. During the AGC settling time (TAGC), the AGC
time constant is fast, allowing a reasonably short
acquisition time of the continuous input signal.
2. After TAGC, the AGC switches to a slower time
constant for data slicing.
Also, the AGC is frozen when the input signal envelope
is low. The AGC tracks only high envelope levels.
DS41232B-page 88
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TABLE 11-3: SETTING FOR MINIMUM
MODULATION DEPTH
11.20 Soft Reset
The AFE issues a Soft Reset in the following events:
REQUIREMENT
MODMIN Bits
(Config. Register 5)
a) After Power-on Reset (POR),
b) After Inactivity timer time-out,
c) If an “Abort” occurs,
Modulation Depth
Bit 6
Bit 5
d) After receiving SPI Soft Reset command.
0
0
1
1
0
1
0
1
50% (default)
75%
The “Abort” occurs if there is no positive signal
detected at the end of the AGC stabilization period
(TAGC). The Soft Reset initializes internal circuits and
brings the AFE into a low current Standby mode
operation. The internal circuits that are initialized by the
Soft Reset include:
25%
12%
• Output Enable Filter
• AGC circuits
• Demodulator
• 32 kHz Internal Oscillator
The Soft Reset has no effect on the Configuration register
setup, except for some of the AFE Status Register 7 bits.
(Register 11-8).
The circuit initialization takes one internal clock cycle
(1/32 kHz = 31.25 μs). During the initialization, the
modulation transistors between each input and
LCCOM pins are turned-on to discharge any internal/
external parasitic charges. The modulation transistors
are turned-off immediately after the initialization time.
The Soft Reset is executed in Active mode only. It is not
valid in Standby mode.
11.21 Minimum Modulation Depth
Requirement for Input Signal
The AFE demodulates the modulated input signal if the
modulation depth of the input signal is greater than the
minimum requirement that is programmed in the AFE
Configuration Register 5 (Register 11-6). Figure 11-7
shows the definition of the modulation depth and
examples. MODMIN<6:5> of the Configuration Register
5 offer four options. They are 75%, 50%, 25% and 12%,
with a default setting of 50%.
The purpose of this feature is to enhance the
demodulation integrity of the input signal. The 12%
setting is the best choice for the input signal with weak
modulation depth, which is typically observed near the
high-voltage base station antenna and also at far-
distance from the base station antenna. It gives the
best demodulation sensitivity, but is very susceptible to
noise spikes that can result in a bit detection error. The
75% setting can reduce the bit errors caused by noise,
but gives the least demodulation sensitivity. See
Table 11-3 for minimum modulation depth requirement
settings.
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FIGURE 11-7:
MODULATION DEPTH EXAMPLES
(a) Modulation Depth Definition
Amplitude
A - B
A
X 100%
Modulation Depth (%) =
B
A
t
(b) LFDATA Output vs. Input vs. Minimum Modulation Depth Setting
Amplitude
10 mVPP
Coil Input Strength
7 mVPP
10 - 7
10
X 100% = 30%
Modulation Depth (%) =
t
Input signal with modulation depth = 30%
Demodulated LFDATA Output when MODMIN Setting = 25%
(LFDATA output = toggled)
t
Amplitude
Demodulated LFDATA Output if MODMIN Setting = 50%
(LFDATA output = not toggled)
t
0
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11.22 Low Current Sleep Mode
11.25 Error Detection of AFE
Configuration Register Data
The Sleep command from the microcontroller, via an
SPI Interface command, places the AFE into an ultra
Low-current mode. All circuits including the RF Limiter,
except the minimum circuitry required to retain register
memory and SPI capability, will be powered down to
minimize the AFE current draw. Power-on Reset or any
SPI command, other than Sleep command, is required
to wake the AFE from Sleep.
The AFE's Configuration registers are volatile memory.
Therefore, the contents of the registers can be
corrupted or cleared by any electrical incidence such
as battery disconnect. To ensure the data integrity, the
AFE has an error detection mechanism using row and
column parity bits of the Configuration register memory
map. The bit 0 of each register is a row parity bit which
is calculated over the eight configuration bits (from bit 1
to bit 8). The Column Parity Register (Configuration
Register 6) holds column parity bits; each bit is
calculated over the respective columns (Configuration
registers 0 to 5) of the Configuration bits. The Status
register is not included for the column parity bit
calculation. Parity is to be odd. The parity bit set or
cleared makes an odd number of set bits. The user
needs to calculate the row and column parity bits using
the contents of the registers and program them. During
operation, the AFE continuously calculates the row and
column parity bits of the configuration memory map. If
a parity error occurs, the AFE lowers the SCLK/ALERT
pin (interrupting the microcontroller section) indicating
the configuration memory has been corrupted or
unloaded and needs to be reprogrammed.
11.23 Low Current Standby Mode
The AFE is in Standby mode when no LF signal is
present on the antenna inputs but the AFE is powered
and ready to receive any incoming signals.
11.24 Low Current Operating Mode
The AFE is in Low-current Operating mode when a LF
signal is present on an LF antenna input and internal
circuitry is switching with the received data.
At an initial condition after a Power-On-Reset, the
values of the registers are all clear (default condition).
Therefore, the AFE will issue the parity bit error by
lowering the SCLK/ALERT pin. If user reprograms the
registers with correct parity bits, the SCLK/ALERT pin
will be toggled to logic high level immediately.
The parity bit errors do not change or affect the AFE's
functional operation.
Table 11-4 shows an example of the register values
and corresponding parity bits.
TABLE 11-4: AFE CONFIGURATION REGISTER PARITY BIT EXAMPLE
Bit 0
(Row Parity)
Register Name
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Configuration Register 0
Configuration Register 1
Configuration Register 2
Configuration Register 3
Configuration Register 4
Configuration Register 5
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
1
1
1
0
1
Configuration Register 6
(Column Parity Register)
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11.26 Factory Calibration
11.28 Battery Back-up and Batteryless
Operation
Microchip calibrates the AFE to reduce the device-to-
device variation in standby current, internal timing and
sensitivity, as well as channel-to-channel sensitivity
variation.
The device supports both battery back-up and
batteryless operation by the addition of external
components, allowing the device to be partially or
completely powered from the field.
11.27 De-Q’ing of Antenna Circuit
Figure 11-8 shows an example of the external circuit for
the battery back-up.
When the transponder is close to the base station, the
transponder coil may develop coil voltage higher than
VDE_Q. This condition is called “near field”. The AFE
detects the strong near field signal through the AGC
control, and de-Q’ing the antenna circuit to reduce the
input signal amplitude.
Note:
Voltage on LCCOM combined with coil input
voltage must not exceed the maximum LC
input voltage.
FIGURE 11-8:
LF FIELD POWERING AND BATTERY BACK-UP EXAMPLE
VBAT
VDD
LCX
LCY
LCZ
RLIM
DFLAT1
DBLOCK
CPOOL
LX
DLIM
CX
LY
Air Coil
CY
LZ
CZ
LCCOM
DFLAT2
CCOM
RCOM
Legend: CCOM = LCCOM charging capacitor.
CPOOL = Pool capacitor (or battery back-up capacitor), charges in field and powers device.
DBLOCK = Battery protection from reverse charge.
Schottky for low forward bias drop.
DFLAT = Field rectifier diodes.
DLIM = Voltage limiting diode, may be required to limit VDD voltage when in strong fields.
RCOM = Ccom discharge path.
RLIM = Current limiting resistor, required for air coil in strong fields.
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11.29 Demodulator
The demodulator recovers the modulation data from
the received signal, containing carrier plus data, by
appropriate envelope detection. The demodulator has
a fast rise (charge) time (TDR) and a fall time (TDF)
appropriate to an envelope of input signal (see
Section 15.0 “Electrical Specifications” for TDR
and TDF specifications). The demodulator contains
the full-wave rectifier, low-pass filter, peak detector
and data slicer.
FIGURE 11-9:
DEMODULATOR CHARGE AND DISCHARGE
Signal into LC input pins
Full-wave Rectifier output
Data Slicer output
(demodulator output)
TDR
TDF
For a clean data output or to save operating power, the
input channels can be individually enabled or disabled. If
more than one channel is enabled, the output is the sum
of each output of all enabled channels. There will be no
valid output if all three channels are disabled. When the
demodulated output is selected, the output is available in
two different conditions depending on how the options of
Configuration Register 0 (Register 11-1) are set: Output
Enable Filter is disabled or enabled.
11.30 Power-On Reset
This circuit remains in a Reset state until a sufficient
supply voltage is applied to the AFE. The Reset
releases when the supply is sufficient for correct AFE
operation, nominally VPOR of AFE.
The Configuration registers are all cleared on a Power-
on Reset. As the Configuration registers are protected
by odd row and column parity, the ALERT pin will be
pulled down – indicating to the microcontroller section
that the AFE configuration memory is cleared and
requires loading.
Related Configuration register bits:
• Configuration Register 1 (Register 11-2),
DATOUT <8:7>:
- bit 8 bit 7
11.31 LFDATA Output Selection
0
0
1
0
0: Demodulator Output
1: Carrier Clock Output
0: RSSI Output
The LFDATA output can be configured to pass the
Demodulator output, Received Signal Strength Indicator
(RSSI) output, or Carrier Clock. See Configuration
Register 1 (Register 11-2) for more details.
1: RSSI Output
• Configuration Register 0 (Register 11-1): all bits
11.31.1 DEMODULATOR OUTPUT
The demodulator output is the default configuration of
the output selection. This is the output of an envelope
detection circuit. See Figure 11-9 for the demodulator
output.
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Case I. When Output Enable Filter is disabled: Demodulated output is available immediately after the AGC stabilization
time (TAGC). Figure 11-10 shows an example of demodulated output when the Output Enable Filter is disabled.
FIGURE 11-10:
INPUT SIGNAL AND DEMODULATOR OUTPUT WHEN THE OUTPUT ENABLE
FILTER IS DISABLED
Input Signal
LFDATA Output
Case II. When Output Enable Filter is enabled: Demodulated output is available only if the incoming signal meets the
enable filter timing criteria that is defined in the Configuration Register 0 (Register 11-1). If the criteria is met, the output
is available after the low timing (TOEL) of the Enable Filter. Figure 11-11 and Figure 11-12 shows examples of
demodulated output when the Output Enable Filter is enabled.
FIGURE 11-11:
INPUT SIGNAL AND DEMODULATOR OUTPUT (WHEN OUTPUT ENABLE
FILTER IS ENABLED AND INPUT MEETS FILTER TIMING REQUIREMENTS)
Input Signal
LFDATA Output
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Preliminary
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FIGURE 11-12:
NO DEMODULATOR OUTPUT (WHEN OUTPUT ENABLE FILTER IS ENABLED
BUT INPUT DOES NOT MEET FILTER TIMING REQUIREMENTS)
Input Signal
No LFDATA Output
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11.31.2 CARRIER CLOCK OUTPUT
When the Carrier Clock output is selected, the LFDATA
output is a square pulse of the input carrier clock and
available as soon as the AGC stabilization time (TAGC) is
completed. There are two Configuration register options
for the carrier clock output: (a) clock divide-by one or (b)
clock divide-by four, depending on bit DATOUT<7> of
Configuration Register 2 (Register 11-3). The carrier
clock output is available immediately after the AGC
settling time. The Output Enable Filter, AGCSIG, and
MODMIN options are applicable for the carrier clock
output in the same way as the demodulated output. The
input channel can be individually enabled or disabled for
the output. If more than one channel is enabled, the
output is the sum of each output of all enabled channels.
Therefore, the carrier clock output waveform is not as
precise as when only one channel is enabled. It is
recommended to enable one channel only if a precise
output waveform is desired.
There will be no valid output if all three channels are
disabled. See Figure 11-13 for carrier clock output
examples.
Related Configuration register bits:
• Configuration Register 1 (Register 11-2),
DATOUT <8:7>:
bit 8 bit 7
0
0
1
1
0: Demodulator Output
1: Carrier Clock Output
0: RSSI Output
1: RSSI Output
• Configuration Register 2 (Register 11-3),
CLKDIV<7>:
0: Carrier Clock/1
1: Carrier Clock/4
• Configuration Register 0 (Register 11-1): all bits
are affected
• Configuration Register 5 (Register 11-6)
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FIGURE 11-13:
CARRIER CLOCK OUTPUT EXAMPLES
(A) CARRIER CLOCK OUTPUT WITH CARRIER/1 OPTION
Carrier Clock Output
Carrier Input
(B) CARRIER CLOCK OUTPUT WITH CARRIER/4 OPTION
Carrier Clock Output
Carrier Input
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11.31.3 RECEIVED SIGNAL STRENGTH
INDICATOR (RSSI) OUTPUT
FIGURE 11-14:
RSSI OUTPUT PATH
An analog current is available at the LFDATA pin when
the Received Signal Strength Indicator (RSSI) output is
selected for the AFE’s Configuration register. The analog
current is linearly proportional to the input signal strength
(see Figure 11-15).
RSSI Output Current
Generator
Current Output
VDD
Off
All timers in the circuit, such as inactivity timer, alarm
timer, and AGC settling time, are disabled during the
RSSI mode. Therefore, the RSSI output is not affected
by the AGC settling time, and available immediately
when the RSSI option is selected. The AFE enters
Active mode immediately when the RSSI output is
selected. The MCU I/O pin (RC3) connected to the
LFDATA pin, must be set to high-impedance state
during the RSSI Output mode.
if RSSI active
RC3/LFDATA/RSSI/CCLK Pin
RSSIFET
When the AFE receives an SPI command during the
RSSI output, the RSSI mode is temporary disabled
until the SPI interface communication is completed. It
returns to the RSSI mode again after the SPI interface
communication is completed. The AFE holds the RSSI
mode until another output type is selected (CS low
turns off the RSSI signal). To obtain the RSSI output
for a particular input channel, or to save operating
power, the input channel can be individually enabled
or disabled. If more than one channel is enabled, the
RSSI output is from the strongest signal channel.
There will be no valid output if all three channels are
disabled.
RSSI Pull-down MOSFET
(controlled by Config. 2, bit 8)
Related AFE Configuration register bits:
• Configuration Register 1 (Register 11-2),
DATOUT<8:7>:
bit 8 bit 7
0
0
1
1
0: Demodulated Output
1: Carrier Clock Output
0: RSSI Output
1: RSSI Output
• Configuration Register 2 (Register 11-3),
RSSIFET<8>:
0: Pull-Down MOSFET off
1: Pull-Down MOSFET on.
Note:
The pull-down MOSFET option is valid
only when the RSSI output is selected.
The MOSFET is not controllable by users
when Demodulated or Carrier Clock
output option is selected.
• Configuration Register 0 (Register 11-1): all bits
are affected.
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FIGURE 11-15:
RSSI OUTPUT CURRENT VS. INPUT SIGNAL LEVEL EXAMPLE
90
80
70
60
50
40
30
20
10
0
0
1
2
3
4
5
6
7
8
9
10
Input Voltage (VPP)
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11.31.3.1 ANALOG-TO-DIGITAL DATA
CONVERSION OF RSSI SIGNAL
11.32 AFE Configuration
11.32.1 SPI COMMUNICATION
The AFE’s RSSI output is an analog current. It needs an
external analog-to-digital (ADC) data conversion device
for digitized output. The ADC data conversion can be
accomplished by using a stand-alone external ADC
device or by firmware utilizing MCU's internal
comparator along with a few external resistors and a
capacitor. For slope ADC implementations, the external
capacitor at the LFDATA pad needs to be discharged
before data sampling. For this purpose, the internal pull-
down MOSFET on the LFDATA pad can be utilized. The
MOSFET can be turned on or off with bit RSSIFET<8> of
the Configuration Register 2 (Register 11-3). When it is
turned on, the internal MOSFET provides a discharge
path for the external capacitor. This MOSFET option is
valid only if RSSI output is selected and not controllable
by users for demodulated or carrier clock output options.
The AFE SPI interface communication is used to read
or write the AFE’s Configuration registers and to send
command only messages. For the SPI interface, the
device has three pads; CS, SCLK/ALERT, and
LFDATA/RSSI/CCLK/SDIO. Figure 11-15, Figure 11-
14, Figure 11-16 and Figure 11-17 shows examples of
the SPI communication sequences.
When the device powers up, these pins will be high-
impedance inputs until firmware modifies them
appropriately. The AFE pins connected to the MCU
pins will be as follows.
CS
• Pin is permanently an input with an internal pull-up.
SCLK/ALERT
• Pin is an open collector output when CS is high.
An internal pull-up resistor exists internal to the
AFE to ensure no spurious SPI communication
between powering and the MCU configuring its
pins. This pin becomes the SPI clock input when
CS is low.
See separate application notes for various external ADC
implementation methods for this device.
LFDATA/RSSI/CCLK/SDIO
• Pin is a digital output (LFDATA) so long as CS is
high. During SPI communication, the pin is the
SPI data input (SDI) unless performing a register
Read, where it will be the SPI data output (SDO).
FIGURE 11-16:
POWER-UP SEQUENCE
CS
SCLK/ALERT
ALERT
(open collector
output)
LFDATA/RSSI/
CCLK/SDIO
LFDATA
(output)
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FIGURE 11-17:
SPI WRITE SEQUENCE
TCSH
2
6
CS
TCSSC
TSCCS TCS1
TCS0
16 Clocks for Write Command, Address and Data
4
THI
TLO
7
SCLK/
ALERT
MSb
THD
LSb
SCLK
(input)
ALERT
(output)
1/FSCLK
ALERT
(output)
1
TSU
LFDATA/RSSI/
CCLK/SDIO
LFDATA
(output)
SDI
(input)
LFDATA
(output)
5
3
MCU SPI Write Details:
1.
Drive the AFE’s open collector ALERT output low.
to ensure no false clocks occur when CS drops
Drop CS.
•
2.
•
•
AFE SCLK/ALERT becomes SCLK input
LFDATA/RSSI/CCLK/SDIO becomes SDI input
3.
4.
Change LFDATA/RSSI/CCLK/SDIO connected pin to output.
driving SPI data
Clock in 16-bit SPI Write sequence - command, address, data and parity bit.
command, address, data and parity bit
•
•
5.
6.
7.
Change LFDATA/RSSI/CCLK/SDIO connected pin to input.
Raise CS to complete the SPI Write.
Change SCLK/ALERT back to input.
© 2005 Microchip Technology Inc.
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FIGURE 11-18:
SPI READ SEQUENCE
TCSH
TCSH
9
6
7
2
CS
10
4
8
16 Clocks for Read Result
16 Clocks for Read Command,
Address and Dummy Data
TCS
0
TCSSC
TSCCS
CSSC TCS1
TCSSC
TCS1
T
TCS
0
T
HI
TLO
SCLK/ALERT
MSb
LSb
SCLK
(input)
SCLK
(input)
ALERT
(output)
ALERT
(output)
ALERT
(output)
1/FSCLK
1
TSU THD
T
DO
LFDATA/RSSI/
CCLK/SDIO
3
LFDATA
(output)
SDO
(output)
LFDATA
(output)
SDI
(input)
LFDATA
(output)
5
MCU SPI Read Details:
7.
8.
Drop CS.
1.
2.
Drive the AFE’s open collector ALERT output low.
To ensure no false clocks occur when CS drops.
Drop CS
•
•
AFE SCLK/ALERT becomes SCLK input.
LFDATA/RSSI/CCLK/SDIO becomes SDO output.
•
Clock out 16-bit SPI Read result.
•
•
AFE SCLK/ALERT becomes SCLK input.
LFDATA/RSSI/CCLK/SDIO becomes SDI input.
•
•
•
First seven bits clocked-out are dummy bits.
Next eight bits are the Configuration register data.
The last bit is the Configuration register row parity bit.
3.
4.
Change LFDATA/RSSI/CCLK/SDIO connected pin to output.
Driving SPI data.
Clock in 16-bit SPI Read sequence.
Command, address and dummy data.
Change LFDATA/RSSI/CCLK/SDIO connected pin to input.
Raise CS to complete the SPI Read entry of command and address.
•
9.
Raise CS to complete the SPI Read.
10. Change SCLK/ALERT back to input.
•
5.
6.
Note:
The TCSH is considered as one clock. Therefore, the
Configuration register data appears at 6th clock after TCSH.
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The AFE operates in SPI mode 0,0. In mode 0,0 the
clock idles in the low state (Figure 11-19). SDI data is
loaded into the AFE on the rising edge of SCLK and
SDO data is clocked out on the falling edge of SCLK.
There must be multiples of 16 clocks (SCLK) while CS
is low or commands will abort.
11.32.2 COMMAND DECODER/
CONTROLLER
The circuit executes 8 SPI commands from the MCU.
The command structure is:
Command (3 bits) + Configuration Address (4 bits) +
Data Byte and Row Parity Bit received by the AFE Most
Significant bit first. Table 11-5 shows the available SPI
commands.
TABLE 11-5: SPI COMMANDS (AFE)
Row
Command Address
Data
Description
Parity
Command only – Address and Data are “Don’t Care”, but need to be clocked in regardless.
000
001
010
011
100
101
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
X
X
X
X
X
X
Clamp on – enable modulation circuit
Clamp off – disable modulation circuit
Enter Sleep mode (any other command wakes the AFE)
AGC Preserve On – to temporarily preserve the current AGC level
AGC Preserve Off – AGC again tracks strongest input signal
Soft Reset – resets various circuit blocks
Read Command – Data will be read from the specified register address.
110
0000
0001
0010
0011
0100
0101
0110
0111
Config Byte 0
Config Byte 1
Config Byte 2
Config Byte 3
Config Byte 4
Config Byte 5
Column Parity
AFE Status
P
P
P
P
P
P
P
X
General – options that may change during normal operation
LCX antenna tuning and LFDATA output format
LCY antenna tuning
LCZ antenna tuning
LCX and LCY sensitivity reduction
LCZ sensitivity reduction and modulation depth
Column parity byte for Config Byte 0 -> Config Byte 5
AFE status – parity error, which input is active, etc.
Write Command – Data will be written to the specified register address.
111
0000
0001
0010
0011
0100
0101
0110
0111
Config Byte 0
Config Byte 1
Config Byte 2
Config Byte 3
Config Byte 4
Config Byte 5
Column Parity
Not Used
P
P
P
P
P
P
P
X
General – options that may change during normal operation
LCX antenna tuning and LFDATA output format
LCY antenna tuning
LCZ antenna tuning
LCX and LCY sensitivity reduction
LCZ sensitivity reduction and modulation depth
Column parity byte for Config Byte 0 -> Config Byte 5
Register is readable, but not writable
Note:
‘P’ denotes the row parity bit (odd parity) for the respective data byte.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 103
PIC12F635/PIC16F636/639
FIGURE 11-19:
CS
DETAILED SPI INTERFACE TIMING (AFE)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SCLK
SDIO
MSb
LSb
Data Byte
Row
Parity Bit
Command
Address
11.32.2.1 Clamp On Command
11.32.2.5 AGC Preserve On Command
This command results in activating (turning on) the
modulation transistors of all enabled channels; channels
enabled in Configuration Register 0 (Register 11-1).
This command results in preserving the AGC level
during each AGC settling time and apply the value to
the data slicing circuit for the following data stream. The
preserved AGC value is reset by a Soft Reset, and a
new AGC value is acquired and preserved when it
starts a new AGC settling time. This feature is disabled
by an AGC Preserve Off command (see Section 11.19
“AGC Preserve”).
11.32.2.2 Clamp Off Command
This command results in de-activating (turning off) the
modulation transistors of all channels.
11.32.2.3 Sleep Command
11.32.2.6 AGC Preserve Off Command
This command places the AFE in Sleep mode –
minimizing current draw by disabling all but the
essential circuitry. Any other command wakes the AFE
(example: Clamp Off command).
This command disables the AGC preserve feature and
returns the AFE to the normal AGC tracking mode, fast
tracking during AGC settling time and slow tracking
after that (see Section 11.19 “AGC Preserve”).
11.32.2.4 Soft Reset Command
11.32.3 CONFIGURATION REGISTERS
The AFE issues a Soft Reset when it receives an
external Soft Reset command. The external Soft Reset
command is typically used to end a SPI communication
sequence or to initialize the AFE for the next signal
detection sequence, etc. See Section 11.20 “Soft
Reset” for more details on Soft Reset.
The AFE includes 8 Configuration registers, including a
column parity register and AFE Status register. All
registers are readable and writable via SPI, except
Status register, which is readable only. Bit 0 of each
register is a row parity bit (except for the AFE Status
Register 7) that makes the register contents an odd
number.
If a Soft Reset command is sent during a “Clamp-on”
condition, the AFE still keeps the “Clamp-on” condition
after the Soft Reset execution. The Soft Reset is
executed in Active mode only, not in Standby mode.
The SPI Soft Reset command is ignored if the AFE is
not in Active mode.
DS41232B-page 104
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
TABLE 11-6: ANALOG FRONT-END CONFIGURATION REGISTERS SUMMARY
Register Name
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Configuration Register 0
Configuration Register 1
Configuration Register 2
Configuration Register 3
Configuration Register 4
OEH
DATOUT
RSSIFET CLKDIV
Unimplemented
Channel X Sensitivity Control
OEL
ALRTIND LCZEN
LCYEN
LCXEN
R0PAR
R1PAR
R2PAR
R3PAR
R4PAR
R5PAR
R6PAR
PEI
Channel X Tuning Capacitor
Channel Y Tuning Capacitor
Channel Z Tuning Capacitor
Channel Y Sensitivity Control
Channel Z Sensitivity Control
Configuration Register 5 AUTOCHSEL AGCSIG MODMIN MODMIN
Column Parity Register 6
AFE Status Register 7
Column Parity Bits
AGCACT Wake-up Channel Indicators
Active Channel Indicators
ALARM
REGISTER 11-1: CONFIGURATION REGISTER 0 (ADDRESS: 0000)
R/W-0
OEH1
R/W-0
OEH0
R/W-0
OEL1
R/W-0
OEL0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R0PAR
bit 0
ALRTIND
LCZEN
LCYEN
LCXEN
bit 8
bit 8-7
bit 6-5
OEH<1:0>: Output Enable Filter High Time (TOEH) bit
00= Output Enable Filter disabled (no wake-up sequence required, passes all signal to LFDATA)
01= 1 ms
10= 2 ms
11= 4 ms
OEL<1:0>: Output Enable Filter Low Time (TOEL) bit
00= 1 ms
01= 1 ms
10= 2 ms
11= 4 ms
bit 4
bit 3
bit 2
bit 1
bit 0
ALRTIND: ALERT bit, output triggered by:
1= Parity error and/or expired Alarm timer (receiving noise, see Section 11.14.3 “Alarm Timer”)
0= Parity error
LCZEN: LCZ Enable bit
1= Disabled
0= Enabled
LCYEN: LCY Enable bit
1= Disabled
0= Enabled
LCXEN: LCX Enable bit
1= Disabled
0= Enabled
R0PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
- n = Value at POR
x = Bit is unknown
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 105
PIC12F635/PIC16F636/639
REGISTER 11-2: CONFIGURATION REGISTER 1 (ADDRESS: 0001)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATOUT1 DATOUT0 LCXTUN5 LCXTUN4 LCXTUN3 LCXTUN2 LCXTUN1 LCXTUN0
bit 8
R1PAR
bit 0
bit 8-7
DATOUT<1:0>: LFDATA Output type bit
00= Demodulated output
01= Carrier Clock output
10= RSSI output
11= RSSI output
bit 6-1
bit 0
LCXTUN<5:0>: LCX Tuning Capacitance bit
000000=+0 pF (Default)
:
111111=+63 pF
R1PAR: Register Parity Bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
- n = Value at POR
x = Bit is unknown
REGISTER 11-3: CONFIGURATION REGISTER 2 (ADDRESS: 0010)
R/W-0
RSSIFET
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CLKDIV
LCYTUN5 LCYTUN4 LCYTUN3 LCYTUN2 LCYTUN1 LCYTUN0
R2PAR
bit 0
bit 8
RSSIFET: Pull-down MOSFET on LFDATA pad bit (controllable by user in the RSSI mode only)
1= Pull-down RSSI MOSFET on
0= Pull-down RSSI MOSFET off
bit 7
CLKDIV: Carrier Clock Divide-by bit
1= Carrier Clock/4
0= Carrier Clock/1
bit 6-1
LCYTUN<5:0>: LCY Tuning Capacitance bit
000000=+0 pF (Default)
:
111111=+63 pF
bit 0
R2PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
- n = Value at POR
x = Bit is unknown
DS41232B-page 106
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
REGISTER 11-4: CONFIGURATION REGISTER 3 (ADDRESS: 0011)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LCZTUN5 LCZTUN4 LCZTUN3 LCZTUN2 LCZTUN1 LCZTUN0
R3PAR
bit 8
bit 0
bit 8-7
bit 6-1
Unimplemented: Read as ‘0’
LCZTUN<5:0>: LCZ Tuning Capacitance bit
000000=+0 pF (Default)
:
111111=+63 pF
bit 0
R3PAR: Register Parity Bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
- n = Value at POR
x = Bit is unknown
REGISTER 11-5: CONFIGURATION REGISTER 4 (ADDRESS: 0100)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LCXSEN3 LCXSEN2 LCXSEN1 LCXSEN0 LCYSEN3 LCYSEN2 LCYSEN1 LCYSEN0
bit 8
R4PAR
bit 0
(1)
bit 8-5
LCXSEN<3:0> : Typical LCX Sensitivity Reduction bit
0000= -0 dB (Default)
0001= -2 dB
0010= -4 dB
0011= -6 dB
0100= -8 dB
0101= -10 dB
0110= -12 dB
0111= -14 dB
1000= -16 dB
1001= -18 dB
1010= -20 dB
1011= -22 dB
1100= -24 dB
1101= -26 dB
1110= -28 dB
1111= -30 dB
(1)
bit 4-1
bit 0
LCYSEN<3:0> : Typical LCY Sensitivity Reduction bit
0000= -0 dB (Default)
:
1111= -30 dB
R4PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
Note 1: Assured monotonic increment (or decrement) by design.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
- n = Value at POR
x = Bit is unknown
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 107
PIC12F635/PIC16F636/639
REGISTER 11-6: CONFIGURATION REGISTER 5 (ADDRESS: 0101)
R/W-0
AUTOCHSEL
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AGCSIG
MODMIN1 MODMIN0 LCZSEN3 LCZSEN2 LCZSEN1 LCZSEN0 R5PAR
bit 0
bit 8
AUTOCHSEL: Auto Channel Select bit
1= Enabled – AFE selects channel(s) that has demodulator output “high” at the end of TSTAB; or otherwise, blocks the
channel(s).
0= Disabled – AFE follows channel enable/disable bits defined in Register 0
bit 7
AGCSIG: Demodulator Output Enable bit, after the AGC loop is active
1= Enabled – No output until AGC is regulating at around 20 mVPP at input pins. The AGC Active Status bit is set
when the AGC begins regulating.
0= Disabled – the AFE passes signal of any level it is capable of detecting
bit 6-5
MODMIN<1:0>: Minimum Modulation Depth bit
00= 50%
01= 75%
10= 25%
11= 12%
(1)
bit 4-1
bit 0
LCZSEN<3:0> : LCZ Sensitivity Reduction bit
0000= -0dB (Default)
:
1111= -30dB
R5PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
Note 1: Assured monotonic increment (or decrement) by design.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
- n = Value at POR
x = Bit is unknown
REGISTER 11-7: COLUMN PARITY REGISTER 6 (ADDRESS: 0110)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R6PAR
bit 0
COLPAR7 COLPAR6 COLPAR5 COLPAR4 COLPAR3 COLPAR2 COLPAR1 COLPAR0
bit 8
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
COLPAR7: Set/Cleared so that this 8th parity bit + the sum of the config register row parity bits contain an odd number of
set bits.
COLPAR6: Set/Cleared such that this 7th parity bit + the sum of the 7th bits in config registers 0 through 5 contain an odd
number of set bits.
COLPAR5: Set/Cleared such that this 6th parity bit + the sum of the 6th bits in config registers 0 through 5 contain an odd
number of set bits.
COLPAR4: Set/Cleared such that this 5th parity bit + the sum of the 5th bits in config registers 0 through 5 contain an odd
number of set bits.
COLPAR3: Set/Cleared such that this 4th parity bit + the sum of the 4th bits in config registers 0 through 5 contain an odd
number of set bits.
COLPAR2: Set/Cleared such that this 3rd parity bit + the sum of the 3rd bits in config registers 0 through 5 contain an odd
number of set bits.
COLPAR1: Set/Cleared such that this 2nd parity bit + the sum of the 2nd bits in config registers 0 through 5 contain an odd
number of set bits.
COLPAR0: Set/Cleared such that this 1st parity bit + the sum of the 1st bits in config registers 0 through 5 contain an odd
number of set bits.
R6PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
- n = Value at POR
x = Bit is unknown
DS41232B-page 108
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
REGISTER 11-8: AFE STATUS REGISTER 7 (ADDRESS: 0111)
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
PEI
CHZACT
CHYACT CHXACT AGCACT WAKEZ
WAKEY
WAKEX
ALARM
bit 8
bit 0
bit 8
bit 7
bit 6
bit 5
CHZACT: Channel Z Active(1) bit (cleared via Soft Reset)
1= Channel Z is passing data after TAGC
0= Channel Z is not passing data after TAGC
CHYACT: Channel Y Active(1) bit (cleared via Soft Reset)
1= Channel Y is passing data after TAGC
0= Channel Y is not passing data after TAGC
CHXACT: Channel X Active(1) bit (cleared via Soft Reset)
1= Channel X is passing data after TAGC
0= Channel X is not passing data after TAGC
AGCACT: AGC Active Status bit (real time, cleared via Soft Reset)
1= AGC is active (Input signal is strong). AGC is active when input signal level is approximately >
20 mVPP range.
0= AGC is inactive (Input signal is weak)
bit 4
bit 3
bit 2
bit 1
WAKEZ: Wake-up Channel Z Indicator Status bit (cleared via Soft Reset)
1= Channel Z caused a AFE wake-up (passed ÷64 clock counter)
0= Channel Z did not cause a AFE wake-up
WAKEY: Wake-up Channel Y Indicator Status bit (cleared via Soft Reset)
1= Channel Y caused a AFE wake-up (passed ÷64 clock counter)
0= Channel Y did not cause a AFE wake-up
WAKEX: Wake-up Channel X Indicator Status bit (cleared via Soft Reset)
1= Channel X caused a AFE wake-up (passed ÷64 clock counter)
0= Channel X did not cause a AFE wake-up
ALARM: Indicates whether an Alarm timer time-out has occurred (cleared via read “Status Register
command”)
1= The Alarm timer time-out has occurred. It may cause the ALERT output to go low depending on the
state of bit 4 of the Configuration register 0
0= The Alarm timer is not timed out
bit 0
PEI: Parity Error Indicator bit – indicates whether a Configuration register parity error has occurred (real
time)
1= A parity error has occurred and caused the ALERT output to go low
0= A parity error has not occurred
Note 1: Bit is high whenever channel is passing data. Bit is low in Standby mode.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
- n = Value at POR
x = Bit is unknown
See Table 11-7 for the bit conditions of the AFE Status
register after various SPI commands and the AFE
Power-on Reset.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 109
PIC12F635/PIC16F636/639
TABLE 11-7: AFE STATUS REGISTER BIT CONDITION (AFTER POWER-ON RESET AND
VARIOUS SPI COMMANDS)
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Condition
CHZACT CHYACT CHXACT AGCACT WAKEZ WAKEY WAKEX ALARM PEI
POR
0
u
0
u
0
u
0
u
0
u
0
u
0
u
0
0
1
u
Read Command
(STATUS Register only)
Sleep Command
Soft Reset Executed(1)
u
0
u
0
u
0
u
0
u
0
u
0
u
0
u
u
u
u
Legend: u= unchanged
Note 1: See Section 11.20 “Soft Reset” and Section 11.32.2.4 “Soft Reset Command” for the condition of Soft
Reset execution.
DS41232B-page 110
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
The PIC12F635/PIC16F636/639 has two timers that
offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), intended to keep the
12.0 SPECIAL FEATURES OF THE
CPU
chip in Reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 64 ms (nominal) on power-up only,
designed to keep the part in Reset while the power
supply stabilizes. There is also circuitry to reset the
device if a brown-out occurs, which can use the Power-
up Timer to provide at least a nominal 64 ms Reset.
With these three functions on-chip, most applications
need no external Reset circuitry.
The PIC12F635/PIC16F636/639 has a host of features
intended to maximize system reliability, minimize cost
through elimination of external components, provide
power saving features and offer code protection.
These features are:
• Reset
- Power-on Reset (POR)
- Wake-up Reset (WUR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Detect (BOD)
• Interrupts
The Sleep mode is designed to offer a very low-current
Power-down mode. The user can wake-up from Sleep
through:
• External Reset
• Watchdog Timer Wake-up
• An Interrupt
• Watchdog Timer (WDT)
• Oscillator selection
• Sleep
Several oscillator options are also made available to
allow the part to fit the application. The INTOSC option
saves system cost while the LP crystal option saves
power. A set of configuration bits are used to select
various options (see Register 12-1).
• Code protection
• ID Locations
• In-Circuit Serial Programming
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 111
PIC12F635/PIC16F636/639
12.1 Configuration Word Bits
Note:
Address 2007h is beyond the user program
memory space. It belongs to the special
configuration memory space (2000h-
3FFFh), which can be accessed only during
programming. See “PIC12F6XX/16F6XX
Memory Programming Specification”
(DS41204) for more information.
The Configuration Word bits can be programmed (read
as ‘0’), or left unprogrammed (read as ‘1’) to select
various device configurations as shown in Register 12-1.
These bits are mapped in program memory location
2007h.
REGISTER 12-1: CONFIG – CONFIGURATION WORD (ADDRESS: 2007h)
U-1
—
R/P-1 R/P-1 R/P-1
R/P-1
R/P-1
R/P-1 R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
(1)
WURE FCMEN IESO BODEN1 BODEN0 CPD
CP
MCLRE PWRTE
WDTE FOSC2 F0SC1 F0SC0
bit 0
bit 13
bit 13
bit 12
Unimplemented: Read as ‘1’
WURE: Wake-up Reset Enable bit
1= Standard wake-up and continue enabled
0= Wake-up and Reset enabled
bit 11
bit 10
bit 9-8
FCMEN: Fail-Safe Clock Monitor Enable bit
1= Fail-Safe Clock Monitor enabled
0= Fail-Safe Clock Monitor disabled
IESO: Internal-External Switchover bit
1= Internal External Switchover mode enabled
0= Internal External Switchover mode disabled
BODEN<1:0>: Brown-out Detect Enable bits
11= BOD enabled and SBODEN bit disabled
10= BOD enabled while running and disabled in Sleep. SBODEN bit disabled.
01= SBODEN in Register 2-6 controls BOD function
00= BOD and SBODEN disabled
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
CPD: Code Protection Data bit
1= Data memory is not protected
0= Data memory is external read protected
CP: Code Protection bit
1= Program memory is not code-protected
0= Program memory is external read and write-protected
MCLRE: MCLR Pin Function Select bit
1= MCLR pin is MCLR function and weak internal pull-up is enabled
0= MCLR pin is alternate function, MCLR function is internally disabled
(1)
PWRTE: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled and can be enabled using SWDTEN in Register 12-2
FOSC<2:0>: Oscillator Selection bits
000 = LP oscillator: Low power crystal on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT
001 = XT oscillator: Crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT
010 = HS oscillator: High-speed crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT
011 = EC: I/O function on RA4/T1G/OSC2/CLKOUT, CLKIN on RA5/T1CKI/OSC1/CLKIN
100 = INTOSCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT, I/O function on RA5/T1CKI/OSC1/CLKIN
101 = INTOSC oscillator: CLKOUT function on RA4/T1G/OSC2/CLKOUT, I/O function on RA5/T1CKI/OSC1/CLKIN
110 = EXTRCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT, RC on RA5/T1CKI/OSC1/CLKIN
111 = EXTRC oscillator: CLKOUT function on RA4/T1G/OSC2/CLKOUT, RC on RA5/T1CKI/OSC1/CLKIN
Note 1: Enabling Brown-out Detect does not automatically enable the Power-up Timer (PWRT).
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS41232B-page 112
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
They are not affected by a WDT wake-up since this is
viewed as the resumption of normal operation. TO and
12.2 Reset
The PIC12F635/PIC16F636/639 differentiates between
various kinds of Reset:
PD bits are set or cleared differently in different Reset
situations, as indicated in Table 12-3. These bits are
used in software to determine the nature of the Reset.
See Table 12-4 for a full description of Reset states of
all registers.
a) Power-on Reset (POR)
b) Wake-up Reset (WUR)
c) WDT Reset during normal operation
d) WDT Reset during Sleep
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 12-1.
e) MCLR Reset during normal operation
f) MCLR Reset during Sleep
g) Brown-out Detect (BOD)
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 15.0 “Electrical
Specifications” for pulse width specifications.
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:
• Power-on Reset
• MCLR Reset
• MCLR Reset during Sleep
• WDT Reset
• Brown-out Detect
FIGURE 12-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Sleep
WURE
External Reset
Sleep
Wake-up Interrupt
RA3 Change
MCLR/VPP pin
WDT
WDT
Module
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out(1)
Detect
<1>
BODEN
BODEN<0>
SBODEN
S
R
OST/PWRT
Chip_Reset
OST
10-bit Ripple Counter
Q
OSC1/
CLKI pin
PWRT
11-bit Ripple Counter
LFINTOSC
Enable PWRT
Enable OST
Note 1: Refer to the Configuration Word register (Register 12-1).
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 113
PIC12F635/PIC16F636/639
12.3 Power-on Reset
12.5 MCLR
The on-chip POR circuit holds the chip in Reset until VDD
has reached a high enough level for proper operation. To
take advantage of the POR, simply connect the MCLR
pin through a resistor to VDD. This will eliminate external
RC components usually needed to create Power-on
Reset. A maximum rise time for VDD is required. See
Section 15.0 “Electrical Specifications” for details. If
the BOD is enabled, the maximum rise time specification
does not apply. The BOD circuitry will keep the device in
Reset until VDD reaches VBOD (see Section 12.6
“Brown-out Detect (BOD)”).
PIC12F635/PIC16F636/639 has a noise filter in the
MCLR Reset path. The filter will ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low. See Figure 12-2 for the recommended
MCLR circuit.
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
cleared, MCLR is internally tied to VDD and an internal
weak pull-up is enabled for the MCLR pin. In-Circuit
Serial Programming is not affected by selecting the
internal MCLR option.
Note:
The POR circuit does not produce an
internal Reset when VDD declines. To
re-enable the POR, VDD must reach VSS
for a minimum of 100 μs.
FIGURE 12-2:
RECOMMENDED MCLR
CIRCUIT
VDD
R1
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
PIC12F635/PIC16F636/639
1 kΩ (or greater)
MCLR
For additional information, refer to the Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
C1
0.1 μF
(optional, not critical)
12.4 Wake-up Reset (WUR)
The PIC12F635/PIC16F636/639 has a modified wake-
up from Sleep mechanism. When waking from Sleep,
the WUR function resets the device and releases Reset
when VDD reaches an acceptable level.
If the WURE bit is enabled (‘0’) in the Configuration
Word register, the device will Wake-up Reset from
Sleep through one of the following events:
1. On any event that causes a wake-up event. The
peripheral must be enabled to generate an
interrupt or wake-up, GIE state is ignored.
2. When WURE is enabled, RA3 will always
generate an interrupt-on-change signal during
Sleep.
The WUR, POR and BOD bits in the PCON register
and the TO and PD bits in the Status register can be
used to determine the cause of device Reset.
To allow WUR upon RA3 change:
1. Enable the WUR function, WURE Configuration
Bit = 0.
2. Enable RA3 as an input, MCLRE Configuration
Bit = 0.
3. Read PORTA to establish the current state of
RA3.
4. Execute SLEEPinstruction.
5. When RA3 changes state, the device will wake-
up and then reset. The WUR bit in PCON will be
cleared to ‘0’.
DS41232B-page 114
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
On any Reset (Power-on, Brown-out Detect, Watchdog
Timer, etc.), the chip will remain in Reset until VDD rises
above VBOD (see Figure 12-3). The Power-up Timer
will now be invoked, if enabled and will keep the chip in
Reset an additional nominal 64 ms.
12.6 Brown-out Detect (BOD)
The BODEN0 and BODEN1 bits in the Configuration
Word register select one of four BOD modes. Two
modes have been added to allow software or hardware
control of the BOD enable. When BODEN<1:0> = 01,
the SBODEN bit (PCON<4>) enables/disables the BOD
allowing it to be controlled in software. By selecting
BODEN<1:0>, the BOD is automatically disabled in
Sleep to conserve power and enabled on wake-up. In
this mode, the SBODEN bit is disabled. See
Register 12-1 for the Configuration Word definition.
Note:
The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word
register.
If VDD drops below VBOD while the Power-up Timer is
running, the chip will go back into a Brown-out Detect
and the Power-up Timer will be re-initialized. Once VDD
rises above VBOD, the Power-up Timer will execute a
64 ms Reset.
If VDD falls below VBOD for greater than parameter
(TBOD) (see Section 15.0 “Electrical Specifications”),
the Brown-out situation will reset the device. This will
occur regardless of VDD slew rate. A Reset is not
ensured to occur if VDD falls below VBOD for less than
parameter (TBOD).
FIGURE 12-3:
BROWN-OUT DETECT SITUATIONS
VDD
VBOD
Internal
Reset
(1)
64 ms
VDD
VBOD
Internal
Reset
< 64 ms
(1)
64 ms
VDD
VBOD
Internal
Reset
(1)
64 ms
Note 1: Nominal 64 ms delay only if PWRTE bit is programmed to ‘0’.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 115
PIC12F635/PIC16F636/639
12.7 Time-out Sequence
12.8 Power Control (PCON) Register
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired, then
OST is activated after the PWRT time-out has expired.
The total time-out will vary based on oscillator
configuration and PWRTE bit status. For example, in EC
mode with PWRTE bit erased (PWRT disabled), there
will be no time-out at all. Figure 12-4, Figure 12-5 and
Figure 12-6 depict time-out sequences. The device can
execute code from the INTOSC, while OST is active, by
enabling Two-Speed Start-up or Fail-Safe Clock Monitor
(See Section 3.6.2 “Two-Speed Start-up Sequence”
and Section 3.7 “Fail-Safe Clock Monitor”).
The Power Control register, PCON (address 8Eh), has
two Status bits to indicate what type of Reset that last
occurred.
Bit 0 is BOD (Brown-out). BOD is unknown on Power-
on Reset. It must then be set by the user and checked
on subsequent Resets to see if BOD = 0, indicating that
a Brown-out has occurred. The BOD Status bit is a
“don’t care” and is not necessarily predictable if the
brown-out circuit is disabled (BODEN<1:0> = 00in the
Configuration Word register).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., VDD may have
gone too low).
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 12-5). This is useful for testing purposes or
to synchronize more than one PIC12F635/PIC16F636/
639 device operating in parallel.
For more information, see Section 4.2.3 “Ultra Low-
Power Wake-up” and Section 12.6 “Brown-out
Detect (BOD)”.
Table 12-5 shows the Reset conditions for some
special registers, while Table 12-4 shows the Reset
conditions for all the registers.
TABLE 12-1: TIME-OUT IN VARIOUS SITUATIONS
Power-up
Oscillator
Brown-out Detect
Wake-up
Configuration
from Sleep
PWRTE = 0
PWRTE = 1
PWRTE = 0
PWRTE = 1
XT, HS, LP
TPWRT + 1024 • TOSC
TPWRT
1024 • TOSC
—
TPWRT + 1024 • TOSC
TPWRT
1024 • TOSC
—
1024 • TOSC
—
RC, EC, INTOSC
TABLE 12-2: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT DETECT
Value on
POR, BOD,
WUR
Value on
all other
Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
03h
STATUS
PCON
IRP
—
RP1
—
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
--01 q-qq --0u u-uu
8Eh
ULPWUE SBODEN WUR
—
POR
BOD
Legend:
u= unchanged, x= unknown, — = unimplemented bit, reads as ‘0’, q= value depends on condition. Shaded cells are
not used by BOD.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
DS41232B-page 116
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
TABLE 12-3: PCON BITS AND THEIR SIGNIFICANCE
POR
BOD
WUR
TO
PD
Condition
0
u
u
u
u
u
u
u
x
0
u
u
u
u
u
0
x
u
u
u
u
u
0
u
1
1
0
0
u
1
1
1
1
1
u
0
u
0
0
1
Power-on Reset
Brown-out Detect
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during Sleep
Wake-up Reset during Sleep
Brown-out Detect during Sleep
Legend: u= unchanged, x= unknown
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 117
PIC12F635/PIC16F636/639
FIGURE 12-4:
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
OST Time-out
Internal Reset
TOST
FIGURE 12-5:
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
OST Time-out
Internal Reset
TOST
FIGURE 12-6:
TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
OST Time-out
Internal Reset
TOST
DS41232B-page 118
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS
MCLR Reset
Wake-up from Sleep
through Interrupt
Wake-up from Sleep
through WDT Time-out
Power-on
Reset
Wake-up Reset
WDT Reset
Brown-out Detect(1)
Wake-up Reset
Register
Address
W
—
00h/80h
01h
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
--xx xx00
--xx xx00
---0 0000
0000 0000
0000 00-0
xxxx xxxx
xxxx xxxx
0000 0000
---0 1000
0000 0000
---- --10
1111 1111
--11 1111
--11 1111
0000 00-0
--01 q-qq
-110 x000
---0 0000
--11 -111
--00 0000
--11 -111
0-0- 0000
0000 0000
0000 0000
---- x000
---- ----
xxxx xxxx
-000 ----
--00 -000
00-- --00
uuuu uuuu
xxxx xxxx
uuuu uuuu
0000 0000
000q quuu(4)
uuuu uuuu
--00 0000
--00 0000
---0 0000
0000 0000
0000 00-0
uuuu uuuu
uuuu uuuu
uuuu uuuu
---0 1000
0000 0000
---- --10
1111 1111
--11 1111
--11 1111
0000 00-0
--0u u-uu(1,5)
-110 x000
---u uuuu
--11 -111
--00 0000
--11 -111
0-0- 0000
0000 0000
0000 0000
---- q000
---- ----
uuuu uuuu
-000 ----
--00 -000
00-- --00
uuuu uuuu
uuuu uuuu
uuuu uuuu
PC + 1(3)
INDF
TMR0
PCL
02h/82h
03h/83h
04h/84h
05h
STATUS
FSR
uuuq quuu(4)
uuuu uuuu
--uu uu00
--uu uu00
---u uuuu
uuuu uuuu(2)
uuuu uu-u(2)
uuuu uuuu
uuuu uuuu
-uuu uuuu
---u uuuu
uuuu uuuu
---- --uu
uuuu uuuu
--uu 1uuu
--uu 1uuu
uuuu uu-u
--0u u-uu
-uuu uuuu
---u uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
u-u- uuuu
uuuu uuuu
uuuu uuuu
---- uuuu
---- ----
uuuu uuuu
-uuu ----
--uu -uuu
uu-- --uu
PORTA
PORTC(6)
PCLATH
INTCON
PIR1
07h
0Ah/8Ah
0Bh/8Bh
0Ch
TMR1L
TMR1H
T1CON
WDTCON
CMCON0
CMCON1
OPTION_REG
TRISA
0Eh
0Fh
10h
18h
19h
1Ah
81h
85h
TRISC(6)
87h
PIE1
8Ch
PCON
8Eh
OSCCON
OSCTUNE
WPUDA
IOCA
8Fh
90h
95h
96h
WDA
97h
VRCON
EEDAT
EEADR
EECON1
EECON2
ADRESL
ADCON1
LVDCON
CRCON
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
94h
110h
Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’, q= value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 12-5 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
6: PIC16F636/639 only.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 119
PIC12F635/PIC16F636/639
TABLE 12-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program
Counter
Status
Register
PCON
Register
Condition
Power-on Reset
000h
000h
0001 1xxx
000u uuuu
0001 0uuu
0000 uuuu
uuu0 0uuu
0001 1uuu
uuu1 0uuu
0001 1xxx
--01 --0x
--0u --uu
--0u --uu
--0u --uu
--uu --uu
--01 --10
--uu --uu
--01 --0x
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Reset
000h
000h
WDT Wake-up
PC + 1
000h
PC + 1(1)
Brown-out Detect
Interrupt Wake-up from Sleep
Wake-up Reset
000h
Legend: u= unchanged, x= unknown, – = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and the Global Interrupt Enable bit, GIE, is set, the PC is loaded
with the interrupt vector (0004h) after execution of PC + 1.
DS41232B-page 120
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
For external interrupt events, such as the INT pin or
PORTA change interrupt, the interrupt latency will be
12.9 Interrupts
The PIC12F635/PIC16F636/639 has 8 sources of
interrupt:
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 12-8). The latency is the same for one or two-
cycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
• External Interrupt RA2/INT
• Timer0 Overflow Interrupt
• PORTA Change Interrupts
• 2 Comparator Interrupts
• Timer1 Overflow Interrupt
• EEPROM Data Write Interrupt
• Fail-Safe Clock Monitor Interrupt
Note 1: Individual interrupt flag bits are set,
regardless of the status of their
corresponding mask bit or the GIE bit.
The Interrupt Control register (INTCON) and Peripheral
Interrupt Request Register 1 (PIR1) record individual
interrupt requests in flag bits. The INTCON register
also has individual and global interrupt enable bits.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts, which were
ignored, are still pending to be serviced
when the GIE bit is set again.
A Global Interrupt Enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in the
INTCON register and PIE1 register. GIE is cleared on
Reset.
For additional information on Timer1, comparators or
data EEPROM modules, refer to the respective
peripheral section.
The Return from Interrupt instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
12.9.1
RA2/INT INTERRUPT
The following interrupt flags are contained in the
INTCON register:
External interrupt on RA2/INT pin is edge-triggered;
either rising if the INTEDG bit (OPTION<6>) is set, or
falling if the INTEDG bit is clear. When a valid edge
appears on the RA2/INT pin, the INTF bit (INTCON<1>)
is set. This interrupt can be disabled by clearing the
INTE control bit (INTCON<4>). The INTF bit must be
cleared in software in the Interrupt Service Routine
before re-enabling this interrupt. The RA2/INT interrupt
can wake-up the processor from Sleep if the INTE bit
was set prior to going into Sleep. The status of the GIE
bit decides whether or not the processor branches to the
interrupt vector following wake-up (0004h). See
Section 12.12 “Power-Down Mode (Sleep)” for details
on Sleep and Figure 12-10 for timing of wake-up from
Sleep through RA2/INT interrupt.
• INT Pin Interrupt
• PORTA Change Interrupt
• TMR0 Overflow Interrupt
The peripheral interrupt flags are contained in the
special register, PIR1. The corresponding interrupt
enable bit is contained in special register, PIE1.
The following interrupt flags are contained in the PIR1
register:
• EEPROM Data Write Interrupt
• 2 Comparator Interrupts
• Timer1 Overflow Interrupt
• Fail-Safe Clock Monitor Interrupt
Note:
The CMCON0 (19h) register must be
initialized to configure an analog channel
as a digital input. Pins configured as
analog inputs will read ‘0’.
When an interrupt is serviced:
• The GIE is cleared to disable any further interrupt.
• The return address is pushed onto the stack.
• The PC is loaded with 0004h.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 121
PIC12F635/PIC16F636/639
12.9.2
TMR0 INTERRUPT
12.9.3
PORTA INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
the T0IF (INTCON<2>) bit. The interrupt can be
enabled/disabled by setting/clearing T0IE (INTCON<5>)
bit. See Section 5.0 “Timer0 Module” for operation of
the Timer0 module.
An input change on PORTA change sets the RAIF
(INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the RAIE (INTCON<3>)
bit. Plus, individual pins can be configured through the
IOCA register.
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
FIGURE 12-7:
INTERRUPT LOGIC
IOC-RA0
IOCA0
IOC-RA1
IOCA1
IOC-RA2
IOCA2
IOC-RA3
IOCA3
IOC-RA4
IOCA4
IOC-RA5
IOCA5
Wake-up (If in Sleep mode)
Interrupt to CPU
T0IF
T0IE
LVDIF
LVDIE
INTF
INTE
RAIF
TMR1IF
TMR1IE
RAIE
C1IF
C1IE
PEIE
GIE
(1)
C2IF
(1)
C2IE
EEIF
EEIE
OSFIF
OSFIE
CRIF
CRIE
Note 1: PIC16F636/639 only.
DS41232B-page 122
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 12-8:
INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(3)
CLKOUT
(4)
INT pin
(1)
(1)
(5)
(2)
Interrupt Latency
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction Flow
PC
0004h
PC + 1
PC + 1
—
0005h
Inst (0005h)
Inst (0004h)
PC
Instruction
Fetched
Inst (PC)
Inst (PC + 1)
Inst (0004h)
Instruction
Executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC – 1)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 15.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 12-6: SUMMARY OF INTERRUPT REGISTERS
Value on
POR, BOD,
WUR
Value on
all other
Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh INTCON
GIE
EEIF
EEIE
PEIE
LVDIF
LVDIE
T0IE
CRIF
CRIE
INTE
RAIE
C1IF
C1IE
T0IF
INTF
—
RAIF
0000 0000 0000 0000
(1)
0Ch
PIR1
PIE1
C2IF
C2IE
OSFIF
OSFIE
TMR1IF 0000 00-0 0000 00-0
TMR1IE 0000 00-0 0000 00-0
(1)
8Ch
—
Legend:
x= unknown, u= unchanged, — = unimplemented, read as ‘0’, q= value depends upon condition.
Shaded cells are not used by the interrupt module.
Note 1: PIC16F636/639 only.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 123
PIC12F635/PIC16F636/639
12.10 Context Saving During Interrupts
Note:
The PIC12F635/PIC16F636/639 normally
does not require saving the PCLATH.
However, if computed GOTO’s are used in
the ISR and the main code, the PCLATH
must be saved and restored in the ISR.
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W and Status
registers). This must be implemented in software.
Since the lower 16 bytes of all banks are common in the
PIC12F635/PIC16F636/639 (see Figure 2-2), temporary
holding registers, W_TEMP and STATUS_TEMP, should
be placed in here. These 16 locations do not require
banking and therefore, make it easier to context save and
restore. The same code shown in Example 12-1 can be
used to:
• Store the W register.
• Store the Status register.
• Execute the ISR code.
• Restore the Status (and Bank Select Bit register).
• Restore the W register.
EXAMPLE 12-1:
SAVING STATUS AND W REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
:
W_TEMP
STATUS,W
STATUS
;Copy W to TEMP register
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
STATUS_TEMP
:(ISR)
:
;Insert user code here
SWAPF
STATUS_TEMP,W
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into Status register
;Swap W_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Swap W_TEMP into W
DS41232B-page 124
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
A new prescaler has been added to the path between
the INTRC and the multiplexers used to select the path
for the WDT. This prescaler is 16 bits and can be
programmed to divide the INTRC by 32 to 65536,
giving the WDT a nominal range of 1 ms to 268s.
12.11 Watchdog Timer (WDT)
The PIC12F635/PIC16F636/639 WDT is code and
functionally compatible with other PIC16F WDT
modules and adds a 16-bit prescaler to the WDT. This
allows the user to have a scaler value for the WDT and
TMR0 at the same time. In addition, the WDT time-out
value can be extended to 268 seconds. WDT is cleared
under certain conditions described in Table 12-7.
12.11.2 WDT CONTROL
The WDTE bit is located in the Configuration Word
register. When set, the WDT runs continuously.
12.11.1 WDT OSCILLATOR
When the WDTE bit in the Configuration Word register
is set, the SWDTEN bit (WDTCON<0>) has no effect.
If WDTE is clear, then the SWDTEN bit can be used to
enable and disable the WDT. Setting the bit will enable
it and clearing the bit will disable it.
The WDT derives its time base from the 31 kHz
LFINTOSC. The LTS bit does not reflect that the
LFINTOSC is enabled.
The value of WDTCON is ‘---0 1000’ on all Resets.
This gives a nominal time base of 16 ms, which is
compatible with the time base generated with previous
PIC12F635/PIC16F636/639 microcontroller versions.
The PSA and PS<2:0> bits (OPTION_REG) have the
same function as in previous versions of the PIC16F
family of microcontrollers. See Section 5.0 “Timer0
Module” for more information.
Note:
When the Oscillator Start-up Timer (OST)
is invoked, the WDT is held in Reset,
because the WDT Ripple Counter is used
by the OST to perform the oscillator delay
count. When the OST count has expired,
the WDT will begin counting (if enabled).
FIGURE 12-9:
WATCHDOG TIMER BLOCK DIAGRAM
0
1
From TMR0 Clock Source
Prescaler(1)
16-bit WDT Prescaler
8
PSA
PS<2:0>
To TMR0
PSA
31 kHz
LFINTOSC Clock
WDTPS<3:0>
1
0
WDTE from Configuration Word Register
SWDTEN from WDTCON
WDT Time-out
Note 1: This is the shared Timer0/WDT prescaler. See Section 5.4 “Prescaler” for more information.
TABLE 12-7: WDT STATUS
Conditions
WDT
WDTE = 0
CLRWDTCommand
Cleared
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, HFINTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
Cleared until the end of OST
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 125
PIC12F635/PIC16F636/639
REGISTER 12-2: WDTCON – WATCHDOG TIMER CONTROL REGISTER (ADDRESS: 18h)
U-0
—
U-0
—
U-0
—
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN(1)
bit 7
bit 0
bit 7-5
bit 4-1
Unimplemented: Read as ‘0’
WDTPS<3:0>: Watchdog Timer Period Select bits
Bit Value = Prescale Rate
0000 = 1:32
0001 = 1:64
0010 = 1:128
0011 = 1:256
0100 = 1:512
0101 = 1:1024
0110 = 1:2048
0111 = 1:4096
1000 = 1:8192
1001 = 1:16394
1010 = 1:32768
1011 = 1:65536
1100 = reserved
1101 = reserved
1110 = reserved
1111 = reserved
bit 0
SWDTEN: Software Enable/Disable for Watchdog Timer bit(1)
1= WDT is turned on
0= WDT is turned off
Note 1: If WDTE configuration bit = 1, then WDT is always enabled, irrespective of this
control bit. If WDTE configuration bit = 0, then it is possible to turn WDT on/off with
this control bit.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
TABLE 12-8: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
18h
Name
WDTCON
OPTION_REG
Bit 7
Bit 6
Bit 5
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN
81h
RAPU INTEDG
CPD CP
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for operation of all Configuration Word register bits.
T0CS
T0SE
PSA
PS2
PS1
PS0
2007h(1) CONFIG
MCLRE PWRTE
WDTE
FOSC2 FOSC1 FOSC0
DS41232B-page 126
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
6. External Interrupt from INT pin.
12.12 Power-Down Mode (Sleep)
Other peripherals cannot generate interrupts, since
during Sleep, no on-chip clocks are present.
The Power-down mode is entered by executing a
SLEEPinstruction.
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction, then branches to the interrupt
address (0004h). In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOPafter the SLEEPinstruction.
If the Watchdog Timer is enabled:
• WDT will be cleared but keeps running.
• PD bit in the Status register is cleared.
• TO bit is set.
• Oscillator driver is turned off.
• I/O ports maintain the status they had before
SLEEPwas executed (driving high, low or
high-impedance).
For lowest current consumption in this mode, all I/O pins
should be either at VDD or VSS, with no external circuitry
drawing current from the I/O pin and the comparators
and CVREF should be disabled. I/O pins that are high-
impedance inputs should be pulled high or low externally
to avoid switching currents caused by floating inputs.
The T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTA should be considered.
Note:
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the corresponding
interrupt flag bits set, the device will
immediately wake-up from Sleep. The
SLEEPinstruction is completely executed.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
The MCLR pin must be at a logic high level.
Note 1: It should be noted that a Reset generated
by a WDT time-out does not drive MCLR
pin low.
Note:
If WUR is enabled (WURE = 0 in
Configuration Word), then the Wake-up
Reset module will force a device Reset.
2: The Analog Front-End (AFE) section in
the PIC16F639 device is independent of
the microcontroller’s power-down mode
(Sleep). See Section 11.32.2.3 “Sleep
Command” for AFE’s Sleep mode.
12.12.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
12.12.1 WAKE-UP FROM SLEEP
• If the interrupt occurs before the execution of a
SLEEPinstruction, the SLEEPinstruction will
complete as a NOP. Therefore, the WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
The device can wake-up from Sleep through one of the
following events:
1. External Reset input on MCLR pin.
2. Watchdog Timer wake-up (if WDT was enabled).
3. Interrupt from RA2/INT pin, PORTA change or a
peripheral interrupt.
• If the interrupt occurs during or after the
execution of a SLEEPinstruction, the device will
immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT prescaler
and postscaler (if enabled) will be cleared, the TO
bit will be set and the PD bit will be cleared.
The first event will cause a device Reset. The two latter
events are considered a continuation of program
execution. The TO and PD bits in the Status register
can be used to determine the cause of device Reset.
The PD bit, which is set on power-up, is cleared when
Sleep is invoked. TO bit is cleared if WDT wake-up
occurred.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
The following peripheral interrupts can wake the device
from Sleep:
1. TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
To ensure that the WDT is cleared, a CLRWDTinstruction
should be executed before a SLEEPinstruction.
2. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
3. EEPROM write operation completion.
4. Comparator output changes state.
5. Interrupt-on-change.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 127
PIC12F635/PIC16F636/639
FIGURE 12-10:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
(2)
TOST
INTF Flag
(INTCON<1>)
Interrupt Latency(3)
GIE bit
(INTCON<7>)
Processor in
Sleep
INSTRUCTION FLOW
PC
PC
PC + 1
PC + 2
PC + 2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = Sleep
Inst(PC – 1)
Fetched
Instruction
Executed
Dummy Cycle
Dummy Cycle
Sleep
Inst(PC + 1)
Inst(0004h)
Note 1: XT, HS or LP Oscillator mode assumed.
2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes.
3: GIE = 1assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.
4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
12.13 Code Protection
12.14 ID Locations
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out using ICSP for verification purposes.
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during Program/Verify mode.
Only the Least Significant 7 bits of the ID locations are
used.
Note:
The entire data EEPROM and Flash
program memory will be erased when the
code protection is turned off. See the
“PIC12F6XX/16F6XX Memory Program-
ming Specification” (DS41204) for more
information.
DS41232B-page 128
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
12.15 In-Circuit Serial Programming
12.16 In-Circuit Debugger
The PIC12F635/PIC16F636/639 microcontrollers can
be serially programmed while in the end application
circuit. This is simply done with two lines for clock and
data and three other lines for:
Since in-circuit debugging requires the loss of clock,
data and MCLR pins, MPLAB® ICD 2 development with
a 14-pin device is not practical. A special 20-pin
PIC16F636 ICD device is used with MPLAB ICD 2 to
provide separate clock, data and MCLR pins and frees
all normally available pins to the user.
• Power
• Ground
Use of the ICD device requires the purchase of a
special header. On the top of the header is an
MPLAB ICD 2 connector. On the bottom of the
header is a 14-pin socket that plugs into the user’s
target via the 14-pin stand-off connector.
• Programming Voltage
This allows customers to manufacture boards with
unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
When the ICD pin on the PIC16F636 ICD device is held
low, the In-Circuit Debugger functionality is enabled.
This function allows simple debugging functions when
used with MPLAB ICD 2. When the microcontroller has
this feature enabled, some of the resources are not
available for general use. Table 12-9 shows which
features are consumed by the background debugger:
The device is placed into a Program/Verify mode by hold-
ing the RA0 and RA1 pins low, while raising the MCLR
(VPP) pin from VIL to VIHH. See the “PIC12F6XX/16F6XX
Memory Programming Specification” (DS41204) for
more information. RA0 becomes the programming data
and RA1 becomes the programming clock. Both RA0
and RA1 are Schmitt Trigger inputs in this mode.
TABLE 12-9: DEBUGGER RESOURCES
After Reset, to place the device into Program/Verify
mode, the Program Counter (PC) is at location 00h. A
6-bit command is then supplied to the device.
Depending on the command, 14 bits of program data
are then supplied to or from the device, depending on
whether the command was a load or a read. For
complete details of serial programming, please refer to
the “PIC12F6XX/16F6XX Memory Programming
Specification” (DS41204).
Resource
I/O pins
Stack
Description
ICDCLK, ICDDATA
1 level
Program Memory Address 0h must be NOP
700h-7FFh
For more information, see the “MPLAB® ICD 2 In-
Circuit Debugger User’s Guide” (DS51331), available
on Microchip’s web site (www.microchip.com).
A typical In-Circuit Serial Programming connection is
shown in Figure 12-11.
FIGURE 12-12:
20-Pin PDIP
20-PIN ICD PINOUT
FIGURE 12-11:
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
In-Circuit Debug Device
To Normal
1
20
NC
ICDMCLR/VPP
VDD
ICDCLK
ICDDATA
VSS
RA0
RA1
RA2
RC0
RC1
RC2
Connections
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
External
Connector
Signals
*
RA5
RA4
RA3
RC5
RC4
RC3
PIC16F636
+5V
0V
VDD
VSS
VPP
MCLR/VPP/RA3
RA1
RA0
CLK
10
11
ICD
ENPORT
Data I/O
*
*
*
To Normal
Connections
*Isolation devices (as required).
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 129
PIC12F635/PIC16F636/639
NOTES:
DS41232B-page 130
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
For example, a CLRF GPIOinstruction will read GPIO,
13.0 INSTRUCTION SET SUMMARY
clear all the data bits, then write the result back to
GPIO. This example would have the unintended result
of clearing the condition that set the GPIF flag.
The PIC12F635/PIC16F636/639 instruction set is
highly orthogonal and is comprised of three basic
categories:
TABLE 13-1: OPCODE FIELD
DESCRIPTIONS
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
Field
Description
Each PIC16FXXX instruction is a 14-bit word divided
into an opcode, which specifies the instruction type
and one or more operands, which further specify the
operation of the instruction. The formats for each of the
categories is presented in Figure 13-1, while the
various opcode fields are summarized in Table 13-1.
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
Don’t care location (= 0or 1).
Table 13-2 lists the instructions recognized by the
MPASMTM assembler. A complete description of each
instruction is also available in the “PICmicro® Mid-Range
MCU Family Reference Manual” (DS33023).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
PC Program Counter
TO Time-out bit
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
PD Power-down bit
FIGURE 13-1:
GENERAL FORMAT FOR
INSTRUCTIONS
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the
operation, while ‘f’ represents the address of the file in
which the bit is located.
Byte-oriented file register operations
13
8
7
6
0
OPCODE
d
f (FILE #)
For literal and control operations, ‘k’ represents an
8-bit or 11-bit constant, or literal value.
d = 0for destination W
d = 1for destination f
f = 7-bit file register address
One instruction cycle consists of four oscillator periods;
for an oscillator frequency of 4 MHz, this gives a normal
instruction execution time of 1 μs. All instructions are
executed within a single instruction cycle, unless a
conditional test is true, or the program counter is
changed as a result of an instruction. When this occurs,
the execution takes two instruction cycles, with the
second cycle executed as a NOP.
Bit-oriented file register operations
13 10 9
b (BIT #)
7
6
0
OPCODE
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
Note: To maintain upward compatibility with
future products, do not use the OPTION
and TRISinstructions.
General
13
8
7
0
0
OPCODE
k (literal)
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
k = 8-bit immediate value
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
13.1 Read-Modify-Write Operations
k (literal)
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified and
the result is stored according to either the instruction, or
the destination designator ‘d’. A read operation is
performed on a register even if the instruction writes to
that register.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 131
PIC12F635/PIC16F636/639
TABLE 13-2: PIC12F635/PIC16F636/639 INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00 0111 dfff ffff C, DC, Z
1, 2
1, 2
2
00 0101 dfff ffff
00 0001 lfff ffff
00 0001 0xxx xxxx
00 1001 dfff ffff
00 0011 dfff ffff
00 1011 dfff ffff
00 1010 dfff ffff
00 1111 dfff ffff
00 0100 dfff ffff
00 1000 dfff ffff
00 0000 lfff ffff
00 0000 0xx0 0000
00 1101 dfff ffff
00 1100 dfff ffff
Z
Z
Z
Z
Z
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1, 2
1, 2
1, 2, 3
1, 2
1, 2, 3
1, 2
1, 2
Z
Z
Z
Move W to f
No Operation
-
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
C
C
1, 2
1, 2
1, 2
1, 2
1, 2
00 0010 dfff ffff C, DC, Z
00 1110 dfff ffff
00 0110 dfff ffff
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01 00bb bfff ffff
1, 2
1, 2
3
01 01bb bfff ffff
01 10bb bfff ffff
01 11bb bfff ffff
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11 111x kkkk kkkk C, DC, Z
11 1001 kkkk kkkk
10 0kkk kkkk kkkk
Z
00 0000 0110 0100 TO, PD
10 1kkk kkkk kkkk
Inclusive OR literal with W
Move literal to W
11 1000 kkkk kkkk
11 00xx kkkk kkkk
00 0000 0000 1001
11 01xx kkkk kkkk
00 0000 0000 1000
Z
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
00 0000 0110 0011 TO, PD
11 110x kkkk kkkk C, DC, Z
11 1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the “PICmicro® Mid-Range MCU
Family Reference Manual” (DS33023).
DS41232B-page 132
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
13.2 Instruction Descriptions
ADDLW
Add Literal and W
BCF
Bit Clear f
Syntax:
[ label ] ADDLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] BCF f,b
Operands:
Operation:
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
(W) + k → (W)
Operation:
0 → (f<b>)
Status Affected: C, DC, Z
Status Affected:
Description:
None
Description:
The contents of the W register are
added to the eight-bit literal ‘k’ and
the result is placed in the W register.
Bit ‘b’ in register ‘f’ is cleared.
ADDWF
Add W and f
BSF
Bit Set f
Syntax:
[ label ] ADDWF f,d
Syntax:
[ label ] BSF f,b
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
(W) + (f) → (destination)
Operation:
1 → (f<b>)
Status Affected: C, DC, Z
Status Affected:
Description:
None
Description:
Add the contents of the W register
Bit ‘b’ in register ‘f’ is set.
with register ‘f’. If ‘d’ is ‘0’, the result
is stored in the W register. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
ANDLW
AND Literal with W
BTFSC
Bit Test f, Skip if Clear
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] BTFSC f,b
Operands:
Operation:
Status Affected:
Description:
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
(W) .AND. (k) → (W)
Operation:
skip if (f<b>) = 0
Z
Status Affected: None
The contents of W register are
AND’ed with the eight-bit literal
‘k’. The result is placed in the W
register.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is discarded and a NOP
is executed instead, making this a
2-cycle instruction.
ANDWF
AND W with f
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] ANDWF f,d
Syntax:
[ label ] BTFSS f,b
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operation:
(W) .AND. (f) → (destination)
Operation:
skip if (f<b>) = 1
Status Affected:
Description:
Z
Status Affected: None
AND the W register with register
‘f’. If ‘d’ is ‘0’, the result is stored in
the W register. If ‘d’ is ‘1’, the
Description: If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next instruction is
discarded and a NOPis executed instead,
making this a 2-cycle instruction.
result is stored back in register ‘f’.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 133
PIC12F635/PIC16F636/639
CALL
Call Subroutine
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL k
0 ≤ k ≤ 2047
Syntax:
[ label ] CLRWDT
Operands:
Operation:
Operands:
Operation:
None
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Status Affected: None
Status Affected: TO, PD
Description:
Call subroutine. First, return address
(PC + 1) is pushed onto the stack.
The eleven-bit immediate address is
loaded into PC bits <10:0>. The
upper bits of the PC are loaded from
PCLATH. CALLis a two-cycle
instruction.
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT. Status bits,
TO and PD, are set.
CLRF
Clear f
COMF
Complement f
Syntax:
[label] CLRF
0 ≤ f ≤ 127
f
Syntax:
[ label ] COMF f,d
Operands:
Operation:
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
00h → (f)
1 → Z
Operation:
(f) → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
The contents of register ‘f’ are
cleared and the Z bit is set.
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’,
the result is stored back in
register ‘f’.
CLRW
Clear W
DECF
Decrement f
Syntax:
[ label ] CLRW
Syntax:
[ label ] DECF f,d
Operands:
Operation:
None
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
00h → (W)
1 → Z
Operation:
(f) – 1 → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
W register is cleared. Zero bit (Z)
is set.
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘0’, the result is
stored back in register ‘f’.
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DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ] INCFSZ f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) – 1 → (destination);
skip if result = 0
Operation:
(f) + 1 → (destination),
skip if result = 0
Status Affected: None
Status Affected: None
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’,
the result is placed back in register ‘f’.
If the result is ‘1’, the next instruction
is executed. If the result is ‘0’, then a
NOPis executed instead, making it a
2-cycle instruction.
incremented. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’, the
result is placed back in
register ‘f’.
If the result is ‘1’, the next instruction
is executed. If the result is ‘0’, a NOPis
executed instead, making it a 2-cycle
instruction.
IORLW
Inclusive OR Literal with W
GOTO
Unconditional Branch
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
[ label ] GOTO k
0 ≤ k ≤ 2047
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
(W) .OR. k → (W)
Z
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Status Affected: None
The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
Description:
GOTOis an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTOis a two-cycle
instruction.
IORWF
Inclusive OR W with f
INCF
Increment f
Syntax:
[ label ] IORWF f,d
Syntax:
[ label ] INCF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) .OR. (f) → (destination)
Operation:
(f) + 1 → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
© 2005 Microchip Technology Inc.
Preliminary
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MOVF
Move f
MOVWF
Move W to f
[ label ] MOVWF
0 ≤ f ≤ 127
(W) → (f)
Syntax:
Operands:
[ label ] MOVF f,d
Syntax:
f
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operation:
(f) → (dest)
None
Status Affected:
Encoding:
Z
00
0000
1fff
ffff
00
1000
dfff
ffff
Move data from W register to
register ‘f’.
Description:
The contents of register ‘f’ are
moved to a destination dependent
upon the status of ‘d’. If ‘d’ = 0,
destination is W register. If d = 1,
the destination is file register ‘f’
itself. d = 1is useful to test a file
register, since status flag Z is
affected.
Words:
1
1
Cycles:
Example:
MOVWF
OPTION
Before Instruction
OPTION =
0xFF
0x4F
W
=
After Instruction
Words:
1
1
OPTION =
W
0x4F
0x4F
Cycles:
Example:
=
MOVF
FSR,
0
After Instruction
W
= value in FSR register
Z
= 1
MOVLW
Move Literal to W
[ label ] MOVLW k
0 ≤ k ≤ 255
NOP
No Operation
[ label ] NOP
None
Syntax:
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
k → (W)
No operation
None
None
11
00xx
kkkk
kkkk
00
0000
0xx0
0000
The eight-bit literal ‘k’ is loaded
into the W register. The “don’t
cares” will assemble as ‘0’s.
No operation.
1
Cycles:
1
Words:
1
1
NOP
Example:
Cycles:
Example:
MOVLW
0x5A
After Instruction
W
=
0x5A
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RETURN
Return from Subroutine
RETFIE
Return from Interrupt
[ label ] RETFIE
None
Syntax:
Syntax:
[ label ] RETURN
None
Operands:
Operation:
Operands:
Operation:
TOS → PC,
1 → GIE
TOS → PC
Status Affected: None
Status Affected: None
Description:
Return from subroutine. The stack
00
0000
0000
1001
Encoding:
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
Description:
Return from interrupt. Stack is POPed
and Top-of-Stack (TOS) is loaded in
the PC. Interrupts are enabled by
setting the Global Interrupt Enable bit,
GIE (INTCON<7>). This is a
two-cycle instruction.
Words:
1
Cycles:
Example:
2
RETFIE
After Interrupt
PC
GIE =
=
TOS
1
RETLW
Return with Literal in W
[ label ] RETLW k
0 ≤ k ≤ 255
RLF
Rotate Left f through Carry
Syntax:
Syntax:
Operands:
[ label ]
RLF f,d
Operands:
Operation:
0 ≤ f ≤ 127
d ∈ [0,1]
k → (W);
TOS → PC
Operation:
See description below
C
Status Affected: None
Status Affected:
Encoding:
11
01xx
kkkk
kkkk
00
1101
dfff
ffff
Encoding:
Description:
The W register is loaded with the
eight-bit literal ‘k’. The program
counter is loaded from the top of the
stack (the return address). This is a
two-cycle instruction.
Description:
The contents of register ‘f’ are
rotated one bit to the left through
the CARRY flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
Words:
1
2
C
Register f
Cycles:
Example:
CALL TABLE;W contains table
;offset value
Words:
1
1
Cycles:
Example:
•
•
•
;W now has table value
TABLE
RLF
REG1,0
Before Instruction
ADDWF PC ;W = offset
RETLW k1 ;Begin table
REG1
=
=
1110 0110
0
RETLW k2
;
C
•
•
•
After Instruction
REG1
W
C
=
=
=
1110 0110
1100 1100
1
RETLW kn ; End of table
Before Instruction
W
=
0x07
After Instruction
W
=
value of k8
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 137
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RRF
Rotate Right f through Carry
SUBWF
Subtract W from f
Syntax:
[ label ] RRF f,d
Syntax:
[ label ] SUBWF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
See description below
Operation:
(f) - (W) → (destination)
Status Affected: C
Status Affected: C, DC, Z
Description:
The contents of register ‘f’ are rotated
Description:
Subtract (2’s complement method)
one bit to the right through the
W register from register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
CARRY flag. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’,
the result is placed back in register ‘f’.
C
Register f
SWAPF
Swap Nibbles in f
SLEEP
Syntax:
[ label ] SLEEP
Syntax:
[ label ] SWAPF f,d
Operands:
Operation:
None
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
00h → WDT,
0 → WDT prescaler,
1 → TO,
Operation:
(f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
0 → PD
Status Affected: None
Status Affected:
Description:
TO, PD
Description:
The upper and lower nibbles of
The Power-down Status bit, PD,
is cleared. Time-out Status bit,
TO, is set. Watchdog Timer and
its prescaler are cleared.
The processor is put into Sleep
mode with the oscillator stopped.
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in the W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
XORLW
Exclusive OR Literal with W
SUBLW
Subtract W from Literal
Syntax:
[label] XORLW k
0 ≤ k ≤ 255
Syntax:
[ label ] SUBLW k
0 ≤ k ≤ 255
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
(W) .XOR. k → (W)
Z
k - (W) → (W)
Status Affected: C, DC, Z
The contents of the W register
are XOR’ed with the eight-bit
literal ‘k’. The result is placed in
the W register.
Description: The W register is subtracted (2’s
complement method) from the
eight-bit literal ‘k’. The result is
placed in the W register.
DS41232B-page 138
Preliminary
© 2005 Microchip Technology Inc.
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XORWF
Exclusive OR W with f
Syntax:
[ label ] XORWF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) .XOR. (f) → (destination)
Status Affected:
Description:
Z
Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 139
PIC12F635/PIC16F636/639
NOTES:
DS41232B-page 140
Preliminary
© 2005 Microchip Technology Inc.
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14.1 MPLAB Integrated Development
Environment Software
14.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• An interface to debugging tools
- simulator
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor with color coded context
• A multiple project manager
- MPLAB C30 C Compiler
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
• Customizable data windows with direct edit of
contents
- MPLAB SIM Software Simulator
- MPLAB dsPIC30 Software Simulator
• Emulators
• High-level source code debugging
• Mouse over variable inspection
• Extensive on-line help
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
• In-Circuit Debugger
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
- MPLAB ICD 2
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools
(automatically updates all project information)
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM.netTM Demonstration Board
- PICDEM 2 Plus Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 4 Demonstration Board
- PICDEM 17 Demonstration Board
- PICDEM 18R Demonstration Board
- PICDEM LIN Demonstration Board
- PICDEM USB Demonstration Board
• Evaluation Kits
• Debug using:
- source files (assembly or C)
- mixed assembly and C
- machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increasing flexibility
and power.
14.2 MPASM Assembler
The MPASM assembler is a full-featured, universal
macro assembler for all PICmicro MCUs.
®
- KEELOQ
- PICDEM MSC
- microID®
- CAN
The MPASM assembler generates relocatable object
files for the MPLINK object linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
- PowerSmart®
- Analog
The MPASM assembler features include:
• Integration into MPLAB IDE projects
• User defined macros to streamline assembly code
• Conditional assembly for multi-purpose source
files
• Directives that allow complete control over the
assembly process
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 141
PIC12F635/PIC16F636/639
14.3 MPLAB C17 and MPLAB C18
C Compilers
14.6 MPLAB ASM30 Assembler, Linker
and Librarian
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI C compilers for Microchip’s
PIC17CXXX and PIC18CXXX family of microcontrol-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of use
not found with other compilers.
MPLAB ASM30 assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 compiler uses the
assembler to produce it’s object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
14.4 MPLINK Object Linker/
MPLIB Object Librarian
• Rich directive set
• Flexible macro language
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
• MPLAB IDE compatibility
14.7 MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code
development in a PC hosted environment by simulating
the PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any pin. The
execution can be performed in Single-Step, Execute
Until Break or Trace mode.
The MPLIB object librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool.
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
14.5 MPLAB C30 C Compiler
14.8 MPLAB SIM30 Software Simulator
The MPLAB C30 C compiler is a full-featured, ANSI
compliant, optimizing compiler that translates standard
ANSI C programs into dsPIC30F assembly language
source. The compiler also supports many command
line options and language extensions to take full
advantage of the dsPIC30F device hardware
capabilities and afford fine control of the compiler code
generator.
The MPLAB SIM30 software simulator allows code
development in a PC hosted environment by simulating
the dsPIC30F series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any of the pins.
The MPLAB SIM30 simulator fully supports symbolic
debugging using the MPLAB C30 C Compiler and
MPLAB ASM30 assembler. The simulator runs in either
a Command Line mode for automated tasks, or from
MPLAB IDE. This high-speed simulator is designed to
debug, analyze and optimize time intensive DSP
routines.
MPLAB C30 is distributed with a complete ANSI C
standard library. All library functions have been
validated and conform to the ANSI C library standard.
The library includes functions for string manipulation,
dynamic memory allocation, data conversion,
timekeeping and math functions (trigonometric,
exponential and hyperbolic). The compiler provides
symbolic information for high-level source debugging
with the MPLAB IDE.
DS41232B-page 142
Preliminary
© 2005 Microchip Technology Inc.
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14.9 MPLAB ICE 2000
High-Performance Universal
In-Circuit Emulator
14.11 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
The MPLAB ICE 2000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers. Software control of the
MPLAB ICE 2000 in-circuit emulator is advanced by
the MPLAB Integrated Development Environment,
which allows editing, building, downloading and source
debugging from a single environment.
USB interface. This tool is based on the Flash
PICmicro MCUs and can be used to develop for these
and other PICmicro microcontrollers. The MPLAB
ICD 2 utilizes the in-circuit debugging capability built
into the Flash devices. This feature, along with
Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM
)
protocol, offers cost effective in-circuit Flash debugging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by setting
breakpoints, single-stepping and watching variables,
CPU status and peripheral registers. Running at full
speed enables testing hardware and applications in
real-time. MPLAB ICD 2 also serves as a development
programmer for selected PICmicro devices.
The MPLAB ICE 2000 is a full-featured emulator system
with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of
different processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLAB ICE 2000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
14.12 PRO MATE II Universal Device
Programmer
The PRO MATE II is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maximum reliability. It features
an LCD display for instructions and error messages
and a modular detachable socket assembly to support
various package types. In Stand-Alone mode, the
PRO MATE II device programmer can read, verify and
program PICmicro devices without a PC connection. It
can also set code protection in this mode.
14.10 MPLAB ICE 4000
High-Performance Universal
In-Circuit Emulator
The MPLAB ICE 4000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for high-
end PICmicro microcontrollers. Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debugging from a single environment.
14.13 MPLAB PM3 Device Programmer
The MPLAB PM3 is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maximum reliability. It features
a large LCD display (128 x 64) for menus and error
messages and a modular detachable socket assembly
to support various package types. The ICSP™ cable
assembly is included as a standard item. In Stand-Alone
mode, the MPLAB PM3 device programmer can read,
verify and program PICmicro devices without a PC
connection. It can also set code protection in this mode.
MPLAB PM3 connects to the host PC via an RS-232 or
The MPLAB ICD 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high-speed
performance for dsPIC30F and PIC18XXXX devices.
Its advanced emulator features include complex
triggering and timing, up to 2 Mb of emulation memory
and the ability to view variables in real-time.
USB
cable.
MPLAB
PM3
has
high-speed
communications and optimized algorithms for quick
programming of large memory devices and incorporates
an SD/MMC card for file storage and secure data
applications.
The MPLAB ICE 4000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 143
PIC12F635/PIC16F636/639
14.14 PICSTART Plus Development
Programmer
14.17 PICDEM 2 Plus
Demonstration Board
The PICSTART Plus development programmer is an
easy-to-use, low-cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus development programmer supports
most PICmicro devices up to 40 pins. Larger pin count
devices, such as the PIC16C92X and PIC17C76X,
may be supported with an adapter socket. The
PICSTART Plus development programmer is CE
compliant.
The PICDEM 2 Plus demonstration board supports many
18, 28 and 40-pin microcontrollers, including PIC16F87X
and PIC18FXX2 devices. All the necessary hardware and
software is included to run the demonstration programs.
The sample microcontrollers provided with the PICDEM 2
demonstration board can be programmed with a PRO
MATE II device programmer, PICSTART Plus
development programmer, or MPLAB ICD 2 with a
Universal Programmer Adapter. The MPLAB ICD 2 and
MPLAB ICE in-circuit emulators may also be used with
the PICDEM 2 demonstration board to test firmware. A
prototype area extends the circuitry for additional
application components. Some of the features include an
RS-232 interface, a 2 x 16 LCD display, a piezo speaker,
an on-board temperature sensor, four LEDs and sample
PIC18F452 and PIC16F877 Flash microcontrollers.
14.15 PICDEM 1 PICmicro
Demonstration Board
The PICDEM 1 demonstration board demonstrates the
capabilities of the PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The sample microcontrollers provided with the
PICDEM 1 demonstration board can be programmed with
a PRO MATE II device programmer or a PICSTART Plus
development programmer. The PICDEM 1 demonstration
board can be connected to the MPLAB ICE in-circuit
emulator for testing. A prototype area extends the circuitry
for additional application components. Features include
an RS-232 interface, a potentiometer for simulated
analog input, push button switches and eight LEDs.
14.18 PICDEM 3 PIC16C92X
Demonstration Board
The PICDEM 3 demonstration board supports the
PIC16C923 and PIC16C924 in the PLCC package. All
the necessary hardware and software is included to run
the demonstration programs.
14.19 PICDEM 4 8/14/18-Pin
Demonstration Board
The PICDEM 4 can be used to demonstrate the
capabilities of the 8, 14 and 18-pin PIC16XXXX and
PIC18XXXX MCUs, including the PIC16F818/819,
PIC16F87/88, PIC16F62XA and the PIC18F1320
family of microcontrollers. PICDEM 4 is intended to
showcase the many features of these low pin count
parts, including LIN and Motor Control using ECCP.
Special provisions are made for low power operation
with the supercapacitor circuit and jumpers allow on-
board hardware to be disabled to eliminate current
draw in this mode. Included on the demo board are
provisions for Crystal, RC or Canned Oscillator modes,
a five volt regulator for use with a nine volt wall adapter
or battery, DB-9 RS-232 interface, ICD connector for
programming via ICSP and development with MPLAB
ICD 2, 2 x 16 liquid crystal display, PCB footprints for H-
Bridge motor driver, LIN transceiver and EEPROM.
Also included are: header for expansion, eight LEDs,
14.16 PICDEM.net Internet/Ethernet
Demonstration Board
The PICDEM.net demonstration board is an Internet/
Ethernet demonstration board using the PIC18F452
microcontroller and TCP/IP firmware. The board
supports any 40-pin DIP device that conforms to the
standard pinout used by the PIC16F877 or
PIC18C452. This kit features a user friendly TCP/IP
stack, web server with HTML, a 24L256 Serial
EEPROM for Xmodem download to web pages into
Serial EEPROM, ICSP/MPLAB ICD
2 interface
connector, an Ethernet interface, RS-232 interface and
a 16 x 2 LCD display. Also included is the book and
CD-ROM “TCP/IP Lean, Web Servers for Embedded
Systems,” by Jeremy Bentham
four potentiometers, three push buttons and
a
prototyping area. Included with the kit is a PIC16F627A
and a PIC18F1320. Tutorial firmware is included along
with the User’s Guide.
DS41232B-page 144
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
14.20 PICDEM 17 Demonstration Board
14.24 PICDEM USB PIC16C7X5
Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
The PICDEM USB Demonstration Board shows off the
capabilities of the PIC16C745 and PIC16C765 USB
microcontrollers. This board provides the basis for
future USB products.
PIC17C756A, PIC17C762 and PIC17C766.
A
programmed sample is included. The PRO MATE II
device programmer, or the PICSTART Plus
development programmer, can be used to reprogram
the device for user tailored application development.
The PICDEM 17 demonstration board supports
program download and execution from external on-
board Flash memory. A generous prototype area is
available for user hardware expansion.
14.25 Evaluation and
Programming Tools
In addition to the PICDEM series of circuits, Microchip
has a line of evaluation kits and demonstration software
for these products.
• KEELOQ evaluation and programming tools for
Microchip’s HCS Secure Data Products
14.21 PICDEM 18R PIC18C601/801
Demonstration Board
• CAN developers kit for automotive network
applications
The PICDEM 18R demonstration board serves to assist
development of the PIC18C601/801 family of Microchip
microcontrollers. It provides hardware implementation
of both 8-bit Multiplexed/Demultiplexed and 16-bit
Memory modes. The board includes 2 Mb external
Flash memory and 128 Kb SRAM memory, as well as
serial EEPROM, allowing access to the wide range of
memory types supported by the PIC18C601/801.
• Analog design boards and filter design software
• PowerSmart battery charging evaluation/
calibration kits
• IrDA® development kit
• microID development and rfLabTM development
software
• SEEVAL® designer kit for memory evaluation and
endurance calculations
14.22 PICDEM LIN PIC16C43X
Demonstration Board
• PICDEM MSC demo boards for Switching mode
power supply, high-power IR driver, delta sigma
ADC and flow rate sensor
The powerful LIN hardware and software kit includes a
series of boards and three PICmicro microcontrollers.
The small footprint PIC16C432 and PIC16C433 are
used as slaves in the LIN communication and feature
Check the Microchip web page and the latest Product
Selector Guide for the complete list of demonstration
and evaluation kits.
on-board LIN transceivers.
A PIC16F874 Flash
microcontroller serves as the master. All three
microcontrollers are programmed with firmware to
provide LIN bus communication.
14.23 PICkitTM 1 Flash Starter Kit
A complete “development system in a box”, the PICkit
Flash Starter Kit includes a convenient multi-section
board for programming, evaluation and development of
8/14-pin Flash PIC® microcontrollers. Powered via
USB, the board operates under a simple Windows GUI.
The PICkit 1 Starter Kit includes the User’s Guide (on
CD ROM), PICkit 1 tutorial software and code for
various applications. Also included are MPLAB® IDE
(Integrated Development Environment) software,
software and hardware “Tips 'n Tricks for 8-pin Flash
PIC® Microcontrollers” Handbook and a USB interface
cable. Supports all current 8/14-pin Flash PIC
microcontrollers, as well as many future planned
devices.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 145
PIC12F635/PIC16F636/639
NOTES:
DS41232B-page 146
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.0 ELECTRICAL SPECIFICATIONS
(†)
Absolute Maximum Ratings
Ambient temperature under bias....................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V
Voltage on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ............................................................................................................................... 800 mW
Maximum current out of VSS/VSST pin ............................................................................................................ 300 mA
Maximum current into VDD/VDDT pin............................................................................................................... 250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)............................................................................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO >VDD)....................................................................................................... 20 mA
Maximum output current sunk by any I/O pin....................................................................................................25 mA
Maximum output current sourced by any I/O pin .............................................................................................. 25 mA
Maximum current sunk by PORTA and PORTC (combined) .......................................................................... 200 mA
Maximum current sourced PORTA and PORTC (combined).......................................................................... 200 mA
Maximum LC Input Voltage (LCX, LCY, LCZ)(2) loaded, with device ............................................................ 10.0 VPP
Maximum LC Input Voltage (LCX, LCY, LCZ)(2) unloaded, without device ................................................. 700.0 VPP
Maximum Input Current (rms) into device per LC Channel(2) ........................................................................... 10 mA
Human Body ESD rating........................................................................................................................4000 (min.) V
Machine Model ESD rating ......................................................................................................................400 (min.) V
Note 1: Power dissipation for PIC12F635/PIC16F636/639 (AFE section not included) is calculated as follows:
PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL).
Power dissipation for AFE section is calculated as follows:
PDIS = VDD x IACT = 3.6V x 16 μA = 57.6 μW
2: Specification applies to the PIC16F639 only.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note:
Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a ‘low’ level to the MCLR pin, rather than
pulling this pin directly to VSS.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 147
PIC12F635/PIC16F636/639
FIGURE 15-1:
PIC12F635/PIC16F636 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
VDD
(Volts)
0
4
10
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 15-2:
PIC16F639 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C
5.5
5.0
4.5
4.0
3.6
3.0
2.5
2.0
VDD
(Volts)
0
4
10
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
DS41232B-page 148
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.1 DC Characteristics: PIC12F635/PIC16F636-I (Industrial)
PIC12F635/PIC16F636-E (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Param
Sym
Characteristic
Min Typ† Max Units
Conditions
No.
VDD
Supply Voltage
D001
D001C
D001D
2.0
3.0
4.5
—
—
—
5.5
5.5
5.5
V
V
V
FOSC < = 4 MHz
FOSC < = 10 MHz
FOSC < = 20 MHz
D002
VDR
RAM Data Retention
Voltage(1)
1.5*
—
—
V
Device in Sleep mode
D003
VPOR
VDD Start Voltage to
ensure internal Power-on
Reset signal
—
VSS
—
V
See Section 12.3 “Power-on Reset” for
details.
D004
D005
SVDD
VBOD
VDD Rise Rate to ensure 0.05*
internal Power-on Reset
signal
—
—
—
V/ms See Section 12.3 “Power-on Reset” for
details.
Brown-out Detect
—
2.1
V
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 149
PIC12F635/PIC16F636/639
15.2 DC Characteristics: PIC12F635/PIC16F636-I (Industrial)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Conditions
Param
No.
Sym
Device Characteristics
Supply Current(1,2)
Min Typ† Max Units
VDD
Note
D010
IDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
mA
μA
μA
μA
μA
μA
μA
mA
mA
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
4.5
5.0
FOSC = 32.768 kHz
LP Oscillator mode
18
35
D011
D012
D013
D014
D015
D016
D017
D018
110
190
330
220
370
600
70
FOSC = 1 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode
FOSC = 1 MHz
EC Oscillator mode
140
260
180
320
580
TBD
TBD
TBD
340
500
800
180
320
580
2.1
FOSC = 4 MHz
EC Oscillator mode
FOSC = 31 kHz
LFINTOSC mode
FOSC = 4 MHz
HFINTOSC mode
FOSC = 4 MHz
EXTRC mode
FOSC = 20 MHz
HS Oscillator mode
2.4
Legend: TBD = To Be Determined
†
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. MCU only, Analog
Front-End not included.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption. MCU only, Analog Front-End not included.
3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
DS41232B-page 150
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.2 DC Characteristics: PIC12F635/PIC16F636-I (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Conditions
Param
No.
Sym
Device Characteristics
Min Typ† Max Units
VDD
Note
D020
IPD
Power-down Base
Current(4)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.99
1.2
2.9
0.3
1.8
8.4
58
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
nA
nA
nA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
2.0 WDT, BOD,
Comparators, VREF
and T1OSC disabled
3.0
5.0
D021
ΔIWDT
2.0 WDT Current(3)
3.0
5.0
D022A ΔIBOD
D022B ΔILVD
3.0 BOD Current(3)
109
TBD
TBD
TBD
3.3
6.1
11.5
58
5.0
2.0 PLVD Current
3.0
5.0
D023
D024
D025
ΔICMP
2.0 Comparator Current(3)
3.0
5.0
ΔIVREF
2.0
3.0
5.0
CVREF Current(3)
85
138
4.0
4.6
6.0
ΔIT1OSC
2.0 T1OSC Current(3)
3.0
5.0
Legend: TBD = To Be Determined
†
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. MCU only, Analog
Front-End not included.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption. MCU only, Analog Front-End not included.
3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 151
PIC12F635/PIC16F636/639
15.3 DC Characteristics: PIC12F635/PIC16F636-E (Extended)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
-40°C ≤ TA ≤ +125°C for extended
Conditions
Param
No.
Sym
Device Characteristics
Min
Typ†
Max
Units
VDD
Note
(1,2)
D010E IDD
Supply Current
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
mA
μA
μA
μA
μA
μA
μA
mA
mA
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
4.5
5.0
FOSC = 32.768 kHz
LP Oscillator mode
18
35
D011E
110
190
330
220
370
600
70
FOSC = 1 MHz
XT Oscillator mode
D012E
D013E
D014E
D015E
D016E
D017E
D018E
FOSC = 4 MHz
XT Oscillator mode
FOSC = 1 MHz
EC Oscillator mode
140
260
180
320
580
TBD
TBD
TBD
340
500
800
180
320
580
2.1
FOSC = 4 MHz
EC Oscillator mode
FOSC = 31 kHz
LFINTOSC
FOSC = 4 MHz
IHFINTOSC
FOSC = 4 MHz
EXTRC mode
FOSC = 20 MHz
HS Oscillator mode
2.4
Legend: TBD = To Be Determined
†
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption.
3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this periph-
eral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this
limit. Max values should be used when calculating total current consumption.
4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
DS41232B-page 152
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.3 DC Characteristics: PIC12F635/PIC16F636-E (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
-40°C ≤ TA ≤ +125°C for extended
Conditions
Param
No.
Sym
Device Characteristics
Min
Typ†
Max
Units
VDD
Note
D020
IPD
Power-down Base
Current
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.0009 TBD
0.0012 TBD
0.0029 TBD
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
2.0
3.0
5.0
2.0
3.0
5.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
WDT, BOD, Comparators,
VREF and T1OSC disabled
(4)
(3)
D021
ΔIWDT
0.3
1.8
8.4
58
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
WDT Current
(3)
D022A ΔIBOD
D022B ΔILVD
BOD Current
109
TBD
TBD
TBD
3.3
PLVD Current
(3)
D023
D024
D025
ΔICMP
Comparator Current
6.1
11.5
58
(3)
ΔIVREF
CVREF Current
85
138
4.0
(3)
ΔIT1OSC
T1OSC Current
4.6
6.0
Legend: TBD = To Be Determined
†
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption.
3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this periph-
eral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this
limit. Max values should be used when calculating total current consumption.
4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 153
PIC12F635/PIC16F636/639
15.4 DC Characteristics: PIC12F635/PIC16F636-I (Industrial)
PIC12F635/PIC16F636-E (Extended)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
VIL
Input Low Voltage
I/O ports:
D030
D030A
D031
D032
D033
D033A
with TTL buffer
VSS
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
—
0.8
V
V
V
V
V
V
4.5V ≤ VDD ≤ 5.5V
Otherwise
0.15 VDD
0.2 VDD
0.2 VDD
0.3
with Schmitt Trigger buffer
MCLR, OSC1 (RC mode)
Entire range
(1)
OSC1 (XT and LP modes)
(1)
OSC1 (HS mode)
0.3 VDD
VIH
Input High Voltage
I/O ports:
D040
D040A
with TTL buffer
2.0
(0.25 VDD +
0.8)
—
—
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
Otherwise
D041
with Schmitt Trigger buffer
MCLR
0.8 VDD
0.8 VDD
1.6
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
Entire range
D042
D043
OSC1 (XT and LP modes)
OSC1 (HS mode)
(Note 1)
(Note 1)
D043A
D043B
0.7 VDD
0.9 VDD
OSC1 (RC mode)
(2)
IIL
Input Leakage Current
D060
I/O ports
—
0.1
1
μA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
D060A
D060B
D061
Analog inputs
VREF
—
—
—
—
0.1
0.1
0.1
0.1
1
1
5
5
μA VSS ≤ VPIN ≤ VDD
μA VSS ≤ VPIN ≤ VDD
μA VSS ≤ VPIN ≤ VDD
(3)
MCLR
D063
OSC1
μA VSS ≤ VPIN ≤ VDD, XT, HS and
LP oscillator configuration
D070
IPUR
VOL
PORTA Weak Pull-up
Current
50*
250
400*
μA VDD = 5.0V, VPIN = VSS
Output Low Voltage
I/O ports
D080
D083
—
—
—
—
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 4.5V (Ind.)
OSC2/CLKOUT (RC mode)
IOL = 1.6 mA, VDD = 4.5V (Ind.)
IOL = 1.2 mA, VDD = 4.5V (Ext.)
*
These parameters are characterized but not tested.
†
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an
external clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
4: See Section 9.4.1 “Using the Data EEPROM” for additional information.
DS41232B-page 154
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.4 DC Characteristics: PIC12F635/PIC16F636-I (Industrial)
PIC12F635/PIC16F636-E (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
VOH
IULP
Output High Voltage
I/O ports
D090
D092
VDD – 0.7
VDD – 0.7
—
—
—
—
V
V
IOH = -3.0 mA, VDD = 4.5V (Ind.)
OSC2/CLKOUT (RC mode)
IOH = -1.3 mA, VDD = 4.5V (Ind.)
IOH = -1.0 mA, VDD = 4.5V (Ext.)
D100
Ultra Low-power Wake-up
Current
—
200
—
nA
Capacitive Loading Specs
on Output Pins
D100 COSC2 OSC2 pin
—
—
—
—
15*
50*
pF In XT, HS and LP modes when
external clock is used to drive
OSC1
D101
CIO
All I/O pins
pF
Data EEPROM Memory
Byte Endurance
Byte Endurance
VDD for Read/Write
D120 ED
D120A ED
100K
10K
1M
100K
—
—
—
E/W -40°C ≤ TA ≤ +85°C
E/W +85°C ≤ TA ≤ +125°C
D121
VDRW
VMIN
5.5
V
Using EECON1 to read/write
VMIN = Minimum operating
voltage
D122
D123
TDEW
Erase/Write cycle time
Characteristic Retention
—
5
6
ms
TRETD
40
—
—
Year Provided no other
specifications are violated
D124
TREF
Number of Total Erase/Write
Cycles before Refresh
1M
10M
—
E/W -40°C ≤ TA ≤ +85°C
(1)
Program Flash Memory
Cell Endurance
D130 EP
D130A ED
10K
1K
100K
10K
—
—
—
E/W -40°C ≤ TA ≤ +85°C
E/W +85°C ≤ TA ≤ +125°C
Cell Endurance
D131
VPR
VDD for Read
VMIN
5.5
V
VMIN = Minimum operating
voltage
D132
D133
D134
VPEW
TPEW
TRETD
VDD for Erase/Write
4.5
—
—
2
5.5
2.5
—
V
Erase/Write cycle time
Characteristic Retention
ms
40
—
Year Provided no other
specifications are violated
*
These parameters are characterized but not tested.
†
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an
external clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
4: See Section 9.4.1 “Using the Data EEPROM” for additional information.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 155
PIC12F635/PIC16F636/639
15.5 DC Characteristics: PIC16F639-I (Industrial), PIC16F639-E (Extended)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Sym
Characteristic
Min Typ† Max Units
Conditions
D001
VDD
Supply Voltage
2.0
2.0
—
—
3.6
3.6
V
V
FOSC ≤ 10 MHz
D001A VDDT
Supply Voltage (AFE)
Analog Front-End VDD voltage. Treated as
VDD in this document.
D002
D003
VDR
RAM Data Retention
Voltage(1)
1.5*
—
—
—
—
V
V
Device in Sleep mode
VPOR
VDD Start Voltage to
ensure internal Power-on
Reset signal
VSS
See Section 12.3 “Power-on Reset” for
details.
D003A VPORT VDD Start Voltage (AFE)
to ensure internal Power-
—
—
—
1.8
—
V
Analog Front-End POR voltage.
on Reset signal
D004
SVDD
VDD Rise Rate to ensure 0.05*
internal Power-on Reset
signal
V/ms See Section 12.3 “Power-on Reset” for
details.
D005
D006
VBOD
RM
Brown-out Detect
—
—
2.1
—
—
V
Turn-on Resistance or
100 Ohm VDD = 3.0V
Modulation Transistor
D007
D008
RPU
IAIL
Digital Input Pull-Up
Resistor
CS, SCLK
50
200 300 kOhm VDD = 3.6V
Analog Input Leakage
Current
LCX, LCY, LCZ
LCCOM
—
—
—
—
±1
±1
μA
μA
VDD = 3.6V, VSS ≤ VIN ≤ VDD, tested at
Sleep mode
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
DS41232B-page 156
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.6 DC Characteristics: PIC16F639-I (Industrial)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
Supply Voltage
-40°C ≤ TA ≤ +85°C for industrial
2.0V ≤ VDD ≤ 3.6V
Conditions
Param
Sym
No.
Device Characteristics
Supply Current(1,2,3)
Min
Typ†
Max
Units
VDD
Note
D010
D011
D012
D013
D014
D015
D016
D017
D020
IDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
nA
nA
2.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
FOSC = 32.768 kHz
LP Oscillator mode
18
110
190
220
370
70
FOSC = 1 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode
FOSC = 1 MHz
EC Oscillator mode
140
180
320
TBD
TBD
340
500
180
320
0.99
1.2
FOSC = 4 MHz
EC Oscillator mode
FOSC = 31 kHz
LFINTOSC mode
FOSC = 4 MHz
HFINTOSC mode
FOSC = 4 MHz
EXTRC mode
IPD
Power-down Base Current(4)
WDT, BOD, Comparators,
VREF and T1OSC disabled
(excludes AFE)
D021
ΔIWDT
—
—
—
—
—
—
—
—
—
—
—
0.3
1.8
58
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
2.0
3.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
WDT Current(3)
D022A
D022B
ΔIBOD
ΔILVD
BOD Current(3)
PLVD Current
TBD
TBD
3.3
6.1
58
D023
D024
D025
D026
ΔICMP
ΔIVREF
ΔIT1OSC
IACT
Comparator Current(3)
CVREF Current(3)
85
4.0
4.6
T1OSC Current(3)
Active Current of AFE only
(receiving signal)
CS = VDD; Input = Continuous
Wave (CW);
1 LC Input Channel Signal
3 LC Input Channel Signals
—
—
10
—
—
16
μA
μA
3.6
3.6
Amplitude = 300 mVPP.
All channels enabled.
D027
ISTDBY
Standby Current of AFE only
(not receiving signal)
1 LC Input Channel Enabled
CS = VDD; ALERT = VDD
—
—
—
3
4
5
5
6
7
μΑ
μA
μA
3.6
3.6
3.6
2 LC Input Channels Enabled
3 LC Input Channels Enabled
D028
ISLEEP
Sleep Current of AFE only
—
0.2
1
μA
3.6
CS = VDD; ALERT = VDD
Legend:
TBD = To Be Determined
†
Data in ‘Typ’ column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-
stated, pulled to VDD; MCLR = VDD; WDT disabled. MCU only, Analog Front-End not included.
Note 1:
2:
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate,
oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. MCU only, Analog
Front-End not included.
3:
4:
The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The
peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when
calculating total current consumption.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep
mode, with all I/O pins in high-impedance state and tied to VDD.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 157
PIC12F635/PIC16F636/639
15.7 DC Characteristics: PIC16F639-E (Extended)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
Supply Voltage
-40°C ≤ TA ≤ +125°C for extended
2.0V ≤ VDD ≤ 3.6V
Conditions
Param
Sym
No.
Device Characteristics
Supply Current(1,2)
Min
Typ†
Max
Units
VDD
Note
D010E
D011E
D012E
D013E
D014E
D015E
D016E
D017E
D020
IDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
nA
nA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
2.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
18
110
190
220
370
70
140
180
320
TBD
TBD
340
500
180
320
0.99
1.2
IPD
Power-down Base Current(4)
WDT, BOD, Comparators, VREF and
T1OSC disabled (excludes AFE)
D021
ΔIWDT
0.3
WDT Current(3)
1.8
D022A
D022B
ΔIBOD
ΔILVD
58
BOD Current(3)
PLVD Current
TBD
TBD
3.3
D023
D024
D025
D026
ΔICMP
ΔIVREF
ΔIT1OSC
IACT
Comparator Current(3)
CVREF Current(3)
6.1
58
85
4.0
T1OSC Current(3)
4.6
Active Current of AFE only
(receiving signal)
CS = VDD; Input = Continuous Wave
(CW); Amplitude = 300 mVPP. All
channels enabled.
1 LC Input Channel Signal
3 LC Input Channel Signals
—
—
10
—
—
16
μA
μA
3.6
3.6
D027
ISTDBY
Standby Current of AFE only
(not receiving signal)
1 LC Input Channel Enabled
CS = VDD; ALERT = VDD
—
—
—
3
4
5
5
6
7
μΑ
μA
μA
3.6
3.6
3.6
2 LC Input Channels Enabled
3 LC Input Channels Enabled
D028
ISLEEP
Sleep Current of AFE only
—
0.2
1
μA
3.6
CS = VDD; ALERT = VDD
Legend:
TBD = To Be Determined
†
Data in ‘Typ’ column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-
stated, pulled to VDD; MCLR = VDD; WDT disabled.
Note 1:
2:
3:
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate,
oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption.
The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The
peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when
calculating total current consumption.
4:
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep
mode, with all I/O pins in high-impedance state and tied to VDD.
DS41232B-page 158
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.8 DC Characteristics: PIC16F639-I (Industrial), PIC16F639-E (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
2.0V ≤ VDD ≤ 3.6V
DC CHARACTERISTICS
Supply Voltage
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
VIL
Input Low Voltage
I/O ports:
with TTL buffer
D030
D030A
D031
D032
D033
D033A
D034
VSS
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
—
0.15 VDD
0.2 VDD
0.2 VDD
0.3
V
V
V
V
V
V
with Schmitt Trigger buffer
MCLR, OSC1 (RC mode)
OSC1 (XT and LP modes)(1)
OSC1 (HS mode)(1)
0.3 VDD
0.3 VDD
Digital Input Low Voltage
Input High Voltage
Analog Front-End section
VIH
I/O ports:
D040
with TTL buffer
D040A
D041
(0.25 VDD + 0.8)
0.8 VDD
0.8 VDD
1.6
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
with Schmitt Trigger buffer
MCLR
D042
D043
OSC1 (XT and LP modes)
OSC1 (HS mode)
(Note 1)
(Note 1)
D043A
D043B
0.7 VDD
0.9 VDD
OSC1 (RC mode)
Digital Input High Voltage
Analog Front-End section
D044
D060
SCLK, CS, SDIO for Analog
Front-End (AFE)
Input Leakage Current(2)
0.7 VDD
—
VDD
V
IIL
I/O ports
—
0.1
1
μA
VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
D060A
D060B
D061
Analog inputs
VREF
MCLR(3)
—
—
—
—
0.1
0.1
0.1
0.1
1
1
5
5
μA
μA
μA
μA
VSS ≤ VPIN ≤ VDD
VSS ≤ VPIN ≤ VDD
VSS ≤ VPIN ≤ VDD
D063
OSC1
VSS ≤ VPIN ≤ VDD, XT, HS and LP
oscillator configuration
Digital Input Leakage Current(2)
VDD = 3.6V, Analog Front-End section
VSS ≤ VPIN ≤ VDD
D064
SDI for Analog Front-End (AFE)
—
—
—
—
1
1
μA
μA
D064A
SCLK, CS for Analog Front-End
(AFE)
VPIN ≤ VDD
D070
IPUR
VOL
PORTA Weak Pull-up Current
Output Low Voltage
I/O ports
50*
250
400*
μA
VDD = 3.6V, VPIN = VSS
D080
D083
—
—
—
—
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 3.6V (Ind.)
OSC2/CLKOUT (RC mode)
IOL = 1.6 mA, VDD = 3.6V (Ind.)
IOL = 1.2 mA, VDD = 3.6V (Ext.)
Digital Output Low Voltage
Analog Front-End section
IOL = 1.0 mA, VDD = 2.0V
D084
ALERT, LFDATA/SDIO for
Analog Front-End (AFE)
—
—
VSS + 0.4
V
*
These parameters are characterized but not tested.
†
Data in ‘Typ’ column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC
mode.
Note 1:
2:
3:
Negative current is defined as current sourced by the pin.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating
conditions. Higher leakage current may be measured at different input voltages.
See Section 9.4.1 “Using the Data EEPROM” for additional information
4:
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 159
PIC12F635/PIC16F636/639
15.8 DC Characteristics: PIC16F639-I (Industrial), PIC16F639-E (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
2.0V ≤ VDD ≤ 3.6V
DC CHARACTERISTICS
Supply Voltage
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
VOH
Output High Voltage
I/O ports
D090
D092
VDD – 0.7
VDD – 0.7
—
—
—
—
V
V
IOH = -3.0 mA, VDD = 3.6V (Ind.)
OSC2/CLKOUT (RC mode)
IOH = -1.3 mA, VDD = 3.6V (Ind.)
IOH = -1.0 mA, VDD = 3.6V (Ext.)
Digital Output High Voltage
Analog Front-End (AFE) section
D093
LFDATA/SDIO for Analog Front-End
(AFE)
VDD – 0.5
—
—
—
V
IOH = -400 μA, VDD = 2.0V
Capacitive Loading Specs on
Output Pins
D100
COSC2 OSC2 pin
—
15*
pF
In XT, HS and LP modes when
external clock is used to drive OSC1
D101
D102
CIO
All I/O pins
—
—
—
50*
—
pF
nA
IULP
Ultra Low-power Wake-up Current
Data EEPROM Memory
Byte Endurance
200
D120
ED
100K
10K
1M
100K
—
—
—
E/W -40°C ≤ TA ≤ +85°C
E/W +85°C ≤ TA ≤ +125°C
D120A ED
Byte Endurance
D121
VDRW
VDD for Read/Write
VMIN
5.5
V
Using EECON1 to read/write
VMIN = Minimum operating voltage
D122
D123
TDEW
Erase/Write cycle time
Characteristic Retention
—
5
6
ms
TRETD
40
—
—
Year Provided no other specifications are
violated
D124
TREF
Number of Total Erase/Write Cycles
before Refresh(1)
1M
10M
—
E/W -40°C ≤ TA ≤ +85°C
Program Flash Memory
Cell Endurance
D130
EP
10K
1K
100K
10K
—
—
—
E/W -40°C ≤ TA ≤ +85°C
E/W +85°C ≤ TA ≤ +125°C
D130A ED
Cell Endurance
D131
D132
D133
D134
VPR
VDD for Read
VMIN
4.5
—
5.5
5.5
2.5
—
V
V
VMIN = Minimum operating voltage
VPEW
TPEW
TRETD
VDD for Erase/Write
Erase/Write cycle time
Characteristic Retention
—
2
ms
40
—
Year Provided no other specifications are
violated
*
These parameters are characterized but not tested.
†
Data in ‘Typ’ column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC
mode.
Note 1:
2:
3:
Negative current is defined as current sourced by the pin.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating
conditions. Higher leakage current may be measured at different input voltages.
See Section 9.4.1 “Using the Data EEPROM” for additional information
4:
DS41232B-page 160
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.9 Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
T
Time
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCLK
SS
SDI
do
dt
SDO
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (High-impedance)
Low
Valid
L
High-impedance
FIGURE 15-3:
LOAD CONDITIONS
Load Condition 1
Load Condition 2
VDD/2
RL
CL
CL
pin
pin
VSS
VSS
Legend:
RL = 464Ω
CL = 50 pF for all pins
15 pF for OSC2 output
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 161
PIC12F635/PIC16F636/639
15.10 AC Characteristics: PIC12F635/PIC16F636/639 (Industrial, Extended)
FIGURE 15-4:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
4
Q1
OSC1
1
3
3
4
2
CLKOUT
TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
Sym
Characteristic
Min Typ†
Max
Units
Conditions
No.
FOSC External CLKIN Frequency(1) DC
—
—
—
—
—
—
—
—
—
—
—
—
—
37
4
kHz LP Oscillator mode
MHz XT Oscillator mode
MHz HS Oscillator mode
MHz EC Oscillator mode
kHz LP Oscillator mode
MHz HFINTOSC Oscillator mode
MHz RC Oscillator mode
MHz XT Oscillator mode
MHz HS Oscillator mode
μs LP Oscillator mode
ns HS Oscillator mode
ns EC Oscillator mode
ns XT Oscillator mode
μs LP Oscillator mode
ns INTOSC Oscillator mode
ns RC Oscillator mode
ns XT Oscillator mode
ns HS Oscillator mode
ns TCY = 4/FOSC
DC
DC
DC
20
20
Oscillator Frequency(1)
5
37
—
—
DC
0.1
1
4
4
20
1
TOSC
External CLKIN Period(1)
Oscillator Period(1)
27
—
50
—
50
—
250
27
—
200
—
—
125
—
250
250
50
—
—
10,000
1,000
DC
—
—
2
3
TCY
Instruction Cycle Time(1)
200
TCY
—
TosL, External CLKIN (OSC1) High 2*
μs LP oscillator, TOSC L/H duty cycle
ns HS oscillator, TOSC L/H duty cycle
ns XT oscillator, TOSC L/H duty cycle
ns LP oscillator
TosH External CLKIN Low
20*
—
—
100*
—
—
4
TosR, External CLKIN Rise
TosF External CLKIN Fall
—
—
—
—
50*
25*
15*
—
ns XT oscillator
—
ns HS oscillator
*
These parameters are characterized but not tested.
†
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at ‘min’
values with an external clock applied to OSC1 pin. When an external clock input is used, the ‘max’ cycle
time limit is ‘DC’ (no clock) for all devices.
DS41232B-page 162
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
TABLE 15-2: PRECISION INTERNAL OSCILLATOR PARAMETERS
Param
No.
Freq
Tolerance
Sym
Characteristic
Min
Typ†
Max Units
Conditions
F10
FOSC Internal Calibrated
INTOSC Frequency(1)
HFINTOSC
1%
2%
—
—
8.00
8.00
TBD
TBD
MHz VDD and Temperature (TBD)
MHz 2.5V ≤ VDD ≤ 5.5V
0°C ≤ TA ≤ +85°C
5%
—
8.00
TBD
MHz 2.0V ≤ VDD ≤ 5.5V
-40°C ≤ TA ≤ +85°C (Ind.)
-40°C ≤ TA ≤ +125°C (Ext.)
F14
TIOSCST Oscillator Wake-up from
Sleep Start-up Time*
—
—
—
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
μs VDD = 2.0V, -40°C to +85°C
μs VDD = 3.0V, -40°C to +85°C
μs VDD = 5.0V, -40°C to +85°C
Legend: TBD = To Be Determined
*
These parameters are characterized but not tested.
†
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended.
FIGURE 15-5:
CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
22
23
CLKOUT
13
12
19
18
14
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 163
PIC12F635/PIC16F636/639
TABLE 15-3: CLKOUT AND I/O TIMING REQUIREMENTS
Param
Sym
Characteristic
Min
Typ†
Max
Units Conditions
No.
10
TOSH2CKL
TOSH2CKH
TCKR
OSC1↑ to CLKOUT↓
—
75
75
35
35
—
—
—
50
—
—
200
200
100
100
20
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns
11
12
13
14
15
16
17
OSC1↑ to CLKOUT↑
CLKOUT Rise Time
—
—
TCKF
CLKOUT Fall Time
—
TCKL2IOV
TIOV2CKH
TCKH2IOI
TOSH2IOV
CLKOUT↓ to Port Out Valid
Port In Valid before CLKOUT↑
Port In Hold after CLKOUT↑
OSC1↑ (Q1 cycle) to Port Out Valid
—
TOSC + 200 ns
—
0
—
—
150*
300
—
—
ns
18
19
TOSH2IOI
OSC1↑ (Q2 cycle) to Port Input
Invalid (I/O in hold time)
100
ns
TIOV2OSH
Port Input Valid to OSC1↑
(I/O in setup time)
0
—
—
ns
20
21
22
23
TIOR
TIOF
TINP
TRBP
Port Output Rise Time
Port Output Fall Time
INT pin High or Low Time
—
—
10
10
—
—
40
40
—
—
ns
ns
ns
ns
25
PORTA Change INT High or Low
Time
TCY
*
These parameters are characterized but not tested.
†
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
FIGURE 15-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
DS41232B-page 164
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
FIGURE 15-7:
BROWN-OUT DETECT TIMING AND CHARACTERISTICS
VDD
VBOD
(Device not in Brown-out Detect)
(Device in Brown-out Detect)
35
Reset (due to BOD)
(1)
64 ms Time-out
Note 1: 64 ms delay only if PWRTE bit in Configuration Word register is programmed to ‘0’.
TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT DETECT REQUIREMENTS
Param
No.
Sym
TMCL
Characteristic
Min
Typ†
Max Units
Conditions
30
MCLR Pulse Width (low)
2
11
—
18
—
μs VDD = 5.0V, -40°C to +85°C
24
ms Extended temperature
31
TWDT
Watchdog Timer Time-out Period
(no prescaler)
10
10
17
17
25
30
ms VDD = 5.0V, -40°C to +85°C
ms Extended temperature
32
TOST
Oscillation Start-up Timer Period
—
1024 TOSC
—
—
TOSC = OSC1 period
33*
TPWRT Power-up Timer Period
28*
TBD
64
TBD
132*
TBD
ms VDD = 5.0V, -40°C to +85°C
ms Extended Temperature
34
TIOZ
I/O High-impedance from MCLR
Low or Watchdog Timer Reset
—
—
2.0
μs
35
36
VBOD
TBOD
Brown-out Detect Voltage
2.025
100*
—
—
2.175
—
V
Brown-out Detect Pulse Width
μs VDD ≤ VBOD (D005)
Legend: TBD = To Be Determined
*
These parameters are characterized but not tested.
†
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 165
PIC12F635/PIC16F636/639
FIGURE 15-8:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
45
46
48
47
TMR0 or
TMR1
TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
TT0H
Characteristic
T0CKI High Pulse Width
Min
Typ† Max Units
Conditions
40*
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
10
0.5 TCY + 20
10
41*
42*
TT0L
TT0P
T0CKI Low Pulse Width
T0CKI Period
Greater of:
20 or TCY + 40
N
ns N = prescale
value (2, 4,...,
256)
45*
46*
47*
TT1H
TT1L
TT1P
T1CKI High
Time
Synchronous, No Prescaler
Synchronous, with Prescaler
Asynchronous
0.5 TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
15
30
T1CKI Low Time Synchronous, No Prescaler
Synchronous, with Prescaler
Asynchronous
0.5 TCY + 20
15
30
T1CKI Input
Period
Synchronous
Greater of:
30 or TCY + 40
N
ns N = prescale
value (1, 2, 4, 8)
Asynchronous
60
—
—
—
ns
48
49
FT1
Timer1 Oscillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN)
DC
200*
kHz
TCKEZTMR1 Delay from External Clock Edge to Timer
increment
2 TOSC*
—
7 TOSC*
—
*
These parameters are characterized but not tested.
†
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
DS41232B-page 166
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
TABLE 15-6: COMPARATOR SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +125°C
Sym Characteristics
Input Offset Voltage
Min
Typ
Max
Units
Comments
VOS
—
0
5.0
—
10
VDD – 1.5
—
mV
V
VCM
CMRR
TRT
Input Common Mode Voltage
Common Mode Rejection Ratio
Response Time(1)
+55*
—
—
db
ns
μs
150
—
400*
TMC2COV Comparator Mode Change to
Output Valid
—
10*
*
These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2 while the other input transitions from
VSS to VDD – 1.5V.
TABLE 15-7: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
Sym. Characteristics
Resolution
-40°C ≤ TA ≤ +125°C
Min
Typ
Max
Units
Comments
—
—
VDD/24*
VDD/32
—
—
LSb Low range (VRR = 1)
LSb High range (VRR = 0)
Absolute Accuracy
—
—
—
—
1/4*
1/2*
LSb Low range (VRR = 1)
LSb High range (VRR = 0)
Unit Resistor Value (R)
Settling Time(1)
—
—
2K*
—
—
Ω
10*
μs
*
These parameters are characterized but not tested.
Note 1: Settling time measured while VRR = 1and VR<3:0> transitions from ‘0000’ to ‘1111‘.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 167
PIC12F635/PIC16F636/639
15.11 AC Characteristics: Analog Front-End for PIC16F639 (industrial, extended)
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Supply Voltage
Operating temperature
2.0V ≤ VDD ≤ 3.6V
-40°C ≤ TAMB ≤ +85°C for industrial
-40°C ≤ TAMB ≤ +125°C for extended
Sinusoidal 300 mVPP
LC Signal Input
Carrier Frequency
LCCOM connected to VSS
125 kHz
Param
No.
Sym.
Characteristic
LC Input Sensitivity
Min
Typ†
Max
Units
Conditions
VSENSE
VDD = 3.0V
1
3.0
6
mVPP Output enable filter disabled
AGCSIG = 0; MODMIN = 00
(50% modulation depth setting)
Input = Continuous Wave (CW)
Output = Logic level transition from low-to-
high at sensitivity level for CW input.
VDE_Q
RFLM
SADJ
Coil de-Q’ing Voltage -
RF Limiter (RFLM) must be active
3
—
—
5
V
VDD = 3.0V, Force IIN = 5 μA
RF Limiter Turn-on Resistance
(LCX, LCY, LCZ)
—
700
Ohm VDD = 2.0V, VIN = 8 VDC
Sensitivity Reduction
VDD = 3.0V
—
—
0
-30
—
—
dB
dB
No sensitivity reduction selected
Max reduction selected
Monotonic increment in attenuation value from
setting = 0000to 1111by design
VIN_MOD Minimum Modulation Depth
75% ± 12%
VDD = 3.0V
63
38
13
0
75
50
25
12
87
62
37
24
%
%
%
%
50% ± 12%
25% ± 12%
12% ± 12%
CTUNX
LCX Tuning Capacitor
VDD = 3.0V,
—
0
—
pF
pF
Config. Reg. 1, bits <6:1> Setting = 000000
44.1
63
81.9
63 pF +/- 30%
Config. Reg. 1, bits <6:1> Setting = 111111
63 steps, 1 pF/step
Monotonic increment in capacitor value from
setting = 000000to 111111by design
CTUNY
LCY Tuning Capacitor
VDD = 3.0V,
—
0
—
pF
pF
Config. Reg. 2, bits <6:1> Setting = 000000
44.1
63
81.9
63 pF +/- 30%
Config. Reg. 2, bits <6:1> Setting = 111111
63 steps, 1 pF/step
Monotonic increment in capacitor value from
setting = 000000to 111111by design
FCARRIER Carrier frequency
—
—
125
—
—
4
kHz
kHz
Characterized at bench.
FMOD
Input modulation frequency
Input data rate, characterized at bench.
*
Parameter is characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: Required output enable filter high time must account for input path analog delays = TOEH - TDR + TDF
2: Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF)
DS41232B-page 168
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.11 AC Characteristics: Analog Front-End for PIC16F639 (industrial, extended) (Continued)
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Supply Voltage
Operating temperature
2.0V ≤ VDD ≤ 3.6V
-40°C ≤ TAMB ≤ +85°C for industrial
-40°C ≤ TAMB ≤ +125°C for extended
Sinusoidal 300 mVPP
LC Signal Input
Carrier Frequency
LCCOM connected to VSS
125 kHz
Param
No.
Sym.
Characteristic
Min
Typ†
Max
Units
Conditions
CTUNZ
LCZ Tuning Capacitor
VDD = 3.0V,
—
0
—
pF
pF
Config. Reg. 3, bits<6:1> Setting = 000000
44.1
63
81.9
63 pF +/- 30%
Config. Reg. 3, bits<6:1> Setting = 111111
63 steps, 1 pF/step
Monotonic increment in capacitor value from
setting = 000000to 111111by design
C_Q
TDR
Q of Trimming Capacitors
50*
—
—
—
pF
Characterized at bench test
Demodulator Charge Time
(delay time of demodulated output
to rise)
—
50
μs
VDD = 3.0V
MOD depth setting = 50%
Input conditions:
Amplitude = 300 mVPP
Modulation depth = 80%
TDF
Demodulator Discharge Time
(delay time of demodulated output
to fall)
—
50
—
μs
VDD = 3.0V
MOD depth setting = 50%
Input conditions:
Amplitude = 300 mVPP
Modulation depth = 80%
TLFDATAR Rise time of LFDATA
TLFDATAF Fall time of LFDATA
—
—
0.5
0.5
—
—
μs
μs
VDD = 3.0V
Time is measured from 10% to 90% of
amplitude
VDD = 3.0V
Time is measured from 10% to 90% of
amplitude
TAGC
TPAGC
TSTAB
AGC stabilization time
—
—
4
3.5*
62.5
—
—
—
—
ms
μs
Time required for AGC stabilization
Equivalent to two Internal clock cycle (FOSC)
AGC stabilization time
High time after AGC settling time
AGC stabilization time plus high
time (after AGC settling time)
(TAGC + TPAGC)
ms
TGAP
TRDY
Gap time after AGC settling time
200
—
—
—
—
μs
Typically 1 TE
Time from exiting Sleep or POR to
being ready to receive signal
50*
ms
TPRES
FOSC
Minimum time AGC level must be
held after receiving AGC Preserve
command
5*
—
—
ms
AGC level must not change more than 10%
during TPRES.
Internal RC oscillator frequency
(±10%)
28.8
32
35.2
kHz
Internal clock trimmed at 32 kHz during test
TINACT
TALARM
RLC
Inactivity timer time-out
Alarm timer time-out
14.4
28.8
16
32
17.6
35.2
ms
ms
512 cycles of RC oscillator @ FOSC
1024 cycles of RC oscillator @ FOSC
LC Pin Input Impedance
LCX, LCY, LCZ
—
1*
—
MOhm Device in Standby mode
*
†
Parameter is characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: Required output enable filter high time must account for input path analog delays = TOEH - TDR + TDF
2: Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF)
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 169
PIC12F635/PIC16F636/639
15.11 AC Characteristics: Analog Front-End for PIC16F639 (industrial, extended) (Continued)
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Supply Voltage
Operating temperature
2.0V ≤ VDD ≤ 3.6V
-40°C ≤ TAMB ≤ +85°C for industrial
-40°C ≤ TAMB ≤ +125°C for extended
Sinusoidal 300 mVPP
LC Signal Input
Carrier Frequency
LCCOM connected to VSS
125 kHz
Param
No.
Sym.
Characteristic
Min
Typ†
Max
Units
Conditions
TE
Time element of pulse
200
—
—
μs
TOEH
Minimum output enable filter high
time
OEH (Bits Config0<7:6>)
01= 1 ms
RC oscillator = FOSC
Viewed from the pin input:
(Note 1)
32 (~1ms)
64 (~2ms)
128 (~ms)
—
—
—
—
—
—
—
—
—
clock
count
10= 2 ms
11= 4 ms
00= Filter Disabled
TOEL
TOET
Minimum output enable filter low
time
OEL (Bits Config0<5:4>)
00= 1 ms
RC oscillator = FOSC
Viewed from the pin input:
clock (Note 2)
32 (~1ms)
32 (~1ms)
64 (~2ms)
128 (~4ms)
—
—
—
—
—
—
—
—
count
01= 1 ms
10= 2 ms
11= 4 ms
Maximum output enable filter
period
RC oscillator = FOSC
OEH OEL
TOEH TOEL
1 ms 1 ms
1 ms 1 ms
1 ms 2 ms
1 ms 4 ms
01
01
01
01
00
01
10
11
=
=
=
=
—
—
—
—
—
—
—
—
96 (~3ms)
96 (~3ms)
128 (~4ms)
192 (~6ms)
clock
count
10
10
10
10
00
01
10
11
=
=
=
=
2 ms 1 ms
2 ms 1 ms
2 ms 2 ms
2 ms 4 ms
—
—
—
—
—
—
—
—
128 (~4ms)
128 (~4ms)
160 (~5ms)
250 (~8ms)
11
11
11
11
00
01
10
11
=
=
=
=
4 ms 1 ms
4 ms 1 ms
4 ms 2 ms
4 ms 4 ms
—
—
—
—
—
—
—
—
192 (~6ms)
192 (~6ms)
256 (~8ms)
320 (~10ms)
00
XX = Filter Disabled
—
—
—
—
—
LFDATA output appears as long as input
signal level is greater than VSENSE.
IRSSI
RSSI current output
100
μA
VDD = 3.0V,
VIN = 0 to 4 VPP
Linearly increases with input signal amplitude.
Tested at VIN = 40 mVPP, 400 mVPP, and
4 VPP
—
—
—
1
10
100
—
—
—
μA
μA
μA
VIN = 40 mVPP
VIN = 400 mVPP
VIN = 4 VPP
IRSSILR RSSI current linearity
—
TBD
—
—
*
Parameter is characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: Required output enable filter high time must account for input path analog delays = TOEH - TDR + TDF
2: Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF)
DS41232B-page 170
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
15.12 SPI Timing: Analog Front-End (AFE) for PIC16F639
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Supply Voltage
2.0V ≤ VDD ≤ 3.6V
Operating temperature
-40°C ≤ TAMB ≤ +85°C for industrial
-40°C ≤ TAMB ≤ +125°C for extended
Sinusoidal 300 mVPP
LC Signal Input
Carrier Frequency
LCCOM connected to VSS
125 kHz
Param
Sym
Characteristic
Min
—
Typ†
—
Max
3
Units
MHz
ns
Conditions
FSCLK SCLK Frequency
Tcssc
100
—
—
CS fall to first SCLK edge
setup time
TSU
THD
THI
SDI setup time
SDI hold time
30
50
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
SCLK high time
SCLK low time
SDO setup time
150
150
—
—
TLO
TDO
—
150
—
TSCCS SCLK last edge to CS rise
setup time
100
TCSH
TCS1
CS high time
500
50
—
—
—
—
ns
ns
CS rise to SCLK edge setup
time
TCS0
SCLK edge to CS fall setup
time
50
—
—
—
—
ns
ns
SCLK edge when CS is high
TSPIR Rise time of SPI data
(SPI Read command)
10
VDD = 3.0V. Time is measured from 10%
to 90% of amplitude
TSPIF
Fall time of SPI data
(SPI Read command)
—
10
—
ns
VDD = 3.0V. Time is measured from 90%
to 10% of amplitude
*
Parameter is characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Required output enable filter high time must account for input path analog delays = TOEH - TDR + TDF
2: Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF)
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 171
PIC12F635/PIC16F636/639
NOTES:
DS41232B-page 172
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
16.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs and Tables are not available at this time.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 173
PIC12F635/PIC16F636/639
NOTES:
DS41232B-page 174
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
17.0 PACKAGING INFORMATION
17.1 Package Marking Information
8-Lead PDIP
Example
12F635/P
017
XXXXXXXX
XXXXXNNN
YYWW
0510
8-Lead SOIC
Example
XXXXXXXX
XXXXYYWW
12F635
/SN0510
NNN
017
8-Lead DFN-S
Example
XXXXXX
XXXXXX
YYWW
NNN
PIC12F
635/MF
0510
017
14-Lead PDIP
Example
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
PIC16F636-I/P
0510017
YYWWNNN
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
)
3
e
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 175
PIC12F635/PIC16F636/639
17.1 Package Marking Information (Continued)
14-Lead SOIC
Example
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
PIC16F636
-I/SL
0510017
14-Lead TSSOP
Example
XXXXXXXX
YYWW
F636/ST
0510
017
NNN
20-Lead SSOP
Example
XXXXXXXXXXX
XXXXXXXXXXX
PIC16F639
-I/SS
YYWWNNN
0510017
DS41232B-page 176
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
17.2 Package Details
The following sections give the technical details of the packages.
8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 177
PIC12F635/PIC16F636/639
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil Body (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
1.27
Overall Height
A
.053
.069
1.35
1.32
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
§
0.10
5.79
3.71
4.80
0.25
0.48
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS41232B-page 178
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
8-Lead Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S) – Saw Singulated
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 179
PIC12F635/PIC16F636/639
14-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
B1
β
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
14
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
0.38
7.62
6.10
18.80
3.18
0.20
1.14
0.36
7.87
5
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.740
.125
.008
.045
.014
.310
5
.145
3.68
.313
.250
.750
.130
.012
.058
.018
.370
10
.325
.260
.760
.135
.015
.070
.022
.430
15
7.94
6.35
19.05
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
19.30
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
DS41232B-page 180
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil Body (SOIC)
E
E1
p
D
2
1
B
n
α
h
45°
c
A2
A
φ
A1
L
β
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
14
.050
.061
.056
.007
.236
.154
.342
.015
.033
4
1.27
Overall Height
A
.053
.052
.004
.228
.150
.337
.010
.016
0
.069
1.35
1.32
1.55
1.42
0.18
5.99
3.90
8.69
0.38
0.84
4
1.75
Molded Package Thickness
Standoff
A2
A1
E
.061
.010
.244
.157
.347
.020
.050
8
1.55
0.25
6.20
3.99
8.81
0.51
1.27
8
§
0.10
5.79
3.81
8.56
0.25
0.41
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.014
0
.009
.017
12
.010
.020
15
0.20
0.36
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 181
PIC12F635/PIC16F636/639
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
φ
A1
A2
β
L
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
14
MAX
n
p
Number of Pins
Pitch
14
.026
0.65
Overall Height
A
.043
1.10
0.95
0.15
6.50
4.50
5.10
0.70
8
Molded Package Thickness
Standoff
A2
A1
E
.033
.002
.246
.169
.193
.020
0
.035
.004
.251
.173
.197
.024
4
.037
.006
.256
.177
.201
.028
8
0.85
0.05
0.90
0.10
6.38
4.40
5.00
0.60
4
§
Overall Width
6.25
4.30
4.90
0.50
0
Molded Package Width
Molded Package Length
Foot Length
E1
D
L
φ
Foot Angle
c
Lead Thickness
.004
.007
0
.006
.010
5
.008
.012
10
0.09
0.19
0
0.15
0.25
5
0.20
0.30
10
Lead Width
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
DS41232B-page 182
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
20-Lead Plastic Shrink Small Outline (SS) – 209 mil Body, 5.30 mm (SSOP)
E
E1
p
D
B
2
1
n
c
A2
A
f
L
A1
Units
Dimension Limits
INCHES
NOM
20
MILLIMETERS*
MIN
MAX
MIN
NOM
20
MAX
n
p
Number of Pins
Pitch
.026
0.65
-
Overall Height
A
A2
A1
E
-
-
.079
-
2.00
1.85
-
Molded Package Thickness
Standoff
.065
.002
.291
.197
.272
.022
.004
0°
.069
-
.073
-
1.65
0.05
7.40
5.00
.295
0.55
0.09
0°
1.75
-
Overall Width
.307
.209
.283
.030
-
.323
.220
.289
.037
.010
8°
7.80
5.30
7.20
0.75
-
8.20
5.60
7.50
0.95
0.25
8°
Molded Package Width
Overall Length
Foot Length
E1
D
L
c
Lead Thickness
Foot Angle
f
4°
4°
Lead Width
B
.009
-
.015
0.22
-
0.38
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions
shall not exceed .010" (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No. C04-072
Revised 11/03/03
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 183
PIC12F635/PIC16F636/639
NOTES:
DS41232B-page 184
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
In addition, there is
a
Development Systems
Information Line which lists the latest versions of
Microchip’s development systems software products.
This line also provides information on how customers
can receive currently available upgrade kits.
The Development Systems Information Line
numbers are:
CUSTOMER CHANGE NOTIFICATION
SERVICE
1-800-755-2345 – United States and most of Canada
1-480-792-7302 – Other International Locations
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 185
PIC12F635/PIC16F636/639
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
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Telephone: (_______) _________ - _________
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Application (optional):
Would you like a reply?
Y
N
PIC12F635/PIC16F636/639
DS41232B
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41232B-page 186
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A
This is a new data sheet.
Revision B
Added PIC16F639 to the data sheet.
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 187
PIC12F635/PIC16F636/639
NOTES:
DS41232B-page 188
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
INDEX
Alarm .................................................................. 81
Auto Channel Selection...................................... 80
A
Absolute Maximum Ratings .............................................. 147
AC Characteristics
Inactivity ............................................................. 81
Period ................................................................. 81
Preamble Counters............................................. 81
Pulse Width ........................................................ 81
RC Oscillator ...................................................... 80
Tuning Capacitor ........................................................ 79
Variable Attenuator..................................................... 79
Analog Input Connection Considerations ........................... 62
Assembler
Analog Front-End (AFE) for PIC16F639................... 168
Industrial and Extended ............................................ 162
Load Conditions........................................................ 161
AGC Settling ....................................................................... 81
Analog Front-End
Configuration Registers
Summary Table ................................................ 105
Analog Front-End (AFE) ..................................................... 79
A/D Data Conversion of RSSI Signal........................ 100
AFE Status Register Bit Condition............................ 110
AGC ................................................................ 80, 81, 88
AGC Preserve............................................................. 88
Battery Back-up and Batteryless Operation................ 92
Block Diagrams
MPASM Assembler .................................................. 141
B
Block Diagrams
Analog Input Model..................................................... 62
Ceramic Resonator Operation.................................... 31
Clock Source .............................................................. 29
Comparator C1 Output ............................................... 65
Comparator C2 Output ............................................... 66
Comparator I/O Operating Modes for PIC12F635...... 63
Comparator I/O Operating Modes for
Bidirectional PKE System Application
Example...................................................... 84
Functional ........................................................... 82
LC Input Path...................................................... 83
Output Enable Filter Timing ................................ 85
Output Enable Filter Timing (Detailed) ............... 86
Carrier Clock Detector ................................................ 80
Carrier Clock Output ................................................... 96
Examples............................................................ 97
Command Decoder/Controller .................................. 103
Configuration Registers ............................................ 104
Data Slicer .................................................................. 80
Demodulator ......................................................... 80, 93
De-Q’ing of Antenna Circuit ........................................ 92
Error Detection............................................................ 91
Factory Calibration...................................................... 92
Fixed Gain Amplifiers.................................................. 80
Input Sensitivity Control .............................................. 87
LF Field Powering/Battery Back-up
PIC16F636/639 .................................................. 64
Comparator Voltage Reference (CVREF).................... 68
External Clock Mode .................................................. 31
Fail-Safe Clock Monitor (FSCM)................................. 36
Functional (AFE)......................................................... 82
In-Circuit Serial Programming Connection ............... 129
Interrupt Logic........................................................... 122
On-Chip Reset Circuit............................................... 113
PIC12F635 Device ....................................................... 5
PIC16F636 Device ....................................................... 6
PIC16F639 Device ....................................................... 7
Quartz Crystal Operation............................................ 31
RA0 Pin ...................................................................... 44
RA1 Pin ...................................................................... 45
RA2 Pin ...................................................................... 45
RA3 Pin ...................................................................... 46
RA4 Pin ...................................................................... 47
RA5 Pin ...................................................................... 47
RC Mode .................................................................... 32
RC0 and RC1 Pins ..................................................... 49
RC2, RC3 and RC5 Pins............................................ 49
RC4 Pin ...................................................................... 50
RCIO Mode................................................................. 32
Recommended MCLR Circuit................................... 114
Timer1 ........................................................................ 57
TMR0/WDT Prescaler ................................................ 53
Watchdog Timer (WDT)............................................ 125
Brown-out Detect (BOD)................................................... 115
Associated Registers................................................ 116
Specifications ........................................................... 165
Examples............................................................ 92
LFDATA Output Selection........................................... 93
Case I ................................................................. 94
Case II ................................................................ 94
Low Current Modes
Operating ............................................................ 91
Sleep................................................................... 91
Standby............................................................... 91
Modulation Circuit ....................................................... 79
Modulation Depth........................................................ 89
Examples............................................................ 90
Output Enable Filter.................................................... 80
Configurable Smart............................................. 85
Output Enable Filter Timing (Table)............................ 87
Power-on Reset .......................................................... 93
RF Limiter ................................................................... 79
RSSI...................................................................... 80, 98
Output Path Diagram .......................................... 98
Power-up Sequence Diagram........................... 100
SPI Read Sequence Diagram........................... 102
SPI Write Sequence Diagram........................... 101
RSSI Output Current vs. Input Signal Level
C
C Compilers
MPLAB C17.............................................................. 142
MPLAB C18.............................................................. 142
MPLAB C30.............................................................. 142
CLKOUT and I/O Timing Requirements........................... 164
Clock Sources..................................................................... 29
Associated Registers.................................................. 38
External Clock Modes................................................. 30
Internal Clock Modes.................................................. 32
Modes......................................................................... 30
Example.............................................................. 99
Sensitivity Control ....................................................... 79
Soft Reset ................................................................... 89
SPI Interface Timing Diagram................................... 104
Timers................................................................... 80, 81
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 189
PIC12F635/PIC16F636/639
Oscillator Configuration...............................................29
Clock Switching...................................................................35
Fail-Safe Clock Monitor...............................................36
Two-Speed Clock Start-up..........................................35
Code Examples
Device Overview................................................................... 5
E
EECON1 (EEPROM Control 1) Register............................ 74
EECON2 (EEPROM Control 2) Register............................ 74
EEPROM Data Memory
Assigning Prescaler to Timer0 ....................................55
Assigning Prescaler to WDT .......................................55
Data EEPROM Read ..................................................75
Data EEPROM Write ..................................................75
Indirect Addressing .....................................................27
Initializing PORTA.......................................................39
Initializing PORTC.......................................................49
Saving Status and W Registers in RAM ...................124
Ultra Low-Power Wake-up Initialization ......................43
Write Verify .................................................................75
Code Protection ................................................................128
Comparator Voltage Reference (CVREF) ............................68
Accuracy/Error ............................................................68
Configuring..................................................................68
Specifications............................................................167
Comparators .......................................................................61
C2OUT as T1 Gate ...............................................58, 67
Configurations.............................................................63
Effects of a Reset........................................................69
Interrupts.....................................................................67
Operation ....................................................................62
Operation During Sleep ..............................................69
Outputs .......................................................................67
Response Time...........................................................69
Specifications............................................................167
Synchronizing C2OUT w/ Timer1 ...............................67
Computed GOTO................................................................26
Configuration Bits..............................................................112
CPU Features ...................................................................111
Customer Change Notification Service .............................185
Customer Notification Service...........................................185
Customer Support.............................................................185
Reading ...................................................................... 75
Write Verify................................................................. 75
Writing ........................................................................ 75
Electrical Specifications.................................................... 147
Errata.................................................................................... 3
Evaluation and Programming Tools.................................. 145
External Clock Timing Requirements ............................... 162
F
Fail-Safe Clock Monitor ...................................................... 36
Fail-Safe Condition Clearing....................................... 37
Reset and Wake-up from Sleep.................................. 37
Firmware Instructions ....................................................... 131
G
General Purpose Register (GPR) File ................................ 12
I
ID Locations...................................................................... 128
In-Circuit Debugger........................................................... 129
In-Circuit Serial Programming (ICSP)............................... 129
Indirect Addressing, INDF and FSR Registers ................... 27
Instruction Format............................................................. 131
Instruction Set................................................................... 131
ADDLW..................................................................... 133
ADDWF..................................................................... 133
ANDLW..................................................................... 133
ANDWF..................................................................... 133
BCF .......................................................................... 133
BSF........................................................................... 133
BTFSC...................................................................... 133
BTFSS ...................................................................... 133
CALL......................................................................... 134
CLRF ........................................................................ 134
CLRW ....................................................................... 134
CLRWDT .................................................................. 134
COMF ....................................................................... 134
DECF........................................................................ 134
DECFSZ ................................................................... 135
GOTO ....................................................................... 135
INCF ......................................................................... 135
INCFSZ..................................................................... 135
IORLW...................................................................... 135
IORWF...................................................................... 135
MOVF ....................................................................... 136
MOVLW .................................................................... 136
MOVWF.................................................................... 136
NOP.......................................................................... 136
RETFIE..................................................................... 137
RETLW ..................................................................... 137
RETURN................................................................... 137
RLF........................................................................... 137
RRF .......................................................................... 138
SLEEP ...................................................................... 138
SUBLW..................................................................... 138
SUBWF..................................................................... 138
SWAPF..................................................................... 138
XORLW .................................................................... 138
XORWF .................................................................... 139
Summary Table ........................................................ 132
D
Data EEPROM Memory
Associated Registers ..................................................76
Code Protection .................................................... 73, 76
Endurance...................................................................75
Protection Against Spurious Write ..............................76
Using...........................................................................75
Data Memory.......................................................................11
DC and AC
Characteristics Graphs and Tables...........................173
DC Characteristics
Extended (PIC12F635/PIC16F636)..........................152
Extended (PIC16F639) .............................................158
Industrial (PIC12F635/PIC16F636)...........................150
Industrial (PIC16F639)..............................................157
Industrial/Extended (PIC12F635/PIC16F636) .. 149, 154
Industrial/Extended (PIC16F639)......................156, 159
Demonstration Boards
PICDEM 1 .................................................................144
PICDEM 17 ...............................................................145
PICDEM 18R ............................................................145
PICDEM 2 Plus.........................................................144
PICDEM 3 .................................................................144
PICDEM 4 .................................................................144
PICDEM LIN .............................................................145
PICDEM USB............................................................145
PICDEM.net Internet/Ethernet ..................................144
Development Support .......................................................141
DS41232B-page 190
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
Internal Oscillator Block
RA1/C1IN-/Vref/ICSPCLK Pin.................................... 45
INTOSC Specifications ............................................. 163
Internet Address................................................................ 185
Interrupts........................................................................... 121
Associated Registers ................................................ 123
Comparators ............................................................... 67
Context Saving.......................................................... 124
Data EEPROM Memory Write .................................... 74
Interrupt-on-change .................................................... 42
PORTA Interrupt-on-change..................................... 122
RA2/INT .................................................................... 121
TMR0 ........................................................................ 122
INTOSC Specifications ..................................................... 163
RA2/T0CKI/INT/C1OUT Pin ....................................... 45
RA3/MCLR/VPP PIN.................................................... 46
RA4/T1G/OSC2/CLKOUT Pin.................................... 47
RA5/T1CKI/OSC1/CLKIN Pin..................................... 47
PORTC ............................................................................... 49
Associated Registers.................................................. 51
RC0/C2IN+ Pin........................................................... 49
RC2 Pin ...................................................................... 49
RC3 Pin ...................................................................... 49
RC4/C2OUT Pin......................................................... 50
Power Control (PCON) Register....................................... 116
Power-Down Mode (Sleep)............................................... 127
Power-on Reset................................................................ 114
Power-up Timer (PWRT)
K
KEELOQ ............................................................................... 77
Specifications ........................................................... 165
Precision Internal Oscillator Parameters .......................... 163
Prescaler
Shared WDT/Timer0................................................... 55
Switching Prescaler Assignment ................................ 55
PRO MATE II Universal Device Programmer................... 143
Product Identification ........................................................ 193
Program Memory................................................................ 11
Program Memory Map and Stack
PIC12F635 ................................................................. 11
PIC16F636/639 .......................................................... 11
Programmable Low-Voltage Detect (PLVD) Module .......... 71
Programming, Device Instructions.................................... 131
L
Load Conditions................................................................ 161
M
MCLR................................................................................ 114
Internal...................................................................... 114
Memory Organization.......................................................... 11
Data ............................................................................ 11
Data EEPROM Memory.............................................. 73
Program ...................................................................... 11
Microchip Internet Web Site.............................................. 185
MPLAB ASM30 Assembler, Linker, Librarian ................... 142
MPLAB ICD 2 In-Circuit Debugger ................................... 143
MPLAB ICE 2000 High-Performance Universal
R
Reader Response............................................................. 186
Read-Modify-Write Operations ......................................... 131
Registers
In-Circuit Emulator ................................................... 143
MPLAB ICE 4000 High-Performance Universal
In-Circuit Emulator ................................................... 143
MPLAB Integrated Development Environment Software .. 141
MPLAB PM3 Device Programmer .................................... 143
MPLINK Object Linker/MPLIB Object Librarian ................ 142
Analog Front-End (AFE)
AFE Status Register 7...................................... 109
Column Parity Register 6.................................. 108
Configuration Register 0................................... 105
Configuration Register 1................................... 106
Configuration Register 2................................... 106
Configuration Register 3................................... 107
Configuration Register 4................................... 107
Configuration Register 5................................... 108
CMCON0 (Comparator Control 0).............................. 61
CMCON1 (Comparator Control 1).............................. 66
CONFIG (Configuration Word) ................................. 112
EEADR (EEPROM Address)...................................... 73
EECON1 (EEPROM Control 1) .................................. 74
EEDAT (EEPROM Data)............................................ 73
INTCON (Interrupt Control) ........................................ 22
IOCA (Interrupt-on-change PORTA) .......................... 42
LVDCON (Low-Voltage Detect Control) ..................... 71
OPTION_REG (Option)........................................ 21, 54
OSCCON (Oscillator Control)..................................... 38
OSCTUNE (Oscillator Tuning).................................... 33
PCON (Power Control)............................................... 25
PIE1 (Peripheral Interrupt Enable 1) .......................... 23
PIR1 (Peripheral Interrupt Request 1)........................ 24
PORTA ....................................................................... 41
PORTC....................................................................... 51
Reset Values ............................................................ 119
Reset Values (Special Registers)............................. 120
Status ......................................................................... 20
T1CON (Timer1 Control) ............................................ 59
TRISA (PORTA Tri-State) .......................................... 41
TRISC (PORTC Tri-State).......................................... 51
VRCON (Voltage Reference Control)......................... 69
O
Opcode Field Descriptions................................................ 131
Oscillator Start-up Timer (OST) .......................................... 30
Specifications............................................................ 165
P
Packaging ......................................................................... 175
Details....................................................................... 177
Marking ..................................................................... 175
PCL and PCLATH............................................................... 26
Computed GOTO........................................................ 26
Stack........................................................................... 26
PICkit 1 Flash Starter Kit................................................... 145
PICSTART Plus Development Programmer ..................... 144
Pin Diagrams ........................................................................ 2
Pinout Descriptions
PIC12F635.................................................................... 8
PIC16F636.................................................................... 9
PIC16F639.................................................................. 10
PORTA................................................................................ 39
Additional Pin Functions ............................................. 39
Interrupt-on-change ............................................ 42
Ultra Low-Power Wake-up............................ 39, 43
Weak Pull-down.................................................. 39
Weak Pull-up ...................................................... 39
Associated Registers .................................................. 48
Pin Descriptions and Diagrams................................... 44
RA0/C1IN+/ICSPDAT/ULPWU Pin............................. 44
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 191
PIC12F635/PIC16F636/639
WDA (Weak Pull-up/Pull-down PORTA).....................40
WDTCON (Watchdog Timer Control)........................126
WPUDA (Weak Pull-up/Pull-down Direction PORTA).40
Reset.................................................................................113
Revision History ................................................................187
Timing Parameter Symbology .......................................... 161
TRISA ................................................................................. 39
Two-Speed Clock Start-up Mode........................................ 35
U
Ultra Low-Power Wake-up.................................. 9, 10, 39, 43
S
V
Software Simulator (MPLAB SIM).....................................142
Software Simulator (MPLAB SIM30).................................142
Special Function Registers (SFR).......................................12
Maps
Voltage Reference. See Comparator Voltage Reference
(CVREF).
W
PIC12F635..........................................................13
PIC16F636/639...................................................14
Summary
Wake-up from Sleep......................................................... 127
Wake-up Reset (WUR)..................................................... 114
Wake-up using Interrupts.................................................. 127
Watchdog Timer (WDT).................................................... 125
Associated Registers................................................ 126
Control ...................................................................... 125
Oscillator................................................................... 125
Specifications ........................................................... 165
WWW Address ................................................................. 185
WWW, On-Line Support ....................................................... 3
PIC12F635, Bank 0.............................................15
PIC12F635, Bank 1.............................................16
PIC12F635/PIC16F636/639, Bank 2 ..................19
PIC16F636/639, Bank 0......................................17
PIC16F636/639, Bank 1......................................18
SPI Timing
Analog Front-End (AFE) for PIC16F639 ...................171
Status Register
IRP Bit.........................................................................20
RP Bits........................................................................20
T
Time-out Sequence...........................................................116
Timer0.................................................................................53
Associated Registers ..................................................55
Interrupt.......................................................................53
Operation ....................................................................53
T0CKI..........................................................................54
Using with External Clock ...........................................54
Timer0 and Timer1
External Clock Requirements ...................................166
Timer1.................................................................................57
Associated Registers ..................................................60
Asynchronous Counter Mode .....................................60
Reading and Writing ...........................................60
Interrupt.......................................................................58
Modes of Operations...................................................58
Operation During Sleep ..............................................60
Oscillator.....................................................................60
Prescaler.....................................................................58
Timer1 Gate
Inverting Gate .....................................................58
Selecting Source...........................................58, 67
Synchronizing C2OUT w/ Timer1 .......................67
TMR1H Register .........................................................57
TMR1L Register..........................................................57
Timing Diagrams
Brown-out Detect (BOD)...........................................165
Brown-out Detect Situations .....................................115
CLKOUT and I/O.......................................................163
External Clock...........................................................162
Fail-Safe Clock Monitor (FSCM).................................37
INT Pin Interrupt........................................................123
Reset, Watchdog Timer, Oscillator Start-up Timer and
Power-up Timer ................................................164
Single Comparator ......................................................62
Time-out Sequence on Power-up (Delayed MCLR) .118
Time-out Sequence on Power-up (MCLR with VDD).118
Timer0 and Timer1 External Clock ...........................166
Timer1 Incrementing Edge..........................................58
Two-Speed Start-up....................................................36
Wake-up from Sleep through Interrupt......................128
DS41232B-page 192
Preliminary
© 2005 Microchip Technology Inc.
PIC12F635/PIC16F636/639
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature Package
Range
Pattern
a)
PIC12F635-E/P 301 = Extended Temp., PDIP
package, 20 MHz, QTP pattern #301
PIC12F635-I/S Industrial Temp., SOIC
package, 20 MHz
b)
=
Device
PIC12F635: Standard VDD range
PIC12F635T: (Tape and Reel)
PIC16F636: Standard VDD range
PIC16F636T: (Tape and Reel)
PIC16F639: Standard VDD range
PIC16F639T: (Tape and Reel)
Temperature Range
Package
I
E
=
=
-40°C to +85°C
-40°C to +125°C
MF
P
SN
SL
SS
ST
=
=
=
=
=
=
DFN-S (6x5 mm, 8-pin)
PDIP (300 mil)
SOIC (Gull wing, 150 mil body, 8-pin)
SOIC (Gull wing, 150 mil body, 14-pin)
SSOP (209 mil, 20-pin)
TSSOP (4.4 mm, 14-pin)
Pattern
3-Digit Pattern Code for QTP (blank otherwise)
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 193
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
India - Bangalore
Tel: 91-80-2229-0061
Fax: 91-80-2229-0062
Austria - Weis
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http:\\support.microchip.com
Web Address:
www.microchip.com
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Denmark - Ballerup
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-5160-8631
Fax: 91-11-5160-8632
China - Chengdu
Tel: 86-28-8676-6200
Fax: 86-28-8676-6599
France - Massy
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Kanagawa
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Atlanta
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Germany - Ismaning
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Korea - Seoul
Alpharetta, GA
Tel: 770-640-0034
Fax: 770-640-0307
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Boston
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Westford, MA
Tel: 978-692-3848
Fax: 978-692-3821
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
England - Berkshire
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Dallas
Addison, TX
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Tel: 972-818-7423
Fax: 972-818-2924
Taiwan - Hsinchu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Shunde
Detroit
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Qingdao
Tel: 86-532-502-7355
Fax: 86-532-502-7205
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
San Jose
Mountain View, CA
Tel: 650-215-1444
Fax: 650-961-0286
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
10/20/04
DS41232B-page 194
Preliminary
© 2005 Microchip Technology Inc.
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