PIC16C54A-10/P301_技术文档

PIC16C5X

M

EPROM/ROM-Based 8-Bit CMOS Microcontroller Series

• 12-bit wide instructions

Devices Included in this Data Sheet:

• 8-bit wide data path

• PIC16C52

• Seven or eight special function hardware registers

• Two-level deep hardware stack

• PIC16C54s

• PIC16CR54s

• PIC16C55s

• Direct, indirect and relative addressing modes for

data and instructions

• PIC16C56s

Peripheral Features:

• 8-bit real time clock/counter (TMR0) with 8-bit

programmable prescaler

• PIC16CR56s

• PIC16C57s

• PIC16CR57s

• PIC16C58s

• Power-On Reset (POR)

• Device Reset Timer (DRT)

• PIC16CR58s

• Watchdog Timer (WDT) with its own on-chip

RC oscillator for reliable operation

Note: The letter "s" used following the part

numbers throughout this document

indicate plural, meaning there is more

than one part variety for the indicated

device.

• Programmable code-protection

• Power saving SLEEP mode

• Selectable oscillator options:

- RC:

- XT:

- HS:

- LP:

Low-cost RC oscillator

High-Performance RISC CPU:

• Only 33 single word instructions to learn

Standard crystal/resonator

High-speed crystal/resonator

Power saving, low-frequency crystal

• All instructions are single cycle (200 ns) except for

program branches which are two-cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

CMOS Technology:

• Low-power, high-speed CMOS EPROM/ROM

technology

EPROM/

Device

Pins I/O

RAM

• Fully static design

ROM

• Wide-operating voltage and temperature range:

- EPROM Commercial/Industrial 2.0V to 6.25V

- ROM Commercial/Industrial 2.0V to 6.25V

- EPROM Extended 2.5V to 6.0V

- ROM Extended 2.5V to 6.0V

PIC16C52

18

28

18

28

18

12

20

12

20

12

384

512

1K

25

24

25

72

73

PIC16C54

PIC16C54A

PIC16C54B

PIC16C54C

PIC16CR54A

PIC16CR54B

PIC16CR54C

PIC16C55

• Low-power consumption

- < 2 mA typical @ 5V, 4 MHz

- 15 µA typical @ 3V, 32 kHz

- < 0.6 µA typical standby current

(with WDT disabled) @ 3V, 0°C to 70°C

PIC16C55A

PIC16C56

PIC16C56A

PIC16CR56A

PIC16C57

1K

Note: In this document, ﬁgure and table titles

refer to all varieties of the part number

indicated, (i.e., The title "Figure 14-1:

Load Conditions - PIC16C54A", also

refers to PIC16LC54A and PIC16LV54A

parts).

1K

2K

PIC16C57C

PIC16CR57B

PIC16CR57C

PIC16C58A

PIC16C58B

PIC16CR58A

PIC16CR58B

2K

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 1

PIC16C5X

Pin Diagrams

PDIP, SOIC, Windowed CERDIP

18

17

16

15

14

RA1

RA0

OSC1/CLKIN

OSC2/CLKOUT

VDD

•1

2

3

4

5

6

7

8

9

RA2

RA3

T0CKI

VDD

N/C

•1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

MCLR/VPP

OSC1/CLKIN

3

OSC2/CLKOUT

RC7

MCLR/VPP

VSS

4

N/C

5

RC6

RB7

RB6

RB5

RB4

13

12

RB0

RB1

RB2

RB3

RA0

RA1

RA2

RA3

RB0

RB1

RB2

RB3

RB4

6

RC5

RC4

RC3

11

10

7

8

RC2

9

RC1

RC0

10

11

12

13

14

RB7

RB6

RB5

SSOP

VSS

•1

2

3

4

5

6

7

8

28

27

26

25

24

23

22

21

20

19

18

17

16

15

MCLR/VPP

OSC1/CLKIN

OSC2/CLKOUT

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RA2

RA3

T0CKI

MCLR/VPP

VSS

•1

2

3

4

20

19

18

17

16

15

14

13

12

11

RA1

RA0

OSC1/CLKIN

OSC2/CLKOUT

T0CKI

VDD

RA0

RA1

RA2

RA3

RB0

RB1

RB2

RB3

RB4

VSS

5

6

7

8

VDD

RB7

RB6

RB5

RB4

VSS

RB0

RB1

9

10

11

12

13

14

RB2

RB3

9

10

RC0

RB7

RB6

RB5

DS30453B-page 2

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

Device Differences

Device

Oscillator

Selection

(Program)

Process

Technology

(Microns)

Voltage

Range

ROM

Equivalent

MCLR

Filter

Oscillator

PIC16C52

PIC16C54

PIC16C54A

PIC16C54B

PIC16C54C

PIC16C55

PIC16C55A

PIC16C56

PIC16C56A

PIC16C57

PIC16C57C

PIC16C58A

3.0-6.25

2.5-6.25

2.0-6.25

2.5-5.5

User

Factory

User

See Note 1

0.9

1.2

0.9

0.7

1.7

0.7

1.7

0.7

1.2

0.7

0.9

—

PIC16CR54A

—

No

User

PIC16CR54B

PIC16CR54C

—

Yes

No

2.5-5.5

User

2.5-6.25

2.5-5.5

Factory

User

—

Yes

No

2.5-6.25

2.5-5.5

Factory

User

—

PIC16CR56A

—

Yes

No

2.5-6.25

2.5-5.5

Factory

User

PIC16CR57C

PIC16CR58A

Yes

(2)

2.0-6.25

User

No

PIC16C58B

2.5-5.5

2.5-6.25

2.5-5.5

2.5-6.25

2.5-5.5

2.5-6.25

2.5-5.5

User

See Note 1

0.7

1.2

0.7

0.9

0.7

0.9

0.7

PIC16CR58B

N/A

Yes

PIC16CR54A

PIC16CR54B

PIC16CR54C

PIC16CR56A

PIC16CR57B

PIC16CR57C

PIC16CR58A

PIC16CR58B

Factory

N/A

Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.

Note 2: In PIC16LV58A, MCLR Filter = Yes

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 3

PIC16C5X

Table of Contents

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

General Description.............................................................................................................................................5

PIC16C5X Device Varieties.................................................................................................................................7

Architectural Overview.........................................................................................................................................9

Memory Organization ........................................................................................................................................15

I/O Ports.............................................................................................................................................................25

Timer0 Module and TMR0 Register...................................................................................................................27

Special Features of the CPU .............................................................................................................................31

Instruction Set Summary ...................................................................................................................................43

Development Support........................................................................................................................................55

10.0 Electrical Characteristics - PIC16C52................................................................................................................59

11.0 Electrical Characteristics - PIC16C54/55/56/57.................................................................................................67

12.0 DC and AC Characteristics - PIC16C54/55/56/57.............................................................................................81

13.0 Electrical Characteristics - PIC16CR54A...........................................................................................................89

14.0 Electrical Characteristics - PIC16C54A ...........................................................................................................103

15.0 Electrical Characteristics - PIC16CR57B.........................................................................................................117

16.0 Electrical Characteristics - PIC16C58A ...........................................................................................................131

17.0 Electrical Characteristics - PIC16CR58A.........................................................................................................145

18.0 DC and AC Characteristics - PIC16C54A/CR57B/C58A/CR58A ....................................................................159

19.0 Electrical Characteristics -

PIC16C54B/C54C/CR54B/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B....................................171

20.0 DC and AC Characteristics -

PIC16C54B/C54C/CR54B/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B....................................183

21.0 Packaging Information.....................................................................................................................................195

Appendix A: Compatibility ...........................................................................................................................................207

Index .........................................................................................................................................................................209

On-Line Support..........................................................................................................................................................211

PIC16C5X Product Identification System....................................................................................................................213

PIC16C54/55/56/57 Product Identification System.....................................................................................................214

To Our Valued Customers

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.

Errata

An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended

workarounds. As device/documentation issues become known to us, we will publish an errata sheet.The errata will specify the revi-

sion of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

Microchip’s Worldwide Web site; http://www.microchip.com

Your local Microchip sales ofﬁce (see last page)

The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277

When contacting a sales ofﬁce or the literature center, please specify which device, revision of silicon and data sheet (include lit-

erature number) you are using.

Corrections to this Data Sheet

We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure

that this document is correct. However, we realize that we may have missed a few things. If you ﬁnd any information that is missing

or appears in error, please:

•

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We appreciate your assistance in making this a better document.

DS30453B-page 4

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

1.1

Applications

1.0

GENERAL DESCRIPTION

The PIC16C5X from Microchip Technology is a family

of low-cost, high performance, 8-bit, fully static,

EPROM/ ROM-based CMOS microcontrollers. It

employs a RISC architecture with only 33 single

word/single cycle instructions. All instructions are sin-

gle cycle (200 ns) except for program branches which

take two cycles. The PIC16C5X delivers performance

an order of magnitude higher than its competitors in the

same price category. The 12-bit wide instructions are

highly symmetrical resulting in 2:1 code compression

over other 8-bit microcontrollers in its class. The easy

to use and easy to remember instruction set reduces

development time signiﬁcantly.

The PIC16C5X series ﬁts perfectly in applications rang-

ing from high-speed automotive and appliance motor

control to low-power remote transmitters/receivers,

pointing devices and telecom processors.The EPROM

technology makes customizing application programs

(transmitter codes, motor speeds, receiver frequen-

cies, etc.) extremely fast and convenient. The small

footprint packages, for through hole or surface mount-

ing, make this microcontroller series perfect for applica-

tions with space limitations. Low-cost, low-power, high

performance, ease of use and I/O ﬂexibility make the

PIC16C5X series very versatile even in areas where no

microcontroller use has been considered before (e.g.,

timer functions, replacement of “glue” logic in larger

systems, coprocessor applications).

The PIC16C5X products are equipped with special fea-

tures that reduce system cost and power requirements.

The Power-On Reset (POR) and Device Reset Timer

(DRT) eliminate the need for external reset circuitry.

There are four oscillator conﬁgurations to choose from,

including the power-saving LP (Low Power) oscillator

and cost saving RC oscillator. Power saving SLEEP

mode, Watchdog Timer and code protection features

improve system cost, power and reliability.

The UV erasable CERDIP packaged versions are ideal

for code development, while the cost-effective One

Time Programmable (OTP) versions are suitable for

production in any volume. The customer can take full

advantage of Microchip’s price leadership in OTP

microcontrollers while beneﬁting from the OTP’s

ﬂexibility.

The PIC16C5X products are supported by

a

full-featured macro assembler, a software simulator, an

in-circuit emulator, a ‘C’ compiler, fuzzy logic support

tools, a low-cost development programmer, and a full

featured programmer. All the tools are supported on

IBM PC and compatible machines.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 5

PIC16C5X

TABLE 1-1:

PIC16C5X FAMILY OF DEVICES

PIC16C52

PIC16C54s

20

PIC16CR54s

20

PIC16C55s

20

PIC16C56s

20

Maximum Frequency

of Operation (MHz)

4

Clock

EPROM Program Memory

(x12 words)

384

—

512

—

512

—

1K

—

Memory

ROM Program Memory

(x12 words)

512

RAM Data Memory (bytes)

Timer Module(s)

I/O Pins

25

24

25

Peripherals

Features

TMR0

12

TMR0

12

TMR0

12

TMR0

20

TMR0

12

Number of Instructions

Packages

33

18-pin DIP,

SOIC

18-pin DIP,

SOIC;

18-pin DIP,

SOIC;

28-pin DIP,

SOIC;

18-pin DIP,

SOIC;

20-pin SSOP

28-pin SSOP

20-pin SSOP

All PICmicro™ Family devices have Power-on Reset, selectable Watchdog Timer (except PIC16C52), selectable code

protect and high I/O current capability.

PIC16CR56s

20

PIC16C57s

20

PIC16CR57s

20

PIC16C58s

20

PIC16CR58s

20

Maximum Frequency

of Operation (MHz)

Clock

EPROM Program Memory

(x12 words)

—

2K

—

2K

—

Memory

ROM Program Memory

(x12 words)

1K

2K

RAM Data Memory (bytes)

25

72

73

Peripherals Timer Module(s)

TMR0

12

TMR0

20

TMR0

20

TMR0

12

TMR0

12

I/O Pins

Number of Instructions

Packages

33

Features

18-pin DIP,

SOIC;

28-pin DIP,

SOIC;

28-pin DIP,

SOIC;

18-pin DIP,

SOIC;

18-pin DIP,

SOIC;

20-pin SSOP

28-pin SSOP 28-pin SSOP

20-pin SSOP 20-pin SSOP

All PICmicro™ Family devices have Power-on Reset, selectable Watchdog Timer (except PIC16C52), selectable code

protect and high I/O current capability.

DS30453B-page 6

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

2.3

Quick-Turnaround-Production (QTP)

Devices

2.0

PIC16C5X DEVICE VARIETIES

A variety of frequency ranges and packaging options

are available. Depending on application and

production requirements, the proper device option can

be selected using the information in this section. When

placing orders, please use the PIC16C5X Product

Identiﬁcation System at the back of this data sheet to

specify the correct part number.

Microchip offers a QTP Programming Service for

factory production orders. This service is made

available for users who choose not to program a

medium to high quantity of units and whose code

patterns have stabilized. The devices are identical to

the OTP devices but with all EPROM locations and

conﬁguration bit options already programmed by the

factory. Certain code and prototype veriﬁcation

procedures apply before production shipments are

available. Please contact your Microchip Technology

sales ofﬁce for more details.

For the PIC16C5X family of devices, there are four

device types, as indicated in the device number:

1. C, as in PIC16C54. These devices have

EPROM program memory and operate over the

standard voltage range.

2. LC, as in PIC16LC54A. These devices have

EPROM program memory and operate over an

extended voltage range.

2.4

Serialized

Quick-Turnaround-Production

(SQTP^SM) Devices

3. LV, as in PIC16LV54A. These devices have

EPROM program memory and operate over a

2.0V to 3.8V range.

Microchip offers the unique programming service

where a few user-deﬁned locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or

sequential. The devices are identical to the OTP

devices but with all EPROM locations and

conﬁguration bit options already programmed by the

factory.

4. CR, as in PIC16CR54A. These devices have

ROM program memory and operate over the

standard voltage range.

5. LCR, as in PIC16LCR54B. These devices have

ROM program memory and operate over an

extended voltage range.

Serial programming allows each device to have a

unique number which can serve as an entry code,

password or ID number.

2.1

UV Erasable Devices (EPROM)

The UV erasable versions, offered in CERDIP

packages, are optimal for prototype development and

pilot programs

2.5

Read Only Memory (ROM) Devices

Microchip offers masked ROM versions of several of

the highest volume parts, giving the customer a low

cost option for high volume, mature products.

UV erasable devices can be programmed for any of

the four oscillator conﬁgurations. Microchip's

PICSTART and PRO MATE programmers both

support programming of the PIC16C5X. Third party

programmers also are available; refer to the Third

Party Guide for a list of sources.

2.2

One-Time-Programmable (OTP)

Devices

The availability of OTP devices is especially useful for

customers expecting frequent code changes and

updates.

The OTP devices, packaged in plastic packages,

permit the user to program them once. In addition to

the program memory, the conﬁguration bits must be

programmed.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 7

PIC16C5X

NOTES:

DS30453B-page 8

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

The PIC16C5X device contains an 8-bit ALU and

3.0

ARCHITECTURAL OVERVIEW

working register. The ALU is

a general purpose

The high performance of the PIC16C5X family can be

attributed to number of architectural features

arithmetic unit. It performs arithmetic and Boolean

functions between data in the working register and any

register ﬁle.

a

commonly found in RISC microprocessors. To begin

with, the PIC16C5X uses a Harvard architecture in

which program and data are accessed on separate

buses. This improves bandwidth over traditional von

Neumann architecture where program and data are

fetched on the same bus. Separating program and

data memory further allows instructions to be sized

differently than the 8-bit wide data word. Instruction

opcodes are 12-bits wide making it possible to have all

The ALU is 8-bits wide and capable of addition,

subtraction, shift and logical operations. Unless

otherwise mentioned, arithmetic operations are two's

complement in nature. In two-operand instructions,

typically one operand is the W (working) register. The

other operand is either a ﬁle register or an immediate

constant. In single operand instructions, the operand

is either the W register or a ﬁle register.

single word instructions.

A 12-bit wide program

memory access bus fetches a 12-bit instruction in a

single cycle. A two-stage pipeline overlaps fetch and

execution of instructions. Consequently, all instructions

(33) execute in a single cycle (200ns @ 20MHz)

except for program branches.

The W register is an 8-bit working register used for

ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC),

and Zero (Z) bits in the STATUS register. The C and

DC bits operate as a borrow and digit borrow out bit,

respectively, in subtraction. See the SUBWFand ADDWF

instructions for examples.

The PIC16C52 addresses 384

x 12 of program

memory, the PIC16C54s/CR54s and PIC16C55s

address 512 x 12 of program memory, the

PIC16C56s/CR56s address 1K

memory, and the PIC16C57s/CR57s

PIC16C58s/CR58s address 2K x 12 of program

memory. All program memory is internal.

X

12 of program

and

A simpliﬁed block diagram is shown in Figure 3-1, with

the corresponding device pins described in Table 3-1.

The PIC16C5X can directly or indirectly address its

register ﬁles and data memory. All special function

registers including the program counter are mapped in

the data memory. The PIC16C5X has

a highly

orthogonal (symmetrical) instruction set that makes it

possible to carry out any operation on any register

using any addressing mode. This symmetrical nature

and lack of ‘special optimal situations’ make

programming with the PIC16C5X simple yet efﬁcient.

In addition, the learning curve is reduced signiﬁcantly.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 9

PIC16C5X

FIGURE 3-1: PIC16C5X SERIES BLOCK DIAGRAM

9-11

T0CKI

OSC1 OSC2 MCLR

CONFIGURATION WORD

9-11

EPROM/ROM

384 X 12 TO

2048 X 12

STACK 1

STACK2

“DISABLE” “OSC

PC

SELECT”

WATCHDOG

TIMER

12

2

“CODE

OSCILLATOR/

TIMING &

CONTROL

PROTECT”

INSTRUCTION

REGISTER

WDT TIME

OUT

CLKOUT

WDT/TMR0

PRESCALER

9

12

8

“SLEEP”

INSTRUCTION

DECODER

6

“OPTION”

OPTION REG.

FROM W

DIRECT ADDRESS

DIRECT RAM

ADDRESS

GENERAL

PURPOSE

REGISTER

FILE

5

5-7

8

(SRAM)

24, 25, 72 or

73 Bytes

STATUS

TMR0

FSR

8

DATA BUS

8

W

ALU

FROM W

8

FROM W

4

FROM W

8

4

8

“TRIS 5”

“TRIS 6”

“TRIS 7”

TRISB PORTB

TRISA PORTA

TRISC

PORTC

8

4

8

RC7:RC0

(28-Pin

RA3:RA0

RB7:RB0

Devices Only)

DS30453B-page 10

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

TABLE 3-1:

Name

PINOUT DESCRIPTION - PIC16C52, PIC16C54s, PIC16CR54s, PIC16C56s,

PIC16CR56s, PIC16C58s, PIC16CR58s

DIP, SOIC SSOP I/O/P Input

Description

No.

No. Type Levels

RA0

RA1

RA2

RA3

17

18

1

19

20

1

I/O

TTL

Bi-directional I/O port

2

RB0

RB1

RB2

RB3

RB4

RB5

RB6

RB7

6

7

8

7

8

9

10

11

12

13

14

I/O

TTL

9

10

11

12

13

T0CKI

3

I

ST

Clock input to Timer0. Must be tied to VSS or VDD, if not in

use, to reduce current consumption.

MCLR/VPP

4

I

ST

Master clear (reset) input/programming voltage input. This

pin is an active low reset to the device. Voltage on the

MCLR/VPP pin must not exceed VDD to avoid unintended

entering of programming mode.

OSC1/CLKIN

16

15

18

17

I

ST

—

Oscillator crystal input/external clock source input.

OSC2/CLKOUT

O

Oscillator crystal output. Connects to crystal or resonator in

crystal oscillator mode. In RC mode, OSC2 pin outputs

CLKOUT which has 1/4 the frequency of OSC1, and denotes

the instruction cycle rate.

VDD

VSS

14

5

15,16

5,6

P

—

Positive supply for logic and I/O pins.

Ground reference for logic and I/O pins.

Legend: I = input, O = output, I/O = input/output,

P = power, — = Not Used, TTL = TTL input,

ST = Schmitt Trigger input

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 11

PIC16C5X

TABLE 3-2:

PINOUT DESCRIPTION - PIC16C55s, PIC16C57s, PIC16CR57s

DIP, SOIC SSOP I/O/P Input

Name

Description

No.

No. Type Levels

RA0

RA1

RA2

RA3

6

7

8

9

5

6

7

8

I/O

TTL Bi-directional I/O port

TTL

RB0

RB1

RB2

RB3

RB4

RB5

RB6

RB7

10

11

12

13

14

15

16

17

9

I/O

TTL Bi-directional I/O port

10

11

12

13

15

16

17

TTL

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

18

19

20

21

22

23

24

25

18

19

20

21

22

23

24

25

I/O

TTL Bi-directional I/O port

TTL

T0CKI

1

2

I

ST

Clock input to Timer0. Must be tied to V_{SS or VDD if not in use}

to reduce current consumption.

MCLR

28

I

ST

Master clear (reset) input.This pin is an active low reset to the

device.

OSC1/CLKIN

27

26

27

26

I

ST

—

Oscillator crystal input/external clock source input.

OSC2/CLKOUT

O

Oscillator crystal output. Connects to crystal or resonator in

crystal oscillator mode. In RC mode, OSC2 pin outputs

CLKOUT which has 1/4 the frequency of OSC1, and denotes

the instruction cycle rate.

VDD

VSS

N/C

2

4

3,4

1,14

—

P

—

Positive supply for logic and I/O pins.

Ground reference for logic and I/O pins.

Unused, do not connect

3,5

—

Legend: I = input, O = output, I/O = input/output,

P = power, — = Not Used,

TTL = TTL input, ST = Schmitt Trigger input

DS30453B-page 12

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

3.1

Clocking Scheme/Instruction Cycle

3.2

Instruction Flow/Pipelining

The clock input (OSC1/CLKIN pin) is internally divided

by four to generate four non-overlapping quadrature

clocks namely Q1, Q2, Q3 and Q4. Internally, the

program counter is incremented every Q1, and the

instruction is fetched from program memory and

latched into instruction register in Q4. It is decoded

and executed during the following Q1 through Q4. The

clocks and instruction execution ﬂow is shown in

Figure 3-2 and Example 3-1.

An Instruction Cycle consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO)

then two cycles are required to complete the

instruction (Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is

latched into the Instruction Register (IR) in cycle Q1.

This instruction is then decoded and executed during

the Q2, Q3, and Q4 cycles. Data memory is read

during Q2 (operand read) and written during Q4

(destination write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

Q2

Q3

Q4

Q2

Q3

Q4

Q2

Q3

Q4

Q1

OSC1

Q1

Q2

Q3

Q4

PC

Internal

phase

clock

PC

PC+1

PC+2

OSC2/CLKOUT

(RC mode)

Fetch INST (PC)

Execute INST (PC-1)

Fetch INST (PC+1)

Execute INST (PC)

Fetch INST (PC+2)

Execute INST (PC+1)

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 55H

Fetch 1

Execute 1

Fetch 2

2. MOVWF PORTB

3. CALL SUB_1

Execute 2

Fetch 3

Execute 3

Fetch 4

4. BSF

PORTA, BIT3

Flush

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch

instruction is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 13

PIC16C5X

NOTES:

DS30453B-page 14

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

FIGURE 4-2: PIC16C54s/CR54s/C55s

4.0

MEMORY ORGANIZATION

PROGRAM MEMORY MAP

AND STACK

PIC16C5X memory is organized into program memory

and data memory. For devices with more than 512

bytes of program memory, a paging scheme is used.

Program memory pages are accessed using one or

two STATUS register bits. For devices with a data

memory register ﬁle of more than 32 registers, a

banking scheme is used. Data memory banks are

accessed using the File Selection Register (FSR).

PC<8:0>

9

CALL, RETLW

Stack Level 1

Stack Level 2

000h

4.1

Program Memory Organization

On-chip

Program

Memory

0FFh

100h

The PIC16C52 has a 9-bit Program Counter (PC)

capable of addressing a 384 x 12 program memory

space (Figure 4-1). The PIC16C54s, PIC16CR54s and

PIC16C55s have a 9-bit Program Counter (PC)

capable of addressing a 512 x 12 program memory

space (Figure 4-2). The PIC16C56s and PIC16CR56s

have a 10-bit Program Counter (PC) capable of

addressing a 1K x 12 program memory space

(Figure 4-3). The PIC16CR57s, PIC16C58s and

PIC16CR58s have an 11-bit Program Counter capable

of addressing a 2K x 12 program memory space

(Figure 4-4). Accessing a location above the physically

implemented address will cause a wraparound.

Reset Vector

1FFh

FIGURE 4-3: PIC16C56s/CR56s

PROGRAM MEMORY MAP

AND STACK

PC<9:0>

10

CALL, RETLW

The reset vector for the PIC16C52 is at 17Fh. A NOP

at the reset vector location will cause a restart at

location 000h. The reset vector for the PIC16C54s,

PIC16CR54s and PIC16C55s is at 1FFh. The reset

vector for the PIC16C56s and PIC16CR56s is at

3FFh. The reset vector for the PIC16C57s,

PIC16CR57s, PIC16C58s, and PIC16CR58s is at

7FFh.

Stack Level 1

Stack Level 2

000h

On-chip Program

Memory (Page 0)

0FFh

100h

1FFh

200h

On-chip Program

Memory (Page 1)

2FFh

300h

FIGURE 4-1: PIC16C52 PROGRAM

MEMORY MAP AND STACK

PC<8:0>

Reset Vector

3FFh

9

CALL, RETLW

Stack Level 1

Stack Level 2

000h

On-chip Program

Memory

Reset Vector

17Fh

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 15

PIC16C5X

FIGURE 4-4: PIC16C57s/CR57s/C58s/

CR58s PROGRAM MEMORY

MAP AND STACK

PC<10:0>

11

CALL, RETLW

Stack Level 1

Stack Level 2

000h

On-chip Program

0FFh

Memory (Page 0)

100h

1FFh

200h

On-chip Program

2FFh

Memory (Page 1)

300h

3FFh

400h

On-chip Program

4FFh

Memory (Page 2)

500h

5FFh

600h

On-chip Program

6FFh

Memory (Page 3)

700h

Reset Vector

7FFh

DS30453B-page 16

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

4.2

Data Memory Organization

FIGURE 4-5: PIC16C52, PIC16C54s,

PIC16CR54s, PIC16C55s,

PIC16C56s, PIC16CR56s

REGISTER FILE MAP

Data memory is composed of registers, or bytes of

RAM. Therefore, data memory for a device is speciﬁed

by its register ﬁle. The register ﬁle is divided into two

functional groups: special function registers and

general purpose registers.

File Address

INDF⁽¹⁾

TMR0

PCL

00h

01h

02h

03h

04h

05h

06h

07h

The special function registers include the TMR0

register, the Program Counter (PC), the Status

Register, the I/O registers (ports), and the File Select

Register (FSR). In addition, special purpose registers

are used to control the I/O port conﬁguration and

prescaler options.

STATUS

FSR

PORTA

PORTB

The general purpose registers are used for data and

control information under command of the instructions.

PORTC⁽²⁾

For the PIC16C52, PIC16C54s, PIC16CR54s,

PIC16C56s and PIC16CR56s, the register ﬁle is

composed of 7 special function registers and 25

general purpose registers (Figure 4-5).

General

Purpose

Registers

0Fh

10h

For the PIC16C55s, the register ﬁle is composed of 8

special function registers and 24 general purpose

registers.

For the PIC16C57s and PIC16CR57s, the register ﬁle

is composed of 8 special function registers, 24 general

purpose registers and up to 48 additional general

purpose registers that may be addressed using a

banking scheme (Figure 4-6).

1Fh

Note 1: Not a physical register. See Section 4.7

2: PIC16C55s only, others are a general

purpose register.

For the PIC16C58s and PIC16CR58s, the register ﬁle

is composed of 7 special function registers, 25 general

purpose registers and up to 48 additional general

purpose registers that may be addressed using a

banking scheme (Figure 4-7).

4.2.1

GENERAL PURPOSE REGISTER FILE

The register ﬁle is accessed either directly or indirectly

through the ﬁle select register FSR (Section 4.7).

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 17

PIC16C5X

FIGURE 4-6: PIC16C57s/CR57s REGISTER FILE MAP

FSR<6:5>

File Address

00h

00

01

10

11

INDF⁽¹⁾

TMR0

PCL

20h

40h

60h

01h

02h

03h

04h

05h

06h

STATUS

FSR

Addresses map back to

addresses in Bank 0.

PORTA

PORTB

07h

08h

PORTC

General

Purpose

Registers

2Fh

30h

4Fh

50h

6Fh

0Fh

10h

1Fh

70h

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

3Fh

5Fh

7Fh

Bank 0

Bank 1

Bank 2

Bank 3

Note 1: Not a physical register. See Section 4.7

FIGURE 4-7: PIC16C58s/CR58s REGISTER FILE MAP

FSR<6:5>

File Address

00h

00

01

10

11

INDF⁽¹⁾

TMR0

PCL

20h

40h

60h

01h

02h

03h

04h

05h

STATUS

FSR

Addresses map back to

addresses in Bank 0.

PORTA

PORTB

06h

07h

General

Purpose

Registers

2Fh

30h

4Fh

50h

6Fh

0Fh

10h

1Fh

70h

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

3Fh

5Fh

7Fh

Bank 0

Bank 1

Bank 2

Bank 3

Note 1: Not a physical register. See Section 4.7

DS30453B-page 18

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

4.2.2

SPECIAL FUNCTION REGISTERS

The special registers can be classiﬁed into two sets.

The special function registers associated with the

“core” functions are described in this section. Those

related to the operation of the peripheral features are

described in the section for each peripheral feature.

The Special Function Registers are registers used by

the CPU and peripheral functions to control the

operation of the device (Table 4-1).

TABLE 4-1:

SPECIAL FUNCTION REGISTER SUMMARY

Value on

Power-On

Reset

Value on

MCLR and

WDT Reset

Address

Name

TRIS

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

N/A

00h

01h

I/O control registers (TRISA, TRISB, TRISC)

1111 1111 1111 1111

--11 1111 --11 1111

xxxx xxxx uuuu uuuu

OPTION

INDF

Contains control bits to conﬁgure Timer0 and Timer0/WDT prescaler

Uses contents of FSR to address data memory (not a physical register)

8-bit real-time clock/counter

TMR0

(1)

02h

PCL

Low order 8 bits of PC

1111 1111 1111 1111

0001 1xxx 000q quuu

1xxx xxxx 1uuu uuuu

---- xxxx ---- uuuu

xxxx xxxx uuuu uuuu

03h

04h

05h

06h

STATUS

FSR

PA2

PA1

PA0

TO

PD

Z

DC

C

Indirect data memory address pointer

PORTA

PORTB

—

RA3

RB3

RA2

RB2

RA1

RB1

RA0

RB0

RB7

RB6

RB5

RB4

(2)

07h

PORTC

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

xxxx xxxx uuuu uuuu

Legend: Shaded boxes = unimplemented or unused, –= unimplemented, read as '0' (if applicable)

x= unknown, u= unchanged, q= see the tables in Section 7.7 for possible values.

Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.5

for an explanation of how to access these bits.

2: File address 07h is a general purpose register on the PIC16C52, PIC16C54s, PIC16CR54s, PIC16C56s, PIC16CR56s,

PIC16C58s and PIC16CR58s.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 19

PIC16C5X

not writable. Therefore, the result of an instruction with

the STATUS register as destination may be different

than intended.

4.3

STATUS Register

This register contains the arithmetic status of the ALU,

the RESET status, and the page preselect bits for

program memories larger than 512 words.

For example, CLRF STATUSwill clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu(where u= unchanged).

The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to

the device logic. Furthermore, the TO and PD bits are

It is recommended, therefore, that only BCF, BSFand

MOVWFinstructions be used to alter the STATUS

register because these instructions do not affect the Z,

DC or C bits from the STATUS register. For other

instructions, which do affect STATUS bits, see

Section 8.0, Instruction Set Summary.

FIGURE 4-8: STATUS REGISTER (ADDRESS:03h)

R/W-0

PA2

R/W-0

PA1

R/W-0

PA0

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC

R/W-x

C

R = Readable bit

W = Writable bit

- n = Value at POR reset

bit7

6

5

4

3

2

1

bit0

bit 7:

PA2: This bit unused at this time.

Use of the PA2 bit as a general purpose read/write bit is not recommended, since this may affect upward

compatibility with future products.

bit 6-5: PA1:PA0: Program page preselect bits (PIC16C56s/CR56s)(PIC16C57s/CR57s)(PIC16C58s/CR58s)

00 = Page 0 (000h - 1FFh) - PIC16C56s/CR56s, PIC16C57s/CR57s, PIC16C58s/CR58s

01 = Page 1 (200h - 3FFh) - PIC16C56s/CR56s, PIC16C57s/CR57s, PIC16C58s/CR58s

10 = Page 2 (400h - 5FFh) - PIC16C57s/CR57s, PIC16C58s/CR58s

11 = Page 3 (600h - 7FFh) - PIC16C57s/CR57s, PIC16C58s/CR58s

Each page is 512 words.

Using the PA1:PA0 bits as general purpose read/write bits in devices which do not use them for program

page preselect is not recommended since this may affect upward compatibility with future products.

bit 4:

bit 3:

bit 2:

bit 1:

TO: Time-out bit

1 = After power-up, CLRWDTinstruction, or SLEEPinstruction

0 = A WDT time-out occurred

PD: Power-down bit

1 = After power-up or by the CLRWDTinstruction

0 = By execution of the SLEEPinstruction

Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

DC: Digit carry/borrow bit (for ADDWFand SUBWFinstructions)

ADDWF

1 = A carry from the 4th low order bit of the result occurred

0 = A carry from the 4th low order bit of the result did not occur

SUBWF

1 = A borrow from the 4th low order bit of the result did not occur

0 = A borrow from the 4th low order bit of the result occurred

bit 0:

C: Carry/borrow bit (for ADDWF, SUBWFand RRF, RLFinstructions)

ADDWF

SUBWF

RRF or RLF

1 = A carry occurred

0 = A carry did not occur

1 = A borrow did not occur

0 = A borrow occurred

Load bit with LSb or MSb, respectively

DS30453B-page 20

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

By executing the OPTIONinstruction, the contents of

the W register will be transferred to the OPTION

register. A RESET sets the OPTION<5:0> bits.

4.4

OPTION Register

The OPTION register is a 6-bit wide, write-only

register which contains various control bits to

conﬁgure the Timer0/WDT prescaler and Timer0.

FIGURE 4-9: OPTION REGISTER

U-0

—

U-0

—

6

W-1

T0CS

5

W-1

T0SE

4

W-1

PSA

3

W-1

PS2

2

W-1

PS1

1

W-1

PS0

W

U

= Writable bit

= Unimplemented bit

bit7

bit0

- n = Value at POR reset

bit 7-6: Unimplemented.

bit 5:

bit 4:

bit 3:

T0CS: Timer0 clock source select bit

1 = Transition on T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

T0SE: Timer0 source edge select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

PSA: Prescaler assignment bit

1 = Prescaler assigned to the WDT (not implemented on PIC16C52)

0 = Prescaler assigned to Timer0

bit 2-0: PS2:PS0: Prescaler rate select bits

Bit Value

Timer0 Rate WDT Rate (not implemented on PIC16C52)

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 21

PIC16C5X

4.5

Program Counter

FIGURE 4-10: LOADING OF PC

BRANCH INSTRUCTIONS -

As a program instruction is executed, the Program

Counter (PC) will contain the address of the next

program instruction to be executed. The PC value is

increased by one every instruction cycle, unless an

instruction changes the PC.

PIC16C52, PIC16C54s,

PIC16CR54s, PIC16C55s

GOTO Instruction

8

7

0

For a GOTOinstruction, bits 8:0 of the PC are provided

by the GOTOinstruction word. The PC Latch (PCL) is

mapped to PC<7:0> (Figure 4-10 and Figure 4-11).

PCL

PC

Instruction Word

For the PIC16C56s, PIC16CR56s, PIC16C57s,

PIC16CR57s, PIC16C58s and PIC16CR58s, a page

number must be supplied as well. Bit5 and bit6 of the

STATUS register provide page information to bit9 and

bit10 of the PC (Figure 4-11 and Figure 4-12).

CALL or Modify PCL Instruction

8

7

0

PCL

PC

For a CALLinstruction, or any instruction where the

PCL is the destination, bits 7:0 of the PC again are

provided by the instruction word. However, PC<8>

does not come from the instruction word, but is always

cleared (Figure 4-10 and Figure 4-11).

Reset to '0'

Instruction Word

FIGURE 4-11: LOADING OF PC

BRANCH INSTRUCTIONS -

PIC16C56s/PIC16CR56s

Instructions where the PCL is the destination, or

Modify PCL instructions, include MOVWF PC, ADDWF

PC,and BSF PC,5.

GOTO Instruction

For the PIC16C56s, PIC16CR56s, PIC16C57s,

PIC16CR57s, PIC16C58s and PIC16CR58s, a page

number again must be supplied. Bit5 and bit6 of the

STATUS register provide page information to bit9 and

bit10 of the PC (Figure 4-11 and Figure 4-12).

10

9

8

7

0

PC

PCL

Instruction Word

Note: Because PC<8> is cleared in the CALL

instruction, or any Modify PCL instruction,

all subroutine calls or computed jumps are

limited to the ﬁrst 256 locations of any pro-

gram memory page (512 words long).

2

PA1:PA0

7

0

STATUS

CALL or Modify PCL Instruction

10

9

8

7

0

PC

PCL

Instruction Word

Reset to ‘0’

PA1:PA0

2

7

0

STATUS

DS30453B-page 22

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

4.5.1

PAGING CONSIDERATIONS –

PIC16C56s/CR56s, PIC16C57s/CR57sAND

PIC16C58s/CR58s

FIGURE 4-12: LOADING OF PC

BRANCH INSTRUCTIONS -

PIC16C57s/PIC16CR57s, AND

PIC16C58s/PIC16CR58s

If the Program Counter is pointing to the last address

of a selected memory page, when it increments it will

cause the program to continue in the next higher page.

However, the page preselect bits in the STATUS

register will not be updated. Therefore, the next GOTO,

CALL, or Modify PCL instruction will send the program

to the page speciﬁed by the page preselect bits (PA0

or PA1:PA0).

GOTO Instruction

10

9

8

7

0

PC

PCL

Instruction Word

2

PA1:PA0

7

0

For example, a NOP at location 1FFh (page 0)

increments the PC to 200h (page 1). A GOTO xxxat

200h will return the program to address 0xxh on page

0 (assuming that PA1:PA0 are clear).

STATUS

To prevent this, the page preselect bits must be

updated under program control.

CALL or Modify PCL Instruction

10

9

8

7

0

PC

PCL

4.5.2

EFFECTS OF RESET

The Program Counter is set upon a RESET, which

means that the PC addresses the last location in the

last page i.e., the reset vector.

Instruction Word

Reset to ‘0’

PA1:PA0

The STATUS register page preselect bits are cleared

upon a RESET, which means that page 0 is

pre-selected.

2

7

0

STATUS

Therefore, upon a RESET, a GOTOinstruction at the

reset vector location will automatically cause the

program to jump to page 0.

4.6

Stack

PIC16C5X devices have a 9-bit, 10-bit or 11-bit wide,

two-level hardware push/pop stack (Figure 4-2,

Figure 4-1, and Figure 4-3 respectively).

A CALLinstruction will push the current value of stack

1 into stack 2 and then push the current program

counter value, incremented by one, into stack level 1. If

more than two sequential CALL’s are executed, only

the most recent two return addresses are stored.

A RETLWinstruction will pop the contents of stack level

1 into the program counter and then copy stack level 2

contents into level 1. If more than two sequential

RETLW’s are executed, the stack will be filled with the

address previously stored in level 2. Note that the

W register will be loaded with the literal value speciﬁed

in the instruction. This is particularly useful for the

implementation of data look-up tables within the

program memory.

For the RETLWinstruction, the PC is loaded with the

Top Of Stack (TOS) contents. All of the devices

covered in this data sheet have a two-level stack. The

stack has the same bit width as the device PC.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 23

PIC16C5X

4.7

Indirect Data Addressing; INDF and

FSR Registers

EXAMPLE 4-2: HOW TO CLEAR RAM

USING INDIRECT

ADDRESSING

The INDF register is not a physical register.

Addressing INDF actually addresses the register

whose address is contained in the FSR register (FSR

is a pointer). This is indirect addressing.

movlw 0x10

;initialize pointer

movwf FSR

; to RAM

incf

INDF

;clear INDF register

FSR,F ;inc pointer

btfsc FSR,4 ;all done?

goto

EXAMPLE 4-1: INDIRECT ADDRESSING

• Register ﬁle 05 contains the value 10h

• Register ﬁle 06 contains the value 0Ah

• Load the value 05 into the FSR register

• A read of the INDF register will return the value

of 10h

• Increment the value of the FSR register by one

(FSR = 06h)

• A read of the INDR register now will return the

value of 0Ah.

CONTINUE

:

;YES, continue

The FSR is either a 5-bit (PIC16C52, PIC16C54s,

PIC16CR54s, PIC16C55s), 6-bit (PIC16C56s,

PIC16CR56s), or 7-bit (PIC16C57s, PIC16CR57s,

PIC16C58s, PIC16CR58s) wide register. It is used in

conjunction with the INDF register to indirectly address

the data memory area.

The FSR<4:0> bits are used to select data memory

addresses 00h to 1Fh.

Reading INDF itself indirectly (FSR = 0) will produce

00h. Writing to the INDF register indirectly results in a

no-operation (although STATUS bits may be affected).

PIC16C52, PIC16C54s, PIC16CR54s, PIC16C55s:

These do not use banking. FSR<6:5> are

unimplemented and read as '1's.

A simple program to clear RAM locations 10h-1Fh

using indirect addressing is shown in Example 4-2.

PIC16C57s,

PIC16CR57s,

PIC16C58s,

PIC16CR58s: FSR<6:5> are the bank select bits and

are used to select the bank to be addressed (00=

bank 0, 01= bank 1, 10= bank 2, 11= bank 3).

FIGURE 4-13: DIRECT/INDIRECT ADDRESSING

Direct Addressing

Indirect Addressing

(FSR)

4

(opcode)

0

5

(FSR)

0

6

4

5

6

location select

bank select

location select

bank

00

01

10

11

00h

Addresses map back

to addresses in Bank 0.

Data

Memory

0Fh

10h

(1)

1Fh

Bank 0

3Fh

Bank 1

5Fh

Bank 2

7Fh

Bank 3

Note 1: For register map detail see Section 4.2.

DS30453B-page 24

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

5.5

I/O Interfacing

5.0

I/O PORTS

As with any other register, the I/O registers can be

written and read under program control. However, read

instructions (e.g., MOVF PORTB,W) always read the I/O

pins independent of the pin’s input/output modes. On

RESET, all I/O ports are deﬁned as input (inputs are at

hi-impedance) since the I/O control registers (TRISA,

TRISB, TRISC) are all set.

The equivalent circuit for an I/O port pin is shown in

Figure 5-1. All ports may be used for both input and

output operation. For input operations these ports are

non-latching. Any input must be present until read by

an input instruction (e.g., MOVF PORTB, W). The

outputs are latched and remain unchanged until the

output latch is rewritten. To use a port pin as output,

the corresponding direction control bit (in TRISA,

TRISB) must be cleared (= 0). For use as an input, the

corresponding TRIS bit must be set. Any I/O pin can

be programmed individually as input or output.

5.1

PORTA

PORTA is a 4-bit I/O register. Only the low order 4 bits

are used (RA3:RA0). Bits 7-4 are unimplemented and

read as '0's.

FIGURE 5-1: EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

5.2

PORTB

Data

Bus

PORTB is an 8-bit I/O register (PORTB<7:0>).

D

Q

Data

Latch

5.3

PORTC

VDD

P

WR

Port

CK

PORTC is an 8-bit I/O register for PIC16C55s,

PIC16C57s and PIC16CR57s.

PORTC is a general purpose register for PIC16C52,

PIC16C54s, PIC16CR54s, PIC16C56s, PIC16C58s

and PIC16CR58s.

N

I/O

pin⁽¹⁾

W

Reg

D

Q

TRIS

Latch

VSS

5.4

TRIS Registers

TRIS ‘f’

CK

The output driver control registers are loaded with the

contents of the W register by executing the TRIS f

instruction. A '1' from a TRIS register bit puts the

corresponding output driver in a hi-impedance mode.

A '0' puts the contents of the output data latch on the

selected pins, enabling the output buffer.

Reset

Note:

A read of the ports reads the pins, not the

output data latches. That is, if an output

driver on a pin is enabled and driven high,

but the external system is holding it low, a

read of the port will indicate that the pin is

low.

RD Port

Note 1: I/O pins have protection diodes to VDD and VSS.

The TRIS registers are “write-only” and are set (output

drivers disabled) upon RESET.

TABLE 5-1:

SUMMARY OF PORT REGISTERS

Value on

Power-On

Reset

Value on

MCLR and

WDT Reset

Address

Name

TRIS

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

N/A

05h

06h

07h

I/O control registers (TRISA, TRISB, TRISC)

1111 1111 1111 1111

---- xxxx ---- uuuu

xxxx xxxx uuuu uuuu

PORTA

PORTB

PORTC

—

RA3

RB3

RC3

RA2

RB2

RC2

RA1

RB1

RC1

RA0

RB0

RC0

RB7

RC7

RB6

RC6

RB5

RC5

RB4

RC4

Legend: Shaded boxes = unimplemented, read as ‘0’,

–= unimplemented, read as '0', x= unknown, u= unchanged

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 25

PIC16C5X

5.6

I/O Programming Considerations

BI-DIRECTIONAL I/O PORTS

EXAMPLE 5-1: READ-MODIFY-WRITE

INSTRUCTIONS ON AN

I/O PORT

;Initial PORT Settings

; PORTB<7:4> Inputs

5.6.1

Some instructions operate internally as read followed

by write operations. The BCFand BSFinstructions, for

example, read the entire port into the CPU, execute

the bit operation and re-write the result. Caution must

be used when these instructions are applied to a port

where one or more pins are used as input/outputs. For

example, a BSFoperation on bit5 of PORTB will cause

all eight bits of PORTB to be read into the CPU, bit5 to

be set and the PORTB value to be written to the output

; PORTB<3:0> Outputs

;PORTB<7:6> have external pull-ups and are

;not connected to other circuitry

;

PORT latch PORT pins

---------- ----------

BCF

MOVLW 03Fh

TRIS PORTB

PORTB, 7

PORTB, 6

;01pp pppp

;10pp pppp

;

11pp pppp

latches. If another bit of PORTB is used as

a

;10pp pppp

10pp pppp

bi-directional I/O pin (say bit0) and it is deﬁned as an

input at this time, the input signal present on the pin

itself would be read into the CPU and rewritten to the

data latch of this particular pin, overwriting the

previous content. As long as the pin stays in the input

mode, no problem occurs. However, if bit0 is switched

into output mode later on, the content of the data latch

may now be unknown.

;

;Note that the user may have expected the pin

;values to be 00pp pppp. The 2nd BCF caused

;RB7 to be latched as the pin value (High).

5.6.2

SUCCESSIVE OPERATIONS ON I/O

PORTS

The actual write to an I/O port happens at the end of

an instruction cycle, whereas for reading, the data

must be valid at the beginning of the instruction cycle

(Figure 5-2). Therefore, care must be exercised if a

write followed by a read operation is carried out on the

same I/O port. The sequence of instructions should

allow the pin voltage to stabilize (load dependent)

before the next instruction, which causes that ﬁle to be

read into the CPU, is executed. Otherwise, the

previous state of that pin may be read into the CPU

rather than the new state. When in doubt, it is better to

separate these instructions with a NOP or another

instruction not accessing this I/O port.

Example 5-1 shows the effect of two sequential

read-modify-write instructions (e.g., BCF, BSF, etc.) on

an I/O port.

A pin actively outputting a high or a low should not be

driven from external devices at the same time in order

to change the level on this pin (“wired-or”, “wired-and”).

The resulting high output currents may damage the

chip.

FIGURE 5-2: SUCCESSIVE I/O OPERATION

Q4

Q1 Q2

Q4

Q3

Q1 Q2

PC

Q1 Q2

PC + 3

NOP

PC + 1

PC + 2

NOP

Instruction

fetched

MOVWF PORTB MOVF PORTB,W

This example shows a write

to PORTB followed by a read

from PORTB.

RB7:RB0

Port pin

written here

Port pin

sampled here

Instruction

executed

MOVWF PORTB MOVF PORTB,W

NOP

(Write to

PORTB)

(Read

PORTB)

DS30453B-page 26

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

Counter mode is selected by setting the T0CS bit

(OPTION<5>). In this mode, Timer0 will increment

either on every rising or falling edge of pin T0CKI. The

incrementing edge is determined by the source edge

select bit T0SE (OPTION<4>). Clearing the T0SE bit

selects the rising edge. Restrictions on the external

clock input are discussed in detail in Section 6.1.

6.0

TIMER0 MODULE AND

TMR0 REGISTER

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

- Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

- Edge select for external clock

The prescaler may be used by either the Timer0

module or the Watchdog Timer, but not both. The

prescaler assignment is controlled in software by the

control bit PSA (OPTION<3>). Clearing the PSA bit

will assign the prescaler to Timer0. The prescaler is

not readable or writable. When the prescaler is

assigned to the Timer0 module, prescale values of 1:2,

1:4,..., 1:256 are selectable. Section 6.2 details the

operation of the prescaler.

Figure 6-1 is a simpliﬁed block diagram of the Timer0

module, while Figure 6-2 shows the electrical structure

of the Timer0 input.

Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In timer mode, the Timer0 module will

increment every instruction cycle (without prescaler). If

TMR0 register is written, the increment is inhibited for

the following two cycles (Figure 6-3 and Figure 6-4).

The user can work around this by writing an adjusted

value to the TMR0 register.

A summary of registers associated with the Timer0

module is found in Table 6-1.

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

Data bus

FOSC/4

0

1

PSout

8

1

0

Sync with

Internal

Clocks

TMR0 reg

T0CKI

Programmable

PSout

Sync

(2)

Prescaler

(1)

(2 cycle delay)

T0SE

3

(1)

PS2, PS1, PS0

PSA

(1)

T0CS

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer (Figure 6-6).

FIGURE 6-2: ELECTRICAL STRUCTURE OF T0CKI PIN

RIN

T0CKI

(1)

Schmitt Trigger

Input Buffer

N

(1)

VSS

Note 1: ESD protection circuits

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 27

PIC16C5X

FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

(Program

Counter)

PC-1

PC

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

Instruction

Fetch

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

MOVWF TMR0

T0

T0+1

T0+2

NT0

NT0+1

NT0+2

Timer0

Instruction

Executed

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 2

Write TMR0

executed

FIGURE 6-4: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

(Program

Counter)

PC-1

PC

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

MOVWF TMR0

Instruction

Fetch

T0

T0+1

NT0+1

T0

NT0

Timer0

Instruction

Execute

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 1

Write TMR0

executed

TABLE 6-1:

Address

REGISTERS ASSOCIATED WITH TIMER0

Value on

Power-On

Reset

Value on

MCLR and

WDT Reset

Name

Bit 7

Timer0 - 8-bit real-time clock/counter

T0CS T0SE PSA

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

01h

N/A

TMR0

xxxx xxxx uuuu uuuu

OPTION

—

PS2

PS1

PS0 --11 1111 --11 1111

Legend: Shaded cells: Unimplemented bits,

-= unimplemented, x = unknown, u= unchanged,

DS30453B-page 28

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

When a prescaler is used, the external clock input is

divided by the asynchronous ripple counter-type

prescaler so that the prescaler output is symmetrical.

For the external clock to meet the sampling

requirement, the ripple counter must be taken into

account. Therefore, it is necessary for T0CKI to have a

period of at least 4TOSC (and a small RC delay of

40 ns) divided by the prescaler value. The only

requirement on T0CKI high and low time is that they

do not violate the minimum pulse width requirement of

10 ns. Refer to parameters 40, 41 and 42 in the

electrical speciﬁcation of the desired device.

6.1

Using Timer0 with an External Clock

When an external clock input is used for Timer0, it

must meet certain requirements. The external clock

requirement is due to internal phase clock (TOSC)

synchronization. Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

6.1.1

EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is

accomplished by sampling the prescaler output on the

Q2 and Q4 cycles of the internal phase clocks

(Figure 6-5). Therefore, it is necessary for T0CKI to be

high for at least 2TOSC (and a small RC delay of 20 ns)

and low for at least 2TOSC (and a small RC delay of

20 ns). Refer to the electrical speciﬁcation of the

desired device.

6.1.2

TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0

module is actually incremented. Figure 6-5 shows the

delay from the external clock edge to the timer

incrementing.

FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Small pulse

External Clock Input or

misses sampling

Prescaler Output (2)

(1)

External Clock/Prescaler

Output After Sampling

(3)

Increment Timer0 (Q4)

Timer0

T0

T0 + 1

T0 + 2

Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).

Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.

2: External clock if no prescaler selected, Prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 29

PIC16C5X

following instruction sequence (Example 6-1) must be

executed when changing the prescaler assignment from

Timer0 to the WDT.

6.2

Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer (WDT) (WDT postscaler not implemented on

PIC16C52), respectively (Section 6.1.2). For simplicity,

this counter is being referred to as “prescaler”

throughout this data sheet. Note that the prescaler

may be used by either the Timer0 module or the WDT,

but not both. Thus, a prescaler assignment for the

Timer0 module means that there is no prescaler for

the WDT, and vice-versa.

EXAMPLE 6-1: CHANGING PRESCALER

(TIMER0→WDT)

1.CLRWDT

2.CLRF

;Clear WDT

TMR0

;Clear TMR0 & Prescaler

3.MOVLW '00xx1111’b ;These 3 lines (5, 6, 7)

4.OPTION

; are required only if

; desired

5.CLRWDT

;PS<2:0> are 000 or 001

6.MOVLW '00xx1xxx’b ;Set Postscaler to

7.OPTION ; desired WDT rate

The PSA and PS2:PS0 bits (OPTION<3:0>) determine

prescaler assignment and prescale ratio.

To change prescaler from the WDT to the Timer0

module, use the sequence shown in Example 6-2. This

sequence must be used even if the WDT is disabled. A

CLRWDTinstruction should be executed before switching

the prescaler.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,

BSF 1,x,etc.) will clear the prescaler. When assigned

to WDT, a CLRWDT instruction will clear the prescaler

along with the WDT. The prescaler is neither readable

nor writable. On a RESET, the prescaler contains all

'0's.

EXAMPLE 6-2: CHANGING PRESCALER

(WDT→TIMER0)

CLRWDT

;Clear WDT and

6.2.1

SWITCHING PRESCALER ASSIGNMENT

;prescaler

MOVLW 'xxxx0xxx'

;Select TMR0, new

;prescale value and

;clock source

The prescaler assignment is fully under software control

(i.e., it can be changed “on the ﬂy” during program

execution). To avoid an unintended device RESET, the

OPTION

FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

TCY ( = Fosc/4)

Data Bus

8

0

M

U

X

1

M

U

X

T0CKI

1

Sync

2

Cycles

TMR0 reg

0

T0SE

T0CS

PSA

0

1

8-bit Prescaler

M

U

X

8

Watchdog

Timer

8 - to - 1MUX

PS2:PS0

PSA

1

0

WDT Enable bit

MUX

PSA

WDT

Time-Out

Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.

WDT not implemented on PIC16C52.

DS30453B-page 30

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

The SLEEP mode is designed to offer a very low

current power-down mode. The user can wake up from

SLEEP through external reset or through a Watchdog

Timer time-out. Several oscillator options are also

made available to allow the part to ﬁt the application.

The RC oscillator option saves system cost while the

LP crystal option saves power. A set of conﬁguration

bits are used to select various options.

7.0

SPECIAL FEATURES OF THE

CPU

What sets

a

microcontroller apart from other

processors are special circuits that deal with the

needs of real-time applications. The PIC16C5X family

of microcontrollers has

intended to maximize system reliability, minimize cost

through elimination of external components, provide

power saving operating modes and offer code

protection. These features are:

a host of such features

7.1

Conﬁguration Bits

Conﬁguration bits can be programmed to select

various device conﬁgurations. Two bits are for the

selection of the oscillator type and one bit is the

Watchdog Timer enable bit. Nine bits are code

protection bits (Figure 7-1 and Figure 7-2) for the

PIC16C54, PIC16CR54, PIC16C56, PIC16CR56,

PIC16C58, and PIC16CR58 devices.

• Oscillator selection

• Reset

• Power-On Reset (POR)

• Device Reset Timer (DRT)

• Watchdog Timer (WDT)

(not implemented on PIC16C52)

QTP or ROM devices have the oscillator conﬁguration

programmed at the factory and these parts are tested

accordingly (see "Product Identiﬁcation System"

diagrams in the back of this data sheet).

• SLEEP

• Code protection

• ID locations (not implemented on PIC16C52)

The PIC16C5X Family has a Watchdog Timer which

can be shut off only through conﬁguration bit WDTE. It

runs off of its own RC oscillator for added reliability.

There is an 18 ms delay provided by the Device Reset

Timer (DRT), intended to keep the chip in reset until

the crystal oscillator is stable. With this timer on-chip,

most applications need no external reset circuitry.

FIGURE 7-1: CONFIGURATION WORD FOR

PIC16CR54A/C54B/CR54B/C54C/CR54C/C55A/C56A/CR56A/C57C/

CR57B/CR57C/C58B/CR58A/CR58B

CP

10

CP

9

CP

8

CP

7

CP

6

CP

5

CP

4

CP

3

WDTE FOSC1 FOSC0

bit0

Register: CONFIG

(1)

Address

:

FFFh

bit11

2

1

bit 11-3: CP: Code protection bits

1 = Code protection off

0 = Code protection on

bit 2:

WDTE: Watchdog timer enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator selection bits

11 = RC oscillator

10 = HS oscillator

01 = XT oscillator

00 = LP oscillator

Note 1: Refer to the PIC16C5X Programming Speciﬁcation (Literature Number DS30190) to deter-

mine how to access the conﬁguration word.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 31

PIC16C5X

FIGURE 7-2: CONFIGURATION WORD FOR PIC16C52/C54/C54A/C55/C56/C57/C58A

—

9

—

8

—

7

—

6

—

5

—

4

CP

3

WDTE FOSC1 FOSC0

bit0

Register: CONFIG

(1)

Address

:

FFFh

bit11

10

2

1

bit 11-4: Unimplemented: Read as ’0’

bit 3:

CP: Code protection bit.

1 = Code protection off

0 = Code protection on

bit 2:

WDTE: Watchdog timer enable bit (not implemented on PIC16C52)

1 = WDT enabled

0 = WDT disabled

(2)

bit 1-0: FOSC1:FOSC0: Oscillator selection bits

11 = RC oscillator

10 = HS oscillator

01 = XT oscillator

00 = LP oscillator

Note 1: Refer to the PIC16C5X Programming Speciﬁcations (Literature Number DS30190) to deter-

mine how to access the conﬁguration word.

2: PIC16C52 supports XT and RC oscillator only.

PIC16LV54A supports XT, RC and LP oscillator only.

PIC16LV58A supports XT, RC and LP oscillator only.

DS30453B-page 32

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

7.2

Oscillator Conﬁgurations

FIGURE 7-4: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP

7.2.1

OSCILLATOR TYPES

OSC CONFIGURATION)

PIC16C5Xs can be operated in four different oscillator

modes. The user can program two conﬁguration bits

(FOSC1:FOSC0) to select one of these four modes:

OSC1

OSC2

Clock from

ext. system

PIC16C5X

• LP:

• XT:

• HS:

• RC:

Low Power Crystal

Open

Crystal/Resonator

High Speed Crystal/Resonator

Resistor/Capacitor

TABLE 7-1:

CAPACITOR SELECTION

FOR CERAMIC RESONATORS

- PIC16C5X, PIC16CR5X

Note: Not all oscillator selections available for all

parts. See Section 7.1.

Osc

Type

Resonator Cap. Range Cap. Range

7.2.2

CRYSTAL OSCILLATOR / CERAMIC

RESONATORS

Freq

C1

C2

XT

455 kHz

2.0 MHz

4.0 MHz

22-100 pF

15-68 pF

22-100 pF

15-68 pF

In XT, LP or HS modes, a crystal or ceramic resonator

is connected to the OSC1/CLKIN and OSC2/CLKOUT

pins to establish oscillation (Figure 7-3). The

PIC16C5X oscillator design requires the use of a

parallel cut crystal. Use of a series cut crystal may give

HS

4.0 MHz

8.0 MHz

16.0 MHz

15-68 pF

10-68 pF

10-22 pF

15-68 pF

10-68 pF

10-22 pF

a

frequency out of the crystal manufacturers

Note: These values are for design guidance only.

Since each resonator has its own charac-

teristics, the user should consult the reso-

nator manufacturer for appropriate values

of external components.

speciﬁcations. When in XT, LP or HS modes, the

device can have an external clock source drive the

OSC1/CLKIN pin (Figure 7-4).

FIGURE 7-3: CRYSTAL OPERATION

(OR CERAMIC RESONATOR)

(HS, XT OR LP OSC

TABLE 7-2:

CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR

- PIC16C5X, PIC16CR5X

CONFIGURATION)

(1)

C1

Osc

Type

Resonator Cap.Range Cap. Range

OSC1

PIC16C5X

Freq

C1

C2

(1)

SLEEP

LP

32 kHz

15 pF

XTAL

(3)

RF

100 kHz

200 kHz

15-30 pF

30-47 pF

15-82 pF

To internal

logic

OSC2

(2)

XT

100 kHz

200 kHz

455 kHz

1 MHz

2 MHz

4 MHz

15-30 pF

15-47 pF

200-300 pF

100-200 pF

15-100 pF

15-30 pF

15-47 pF

RS

(1)

C2

Note 1: See Capacitor Selection tables for

recommended values of C1 and C2.

2: A series resistor (RS) may be required for

AT strip cut crystals.

HS

4 MHz

8 MHz

20 MHz

15-30 pF

3: RF varies with the crystal chosen (approx.

value = 10 MΩ).

Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is

recommended.

2: These values are for design guidance only.

Rs may be required in HS mode as well as

XT mode to avoid overdriving crystals with

low drive level speciﬁcation. Since each

crystal has its own characteristics, the user

should consult the crystal manufacturer for

appropriate values of external components.

Note: If you change from this device to

another device, please verify oscillator

characteristics in your application.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 33

PIC16C5X

7.2.3

EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

FIGURE 7-6: EXTERNAL SERIES

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

(USING XT, HS OR LP

Either a prepackaged oscillator or a simple oscillator

circuit with TTL gates can be used as an external

crystal oscillator circuit. Prepackaged oscillators

provide a wide operating range and better stability. A

well-designed crystal oscillator will provide good

performance with TTL gates. Two types of crystal

oscillator circuits can be used: one with parallel

resonance, or one with series resonance.

OSCILLATOR MODE)

To Other

Devices

330

PIC16C5X

74AS04

OSC1

0.1 µF

Figure 7-5 shows implementation of

a

parallel

OSC2

XTAL

resonant oscillator circuit. The circuit is designed to

use the fundamental frequency of the crystal. The

74AS04 inverter performs the 180-degree phase shift

that a parallel oscillator requires. The 4.7 kΩ resistor

provides the negative feedback for stability. The 10 kΩ

potentiometers bias the 74AS04 in the linear region.

This circuit could be used for external oscillator

designs.

100k

Note: If you change from this device to

another device, please verify oscillator

characteristics in your application.

7.2.4

RC OSCILLATOR

FIGURE 7-5: EXTERNAL PARALLEL

RESONANT CRYSTAL

For timing insensitive applications, the RC device

option offers additional cost savings. The RC oscillator

frequency is a function of the supply voltage, the

resistor (Rext) and capacitor (Cext) values, and the

operating temperature. In addition to this, the oscillator

frequency will vary from unit to unit due to normal

process parameter variation. Furthermore, the

difference in lead frame capacitance between package

types will also affect the oscillation frequency,

especially for low Cext values. The user also needs to

take into account variation due to tolerance of external

R and C components used.

OSCILLATOR CIRCUIT

(USING XT, HS OR LP

OSCILLATOR MODE)

+5V

To Other

Devices

10k

74AS04

PIC16C5X

4.7k

74AS04

OSC1

OSC2

Figure 7-7 shows how the R/C combination is

connected to the PIC16C5X. For Rext values below

2.2 kΩ, the oscillator operation may become unstable,

or stop completely. For very high Rext values

(e.g., 1 MΩ) the oscillator becomes sensitive to noise,

humidity and leakage. Thus, we recommend keeping

Rext between 3 kΩ and 100 kΩ.

10k

100k

XTAL

10k

20 pF

Although the oscillator will operate with no external

capacitor (Cext = 0 pF), we recommend using values

above 20 pF for noise and stability reasons. With no or

small external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or

package lead frame capacitance.

Note: If you change from this device to

another device, please verify oscillator

characteristics in your application.

This circuit is also designed to use the fundamental

frequency of the crystal. The inverter performs a

180-degree phase shift in a series resonant oscillator

circuit. The 330 Ω resistors provide the negative

feedback to bias the inverters in their linear region.

DS30453B-page 34

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

The Electrical Speciﬁcations sections show RC

frequency variation from part to part due to normal

process variation.

7.3

Reset

PIC16C5X devices may be reset in one of the

following ways:

Also, see the Electrical Speciﬁcations sections for

variation of oscillator frequency due to VDD for given

Rext/Cext values as well as frequency variation due to

operating temperature for given R, C, and VDD values.

• Power-On Reset (POR)

• MCLR reset (normal operation)

• MCLR wake-up reset (from SLEEP)

• WDT reset (normal operation)

• WDT wake-up reset (from SLEEP)

The oscillator frequency, divided by 4, is available on

the OSC2/CLKOUT pin, and can be used for test

purposes or to synchronize other logic.

Table 7-3 shows these reset conditions for the PCL

and STATUS registers.

FIGURE 7-7: RC OSCILLATOR MODE

Some registers are not affected in any reset condition.

Their status is unknown on POR and unchanged in

any other reset. Most other registers are reset to a

“reset state” on Power-On Reset (POR), MCLR or

WDT reset. A MCLR or WDT wake-up from SLEEP

also results in a device reset, and not a continuation of

operation before SLEEP.

VDD

Rext

Internal

clock

OSC1

N

Cext

VSS

PIC16C5X

The TO and PD bits (STATUS <4:3>) are set or

cleared depending on the different reset conditions

(Section 7.7). These bits may be used to determine

the nature of the reset.

Fosc/4

OSC2/CLKOUT

Table 7-4 lists a full description of reset states of all

registers. Figure 7-8 shows a simpliﬁed block diagram

of the on-chip reset circuit.

Note: If you change from this device to

another device, please verify oscillator

characteristics in your application.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 35

PIC16C5X

TABLE 7-3:

RESET CONDITIONS FOR SPECIAL REGISTERS

PCL

Addr: 02h

STATUS

Addr: 03h

Condition

Power-On Reset

1111 1111

0001 1xxx

(1)

MCLR reset (normal operation)

MCLR wake-up (from SLEEP)

WDT reset (normal operation)

WDT wake-up (from SLEEP)

000u uuuu

0001 0uuu

(2)

0000 uuuu

0000 0uuu

Legend: u= unchanged, x= unknown, -= unimplemented read as '0'.

Note 1: TO and PD bits retain their last value until one of the other reset conditions occur.

2: The CLRWDTinstruction will set the TO and PD bits.

TABLE 7-4:

Register

RESET CONDITIONS FOR ALL REGISTERS

Address

Power-On Reset

MCLR or WDT Reset

W

N/A

xxxx xxxx

1111 1111

--11 1111

xxxx xxxx

1111 1111

0001 1xxx

1xxx xxxx

---- xxxx

xxxx xxxx

uuuu uuuu

1111 1111

--11 1111

uuuu uuuu

1111 1111

000q quuu

1uuu uuuu

---- uuuu

uuuu uuuu

TRIS

OPTION

INDF

TMR0

N/A

00h

01h

(1)

PCL

02h

(1)

STATUS

03h

FSR

04h

PORTA

PORTB

05h

06h

(2)

PORTC

07h

General Purpose Register Files

07-7Fh

Legend: u= unchanged, x= unknown, -= unimplemented, read as '0',

q= see tables in Section 7.7 for possible values.

Note 1: See Table 7-3 for reset value for speciﬁc conditions.

2: General purpose register ﬁle on PIC16C52/C54s/CR54s/C56s/CR56s/C58s/CR58s

FIGURE 7-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Power-Up

Detect

POR (Power-On Reset)

VDD

MCLR/VPP pin

WDT Time-out

RESET

8-bit Asynch

S

R

Q

WDT

On-Chip

RC OSC

Ripple Counter

(Start-Up Timer)

CHIP RESET

DS30453B-page 36

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

7.4

Power-On Reset (POR)

FIGURE 7-9: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW

VDD POWER-UP)

The PIC16C5X family incorporates on-chip Power-On

Reset (POR) circuitry which provides an internal chip

reset for most power-up situations. To use this feature,

the user merely ties the MCLR/VPP pin to VDD. A

simpliﬁed block diagram of the on-chip Power-On

Reset circuit is shown in Figure 7-8.

VDD

D

R

R1

MCLR

The Power-On Reset circuit and the Device Reset

Timer (Section 7.5) circuit are closely related. On

power-up, the reset latch is set and the DRT is reset.

The DRT timer begins counting once it detects MCLR

to be high. After the time-out period, which is typically

18 ms, it will reset the reset latch and thus end the

on-chip reset signal.

PIC16C5X

C

• External Power-On Reset circuit is required

only if VDD power-up is too slow. The diode D

helps discharge the capacitor quickly when

VDD powers down.

A power-up example where MCLR is not tied to VDD is

shown in Figure 7-10. VDD is allowed to rise and

stabilize before bringing MCLR high. The chip will

actually come out of reset TDRT msec after MCLR

goes high.

• R < 40 kΩ is recommended to make sure that

voltage drop across R does not violate the

device electrical speciﬁcation.

• R1 = 100Ω to 1 kΩ will limit any current

ﬂowing into MCLR from external capacitor C

in the event of MCLR pin breakdown due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS).

In Figure 7-11, the on-chip Power-On Reset feature is

being used (MCLR and VDD are tied together). The

VDD is stable before the start-up timer times out and

there is no problem in getting a proper reset. However,

Figure 7-12 depicts a problem situation where VDD

rises too slowly. The time between when the DRT

senses a high on the MCLR/VPP pin, and when the

MCLR/VPP pin (and VDD) actually reach their full value,

is too long. In this situation, when the start-up timer

times out, VDD has not reached the VDD (min) value

and the chip is, therefore, not guaranteed to function

correctly. For such situations, we recommend that

external RC circuits be used to achieve longer POR

delay times (Figure 7-9).

Note: When the device starts normal operation

(exits the reset condition), device operat-

ing parameters (voltage, frequency, tem-

perature, etc.) must be meet to ensure

operation. If these conditions are not met,

the device must be held in reset until the

operating conditions are met.

For more information on PIC16C5X POR, see

Power-Up Considerations - AN522 in the Embedded

Control Handbook.

The POR circuit does not produce an internal reset

when VDD declines.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 37

PIC16C5X

FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)

VDD

MCLR

INTERNAL POR

TDRT

DRT TIME-OUT

INTERNAL RESET

FIGURE 7-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME

VDD

MCLR

INTERNAL POR

TDRT

DRT TIME-OUT

INTERNAL RESET

FIGURE 7-12: TIME-OUT SEQUENCE ON POWER-UP (MCLRTIED TO VDD): SLOW VDD RISETIME

V1

VDD

MCLR

INTERNAL POR

TDRT

DRT TIME-OUT

INTERNAL RESET

When VDD rises slowly, the TDRT time-out expires long before VDD has reached its ﬁnal value. In

this example, the chip will reset properly if, and only if, V1 ≥ VDD min

DS30453B-page 38

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

7.5

Device Reset Timer (DRT)

7.6

Watchdog Timer (WDT) (not

implemented on PIC16C52)

The Device Reset Timer (DRT) provides a ﬁxed 18 ms

nominal time-out on reset. The DRT operates on an

internal RC oscillator. The processor is kept in RESET

as long as the DRT is active. The DRT delay allows

VDD to rise above VDD min., and for the oscillator to

stabilize.

The Watchdog Timer (WDT) is a free running on-chip

RC oscillator which does not require any external

components. This RC oscillator is separate from the

RC oscillator of the OSC1/CLKIN pin. That means that

the WDT will run even if the clock on the OSC1/CLKIN

and OSC2/CLKOUT pins have been stopped, for

example, by execution of a SLEEP instruction. During

normal operation or SLEEP, a WDT reset or wake-up

reset generates a device RESET.

Oscillator circuits based on crystals or ceramic

resonators require a certain time after power-up to

establish a stable oscillation. The on-chip DRT keeps

the device in a RESET condition for approximately 18

ms after the voltage on the MCLR/VPP pin has

reached a logic high (VIH) level. Thus, external RC

networks connected to the MCLR input are not

required in most cases, allowing for savings in

cost-sensitive and/or space restricted applications.

The TO bit (STATUS<4>) will be cleared upon a

Watchdog Timer reset.

The WDT can be permanently disabled by

programming the conﬁguration bit WDTE as a '0'

(Section 7.1). Refer to the PIC16C5X Programming

Speciﬁcations (Literature Number DS30190) to

determine how to access the conﬁguration word.

The Device Reset time delay will vary from device to

device due to VDD, temperature, and process

variation. See AC parameters for details.

7.6.1

WDT PERIOD

The DRT will also be triggered upon a Watchdog Timer

time-out. This is particularly important for applications

using the WDT to wake the PIC16C5X from SLEEP

mode automatically.

The WDT has a nominal time-out period of 18 ms,

(with no prescaler). If a longer time-out period is

desired, a prescaler with a division ratio of up to 1:128

can be assigned to the WDT (under software control)

by writing to the OPTION register. Thus, time-out a

period of a nominal 2.3 seconds can be realized.

These periods vary with temperature, VDD and

part-to-part process variations (see DC specs).

Under worst case conditions (VDD = Min., Temperature

= Max., max. WDT prescaler), it may take several

seconds before a WDT time-out occurs.

7.6.2

WDT PROGRAMMING CONSIDERATIONS

The CLRWDT instruction clears the WDT and the

postscaler, if assigned to the WDT, and prevents it

from timing out and generating a device RESET.

The SLEEP instruction resets the WDT and the

postscaler, if assigned to the WDT. This gives the

maximum SLEEP time before a WDT wake-up reset.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 39

PIC16C5X

FIGURE 7-13: WATCHDOG TIMER BLOCK DIAGRAM

From TMR0 Clock Source

0

M

Postscaler

1

Watchdog

Timer

U

X

8 - to - 1 MUX

PS2:PS0

PSA

WDT Enable

EPROM Bit

To TMR0

1

0

PSA

MUX

Note: T0CS, T0SE, PSA, PS2:PS0

are bits in the OPTION register.

WDT

Time-out

TABLE 7-5:

SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Value on

Power-On

Reset

Value on

MCLR and

WDT Reset

Address

Name

OPTION

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

N/A

—

T0CS

T0SE

PSA

PS2

PS1

PS0

--11 1111 --11 1111

Legend: Shaded boxes = Not used by Watchdog Timer,

–= unimplemented, read as '0', u= unchanged

DS30453B-page 40

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

7.7

Time-Out Sequence and Power Down

Status Bits (TO/PD)

7.8

Reset on Brown-Out

A brown-out is a condition where device power (VDD)

dips below its minimum value, but not to zero, and then

recovers. The device should be reset in the event of a

brown-out.

The TO and PD bits in the STATUS register can be

tested to determine if a RESET condition has been

caused by a power-up condition, a MCLR or Watchdog

Timer (WDT) reset, or a MCLR or WDT wake-up reset.

To reset PIC16C5X devices when a brown-out occurs,

external brown-out protection circuits may be built, as

shown in Figure 7-14 and Figure 7-15.

TABLE 7-6:

TO/PD STATUS AFTER

RESET

FIGURE 7-14: BROWN-OUT PROTECTION

CIRCUIT 1

TO

PD

RESET was caused by

Power-up (POR)

1

u

1

u

(1)

VDD

MCLR reset (normal operation)

1

0

1

0

MCLR wake-up reset (from SLEEP)

WDT reset (normal operation)

VDD

33k

WDT wake-up reset (from SLEEP)

Q1

Legend: u= unchanged

10k

MCLR

Note 1: The TO and PD bits maintain their status (u) until

a reset occurs. A low-pulse on the MCLR input

does not change the TO and PD status bits.

40k

PIC16C5X

These STATUS bits are only affected by events listed

in Table 7-7.

This circuit will activate reset when VDD goes below Vz +

0.7V (where Vz = Zener voltage).

TABLE 7-7:

EVENTS AFFECTING TO/PD

STATUS BITS

Event

TO PD

Remarks

1

0

1

u

0

1

Power-up

FIGURE 7-15: BROWN-OUT PROTECTION

CIRCUIT 2

WDT Time-out

No effect on PD

SLEEPinstruction

CLRWDTinstruction

Legend: u= unchanged

VDD

Note: A WDT time-out will occur regardless of

the status of the TO bit. A SLEEPinstruc-

tion will be executed, regardless of the sta-

tus of the PD bit.

R1

Q1

MCLR

R2

40k

PIC16C5X

Table 7-3 lists the reset conditions for the special

function registers, while Table 7-4 lists the reset

conditions for all the registers.

This brown-out circuit is less expensive, although

less accurate. Transistor Q1 turns off when VDD

is below a certain level such that:

R1

= 0.7V

VDD •

R1 + R2

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 41

PIC16C5X

7.9

Power-Down Mode (SLEEP)

7.10

Program Veriﬁcation/Code Protection

A device may be powered down (SLEEP) and later

powered up (Wake-up from SLEEP).

If the code protection bit(s) have not been

programmed, the on-chip program memory can be

read out for veriﬁcation purposes.

7.9.1

SLEEP

Note: Microchip does not recommend code pro-

The Power-Down mode is entered by executing a

tecting windowed devices.

SLEEPinstruction.

7.11

ID Locations (not implemented on

PIC16C52)

If enabled, the Watchdog Timer will be cleared but

keeps running, the TO bit (STATUS<4>) is set, the PD

bit (STATUS<3>) is cleared and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, driving low, or hi-impedance).

Four memory locations are designated as ID locations

where the user can store checksum or other

code-identiﬁcation numbers. These locations are not

accessible during normal execution but are readable

and writable during program/verify.

It should be noted that a RESET generated by a WDT

time-out does not drive the MCLR/VPP pin low.

Use only the lower 4 bits of the ID locations and

always program the upper 8 bits as '1's.

For lowest current consumption while powered down,

the T0CKI input should be at VDD or VSS and the

MCLR/VPP pin must be at a logic high level.

Note: Microchip will assign a unique pattern

number for QTP and SQTP requests and

for ROM devices. This pattern number will

be unique and traceable to the submitted

code.

7.9.2

WAKE-UP FROM SLEEP

The device can wake up from SLEEP through one of

the following events:

1. An external reset input on MCLR/VPP pin.

2. A Watchdog Timer time-out reset (if WDT was

enabled).

Both of these events cause a device reset.The TO and

PD bits can be used to determine the cause of device

reset.

The TO bit is cleared if a WDT time-out

occurred (and caused wake-up). The PD bit, which is

set on power-up, is cleared when SLEEPis invoked.

The WDT is cleared when the device wakes from

sleep, regardless of the wake-up source.

DS30453B-page 42

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

All instructions are executed within one single

instruction cycle, unless a conditional test is true or the

8.0

INSTRUCTION SET SUMMARY

Each PIC16C5X instruction is a 12-bit word divided into an

OPCODE, which speciﬁes the instruction type, and one or

more operands which further specify the operation of the

instruction. The PIC16C5X instruction set summary in

Table 8-2 groups the instructions into byte-oriented,

bit-oriented, and literal and control operations. Table 8-1

shows the opcode ﬁeld descriptions.

program counter is changed as

a result of an

instruction. In this case, the execution takes two

instruction cycles. One instruction cycle consists of

four oscillator periods. Thus, for an oscillator frequency

of 4 MHz, the normal instruction execution time is 1 µs.

If a conditional test is true or the program counter is

changed as a result of an instruction, the instruction

execution time is 2 µs.

For byte-oriented instructions, 'f' represents a ﬁle register

designator and 'd' represents a destination designator.The

ﬁle register designator is used to specify which one of the

32 ﬁle registers is to be used by the instruction.

Figure 8-1 shows the three general formats that the

instructions can have. All examples in the ﬁgure use the

following format to represent a hexadecimal number:

The destination designator speciﬁes where the result

of the operation is to be placed. If 'd' is '0', the result is

placed in the W register. If 'd' is '1', the result is placed

in the ﬁle register speciﬁed in the instruction.

0xhhh

where 'h' signiﬁes a hexadecimal digit.

FIGURE 8-1: GENERAL FORMAT FOR

INSTRUCTIONS

For bit-oriented instructions, 'b' represents a bit ﬁeld

designator which selects the number of the bit affected

by the operation, while 'f' represents the number of the

ﬁle in which the bit is located.

Byte-oriented ﬁle register operations

11

6

5

4

0

OPCODE

d

f (FILE #)

For literal and control operations, 'k' represents an

8 or 9-bit constant or literal value.

d = 0 for destination W

d = 1 for destination f

f = 5-bit ﬁle register address

Bit-oriented ﬁle register operations

11 8 7

b (BIT #)

TABLE 8-1:

OPCODE FIELD

DESCRIPTIONS

5

4

0

Field

Description

OPCODE

f (FILE #)

f

W

b

k

Register ﬁle address (0x00 to 0x7F)

Working register (accumulator)

b = 3-bit bit address

f = 5-bit ﬁle register address

Bit address within an 8-bit ﬁle register

Literal ﬁeld, constant data or label

Literal and control operations (except GOTO)

11

Don't care location (= 0 or 1)

8

7

0

The assembler will generate code with x = 0. It is

the recommended form of use for compatibility

with all Microchip software tools.

x

d

OPCODE

k (literal)

k = 8-bit immediate value

Literal and control operations - GOTOinstruction

11 0

Destination select;

d = 0 (store result in W)

d = 1 (store result in ﬁle register 'f')

Default is d = 1

9

8

OPCODE

k (literal)

label Label name

TOS

PC

Top of Stack

k = 9-bit immediate value

Program Counter

Watchdog Timer Counter

Time-Out bit

WDT

TO

PD

Power-Down bit

Destination, either the W register or the speciﬁed

register ﬁle location

dest

[ ]

( )

→

Options

Contents

Assigned to

< >

Register bit ﬁeld

In the set of

italics

User deﬁned term (font is courier)

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 43

PIC16C5X

TABLE 8-2:

INSTRUCTION SET SUMMARY

12-Bit Opcode

Mnemonic,

Operands

Status

Description

Cycles MSb

LSb Affected Notes

1

0001 11df ffff

C,DC,Z 1,2,4

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate left f through Carry

Rotate right f through Carry

Subtract W from f

Swap f

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

f,d

f

0001 01df ffff

0000 011f ffff

0000 0100 0000

0010 01df ffff

0000 11df ffff

Z

2,4

4

–

Z

f, d

f

Z

None

Z

None

Z

None

C

2,4

1,4

1(2) 0010 11df ffff

0010 10df ffff

1(2) 0011 11df ffff

1

0001 00df ffff

0010 00df ffff

0000 001f ffff

0000 0000 0000

0011 01df ffff

0011 00df ffff

0000 10df ffff

0011 10df ffff

0001 10df ffff

–

2,4

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

C

C,DC,Z 1,2,4

None

Z

2,4

Exclusive OR W with f

BIT-ORIENTED FILE REGISTER OPERATIONS

1

0100 bbbf ffff

0101 bbbf ffff

None

2,4

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

BCF

BSF

BTFSC

BTFSS

f, b

1 (2) 0110 bbbf ffff

1 (2) 0111 bbbf ffff

LITERAL AND CONTROL OPERATIONS

1

2

1

2

1

2

1

1110 kkkk kkkk

1001 kkkk kkkk

0000 0000 0100

101k kkkk kkkk

1101 kkkk kkkk

1100 kkkk kkkk

0000 0000 0010

1000 kkkk kkkk

0000 0000 0011

0000 0000 0fff

1111 kkkk kkkk

Z

None

AND literal with W

Call subroutine

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

OPTION

RETLW

SLEEP

TRIS

k

–

f

1

3

T

Clear Watchdog Timer

Unconditional branch

Inclusive OR Literal with W

Move Literal to W

Load OPTION register

Return, place Literal in W

Go into standby mode

Load TRIS register

O, PD

None

Z

None

TO, PD

None

Z

Exclusive OR Literal to W

XORLW

k

Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except for GOTO.

(See individual device data sheets, Memory Section/Indirect Data Addressing, INDF and FSR Registers)

2: When an I/O register is modiﬁed as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value

present on the pins themselves. For example, if the data latch is '1' for a pin conﬁgured as input and is driven

low by an external device, the data will be written back with a '0'.

3: The instruction TRIS f, where f = 5 or 6 causes the contents of the W register to be written to the tristate

latches of PORTA or B respectively. A '1' forces the pin to a hi-impedance state and disables the output buff-

ers.

4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared

(if assigned to TMR0).

DS30453B-page 44

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

ADDWF

Syntax:

Add W and f

[ label ] ADDWF f,d

0 ≤ f ≤ 31

ANDWF

Syntax:

AND W with f

[ label ] ANDWF f,d

Operands:

0 ≤ f ≤ 31

d

[0,1]

d

[0,1]

Operation:

(W) + (f) → (dest)

Operation:

(W) .AND. (f) → (dest)

Status Affected: C, DC, Z

Status Affected:

Encoding:

Z

0001

11df

ffff

0001

01df

ffff

Encoding:

Add the contents of the W register and

register 'f'. If 'd' is 0 the result is stored

in the W register. If 'd' is '1' the result is

stored back in register 'f'.

The contents of the W register are

AND’ed with register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is

'1' the result is stored back in register 'f'.

Description:

Words:

1

Words:

1

Cycles:

Example:

1

Cycles:

Example:

ADDWF FSR, 0

ANDWF FSR,

1

Before Instruction

0x17

W

=

0x17

W

=

FSR = 0xC2

After Instruction

W

=

0xD9

W

=

0x17

FSR = 0xC2

FSR = 0x02

ANDLW

And literal with W

BCF

Bit Clear f

Syntax:

[ label ] ANDLW

k

Syntax:

Operands:

[ label ] BCF f,b

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 ≤ k ≤ 255

0 ≤ f ≤ 31

0 ≤ b ≤ 7

(W).AND. (k) → (W)

Operation:

0 → (f<b>)

Z

Status Affected: None

1110

kkkk

0100

bbbf

ffff

Encoding:

Description:

Words:

The contents of the W register are

AND’ed with the eight-bit literal 'k'. The

result is placed in the W register.

Bit 'b' in register 'f' is cleared.

1

Words:

1

Cycles:

Example:

1

BCF

FLAG_REG,

7

Example:

ANDLW 0x5F

Before Instruction

FLAG_REG = 0xC7

Before Instruction

0xA3

W

=

After Instruction

FLAG_REG = 0x47

After Instruction

0x03

W

=

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 45

PIC16C5X

BSF

Bit Set f

BTFSS

Bit Test f, Skip if Set

Syntax:

Operands:

[ label ] BSF f,b

Syntax:

[ label ] BTFSS f,b

0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operands:

0 ≤ f ≤ 31

0 ≤ b < 7

Operation:

1 → (f<b>)

Operation:

skip if (f<b>) = 1

Status Affected: None

0101

bbbf

ffff

0111

bbbf

ffff

Encoding:

Description:

Words:

Encoding:

Bit 'b' in register 'f' is set.

If bit 'b' in register 'f' is '1' then the next

instruction is skipped.

Description:

1

If bit 'b' is '1', then the next instruction

fetched during the current instruction

execution, is discarded and an NOP is

executed instead, making this a 2 cycle

instruction.

Cycles:

BSF

FLAG_REG,

7

Example:

Before Instruction

FLAG_REG = 0x0A

Words:

1

After Instruction

FLAG_REG = 0x8A

Cycles:

Example:

1(2)

HERE

FALSE GOTO

TRUE

BTFSS FLAG,1

PROCESS_CODE

•

BTFSC

Bit Test f, Skip if Clear

•

Syntax:

[ label ] BTFSC f,b

Operands:

0 ≤ f ≤ 31

0 ≤ b ≤ 7

Before Instruction

PC

=

address (HERE)

After Instruction

If FLAG<1>

PC

Operation:

skip if (f<b>) = 0

=

0,

Status Affected: None

address (FALSE);

1,

address (TRUE)

bbbf

ffff

if FLAG<1>

PC

Encoding:

0110

If bit 'b' in register 'f' is 0 then the next

instruction is skipped.

Description:

If bit 'b' is 0 then the next instruction

fetched during the current instruction

execution is discarded, and an NOP is

executed instead, making this a 2 cycle

instruction.

Words:

1

Cycles:

Example:

1(2)

HERE

FALSE GOTO

TRUE

BTFSC

FLAG,1

PROCESS_CODE

•

Before Instruction

PC

=

address (HERE)

After Instruction

if FLAG<1>

PC

=

0,

address (TRUE);

1,

address(FALSE)

if FLAG<1>

PC

DS30453B-page 46

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

CALL

Subroutine Call

[ label ] CALL

0 ≤ k ≤ 255

CLRW

Clear W

Syntax:

k

Syntax:

[ label ] CLRW

None

Operands:

Operation:

Operands:

Operation:

(PC) + 1→ Top of Stack;

k → PC<7:0>;

00h → (W);

1 → Z

(STATUS<6:5>) → PC<10:9>;

0 → PC<8>

Status Affected:

Encoding:

Z

0000

0100

0000

Status Affected: None

The W register is cleared. Zero bit (Z)

is set.

Description:

1001

kkkk

Encoding:

Subroutine call. First, return address

(PC+1) is pushed onto the stack. The

eight bit immediate address is loaded

into PC bits <7:0>. The upper bits

PC<10:9> are loaded from STA-

TUS<6:5>, PC<8> is cleared. CALLis

a two cycle instruction.

Description:

Words:

1

Cycles:

Example:

1

CLRW

Before Instruction

0x5A

W

=

After Instruction

Words:

1

2

W

=

0x00

Cycles:

Example:

Z

=

1

HERE

CALL

THERE

Before Instruction

PC address (HERE)

CLRWDT

Clear Watchdog Timer

[ label ] CLRWDT

None

=

Syntax:

After Instruction

PC address (THERE)

TOS =

=

Operands:

Operation:

address (HERE + 1)

00h → WDT;

0 → WDT prescaler (if assigned);

1 → TO;

1 → PD

CLRF

Clear f

Syntax:

[ label ] CLRF

f

Status Affected: TO, PD

Operands:

Operation:

0 ≤ f ≤ 31

0000

0100

Encoding:

00h → (f);

1 → Z

The CLRWDTinstruction resets the

WDT. It also resets the prescaler, if the

prescaler is assigned to the WDT and

not Timer0. Status bits TO and PD are

set.

Description:

Status Affected:

Encoding:

Z

0000

011f

ffff

The contents of register 'f' are cleared

and the Z bit is set.

Description:

Words:

1

Cycles:

Example:

1

Words:

1

CLRWDT

Cycles:

Example:

Before Instruction

CLRF

FLAG_REG

WDT counter

=

?

Before Instruction

FLAG_REG

After Instruction

WDT counter

=

0x5A

0x00

After Instruction

WDT prescale =

0

1

FLAG_REG

Z

=

0x00

1

TO

PD

=

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 47

PIC16C5X

COMF

Complement f

DECFSZ

Syntax:

Decrement f, Skip if 0

[ label ] DECFSZ f,d

0 ≤ f ≤ 31

Syntax:

Operands:

[ label ] COMF f,d

0 ≤ f ≤ 31

Operands:

d

[0,1]

d

[0,1]

Operation:

(f) → (dest)

Operation:

(f) – 1 → d; skip if result = 0

Status Affected:

Encoding:

Z

Status Affected: None

0010

01df

ffff

0010

11df

ffff

Encoding:

The contents of register 'f' are comple-

mented. If 'd' is 0 the result is stored in

the W register. If 'd' is 1 the result is

stored back in register 'f'.

The contents of register 'f' are decre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Description:

If the result is 0, the next instruction,

which is already fetched, is discarded

and an NOP is executed instead mak-

ing it a two cycle instruction.

Words:

1

Cycles:

Example:

COMF

REG1,0

Words:

1

Before Instruction

REG1

=

0x13

Cycles:

Example:

1(2)

After Instruction

HERE

DECFSZ

GOTO

CONTINUE •

CNT, 1

LOOP

REG1

=

W

=

0xEC

•

DECF

Decrement f

[ label ] DECF f,d

0 ≤ f ≤ 31

Before Instruction

PC

=

address (HERE)

Syntax:

After Instruction

Operands:

CNT

if CNT

PC

if CNT

PC

=

≠

=

CNT - 1;

0,

address (CONTINUE);

0,

d

[0,1]

Operation:

(f) – 1 → (dest)

Status Affected:

Encoding:

Z

address (HERE+1)

0000

11df

ffff

Decrement register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is

1 the result is stored back in register 'f'.

Description:

GOTO

Unconditional Branch

Syntax:

[ label ] GOTO

0 ≤ k ≤ 511

k

Words:

1

Operands:

Cycles:

Example:

Operation:

k → PC<8:0>;

STATUS<6:5> → PC<10:9>

DECF

CNT,

1

Before Instruction

Status Affected: None

CNT

=

0x01

0

101k

kkkk

Encoding:

Z

=

GOTOis an unconditional branch. The

9-bit immediate value is loaded into PC

bits <8:0>. The upper bits of PC are

loaded from STATUS<6:5>. GOTOis a

two cycle instruction.

Description:

After Instruction

CNT

=

0x00

1

Z

=

Words:

1

Cycles:

Example:

2

GOTO THERE

After Instruction

PC

=

address (THERE)

DS30453B-page 48

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

INCF

Increment f

IORLW

Inclusive OR literal with W

Syntax:

Operands:

[ label ] INCF f,d

Syntax:

[ label ] IORLW k

0 ≤ f ≤ 31

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 ≤ k ≤ 255

d

[0,1]

(W) .OR. (k) → (W)

Operation:

(f) + 1 → (dest)

Z

Status Affected:

Encoding:

Z

1101

kkkk

0010

10df

ffff

The contents of the W register are

OR’ed with the eight bit literal 'k'. The

result is placed in the W register.

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Description:

Words:

1

Cycles:

Example:

1

Words:

1

IORLW 0x35

Cycles:

Example:

Before Instruction

0x9A

INCF

CNT,

1

W

=

Before Instruction

After Instruction

CNT

=

0xFF

0

W

=

0xBF

Z

=

Z

=

0

After Instruction

CNT

Z

=

0x00

1

IORWF

Inclusive OR W with f

[ label ] IORWF f,d

0 ≤ f ≤ 31

Syntax:

Operands:

INCFSZ

Increment f, Skip if 0

[ label ] INCFSZ f,d

0 ≤ f ≤ 31

d

[0,1]

Syntax:

Operation:

(W).OR. (f) → (dest)

Operands:

Status Affected:

Encoding:

Z

d

[0,1]

0001

00df

ffff

Operation:

(f) + 1 → (dest), skip if result = 0

Inclusive OR the W register with regis-

ter 'f'. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Description:

Status Affected: None

0011

11df

ffff

Encoding:

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Description:

Words:

1

Cycles:

Example:

If the result is 0, then the next instruc-

tion, which is already fetched, is dis-

carded and an NOP is executed

instead making it a two cycle instruc-

tion.

IORWF

RESULT, 0

Before Instruction

RESULT

W

=

0x13

=

0x91

After Instruction

Words:

1

RESULT

=

0x13

0x93

0

Cycles:

Example:

1(2)

W

Z

HERE

INCFSZ

GOTO

CNT,

LOOP

1

CONTINUE •

•

Before Instruction

PC

=

address (HERE)

After Instruction

CNT

if CNT

PC

if CNT

PC

=

≠

=

CNT + 1;

0,

address (CONTINUE);

0,

address (HERE +1)

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 49

PIC16C5X

MOVF

Move f

MOVWF

Syntax:

Move W to f

[ label ] MOVWF

0 ≤ f ≤ 31

Syntax:

Operands:

[ label ] MOVF f,d

f

0 ≤ f ≤ 31

Operands:

Operation:

d

[0,1]

(W) → (f)

Operation:

(f) → (dest)

Status Affected: None

Status Affected:

Encoding:

Z

0000

001f

ffff

Encoding:

0010

00df

ffff

Move data from the W register to regis-

ter 'f'.

Description:

The contents of register 'f' is moved to

destination 'd'. If 'd' is 0, destination is

the W register. If 'd' is 1, the destination

is ﬁle register 'f'. 'd' is 1 is useful to test

a ﬁle register since status ﬂag Z is

affected.

Description:

Words:

1

Cycles:

Example:

1

MOVWF TEMP_REG

Before Instruction

Words:

1

TEMP_REG

W

=

0xFF

0x4F

Cycles:

Example:

MOVF

FSR,

0

After Instruction

TEMP_REG

W

=

0x4F

After Instruction

W

=

value in FSR register

NOP

No Operation

[ label ] NOP

None

MOVLW

Move Literal to W

[ label ] MOVLW

0 ≤ k ≤ 255

Syntax:

k

Operands:

Operation:

Operands:

Operation:

No operation

k → (W)

Status Affected: None

0000

Status Affected: None

Encoding:

Description:

Words:

1100

kkkk

Encoding:

No operation.

The eight bit literal 'k' is loaded into the

W register. The don’t cares will assem-

ble as 0s.

Description:

1

Cycles:

1

NOP

Example:

Words:

1

Cycles:

Example:

1

MOVLW 0x5A

After Instruction

W

=

0x5A

DS30453B-page 50

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

OPTION

Syntax:

Load OPTION Register

[ label ] OPTION

None

RLF

Rotate Left f through Carry

Syntax:

Operands:

[ label ] RLF f,d

Operands:

Operation:

0 ≤ f ≤ 31

d

[0,1]

(W) → OPTION

Status Affected: None

Operation:

See description below

C

0000

0010

Encoding:

Status Affected:

Encoding:

The content of the W register is loaded

into the OPTION register.

Description:

0011

01df

ffff

The contents of register 'f' are rotated

one bit to the left through the Carry

Flag. If 'd' is 0 the result is placed in the

W register. If 'd' is 1 the result is stored

back in register 'f'.

Description:

Words:

Cycles:

Example

1

OPTION

Before Instruction

register 'f'

C

W

=

0x07

After Instruction

OPTION

Words:

1

=

Cycles:

Example:

1

RLF

REG1,0

RETLW

Return with Literal in W

Before Instruction

Syntax:

[ label ] RETLW

k

REG1

C

=

1110 0110

0

Operands:

Operation:

0 ≤ k ≤ 255

After Instruction

k → (W);

TOS → PC

REG1

W

C

=

1110 0110

1100 1100

1

Status Affected: None

1000

kkkk

Encoding:

The W register is loaded with the eight

bit literal 'k'. The program counter is

loaded from the top of the stack (the

return address). This is a two cycle

instruction.

Description:

RRF

Rotate Right f through Carry

[ label ] RRF f,d

0 ≤ f ≤ 31

Syntax:

Operands:

d

[0,1]

Words:

1

2

Operation:

See description below

C

Cycles:

Example:

Status Affected:

Encoding:

CALL TABLE ;W contains

;table offset

;value.

0011

00df

ffff

The contents of register 'f' are rotated

one bit to the right through the Carry

Flag. If 'd' is 0 the result is placed in the

W register. If 'd' is 1 the result is placed

back in register 'f'.

Description:

•

;W now has table

;value.

•

TABLE

ADDWF PC

RETLW k1

RETLW k2

;W = offset

;Begin table

;

register 'f'

C

•

Words:

1

•

Cycles:

Example:

1

RETLW kn

; End of table

RRF

REG1,0

Before Instruction

W

=

0x07

Before Instruction

REG1

C

=

1110 0110

0

After Instruction

value of k8

W

=

After Instruction

REG1

W

C

=

1110 0110

0111 0011

0

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 51

PIC16C5X

SLEEP

Enter SLEEP Mode

SUBWF

Subtract W from f

Syntax:

[label]

None

[label] SUBWF f,d

SLEEP

Operands:

0 ≤ f ≤ 31

Operands:

Operation:

d

[0,1]

00h → WDT;

0 → WDT prescaler;

1 → TO;

Operation:

(f) – (W) → (dest)

Status Affected: C, DC, Z

0 → PD

0000

10df

ffff

Encoding:

Status Affected: TO, PD

Subtract (2’s complement method) the

W register from register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is

1 the result is stored back in register 'f'.

Description:

0000

0011

Encoding:

Time-out status bit (TO) is set. The

power down status bit (PD) is cleared.

The WDT and its prescaler are

cleared.

Description:

Words:

1

Cycles:

The processor is put into SLEEP mode

with the oscillator stopped. See sec-

tion on SLEEP for more details.

SUBWF

REG1, 1

Example 1:

Before Instruction

Words:

1

REG1

W

C

=

3

2

?

Cycles:

Example:

1

SLEEP

After Instruction

REG1

W

C

=

1

2

1

; result is positive

Example 2:

Before Instruction

REG1

W

C

=

2

?

After Instruction

REG1

W

C

=

0

2

1

; result is zero

Example 3:

Before Instruction

REG1

W

C

=

1

2

?

After Instruction

REG1

W

C

=

FF

2

0

; result is negative

DS30453B-page 52

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

SWAPF

Syntax:

Swap Nibbles in f

[ label ] SWAPF f,d

0 ≤ f ≤ 31

XORLW

Exclusive OR literal with W

Syntax:

[label] XORLW

0 ≤ k ≤ 255

k

Operands:

d

[0,1]

Operation:

(W) .XOR. k → (W)

Z

Operation:

(f<3:0>) → (dest<7:4>);

(f<7:4>) → (dest<3:0>)

Status Affected:

Encoding:

1111

kkkk

Status Affected: None

The contents of the W register are

XOR’ed with the eight bit literal 'k'. The

result is placed in the W register.

Description:

0011

10df

ffff

Encoding:

The upper and lower nibbles of register

'f' are exchanged. If 'd' is 0 the result is

placed in W register. If 'd' is 1 the result

is placed in register 'f'.

Description:

Words:

1

Cycles:

Example:

1

Words:

Cycles:

Example

1

XORLW 0xAF

Before Instruction

0xB5

W

=

SWAPF

REG1,

0

After Instruction

Before Instruction

REG1

W

=

0x1A

=

0xA5

After Instruction

REG1

W

=

0xA5

0X5A

XORWF

Exclusive OR W with f

[ label ] XORWF f,d

0 ≤ f ≤ 31

Syntax:

Operands:

TRIS

Load TRIS Register

d

[0,1]

Syntax:

[ label ] TRIS

f = 5, 6 or 7

f

Operation:

(W) .XOR. (f) → (dest)

Operands:

Operation:

Status Affected:

Encoding:

Z

(W) → TRIS register f

0001

10df

ffff

Status Affected: None

Exclusive OR the contents of the W

register with register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is

1 the result is stored back in register 'f'.

Description:

0000

0fff

Encoding:

TRIS register 'f' (f = 5, 6, or 7) is loaded

with the contents of the W register

Description:

Words:

Cycles:

Example

1

Words:

Cycles:

Example

1

TRIS

PORTA

REG,1

XORWF

Before Instruction

W

=

0XA5

REG

=

0xAF

0xB5

W

=

After Instruction

TRISA

=

After Instruction

REG

W

=

0x1A

0xB5

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 53

PIC16C5X

NOTES:

DS30453B-page 54

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

9.3

ICEPIC: Low-Cost PICmicro™

In-Circuit Emulator

9.0

DEVELOPMENT SUPPORT

9.1

Development Tools

ICEPIC is a low-cost in-circuit emulator solution for the

Microchip PIC12CXXX, PIC16C5X and PIC16CXXX

families of 8-bit OTP microcontrollers.

The PICmicrο microcontrollers are supported with a

full range of hardware and software development

tools:

ICEPIC is designed to operate on PC-compatible

machines ranging from 286-AT through Pentium

based machines under Windows 3.x environment.

ICEPIC features real time, non-intrusive emulation.

• PICMASTER /PICMASTER CE Real-Time

In-Circuit Emulator

• ICEPIC Low-Cost PIC16C5X and PIC16CXXX

In-Circuit Emulator

9.4

PRO MATE II: Universal Programmer

• PRO MATE II Universal Programmer

• PICSTART Plus Entry-Level Prototype

Programmer

The PRO MATE II Universal Programmer is

a

full-featured programmer capable of operating in

stand-alone mode as well as PC-hosted mode. PRO

MATE II is CE compliant.

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• PICDEM-3 Low-Cost Demonstration Board

• MPASM Assembler

The PRO MATE II has programmable VDD and VPP

supplies which allows it to verify programmed memory

at VDD min and VDD max for maximum reliability. It has

an LCD display for displaying error messages, keys to

enter commands and a modular detachable socket

assembly to support various package types. In stand-

alone mode the PRO MATE II can read, verify or

program PIC12CXXX, PIC14C000, PIC16C5X,

PIC16CXXX and PIC17CXX devices. It can also set

conﬁguration and code-protect bits in this mode.

• MPLAB SIM Software Simulator

• MPLAB-C17 (C Compiler)

• Fuzzy Logic Development System

(fuzzyTECH −MP)

9.2

PICMASTER: High Performance

Universal In-Circuit Emulator with

MPLAB IDE

9.5

PICSTART Plus Entry Level

Development System

The PICMASTER Universal In-Circuit Emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for all

microcontrollers in the PIC14C000, PIC12CXXX,

PIC16C5X, PIC16CXXX and PIC17CXX families.

PICMASTER is supplied with the MPLAB Integrated

Development Environment (IDE), which allows editing,

“make” and download, and source debugging from a

single environment.

The PICSTART programmer is an easy-to-use,

low-cost prototype programmer. It connects to the PC

via one of the COM (RS-232) ports. MPLAB Integrated

Development Environment software makes using the

programmer simple and efﬁcient. PICSTART Plus is

not recommended for production programming.

PICSTART

Plus

supports

all

PIC12CXXX,

Interchangeable target probes allow the system to be

easily reconﬁgured for emulation of different

processors. The universal architecture of the

PICMASTER allows expansion to support all new

Microchip microcontrollers.

PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX

devices with up to 40 pins. Larger pin count devices

such as the PIC16C923, PIC16C924 and PIC17C756

may be supported with an adapter socket. PICSTART

Plus is CE compliant.

The PICMASTER Emulator System has been

designed as

a real-time emulation system with

advanced features that are generally found on more

expensive development tools. The PC compatible 386

(and higher) machine platform and Microsoft Windows

3.x environment were chosen to best make these

features available to you, the end user.

A CE compliant version of PICMASTER is available for

European Union (EU) countries.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 55

PIC16C5X

connecting it to the microcontroller socket(s). Some

of the features include an RS-232 interface,

push-button switches, a potentiometer for simulated

analog input, a thermistor and separate headers for

connection to an external LCD module and a keypad.

Also provided on the PICDEM-3 board is an LCD

panel, with 4 commons and 12 segments, that is

capable of displaying time, temperature and day of the

week. The PICDEM-3 provides an additional RS-232

interface and Windows 3.1 software for showing the

demultiplexed LCD signals on a PC. A simple serial

interface allows the user to construct a hardware

demultiplexer for the LCD signals.

9.6

PICDEM-1 Low-Cost PICmicro

Demonstration Board

The PICDEM-1 is a simple board which demonstrates

the capabilities of several of Microchip’s

microcontrollers. The microcontrollers supported are:

PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61,

PIC16C62X, PIC16C71, PIC16C8X, PIC17C42,

PIC17C43 and PIC17C44. All necessary hardware

and software is included to run basic demo programs.

The users can program the sample microcontrollers

provided with the PICDEM-1 board, on

a

PRO MATE II or PICSTART-Plus programmer, and

easily test ﬁrmware. The user can also connect the

PICDEM-1 board to the PICMASTER emulator and

download the ﬁrmware to the emulator for testing.

Additional prototype area is available for the user to

build some additional hardware and connect it to the

microcontroller socket(s). Some of the features include

an RS-232 interface, a potentiometer for simulated

analog input, push-button switches and eight LEDs

connected to PORTB.

9.9

MPLAB™ Integrated Development

Environment Software

The MPLAB IDE Software brings an ease of software

development previously unseen in the 8-bit

microcontroller market. MPLAB is a windows based

application which contains:

• A full featured editor

• Three operating modes

- editor

9.7

PICDEM-2 Low-Cost PIC16CXX

Demonstration Board

- emulator

- simulator

The PICDEM-2 is a simple demonstration board that

supports the PIC16C62, PIC16C64, PIC16C65,

PIC16C73 and PIC16C74 microcontrollers. All the

necessary hardware and software is included to

run the basic demonstration programs. The user

can program the sample microcontrollers provided

with the PICDEM-2 board, on a PRO MATE II

programmer or PICSTART-Plus, and easily test

ﬁrmware. The PICMASTER emulator may also be

used with the PICDEM-2 board to test ﬁrmware.

Additional prototype area has been provided to the

user for adding additional hardware and connecting it

to the microcontroller socket(s). Some of the features

include a RS-232 interface, push-button switches, a

potentiometer for simulated analog input, a Serial

• A project manager

• Customizable tool bar and key mapping

• A status bar with project information

• Extensive on-line help

MPLAB allows you to:

• Edit your source ﬁles (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PICmicro tools (automatically updates all

project information)

• Debug using:

- source ﬁles

- absolute listing ﬁle

• Transfer data dynamically via DDE (soon to be

replaced by OLE)

2

EEPROM to demonstrate usage of the I C bus and

• Run up to four emulators on the same PC

separate headers for connection to an LCD module

and a keypad.

The ability to use MPLAB with Microchip’s simulator

allows a consistent platform and the ability to easily

switch from the low cost simulator to the full featured

emulator with minimal retraining due to development

tools.

9.8

PICDEM-3 Low-Cost PIC16CXXX

Demonstration Board

The PICDEM-3 is a simple demonstration board that

supports the PIC16C923 and PIC16C924 in the PLCC

package. It will also support future 44-pin PLCC

9.10

Assembler (MPASM)

The MPASM Universal Macro Assembler is

a

microcontrollers with

a LCD Module. All the

PC-hosted symbolic assembler. It supports all

microcontroller series including the PIC12C5XX,

PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX

families.

necessary hardware and software is included to

run the basic demonstration programs. The user

can program the sample microcontrollers provided

with the PICDEM-3 board, on a PRO MATE II

programmer or PICSTART Plus with an adapter

socket, and easily test ﬁrmware. The PICMASTER

emulator may also be used with the PICDEM-3 board

to test ﬁrmware. Additional prototype area has been

provided to the user for adding hardware and

MPASM offers full featured Macro capabilities,

conditional assembly, and several source and listing

formats. It generates various object code formats to

support Microchip's development tools as well as third

party programmers.

DS30453B-page 56

Preliminary

1998 Microchip Technology Inc.

PIC16C5X

MPASM allows full symbolic debugging from

PICMASTER, Microchip’s Universal Emulator System.

9.14

MP-DriveWay – Application Code

Generator

MPASM has the following features to assist in

developing software for speciﬁc use applications.

MP-DriveWay is an easy-to-use Windows-based

Application Code Generator. With MP-DriveWay you

can visually conﬁgure all the peripherals in a PICmicro

device and, with a click of the mouse, generate all the

initialization and many functional code modules in C

language. The output is fully compatible with

Microchip’s MPLAB-C C compiler. The code produced

is highly modular and allows easy integration of your

own code. MP-DriveWay is intelligent enough to

maintain your code through subsequent code

generation.

• Provides translation of Assembler source code to

object code for all Microchip microcontrollers.

• Macro assembly capability.

• Produces all the ﬁles (Object, Listing, Symbol,

and special) required for symbolic debug with

Microchip’s emulator systems.

• Supports Hex (default), Decimal and Octal source

and listing formats.

MPASM provides a rich directive language to support

programming of the PICmicro. Directives are helpful in

making the development of your assemble source

code shorter and more maintainable.

9.15

SEEVAL Evaluation and

Programming System

The SEEVAL SEEPROM Designer’s Kit supports all

Microchip 2-wire and 3-wire Serial EEPROMs. The kit

includes everything necessary to read, write, erase or

program special features of any Microchip SEEPROM

product including Smart Serials and secure serials.

9.11

Software Simulator (MPLAB-SIM)

The MPLAB-SIM Software Simulator allows code

development in a PC host environment. It allows the

user to simulate the PICmicro series microcontrollers

on an instruction level. On any given instruction, the

user may examine or modify any of the data areas or

provide external stimulus to any of the pins. The

input/output radix can be set by the user and the

execution can be performed in; single step, execute

until break, or in a trace mode.

The Total Endurance

Disk is included to aid in

trade-off analysis and reliability calculations. The total

kit can signiﬁcantly reduce time-to-market and result in

an optimized system.

9.16

KEELOQ Evaluation and

Programming Tools

MPLAB-SIM fully supports symbolic debugging using

MPLAB-C and MPASM. The Software Simulator offers

the low cost ﬂexibility to develop and debug code

outside of the laboratory environment making it an

excellent multi-project software development tool.

KEELOQ evaluation and programming tools support

Microchips HCS Secure Data Products. The HCS

evaluation kit includes an LCD display to show

changing codes, a decoder to decode transmissions,

and

a programming interface to program test

transmitters.

9.12

C Compiler (MPLAB-C17)

The MPLAB-C Code Development System is

a

complete ‘C’ compiler and integrated development

environment for Microchip’s PIC17CXXX family of

microcontrollers. The compiler provides powerful

integration capabilities and ease of use not found with

other compilers.

For easier source level debugging, the compiler

provides symbol information that is compatible with the

MPLAB IDE memory display.

9.13

Fuzzy Logic Development System

(fuzzyTECH-MP)

fuzzyTECH-MP fuzzy logic development tool is

available in two versions - a low cost introductory

version, MP Explorer, for designers to gain

comprehensive working knowledge of fuzzy logic

system design; and full-featured version,

a

fuzzyTECH-MP, Edition for implementing more

complex systems.

Both versions include Microchip’s fuzzyLAB

demonstration board for hands-on experience with

fuzzy logic systems implementation.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 57

PIC16C52

PIC16C5X

10.0 ELECTRICAL CHARACTERISTICS - PIC16C52

Absolute Maximum Ratings†

Ambient Temperature under bias ...........................................................................................................–55°C to +125°C

Storage Temperature..............................................................................................................................–65°C to +150°C

Voltage on VDD with respect to VSS ..............................................................................................................0 V to +7.5 V

Voltage on MCLR with respect to VSS............................................................................................................0 V to +14 V

Voltage on all other pins with respect to VSS ................................................................................–0.6 V to (VDD + 0.6 V)

(1)

Total Power Dissipation ....................................................................................................................................800 mW

Max. Current out of VSS pin...................................................................................................................................150 mA

Max. Current into VDD pin........................................................................................................................................50 mA

Max. Current into an input pin (T0CKI only).....................................................................................................................±500 µA

Input Clamp Current, IIK (VI < 0 or VI > VDD) ....................................................................................................................±20 mA

Output Clamp Current, IOK (VO < 0 or VO > VDD)............................................................................................................±20 mA

Max. Output Current sunk by any I/O pin................................................................................................................10 mA

Max. Output Current sourced by any I/O pin...........................................................................................................10 mA

Max. Output Current sourced by a single I/O port (PORTA or B)............................................................................10 mA

Max. Output Current sunk by a single I/O port (PORTA or B).................................................................................10 mA

Note 1: Power Dissipation is calculated as follows: Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)

†

NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This

is a stress rating only and functional operation of the device at those or any other conditions above those indicated

in the operation listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 59

PIC16C5X

PIC16C52

10.1

DC Characteristics: PIC16C52-04 (Commercial)

PIC16C52-04I (Industrial)

Standard Operating Conditions (unless otherwise speciﬁed)

DC Characteristics

Power Supply Pins

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

(1)

Characteristic

Sym Min

Typ

Max Units

Conditions

Supply Voltage

VDD

VDR

IDD

3.0

—

6.25

—

V

FOSC = DC to 4 MHz

(2)

RAM Data Retention Voltage

1.5*

Device in SLEEP Mode

FOSC = 4 MHz, VDD = 5.5 V

(3,4)

Supply Current

—

1.8

3.3

mA

(5)

Power Down Current

IPD

—

Commercial

Industrial

0.6

9

12

µA

VDD = 3.0 V

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C.This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

Vss, T0CKI = VDD, MCLR = VDD.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: For RC option, does not include current through Rext. The current through the resistor can be estimated by

the formula: IR = VDD/2Rext (mA) with Rext in kΩ.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

DS30453B-page 60

Preliminary

1998 Microchip Technology Inc.

PIC16C52

PIC16C5X

10.2

DC Characteristics: PIC16C52-04 (Commercial)

PIC16C52-04I (Industrial)

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

DC Characteristics

All Pins Except

Power Supply Pins

Operating Voltage VDD range is described in Section 10.1.

(1)

Characteristic

Sym

Min

Typ

Max

Units

Conditions

Input Low Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

VIL

—

VSS

0.2 VDD

0.15 VDD

0.3 VDD

V

Pin at hi-impedance

(4)

RC option only

XT option

Input High Voltage

I/O ports

VIH

—

(5)

0.45 VDD

2.0

VDD

V

For all VDD

(5)

4.0 V < VDD ≤ 5.5 V

VDD > 5.5 V

0.36 VDD

0.85 VDD

0.7 VDD

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

(4)

RC option only

XT option

Hysteresis of Schmitt

Trigger inputs

VHYS

IIL

0.15VDD*

—

V

(2,3)

Input Leakage Current

For VDD ≤ 5.5 V

VSS ≤ VPIN ≤ VDD,

Pin at hi-impedance

VPIN = VSS + 0.25 V

VPIN = VDD

VSS ≤ VPIN ≤ VDD

VSS ≤ VPIN ≤ VDD,

XT option

I/O ports

–1

–5

0.5

+1

µA

MCLR

µA

0.5

+5

+3

T0CKI

OSC1

–3

Output Low Voltage

I/O ports

OSC2/CLKOUT

VOL

VOH

—

0.6

V

IOL = 2.0 mA, VDD = 4.5 V

IOL = 1.6 mA, VDD = 4.5 V,

RC option

Output High Voltage

—

(3)

I/O ports

VDD – 0.7

V

IOH = –2.0 mA, VDD = 4.5 V

IOH = –1.0 mA, VDD = 4.5 V,

RC option

OSC2/CLKOUT

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C.This data is for design guidance

only and is not tested.

2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The speciﬁed

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltage.

3: Negative current is deﬁned as coming out of the pin.

4: For RC option, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C52 be

driven with external clock in RC mode.

5: The user may use the better of the two speciﬁcations.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 61

PIC16C5X

PIC16C52

10.3

Timing Parameter Symbology and Load Conditions

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase subscripts (pp) and their meanings:

pp

T

Time

2

to

mc

osc

os

MCLR

oscillator

OSC1

ck

cy

drt

io

CLKOUT

cycle time

device reset timer

I/O port

t0

T0CKI

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (Hi-impedance)

Low

Valid

L

Hi-impedance

FIGURE 10-1: LOAD CONDITIONS - PIC16C52

CL = 50 pF for all pins except OSC2

CL

15 pF for OSC2 in XT mode when

external clock is used to

drive OSC1

VSS

DS30453B-page 62

Preliminary

1998 Microchip Technology Inc.

PIC16C52

PIC16C5X

10.4

Timing Diagrams and Speciﬁcations

FIGURE 10-2: EXTERNAL CLOCK TIMING - PIC16C52

Q4

Q3

Q4

4

Q1

Q2

OSC1

1

3

4

2

CLKOUT

TABLE 10-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C52

AC Characteristics

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

Operating Voltage VDD range is described in Section 10.1.

Parameter

(1)

No.

Sym

Characteristic

Min Typ

Max Units

Conditions

(2)

FOSC

External CLKIN Frequency

DC

0.1

250

—

4

MHz XT osc mode

MHz RC osc mode

MHz XT osc mode

(2)

Oscillator Frequency

—

4

(2)

1

TOSC

External CLKIN Period

—

ns

—

ns

RC osc mode

XT osc mode

RC osc mode

XT osc mode

—

(2)

Oscillator Period

—

10,000

—

(3)

2

3

4

TCY

Instruction Cycle Time

4/FOSC

—

TosL, TosH Clock in (OSC1) Low or High Time

TosR, TosF Clock in (OSC1) Rise or Fall Time

85*

—

XT oscillator

—

25*

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

2: All speciﬁed values are based on characterization data for that particular oscillator type under standard operating condi-

tions with the device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation and/or

higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruction cycle period (TCY) equals four times the input oscillator time base period.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 63

PIC16C5X

PIC16C52

FIGURE 10-3: CLKOUT AND I/O TIMING - PIC16C52

Q1

Q2

Q3

Q4

OSC1

10

11

CLKOUT

13

12

18

14

19

16

I/O Pin

(input)

15

17

I/O Pin

(output)

New Value

Old Value

20, 21

Note: All tests must be done with speciﬁed capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

TABLE 10-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C52

AC Characteristics

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

Operating Voltage VDD range is described in Section 10.1.

Parameter

(1)

Typ

No.

Sym

Characteristic

(2)

Min

Max

Units

10

11

12

13

14

15

16

17

18

TosH2ckL

TosH2ckH

TckR

OSC1↑ to CLKOUT↓

—

15

5

30**

15**

40**

—

ns

(2)

OSC1↑ to CLKOUT↑

—

(2)

CLKOUT rise time

—

(2)

TckF

CLKOUT fall time

—

5

(2)

CLKOUT↓ to Port out valid

TckL2ioV

TioV2ckH

TckH2ioI

TosH2ioV

TosH2ioI

—

(2)

Port in valid before CLKOUT↑

(2)

0.25 TCY+30*

Port in hold after CLKOUT↑

OSC1↑ (Q1 cycle) to Port out valid

0*

—

(3)

100*

—

OSC1↑ (Q2 cycle) to Port input invalid

TBD

(I/O in hold time)

19

TioV2osH

Port input valid to OSC1↑

TBD

—

ns

(I/O in setup time)

(3)

20

21

TioR

TioF

Port output rise time

—

10

25**

ns

(3)

Port output fall time

*

These parameters are characterized but not tested.

** These parameters are design targets and are not tested. No characterization data available at this time.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

3: See Figure 10-1 for loading conditions.

DS30453B-page 64

Preliminary

1998 Microchip Technology Inc.

PIC16C52

PIC16C5X

FIGURE 10-4: RESET AND DEVICE RESET TIMER TIMING - PIC16C52

VDD

MCLR

30

Internal

POR

32

DRT

Time-out

Internal

RESET

34

I/O pin

(Note 1)

Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.

TABLE 10-3: RESET AND DEVICE RESET TIMER - PIC16C52

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

Operating Voltage VDD range is described in Section 10.1.

Parameter

No.

(1)

Sym Characteristic

Min Typ

Max Units

Conditions

30

32

34

TmcL MCLR Pulse Width (low)

100*

9*

—

18*

—

ns VDD = 5 V

TDRT Device Reset Timer Period

TioZ I/O Hi-impedance from MCLR Low

30*

ms VDD = 5 V (Commercial)

ns

—

100*

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 65

PIC16C5X

PIC16C52

FIGURE 10-5: TIMER0 CLOCK TIMINGS - PIC16C52

T0CKI

40

41

42

TABLE 10-4: TIMER0 CLOCK REQUIREMENTS - PIC16C52

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

Operating Voltage VDD range is described in Section 10.1.

Parameter

(1)

Sym Characteristic

Min

Typ

Max Units Conditions

No.

40

Tt0H T0CKI High Pulse Width - No Prescaler

- With Prescaler

0.5 TCY + 20*

10*

—

ns

41

42

Tt0L T0CKI Low Pulse Width - No Prescaler

- With Prescaler

0.5 TCY + 20*

10*

Tt0P T0CKI Period

20 or TCY + 40*

N

ns Whichever is greater.

N = Prescale Value

(1, 2, 4,..., 256)

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

DS30453B-page 66

Preliminary

1998 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

11.0 ELECTRICAL CHARACTERISTICS - PIC16C54/55/56/57

Absolute Maximum Ratings†

Ambient Temperature under bias ...........................................................................................................–55°C to +125°C

Storage Temperature..............................................................................................................................–65°C to +150°C

Voltage on VDD with respect to VSS ............................................................................................................... 0V to +7.5V

(2)

Voltage on MCLR with respect to VSS ......................................................................................................... 0V to +14V

Voltage on all other pins with respect to VSS ................................................................................. –0.6V to (VDD + 0.6V)

(1)

Total Power Dissipation ....................................................................................................................................800 mW

Max. Current out of VSS pin...................................................................................................................................150 mA

Max. Current into VDD pin......................................................................................................................................100 mA

Max. Current into an input pin (T0CKI only).....................................................................................................................±500 µA

Input Clamp Current, IIK (VI < 0 or VI > VDD) ....................................................................................................................±20 mA

Output Clamp Current, IOK (VO < 0 or VO > VDD)............................................................................................................±20 mA

Max. Output Current sunk by any I/O pin................................................................................................................25 mA

Max. Output Current sourced by any I/O pin...........................................................................................................20 mA

Max. Output Current sourced by a single I/O port (PORTA, B or C) .......................................................................40 mA

Max. Output Current sunk by a single I/O port (PORTA, B or C) ............................................................................50 mA

Note 1: Power Dissipation is calculated as follows: Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)

Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.Thus,

a series resistor of 50 to 100 Ω should be used when applying a “low” level to the MCLR pin rather than pull-

ing this pin directly to VSS

†

NOTICE: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This

is a stress rating only and functional operation of the device at those or any other conditions above those indicated

in the operation listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 67

PIC16C5X

PIC16C54/55/56/57

TABLE 11-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

(RC, XT & 10) AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

OSC

PIC16C5X-RC

VDD: 3.0 V to 6.25 V

PIC16C5X-XT

PIC16C5X-10

IDD: 3.3 mA max. at 5. V

IPD: 9 µA max. at 3.0 V, WDT dis

Freq: 4 MHz max.

RC

N/A

VDD: 3.0V to 6.25V

IDD: 1.8 mA typ. at 5.5V

IPD: 0.6 µA typ. at 3.0V WDT dis

Freq: 4 MHz max.

IDD: 3.3 mA max. at 5.5V

IPD: 9 µA max. at 3.0V, WDT dis

Freq: 4 MHz max.

XT

HS

LP

N/A

VDD: 4.5V to 5.5V

IDD: 10 mA max. at 5.5V

IPD: 9 µA max. at 3.0V, WDT dis

Freq: 10 MHz max.

N/A

VDD: 2.5V to 6.25V

IDD: 15 µA typ. at 3.0V

IPD: 0.6 µA typ. at 3.0V, WDT dis

Freq: 40 kHz max.

IDD: 15 µA typ. at 3.0V

IPD: 0.6 µA typ. at 3.0V, WDT dis

Freq: 40 kHz max.

IDD: 15 µA typ. at 3.0V

IPD: 0.6 µA typ. at 3.0V, WDT dis

Freq: 40 kHz max.

The shaded sections indicate oscillator selections which should work by design, but are not tested. It is recommended

that the user select the device type from information in unshaded sections.

TABLE 11-2: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

(HS, LP & JW) AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

OSC

PIC16C5X-HS

PIC16C5X-LP

PIC16C5X/JW

VDD: 3.0V to 6.25V

IDD: 3.3 mA max. at 5.5V

IPD: 9 µA max. at 3.0V, WDT dis

Freq: 4 MHz max.

RC

N/A

VDD: 3.0V to 6.25V

IDD: 3.3 mA max. at 5.5V

IPD: 9 µA max. at 3.0V, WDT dis

Freq: 4 MHz max.

XT

HS

LP

N/A

VDD: 4.5V to 5.5V

IDD: 20 mA max. at 5.5V

IPD: 9 µA max. at 3.0V, WDT dis

Freq: 20 MHz max.

IDD: 20 mA max. at 5.5V

IPD: 9 µA max. at 3.0V, WDT dis

Freq: 20 MHz max.

VDD: 2.5V to 6.25V

IDD: 15 µA typ. at 3.0V

IPD: 0.6 µA typ. at 3.0V, WDT dis

Freq: 40 kHz max.

IDD: 32 µA max. at 32 kHz, 3.0V

IPD: 9 µA max. at 3.0V, WDT dis

Freq: 40 kHz max.

IDD: 32 µA max. at 32 kHz, 3.0V

IPD: 9 µA max. at 3.0V, WDT dis

Freq: 40 kHz max.

The shaded sections indicate oscillator selections which should work by design, but are not tested. It is recommended

that the user select the device type from information in unshaded sections.

DS30453B-page 68

Preliminary

1998 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

11.1

DC Characteristics: PIC16C54/55/56/57-RC, XT, 10, HS, LP (Commercial)

DC Characteristics

Power Supply Pins

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature 0°C ≤ TA ≤ +70°C

(1)

Characteristic

Sym Min

Typ

Max Units

Conditions

Supply Voltage

PIC16C5X-RC

PIC16C5X-XT

PIC16C5X-10

PIC16C5X-HS

PIC16C5X-LP

VDD

3.0

4.5

2.5

—

6.25

5.5

6.25

V

FOSC = DC to 4 MHz

FOSC = DC to 10 MHz

FOSC = DC to 20 MHz

FOSC = DC to 40 kHz

(2)

RAM Data Retention Voltage

VDR

1.5*

VSS

—

V

Device in SLEEP Mode

VDD Start Voltage to ensure

Power-On Reset

VPOR

See Section 7.4 for details on

Power-On Reset

VDD Rise Rate to ensure

Power-On Reset

SVDD 0.05*

—

V/ms See Section 7.4 for details on

Power-On Reset

(3)

Supply Current

PIC16C5X-RC

PIC16C5X-XT

PIC16C5X-10

PIC16C5X-HS

IDD

—

(4)

1.8

4.8

9.0

15

3.3

10

20

32

mA

µA

FOSC = 4 MHz, VDD = 5.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 20 MHz, VDD = 5.5V

FOSC = 32 kHz, VDD = 3.0V,

WDT disabled

PIC16C5X-LP

(5)

Power Down Current

IPD

—

4.0

0.6

12

9

µA

VDD = 3.0V, WDT enabled

VDD = 3.0V, WDT disabled

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C.This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as speciﬁed.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: IR = VDD/2Rext (mA) with Rext in kΩ.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 69

PIC16C5X

PIC16C54/55/56/57

11.2

DC Characteristics: PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI (Industrial)

DC Characteristics

Power Supply Pins

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature –40°C ≤ TA ≤ +85°C

(1)

Characteristic

Sym Min

Typ

Max Units

Conditions

Supply Voltage

PIC16C5X-RCI

PIC16C5X-XTI

PIC16C5X-10I

PIC16C5X-HSI

PIC16C5X-LPI

VDD

3.0

4.5

2.5

—

6.25

5.5

6.25

V

FOSC = DC to 4 MHz

FOSC = DC to 10 MHz

FOSC = DC to 20 MHz

FOSC = DC to 40 kHz

(2)

RAM Data Retention Voltage

VDR

—

1.5*

VSS

—

V

Device in SLEEP mode

VDD Start Voltage to ensure

Power-On Reset

VPOR

See Section 7.4 for details on

Power-On Reset

VDD Rise Rate to ensure

Power-On Reset

SVDD 0.05*

—

V/ms See Section 7.4 for details on

Power-On Reset

(3)

Supply Current

PIC16C5X-RCI

PIC16C5X-XTI

PIC16C5X-10I

PIC16C5X-HSI

IDD

—

(4)

1.8

4.8

9.0

15

3.3

10

20

40

mA

µA

FOSC = 4 MHz, VDD = 5.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 20 MHz, VDD = 5.5V

FOSC = 32 kHz, VDD = 3.0V,

WDT disabled

PIC16C5X-LPI

(5)

Power Down Current

IPD

—

4.0

0.6

14

12

µA

VDD = 3.0V, WDT enabled

VDD = 3.0V, WDT disabled

—

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C.This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as speciﬁed.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: IR = VDD/2Rext (mA) with Rext in kΩ.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

DS30453B-page 70

Preliminary

1998 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

11.3

DC Characteristics: PIC16C54/55/56/57-RCE, XTE, 10E, HSE, LPE (Extended)

DC Characteristics

Power Supply Pins

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature –40°C ≤ TA ≤ +125°C

(1)

Characteristic

Sym Min

Typ

Max Units

Conditions

Supply Voltage

PIC16C5X-RCE

PIC16C5X-XTE

PIC16C5X-10E

PIC16C5X-HSE

PIC16C5X-LPE

VDD

3.25

4.5

—

6.0

5.5

6.0

V

FOSC = DC to 4 MHz

—

FOSC = DC to 4 MHz

FOSC = DC to 10 MHz

FOSC = DC to 16 MHz

FOSC = DC to 40 kHz

4.5

2.5

(2)

RAM Data Retention Voltage

VDR

—

1.5*

VSS

—

V

Device in SLEEP mode

VDD Start Voltage to ensure

Power-On Reset

VPOR

See Section 7.4 for details on

Power-On Reset

VDD rise rate to ensure

Power-On Reset

SVDD 0.05*

—

V/ms See Section 7.4 for details on

Power-On Reset

(3)

Supply Current

PIC16C5X-RCE

PIC16C5X-XTE

PIC16C5X-10E

PIC16C5X-HSE

IDD

—

(4)

1.8

4.8

9.0

19

3.3

10

20

55

mA

µA

FOSC = 4 MHz, VDD = 5.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 16 MHz, VDD = 5.5V

FOSC = 32 kHz, VDD = 3.25V,

WDT disabled

PIC16C5X-LPE

(5)

Power Down Current

IPD

—

5.0

0.8

22

18

µA

VDD = 3.25V, WDT enabled

VDD = 3.25V, WDT disabled

—

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C.This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as speciﬁed.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: IR = VDD/2Rext (mA) with Rext in kΩ.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 71

PIC16C5X

PIC16C54/55/56/57

11.4

DC Characteristics: PIC16C54/55/56/57-RC, XT, 10, HS, LP (Commercial)

PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI (Industrial)

Standard Operating Conditions (unless otherwise speciﬁed)

DC Characteristics

All Pins Except

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

Power Supply Pins

Operating Voltage VDD range is described in Section 11.1, Section 11.2 and

Section 11.3.

(1)

Characteristic

Sym

Min

Typ

Max

Units

Conditions

Input Low Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

VIL

VSS

—

0.2 VDD

0.15 VDD

0.3 VDD

V

Pin at hi-impedance

(4)

PIC16C5X-RC only

PIC16C5X-XT, 10, HS, LP

Input High Voltage

I/O ports

VIH

(5)

0.45 VDD

2.0

—

VDD

V

For all VDD

(5)

4.0V < VDD ≤ 5.5V

VDD > 5.5V

0.36 VDD

0.85 VDD

0.7 VDD

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

(4)

PIC16C5X-RC only

PIC16C5X-XT, 10, HS, LP

Hysteresis of Schmitt

Trigger inputs

VHYS

IIL

0.15VDD*

—

V

(2,3)

Input Leakage Current

For VDD ≤ 5.5V

I/O ports

–1

–5

0.5

+1

µA

VSS ≤ VPIN ≤ VDD,

Pin at hi-impedance

VPIN = VSS + 0.25V

VPIN = VDD

VSS ≤ VPIN ≤ VDD

VSS ≤ VPIN ≤ VDD,

PIC16C5X-XT, 10, HS, LP

MCLR

µA

0.5

+5

+3

T0CKI

OSC1

–3

Output Low Voltage

I/O ports

OSC2/CLKOUT

VOL

VOH

—

0.6

V

IOL = 8.7 mA, VDD = 4.5V

IOL = 1.6 mA, VDD = 4.5V,

PIC16C5X-RC

Output High Voltage

(3)

I/O ports

VDD – 0.7

—

V

IOH = –5.4 mA, VDD = 4.5V

IOH = –1.0 mA, VDD = 4.5V,

PIC16C5X-RC

OSC2/CLKOUT

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C.This data is for design guidance

only and is not tested.

2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The speciﬁed

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltage.

3: Negative current is deﬁned as coming out of the pin.

4: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the

PIC16C5X be driven with external clock in RC mode.

5: The user may use the better of the two speciﬁcations.

DS30453B-page 72

Preliminary

1998 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

11.5

DC Characteristics: PIC16C54/55/56/57-RC, XT, 10, HS, LP (Extended)

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature –40°C ≤ TA ≤ +125°C

Operating Voltage VDD range is described in Section 11.1, Section 11.2 and

Section 11.3.

DC Characteristics

All Pins Except

Power Supply Pins

(1)

Characteristic

Sym

Min

Typ

Max

Units

Conditions

Input Low Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

VIL

Vss

—

0.15 VDD

0.3 VDD

V

Pin at hi-impedance

(4)

PIC16C5X-RC only

PIC16C5X-XT, 10, HS, LP

Input High Voltage

I/O ports

VIH

(5)

0.45 VDD

2.0

—

VDD

V

For all VDD

(5)

4.0V < VDD ≤ 5.5V

VDD > 5.5 V

0.36 VDD

0.85 VDD

0.7 VDD

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

(4)

PIC16C5X-RC only

PIC16C5X-XT, 10, HS, LP

Hysteresis of Schmitt

Trigger inputs

VHYS

IIL

0.15VDD*

—

V

(2,3)

Input Leakage Current

For VDD ≤ 5.5 V

I/O ports

–1

–5

0.5

+1

µA

VSS ≤ VPIN ≤ VDD,

Pin at hi-impedance

VPIN = VSS + 0.25V

VPIN = VDD

VSS ≤ VPIN ≤ VDD

VSS ≤ VPIN ≤ VDD,

PIC16C5X-XT, 10, HS, LP

MCLR

µA

0.5

+5

+3

T0CKI

OSC1

–3

Output Low Voltage

I/O ports

OSC2/CLKOUT

VOL

VOH

—

0.6

V

IOL = 8.7 mA, VDD = 4.5V

IOL = 1.6 mA, VDD = 4.5V,

PIC16C5X-RC

Output High Voltage

(3)

I/O ports

VDD – 0.7

—

V

IOH = –5.4 mA, VDD = 4.5V

IOH = –1.0 mA, VDD = 4.5V,

PIC16C5X-RC

OSC2/CLKOUT

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C.This data is for design guidance

only and is not tested.

2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The speciﬁed

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltage.

3: Negative current is deﬁned as coming out of the pin.

4: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the

PIC16C5X be driven with external clock in RC mode.

5: The user may use the better of the two speciﬁcations.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 73

PIC16C5X

PIC16C54/55/56/57

11.6

Timing Parameter Symbology and Load Conditions

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase subscripts (pp) and their meanings:

pp

T

Time

2

to

mc

osc

os

MCLR

oscillator

OSC1

ck

cy

drt

io

CLKOUT

cycle time

device reset timer

I/O port

t0

T0CKI

wdt

watchdog timer

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (Hi-impedance)

Low

Valid

L

Hi-impedance

FIGURE 11-1: LOAD CONDITIONS - PIC16C54/55/56/57

CL = 50 pF for all pins except OSC2

CL

15 pF for OSC2 in XT, HS or LP

modes when external clock

is used to drive OSC1

VSS

DS30453B-page 74

Preliminary

1998 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

11.7

Timing Diagrams and Speciﬁcations

FIGURE 11-2: EXTERNAL CLOCK TIMING - PIC16C54/55/56/57

Q4

Q3

Q4

4

Q1

Q2

OSC1

1

3

4

2

CLKOUT

TABLE 11-3: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 11.1, Section 11.2 and Section 11.3

Parameter

No.

(1)

Sym

Characteristic

Min Typ

Max Units

Conditions

(2)

FOSC

External CLKIN Frequency

DC

0.1

4

—

4

MHz XT osc mode

MHz 10 MHz mode

10

20

16

40

4

MHz HS osc mode (Com/Indust)

MHz HS osc mode (Extended)

kHz LP osc mode

(2)

Oscillator Frequency

MHz RC osc mode

4

MHz XT osc mode

10

20

16

40

MHz 10 MHz mode

4

MHz HS osc mode (Com/Indust)

MHz HS osc mode (Extended)

kHz LP osc mode

4

DC

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated.These parameters are for design guidance only

and are not tested.

2: All speciﬁed values are based on characterization data for that particular oscillator type under standard operating

conditions with the device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation

and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruction cycle period (TCY) equals four times the input oscillator time base period.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 75

PIC16C5X

PIC16C54/55/56/57

TABLE 11-3: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57 (CON’T)

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 11.1, Section 11.2 and Section 11.3

Parameter

(1)

No.

Sym

Characteristic

Min Typ

Max Units

Conditions

XT osc mode

(2)

1

TOSC

External CLKIN Period

250

100

50

—

ns

µs

ns

µs

—

ns

µs

ns

10 MHz mode

—

HS osc mode (Com/Indust)

HS osc mode (Extended)

LP osc mode

62.5

25

—

(2)

Oscillator Period

250

100

50

—

RC osc mode

—

10,000

250

—

XT osc mode

—

10 MHz mode

—

HS osc mode (Com/Indust)

HS osc mode (Extended)

LP osc mode

62.5

25

—

(3)

2

3

TCY

Instruction Cycle Time

—

4/FOSC

—

TosL, TosH Clock in (OSC1) Low or High Time

85*

20*

2*

—

XT oscillator

HS oscillator

LP oscillator

XT oscillator

HS oscillator

LP oscillator

—

4

TosR, TosF Clock in (OSC1) Rise or Fall Time

—

25*

50*

—

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated.These parameters are for design guidance only

and are not tested.

2: All speciﬁed values are based on characterization data for that particular oscillator type under standard operating

conditions with the device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation

and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruction cycle period (TCY) equals four times the input oscillator time base period.

DS30453B-page 76

Preliminary

1998 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

FIGURE 11-3: CLKOUT AND I/O TIMING - PIC16C54/55/56/57

Q1

Q2

Q3

Q4

OSC1

10

11

CLKOUT

13

12

16

18

14

19

I/O Pin

(input)

15

17

I/O Pin

(output)

New Value

Old Value

20, 21

Note: All tests must be done with speciﬁed capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

TABLE 11-4: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54/55/56/57

AC Characteristics

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 11.1, Section 11.2 and

Section 11.3

Parameter

(1)

No.

Sym

Characteristic

(2)

Min

Typ

Max

Units

10

11

12

13

14

15

16

17

18

TosH2ckL

TosH2ckH

TckR

OSC1↑ to CLKOUT↓

—

15

5

30**

15**

40**

—

ns

(2)

OSC1↑ to CLKOUT↑

—

(2)

CLKOUT rise time

—

(2)

TckF

CLKOUT fall time

—

5

(2)

CLKOUT↓ to Port out valid

TckL2ioV

TioV2ckH

TckH2ioI

TosH2ioV

TosH2ioI

—

(2)

Port in valid before CLKOUT↑

(2)

0.25 TCY+30*

Port in hold after CLKOUT↑

OSC1↑ (Q1 cycle) to Port out valid

0*

—

(3)

100*

—

OSC1↑ (Q2 cycle) to Port input invalid

TBD

(I/O in hold time)

19

TioV2osH

Port input valid to OSC1↑

TBD

—

ns

(I/O in setup time)

(3)

20

21

TioR

TioF

Port output rise time

—

10

25**

ns

(3)

Port output fall time

*

These parameters are characterized but not tested.

** These parameters are design targets and are not tested. No characterization data available at this time.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

3: See Figure 11-1 for loading conditions.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 77

PIC16C5X

PIC16C54/55/56/57

FIGURE 11-4: RESET, WATCHDOG TIMER, AND

DEVICE RESET TIMER TIMING - PIC16C54/55/56/57

VDD

MCLR

30

Internal

POR

32

DRT

Time-out

Internal

RESET

Watchdog

Timer

RESET

31

34

I/O pin

(Note 1)

Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.

TABLE 11-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54/55/56/57

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 11.1, Section 11.2 and Section 11.3

Parameter

No.

(1)

Sym Characteristic

Min Typ

Max Units

Conditions

30

31

TmcL MCLR Pulse Width (low)

100*

9*

—

ns VDD = 5.0V

Twdt Watchdog Timer Time-out Period

(No Prescaler)

18*

30*

ms VDD = 5.0V (Commercial)

32

34

TDRT Device Reset Timer Period

9*

—

18*

—

30*

ms VDD = 5.0V (Commercial)

ns

TioZ I/O Hi-impedance from MCLR Low

100*

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

DS30453B-page 78

Preliminary

1998 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

FIGURE 11-5: TIMER0 CLOCK TIMINGS - PIC16C54/55/56/57

T0CKI

40

41

42

TABLE 11-6: TIMER0 CLOCK REQUIREMENTS - PIC16C54/55/56/57

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 11.1, Section 11.2 and

Section 11.3

Parameter

(1)

Sym Characteristic

Min

Typ

Max Units Conditions

No.

40

Tt0H T0CKI High Pulse Width - No Prescaler

- With Prescaler

0.5 TCY + 20*

10*

—

ns

41

42

Tt0L T0CKI Low Pulse Width - No Prescaler

- With Prescaler

0.5 TCY + 20*

10*

Tt0P T0CKI Period

20 or TCY + 40*

N

ns Whichever is greater.

N = Prescale Value

(1, 2, 4,..., 256)

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated.These parameters are for design guidance only

and are not tested.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 79

PIC16C5X

PIC16C54/55/56/57

NOTES:

DS30453B-page 80

Preliminary

1998 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

12.0 DC AND AC CHARACTERISTICS - PIC16C54/55/56/57

The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables the

data presented are outside speciﬁed operating range (e.g., outside speciﬁed VDD range). This is for information only

and devices will operate properly only within the speciﬁed range.

The data presented in this section is a statistical summary of data collected on units from different lots over a period of

time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean – 3σ)

respectively, where σ is standard deviation.

FIGURE 12-1: TYPICAL RC OSCILLATOR FREQUENCY vs.TEMPERATURE

FOSC

Frequency normalized to +25°C

FOSC (25°C)

1.10

Rext ≥ 10 kΩ

Cext = 100 pF

1.08

1.06

1.04

1.02

1.00

0.98

0.96

0.94

VDD = 5.5 V

VDD = 3.5 V

0.92

0.90

0.88

0

10

20

25

30

40

50

60

70

T(°C)

TABLE 12-1: RC OSCILLATOR FREQUENCIES

Average

Fosc @ 5 V, 25°C

Cext

Rext

20 pF

3.3 k

5 k

4.973 MHz

3.82 MHz

2.22 MHz

262.15 kHz

1.63 MHz

1.19 MHz

684.64 kHz

71.56 kHz

660 kHz

± 27%

± 21%

± 31%

± 13%

± 18%

± 25%

± 10%

± 14%

± 15%

± 19%

10 k

100 k

3.3 k

5 k

100 pF

300 pF

10 k

100 k

3.3 k

5.0 k

10 k

160 k

484.1 kHz

267.63 kHz

29.44 kHz

The frequencies are measured on DIP packages.

The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation

indicated is ±3 standard deviation from average value for VDD = 5 V.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 81

PIC16C5X

PIC16C54/55/56/57

FIGURE 12-2: TYPICAL RC OSCILLATOR

FREQUENCY vs. VDD,

FIGURE 12-3: TYPICAL RC OSCILLATOR

FREQUENCY vs. VDD,

CEXT = 20 PF

CEXT = 100 PF

5.5

1.8

R = 3.3k

5.0

1.6

4.5

1.4

R = 5k

4.0

1.2

1.0

3.5

3.0

0.8

R = 10k

2.5

0.6

Measured on DIP Packages, T = 25°C

2.0

0.4

Measured on DIP Packages, T = 25°C

0.2

1.5

R = 100k

0.0

1.0

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (Volts)

R = 100k

0.5

FIGURE 12-4: TYPICAL RC OSCILLATOR

FREQUENCY vs. VDD,

0.0

CEXT = 300 PF

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (Volts)

800

700

R = 3.3k

600

R = 5k

500

400

300

200

100

0

R = 10k

Measured on DIP Packages, T = 25°C

R = 100k

5.5 6.0

3.0

3.5

4.0

4.5

5.0

VDD (Volts)

DS30453B-page 82

Preliminary

1998 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

FIGURE 12-5: TYPICAL IPD vs. VDD,

WATCHDOG DISABLED

FIGURE 12-7: TYPICAL IPD vs. VDD,

WATCHDOG ENABLED

2.5

20

18

16

2.0

14

12

T = 25°C

1.5

10

8

1.0

0.5

6

4

2

0

0.0

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (Volts)

FIGURE 12-6: MAXIMUM IPD vs. VDD,

WATCHDOG DISABLED

FIGURE 12-8: MAXIMUM IPD vs. VDD,

WATCHDOG ENABLED

60

100

50

+125˚C

+85˚C

10

40

–55°C

+70˚C

0˚C

+85°C

30

–40˚C

+125°C

–40°C

+70°C

–55˚C

1

20

10

0

0°C

0

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

VDD (Volts)

IPD, with WDT enabled, has two components:

The leakage current which increases with higher temperature

and the operating current of the WDT logic which increases

with lower temperature. At –40°C, the latter dominates

explaining the apparently anomalous behavior.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 83

PIC16C5X

PIC16C54/55/56/57

FIGURE 12-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD

2.00

1.80

1.60

1.40

1.20

1.00

0.80

0.60

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (Volts)

FIGURE 12-10: VIH, VIL OF MCLR,T0CKI AND OSC1 (IN RC MODE) vs. VDD

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

2.5

3.0

3.5

4.0

4.5

VDD (Volts)

5.0

5.5

6.0

Note: These input pins have Schmitt Trigger input buffers.

FIGURE 12-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT

(IN XT, HS, AND LP MODES) vs. VDD

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (Volts)

DS30453B-page 84

Preliminary

1998 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

FIGURE 12-12: TYPICAL IDD vs. FREQUENCY (EXTERNAL CLOCK, 25°C)

10

1.0

0.1

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

0.01

10k

100k

1M

10M

100M

External Clock Frequency (Hz)

FIGURE 12-13: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK, –40°C TO +85°C)

10

1.0

7.0

6.5

6.0

0.1

5.5

5.0

4.5

4.0

3.5

3.0

2.5

0.01

10k

100k

1M

10M

100M

External Clock Frequency (Hz)

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 85

PIC16C5X

PIC16C54/55/56/57

FIGURE 12-14: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK –55°C TO +125°C)

10

1.0

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

0.1

2.5

0.01

10k

100k

1M

10M

100M

External Clock Frequency (Hz)

FIGURE 12-15: WDT TIMER TIME-OUT

PERIOD vs. VDD

FIGURE 12-16: TRANSCONDUCTANCE (gm)

OF HS OSCILLATOR vs. VDD

50

45

40

9000

8000

Max –40°C

7000

6000

35

30

5000

Max +85°C

Typ +25°C

25

4000

3000

Max +70°C

20

Typ +25°C

Min +85°C

15

2000

MIn 0°C

10

100

0

MIn –40°C

5

2

3

4

5

6

7

2

3

4

5

6

7

VDD (Volts)

DS30453B-page 86

Preliminary

1998 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

FIGURE 12-17: TRANSCONDUCTANCE (gm)

OF LP OSCILLATOR vs. VDD

FIGURE 12-19: TRANSCONDUCTANCE (gm)

OF XT OSCILLATOR vs. VDD

45

2500

40

Max –40°C

2000

35

30

1500

25

Typ +25°C

20

1000

15

Min +85°C

500

10

Min +85°C

5

0

2

3

4

5

6

7

2

3

4

5

6

7

VDD (Volts)

FIGURE 12-18: IOH vs. VOH, VDD = 3 V

FIGURE 12-20: IOH vs. VOH, VDD = 5 V

0

Min +85°C

–5

–10

Min +85°C

–10

–20

Typ +25°C

–15

Max –40°C

–30

Max –40°C

–20

–40

–25

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

0

0.5 1.0 1.5 2.0 2.5 3.0

VOH (Volts)

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 87

PIC16C5X

PIC16C54/55/56/57

FIGURE 12-21: IOL vs. VOL, VDD = 3 V

FIGURE 12-22: IOL vs. VOL, VDD = 5 V

90

80

70

45

Max –40°C

40

35

60

50

30

25

Typ +25°C

Min +85°C

40

20

Min +85°C

30

20

15

10

0

5

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0

0.0

0.5 1.0 1.5 2.0 2.5 3.0

VOL (Volts)

TABLE 12-2: INPUT CAPACITANCE FOR

PIC16C54/56

TABLE 12-3: INPUT CAPACITANCE FOR

PIC16C55/57

Typical Capacitance (pF)

18L PDIP

18L SOIC

28L PDIP

(600 mil)

28L SOIC

RA port

RB port

5.0

4.3

RA port

RB port

5.2

5.6

5.0

17.0

6.6

4.6

4.5

4.8

4.7

4.1

17.0

3.5

5.0

4.3

MCLR

17.0

4.0

17.0

3.5

RC port

OSC1

MCLR

OSC2/CLKOUT

T0CKI

4.3

3.5

OSC1

3.2

2.8

OSC2/CLKOUT

T0CKI

All capacitance values are typical at 25°C. A part-to-part

variation of ±25% (three standard deviations) should be

taken into account.

All capacitance values are typical at 25°C. A part-to-part

variation of ±25% (three standard deviations) should be

taken into account.

DS30453B-page 88

Preliminary

1998 Microchip Technology Inc.

PIC16CR54A

PIC16C5X

13.0 ELECTRICAL CHARACTERISTICS - PIC16CR54A

Absolute Maximum Ratings†

Ambient Temperature under bias ...........................................................................................................–55°C to +125°C

Storage Temperature..............................................................................................................................–65°C to +150°C

Voltage on VDD with respect to VSS ..................................................................................................................0 to +7.5V

(2)

Voltage on MCLR with respect to VSS ............................................................................................................0 to +14V

Voltage on all other pins with respect to VSS ................................................................................. –0.6V to (VDD + 0.6V)

(1)

Total Power Dissipation ....................................................................................................................................800 mW

Max. Current out of VSS pin...................................................................................................................................150 mA

Max. Current into VDD pin........................................................................................................................................50 mA

Max. Current into an input pin (T0CKI only).....................................................................................................................±500 µA

Input Clamp Current, IIK (VI < 0 or VI > VDD)....................................................................................................................±20 mA

Output Clamp Current, IOK (V0 < 0 or V0 > VDD).............................................................................................................±20 mA

Max. Output Current sunk by any I/O pin................................................................................................................25 mA

Max. Output Current sourced by any I/O pin...........................................................................................................20 mA

Max. Output Current sourced by a single I/O port (PORTA or B)............................................................................40 mA

Max. Output Current sunk by a single I/O port (PORTA or B).................................................................................50 mA

Note 1: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)

Note 2: Voltage spikes below Vss at the MCLR pin, inducing currents greater than 80 mA may cause latch-up.Thus,

a series resistor of 50 to 100Ω should be used when applying a low level to the MCLR pin rather than pulling

this pin directly to Vss.

†

NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 89

PIC16C5X

PIC16CR54A

TABLE 13-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

OSC

PIC16CR54A-04

PIC16CR54A-10

PIC16CR54A-20

PIC16LCR54A-04

RC

VDD: 2.5 V to 6.25 V

IDD: 3.6 mA max at 6.0 V

IPD: 6.0 µA max at 2.5 V,

WDT dis

N/A

Freq: 4 MHz max

XT

HS

LP

VDD: 2.5 V to 6.25 V

IDD: 3.6 mA max at 6.0 V

IPD: 6.0 µA max at 2.5 V,

WDT dis

N/A

Freq: 4.0 MHz max

VDD: 4.5 V to 5.5 V

IDD: 10 mA max at 5.5 V

IPD: 6.0 µA max at 2.5 V,

WDT dis

VDD: 4.5 V to 5.5 V

IDD: 10 mA max at 5.5 V

IPD: 6.0 µA max at 2.5 V,

WDT dis

N/A

Freq: 10 MHz max

Freq: 20 MHz max

VDD: 2.0 V to 6.25 V

IDD: 20 µA max at 32 kHz,

2.0 V

IPD: 6.0 µA max at 2.5 V,

WDT dis

N/A

Freq: 200 kHz max

The shaded sections indicate oscillator selections which should work by design, but are not tested. It is recommended

that the user select the device type from information in unshaded sections.

DS30453B-page 90

Preliminary

1998 Microchip Technology Inc.

PIC16CR54A

PIC16C5X

13.1

DC Characteristics: PIC16CR54A-04, 10, 20 (Commercial)

PIC16CR54A-04I, 10I, 20I (Industrial)

Standard Operating Conditions (unless otherwise speciﬁed)

DC Characteristics

Power Supply Pins

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

(1)

Characteristic

Sym

Min Typ

Max

Units

Conditions

Supply Voltage

RC and XT options

HS option

VDD

2.5

4.5

6.25

5.5

V

(2)

RAM Data Retention Voltage

VDR

—

1.5*

—

V

Device in SLEEP mode

VDD Start Voltage to ensure

Power-on Reset

VPOR

VSS

See Section 7.4 for details on

Power-on Reset

VDD Rise Rate to ensure

Power-on Reset

SVDD 0.05*

IDD

—

V/ms See Section 7.4 for details on

Power-on Reset

(3)

Supply Current

(4)

RC and XT options

2.0

0.8

90

4.8

9.0

3.6

1.8

350

10

mA

µA

FOSC = 4.0 MHz, VDD = 6.0V

FOSC = 4.0 MHz, VDD = 3.0V

FOSC = 200 kHz, VDD = 2.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 20 MHz, VDD = 5.5V

HS option

mA

20

(5)

Power-Down Current

Commercial

IPD

1.0

2.0

3.0

5.0

6.0

8.0*

15

µA

VDD = 2.5V, WDT disabled

VDD = 4.0V, WDT disabled

VDD = 6.0V, WDT disabled

VDD = 6.0V, WDT enabled

25

(5)

Power-Down Current

Industrial

1.0

2.0

3.0

5.0

8.0

10*

20*

18

µA

VDD = 2.5V, WDT disabled

VDD = 4.0V, WDT disabled

VDD = 4.0V, WDT enabled

VDD = 6.0V, WDT disabled

VDD = 6.0V, WDT enabled

45

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C.This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as speciﬁed.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: IR = VDD/2Rext (mA) with Rext in kΩ.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 91

PIC16C5X

PIC16CR54A

13.2

DC Characteristics: PIC16CR54A-04E, 10E, 20E (Extended)

DC Characteristics

Power Supply Pins

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

–40°C ≤ TA ≤ +125°C (extended)

(1)

Characteristic

Sym

Min Typ

Max Units

Conditions

Supply Voltage

RC, XT and LP options

HS options

VDD

3.25

4.5

—

6.0

5.5

V

(2)

RAM Data Retention Voltage

VDR

—

1.5*

VSS

—

V

Device in SLEEP mode

VDD Start Voltage to ensure

Power-on Reset

VPOR

See Section 7.4 for details on

Power-on Reset

VDD Rise Rate to ensure

Power-on Reset

SVDD 0.05*

—

V/ms See Section 7.4 for details on

Power-on Reset

(3)

Supply Current

IDD

—

(4)

RC and XT options

1.8

4.8

9.0

3.3

10

20

mA

FOSC = 4.0 MHz, VDD = 5.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 16 MHz, VDD = 5.5V

HS option

—

(5)

Power-Down Current

IPD

—

5.0

0.8

22

18

µA

VDD = 3.25V, WDT enabled

VDD = 3.25V, WDT disabled

—

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C.This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as speciﬁed.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: IR = VDD/2Rext (mA) with Rext in kΩ.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

DS30453B-page 92

Preliminary

1998 Microchip Technology Inc.

PIC16CR54A

PIC16C5X

13.3

DC Characteristics: PIC16LCR54A-04 (Commercial)

PIC16LCR54A-04I (Industrial)

Standard Operating Conditions (unless otherwise speciﬁed)

DC Characteristics

Power Supply Pins

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

(1)

Characteristic

Sym

Min Typ

Max

Units Conditions

Supply Voltage

VDD

VDR

2.0

—

6.25

—

V

LP Option

(2)

RAM Data Retention Voltage

1.5*

VSS

Device in SLEEP mode

VDD Start Voltage to ensure

Power-on Reset

VPOR

—

See Section 7.4 for details on

Power-on Reset

VDD Rise Rate to ensure

Power-on Reset

SVDD 0.05*

—

V/ms See Section 7.4 for details on

Power-on Reset

(3)

Supply Current

IDD

IPD

—

10

20

70

µA

FOSC = 32 kHz, VDD = 2.0V

FOSC = 32 kHz, VDD = 6.0V

(5)

Power-Down Current

Commercial

—

1.0

2.0

3.0

5.0

6.0

8.0*

15

µA

VDD = 2.5V, WDT disabled

VDD = 4.0V, WDT disabled

VDD = 6.0V, WDT disabled

VDD = 6.0V, WDT enabled

25

(5)

Power-Down Current

IPD

Industrial

—

1.0

2.0

3.0

5.0

8.0

10*

20*

18

µA

VDD = 2.5V, WDT disabled

VDD = 4.0V, WDT disabled

VDD = 4.0V, WDT enabled

VDD = 6.0V, WDT disabled

VDD = 6.0V, WDT enabled

45

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C.This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as speciﬁed.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: IR = VDD/2Rext (mA) with Rext in kΩ.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 93

PIC16C5X

PIC16CR54A

13.4

DC Characteristics: PIC16CR54A-04, 10, 20, PIC16LCR54A-04 (Commercial)

PIC16CR54A-04I, 10I, 20I, PIC16LCR54A-04I (Industrial)

Standard Operating Conditions (unless otherwise speciﬁed)

DC Characteristics

All Pins Except

Power Supply Pins

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

Operating Voltage VDD range is described in Section 13.1 and Section 13.3.

(1)

Characteristic

Sym

Min

Typ

Max

Units

Conditions

Input Low Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

VIL

VSS

—

0.2 VDD

0.15 VDD

V

Pin at hi-impedance

(4)

RC option only

XT, HS and LP options

Input High Voltage

I/O ports

VIH

(5)

2.0

—

VDD

V

VDD = 3.0V to 5.5V

Full VDD range

(5)

0.6 VDD

0.85 VDD

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

(4)

RC option only

XT, HS and LP options

Hysteresis of Schmitt

Trigger inputs

VHYS 0.15VDD*

—

V

(3)

Input Leakage Current

IIL

For VDD ≤ 5.5V

I/O ports

–1.0

+1.0

µA

VSS ≤ VPIN ≤ VDD,

Pin at hi-impedance

(2)

MCLR

–5.0

µA

VPIN = VSS + 0.25V

(2)

0.5

+5.0

+3.0

VPIN = VDD

T0CKI

OSC1

–3.0

VSS ≤ VPIN ≤ VDD

VSS ≤ VPIN ≤ VDD,

XT, HS and LP options

Output Low Voltage

I/O ports

OSC2/CLKOUT

VOL

—

0.5

V

IOL = 10 mA, VDD = 6.0V

IOL = 1.9 mA, VDD = 6.0V,

RC option only

—

(3)

Output High Voltage

VOH

I/O ports

OSC2/CLKOUT

VDD –0.5

—

V

IOH = –4.0 mA, VDD = 6.0V

IOH = –0.8 mA, VDD = 6.0V,

RC option only

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C.This data is for design guidance

only and is not tested.

2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The speciﬁed

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltage.

3: Negative current is deﬁned as coming out of the pin.

4: For the RC option, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X

be driven with external clock in RC mode.

5: The user may use the better of the two speciﬁcations.

DS30453B-page 94

Preliminary

1998 Microchip Technology Inc.

PIC16CR54A

PIC16C5X

13.5

DC Characteristics: PIC16CR54A-04E, 10E, 20E (Extended)

DC Characteristics

All Pins Except

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature –40°C ≤ TA ≤ +125°C

Power Supply Pins

Operating Voltage VDD range is described in Section 13.2.

(1)

Characteristic

Sym

Min

Typ

Max

Units

Conditions

Input Low Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

VIL

Vss

—

0.15 VDD

0.3 VDD

V

Pin at hi-impedance

(4)

RC option only

XT, HS and LP options

Input High Voltage

I/O ports

VIH

(5)

0.45 VDD

2.0

—

VDD

V

For all VDD

(5)

4.0V < VDD ≤ 5.5V

VDD > 5.5V

0.36 VDD

0.85 VDD

0.7 VDD

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

(4)

RC option only

XT, HS and LP options

Hysteresis of Schmitt

Trigger inputs

VHYS 0.15VDD*

—

V

(3)

Input Leakage Current

IIL

For VDD ≤ 5.5V

I/O ports

–1.0

0.5

+1.0

µA

VSS ≤ VPIN ≤ VDD,

Pin at hi-impedance

(2)

MCLR

–5.0

µA

VPIN = VSS + 0.25V

(2)

0.5

+5.0

+3.0

VPIN = VDD

T0CKI

OSC1

–3.0

VSS ≤ VPIN ≤ VDD

VSS ≤ VPIN ≤ VDD,

XT, HS and LP options

Output Low Voltage

I/O ports

OSC2/CLKOUT

VOL

—

0.6

V

IOL = 8.7 mA, VDD = 4.5V

IOL = 1.6 mA, VDD = 4.5V,

RC option only

—

(3)

Output High Voltage

I/O ports

VOH

VDD –0.7

—

V

IOH = –5.4 mA, VDD = 4.5V

IOH = –1.0 mA, VDD = 4.5V,

RC option only

OSC2/CLKOUT

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance

only and is not tested.

2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The speciﬁed

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltage.

3: Negative current is deﬁned as coming out of the pin.

4: For the RC option, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X

be driven with external clock in RC mode.

5: The user may use the better of the two speciﬁcations.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 95

PIC16C5X

PIC16CR54A

13.6

Timing Parameter Symbology and Load Conditions

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase subscripts (pp) and their meanings:

pp

T

Time

2

to

mc

osc

os

MCLR

ck

cy

drt

io

CLKOUT

cycle time

device reset timer

I/O port

oscillator

OSC1

t0

T0CKI

wdt

watchdog timer

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (Hi-impedance)

Low

Valid

L

Hi-impedance

FIGURE 13-1: LOAD CONDITIONS

CL = 50 pF for all pins except OSC2

CL

15 pF for OSC2 in XT, HS or LP

options when external clock

is used to drive OSC1

VSS

DS30453B-page 96

Preliminary

1998 Microchip Technology Inc.

PIC16CR54A

PIC16C5X

13.7

Timing Diagrams and Speciﬁcations

FIGURE 13-2: EXTERNAL CLOCK TIMING - PIC16CR54A

Q4

Q3

Q4

4

Q1

Q2

OSC1

1

3

4

2

CLKOUT

TABLE 13-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54A

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 13.1, Section 13.2 and Section 13.3.

Parameter

No.

(1)

Sym

Characteristic

Min Typ

Max Units

Conditions

(2)

FOSC

External CLKIN Frequency

DC

0.1

4.0

5.0

—

4.0

10

MHz XT osc mode

MHz HS osc mode (04)

MHz HS osc mode (10)

MHz HS osc mode (20)

kHz LP osc mode

20

200

4.0

10

(2)

Oscillator Frequency

MHz RC osc mode

MHz XT osc mode

MHz HS osc mode (04)

MHz HS osc mode (10)

MHz HS osc mode (20)

kHz LP osc mode

20

200

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated.These parameters are for design guidance only

and are not tested.

2: All speciﬁed values are based on characterization data for that particular oscillator type under standard operating

conditions with the device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation

and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruction cycle period (TCY) equals four times the input oscillator time base period.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 97

PIC16C5X

PIC16CR54A

TABLE 13-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54A (CON’T)

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 13.1, Section 13.2 and Section 13.3.

Parameter

(1)

No.

Sym

Characteristic

Min Typ

Max Units

Conditions

XT osc mode

(2)

1

TOSC

External CLKIN Period

250

100

50

—

ns

µs

ns

µs

—

ns

µs

ns

HS osc mode (04)

HS osc mode (10)

HS osc mode (20)

LP osc mode

—

5.0

250

100

50

—

(2)

Oscillator Period

—

RC osc mode

—

10,000

250

200

—

XT osc mode

—

HS osc mode (04)

HS osc mode (10)

HS osc mode (20)

LP osc mode

—

5.0

—

(3)

2

3

TCY

Instruction Cycle Time

4/FOSC

—

TosL, TosH Clock in (OSC1) Low or High Time

50*

20*

2.0*

—

XT oscillator

HS oscillator

LP oscillator

XT oscillator

HS oscillator

LP oscillator

—

4

TosR, TosF Clock in (OSC1) Rise or Fall Time

—

25*

50*

—

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated.These parameters are for design guidance only

and are not tested.

2: All speciﬁed values are based on characterization data for that particular oscillator type under standard operating

conditions with the device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation

and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruction cycle period (TCY) equals four times the input oscillator time base period.

DS30453B-page 98

Preliminary

1998 Microchip Technology Inc.

PIC16CR54A

PIC16C5X

FIGURE 13-3: CLKOUT AND I/O TIMING - PIC16CR54A

Q1

Q4

Q2

Q3

OSC1

10

11

CLKOUT

12

16

13

18

19

14

I/O Pin

(input)

15

17

I/O Pin

Old Value

(output)

New Value

20, 21

Note: All tests must be done with speciﬁed capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

TABLE 13-3: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16CR54A

AC Characteristics

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 13.1, Section 13.2 and

Section 13.3.

Parameter

(1)

No.

Sym

Characteristic

(2)

Min

Typ

Max

Units

10

11

12

13

14

15

16

17

18

TosH2ckL

TosH2ckH

TckR

OSC1↑ to CLKOUT↓

—

15

5.0

—

30**

15**

40**

—

ns

(2)

OSC1↑ to CLKOUT↑

—

(2)

CLKOUT rise time

—

(2)

TckF

CLKOUT fall time

—

(2)

CLKOUT↓ to Port out valid

TckL2ioV

TioV2ckH

TckH2ioI

TosH2ioV

TosH2ioI

—

(2)

Port in valid before CLKOUT↑

(2)

0.25 TCY+30*

—

Port in hold after CLKOUT↑

OSC1↑ (Q1 cycle) to Port out valid

0*

—

(3)

—

100*

—

OSC1↑ (Q2 cycle) to Port input invalid

TBD

—

(I/O in hold time)

19

TioV2osH

Port input valid to OSC1↑

TBD

—

ns

(I/O in setup time)

(3)

20

21

TioR

TioF

Port output rise time

—

10

25**

ns

(3)

Port output fall time

*

These parameters are characterized but not tested.

** These parameters are design targets and are not tested. No characterization data available at this time.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

3: See Figure 13-1 for loading conditions.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 99

PIC16C5X

PIC16CR54A

FIGURE 13-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16CR54A

VDD

MCLR

30

Internal

POR

32

DRT

Time-out

Internal

RESET

Watchdog

Timer

RESET

31

34

I/O pin

(Note 1)

Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.

TABLE 13-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16CR54A

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 13.1, Section 13.2 and Section 13.3.

Parameter

No.

(1)

Sym Characteristic

Min Typ

Max Units

Conditions

30

31

TmcL MCLR Pulse Width (low)

1.0*

7.0*

—

µs VDD = 5.0V

Twdt Watchdog Timer Time-out Period

(No Prescaler)

18*

40*

ms VDD = 5.0V (Commercial)

32

34

TDRT Device Reset Timer Period

7.0*

—

18*

—

30*

ms VDD = 5.0V (Commercial)

TioZ I/O Hi-impedance from MCLR Low

1.0*

µs

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

DS30453B-page 100

Preliminary

1998 Microchip Technology Inc.

PIC16CR54A

PIC16C5X

FIGURE 13-5: TIMER0 CLOCK TIMINGS - PIC16CR54A

T0CKI

40

41

42

TABLE 13-5: TIMER0 CLOCK REQUIREMENTS - PIC16CR54A

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 13.1, Section 13.2 and

Section 13.3.

Parameter

(1)

Sym Characteristic

Min

Typ

Max Units Conditions

No.

40

Tt0H T0CKI High Pulse Width - No Prescaler

- With Prescaler

0.5 TCY + 20*

10*

—

ns

41

42

Tt0L T0CKI Low Pulse Width - No Prescaler

- With Prescaler

0.5 TCY + 20*

10*

Tt0P T0CKI Period

20 or TCY + 40*

N

ns Whichever is greater.

N = Prescale Value

(1, 2, 4,..., 256)

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated.These parameters are for design guidance only

and are not tested.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 101

PIC16C5X

PIC16CR54A

NOTES:

DS30453B-page 102

Preliminary

1998 Microchip Technology Inc.

PIC16C54A

PIC16C5X

14.0 ELECTRICAL CHARACTERISTICS - PIC16C54A

†

Absolute Maximum Ratings

Ambient temperature under bias............................................................................................................–55°C to +125°C

Storage temperature ............................................................................................................................. –65°C to +150°C

Voltage on VDD with respect to VSS ..................................................................................................................0 to +7.5V

Voltage on MCLR with respect to VSS................................................................................................................0 to +14V

Voltage on all other pins with respect to VSS ................................................................................. –0.6V to (VDD + 0.6V)

(1)

Total power dissipation .....................................................................................................................................800 mW

Max. current out of VSS pin....................................................................................................................................150 mA

Max. current into VDD pin ......................................................................................................................................100 mA

Max. current into an input pin (T0CKI only)......................................................................................................................±500 µA

Input clamp current, IIK (VI < 0 or VI > VDD)....................................................................................................................±20 mA

Output clamp current, IOK (VO < 0 or VO > VDD) ..............................................................................................................±20 mA

Max. output current sunk by any I/O pin..................................................................................................................25 mA

Max. output current sourced by any I/O pin ............................................................................................................20 mA

Max. output current sourced by a single I/O port (PORTA or B) .............................................................................50 mA

Max. output current sunk by a single I/O port (PORTA or B)...................................................................................50 mA

Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)

†

NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 103

PIC16C5X

PIC16C54A

TABLE 14-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

OSC

PIC16C54A-04

PIC16C54A-10

PIC16C54A-20

PIC16LC54A-04

VDD: 3.0V to 6.25V

IDD: 2.4 mA max. at

5.5V

IPD: 4.0 µA max. at

3.0V WDT dis

VDD: 3.0V to 6.25V

IDD: 1.7 mA typ. at

5.5V

IPD: 0.25 µA typ. at

3.0V WDT dis

VDD: 3.0V to 6.25V

IDD: 1.7 mA typ. at

5.5V

IPD: 0.25 µA typ. at

3.0V WDT dis

VDD: 3.0V to 6.25V

IDD: 0.5 mA typ. at

5.5V

IPD: 0.25 µA typ. at

3.0V WDT dis

RC

Freq: 4 MHz max.

Freq: 4.0 MHz max.

VDD: 3.0V to 6.25V

IDD 2.4 mA max. at

5.5V

IPD: 4.0 µA max. at

3.0V WDT dis

VDD: 3.0V to 6.25V

IDD: 1.7 mA typ. at

5.5V

IPD: 0.25 µA typ. at

3.0V WDT dis

VDD: 3.0V to 6.25V

IDD: 1.7 mA typ. at

5.5V

IPD: 0.25 µA typ. at

3.0V WDT dis

VDD: 3.0V to 6.25V

IDD: 0.5 mA typ. at

5.5V

IPD: 0.25 µA typ. at

3.0V WDT dis

XT

HS

Freq: 4 MHz max.

Freq: 4.0 MHz max.

VDD: 4.5V to 5.5V

IDD: 8.0 mA max. at

5.5V

IPD: 4.0 µA max. at

3.0V WDT dis

VDD: 4.5V to 5.5V

IDD: 16 mA max. at

5.5V

IPD: 4.0 µA max. at

3.0V WDT dis

Do not use in

HS mode

N/A

Freq: 10 MHz max.

Freq: 20 MHz max.

VDD: 3.0V to 6.25V

IDD: 14 µA typ. at

32kHz, 3.0V

IPD: 0.25 µA typ. at

3.0V WDT dis

VDD: 2.5V to 6.25V

IDD: 27 µA max. at

32kHz, 2.5V

WDT dis

IPD: 4.0 µA max. at

2.5V WDT dis

Do not use in

LP mode

Do not use in

LP mode

LP

Freq: 200 kHz max.

The shaded sections indicate oscillator selections which should work by design, but are not

tested. It is recommended that the user select the device type from information in unshaded

sections.

OSC

PIC16C54A/JW

PIC16LV54A-02

VDD: 3.0V to 6.25V

IDD: 2.4 mA max. at

5.5V

IPD: 4.0 µA max. at

3.0V WDT dis

VDD: 2.0V to 3.8V

IDD: 0.5 mA typ. at

3.0V

IPD: 0.25 µA typ. at

3.0V WDT dis

RC

Freq: 4.0 MHz max.

Freq: 2.0 MHz max.

VDD: 3.0V to 6.25V

IDD 2.4 mA max. at

5.5V

IPD: 4.0 µA max. at

3.0V WDT dis

VDD: 2.0V to 3.8V

IDD: 0.5 mA typ. at

3.0V

IPD: 0.25 µA typ. at

3.0V WDT dis

XT

HS

Freq: 4.0 MHz max.

Freq: 2.0 MHz max.

VDD: 4.5V to 5.5V

IDD: 8 mA max. at

5.5V

IPD: 4.0 µA max. at

3.0V WDT dis

Do not use in

HS mode

Freq: 10 MHz max.

VDD: 2.5V to 6.25V

IDD: 27 µA max. at

32kHz, 2.5V

VDD: 2.0V to 3.8V

IDD: 27 µA max. at

32kHz, 2.5V

LP

WDT dis

IPD: 4.0 µA max. at

2.5V WDT dis

IPD: 4.0 µA max. at

2.5V WDT dis

Freq: 200 kHz max.

The shaded sections indicate oscillator selections

which should work by design, but are not tested. It

is recommended that the user select the device

type from information in unshaded sections.

DS30453B-page 104

Preliminary

1998 Microchip Technology Inc.

PIC16C54A

PIC16C5X

14.1

DC Characteristics: PIC16C54A-04, 10, 20 (Commercial)

PIC16C54A-04I, 10I, 20I (Industrial)

Standard Operating Conditions (unless otherwise speciﬁed)

DC Characteristics

Power Supply Pins

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

(1)

Characteristic

Sym Min Typ

Max Units

Conditions

Supply Voltage

XT, RC and LP options

HS option

VDD

3.0

4.5

—

6.25

5.5

V

(2)

RAM Data Retention Voltage

VDR

—

1.5*

VSS

—

V

Device in SLEEP mode

VDD start voltage to ensure

Power-On Reset

VPOR

See Section 7.4 for details on

Power-on Reset

VDD rise rate to ensure

Power-On Reset

SVDD

IDD

0.05*

—

V/ms See Section 7.4 for details on

Power-on Reset

(3)

Supply Current

(4)

XT and RC options

—

1.8

2.4

4.5

14

2.4 mA FOSC = 4.0 MHz, VDD = 5.5V

8.0 mA FOSC = 10 MHz, VDD = 5.5V

16

29

37

HS option

mA FOSC = 20 MHz, VDD = 5.5V

µA FOSC = 32 kHz, VDD = 3.0V, WDT disabled

LP option, Commercial

LP option, Industrial

17

(5)

Power Down Current

IPD

Commercial

—

4.0

0.25 4.0

5.0

0.3

12

µA VDD = 3.0V, WDT enabled

µA VDD = 3.0V, WDT disabled

µA VDD = 3.0V, WDT enabled

µA VDD = 3.0V, WDT disabled

Industrial

14

5.0

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C.This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as speciﬁed.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: IR = VDD/2Rext (mA) with Rext in kΩ.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 105

PIC16C5X

PIC16C54A

14.2

DC Characteristics: PIC16C54A-04E, 10E, 20E (Extended)

DC Characteristics

Power Supply Pins

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

–40°C ≤ TA ≤ +125°C (extended)

(1)

Characteristic

Sym Min Typ

Max Units Conditions

Supply Voltage

XT and RC options

HS option

VDD

3.5

4.5

—

5.5

V

(2)

RAM Data Retention Voltage

VDR

—

1.5*

VSS

—

V

Device in SLEEP mode

VDD start voltage to ensure

Power-On Reset

VPOR

See Section 7.4 for details on

Power-on Reset

VDD rise rate to ensure

Power-On Reset

SVDD

IDD

0.05*

—

V/ms See Section 7.4 for details on

Power-on Reset

(3)

Supply Current

(4)

XT and RC options

—

1.8

4.8

9.0

3.3 mA FOSC = 4.0 MHz, VDD = 5.5V

10

20

HS option

mA FOSC = 10 MHz, VDD = 5.5V

mA FOSC = 20 MHz, VDD = 5.5V

(5)

Power Down Current

IPD

XT and RC options

—

5.0

0.8

4.0

22

18

22

18

µA VDD = 3.5V, WDT enabled

µA VDD = 3.5V, WDT disabled

µA VDD = 3.5V, WDT enabled

µA VDD = 3.5V, WDT disabled

HS option

0.25

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C.This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as speciﬁed.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: IR = VDD/2Rext (mA) with Rext in kΩ.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

DS30453B-page 106

Preliminary

1998 Microchip Technology Inc.

PIC16C54A

PIC16C5X

14.3

DC Characteristics: PIC16LC54A-04 (Commercial)

PIC16LC54A-04I (Industrial)

PIC16LC54A-04E (Extended)

Standard Operating Conditions (unless otherwise speciﬁed)

DC Characteristics

Power Supply Pins

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

(1)

Characteristic

Sym Min Typ

Max Units

Conditions

Supply Voltage

VDD

XT, RC and LP options

2.5

—

6.25

—

V

(2)

RAM Data Retention Voltage

VDR

—

1.5*

VSS

Device in SLEEP mode

VDD start voltage to ensure

Power-On Reset

VPOR

—

See Section 7.4 for details on

Power-on Reset

VDD rise rate to ensure

Power-On Reset

SVDD

IDD

0.05*

—

V/ms See Section 7.4 for details on

Power-on Reset

(3)

Supply Current

(4)

XT and RC options

—

0.5

11

25

27

35

37

mA FOSC = 4.0 MHz, VDD = 5.5V

LP option, Commercial

LP option, Industrial

LP option, Extended

µA FOSC = 32 kHz, VDD = 2.5V WDT disabled

(5)

Power Down Current

IPD

Commercial

—

2.5

12

µA VDD = 2.5V, WDT enabled

µA VDD = 2.5V, WDT disabled

µA VDD = 2.5V, WDT enabled

µA VDD = 2.5V, WDT disabled

µA VDD = 2.5V, WDT enabled

µA VDD = 2.5V, WDT disabled

0.25 4.0

2.5 14

0.25 5.0

2.5 15

0.25 7.0

Industrial

Extended

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-

ance only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as speciﬁed.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: IR = VDD/2Rext (mA) with Rext in kΩ.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 107

PIC16C5X

PIC16C54A

14.4

DC Characteristics: PIC16LV54A-02 (Commercial)

PIC16LV54A-02 (Industrial)

Standard Operating Conditions (unless otherwise speciﬁed)

DC Characteristics

Power Supply Pins

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–20°C ≤ TA ≤ +85°C (industrial)

(1)

Characteristic

Sym Min Typ

Max Units Conditions

Supply Voltage

VDD

XT, RC and LP options

2.0

—

3.8

—

V

(2)

RAM Data Retention Voltage

VDR

—

1.5*

VSS

Device in SLEEP mode

VDD start voltage to ensure

Power-On Reset

VPOR

—

See Section 7.4 for details on

Power-on Reset

VDD rise rate to ensure

Power-On Reset

SVDD

IDD

0.05*

—

V/ms See Section 7.4 for details on

Power-on Reset

(3)

Supply Current

(4)

XT and RC options

—

0.5

11

14

—

27

35

mA FOSC = 2.0 MHz, VDD = 3.0V

µA FOSC = 32 kHz, VDD = 2.5V, WDT disabled

LP option, Commercial

LP option, Industrial

(5)(6)

Power Down Current

IPD

Commercial

—

2.5

0.25 4.0

3.5

0.3

12

µA VDD = 2.5V, WDT enabled

µA VDD = 2.5V, WDT disabled

µA VDD = 2.5V, WDT enabled

µA VDD = 2.5V, WDT disabled

Industrial

14

5.0

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C.This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as speciﬁed.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: IR = VDD/2Rext (mA) with Rext in kΩ.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

6: The oscillator start-up time can be as much as 8 seconds for XT and LP oscillator selection, if the SLEEP

mode is entered or during initial power-up.

DS30453B-page 108

Preliminary

1998 Microchip Technology Inc.

PIC16C54A

PIC16C5X

14.5

DC Characteristics: PIC16C54A-04, 10, 20, PIC16LC54A-04, PIC16LV54A-02 (Commercial)

PIC16C54A-04I, 10I, 20I, PIC16LC54A-04I, PIC16LV54A-02I (Industrial)

PIC16C54A-04E, 10E, 20E (Extended)

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

DC Characteristics

All Pins Except

Power Supply Pins

–20°C ≤ TA ≤ +85°C (industrial - PIC16LV54A-02I)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 14.1, Section 14.2 and

Section 14.3.

(1)

Characteristic

Sym

Min

Typ

Max

Units

Conditions

Input Low Voltage

VIL

I/O ports

VSS

—

0.2 VDD

0.8VDD

0.15 VDD

0.3 VDD

V

Pin at hi-impedance

4.0V < VDD ≤ 5.5V

(5)

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

(4)

RC option only

XT, HS and LP options

Input High Voltage

I/O ports

VIH

(5)

0.2 VDD+1V

2.0

0.85 VDD

0.7 VDD

—

VDD

V

For all VDD

(5)

4.0V < VDD ≤ 5.5V

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

(4)

RC option only

XT, HS and LP options

Hysteresis of Schmitt

Trigger inputs

VHYS 0.15VDD*

—

V

(3)

Input Leakage Current

IIL

For VDD ≤ 5.5V

I/O ports

-1.0

—

-5.0

0.5

—

0.5

+1.0

—

+5.0

+3.0

—

µA VSS ≤ VPIN ≤ VDD,

Pin at hi-impedance

—

(2)

MCLR

µA VPIN = VSS +0.25V

(2)

µA VPIN = VDD

T0CKI

OSC1

-3.0

µA VSS ≤ VPIN ≤ VDD

µA VSS ≤ VPIN ≤ VDD,

XT, HS and LP options

Output Low Voltage

I/O ports

OSC2/CLKOUT

VOL

VOH

—

0.6

V

IOL = 8.7 mA, VDD = 4.5V

IOL = 1.6 mA, VDD = 4.5V,

RC option only

Output High Voltage

(3)

I/O ports

VDD-0.7

—

V

IOH = -5.4 mA, VDD = 4.5V

IOH = -1.0 mA, VDD = 4.5V,

RC option only

OSC2/CLKOUT

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C.This data is for design guidance

only and is not tested.

2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The speciﬁed

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltage.

3: Negative current is deﬁned as coming out of the pin.

4: For the RC option, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X

be driven with external clock in RC mode.

5: The user may use the better of the two speciﬁcations.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 109

PIC16C5X

PIC16C54A

14.6

Timing Parameter Symbology and Load Conditions

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase subscripts (pp) and their meanings:

pp

T

Time

2

to

mc

osc

os

MCLR

ck

cy

drt

io

CLKOUT

cycle time

device reset timer

I/O port

oscillator

OSC1

t0

T0CKI

wdt

watchdog timer

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (Hi-impedance)

Low

Valid

L

Hi-impedance

FIGURE 14-1: LOAD CONDITIONS - PIC16C54A

CL = 50 pF for all pins except OSC2

CL

15 pF for OSC2 in XT, HS or LP

options when external clock

is used to drive OSC1

VSS

DS30453B-page 110

Preliminary

1998 Microchip Technology Inc.

PIC16C54A

PIC16C5X

14.7

Timing Diagrams and Speciﬁcations

FIGURE 14-2: EXTERNAL CLOCK TIMING - PIC16C54A

Q4

Q3

Q4

4

Q1

Q2

OSC1

1

3

4

2

CLKOUT

TABLE 14-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54A

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–20°C ≤ TA ≤ +85°C (industrial - PIC16LV54A-02I)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 14.1, Section 14.2 and Section 14.3.

Parameter

No.

(1)

Sym

Characteristic

Min Typ

Max Units

Conditions

(2)

FOSC

External CLKIN Frequency

DC

0.1

4

—

4.0

2.0

4.0

10

MHz XT osc mode

MHz XT osc mode (PIC16LV54A)

MHz HS osc mode (04)

MHz HS osc mode (10)

MHz HS osc mode (20)

kHz LP osc mode

20

200

4.0

2.0

4.0

2.0

4.0

10

(2)

Oscillator Frequency

MHz RC osc mode

MHz RC osc mode (PIC16LV54A)

MHz XT osc mode

MHz XT osc mode (PIC16LV54A)

MHz HS osc mode (04)

MHz HS osc mode (10)

MHz HS osc mode (20)

kHz LP osc mode

4

20

5

200

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

2: All speciﬁed values are based on characterization data for that particular oscillator type under standard operating condi-

tions with the device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation and/or

higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruction cycle period (TCY) equals four times the input oscillator time base period.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 111

PIC16C5X

PIC16C54A

TABLE 14-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54A (CON’T)

AC Characteristics

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–20°C ≤ TA ≤ +85°C (industrial - PIC16LV54A-02I)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 14.1, Section 14.2 and Section 14.3.

Parameter

(1)

No.

Sym

Characteristic

Min Typ

Max Units

Conditions

XT osc mode

(2)

1

TOSC

External CLKIN Period

250

500

250

100

50

—

ns

µs

ns

µs

—

ns

µs

ns

XT osc mode (PIC16LV54A)

HS osc mode (04)

HS osc mode (10)

HS osc mode (20)

LP osc mode

—

5.0

250

500

250

500

250

100

50

—

(2)

Oscillator Period

—

RC osc mode

—

RC osc mode (PIC16LV54A)

XT osc mode

—

10,000

—

XT osc mode (PIC16LV54A)

HS osc mode (04)

HS osc mode (10)

HS osc mode (20)

LP osc mode

—

250

200

—

5.0

—

(3)

2

3

TCY

Instruction Cycle Time

4/FOSC

—

TosL, TosH Clock in (OSC1) Low or High Time

85*

20*

2.0*

—

XT oscillator

HS oscillator

LP oscillator

XT oscillator

HS oscillator

LP oscillator

—

4

TosR, TosF Clock in (OSC1) Rise or Fall Time

—

25*

50*

—

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

2: All speciﬁed values are based on characterization data for that particular oscillator type under standard operating condi-

tions with the device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation and/or

higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruction cycle period (TCY) equals four times the input oscillator time base period.

DS30453B-page 112

Preliminary

1998 Microchip Technology Inc.

PIC16C54A

PIC16C5X

FIGURE 14-3: CLKOUT AND I/O TIMING - PIC16C54A

Q1

Q2

Q3

Q4

OSC1

10

11

CLKOUT

13

12

16

18

14

19

I/O Pin

(input)

15

17

I/O Pin

(output)

New Value

Old Value

20, 21

Note: All tests must be done with speciﬁed capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

TABLE 14-3: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54A

AC Characteristics

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–20°C ≤ TA ≤ +85°C (industrial - PIC16LV54A-02I)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 14.1, Section 14.2 and

Section 14.3.

Parameter

(1)

No.

Sym

Characteristic

(2)

Min

Typ

Max

Units

10

11

12

13

14

15

16

17

18

TosH2ckL

TosH2ckH

TckR

OSC1↑ to CLKOUT↓

—

15

5.0

—

30**

15**

40**

—

ns

(2)

OSC1↑ to CLKOUT↑

—

(2)

CLKOUT rise time

—

(2)

TckF

CLKOUT fall time

—

(2)

CLKOUT↓ to Port out valid

TckL2ioV

TioV2ckH

TckH2ioI

TosH2ioV

TosH2ioI

—

(2)

Port in valid before CLKOUT↑

(2)

0.25 TCY+30*

—

Port in hold after CLKOUT↑

OSC1↑ (Q1 cycle) to Port out valid

0*

—

(3)

—

100*

—

OSC1↑ (Q2 cycle) to Port input invalid

TBD

—

(I/O in hold time)

19

TioV2osH

Port input valid to OSC1↑

TBD

—

ns

(I/O in setup time)

(3)

20

21

TioR

TioF

Port output rise time

—

10

25**

ns

(3)

Port output fall time

*

These parameters are characterized but not tested.

** These parameters are design targets and are not tested. No characterization data available at this time.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

3: See Figure 14-1 for loading conditions.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 113

PIC16C5X

PIC16C54A

FIGURE 14-4: RESET, WATCHDOG TIMER, AND

DEVICE RESET TIMER TIMING - PIC16C54A

VDD

MCLR

30

Internal

POR

32

DRT

Time-out

Internal

RESET

Watchdog

Timer

RESET

31

34

I/O pin

(Note 1)

Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.

TABLE 14-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54A

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–20°C ≤ TA ≤ +85°C (industrial - PIC16LV54A-02I)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 14.1, Section 14.2 and Section 14.3.

Parameter

No.

(1)

Sym Characteristic

Min Typ

Max Units

Conditions

30

TmcL MCLR Pulse Width (low)

100*

1µs

—

ns VDD = 5.0V

—

VDD = 5.0V (PIC16LV54A only)

31

Twdt Watchdog Timer Time-out

Period (No Prescaler)

9.0*

18*

30*

ms VDD = 5.0V (Commercial)

32

34

TDRT Device Reset Timer Period

9.0*

18*

30*

ms VDD = 5.0V (Commercial)

ns

TioZ I/O Hi-impedance from MCLR

Low

—

100*

1µs

—

(PIC16LV54A only)

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

DS30453B-page 114

Preliminary

1998 Microchip Technology Inc.

PIC16C54A

PIC16C5X

FIGURE 14-5: TIMER0 CLOCK TIMINGS - PIC16C54A

T0CKI

40

41

42

TABLE 14-5: TIMER0 CLOCK REQUIREMENTS - PIC16C54A

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–20°C ≤ TA ≤ +85°C (industrial - PIC16LV54A-02I)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 14.1, Section 14.2 and

Section 14.3.

Parameter

(1)

Sym Characteristic

Min

Typ

Max Units Conditions

No.

40

Tt0H T0CKI High Pulse Width - No Prescaler

- With Prescaler

0.5 TCY + 20*

10*

—

ns

41

42

Tt0L T0CKI Low Pulse Width - No Prescaler

- With Prescaler

0.5 TCY + 20*

10*

Tt0P T0CKI Period

20 or TCY + 40*

N

ns Whichever is greater.

N = Prescale Value

(1, 2, 4,..., 256)

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 115

PIC16C5X

PIC16C54A

NOTES:

DS30453B-page 116

Preliminary

1998 Microchip Technology Inc.

PIC16CR57B

PIC16C5X

15.0 ELECTRICAL CHARACTERISTICS - PIC16CR57B

Absolute Maximum Ratings†

Ambient Temperature under bias ...........................................................................................................–55°C to +125°C

Storage Temperature..............................................................................................................................–65°C to +150°C

Voltage on VDD with respect to VSS ..................................................................................................................0 to +7.5V

Voltage on MCLR with respect to VSS................................................................................................................0 to +14V

Voltage on all other pins with respect to VSS ................................................................................. –0.6V to (VDD + 0.6V)

(1)

Total Power Dissipation ....................................................................................................................................800 mW

Max. Current out of VSS pin...................................................................................................................................150 mA

Max. Current into VDD pin......................................................................................................................................100 mA

Max. Current into an input pin (T0CKI only).....................................................................................................................±500 µA

Input Clamp Current, IIK (VI < 0 or VI > VDD) ...................................................................................................................±20 mA

Output Clamp Current, IOK (VO < 0 or VO > VDD) ............................................................................................................±20 mA

Max. Output Current sunk by any I/O pin................................................................................................................25 mA

Max. Output Current sourced by any I/O pin...........................................................................................................20 mA

Max. Output Current sourced by a single I/O port (PORTA, B or C) .......................................................................50 mA

Max. Output Current sunk by a single I/O port (PORTA, B or C) ............................................................................50 mA

Note 1: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)

†

NOTICE: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 117

PIC16C5X

PIC16CR57B

TABLE 15-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

OSC

PIC16CR57B-04

PIC16CR57B-10

PIC16CR57B-20

PIC16LCR57B-04

RC

VDD: 3.0V to 6.25V

IDD: 2.5 mA max at 5.5V

IPD: 4.0 µA max at 3.0V,

WDT dis

N/A

Freq: 4.0 MHz max

XT

HS

LP

VDD: 3.0V to 6.25V

IDD: 2.5 mA max at 5.5V

IPD: 4.0 µA max at 3.0V,

WDT dis

N/A

Freq: 4.0 MHz max

VDD: 4.5V to 5.5V

IDD: 10 mA max at 5.5V

IPD: 4.0 µA max at 3.0V,

WDT dis

IDD: 20 mA max at 5.5V

IPD: 4.0 µA max at 3.0V,

WDT dis

N/A

Freq: 10 MHz max

Freq: 20 MHz max

VDD: 2.5V to 6.25V

IDD: 32 µA max at 32 kHz,

2.5V

IPD: 4.0 µA max at 2.5V,

WDT dis

N/A

Freq: 200 kHz max

The shaded sections indicate oscillator selections which should work by design, but are not tested. It is recommended

that the user select the device type from information in unshaded sections.

DS30453B-page 118

Preliminary

1998 Microchip Technology Inc.

PIC16CR57B

PIC16C5X

15.1

DC Characteristics: PIC16CR57B-04, 10, 20 (Commercial)

PIC16CR57B-04I, 10I, 20I (Industrial)

Standard Operating Conditions (unless otherwise speciﬁed)

DC Characteristics

Power Supply Pins

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

(1)

Characteristic

Sym

Min Typ

Max

Units

Conditions

Supply Voltage

RC and XT options

HS option

VDD

3.0

4.5

—

6.25

5.5

V

(2)

RAM Data Retention Voltage

VDR

—

1.5*

VSS

—

V

Device in SLEEP mode

VDD Start Voltage to ensure

Power-on Reset

VPOR

See Section 7.4 for details on

Power-on Reset

VDD Rise Rate to ensure

Power-on Reset

SVDD 0.05*

—

V/ms See Section 7.4 for details on

Power-on Reset

(3)

Supply Current

IDD

—

(4)

RC and XT options

1.9

2.5

4.7

2.5

8.0

17

mA

FOSC = 4 MHz, VDD = 5.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 20 MHz, VDD = 5.5V

HS option

—

(5)

Power-Down Current

Commercial

IPD

—

4.0

0.25

4.0

12

4.0

14

µA

VDD = 3.0V, WDT enabled

VDD = 3.0V, WDT disabled

VDD = 3.0V, WDT enabled

VDD = 3.0V, WDT disabled

Industrial

0.25

5.0

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C.This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as speciﬁed.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: IR = VDD/2Rext (mA) with Rext in kΩ.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 119

PIC16C5X

PIC16CR57B

15.2

DC Characteristics: PIC16CR57B-04E, 10E, 20E (Extended)

DC Characteristics

Power Supply Pins

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

–40°C ≤ TA ≤ +125°C (extended)

(1)

Characteristic

Sym

Min Typ

Max Units

Conditions

Supply Voltage

RC and XT options

HS options

VDD

3.25

4.5

—

6.0

5.5

V

(2)

RAM Data Retention Voltage

VDR

—

1.5*

VSS

—

V

Device in SLEEP mode

VDD Start Voltage to ensure

Power-on Reset

VPOR

See Section 7.4 for details on

Power-on Reset

VDD Rise Rate to ensure

Power-on Reset

SVDD 0.05*

—

V/ms See Section 7.4 for details on

Power-on Reset

(3)

Supply Current

IDD

—

(4)

RC and XT options

1.9

4.8

9.0

3.3

10

20

mA

FOSC = 4 MHz, VDD = 5.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 20 MHz, VDD = 5.5V

HS option

—

(5)

Power-Down Current

IPD

—

5.0

0.8

22

18

µA

VDD = 3.25V, WDT enabled

VDD = 3.25V, WDT disabled

—

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design

guidance only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as speciﬁed.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: IR = VDD/2Rext (mA) with Rext in kΩ.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

DS30453B-page 120

Preliminary

1998 Microchip Technology Inc.

PIC16CR57B

PIC16C5X

15.3

DC Characteristics: PIC16LCR57B-04 (Commercial)

PIC16LCR57B-04I (Industrial)

Standard Operating Conditions (unless otherwise speciﬁed)

DC Characteristics

Power Supply Pins

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

(1)

Characteristic

Sym

Min Typ

Max

Units Conditions

Supply Voltage

VDD

VDR

2.5

—

6.25

—

V

LP option

(2)

RAM Data Retention Voltage

1.5*

VSS

Device in SLEEP mode

VDD Start Voltage to ensure

Power-on Reset

VPOR

—

See Section 7.4 for details on

Power-on Reset

VDD Rise Rate to ensure

Power-on Reset

SVDD 0.05*

—

V/ms See Section 7.4 for details on

Power-on Reset

(3)

Supply Current

Commercial

IDD

—

12

15

28

37

µA

FOSC = 32 kHz, VDD = 2.5V,

WDT disabled

FOSC = 32 kHz, VDD = 2.5V,

WDT disabled

Industrial

—

(5)

Power-Down Current

IPD

Commercial

3.5

0.2

3.5

0.2

12

4.0

14

µA

VDD = 2.5V, WDT enabled

VDD = 2.5V, WDT disabled

VDD = 2.5V, WDT enabled

VDD = 2.5V, WDT disabled

Industrial

5.0

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C.This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as speciﬁed.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: IR = VDD/2Rext (mA) with Rext in kΩ.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 121

PIC16C5X

PIC16CR57B

15.4

DC Characteristics: PIC16CR57B-04, 10, 20, PIC16LCR57B-04 (Commercial)

PIC16CR57B-04I, 10I, 20I, PIC16LCR57B-04I (Industrial)

Standard Operating Conditions (unless otherwise speciﬁed)

DC Characteristics

All Pins Except

Power Supply Pins

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

Operating Voltage VDD range is described in Section 15.1 and Section 15.3.

(1)

Characteristic

Sym

Min

Typ

Max

Units

Conditions

Input Low Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

VIL

VSS

—

0.2 VDD

0.15 VDD

0.3 VDD

V

Pin at hi-impedance

(4)

RC option only

XT, HS and LP options

Input High Voltage

I/O ports

VIH

(5)

0.45 VDD

2.0

—

VDD

V

For all VDD

(5)

4.0V < VDD ≤ 5.5V

VDD > 5.5V

0.36 VDD

0.85 VDD

0.7 VDD

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

(4)

RC option only

XT, HS and LP options

Hysteresis of Schmitt

Trigger inputs

VHYS 0.15VDD*

—

V

(3)

Input Leakage Current

IIL

For VDD ≤ 5.5V

I/O ports

–1.0

+1.0

µA

VSS ≤ VPIN ≤ VDD,

Pin at hi-impedance

(2)

MCLR

–5.0

—

µA

VPIN = VSS + 0.25V

(2)

0.5

+5.0

+3.0

VPIN = VDD

T0CKI

OSC1

–3.0

VSS ≤ VPIN ≤ VDD

VSS ≤ VPIN ≤ VDD,

XT, HS and LP options

Output Low Voltage

I/O ports

OSC2/CLKOUT

VOL

—

0.6

V

IOL = 8.7 mA, VDD = 4.5V

IOL = 1.6 mA, VDD = 4.5V,

RC option only

—

(3)

Output High Voltage

VOH

I/O ports

OSC2/CLKOUT

VDD –0.7

—

V

IOH = –5.4 mA, VDD = 4.5V

IOH = –1.0 mA, VDD = 4.5V,

RC option only

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C.This data is for design guidance

only and is not tested.

2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The speciﬁed

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltage.

3: Negative current is deﬁned as coming out of the pin.

4: For the RC option, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X

be driven with external clock in RC mode.

5: The user may use the better of the two speciﬁcations.

DS30453B-page 122

Preliminary

1998 Microchip Technology Inc.

PIC16CR57B

PIC16C5X

15.5

DC Characteristics: PIC16CR57B-04E, 10E, 20E (Extended)

DC Characteristics

All Pins Except

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature –40°C ≤ TA ≤ +125°C

Power Supply Pins

Operating Voltage VDD range is described in Section 15.2.

(1)

Characteristic

Sym

Min

Typ

Max

Units

Conditions

Input Low Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

VIL

VSS

—

0.2 VDD

0.15 VDD

0.3 VDD

V

Pin at hi-impedance

(4)

RC option only

XT, HS and LP options

Input High Voltage

I/O ports

VIH

(5)

0.45 VDD

2.0

—

VDD

V

For all VDD

(5)

4.0V < VDD ≤ 5.5V

VDD > 5.5V

0.36 VDD

0.85 VDD

0.7 VDD

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

OSC1

(4)

RC option only

XT, HS and LP options

Hysteresis of Schmitt

Trigger inputs

VHYS 0.15VDD*

—

V

(3)

Input Leakage Current

IIL

For VDD ≤ 5.5V

I/O ports

–1.0

—

+1.0

µA

VSS ≤ VPIN ≤ VDD,

Pin at hi-impedance

(2)

MCLR

–5.0

—

µA

VPIN = VSS + 0.25 V

VPIN = VDD

VSS ≤ VPIN ≤ VDD

(2)

0.5

+5.0

+3.0

T0CKI

OSC1

–3.0

VSS ≤ VPIN ≤ VDD,

XT, HS and LP options

Output Low Voltage

I/O ports

OSC2/CLKOUT

VOL

—

0.6

V

IOL = 8.7 mA, VDD = 4.5V

IOL = 1.6 mA, VDD = 4.5V,

RC option only

—

(3)

Output High Voltage

VOH

I/O ports

OSC2/CLKOUT

VDD –0.7

—

V

IOH = –5.4 mA, VDD = 4.5V

IOH = –1.0 mA, VDD = 4.5V,

RC option only

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance

only and is not tested.

2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The speciﬁed

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltage.

3: Negative current is deﬁned as coming out of the pin.

4: For the RC option, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X

be driven with external clock in RC mode.

5: The user may use the better of the two speciﬁcations.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 123

PIC16C5X

PIC16CR57B

15.6

Timing Parameter Symbology and Load Conditions

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase subscripts (pp) and their meanings:

pp

T

Time

2

to

mc

osc

os

MCLR

ck

cy

drt

io

CLKOUT

cycle time

device reset timer

I/O port

oscillator

OSC1

t0

T0CKI

wdt

watchdog timer

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (Hi-impedance)

Low

Valid

L

Hi-impedance

FIGURE 15-1: LOAD CONDITIONS

CL = 50 pF for all pins except OSC2

CL

15 pF for OSC2 in XT, HS or LP

options when external clock

is used to drive OSC1

VSS

DS30453B-page 124

Preliminary

1998 Microchip Technology Inc.

PIC16CR57B

PIC16C5X

15.7

Timing Diagrams and Speciﬁcations

FIGURE 15-2: EXTERNAL CLOCK TIMING - PIC16CR57B

Q4

Q3

Q4

4

Q1

Q2

OSC1

1

3

4

2

CLKOUT

TABLE 15-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR57B

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 15.1, Section 15.2 and Section 15.3.

Parameter

No.

(1)

Sym

Characteristic

Min Typ

Max Units

Conditions

(2)

FOSC

External CLKIN Frequency

DC

0.1

4.0

5.0

—

4.0

10

MHz XT osc mode

MHz HS osc mode (04)

MHz HS osc mode (10)

MHz HS osc mode (20)

kHz LP osc mode

20

200

4.0

10

(2)

Oscillator Frequency

MHz RC osc mode

MHz XT osc mode

MHz HS osc mode (04)

MHz HS osc mode (10)

MHz HS osc mode (20)

kHz LP osc mode

20

200

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated.These parameters are for design guidance only

and are not tested.

2: All speciﬁed values are based on characterization data for that particular oscillator type under standard operating

conditions with the device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation

and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruction cycle period (TCY) equals four times the input oscillator time base period.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 125

PIC16C5X

PIC16CR57B

TABLE 15-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR57B (CON’T)

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 15.1, Section 15.2 and Section 15.3.

Parameter

(1)

No.

Sym

Characteristic

Min Typ

Max Units

Conditions

XT osc mode

(2)

1

TOSC

External CLKIN Period

250

100

50

—

ns

µs

ns

µs

—

ns

µs

ns

HS osc mode (04)

HS osc mode (10)

HS osc mode (20)

LP osc mode

—

5.0

250

100

50

—

(2)

Oscillator Period

—

RC osc mode

—

10,000

250

200

—

XT osc mode

—

HS osc mode (04)

HS osc mode (10)

HS osc mode (20)

LP osc mode

—

5.0

—

(3)

2

3

TCY

Instruction Cycle Time

4/FOSC

—

TosL, TosH Clock in (OSC1) Low or High Time

85*

20*

2.0*

—

XT oscillator

HS oscillator

LP oscillator

XT oscillator

HS oscillator

LP oscillator

—

4

TosR, TosF Clock in (OSC1) Rise or Fall Time

—

25*

50*

—

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated.These parameters are for design guidance only

and are not tested.

2: All speciﬁed values are based on characterization data for that particular oscillator type under standard operating

conditions with the device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation

and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruction cycle period (TCY) equals four times the input oscillator time base period.

DS30453B-page 126

Preliminary

1998 Microchip Technology Inc.

PIC16CR57B

PIC16C5X

FIGURE 15-3: CLKOUT AND I/O TIMING - PIC16CR57B

Q1

Q4

Q2

Q3

OSC1

10

11

CLKOUT

12

16

13

18

19

14

I/O Pin

(input)

15

17

I/O Pin

Old Value

(output)

New Value

20, 21

Note: All tests must be done with speciﬁed capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

TABLE 15-3: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16CR57B

AC Characteristics

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 15.1, Section 15.2 and

Section 15.3.

Parameter

(1)

No.

Sym

Characteristic

(2)

Min

Typ

Max

Units

10

11

12

13

14

15

16

17

18

TosH2ckL

TosH2ckH

TckR

OSC1↑ to CLKOUT↓

—

15

5.0

—

30**

15**

40**

—

ns

(2)

OSC1↑ to CLKOUT↑

—

(2)

CLKOUT rise time

—

(2)

TckF

CLKOUT fall time

—

(2)

CLKOUT↓ to Port out valid

TckL2ioV

TioV2ckH

TckH2ioI

TosH2ioV

TosH2ioI

—

(2)

Port in valid before CLKOUT↑

(2)

0.25 TCY+30*

—

Port in hold after CLKOUT↑

OSC1↑ (Q1 cycle) to Port out valid

0*

—

(3)

—

100*

—

OSC1↑ (Q2 cycle) to Port input invalid

TBD

—

(I/O in hold time)

19

TioV2osH

Port input valid to OSC1↑

TBD

—

ns

(I/O in setup time)

(3)

20

21

TioR

TioF

Port output rise time

—

10

25**

ns

(3)

Port output fall time

*

These parameters are characterized but not tested.

** These parameters are design targets and are not tested. No characterization data available at this time.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated.These parameters are for design guidance only

and are not tested.

2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

3: See Figure 15-1 for loading conditions.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 127

PIC16C5X

PIC16CR57B

FIGURE 15-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16CR57B

VDD

MCLR

30

Internal

POR

32

DRT

Time-out

Internal

RESET

Watchdog

Timer

RESET

31

34

I/O pin

(Note 1)

Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.

TABLE 15-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16CR57B

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 15.1, Section 15.2 and Section 15.3.

Parameter

No.

(1)

Sym Characteristic

Min Typ

Max Units

Conditions

30

31

TmcL MCLR Pulse Width (low)

1.0*

9.0*

—

µs VDD = 5.0V

Twdt Watchdog Timer Time-out Period

(No Prescaler)

18*

30*

ms VDD = 5.0V (Commercial)

32

34

TDRT Device Reset Timer Period

9.0*

—

18*

—

30*

ms VDD = 5.0V (Commercial)

TioZ I/O Hi-impedance from MCLR Low

1.0*

µs

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

DS30453B-page 128

Preliminary

1998 Microchip Technology Inc.

PIC16CR57B

PIC16C5X

FIGURE 15-5: TIMER0 CLOCK TIMINGS - PIC16CR57B

T0CKI

40

41

42

TABLE 15-5: TIMER0 CLOCK REQUIREMENTS - PIC16CR57B

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 15.1, Section 15.2 and

Section 15.3.

Parameter

(1)

Sym Characteristic

Min

Typ

Max Units Conditions

No.

40

Tt0H T0CKI High Pulse Width - No Prescaler

- With Prescaler

0.5 TCY + 20*

10*

—

ns

41

42

Tt0L T0CKI Low Pulse Width - No Prescaler

- With Prescaler

0.5 TCY + 20*

10*

Tt0P T0CKI Period

20 or TCY + 40*

N

ns Whichever is greater.

N = Prescale Value

(1, 2, 4,..., 256)

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated.These parameters are for design guidance only

and are not tested.

1998 Microchip Technology Inc.

Preliminary

DS30453B-page 129

PIC16C5X

PIC16CR57B

NOTES:

DS30453B-page 130

Preliminary

1998 Microchip Technology Inc.

PIC16C58A

PIC16C5X

16.0 ELECTRICAL CHARACTERISTICS - PIC16C58A

†

Absolute Maximum Ratings

Ambient Temperature under bias ...........................................................................................................–55°C to +125°C

Storage Temperature............................................................................................................................. –65°C to +150°C