PIC16C554T-20/SO [MICROCHIP]
8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PDSO18, 0.300 INCH, PLASTIC, SOIC-18;
| 型号： | PIC16C554T-20/SO |
| 厂家： | 
MICROCHIP |
| 描述： | 8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PDSO18, 0.300 INCH, PLASTIC, SOIC-18 可编程只读存储器 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总108页 (文件大小：812K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC16C55X
EPROM-Based 8-Bit CMOS Microcontrollers
Devices Included in this Data Sheet:
Pin Diagram
Referred to collectively as PIC16C55X.
PDIP, SOIC, Windowed CERDIP
• PIC16C554
• PIC16C557
• PIC16C558
RA1
RA0
RA2
RA3
RA4/T0CKI
MCLR/Vpp
VSS
•1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
OSC1/CLKIN
OSC2/CLKOUT
VDD
High Performance RISC CPU:
RB0/INT
RB1
RB7
RB6
RB5
• Only 35 instructions to learn
RB2
RB3
• All single-cycle instructions (200 ns), except for
program branches which are two-cycle
RB4
• Operating speed:
SSOP
- DC - 20 MHz clock input
- DC - 20 ns instruction cycle
RA2
RA3
RA4/T0CKI
MCLR/Vpp
VSS
VSS
RB0/INT
RB1
•1
2
3
4
5
6
7
8
9
RA1
RA0
20
19
18
17
16
15
14
13
12
11
OSC1/CLKIN
OSC2/CLKOUT
VDD
VDD
RB7
Program
Memory
Device
Data Memory
PIC16C554
PIC16C557
512
2 K
2 K
80
RB6
RB5
RB4
128
128
RB2
RB3
PIC16C558
10
• Interrupt capability
PDIP, SOIC, Windowed CERDIP
• 16-18 special function hardware registers
• 8-level deep hardware stack
•1
RA4/T0CKI
VDD
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MCLR/VPP
OSC1/CLKIN
OSC2/CLKOUT
RC7
2
3
4
5
6
7
8
9
• Direct, Indirect and Relative Addressing modes
N/C
VSS
RA5
RC6
RA0
Peripheral Features:
RC5
RA1
RC4
RA2
RC3
• 13-22 I/O pins with individual direction control
- Pull-up resistors on PORTB
RA3
RC2
RB0/INT
RC1
10
11
12
13
14
RB1
RB2
RB3
RB4
RC0
RB7
RB6
RB5
• High current sink/source for direct LED drive
• Timer0: 8-bit timer/counter with 8-bit programma-
ble prescaler
SSOP
VSS
•1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
MCLR/VPP
OSC1/CLKIN
OSC2/CLKOUT
RC7
RA4/T0CKI
VDD
RA5
RA0
RC6
RA1
RC5
RA2
RC4
RA3
RC3
RB0/INT
RB1
RC2
19
RC1
RB2
RB3
RB4
VSS
18
17
16
15
RC0
RB7
RB6
RB5
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 1
PIC16C55X
Special Microcontroller Features:
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• Serial in-circuit programming (via two pins)
• Four user programmable ID locations
Note: For additional information on enhance-
ments, see Appendix A
CMOS Technology:
• Low power, high speed CMOS EPROM technol-
ogy
• Fully static design
• Wide operating voltage range
- 2.5V to 5.5V
• Commercial, Industrial and Extended temperature
range
• Low power consumption
- < 2.0 mA @ 5.0V, 4.0 MHz
- 15 A typical 3.0V, 32 kHz
- < 1.0 A typical standby current @ 3.0V
Device Differences
Device
Voltage Range
Oscillator
PIC16C554
PIC16C557
PIC16C558
2.5 - 5.5
2.5 - 5.5
2.5 - 5.5
(Note 1)
(Note 1)
(Note 1)
Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.
DS40143E-page 2
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
Table of Contents
1.0 General Description...................................................................................................................................................................... 5
2.0 PIC16C55X Device Varieties ....................................................................................................................................................... 7
3.0 Architectural Overview ................................................................................................................................................................. 9
4.0 Memory Organization................................................................................................................................................................. 13
5.0 I/O Ports ..................................................................................................................................................................................... 23
6.0 Special Features of the CPU...................................................................................................................................................... 31
7.0 Timer0 Module ........................................................................................................................................................................... 47
8.0 Instruction Set Summary............................................................................................................................................................ 53
9.0 Development Support................................................................................................................................................................. 67
10.0 Electrical Specifications.............................................................................................................................................................. 73
11.0 Packaging Information................................................................................................................................................................ 87
Appendix A: Enhancements............................................................................................................................................................. 97
Appendix B:
Compatibility ............................................................................................................................................................... 97
Index .................................................................................................................................................................................................... 99
On-Line Support................................................................................................................................................................................. 101
Systems Information and Upgrade Hot Line ...................................................................................................................................... 101
Reader Response.............................................................................................................................................................................. 102
Product Identification System ............................................................................................................................................................ 103
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 3
PIC16C55X
NOTES:
DS40143E-page 4
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
A UV-erasable CERDIP packaged version is ideal for
code development while the cost effective One-Time
Programmable (OTP) version is suitable for production
in any volume.
1.0
GENERAL DESCRIPTION
The PIC16C55X are 18, 20 and 28-Pin EPROM-based
members of the versatile PIC16CXX family of low cost,
high
performance,
CMOS,
fully-static,
8-bit
Table 1-1 shows the features of the PIC16C55X mid-
range microcontroller families.
microcontrollers.
All PIC® microcontrollers employ an advanced RISC
architecture. The PIC16C55X have enhanced core fea-
tures, eight-level deep stack, and multiple internal and
external interrupt sources. The separate instruction
and data buses of the Harvard architecture allow a 14-
bit wide instruction word with the separate 8-bit wide
data. The two-stage instruction pipeline allows all
instructions to execute in a single-cycle, except for pro-
gram branches (which require two cycles). A total of 35
instructions (reduced instruction set) are available.
Additionally, a large register set gives some of the
architectural innovations used to achieve a very high
performance.
A simplified block diagram of the PIC16C55X is shown
in Figure 3-1.
The PIC16C55X series fit perfectly in applications
ranging from motor control to low power remote sen-
sors. The EPROM technology makes customization of
application programs (detection levels, pulse genera-
tion, timers, etc.) extremely fast and convenient. The
small footprint packages make this microcontroller
series perfect for all applications with space limitations.
Low cost, low power, high performance, ease of use
and I/O flexibility make the PIC16C55X very versatile.
1.1
Family and Upward Compatibility
PIC16C55X microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
Users familiar with the family of microcontrollers will
realize that this is an enhanced version of the architec-
ture. Please refer to Appendix A for a detailed list of
enhancements. Code written for can be easily ported
to PIC16C55X family of devices (Appendix B).
The PIC16C554 has 80 bytes of RAM. The PIC16C557
and PIC16C558 have 128 bytes of RAM. The
PIC16C554 and PIC16C558 have 13 I/O pins and an 8-
bit timer/counter with an 8-bit programmable prescaler.
The PIC16C557 has 22 I/O pins and an 8-bit timer/
counter with an 8-bit programmable prescaler.
The PIC16C55X family fills the niche for users wanting
to migrate up from the family and not needing various
peripheral features of other members of the PIC16XX
mid-range microcontroller family.
PIC16C55X devices have special features to reduce
external components, thus reducing cost, enhancing
system reliability and reducing power consumption.
There are four oscillator options, of which the single pin
RC oscillator provides a low cost solution, the LP
oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for high speed crystals.
The SLEEP (power-down) mode offers power saving.
The user can wake-up the chip from SLEEP through
several external and internal interrupts and RESET.
1.2
Development Support
The PIC16C55X family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low cost development programmer and a
full-featured programmer.
A highly reliable Watchdog Timer, with its own on-chip
RC oscillator, provides protection against software
lock-up.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 5
PIC16C55X
TABLE 1-1:
PIC16C55X FAMILY OF DEVICES
PIC16C554
PIC16C557
PIC16C558
Maximum Frequency of Operation
(MHz)
20
20
20
Clock
EPROM Program Memory
(x14 words)
512
2K
2K
Memory
Data Memory (bytes)
Timer Module(s)
Interrupt Sources
I/O Pins
80
TMR0
3
128
TMR0
3
128
TMR0
3
Peripherals
13
22
13
Voltage Range (Volts)
Brown-out Reset
Packages
2.5-5.5
—
2.5-5.5
—
2.5-5.5
—
Features
18-pin DIP, SOIC;
20-pin SSOP
28-pin DIP, SOIC;
28-pin SSOP
18-pin DIP, SOIC,
SSOP
All PIC® Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
I/O current capability. All PIC16C55X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS40143E-page 6
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
2.3
Quick-Turnaround Production
(QTP) Devices
2.0
PIC16C55X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16C55X Product
Identification System section at the end of this data
sheet. When placing orders, please use this page of
the data sheet to specify the correct part number.
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium-to-high quantity of units and whose code pat-
terns have stabilized. The devices are identical to the
OTP devices, but with all EPROM locations and config-
uration options already programmed by the factory.
Certain code and prototype verification procedures
apply before production shipments are available.
Please contact your Microchip Technology sales office
for more details.
2.1
UV Erasable Devices
The UV erasable version, offered in CERDIP package,
is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the oscillator modes.
2.4
Serialized Quick-Turnaround
Microchip's
PICSTART and
PROMATE
SM
Production (SQTP ) Devices
programmers both support programming of the
PIC16C55X.
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
2.2
One-Time Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications. In addition to
the program memory, the configuration bits must also
be programmed.
Serial programming allows each device to have a
unique number which can serve as an entry code,
password or ID number.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 7
PIC16C55X
NOTES:
DS40143E-page 8
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16C55X family can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16C55X uses a Harvard architecture in
which program and data are accessed from separate
memories using separate busses. This improves
bandwidth over traditional von Neumann architecture
where program and data are fetched from the same
memory. Separating program and data memory further
allows instructions to be sized differently from 8-bit
wide data words. Instruction opcodes are 14-bit wide
making it possible to have all single word instructions.
A 14-bit wide program memory access bus fetches a
14-bit instruction in a single cycle. A two-stage pipeline
overlaps fetch and execution of instructions.
Consequently, all instructions (35) execute in a single-
cycle (200 ns @ 20 MHz) except for program branches.
The table below lists the memory (EPROM and RAM).
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a Borrow and Digit Borrow out bit,
respectively, in subtraction. See the SUBLWand SUBWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1, with
a description of the device pins in Table 3-1.
Program
Memory
(EPROM)
Data
Memor
(RAM)
Device
PIC16C554
PIC16C557
PIC16C558
512
2 K
2 K
80
128
128
The PIC16C554 addresses 512 x 14 on-chip program
memory. The PIC16C557 and PIC16C558 addresses
2 K x 14 program memory. All program memory is inter-
nal.
The PIC16C55X can directly or indirectly address its
register files or data memory. All special function
registers, including the program counter, are mapped
into the data memory. The PIC16C55X has an orthog-
onal (symmetrical) instruction set that makes it possible
to carry out any operation on any register using any
Addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC16C55X simple yet efficient. In addition, the
learning curve is reduced significantly.
The PIC16C55X devices contain an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 9
PIC16C55X
FIGURE 3-1:
BLOCK DIAGRAM
Program
Memory
Data
Memory
Device
PIC16C554
PIC16C557
PIC16C558
512 x 14
2 K x 14
2 K x 14
80 x 8
128 x 8
128 x 8
13
8
PORTA
EPROM
Data Bus
RAM
Program Counter
Program
Memory
RA0
RA1
RA2
RA3
512 x 14
to
2K x 14
File
8-Level Stack
(13-bit)
Registers
80 x 8 to
128 x 8
RA4/T0CKI
Program
Bus
14
PORTB
RAM Addr(1)
8
Addr MUX
Instruction reg
RB0/INT
RB7:RB1
Indirect
Addr
7
Direct Addr
8
FSR
STATUS reg
8
PORTC(2)
3
MUX
Power-up
Timer
RC7:RC0
Oscillator
Instruction
Decode &
Control
Start-up Timer
ALU
Power-on
Reset
8
Timing
Generation
Watchdog
Timer
W reg
OSC1/CLKIN
OSC2/CLKOUT
Timer0
VPP
VDD, VSS
Note 1: Higher order bits are from STATUS Register.
2: PIC16C557 only.
DS40143E-page 10
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
TABLE 3-1:
PIC16C55X PINOUT DESCRIPTION
Pin Number
Pin
Type
Buffer
Type
Name
PDIP
SOIC
SSOP
Description
ST/CMOS Oscillator crystal input/external clock source output.
OSC1/CLKIN
16
15
16
15
18
17
I
OSC2/CLKOUT
O
—
Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
MCLR/VPP
4
4
4
I/P
ST
Master clear (Reset) input/programming voltage input.
This pin is an active low RESET to the device.
RA0
17
18
1
17
18
1
19
20
1
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
Bi-directional I/O port
Bi-directional I/O port
Bi-directional I/O port
Bi-directional I/O port
RA1
RA2
RA3
2
2
2
RA4/T0CKI
3
3
3
Bi-directional I/O port or external clock input for TMR0.
Output is open drain type.
(1)
RB0/INT
6
6
7
I/O
TTL/ST
Bi-directional I/O port can be software programmed for
internal weak pull-up. RB0/INT can also be selected as an
external interrupt pin.
RB1
RB2
RB3
RB4
RB5
RB6
7
8
7
8
8
I/O
I/O
I/O
I/O
I/O
I/O
TTL
TTL
Bi-directional I/O port can be software programmed for
internal weak pull-up.
9
Bi-directional I/O port can be software programmed for
internal weak pull-up.
9
9
10
11
12
13
TTL
Bi-directional I/O port can be software programmed for
internal weak pull-up.
10
11
12
10
11
12
TTL
Bi-directional I/O port can be software programmed for
internal weak pull-up. Interrupt-on-change pin.
TTL
Bi-directional I/O port can be software programmed for
internal weak pull-up. Interrupt-on-change pin.
(2)
(2)
TTL/ST
Bi-directional I/O port can be software programmed for
internal weak pull-up. Interrupt-on-change pin. Serial pro-
gramming clock.
RB7
13
13
14
I/O
TTL/ST
Bi-directional I/O port can be software programmed for
internal weak pull-up. Interrupt-on-change pin. Serial pro-
gramming data.
(3)
RC0
18
19
20
21
22
23
24
18
19
20
21
22
23
24
18
19
20
21
22
23
24
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Bi-directional I/O port input buffer.
Bi-directional I/O port input buffer.
Bi-directional I/O port input buffer.
Bi-directional I/O port input buffer.
Bi-directional I/O port input buffer.
Bi-directional I/O port input buffer.
Bi-directional I/O port input buffer.
(3)
RC1
(3)
RC2
(3)
RC3
(3)
RC4
(3)
RC5
(3)
RC6
(3)
RC7
25
5
25
5
25
5,6
I/O
P
TTL
—
Bi-directional I/O port input buffer.
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
VSS
VDD
14
14
15,16
P
—
Legend:
O = Output
— = Not used
TTL = TTL input
I/O = Input/output
I = Input
P = Power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: PIC16C557 only.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 11
PIC16C55X
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 3-1).
3.1
Clocking Scheme/Instruction
Cycle
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow are shown in Figure 3-2.
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
3.2
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
phase
clocks
Q4
PC
PC
PC+1
PC+2
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1:
INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
3. CALL SUB_1
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS40143E-page 12
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
FIGURE 4-2:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16C557 AND
4.0
4.1
MEMORY ORGANIZATION
Program Memory Organization
PIC16C558
The PIC16C55X has a 13-bit program counter capable
of addressing an 8 K x 14 program memory space.
Only the first 512 x 14 (0000h - 01FFh) for the
PIC16C554 and 2K x 14 (0000h - 07FFh) for the
PIC16C557 and PIC16C558 are physically imple-
mented. Accessing a location above these boundaries
will cause a wrap-around within the first 512 x 14
spaces in the PIC16C554, or 2K x 14 space of the
PIC16C558 and PIC16C557. The RESET vector is at
0000h and the interrupt vector is at 0004h (Figure 4-1,
Figure 4-2).
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
RESET Vector
000h
FIGURE 4-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16C554
Interrupt Vector
0004
0005
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
On-chip Program
Memory
Stack Level 1
Stack Level 2
07FFh
0800h
1FFFh
Stack Level 8
RESET Vector
4.2
Data Memory Organization
000h
The data memory (Figure 4-3 through Figure 4-5) is
partitioned into two banks which contain the General
Purpose Registers (GPR) and the Special Function
Registers (SFR). Bank 0 is selected when the RP0 bit
(STATUS <5>) is cleared. Bank 1 is selected when the
RP0 bit is set. The Special Function Registers are
located in the first 32 locations of each Bank. Register
locations 20-6Fh (Bank 0) on the PIC16C554 and 20-
7Fh (Bank 0) and A0-BFh (Bank 1) on the PIC16C558
and PIC16C557 are General Purpose Registers imple-
mented as static RAM. Some special purpose registers
are mapped in Bank 1.
Interrupt Vector
0004
0005
On-chip Program
Memory
01FFh
0200h
4.2.1
GENERAL PURPOSE REGISTER
FILE
1FFFh
The register file is organized as 80 x 8 in the
PIC16C554 and 128 x 8 in the PIC16C557 and
PIC16C558. Each can be accessed either directly or
indirectly through the File Select Register, FSR
(Section 4.4).
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 13
PIC16C55X
FIGURE 4-3:
DATA MEMORY MAP FOR
THE PIC16C554
FIGURE 4-4:
DATA MEMORY MAP FOR
THE PIC16C557
File
Address
File
Address
File
Address
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
INDF(1)
TMR0
PCL
INDF(1)
OPTION
PCL
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
INDF(1)
TMR0
INDF(1)
OPTION
PCL
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
PCL
STATUS
FSR
STATUS
FSR
STATUS
FSR
STATUS
FSR
PORTA
PORTB
TRISA
TRISB
PORTA
PORTB
PORTC
TRISA
TRISB
TRISC
PCLATH
INTCON
PCLATH
INTCON
PCLATH
INTCON
PCLATH
INTCON
PCON
PCON
A0h
A0h
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
6Fh
70h
BFh
C0h
FFh
FFh
7Fh
7Fh
Bank 0
Bank 1
Bank 0
Bank 1
Unimplemented data memory locations, read as '0'.
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
Note 1: Not a physical register.
DS40143E-page 14
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
FIGURE 4-5:
DATA MEMORY MAP FOR
THE PIC16C558
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (Table 4-1). These
registers are static RAM.
File
Address
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
INDF(1)
TMR0
PCL
INDF(1)
OPTION
PCL
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
The Special Function Registers can be classified into
two sets (core and peripheral). The special function
registers associated with the “core” functions are
described in this section. Those related to the operation
of the peripheral features are described in the section
of that peripheral feature.
STATUS
FSR
STATUS
FSR
PORTA
PORTB
TRISA
TRISB
PCLATH
INTCON
PCLATH
INTCON
PCON
A0h
General
Purpose
Register
General
Purpose
Register
BFh
C0h
FFh
7Fh
Bank 0
Bank 1
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 15
PIC16C55X
TABLE 4-1:
Address
SPECIAL REGISTERS FOR THE PIC16C55X
Value on
POR Reset
Detail on
Page:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0
00h
INDF
TMR0
Addressing this location uses contents of FSR to address data memory (not a xxxx xxxx
physical register)
21
01h
02h
Timer0 Module’s Register
xxxx xxxx
0000 0000
47
21
PCL
Program Counter's (PC) Least Significant Byte
(2)
(2)
03h
04h
05h
06h
STATUS
FSR
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
xxxx xxxx
---x xxxx
xxxx xxxx
17
21
23
25
Indirect data memory address pointer
PORTA
PORTB
—
—
—
RA4
RB4
RA3
RB3
RA2
RB2
RA1
RB1
RA0
RB0
RB7
RB6
RB5
(4)
07h
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
27
—
—
21
19
—
—
—
08h
—
—
Unimplemented
Unimplemented
—
—
09h
0Ah
PCLATH
INTCON
—
—
—
—
Write buffer for upper 5 bits of program counter ---0 0000
0Bh
GIE
(3)
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x
0Ch
Unimplemented
Unimplemented
Unimplemented
—
—
—
0Dh-1Eh
1Fh
—
—
Bank 1
80h
INDF
Addressing this location uses contents of FSR to address data memory (not a xxxx xxxx
21
physical register)
81h
82h
OPTION
PCL
RBPU INTEDG T0CS
T0SE
PSA
PS2
Z
PS1
DC
PS0
C
1111 1111
0000 0000
18
21
Program Counter's (PC) Least Significant Byte
83h
84h
85h
86h
STATUS
FSR
—
—
—
—
RP0
TO
PD
0001 1xxx
xxxx xxxx
17
21
23
25
Indirect data memory address pointer
TRISA
TRISB
—
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111
(4)
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
TRISC
27
—
—
21
19
—
—
—
—
Unimplemented
Unimplemented
—
—
PCLATH
INTCON
—
—
—
—
Write buffer for upper 5 bits of program counter ---0 0000
GIE
(3)
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x
Unimplemented
Unimplemented
—
—
—
8Eh
PCON
—
—
—
—
—
—
—
POR
—
---- --0-
20
—
—
8Fh-9Eh
9Fh
Unimplemented
Unimplemented
—
—
—
Legend: — = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,
shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: IRP & RP1 bits are reserved, always maintain these bits clear.
3: Bit 6 of INTCON register is reserved for future use. Always maintain this bit as clear.
4: PIC16C557 only.
DS40143E-page 16
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions be used to alter the
STATUS register because these instructions do not
affect any status bits. For other instructions, not affect-
ing any status bits, see the “Instruction Set Summary”.
4.2.2.1
STATUS Register
The STATUS register, shown in Figure 4-2, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as the destination may be different
than intended.
Note 1: The IRP and RP1 bits (STATUS<7:6>)
are not used by the PIC16C55X and
should be programmed as ’0'. Use of
these bits as general purpose R/W bits is
NOT recommended, since this may affect
upward compatibility with future products.
2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUSwill clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000uu1uu(where u= unchanged).
REGISTER 4-1:
STATUS REGISTER (ADDRESS 03h OR 83h)
Reserved Reserved
IRP RP1
bit7
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit0
IRP: Register Bank Select bit (used for Indirect addressing)
1= Bank 2, 3 (100h - 1FFh)
bit 7
0= Bank 0, 1 (00h - FFh)
The IRP bit is reserved on the PIC16C55X, always maintain this bit clear
RP1:RP0: Register Bank Select bits (used for Direct addressing)
11= Bank 3 (180h - 1FFh)
bit 6-5
10= Bank 2 (100h - 17Fh)
01= Bank 1 (80h - FFh)
00= Bank 0 (00h - 7Fh)
Each bank is 128 bytes. The RP1 bit is reserved on the PIC16C55X, always maintain this bit clear.
TO: Timeout bit
bit 4
bit 3
bit 2
bit 1
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT timeout occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) (for borrow the polarity is
reversed)
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
bit 0
Note 1: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the
source register.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 17
PIC16C55X
4.2.2.2
OPTION Register
Note 1: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT
(PSA = 1).
The OPTION register is a readable and writable
register which contains various control bits to configure
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 4-2:
OPTION REGISTER (ADDRESS 81H)
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
bit7
bit0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
RBPU: PORTB Pull-up Enable bit
1= PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
DS40143E-page 18
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
4.2.2.3
INTCON Register
The INTCON register is a readable and writable
register which contains the various enable and flag bits
for all interrupt sources.
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
REGISTER 4-3:
INTCON REGISTER (ADDRESS 0BH OR 8BH)
R/W-0
GIE
Reserved
—
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
bit7
bit0
bit 7
GIE: Global Interrupt Enable bit
1= Enables all un-masked interrupts
0= Disables all interrupts
bit 6
bit 5
Reserved: For future use. Always maintain this bit clear.
T0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
bit 4
bit 3
bit 2
bit 1
bit 0
INTE: RB0/INT External Interrupt Enable bit
1= Enables the RB0/INT external interrupt
0= Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1= The RB0/INT external interrupt occurred (must be cleared in software)
0= The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 19
PIC16C55X
4.2.2.4
PCON Register
The PCON register contains a flag bit to differentiate
between a Power-on Reset, an external MCLR Reset
or WDT Reset. See Section 6.3 and Section 6.4 for
detailed RESET operation.
REGISTER 4-4:
PCON REGISTER (ADDRESS 8Eh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
POR
U-0
—
bit7
bit0
bit 7-2
bit 1
Unimplemented: Read as '0'
POR: Power-on Reset status bit
1= No Power-on Reset occurred
0= Power-on Reset occurred
bit 0
Unimplemented: Read as '0'
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
DS40143E-page 20
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
4.3
PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high bits (PC<12:8>) are not
directly readable or writable and come from PCLATH.
On any RESET, the PC is cleared. Figure 4-6 shows
the two situations for the loading of the PC. The upper
example in the figure shows how the PC is loaded on a
write to PCL (PCLATH<4:0> PCH). The lower exam-
ple in Figure 4-6 shows how the PC is loaded during a
CALLor GOTOinstruction (PCLATH<4:3> PCH).
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or vectoring to an interrupt
address.
FIGURE 4-6:
LOADING OF PC IN
DIFFERENT SITUATIONS
4.4
Indirect Addressing, INDF and
FSR Registers
PCH
PCL
12
8
7
0
Instruction with
PCL as
Destination
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
PC
8
PCLATH<4:0>
PCLATH
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses data pointed to by the file select register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a no-
operation (although status bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 4-7. However, IRP is not used in the
PIC16C55X.
5
ALU result
PCH
12 11 10
PC
PCL
8
7
0
GOTO, CALL
PCLATH<4:3>
PCLATH
11
2
Opcode <10:0>
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-1.
EXAMPLE 4-1:
INDIRECT ADDRESSING
4.3.1
COMPUTED GOTO
movlw
movwf
clrf
incf
btfss
goto
0x20
FSR
INDF
FSR
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
NEXT
FSR,4 ;all done?
NEXT ;no clear next
;yes continue
CONTINUE:
4.3.2
STACK
The PIC16C55X family has an 8-level deep x 13-bit
wide hardware stack (Figure 4-1 and Figure 4-2). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALLinstruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLWor a RET-
FIEinstruction execution. PCLATH is not affected by a
PUSH or POP operation.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 21
PIC16C55X
FIGURE 4-7:
DIRECT/INDIRECT ADDRESSING PIC16C55X
Direct Addressing
Indirect Addressing
(1)
(1)
from opcode
7
RP1 RP0
6
0
0
IRP
FSR register
bank select
00h
location select
bank select
location select
00
01
10
11
00h
not used
Data
Memory
7Fh
7Fh
Bank 0
Bank 1 Bank 2
Bank 3
For memory map detail see Figure 4-3 and Figure 4-5.
Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.
DS40143E-page 22
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
FIGURE 5-2:
BLOCK DIAGRAM OF RA4
PIN
5.0
I/O PORTS
The PIC16C554 and PIC16C558 have two ports,
PORTA and PORTB. The PIC16C557 has three ports,
PORTA, PORTB and PORTC.
Data
bus
D
Q
Q
WR
PORTA
5.1
PORTA and TRISA Registers
CK
I/O pin(1)
N
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger
input and an open-drain output. Port RA4 is multiplexed
with the T0CKI clock input. All other RA port pins have
Schmitt Trigger input levels and full CMOS output driv-
ers. All pins have data direction bits (TRIS registers)
which can configure these pins as input or output.
Data Latch
D
Q
VSS
WR
TRISA
VSS
Schmitt
Q
CK
Trigger
input
TRISA Latch
buffer
A '1' in the TRISA register puts the corresponding out-
put driver in a Hi-impedance mode. A '0' in the TRISA
register puts the contents of the output latch on the
selected pin(s).
RD TRISA
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations. So a
write to a port implies that the port pins are first read,
then this value is modified and written to the port data
latch.
Q
D
EN
RD PORTA
TMR0 clock input
Note 1: On RESET, the TRISA register is set to all
inputs.
FIGURE 5-1:
BLOCK DIAGRAM OF
PORT PINS RA<3:0>
Data
Bus
D
Q
Q
VDD
VDD
WR
PORTA
CK
P
Data Latch
N
Q
Q
D
I/O pin
WR
TRISA
VSS
Schmitt
CK
VSS
Trigger
input
TRIS Latch
buffer
RD TRISA
Q
D
EN
RD PORTA
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 23
PIC16C55X
TABLE 5-1:
Name
PORTA FUNCTIONS
Buffer
Type
Bit #
Function
RA0
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
ST
ST
ST
ST
ST
Bi-directional I/O port.
Bi-directional I/O port.
Bi-directional I/O port.
Bi-directional I/O port.
RA1
RA2
RA3
RA4/T0CKI
Bi-directional I/O port or external clock input for TMR0. Output is open
drain type.
Legend: ST = Schmitt Trigger input
TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
Value on
POR
Address
Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Other
RESETS
05h
85h
PORTA
TRISA
—
—
—
—
—
—
RA4
RA3
RA2
RA1
RA0
---x xxxx
---1 1111
---u uuuu
---1 1111
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
Legend: — = Unimplemented locations, read as ‘0’, x = unknown, u = unchanged
Note 1: Shaded bits are not used by PORTA.
DS40143E-page 24
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
latched in INTCON<0>). This interrupt can wake the
device from SLEEP. The user, in the interrupt service
routine, can clear the interrupt in the following manner:
5.2
PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The
corresponding data direction register is TRISB. A '1' in
the TRISB register puts the corresponding output driver
in a Hi-impedance mode. A '0' in the TRISB register
puts the contents of the output latch on the selected
pin(s).
• Any read or write of PORTB (this will end the mis-
match condition)
• Clear flag bit RBIF
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
Reading PORTB register reads the status of the pins
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
The interrupt on mismatch feature, together with
software configurable pull-ups on these four pins,
allows easy interface to a key pad and make it possible
for wake-up on key-depression. (See AN552 in the
Microchip Embedded Control Handbook.)
Each of the PORTB pins has a weak internal pull-up
(200 A typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION<7>) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Note 1: If a change on the I/O pin should occur
when the read operation is being exe-
cuted (start of the Q2 cycle), then the
RBIF interrupt flag may not get set.
Four of PORTB’s pins, RB7:RB4, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RBIF interrupt (flag
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
FIGURE 5-3:
BLOCK DIAGRAM OF RB7:RB4 PINS
RBPU(1)
VDD
weak
pull-up
P
VDD
P
Data Latch
VDD
Data Bus
D
Q
WR PORTB
CK
TRIS Latch
I/O
pin
N
D
Q
VSS
WR TRISB
VSS
CK
Q
TTL
ST
Buffer
Input
Buffer
RD TRISB
Latch
D
Q
RD PORTB
EN
Set RBIF
From other
RB7:RB4 pins
Q
D
EN
RD PORTB
RB7:RB6 in Serial Programming mode
Note 1: TRISB = 1 enables weak pull-up if RBPU = ‘0’ (OPTION<7>).
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 25
PIC16C55X
FIGURE 5-4:
BLOCK DIAGRAM OF RB3:RB0 PINS
RBPU(1)
VDD
weak
pull-up
P
VDD
P
VDD
Data Latch
Data Bus
D
Q
WR PORTB
CK
TRIS Latch
I/O
pin
N
D
Q
VSS
WR TRISB
VSS
CK
Q
TTL
ST
Buffer
Input
Buffer
RD TRISB
Latch
D
Q
EN
RD PORTB
RB0/INT
ST
Buffer
RD PORTB
Note 1: TRISB = 1 enables weak pull-up if RBPU = ‘0’ (OPTION<7>).
TABLE 5-3:
PORTB FUNCTIONS
Name
RB0/INT
Bit #
Buffer Type
Function
(1)
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
TTL/ST
Bi-directional I/O port. Internal software programmable weak pull-up.
Bi-directional I/O port. Internal software programmable weak pull-up.
Bi-directional I/O port. Internal software programmable weak pull-up.
Bi-directional I/O port. Internal software programmable weak pull-up.
RB1
RB2
RB3
RB4
TTL
TTL
TTL
TTL
Bi-directional I/O port (with interrupt-on-change). Internal software programmable
weak pull-up.
RB5
RB6
RB7
Bit 5
Bit 6
Bit 7
TTL
Bi-directional I/O port (with interrupt-on-change). Internal software programmable
weak pull-up.
(2)
TTL/ST
Bi-directional I/O port (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming clock pin.
(2)
TTL/ST
Bi-directional I/O port (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming data pin.
Legend: ST = Schmitt Trigger, TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 5-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB AND TRISB
Value on
All Other
RESETS
Value on
POR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
06h
86h
PORTB
TRISB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
1111 1111
uuuu uuuu
1111 1111
TRISB7
TRISB6
TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
81h
OPTION
RBPU
GIE
INTEDG
T0CS
T0IE
T0SE
INTE
PSA
PS2
T0IF
PS1
PS0
1111 1111
0000 000x
1111 1111
0000 000x
0BH, 8BH INTCON
Legend:
Reserved
BRIE
INTF
RBIF
x = unknown, u = unchanged
Note 1: Shaded bits are not used by PORTB.
DS40143E-page 26
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
(1)
FIGURE 5-5:
BLOCK DIAGRAM OF
PORT PINS RC<7:0>
5.3
PORTC and TRISC Registers
PORTC is a 8-bit wide latch. All pins have data direc-
tion bits (TRIS registers) which can configure these
pins as input or output.
Data
Bus
D
Q
Q
A '1' in the TRISC register puts the corresponding out-
put driver in a Hi-impedance mode. A '0' in the TRISC
register puts the contents of the output latch on the
selected pin(s).
VDD
VDD
WR
PORTC
CK
P
Data Latch
Reading the PORTC register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations. So a
write to a port implies that the port pins are first read,
then this value is modified and written to the port data
latch
N
Q
Q
D
I/O pin
WR
TRISC
VSS
VSS
CK
TRIS Latch
TTL
Input
Buffer
RD TRISC
Q
D
EN
RD PORTC
TABLE 5-5:
PORTC FUNCTIONS
Name
Bit #
Buffer Type
Function
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Bi-directional I/O port.
Bi-directional I/O port.
Bi-directional I/O port.
Bi-directional I/O port.
Bi-directional I/O port.
Bi-directional I/O port.
Bi-directional I/O port.
Bi-directional I/O port.
Legend: ST = Schmitt Trigger, TTL = TTL input
TABLE 5-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC AND TRISC
Value on
All Other
RESETS
Value on
POR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
07h
PORTC
TRISC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
1111 1111
uuuu uuuu
1111 1111
87h
TRISC7
TRISC6
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
Legend:
x = unknown, u = unchanged
Note 1: PIC16C557 ONLY.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 27
PIC16C55X
Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(ex. BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
5.4
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
5.4.1
Any instruction which writes, operates internally as a
read followed by a write operation. The BCFand BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result
back to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSFoperation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSFoperation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(e.g., bit 0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and re-written to the data latch of this
particular pin, overwriting the previous content. As long
as the pin stays in the Input mode, no problem occurs.
However, if bit 0 is switched into Output mode later on,
the content of the data latch may now be unknown.
Example 5-1 shows the effect of two sequential read-
modify-write instructions (ex., BCF,BSF, etc.) on an
I/O port.
A pin actively outputting a low or high should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage
the chip.
DS40143E-page 28
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
EXAMPLE 5-1:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
5.4.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle, as shown
in Figure 5-6. Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load
dependent) before the next instruction which causes
that file to be read into the CPU is executed. Otherwise,
the previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with an NOP or another
instruction not accessing this I/O port.
; Initial PORT settings: PORTB<7:4> Inputs
;
;
PORTB<3:0> Outputs
; PORTB<7:6> have external pull-up and are
; not connected to other circuitry
;
;
;
;
PORT latch PORT pins
---------- ---------
BCF PORTB, 7
BCF PORTB, 6
; 01pp pppp 11pp pppp
; 10pp pppp 11pp pppp
BSF STATUS, RP0 ;
BCF TRISB, 7
BCF TRISB, 6
; 10pp pppp 11pp pppp
; 10pp pppp 10pp pppp
FIGURE 5-6:
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC + 1
PC + 2
NOP
PC + 3
NOP
PC
Instruction
PC
MOVWF PORTB
Write to
MOVF PORTB, W
Read PORTB
fetched
PORTB
RB <7:0>
Port pin
sampled here
T
PD
Execute
MOVWF
PORTB
Execute
MOVF
Execute
NOP
PORTB, W
Note 1: This example shows write to PORTB followed by a read from PORTB.
2: Data setup time = (0.25 TCY - TPD) where TCY = instruction cycle and TPD = propagation delay of Q1 cycle to
output valid. Therefore, at higher clock frequencies, a write followed by a read may be problematic.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 29
PIC16C55X
NOTES:
DS40143E-page 30
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
6.1
Configuration Bits
6.0
SPECIAL FEATURES OF THE
CPU
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in
program memory location 2007h.
What sets
a
microcontroller apart from other
processors are special circuits to deal with the needs of
real-time applications. The PIC16C55X family has a
host of such features intended to maximize system
reliability, minimize cost through elimination of external
components, provide power saving operating modes
and offer code protection.
The user will note that address 2007h is beyond
the user program memory space. In fact, it belongs
to the special test/configuration memory space
(2000h – 3FFFh), which can be accessed only during
programming.
These are:
1. OSC selection
2. RESET
3. Power-on Reset (POR)
4. Power-up Timer (PWRT)
5. Oscillator Start-Up Timer (OST)
6. Interrupts
7. Watchdog Timer (WDT)
8. SLEEP
9. Code protection
10. ID Locations
11. In-circuit serial programming™
The PIC16C55X has a Watchdog Timer which is
controlled by configuration bits. It runs off its own RC
oscillator for added reliability. There are two timers that
offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), which is intended to
keep the chip in RESET until the crystal oscillator is sta-
ble. The other is the Power-up Timer (PWRT), which
provides a fixed delay of 72 ms (nominal) on power-up
only, designed to keep the part in RESET while the
power supply stabilizes. With these two functions on-
chip, most applications need no external RESET cir-
cuitry.
The SLEEP mode is designed to offer a very low
current Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
wake-up or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The RC oscillator option saves system
cost while the LP crystal option saves power. A set of
configuration bits are used to select various options.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 31
PIC16C55X
REGISTER 6-1:
CONFIGURATION WORD
CP1
CP0
CP1
CP0
CP1
CP0
—
Reserved
CP1
CP0
PWRTE
WDTE
F0SC1
F0SC0
bit 0
bit 13
bit 13-8
bit 5-4
CP<1:0>: Code protection bits(1)
11= Program Memory code protection off
10= 0400h - 07FFh code protected
01= 0200h - 07FFh code protected
11= 0000h - 07FFh code protected
bit 7
bit 6
bit 3
Unimplemented: Read as '1'
Reserved: Do not use
PWRTE: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
bit 2
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
bit 1-0
FOSC1:FOSC0: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
Note 1: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
DS40143E-page 32
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
TABLE 6-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
(PRELIMINARY)
6.2
Oscillator Configurations
6.2.1
OSCILLATOR TYPES
The PIC16C55X can be operated in four different
oscillator options. The user can program two
configuration bits (FOSC1 and FOSC0) to select one of
these four modes:
Ranges Characterized:
Mode
Freq
OSC1(C1)
OSC2(C2)
XT
455 kHz
2.0 MHz
4.0 MHz
22 - 100 pF
15 - 68 pF
15 - 68 pF
22 - 100 pF
15 - 68 pF
15 - 68 pF
• LP
• XT
• HS
• RC
Low Power Crystal
Crystal/Resonator
HS
8.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
High Speed Crystal/Resonator
Resistor/Capacitor
16.0 MHz
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time. These values are for design
guidance only. Since each resonator has
its own characteristics, the user should
consult with the resonator manufacturer for
appropriate values of external compo-
nents.
6.2.2
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1 and OSC2 pins to establish
oscillation (Figure 6-1). The PIC16C55X oscillator
design requires the use of a parallel cut crystal. Use of
a series cut crystal may give a frequency out of the
crystal manufacturers specifications. When in XT, LP or
HS modes, the device can have an external clock
source to drive the OSC1 pin (Figure 6-2).
TABLE 6-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
(PRELIMINARY)
FIGURE 6-1:
CRYSTAL OPERATION
(OR CERAMIC
RESONATOR) (HS, XT OR
LP OSC
Mode
Freq
OSC1(C1)
OSC2(C2)
LP
32 kHz
200 kHz
68 - 100 pF
15 - 30 pF
68 - 100 pF
15 - 30 pF
XT
HS
100 kHz
2 MHz
4 MHz
68 - 150 pF 150 - 200 pF
15 - 30 pF
15 - 30 pF
CONFIGURATION)
15 - 30 pF
15 - 30 pF
OSC1
To internal logic
SLEEP
C1
C2
8 MHz
10 MHz
20 MHz
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
XTAL
OSC2
RF
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time. These values are for design
guidance only. Rs may be required in HS
mode as well as XT mode to avoid over-
driving crystals with low-drive level specifi-
cation. Since each crystal has its own
characteristics, the user should consult
with the crystal manufacturer for appropri-
ate values of external components.
RS
Note 1
PIC16C55X
Note 1: A series resistor may be required for AT strip cut
crystals.
2: See Table 6-1 and Table 6-2 for recommended val-
ues of C1 and C2.
FIGURE 6-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
CONFIGURATION)
Clock from
ext. system
OSC1
PIC16C55X
OSC2
Open
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 33
PIC16C55X
6.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
6.2.4
RC OSCILLATOR
For timing insensitive applications the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (REXT) and capacitor (CEXT) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low CEXT values. The user also needs to
take into account variation due to tolerance of external
R and C components used. Figure 6-5 shows how the
R/C combination is connected to the PIC16C55X. For
REXT values below 2.2 k, the oscillator operation may
become unstable, or stop completely. For very high
REXT values (e.g., 1 M), the oscillator becomes
sensitive to noise, humidity and leakage. Thus, we
recommend to keep REXT between 3 k and 100 k.
Either a pre-packaged oscillator can be used or a sim-
ple oscillator circuit with TTL gates can be built.
Prepackaged oscillators provide a wide operating
range and better stability. A well-designed crystal
oscillator will provide good performance with TTL
gates. Two types of crystal oscillator circuits can be
used: one with series resonance, or one with parallel
resonance.
Figure 6-3 shows implementation of a parallel resonant
oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180 phase shift that a parallel
oscillator requires. The 4.7 k resistor provides the
negative feedback for stability. The 10 k
potentiometers bias the 74AS04 in the linear region.
This could be used for external oscillator designs.
Although the oscillator will operate with no external
capacitor (CEXT = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
FIGURE 6-3:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
10k
To other
Devices
PIC16C55X
74AS04
4.7k
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test
purposes or to synchronize other logic (Figure 3-2 for
waveform).
CLKIN
74AS04
10k
XTAL
FIGURE 6-5:
RC OSCILLATOR MODE
10k
VDD
20 pF
20 pF
PIC16C55X
REXT
OSC1
Figure 6-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180
phase shift in a series resonant oscillator circuit. The
330 resistors provide the negative feedback to bias
the inverters in their linear region.
Internal Clock
CEXT
VSS
OSC2/CLKOUT
Fosc/4
FIGURE 6-4:
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
To other
Devices
330
330
PIC16C55X
74AS04
74AS04
74AS04
CLKIN
0.1 F
XTAL
DS40143E-page 34
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 6-6.
6.3
RESET
The PIC16C55X differentiates between various kinds
of RESET:
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Table 10-3 for pulse width
specification.
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during SLEEP
• WDT Reset (normal operation)
• WDT wake-up (SLEEP)
Some registers are not affected in any RESET condi-
tion; their status is unknown on POR and unchanged in
any other RESET. Most other registers are reset to a
“RESET state” on Power-on Reset, on MCLR or WDT
Reset and on MCLR Reset during SLEEP. They are not
affected by a WDT wake-up, since this is viewed as the
resumption of normal operation. TO and PD bits are set
or cleared differently in different RESET situations as
indicated in Table 6-4. These bits are used in software
to determine the nature of the RESET. See Table 6-6
for a full description of RESET states of all registers.
FIGURE 6-6:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/
VPP Pin
SLEEP
WDT
WDT
Module
Timeout
Reset
VDD rise
detect
Power-on Reset
VDD
S
OST/PWRT
OST
Chip_Reset
10-bit Ripple-counter
R
Q
OSC1/
CLKIN
Pin
PWRT
(1)
On-chip
RC OSC
10-bit Ripple-counter
Enable PWRT
Enable OST
See Table 6-3 for timeout situations.
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 35
PIC16C55X
6.4.3
OSCILLATOR START-UP TIMER
(OST)
6.4
Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST)
The Oscillator Start-Up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
6.4.1
POWER-ON RESET (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.6V – 1.8V). To
take advantage of the POR, just tie the MCLR pin
through a resistor to VDD. This will eliminate external
RC components usually needed to create Power-on
Reset. A maximum rise time for VDD is required. See
Electrical Specifications for details.
The OST timeout is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
6.4.4
TIMEOUT SEQUENCE
On power-up, the timeout sequence is as follows: First
PWRT timeout is invoked after POR has expired, then
OST is activated. The total timeout will vary based on
oscillator configuration and PWRTE bit status. For
example, in RC mode with PWRTE bit erased (PWRT
disabled), there will be no timeout at all. Figure 6-7,
Figure 6-8 and Figure 6-9 depict timeout sequences.
The POR circuit does not produce internal RESET
when VDD declines.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating con-
ditions are met.
Since the timeouts occur from the POR pulse, if MCLR
is kept low long enough, the timeouts will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 6-8). This is useful for testing purposes or
to synchronize more than one PIC16C55X device oper-
ating in parallel.
For additional information, refer to Application Note
AN607 “Power-up Trouble Shooting”.
6.4.2
POWER-UP TIMER (PWRT)
Table 6-5 shows the RESET conditions for some spe-
cial registers, while Table 6-6 shows the RESET condi-
tions for all the registers.
The Power-up Timer provides a fixed 72 ms (nominal)
timeout on power-up only, from POR. The Power-up
Timer operates on an internal RC oscillator. The chip is
kept in RESET as long as PWRT is active. The PWRT
delay allows the VDD to rise to an acceptable level. A
configuration bit, PWRTE can disable (if set) or enable
(if cleared or programmed) the Power-up Timer. The
Power-Up Time delay will vary from chip to chip and
due to VDD, temperature and process variation. See
DC parameters for details.
DS40143E-page 36
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
6.4.5
POWER CONTROL/STATUS
REGISTER (PCON)
Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a subse-
quent RESET if POR is ‘0’, it will indicate that a Power-
on Reset must have occurred (VDD may have gone too
low).
TABLE 6-3:
TIMEOUT IN VARIOUS SITUATIONS
Power-up
Oscillator
Configuration
Wake-up from
SLEEP
PWRTE = 0
PWRTE = 1
XT, HS, LP
72 ms + 1024 TOSC
72 ms
1024 TOSC
—
1024 TOSC
—
RC
TABLE 6-4:
STATUS BITS AND THEIR SIGNIFICANCE
POR
TO
PD
1
0
0
1
0
Power-on Reset
X
Illegal, TO is set on POR
0
1
1
X
0
0
0
u
0
Illegal, PD is set on POR
WDT Reset
WDT Wake-up
1
1
u
1
u
0
MCLR Reset during normal operation
MCLR Reset during SLEEP
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 37
PIC16C55X
TABLE 6-5:
INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Condition
Power-on Reset
000h
000h
0001 1xxx
000u uuuu
0001 0uuu
0000 uuuu
uuu0 0uuu
uuu1 0uuu
---- --0-
---- --u-
---- --u-
---- --u-
---- --u-
---- --u-
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset
000h
000h
WDT Wake-up
PC + 1
PC + 1(1)
Interrupt Wake-up from SLEEP
Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’, q= value depends on condition.
Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the inter-
rupt vector (0004h) after execution of PC+1.
TABLE 6-6:
Register
INITIALIZATION CONDITION FOR REGISTERS
MCLRResetduringnormal
Wake-up from SLEEP
through interrupt
Wake-up from SLEEP
through WDT timeout
operation
MCLR Reset during SLEEP
WDT Reset
Address
Power-on Reset
W
—
xxxx xxxx
—
uuuu uuuu
—
uuuu uuuu
—
INDF
TMR0
PCL
00h
01h
02h
03h
04h
05h
06h
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
---x xxxx
xxxx xxxx
uuuu uuuu
0000 0000
000q quuu(3)
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
PC + 1(2)
uuuq quuu(3)
uuuu uuuu
---u uuuu
uuuu uuuu
STATUS
FSR
PORTA
PORTB
PORTC(4)
PCLATH
INTCON
OPTION
TRISA
06h
0Ah
0Bh
81h
85h
86h
86h
xxxx xxxx
---0 0000
0000 000x
1111 1111
---1 1111
1111 1111
1111 1111
uuuu uuuu
---0 0000
0000 000u
1111 1111
---1 1111
1111 1111
1111 1111
uuuu uuuu
---u uuuu
uuuu uuuu(1)
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
TRISB
TRISC(4)
PCON
8Eh
---- --0-
---- --u-
---- --u-
Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’, q= value depends on condition.
Note 1: One or more bits in INTCON will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
3: See Table 6-5 for RESET value for specific condition.
4: PIC16C557 only.
DS40143E-page 38
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
FIGURE 6-7:
TIMEOUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIMEOUT
OST TIMEOUT
TOST
INTERNAL RESET
FIGURE 6-8:
TIMEOUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIMEOUT
OST TIMEOUT
TOST
INTERNAL RESET
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 39
PIC16C55X
FIGURE 6-9:
TIMEOUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): CASE 3
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIMEOUT
OST TIMEOUT
TOST
INTERNAL RESET
FIGURE 6-10:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
VDD
VDD
D
R
R1
MCLR
PIC16C55X
C
Note 1: External Power-on Reset circuit is required only if
VDD power-up slope is too slow. The diode D helps
discharge the capacitor quickly when VDD powers
down.
2: < 40 k is recommended to make sure that voltage
drop across R does not violate the device’s electrical
specification.
3: R1 = 100 to 1 k will limit any current flowing into
MCLR from external capacitor C in the event of
MCLR/VPP pin breakdown due to Electrostatic Dis-
charge (ESD) or Electrical Overstress (EOS).
DS40143E-page 40
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure 6-12).
The latency is the same for one or two cycle
instructions. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid multiple interrupt requests. Individual interrupt
flag bits are set regardless of the status of their
corresponding mask bit or the GIE bit.
6.5
Interrupts
The PIC16C55X has 3 sources of interrupt:
• External interrupt RB0/INT
• TMR0 overflow interrupt
• PORTB change interrupts (pins RB7:RB4)
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on RESET.
Note 1: Individual interrupt flag bits are set
regardless of the status of their
corresponding mask bit or the GIE bit.
The “Return from Interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables RB0/INT interrupts.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The CPU will execute a NOP
in the cycle immediately following the
instruction which clears the GIE bit. The
interrupts which were ignored are still
pending to be serviced when the GIE bit
is set again.
The INT pin interrupt, the RB port change interrupt and
the TMR0 overflow interrupt flags are contained in the
INTCON register.
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the interrupt service routine the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in soft-
ware before re-enabling interrupts to avoid RB0/INT
recursive interrupts.
FIGURE 6-11:
INTERRUPT LOGIC
Wake-up
(If in SLEEP mode)
T0IF
T0IE
INTF
INTE
Interrupt
to CPU
RBIF
RBIE
GIE
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 41
PIC16C55X
6.5.1
RB0/INT INTERRUPT
6.5.2
TMR0 INTERRUPT
An external interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION<6>) is set, or fall-
ing if INTEDG bit is clear. When a valid edge appears
on the RB0/INT pin, the INTF bit (INTCON<1>) is set.
This interrupt can be disabled by clearing the INTE
control bit (INTCON<4>). The INTF bit must be cleared
in software in the interrupt service routine before re-
enabling this interrupt. The RB0/INT interrupt can
wake-up the processor from SLEEP, if the INTE bit was
set prior to going into SLEEP. The status of the GIE bit
decides whether or not the processor branches to the
interrupt vector following wake-up. See Section 6.8 for
details on SLEEP and Figure 6-14 for timing of wake-
up from SLEEP through RB0/INT interrupt.
An overflow (FFh 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be enabled/disabled by setting/clearing T0IE
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 7.0.
6.5.3
PORTB INTERRUPT
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/dis-
abled by setting/clearing the RBIE (INTCON<4>) bit.
For operation of PORTB (Section 5.2).
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may get set.
FIGURE 6-12:
INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT
3
4
INT pin
1
1
Interrupt Latency
INTF flag
(INTCON<1>)
5
2
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
PC+1
PC+1
—
0004h
0005h
Instruction
fetched
Inst (PC+1)
Inst (0004h)
Inst (PC)
Inst (0005h)
Inst (0004h)
Instruction
executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC-1)
Note 1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4 TCY where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single
cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC Oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
DS40143E-page 42
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
6.6
Context Saving During Interrupts
6.7
Watchdog Timer (WDT)
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt (e.g., W register and STATUS
register). This will have to be implemented in software.
The Watchdog Timer is a free running on-chip RC oscil-
lator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the CLKIN pin. That means that the WDT will run, even
if the clock on the OSC1 and OSC2 pins of the device
has been stopped, for example, by execution of a
SLEEP instruction. During normal operation, a WDT
timeout generates a device RESET. If the device is in
SLEEP mode, a WDT timeout causes the device to
wake-up and continue with normal operation. The WDT
can be permanently disabled by programming the con-
figuration bit WDTE as clear (Section 6.1).
Example 6-1 stores and restores the STATUS and W
registers. The user register, W_TEMP, must be defined
in both banks and must be defined at the same offset
from the bank base address (i.e., W_TEMPis defined at
0x20 in Bank 0 and it must also be defined at 0xA0 in
Bank 1). The user register, STATUS_TEMP, must be
defined in Bank 0. The Example 6-1:
• Stores the W register
6.7.1
WDT PERIOD
• Stores the STATUS register in Bank 0
• Executes the ISR code
The WDT has a nominal timeout period of 18 ms, (with
no prescaler). The timeout periods vary with tempera-
ture, V and process variations from part-to-part (see
• Restores the STATUS (and bank select bit
register)
DD
• Restores the W register
DC specs). If longer timeout periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, timeout periods up to 2.3
seconds can be realized.
EXAMPLE 6-1:
SAVING THE STATUS
AND W REGISTERS IN
RAM
The CLRWDTand SLEEPinstructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
MOVWF W_TEMP
;copy W to TEMP
;register, could be in
;either bank
;swap STATUS to be
;saved into W
;change to bank0
;regardless of
;current bank
SWAPF STATUS,W
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer timeout.
BCF
STATUS,RP0
6.7.2
WDT PROGRAMMING
CONSIDERATIONS
MOVWF STATUS_TEMP ;save STATUS to bank0
;register
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., max.
WDT prescaler) it may take several seconds before a
WDT timeout occurs.
:
:
:
SWAPF STATUS_TEMP,W;swap STATUS_TEMP
;register into W, sets
;bank to original state
MOVWF STATUS
;move W into STATUS
;register
SWAPF W_TEMP,F
SWAPF W_TEMP,W
;swap W_TEMP
;swap W_TEMP into W
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 43
PIC16C55X
FIGURE 6-13:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 7-6)
0
M
U
X
Postscaler
8
Watchdog
Timer
1
8 - to - 1 MUX
PS<2:0>
PSA
WDT
Enable Bit
To TMR0
(Figure 7-6)
0
1
MUX
PSA
WDT
Timeout
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
TABLE 6-7:
SUMMARY OF WATCHDOG TIMER REGISTERS
Value on all
other RESETS
Address
Name
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on POR
2007h
81h
Config. bits
OPTION
—
Reserved CP1
CP0 PWRTE WDTE FOSC1 FOSC0
PSA PS2 PS1 PS0
RBPU INTEDG T0CS T0SE
1111 1111
1111 1111
Legend: x= unknown, u= unchanged, q= value depends on condition, — = unimplemented, read as ‘0’.
Shaded cells are not used by the Watchdog Timer.
DS40143E-page 44
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
The first event will cause a device RESET. The two lat-
ter events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device RESET.
PD bit, which is set on power-up is cleared when
SLEEP is invoked. TO bit is cleared if WDT Wake-up
occurred.
6.8
Power-Down Mode (SLEEP)
The Power-down mode is entered by executing a
SLEEPinstruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the STATUS register is
cleared, the TO bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before SLEEPwas executed (driving high, low, or hi-
impedance).
When the SLEEP instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the correspond-
ing interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEPinstruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have an NOPafter the SLEEPinstruction.
For lowest current consumption in this mode, all I/O
pins should be either at VDD, or VSS, with no external
circuitry drawing current from the I/O pin. I/O pins that
are hi-impedance inputs should be pulled high or low
externally to avoid switching currents caused by float-
ing inputs. The T0CKI input should also be at VDD or
VSS for lowest current consumption. The contribution
from on-chip pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
Note: If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from SLEEP. The
SLEEP instruction is completely executed.
Note: It should be noted that a RESET generated
by a WDT timeout does not drive MCLR
pin low.
6.8.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
The WDT is cleared when the device wakes-up from
SLEEP, regardless of the source of wake-up.
1. External RESET input on MCLR pin
2. Watchdog Timer Wake-up (if WDT was enabled)
3. Interrupt from RB0/INT pin or RB Port change
FIGURE 6-14:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
(2)
TOST
INTF flag
Interrupt Latency(2)
(INTCON<1>)
GIE bit
Processor in
SLEEP
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
Inst(PC - 1)
fetched
Instruction
executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(0004h)
Note 1: XT, HS or LP Oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale). This delay will not be there for RC osc mode.
3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 45
PIC16C55X
FIGURE 6-15:
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
6.9
Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
To Normal
Connections
Note: Microchip does not recommend code
External
Connector
Signals
protecting windowed devices.
PIC16C55X
6.10 ID Locations
+5V
0V
VDD
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are
readable and writable during program/verify.
VSS
VPP
MCLR/VPP
RB6
RB7
CLK
Data I/O
6.11 In-Circuit Serial Programming™
VDD
The PIC16C55X microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
To Normal
Connections
The device is placed into a Program/Verify mode by
holding the RB6 and RB7 pins low while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). RB6 becomes the programming clock
and RB7 becomes the programming data. Both RB6
and RB7 are Schmitt Trigger inputs in this mode.
After RESET, to place the device into Programming/
Verify mode, the program counter (PC) is at location
00h. A 6-bit command is then supplied to the device.
Depending on the command, 14 bits of program data
are then supplied to or from the device, depending if
the command was a load or a read. For complete
details of serial programming, please refer to the
PIC16C6X/7X Programming Specifications (Literature
#DS30228).
A typical in-circuit serial programming connection is
shown in Figure 6-15.
DS40143E-page 46
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
bit (OPTION<4>). Clearing the T0SE bit selects the
rising edge. Restrictions on the external clock input are
discussed in detail in Section 7.2.
7.0
TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
The prescaler is shared between the Timer0 module
and the Watchdog Timer. The prescaler assignment is
controlled in software by the control bit PSA
(OPTION<3>). Clearing the PSA bit will assign the
prescaler to Timer0. The prescaler is not readable or
writable. When the prescaler is assigned to the Timer0
module, prescale value of 1:2, 1:4, ..., 1:256 are
selectable. Section 7.3 details the operation of the
prescaler.
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0
module.
7.1
TIMER0 Interrupt
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In Timer mode, the TMR0 will increment
every instruction cycle (without prescaler). If Timer0 is
written, the increment is inhibited for the following two
cycles (Figure 7-2 and Figure 7-3). The user can work
around this by writing an adjusted value to TMR0.
Timer0 interrupt is generated when the TMR0 register
timer/counter overflows from FFh to 00h. This overflow
sets the T0IF bit. The interrupt can be masked by
clearing the T0IE bit (INTCON<5>). The T0IF bit
(INTCON<2>) must be cleared in software by the
Timer0 module interrupt service routine before re-
enabling this interrupt. The Timer0 interrupt cannot
wake the processor from SLEEP since the timer is shut
off during SLEEP. See Figure 7-4 for Timer0 interrupt
timing.
Counter mode is selected by setting the T0CS bit. In
this mode Timer0 will increment either on every rising
or falling edge of pin RA4/T0CKI. The incrementing
edge is determined by the source edge (T0SE) control
FIGURE 7-1:
TIMER0 BLOCK DIAGRAM
Data bus
RA4/T0CKI
pin
FOSC/4
0
1
PSout
8
1
0
Sync with
Internal
clocks
TMR0
Programmable
Prescaler
PSout
(2 Tcy delay)
T0SE
Set Flag bit T0IF
on Overflow
PSA
PS2:PS0
T0CS
Note 1: Bits, T0SE, T0CS, PS2, PS1, PS0 and PSA are located in the OPTION register.
2: The prescaler is shared with Watchdog Timer (Figure 7-6)
FIGURE 7-2:
TIMER0 (TMR0) TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
Instruction
Fetch
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
0
T0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
TMR0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0 Read TMR0 Read TMR0
reads NT0 reads NT0 reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 47
PIC16C55X
FIGURE 7-3:
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
Instruction
Fetch
T0
T0+1
NT0+1
NT0
TMR0
Instruction
Execute
Read TMR0
reads NT0
Read TMR0 Read TMR0 Read TMR0
reads NT0 reads NT0 reads NT0
Read TMR0
reads NT0 + 1
Write TMR0
executed
FIGURE 7-4:
TIMER0 INTERRUPT TIMING
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
OSC1
CLKOUT(3)
TMR0 timer
FEh
1
FFh
1
00h
01h
02h
T0IF bit
(INTCON<2>)
GIE bit
(INTCON<7>)
Interrupt Latency Time
INSTRUCTION FLOW
PC
PC
PC +1
PC +1
0004h
0005h
Instruction
fetched
Inst (PC)
Inst (PC+1)
Inst (0004h)
Inst (0005h)
Inst (0004h)
Instruction
executed
Inst (PC-1)
Dummy cycle
Dummy cycle
Inst (PC)
Note 1: T0IF interrupt flag is sampled here (every Q1).
2: Interrupt latency = 4 TCY, where TCY = instruction cycle time.
3: CLKOUT is available only in RC Oscillator mode.
DS40143E-page 48
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple-counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4TOSC (and a small RC delay of 40 ns)
divided by the prescaler value. The only requirement
on T0CKI high and low time is that they do not violate
the minimum pulse width requirement of 10 ns. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device.
7.2
Using Timer0 with External Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
7.2.1
EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 7-5). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small RC delay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
7.2.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the TMR0 is
actually incremented. Figure 7-5 shows the delay from
the external clock edge to the timer incrementing.
FIGURE 7-5:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small pulse
misses sampling
External Clock Input or
(2)
Prescaler output
(1)
(3)
External Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC).
Therefore, the error in measuring the interval between two edges on Timer0 input = ±4 TOSC max.
2: External clock if no prescaler selected, prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
7.3
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 7-6). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1,
MOVWF 1, BSF 1,x....etc.) will clear the prescaler.
When assigned to WDT, a CLRWDTinstruction will clear
the prescaler along with the Watchdog Timer. The
prescaler is not readable or writable.
Note: There is only one prescaler available
which is mutually exclusive between the
Timer0 module and the Watchdog Timer.
Thus, a prescaler assignment for the
Timer0 module means that there is no
prescaler for the Watchdog Timer, and
vice-versa.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 49
PIC16C55X
FIGURE 7-6:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
8
CLKOUT (=Fosc/4)
M
U
X
1
0
0
1
M
U
X
T0CKI
pin
SYNC
2
Tcy
TMR0 reg
T0SE
T0CS
Set flag bit T0IF
on Overflow
PSA
0
1
8-bit Prescaler
M
U
X
Watchdog
Timer
8
8-to-1MUX
PS0 - PS2
PSA
0
1
WDT Enable bit
M U X
PSA
WDT
Timeout
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
DS40143E-page 50
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
To change prescaler from the WDT to the TMR0
module use the sequence shown in Example 7-2. This
precaution must be taken even if the WDT is disabled.
7.3.1
SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution). To avoid an unintended device
EXAMPLE 7-2:
CHANGING PRESCALER
(WDTTIMER0)
RESET,
the
following
instruction
sequence
CLRWDT
;Clear WDT and
(Example 7-1) must be executed when changing the
prescaler assignment from Timer0 to WDT. Lines 5-7
are required only if the desired postscaler rate is 1:1
(PS<2:0> = 000) or 1:2 (PS<2:0> = 001).
;prescaler
BSF
STATUS, RP0
MOVLW
b'xxxx0xxx' ;Select TMR0, new
;prescale value and
;clock source
MOVWF
BCF
OPTION
STATUS, RP0
EXAMPLE 7-1:
CHANGING PRESCALER
(TIMER0WDT)
BCF
STATUS, RP0 ;Skip if already in
;Bank 0 CLRWDT Clear WDT
CLRF
BSF
TMR0
;Clear TMR0 & Prescaler
STATUS, RP0 ;Bank 1
MOVLW '00101111’b ;These 3 lines (5, 6, 7)
MOVWF OPTION
;Are required only if
;Desired PS<2:0> are
;CLRWDT 000 or 001
MOVLW '00101xxx’b ;Set Postscaler to
MOVWF OPTION ;Desired WDT rate
BCF STATUS, RP0 ;Return to Bank 0
TABLE 7-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
Value on
POR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Other
RESETS
01h
TMR0
Timer0 module’s register
xxxx xxxx
0000 000x
uuuu uuuu
0000 000x
0Bh/8Bh INTCON
GIE
Reserved
T0IE
INTE
RBIE
T0IF
INTF
RBIF
81h
OPTION
TRISA
RBPU
—
INTEDG
—
T0CS
—
T0SE
PSA
PS2
PS1
PS0
1111 1111
---1 1111
1111 1111
---1 1111
85h
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
Legend:
— = Unimplemented locations, read as ‘0’,
Note 1: Shaded bits are not used by TMR0 module.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 51
PIC16C55X
NOTES:
DS40143E-page 52
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
The instruction set is highly orthogonal and is grouped
into three basic categories:
8.0
INSTRUCTION SET SUMMARY
Each PIC16C55X instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16C55X instruc-
tion set summary in Table 8-2 lists byte-oriented, bit-
oriented, and literal and control operations. Table 8-
1 shows the opcode field descriptions.
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of an
instruction. In this case, the execution takes two
instruction cycles with the second cycle executed as a
NOP. One instruction cycle consists of four oscillator
periods. Thus, for an oscillator frequency of 4 MHz, the
For byte-oriented instructions, 'f' represents a file
register designator and 'd' represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
normal instruction execution time is 1 s. If
a
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
conditional test is true or the program counter is
changed as a result of an instruction, the instruction
execution time is 2 s.
Table 8-1 lists the instructions recognized by the
MPASM™ assembler.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
Figure 8-1 shows the three general formats that the
instructions can have.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
Note: To maintain upward compatibility with
future PIC® MCU products, do not use the
OPTIONand TRISinstructions.
TABLE 8-1:
OPCODE FIELD
DESCRIPTIONS
All examples use the following format to represent a
hexadecimal number:
0xhh
Field
Description
where h signifies a hexadecimal digit.
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
FIGURE 8-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Bit address within an 8-bit file register
Literal field, constant data or label
Byte-oriented file register operations
13
Don't care location (= 0or 1)
8
7
6
0
The assembler will generate code with x = 0. It
is the recommended form of use for compatibil-
ity with all Microchip software tools.
OPCODE
d
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
Bit-oriented file register operations
13 10 9
b (BIT #)
label Label name
7
6
0
TOS
PC
Top of Stack
OPCODE
f (FILE #)
Program Counter
PCLATH Program Counter High Latch
b = 3-bit bit address
f = 7-bit file register address
GIE
WDT
TO
Global Interrupt Enable bit
Watchdog Timer/Counter
Timeout bit
Literal and control operations
PD
Power-down bit
General
dest
Destination either the W register or the specified
register file location
13
8
7
0
0
OPCODE
k (literal)
[
(
]
)
Options
k = 8-bit immediate value
Contents
Assigned to
Register bit field
In the set of
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
< >
k (literal)
italics User defined term (font is courier)
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 53
PIC16C55X
TABLE 8-2:
PIC16C55X INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00 0111 dfff ffff C,DC,Z
1,2
1,2
2
00 0101 dfff ffff
00 0001 lfff ffff
00 0001 0000 0011
00 1001 dfff ffff
00 0011 dfff ffff
00 1011 dfff ffff
00 1010 dfff ffff
00 1111 dfff ffff
00 0100 dfff ffff
00 1000 dfff ffff
00 0000 lfff ffff
00 0000 0xx0 0000
00 1101 dfff ffff
00 1100 dfff ffff
Z
Z
Z
Z
Z
-
f, d
f, d
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
DECFSZ f, d
INCF
f, d
f, d
f, d
f, d
f
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
Move W to f
No Operation
-
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
00 0010 dfff ffff C,DC,Z
00 1110 dfff ffff
00 0110 dfff ffff
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1(2)
1(2)
01 00bb bfff ffff
1,2
1,2
3
01 01bb bfff ffff
01 10bb bfff ffff
01 11bb bfff ffff
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11 111x kkkk kkkk C,DC,Z
11 1001 kkkk kkkk
10 0kkk kkkk kkkk
00 0000 0110 0100
10 1kkk kkkk kkkk
11 1000 kkkk kkkk
11 00xx kkkk kkkk
00 0000 0000 1001
11 01xx kkkk kkkk
00 0000 0000 1000
00 0000 0110 0011
Z
TO,PD
Z
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
TO,PD
11 110x kkkk kkkk C,DC,Z
11 1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS40143E-page 54
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
8.1
Instruction Descriptions
ANDLW
AND Literal with W
ADDLW
Syntax:
Add Literal and W
Syntax:
[ label ] ANDLW
0 k 255
k
[ label ] ADDLW
0 k 255
k
Operands:
Operation:
Status Affected:
Encoding:
Operands:
(W) .AND. (k) (W)
Operation:
(W) + k (W)
C, DC, Z
Z
Status Affected:
Encoding:
11
1001
kkkk
kkkk
11
111x
kkkk
kkkk
The contents of W register are
AND’ed with the eight bit literal 'k'. The
result is placed in the W register.
Description:
The contents of the W register are
added to the eight bit literal 'k' and the
result is placed in the W register.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
ANDLW
0x5F
ADDLW
0x15
Before Instruction
Before Instruction
W
=
0xA3
W
=
0x10
After Instruction
After Instruction
W
=
0x03
W
=
0x25
ANDWF
AND W with f
ADDWF
Add W and f
Syntax:
[ label ] ANDWF f,d
Syntax:
[ label ] ADDWF f,d
Operands:
0 f 127
d
Operands:
0 f 127
d
Operation:
(W) .AND. (f) (dest)
Operation:
(W) + (f) (dest)
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
C, DC, Z
00
0101
dfff
ffff
00
0111
dfff
ffff
AND the W register with register 'f'. If
'd' is 0 the result is stored in the W
register. If 'd' is 1 the result is stored
back in register 'f'.
Description:
Add the contents of the W register
with register 'f'. If 'd' is 0 the result is
stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
ANDWF
FSR,
1
ADDWF
FSR,
0
Before Instruction
Before Instruction
W
=
0x17
0xC2
W
=
0x17
0xC2
FSR =
FSR =
After Instruction
After Instruction
W
=
0x17
0x02
W
=
0xD9
0xC2
FSR =
FSR =
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 55
PIC16C55X
BCF
Bit Clear f
BTFSC
Bit Test, Skip if Clear
Syntax:
[ label ] BCF f,b
Syntax:
[ label ] BTFSC f,b
Operands:
0 f 127
0 b 7
Operands:
0 f 127
0 b 7
Operation:
Status Affected:
Encoding:
Description:
Words:
0 (f<b>)
Operation:
skip if (f<b>) = 0
None
None
Status Affected:
Encoding:
01
00bb
bfff
ffff
01
10bb
bfff
ffff
Bit 'b' in register 'f' is cleared.
If bit 'b' in register 'f' is '0' then the next
instruction is skipped. If bit 'b' is '0' then
the next instruction fetched during the
current instruction execution is dis-
carded, and a NOPis executed instead,
making this a two-cycle instruction.
Description:
1
1
Cycles:
BCF
FLAG_REG, 7
Example
Before Instruction
FLAG_REG
Words:
Cycles:
Example
1
=
=
0xC7
0x47
1(2)
After Instruction
FLAG_REG
HERE
FALSE
TRUE
BTFSC
FLAG,1
GOTO
PROCESS_CODE
•
•
•
BSF
Bit Set f
Before Instruction
PC address HERE
After Instruction
if FLAG<1> = 0,
PC address TRUE
if FLAG<1> = 1,
PC address FALSE
Syntax:
[ label ] BSF f,b
=
Operands:
0 f 127
0 b 7
Operation:
Status Affected:
Encoding:
Description:
Words:
1 (f<b>)
=
None
=
01
01bb
bfff
ffff
Bit 'b' in register 'f' is set.
1
1
Cycles:
BSF
FLAG_REG,
7
Example
Before Instruction
FLAG_REG
=
=
0x0A
0x8A
After Instruction
FLAG_REG
DS40143E-page 56
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
BTFSS
Bit Test f, Skip if Set
CALL
Call Subroutine
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CALL k
0 k 2047
Operands:
0 f 127
0 b < 7
Operands:
Operation:
(PC)+ 1 TOS,
Operation:
skip if (f<b>) = 1
None
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Status Affected:
Encoding:
Status Affected:
Encoding:
None
01
11bb
bfff
ffff
10
0kkk
kkkk
kkkk
If bit 'b' in register 'f' is '1' then the next
instruction is skipped.
Description:
Call Subroutine. First, return address
(PC+1) is pushed onto the stack. The
eleven bit immediate address is
loaded into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALLis a two-cycle instruc-
tion.
Description:
If bit 'b' is '1', then the next instruction
fetched during the current instruction
execution, is discarded and a NOPis
executed instead, making this a two-
cycle instruction.
Words:
Cycles:
Example
1
Words:
Cycles:
Example
1
2
1(2)
HERE
FALSE
TRUE
BTFSS
GOTO
•
•
•
FLAG,1
PROCESS_CODE
HERE
CALL
THERE
Before Instruction
PC = Address HERE
After Instruction
Before Instruction
PC address HERE
PC = Address THERE
TOS = Address HERE+1
=
After Instruction
if FLAG<1> = 0,
PC =
address FALSE
CLRF
Clear f
if FLAG<1> = 1,
PC =
address TRUE
Syntax:
[ label ] CLRF
0 f 127
f
Operands:
Operation:
00h (f)
1 Z
Status Affected:
Encoding:
Z
00
0001
1fff
ffff
The contents of register 'f' are cleared
and the Z bit is set.
Description:
Words:
Cycles:
Example
1
1
CLRF
FLAG_REG
Before Instruction
FLAG_REG=0x5A
After Instruction
FLAG_REG=0x00
=1
Z
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 57
PIC16C55X
CLRW
Clear W
COMF
Complement f
Syntax:
[ label ] CLRW
Syntax:
[ label ] COMF f,d
Operands:
Operation:
None
Operands:
0 f 127
d [0,1]
00h (W)
1 Z
Operation:
(f) (dest)
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
Z
00
0001
0000
0011
00
1001
dfff
ffff
W register is cleared. Zero bit (Z) is
set.
The contents of register 'f' are
Description:
Description:
complemented. If 'd' is 0 the result is
stored in W. If 'd' is 1 the result is
stored back in register 'f'.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
CLRW
Before Instruction
COMF
REG1,0
W
=
0x5A
Before Instruction
REG1
After Instruction
After Instruction
=
0x13
W
Z
=
=
0x00
1
REG1
W
=
=
0x13
0xEC
DECF
Decrement f
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] DECF f,d
Syntax:
[ label ] CLRWDT
Operands:
0 f 127
d [0,1]
Operands:
Operation:
None
00h WDT
0 WDT prescaler,
1 TO
Operation:
(f) - 1 (dest)
Status Affected:
Encoding:
Z
1 PD
00
0011
dfff
ffff
Status Affected:
Encoding:
TO, PD
Decrement register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd'
is 1 the result is stored back in register
'f'.
Description:
00
0000
0110
0100
CLRWDTinstruction resets the
Description:
Watchdog Timer. It also resets the
prescaler of the WDT. Status bits TO
and PD are set.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
DECF
CNT,
1
1
Before Instruction
CLRWDT
CNT
Z
= 0x01
= 0
Before Instruction
WDT counter
After Instruction
WDT counter
= ?
After Instruction
CNT
Z
= 0x00
= 1
= 0x00
WDT prescaler = 0
TO
PD
= 1
= 1
DS40143E-page 58
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
DECFSZ
Decrement f, Skip if 0
GOTO
Unconditional Branch
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ] GOTO k
0 k 2047
Operands:
0 f 127
d [0,1]
Operands:
Operation:
k PC<10:0>
Operation:
(f) - 1 (dest); skip if result = 0
PCLATH<4:3> PC<12:11>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
00
1011
dfff
ffff
10
1kkk
kkkk
kkkk
The contents of register 'f' are
GOTOis an unconditional branch. The
eleven bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTOis a two-cycle instruction.
Description:
Description:
decremented. If 'd' is 0 the result is
placed in the W register. If 'd' is 1 the
result is placed back in register 'f'.
If the result is 0, the next instruction,
which is already fetched, is discarded.
A NOPis executed instead making it a
two-cycle instruction.
Words:
Cycles:
Example
1
2
GOTO THERE
Words:
Cycles:
Example
1
1(2)
After Instruction
PC
=
Address THERE
HERE
DECFSZ
GOTO
CNT, 1
LOOP
CONTINUE •
•
•
INCF
Increment f
Syntax:
[ label ] INCF f,d
Before Instruction
Operands:
0 f 127
d [0,1]
PC
= address HERE
After Instruction
CNT = CNT - 1
if CNT = 0,
Operation:
(f) + 1 (dest)
Status Affected:
Encoding:
Z
PC
if CNT 0,
PC = address HERE+1
= address CONTINUE
00
1010
dfff
ffff
The contents of register 'f' are
Description:
incremented. If 'd' is 0 the result is
placed in the W register. If 'd' is 1 the
result is placed back in register 'f'.
Words:
Cycles:
Example
1
1
INCF
CNT,
1
Before Instruction
CNT =
0xFF
0
Z
=
After Instruction
CNT =
0x00
1
Z
=
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 59
PIC16C55X
INCFSZ
Increment f, Skip if 0
IORWF
Inclusive OR W with f
Syntax:
[ label ] INCFSZ f,d
Syntax:
[ label ] IORWF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) + 1 (dest), skip if result = 0
Operation:
(W) .OR. (f) (dest)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
Z
00
1111
dfff
ffff
00
0100
dfff
ffff
The contents of register 'f' are
Inclusive OR the W register with
register 'f'. If 'd' is 0 the result is placed
in the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
Description:
incremented. If 'd' is 0 the result is
placed in the W register. If 'd' is 1 the
result is placed back in register 'f'.
If the result is 0, the next instruction,
which is already fetched, is discarded.
A NOPis executed instead making it a
two-cycle instruction.
Words:
Cycles:
Example
1
1
IORWF
RESULT, 0
Words:
Cycles:
Example
1
Before Instruction
1(2)
RESULT = 0x13
= 0x91
After Instruction
RESULT = 0x13
HERE
INCFSZ
GOTO
CNT,
LOOP
1
W
CONTINUE •
•
•
W
Z
= 0x93
= 1
Before Instruction
PC
After Instruction
CNT CNT + 1
if CNT = 0,
PC address CONTINUE
if CNT 0,
PC address HERE +1
= address HERE
=
=
=
MOVLW
Move Literal to W
IORLW
Inclusive OR Literal with W
Syntax:
[ label ] MOVLW k
0 k 255
k (W)
Syntax:
[ label ] IORLW k
0 k 255
Operands:
Operation:
Status Affected:
Encoding:
Operands:
Operation:
Status Affected:
Encoding:
(W) .OR. k (W)
Z
None
11
00xx
kkkk
kkkk
11
1000
kkkk
kkkk
The eight bit literal 'k' is loaded into W
register. The don’t cares will assemble
as 0’s.
Description:
The contents of the W register is
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
MOVLW
0x5A
IORLW
0x35
After Instruction
Before Instruction
W
=
0x5A
W
=
0x9A
After Instruction
W
Z
=
=
0xBF
1
DS40143E-page 60
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
MOVF
Move f
NOP
No Operation
Syntax:
[ label ] MOVF f,d
Syntax:
[ label ] NOP
None
Operands:
0 f 127
d [0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
No operation
None
Operation:
(f) (dest)
Status Affected:
Encoding:
Z
00
0000
0xx0
0000
00
1000
dfff
ffff
No operation.
Description:
The contents of register f is
1
moved to a destination dependant
upon the status of d. If d = 0, des-
tination is W register. If d = 1, the
destination is file register f itself. d
= 1 is useful to test a file register
since status flag Z is affected.
Cycles:
1
NOP
Example
Words:
Cycles:
Example
1
1
MOVF
FSR,
0
After Instruction
W
Z
= value in FSR register
= 1
MOVWF
Move W to f
OPTION
Load Option Register
Syntax:
[ label ] OPTION
None
Syntax:
[ label ] MOVWF
0 f 127
(W) (f)
f
Operands:
Operation:
Status Affected:
Encoding:
Operands:
Operation:
Status Affected:
Encoding:
(W) OPTION
None
None
00
0000
0110
0010
00
0000
1fff
ffff
The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code
compatibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly
address it.
Description:
Move data from W register to register
'f'.
Description:
Words:
Cycles:
Example
1
1
MOVWF
OPTION
Words:
Cycles:
Example
1
1
Before Instruction
OPTION = 0xFF
W
= 0x4F
After Instruction
To maintain upward compatibility
with future PIC MCU products, do
not use this instruction.
OPTION = 0x4F
= 0x4F
W
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 61
PIC16C55X
RETFIE
Return from Interrupt
RETURN
Return from Subroutine
Syntax:
[ label ] RETFIE
Syntax:
[ label ] RETURN
None
Operands:
Operation:
None
Operands:
Operation:
Status Affected:
Encoding:
TOS PC,
1 GIE
TOS PC
None
Status Affected:
Encoding:
None
00
0000
0000
1000
00
0000
0000
1001
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a two-cycle instruction.
Description:
Return from Interrupt. Stack is POPed
and Top of Stack (TOS) is loaded in
the PC. Interrupts are enabled by
setting Global Interrupt Enable bit,
GIE (INTCON<7>). This is a two-cycle
instruction.
Description:
Words:
Cycles:
Example
1
2
RETURN
Words:
Cycles:
Example
1
After Interrupt
2
PC
=
TOS
RETFIE
After Interrupt
PC
=
=
TOS
1
GIE
RETLW
Return with Literal in W
RLF
Rotate Left f through Carry
Syntax:
[ label ] RETLW k
0 k 255
Syntax:
[ label ] RLF f,d
Operands:
Operation:
Operands:
0 f 127
d [0,1]
k (W);
TOS PC
Operation:
See description below
C
Status Affected:
Encoding:
None
Status Affected:
Encoding:
11
01xx
kkkk
kkkk
00
1101
dfff
ffff
The W register is loaded with the eight
bit literal 'k'. The program counter is
loaded from the top of the stack (the
return address). This is a two-cycle
instruction.
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
stored back in register 'f'.
Description:
Description:
C
Register f
Words:
Cycles:
Example
1
2
Words:
Cycles:
Example
1
1
CALL TABLE;W contains table
;offset value
•
;W now has table
value
RLF
REG1,0
•
Before Instruction
REG1 = 1110 0110
= 0
After Instruction
REG1 = 1110 0110
•
ADDWF PC ;W = offset
RETLW k1 ;Begin table
TABLE
RETLW k2
;
C
•
•
•
RETLW kn ; End of table
W
C
= 1100 1100
= 1
Before Instruction
W
=
0x07
After Instruction
W
=
value of k8
DS40143E-page 62
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
RRF
Rotate Right f through Carry
SUBLW
Subtract W from Literal
Syntax:
[ label ] RRF f,d
Syntax:
[ label ] SUBLW k
0 k 255
Operands:
0 f 127
d [0,1]
Operands:
Operation:
k - (W) W)
C, DC, Z
Operation:
See description below
C
Status
Affected:
Status Affected:
Encoding:
00
1100
dfff
ffff
11
110x
kkkk
kkkk
Encoding:
The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
The W register is subtracted (2’s com-
plement method) from the eight bit literal
'k'. The result is placed in the W register.
Description:
Description:
Words:
1
1
Cycles:
C
Register f
SUBLW
0x02
Example 1:
Before Instruction
Words:
Cycles:
Example
1
1
W
C
=
=
1
?
RRF
REG1,0
After Instruction
Before Instruction
REG1 = 1110 0110
W
C
=
=
1
1; result is positive
C
=
0
After Instruction
REG1 = 1110 0110
Example 2:
Before Instruction
W
C
=
=
2
?
W
C
=
=
0111 0011
0
After Instruction
W
C
=
=
0
1; result is zero
SLEEP
Example 3:
Before Instruction
Syntax:
[ label SLEEP
W
C
=
=
3
?
]
Operands:
Operation:
None
After Instruction
00h WDT,
0 WDT prescaler,
1 TO,
0 PD
W
=
=
0xFF
C
tive
0; result is nega-
Status Affected:
Encoding:
TO, PD
00
0000
0110
0011
The power-down status bit, PD is
cleared. Timeout status bit, TO is
set. Watchdog Timer and its
prescaler are cleared.
Description:
The processor is put into SLEEP
mode with the oscillator stopped.
See Section 6.8 for more details.
Words:
1
Cycles:
Example:
1
SLEEP
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 63
PIC16C55X
SUBWF
Subtract W from f
SWAPF
Swap Nibbles in f
Syntax:
[ label ] SUBWF f,d
Syntax:
[ label ] SWAPF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - (W) dest)
Operation:
(f<3:0>) (dest<7:4>),
(f<7:4>) (dest<3:0>)
Status
C, DC, Z
Affected:
Status Affected:
Encoding:
None
00
0010
dfff
ffff
00
1110
dfff
ffff
Encoding:
Subtract (2’s complement method)
W register from register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is 1
the result is stored back in register 'f'.
The upper and lower nibbles of
Description:
Description:
register 'f' are exchanged. If 'd' is 0
the result is placed in W register. If 'd'
is 1 the result is placed in register 'f'.
Words:
1
1
Words:
Cycles:
Example
1
1
Cycles:
SUBWF
REG1,1
SWAPF
REG,
0
Example 1:
Before Instruction
REG1 =
Before Instruction
REG1 = 0xA5
After Instruction
REG1 = 0xA5
= 0x5A
3
2
?
W
C
=
=
After Instruction
REG1 =
W
1
W
C
=
=
2
TRIS
Load TRIS Register
1; result is positive
Syntax:
[ label ] TRIS
5 f 7
f
Example 2:
Before Instruction
REG1 =
Operands:
Operation:
Status Affected:
Encoding:
2
2
?
(W) TRIS register f;
W
C
=
=
None
00
0000
0110
0fff
After Instruction
REG1 =
The instruction is supported for code
compatibility with the PIC16C5X
products. Since TRIS registers are
readable and writable, the user can
directly address them.
Description:
0
W
C
=
=
2
1; result is zero
Example 3:
Before Instruction
REG1 =
Words:
Cycles:
Example
1
1
1
2
?
W
C
=
=
To maintain upward compatibility
with future PIC MCU products, do
not use this instruction.
After Instruction
REG1 = 0xFF
W
C
=
=
2
0; result is negative
DS40143E-page 64
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
XORLW
Exclusive OR Literal with W
Syntax:
[ label ] XORLW k
0 k 255
Operands:
Operation:
Status Affected:
Encoding:
(W) .XOR. k W)
Z
11
1010
kkkk
kkkk
The contents of the W register are
XOR’ed with the eight bit literal 'k'.
The result is placed in the W register.
Description:
Words:
1
1
Cycles:
Example:
XORLW
0xAF
Before Instruction
W
=
0xB5
After Instruction
W
=
0x1A
XORWF
Exclusive OR W with f
Syntax:
[ label ] XORWF f,d
Operands:
0 f 127
d [0,1]
Operation:
(W) .XOR. (f) dest)
Status Affected:
Encoding:
Z
00
0110
dfff
ffff
Exclusive OR the contents of the
W register with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd'
is 1 the result is stored back in register
'f'.
Description:
Words:
Cycles:
Example
1
1
XORWF
REG
1
Before Instruction
REG =
0xAF
0xB5
W
=
After Instruction
REG =
0x1A
0xB5
W
=
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 65
PIC16C55X
NOTES:
DS40143E-page 66
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
The MPLAB IDE allows you to:
9.0
DEVELOPMENT SUPPORT
• Edit your source files (either assembly or ‘C’)
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools (auto-
matically updates all project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- absolute listing file
- machine code
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
The ability to use MPLAB IDE with multiple debugging
tools allows users to easily switch from the cost-
effective simulator to a full-featured emulator with
minimal retraining.
MPLIBTM Object Librarian
• Simulators
- MPLAB SIM Software Simulator
• Emulators
9.2
MPASM Assembler
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
• In-Circuit Debugger
The MPASM assembler is a full-featured universal
macro assembler for all PIC MCUs.
- MPLAB ICD
The MPASM assembler has a command line interface
and a Windows shell. It can be used as a stand-alone
application on a Windows 3.x or greater system, or it
can be used through MPLAB IDE. The MPASM assem-
bler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
detail memory usage and symbol reference, an abso-
lute LST file that contains source lines and generated
machine code, and a COD file for debugging.
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Entry-Level Development
Programmer
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 17 Demonstration Board
- KEELOQ® Demonstration Board
The MPASM assembler features include:
• Integration into MPLAB IDE projects.
• User-defined macros to streamline assembly
code.
9.1
MPLAB Integrated Development
Environment Software
• Conditional assembly for multi-purpose source
files.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. The MPLAB IDE is a Windows®-based
application that contains:
• Directives that allow complete control over the
assembly process.
9.3
MPLAB C17 and MPLAB C18
C Compilers
• An interface to debugging tools
- simulator
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI ‘C’ compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers, respectively. These compilers provide
powerful integration capabilities and ease of use not
found with other compilers.
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor
• A project manager
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• Customizable toolbar and key mapping
• A status bar
• On-line help
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 67
PIC16C55X
9.4
MPLINK Object Linker/
MPLIB Object Librarian
9.6
MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can also
link relocatable objects from pre-compiled libraries,
using directives from a linker script.
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC micro-
controllers (MCUs). Software control of the MPLAB ICE
in-circuit emulator is provided by the MPLAB Integrated
Development Environment (IDE), which allows editing,
building, downloading and source debugging from a
single environment.
The MPLIB object librarian is a librarian for pre-
compiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine will be linked in with the application. This allows
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily re configured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PIC microcontrollers.
The MPLINK object linker features include:
• Integration with MPASM assembler and MPLAB
C17 and MPLAB C18 C compilers.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows environment were chosen to best
make these features available to you, the end user.
• Allows all memory areas to be defined as sections
to provide link-time flexibility.
The MPLIB object librarian features include:
• Easier linking because single libraries can be
included instead of many smaller files.
• Helps keep code maintainable by grouping
related modules together.
9.7
ICEPIC In-Circuit Emulator
• Allows libraries to be created and modules to be
added, listed, replaced, deleted or extracted.
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit One-
Time-Programmable (OTP) microcontrollers. The mod-
ular system can support different subsets of PIC16C5X
or PIC16CXXX products through the use of inter-
changeable personality modules, or daughter boards.
The emulator is capable of emulating without target
application circuitry being present.
9.5
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC-hosted environment by simulating the
PIC series microcontrollers on an instruction level. On
any given instruction, the data areas can be examined
or modified and stimuli can be applied from a file, or
user-defined key press, to any of the pins. The execu-
tion can be performed in single step, execute until
break, or Trace mode.
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and the MPLAB C18
C compilers and the MPASM assembler. The software
simulator offers the flexibility to develop and debug
code outside of the laboratory environment, making it
an excellent multi-project software development tool.
DS40143E-page 68
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
9.8
MPLAB ICD In-Circuit Debugger
9.11 PICDEM 1 Low Cost PIC MCU
Demonstration Board
Microchip's In-Circuit Debugger, MPLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based on the FLASH PIC MCUs and can be used to
develop for this and other PIC microcontrollers. The
MPLAB ICD utilizes the in-circuit debugging capability
built into the FLASH devices. This feature, along with
Microchip's In-Circuit Serial ProgrammingTM protocol,
offers cost-effective in-circuit FLASH debugging from
the graphical user interface of the MPLAB Integrated
Development Environment. This enables a designer to
develop and debug source code by watching variables,
single-stepping and setting break points. Running at
full speed enables testing hardware in real-time.
The PICDEM 1 demonstration board is a simple board
which demonstrates the capabilities of several of
Microchip’s microcontrollers. The microcontrollers sup-
ported are: PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcon-
trollers provided with the PICDEM 1 demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulator and download the firmware to the emu-
lator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simu-
lated analog input, push button switches and eight
LEDs connected to PORTB.
9.9
PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
Stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions
and error messages, keys to enter commands and a
modular detachable socket assembly to support various
package types. In Stand-alone mode, the PRO MATE II
device programmer can read, verify, or program PIC
devices. It can also set code protection in this mode.
9.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PICDEM 2 demonstration board is a simple dem-
onstration board that supports the PIC16C62,
PIC16C64, PIC16C65, PIC16C73 and PIC16C74
microcontrollers. All the necessary hardware and soft-
ware is included to run the basic demonstration pro-
grams. The user can program the sample
microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches, a potentiometer for simulated analog input, a
serial EEPROM to demonstrate usage of the I2CTM bus
and separate headers for connection to an LCD
module and a keypad.
9.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient.
The PICSTART Plus development programmer sup-
ports all PIC devices with up to 40 pins. Larger pin
count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 69
PIC16C55X
9.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
9.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. All neces-
sary hardware is included to run basic demo programs,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM 17 dem-
onstration board supports downloading of programs to
and executing out of external FLASH memory on board.
The PICDEM 17 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMASTER emulator and all of the sample programs
can be run and modified using either emulator. Addition-
ally, a generous prototype area is available for user
hardware.
The PICDEM 3 demonstration board is a simple dem-
onstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-pin PLCC microcontrollers with an LCD Mod-
ule. All the necessary hardware and software is
included to run the basic demonstration programs. The
user can program the sample microcontrollers pro-
vided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer, or a PICSTART Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding hardware and connecting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commons and 12 segments, that is capable of display-
ing time, temperature and day of the week. The
PICDEM 3 demonstration board provides an additional
RS-232 interface and Windows software for showing
the demultiplexed LCD signals on a PC. A simple serial
interface allows the user to construct a hardware
demultiplexer for the LCD signals.
9.15 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS eval-
uation kit includes a LCD display to show changing
codes, a decoder to decode transmissions and a pro-
gramming interface to program test transmitters.
DS40143E-page 70
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
TABLE 9-1:
DEVELOPMENT TOOLS FROM MICROCHIP
0 1 5 2 P M C
X X X C R M F
H C S X X X
X X C 9 3
/ X X C 2 5
/ X X C 2 4
X X X F 8 C 1 P I
X X C 8 2 C 1 P I
X 7 X 7 C 1 C I P
X 4 1 7 C I C P
X 9 X 6 C 1 C I P
X 8 X 6 F 1 C I P
X 8 1 6 C I C P
X 7 X 6 C 1 C I P
X 7 1 6 C I C P
X 6 2 1 6 C I F P
X
X X C 6 C 1 P I
X 6 1 6 C I C P
X 5 1 6 C I C P
0 0 1 4 C I 0 P
X
X X C 2 C 1 P I
s o l T e o r a w f t S o s r o t a u l E m r e g g u b D e s r e m m a o g P r r
s t K l a i E d v n a s d r a B o o m D e
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 71
PIC16C55X
NOTES:
DS40143E-page 72
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
10.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings †
Ambient Temperature under bias...............................................................................................................-40to +125C
Storage Temperature ................................................................................................................................ -65 to +150C
Voltage on any pin with respect to VSS (except VDD and MCLR) .......................................................-0.6V to VDD +0.6V
Voltage on VDD with respect to VSS ................................................................................................................. 0 to +7.5V
Voltage on MCLR with respect to VSS................................................................................................................0 to +14V
Total power Dissipation (Note 1)...............................................................................................................................1.0W
Maximum Current out of VSS pin ..........................................................................................................................300 mA
Maximum Current into VDD pin .............................................................................................................................250 mA
Input Clamp Current, IIK (VI < 0 or VI > VDD) ........................................................................................................±20 mA
Output Clamp Current, IOK (V0 < 0 or V0 > VDD)..................................................................................................±20 mA
Maximum Output Current sunk by any I/O pin........................................................................................................25 mA
Maximum Output Current sourced by any I/O pin...................................................................................................25 mA
Maximum Current sunk by PORTA, PORTB and PORTC ....................................................................................200 mA
Maximum Current sourced by PORTA, PORTB and PORTC...............................................................................200 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 73
PIC16C55X
FIGURE 10-1:
6.0
VOLTAGE-FREQUENCY GRAPH, 0C TA +70C (COMMERCIAL TEMPS)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
VDD
(Volts)
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
FIGURE 10-2:
VOLTAGE-FREQUENCY GRAPH,
-40C TA 0C, +70C TA +125C (OUTSIDE OF COMMERCIAL TEMPS)
6.0
5.5
5.0
4.5
4.0
3.5
VDD
(Volts)
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
DS40143E-page 74
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
FIGURE 10-3:
6.0
VOLTAGE-FREQUENCY GRAPH, 0C TA +85C
5.5
5.0
4.5
4.0
3.5
VDD
(Volts)
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
FIGURE 10-4:
6.0
PIC16LC554/557/558 VOLTAGE-FREQUENCY GRAPH, -40C TA 0C
5.5
5.0
4.5
4.0
3.5
3.0
VDD
(Volts)
2.7
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 75
PIC16C55X
10.1 DC Characteristics: PIC16C55X-04 (Commercial, Industrial, Extended)
PIC16C55X-20 (Commercial, Industrial, Extended)
HCS1365-04 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40C TA +85C for industrial and
DC Characteristics
0C TA +70C for commercial and
-40C TA +125C for extended
Param
No.
Sym
Characteristic
Min Typ† Max Units
Conditions
VDD
Supply Voltage
D001
16LC55X 3.0
—
5.5
5.5
V
XT and RC osc configuration
LP osc configuration
2.5
D001
D001A
16C55X 3.0
4.5
—
—
5.5
5.5
V
V
XT, RC and LP osc configuration
HS osc configuration
D002
D003
D004
VDR
RAM Data Retention
Voltage(1)
—
1.5*
VSS
—
—
—
—
V
Device in SLEEP mode
VPOR VDD Start Voltage to
—
V
See Section 6.4, Power-on Reset for
details
ensure Power-on Reset
SVDD VDD Rise Rate to ensure
0.05*
V/ms See Section 6.4, Power-on Reset for
details
Power-on Reset
IDD
Supply Current(2)
16LC55X
16C55X
D010
—
—
1.4
26
2.5 mA XT and RC osc configuration
Fosc = 2.0 MHz, VDD = 3.0V, WDT
disabled(4)
D010A
53
A LP osc configuration
Fosc = 32 kHz, VDD = 3.0V, WDT
disabled
D010
—
—
1.8
35
3.3 mA XT and RC osc configuration
FOSC = 4 MHz, VDD = 5.5V,
WDT disabled(4)
D010A
70
A LP osc configuration,
PIC16C55X-04 only
FOSC = 32 kHz, VDD = 4.0V,
WDT disabled
D013
*
—
9.0
20
mA HS osc configuration
FOSC = 20 MHz, VDD = 5.5V,
WDT disabled
These parameters are characterized but not tested.
†
Data is “Typ” column is at 5V, 25C,unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins configured as input, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins configured as input and tied to VDD or VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in k
5: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
DS40143E-page 76
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
10.1 DC Characteristics: PIC16C55X-04 (Commercial, Industrial, Extended)
PIC16C55X-20 (Commercial, Industrial, Extended)
HCS1365-04 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40C TA +85C for industrial and
0C TA +70C for commercial and
DC Characteristics
-40C TA +125C for extended
Param
Sym
No.
Characteristic
Power-Down Current(3)
Min Typ† Max Units
Conditions
D020
IPD
16LC55X
—
—
0.7
1.0
2
A VDD = 3.0V, WDT disabled
16C55X
2.5
15
A VDD = 4.0V, WDT disabled
A (+85C to +125C)
IWDT WDT Current(5)
16LC55X
16C55X
—
—
6.0
6.0
15
20
A VDD = 3.0V
A VDD = 4.0V
(+85C to +125C)
*
These parameters are characterized but not tested.
†
Data is “Typ” column is at 5V, 25C,unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins configured as input, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins configured as input and tied to VDD or VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in k
5: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 77
PIC16C55X
10.2 DC Characteristics: PIC16C55X (Commercial, Industrial, Extended)
PIC16LC55X(Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial and
DC Characteristics
0°C TA +70°C for commercial and
-40°C TA +125°C for automotive
Operating voltage VDD range as described in DC spec Table 10-1
Param.
Sym
Characteristic
Min
Typ†
Max
Unit
Conditions
No.
VIL
Input Low Voltage
I/O ports
D030
with TTL buffer
VSS
—
—
0.8V
0.15 VDD
V
VDD = 4.5V to 5.5V
otherwise
D031
D032
with Schmitt Trigger input
VSS
VSS
0.2 VDD
0.2 VDD
V
V
MCLR, RA4/T0CKI,OSC1 (in
RC mode)
(Note1)
D033
OSC1 (in XT* and HS)
OSC1 (in LP*)
VSS
VSS
—
—
0.3 VDD
V
V
0.6 VDD-1.0
VIH
Input High Voltage
I/O ports
—
D040
with TTL buffer
2.0V
0.8 + 0.25 VDD
—
—
VDD
VDD
V
V
VDD = 4.5V to 5.5V
otherwise
D041
D042
with Schmitt Trigger input
MCLR RA4/T0CKI
0.8V
VDD
VDD
VDD
0.8 VDD
—
—
V
V
D043
D043A
OSC1 (XT*, HS and LP*)
OSC1 (in RC mode)
0.7 VDD
0.9 VDD
(Note1)
D070
PORTB weak pull-up current
50
200
400
VDD = 5.0V, VPIN = VSS
IPURB
IIL
A
(2)(3)
Input Leakage Current
I/O ports (Except PORTA)
PORTA
1.0
0.5
VSS VPIN VDD, pin at hi-
impedance
A
A
D060
—
—
Vss VPIN VDD, pin at hi-
impedance
D061
D063
RA4/T0CKI
—
—
—
—
1.0
5.0
Vss VPIN VDD
A
A
OSC1, MCLR
Vss VPIN VDD, XT, HS and
LP osc configuration
VOL
Output Low Voltage
D080
D083
I/O ports
—
—
0.6
V
IOL=8.5 mA, VDD=4.5V, -40 to
+85C
—
—
—
—
0.6
0.6
V
V
IOL=7.0 mA, VDD=4.5V, +125C
OSC2/CLKOUT
(RC only)
IOL=1.6 mA, VDD=4.5V, -40 to
+85C
—
—
—
0.6
—
V
V
IOL=1.2 mA, VDD=4.5V, +125C
(3)
VOH
Output High Voltage
D090
I/O ports (Except RA4)
VDD-0.7
IOH=-3.0 mA, VDD=4.5V, -40 to
+85C
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C55X be
driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent nor-
mal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
DS40143E-page 78
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
10.2 DC Characteristics: PIC16C55X (Commercial, Industrial, Extended)
PIC16LC55X(Commercial, Industrial, Extended) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial and
0°C TA +70°C for commercial and
DC Characteristics
-40°C TA +125°C for automotive
Operating voltage VDD range as described in DC spec Table 10-1
Param.
Sym
Characteristic
Min
Typ†
Max
Unit
Conditions
No.
VDD-0.7
—
—
V
IOH=-2.5 mA,
VDD=4.5V, +125C
D092
OSC2/CLKOUT
(RC only)
VDD-0.7
VDD-0.7
—
—
—
—
V
V
V
IOH=-1.3 mA, VDD=4.5V, -40 to
+85C
IOH=-1.0 mA,
VDD=4.5V, +125C
*
VOD
Open-Drain High Voltage
Capacitive Loading Specs on Output Pins
10*
RA4 pin
D100
COSC OSC2 pin
2
15
50
pF In XT, HS and LP modes when
external clock used to drive
OSC1.
D101
CIO
All I/O pins/OSC2 (in RC
mode)
These parameters are characterized but not tested.
pF
*
†
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C55X be
driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent nor-
mal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 79
PIC16C55X
10.3 Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase subscripts (pp) and their meanings:
pp
ck
T
Time
CLKOUT
I/O port
MCLR
os
t0
OSC1
T0CKI
io
mc
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
FIGURE 10-5:
LOAD CONDITIONS
Load condition 1
VDD/2
Load condition 2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
DS40143E-page 80
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
10.4 Timing Diagrams and Specifications
FIGURE 10-6:
EXTERNAL CLOCK TIMING
Q4
Q3
Q4
4
Q1
Q1
Q2
OSC1
1
3
3
4
2
CLKOUT
TABLE 10-1: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
Sym Characteristic
Min
Typ†
Max
Units
Conditions
No.
(1)
Fos External CLKIN Frequency
DC
DC
DC
—
—
—
4
MHz XT and RC osc mode, VDD=5.0V
MHz HS osc mode
20
200
kHz LP osc mode
(1)
Oscillator Frequency
DC
0.1
1
—
—
—
–
4
4
MHz RC osc mode, VDD=5.0V
MHz XT osc mode
20
200
MHz HS osc mode
DC
kHz LP osc mode
(1)
1
Tosc External CLKIN Period
250
50
5
—
—
—
—
—
—
ns
ns
XT and RC osc mode
HS osc mode
s LP osc mode
(1)
Oscillator Period
250
250
50
—
—
—
—
—
10,000
1,000
—
ns
ns
ns
RC osc mode
XT osc mode
HS osc mode
5
s LP osc mode
(1)
2
Tcy
Instruction Cycle Time
1.0
100*
2*
Fos/4
—
DC
—
—
—
—
—
—
s
ns
TCY=FOS/4
3*
TosL, External Clock in (OSC1) High or
TosH Low Time
XT osc mode
—
s LP osc mode
20*
25*
50*
15*
—
ns
ns
ns
ns
HS osc mode
XT osc mode
LP osc mode
HS osc mode
4*
TosR, External Clock in (OSC1) Rise or
TosF Fall Time
—
—
—
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0 V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1 pin.
When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 81
PIC16C55X
FIGURE 10-7:
CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
10
11
22
23
CLKOUT
12
13
18
19
14
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note 1: All tests must be done with specified capacitance loads (Figure 10-5) 50 pF on I/O pins and CLKOUT.
DS40143E-page 82
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
TABLE 10-2: CLKOUT AND I/O TIMING REQUIREMENTS
Parameter #
Sym
Characteristic
Min
Typ†
Max
Units
10*
TosH2ckL OSC1 to CLKOUT(1)
—
—
75
—
200
400
ns
ns
11*
12*
13*
TosH2ckH OSC1 to CLKOUT (1)
—
—
75
—
200
400
ns
ns
TckR
TckF
CLKOUT rise time(1)
CLKOUT fall time(1)
—
—
35
—
100
200
ns
ns
—
—
35
—
100
200
ns
ns
14*
15*
TckL2ioV CLKOUT to Port out valid(1)
TioV2ckH Port in valid before CLKOUT (1)
—
—
20
ns
Tosc +200 ns
Tosc +400 ns
—
—
—
—
ns
ns
16*
17*
TckH2ioI Port in hold after CLKOUT (1)
TosH2ioV OSC1 (Q1 cycle) to Port out valid
0
—
—
ns
—
—
50
150
300
ns
ns
18*
TosH2ioI OSC1 (Q2 cycle) to Port input invalid (I/O in
100
200
—
—
—
—
ns
ns
hold time)
19*
20*
TioV2osH Port input valid to OSC1(I/O in setup time)
0
—
—
ns
TioR
TioF
Tinp
Trbp
Port output rise time
—
—
10
—
40
80
ns
ns
21*
22*
23*
Port output fall time
—
—
10
—
40
80
ns
ns
RB0/INT pin high or low time
RB<7:4> change interrupt high or low time
25
40
—
—
—
—
ns
ns
Tcy
—
—
ns
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 83
PIC16C55X
FIGURE 10-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Timeout
32
OSC
Timeout
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
TABLE 10-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
30
31
TmcL MCLR Pulse Width (low)
2000
7*
—
—
ns
-40 to +85C
Twdt Watchdog Timer Timeout Period
(No Prescaler)
18
33*
ms VDD = 5.0V, -40 to +85C
32
Tost Oscillation Start-up Timer Period
—
1024
TOSC
—
—
TOSC = OSC1 period
33
34
Tpwrt Power-up Timer Period
28*
72
—
132*
2.0*
ms VDD = 5.0V, -40 to +85C
s
TIOZ
I/O hi-impedance from MCLR low
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS40143E-page 84
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
FIGURE 10-9:
RA4/T0CKI
TIMER0 CLOCK TIMING
41
40
42
TMR0
TABLE 10-4: TIMER0 CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max Units
Conditions
40
Tt0H T0CKI High Pulse Width
Tt0L T0CKI Low Pulse Width
Tt0P T0CKI Period
No Prescaler
0.5 TCY + 20*
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
With Prescaler
No Prescaler
With Prescaler
41
42
0.5 TCY + 20*
10*
TCY + 40*
N
N = prescale value
(1, 2, 4, ..., 256)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
FIGURE 10-10:
LOAD CONDITIONS
Load condition 1
VDD/2
Load condition 2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 85
PIC16C55X
NOTES:
DS40143E-page 86
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
11.0 PACKAGING INFORMATION
11.1 Package Marking Information
18-Lead PDIP
Example
PIC16C558
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
-04I / P456
YYWWNNN
9823 CBA
28-Lead PDIP
Example
PIC16C557
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
-04I / P456
9823 CBA
20-Lead SSOP
Example
XXXXXXXXXXX
XXXXXXXXXXX
PIC16C558
-04/SS218
0020 CBP
YYWWNNN
28-Lead SSOP
Example
PIC16C557
-04I / SS123
XXXXXXXXXXXX
XXXXXXXXXXXX
0025 CBA
YYWWNNN
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( )
e
3
*
e
3
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 87
PIC16C55X
Package Marking Information (Cont’d)
18-Lead SOIC (.300”)
Example
PIC16C558
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
-04I / S0218
9818 CDK
YYWWNNN
28-Lead SOIC (.300”)
Example
PIC16C557
-04I / P456
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
9823 CBA
YYWWNNN
18-Lead CERDIP Windowed
Example
XXXXXXXX
XXXXXXXX
16C558
/JW
YYWWNNN
9801 CBA
28-Lead CERDIP Windowed
Example
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
16C557
/JW
YYWWNNN
9801 CBA
DS40143E-page 88
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
18-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
D
2
n
1
E
A2
L
A
c
A1
B1
p
B
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.890
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
22.61
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.898
.130
.012
.058
.018
.370
10
.325
.260
.905
.135
.015
.070
.022
.430
15
7.94
6.35
22.80
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
22.99
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-007
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 89
PIC16C55X
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
D
2
n
1
E
A2
L
A
c
B1
A1
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.100
.150
.130
2.54
3.81
3.30
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A
A2
A1
E
.140
.160
3.56
4.06
.125
.015
.300
.275
1.345
.125
.008
.040
.016
.320
.135
3.18
0.38
7.62
6.99
34.16
3.18
0.20
1.02
3.43
.310
.285
1.365
.130
.012
.053
.019
.350
10
.325
.295
1.385
.135
.015
.065
.022
.430
15
7.87
7.24
8.26
7.49
35.18
3.43
0.38
1.65
0.56
10.92
15
E1
D
34.67
3.30
Tip to Seating Plane
Lead Thickness
L
c
0.29
Upper Lead Width
B1
B
1.33
Lower Lead Width
0.41
8.13
5
0.48
8.89
10
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
5
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
DS40143E-page 90
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
p
E1
D
2
B
n
1
h
45
c
A2
A
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.050
.099
.091
.008
.407
.295
.454
.020
.033
4
1.27
Overall Height
A
.093
.104
2.36
2.24
2.50
2.31
0.20
10.34
7.49
11.53
0.50
0.84
4
2.64
2.39
0.30
10.67
7.59
11.73
0.74
1.27
8
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.291
.446
.010
.016
0
.094
.012
.420
.299
.462
.029
.050
8
§
0.10
10.01
7.39
11.33
0.25
0.41
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
Foot Angle
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.012
.020
15
0.23
0.36
0
0.27
0.42
12
0.30
0.51
15
B
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-051
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 91
PIC16C55X
28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
p
D
B
2
n
1
h
45
c
A2
A
L
A1
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
28
28
.050
.099
.091
.008
.407
.295
.704
.020
.033
4
1.27
2.50
2.31
0.20
10.34
7.49
17.87
0.50
0.84
4
Overall Height
A
.093
.104
2.36
2.64
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.288
.695
.010
.016
0
.094
.012
.420
.299
.712
.029
.050
8
2.24
0.10
10.01
7.32
17.65
0.25
0.41
0
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
Foot Angle Top
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.013
.020
15
0.23
0.36
0
0.28
0.42
12
0.33
0.51
15
B
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
DS40143E-page 92
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
D
W2
2
1
n
W1
E
A2
A
c
L
A1
B1
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.100
.183
.160
.023
.313
.290
.900
.138
.010
.055
.019
.385
.140
.200
2.54
Top to Seating Plane
Ceramic Package Height
Standoff
A
.170
.195
4.32
3.94
4.64
4.06
0.57
7.94
7.37
22.86
3.49
0.25
1.40
0.47
9.78
3.56
5.08
4.95
A2
A1
.155
.015
.300
.285
.880
.125
.008
.050
.016
.345
.130
.190
.165
.030
.325
.295
.920
.150
.012
.060
.021
.425
.150
.210
4.19
0.76
8.26
7.49
23.37
3.81
0.30
1.52
0.53
10.80
3.81
5.33
0.38
7.62
7.24
22.35
3.18
0.20
1.27
0.41
8.76
3.30
4.83
Shoulder to Shoulder Width
Ceramic Pkg. Width
Overall Length
E
E1
D
L
Tip to Seating Plane
Lead Thickness
c
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Window Width
B1
B
§
eB
W1
W2
Window Length
* Controlling Parameter
§ Significant Characteristic
JEDEC Equivalent: MO-036
Drawing No. C04-010
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 93
PIC16C55X
28-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
D
W2
2
1
n
W1
E
A2
A
c
L
B1
B
A1
eB
p
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.100
.183
.160
.023
.313
.290
1.458
.140
.010
.058
.019
.385
.140
.300
2.54
Top to Seating Plane
Ceramic Package Height
Standoff
A
.170
.195
4.32
3.94
4.64
4.06
0.57
7.94
7.37
37.02
3.56
0.25
1.46
0.47
9.78
3.56
7.62
4.95
A2
A1
.155
.015
.300
.285
1.430
.135
.008
.050
.016
.345
.130
.290
.165
.030
.325
.295
1.485
.145
.012
.065
.021
.425
.150
.310
4.19
0.76
8.26
7.49
37.72
3.68
0.30
1.65
0.53
10.80
3.81
7.87
0.38
7.62
7.24
36.32
3.43
0.20
1.27
0.41
8.76
3.30
7.37
Shoulder to Shoulder Width
Ceramic Pkg. Width
Overall Length
E
E1
D
L
Tip to Seating Plane
Lead Thickness
c
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Window Width
B1
B
§
eB
W1
W2
Window Length
* Controlling Parameter
§ Significant Characteristic
JEDEC Equivalent: MO-058
Drawing No. C04-080
DS40143E-page 94
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
p
D
B
2
1
n
c
A2
A
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
20
MAX
n
p
Number of Pins
Pitch
20
.026
.073
.068
.006
.309
.207
.284
.030
.007
4
0.65
Overall Height
A
.068
.078
1.73
1.63
1.85
1.73
0.15
7.85
5.25
7.20
0.75
0.18
101.60
0.32
5
1.98
1.83
0.25
8.18
5.38
7.34
0.94
0.25
203.20
0.38
10
Molded Package Thickness
Standoff
A2
A1
E
.064
.002
.299
.201
.278
.022
.004
0
.072
.010
.322
.212
.289
.037
.010
8
§
0.05
7.59
5.11
7.06
0.56
0.10
0.00
0.25
0
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
c
Lead Thickness
Foot Angle
Lead Width
B
.010
0
.013
5
.015
10
Mold Draft Angle Top
Mold Draft Angle Bottom
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No. C04-072
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 95
PIC16C55X
28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
p
D
B
2
n
1
A
c
A2
A1
L
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.026
.073
.068
.006
.309
.207
.402
.030
.007
4
0.65
Overall Height
A
.068
.078
1.73
1.63
1.85
1.73
0.15
7.85
5.25
10.20
0.75
0.18
101.60
0.32
5
1.98
Molded Package Thickness
Standoff
A2
A1
E
.064
.002
.299
.201
.396
.022
.004
0
.072
.010
.319
.212
.407
.037
.010
8
1.83
0.25
8.10
5.38
10.34
0.94
0.25
203.20
0.38
10
§
0.05
7.59
5.11
10.06
0.56
0.10
0.00
0.25
0
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
c
Lead Thickness
Foot Angle
Lead Width
B
.010
0
.013
5
.015
10
Mold Draft Angle Top
Mold Draft Angle Bottom
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-150
Drawing No. C04-073
DS40143E-page 96
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
APPENDIX A: ENHANCEMENTS
APPENDIX B: COMPATIBILITY
The following are the list of enhancements over the
PIC16C5X microcontroller family:
To convert code written for PIC16C5X to PIC16C55X,
the user should take the following steps:
1. Instruction word length is increased to 14 bits.
This allows larger page sizes both in program
memory (4K now as opposed to 512 before) and
register file (up to 128 bytes now versus 32
bytes before).
1. Remove any program memory page select
operations (PA2, PA1, PA0 bits) for CALL, GOTO.
2. Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
2. A PC high latch register (PCLATH) is added to
handle program memory paging. PA2, PA1, PA0
bits are removed from STATUS register.
3. Eliminate any data memory page switching.
Redefine data variables to reallocate them.
4. Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
3. Data memory paging is slightly redefined.
STATUS register is modified.
5. Change RESET vector to 0000h.
4. Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW.
APPENDIX C: REVISION HISTORY
Two instructions TRIS and OPTION are being
phased out although they are kept for
compatibility with PIC16C5X.
Revision E (January 2013)
Added a note to each package outline drawing.
5. OPTION and TRIS registers are made
addressable.
6. Interrupt capability is added. Interrupt vector is
at 0004h.
7. Stack size is increased to 8 deep.
8. RESET vector is changed to 0000h.
9. RESET of all registers is revised. Three different
RESET (and wake-up) types are recognized.
Registers are reset differently.
10. Wake-up from SLEEP through interrupt is
added.
11. Two separate timers, Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) are
included for more reliable power-up. These
timers are invoked selectively to avoid
unnecessary delays on power-up and wake-up.
12. PORTB has weak pull-ups and interrupt-on-
change feature.
13. Timer0 clock input, T0CKI pin is also a port pin
(RA4/T0CKI) and has a TRIS bit.
14. FSR is made a full 8-bit register.
15. “In-circuit programming” is made possible. The
user can program PIC16C55X devices using
only five pins: VDD, VSS, VPP, RB6 (clock) and
RB7 (data in/out).
16. PCON status register is added with a Power-on
Reset (POR) status bit.
17. Code protection scheme is enhanced such that
portions of the program memory can be
protected, while the remainder is unprotected.
18. PORTA inputs are now Schmitt Trigger inputs.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 97
PIC16C55X
NOTES:
DS40143E-page 98
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
CLRW......................................................................... 58
CLRWDT .................................................................... 58
COMF......................................................................... 58
DECF.......................................................................... 58
DECFSZ ..................................................................... 59
GOTO......................................................................... 59
INCF ........................................................................... 59
INCFSZ....................................................................... 60
IORLW ........................................................................ 60
IORWF........................................................................ 60
MOVF ......................................................................... 61
MOVLW ...................................................................... 60
MOVWF...................................................................... 61
NOP............................................................................ 61
OPTION...................................................................... 61
RETFIE....................................................................... 62
RETLW ....................................................................... 62
RETURN..................................................................... 62
RLF............................................................................. 62
RRF ............................................................................ 63
SLEEP........................................................................ 63
SUBLW....................................................................... 63
SUBWF....................................................................... 64
SWAPF....................................................................... 64
TRIS ........................................................................... 64
XORLW....................................................................... 65
XORWF ...................................................................... 65
Instruction Set Summary .................................................... 53
INT Interrupt ....................................................................... 42
INTCON Register................................................................ 19
Interrupts ............................................................................ 41
IORLW Instruction .............................................................. 60
IORWF Instruction .............................................................. 60
INDEX
A
ADDLW Instruction ............................................................. 55
ADDWF Instruction ............................................................. 55
ANDLW Instruction ............................................................. 55
ANDWF Instruction ............................................................. 55
Architectural Overview .......................................................... 9
Assembler
MPASM Assembler ..................................................... 67
B
BCF Instruction ................................................................... 56
Block Diagram
TIMER0....................................................................... 47
TMR0/WDT PRESCALER .......................................... 50
BSF Instruction ................................................................... 56
BTFSC Instruction............................................................... 56
BTFSS Instruction............................................................... 57
C
CALL Instruction ................................................................. 57
Clocking Scheme/Instruction Cycle .................................... 12
CLRF Instruction................................................................. 57
CLRW Instruction................................................................ 58
CLRWDT Instruction ........................................................... 58
Code Protection .................................................................. 46
COMF Instruction................................................................ 58
Configuration Bits................................................................ 31
D
Data Memory Organization ................................................. 13
DECF Instruction................................................................. 58
DECFSZ Instruction ............................................................ 59
Development Support ......................................................... 67
K
KEELOQ Evaluation and Programming Tools...................... 70
E
M
Errata .................................................................................... 3
External Crystal Oscillator Circuit ....................................... 34
MOVF Instruction................................................................ 61
MOVLW Instruction............................................................. 60
MOVWF Instruction ............................................................ 61
MPLAB C17 and MPLAB C18 C Compilers ....................... 67
MPLAB ICD In-Circuit Debugger ........................................ 69
MPLAB ICE High Performance Universal In-Circuit Emulator
with MPLAB IDE ................................................................. 68
MPLAB Integrated Development Environment Software.... 67
MPLINK Object Linker/MPLIB Object Librarian.................. 68
G
General purpose Register File ............................................ 13
GOTO Instruction................................................................ 59
I
I/O Ports.............................................................................. 23
I/O Programming Considerations........................................ 28
ICEPIC In-Circuit Emulator ................................................. 68
ID Locations........................................................................ 46
INCF Instruction .................................................................. 59
INCFSZ Instruction ............................................................. 60
In-Circuit Serial Programming............................................. 46
Indirect Addressing, INDF and FSR Registers ................... 21
Instruction Flow/Pipelining .................................................. 12
Instruction Set
N
NOP Instruction .................................................................. 61
O
One-Time-Programmable (OTP) Devices ............................ 7
OPTION Instruction ............................................................ 61
OPTION Register................................................................ 18
Oscillator Configurations..................................................... 33
Oscillator Start-up Timer (OST).......................................... 36
ADDLW ....................................................................... 55
ADDWF....................................................................... 55
ANDLW ....................................................................... 55
ANDWF....................................................................... 55
BCF............................................................................. 56
BSF............................................................................. 56
BTFSC ........................................................................ 56
BTFSS ........................................................................ 57
CALL........................................................................... 57
CLRF........................................................................... 57
P
PCL and PCLATH............................................................... 21
PCON Register................................................................... 20
PICDEM 1 Low Cost PIC MCU Demonstration Board........ 69
PICDEM 17 Demonstration Board...................................... 70
PICDEM 2 Low Cost PIC16CXX Demonstration Board ..... 69
PICDEM 3 Low Cost PIC16CXXX Demonstration Board... 70
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 99
PIC16C55X
PICSTART Plus Entry Level Development Programmer ....69
Port RB Interrupt .................................................................42
PORTA................................................................................23
PORTB.......................................................................... 25, 27
Power Control/Status Register (PCON)..............................37
Power-Down Mode (SLEEP)...............................................45
Power-On Reset (POR) ......................................................36
Power-up Timer (PWRT).....................................................36
Prescaler.............................................................................49
PRO MATE II Universal Device Programmer .....................69
Program Memory Organization...........................................13
Q
Quick-Turnaround-Production (QTP) Devices ......................7
R
RC Oscillator.......................................................................34
Reset...................................................................................35
RETFIE Instruction..............................................................62
RETLW Instruction..............................................................62
RETURN Instruction............................................................62
RLF Instruction....................................................................62
RRF Instruction ...................................................................63
S
Serialized Quick-Turnaround-Production (SQTP) Devices...7
SLEEP Instruction...............................................................63
Software Simulator (MPLAB SIM).......................................68
Special Features of the CPU...............................................31
Special Function Registers .................................................15
Stack ...................................................................................21
Status Register....................................................................17
SUBLW Instruction..............................................................63
SUBWF Instruction..............................................................64
SWAPF Instruction..............................................................64
T
Timer0
TIMER0.......................................................................47
TIMER0 (TMR0) Interrupt ...........................................47
TIMER0 (TMR0) Module.............................................47
TMR0 with External Clock...........................................49
Timer1
Switching Prescaler Assignment.................................51
Timing Diagrams and Specifications...................................81
TMR0 Interrupt....................................................................42
TRIS Instruction ..................................................................64
TRISA..................................................................................23
TRISB............................................................................ 25, 27
W
Watchdog Timer (WDT) ......................................................43
WWW, On-Line Support........................................................3
X
XORLW Instruction .............................................................65
XORWF Instruction .............................................................65
DS40143E-page 100
Preliminary
1996-2013 Microchip Technology Inc.
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
1996-2013 Microchip Technology Inc.
DS40143E-page 101
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
RE:
Technical Publications Manager
Reader Response
Total Pages Sent ________
From:
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Literature Number: DS40143E
Application (optional):
Would you like a reply?
Y
N
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS40143E-page 102
1996-2013 Microchip Technology Inc.
PIC16C55X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature Package
Range
Pattern
a)
b)
c)
PIC17C756–16L Commercial Temp.,
PLCC package, 16 MHz,
normal VDD limits
PIC17LC756–08/PT Commercial Temp.,
TQFP package, 8MHz,
extended VDD limits
Device
PIC17C756: Standard VDD range
PIC17C756T: (Tape and Reel)
PIC17LC756: Extended VDD range
PIC17C756–33I/PT Industrial Temp.,
TQFP package, 33 MHz,
normal VDD limits
Temperature Range
Package
-
I
=
=
0C to +70C
-40C to +85C
CL
PT
L
=
=
=
Windowed LCC
TQFP
PLCC
Pattern
QTP, SQTP, ROM Code (factory specified) or
Special Requirements. Blank for OTP and
Windowed devices.
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Worldwide Site (www.microchip.com)
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 103
PIC16C55X
NOTES:
DS40143E-page 104
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
NOTES:
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 105
PIC16C55X
DS40143E-page 106
Preliminary
1996-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
32
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 1996-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620769737
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 107
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
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Technical Support:
http://www.microchip.com/
support
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11/29/12
DS40143E-page 108
Preliminary
1996-2013 Microchip Technology Inc.
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