PIC16CR620A-20E/P301

PIC16C62X

EPROM-Based 8-Bit CMOS Microcontroller

Devices included in this data sheet:

Pin Diagrams

Referred to collectively as PIC16C62X .

PDIP, SOIC, Windowed CERDIP

• PIC16C620

• PIC16C621

• PIC16C622

• PIC16C620A

• PIC16C621A

• PIC16C622A

RA1/AN1

RA2/AN2/VREF

RA3/AN3

•1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

RA0/AN0

OSC1/CLKIN

OSC2/CLKOUT

VDD

RB7

RB6

RB5

RA4/T0CKI

MCLR/VPP

• PIC16CR620A

VSS

RB0/INT

RB1

High Performance RISC CPU:

RB2

RB3

• Only 35 instructions to learn

• All single-cycle instructions (200 ns), except for

program branches which are two-cycle

• Operating speed:

RB4

- DC - 20 MHz clock input

SSOP

- DC - 200 ns instruction cycle

RA1/AN1

RA2/AN2/VREF

RA3/AN3

•1

2

20

19

18

17

16

15

14

13

12

11

Device

Program

Memory

Data

Memory

RA0/AN0

OSC1/CLKIN

OSC2/CLKOUT

RA4/T0CKI

3

MCLR/VPP

4

VDD

RB7

RB6

RB5

RB4

VSS

5

PIC16C620

512

1K

80

96

VSS

6

RB0/INT

RB1

7

PIC16C620A

PIC16CR620A

PIC16C621

8

RB2

RB3

9

96

10

80

PIC16C621A

PIC16C622

1K

96

2K

128

Special Microcontroller Features (cont’d)

PIC16C622A

• Interrupt capability

2K

• Programmable code protection

• Power saving SLEEP mode

• Selectable oscillator options

• Serial in-circuit programming (via two pins)

• Four user programmable ID locations

• 16 special function hardware registers

• 8-level deep hardware stack

• Direct, Indirect and Relative addressing modes

CMOS Technology:

Peripheral Features:

• Low-power, high-speed CMOS EPROM technol-

ogy

• Fully static design

• Wide operating voltage range

- PIC16C62X - 2.5V to 6.0V

• 13 I/O pins with individual direction control

• High current sink/source for direct LED drive

• Analog comparator module with:

- Two analog comparators

- Programmable on-chip voltage reference

(VREF) module

- Programmable input multiplexing from device

inputs and internal voltage reference

- Comparator outputs can be output signals

• Timer0: 8-bit timer/counter with 8-bit

programmable prescaler

- PIC16C62XA - 2.5V to 5.5V

- PIC16CR620A - 2.0V to 5.5V

• Commercial, industrial and extended tempera-

ture range

• Low power consumption

- < 2.0 mA @ 5.0V, 4.0 MHz

- 15 µA typical @ 3.0V, 32 kHz

- < 1.0 µA typical standby current @ 3.0V

Special Microcontroller Features:

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up

Timer (OST)

• Brown-out Reset

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 1

PIC16C62X

Device Differences

Process

Technology

(Microns)

Voltage

Range

Device

Oscillator

PIC16C620

PIC16C621

PIC16C622

PIC16C620A

PIC16CR620A

PIC16C621A

PIC16C622A

2.5 - 6.0

2.5 - 5.5

2.0 - 5.5

2.5 - 5.5

See Note 1

0.9

0.7

Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.

DS30235G-page 2

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

Table of Contents

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

General Description......................................................................................................................................................................5

PIC16C62X Device Varieties .......................................................................................................................................................7

Architectural Overview .................................................................................................................................................................9

Memory Organization................................................................................................................................................................ 13

I/O Ports .................................................................................................................................................................................... 25

Timer0 Module .......................................................................................................................................................................... 31

Comparator Module................................................................................................................................................................... 37

Voltage Reference Module........................................................................................................................................................ 43

Special Features of the CPU..................................................................................................................................................... 45

10.0 Instruction Set Summary........................................................................................................................................................... 61

11.0 Development Support................................................................................................................................................................ 73

12.0 Electrical Specifications............................................................................................................................................................. 79

13.0 Device Characterization Information ......................................................................................................................................... 93

14.0 Packaging Information............................................................................................................................................................... 95

Appendix A:

Appendix B:

Appendix C:

Appendix D:

Enhancements.......................................................................................................................................................... 101

Compatibility ............................................................................................................................................................. 101

What’s New............................................................................................................................................................... 102

What’s Changed ....................................................................................................................................................... 102

Index .................................................................................................................................................................................................. 103

PIC16C62X Product Identification System ........................................................................................................................................ 107

To Our Valued Customers

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.

Errata

An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended

workarounds. As device/documentation issues become known to us, we will publish an errata sheet.The errata will specify the revi-

sion of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales ofﬁce (see last page)

• The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277

When contacting a sales ofﬁce or the literature center, please specify which device, revision of silicon and data sheet (include lit-

erature number) you are using.

Corrections to this Data Sheet

We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure

that this document is correct. However, we realize that we may have missed a few things. If you ﬁnd any information that is missing

or appears in error, please:

• Fill out and mail in the reader response form in the back of this data sheet.

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We appreciate your assistance in making this a better document.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 3

PIC16C62X

NOTES:

DS30235G-page 4

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

A highly reliable Watchdog Timer with its own on-chip

RC oscillator provides protection against software

lock- up.

1.0

The

GENERAL DESCRIPTION

PIC16C62X

are

18

and

20

ROM/EPROM-based members of the versatile PICmi-

cro™ family of low-cost, high-performance, CMOS,

fully-static, 8-bit microcontrollers.

A UV-erasable CERDIP-packaged version is ideal for

code development while the cost-effective One-Time

Programmable (OTP) version is suitable for production

in any volume.

All PICmicro™ microcontrollers employ an advanced

RISC architecture. The PIC16C62X have enhanced

core features, eight-level deep stack, and multiple inter-

nal and external interrupt sources. The separate

instruction and data buses of the Harvard architecture

allow a 14-bit wide instruction word with the separate

8-bit wide data. The two-stage instruction pipeline

allows all instructions to execute in a single-cycle,

except for program branches (which require two

cycles). A total of 35 instructions (reduced instruction

set) are available. Additionally, a large register set gives

some of the architectural innovations used to achieve a

very high performance.

Table 1-1 shows the features of the PIC16C62X

mid-range microcontroller families.

A simpliﬁed block diagram of the PIC16C62X is shown

in Figure 3-1.

The PIC16C62X series ﬁt perfectly in applications

ranging from battery chargers to low-power remote

sensors.The EPROM technology makes customization

of application programs (detection levels, pulse gener-

ation, timers, etc.) extremely fast and convenient. The

small footprint packages make this microcontroller

series perfect for all applications with space limitations.

Low-cost, low-power, high-performance, ease of use

and I/O ﬂexibility make the PIC16C62X very versatile.

PIC16C62X microcontrollers typically achieve a 2:1

code compression and a 4:1 speed improvement over

other 8-bit microcontrollers in their class.

1.1

Family and Upward Compatibility

The PIC16C620A, PIC16C621A and PIC16CR620A

have 96 bytes of RAM. The PIC16C622(A) has 128

bytes of RAM. Each device has 13 I/O pins and an 8-bit

timer/counter with an 8-bit programmable prescaler. In

addition, the PIC16C62X adds two analog comparators

with a programmable on-chip voltage reference mod-

ule. The comparator module is ideally suited for appli-

cations requiring a low-cost analog interface (e.g.,

battery chargers, threshold detectors, white goods

controllers, etc).

Those users familiar with the PIC16C5X family of

microcontrollers will realize that this is an enhanced

version of the PIC16C5X architecture. Please refer to

Appendix A for a detailed list of enhancements. Code

written for the PIC16C5X can be easily ported to

PIC16C62X family of devices (Appendix B). The

PIC16C62X family ﬁlls the niche for users wanting to

migrate up from the PIC16C5X family and not needing

various peripheral features of other members of the

PIC16XX mid-range microcontroller family.

PIC16C62X devices have special features to reduce

external components, thus reducing system cost,

enhancing system reliability and reducing power con-

sumption.There are four oscillator options, of which the

single pin RC oscillator provides a low-cost solution,

the LP oscillator minimizes power consumption, XT is a

standard crystal, and the HS is for High Speed crystals.

The SLEEP (power-down) mode offers power savings.

The user can wake up the chip from SLEEP through

several external and internal interrupts and reset.

1.2

Development Support

The PIC16C62X family is supported by a full-featured

macro assembler, a software simulator, an in-circuit

emulator, a low-cost development programmer and a

full-featured programmer. A “C” compiler and fuzzy

logic support tools are also available.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 5

PIC16C62X

TABLE 1-1:

PIC16C62X FAMILY OF DEVICES

PIC16C620 PIC16C620A PIC16CR620A PIC16C621

PIC16C621A PIC16C622 PIC16C622A

Maximum Frequency 20

of Operation (MHz)

20

Clock

EPROM Program

Memory

(x14 words)

512

1K

2K

Memory

Data Memory (bytes) 80

96

80

96

128

TMR0

2

128

TMR0

2

Timer Module(s)

Comparators(s)

TMR0

2

TMRO

2

TMR0

2

TMR0

2

Peripherals

Features

Internal Reference

Voltage

Yes

Interrupt Sources

I/O Pins

4

13

Voltage Range (Volts) 2.5-6.0

3.0-5.5

Yes

2.5-5.5

Yes

2.5-6.0

Yes

3.0-5.5

Yes

2.5-6.0

Yes

3.0-5.5

Yes

Brown-out Reset

Packages

Yes

18-pin DIP,

SOIC;

18-pin DIP,

SOIC;

18-pin DIP,

SOIC;

18-pin DIP,

SOIC;

18-pin DIP,

SOIC;

18-pin DIP,

SOIC;

18-pin DIP,

SOIC;

20-pin SSOP 20-pin SSOP 20-pin SSOP

20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP

All PICmicro™ Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high

I/O current capability. All PIC16C62X Family devices use serial programming with clock pin RB6 and data pin RB7.

DS30235G-page 6

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

2.3

Quick-Turnaround-Production (QTP)

Devices

2.0

PIC16C62X DEVICE VARIETIES

A variety of frequency ranges and packaging options are

available. Depending on application and production

requirements the proper device option can be selected

using the information in the PIC16C62X Product

Identiﬁcation System section at the end of this data

sheet. When placing orders, please use this page of the

data sheet to specify the correct part number.

Microchip offers a QTP Programming Service for

factory production orders. This service is made

available for users who chose not to program a medium

to high quantity of units and whose code patterns have

stabilized.The devices are identical to the OTP devices

but with all EPROM locations and conﬁguration options

already programmed by the factory. Certain code and

prototype veriﬁcation procedures apply before

production shipments are available. Please contact

your MicrochipTechnology sales ofﬁce for more details.

2.1

UV Erasable Devices

The UV erasable version, offered in CERDIP package

is optimal for prototype development and pilot

programs. This version can be erased and

reprogrammed to any of the oscillator modes.

2.4

Serialized

Quick-Turnaround-Production

(SQTP^SM) Devices

Microchip's

PICSTART

and

PRO MATE

programmers both support programming of the

PIC16C62X.

Microchip offers a unique programming service where

a few user-deﬁned locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or

sequential.

2.2

One-Time-Programmable (OTP)

Devices

The availability of OTP devices is especially useful for

customers who need the ﬂexibility for frequent code

updates and small volume applications. In addition to

the program memory, the conﬁguration bits must also

be programmed.

Serial programming allows each device to have a

unique number which can serve as an entry-code,

password or ID number.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 7

PIC16C62X

NOTES:

DS30235G-page 8

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

The PIC16C62X devices contain an 8-bit ALU and

working register. The ALU is a general purpose

arithmetic unit. It performs arithmetic and Boolean

functions between data in the working register and any

register ﬁle.

3.0

ARCHITECTURAL OVERVIEW

The high performance of the PIC16C62X family can be

attributed to a number of architectural features

commonly found in RISC microprocessors. To begin

with, the PIC16C62X uses a Harvard architecture, in

which, program and data are accessed from separate

memories using separate busses. This improves

bandwidth over traditional von Neumann architecture

where program and data are fetched from the same

memory. Separating program and data memory further

allows instructions to be sized differently than 8-bit

wide data word. Instruction opcodes are 14-bits wide

making it possible to have all single word instructions.

A 14-bit wide program memory access bus fetches a

14-bit instruction in a single cycle. A two-stage pipeline

overlaps fetch and execution of instructions.

Consequently, all instructions (35) execute in a sin-

gle-cycle (200 ns @ 20 MHz) except for program

branches.

The ALU is 8-bit wide and capable of addition,

subtraction, shift and logical operations. Unless

otherwise mentioned, arithmetic operations are two's

complement in nature. In two-operand instructions,

typically one operand is the working register

(W register). The other operand is a ﬁle register or an

immediate constant. In single operand instructions, the

operand is either the W register or a ﬁle register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC), and

Zero (Z) bits in the STATUS register.The C and DC bits

operate as a Borrow and Digit Borrow out bit,

respectively, bit in subtraction. See the SUBLW and

SUBWFinstructions for examples.

The PIC16C620A and PIC16CR620A address 512 x

14 on-chip program memory. The PIC16C621(A)

addresses 1K

PIC16C622(A) addresses 2K x 14 program memory.

All program memory is internal.

x

14 program memory. The

A simpliﬁed block diagram is shown in Figure 3-1, with

a description of the device pins in Table 3-1.

The PIC16C62X can directly or indirectly address its

register ﬁles or data memory. All special function

registers including the program counter are mapped in

the data memory. The PIC16C62X have an orthogonal

(symmetrical) instruction set that makes it possible to

carry out any operation on any register using any

addressing mode. This symmetrical nature and lack of

‘special optimal situations’ make programming with the

PIC16C62X simple yet efﬁcient. In addition, the

learning curve is reduced signiﬁcantly.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 9

PIC16C62X

FIGURE 3-1:

BLOCK DIAGRAM

Data Memory

(RAM)

Device

Program Memory

PIC16C620

PIC16C620A

PIC16CR620A

PIC16C621

PIC16C621A

PIC16C622

PIC16C622A

512 x 14

1K x 14

2K x 14

80 x 8

96 x 8

80 x 8

96 x 8

128 x 8

Voltage

Reference

13

8

Data Bus

Program Counter

EPROM

Program

Memory

RAM

8 Level Stack

(13-bit)

File

Registers

Program

Bus

14

RAM Addr ⁽¹⁾

9

Comparator

RA0/AN0

Addr MUX

Instruction reg

RA1/AN1

-

+

Indirect

Addr

7

Direct Addr

RA2/AN2/VREF

RA3/AN3

8

-

+

FSR reg

STATUS reg

TMR0

3

MUX

Power-up

Timer

RA4/T0CKI

Instruction

Decode &

Control

Oscillator

Start-up Timer

ALU

Power-on

Reset

Timing

Generation

W reg

I/O Ports

Watchdog

Timer

OSC1/CLKIN

OSC2/CLKOUT

Brown-out

Reset

PORTB

MCLR VDD, VSS

Note 1: Higher order bits are from the STATUS register.

DS30235G-page 10

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

TABLE 3-1:

Name

PIC16C62X PINOUT DESCRIPTION

DIP/

SSOP

Pin #

I/O/P

Type

Buffer

Type

SOIC

Pin #

Description

OSC1/CLKIN

16

15

18

17

I

ST/CMOS Oscillator crystal input/external clock source input.

OSC2/CLKOUT

O

—

Oscillator crystal output. Connects to crystal or resonator

in crystal oscillator mode. In RC mode, OSC2 pin outputs

CLKOUT which has 1/4 the frequency of OSC1, and

denotes the instruction cycle rate.

4

I/P

ST

Master clear (reset) input/programming voltage input.

This pin is an active low reset to the device.

MCLR/VPP

PORTA is a bi-directional I/O port.

Analog comparator input

RA0/AN0

17

18

1

19

20

1

I/O

ST

RA1/AN1

Analog comparator input

RA2/AN2/VREF

RA3/AN3

Analog comparator input or VREF output

Analog comparator input /output

2

RA4/T0CKI

3

Can be selected to be the clock input to the Timer0

timer/counter or a comparator output. Output is open

drain type.

PORTB is a bi-directional I/O port. PORTB can be

software programmed for internal weak pull-up on all

inputs.

(1)

RB0/INT

6

7

I/O

RB0/INT can also be selected as an external

interrupt pin.

TTL/ST

RB1

RB2

RB3

RB4

RB5

RB6

RB7

VSS

7

8

9

I/O

P

TTL

9

10

11

12

13

5

11

Interrupt on change pin.

12

Interrupt on change pin.

(2)

13

TTL/ST

—

Interrupt on change pin. Serial programming clock.

Interrupt on change pin. Serial programming data.

Ground reference for logic and I/O pins.

Positive supply for logic and I/O pins.

14

5,6

15,16

VDD

14

P

—

Legend:

O = output

— = Not used

TTL = TTL input

I/O = input/output

I = Input

P = power

ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 11

PIC16C62X

3.1

Clocking Scheme/Instruction Cycle

3.2

Instruction Flow/Pipelining

The clock input (OSC1/CLKIN pin) is internally divided

by four to generate four non-overlapping quadrature

clocks namely Q1, Q2, Q3 and Q4. Internally, the

program counter (PC) is incremented every Q1, the

instruction is fetched from the program memory and

latched into the instruction register in Q4. The

instruction is decoded and executed during the

following Q1 through Q4. The clocks and instruction

execution ﬂow is shown in Figure 3-2.

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO)

then two cycles are required to complete the instruction

(Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the “Instruction Register (IR)” in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3, and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

Q2

Q3

Q4

Q2

Q3

Q4

Q2

Q3

Q4

Q1

OSC1

Q1

Q2

Q3

Internal

phase

clock

Q4

PC

PC+1

PC+2

OSC2/CLKOUT

(RC mode)

Fetch INST (PC)

Execute INST (PC-1)

Fetch INST (PC+1)

Execute INST (PC)

Fetch INST (PC+2)

Execute INST (PC+1)

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 55h

Fetch 1

Execute 1

Fetch 2

2. MOVWF PORTB

3. CALL SUB_1

Execute 2

Fetch 3

Execute 3

Fetch 4

4. BSF

PORTA, BIT3

Flush

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch

instruction is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed.

DS30235G-page 12

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

FIGURE 4-2: PROGRAM MEMORY MAP

AND STACK FOR THE

4.0

MEMORY ORGANIZATION

4.1

Program Memory Organization

PIC16C621/PIC16C621A

The PIC16C62X has a 13-bit program counter capable

of addressing an 8K x 14 program memory space. Only

PC<12:0>

CALL, RETURN

RETFIE, RETLW

13

the ﬁrst 512

x 14 (0000h - 01FFh) for the

PIC16C620(A) and PIC16CR620, 1K x 14 (0000h -

03FFh) for the PIC16C621(A) and 2K x 14 (0000h -

07FFh) for the PIC16C622(A) are physically imple-

mented. Accessing a location above these boundaries

will cause a wrap-around within the ﬁrst 512 x 14 space

(PIC16C(R)620(A)) or 1K x 14 space (PIC16C621(A))

or 2K x 14 space (PIC16C622(A)). The reset vector is

at 0000h and the interrupt vector is at 0004h

(Figure 4-1, Figure 4-2, Figure 4-3).

Stack Level 1

Stack Level 2

Stack Level 8

Reset Vector

000h

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK FOR THE

Interrupt Vector

0004

0005

PIC16C620/PIC16C620A/

PIC16CR620A

On-chip Program

Memory

PC<12:0>

CALL, RETURN

RETFIE, RETLW

13

03FFh

0400h

Stack Level 1

Stack Level 2

1FFFh

FIGURE 4-3: PROGRAM MEMORY MAP

AND STACK FOR THE

Stack Level 8

PIC16C622/PIC16C622A

Reset Vector

000h

PC<12:0>

CALL, RETURN

RETFIE, RETLW

13

Stack Level 1

Stack Level 2

Interrupt Vector

0004

0005

On-chip Program

Memory

Stack Level 8

Reset Vector

000h

01FFh

0200h

Interrupt Vector

0004

0005

1FFFh

On-chip Program

Memory

07FFh

0800h

1FFFh

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 13

PIC16C62X

4.2.1

GENERAL PURPOSE REGISTER FILE

4.2

Data Memory Organization

The register ﬁle is organized as 80 x 8 in the

The data memory (Figure 4-4, Figure 4-5, Figure 4-6 and

Figure 4-7) is partitioned into two Banks which contain the

general purpose registers and the special function regis-

ters. Bank 0 is selected when the RP0 bit is cleared. Bank

1 is selected when the RP0 bit (STATUS <5>) is set. The

Special Function Registers are located in the ﬁrst 32 loca-

tions of each Bank. Register locations 20-7Fh (Bank0) on

the PIC16C620A/CR620A/621A and 20-7Fh (Bank0) and

A0-BFh (Bank1) on the PIC16C622 and PIC16C622A are

general purpose registers implemented as static RAM.

Some special purpose registers are mapped in Bank 1.

PIC16C620/621, 96 in the

x

8

PIC16C620A/621A/CR620A and 128 x 8 in the

PIC16C622(A). Each is accessed either directly or indi-

rectly through the File Select Register FSR

(Section 4.4).

Addresses F0h-FFh of bank1 are implemented as common

ram and mapped back to addresses 70h-7Fh in bank0 on

the PIC16C620A/CR620A/621A/622A.

DS30235G-page 14

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

FIGURE 4-4: DATA MEMORY MAP FOR

THE PIC16C620/621

FIGURE 4-5: DATA MEMORY MAP FOR

THE PIC16C622

File

Address

File

Address

File

Address

File

Address

(1)

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

INDF

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

INDF

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

TMR0

PCL

OPTION

PCL

TMR0

PCL

OPTION

PCL

STATUS

FSR

STATUS

FSR

STATUS

FSR

STATUS

FSR

PORTA

PORTB

TRISA

TRISB

PORTA

PORTB

TRISA

TRISB

PCLATH

INTCON

PIR1

PCLATH

INTCON

PIE1

PCLATH

INTCON

PIR1

PCLATH

INTCON

PIE1

PCON

CMCON

VRCON

CMCON

VRCON

A0h

General

Purpose

Register

General

Purpose

Register

General

Purpose

Register

6Fh

70h

BFh

C0h

FFh

7Fh

Bank 0

Bank 1

Bank 0

Bank 1

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 15

PIC16C62X

FIGURE 4-6: DATA MEMORY MAP FOR THE

PIC16C620A/

FIGURE 4-7: DATA MEMORY MAP FOR

THE PIC16C622A

CR620A/621A

File

Address

File

Address

File

Address

(1)

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

INDF

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

(1)

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

INDF

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

TMR0

PCL

OPTION

PCL

TMR0

PCL

OPTION

PCL

STATUS

FSR

STATUS

FSR

STATUS

FSR

STATUS

FSR

PORTA

PORTB

TRISA

TRISB

PORTA

PORTB

TRISA

TRISB

PCLATH

INTCON

PIR1

PCLATH

INTCON

PIE1

PCLATH

INTCON

PIR1

PCLATH

INTCON

PIE1

PCON

CMCON

VRCON

CMCON

VRCON

A0h

General

Purpose

Register

General

Purpose

Register

A0h

General

Purpose

Register

BFh

C0h

6Fh

70h

F0h

FFh

6Fh

70h

Accesses

70h-7Fh

F0h

FFh

Accesses

70h-7Fh

7Fh

Bank 0

Bank 1

7Fh

Bank 0

Bank 1

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

DS30235G-page 16

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

4.2.2

SPECIAL FUNCTION REGISTERS

The special registers can be classiﬁed into two sets

(core and peripheral). The special function registers

associated with the “core” functions are described in

this section. Those related to the operation of the

peripheral features are described in the section of that

peripheral feature.

The special function registers are registers used by the

CPU and Peripheral functions for controlling the

desired operation of the device (Table 4-1). These

registers are static RAM.

TABLE 4-1:

SPECIAL REGISTERS FOR THE PIC16C62X

Value on all

Value on

other

Address Name

Bank 0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR Reset

resets⁽¹⁾

Addressing this location uses contents of FSR to address data memory (not a physical

register)

00h

INDF

xxxx xxxx

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

TMR0

Timer0 Module’s Register

xxxx xxxx

0000 0000

0001 1xxx

uuuu uuuu

0000 0000

000q quuu

PCL

Program Counter's (PC) Least Signiﬁcant Byte

IRP⁽²⁾

RP1⁽²⁾

STATUS

FSR

RP0

TO

PD

Z

DC

C

Indirect data memory address pointer

xxxx xxxx

---x 0000

xxxx xxxx

—

uuuu uuuu

---u 0000

uuuu uuuu

—

PORTA

—

RA4

RB4

RA3

RB3

RA2

RB2

RA1

RB1

RA0

RB0

PORTB

RB7

RB6

RB5

Unimplemented

PCLATH

INTCON

PIR1

—

GIE

—

T0IE

—

Write buffer for upper 5 bits of program counter

---0 0000

0000 000x

-0-- ----

—

---0 0000

0000 000u

-0-- ----

—

PEIE

CMIF

INTE

—

RBIE

—

T0IF

—

INTF

—

RBIF

—

0Dh-1Eh Unimplemented

1Fh

CMCON

C2OUT

C1OUT

—

CIS

CM2

CM1

CM0

00-- 0000

Bank 1

Addressing this location uses contents of FSR to address data memory (not a physical

register)

xxxx xxxx

80h

INDF

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

OPTION

PCL

RBPU

Program Counter's (PC) Least Signiﬁcant Byte

RP0 TO

Indirect data memory address pointer

TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

0000 0000

0001 1xxx

1111 1111

0000 0000

000q quuu

IRP⁽²⁾

RP1⁽²⁾

STATUS

PD

Z

DC

C

FSR

xxxx xxxx

uuuu uuuu

TRISA

—

---1 1111

TRISB

1111 1111

Unimplemented

PCLATH

INTCON

PIE1

—

GIE

—

T0IE

—

Write buffer for upper 5 bits of program counter

---0 0000

0000 000x

-0-- ----

—

---0 0000

0000 000u

-0-- ----

—

PEIE

CMIE

INTE

—

RBIE

—

T0IF

—

INTF

—

RBIF

—

Unimplemented

PCON

—

POR

BOR

---- --0x

—

---- --uq

—

8Fh-9Eh Unimplemented

9Fh VRCON

VREN

VROE

VRR

—

VR3

VR2

VR1

VR0

000- 0000

Legend: — = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,

shaded = unimplemented

Note 1: Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during

normal operation.

Note 2: IRP & RPI bits are reserved, always maintain these bits clear.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 17

PIC16C62X

4.2.2.1

STATUS REGISTER

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register because these instructions do not

affect any status bit. For other instructions, not affecting

any status bits, see the “Instruction Set Summary”.

The STATUS register, shown in Figure 4-8, contains

the arithmetic status of the ALU, the RESET status and

the bank select bits for data memory.

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled.These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

Note 1: The IRP and RP1 bits (STATUS<7:6>)

are not used by the PIC16C62X and

should be programmed as ’0'. Use of

these bits as general purpose R/W bits

is NOT recommended, since this may

affect upward compatibility with future

products.

Note 2: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction. See the SUBLW and SUBWF

instructions for examples.

For example, CLRF STATUSwill clear the upper-three

bits and set the Z bit. This leaves the status register as

000uu1uu(where u= unchanged).

FIGURE 4-8: STATUS REGISTER (ADDRESS 03H OR 83H)

Reserved Reserved R/W-0

IRP RP1 RP0

bit7

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC

R/W-x

C

R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

bit0

- n = Value at POR reset

-x = Unknown at POR reset

bit 7:

IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)

The IRP bit is reserved on the PIC16C62X, always maintain this bit clear.

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)

11= Bank 3 (180h - 1FFh)

10= Bank 2 (100h - 17Fh)

01= Bank 1 (80h - FFh)

00= Bank 0 (00h - 7Fh)

Each bank is 128 bytes. The RP1 bit is reserved on the PIC16C62X, always maintain this bit clear.

bit 4:

bit 3:

bit 2:

bit 1:

bit 0:

TO: Time-out bit

1 = After power-up, CLRWDTinstruction, or SLEEPinstruction

0 = A WDT time-out occurred

PD: Power-down bit

1 = After power-up or by the CLRWDTinstruction

0 = By execution of the SLEEPinstruction

Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)(for borrow the polarity is reversed)

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the most signiﬁcant bit of the result occurred

0 = No carry-out from the most signiﬁcant bit of the result occurred

Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of

the source register.

DS30235G-page 18

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

4.2.2.2

OPTION REGISTER

Note: To achieve a 1:1 prescaler assignment for

TMR0, assign the prescaler to the WDT

(PSA = 1).

The OPTION register is a readable and writable

register which contains various control bits to conﬁgure

the TMR0/WDT prescaler, the external RB0/INT

interrupt, TMR0, and the weak pull-ups on PORTB.

FIGURE 4-9: OPTION REGISTER (ADDRESS 81H)

R/W-1

RBPU

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

PS2

R/W-1

PS1

R/W-1

PS0

INTEDG

R = Readable bit

W = Writable bit

- n = Value at POR reset

bit7

bit0

bit 7:

RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual port latch values

bit 6:

bit 5:

bit 4:

bit 3:

INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin

0 = Interrupt on falling edge of RB0/INT pin

T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin

0 = Increment on low-to-high transition on RA4/T0CKI pin

PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0: PS2:PS0: Prescaler Rate Select bits

Bit Value

TMR0 Rate WDT Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 19

PIC16C62X

4.2.2.3

INTCON REGISTER

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

The INTCON register is a readable and writable

register which contains the various enable and ﬂag bits

for all interrupt sources except the comparator module.

See Section 4.2.2.4 and Section 4.2.2.5 for

description of the comparator enable and ﬂag bits.

a

FIGURE 4-10: INTCON REGISTER (ADDRESS 0BH OR 8BH)

R/W-0

GIE

R/W-0

PEIE

R/W-0

T0IE

R/W-0

INTE

R/W-0

RBIE

R/W-0

T0IF

R/W-0

INTF

R/W-x

RBIF

R

= Readable bit

W = Writable bit

bit7

bit0

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

-x = Unknown at POR reset

bit 7:

GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts

0 = Disables all interrupts

bit 6:

bit 5:

bit 4:

bit 3:

bit 2:

bit 1:

bit 0:

PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts

0 = Disables all peripheral interrupts

T0IE: TMR0 Overﬂow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt

0 = Disables the RB0/INT external interrupt

RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

T0IF: TMR0 Overﬂow Interrupt Flag bit

1 = TMR0 register has overﬂowed (must be cleared in software)

0 = TMR0 register did not overﬂow

INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)

0 = The RB0/INT external interrupt did not occur

RBIF: RB Port Change Interrupt Flag bit

1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)

0 = None of the RB7:RB4 pins have changed state

DS30235G-page 20

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

4.2.2.4

PIE1 REGISTER

This register contains the individual enable bit for the

comparator interrupt.

FIGURE 4-11: PIE1 REGISTER (ADDRESS 8CH)

U-0

—

R/W-0

CMIE

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R

= Readable bit

W = Writable bit

bit7

bit0

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

Unimplemented: Read as '0'

bit 6:

CMIE: Comparator Interrupt Enable bit

1 = Enables the Comparator interrupt

0 = Disables the Comparator interrupt

bit 5-0: Unimplemented: Read as '0'

4.2.2.5

PIR1 REGISTER

This register contains the individual ﬂag bit for the

comparator interrupt.

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User

software should ensure the appropriate

interrupt ﬂag bits are clear prior to enabling

an interrupt.

FIGURE 4-12: PIR1 REGISTER (ADDRESS 0CH)

U-0

—

R/W-0

CMIF

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R

= Readable bit

W = Writable bit

bit7

bit0

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

Unimplemented: Read as'0'

bit 6:

CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed

0 = Comparator input has not changed

bit 5-0: Unimplemented: Read as '0'

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 21

PIC16C62X

4.2.2.6

PCON REGISTER

The PCON register contains ﬂag bits to differentiate

between a Power-on Reset, an external MCLR reset,

WDT reset or a Brown-out Reset.

Note: BOR is unknown on Power-on Reset. It

must then be set by the user and checked

on subsequent resets to see if BOR is

cleared, indicating

a

brown-out has

occurred. The BOR status bit is a "don't

care" and is not necessarily predictable if

the brown-out circuit is disabled (by

programming

BOREN

bit

in

the

Conﬁguration word).

FIGURE 4-13: PCON REGISTER (ADDRESS 8Eh)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

POR

R/W-0

BOR

R

= Readable bit

W = Writable bit

bit7

bit0

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7-2: Unimplemented: Read as '0'

bit 1:

POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0:

BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

DS30235G-page 22

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

4.3.2

STACK

4.3

PCL and PCLATH

The PIC16C62X family has an 8 level deep x 13-bit

wide hardware stack (Figure 4-2 and Figure 4-3). The

stack space is not part of either program or data space

and the stack pointer is not readable or writable. The

PC is PUSHed onto the stack when a CALLinstruction

is executed or an interrupt causes a branch. The stack

is POPed in the event of a RETURN, RETLWor a RETFIE

instruction execution. PCLATH is not affected by a

PUSH or POP operation.

The program counter (PC) is 13-bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<12:8>) is not directly

readable or writable and comes from PCLATH. On any

reset, the PC is cleared. Figure 4-14 shows the two

situations for the loading of the PC.The upper example in

the ﬁgure shows how the PC is loaded on a write to PCL

(PCLATH<4:0> → PCH).The lower example in the ﬁgure

shows how the PC is loaded during a CALL or GOTO

instruction (PCLATH<4:3> → PCH).

The stack operates as a circular buffer.This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the ﬁrst

push. The tenth push overwrites the second push (and

so on).

FIGURE 4-14: LOADING OF PC IN

DIFFERENT SITUATIONS

PCH

PCL

Note 1: There are no STATUS bits to indicate

stack overﬂow or stack underﬂow

conditions.

12

8

7

0

Instruction with

PCL as

Destination

PC

8

PCLATH<4:0>

PCLATH

5

Note 2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions, or the vectoring to an

interrupt address.

ALU result

PCH

12 11 10

PCL

8

7

0

GOTO, CALL

PC

PCLATH<4:3>

PCLATH

11

2

Opcode <10:0>

4.3.1

COMPUTED GOTO

A computed GOTO is accomplished by adding an

offset to the program counter (ADDWF PCL).When doing

a table read using a computed GOTO method, care

should be exercised if the table location crosses a PCL

memory boundary (each 256 byte block). Refer to the

application note “Implementing a Table Read" (AN556).

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 23

PIC16C62X

4.4

Indirect Addressing, INDF and FSR

Registers

EXAMPLE 4-1: INDIRECT ADDRESSING

movlw 0x20

movwf FSR

;initialize pointer

;to RAM

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing.

incf

INDF

FSR

;clear INDF register

;inc pointer

Indirect addressing is possible by using the INDF reg-

ister. Any instruction using the INDF register actually

accesses data pointed to by the ﬁle select register

(FSR). Reading INDF itself indirectly will produce 00h.

Writing to the INDF register indirectly results in a

no-operation (although status bits may be affected). An

effective 9-bit address is obtained by concatenating the

8-bit FSR register and the IRP bit (STATUS<7>), as

shown in Figure 4-15. However, IRP is not used in the

PIC16C62X.

btfss FSR,4 ;all done?

goto

;yes continue

CONTINUE:

A simple program to clear RAM location 20h-2Fh using

indirect addressing is shown in Example 4-1.

FIGURE 4-15: DIRECT/INDIRECT ADDRESSING PIC16C62X

Direct Addressing

Indirect Addressing

(1)

from opcode

7

RP1 RP0

6

0

IRP

FSR register

bank select

180h

location select

bank select

location select

00

01

10

11

00h

not used

Data

Memory

7Fh

1FFh

Bank 0

Bank 1 Bank 2

Bank 3

For memory map detail see (Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7).

Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.

DS30235G-page 24

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

Note: On reset, the TRISA register is set to all

inputs. The digital inputs are disabled and

the comparator inputs are forced to ground

to reduce excess current consumption.

5.0

I/O PORTS

The PIC16C62X have two ports, PORTA and PORTB.

Some pins for these I/O ports are multiplexed with an

alternate function for the peripheral features on the

device. In general, when a peripheral is enabled, that

pin may not be used as a general purpose I/O pin.

TRISA controls the direction of the RA pins, even when

they are being used as comparator inputs. The user

must make sure to keep the pins conﬁgured as inputs

when using them as comparator inputs.

5.1

PORTA and TRISA Registers

The RA2 pin will also function as the output for the

voltage reference.When in this mode, the VREF pin is a

very high impedance output. The user must conﬁgure

TRISA<2> bit as an input and use high impedance

loads.

PORTA is a 5-bit wide latch. RA4 is a SchmittTrigger input

and an open drain output.Port RA4 is multiplexed with the

T0CKI clock input. All other RA port pins have Schmitt

Trigger input levels and full CMOS output drivers. All pins

have data direction bits (TRIS registers) which can conﬁg-

ure these pins as input or output.

In one of the comparator modes deﬁned by the

CMCON register, pins RA3 and RA4 become outputs

of the comparators. The TRISA<4:3> bits must be

cleared to enable outputs to use this function.

A '1' in the TRISA register puts the corresponding output

driver in a hi- impedance mode. A '0' in the TRISA register

puts the contents of the output latch on the selected pin(s).

Reading the PORTA register reads the status of the pins

whereas writing to it will write to the port latch. All write

operations are read-modify-write operations. So a write

to a port implies that the port pins are ﬁrst read, then this

value is modiﬁed and written to the port data latch.

EXAMPLE 5-1: INITIALIZING PORTA

CLRF PORTA

;Initialize PORTA by setting

;output data latches

;Turn comparators off and

;enable pins for I/O

;functions

MOVLW 0X07

MOVWF CMCON

The PORTA pins are multiplexed with comparator and

voltage reference functions. The operation of these

pins are selected by control bits in the CMCON

(comparator control register) register and the VRCON

(voltage reference control register) register. When

selected as a comparator input, these pins will read

as '0's.

BSF

STATUS, RP0 ;Select Bank1

MOVLW 0x1F

;Value used to initialize

;data direction

MOVWF TRISA

;Set RA<4:0> as inputs

;TRISA<7:5> are always

;read as '0'.

FIGURE 5-2: BLOCK DIAGRAM OF RA2 PIN

Data

FIGURE 5-1: BLOCK DIAGRAM OF

RA1:RA0 PINS

bus

D

Q

Data

VDD

P

WR

PortA

bus

D

Q

CK

VDD

P

WR

PortA

Data Latch

CK

D

Q

Data Latch

RA2 Pin

N

WR

TRISA

D

Q

CK

I/O Pin

N

WR

TRISA

VSS

TRIS Latch

CK

Q

Analog

Input Mode

VSS

TRIS Latch

Analog

Schmitt Trigger

Input Buffer

Input Mode

RD TRISA

Schmitt Trigger

Input Buffer

RD TRISA

Q

D

Q

D

EN

RD PORTA

To Comparator

VROE

To Comparator

VREF

Note: I/O pins have protection diodes to VDD and VSS.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 25

PIC16C62X

FIGURE 5-3: BLOCK DIAGRAM OF RA3 PIN

Data

Comparator Mode = 110

Comparator Output

bus

D

Q

VDD

P

WR

PortA

CK

Data Latch

D

Q

RA3 Pin

N

WR

TRISA

CK

Q

VSS

TRIS Latch

Analog

Input Mode

Schmitt Trigger

Input Buffer

RD TRISA

Q

D

EN

RD PORTA

To Comparator

Note: I/O pins have protection diodes to VDD and VSS

FIGURE 5-4: BLOCK DIAGRAM OF RA4 PIN

Data

Comparator Mode = 110

bus

D

Q

Comparator Output

WR

PortA

CK

Data Latch

D

Q

RA4 Pin

N

WR

TRISA

CK

Q

VSS

TRIS Latch

Schmitt Trigger

Input Buffer

RD TRISA

Q

D

EN

RD PORTA

TMR0 Clock Input

Note: RA4 has protection diodes to VSS only

DS30235G-page 26

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

TABLE 5-1:

Name

PORTA FUNCTIONS

Buffer

Bit #

Type

Function

RA0/AN0

bit0

bit1

bit2

bit3

bit4

ST

Input/output or comparator input

RA1/AN1

RA2/AN2/VREF

RA3/AN3

Input/output or comparator input or VREF output

Input/output or comparator input/output

RA4/T0CKI

Input/output or external clock input for TMR0 or comparator output.

Output is open drain type.

Legend: ST = Schmitt Trigger input

TABLE 5-2:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on

All Other

Resets

Value on

POR

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

05h

85h

1Fh

9Fh

PORTA

TRISA

—

RA4

RA3

RA2

RA1

RA0

---x 0000 ---u 0000

TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111

CMCON C2OUT C1OUT

VRCON VREN

—

CIS

CM2

VR2

CM1

VR1

CM0

VR0

00-- 0000 00-- 0000

000- 0000 000- 0000

VROE VRR

VR3

Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown

Note: Note: Shaded bits are not used by PORTA.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 27

PIC16C62X

This interrupt can wake the device from SLEEP. The

user, in the interrupt service routine, can clear the

interrupt in the following manner:

5.2

PORTB and TRISB Registers

PORTB is an 8-bit wide bi-directional port. The

corresponding data direction register is TRISB. A '1' in

theTRISB register puts the corresponding output driver

in a high impedance mode. A '0' in the TRISB register

puts the contents of the output latch on the selected

pin(s).

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear ﬂag bit RBIF.

A mismatch condition will continue to set ﬂag bit RBIF.

Reading PORTB will end the mismatch condition, and

allow ﬂag bit RBIF to be cleared.

Reading PORTB register reads the status of the pins,

whereas writing to it will write to the port latch. All write

operations are read-modify-write operations. So a write

to a port implies that the port pins are ﬁrst read, then

this value is modiﬁed and written to the port data latch.

This interrupt on mismatch feature, together with

software conﬁgurable pull-ups on these four pins allow

easy interface to a key pad and make it possible for

wake-up on key-depression. (See AN552 in the

Microchip Embedded Control Handbook.)

Each of the PORTB pins has a weak internal pull-up

(≈200 µA typical). A single control bit can turn on all the

pull-ups. This is done by clearing the RBPU

(OPTION<7>) bit. The weak pull-up is automatically

turned off when the port pin is conﬁgured as an output.

The pull-ups are disabled on Power-on Reset.

Note: If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RBIF inter-

rupt ﬂag may not get set.

Four of PORTB’s pins, RB7:RB4, have an interrupt on

change feature. Only pins conﬁgured as inputs can

cause this interrupt to occur (i.e., any RB7:RB4 pin

conﬁgured as an output is excluded from the interrupt

on change comparison). The input pins (of RB7:RB4)

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of RB7:RB4

are OR’ed together to generate the RBIF interrupt (ﬂag

latched in INTCON<0>).

The interrupt on change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt on change

feature. Polling of PORTB is not recommended while

using the interrupt on change feature.

FIGURE 5-6: BLOCK DIAGRAM OF

RB3:RB0 PINS

VDD

RBPU⁽²⁾

FIGURE 5-5: BLOCK DIAGRAM OF

weak

P

pull-up

RB7:RB4 PINS

Data Latch

Data bus

VDD

D

Q

RBPU⁽²⁾

weak

I/O

pin⁽¹⁾

P

WR PortB

pull-up

Q

CK

Data Latch

Data bus

D

Q

D

I/O

pin⁽¹⁾

TTL

Input

Buffer

WR PortB

CK Q

WR TRISB

CK Q

TRIS Latch

D

Q

WR TRISB

TTL

Input

Buffer

Q

CK

RD TRISB

RD PortB

ST

Buffer

Q

D

EN

RD TRISB

RD PortB

Latch

D

Q

RB0/INT

EN

ST

Buffer

RD Port

Set RBIF

From other

RB7:RB4 pins

D

Note 1: I/O pins have diode protection to VDD and VSS.

Note 2: TRISB = 1 enables weak pull-up if RBPU = '0'

(OPTION<7>).

EN

RD Port

RB7:RB6 in serial programming mode

Note 1: I/O pins have diode protection to VDD and VSS.

Note 2: TRISB = 1 enables weak pull-up if RBPU = '0'

(OPTION<7>).

DS30235G-page 28

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

TABLE 5-3:

PORTB FUNCTIONS

Name

Bit #

Buffer Type

Function

(1)

RB0/INT

bit0

Input/output or external interrupt input. Internal software programmable

weak pull-up.

TTL/ST

RB1

RB2

RB3

RB4

bit1

bit2

bit3

bit4

TTL

Input/output pin. Internal software programmable weak pull-up.

Input/output pin (with interrupt on change). Internal software

programmable weak pull-up.

RB5

RB6

RB7

bit5

bit6

bit7

TTL

Input/output pin (with interrupt on change). Internal software

programmable weak pull-up.

(2)

Input/output pin (with interrupt on change). Internal software

programmable weak pull-up. Serial programming clock pin.

TTL/ST

(2)

Input/output pin (with interrupt on change). Internal software

programmable weak pull-up. Serial programming data pin.

TTL/ST

Legend: ST = Schmitt Trigger, TTL = TTL input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.

TABLE 5-4:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Value on

All Other

Resets

Value on

POR

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

06h

86h

81h

PORTB

TRISB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx xxxx uuuu uuuu

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

OPTION

RBPU INTEDG T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111 1111 1111

Note: Shaded bits are not used by PORTB.

u = unchanged

x = unknown

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 29

PIC16C62X

5.3

I/O Programming Considerations

EXAMPLE 5-2: READ-MODIFY-WRITE

INSTRUCTIONS ON AN

5.3.1

BI-DIRECTIONAL I/O PORTS

I/O PORT

;Initial PORT settings: PORTB<7:4> Inputs

;

Any instruction which writes, operates internally as a

read followed by a write operation. The BCF and BSF

instructions, for example, read the register into the

CPU, execute the bit operation and write the result back

to the register. Caution must be used when these

instructions are applied to a port with both inputs and

outputs deﬁned. For example, a BSFoperation on bit5

of PORTB will cause all eight bits of PORTB to be read

into the CPU. Then the BSF operation takes place on

bit5 and PORTB is written to the output latches. If

another bit of PORTB is used as a bidirectional I/O pin

(e.g., bit0) and it is deﬁned as an input at this time, the

input signal present on the pin itself would be read into

the CPU and re-written to the data latch of this

particular pin, overwriting the previous content. As long

as the pin stays in the input mode, no problem occurs.

However, if bit0 is switched into output mode later on,

the content of the data latch may now be unknown.

;

PORTB<3:0> Outputs

;PORTB<7:6> have external pull-up and are not

;connected to other circuitry

;

PORT latch PORT pins

---------- ----------

BCF PORTB, 7

BCF PORTB, 6

BSF STATUS,RP0

BCF TRISB, 7

BCF TRISB, 6

;01pp pppp 11pp pppp

;10pp pppp 11pp pppp

;

;10pp pppp 11pp pppp

;10pp pppp 10pp pppp

;

;Note that the user may have expected the pin

;values to be 00pp pppp. The 2nd BCF caused

;RB7 to be latched as the pin value (High).

5.3.2

SUCCESSIVE OPERATIONS ON I/O PORTS

Reading the port register, reads the values of the port

pins. Writing to the port register writes the value to the

port latch. When using read modify write instructions

(ex. BCF, BSF, etc.) on a port, the value of the port pins

is read, the desired operation is done to this value, and

this value is then written to the port latch.

The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be

valid at the beginning of the instruction cycle

(Figure 5-7). Therefore, care must be exercised if a

write followed by a read operation is carried out on the

same I/O port. The sequence of instructions should be

such to allow the pin voltage to stabilize (load

dependent) before the next instruction which causes

that ﬁle to be read into the CPU is executed. Otherwise,

the previous state of that pin may be read into the CPU

rather than the new state. When in doubt, it is better to

separate these instructions with a NOP or another

instruction not accessing this I/O port.

Example 5-2 shows the effect of two sequential

read-modify-write instructions (ex., BCF, BSF, etc.) on

an I/O port.

A pin actively outputting a Low or High should not be

driven from external devices at the same time in order

to change the level on this pin (“wired-or”, “wired-and”).

The resulting high output currents may damage

the chip.

FIGURE 5-7: SUCCESSIVE I/O OPERATION

Note:

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

This example shows write to PORTB

followed by a read from PORTB.

PC + 1

MOVWF PORTB MOVF PORTB, W

PC + 2

NOP

PC + 3

NOP

PC

Instruction

fetched

PC

Note that:

Write to

PORTB

Read PORTB

data setup time = (0.25 TCY - TPD)

where TCY = instruction cycle and

TPD = propagation delay of Q1 cycle

to output valid.

RB7:RB0

RB <7:0>

Port pin

sampled here

Therefore, at higher clock frequencies,

a write followed by a read may be

problematic.

TPD

Execute

MOVWF

PORTB

Execute

MOVF

PORTB, W

Execute

NOP

DS30235G-page 30

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

bit (OPTION<4>). Clearing the T0SE bit selects the

rising edge. Restrictions on the external clock input are

discussed in detail in Section 6.2.

6.0

TIMER0 MODULE

The Timer0 module timer/counter has the following

features:

The prescaler is shared between the Timer0 module

and the Watchdog Timer. The prescaler assignment is

controlled in software by the control bit PSA

(OPTION<3>). Clearing the PSA bit will assign the

prescaler to Timer0. The prescaler is not readable or

writable. When the prescaler is assigned to the Timer0

module, prescale value of 1:2, 1:4, ..., 1:256 are

selectable. Section 6.3 details the operation of the

prescaler.

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overﬂow from FFh to 00h

• Edge select for external clock

Figure 6-1 is a simpliﬁed block diagram of the Timer0

module.

6.1

TIMER0 Interrupt

Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In timer mode, the TMR0 will increment

every instruction cycle (without prescaler). If Timer0 is

written, the increment is inhibited for the following two

cycles (Figure 6-2 and Figure 6-3). The user can work

around this by writing an adjusted value to TMR0.

Timer0 interrupt is generated when the TMR0 register

timer/counter overﬂows from FFh to 00h. This overﬂow

sets the T0IF bit. The interrupt can be masked by

clearing the T0IE bit (INTCON<5>). The T0IF bit

(INTCON<2>) must be cleared in software by the

Timer0 module interrupt service routine before

re-enabling this interrupt. The Timer0 interrupt cannot

wake the processor from SLEEP since the timer is shut

off during SLEEP. See Figure 6-4 for Timer0 interrupt

timing.

Counter mode is selected by setting the T0CS bit. In

this mode Timer0 will increment either on every rising

or falling edge of pin RA4/T0CKI. The incrementing

edge is determined by the source edge (T0SE) control

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

Data bus

RA4/T0CKI

FOSC/4

0

1

PSout

8

1

0

Sync with

Internal

clocks

TMR0

Programmable

Prescaler

PSout

(2 TCY delay)

T0SE

Set Flag bit T0IF

on Overﬂow

PS2:PS0

PSA

T0CS

Note 1:

Bits T0SE, T0CS, PS2, PS1, PS0 and PSA are located in the OPTION register.

2: The prescaler is shared with Watchdog Timer (Figure 6-6)

FIGURE 6-2: TIMER0 (TMR0) TIMING: INTERNAL CLOCK/NO PRESCALER

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

(Program

Counter)

PC-1

PC

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

Instruction

Fetch

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

MOVWF TMR0

NT0

T0

T0+1

T0+2

NT0+1

NT0+2

TMR0

Instruction

Executed

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 2

Write TMR0

executed

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 31

PIC16C62X

FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

(Program

Counter)

PC-1

PC

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

MOVWF TMR0

Instruction

Fetch

T0

T0+1

NT0+1

NT0

TMR0

Instruction

Execute

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 1

Write TMR0

executed

FIGURE 6-4: TIMER0 INTERRUPT TIMING

Q1 Q2 Q3

Q4

Q1 Q2 Q3

Q4

Q1 Q2 Q3

Q4

Q1 Q2 Q3

Q4

Q1 Q2 Q3

Q4

OSC1

CLKOUT(3)

TMR0 timer

FEh

1

FFh

1

00h

01h

02h

T0IF bit

(INTCON<2>)

GIE bit

(INTCON<7>)

Interrupt Latency Time

INSTRUCTION FLOW

PC

PC +1

0004h

0005h

Instruction

fetched

Inst (PC)

Inst (PC+1)

Inst (0004h)

Inst (0005h)

Instruction

executed

Inst (PC-1)

Dummy cycle

Inst (0004h)

Inst (PC)

Note 1: T0IF interrupt ﬂag is sampled here (every Q1).

2: Interrupt latency = 3TCY, where TCY = instruction cycle time.

3: CLKOUT is available only in RC oscillator mode.

DS30235G-page 32

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

When a prescaler is used, the external clock input is

divided by the asynchronous ripple-counter type

prescaler so that the prescaler output is symmetrical.

For the external clock to meet the sampling

requirement, the ripple-counter must be taken into

account. Therefore, it is necessary for T0CKI to have a

period of at least 4TOSC (and a small RC delay of

40 ns) divided by the prescaler value. The only

requirement on T0CKI high and low time is that they do

not violate the minimum pulse width requirement of

10 ns. Refer to parameters 40, 41 and 42 in the

electrical speciﬁcation of the desired device.

6.2

Using Timer0 with External Clock

When an external clock input is used for Timer0, it must

meet certain requirements. The external clock

requirement is due to internal phase clock (TOSC)

synchronization. Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

6.2.1

EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is

accomplished by sampling the prescaler output on the

Q2 and Q4 cycles of the internal phase clocks

(Figure 6-5). Therefore, it is necessary for T0CKI to be

high for at least 2TOSC (and a small RC delay of 20 ns)

and low for at least 2TOSC (and a small RC delay of

20 ns). Refer to the electrical speciﬁcation of the

desired device.

6.2.2

TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the TMR0 is

actually incremented. Figure 6-5 shows the delay from

the external clock edge to the timer incrementing.

FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Small pulse

misses sampling

External Clock Input or

(2)

Prescaler output

(1)

(3)

External Clock/Prescaler

Output after sampling

Increment Timer0 (Q4)

Timer0

T0

T0 + 1

T0 + 2

Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).

Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max.

2: External clock if no prescaler selected, Prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 33

PIC16C62X

The PSA and PS2:PS0 bits (OPTION<3:0>) determine

the prescaler assignment and prescale ratio.

6.3

Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer, respectively (Figure 6-6). For simplicity, this

counter is being referred to as “prescaler” throughout

this data sheet. Note that there is only one prescaler

available which is mutually exclusive between the

Timer0 module and the Watchdog Timer. Thus, a

prescaler assignment for the Timer0 module means

that there is no prescaler for the Watchdog Timer, and

vice-versa.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,

BSF 1,x....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the

prescaler along with the Watchdog Timer. The

prescaler is not readable or writable.

FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

Data Bus

8

CLKOUT (=Fosc/4)

M

U

X

1

0

1

M

U

X

T0CKI

SYNC

2

Cycles

TMR0 reg

T0SE

T0CS

Set ﬂag bit T0IF

on Overﬂow

PSA

0

1

8-bit Prescaler

M

U

X

Watchdog

Timer

8

8-to-1MUX

PS0 - PS2

PSA

1

0

WDT Enable bit

M U X

PSA

WDT

Time-out

Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.

DS30235G-page 34

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

6.3.1

SWITCHING PRESCALER ASSIGNMENT

To change prescaler from the WDT to the TMR0

module use the sequence shown in Example 6-2. This

precaution must be taken even if the WDT is disabled.

The prescaler assignment is fully under software

control (i.e., it can be changed “on the ﬂy” during

program execution). To avoid an unintended device

EXAMPLE 6-2: CHANGING PRESCALER

RESET,

the

following

instruction

sequence

(WDT→TIMER0)

(Example 6-1) must be executed when changing the

prescaler assignment from Timer0 to WDT.

CLRWDT

;Clear WDT and

;prescaler

EXAMPLE 6-1: CHANGING PRESCALER

BSF

STATUS, RP0

(TIMER0→WDT)

STATUS, RP0 ;Skip if already in

MOVLW

b'xxxx0xxx' ;Select TMR0, new

;prescale value and

;clock source

1.BCF

; Bank 0

2.CLRWDT

3.CLRF

4.BSF

;Clear WDT

;Clear TMR0 & Prescaler

STATUS, RP0 ;Bank 1

MOVWF

BCF

OPTION_REG

STATUS, RP0

TMR0

5.MOVLW '00101111’b; ;These 3 lines (5, 6, 7)

6.MOVWF OPTION

; are required only if

; desired PS<2:0> are

; 000 or 001

7.CLRWDT

8.MOVLW '00101xxx’b ;Set Postscaler to

9.MOVWF OPTION ; desired WDT rate

10.BCF STATUS, RP0 ;Return to Bank 0

TABLE 6-1:

REGISTERS ASSOCIATED WITH TIMER0

Value on

POR

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All Other

Resets

01h

TMR0

Timer0 module register

GIE PEIE T0IE

xxxx xxxx uuuu uuuu

0000 000x 0000 000u

1111 1111 1111 1111

0Bh/8Bh

81h

INTCON

INTE

T0SE

RBIE

PSA

T0IF

PS2

INTF

PS1

RBIF

PS0

OPTION RBPU INTEDG T0CS

TRISA

85h

—

TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111

Legend: — = Unimplemented locations, read as ‘0’.

Note: Shaded bits are not used by TMR0 module.

u = unchanged

x = unknown

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 35

PIC16C62X

NOTES:

DS30235G-page 36

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

The CMCON register, shown in Figure 7-1, controls the

comparator input and output multiplexers. A block

diagram of the comparator is shown in Figure 7-2.

7.0

COMPARATOR MODULE

The comparator module contains two analog

comparators. The inputs to the comparators are

multiplexed with the RA0 through RA3 pins. The

on-chip Voltage Reference (Section 8.0) can also be an

input to the comparators.

FIGURE 7-1:

CMCON REGISTER (ADDRESS 1Fh)

R-0

U-0

R/W-0

CIS

R/W-0

CM2

R/W-0

CM1

R/W-0

CM0

C2OUT C1OUT

bit7

R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

bit0

- n =Value at POR reset

bit 7:

bit 6:

C2OUT: Comparator 2 output

1 = C2 VIN+ > C2 VIN–

0 = C2 VIN+ < C2 VIN–

C1OUT: Comparator 1 output

1 = C1 VIN+ > C1 VIN–

0 = C1 VIN+ < C1 VIN–

bit 5-4: Unimplemented: Read as '0'

bit 3:

CIS: Comparator Input Switch

When CM<2:0>: = 001:

1 = C1 VIN– connects to RA3

0 = C1 VIN– connects to RA0

When CM<2:0> = 010:

1 = C1 VIN– connects to RA3

C2 VIN– connects to RA2

0 = C1 VIN– connects to RA0

C2 VIN– connects to RA1

bit 2-0: CM<2:0>: Comparator mode

Figure 7-2.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 37

PIC16C62X

changed, the comparator output level may not be valid

for the speciﬁed mode change delay shown in

Table 12-2.

7.1

Comparator Conﬁguration

There are eight modes of operation for the

comparators.The CMCON register is used to select the

mode. Figure 7-2 shows the eight possible modes. The

TRISA register controls the data direction of the com-

parator pins for each mode. If the comparator mode is

Note: Comparator interrupts should be disabled

during a comparator mode change other-

wise a false interrupt may occur.

FIGURE 7-2: COMPARATOR I/O OPERATING MODES

VIN-

A

D

-

Off

RA0/AN0

RA3/AN3

RA0/AN0

RA3/AN3

C1

C2

C1

C2

VIN+

(Read as '0')

+

VIN-

A

D

-

Off

RA1/AN1

RA2/AN2

RA1/AN1

RA2/AN2

VIN+

(Read as '0')

+

CM<2:0> = 000

C1OUT

CM<2:0> = 111

Comparators Reset

Comparators Off

VIN-

A

-

RA0/AN0

CIS=0

CIS=1

VIN-

RA0/AN0

RA3/AN3

-

C1

C2

VIN+

A

C1OUT

RA3/AN3

+

C1

VIN+

+

VIN-

A

-

RA1/AN1

CIS=0

CIS=1

VIN-

RA1/AN1

RA2/AN2

-

C2OUT

VIN+

A

C2OUT

RA2/AN2

+

C2

VIN+

+

CM<2:0> = 100

From VREF Module

CM<2:0> = 010

Two Independent Comparators

Four Inputs Multiplexed to

Two Comparators

VIN-

A

-

RA0/AN0

C1OUT

C1

C2

C1

VIN+

D

+

RA3/AN3

VIN-

A

-

RA1/AN1

C2OUT

C2

VIN+

A

+

RA2/AN2

RA4 Open Drain

CM<2:0> = 011

CM<2:0> = 110

Two Common Reference Comparators

Two Common Reference Comparators with Outputs

VIN-

A

CIS=0

VIN-

CIS=1

VIN+

D

-

RA0/AN0

RA3/AN3

Off

RA0/AN0

RA3/AN3

-

C1

C2

VIN+

(Read as '0')

C1OUT

+

C1

C2

+

VIN-

A

-

VIN-

RA1/AN1

RA2/AN2

A

-

C2OUT

RA1/AN1

RA2/AN2

VIN+

C2OUT

+

VIN+

+

CM<2:0> = 101

CM<2:0> = 001

Three Inputs Multiplexed to

Two Comparators

One Independent Comparator

A = Analog Input, Port Reads Zeros Always

D = Digital Input

CIS = CMCON<3>, Comparator Input Switch

DS30235G-page 38

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

The code example in Example 7-1 depicts the steps

required to conﬁgure the comparator module. RA3 and

RA4 are conﬁgured as digital output. RA0 and RA1 are

conﬁgured as the V- inputs and RA2 as the V+ input to

both comparators.

7.3

Comparator Reference

An external or internal reference signal may be used

depending on the comparator operating mode. The

analog signal that is present at VIN– is compared to the

signal at VIN+, and the digital output of the comparator

is adjusted accordingly (Figure 7-3).

EXAMPLE 7-1: INITIALIZING

COMPARATOR MODULE

FIGURE 7-3: SINGLE COMPARATOR

FLAG_REG EQU

0X20

CLRF

FLAG_REG

PORTA

;Init flag register

;Init PORTA

MOVF

CMCON, W

0xC0

;Load comparator bits

;Mask comparator bits

VIN+

+

–

ANDLW

IORWF

MOVLW

MOVWF

BSF

Output

FLAG_REG,F ;Store bits in flag register

0x03

CMCON

VIN–

;Init comparator mode

;CM<2:0> = 011

STATUS,RP0 ;Select Bank1

MOVLW

MOVWF

0x07

TRISA

;Initialize data direction

;Set RA<2:0> as inputs

;RA<4:3> as outputs

;TRISA<7:5> always read ‘0’

STATUS,RP0 ;Select Bank 0

VIN–

VIN+

BCF

CALL

MOVF

BCF

BSF

BCF

BSF

DELAY 10

CMCON,F

PIR1,CMIF

;10µs delay

;Read CMCONtoendchangecondition

;Clear pending interrupts

STATUS,RP0 ;Select Bank 1

PIE1,CMIE

;Enable comparator interrupts

Output

STATUS,RP0 ;Select Bank 0

INTCON,PEIE ;Enable peripheral interrupts

INTCON,GIE ;Global interrupt enable

7.2

Comparator Operation

7.3.1

EXTERNAL REFERENCE SIGNAL

A single comparator is shown in Figure 7-3 along with

the relationship between the analog input levels and

the digital output. When the analog input at VIN+ is less

than the analog input VIN–, the output of the

comparator is a digital low level.When the analog input

at VIN+ is greater than the analog input VIN–, the output

of the comparator is a digital high level. The shaded

areas of the output of the comparator in Figure 7-3

represent the uncertainty due to input offsets and

response time.

When external voltage references are used, the

comparator module can be conﬁgured to have the com-

parators operate from the same or different reference

sources. However, threshold detector applications may

require the same reference. The reference signal must

be between VSS and VDD, and can be applied to either

pin of the comparator(s).

7.3.2

INTERNAL REFERENCE SIGNAL

The comparator module also allows the selection of an

internally generated voltage reference for the

comparators. Section 13, Instruction Sets, contains a

detailed description of the Voltage Reference Module

that provides this signal. The internal reference signal

is used when the comparators are in mode

CM<2:0>=010 (Figure 7-2). In this mode, the internal

voltage reference is applied to theVIN+ pin of both com-

parators.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 39

PIC16C62X

7.4

Comparator Response Time

7.5

Comparator Outputs

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comparator output is guaranteed to have a valid level.

If the internal reference is changed, the maximum

delay of the internal voltage reference must be

considered when using the comparator outputs.

Otherwise the maximum delay of the comparators

should be used (Table 12-2 ).

The comparator outputs are read through the CMCON

register. These bits are read only. The comparator

outputs may also be directly output to the RA3 and RA4

I/O pins. When the CM<2:0> = 110, multiplexors in the

output path of the RA3 and RA4 pins will switch and the

output of each pin will be the unsynchronized output of

the comparator. The uncertainty of each of the

comparators is related to the input offset voltage and

the response time given in the speciﬁcations.

Figure 7-4 shows the comparator output block

diagram.

The TRISA bits will still function as an output

enable/disable for the RA3 and RA4 pins while in this

mode.

Note 1: When reading the PORT register, all pins

conﬁgured as analog inputs will read as

a ‘0’. Pins conﬁgured as digital inputs will

convert an analog input according to the

Schmitt Trigger input speciﬁcation.

2: Analog levels on any pin that is deﬁned

as a digital input may cause the input

buffer to consume more current than is

speciﬁed.

FIGURE 7-4: COMPARATOR OUTPUT BLOCK DIAGRAM

Port Pins

MULTIPLEX

+

-

To RA3 or

RA4 Pin

Bus

Data

Q

D

RD CMCON

EN

Set

CMIF

Bit

Q

D

From

Other

Comparator

EN

CL

RD CMCON

NRESET

DS30235G-page 40

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

wake up the device from SLEEP mode when enabled.

While the comparator is powered-up, higher sleep

currents than shown in the power down current

speciﬁcation will occur. Each comparator that is

operational will consume additional current as shown in

the comparator speciﬁcations. To minimize power

consumption while in SLEEP mode, turn off the

comparators, CM<2:0> = 111, before entering sleep. If

the device wakes-up from sleep, the contents of the

CMCON register are not affected.

7.6

Comparator Interrupts

The comparator interrupt ﬂag is set whenever there is

a change in the output value of either comparator.

Software will need to maintain information about the

status of the output bits, as read from CMCON<7:6>, to

determine the actual change that has occurred. The

CMIF bit, PIR1<6>, is the comparator interrupt ﬂag.

The CMIF bit must be reset by clearing ‘0’. Since it is

also possible to write a '1' to this register, a simulated

interrupt may be initiated.

7.8

Effects of a RESET

The CMIE bit (PIE1<6>) and the PEIE bit

(INTCON<6>) must be set to enable the interrupt. In

addition, the GIE bit must also be set. If any of these

bits are clear, the interrupt is not enabled, though the

CMIF bit will still be set if an interrupt condition occurs.

A device reset forces the CMCON register to its reset

state. This forces the comparator module to be in the

comparator reset mode, CM2:CM0 = 000. This

ensures that all potential inputs are analog inputs.

Device current is minimized when analog inputs are

present at reset time. The comparators will be

powered-down during the reset interval.

Note: If a change in the CMCON register

(C1OUT or C2OUT) should occur when a

read operation is being executed (start of

the Q2 cycle), then the CMIF (PIR1<6>)

interrupt ﬂag may not get set.

7.9

Analog Input Connection

Considerations

The user, in the interrupt service routine, can clear the

interrupt in the following manner:

A simpliﬁed circuit for an analog input is shown in

Figure 7-5. Since the analog pins are connected to a

digital output, they have reverse biased diodes to VDD

and VSS. The analog input therefore, must be between

VSS and VDD. If the input voltage deviates from this

range by more than 0.6V in either direction, one of the

diodes is forward biased and a latch-up may occur. A

a) Any read or write of CMCON. This will end the

mismatch condition.

b) Clear ﬂag bit CMIF.

A mismatch condition will continue to set ﬂag bit CMIF.

Reading CMCON will end the mismatch condition, and

allow ﬂag bit CMIF to be cleared.

maximum

source

impedance

of

10 kΩ

is

recommended for the analog sources. Any external

component connected to an analog input pin, such as

a capacitor or a Zener diode, should have very little

leakage current.

7.7

Comparator Operation During SLEEP

When a comparator is active and the device is placed

in SLEEP mode, the comparator remains active and

the interrupt is functional if enabled. This interrupt will

FIGURE 7-5: ANALOG INPUT MODEL

VDD

VT = 0.6V

RIC

RS < 10K

AIN

ILEAKAGE

±500 nA

CPIN

5 pF

VA

VT = 0.6V

VSS

Legend

CPIN

VT

= Input Capacitance

= Threshold Voltage

ILEAKAGE

RIC

= Leakage Current At The Pin Due To Various Junctions

= Interconnect Resistance

RS

= Source Impedance

VA

= Analog Voltage

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 41

PIC16C62X

TABLE 7-1:

REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Value on

All Other

Resets

Value on

POR

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1Fh

9Fh

0Bh

0Ch

8Ch

85h

CMCON C2OUT C1OUT

—

VRR

T0IE

—

CIS

VR3

RBIE

—

CM2

VR2

T0IF

—

CM1

VR1

INTF

—

CM0

VR0

RBIF

—

00-- 0000 00-- 0000

000- 0000 000- 0000

0000 000x 0000 000u

-0-- ---- -0-- ----

VRCON

INTCON

PIR1

VREN

GIE

—

VROE

PEIE

CMIF

CMIE

—

INTE

—

PIE1

—

TRISA

—

TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111

Legend: x = unknown

u = unchanged

- = unimplemented, read as "0"

DS30235G-page 42

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

8.1

Conﬁguring the Voltage Reference

8.0

VOLTAGE REFERENCE

MODULE

The Voltage Reference can output 16 distinct voltage

levels for each range.

The Voltage Reference is a 16-tap resistor ladder

network that provides a selectable voltage reference.

The resistor ladder is segmented to provide two ranges

of VREF values and has a power-down function to

conserve power when the reference is not being used.

The VRCON register controls the operation of the

reference as shown in Figure 8-1.The block diagram is

given in Figure 8-2.

The equations used to calculate the output of the

Voltage Reference are as follows:

if VRR = 1: VREF = (VR<3:0>/24) x VDD

if VRR = 0: VREF = (VDD x 1/4) + (VR<3:0>/32) x VDD

The setting time of the Voltage Reference must be

considered when changing the VREF output

(Table 12-2). Example 8-1 shows an example of how to

conﬁgure the Voltage Reference for an output voltage

of 1.25V with VDD = 5.0V.

FIGURE 8-1:

VRCON REGISTER(ADDRESS 9Fh)

R/W-0

VREN

bit7

R/W-0

VRR

U-0

—

R/W-0

VR3

R/W-0

VR2

R/W-0

VR1

R/W-0

VR0

VROE

R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

bit0

- n =Value at POR reset

bit 7:

bit 6:

bit 5:

bit 4:

VREN: VREF Enable

1 = VREF circuit powered on

0 = VREF circuit powered down, no IDD drain

VROE: VREF Output Enable

1 = VREF is output on RA2 pin

0 = VREF is disconnected from RA2 pin

VRR: VREF Range selection

1 = Low Range

0 = High Range

Unimplemented: Read as '0'

bit 3-0: VR<3:0>: VREF value selection 0 ≤ VR [3:0] ≤ 15

when VRR = 1: VREF = (VR<3:0>/ 24) * VDD

when VRR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD

FIGURE 8-2: VOLTAGE REFERENCE BLOCK DIAGRAM

16 Stages

VREN

R

8R

VRR

VR3

VR0

VREF

(From VRCON<3:0>)

16-1 Analog Mux

Note: R is deﬁned in Table 12-3.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 43

PIC16C62X

EXAMPLE 8-1: VOLTAGE REFERENCE

CONFIGURATION

8.4

Effects of a Reset

A device reset disables the Voltage Reference by clear-

ing bit VREN (VRCON<7>). This reset also disconnects

the reference from the RA2 pin by clearing bit VROE

(VRCON<6>) and selects the high voltage range by

clearing bit VRR (VRCON<5>). The VREF value select

bits, VRCON<3:0>, are also cleared.

MOVLW

MOVWF

BSF

0x02

; 4 Inputs Muxed

; to 2 comps.

; go to Bank 1

; RA3-RA0 are

; outputs

CMCON

STATUS,RP0

0x07

MOVLW

MOVWF

MOVLW

MOVWF

TRISA

0xA6

; enable VREF

; low range

8.5

Connection Considerations

VRCON

; set VR<3:0>=6

; go to Bank 0

; 10µs delay

TheVoltage Reference Module operates independently

of the comparator module. The output of the reference

generator may be connected to the RA2 pin if the

TRISA<2> bit is set and the VROE bit, VRCON<6>, is

set. Enabling the Voltage Reference output onto the

RA2 pin with an input signal present will increase cur-

rent consumption. Connecting RA2 as a digital output

with VREF enabled will also increase current consump-

tion.

BCF

STATUS,RP0

DELAY10

CALL

8.2

Voltage Reference Accuracy/Error

The full range of VSS to VDD cannot be realized due to

the construction of the module. The transistors on the

top and bottom of the resistor ladder network

(Figure 8-2) keep VREF from approaching VSS or VDD.

The Voltage Reference is VDD derived and therefore,

the VREF output changes with ﬂuctuations in VDD. The

tested absolute accuracy of the Voltage Reference can

be found in Table 12-3.

The RA2 pin can be used as a simple D/A output with

limited drive capability. Due to the limited drive

capability, a buffer must be used in conjunction with the

Voltage Reference output for external connections to

VREF. Figure 8-3 shows an example buffering

technique.

8.3

Operation During Sleep

When the device wakes up from sleep through an

interrupt or a Watchdog Timer time-out, the contents of

the VRCON register are not affected. To minimize

current consumption in SLEEP mode, the Voltage

Reference should be disabled.

FIGURE 8-3: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

(1)

RA2

R

VREF

Module

+

–

•

VREF Output

•

Voltage

Reference

Output

Impedance

Note 1: R is dependent upon the Voltage Reference Conﬁguration VRCON<3:0> and VRCON<5>.

TABLE 8-1:

REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE

Value On

All Other

Resets

Value On

POR

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

9Fh

1Fh

85h

VRCON

VREN

VROE VRR

—

VR3

CIS

VR2

CM2

VR1

CM1

VR0

CM0

000- 0000 000- 0000

00-- 0000 00-- 0000

CMCON C2OUT C1OUT

TRISA

—

TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111

Note: - = Unimplemented, read as "0"

DS30235G-page 44

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

The PIC16C62X has a Watchdog Timer which is

controlled by conﬁguration bits. It runs off its own RC

oscillator for added reliability. There are two timers that

offer necessary delays on power-up. One is the

Oscillator Start-up Timer (OST), intended to keep the

chip in reset until the crystal oscillator is stable. The

other is the Power-up Timer (PWRT), which provides a

ﬁxed delay of 72 ms (nominal) on power-up only,

designed to keep the part in reset while the power

supply stabilizes. There is also circuitry to reset the

device if a brown-out occurs which provides at least a

72 ms reset. With these three functions on-chip, most

applications need no external reset circuitry.

9.0

SPECIAL FEATURES OF THE

CPU

Special circuits to deal with the needs of real time appli-

cations are what sets a microcontroller apart from other

processors. The PIC16C62X family has a host of such

features intended to maximize system reliability, mini-

mize cost through elimination of external components,

provide power saving operating modes and offer code

protection.

These are:

1. OSC selection

2. Reset

The SLEEP mode is designed to offer a very low

current power-down mode.The user can wake-up from

SLEEP through external reset, Watchdog Timer

wake-up or through an interrupt. Several oscillator

options are also made available to allow the part to ﬁt

the application. The RC oscillator option saves system

cost while the LP crystal option saves power. A set of

conﬁguration bits are used to select various options.

Power-on Reset (POR)

Power-up Timer (PWRT)

Oscillator Start-Up Timer (OST)

Brown-out Reset (BOR)

3. Interrupts

4. Watchdog Timer (WDT)

5. SLEEP

6. Code protection

7. ID Locations

8. In-circuit serial programming

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 45

PIC16C62X

The user will note that address 2007h is beyond

the user program memory space. In fact, it belongs

to the special test/conﬁguration memory space

(2000h – 3FFFh), which can be accessed only during

programming.

9.1

Conﬁguration Bits

The conﬁguration bits can be programmed (read as '0')

or left unprogrammed (read as '1') to select various

device conﬁgurations. These bits are mapped in

program memory location 2007h.

FIGURE 9-1: CONFIGURATION WORD

CP0⁽²⁾

(2)

CP0

(2)

CP0

(2)

CP0

(1)

CP1

—

CP1

WDTE F0SC1 F0SC0

BOREN

PWRTE

CONFIG

Address

REGISTER: 2007h

bit13

bit0

(2)

bit 13-8, CP<1:0>: Code protection bit pairs

5-4: Code protection for 2K program memory

11= Program memory code protection off

10= 0400h-07FFh code protected

01= 0200h-07FFh code protected

00= 0000h-07FFh code protected

Code protection for 1K program memory

11= Program memory code protection off

10=Program memory code protection on

01= 0200h-03FFh code protected

00= 0000h-03FFh code protected

Code protection for 0.5K program memory

11= Program memory code protection off

10= Program memory code protection off

01= Program memory code protection off

00= 0000h-01FFh code protected

bit 7:

bit 6:

Unimplemented: Read as '1'

(1)

BOREN: Brown-out Reset Enable bit

1 = BOR enabled

0 = BOR disabled

(1, 3)

bit 3:

bit 2:

PWRTE: Power-up Timer Enable bit

1 = PWRT disabled

0 = PWRT enabled

WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator Selection bits

11= RC oscillator

10= HS oscillator

01= XT oscillator

00= LP oscillator

Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. We

recommend that whenever Brown-out Reset is enabled, the Power-up Timer is also enabled.

2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.

3: Unprogrammed parts default the Power-up Timer disabled.

DS30235G-page 46

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

9.2

Oscillator Conﬁgurations

TABLE 9-1:

CAPACITOR SELECTION

FOR CERAMIC RESONATORS

9.2.1

OSCILLATOR TYPES

Ranges Characterized:

The PIC16C62X can be operated in four different

oscillator options. The user can program two

conﬁguration bits (FOSC1 and FOSC0) to select one of

these four modes:

Mode

Freq

OSC1(C1)

OSC2(C2)

XT

455 kHz

2.0 MHz

4.0 MHz

22 - 100 pF

15 - 68 pF

22 - 100 pF

15 - 68 pF

• LP

• XT

• HS

• RC

Low Power Crystal

Crystal/Resonator

HS

8.0 MHz

10 - 68 pF

10 - 22 pF

10 - 68 pF

10 - 22 pF

16.0 MHz

High Speed Crystal/Resonator

Resistor/Capacitor

Higher capacitance increases the stability of the oscillator

but also increases the start-up time. These values are for

design guidance only. Since each resonator has its own

characteristics, the user should consult the resonator man-

ufacturer for appropriate values of external components.

9.2.2

CRYSTAL OSCILLATOR / CERAMIC

RESONATORS

In XT, LP or HS modes a crystal or ceramic resonator

is connected to the OSC1 and OSC2 pins to establish

oscillation (Figure 9-2). The PIC16C62X oscillator

design requires the use of a parallel cut crystal. Use of

a series cut crystal may give a frequency out of the

crystal manufacturers speciﬁcations.When in XT, LP or

HS modes, the device can have an external clock

source to drive the OSC1 pin (Figure 9-3).

TABLE 9-2:

CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR

Mode

Freq

OSC1(C1)

OSC2(C2)

32 kHz

68 - 100 pF

15 - 30 pF

68 - 100 pF

15 - 30 pF

LP

200 kHz

100 kHz

2 MHz

4 MHz

68 - 150 pF

15 - 30 pF

150 - 200 pF

15 - 30 pF

XT

HS

FIGURE 9-2: CRYSTAL OPERATION

(OR CERAMIC RESONATOR)

(HS, XT OR LP OSC

8 MHz

10 MHz

20 MHz

15 - 30 pF

CONFIGURATION)

OSC1

Higher capacitance increases the stability of the oscillator

but also increases the start-up time. These values are for

design guidance only. Rs may be required in HS mode as

well as XT mode to avoid overdriving crystals with low drive

level speciﬁcation. Since each crystal has its own

characteristics, the user should consult the crystal manu-

facturer for appropriate values of external components.

To internal logic

C1

XTAL

RS

SLEEP

RF

OSC2

see Note

C2

PIC16C62X

See Table 9-1 and Table 9-2 for recommended

values of C1 and C2.

Note: A series resistor may be required for

AT strip cut crystals.

FIGURE 9-3: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP

OSC CONFIGURATION)

Clock from

ext. system

OSC1

PIC16C62X

OSC2

Open

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 47

PIC16C62X

9.2.3

EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

9.2.4

RC OSCILLATOR

For timing insensitive applications the “RC” device

option offers additional cost savings. The RC oscillator

frequency is a function of the supply voltage, the

resistor (Rext) and capacitor (Cext) values, and the

operating temperature. In addition to this, the oscillator

frequency will vary from unit to unit due to normal

process parameter variation. Furthermore, the

difference in lead frame capacitance between package

types will also affect the oscillation frequency,

especially for low Cext values. The user also needs to

take into account variation due to tolerance of external

R and C components used. Figure 9-6 shows how the

R/C combination is connected to the PIC16C62X. For

Rext values below 2.2 kΩ, the oscillator operation may

become unstable, or stop completely. For very high

Rext values (e.g., 1 MΩ), the oscillator becomes

sensitive to noise, humidity and leakage. Thus, we

recommend to keep Rext between 3 kΩ and 100 kΩ.

Either a prepackaged oscillator can be used or a simple

oscillator circuit with TTL gates can be built.

Prepackaged oscillators provide a wide operating

range and better stability. A well-designed crystal

oscillator will provide good performance with TTL

gates. Two types of crystal oscillator circuits can be

used; one with series resonance, or one with parallel

resonance.

Figure 9-4 shows implementation of a parallel resonant

oscillator circuit. The circuit is designed to use the

fundamental frequency of the crystal. The 74AS04

inverter performs the 180° phase shift that a parallel

oscillator requires. The 4.7 kΩ resistor provides the

negative feedback for stability. The 10 kΩ

potentiometers bias the 74AS04 in the linear region.

This could be used for external oscillator designs.

FIGURE 9-4: EXTERNAL PARALLEL

RESONANT CRYSTAL

Although the oscillator will operate with no external

capacitor (Cext = 0 pF), we recommend using values

above 20 pF for noise and stability reasons. With no or

small external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or

package lead frame capacitance.

OSCILLATOR CIRCUIT

+5V

To other

Devices

10k

74AS04

4.7k

PIC16C62X

See Section 13.0 for RC frequency variation from part

to part due to normal process variation.The variation is

larger for larger R (since leakage current variation will

affect RC frequency more for large R) and for smaller C

(since variation of input capacitance will affect RC fre-

quency more).

CLKIN

74AS04

10k

XTAL

10k

See Section 13.0 for variation of oscillator frequency

due to VDD for given Rext/Cext values as well as

frequency variation due to operating temperature for

given R, C, and VDD values.

20 pF

Figure 9-5 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental

frequency of the crystal. The inverter performs a 180°

phase shift in a series resonant oscillator circuit. The

330 kΩ resistors provide the negative feedback to bias

the inverters in their linear region.

The oscillator frequency, divided by 4, is available on

the OSC2/CLKOUT pin, and can be used for test

purposes or to synchronize other logic (Figure 3-2 for

waveform).

FIGURE 9-6: RC OSCILLATOR MODE

FIGURE 9-5: EXTERNAL SERIES

RESONANT CRYSTAL

VDD

PIC16C62X

Rext

OSCILLATOR CIRCUIT

OSC1

To other

Internal Clock

Devices

330 kΩ

Cext

PIC16C62X

74AS04

VDD

CLKIN

OSC2/CLKOUT

Fosc/4

0.1 µF

XTAL

DS30235G-page 48

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

state” on Power-on reset, MCLR reset, WDT reset and

MCLR reset during SLEEP. They are not affected by a

WDT wake-up, since this is viewed as the resumption

of normal operation. TO and PD bits are set or cleared

differently in different reset situations as indicated in

Table 9-4.These bits are used in software to determine

the nature of the reset. See Table 9-7 for a full descrip-

tion of reset states of all registers.

9.3

Reset

The PIC16C62X differentiates between various kinds

of reset:

a) Power-on reset (POR)

b) MCLR reset during normal operation

c) MCLR reset during SLEEP

d) WDT reset (normal operation)

e) WDT wake-up (SLEEP)

A simpliﬁed block diagram of the on-chip reset circuit is

shown in Figure 9-7.

f) Brown-out Reset (BOR)

The MCLR reset path has a noise ﬁlter to detect and

ignore small pulses. See Table 12-6 for pulse width

speciﬁcation.

Some registers are not affected in any reset condition;

their status is unknown on POR and unchanged in any

other reset. Most other registers are reset to a “reset

FIGURE 9-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/

VPP Pin

SLEEP

WDT

Module

Time-out

Reset

VDD rise

detect

Power-on Reset

VDD

Brown-out

Reset

Q

S

R

BOREN

OST/PWRT

OST

10-bit Ripple-counter

Chip_Reset

OSC1/

CLKIN

PWRT

10-bit Ripple-counter

(1)

On-chip

RC OSC

Enable PWRT

Enable OST

See Table 9-3 for time-out situations.

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 49

PIC16C62X

The Power-Up Time delay will vary from chip to chip

and due to VDD, temperature and process variation.

See DC parameters for details.

9.4

Power-on Reset (POR), Power-up

Timer (PWRT), Oscillator Start-up

Timer (OST) and Brown-out Reset

(BOR)

9.4.3

OSCILLATOR START-UP TIMER (OST)

9.4.1

POWER-ON RESET (POR)

The Oscillator Start-Up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over. This ensures that the crystal

oscillator or resonator has started and stabilized.

The on-chip POR circuit holds the chip in reset until

VDD has reached a high enough level for proper opera-

tion. To take advantage of the POR, just tie the MCLR

pin through a resistor to VDD. This will eliminate exter-

nal RC components usually needed to create Power-on

Reset. A maximum rise time for VDD is required. See

Electrical Speciﬁcations for details.

The OST time-out is invoked only for XT, LP and HS

modes and only on power-on reset or wake-up from

SLEEP.

9.4.4

BROWN-OUT RESET (BOR)

The POR circuit does not produce an internal reset

when VDD declines.

The PIC16C62X members have on-chip Brown-out

Reset circuitry. A conﬁguration bit, BOREN, can dis-

able (if clear/programmed) or enable (if set) the

Brown-out Reset circuitry. If VDD falls below 4.0V refer

When the device starts normal operation (exits the

reset condition), device operating parameters (voltage,

frequency, temperature, etc.) must be met to ensure

operation. If these conditions are not met, the device

must be held in reset until the operating conditions are

met.

to V

parameter D005(V

) for greater than

BOR

parameter (TBOR) in Table 12-6, the brown-out situa-

tion will reset the chip. A reset is not guaranteed to

occur if VDD falls below 4.0V for less than parameter

(TBOR).

For additional information, refer to Application Note

AN607 “Power-up Trouble Shooting”.

On any reset (Power-on, Brown-out, Watchdog, etc.)

the chip will remain in Reset until VDD rises above

BVDD.The Power-up Timer will now be invoked and will

keep the chip in reset an additional 72 ms.

9.4.2

POWER-UP TIMER (PWRT)

The Power-up Timer provides a ﬁxed 72 ms (nominal)

time-out on power-up only, from POR or Brown-out

Reset.The Power-up Timer operates on an internal RC

oscillator. The chip is kept in reset as long as PWRT is

active. The PWRT delay allows the VDD to rise to an

acceptable level. A conﬁguration bit, PWRTE can

disable (if set) or enable (if cleared or programmed) the

Power-up Timer.The Power-up Timer should always be

enabled when Brown-out Reset is enabled.

If VDD drops below BVDD while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Power-up Timer will be re-initialized. Once VDD

rises above BVDD, the Power-Up Timer will execute a

72 ms reset. The Power-up Timer should always be

enabled when Brown-out Reset is enabled. Figure 9-8

shows typical Brown-out situations.

FIGURE 9-8: BROWN-OUT SITUATIONS

VDD

BVDD Max.

BVDD Min.

Internal

Reset

72 ms

VDD

BVDD Max.

BVDD Min.

Internal

Reset

<72 ms

72 ms

VDD

BVDD Max.

BVDD Min.

Internal

Reset

72 ms

DS30235G-page 50

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

9.4.5

TIME-OUT SEQUENCE

9.4.6

POWER CONTROL (PCON)/

STATUS REGISTER

On power-up the time-out sequence is as follows: First

PWRT time-out is invoked after POR has expired.Then

OST is activated. The total time-out will vary based on

oscillator conﬁguration and PWRTE bit status. For

example, in RC mode with PWRTE bit erased (PWRT

disabled), there will be no time-out at all. Figure 9-9,

Figure 9-10 and Figure 9-11 depict time-out

sequences.

The power control/status register, PCON (address

8Eh) has two bits.

Bit0 is BOR (Brown-out). BOR is unknown on

power-on-reset. It must then be set by the user and

checked on subsequent resets to see if BOR = 0

indicating that a brown-out has occurred. The BOR

status bit is a don’t care and is not necessarily

predictable if the brown-out circuit is disabled (by

setting BOREN bit = 0 in the Conﬁguration word).

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then

bringing MCLR high will begin execution immediately

(see Figure 9-10).This is useful for testing purposes or

to synchronize more than one PIC16C62X device oper-

ating in parallel.

Bit1 is POR (Power-on-reset). It is

a ‘0’ on

power-on-reset and unaffected otherwise. The user

must write a ‘1’ to this bit following a power-on-reset.

On a subsequent reset if POR is ‘0’, it will indicate that

a power-on-reset must have occurred (VDD may have

gone too low).

Table 9-6 shows the reset conditions for some special

registers, while Table 9-7 shows the reset conditions for

all the registers.

TABLE 9-3:

TIME-OUT IN VARIOUS SITUATIONS

Power-up

Wake-up

Brown-out Reset

Oscillator Conﬁguration

from SLEEP

PWRTE = 0

PWRTE = 1

XT, HS, LP

RC

72 ms + 1024 TOSC

72 ms

1024 TOSC

—

72 ms + 1024 TOSC

72 ms

1024 TOSC

—

TABLE 9-4:

POR

STATUS/PCON BITS AND THEIR SIGNIFICANCE

BOR

TO

PD

Power-on-reset

0

1

X

0

1

0

X

0

u

1

X

0

X

u

0

u

0

Illegal, TO is set on POR

Illegal, PD is set on POR

Brown-out Reset

WDT Reset

WDT Wake-up

MCLR reset during normal operation

MCLR reset during SLEEP

Legend: u = unchanged, x = unknown

TABLE 9-5:

SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT

Value on all

other resets⁽¹⁾

Value on POR

Reset

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

83h

8Eh

STATUS

PCON

TO

—

PD

—

0001 1xxx

---- --0x

000q quuu

---- --uq

—

POR

BOR

Note1: Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during normal operation.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 51

PIC16C62X

TABLE 9-6:

INITIALIZATION CONDITION FOR SPECIAL REGISTERS

Program

Counter

STATUS

Register

PCON

Register

Condition

Power-on Reset

000h

PC + 1

000h

0001 1xxx

000u uuuu

0001 0uuu

0000 uuuu

uuu0 0uuu

000x xuuu

uuu1 0uuu

---- --0x

---- --uu

---- --u0

---- --uu

MCLR reset during normal operation

MCLR reset during SLEEP

WDT reset

WDT Wake-up

Brown-out Reset

(1)

Interrupt Wake-up from SLEEP

PC + 1

Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector

(0004h) after execution of PC+1.

TABLE 9-7:

INITIALIZATION CONDITION FOR REGISTERS

• MCLR Reset during

normal operation

• MCLR Reset during

SLEEP

• Wake up from SLEEP

through interrupt

• Wake up from SLEEP

through WDT time-out

• WDT Reset

(1)

Register

Address

Power-on Reset

• Brown-out Reset

xxxx xxxx

-

uuuu uuuu

-

uuuu uuuu

-

W

-

INDF

TMR0

00h

01h

xxxx xxxx

uuuu uuuu

(3)

0000 0000

PC + 1

PCL

02h

(4)

0001 1xxx

xxxx xxxx

---x xxxx

xxxx xxxx

00-- 0000

---0 0000

000q quuu

uuuq quuu

STATUS

FSR

03h

04h

05h

06h

1Fh

0Ah

uuuu uuuu

---u uuuu

uuuu uuuu

00-- 0000

---0 0000

uuuu uuuu

---u uuuu

uuuu uuuu

uu-- uuuu

---u uuuu

PORTA

PORTB

CMCON

PCLATH

(2)

0000 000x

0000 000u

uuuu uqqq

INTCON

0Bh

(2,5)

-0-- ----

1111 1111

---1 1111

1111 1111

-0-- ----

1111 1111

---1 1111

1111 1111

-0-- ----

-q-- ----

PIR1

0Ch

81h

85h

86h

8Ch

uuuu uuuu

---u uuuu

uuuu uuuu

-u-- ----

OPTION

TRISA

TRISB

PIE1

(1,6)

---- --0x

000- 0000

---- --uq

000- 0000

---- --uu

uuu- uuuu

PCON

8Eh

9Fh

VRCON

Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’,q= value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

4: See Table 9-6 for reset value for speciﬁc condition.

5: If wake-up was due to comparator input changing, then bit 6 = 1. All other interrupts generating a wake-up will cause bit 6 = u.

6: If reset was due to brown-out, then bit 0 = 0. All other resets will cause bit 0 = u.

DS30235G-page 52

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

FIGURE 9-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

TOST

OST TIME-OUT

INTERNAL RESET

FIGURE 9-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

TOST

OST TIME-OUT

INTERNAL RESET

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 53

PIC16C62X

FIGURE 9-12: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW

VDD POWER-UP)

FIGURE 9-13: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 1

VDD

33k

VDD

10k

MCLR

D

R

40k

R1

PIC16C62X

MCLR

PIC16C62X

C

Note 1: External power-on reset circuit is required

only if VDD power-up slope is too slow.

The diode D helps discharge the capaci-

tor quickly when VDD powers down.

Note 1: This circuit will activate reset when VDD

goes below (Vz + 0.7V) where

Vz = Zener voltage.

2: Internal Brown-out Reset circuitry

should be disabled when using this cir-

cuit.

2: < 40 kΩ is recommended to make sure

that voltage drop across R does not vio-

late the device’s electrical speciﬁcation.

3: R1 = 100Ω to 1 kΩ will limit any current

ﬂowing into MCLR from external capaci-

tor C in the event of MCLR/VPP pin break-

down due to Electrostatic Discharge

FIGURE 9-14: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 2

VDD

(ESD) or Electrical Overstress (EOS).

VDD

R1

Q1

MCLR

R2

40k

PIC16C62X

Note 1: This brown-out circuit is less expensive,

albeit less accurate. Transistor Q1 turns

off when VDD is below a certain level

such that:

R1

= 0.7 V

VDD x

R1 + R2

2: Internal brown-out reset should be dis-

abled when using this circuit.

3: Resistors should be adjusted for the

characteristics of the transistor.

DS30235G-page 54

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

the interrupt can be determined by polling the interrupt

ﬂag bits.The interrupt ﬂag bit(s) must be cleared in soft-

ware before re-enabling interrupts to avoid RB0/INT

recursive interrupts.

9.5

Interrupts

The PIC16C62X has 4 sources of interrupt:

• External interrupt RB0/INT

• TMR0 overﬂow interrupt

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs (Figure 9-16).

The latency is the same for one or two cycle

instructions. Once in the interrupt service routine the

source(s) of the interrupt can be determined by polling

the interrupt ﬂag bits. The interrupt ﬂag bit(s) must be

cleared in software before re-enabling interrupts to

avoid multiple interrupt requests. Individual interrupt

ﬂag bits are set regardless of the status of their

corresponding mask bit or the GIE bit.

• PortB change interrupts (pins RB7:RB4)

• Comparator interrupt

The interrupt control register (INTCON) records

individual interrupt requests in ﬂag bits. It also has

individual and global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in

INTCON register. GIE is cleared on reset.

The “return from interrupt” instruction, RETFIE, exits

interrupt routine as well as sets the GIE bit, which

re-enable RB0/INT interrupts.

Note 1: Individual interrupt ﬂag bits are set

regardless of the status of their

corresponding mask bit or the GIE bit.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The CPU will execute a

NOP in the cycle immediately following

the instruction which clears the GIE bit.

The interrupts which were ignored are

still pending to be serviced when the GIE

bit is set again.

The INT pin interrupt, the RB port change interrupt and

the TMR0 overﬂow interrupt ﬂags are contained in the

INTCON register.

The peripheral interrupt ﬂag is contained in the special

register PIR1.The corresponding interrupt enable bit is

contained in special registers PIE1.

When an interrupt is responded to, the GIE is cleared

to disable any further interrupt, the return address is

pushed into the stack and the PC is loaded with 0004h.

Once in the interrupt service routine the source(s) of

FIGURE 9-15: INTERRUPT LOGIC

Wake-up

(If in SLEEP mode)

T0IF

T0IE

INTF

INTE

Interrupt

to CPU

RBIF

RBIE

CMIF

CMIE

PEIE

GIE

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 55

PIC16C62X

9.5.1

RB0/INT INTERRUPT

9.5.3

PORTB INTERRUPT

External interrupt on RB0/INT pin is edge triggered:

either rising if INTEDG bit (OPTION<6>) is set, or fall-

ing, if INTEDG bit is clear. When a valid edge appears

on the RB0/INT pin, the INTF bit (INTCON<1>) is set.

This interrupt can be disabled by clearing the INTE

control bit (INTCON<4>).The INTF bit must be cleared

in software in the interrupt service routine before

re-enabling this interrupt. The RB0/INT interrupt can

wake-up the processor from SLEEP, if the INTE bit was

set prior to going into SLEEP. The status of the GIE bit

decides whether or not the processor branches to the

interrupt vector following wake-up. See Section 9.8 for

details on SLEEP and Figure 9-18 for timing of

wake-up from SLEEP through RB0/INT interrupt.

An input change on PORTB <7:4> sets the RBIF

(INTCON<0>) bit. The interrupt can be enabled/dis-

abled by setting/clearing the RBIE (INTCON<4>) bit.

For operation of PORTB (Section 5.2).

Note: If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RBIF inter-

rupt ﬂag may not get set.

9.5.4

COMPARATOR INTERRUPT

See Section 7.6 for complete description of comparator

interrupts.

9.5.2

TMR0 INTERRUPT

An overﬂow (FFh → 00h) in the TMR0 register will

set the T0IF (INTCON<2>) bit. The interrupt can

be enabled/disabled by setting/clearing T0IE

(INTCON<5>) bit. For operation of the Timer0 module,

see Section 6.0.

FIGURE 9-16: INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT

3

4

INT pin

1

Interrupt Latency

INTF ﬂag

(INTCON<1>)

5

2

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

PC

0004h

PC+1

—

0005h

PC

Instruction

fetched

Inst (PC)

Inst (PC+1)

Inst (0004h)

Inst (0005h)

Inst (0004h)

Instruction

executed

Dummy Cycle

Inst (PC)

Inst (PC-1)

Note

1: INTF ﬂag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 Tcy. Synchronous latency = 3 Tcy, where Tcy = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in RC oscillator mode.

4: For minimum width of INT pulse, refer to AC specs.

5: INTF is enabled to be set anytime during the Q4-Q1 cycles.

TABLE 9-8:

SUMMARY OF INTERRUPT REGISTERS

Value on all

other resets⁽¹⁾

Value on POR

Reset

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh

0Ch

8Ch

INTCON

GIE

—

PEIE

CMIF

CMIE

T0IE

—

INTE

—

RBIE

—

T0IF

—

INTF

—

RBIF

—

0000 000x

-0-- ----

0000 000u

-0-- ----

PIR1

PIE1

—

Note1: Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during normal operation.

DS30235G-page 56

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

9.6

Context Saving During Interrupts

9.7

Watchdog Timer (WDT)

During an interrupt, only the return PC value is saved

on the stack.Typically, users may wish to save key reg-

isters during an interrupt e.g. W register and STATUS

register. This will have to be implemented in software.

The watchdog timer is a free running on-chip RC oscil-

lator which does not require any external components.

This RC oscillator is separate from the RC oscillator of

the CLKIN pin. That means that the WDT will run, even

if the clock on the OSC1 and OSC2 pins of the device

has been stopped, for example, by execution of a

SLEEP instruction. During normal operation, a WDT

time-out generates a device RESET. If the device is in

SLEEP mode, a WDT time-out causes the device to

wake-up and continue with normal operation.The WDT

can be permanently disabled by programming the con-

ﬁguration bit WDTE as clear (Section 9.1).

Example 9-1 stores and restores the STATUS and W

registers. The user register, W_TEMP, must be deﬁned

in both banks and must be deﬁned at the same offset

from the bank base address (i.e., W_TEMP is deﬁned

at 0x20 in Bank 0 and it must also be deﬁned at 0xA0

in Bank 1). The user register, STATUS_TEMP, must be

deﬁned in Bank 0. The Example 9-1:

• Stores the W register

9.7.1

WDT PERIOD

• Stores the STATUS register in Bank 0

• Executes the ISR code

The WDT has a nominal time-out period of 18 ms, (with

no prescaler). The time-out periods vary with tempera-

ture, V and process variations from part to part (see

• Restores the STATUS (and bank select bit

register)

DD

• Restores the W register

DC specs). If longer time-out periods are desired, a

prescaler with a division ratio of up to 1:128 can be

assigned to the WDT under software control by writing

to the OPTION register. Thus, time-out periods up to

2.3 seconds can be realized.

EXAMPLE 9-1: SAVING THE STATUS AND

W REGISTERS IN RAM

MOVWF

W_TEMP

;copy W to temp register,

;could be in either bank

The CLRWDTand SLEEPinstructions clear the WDT

and the postscaler, if assigned to the WDT, and prevent

it from timing out and generating a device RESET.

SWAPF

BCF

STATUS,W

;swap status to be saved into W

STATUS,RP0

;change to bank 0 regardless

;of current bank

The TO bit in the STATUS register will be cleared upon

a Watchdog Timer time-out.

MOVWF

STATUS_TEMP

(ISR)

;save status to bank 0

;register

:

9.7.2

WDT PROGRAMMING CONSIDERATIONS

:

It should also be taken in account that under worst case

conditions (VDD = Min., Temperature = Max., max.

WDT prescaler) it may take several seconds before a

WDT time-out occurs.

SWAPF

STATUS_TEMP,W ;swap STATUS_TEMP register

;into W, sets bank to original

;state

MOVWF

SWAPF

STATUS

;move W into STATUS register

;swap W_TEMP

W_TEMP,F

W_TEMP,W

;swap W_TEMP into W

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 57

PIC16C62X

FIGURE 9-17: WATCHDOG TIMER BLOCK DIAGRAM

From TMR0 Clock Source

(Figure 6-6)

0

M

U

X

Postscaler

8

1

Watchdog

Timer

•

PS<2:0>

To TMR0 (Figure 6-6)

PSA

8 - to -1 MUX

PSA

WDT

Enable Bit

•

1

0

MUX

WDT

Time-out

Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.

TABLE 9-9:

Address

SUMMARY OF WATCHDOG TIMER REGISTERS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

2007h

81h

Conﬁg. bits

OPTION

---

BOREN

INTEDG

CP1

CP0

PWRTE

PSA

WDTE

PS2

FOSC1

PS1

FOSC0

PS0

RBPU

T0CS

T0SE

Legend: Shaded cells are not used by the Watchdog Timer.

_

Note:

= Unimplemented location, read as “0”

+ = Reserved for future use

DS30235G-page 58

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

The ﬁrst event will cause a device reset. The two latter

events are considered a continuation of program exe-

cution. The TO and PD bits in the STATUS register can

be used to determine the cause of device reset. PD

bit, which is set on power-up is cleared when SLEEP is

invoked. TO bit is cleared if WDT Wake-up occurred.

9.8

Power-Down Mode (SLEEP)

The Power-down mode is entered by executing a

SLEEPinstruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the PD bit in the STATUS register is

cleared, the TO bit is set, and the oscillator driver is

turned off. The I/O ports maintain the status they had,

before SLEEP was executed (driving high, low, or

hi-impedance).

When the SLEEP instruction is being executed, the

next instruction (PC + 1) is pre-fetched. For the device

to wake-up through an interrupt event, the correspond-

ing interrupt enable bit must be set (enabled). Wake-up

is regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEPinstruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEPinstruction and then branches to the inter-

rupt address (0004h). In cases where the execution of

the instruction following SLEEP is not desirable, the

user should have an NOPafter the SLEEPinstruction.

For lowest current consumption in this mode, all I/O

pins should be either at VDD, or VSS, with no external

circuitry drawing current from the I/O pin and the com-

parators and VREF should be disabled. I/O pins that are

hi-impedance inputs should be pulled high or low exter-

nally to avoid switching currents caused by ﬂoating

inputs. The T0CKI input should also be at VDD or VSS

for lowest current consumption. The contribution from

on chip pull-ups on PORTB should be considered.

Note: If the global interrupts are disabled (GIE is

cleared), but any interrupt source has both

its interrupt enable bit and the correspond-

ing interrupt ﬂag bits set, the device will

immediately wakeup from sleep.The sleep

instruction is completely executed.

The MCLR pin must be at a logic high level (VIHMC).

Note: It should be noted that a RESET generated

by a WDT time-out does not drive MCLR

pin low.

9.8.1

WAKE-UP FROM SLEEP

The WDT is cleared when the device wakes-up from

sleep, regardless of the source of wake-up.

The device can wake-up from SLEEP through one of

the following events:

1. External reset input on MCLR pin

2. Watchdog Timer Wake-up (if WDT was enabled)

3. Interrupt from RB0/INT pin, RB Port change, or

the Peripheral Interrupt (Comparator).

FIGURE 9-18: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

TOST(2)

INTF ﬂag

(INTCON<1>)

Interrupt Latency

(Note 2)

GIE bit

(INTCON<7>)

Processor in

SLEEP

INSTRUCTION FLOW

PC

PC+1

PC+2

PC + 2

0004h

0005h

Instruction

Inst(0004h)

Inst(PC + 1)

Inst(PC + 2)

Inst(0005h)

Inst(PC) = SLEEP

Inst(PC - 1)

fetched

Instruction

executed

Dummy cycle

SLEEP

Inst(PC + 1)

Inst(0004h)

Note 1: XT, HS or LP oscillator mode assumed.

2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.

3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.

4: CLKOUT is not available in these osc modes, but shown here for timing reference.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 59

PIC16C62X

9.9

Code Protection

9.11

In-Circuit Serial Programming

If the code protection bit(s) have not been

programmed, the on-chip program memory can be

read out for veriﬁcation purposes.

The PIC16C62X microcontrollers can be serially

programmed while in the end application circuit.This is

simply done with two lines for clock and data, and three

other lines for power, ground, and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices, and then program the

microcontroller just before shipping the product. This

also allows the most recent ﬁrmware or a custom

ﬁrmware to be programmed.

Note: Microchip does not recommend code

protecting windowed devices.

9.10

ID Locations

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code-identiﬁcation numbers. These locations are

not accessible during normal execution but are

readable and writable during program/verify. Only the

least signiﬁcant 4 bits of the ID locations are used.

The device is placed into a program/verify mode by

holding the RB6 and RB7 pins low while raising the

MCLR (VPP) pin from VIL to VIHH (see programming

speciﬁcation). RB6 becomes the programming clock

and RB7 becomes the programming data. Both RB6

and RB7 are Schmitt Trigger inputs in this mode.

After reset, to place the device into programming/verify

mode, the program counter (PC) is at location 00h. A

6-bit command is then supplied to the device.

Depending on the command, 14-bits of program data

are then supplied to or from the device, depending if the

command was a load or a read. For complete details of

serial

programming,

please

refer

to

the

PIC16C6X/7X/9XX

(#DS30228).

Programming

Speciﬁcations

A typical in-circuit serial programming connection is

shown in Figure 9-19.

FIGURE 9-19: TYPICAL IN-CIRCUIT SERIAL

PROGRAMMING

CONNECTION

To Normal

Connections

External

Connector

Signals

PIC16C62X

+5V

0V

VDD

VSS

VPP

MCLR/VPP

RB6

RB7

CLK

Data I/O

VDD

To Normal

Connections

DS30235G-page 60

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

The instruction set is highly orthogonal and is grouped

into three basic categories:

10.0 INSTRUCTION SET SUMMARY

Each PIC16C62X instruction is a 14-bit word divided

into an OPCODE which speciﬁes the instruction type

and one or more operands which further specify the

operation of the instruction. The PIC16C62X instruc-

tion set summary in Table 10-2 lists byte-oriented,

bit-oriented, and literal and control operations.

Table 10-1 shows the opcode ﬁeld descriptions.

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations

All instructions are executed within one single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of an

instruction. In this case, the execution takes two

instruction cycles with the second cycle executed as a

NOP. One instruction cycle consists of four oscillator

periods.Thus, for an oscillator frequency of 4 MHz, the

For byte-oriented instructions, 'f' represents a ﬁle

register designator and 'd' represents a destination

designator. The ﬁle register designator speciﬁes which

ﬁle register is to be used by the instruction.

normal instruction execution time is 1 µs. If

a

The destination designator speciﬁes where the result of

the operation is to be placed. If 'd' is zero, the result is

placed in the W register. If 'd' is one, the result is placed

in the ﬁle register speciﬁed in the instruction.

conditional test is true or the program counter is

changed as a result of an instruction, the instruction

execution time is 2 µs.

Table 10-1 lists the instructions recognized by the

MPASM assembler.

For bit-oriented instructions, 'b' represents a bit ﬁeld

designator which selects the number of the bit affected

by the operation, while 'f' represents the number of the

ﬁle in which the bit is located.

Figure 10-1 shows the three general formats that the

instructions can have.

For literal and control operations, 'k' represents an

eight or eleven bit constant or literal value.

Note: To maintain upward compatibility with

future PICmicro™ products, do not use the

OPTIONand TRISinstructions.

TABLE 10-1: OPCODE FIELD

DESCRIPTIONS

All examples use the following format to represent a

hexadecimal number:

Field

Description

0xhh

f

W

b

k

x

Register ﬁle address (0x00 to 0x7F)

Working register (accumulator)

where h signiﬁes a hexadecimal digit.

FIGURE 10-1: GENERAL FORMAT FOR

INSTRUCTIONS

Bit address within an 8-bit ﬁle register

Literal ﬁeld, constant data or label

Don't care location (= 0 or 1)

Byte-oriented ﬁle register operations

The assembler will generate code with x = 0. It is the

recommended form of use for compatibility with all

Microchip software tools.

13

8

7

6

0

OPCODE

d

f (FILE #)

d

Destination select; d = 0: store result in W,

d = 1: store result in ﬁle register f.

Default is d = 1

d = 0 for destination W

d = 1 for destination f

f = 7-bit ﬁle register address

label Label name

TOS Top of Stack

PC Program Counter

Bit-oriented ﬁle register operations

13 10 9

b (BIT #)

7

6

OPCODE

f (FILE #)

PCLATH

Program Counter High Latch

GIE Global Interrupt Enable bit

WDT Watchdog Timer/Counter

TO Time-out bit

b = 3-bit bit address

f = 7-bit ﬁle register address

PD Power-down bit

Literal and control operations

dest Destination either the W register or the speciﬁed

register ﬁle location

General

[ ] Options

13

8

7

0

Contents

( )

→

OPCODE

k (literal)

Assigned to

k = 8-bit immediate value

Register bit ﬁeld

In the set of

< >

CALLand GOTOinstructions only

13 11 10

OPCODE

k = 11-bit immediate value

User deﬁned term (font is courier)

italics

k (literal)

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 61

PIC16C62X

TABLE 10-2: PIC16C62X INSTRUCTION SET

Mnemonic,

Operands

Description

Cycles

14-Bit Opcode

Status

Affected

Notes

MSb

LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

f, d

f

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

1

1(2)

1

1(2)

1

00

0111 dfff ffff C,DC,Z

1,2

2

0101 dfff ffff

0001 lfff ffff

0001 0000 0011

1001 dfff ffff

0011 dfff ffff

1011 dfff ffff

1010 dfff ffff

1111 dfff ffff

0100 dfff ffff

1000 dfff ffff

0000 lfff ffff

0000 0xx0 0000

1101 dfff ffff

1100 dfff ffff

Z

-

f, d

f

1,2

1,2,3

1,2

1,2,3

1,2

DECFSZ

INCF

Z

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

Z

1,2

Move W to f

No Operation

-

f, d

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

C

1,2

0010 dfff ffff C,DC,Z

1110 dfff ffff

0110 dfff ffff Z

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1

01

00bb bfff ffff

01bb bfff ffff

10bb bfff ffff

11bb bfff ffff

1,2

3

1 (2) 01

3

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

k

-

k

-

k

-

k

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

1

2

1

2

1

2

1

11

10

00

10

11

00

11

00

11

111x kkkk kkkk C,DC,Z

1001 kkkk kkkk

0kkk kkkk kkkk

Z

0000 0110 0100 TO,PD

1kkk kkkk kkkk

Inclusive OR literal with W

Move literal to W

1000 kkkk kkkk

00xx kkkk kkkk

0000 0000 1001

01xx kkkk kkkk

0000 0000 1000

Z

Return from interrupt

Return with literal in W

Return from Subroutine

Go into standby mode

Subtract W from literal

Exclusive OR literal with W

0000 0110 0011 TO,PD

110x kkkk kkkk C,DC,Z

1010 kkkk kkkk

Z

Note 1: When an I/O register is modiﬁed as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is '1' for a pin conﬁgured as input and is driven low by an external

device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned

to the Timer0 Module.

3: If Program Counter (PC) is modiﬁed or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

DS30235G-page 62

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

10.1

Instruction Descriptions

ANDLW

AND Literal with W

ADDLW

Add Literal and W

Syntax:

[ label ] ANDLW

k

Syntax:

[ label ] ADDLW

k

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 ≤ k ≤ 255

Operands:

0 ≤ k ≤ 255

(W) + k → (W)

C, DC, Z

(W) .AND. (k) → (W)

Operation:

Z

Status Affected:

Encoding:

11

1001

kkkk

11

111x

kkkk

The contents of W register are

AND’ed with the eight bit literal 'k'.The

result is placed in the W register.

The contents of the W register are

added to the eight bit literal 'k' and the

result is placed in the W register.

Description:

Words:

Cycles:

Example

1

Words:

Cycles:

Example

1

ANDLW

0x5F

ADDLW

0x15

Before Instruction

W

=

0xA3

0x03

W

=

0x10

0x25

After Instruction

W

=

W

=

ADDWF

Syntax:

Add W and f

ANDWF

Syntax:

AND W with f

[ label ] ADDWF f,d

[ label ] ANDWF f,d

Operands:

0 ≤ f ≤ 127

Operands:

0 ≤ f ≤ 127

d

[0,1]

d

[0,1]

Operation:

(W) + (f) → (dest)

Operation:

(W) .AND. (f) → (dest)

Status Affected:

Encoding:

C, DC, Z

Status Affected:

Encoding:

Z

00

0111

dfff

ffff

00

0101

dfff

ffff

Add the contents of the W register

with register 'f'. If 'd' is 0 the result is

stored in the W register. If 'd' is 1 the

result is stored back in register 'f'.

AND the W register with register 'f'. If

'd' is 0 the result is stored in the W

register. If 'd' is 1 the result is stored

back in register 'f'.

Description:

Words:

Cycles:

Example

1

Words:

Cycles:

Example

1

ADDWF

FSR,

0

ANDWF

FSR, 1

Before Instruction

W

FSR =

=

0x17

0xC2

W

FSR =

=

0x17

0xC2

After Instruction

W

FSR =

=

0xD9

0xC2

W

FSR =

=

0x17

0x02

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 63

PIC16C62X

BCF

Bit Clear f

BTFSC

Bit Test, Skip if Clear

Syntax:

Operands:

[ label ] BCF f,b

Syntax:

[ label ] BTFSC f,b

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation:

Status Affected:

Encoding:

Description:

Words:

0 → (f<b>)

Operation:

skip if (f<b>) = 0

None

Status Affected:

Encoding:

01

00bb

bfff

ffff

01

10bb

bfff

ffff

If bit 'b' in register 'f' is '0' then the next

instruction is skipped.

Bit 'b' in register 'f' is cleared.

Description:

1

If bit 'b' is '0' then the next instruction

fetched during the current instruction

execution is discarded, and a NOP is

executed instead, making this a

two-cycle instruction.

Cycles:

BCF

FLAG_REG, 7

Example

Before Instruction

FLAG_REG = 0xC7

After Instruction

Words:

Cycles:

Example

1

1(2)

FLAG_REG = 0x47

HERE

FALSE

TRUE

BTFSC FLAG,1

GOTO

PROCESS_CODE

•

Before Instruction

PC

=

address HERE

After Instruction

if FLAG<1> = 0,

PC =

address TRUE

if FLAG<1>=1,

PC =

address FALSE

BSF

Bit Set f

Syntax:

Operands:

[ label ] BSF f,b

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation:

Status Affected:

Encoding:

Description:

Words:

1 → (f<b>)

None

01

01bb

bfff

ffff

Bit 'b' in register 'f' is set.

1

Cycles:

BSF

FLAG_REG,

7

Example

Before Instruction

FLAG_REG = 0x0A

After Instruction

FLAG_REG = 0x8A

DS30235G-page 64

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

BTFSS

Bit Test f, Skip if Set

CLRF

Clear f

Syntax:

[ label ] BTFSS f,b

Syntax:

[ label ] CLRF

f

Operands:

0 ≤ f ≤ 127

0 ≤ b < 7

Operands:

Operation:

0 ≤ f ≤ 127

00h → (f)

1 → Z

Operation:

skip if (f<b>) = 1

None

Status Affected:

Encoding:

Status Affected:

Encoding:

Z

01

11bb

bfff

ffff

00

0001

1fff

ffff

If bit 'b' in register 'f' is '1' then the next

instruction is skipped.

If bit 'b' is '1', then the next instruction

fetched during the current instruction

execution, is discarded and a NOP is

executed instead, making this a

two-cycle instruction.

The contents of register 'f' are cleared

and the Z bit is set.

Description:

Words:

Cycles:

Example

1

CLRF

FLAG_REG

Words:

Cycles:

Example

1

Before Instruction

FLAG_REG

After Instruction

FLAG_REG

Z

1(2)

=

0x5A

HERE

FALSE

TRUE

BTFSS FLAG,1

=

0x00

1

GOTO

PROCESS_CODE

•

Before Instruction

PC

=

address HERE

After Instruction

if FLAG<1> = 0,

PC =

address FALSE

if FLAG<1> = 1,

PC =

address TRUE

CLRW

Clear W

CALL

Call Subroutine

[ label ] CALL k

0 ≤ k ≤ 2047

Syntax:

[ label ] CLRW

None

Syntax:

Operands:

Operation:

Operands:

Operation:

00h → (W)

1 → Z

(PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Status Affected:

Encoding:

Z

Status Affected:

Encoding:

None

00

0001

0000

0011

10

0kkk

kkkk

W register is cleared. Zero bit (Z) is

set.

Description:

Call Subroutine. First, return address

(PC+1) is pushed onto the stack. The

eleven bit immediate address is loaded

into PC bits <10:0>. The upper bits of

the PC are loaded from PCLATH.

CALLis a two-cycle instruction.

Description:

Words:

Cycles:

Example

1

CLRW

Words:

Cycles:

Example

1

2

Before Instruction

W

=

0x5A

After Instruction

HERE

CALL THERE

W

=

0x00

1

Before Instruction

Z

=

PC

=

Address HERE

After Instruction

PC

= Address THERE

TOS = Address HERE+1

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 65

PIC16C62X

CLRWDT

Syntax:

Clear Watchdog Timer

DECF

Decrement f

[ label ] DECF f,d

0 ≤ f ≤ 127

[ label ] CLRWDT

None

Syntax:

Operands:

Operation:

d

[0,1]

00h → WDT

0 → WDT prescaler,

1 → TO

Operation:

(f) - 1 → (dest)

Status Affected:

Encoding:

Z

1 → PD

00

0011

dfff

ffff

Status Affected:

Encoding:

TO, PD

Decrement register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd'

is 1 the result is stored back in register

'f'.

Description:

00

0000

0110

0100

CLRWDTinstruction resets the

Description:

Watchdog Timer. It also resets the

prescaler of the WDT. Status bits TO

and PD are set.

Words:

Cycles:

Example

1

Words:

Cycles:

Example

1

DECF

CNT, 1

1

Before Instruction

CLRWDT

CNT

Z

=

0x01

0

Before Instruction

After Instruction

WDT counter

After Instruction

=

?

CNT

Z

=

0x00

1

WDT counter

0x00

WDT prescaler=

0

1

TO

PD

=

COMF

Complement f

[ label ] COMF f,d

0 ≤ f ≤ 127

DECFSZ

Syntax:

Decrement f, Skip if 0

[ label ] DECFSZ f,d

0 ≤ f ≤ 127

Syntax:

Operands:

d

[0,1]

d

[0,1]

Operation:

(f) → (dest)

Operation:

(f) - 1 → (dest); skip if result = 0

Status Affected:

Encoding:

Z

Status Affected:

Encoding:

None

00

1001

dfff

ffff

00

1011

dfff

ffff

The contents of register 'f' are

Description:

decremented. If 'd' is 0 the result is

placed in the W register. If 'd' is 1 the

result is placed back in register 'f'.

If the result is 0, the next instruction,

which is already fetched, is discarded. A

NOP is executed instead making it a

two-cycle instruction.

complemented. If 'd' is 0 the result is

stored in W. If 'd' is 1 the result is

stored back in register 'f'.

Words:

Cycles:

Example

1

COMF

REG1,0

Words:

Cycles:

Example

1

Before Instruction

1(2)

REG1

After Instruction

REG1

=

0x13

HERE

DECFSZ

GOTO

CNT, 1

LOOP

=

0x13

0xEC

CONTINUE •

W

•

Before Instruction

PC

=

address HERE

After Instruction

CNT

if CNT =

PC

if CNT ≠

PC

=

CNT - 1

0,

address CONTINUE

0,

address HERE+1

=

DS30235G-page 66

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

GOTO

Unconditional Branch

[ label ] GOTO k

0 ≤ k ≤ 2047

INCFSZ

Syntax:

Increment f, Skip if 0

Syntax:

[ label ] INCFSZ f,d

Operands:

Operation:

Operands:

0 ≤ f ≤ 127

d

[0,1]

k → PC<10:0>

PCLATH<4:3> → PC<12:11>

Operation:

(f) + 1 → (dest), skip if result = 0

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

10

1kkk

kkkk

00

1111

dfff

ffff

GOTOis an unconditional branch. The

eleven bit immediate value is loaded

into PC bits <10:0>. The upper bits of

PC are loaded from PCLATH<4:3>.

GOTOis a two-cycle instruction.

The contents of register 'f' are

Description:

incremented. If 'd' is 0 the result is

placed in the W register. If 'd' is 1 the

result is placed back in register 'f'.

If the result is 0, the next instruction,

which is already fetched, is discarded.

A NOP is executed instead making it

a two-cycle instruction.

Words:

Cycles:

Example

1

2

Words:

Cycles:

Example

1

GOTO THERE

1(2)

After Instruction

HERE

INCFSZ

GOTO

CNT,

LOOP

1

PC

=

Address THERE

CONTINUE •

•

Before Instruction

PC

=

address HERE

After Instruction

CNT

=

CNT + 1

if CNT=

0,

PC

if CNT≠

=

address CONTINUE

0,

PC

=

address HERE +1

INCF

Increment f

IORLW

Inclusive OR Literal with W

[ label ] IORLW k

0 ≤ k ≤ 255

Syntax:

Operands:

[ label ] INCF f,d

Syntax:

0 ≤ f ≤ 127

Operands:

Operation:

Status Affected:

Encoding:

Description:

d

[0,1]

(W) .OR. k → (W)

Z

Operation:

(f) + 1 → (dest)

Status Affected:

Encoding:

Z

11

1000

kkkk

00

1010

dfff

ffff

The contents of the W register is

OR’ed with the eight bit literal 'k'. The

result is placed in the W register.

The contents of register 'f' are

Description:

incremented. If 'd' is 0 the result is

placed in the W register. If 'd' is 1 the

result is placed back in register 'f'.

Words:

Cycles:

Example

1

Words:

Cycles:

Example

1

IORLW

0x35

Before Instruction

INCF

CNT, 1

W

=

0x9A

Before Instruction

After Instruction

CNT

Z

=

0xFF

0

W

=

0xBF

1

Z

=

After Instruction

CNT

Z

=

0x00

1

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 67

PIC16C62X

IORWF

Inclusive OR W with f

MOVF

Move f

Syntax:

[ label ] IORWF f,d

Syntax:

Operands:

[ label ] MOVF f,d

Operands:

0 ≤ f ≤ 127

d

[0,1]

d

[0,1]

Operation:

(W) .OR. (f) → (dest)

Operation:

(f) → (dest)

Status Affected:

Encoding:

Z

Status Affected:

Encoding:

Z

00

0100

dfff

ffff

00

1000

dfff

ffff

Inclusive OR the W register with

register 'f'. If 'd' is 0 the result is placed

in the W register. If 'd' is 1 the result is

placed back in register 'f'.

The contents of register f is moved to

a destination dependent upon the

status of d. If d = 0, destination is W

register. If d = 1, the destination is ﬁle

register f itself. d = 1 is useful to test a

ﬁle register since status ﬂag Z is

affected.

Description:

Words:

Cycles:

Example

1

IORWF

RESULT, 0

Words:

Cycles:

Example

1

Before Instruction

RESULT =

0x13

0x91

MOVF

FSR, 0

W

=

After Instruction

RESULT =

W

Z

0x13

0x93

1

W = value in FSR register

=

Z

= 1

MOVLW

Move Literal to W

[ label ] MOVLW k

0 ≤ k ≤ 255

MOVWF

Move W to f

[ label ] MOVWF

0 ≤ f ≤ 127

(W) → (f)

Syntax:

f

Operands:

Operation:

Status Affected:

Encoding:

Description:

Operands:

Operation:

Status Affected:

Encoding:

Description:

k → (W)

None

11

00xx

kkkk

00

0000

1fff

ffff

The eight bit literal 'k' is loaded into W

register.The don’t cares will assemble

as 0’s.

Move data from W register to register

'f'.

Words:

Cycles:

Example

1

Words:

Cycles:

Example

1

MOVWF

OPTION

MOVLW

0x5A

Before Instruction

OPTION =

After Instruction

0xFF

0x4F

W

=

0x5A

W

=

After Instruction

OPTION =

0x4F

W

=

DS30235G-page 68

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

NOP

No Operation

[ label ] NOP

None

RETFIE

Return from Interrupt

[ label ] RETFIE

None

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Operands:

Operation:

No operation

None

TOS → PC,

1 → GIE

Status Affected:

Encoding:

None

00

0000

0xx0

0000

00

0000

1001

No operation.

Return from Interrupt. Stack is POPed

and Top of Stack (TOS) is loaded in

the PC. Interrupts are enabled by

setting Global Interrupt Enable bit,

GIE (INTCON<7>).This is a two-cycle

instruction.

Description:

1

Cycles:

1

NOP

Example

Words:

Cycles:

Example

1

2

RETFIE

After Interrupt

PC

GIE =

=

TOS

1

RETLW

Return with Literal in W

[ label ] RETLW k

0 ≤ k ≤ 255

OPTION

Syntax:

Load Option Register

[ label ] OPTION

None

Syntax:

Operands:

Operation:

Operands:

Operation:

(W) → OPTION

k → (W);

TOS → PC

Status Affected: None

00

0000

0110

0010

Encoding:

Status Affected:

Encoding:

None

The contents of the W register are

loaded in the OPTION register. This

instruction is supported for code

compatibility with PIC16C5X products.

Since OPTION is a readable/writable

register, the user can directly

address it.

Description:

11

01xx

kkkk

The W register is loaded with the eight

bit literal 'k'. The program counter is

loaded from the top of the stack (the

return address). This is a two-cycle

instruction.

Description:

Words:

Cycles:

Example

1

2

Words:

Cycles:

Example

1

CALL TABLE

;W contains table

;offset value

•

;W now has table

To maintain upward compatibility

with future PICmicro™ products,

do not use this instruction.

value

•

TABLE

ADDWF PC

;W = offset

;Begin table

;

RETLW k1

RETLW k2

•

RETLW kn

; End of table

Before Instruction

W

=

0x07

After Instruction

W

=

value of k8

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 69

PIC16C62X

RETURN

Return from Subroutine

RRF

Rotate Right f through Carry

[ label ] RRF f,d

0 ≤ f ≤ 127

Syntax:

[ label ] RETURN

None

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

d

[0,1]

TOS → PC

None

Operation:

See description below

C

Status Affected:

Encoding:

00

0000

1000

00

1100

dfff

ffff

Return from subroutine. The stack is

POPed and the top of the stack (TOS)

is loaded into the program counter.

This is a two cycle instruction.

The contents of register 'f' are rotated

one bit to the right through the Carry

Flag. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Description:

Words:

Cycles:

Example

1

2

C

Register f

RETURN

After Interrupt

Words:

Cycles:

Example

1

PC

=

TOS

RRF

REG1,0

Before Instruction

REG1

C

=

1110 0110

0

After Instruction

REG1

W

C

=

1110 0110

0111 0011

0

RLF

Rotate Left f through Carry

SLEEP

Syntax:

Operands:

[ label ]

RLF f,d

Syntax:

[ label ] SLEEP

None

0 ≤ f ≤ 127

Operands:

Operation:

d

[0,1]

00h → WDT,

0 → WDT prescaler,

1 → TO,

Operation:

See description below

C

Status Affected:

Encoding:

0 → PD

00

1101

dfff

ffff

Status Affected:

Encoding:

TO, PD

The contents of register 'f' are rotated

one bit to the left through the Carry

Flag. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

stored back in register 'f'.

Description:

00

0000

0110

0011

The power-down status bit, PD is

cleared. Time-out status bit, TO is

set. Watchdog Timer and its

Description:

C

Register f

prescaler are cleared.

The processor is put into SLEEP

mode with the oscillator stopped.

See Section 9.8 for more details.

Words:

Cycles:

Example

1

Words:

1

RLF

REG1,0

Cycles:

Example:

1

Before Instruction

SLEEP

REG1

=

1110 0110

0

C

After Instruction

REG1

W

C

=

1110 0110

1100 1100

1

DS30235G-page 70

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

SUBLW

Subtract W from Literal

SUBWF

Syntax:

Subtract W from f

Syntax:

[ label ]

SUBLW k

[ label ]

SUBWF f,d

Operands:

Operation:

0 ≤ k ≤ 255

Operands:

0 ≤ f ≤ 127

d

[0,1]

k - (W) → (W)

Operation:

(f) - (W) → (dest)

Status

C, DC, Z

Affected:

Status

C, DC, Z

Affected:

Encoding:

11

110x

kkkk

Encoding:

00

0010

dfff

ffff

The W register is subtracted (2’s com-

plement method) from the eight bit literal

'k'. The result is placed in the W register.

Description:

Subtract (2’s complement method)

Description:

W register from register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is 1

the result is stored back in register 'f'.

Words:

1

Cycles:

Words:

1

Example 1:

SUBLW

0x02

Cycles:

Before Instruction

Example 1:

SUBWF

REG1,1

W

C

=

1

?

Before Instruction

REG1

W

C

=

3

2

?

After Instruction

W

=

1

C

=

1; result is posi-

After Instruction

tive

REG1

W

C

=

1

2

Example 2:

Example 3:

Before Instruction

W

C

=

2

?

1; result is positive

Example 2:

Before Instruction

After Instruction

REG1

W

C

=

2

?

W

C

=

0

1; result is zero

Before Instruction

After Instruction

W

C

=

3

?

REG1

W

C

=

0

2

1; result is zero

After Instruction

Example 3:

Before Instruction

W

=

0xFF

C

tive

=

0; result is nega-

REG1

W

C

=

1

2

?

After Instruction

REG1

W

C

=

0xFF

2

0; result is negative

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 71

PIC16C62X

SWAPF

Syntax:

Swap Nibbles in f

XORLW

Exclusive OR Literal with W

[ label ] SWAPF f,d

Syntax:

[ label ] XORLW k

0 ≤ k ≤ 255

Operands:

0 ≤ f ≤ 127

Operands:

Operation:

Status Affected:

Encoding:

d

[0,1]

(W) .XOR. k → (W)

Z

Operation:

(f<3:0>) → (dest<7:4>),

(f<7:4>) → (dest<3:0>)

11

1010 kkkk kkkk

Status Affected:

Encoding:

None

The contents of the W register are

XOR’ed with the eight bit literal 'k'.

The result is placed in the

W register.

Description:

00

1110

dfff

ffff

The upper and lower nibbles of

Description:

register 'f' are exchanged. If 'd' is 0

the result is placed in W register. If 'd'

is 1 the result is placed in register 'f'.

Words:

1

Cycles:

Example:

Words:

Cycles:

Example

1

XORLW

0xAF

Before Instruction

SWAPF REG,

0

W

=

0xB5

0x1A

Before Instruction

REG1

After Instruction

=

0xA5

W

=

After Instruction

REG1

W

=

0xA5

0x5A

TRIS

Load TRIS Register

XORWF

Syntax:

Exclusive OR W with f

[ label ] XORWF f,d

0 ≤ f ≤ 127

Syntax:

[ label ] TRIS

f

Operands:

Operation:

5 ≤ f ≤ 7

Operands:

d

[0,1]

(W) → TRIS register f;

Status Affected: None

Operation:

(W) .XOR. (f) → (dest)

00

Encoding:

0000 0110

0fff

Status Affected:

Encoding:

Z

The instruction is supported for code

compatibility with the PIC16C5X

products. Since TRIS registers are

readable and writable, the user can

directly address them.

Description:

00

0110

dfff

ffff

Exclusive OR the contents of the

W register with register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd'

is 1 the result is stored back in register

'f'.

Description:

Words:

Cycles:

Example

1

Words:

Cycles:

Example

1

To maintain upward compatibility

with future PICmicro™ products,

do not use this instruction.

REG

1

XORWF

Before Instruction

REG

W

=

0xAF

0xB5

After Instruction

REG

W

=

0x1A

0xB5

DS30235G-page 72

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

11.3

ICEPIC: Low-Cost PICmicro™

In-Circuit Emulator

11.0 DEVELOPMENT SUPPORT

11.1

Development Tools

ICEPIC is a low-cost in-circuit emulator solution for the

Microchip PIC12CXXX, PIC16C5X and PIC16CXXX

families of 8-bit OTP microcontrollers.

The PICmicrο microcontrollers are supported with a

full range of hardware and software development tools:

• MPLAB™-ICE Real-Time In-Circuit Emulator

ICEPIC is designed to operate on PC-compatible

machines ranging from 386 through Pentium based

machines under Windows 3.x, Windows 95, or Win-

dows NT environment. ICEPIC features real time, non-

intrusive emulation.

• ICEPIC Low-Cost PIC16C5X and PIC16CXXX

In-Circuit Emulator

• PRO MATE II Universal Programmer

• PICSTART Plus Entry-Level Prototype

Programmer

11.4

PRO MATE II: Universal Programmer

• SIMICE

The PRO MATE II Universal Programmer is a full-fea-

tured programmer capable of operating in stand-alone

mode as well as PC-hosted mode. PRO MATE II is CE

compliant.

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• PICDEM-3 Low-Cost Demonstration Board

• MPASM Assembler

The PRO MATE II has programmable VDD and VPP

supplies which allows it to verify programmed memory

at VDD min and VDD max for maximum reliability. It has

an LCD display for displaying error messages, keys to

enter commands and a modular detachable socket

assembly to support various package types. In stand-

alone mode the PRO MATE II can read, verify or pro-

• MPLAB SIM Software Simulator

• MPLAB-C17 (C Compiler)

• Fuzzy Logic Development System

(fuzzyTECH −MP)

®

• KEELOQ Evaluation Kits and Programmer

11.2

MPLAB-ICE: High Performance

Universal In-Circuit Emulator with

MPLAB IDE

gram

PIC12CXXX,

PIC14C000,

PIC16C5X,

PIC16CXXX and PIC17CXX devices. It can also set

conﬁguration and code-protect bits in this mode.

11.5

PICSTART Plus Entry Level

Development System

The MPLAB-ICE Universal In-Circuit Emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for

PICmicro microcontrollers (MCUs). MPLAB-ICE is sup-

plied with the MPLAB Integrated Development Environ-

ment (IDE), which allows editing, “make” and

download, and source debugging from a single envi-

ronment.

The PICSTART programmer is an easy-to-use, low-

cost prototype programmer. It connects to the PC via

one of the COM (RS-232) ports. MPLAB Integrated

Development Environment software makes using the

programmer simple and efﬁcient. PICSTART Plus is

not recommended for production programming.

Interchangeable processor modules allow the system

to be easily reconﬁgured for emulation of different pro-

cessors. The universal architecture of the MPLAB-ICE

allows expansion to support all new Microchip micro-

controllers.

PICSTART Plus supports all PIC12CXXX, PIC14C000,

PIC16C5X, PIC16CXXX and PIC17CXX devices with

up to 40 pins. Larger pin count devices such as the

PIC16C923, PIC16C924 and PIC17C756 may be sup-

ported with an adapter socket. PICSTART Plus is CE

compliant.

The MPLAB-ICE Emulator System has been designed

as a real-time emulation system with advanced fea-

tures that are generally found on more expensive

development tools.The PC compatible 386 (and higher)

machine platform and Microsoft Windows 3.x or

Windows 95 environment were chosen to best make

these features available to you, the end user.

MPLAB-ICE

is

available

in

two

versions.

MPLAB-ICE 1000 is a basic, low-cost emulator system

with simple trace capabilities. It shares processor mod-

ules with the MPLAB-ICE 2000. This is a full-featured

emulator system with enhanced trace, trigger, and data

monitoring features. Both systems will operate across

the entire operating speed reange of the PICmicro

MCU.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 73

PIC16C62X

11.6

SIMICE Entry-Level Hardware

Simulator

11.8

PICDEM-2 Low-Cost PIC16CXX

Demonstration Board

SIMICE is an entry-level hardware development sys-

tem designed to operate in a PC-based environment

with Microchip’s simulator MPLAB™-SIM. Both SIM-

ICE and MPLAB-SIM run under Microchip Technol-

ogy’s MPLAB Integrated Development Environment

(IDE) software. Speciﬁcally, SIMICE provides hardware

simulation for Microchip’s PIC12C5XX, PIC12CE5XX,

and PIC16C5X families of PICmicro™ 8-bit microcon-

trollers. SIMICE works in conjunction with MPLAB-SIM

to provide non-real-time I/O port emulation. SIMICE

enables a developer to run simulator code for driving

the target system. In addition, the target system can

provide input to the simulator code. This capability

allows for simple and interactive debugging without

having to manually generate MPLAB-SIM stimulus

ﬁles. SIMICE is a valuable debugging tool for entry-

level system development.

The PICDEM-2 is a simple demonstration board that

supports the PIC16C62, PIC16C64, PIC16C65,

PIC16C73 and PIC16C74 microcontrollers. All the

necessary hardware and software is included to

run the basic demonstration programs. The user

can program the sample microcontrollers provided

with the PICDEM-2 board, on a PRO MATE II pro-

grammer or PICSTART-Plus, and easily test ﬁrmware.

The MPLAB-ICE emulator may also be used with the

PICDEM-2 board to test ﬁrmware. Additional prototype

area has been provided to the user for adding addi-

tional hardware and connecting it to the microcontroller

socket(s). Some of the features include a RS-232 inter-

face, push-button switches, a potentiometer for simu-

lated analog input, a Serial EEPROM to demonstrate

2

usage of the I C bus and separate headers for connec-

tion to an LCD module and a keypad.

11.7

PICDEM-1 Low-Cost PICmicro

Demonstration Board

11.9

PICDEM-3 Low-Cost PIC16CXXX

Demonstration Board

The PICDEM-1 is a simple board which demonstrates

the capabilities of several of Microchip’s microcontrol-

lers. The microcontrollers supported are: PIC16C5X

(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,

PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and

PIC17C44. All necessary hardware and software is

included to run basic demo programs. The users can

program the sample microcontrollers provided with

the PICDEM-1 board, on a PRO MATE II or

PICSTART-Plus programmer, and easily test ﬁrm-

ware. The user can also connect the PICDEM-1

board to the MPLAB-ICE emulator and download the

ﬁrmware to the emulator for testing. Additional proto-

type area is available for the user to build some addi-

tional hardware and connect it to the microcontroller

socket(s). Some of the features include an RS-232

interface, a potentiometer for simulated analog input,

push-button switches and eight LEDs connected to

PORTB.

The PICDEM-3 is a simple demonstration board that

supports the PIC16C923 and PIC16C924 in the PLCC

package. It will also support future 44-pin PLCC

microcontrollers with a LCD Module. All the neces-

sary hardware and software is included to run the

basic demonstration programs. The user can pro-

gram the sample microcontrollers provided with

the PICDEM-3 board, on a PRO MATE II program-

mer or PICSTART Plus with an adapter socket, and

easily test ﬁrmware. The MPLAB-ICE emulator may

also be used with the PICDEM-3 board to test ﬁrm-

ware. Additional prototype area has been provided to

the user for adding hardware and connecting it to the

microcontroller socket(s). Some of the features include

an RS-232 interface, push-button switches, a potenti-

ometer for simulated analog input, a thermistor and

separate headers for connection to an external LCD

module and a keypad. Also provided on the PICDEM-3

board is an LCD panel, with 4 commons and 12 seg-

ments, that is capable of displaying time, temperature

and day of the week. The PICDEM-3 provides an addi-

tional RS-232 interface and Windows 3.1 software for

showing the demultiplexed LCD signals on a PC. A sim-

ple serial interface allows the user to construct a hard-

ware demultiplexer for the LCD signals.

DS30235G-page 74

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

11.10 MPLAB Integrated Development

Environment Software

11.12 Software Simulator (MPLAB-SIM)

The MPLAB-SIM Software Simulator allows code

development in a PC host environment. It allows the

user to simulate the PICmicro series microcontrollers

on an instruction level. On any given instruction, the

user may examine or modify any of the data areas or

provide external stimulus to any of the pins. The input/

output radix can be set by the user and the execution

can be performed in; single step, execute until break, or

in a trace mode.

The MPLAB IDE Software brings an ease of software

development previously unseen in the 8-bit microcon-

troller market. MPLAB is a windows based application

which contains:

• A full featured editor

• Three operating modes

- editor

- emulator

MPLAB-SIM fully supports symbolic debugging using

MPLAB-C17 and MPASM. The Software Simulator

offers the low cost ﬂexibility to develop and debug code

outside of the laboratory environment making it an

excellent multi-project software development tool.

- simulator

• A project manager

• Customizable tool bar and key mapping

• A status bar with project information

• Extensive on-line help

MPLAB allows you to:

11.13 MPLAB-C17 Compiler

• Edit your source ﬁles (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PICmicro tools (automatically updates all

project information)

• Debug using:

- source ﬁles

The MPLAB-C17 Code Development System is a

complete ANSI ‘C’ compiler and integrated develop-

ment environment for Microchip’s PIC17CXXX family of

microcontrollers. The compiler provides powerful inte-

gration capabilities and ease of use not found with

other compilers.

- absolute listing ﬁle

For easier source level debugging, the compiler pro-

vides symbol information that is compatible with the

MPLAB IDE memory display.

The ability to use MPLAB with Microchip’s simulator

allows a consistent platform and the ability to easily

switch from the low cost simulator to the full featured

emulator with minimal retraining due to development

tools.

11.14 Fuzzy Logic Development System

(fuzzyTECH-MP)

11.11 Assembler (MPASM)

fuzzyTECH-MP fuzzy logic development tool is avail-

able in two versions - a low cost introductory version,

MP Explorer, for designers to gain a comprehensive

working knowledge of fuzzy logic system design; and a

full-featured version, fuzzyTECH-MP, Edition for imple-

menting more complex systems.

The MPASM Universal Macro Assembler is a PC-

hosted symbolic assembler. It supports all microcon-

troller series including the PIC12C5XX, PIC14000,

PIC16C5X, PIC16CXXX, and PIC17CXX families.

MPASM offers full featured Macro capabilities, condi-

tional assembly, and several source and listing formats.

It generates various object code formats to support

Microchip's development tools as well as third party

programmers.

Both versions include Microchip’s fuzzyLAB demon-

stration board for hands-on experience with fuzzy logic

systems implementation.

11.15 SEEVAL Evaluation and

Programming System

MPASM allows full symbolic debugging from MPLAB-

ICE, Microchip’s Universal Emulator System.

The SEEVAL SEEPROM Designer’s Kit supports all

Microchip 2-wire and 3-wire Serial EEPROMs. The kit

includes everything necessary to read, write, erase or

program special features of any Microchip SEEPROM

product including Smart Serials and secure serials.

The Total Endurance Disk is included to aid in trade-

off analysis and reliability calculations. The total kit can

signiﬁcantly reduce time-to-market and result in an

optimized system.

MPASM has the following features to assist in develop-

ing software for speciﬁc use applications.

• Provides translation of Assembler source code to

object code for all Microchip microcontrollers.

• Macro assembly capability.

• Produces all the ﬁles (Object, Listing, Symbol, and

special) required for symbolic debug with

Microchip’s emulator systems.

• Supports Hex (default), Decimal and Octal source

and listing formats.

MPASM provides a rich directive language to support

programming of the PICmicro. Directives are helpful in

making the development of your assemble source code

shorter and more maintainable.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 75

PIC16C62X

11.16 KEELOQ Evaluation and

Programming Tools

KEELOQ evaluation and programming tools support

Microchips HCS Secure Data Products.The HCS eval-

uation kit includes an LCD display to show changing

codes, a decoder to decode transmissions, and a pro-

gramming interface to program test transmitters.

DS30235G-page 76

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

NOTES:

DS30235G-page 78

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

12.0 89ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings †

Ambient Temperature under bias .............................................................................................................. -40° to +125°C

Storage Temperature................................................................................................................................. -65° to +150°C

Voltage on any pin with respect to VSS (except VDD and MCLR)....................................................... -0.6V to VDD +0.6V

Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V

Voltage on MCLR with respect to VSS (Note 2)..................................................................................................0 to +14V

Total power Dissipation (Note 1) ...............................................................................................................................1.0W

Maximum Current out of VSS pin...........................................................................................................................300 mA

Maximum Current into VDD pin .............................................................................................................................250 mA

Input Clamp Current, IIK (VI <0 or VI> VDD)......................................................................................................................±20 mA

Output Clamp Current, IOK (VO <0 or VO>VDD) ...............................................................................................................±20 mA

Maximum Output Current sunk by any I/O pin........................................................................................................25 mA

Maximum Output Current sourced by any I/O pin...................................................................................................25 mA

Maximum Current sunk by PORTA and PORTB ...................................................................................................200 mA

Maximum Current sourced by PORTA and PORTB..............................................................................................200 mA

Note 1: Power dissipation is calculated as follows: P^DIS= VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)

† NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above

those indicated in the operation listings of this speciﬁcation is not implied. Exposure to maximum rating conditions

for extended periods may affect device reliability.

Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.

Thus, a series resistor of 50-100Ω should be used when applying a "low" level to the MCLR pin rather

than pulling this pin directly to VSS.

Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.

Thus, a series resistor of 50-100Ω should be used when applying a "low" level to the MCLR pin rather

than pulling this pin directly to VSS.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 79

PIC16C62X

TABLE 12-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

OSC

PIC16C62X-04

PIC16C62XA-04

PIC16C62X-20

PIC16C62XA-20

PIC16LC62X-04

PIC16C62X/JW

PIC16C62XA/JW

RC

VDD: 3.0V to 6.0V VDD: 3.0V to 5.5V VDD: 3.0V to 6.0V VDD: 3.0V to 5.5V VDD: 3.0V to 6.0V VDD: 3.0V to 6.0V VDD: 3.0V to 5.5V

IDD: 3.3 mA max.

@5.5V

IPD: 20 µA max.

@4.0V

IDD: 3.3 mA max.

@5.5V

IPD: 20 µA max.

@4.0V

IDD: 1.8 mA typ.

@5.5V

IPD: 1.0 µA typ.

@4.5V

IDD: 1.8 mA typ.

@5.5V

IPD: 1.0 µA typ.

@4.5V

IDD: 1.4 mA typ.

@3.0V

IPD: 0.7 µA typ.

@3.0V

IDD: 3.3 mA max. IDD: 3.3 mA max.

@5.5V

IPD: 20 µA max.

@4.0V

@5.5V

IPD: 20 µA max.

@4.0V

Freq: 4.0 MHz

max.

Freq: 4.0 MHz

max.

Freq: 4.0 MHz

max.

Freq: 4.0 MHz

max.

Freq: 4.0 MHz

max.

Freq: 4.0 MHz

max.

Freq: 4.0 MHz

max.

XT

HS

LP

VDD: 3.0V to 6.0V VDD: 3.0V to 5.5V VDD: 3.0V to 6.0V VDD: 3.0V to 5.5V VDD: 3.0V to 6.0V VDD: 3.0V to 6.0V VDD: 3.0V to 5.5V

IDD: 3.3 mA max.

@5.5V

IPD: 20 µA max.

@4.0V

IDD: 3.3 mA max.

@5.5V

IPD: 20 µA max.

@4.0V

IDD: 1.8 mA typ.

@5.5V

IPD: 1.0 µA typ.

@4.5V

IDD: 1.8 mA typ.

@5.5V

IPD: 1.0 µA typ.

@4.5V

IDD: 1.4 mA typ.

@3.0V

IPD: 0.7 µA typ.

@3.0V

IDD: 3.3 mA max. IDD: 3.3 mA max.

@5.5V

IPD: 20 µA max.

@4.0V

@5.5V

IPD: 20 µA max.

@4.0V

Freq: 4.0 MHz

max.

Freq: 4.0 MHz

max.

Freq: 4.0 MHz

max.

Freq: 4.0 MHz

max.

Freq: 4.0 MHz

max.

Freq: 4.0 MHz

max.

Freq: 4.0 MHz

max.

VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V

VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V

IDD: 9.0 mA typ.

@5.5V

IDD: 3.5 mA typ.

@5.5V

IDD: 20 mA max.

@5.5V

IDD: 7.5 mA max.

@5.5V

IDD: 20 mA max.

@5.5V

IDD: 20 mA max.

@5.5V

IPD: 1.0 µA typ.

@4.0V

IPD: 1.0 µA typ.

@4.0V

IPD: 1.0 µA typ.

@4.5V

IPD: 1.0 µA typ.

@4.5V

N/A

IPD: 1.0 µA typ.

@4.5V

IPD: 1.0 µA typ.

@4.5V

Freq: 4.0 MHz

max.

Freq: 4.0 MHz

max.

Freq: 20 MHz

max.

Freq: 20 MHz

max.

Freq: 20 MHz

max.

Freq: 20 MHz

max.

VDD: 3.0V to 6.0V VDD: 3.0V to 5.5V

VDD: 2.5V to 6.0V VDD: 2.5V to 6.0V

VDD: 3.0V to 5.5V

IDD: 32 µA max.

@32 kHz, 3.0V

IPD: 9.0 µA Max.

@3.0V

IDD: 35 µA typ.

@32 kHz,

3.0V

IDD: 35 µA typ.

@32 kHz,

3.0V

IDD: 32 µA max.

@32 kHz,

3.0V

IDD: 32 µA max.

@32 kHz,

3.0V

N/A

IPD: 1.0 µA typ.

@4.0 V

IPD: 1.0 µA typ.

@4.0 V

IPD: 9.0 µA max.

@3.0V

IPD: 9.0 µA Max.

@3.0V

Freq: 200 kHz

max.

Freq: 200 kHz

max.

Freq: 200 kHz

max.

Freq: 200 kHz

max.

Freq: 200 kHz

max.

The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX speciﬁcations. It is recom-

mended that the user select the device type that the speciﬁcations required.

DS30235G-page 80

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

12.1

DC CHARACTERISTICS:

PIC16C62X-04 (Commercial, Industrial, Extended)

PIC16C62X-20 (Commercial, Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature –40°C ≤ TA ≤ +85°C for industrial and

0°C ≤ TA ≤ +70°C for commercial and

–40°C ≤ TA ≤ +125°C for extended

Param

No.

Sym

Characteristic

Min Typ† Max Units

Conditions

D001

D001A

Vdd

Supply Voltage

3.0

4.5

-

6.0

5.5

V

XT, RC and LP osc conﬁguration

HS osc conﬁguration

D002

D003

D004

D005

D010

Vdr

RAM Data Retention

Voltage (Note 1)

–

1.5*

Vss

–

V

Device in SLEEP mode

Vpor

Svdd

VBOR

Idd

VDD start voltage to

ensure Power-on Reset

–

V

See section on power-on reset for details

VDD rise rate to ensure

Power-on Reset

0.05*

V/ms See section on power-on reset for details

Brown-out Detect Voltage

3.7

4.0

4.3

4.4

V

BOREN conﬁguration bit is cleared

(Extended)

Supply Current (Note 2)

–

1.8

3.3

mA

XT and RC osc conﬁguration

FOSC = 4 MHz, VDD = 5.5V, WDT dis-

abled (Note 4)

D010A

–

35

70

µA

LP osc conﬁguration, PIC16C62X-04

only

FOSC = 32 kHz, VDD = 4.0V, WDT dis-

abled

D013

D020

–

9.0

1.0

20

mA

HS osc conﬁguration

FOSC = 20 MHz, VDD = 5.5V, WDT dis-

abled

Ipd

Power Down Current (Note 3)

WDT Current (Note 5)

2.5

15

µA

VDD=4.0V, WDT disabled

(125°C)

∆IWDT

∆IBOR

–

6.0

20

25

µA

VDD=4.0V

(125°C)

BOR enabled, VDD = 5.0V

D023

Brown-out Reset Current (Note 5)

Comparator Current for each Com-

parator (Note 5)

350

425 µA

100 µA

300 µA

∆ICOMP

∆IVREF

VDD = 4.0V

VREF Current (Note 5)

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and

switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-

sumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,

MCLR = VDD; WDT enabled/disabled as speciﬁed.

3: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with

the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.

4: For RC osc conﬁguration, current through Rext is not included. The current through the resistor can be estimated by the

formula Ir = VDD/2Rext (mA) with Rext in kΩ.

5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the

base IDD or IPD measurement.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 81

PIC16C62X

12.2

DC CHARACTERISTICS:

PIC16LC62X-04 (Commercial, Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature –40˚C ≤ TA ≤ +85˚C for industrial and

0˚C ≤ TA ≤ +70˚C for commercial and

–40˚C ≤ TA ≤ +125˚C for extended

Operating voltage VDD range as described in DC spec Table 12-1 and Table 12-2

Param

No.

Sym

Characteristic

Min Typ† Max Units

Conditions

D001

D002

D003

D004

VDD

Supply Voltage

3.0

2.5

-

6.0

V

XT and RC osc conﬁguration

LP osc conﬁguration

VDR

RAM Data Retention

Voltage (Note 1)

–

1.5*

VSS

–

Device in SLEEP mode

VPOR

SVDD

VDD start voltage to

ensure Power-on Reset

–

See section on Power-on Reset for

details

VDD rise rate to ensure

Power-on Reset

0.05*

V/ms See section on Power-on Reset for

details

D005

D010

VBOR

IDD

Brown-out Detect Voltage

Supply Current (Note 2)

3.7

–

4.0

1.4

4.3

2.5

V

BOREN conﬁguration bit is cleared

mA XT and RC osc conﬁguration

FOSC = 2.0 MHz, VDD = 3.0V, WDT dis-

abled (Note 4)

D010A

–

26

53

µA

LP osc conﬁguration

FOSC = 32 kHz, VDD = 3.0V, WDT dis-

abled

D020

D023

IPD

Power Down Current (Note 3)

–

0.7

2

µA

VDD=3.0V, WDT disabled

∆IWDT

∆IBOR

WDT Current (Note 5)

Brown-out Reset Current

(Note 5)

–

6.0

350

15

425

µA

VDD=3.0V

BOR enabled, VDD = 5.0V

∆ICOMP

Comparator Current for each

Comparator (Note 5)

VREF Current (Note 5)

–

100

300

µA

VDD = 3.0V

∆IVREF

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated.These parameters are for design guidance only and are not

tested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and

switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-

sumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,

MCLR = VDD; WDT enabled/disabled as speciﬁed.

3: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the

part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD to VSS.

4: For RC osc conﬁguration, current through Rext is not included. The current through the resistor can be estimated by the

formula Ir = VDD/2Rext (mA) with Rext in kΩ.

5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the

base IDD or IPD measurement.

DS30235G-page 82

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

12.3 DC CHARACTERISTICS: PIC16C62XA/CR62XA-04 (Commercial, Industrial, Extended)

PIC16C62XA/CR62XA-20 (Commercial, Industrial, Extended)

PIC16LC62XA/LCR62XA-04 (Commercial, Industrial)

PIC16LC62XA/LCR62XA-20 (Commercial, Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature –40°C ≤ TA ≤ +85°C for industrial and

0°C ≤ TA ≤ +70°C for commercial and

–40°C ≤ TA ≤ +125°C for extended

Param Sym

No.

Characteristic

Min Typ† Max Units

Conditions

D001

D001A

VDD

Supply Voltage

3.0

4.5

-

5.5

V

XT, RC and LP osc conﬁguration

HS osc conﬁguration

D002

D003

D004

D005

D010

VDR

RAM Data Retention

Voltage (Note 1)

–

1.5*

VSS

–

V

Device in SLEEP mode

VPOR

SVDD

VBOR

IDD

VDD start voltage to

ensure Power-on Reset

–

V

See section on power-on reset for details

VDD rise rate to ensure

Power-on Reset

0.05*

V/ms See section on power-on reset for details

Brown-out Detect Voltage

3.7

4.0

4.3

4.4

V

BOREN conﬁguration bit is cleared

(Extended)

Supply Current (Note 2)

–

1.2

2.0

mA XT and RC osc conﬁguration

FOSC = 4 MHz, VDD = 5.5V, WDT disabled

(Note 4)

D010A

–

35

70

µA

LP osc conﬁguration, PIC16C62XA-04

only

FOSC = 32 kHz, VDD = 4.0V, WDT disabled

HS osc conﬁguration

D013

D020

–

3.0

1.0

7.5

mA FOSC = 20 MHz, VDD = 5.5V, WDT disabled

IPD

Power Down Current (Note 3)

WDT Current (Note 5)

2.5

15

µA

VDD=4.0V, WDT disabled

(125°C)

∆IWDT

∆IBOR

–

6.0

75

60

90

10

12

150

µA

VDD=4.0V

(125°C)

BOR enabled, VDD = 5.0V

D023

Brown-out Reset Current

(Note 5)

Comparator Current for each

Comparator (Note 5)

VREF Current (Note 5)

∆ICOMP

∆IVREF

75

µA

VDD = 4.0V

200

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and

switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-

sumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,

MCLR = VDD; WDT enabled/disabled as speciﬁed.

3: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with

the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.

4: For RC osc conﬁguration, current through Rext is not included. The current through the resistor can be estimated by the

formula Ir = VDD/2Rext (mA) with Rext in kΩ.

5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the

base IDD or IPD measurement.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 83

PIC16C62X

12.4 DC CHARACTERISTICS: PIC16C62X/C62XA/CR62XA (Commercial, Industrial, Extended)

PIC16LC62X/LC62XA/LCR62XA (Commercial, Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature

–40˚C ≤ TA ≤ +85˚C for industrial and

0˚C ≤ TA ≤ +70˚C for commercial and

–40˚C ≤ TA ≤ +125˚C for extended

Operating voltage VDD range as described in DC spec Table 12-1 and Table 12-2

Param. Sym

No.

Characteristic

Min

Typ†

Max

Unit

Conditions

VIL

Input Low Voltage

I/O ports

with TTL buffer

D030

VSS

-

0.8V

V

VDD = 4.5V to 5.5V

otherwise

0.15VDD

0.2VDD

D031

D032

with Schmitt Trigger input

MCLR, RA4/T0CKI,OSC1 (in RC

mode)

VSS

Vss

V

Note1

D033

OSC1 (in XT and HS)

OSC1 (in LP)

Vss

-

0.3VDD

V

0.6VDD-1.0

VIH Input High Voltage

I/O ports

-

D040

with TTL buffer

2.0V

.25VDD + 0.8V

0.8VDD

0.7VDD

0.9VDD

50

VDD

V

VDD = 4.5V to 5.5V

otherwise

D041

D042

D043

D043A

D070

with Schmitt Trigger input

VDD

MCLR RA4/T0CKI

OSC1 (XT, HS and LP)

OSC1 (in RC mode)

-

V

Note1

IPURB PORTB weak pull-up current

Input Leakage Current

200

400

µA VDD = 5.0V, VPIN = VSS

IIL

(Notes 2, 3)

I/O ports (Except PORTA)

PORTA

±1.0

±0.5

±1.0

±5.0

µA VSS ≤ VPIN ≤ VDD, pin at hi-impedance

µA Vss ≤ VPIN ≤ VDD, pin at hi-impedance

µA Vss ≤ VPIN ≤ VDD

D060

D061

D063

-

RA4/T0CKI

OSC1, MCLR

µA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc

conﬁguration

VOL Output Low Voltage

D080

D083

I/O ports

-

0.6

V

IOL=8.5 mA, VDD=4.5V, -40° to +85°C

IOL=7.0 mA, VDD=4.5V, +125°C

IOL=1.6 mA, VDD=4.5V, -40° to +85°C

IOL=1.2 mA, VDD=4.5V, +125°C

OSC2/CLKOUT (RC only)

VOH Output High Voltage (Note 3)

D090

D092

*

I/O ports (Except RA4)

VDD-0.7

-

V

IOH=-3.0 mA, VDD=4.5V, -40° to +85°C

IOH=-2.5 mA, VDD=4.5V, +125°C

IOH=-1.3 mA, VDD=4.5V, -40° to +85°C

IOH=-1.0 mA, VDD=4.5V, +125°C

RA4 pin PIC16C62X, PIC16LC62X

RA4 pin PIC16C62XA, PICLC62XA,

CR62XA, LCR62XA

OSC2/CLKOUT (RC only)

-

Open-Drain High Voltage

10*

VOD

Capacitive Loading Specs on

Output Pins

D100

COSC2 OSC2 pin

15

50

pF In XT, HS and LP modes when external

clock used to drive OSC1.

pF

D101

Cio All I/O pins/OSC2 (in RC mode)

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

In RC oscillator conﬁguration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C62X(A) be driven

with external clock in RC mode.

Note 1:

2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The speciﬁed levels represent normal operat-

ing conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is deﬁned as coming out of the pin.

DS30235G-page 84

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

TABLE 12-2: COMPARATOR SPECIFICATIONS

Operating Conditions: Vdd range as described in Table 12-1, -40°C<TA<+125°C. Current consumption is speciﬁed in

Table 12-1.

Characteristics

Input offset voltage

Sym

Min

Typ

Max

Units

Comments

± 5.0

± 10

mV

V

Input common mode voltage

CMRR

0

VDD - 1.5

+55*

db

(1)

150*

400*

600*

ns

PIC16C62X(A)

PIC16LC62X

Response Time

Comparator Mode Change to

Output Valid

10*

µs

* These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from

V^SSto VDD.

TABLE 12-3: VOLTAGE REFERENCE SPECIFICATIONS

Operating Conditions:Vdd range as described in Table 12-1, -40°C<TA<+125°C. Current consumption is speciﬁed in

Table 12-1.

Characteristics

Resolution

Sym

Min

Typ

Max

Units

Comments

VDD/24

VDD/32

LSB

Absolute Accuracy

+1/4

+1/2

LSB

Low Range (VRR=1)

High Range (VRR=0)

Unit Resistor Value (R)

2K*

Ω

Figure 8-2

(1)

10*

µs

Settling Time

* These parameters are characterized but not tested.

Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 85

PIC16C62X

12.5

Timing Parameter Symbology

The timing parameter symbols have been created with one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase subscripts (pp) and their meanings:

pp

ck

T

Time

CLKOUT

I/O port

MCLR

osc

t0

OSC1

T0CKI

io

mc

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (Hi-impedance)

Low

Valid

L

Hi-Impedance

FIGURE 12-1: LOAD CONDITIONS

Load condition 1

Load condition 2

VDD/2

RL

CL

VSS

RL = 464Ω

CL = 50 pF for all pins except OSC2

15 pF for OSC2 output

DS30235G-page 86

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

12.6

Timing Diagrams and Speciﬁcations

FIGURE 12-2: EXTERNAL CLOCK TIMING

Q4

Q3

Q4

4

Q1

Q2

OSC1

1

3

4

2

CLKOUT

TABLE 12-4: EXTERNAL CLOCK TIMING REQUIREMENTS

Parameter Sym Characteristic

No.

Min

Typ†

Max

Units Conditions

Fos External CLKIN Frequency

DC

0.1

1

—

4

20

MHz XT and RC osc mode, VDD=5.0V

MHz HS osc mode

(Note 1)

—

200

4

kHz LP osc mode

Oscillator Frequency

(Note 1)

—

MHz RC osc mode, VDD=5.0V

MHz XT osc mode

—

4

—

20

MHz HS osc mode

DC

250

50

–

200

—

kHz LP osc mode

1

Tosc External CLKIN Period

—

ns

µs

ns

µs

ns

µs

ns

XT and RC osc mode

HS osc mode

(Note 1)

—

5

—

LP osc mode

Oscillator Period

(Note 1)

250

50

—

RC osc mode

—

10,000

1,000

—

XT osc mode

—

HS osc mode

5

—

LP osc mode

2

TCY

Instruction Cycle Time (Note 1)

1.0

100*

2*

Fosc/4

—

DC

—

TCYS=FOSC/4

3*

TosL, External Clock in (OSC1) High or

TosH Low Time

XT oscillator, TOSC L/H duty cycle

LP oscillator, TOSC L/H duty cycle

—

20*

—

HS oscillator, TOSC L/H duty

cycle

4*

TosR, External Clock in (OSC1) Rise or

TosF Fall Time

25*

50*

15*

—

ns

XT oscillator

LP oscillator

HS oscillator

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All speciﬁed values are

based on characterization data for that particular oscillator type under standard operating conditions with the

device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation

and/or higher than expected current consumption. All devices are tested to operate at "min." values with an

external clock applied to the OSC1 pin.

When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 87

PIC16C62X

FIGURE 12-3: CLKOUT AND I/O TIMING

Q1

Q2

Q3

Q4

OSC1

11

10

22

23

CLKOUT

13

14

12

18

19

16

I/O Pin

(input)

15

17

I/O Pin

new value

old value

(output)

20, 21

Note: All tests must be do with speciﬁed capacitance loads (Figure 12-1) 50 pF on I/O pins and CLKOUT

DS30235G-page 88

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

TABLE 12-5: CLKOUT AND I/O TIMING REQUIREMENTS

Parameter # Sym

Characteristic

Min

Typ†

Max

Units

Conditions

(1)

10*

TosH2ckL

—

75

—

200

400

ns

PIC16C62X(A)

PIC16LC62X(A)

PIC16CR62XA

PIC16LCR62XA

OSC1↑ to CLKOUT↓

(1)

11*

TosH2ckH

TckR

—

75

—

ns

OSC1↑ to CLKOUT↑

200

400

PIC16C62X(A)

PIC16LC62X(A)

PIC16CR62XA

PIC16LCR62XA

(1)

12*

13*

—

35

—

100

200

ns

CLKOUT rise time

CLKOUT fall time

PIC16C62X(A)

PIC16LC62X(A)

PIC16CR62XA

PIC16LCR62XA

(1)

TckF

—

35

—

100

200

ns

PIC16C62X(A)

PIC16LC62X(A)

PIC16CR62XA

PIC16LCR62XA

(1)

14*

15*

TckL2ioV

TioV2ckH

—

20

ns

CLKOUT ↓ to Port out valid

Port in valid before CLKOUT ↑

(1)

Tosc +200 ns

Tosc +400 ns

—

ns

PIC16C62X(A)

PIC16LC62X(A)

PIC16CR62XA

PIC16LCR62XA

(1)

16*

17*

TckH2ioI

TosH2ioV

0

—

ns

Port in hold after CLKOUT ↑

OSC1↑ (Q1 cycle) to Port out valid

—

50

150

300

ns

PIC16C62X(A)

PIC16LC62X(A)

PIC16CR62XA

PIC16LCR62XA

18*

TosH2ioI

OSC1↑ (Q2 cycle) to Port input invalid

(I/O in hold time)

100

200

—

ns

PIC16C62X(A)

PIC16LC62X(A)

PIC16CR62XA

PIC16LCR62XA

19*

20*

TioV2osH Port input valid to OSC1↑ (I/O in setup

0

—

ns

time)

TioR

TioF

Tinp

Trbp

Port output rise time

—

10

—

40

80

ns

PIC16C62X(A)

PIC16LC62X(A)

PIC16CR62XA

PIC16LCR62XA

21*

22*

23

Port output fall time

—

10

—

40

80

ns

PIC16C62X(A)

PIC16LC62X(A)

PIC16CR62XA

PIC16LCR62XA

RB0/INT pin high or low time

RB<7:4> change interrupt high or low time

25

40

—

ns

PIC16C62X(A)

PIC16LC62X(A)

PIC16CR62XA

PIC16LCR62XA

TCY

—

ns

*

†

These parameters are characterized but not tested

Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 89

PIC16C62X

FIGURE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

VDD

MCLR

30

Internal

POR

33

PWRT

Timeout

32

OSC

Timeout

Internal

RESET

Watchdog

Timer

RESET

31

34

I/O Pins

FIGURE 12-5: BROWN-OUT RESET TIMING

BVDD

VDD

35

TABLE 12-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER REQUIREMENTS

Parameter

No.

Sym

Characteristic

Min

Typ†

Max Units

Conditions

30

31

TmcL MCLR Pulse Width (low)

2000

7*

—

ns

-40° to +85°C

Twdt

Watchdog Timer Time-out Period

18

33*

ms

VDD = 5.0V, -40° to +85°C

(No Prescaler)

32

33

34

35

Tost

Oscillation Start-up Timer Period

—

1024 TOSC

—

132*

2.0

—

ms

µs

TOSC = OSC1 period

Tpwrt Power-up Timer Period

28*

72

—

VDD = 5.0V, -40° to +85°C

TIOZ

I/O hi-impedance from MCLR low

Brown-out Reset Pulse Width

TBOR

100*

µs 3.7V ≤ VDD ≤ 4.3V

*

†

These parameters are characterized but not tested.

Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

DS30235G-page 90

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

FIGURE 12-6: TIMER0 CLOCK TIMING

RA4/T0CKI

41

40

42

TMR0

TABLE 12-7: TIMER0 CLOCK REQUIREMENTS

Parameter Sym Characteristic

No.

Min

Typ† Max Units Conditions

40

41

42

Tt0H T0CKI High Pulse Width

Tt0L T0CKI Low Pulse Width

Tt0P T0CKI Period

No Prescaler

0.5 TCY + 20*

10*

—

ns

With Prescaler

No Prescaler

With Prescaler

0.5 TCY + 20*

10*

TCY + 40*

N

N = prescale value

(1, 2, 4, ..., 256)

*

†

These parameters are characterized but not tested.

Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

FIGURE 12-7: LOAD CONDITIONS

Load condition 1

Load condition 2

VDD/2

RL

CL

VSS

RL = 464Ω

CL = 50 pF for all pins except OSC2

15 pF for OSC2 output

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 91

PIC16C62X

NOTES:

DS30235G-page 92

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

13.0 DEVICE CHARACTERIZATION

INFORMATION

Not Available at this time.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 93

PIC16C62X

NOTES:

DS30235G-page 94

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

14.0 PACKAGING INFORMATION

Package Type: K04-010 18-Lead Ceramic Dual In-line with Window (JW) – 300 mil

E

D

W2

2

1

n

W1

E1

A

A1

R

L

c

A2

B1

eB

p

B

Units

Dimension Limits

PCB Row Spacing

Number of Pins

Pitch

Lower Lead Width

Upper Lead Width

Shoulder Radius

Lead Thickness

Top to Seating Plane

Top of Lead to Seating Plane

Base to Seating Plane

Tip to Seating Plane

Package Length

INCHES*

NOM

0.300

18

MILLIMETERS

MIN

MAX

MIN

NOM

7.62

18

MAX

n

p

B

B1

R

c

A

A1

A2

L

D

E

E1

eB

W1

W2

0.098

0.100

0.019

0.055

0.013

0.010

0.183

0.111

0.023

0.138

0.900

0.298

0.270

0.385

0.140

0.200

0.102

2.49

0.41

2.54

0.47

1.40

0.32

0.25

4.64

2.82

0.57

3.49

22.86

7.56

6.86

9.78

0.14

0.2

2.59

0.016

0.050

0.010

0.008

0.175

0.091

0.015

0.125

0.880

0.285

0.255

0.345

0.130

0.190

0.021

0.060

0.015

0.012

0.190

0.131

0.030

0.150

0.920

0.310

0.285

0.425

0.150

0.210

0.53

1.52

0.38

0.30

4.83

3.33

0.76

3.81

23.37

7.87

7.24

10.80

0.15

0.21

1.27

0.25

0.20

4.45

2.31

0.00

3.18

22.35

7.24

6.48

8.76

0.13

0.19

Package Width

Radius to Radius Width

Overall Row Spacing

Window Width

Window Length

* Controlling Parameter.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 95

PIC16C62X

Package Type: K04-007 18-Lead Plastic Dual In-line (P) – 300 mil

E

D

2

α

n

1

E1

A1

L

A

R

c

A2

B1

β

p

B

eB

Units

INCHES*

NOM

0.300

18

MILLIMETERS

Dimension Limits

PCB Row Spacing

Number of Pins

Pitch

Lower Lead Width

Upper Lead Width

Shoulder Radius

Lead Thickness

Top to Seating Plane

Top of Lead to Seating Plane

Base to Seating Plane

Tip to Seating Plane

Package Length

Molded Package Width

Radius to Radius Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

MIN

MAX

MIN

NOM

7.62

18

MAX

n

p

B

B1

R

c

A

A1

A2

L

D

E

E1

eB

α

0.100

0.018

0.060

0.005

0.010

0.155

0.095

0.020

0.130

0.895

0.255

0.250

0.349

10

2.54

0.013

0.023

0.33

1.40

0.46

1.52

0.13

0.25

3.94

2.41

0.51

3.30

22.73

6.48

6.35

8.85

10

0.58

†

0.055

0.000

0.005

0.110

0.075

0.000

0.125

0.890

0.245

0.230

0.310

5

0.065

0.010

0.015

0.155

0.115

0.020

0.135

0.900

0.265

0.270

0.387

15

1.65

0.25

0.38

3.94

2.92

0.51

3.43

22.86

6.73

6.86

9.83

15

0.00

0.13

2.79

1.91

0.00

3.18

22.61

6.22

5.84

7.87

5

‡

β

5

10

15

5

10

15

* Controlling Parameter.

†

Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”

(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”

‡

Dimensions “D” and “E” do not include mold ﬂash or protrusions. Mold ﬂash or protrusions shall not

exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

DS30235G-page 96

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

Package Type: K04-051 18-Lead Plastic Small Outline (SO) – Wide, 300 mil

E1

E

p

D

2

1

B

n

X

α

45°

L

R2

c

A

A1

R1

φ

β

L1

A2

Units

Dimension Limits

Pitch

INCHES*

NOM

0.050

18

MILLIMETERS

MIN

MAX

MIN

NOM

1.27

18

MAX

p

n

A

A1

A2

Number of Pins

Overall Pack. Height

Shoulder Height

Standoff

Molded Package Length

Molded Package Width

Outside Dimension

Chamfer Distance

Shoulder Radius

Gull Wing Radius

Foot Length

0.093

0.099

0.058

0.008

0.456

0.296

0.407

0.020

0.005

0.016

4

0.104

2.36

1.22

2.50

1.47

0.19

11.58

7.51

10.33

0.50

0.13

0.41

4

2.64

1.73

0.28

11.73

7.59

10.64

0.74

0.25

0.53

8

0.048

0.004

0.450

0.292

0.394

0.010

0.005

0.011

0

0.068

0.011

0.462

0.299

0.419

0.029

0.010

0.021

8

0.10

11.43

7.42

10.01

0.25

0.13

0.28

0

‡

D

E

‡

E1

X

R1

R2

L

Foot Angle

φ

Radius Centerline

Lead Thickness

Lower Lead Width

Mold Draft Angle Top

Mold Draft Angle Bottom

*

L1

c

B

α

β

0.010

0.009

0.014

0

0.015

0.011

0.017

12

0.020

0.012

0.019

15

0.25

0.23

0.36

0

0.38

0.27

0.42

12

0.51

0.30

0.48

15

†

0

12

15

0

12

15

Controlling Parameter.

†

Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”

(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”

‡

Dimensions “D” and “E” do not include mold ﬂash or protrusions. Mold ﬂash or protrusions shall not

exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 97

PIC16C62X

Package Type: K04-072 20-Lead Plastic Shrink Small Outine (SS) – 5.30 mm

E1

E

p

D

B

2

n

1

α

L

R2

c

A

A1

R1

φ

L1

A2

β

Units

Dimension Limits

Pitch

INCHES

NOM

0.026

MILLIMETERS*

MIN

MAX

MIN

NOM

0.65

20

MAX

p

n

A

A1

A2

D

E

E1

R1

R2

L

Number of Pins

Overall Pack. Height

Shoulder Height

Standoff

Molded Package Length

Molded Package Width

Outside Dimension

Shoulder Radius

Gull Wing Radius

Foot Length

20

0.073

0.036

0.005

0.283

0.208

0.306

0.005

0.020

4

0.068

0.078

1.73

0.66

1.86

0.91

0.13

7.20

5.29

7.78

0.13

0.51

4

1.99

0.026

0.002

0.278

0.205

0.301

0.005

0.015

0

0.046

0.008

0.289

0.212

0.311

0.010

0.025

8

1.17

0.21

7.33

5.38

7.90

0.25

0.64

8

0.05

7.07

5.20

7.65

0.13

0.38

0

‡

Foot Angle

φ

Radius Centerline

Lead Thickness

Lower Lead Width

Mold Draft Angle Top

L1

c

B

α

β

0.000

0.005

0.010

0

0.005

0.007

0.012

5

0.010

0.009

0.015

10

0.00

0.13

0.25

0

0.13

0.18

0.32

5

0.25

0.22

0.38

10

†

Mold Draft Angle Bottom

0

5

10

0

5

10

*

Controlling Parameter.

†

‡

Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”

(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”

Dimensions “D” and “E” do not include mold ﬂash or protrusions. Mold ﬂash or protrusions shall not

exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

DS30235G-page 98

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

14.1

Package Marking Information

18-Lead PDIP

Example

XXXXXXXXXXXXXXXXX

PIC16C622A

-04I / P456

9823 CBA

AABBCDE

18-Lead SOIC (.300")

Example

XXXXXXXXXXXX

PIC16C622

-04I / S0218

AABBCDE

9818 CDK

18-Lead CERDIP Windowed

Example

XXXXXXXX

AABBCDE

16C622

/JW

9801 CBA

20-Lead SSOP

Example

XXXXXXXXXX

AABBCDE

PIC16C622A

-04I / 218

9851 CBP

Legend: MM...M Microchip part number information

XX...X Customer speciﬁc information*

AA

BB

C

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Facility code of the plant at which wafer is manufactured

O = Outside Vendor

C = 5” Line

S = 6” Line

H = 8” Line

D

E

Mask revision number

Assembly code of the plant or country of origin in which

part was assembled

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line thus limiting the number of available characters

for customer speciﬁc information.

*

Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask

rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with

your Microchip Sales Ofﬁce. For QTP devices, any special marking adders are included in QTP price.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 99

PIC16C62X

NOTES:

DS30235G-page 100

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

APPENDIX A: ENHANCEMENTS

APPENDIX B: COMPATIBILITY

The following are the list of enhancements over the

PIC16C5X microcontroller family:

To convert code written for PIC16C5X to PIC16CXX,

the user should take the following steps:

1. Instruction word length is increased to 14 bits.

This allows larger page sizes both in program

memory (4K now as opposed to 512 before) and

register ﬁle (up to 128 bytes now versus 32

bytes before).

1. Remove any program memory page select

operations (PA2, PA1, PA0 bits) for CALL, GOTO.

2. Revisit any computed jump operations (write to

PC or add to PC, etc.) to make sure page bits

are set properly under the new scheme.

2. A PC high latch register (PCLATH) is added to

handle program memory paging. PA2, PA1, PA0

bits are removed from STATUS register.

3. Eliminate any data memory page switching.

Redeﬁne data variables to reallocate them.

4. Verify all writes to STATUS, OPTION, and FSR

registers since these have changed.

3. Data memory paging is slightly redeﬁned.

STATUS register is modiﬁed.

5. Change reset vector to 0000h.

4. Four new instructions have been added:

RETURN, RETFIE, ADDLW, and SUBLW.

Two instructions TRIS and OPTION are being

phased out although they are kept for

compatibility with PIC16C5X.

5. OPTION and TRIS registers are made

addressable.

6. Interrupt capability is added. Interrupt vector is

at 0004h.

7. Stack size is increased to 8 deep.

8. Reset vector is changed to 0000h.

9. Reset of all registers is revisited. Five different

reset (and wake-up) types are recognized.

Registers are reset differently.

10. Wake up from SLEEP through interrupt is

added.

11. Two separate timers, Oscillator Start-up Timer

(OST) and Power-up Timer (PWRT) are

included for more reliable power-up. These

timers are invoked selectively to avoid

unnecessary delays on power-up and wake-up.

12. PORTB has weak pull-ups and interrupt on

change feature.

13. Timer0 clock input, T0CKI pin is also a port pin

(RA4/T0CKI) and has a TRIS bit.

14. FSR is made a full 8-bit register.

15. “In-circuit programming” is made possible. The

user can program PIC16CXX devices using only

ﬁve pins: VDD, VSS, /VPP, RB6 (clock) and RB7

(data in/out).

16. PCON status register is added with

Power-on-Reset (POR) status bit and

Brown-out Reset status bit (BOR).

a

17. Code protection scheme is enhanced such that

portions of the program memory can be

protected, while the remainder is unprotected.

18. PORTA inputs are now Schmitt Trigger inputs.

19. Brown-out Reset reset has been added.

20. Common RAM registers F0h-FFh implemented

in bank1.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 101

PIC16C62X

APPENDIX C: WHAT’S NEW

APPENDIX D: WHAT’S CHANGED

1. Table 3-1 was changed to reﬂect the TTL input

buffers on PORTB.

The format of certain sections of this data sheet have

been changed to be consistent with other product

families.

2. Figure 5-5 and Figure 5-6 were updated to

reﬂect the TTL input buffers on PORTB.

1. PORTB input buffers have changed to TTL from

Schmitt Trigger.

3. Figure 9-7 was updated.

4. The orientation of the diode in Figure 9-19 was

changed.

5. A device speciﬁcation for JW devices was added

to Table 12-1.

6. Max spec for Brown-out Reset current was

changed to 15 µA in Section 12.1 and

Section 12.2.

7. Information added to support the 2.5V "LC"

devices.

8. Information added to support the "A" version of

the devices.

DS30235G-page 102

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

Instruction Set

INDEX

A

ADDLW....................................................................... 63

ADDWF ...................................................................... 63

ANDLW....................................................................... 63

ANDWF ...................................................................... 63

BCF ............................................................................ 64

BSF............................................................................. 64

BTFSC........................................................................ 64

BTFSS........................................................................ 65

CALL........................................................................... 65

CLRF .......................................................................... 65

CLRW......................................................................... 65

CLRWDT .................................................................... 66

COMF......................................................................... 66

DECF.......................................................................... 66

DECFSZ ..................................................................... 66

GOTO......................................................................... 67

INCF ........................................................................... 67

INCFSZ....................................................................... 67

IORLW........................................................................ 67

IORWF........................................................................ 68

MOVF ......................................................................... 68

MOVLW...................................................................... 68

MOVWF...................................................................... 68

NOP............................................................................ 69

OPTION...................................................................... 69

RETFIE....................................................................... 69

RETLW....................................................................... 69

RETURN..................................................................... 70

RLF............................................................................. 70

RRF ............................................................................ 70

SLEEP........................................................................ 70

SUBLW....................................................................... 71

SUBWF....................................................................... 71

SWAPF....................................................................... 72

TRIS ........................................................................... 72

XORLW ...................................................................... 72

XORWF ...................................................................... 72

Instruction Set Summary .................................................... 61

INT Interrupt ....................................................................... 56

INTCON Register ............................................................... 20

Interrupts ............................................................................ 55

IORLW Instruction .............................................................. 67

IORWF Instruction.............................................................. 68

ADDLW Instruction ............................................................. 63

ADDWF Instruction ............................................................. 63

ANDLW Instruction ............................................................. 63

ANDWF Instruction ............................................................. 63

Architectural Overview.......................................................... 9

Assembler

MPASM Assembler..................................................... 75

B

BCF Instruction ................................................................... 64

Block Diagram

TIMER0....................................................................... 31

TMR0/WDT PRESCALER .......................................... 34

Brown-Out Detect (BOD) .................................................... 50

BSF Instruction ................................................................... 64

BTFSC Instruction............................................................... 64

BTFSS Instruction............................................................... 65

C

CALL Instruction ................................................................. 65

Clocking Scheme/Instruction Cycle .................................... 12

CLRF Instruction................................................................. 65

CLRW Instruction................................................................ 65

CLRWDT Instruction........................................................... 66

CMCON Register................................................................ 37

Code Protection .................................................................. 60

COMF Instruction................................................................ 66

Comparator Configuration................................................... 38

Comparator Interrupts......................................................... 41

Comparator Module ............................................................ 37

Comparator Operation ........................................................ 39

Comparator Reference ....................................................... 39

Configuration Bits................................................................ 46

Configuring the Voltage Reference..................................... 43

Crystal Operation................................................................ 47

D

Data Memory Organization................................................. 14

DECF Instruction................................................................. 66

DECFSZ Instruction............................................................ 66

Development Support ......................................................... 73

Development Tools............................................................. 73

E

K

Errata .................................................................................... 3

External Crystal Oscillator Circuit ....................................... 48

KeeLoq Evaluation and Programming Tools ................... 76

M

F

MOVF Instruction................................................................ 68

MOVLW Instruction ............................................................ 68

MOVWF Instruction ............................................................ 68

MPLAB Integrated Development Environment

Fuzzy Logic Dev. System (fuzzyTECH -MP) .................... 75

G

General purpose Register File............................................ 14

GOTO Instruction................................................................ 67

Software ............................................................................. 75

I

N

I/O Ports.............................................................................. 25

I/O Programming Considerations........................................ 30

ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ............ 73

ID Locations........................................................................ 60

INCF Instruction.................................................................. 67

INCFSZ Instruction ............................................................. 67

In-Circuit Serial Programming............................................. 60

Indirect Addressing, INDF and FSR Registers ................... 24

Instruction Flow/Pipelining .................................................. 12

NOP Instruction .................................................................. 69

O

One-Time-Programmable (OTP) Devices .............................7

OPTION Instruction ............................................................ 69

OPTION Register ............................................................... 19

Oscillator Configurations .................................................... 47

Oscillator Start-up Timer (OST).......................................... 50

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 103

PIC16C62X

P

V

Package Marking Information .............................................99

Packaging Information ........................................................95

PCL and PCLATH...............................................................23

PCON Register ...................................................................22

PICDEM-1 Low-Cost PICmicro Demo Board......................74

PICDEM-2 Low-Cost PIC16CXX Demo Board ...................74

PICDEM-3 Low-Cost PIC16CXXX Demo Board.................74

PICSTART Plus Entry Level Development System .........73

PIE1 Register......................................................................21

Pinout Description...............................................................11

PIR1 Register......................................................................21

Port RB Interrupt .................................................................56

PORTA................................................................................25

PORTB................................................................................28

Power Control/Status Register (PCON)..............................51

Power-Down Mode (SLEEP)...............................................59

Power-On Reset (POR) ......................................................50

Power-up Timer (PWRT).....................................................50

Prescaler.............................................................................34

PRO MATE II Universal Programmer...............................73

Program Memory Organization...........................................13

Voltage Reference Module ................................................. 43

VRCON Register ................................................................ 43

W

Watchdog Timer (WDT)...................................................... 57

WWW, On-Line Support ....................................................... 3

X

XORLW Instruction............................................................. 72

XORWF Instruction............................................................. 72

Q

Quick-Turnaround-Production (QTP) Devices ......................7

R

RC Oscillator.......................................................................48

Reset...................................................................................49

RETFIE Instruction..............................................................69

RETLW Instruction..............................................................69

RETURN Instruction............................................................70

RLF Instruction....................................................................70

RRF Instruction ...................................................................70

S

SEEVAL Evaluation and Programming System...............75

Serialized Quick-Turnaround-Production

(SQTP) Devices ....................................................................7

SLEEP Instruction...............................................................70

Software Simulator (MPLAB-SIM).......................................75

Special Features of the CPU...............................................45

Special Function Registers .................................................17

Stack ...................................................................................23

Status Register....................................................................18

SUBLW Instruction..............................................................71

SUBWF Instruction..............................................................71

SWAPF Instruction..............................................................72

T

Timer0

TIMER0.......................................................................31

TIMER0 (TMR0) Interrupt ...........................................31

TIMER0 (TMR0) Module.............................................31

TMR0 with External Clock...........................................33

Timer1

Switching Prescaler Assignment.................................35

Timing Diagrams and Specifications...................................87

TMR0 Interrupt....................................................................56

TRIS Instruction ..................................................................72

TRISA..................................................................................25

TRISB..................................................................................28

DS30235G-page 104

Preliminary

1998 Microchip Technology Inc.

PIC16C62X

Systems Information and Upgrade Hot Line

ON-LINE SUPPORT

The Systems Information and Upgrade Line provides

system users a listing of the latest versions of all of

Microchip's development systems software products.

Plus, this line provides information on how customers

can receive any currently available upgrade kits.The

Hot Line Numbers are:

Microchip provides on-line support on the Microchip

World Wide Web (WWW) site.

The web site is used by Microchip as a means to make

ﬁles and information easily available to customers. To

view the site, the user must have access to the Internet

and a web browser, such as Netscape or Microsoft

Explorer. Files are also available for FTP download

from our FTP site.

1-800-755-2345 for U.S. and most of Canada, and

1-602-786-7302 for the rest of the world.

980106

ConnectingtotheMicrochipInternetWebSite

The Microchip web site is available by using your

favorite Internet browser to attach to:

www.microchip.com

The ﬁle transfer site is available by using an FTP ser-

vice to connect to:

ftp://ftp.futureone.com/pub/microchip

The web site and ﬁle transfer site provide a variety of

services. Users may download ﬁles for the latest

Development Tools, Data Sheets, Application Notes,

User's Guides, Articles and Sample Programs. A vari-

ety of Microchip speciﬁc business information is also

available, including listings of Microchip sales ofﬁces,

distributors and factory representatives. Other data

available for consideration is:

Trademarks: The Microchip name, logo, PIC, PICSTART,

PICMASTER and PRO MATE are registered trademarks

of Microchip Technology Incorporated in the U.S.A. and

other countries. PICmicro, FlexROM, MPLAB and fuzzy-

LAB are trademarks and SQTP is a service mark of Micro-

chip in the U.S.A.

• Latest Microchip Press Releases

• Technical Support Section with Frequently Asked

Questions

• Design Tips

• Device Errata

All other trademarks mentioned herein are the property of

their respective companies.

• Job Postings

• Microchip Consultant Program Member Listing

• Links to other useful web sites related to

Microchip Products

• Conferences for products, Development Systems,

technical information and more

• Listing of seminars and events

1998 Microchip Technology Inc.

DS30235G-page 105

PIC16C62X

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.

Please list the following information, and use this outline to provide us with your comments about this Data Sheet.

To:

Technical Publications Manager

Reader Response

Total Pages Sent

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

Literature Number:

DS30235G

Device:

PIC16C62X

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you ﬁnd the organization of this data sheet easy to follow? If not, why?

4. What additions to the data sheet do you think would enhance the structure and subject?

5. What deletions from the data sheet could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

8. How would you improve our software, systems, and silicon products?

DS30235G-page 106

1998 Microchip Technology Inc.

PIC16C62X

PIC16C62X PRODUCT IDENTIFICATION SYSTEM

To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed

sales ofﬁces.

PART NO. -XX X /XX XXX

Pattern:

3-Digit Pattern Code for QTP (blank otherwise)

Package:

P

=

PDIP

SO

SS

JW*

SOIC (Gull Wing, 300 mil body)

SSOP (209 mil)

Examples:

Windowed CERDIP

g) PIC16C621A - 04/P 301 =

Commercial temp., PDIP pack-

age, 4 MHz, normal VDD limits,

QTP pattern #301.

h) PIC16LC622- 04I/SO =

Industrial temp., SOIC pack-

age, 200kHz, extended VDD

limits.

Temperature -

=

0˚C to +70˚C

Range:

I

–40˚C to +85˚C

–40˚C to +125˚C

E

Frequency 04

=

200kHz (LP osc)

4 MHz (XT and RC osc)

20 MHz (HS osc)

Range:

04

20

Device:

PIC16C62X :VDD range 3.0V to 6.0V

PIC16C62XT:VDD range 3.0V to 6.0V (Tape and Reel)

PIC16C62XA: VDD range 3.0V to 5.5V

PIC16C62XAT: VDD range 3.0V to 5.5V (Tape and Reel)

PIC16LC62X:VDD range 2.5V to 6.0V

PIC16LC62XT:VDD range 2.5V to 6.0V (Tape and Reel)

PIC16LC62XA:VDD range 2.5V to 5.5V

PIC16LC62XAT:VDD range 2.5V to 5.5V (Tape and Reel)

PIC16CR620A: VDD range 2.5V to 5.5V

PIC16CR620AT: VDD range 2.5V to 5.5V (Tape and Reel)

PIC16LCR620A: VDD range 2.0V to 5.5V

PIC16LCR620AT: Vdd range 2.0V to 5.5V (Tape and Reel)

PIC16CR620T: VDD range 3.0V to 5.5V (Tape and Reel)

* JW Devices are UV erasable and can be programmed to any device conﬁguration. JW Devices meet the electrical requirement of

each oscillator type (including LC devices).

Sales and Support

Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and

recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1.

2.

Your local Microchip sales ofﬁce.

The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.

1998 Microchip Technology Inc.

Preliminary

DS30235G-page 107


型号：	PIC16CR620A-20E/P301
厂家：	MICROCHIP
描述：	8-BIT, MROM, 20 MHz, RISC MICROCONTROLLER, PDIP18, 0.300 INCH, PLASTIC, DIP-18 时钟光电二极管外围集成电路
文件：	总108页 (文件大小：674K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC16CR620A-20E/P301 [MICROCHIP]

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