PIC16F18324T-I/ML [MICROCHIP]
IC MCU 8BIT 7KB FLASH 16QFN;型号: | PIC16F18324T-I/ML |
厂家: | MICROCHIP |
描述: | IC MCU 8BIT 7KB FLASH 16QFN |
文件: | 总23页 (文件大小:236K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PIC16(L)F183XX
Full-Featured, Low Pin Count Microcontrollers with XLP Product Brief
Description
PIC16(L)F183XX microcontrollers feature Analog, Core Independent Peripherals and communication peripherals,
combined with eXtreme Low Power (XLP) for a wide range of general purpose and low-power applications. The
Peripheral Pin Select (PPS) functionality enables pin mapping when using the digital peripherals (CLC, CWG, CCP,
PWM and communications) to add flexibility to the application design.
Core Features
Power-Saving Functionality
• C Compiler Optimized RISC Architecture
• Only 49 Instructions
• Operating Speed:
• Doze mode: Ability to run the CPU core slower
than the system clock used by the internal
peripherals
- DC – 32 MHz clock input
- 125 ns minimum instruction cycle
• Interrupt Capability
• Idle mode: Ability to put the CPU core to sleep
while internal peripherals continue operating from
the system clock
• 16-Level Deep Hardware Stack
• Up to Four 8-Bit Timers
• Up to Three 16-Bit Timers
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRTE)
• Brown-out Reset (BOR) with Fast Recovery
• Low-Power BOR (LPBOR) Option
• Extended Watchdog Timer (WDT) with Dedicated
On-Chip Oscillator for Reliable Operation
• Programmable Code Protection
• Sleep mode: Lowest Power Consumption
• Peripheral Module Disable: Peripheral power
disable hardware module to minimize power
consumption of unused peripherals
Digital Peripherals
• Configurable Logic Cell (CLC):
- Up to four CLCs
- Integrated combinational and sequential logic
• Complementary Waveform Generator (CWG):
- Rising and falling edge dead-band control
- Full-bridge, half-bridge, 1-channel drive
- Up to two CWGs
Memory
• Up to 28 KB Program Flash Memory (PFM)
• Up to 2 KB Data SRAM Memory
- Multiple signal sources
• 256B of EEPROM Data Flash Memory (DFM)
• Direct, Indirect and Relative Addressing modes
• Up to Four Capture/Compare/PWM (CCP)
modules
• PWM: Two 10-bit Pulse-Width Modulators
• Numerically Controlled Oscillator (NCO):
- Precision linear frequency generator (@50%
duty cycle) with 0.0001% step size of source
input clock
Operating Characteristics
• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF183XX)
- 2.3V to 5.5V (PIC16F183XX)
• Temperature Range:
- Input Clock: 0 Hz < FNCO < 32 MHz
- Resolution: FNCO/220
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
• Serial Communications:
- SPI, I2C, EUSART
- RS-232, RS-485, LIN compatible
• Data Signal Modulator (DSM):
- Modulates a carrier signal with digital data to
create custom carrier synchronized output
waveforms
eXtreme Low-Power (XLP) Features
• Sleep mode: 40 nA @ 1.8V, typical
• Watchdog Timer: 250 nA @ 1.8V, typical
• Secondary Oscillator: 300 nA @ 32 kHz
• Operating Current:
- 8 uA @ 32 kHz, 1.8V, typical
- 37 uA/MHz @ 1.8V, typical
2014-2016 Microchip Technology Inc.
DS40001744C-page 1
PIC16(L)F183XX
• Peripheral Pin Select (PPS):
- I/O pin remapping of digital peripherals
• Up to 18 I/O Pins:
- Individually programmable pull ups
- Slew rate control
- Interrupt-on-change with edge-select
- Input level selection control (ST or TTL)
- Digital open-drain enable
Clocking Structure
• High-Precision Internal Oscillator:
- Selectable frequency range up to 32 MHz
• x2/x4 PLL with Internal and External Sources
• Low-Power Internal 32 kHz Oscillator
(LFINTOSC)
• External 32 kHz Crystal Oscillator (SOCS)
• External High-Speed Crystal Oscillators
Analog Peripherals
• 10-Bit Analog-to-Digital Converter (ADC):
- Up to 17 external channels
- Conversion available during Sleep
• Comparator:
- Up to two comparators
- Low and High-Speed modes
- Fixed Voltage Reference at inverting/
noninverting input(s)
- Comparator outputs externally accessible
• 5-Bit Digital-to-Analog Converter (DAC):
- 5-bit resolution, rail-to-rail
- Positive Reference Selection
- Unbuffered I/O pin output
- Internal connections to ADCs and
comparators
• Voltage Reference:
- Fixed Voltage Reference with 1.024V, 2.048V
and 4.096V output levels
DS40001744C-page 2
2014-2016 Microchip Technology Inc.
TABLE 1:
PIC16(L)F183XX Family Types
Device
PIC16(L)F18313
PIC16(L)F18323
PIC16(L)F18324
PIC16(L)F18325
PIC16(L)F18326
PIC16(L)F18344
PIC16(L)F18345
PIC16(L)F18346
(A)
(A)
(B)
(C)
(D)
(B)
(C)
(D)
3.5
3.5
7
2
2
256
256
256
256
256
256
256
256
256
256
512
1K
6
5
1
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1/1/1 2/2
1/1/1 2/2
1/3/3 4/2
1/3/3 4/2
1/3/3 4/2
1/3/3 4/2
1/3/3 4/2
1/3/3 4/2
1
1
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
2
2
1
2
2
1
1
1
2
2
1
2
2
2
2
4
4
4
4
4
4
1
1
1
1
1
1
1
1
Y
Y
Y
Y
Y
Y
Y
Y
I
I
I
I
I
I
I
I
12
12
12
12
18
18
18
11
11
11
11
17
17
17
4
14
28
7
8
16
4
2K
512
1K
14
28
8
16
2K
Note 1: One pin is input-only.
2: Debugging Methods: (I) – Integrated on Chip; E – using Emulation Header.
Data Sheet Index: (Unshaded devices are described in this document.)
A) DS40001799
B) DS40001800
C) DS40001795
PIC16(L)F18313/18323 Data Sheet, Full-Featured, Low Pin Count Microcontrollers with XLP
PIC16(L)F18324/18344 Data Sheet, Full-Featured, Low Pin Count Microcontrollers with XLP
PIC16(L)F18325/18345 Data Sheet, Full-Featured, Low Pin Count Microcontrollers with XLP
D) Future Release PIC16(L)F18326/18346 Data Sheet, Full-Featured, Low Pin Count Microcontrollers with XLP
Note:
For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
PIC16(L)F183XX
TABLE 2:
Packages
PACKAGES
PDIP
SOIC
UDFN
TSSOP
UQFN
SSOP
PIC16(L)F18313
PIC16(L)F18323
PIC16(L)F18324
PIC16(L)F18325
PIC16(L)F18326
PIC16(L)F18344
PIC16(L)F18345
PIC16(L)F18346
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Note:
Pin details are subject to change.
DS40001744C-page 4
2014-2016 Microchip Technology Inc.
PIC16(L)F183XX
PIN DIAGRAMS
Pin Diagram – 8-Pin PDIP, SOIC, UDFN
VSS
VDD
1
2
3
4
8
7
6
5
RA5
RA4
RA0/ICSPDAT
RA1/ICSPCLK
RA2
VPP/MCLR/RA3
Note:
See Table 3 for location of all peripheral functions.
Pin Diagram – 14-Pin PDIP, SOIC, TSSOP
14
VSS
1
VDD
13
12
11
10
9
2
3
4
5
6
7
RA0/ICSPDAT
RA1/ICSPCLK
RA5
RA4
VPP/MCLR/RA3
RC5
RA2
RC0
RC1
RC2
RC4
RC3
8
Note:
See Table 4, Table 5, Table 6 and Table 7 for location of all peripheral functions.
Pin Diagram – 16-Pin UQFN (4x4)
13
16 15 14
PIC16(L)F18323 12
RA0/ICSPDAT
RA1/ICSPCLK
RA5
RA4
RA3/MCLR/VPP
RC5
1
2
3
4
11
PIC16(L)F18324
PIC16(L)F18325
PIC16(L)F18326
10 RA2
9
RC0
5
6 7 8
Note 1: See Table 4, Table 5, Table 6 and Table 7 for location of all peripheral functions.
2: It is recommended that the exposed bottom pad be connected to VSS.
2014-2016 Microchip Technology Inc.
DS40001744C-page 5
PIC16(L)F183XX
Pin Diagram – 20-Pin PDIP, SOIC, SSOP
VDD
1
VSS
20
19
18
17
16
15
14
13
12
11
RA5
RA0/ICSPDAT
RA1/ICSPCLK
RA2
2
3
4
RA4
MCLR/VPP/RA3
RC0
RC5
RC4
RC3
RC6
RC7
RB7
5
RC1
6
RC2
7
RB4
RB5
RB6
8
9
10
Note:
See Table 8, Table 9 and Table 10 for location of all peripheral functions.
Pin Diagram – 20-Pin UQFN (4x4)
20 19 18 17 16
RA3/MCLR/VPP
1
2
3
4
5
15 RA1/ICSPCLK
-
RC5
RC4
RC3
RC6
14
13
12
RA2
RC0
RC1
11 RC2
6
7 8 9 10
Note 1: See Table 8, Table 9 and Table 10 for location of all peripheral functions.
2: It is recommended that the exposed bottom pad be connected to VSS.
DS40001744C-page 6
2014-2016 Microchip Technology Inc.
PIN ALLOCATION TABLES
TABLE 3:
8-PIN ALLOCATION TABLE (PIC16(L)F18313)
RA0
RA1
7
ANA0
—
C1IN0+
C1IN0-
—
—
DAC1OUT
DAC1REF+
MDCIN1(1)
MDMIN(1)
—
—
—
—
—
—
—
—
—
TX(1)
CK(1)
RX(1)
CLCIN3(1)
CLCIN2(1)
—
—
IOCA0
IOCA1
Y
Y
ICDDAT/
ICSPDAT
6
ANA1 VREF+
ANA2 VREF-
SCK(1)
ICDCLK/
ICSPCLK
SCL(1,3,4) DT(1,3)
INT(1)
IOCA2
RA2
RA3
RA4
RA5
5
4
3
2
—
—
—
—
DAC1REF-
—
—
—
T0CKI(1)
—
—
—
—
—
CWG1(1) SDA(1,3,4)
SDO(1)
—
—
—
—
Y
Y
Y
Y
—
—
—
—
SS(1)
—
CLCIN0(1)
IOCA3
IOCA4
IOCA5
MCLR
VPP
ANA4
ANA5
T1G(1)
SOSCO
CLKOUT
OSC2
—
—
C1IN1-
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MDCIN2(1) T1CKI(1)
SOSCIN
CLCIN1(1)
CLKIN
OSC1
CCP1(1)
CCP2(1)
SOSCI
VDD
VSS
1
8
—
—
VDD
VSS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C1OUT
—
NCO
—
—
—
—
—
DSM
—
TMR0
—
CCP1
CCP2
—
PWM5
PWM6
—
CWG1A
CWG1B
CWG1C
CWG1D
SDA(3)
SCL(3)
SDO
CK
DT(3)
TX
CLC1OUT CLKR
—
—
—
—
—
—
—
—
—
—
—
—
CLC2OUT
—
—
—
OUT(2)
—
—
—
—
—
—
—
—
—
—
—
—
SCK
—
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
3:
4:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to the other pins (e.g., RA5) will operate, but logic levels will be standard TTL/
ST as selected by the INLVL register.
TABLE 4:
14/16-PIN ALLOCATION TABLE (PIC16(L)F18323)
RA0
RA1
13
12
11
ANA0
—
C1IN0+
—
—
—
—
DAC1OUT
DAC1REF+
DAC1REF-
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOCA0
IOCA1
Y
Y
ICDDAT/
ICSPDAT
—
—
12
ANA1 VREF+ C1IN0-
C2IN0-
ICDCLK/
ICSPCLK
RA2
RA3
RA4
RA5
11
4
10
3
ANA2 VREF-
—
T0CKI(1)
—
CWG1(1)
—
—
—
INT(1)
IOCA2
Y
Y
Y
Y
—
—
—
—
IOCA3
IOCA4
IOCA5
MCLR
VPP
3
2
ANA4
ANA5
T1G(1)
SOSCO
T1CKI(1)
SOSCIN
SOSCI
CLKOUT
OSC2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
1
CLCIN3(1)
CLKIN
OSC1
RC0
10
9
ANC0
ANC1
ANC2
ANC3
—
—
—
—
C2IN0+
IOCC0
Y
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCK(1)
—
—
—
—
—
SCL(1,3,4)
RC1
RC2
RC3
RC4
9
8
7
6
8
7
6
5
C1IN1-
C2IN1-
—
SDI(1)
CLCIN2(1)
IOCC1
IOCC2
IOCC3
IOCC4
Y
Y
Y
Y
—
—
—
—
SDA(1,3,4)
—
—
—
—
MDCIN1(1)
MDMIN(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C1IN2-
C2IN2-
C1IN3-
C2IN3-
CCP2(1)
SS(1)
CLCIN0(1)
CLCIN1(1)
ANC4
ANC5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TX(1)
CK(1)
RC5
5
4
—
MDCIN2(1)
CCP1(1)
RX(1)
—
—
IOCC5
Y
—
DT(1,3)
VDD
VSS
1
16
13
VDD
VSS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
14
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
3:
4:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
TABLE 4:
14/16-PIN ALLOCATION TABLE (PIC16(L)F18323) (CONTINUED)
—
—
—
—
—
—
—
—
—
—
—
—
—
C1OUT
C2OUT
—
NCO
—
—
—
—
—
DSM
—
TMR0
—
CCP1
CCP2
—
PWM5
PWM6
—
CWG1A
CWG1B
CWG1C
CWG1D
SDA(3)
SCL(3)
SDO
CK
CLC1OUT CLKR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DT(3) CLC2OUT
—
—
—
OUT(2)
—
—
—
TX
—
—
—
—
—
—
—
—
—
SCK
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
3:
4:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
TABLE 5:
14/16-PIN ALLOCATION TABLE (PIC16(L)F18324)
RA0
RA1
13
12
11
ANA0
—
C1IN0+
—
—
—
—
DAC1OUT
DAC1REF+
DAC1REF-
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOCA0
IOCA1
Y
Y
ICDDAT/
ICSPDAT
—
—
12
ANA1 VREF+ C1IN0-
C2IN0-
ICDCLK/
ICSPCLK
RA2
RA3
RA4
RA5
11
4
10
3
ANA2 VREF-
—
T0CKI(1) CCP3(1)
CWG1(1)
CWG2(1)
—
—
INT(1)
IOCA2
Y
Y
Y
Y
—
—
—
—
—
—
—
IOCA3
IOCA4
IOCA5
MCLR
VPP
3
2
ANA4
ANA5
T1G(1)
SOSCO
T1CKI(1)
SOSCIN
SOSCI
CLKOUT
OSC2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
1
CLCIN3(1)
CLKIN
OSC1
RC0
10
9
ANC0
ANC1
ANC2
ANC3
—
—
—
—
C2IN0+
IOCC0
Y
—
—
—
—
—
—
—
T5CKI(1)
—
—
—
—
—
SCK(1)
—
—
—
—
—
SCL(1,3,4)
RC1
RC2
RC3
RC4
9
8
7
6
8
7
6
5
C1IN1-
C2IN1-
—
CCP4(1)
SDI(1)
CLCIN2(1)
IOCC1
IOCC2
IOCC3
IOCC4
Y
Y
Y
Y
—
—
—
—
SDA(1,3,4)
—
—
—
—
MDCIN1(1)
MDMIN(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
C1IN2-
C2IN2-
C1IN3-
C2IN3-
T5G(1) CCP2(1)
T3G(1)
SS(1)
CLCIN0(1)
CLCIN1(1)
ANC4
ANC5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TX(1)
CK(1)
RC5
5
4
—
MDCIN2(1) T3CKI(1) CCP1(1)
RX(1)
—
—
IOCC5
Y
—
DT(1,3)
VDD
VSS
1
16
13
VDD
VSS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
14
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
3:
4:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
TABLE 5:
14/16-PIN ALLOCATION TABLE (PIC16(L)F18324) (CONTINUED)
—
—
—
—
—
—
—
C1OUT
C2OUT
NCO
—
—
—
DSM
—
TMR0
—
CCP1
CCP2
PWM5
PWM6
CWG1A
CWG2A
SDA(3)
SCL(3)
CK
CLC1OUT CLKR
—
—
—
—
—
—
—
—
—
CWG1B
CWG2B
DT(3) CLC2OUT
—
—
—
OUT(2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CCP3
CCP4
—
—
CWG1C
CWG2C
SDO
SCK
TX
—
CLC3OUT
CLC4OUT
—
—
—
—
—
—
CWG1D
CWG2D
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
3:
4:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
TABLE 6:
14/16-PIN ALLOCATION TABLE (PIC16(L)F18325)
RA0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Y
Y
ICDDAT/
ICSPDAT
13
12 ANA0
C1IN0+
DAC1OUT
DAC1REF+
SS2(1)
—
IOCA0
IOCA1
—
—
RA1
12
11
ANA1 VREF
+
C1IN0-
C2IN0-
ICDCLK/
ICSPCLK
—
RA2
RA3
RA4
RA5
11
4
10 ANA2 VREF-
—
DAC1REF-
—
T0CKI(1) CCP3(1)
CWG1(1)
CWG2(1)
—
—
INT(1)
IOCA2
Y
Y
Y
Y
—
3
2
1
—
—
—
—
—
—
—
IOCA3
IOCA4
IOCA5
MCLR
VPP
3
ANA4
ANA5
T1G(1)
SOSCO
T1CKI(1)
SOSCIN
SOSCI
CLKOUT
OSC2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
CLCIN3(1)
CLKIN
OSC1
RC0
10
9
ANC0
ANC1
ANC2
ANC3
—
—
—
—
C2IN0+
IOCC0
Y
—
—
—
—
—
—
—
T5CKI(1)
—
—
—
—
—
SCK1(1)
—
—
—
—
—
SCL1(1,3,4)
RC1
RC2
RC3
RC4
9
8
7
6
8
7
6
5
C1IN1-
C2IN1-
—
CCP4(1)
SDI1(1)
CLCIN2(1)
IOCC1
IOCC2
IOCC3
IOCC4
Y
Y
Y
Y
—
—
—
—
SDA1(1,3,4)
—
—
—
—
MDCIN1(1)
MDMIN(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
C1IN2-
C2IN2-
C1IN3-
C2IN3-
T5G(1) CCP2(1)
T3G(1)
SS1(1)
CLCIN0(1)
CLCIN1(1)
ANC4
ANC5
—
—
—
—
—
—
—
—
—
—
—
—
—
SCK2(1)
TX(1)
SCL2(1,3,4) CK(1)
RC5
5
4
—
MDCIN2(1) T3CKI(1) CCP1(1)
SDI2(1)
RX(1)
—
—
IOCC5
Y
—
SDA2(1,3,4) DT(1,3
)
VDD
VSS
1
16
13
VDD
VSS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
14
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
3:
4:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
TABLE 6:
14/16-PIN ALLOCATION TABLE (PIC16(L)F18325) (CONTINUED)
—
—
—
—
—
—
—
C1OUT
C2OUT
DDS
—
—
—
DSM
—
TMR0
—
CCP1
CCP2
PWM5
PWM6
CWG1A
CWG2A
SDA1(3)
SDA2(3)
SCL1(3)
SCL2(3)
CK
CLC1OUT CLKR
—
—
—
—
—
—
—
—
—
CWG1B
CWG2B
DT(3) CLC2OUT
—
—
—
OUT(2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CCP3
CCP4
—
—
CWG1C
CWG2C
SDO1
SDO2
TX
—
CLC3OUT
CLC4OUT
—
—
—
—
—
—
CWG1D
CWG2D
SCK1
SCK2
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
3:
4:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
TABLE 7:
14/16-PIN ALLOCATION TABLE (PIC16(L)F18326)
RA0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Y
Y
ICDDAT/
ICSPDAT
13
12 ANA0
C1IN0+
DAC1OUT
DAC1REF+
SS2(1)
—
IOCA0
IOCA1
—
—
RA1
12
11
ANA1 VREF
+
C1IN0-
C2IN0-
ICDCLK/
ICSPCLK
—
RA2
RA3
RA4
RA5
11
4
10 ANA2 VREF-
—
DAC1REF-
—
T0CKI(1) CCP3(1)
CWG1(1)
CWG2(1)
—
—
INT(1)
IOCA2
Y
Y
Y
Y
—
3
2
1
—
—
—
—
—
—
—
IOCA3
IOCA4
IOCA5
MCLR
VPP
3
ANA4
ANA5
T1G(1)
SOSCO
T1CKI(1)
SOSCIN
SOSCI
CLKOUT
OSC2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
CLCIN3(1)
CLKIN
OSC1
RC0
10
9
ANC0
ANC1
ANC2
ANC3
—
—
—
—
C2IN0+
IOCC0
Y
—
—
—
—
—
—
—
T5CKI(1)
—
—
—
—
—
SCK1(1)
—
—
—
—
—
SCL1(1,3,4)
RC1
RC2
RC3
RC4
9
8
7
6
8
7
6
5
C1IN1-
C2IN1-
—
CCP4(1)
SDI1(1)
CLCIN2(1)
IOCC1
IOCC2
IOCC3
IOCC4
Y
Y
Y
Y
—
—
—
—
SDA1(1,3,4)
—
—
—
—
MDCIN1(1)
MDMIN(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
C1IN2-
C2IN2-
C1IN3-
C2IN3-
T5G(1) CCP2(1)
T3G(1)
SS1(1)
CLCIN0(1)
CLCIN1(1)
ANC4
ANC5
—
—
—
—
—
—
—
—
—
—
—
—
—
SCK2(1)
TX(1)
SCL2(1,3,4) CK(1)
RC5
5
4
—
MDCIN2(1) T3CKI(1) CCP1(1)
SDI2(1)
RX(1)
—
—
IOCC5
Y
—
SDA2(1,3,4) DT(1,3
)
VDD
VSS
1
16
13
VDD
VSS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
14
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
3:
4:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
TABLE 7:
14/16-PIN ALLOCATION TABLE (PIC16(L)F18326) (CONTINUED)
—
—
—
—
—
—
—
C1OUT
C2OUT
DDS
—
—
—
DSM
—
TMR0
—
CCP1
CCP2
PWM5
PWM6
CWG1A
CWG2A
SDA1(3)
SDA2(3)
SCL1(3)
SCL2(3)
CK
CLC1OUT CLKR
—
—
—
—
—
—
—
—
—
CWG1B
CWG2B
DT(3) CLC2OUT
—
—
—
OUT(2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CCP3
CCP4
—
—
CWG1C
CWG2C
SDO1
SDO2
TX
—
CLC3OUT
CLC4OUT
—
—
—
—
—
—
CWG1D
CWG2D
SCK1
SCK2
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
3:
4:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
TABLE 8:
20-PIN ALLOCATION TABLE (PIC16(L)F18344)
RA0
RA1
19
16
15
ANA0
—
C1IN0+
—
—
DAC1OUT
DAC1REF+
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOCA0
IOCA1
Y
Y
ICDDAT/
ICSPDAT
—
—
18
17
4
ANA1 VREF
+
C1IN0-
C2IN0-
ICDCLK/
ICSPCLK
CLCIN0(1)
RA2
RA3
RA4
14
1
ANA2 VREF-
—
—
—
—
—
—
DAC1REF-
—
—
—
T0CKI(1) CCP3(1)
—
—
—
CWG1(1)
CWG2(1)
—
—
—
—
—
—
INT(1)
IOCA2
Y
Y
Y
—
—
—
—
—
—
—
—
—
—
—
—
—
IOCA3
MCLR
VPP
T1G(1)
T3G(1)
T5G(1)
SOSCO
IOCA4
CLKOUT
OSC2
CCP4(1)
—
3
20
ANA4
RA5
2
19
ANA5
—
—
—
—
—
T1CKI(1)
T3CKI(1)
T5CKI(1)
SOSCIN
SOSCI
—
—
—
—
—
—
—
—
IOCA5
Y
CLKIN
OSC1
RB4
RB5
RB6
RB7
13
12
11
10
10
9
CLCIN2(1)
ANB4
ANB5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDI(1)
—
—
IOCB4
IOCB5
Y
Y
—
—
SDA(1,3,4)
—
—
RX(1) CLCIN3(1)
DT(1)
ANB6
ANB7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCK(1)
—
—
—
—
IOCB6
IOCB7
Y
Y
—
—
8
SCL(1,3,4)
TX(1)
CK(1)
7
—
—
RC0
RC1
16
15
13 ANC0
12 ANC1
—
—
C2IN0+
IOCC0
IOCC1
Y
Y
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C1IN1-
C2IN1-
MDCIN1(1)
—
—
—
—
—
—
—
—
RC2
14
11
ANC2
—
C1IN2-
C2IN2-
IOCC2
Y
—
—
—
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
3:
4:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
TABLE 8:
20-PIN ALLOCATION TABLE (PIC16(L)F18344) (CONTINUED)
RC3
RC4
7
4
3
ANC3
—
C1IN3-
C2IN3-
—
—
MDMIN(1)
—
CCP2(1)
—
—
—
—
—
CLCIN1(1)
—
—
IOCC3
IOCC4
Y
Y
—
—
6
ANC4
ANC5
ANC6
ANC7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CCP1(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RC5
RC6
RC7
VDD
VSS
5
8
2
5
MDCIN2(1)
—
SS(1)
—
—
—
—
—
—
IOCC5
IOCC6
IOCC7
—
Y
Y
—
—
—
—
—
—
9
6
—
Y
—
1
18
17
VDD
VSS
—
—
—
—
20
—
—
—
—
—
—
—
—
C1OUT
NCO
—
DSM
TMR0
CCP1
PWM5
CWG1A
CWG2A
SDO
DT(3) CLC1OUT CLKR
—
—
—
—
—
—
—
C2OUT
—
—
—
—
CCP2
PWM6
CWG1B
CWG2B
SCK
CK
TX
—
CLC2OUT
CLC3OUT
CLC4OUT
—
—
—
—
—
—
OUT(2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CCP3
CCP4
—
—
CWG1C
CWG2C
SCL(3)
SDA(3)
—
—
—
—
—
—
CWG1D
CWG2D
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
3:
4:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
TABLE 9:
20-PIN ALLOCATION TABLE (PIC16(L)F18345)
RA0
RA1
19
16 ANA0
—
C1IN0+
—
—
DAC1OUT
DAC1REF+
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOCA0
IOCA1
Y
Y
ICDDAT/
ICSPDAT
—
—
SS2(1)
—
18
17
4
15 ANA1 VREF
+
C1IN0-
C2IN0-
ICDCLK/
ICSPCLK
T0CKI(1)
CLCIN0(1)
INT(1)
IOCA2
RA2
RA3
RA4
14 ANA2 VREF-
—
—
—
—
—
—
DAC1REF-
—
—
—
CCP3(1)
—
—
—
—
CWG1(1)
CWG2(1)
—
—
—
—
—
—
Y
Y
Y
—
1
—
—
—
—
—
—
—
—
—
—
—
IOCA3
MCLR
VPP
T1G(1)
T3G(1)
T5G(1)
SOSCO
IOCA4
CLKOUT
OSC2
CCP4(1)
—
3
20 ANA4
RA5
2
19 ANA5
—
—
—
—
—
T1CKI(1)
T3CKI(1)
T5CKI(1)
SOSCIN
SOSCI
—
—
—
—
—
—
—
—
IOCA5
Y
CLKIN
OSC1
RB4
RB5
RB6
RB7
13
12
11
10
10
9
CLCIN2(1)
ANB4
ANB5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDI1(1)
—
—
IOCB4
IOCB5
Y
Y
—
—
SDA1(1,3,4)
—
SDI2(1)
RX(1) CLCIN3(1)
SDA2(1,3,4) DT(1)
ANB6
ANB7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCK1(1)
—
—
—
—
—
IOCB6
IOCB7
Y
Y
—
—
8
SCL1(1,3,4)
SCK2(1)
TX(1)
CK(1)
7
SCL2(1,3,4)
RC0
RC1
16
15
13 ANC0
12 ANC1
—
—
C2IN0+
IOCC0
IOCC1
Y
Y
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C1IN1-
C2IN1-
MDCIN1(1)
MDMIN(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RC2
RC3
14
7
11
4
ANC2
ANC3
—
—
C1IN2-
C2IN2-
IOCC2
IOCC3
Y
Y
—
—
—
—
—
—
C1IN3-
C2IN3-
CCP2(1)
CLCIN1(1)
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
3:
4:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
TABLE 9:
20-PIN ALLOCATION TABLE (PIC16(L)F18345) (CONTINUED)
RC4
RC5
RC6
RC7
VDD
6
3
2
—
—
—
—
IOCC4
IOCC5
IOCC6
IOCC7
Y
Y
Y
Y
—
—
ANC4
ANC5
ANC6
ANC7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CCP1(1)
—
—
—
—
—
—
—
—
—
—
—
SS(1)
—
—
—
—
—
—
—
—
5
8
9
1
MDCIN2(1)
5
—
—
—
6
—
—
—
18
VDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VSS
20
—
17
—
VSS
—
C1OUT
NCO
DSM
TMR0
CCP1
PWM5
CWG1A
CWG2A
SDO1
SDO2
DT(3) CLC1OUT CLKR
—
—
—
—
C2OUT
—
—
—
—
CCP2
PWM6
CWG1B
CWG2B
SCK1
SCK2
CK
CLC2OUT
—
—
—
—
OUT(2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CCP3
CCP4
—
—
CWG1C
CWG2C
SCL1(3)
SCL2(3)
SDA1(3)
SDA2(3)
TX
—
CLC3OUT
CLC4OUT
—
—
—
—
—
—
—
—
CWG1D
CWG2D
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
3:
4:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
TABLE 10:
20-PIN ALLOCATION TABLE (PIC16(L)F18346)
RA0
RA1
19
18
16 ANA0
—
C1IN0+
—
—
DAC1OUT
DAC1REF+
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOCA0
IOCA1
Y
Y
ICDDAT/
ICSPDAT
—
—
SS2(1)
—
15 ANA1 VREF
+
C1IN0-
C2IN0-
ICDCLK/
ICSPCLK
T0CKI(1)
CLCIN0(1)
INT(1)
IOCA2
RA2
RA3
RA4
17
4
14 ANA2 VREF-
—
—
—
—
—
—
DAC1REF-
—
—
—
CCP3(1)
—
—
—
—
CWG1(1)
CWG2(1)
—
—
—
—
—
—
Y
Y
Y
—
1
—
—
—
—
—
—
—
—
—
—
—
IOCA3
MCLR
VPP
T1G(1)
T3G(1)
T5G(1)
SOSCO
IOCA4
CLKOUT
OSC2
CCP4(1)
—
3
20 ANA4
RA5
2
19 ANA5
—
—
—
—
—
T1CKI(1)
T3CKI(1)
T5CKI(1)
SOSCIN
SOSCI
—
—
—
—
—
—
—
—
IOCA5
Y
CLKIN
OSC1
RB4
RB5
RB6
RB7
13
12
11
10
10
9
CLCIN2(1)
ANB4
ANB5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDI1(1)
—
—
IOCB4
IOCB5
Y
Y
—
—
SDA1(1,3,4)
—
SDI2(1)
RX(1) CLCIN3(1)
SDA2(1,3,4) DT(1)
ANB6
ANB7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCK1(1)
—
—
—
—
—
IOCB6
IOCB7
Y
Y
—
—
8
SCL1(1,3,4)
SCK2(1)
TX(1)
CK(1)
7
SCL2(1,3,4)
RC0
RC1
16
15
13 ANC0
12 ANC1
—
—
C2IN0+
IOCC0
IOCC1
Y
Y
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C1IN1-
C2IN1-
MDCIN1(1)
—
—
—
—
—
—
—
—
RC2
14
11
ANC2
—
C1IN2-
C2IN2-
IOCC2
Y
—
—
—
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
3:
4:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
TABLE 10:
20-PIN ALLOCATION TABLE (PIC16(L)F18346) (CONTINUED)
RC3
RC4
7
6
4
3
ANC3
—
C1IN3-
C2IN3-
—
—
MDMIN(1)
—
CCP2(1)
—
—
—
—
CLCIN1(1)
—
—
IOCC3
IOCC4
Y
Y
—
—
ANC4
ANC5
ANC6
ANC7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CCP1(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SS(1)
—
—
—
—
—
—
—
—
—
—
—
—
RC5
RC6
RC7
VDD
VSS
5
8
2
5
MDCIN2(1)
—
—
—
—
—
IOCC5
IOCC6
IOCC7
—
Y
Y
—
—
—
—
—
—
9
6
—
—
Y
—
1
18
17
VDD
VSS
—
—
—
—
20
—
—
—
—
—
—
—
—
C1OUT
NCO
—
DSM
TMR0
CCP1
PWM5
CWG1A
CWG2A
SDO1
SDO2
DT(3) CLC1OUT CLKR
—
—
—
—
—
—
—
C2OUT
—
—
—
—
CCP2
PWM6
CWG1B
CWG2B
SCK1
SCK2
CK
TX
—
CLC2OUT
CLC3OUT
CLC4OUT
—
—
—
—
—
—
OUT(2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CCP3
CCP4
—
—
CWG1C
CWG2C
SCL1(3)
SCL2(3)
SDA1(3)
SDA2(3)
—
—
—
—
—
—
CWG1D
CWG2D
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
3:
4:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
32
OptoLyzer, PIC, PICSTART, PIC logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,
Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2014-2016, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0183-4
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
DS40001744C-page 22
2014-2016 Microchip Technology Inc.
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
www.microchip.com
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Germany - Dusseldorf
Tel: 49-2129-3766400
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Germany - Karlsruhe
Tel: 49-721-625370
India - Pune
Tel: 91-20-3019-1500
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Austin, TX
Tel: 512-257-3370
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Boston
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
China - Dongguan
Tel: 86-769-8702-9880
Italy - Venice
Tel: 39-049-7625286
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
Cleveland
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Poland - Warsaw
Tel: 48-22-3325737
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Sweden - Stockholm
Tel: 46-8-5090-4654
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Detroit
Novi, MI
UK - Wokingham
Tel: 44-118-921-5800
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Tel: 248-848-4000
Fax: 44-118-921-5820
Houston, TX
Tel: 281-894-5983
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
New York, NY
Tel: 631-435-6000
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
San Jose, CA
Tel: 408-735-9110
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
07/14/15
2014-2016 Microchip Technology Inc.
DS40001744C-page 23
相关型号:
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明