PIC16F18325-I/SL [MICROCHIP]

IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,14PIN,PLASTIC;


型号：	PIC16F18325-I/SL
厂家：	MICROCHIP
描述：	IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,14PIN,PLASTIC 时钟微控制器光电二极管外围集成电路
文件：	总23页 (文件大小：189K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC16(L)F183XX

Full-Featured, Low Pin Count Microcontrollers with XLP Product Brief

Description

PIC16(L)F183XX microcontrollers feature Analog, Core Independent Peripherals and communication peripherals,

combined with eXtreme Low Power (XLP) for a wide range of general purpose and low-power applications. The

Peripheral Pin Select (PPS) functionality enables pin mapping when using the digital peripherals (CLC, CWG, CCP,

PWM and communications) to add flexibility to the application design.

Core Features

Power-Saving Functionality

• C Compiler Optimized RISC Architecture

• Only 49 Instructions

• Operating Speed:

• Doze mode: Ability to run the CPU core slower

than the system clock used by the internal

peripherals

- DC – 32 MHz clock input

- 125 ns minimum instruction cycle

• Interrupt Capability

• Idle mode: Ability to put the CPU core to sleep

while internal peripherals continue operating from

the system clock

• 16-Level Deep Hardware Stack

• Up to Four 8-Bit Timers

• Up to Three 16-Bit Timers

• Low-Current Power-on Reset (POR)

• Configurable Power-up Timer (PWRTE)

• Brown-out Reset (BOR) with Fast Recovery

• Low-Power BOR (LPBOR) Option

• Extended Watchdog Timer (WDT) with Dedicated

On-Chip Oscillator for Reliable Operation

• Programmable Code Protection

• Sleep mode: Lowest Power Consumption

• Peripheral Module Disable: Peripheral power

disable hardware module to minimize power

consumption of unused peripherals

Digital Peripherals

• Configurable Logic Cell (CLC):

- Up to four CLCs

- Integrated combinational and sequential logic

• Complementary Waveform Generator (CWG):

- Rising and falling edge dead-band control

- Full-bridge, half-bridge, 1-channel drive

- Up to two CWGs

Memory

• Up to 28 KB Program Flash Memory (PFM)

• Up to 2 KB Data SRAM Memory

- Multiple signal sources

• 256B of EEPROM Data Flash Memory (DFM)

• Direct, Indirect and Relative Addressing modes

• Up to Four Capture/Compare/PWM (CCP)

modules

• PWM: Two 10-bit Pulse-Width Modulators

• Numerically Controlled Oscillator (NCO):

- Precision linear frequency generator (@50%

duty cycle) with 0.0001% step size of source

input clock

Operating Characteristics

• Operating Voltage Range:

- 1.8V to 3.6V (PIC16LF183XX)

- 2.3V to 5.5V (PIC16F183XX)

• Temperature Range:

- Input Clock: 0 Hz < FNCO < 32 MHz

- Resolution: FNCO/2²⁰

- Industrial: -40°C to 85°C

- Extended: -40°C to 125°C

• Serial Communications:

- SPI, I²C, EUSART

- RS-232, RS-485, LIN compatible

• Data Signal Modulator (DSM):

- Modulates a carrier signal with digital data to

create custom carrier synchronized output

waveforms

eXtreme Low-Power (XLP) Features

• Sleep mode: 40 nA @ 1.8V, typical

• Watchdog Timer: 250 nA @ 1.8V, typical

• Secondary Oscillator: 300 nA @ 32 kHz

• Operating Current:

- 8 uA @ 32 kHz, 1.8V, typical

- 37 uA/MHz @ 1.8V, typical

 2014-2016 Microchip Technology Inc.

DS40001744C-page 1

PIC16(L)F183XX

• Peripheral Pin Select (PPS):

- I/O pin remapping of digital peripherals

• Up to 18 I/O Pins:

- Individually programmable pull ups

- Slew rate control

- Interrupt-on-change with edge-select

- Input level selection control (ST or TTL)

- Digital open-drain enable

Clocking Structure

• High-Precision Internal Oscillator:

- Selectable frequency range up to 32 MHz

• x2/x4 PLL with Internal and External Sources

• Low-Power Internal 32 kHz Oscillator

(LFINTOSC)

• External 32 kHz Crystal Oscillator (SOCS)

• External High-Speed Crystal Oscillators

Analog Peripherals

• 10-Bit Analog-to-Digital Converter (ADC):

- Up to 17 external channels

- Conversion available during Sleep

• Comparator:

- Up to two comparators

- Low and High-Speed modes

- Fixed Voltage Reference at inverting/

noninverting input(s)

- Comparator outputs externally accessible

• 5-Bit Digital-to-Analog Converter (DAC):

- 5-bit resolution, rail-to-rail

- Positive Reference Selection

- Unbuffered I/O pin output

- Internal connections to ADCs and

comparators

• Voltage Reference:

- Fixed Voltage Reference with 1.024V, 2.048V

and 4.096V output levels

DS40001744C-page 2

 2014-2016 Microchip Technology Inc.

TABLE 1:

PIC16(L)F183XX Family Types

Device

PIC16(L)F18313

PIC16(L)F18323

PIC16(L)F18324

PIC16(L)F18325

PIC16(L)F18326

PIC16(L)F18344

PIC16(L)F18345

PIC16(L)F18346

(A)

(B)

(C)

(D)

(B)

(C)

(D)

3.5

256

512

1/1/1 2/2

1/3/3 4/2

512

Note 1: One pin is input-only.

2: Debugging Methods: (I) – Integrated on Chip; E – using Emulation Header.

Data Sheet Index: (Unshaded devices are described in this document.)

A) DS40001799

B) DS40001800

C) DS40001795

PIC16(L)F18313/18323 Data Sheet, Full-Featured, Low Pin Count Microcontrollers with XLP

PIC16(L)F18324/18344 Data Sheet, Full-Featured, Low Pin Count Microcontrollers with XLP

PIC16(L)F18325/18345 Data Sheet, Full-Featured, Low Pin Count Microcontrollers with XLP

D) Future Release PIC16(L)F18326/18346 Data Sheet, Full-Featured, Low Pin Count Microcontrollers with XLP

Note:

For other small form-factor package availability and marking information, please visit

http://www.microchip.com/packaging or contact your local sales office.

PIC16(L)F183XX

TABLE 2:

Packages

PACKAGES

PDIP

SOIC

UDFN

TSSOP

UQFN

SSOP

PIC16(L)F18313

PIC16(L)F18323

PIC16(L)F18324

PIC16(L)F18325

PIC16(L)F18326

PIC16(L)F18344

PIC16(L)F18345

PIC16(L)F18346

Note:

Pin details are subject to change.

DS40001744C-page 4

 2014-2016 Microchip Technology Inc.

PIC16(L)F183XX

PIN DIAGRAMS

Pin Diagram – 8-Pin PDIP, SOIC, UDFN

VSS

VDD

RA5

RA4

RA0/ICSPDAT

RA1/ICSPCLK

RA2

VPP/MCLR/RA3

Note:

See Table 3 for location of all peripheral functions.

Pin Diagram – 14-Pin PDIP, SOIC, TSSOP

VSS

VDD

RA0/ICSPDAT

RA1/ICSPCLK

RA5

RA4

VPP/MCLR/RA3

RC5

RA2

RC0

RC1

RC2

RC4

RC3

Note:

See Table 4, Table 5, Table 6 and Table 7 for location of all peripheral functions.

Pin Diagram – 16-Pin UQFN (4x4)

16 15 14

PIC16(L)F18323 12

RA0/ICSPDAT

RA1/ICSPCLK

RA5

RA4

RA3/MCLR/VPP

RC5

PIC16(L)F18324

PIC16(L)F18325

PIC16(L)F18326

10 RA2

RC0

6 7 8

Note 1: See Table 4, Table 5, Table 6 and Table 7 for location of all peripheral functions.

2: It is recommended that the exposed bottom pad be connected to VSS.

 2014-2016 Microchip Technology Inc.

DS40001744C-page 5

PIC16(L)F183XX

Pin Diagram – 20-Pin PDIP, SOIC, SSOP

VDD

VSS

RA5

RA0/ICSPDAT

RA1/ICSPCLK

RA2

RA4

MCLR/VPP/RA3

RC0

RC5

RC4

RC3

RC6

RC7

RB7

RC1

RC2

RB4

RB5

RB6

Note:

See Table 8, Table 9 and Table 10 for location of all peripheral functions.

Pin Diagram – 20-Pin UQFN (4x4)

20 19 18 17 16

RA3/MCLR/VPP

15 RA1/ICSPCLK

RC5

RC4

RC3

RC6

RA2

RC0

RC1

11 RC2

7 8 9 10

Note 1: See Table 8, Table 9 and Table 10 for location of all peripheral functions.

2: It is recommended that the exposed bottom pad be connected to VSS.

DS40001744C-page 6

 2014-2016 Microchip Technology Inc.

PIN ALLOCATION TABLES

TABLE 3:

8-PIN ALLOCATION TABLE (PIC16(L)F18313)

RA0

RA1

ANA0

—

C1IN0+

C1IN0-

—

DAC1OUT

DAC1REF+

MDCIN1⁽¹⁾

MDMIN⁽¹⁾

—

TX⁽¹⁾

CK⁽¹⁾

RX⁽¹⁾

CLCIN3⁽¹⁾

CLCIN2⁽¹⁾

—

IOCA0

IOCA1

ICDDAT/

ICSPDAT

ANA1 VREF+

ANA2 VREF-

SCK⁽¹⁾

ICDCLK/

ICSPCLK

SCL^(1,3,4)DT^(1,3)

INT⁽¹⁾

IOCA2

RA2

RA3

RA4

RA5

—

DAC1REF-

—

T0CKI⁽¹⁾

—

CWG1⁽¹⁾SDA^(1,3,4)

SDO⁽¹⁾

—

SS⁽¹⁾

—

CLCIN0⁽¹⁾

IOCA3

IOCA4

IOCA5

MCLR

VPP

ANA4

ANA5

T1G⁽¹⁾

SOSCO

CLKOUT

OSC2

—

C1IN1-

—

MDCIN2⁽¹⁾T1CKI⁽¹⁾

SOSCIN

CLCIN1⁽¹⁾

CLKIN

OSC1

CCP1⁽¹⁾

CCP2⁽¹⁾

SOSCI

VDD

VSS

—

VDD

VSS

—

C1OUT

—

NCO

—

DSM

—

TMR0

—

CCP1

CCP2

—

PWM5

PWM6

—

CWG1A

CWG1B

CWG1C

CWG1D

SDA⁽³⁾

SCL⁽³⁾

SDO

DT⁽³⁾

CLC1OUT CLKR

—

CLC2OUT

—

OUT⁽²⁾

—

SCK

—

Note 1:

Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.

These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

These pins are configured for I²C logic levels; clock and data signals may be assigned to any of these pins. Assignments to the other pins (e.g., RA5) will operate, but logic levels will be standard TTL/

ST as selected by the INLVL register.

TABLE 4:

14/16-PIN ALLOCATION TABLE (PIC16(L)F18323)

RA0

RA1

ANA0

—

C1IN0+

—

DAC1OUT

DAC1REF+

DAC1REF-

—

IOCA0

IOCA1

ICDDAT/

ICSPDAT

—

ANA1 VREF+ C1IN0-

C2IN0-

ICDCLK/

ICSPCLK

RA2

RA3

RA4

RA5

ANA2 VREF-

—

T0CKI⁽¹⁾

—

CWG1⁽¹⁾

—

INT⁽¹⁾

IOCA2

—

IOCA3

IOCA4

IOCA5

MCLR

VPP

ANA4

ANA5

T1G⁽¹⁾

SOSCO

T1CKI⁽¹⁾

SOSCIN

SOSCI

CLKOUT

OSC2

—

CLCIN3⁽¹⁾

CLKIN

OSC1

RC0

ANC0

ANC1

ANC2

ANC3

—

C2IN0+

IOCC0

—

SCK⁽¹⁾

—

SCL^(1,3,4)

RC1

RC2

RC3

RC4

C1IN1-

C2IN1-

—

SDI⁽¹⁾

CLCIN2⁽¹⁾

IOCC1

IOCC2

IOCC3

IOCC4

—

SDA^(1,3,4)

—

MDCIN1⁽¹⁾

MDMIN⁽¹⁾

—

C1IN2-

C2IN2-

C1IN3-

C2IN3-

CCP2⁽¹⁾

SS⁽¹⁾

CLCIN0⁽¹⁾

CLCIN1⁽¹⁾

ANC4

ANC5

—

TX⁽¹⁾

CK⁽¹⁾

RC5

—

MDCIN2⁽¹⁾

CCP1⁽¹⁾

RX⁽¹⁾

—

IOCC5

—

DT^(1,3)

VDD

VSS

VDD

VSS

—

Note 1:

Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.

These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

These pins are configured for I²C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard

TTL/ST as selected by the INLVL register.

TABLE 4:

14/16-PIN ALLOCATION TABLE (PIC16(L)F18323) (CONTINUED)

—

C1OUT

C2OUT

—

NCO

—

DSM

—

TMR0

—

CCP1

CCP2

—

PWM5

PWM6

—

CWG1A

CWG1B

CWG1C

CWG1D

SDA⁽³⁾

SCL⁽³⁾

SDO

CLC1OUT CLKR

—

DT⁽³⁾CLC2OUT

—

OUT⁽²⁾

—

SCK

Note 1:

Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.

These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

These pins are configured for I²C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard

TTL/ST as selected by the INLVL register.

TABLE 5:

14/16-PIN ALLOCATION TABLE (PIC16(L)F18324)

RA0

RA1

ANA0

—

C1IN0+

—

DAC1OUT

DAC1REF+

DAC1REF-

—

IOCA0

IOCA1

ICDDAT/

ICSPDAT

—

ANA1 VREF+ C1IN0-

C2IN0-

ICDCLK/

ICSPCLK

RA2

RA3

RA4

RA5

ANA2 VREF-

—

T0CKI⁽¹⁾CCP3⁽¹⁾

CWG1⁽¹⁾

CWG2⁽¹⁾

—

INT⁽¹⁾

IOCA2

—

IOCA3

IOCA4

IOCA5

MCLR

VPP

ANA4

ANA5

T1G⁽¹⁾

SOSCO

T1CKI⁽¹⁾

SOSCIN

SOSCI

CLKOUT

OSC2

—

CLCIN3⁽¹⁾

CLKIN

OSC1

RC0

ANC0

ANC1

ANC2

ANC3

—

C2IN0+

IOCC0

—

T5CKI⁽¹⁾

—

SCK⁽¹⁾

—

SCL^(1,3,4)

RC1

RC2

RC3

RC4

C1IN1-

C2IN1-

—

CCP4⁽¹⁾

SDI⁽¹⁾

CLCIN2⁽¹⁾

IOCC1

IOCC2

IOCC3

IOCC4

—

SDA^(1,3,4)

—

MDCIN1⁽¹⁾

MDMIN⁽¹⁾

—

C1IN2-

C2IN2-

C1IN3-

C2IN3-

T5G⁽¹⁾CCP2⁽¹⁾

T3G⁽¹⁾

SS⁽¹⁾

CLCIN0⁽¹⁾

CLCIN1⁽¹⁾

ANC4

ANC5

—

TX⁽¹⁾

CK⁽¹⁾

RC5

—

MDCIN2⁽¹⁾T3CKI⁽¹⁾CCP1⁽¹⁾

RX⁽¹⁾

—

IOCC5

—

DT^(1,3)

VDD

VSS

VDD

VSS

—

Note 1:

Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.

These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

These pins are configured for I²C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard

TTL/ST as selected by the INLVL register.

TABLE 5:

14/16-PIN ALLOCATION TABLE (PIC16(L)F18324) (CONTINUED)

—

C1OUT

C2OUT

NCO

—

DSM

—

TMR0

—

CCP1

CCP2

PWM5

PWM6

CWG1A

CWG2A

SDA⁽³⁾

SCL⁽³⁾

CLC1OUT CLKR

—

CWG1B

CWG2B

DT⁽³⁾CLC2OUT

—

OUT⁽²⁾

—

CCP3

CCP4

—

CWG1C

CWG2C

SDO

SCK

—

CLC3OUT

CLC4OUT

—

CWG1D

CWG2D

Note 1:

Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.

These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

These pins are configured for I²C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard

TTL/ST as selected by the INLVL register.

TABLE 6:

14/16-PIN ALLOCATION TABLE (PIC16(L)F18325)

RA0

—

ICDDAT/

ICSPDAT

12 ANA0

C1IN0+

DAC1OUT

DAC1REF+

SS2⁽¹⁾

—

IOCA0

IOCA1

—

RA1

ANA1 VREF

C1IN0-

C2IN0-

ICDCLK/

ICSPCLK

—

RA2

RA3

RA4

RA5

10 ANA2 VREF-

—

DAC1REF-

—

T0CKI⁽¹⁾CCP3⁽¹⁾

CWG1⁽¹⁾

CWG2⁽¹⁾

—

INT⁽¹⁾

IOCA2

—

IOCA3

IOCA4

IOCA5

MCLR

VPP

ANA4

ANA5

T1G⁽¹⁾

SOSCO

T1CKI⁽¹⁾

SOSCIN

SOSCI

CLKOUT

OSC2

—

CLCIN3⁽¹⁾

CLKIN

OSC1

RC0

ANC0

ANC1

ANC2

ANC3

—

C2IN0+

IOCC0

—

T5CKI⁽¹⁾

—

SCK1⁽¹⁾

—

SCL1^(1,3,4)

RC1

RC2

RC3

RC4

C1IN1-

C2IN1-

—

CCP4⁽¹⁾

SDI1⁽¹⁾

CLCIN2⁽¹⁾

IOCC1

IOCC2

IOCC3

IOCC4

—

SDA1^(1,3,4)

—

MDCIN1⁽¹⁾

MDMIN⁽¹⁾

—

C1IN2-

C2IN2-

C1IN3-

C2IN3-

T5G⁽¹⁾CCP2⁽¹⁾

T3G⁽¹⁾

SS1⁽¹⁾

CLCIN0⁽¹⁾

CLCIN1⁽¹⁾

ANC4

ANC5

—

SCK2⁽¹⁾

TX⁽¹⁾

SCL2^(1,3,4)CK⁽¹⁾

RC5

—

MDCIN2⁽¹⁾T3CKI⁽¹⁾CCP1⁽¹⁾

SDI2⁽¹⁾

RX⁽¹⁾

—

IOCC5

—

SDA2^(1,3,4)DT^(1,3

)

VDD

VSS

VDD

VSS

—

Note 1:

Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.

These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

These pins are configured for I²C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard

TTL/ST as selected by the INLVL register.

TABLE 6:

14/16-PIN ALLOCATION TABLE (PIC16(L)F18325) (CONTINUED)

—

C1OUT

C2OUT

DDS

—

DSM

—

TMR0

—

CCP1

CCP2

PWM5

PWM6

CWG1A

CWG2A

SDA1⁽³⁾

SDA2⁽³⁾

SCL1⁽³⁾

SCL2⁽³⁾

CLC1OUT CLKR

—

CWG1B

CWG2B

DT⁽³⁾CLC2OUT

—

OUT⁽²⁾

—

CCP3

CCP4

—

CWG1C

CWG2C

SDO1

SDO2

—

CLC3OUT

CLC4OUT

—

CWG1D

CWG2D

SCK1

SCK2

Note 1:

Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.

These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

These pins are configured for I²C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard

TTL/ST as selected by the INLVL register.

TABLE 7:

14/16-PIN ALLOCATION TABLE (PIC16(L)F18326)

RA0

—

ICDDAT/

ICSPDAT

12 ANA0

C1IN0+

DAC1OUT

DAC1REF+

SS2⁽¹⁾

—

IOCA0

IOCA1

—

RA1

ANA1 VREF

C1IN0-

C2IN0-

ICDCLK/

ICSPCLK

—

RA2

RA3

RA4

RA5

10 ANA2 VREF-

—

DAC1REF-

—

T0CKI⁽¹⁾CCP3⁽¹⁾

CWG1⁽¹⁾

CWG2⁽¹⁾

—

INT⁽¹⁾

IOCA2

—

IOCA3

IOCA4

IOCA5

MCLR

VPP

ANA4

ANA5

T1G⁽¹⁾

SOSCO

T1CKI⁽¹⁾

SOSCIN

SOSCI

CLKOUT

OSC2

—

CLCIN3⁽¹⁾

CLKIN

OSC1

RC0

ANC0

ANC1

ANC2

ANC3

—

C2IN0+

IOCC0

—

T5CKI⁽¹⁾

—

SCK1⁽¹⁾

—

SCL1^(1,3,4)

RC1

RC2

RC3

RC4

C1IN1-

C2IN1-

—

CCP4⁽¹⁾

SDI1⁽¹⁾

CLCIN2⁽¹⁾

IOCC1

IOCC2

IOCC3

IOCC4

—

SDA1^(1,3,4)

—

MDCIN1⁽¹⁾

MDMIN⁽¹⁾

—

C1IN2-

C2IN2-

C1IN3-

C2IN3-

T5G⁽¹⁾CCP2⁽¹⁾

T3G⁽¹⁾

SS1⁽¹⁾

CLCIN0⁽¹⁾

CLCIN1⁽¹⁾

ANC4

ANC5

—

SCK2⁽¹⁾

TX⁽¹⁾

SCL2^(1,3,4)CK⁽¹⁾

RC5

—

MDCIN2⁽¹⁾T3CKI⁽¹⁾CCP1⁽¹⁾

SDI2⁽¹⁾

RX⁽¹⁾

—

IOCC5

—

SDA2^(1,3,4)DT^(1,3

)

VDD

VSS

VDD

VSS

—

Note 1:

Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.

These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

These pins are configured for I²C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard

TTL/ST as selected by the INLVL register.

TABLE 7:

14/16-PIN ALLOCATION TABLE (PIC16(L)F18326) (CONTINUED)

—

C1OUT

C2OUT

DDS

—

DSM

—

TMR0

—

CCP1

CCP2

PWM5

PWM6

CWG1A

CWG2A

SDA1⁽³⁾

SDA2⁽³⁾

SCL1⁽³⁾

SCL2⁽³⁾

CLC1OUT CLKR

—

CWG1B

CWG2B

DT⁽³⁾CLC2OUT

—

OUT⁽²⁾

—

CCP3

CCP4

—

CWG1C

CWG2C

SDO1

SDO2

—

CLC3OUT

CLC4OUT

—

CWG1D

CWG2D

SCK1

SCK2

Note 1:

Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.

These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

These pins are configured for I²C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard

TTL/ST as selected by the INLVL register.

TABLE 8:

20-PIN ALLOCATION TABLE (PIC16(L)F18344)

RA0

RA1

ANA0

—

C1IN0+

—

DAC1OUT

DAC1REF+

—

IOCA0

IOCA1

ICDDAT/

ICSPDAT

—

ANA1 VREF

C1IN0-

C2IN0-

ICDCLK/

ICSPCLK

CLCIN0⁽¹⁾

RA2

RA3

RA4

ANA2 VREF-

—

DAC1REF-

—

T0CKI⁽¹⁾CCP3⁽¹⁾

—

CWG1⁽¹⁾

CWG2⁽¹⁾

—

INT⁽¹⁾

IOCA2

—

IOCA3

MCLR

VPP

T1G⁽¹⁾

T3G⁽¹⁾

T5G⁽¹⁾

SOSCO

IOCA4

CLKOUT

OSC2

CCP4⁽¹⁾

—

ANA4

RA5

ANA5

—

T1CKI⁽¹⁾

T3CKI⁽¹⁾

T5CKI⁽¹⁾

SOSCIN

SOSCI

—

IOCA5

CLKIN

OSC1

RB4

RB5

RB6

RB7

CLCIN2⁽¹⁾

ANB4

ANB5

—

SDI⁽¹⁾

—

IOCB4

IOCB5

—

SDA^(1,3,4)

—

RX⁽¹⁾CLCIN3⁽¹⁾

DT⁽¹⁾

ANB6

ANB7

—

SCK⁽¹⁾

—

IOCB6

IOCB7

—

SCL^(1,3,4)

TX⁽¹⁾

CK⁽¹⁾

—

RC0

RC1

13 ANC0

12 ANC1

—

C2IN0+

IOCC0

IOCC1

—

C1IN1-

C2IN1-

MDCIN1⁽¹⁾

—

RC2

ANC2

—

C1IN2-

C2IN2-

IOCC2

—

Note 1:

Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.

These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

These pins are configured for I²C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard

TTL/ST as selected by the INLVL register.

TABLE 8:

20-PIN ALLOCATION TABLE (PIC16(L)F18344) (CONTINUED)

RC3

RC4

ANC3

—

C1IN3-

C2IN3-

—

MDMIN⁽¹⁾

—

CCP2⁽¹⁾

—

CLCIN1⁽¹⁾

—

IOCC3

IOCC4

—

ANC4

ANC5

ANC6

ANC7

—

CCP1⁽¹⁾

—

RC5

RC6

RC7

VDD

VSS

MDCIN2⁽¹⁾

—

SS⁽¹⁾

—

IOCC5

IOCC6

IOCC7

—

VDD

VSS

—

C1OUT

NCO

—

DSM

TMR0

CCP1

PWM5

CWG1A

CWG2A

SDO

DT⁽³⁾CLC1OUT CLKR

—

C2OUT

—

CCP2

PWM6

CWG1B

CWG2B

SCK

—

CLC2OUT

CLC3OUT

CLC4OUT

—

OUT⁽²⁾

—

CCP3

CCP4

—

CWG1C

CWG2C

SCL⁽³⁾

SDA⁽³⁾

—

CWG1D

CWG2D

Note 1:

Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.

These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

These pins are configured for I²C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard

TTL/ST as selected by the INLVL register.

TABLE 9:

20-PIN ALLOCATION TABLE (PIC16(L)F18345)

RA0

RA1

16 ANA0

—

C1IN0+

—

DAC1OUT

DAC1REF+

—

IOCA0

IOCA1

ICDDAT/

ICSPDAT

—

SS2⁽¹⁾

—

15 ANA1 VREF

C1IN0-

C2IN0-

ICDCLK/

ICSPCLK

T0CKI⁽¹⁾

CLCIN0⁽¹⁾

INT⁽¹⁾

IOCA2

RA2

RA3

RA4

14 ANA2 VREF-

—

DAC1REF-

—

CCP3⁽¹⁾

—

CWG1⁽¹⁾

CWG2⁽¹⁾

—

IOCA3

MCLR

VPP

T1G⁽¹⁾

T3G⁽¹⁾

T5G⁽¹⁾

SOSCO

IOCA4

CLKOUT

OSC2

CCP4⁽¹⁾

—

20 ANA4

RA5

19 ANA5

—

T1CKI⁽¹⁾

T3CKI⁽¹⁾

T5CKI⁽¹⁾

SOSCIN

SOSCI

—

IOCA5

CLKIN

OSC1

RB4

RB5

RB6

RB7

CLCIN2⁽¹⁾

ANB4

ANB5

—

SDI1⁽¹⁾

—

IOCB4

IOCB5

—

SDA1^(1,3,4)

—

SDI2⁽¹⁾

RX⁽¹⁾CLCIN3⁽¹⁾

SDA2^(1,3,4)DT⁽¹⁾

ANB6

ANB7

—

SCK1⁽¹⁾

—

IOCB6

IOCB7

—

SCL1^(1,3,4)

SCK2⁽¹⁾

TX⁽¹⁾

CK⁽¹⁾

SCL2^(1,3,4)

RC0

RC1

13 ANC0

12 ANC1

—

C2IN0+

IOCC0

IOCC1

—

C1IN1-

C2IN1-

MDCIN1⁽¹⁾

MDMIN⁽¹⁾

—

RC2

RC3

ANC2

ANC3

—

C1IN2-

C2IN2-

IOCC2

IOCC3

—

C1IN3-

C2IN3-

CCP2⁽¹⁾

CLCIN1⁽¹⁾

Note 1:

Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.

These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

These pins are configured for I²C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard

TTL/ST as selected by the INLVL register.

TABLE 9:

20-PIN ALLOCATION TABLE (PIC16(L)F18345) (CONTINUED)

RC4

RC5

RC6

RC7

VDD

—

IOCC4

IOCC5

IOCC6

IOCC7

—

ANC4

ANC5

ANC6

ANC7

—

CCP1⁽¹⁾

—

SS⁽¹⁾

—

MDCIN2⁽¹⁾

—

VDD

—

VSS

—

VSS

—

C1OUT

NCO

DSM

TMR0

CCP1

PWM5

CWG1A

CWG2A

SDO1

SDO2

DT⁽³⁾CLC1OUT CLKR

—

C2OUT

—

CCP2

PWM6

CWG1B

CWG2B

SCK1

SCK2

CLC2OUT

—

OUT⁽²⁾

—

CCP3

CCP4

—

CWG1C

CWG2C

SCL1⁽³⁾

SCL2⁽³⁾

SDA1⁽³⁾

SDA2⁽³⁾

—

CLC3OUT

CLC4OUT

—

CWG1D

CWG2D

Note 1:

Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.

These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

These pins are configured for I²C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard

TTL/ST as selected by the INLVL register.

TABLE 10:

20-PIN ALLOCATION TABLE (PIC16(L)F18346)

RA0

RA1

16 ANA0

—

C1IN0+

—

DAC1OUT

DAC1REF+

—

IOCA0

IOCA1

ICDDAT/

ICSPDAT

—

SS2⁽¹⁾

—

15 ANA1 VREF

C1IN0-

C2IN0-

ICDCLK/

ICSPCLK

T0CKI⁽¹⁾

CLCIN0⁽¹⁾

INT⁽¹⁾

IOCA2

RA2

RA3

RA4

14 ANA2 VREF-

—

DAC1REF-

—

CCP3⁽¹⁾

—

CWG1⁽¹⁾

CWG2⁽¹⁾

—

IOCA3

MCLR

VPP

T1G⁽¹⁾

T3G⁽¹⁾

T5G⁽¹⁾

SOSCO

IOCA4

CLKOUT

OSC2

CCP4⁽¹⁾

—

20 ANA4

RA5

19 ANA5

—

T1CKI⁽¹⁾

T3CKI⁽¹⁾

T5CKI⁽¹⁾

SOSCIN

SOSCI

—

IOCA5

CLKIN

OSC1

RB4

RB5

RB6

RB7

CLCIN2⁽¹⁾

ANB4

ANB5

—

SDI1⁽¹⁾

—

IOCB4

IOCB5

—

SDA1^(1,3,4)

—

SDI2⁽¹⁾

RX⁽¹⁾CLCIN3⁽¹⁾

SDA2^(1,3,4)DT⁽¹⁾

ANB6

ANB7

—

SCK1⁽¹⁾

—

IOCB6

IOCB7

—

SCL1^(1,3,4)

SCK2⁽¹⁾

TX⁽¹⁾

CK⁽¹⁾

SCL2^(1,3,4)

RC0

RC1

13 ANC0

12 ANC1

—

C2IN0+

IOCC0

IOCC1

—

C1IN1-

C2IN1-

MDCIN1⁽¹⁾

—

RC2

ANC2

—

C1IN2-

C2IN2-

IOCC2

—

Note 1:

Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.

These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

These pins are configured for I²C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard

TTL/ST as selected by the INLVL register.

TABLE 10:

20-PIN ALLOCATION TABLE (PIC16(L)F18346) (CONTINUED)

RC3

RC4

ANC3

—

C1IN3-

C2IN3-

—

MDMIN⁽¹⁾

—

CCP2⁽¹⁾

—

CLCIN1⁽¹⁾

—

IOCC3

IOCC4

—

ANC4

ANC5

ANC6

ANC7

—

CCP1⁽¹⁾

—

SS⁽¹⁾

—

RC5

RC6

RC7

VDD

VSS

MDCIN2⁽¹⁾

—

IOCC5

IOCC6

IOCC7

—

VDD

VSS

—

C1OUT

NCO

—

DSM

TMR0

CCP1

PWM5

CWG1A

CWG2A

SDO1

SDO2

DT⁽³⁾CLC1OUT CLKR

—

C2OUT

—

CCP2

PWM6

CWG1B

CWG2B

SCK1

SCK2

—

CLC2OUT

CLC3OUT

CLC4OUT

—

OUT⁽²⁾

—

CCP3

CCP4

—

CWG1C

CWG2C

SCL1⁽³⁾

SCL2⁽³⁾

SDA1⁽³⁾

SDA2⁽³⁾

—

CWG1D

CWG2D

Note 1:

Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.

All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.

These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.

These pins are configured for I²C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard

TTL/ST as selected by the INLVL register.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,

LANCheck, MediaLB, MOST, MOST logo, MPLAB,

OptoLyzer, PIC, PICSTART, PIC logo, RightTouch, SpyNIC,

SST, SST Logo, SuperFlash and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

The Embedded Control Solutions Company and mTouch are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,

CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit

Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,

KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB

Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,

PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,

Total Endurance, TSHARC, USBCheck, VariSense,

ViewSpan, WiperLock, Wireless DNA, and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-5224-0183-4

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

== ISO/TS 16949 ==

DS40001744C-page 22

 2014-2016 Microchip Technology Inc.

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07/14/15

 2014-2016 Microchip Technology Inc.

DS40001744C-page 23

PIC16F18325-I/SL [MICROCHIP]

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