PIC16F18326-I/P [MICROCHIP]
RISC MICROCONTROLLER;型号: | PIC16F18326-I/P |
厂家: | MICROCHIP |
描述: | RISC MICROCONTROLLER 时钟 光电二极管 外围集成电路 装置 |
文件: | 总471页 (文件大小:4743K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PIC16(L)F18326/18346
Full-Featured, 14/20 Low Pin Count Microcontrollers with XLP
Description
PIC16(L)F18326/18346 microcontrollers feature Analog, Core Independent Peripherals and Communication
Peripherals, combined with eXtreme Low Power (XLP) for a wide range of general purpose and low-power applications.
The Peripheral Pin Select (PPS) functionality enables pin mapping when using the digital peripherals (CLC, CWG, CCP,
PWM and communications) to add flexibility to the application design.
Core Features
Power-Saving Functionality
• C Compiler Optimized RISC Architecture
• Operating Speed:
- DC – 32 MHz clock input
• IDLE mode: ability to put the CPU core to Sleep
while internal peripherals continue operating from
the system clock
- 125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Up to Four 8-bit Timers
• Up to Three 16-bit Timers
• Low-Current Power-on Reset (POR)
• Power-up Timer (PWRTE)
• DOZE mode: ability to run the CPU core slower
than the system clock used by the internal
peripherals
• SLEEP mode: Lowest Power Consumption
• Peripheral Module Disable (PMD): peripheral
power disable hardware module to minimize
power consumption of unused peripherals
• Brown-out Reset (BOR) Option
• Low-Power BOR (LPBOR) Option
• Extended Watchdog Timer (WDT) with Dedicated
On-Chip Oscillator for Reliable Operation
• Programmable Code Protection
Digital Peripherals
• Configurable Logic Cell (CLC):
- Four CLCs
- Integrated combinational and sequential logic
• Complementary Waveform Generator (CWG):
- Two CWGs
Memory
• 28 Kbytes Program Flash Memory
• 2 KB Data SRAM Memory
• 256B of EEPROM
- Rising and falling edge dead-band control
- Full-bridge, half-bridge, 1-channel drive
- Multiple signal sources
• Direct, Indirect and Relative Addressing Modes
• Capture/Compare/PWM (CCP) modules:
- Four CCPs
- 16-bit resolution for Capture/Compare modes
- 10-bit resolution for PWM mode
• Pulse-Width Modulators (PWM):
- Two 10-bit PWMs
• Numerically Controlled Oscillator (NCO):
- Precision linear frequency generator (@50%
duty cycle) with 0.0001% step size of source
input clock
Operating Characteristics
• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF18326/18346)
- 2.3V to 5.5V (PIC16F18326/18346)
• Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
- Input Clock: 0 Hz < FNCO < 32 MHz
eXtreme Low-Power (XLP) Features
- Resolution: FNCO/220
• Sleep mode: 40 nA @ 1.8V, typical
• Watchdog Timer: 250 nA @ 1.8V, typical
• Secondary Oscillator: 300 nA @ 32 kHz
• Operating Current:
- 8 A @ 32 kHz, 1.8V, typical
- 37 A/MHz @ 1.8V, typical
• Serial Communications:
- EUSART
- RS-232, RS-485, LIN compatible
- Auto-Baud Detect, auto-wake-up on start
- Master Synchronous Serial Port (MSSP)
- SPI
- I2C, SMBus, PMBus™ compatible
• Data Signal Modulator (DSM):
- Modulates a carrier signal with digital data to
create custom carrier synchronized output
waveforms
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 1
PIC16(L)F18326/18346
• Up to 18 I/O Pins:
- Individually programmable pull-ups
- Slew rate control
- Interrupt-on-change with edge-select
- Input level selection control (ST or TTL)
- Digital open-drain enable
• Peripheral Pin Select (PPS):
- I/O pin remapping of digital peripherals
• Timer modules:
Analog Peripherals
• 10-bit Analog-to-Digital Converter (ADC):
- 17 external channels
- Conversion available during Sleep
• Comparator:
- Two comparators
- Fixed Voltage Reference at non-inverting
input(s)
- Comparator outputs externally accessible
• 5-bit Digital-to-Analog Converter (DAC):
- 5-bit resolution, rail-to-rail
- Positive Reference Selection
- Unbuffered I/O pin output
- Internal connections to ADCs and
comparators
- Timer0:
- 8/16-bit timer/counter
- Synchronous or asynchronous operation
- Programmable prescaler/postscaler
- Time base for capture/compare function
- Timer1/3/5 with gate control:
- 16-bit timer/counter
- Programmable internal or external clock
sources
- Multiple gate sources
• Voltage Reference:
- Fixed Voltage Reference with 1.024V, 2.048V
and 4.096V output levels Flexible Oscillator
Structure
• High-Precision Internal Oscillator:
- Software-selectable frequency range up to 32
MHz
- ±1% at nominal 4 MHz calibration point
• 4x PLL with External Sources
• Low-Power Internal 31 kHz Oscillator
(LFINTOSC)
- Multiple gate modes
- Time base for capture/compare function
- Timer2/4/6:
-
-
-
8-bit timers
Programmable prescaler/postscaler
Time base for PWM function
• External Low-Power 32 kHz Crystal Oscillator
(SOSC)
• External Oscillator Block with:
- Three Crystal/Resonator modes up to
20 MHz
- Three External Clock modes up to 20 MHz
- Fail-Safe Clock Monitor
- Detects clock source failure
- Oscillator Start-up Timer (OST)
- Ensures stability of crystal oscillator
sources
DS40001839B-page 2
Preliminary
2016-2017 Microchip Technology Inc.
TABLE 1:
PIC16(L)F183XX FAMILY TYPES
Device
PIC16(L)F18313
PIC16(L)F18323
PIC16(L)F18324
PIC16(L)F18325
PIC16(L)F18326
PIC16(L)F18344
PIC16(L)F18345
PIC16(L)F18346
(A)
(A)
(B)
(C)
(D)
(B)
(C)
(D)
3.5
3.5
7
2
2
256
256
256
256
256
256
256
256
256
256
512
1K
6
5
1
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1/1/1 2/2
1/1/1 2/2
1/3/3 4/2
1/3/3 4/2
1/3/3 4/2
1/3/3 4/2
1/3/3 4/2
1/3/3 4/2
1
1
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
2
2
1
2
2
1
1
1
2
2
1
2
2
2
2
4
4
4
4
4
4
1
1
1
1
1
1
1
1
Y
Y
Y
Y
Y
Y
Y
Y
I
I
I
I
I
I
I
I
12
12
12
12
18
18
18
11
11
11
11
17
17
17
4
14
28
7
8
16
4
2K
512
1K
14
28
8
16
2K
Note 1: One pin is input-only.
2: Debugging Methods: (I) – Integrated on Chip; E – using Emulation Header.
Data Sheet Index: (Unshaded devices are described in this document.)
Note A:
DS40001799
DS40001800
DS40001795
DS40001839
PIC16(L)F18313/18323 Data Sheet,Full-Featured, Low Pin Count Microcontrollers with XLP
PIC16(L)F18324/18344 Data Sheet,Full-Featured, Low Pin Count Microcontrollers with XLP
PIC16(L)F18325/18345 Data Sheet,Full-Featured, Low Pin Count Microcontrollers with XLP
PIC16(L)F18326/18346 Data Sheet,Full-Featured, Low Pin Count Microcontrollers with XLP
B:
C:
D:
Note:
For other small form-factor package availability and marking information, visit
http://www.microchip.com/packaging or contact your local sales office.
PIC16(L)F18326/18346
Pin Diagrams
FIGURE 1:
14-PIN PDIP, SOIC, TSSOP
14
13
12
11
10
9
VSS
1
2
3
4
5
6
7
VDD
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RA5
RA4
VPP/MCLR/RA3
RC5
RC0
RC1
RC2
RC4
RC3
8
Note:
See Table 2 for location of all peripheral functions.
FIGURE 2:
16-PIN UQFN (4x4)
1
12
RA5
RA4
RA0/ICSPDAT
2
11 RA1/ICSPCLK
10
PIC16(L)F18326
3
RA3/MCLR/VPP
RC5 4
RA2
RC0
9
Note 1: See Table 2 for location of all peripheral functions.
2: It is recommended that the exposed bottom pad be connected to VSS, but must not be the main VSS connection
to the device.
FIGURE 3:
20-PIN PDIP, SOIC, SSOP
VSS
VDD
1
2
3
4
5
20
19
18
17
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RA5
RA4
MCLR/VPP/RA3
RC5
16 RC0
RC1
RC2
RB4
15
14
13
RC4
6
RC3
RC6
7
8
12 RB5
11
RC7
RB7
9
RB6
10
Note:
See Table 3 for location of all peripheral functions.
DS40001839B-page 4
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
FIGURE 4:
20-PIN UQFN (4x4)
1
MCLR/VPP/RA3
RA1/ICSPCLK
RA2
PIC16(L)F1834613 RC0
15
14
RC5 2
3
4
RC4
RC3
RC1
RC2
12
11
RC6 5
Note 1: See Table 3 for location of all peripheral functions.
2: It is recommended that the exposed bottom pad be connected to VSS, but must not be the main VSS connection to the device.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 5
Pin Allocation Tables
TABLE 2: 14/16-PIN ALLOCATION TABLE (PIC16(L)F18326)
ICDDAT/
ICSPDAT
RA0
RA1
13
12
12
11
ANA0
—
C1IN0+
—
—
DAC1OUT
DAC1REF+
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SS2(1)
—
—
—
—
—
—
—
IOC
IOC
Y
Y
C1IN0-
C2IN0-
ICDCLK/
ICSPCLK
ANA1 VREF+
ANA2 VREF-
CWG1IN(1)
CWG2IN(1)
INT(1)
IOC
RA2
RA3
RA4
11
4
10
3
—
—
—
—
—
—
DAC1REF-
T0CKI(1) CCP3(1)
—
—
—
—
—
—
—
—
—
—
—
—
Y
Y
Y
—
MCLR
VPP
—
—
—
—
—
—
—
—
—
—
IOC
IOC
T1G(1)
SOSCO
CLKOUT
OSC2
3
2
ANA4
T1CKI(1)
SOSCIN
SOSCI
CLKIN
OSC1
RA5
2
1
ANA5
—
—
—
—
—
—
—
—
—
—
CLCIN3(1)
—
IOC
Y
SCK1(1)
RC0
RC1
RC2
RC3
RC4
10
9
9
8
7
6
5
ANC0
ANC1
ANC2
ANC3
ANC4
—
—
—
—
—
C2IN0+
—
—
—
—
—
—
—
—
—
—
—
—
T5CKI(1)
—
—
CCP4(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOC
IOC
IOC
IOC
IOC
Y
Y
Y
Y
Y
—
—
—
—
—
SCL1(1,3,4)
C1IN1-
C2IN1-
SDI1(1)
CLCIN2(1)
—
SDA1(1,3,4)
C1IN2-
C2IN2-
8
MDCIN1(1)
MDMIN(1)
—
—
—
C1IN3-
C2IN3-
7
T5G(1)
T3G(1)
SS1(1)
CLCIN0(1)
CLCIN1(1)
CCP2(1)
—
SCK2(1)
6
—
SCL2(1,3,4)
SDI2(1)
MDCIN2(1) T3CKI(1)
—
—
—
—
RX(1)
—
—
—
—
—
IOC
—
Y
—
CCP1(1)
—
RC5
VDD
5
1
4
ANC5
—
—
—
—
—
—
—
—
—
SDA2(1,3,4)
VDD
16
—
—
—
—
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
3:
4:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to the other pins (e.g., RA5) will operate, but logic levels will be standard TTL/
ST as selected by the INLVL register.
TABLE 2:
14/16-PIN ALLOCATION TABLE (PIC16(L)F18326) (CONTINUED)
VSS
14
—
13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VSS
—
CWG1A
CWG2A
SDA1(3)
SDA2(3)
C1OUT
NCO1
DSM
TMR0
CCP1
PWM5
CK
CLC1OUT CLKR
CWG1B
CWG2B
SCL1(3)
SCL2(3)
—
—
—
—
C2OUT
—
—
—
—
CCP2
PWM6
DT
CLC2OUT
—
—
—
—
OUT(2)
CWG1C
CWG2C
SDO1
SDO2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CCP3
CCP4
—
—
TX
—
CLC3OUT
CLC4OUT
—
—
—
—
—
—
—
—
CWG1D
CWG2D
SCK1
SCK2
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
3:
4:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to the other pins (e.g., RA5) will operate, but logic levels will be standard TTL/
ST as selected by the INLVL register.
TABLE 3:
20-PIN ALLOCATION TABLE (PIC16(L)F18346)
ICDDAT
ICSPDAT
RA0
RA1
19
16 ANA0
—
C1IN0+
—
—
DAC1OUT
DAC1REF+
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOC
IOC
Y
Y
—
—
C1IN0-
C2IN0-
ICDCLK
ICSPCLK
18
15 ANA1 VREF+
14 ANA2 VREF-
—
SS2
CWG1IN(1)
CWG2IN(1)
IOC
RA2
RA3
17
4
—
—
—
—
DAC1REF-
—
—
—
T0CKI(1) CCP3(1)
—
—
—
—
—
—
CLCIN0(1)
—
—
—
Y
Y
—
INT(1)
MCLR
VPP
1
—
—
—
—
—
—
IOC
IOC
T1G(1)
T3G(1)
T5G(1)
SOSCO
T1CKI(1)
T3CKI(1)
T5CKI(1)
SOSCIN
SOSCI
CLKOUT
OSC2
—
—
—
—
—
—
—
—
CCP4(1)
—
—
—
—
—
—
—
—
—
—
—
RA4
RA5
3
2
20 ANA4
Y
Y
CLKIN
OSC1
19 ANA5
10 ANB4
—
—
—
IOC
SDI1(1)
RB4
RB5
RB6
13
12
11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RX(1)
—
CLCIN2(1)
CLCIN3(1)
—
—
—
—
IOC
IOC
IOC
Y
Y
Y
—
—
—
SDA1(1,3,4)
SDI2(1)
9
8
7
ANB5
ANB6
ANB7
SDA2(1,3,4)
SCK1(1)
SCL1(1,3,4)
SCK2(1)
RB7
RC0
RC1
10
16
15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOC
IOC
IOC
Y
Y
Y
—
—
—
SCL2(1,3,4)
13 ANC0
12 ANC1
C2IN0+
—
—
C1IN1-
C2IN1-
C1IN2-
C2IN2-
MDCIN1(1)
—
—
—
—
—
—
—
—
RC2
14
11 ANC2
—
IOC
Y
—
—
—
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
3:
4:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
TABLE 3:
20-PIN ALLOCATION TABLE (PIC16(L)F18346) (CONTINUED)
C1IN3-
C2IN3-
RC3
RC4
7
4
3
ANC3
—
—
—
MDMIN(1)
—
CCP2(1)
—
—
—
—
CLCIN1(1)
—
IOC
IOC
Y
Y
—
—
6
ANC4
ANC5
ANC6
ANC7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CCP1(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SS1(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RC5
RC6
RC7
VDD
VSS
5
8
2
5
MDCIN2(1)
IOC
IOC
IOC
—
Y
Y
—
—
—
—
—
—
9
6
—
—
Y
—
1
18
17
VDD
VSS
—
—
—
—
20
—
—
—
—
CWG1A
CWG2A
SDO1
SDO2
DT
CK
TX
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C1OUT
C2OUT
—
NCO1
—
—
—
—
—
DSM
—
TMR0
—
CCP1
CCP2
CCP3
CCP4
PWM5
PWM6
—
CLC1OUT CLKR
—
—
—
—
—
—
—
—
—
—
—
—
CWG1B
CWG2B
SCK1
SCK2
CLC2OUT
CLC3OUT
CLC4OUT
—
—
—
OUT(2)
CWG1C
CWG2C
SCL1(3)
SCL2(3)
—
—
—
SDA1(3)
SDA2(3)
CWG1D
CWG2D
—
—
—
—
—
Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
3:
4:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard
TTL/ST as selected by the INLVL register.
PIC16(L)F18326/18346
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 12
2.0 Guidelines for Getting Started With PIC16(L)F183XX Microcontrollers..................................................................................... 22
3.0 Enhanced Mid-Range CPU........................................................................................................................................................ 25
4.0 Memory Organization................................................................................................................................................................. 27
5.0 Device Configuration .................................................................................................................................................................. 63
6.0 Resets ........................................................................................................................................................................................ 70
7.0 Oscillator Module........................................................................................................................................................................ 78
8.0 Interrupts .................................................................................................................................................................................... 96
9.0 Power-Saving Operation Modes .............................................................................................................................................. 112
10.0 Watchdog Timer (WDT) ........................................................................................................................................................... 119
11.0 Nonvolatile Memory (NVM) Control.......................................................................................................................................... 123
12.0 I/O Ports ................................................................................................................................................................................... 140
13.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 160
14.0 Peripheral Module Disable ....................................................................................................................................................... 166
15.0 Interrupt-on-Change................................................................................................................................................................. 172
16.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 179
17.0 Temperature Indicator Module ................................................................................................................................................. 182
18.0 Comparator Module.................................................................................................................................................................. 184
19.0 Pulse-Width Modulation (PWM) ............................................................................................................................................... 193
20.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 199
21.0 Configurable Logic Cell (CLC).................................................................................................................................................. 221
22.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 236
23.0 Numerically Controlled Oscillator (NCO1) Module ................................................................................................................... 250
24.0 5-bit Digital-to-Analog Converter (DAC1) Module .................................................................................................................... 261
25.0 Data Signal Modulator (DSM) Module...................................................................................................................................... 265
26.0 Timer0 Module ......................................................................................................................................................................... 276
27.0 Timer1/3/5 Module with Gate Control....................................................................................................................................... 283
28.0 Timer 2/4/6 Module .................................................................................................................................................................. 296
29.0 Capture/Compare/PWM Modules ............................................................................................................................................ 301
30.0 Master Synchronous Serial Port (MSSPx) Module .................................................................................................................. 313
31.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART1) ............................................................. 366
32.0 Reference Clock Output Module .............................................................................................................................................. 391
33.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 394
34.0 Instruction Set Summary.......................................................................................................................................................... 396
35.0 Electrical Specifications............................................................................................................................................................ 410
36.0 DC and AC Characteristics Graphs and Charts....................................................................................................................... 440
37.0 Development Support............................................................................................................................................................... 441
38.0 Packaging Information.............................................................................................................................................................. 445
Appendix A: Data Sheet Revision History.......................................................................................................................................... 467
The Microchip Website....................................................................................................................................................................... 468
Customer Change Notification Service .............................................................................................................................................. 468
Customer Support.............................................................................................................................................................................. 468
Product Identification System............................................................................................................................................................. 469
DS40001839B-page 10
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
TO OUR VALUED CUSTOMERS
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2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 11
PIC16(L)F18326/18346
1.0
DEVICE OVERVIEW
TABLE 1-1:
DEVICE PERIPHERAL
SUMMARY
The PIC16(L)F18326/18346 devices are described
within this data sheet. PIC16(L)F18326 are available in
14-pin PDIP, SOIC, TSSOP and 16-pin UQFN
packages. PIC16(L)F18346 are available in 20-pin
PDIP, SOIC, SSOP and UQFN packages. See
Section 38.0 “Packaging Information” for further
packaging information. Figure 1-1 shows a block
diagram of the PIC16(L)F18326/18346 devices.
Table 1-2 shows the pinout descriptions.
Peripheral
Analog-to-Digital Converter (ADC)
Temperature Indicator
●
●
●
●
Digital-to-Analog Converter (DAC)
Reference Table 1-1 for peripherals available per device.
DAC1
●
●
Fixed Voltage Reference (FVR)
ADCFVR
CDAFVR
●
●
●
●
Digital Signal Modulator (DSM)
DSM1
NCO1
●
●
●
●
Numerically Controlled Oscillator (NCO)
Capture/Compare/PWM (CCP) Modules
CCP1
CCP2
CCP3
CCP4
●
●
●
●
●
●
●
●
Comparators
C1
C2
●
●
●
●
Complementary Waveform Generator (CWG)
Configurable Logic Cell (CLC)
CWG1
CWG2
●
●
●
●
CLC1
CLC2
CLC3
CLC4
●
●
●
●
●
●
●
●
Enhanced Universal Synchronous/Asynchronous Receiver/Transmit-
ter (EUSART)
EUSART1
●
●
Master Synchronous Serial Port (MSSP)
Pulse-Width Modulator (PWM)
Timers (TMR)
MSSP1
MSSP2
●
●
●
●
PWM5
PWM6
●
●
●
●
TMR0
TMR1
TMR2
TMR3
TMR4
TMR5
TMR6
●
●
●
●
●
●
●
●
●
●
●
●
●
●
DS40001839B-page 12
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
FIGURE 1-1:
PIC16(L)F18326/18346 BLOCK DIAGRAM
Program
Flash Memory
RAM
PORTA
PORTB(1)
PORTC
CLKOUT
CLKIN
Timing
Generation
HFINTOSC/
LFINTOSC
Oscillator
CPU
See Figure 3-1
MCLR
DSM
NCO1
PWMs
Timer0
Timer1/3/5
Timer2/4/6
MSSP1/2
Comparators
CWG1/2
Temp.
Indicator
ADC
10-bit
FVR
CLCs
DAC
CCPs
EUSART1
Note 1: PIC16(L)F18346 only.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 13
PIC16(L)F18326/18346
TABLE 1-2:
PIC16(L)F18326 PINOUT DESCRIPTION
Input
Type
Name
Function
Output Type
Description
General purpose I/O.
RA0/ANA0/C1IN0+/DAC1OUT/
SS2 / ICDDAT/ICSPDAT
RA0
ANA0
TTL/ST
AN
CMOS
―
(1)
ADC Channel A0 input.
C1IN0+
DAC1OUT
SS2
AN
―
Comparator C1 positive input.
Digital-to-Analog Converter output.
Slave Select 2 input.
―
AN
TTL/ST
TTL/ST
TTL/ST
TTL/ST
AN
―
ICDDAT
ICSPDAT
RA1
CMOS
CMOS
CMOS
―
In-Circuit Debug Data I/O.
ICSP™ Data I/O.
RA1/ANA1/VREF+/C1IN0-/
C2IN0-/DAC1REF+/ ICDCLK/
ICSPCLK
General purpose I/O.
ANA1
ADC Channel A1 input.
VREF+
C1IN0-
C2IN0-
DAC1REF+
ICDCLK
ICSPCLK
RA2
AN
―
ADC positive voltage reference input.
Comparator C1 negative input.
Comparator C2 negative input.
Digital-to-Analog Converter positive reference input.
In-Circuit Debug Clock I/O.
ICSP Clock I/O.
AN
—
AN
―
―
AN
TTL/ST
TTL/ST
TTL/ST
AN
CMOS
CMOS
CMOS
―
RA2/ANA2/VREF-/ DAC1REF-/
General purpose I/O.
(1)
(1)
(1)
T0CKI / CCP3 /CWG1IN
/
ANA2
ADC Channel A2 input.
(1)
(1)
CWG2IN /INT
VREF-
AN
―
ADC negative voltage reference input.
Digital-to-Analog Converter negative reference input.
TMR0 Clock input.
DAC1REF-
T0CKI
CCP3
―
AN
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
HV
―
CMOS
―
Capture/Compare/PWM 3 input.
Complementary Waveform Generator 1 input.
Complementary Waveform Generator 2 input.
External interrupt input.
CWG1IN
CWG2IN
INT
―
―
RA3/MCLR/VPP
RA3
CMOS
―
General purpose I/O.
MCLR
VPP
Master Clear with internal pull-up.
Programming voltage.
―
(1)
RA4/ANA4/T1G / SOSCO/
CLKOUT/OSC2
RA4
TTL/ST
AN
CMOS
―
General purpose I/O.
ANA4
ADC Channel A4 input.
T1G
ST
―
TMR1 gate input.
SOSCO
CLKOUT
OSC2
―
XTAL
CMOS
XTAL
Secondary Oscillator connection.
FOSC/4 output.
―
―
Crystal/Resonator (LP, XT, HS modes).
Legend: AN = Analog input or output CMOS=CMOS compatible input or output
TTL= TTL compatible input ST =Schmitt Trigger input with CMOS levels I C =Schmitt Trigger input with I C
HV = High Voltage XTAL =Crystal levels
OD =Open-Drain
2
2
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output
selection registers. See Register 13-2.
2
3: These I C functions are bidirectional. The output pin selections must be the same as the input pin selections.
DS40001839B-page 14
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
TABLE 1-2:
PIC16(L)F18326 PINOUT DESCRIPTION (CONTINUED)
Input
Type
Name
Function
Output Type
Description
(1)
RA5/ANA5/T1CKI / SOSCIN/
RA5
ANA5
T1CKI
SOSCIN
SOSCI
CLCIN3
CLKIN
OSC1
RC0
TTL/ST
AN
CMOS
―
General purpose I/O.
(1)
SOSCI/ CLCIN3 /CLKIN/
ADC Channel A5 input.
OSC1
TTL/ST
TTL/ST
XTAL
―
TMR1 Clock input.
―
Secondary Oscillator input connection.
Secondary Oscillator connection.
Configurable Logic Cell 3 input.
External clock input.
―
TTL/ST
TTL/ST
XTAL
―
―
―
Crystal/Resonator (LP, XT, HS modes).
General purpose I/O.
(1)
RC0/ANC0/C2IN0+/ T5CKI
/
TTL/ST
AN
CMOS
―
(1)
(1,3)
SCK1 / SCL1
ANC0
C2IN0+
T5CKI
SCK1
SCL1
ADC Channel C0 input.
Comparator C2 positive input.
TMR5 Clock input.
AN
―
TTL/ST
TTL/ST
―
CMOS
OD
CMOS
―
SPI Clock 1.
2
2
I C
I C Clock 1.
RC1/ANC1/C1IN1-/C2IN1-/
CCP4 /SDI1 / SDA1
RC1
TTL/ST
AN
General purpose I/O.
(1)
(1)
(1,3)
/
ANC1
C1IN1-
C2IN1-
CCP4
SDI1
ADC Channel C1 input.
(1)
CLCIN2
AN
―
Comparator C1 negative input.
Comparator C2 negative input.
Capture/Compare/PWM 4 input.
SPI Data input 1.
AN
―
TTL/ST
TTL/ST
CMOS
CMOS
OD
―
2
2
SDA1
CLCIN2
RC2
I C
I C Data 1.
TTL/ST
TTL/ST
AN
Configurable Logic Cell 2 input.
General purpose I/O.
RC2/ANC2/C1IN2-/C2IN2-/
CMOS
―
(1)
MDCIN1
ANC2
C1IN2-
C2IN2-
MDCIN1
RC3
ADC Channel C2 input.
AN
―
Comparator C1 negative input.
Comparator C2 negative input.
Modular Carrier input 1.
General purpose I/O.
AN
―
TTL/ST
TTL/ST
AN
―
RC3/ANC3/C1IN3-/C2IN3-/
MDMIN /T5G / CCP2
CMOS
―
(1)
(1)
(1)
/
ANC3
C1IN3-
C2IN3-
MDMIN
T5G
ADC Channel C3 input.
(1)
(1)
SS1 /CLCIN0
AN
―
Comparator C1 negative input.
Comparator C2 negative input.
Modular Source input.
AN
―
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
―
―
TMR5 gate input.
CCP2
SS1
CMOS
―
Capture/Compare/PWM 2 input.
Slave Select 1 input.
CLCIN0
―
Configurable Logic Cell 0 input.
Legend: AN = Analog input or output CMOS=CMOS compatible input or output
TTL= TTL compatible input ST =Schmitt Trigger input with CMOS levels I C =Schmitt Trigger input with I C
HV = High Voltage XTAL =Crystal levels
OD =Open-Drain
2
2
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output
selection registers. See Register 13-2.
2
3: These I C functions are bidirectional. The output pin selections must be the same as the input pin selections.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 15
PIC16(L)F18326/18346
TABLE 1-2:
PIC16(L)F18326 PINOUT DESCRIPTION (CONTINUED)
Input
Type
Name
Function
Output Type
Description
(1)
(1)
RC4/ANC4/T3G / SCK2
SCL2
/
RC4
ANC4
T3G
TTL/ST
AN
CMOS
―
General purpose I/O.
(1,3)
(1)
/ CLCIN1
ADC Channel C4 input.
TMR3 gate input.
SPI Clock 2.
TTL/ST
TTL/ST
―
SCK2
SCL2
CLCIN1
RC5
CMOS
OD
2
2
I C
I C Clock 2.
TTL/ST
TTL/ST
AN
―
Configurable Logic Cell 1 input.
General purpose I/O.
ADC Channel C5 input.
Modular Carrier input 2.
TMR3 Clock input.
(1)
RC5/ANC5/MDCIN2
/
CMOS
―
(1)
(1)
(1)
T3CKI /CCP1 /SDI2
/
ANC5
MDCIN2
T3CKI
CCP1
SDI2
SDA2
RX
(1,3)
(1)
SDA2
/RX /DT
TTL/ST
TTL/ST
TTL/ST
TTL/ST
―
―
CMOS
CMOS
OD
Capture/Compare/PWM 1 input.
SPI Data 2.
2
2
I C
I C Data 2.
TTL/ST
TTL/ST
Power
Power
CMOS
CMOS
―
EUSART asynchronous input.
EUSART synchronous data output.
Positive supply.
DT
VDD
VSS
VDD
VSS
―
Ground reference.
Legend: AN = Analog input or output CMOS=CMOS compatible input or output
TTL= TTL compatible input ST =Schmitt Trigger input with CMOS levels I C =Schmitt Trigger input with I C
HV = High Voltage XTAL =Crystal levels
OD =Open-Drain
2
2
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output
selection registers. See Register 13-2.
2
3: These I C functions are bidirectional. The output pin selections must be the same as the input pin selections.
DS40001839B-page 16
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
TABLE 1-2:
PIC16(L)F18326 PINOUT DESCRIPTION (CONTINUED)
Input
Type
Name
Function
Output Type
Description
(2)
OUT
C1
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
OD
Comparator C1 output.
C2
Comparator C2 output.
NCO1
DSM
Numerically Controlled Oscillator output.
Digital Signal Modulator output.
TMR0
TMR0 clock output.
CCP1
Capture/Compare/PWM 1 output.
CCP2
Capture/Compare/PWM 2 output.
CCP3
Capture/Compare/PWM 3 output.
CCP4
Capture/Compare/PWM 4 output.
PWM5
PWM6
CWG1A
CWG2A
CWG1B
CWG2B
CWG1C
CWG2C
CWG1D
CWG2D
Pulse-Width Modulator 5 output.
Pulse-Width Modulator 6 output.
Complementary Waveform Generator 1 output A.
Complementary Waveform Generator 2 output A.
Complementary Waveform Generator 1 output B.
Complementary Waveform Generator 2 output B.
Complementary Waveform Generator 1 output C.
Complementary Waveform Generator 2 output C.
Complementary Waveform Generator 1 output D.
Complementary Waveform Generator 2 output D.
(3)
2
2
SDA1
I C
I C data output.
(3)
2
2
SDA2
I C
OD
I C data output.
(3)
2
2
SCL1
I C
OD
I C clock output.
(3)
2
2
SCL2
I C
OD
I C clock output.
SDO1
SD02
―
―
―
―
―
―
―
―
―
―
―
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
SPI1 data output.
SPI2 data output.
SCK1
SPI1 clock output.
SCK2
SPI2 clock output.
TX/CK
Asynchronous TX data/synchronous clock output.
EUSART synchronous data output.
Configurable Logic Cell 1 source output.
Configurable Logic Cell 2 source output.
Configurable Logic Cell 3 source output.
Configurable Logic Cell 4 source output.
Clock Reference output.
DT
CLC1OUT
CLC2OUT
CLC3OUT
CLC4OUT
CLKR
Legend: AN = Analog input or output CMOS=CMOS compatible input or output
TTL= TTL compatible input ST =Schmitt Trigger input with CMOS levels I C =Schmitt Trigger input with I C
HV = High Voltage XTAL =Crystal levels
OD =Open-Drain
2
2
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output
selection registers. See Register 13-2.
2
3: These I C functions are bidirectional. The output pin selections must be the same as the input pin selections.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 17
PIC16(L)F18326/18346
TABLE 1-3:
PIC16(L)F18346 PINOUT DESCRIPTION
Input
Type
Output
Type
Name
Function
Description
RA0/ANA0/C1IN0+/DAC1OUT/
ICDDAT/ICSPDAT
RA0
ANA0
TTL/ST
AN
CMOS
―
General purpose I/O.
ADC Channel A0 input.
C1IN0+
DAC1OUT
ICDDAT
ICSPDAT
RA1
AN
―
Comparator C1 positive input.
Digital-to-Analog Converter output.
In-Circuit Debug Data I/O.
ICSP™ Data I/O.
―
AN
TTL/ST
TTL/ST
TTL/ST
AN
CMOS
CMOS
CMOS
―
RA1/ANA1/VREF+/C1IN0-/
C2IN0-/ DAC1REF+/SS2 )/
ICDCLK/ ICSPCLK
General purpose I/O.
(1)
ANA1
ADC Channel A1 input.
VREF+
C1IN0-
C2IN0-
DAC1REF+
SS2
AN
―
ADC positive voltage reference input.
Comparator C1 negative input.
Comparator C2 negative input.
Digital-to-Analog Converter positive reference input.
Slave Select 2 input.
AN
—
AN
―
AN
―
TTL/ST
TTL/ST
TTL/ST
TTL/ST
AN
―
ICDCLK
ICSPCLK
RA2
CMOS
CMOS
CMOS
―
In-Circuit Debug Clock I/O.
ICSP Clock I/O.
RA2/ANA2/VREF-/ DAC1REF-/
General purpose I/O.
(1)
(1)
(1)
T0CKI / CCP3 /CWG1IN
/
ANA2
ADC Channel A2 input.
(1)
(1)
(1)
CWG2IN /CLCIN0 / INT
VREF-
AN
―
ADC negative voltage reference input.
Digital-to-Analog Converter negative reference input.
TMR0 Clock input.
DAC1REF-
T0CKI
CCP3
AN
―
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
HV
―
CMOS
―
Capture/Compare/PWM 3 input.
Complementary Waveform Generator 1 input.
Complementary Waveform Generator 2 input.
Configurable Logic Cell 0 input.
External interrupt input.
CWG1IN
CWG2IN
CLCIN0
INT
―
―
―
RA3/MCLR/VPP
RA3
CMOS
―
General purpose I/O.
MCLR
VPP
Master Clear with internal pull-up.
Programming voltage.
―
(1)
RA4/ANA4/T1G(1)/T3G
T5G /SOSCO/CCP4
CLKOUT/OSC2
/
RA4
TTL/ST
AN
CMOS
―
General purpose I/O.
(1)
(1)
/
ANA4
ADC Channel A4 input.
T1G
TTL/ST
TTL/ST
TTL/ST
―
―
TMR1 gate input.
T3G
―
TMR3 gate input.
T5G
―
TMR5 gate input.
SOSCO
CCP4
XTAL
CMOS
CMOS
XTAL
Secondary Oscillator connection.
Capture/Compare/PWM 4 input.
FOSC/4 output.
TTL/ST
―
CLKOUT
OSC2
―
Crystal/Resonator (LP, XT, HS modes).
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I C = Schmitt Trigger input with I C
HV = High Voltage XTAL = Crystal levels
OD = Open-Drain
2
2
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-2.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output
selection registers. See Register 13-2.
2
3: These I C functions are bidirectional. The output pin selections must be the same as the input pin selections.
DS40001839B-page 18
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
TABLE 1-3:
PIC16(L)F18346 PINOUT DESCRIPTION (CONTINUED)
Input
Type
Output
Type
Name
Function
Description
(1)
(1)
RA5/ANA5/T1CKI / T3CKI
/
RA5
ANA5
T1CKI
T3CKI
T5CKI
SOSCIN
SOSCI
CLKIN
OSC1
RB4
TTL/ST
AN
CMOS
―
General purpose I/O.
ADC Channel A5 input.
TMR1 Clock input.
TMR3 Clock input.
TMR5 Clock input.
(1)
T5CKI / SOSCIN/SOSCI/
CLKIN/OSC1
TTL/ST
TTL/ST
TTL/ST
TTL/ST
XTAL
―
―
―
―
Secondary Oscillator input connection.
Secondary Oscillator connection.
External clock input.
―
TTL/ST
XTAL
―
―
Crystal/Resonator (LP, XT, HS modes).
General purpose I/O.
(1)
(1,3)
RB4/ANB4/SDI1 / SDA1
/
TTL/ST
AN
CMOS
―
(1)
CLCIN2
ANB4
SDI1
ADC Channel B4 input.
TTL/ST
CMOS
OD
SPI Data input 1.
2
2
SDA1
CLCIN2
RB5
I C
I C Data 1.
TTL/ST
TTL/ST
AN
―
Configurable Logic Cell 2 input.
General purpose I/O.
ADC Channel B5 input.
SPI Data input 2.
(1)
(1,3)
RB5/ANB5/SDI2 / SDA2
/
CMOS
―
(1)
(1)
RX /DT/CLCIN3
ANB5
SDI2
TTL/ST
CMOS
OD
2
2
SDA2
RX
I C
I C Data 2.
TTL/ST
TTL/ST
TTL/ST
TTL/ST
AN
CMOS
CMOS
―
EUSART asynchronous input.
EUSART synchronous data output.
Configurable Logic Cell 3 input.
General purpose I/O.
DT
CLCIN3
RB6
(1)
(1,3)
(1,3)
RB6/ANB6/SCK1 / SCL1
CMOS
―
ANB6
SCK1
SCL1
RB7
ADC Channel B6 input.
SPI Clock 1.
TTL/ST
CMOS
OD
2
2
I C
I C Clock 1.
(1)
RB7/ANB7/SCK2 / SCL2
TTL/ST
AN
CMOS
―
General purpose I/O.
ADC Channel B7 input.
SPI Clock 2.
ANB7
SCK2
SCL2
RC0
TTL/ST
CMOS
OD
2
2
I C
I C Clock 2.
RC0/ANC0/C2IN0+
TTL/ST
AN
CMOS
―
General purpose I/O.
ANC0
C2IN0+
RC1
ADC Channel C0 input.
AN
―
Comparator C2 positive input.
General purpose I/O.
RC1/ANC1/C1IN1-/C2IN1-
TTL/ST
AN
CMOS
―
ANC1
C1IN1-
C2IN1-
RC2
ADC Channel C1 input.
AN
―
Comparator C1 negative input.
Comparator C2 negative input.
General purpose I/O.
AN
―
RC2/ANC2/C1IN2-/C2IN2-/
TTL/ST
AN
CMOS
―
(1)
MDCIN1
ANC2
C1IN2-
C2IN2-
MDCIN1
ADC Channel C2 input.
AN
―
Comparator C1 negative input.
Comparator C2 negative input.
Modular Carrier input 1.
AN
―
TTL/ST
―
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I C = Schmitt Trigger input with I C
HV = High Voltage XTAL = Crystal levels
OD = Open-Drain
2
2
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-2.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output
selection registers. See Register 13-2.
2
3: These I C functions are bidirectional. The output pin selections must be the same as the input pin selections.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 19
PIC16(L)F18326/18346
TABLE 1-3:
PIC16(L)F18346 PINOUT DESCRIPTION (CONTINUED)
Input
Type
Output
Type
Name
Function
Description
RC3/ANC3/C1IN3-/C2IN3-/
MDMIN / CCP2 /CLCIN1
RC3
ANC3
C1IN3-
C2IN3-
MDMIN
CCP2
CLCIN1
RC4
TTL/ST
AN
CMOS
―
General purpose I/O.
(1)
(1)
(1)
/
ADC Channel C3 input.
AN
―
Comparator C1 negative input.
Comparator C2 negative input.
Modular Source input.
Capture/Compare/PWM 2 input.
Configurable Logic Cell 1 input.
General purpose I/O.
AN
―
TTL/ST
TTL/ST
TTL/ST
TTL/ST
AN
―
CMOS
―
RC4/ANC4
CMOS
―
ANC4
RC5
ADC Channel C4 input.
General purpose I/O.
(1)
(1)
RC5/ANC5/MDCIN2 / CCP1
TTL/ST
AN
CMOS
―
ANC5
MDCIN2
CCP1
RC6
ADC Channel C5 input.
Modular Carrier input 2.
Capture/Compare/PWM 1 input.
General purpose I/O.
TTL/ST
TTL/ST
TTL/ST
AN
―
CMOS
CMOS
―
(1)
RC6/ANC6/SS1
ANC6
SS1
ADC Channel C6 input.
Slave Select 1 input.
TTL/ST
TTL/ST
AN
―
RC7/ANC7
RC7
CMOS
―
General purpose I/O.
ANC7
VDD
ADC Channel C7 input.
Positive supply.
VDD
VSS
Power
Power
―
VSS
―
Ground reference.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I C = Schmitt Trigger input with I C
HV = High Voltage XTAL = Crystal levels
OD = Open-Drain
2
2
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-2.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output
selection registers. See Register 13-2.
2
3: These I C functions are bidirectional. The output pin selections must be the same as the input pin selections.
DS40001839B-page 20
Preliminary
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PIC16(L)F18326/18346
TABLE 1-3:
PIC16(L)F18346 PINOUT DESCRIPTION (CONTINUED)
Input
Type
Output
Type
Name
Function
Description
(2)
OUT
C1
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
OD
Comparator C1 output.
Comparator C2 output.
C2
NCO1
DSM
Numerically Controlled Oscillator output.
Digital Signal Modulator output.
TMR0
Timer0 clock output.
CCP1
Capture/Compare/PWM 1 output.
CCP2
Capture/Compare/PWM 2 output.
CCP3
Capture/Compare/PWM 3 output.
CCP4
Capture/Compare/PWM 4 output.
PWM5
PWM6
CWG1A
CWG2A
CWG1B
CWG2B
CWG1C
CWG2C
CWG1D
CWG2D
Pulse-Width Modulator 5 output.
Pulse-Width Modulator 6 output.
Complementary Waveform Generator 1 output A.
Complementary Waveform Generator 2 output A.
Complementary Waveform Generator 1 output B.
Complementary Waveform Generator 2 output B.
Complementary Waveform Generator 1 output C.
Complementary Waveform Generator 2 output C.
Complementary Waveform Generator 1 output D.
Complementary Waveform Generator 2 output D.
(3)
2
2
SDA1
I C
I C data output.
(3)
2
2
SDA2
I C
OD
I C data output.
(3)
2
2
SCL1
I C
OD
I C clock output.
(3)
2
2
SCL2
I C
OD
I C clock output.
SDO1
SD02
―
―
―
―
―
―
―
―
―
―
―
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
SPI1 data output.
SPI2 data output.
SCK1
SPI1 clock output.
SCK2
SPI2 clock output.
TX/CK
Asynchronous TX data/synchronous clock output.
EUSART synchronous data output.
Configurable Logic Cell 1 source output.
Configurable Logic Cell 2 source output.
Configurable Logic Cell 3 source output.
Configurable Logic Cell 4 source output.
Clock Reference output.
DT
CLC1OUT
CLC2OUT
CLC3OUT
CLC4OUT
CLKR
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I C = Schmitt Trigger input with I C
HV = High Voltage XTAL = Crystal levels
OD = Open-Drain
2
2
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-2.
2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output
selection registers. See Register 13-2.
2
3: These I C functions are bidirectional. The output pin selections must be the same as the input pin selections.
2016-2017 Microchip Technology Inc.
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PIC16(L)F18326/18346
2.2
Power Supply Pins
2.0
GUIDELINES FOR GETTING
STARTED WITH
PIC16(L)F183XX
2.2.1
DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins (VDD and VSS) is required. All VDD
and VSS pins must be connected. None can be left
floating.
MICROCONTROLLERS
2.1
Basic Connection Requirements
Consider the following criteria when using decoupling
capacitors:
Getting started with the PIC16(L)F183XX family of 8-bit
microcontrollers requires attention to a minimal set of
device pin connections before proceeding with
development.
• Value and type of capacitor: A 0.1 µF (100 nF),
10-25V capacitor is recommended. The capacitor
should be a low-ESR device, with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
• Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type
capacitor in parallel to the above described
decoupling capacitor. The value of the second
capacitor can be in the range of 0.01 µF to
0.001 µF. Place this second capacitor next to
each primary decoupling capacitor. In high-speed
circuit designs, consider implementing a decade
pair of capacitances as close to the power and
ground pins as possible (e.g., 0.1 µF in parallel
with 0.001 µF).
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
The following pins must always be connected:
• All VDD and VSS pins
(see Section 2.2 “Power Supply Pins”)
• MCLR pin (when configured for external
operation)
(see Section 2.3 “Master Clear (MCLR) Pin”)
These pins must also be connected if they are being
used in the end application:
• ICSPCLK/ICSPDAT pins used for In-Circuit Serial
Programming™
(ICSP™)
and
debugging
purposes (see Section 2.4 “ICSP™ Pins”)
• OSC1 and OSC2 pins when an external oscillator
source is used
(see Section 2.5 “External Oscillator Pins”)
Additionally, the following pins may be required:
• VREF+/VREF- pins are used when external voltage
reference for analog modules is implemented
The minimum mandatory connections are shown in
Figure 2-1.
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTIONS
(Note 1)
VDD
C2
R1
R2
MCLR/VPP
minimum,
thereby
reducing
PCB
trace
inductance.
C1
PIC16(L)F1xxx
2.2.2
TANK CAPACITORS
VSS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits, including microcontrollers, to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 µF to 47 µF.
Key (all values are recommendations):
C1 and C2: 0.1 PF, V ceramic
16
R1: 10 kȍ
R2: 100ȍ to 470ȍ
Note1: Only when MCLRE configuration bit is 1 and the
MCLR pin does not have a weak pull-up.
DS40001839B-page 22
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2.3
Master Clear (MCLR) Pin
2.4
ICSP™ Pins
The MCLR pin provides three specific device functions:
The ICSPCLK and ICSPDAT pins are used for
In-Circuit Serial Programming™ (ICSP™) and
debugging purposes. It is recommended to keep the
trace length between the ICSP connector and the ICSP
pins on the device as short as possible. If the ICSP
connector is expected to experience an ESD event, a
series resistor is recommended, with the value in the
range of a few tens of ohms, not to exceed 100Ω.
• Device Reset (when MCLRE = 1)
• Digital input pin (when MCLRE = 0)
• Device Programming and Debugging
If programming and debugging are not required in the
end application then either set the MCLRE
Configuration bit to ‘1’ and use the pin as a digital input
or clear the MCLRE Configuration bit and leave the pin
open to use the internal weak pull-up. The addition of
other components, to help increase the application’s
resistance to spurious Resets from voltage sags, may
be beneficial. A typical configuration is shown in
Figure 2-1. Other circuit designs may be implemented,
depending on the application’s requirements.
Pull-up resistors, series diodes and capacitors on the
ICSPCLK and ICSPDAT pins are not recommended as
they will interfere with the programmer/debugger
communications to the device. If such discrete
components are an application requirement, they
should be isolated from the programmer by resistors
between the application and the device pins or
removed from the circuit during programming.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits, and pin input voltage high
(VIH) and input low (VIL) requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must be
considered. Device programmers and debuggers drive
the MCLR pin. Consequently, specific voltage levels
(VIH and VIL) and fast signal transitions must not be
adversely affected. Therefore, the programmer
MCLR/VPP output should be connected directly to the
pin so that R1 isolates the capacitor, C1 from the MCLR
pin during programming and debugging operations.
For device emulation, ensure that the “Communication
Channel Select” (i.e., ICSPCLK/ICSPDAT pins),
programmed into the device, matches the physical
connections for the ICSP to the Microchip debugger/
emulator tool.
Any components associated with the MCLR pin should
be placed within 0.25 inch (6 mm) of the pin.
For more information on available Microchip
development tools connection requirements, refer to
Section 37.0 “Development Support”.
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PIC16(L)F18326/18346
2.5
External Oscillator Pins
2.6
Unused I/Os
Many microcontrollers have options for at least two
oscillators: a high-frequency primary oscillator and a
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output logic low.
low-frequency
secondary
oscillator
(refer to
Section 7.0 “Oscillator Module” for details).
The oscillator circuit should be placed on the same side
of the board as the device. Place the oscillator circuit
close to the respective oscillator pins with no more than
0.5 inch (12 mm) between the circuit components and
the pins. The load capacitors should be placed next to
the oscillator itself, on the same side of the board.
FIGURE 2-2:
SUGGESTED
PLACEMENT OF THE
OSCILLATOR CIRCUIT
Single-Sided and In-Line Layouts:
Use a grounded copper pour around the oscillator
circuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.
Copper Pour
Primary Oscillator
Crystal
(tied to ground)
DEVICE PINS
Primary
OSC1
OSC2
GND
Oscillator
C1
Layout suggestions are shown in Figure 2-2. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to
completely surround the pins and components. A
suitable solution is to tie the broken guard sections to a
mirrored ground layer. In all cases, the guard trace(s)
must be returned to ground.
`
`
C2
SOSCO
SOSCI
Secondary Oscillator
(SOSC)
`
Crystal
In planning the application’s routing and I/O
assignments, ensure that adjacent port pins, and other
signals in close proximity to the oscillator, are benign
(i.e., free of high frequencies, short rise and fall times,
and other similar noise).
SOSC: C2
SOSC: C1
Fine-Pitch (Dual-Sided) Layouts:
For additional information and design guidance on
oscillator circuits, refer to these Microchip Application
Notes, available at the corporate website
(www.microchip.com):
Top Layer Copper Pour
(tied to ground)
Bottom Layer
Copper Pour
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC™ and PICmicro® Devices”
• AN849, “Basic PICmicro® Oscillator Design”
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
(tied to ground)
OSCO
• AN949, “Making Your Oscillator Work”
C2
Oscillator
Crystal
GND
C1
OSCI
DEVICE PINS
DS40001839B-page 24
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PIC16(L)F18326/18346
Relative Addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
3.0
ENHANCED MID-RANGE CPU
This family of devices contains an enhanced mid-range
8-bit CPU core. The CPU has 48 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16-levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
• Automatic Interrupt Context Saving
• 16-level Stack with Overflow and Underflow
• File Select Registers
• Instruction Set
FIGURE 3-1:
CORE BLOCK DIAGRAM
Rev. 10-000055B
8/23/2016
15
Configuration
Data Bus
8
15
Program Counter
Flash
Program
Memory
16-Level Stack
RAM
(15-bit)
14
Program
Bus
12
Program Memory
Read (PMR)
RAM Addr
Addr MUX
Instruction Reg
Indirect
Addr
Direct Addr
7
12
5
12
BSR Reg
15
FSR0 Reg
STATUS Reg
MUX
15
FSR1 Reg
8
3
Power-up
Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode and
Control
ALU
8
OSC1/CLKIN
Brown-out
Reset
OSC2/CLKOUT
SOSCI
Timing
Generation
W Reg
SOSCO
VDD
VSS
Internal
Oscillator
Block
2016-2017 Microchip Technology Inc.
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3.1
Automatic Interrupt Context
Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 8.5 “Automatic Context Saving”
for more information.
3.2
16-Level Stack with Overflow and
Underflow
These devices have a hardware stack memory 15 bits
wide and 16 words deep. A Stack Overflow or
Underflow will set the appropriate bit (STKOVF or
STKUNF) in the PCON register, and if enabled, will
cause a software Reset. See Section 4.4 “Stack” for
more details.
3.3
File Select Registers
There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers, program memory, and data
EEPROM, which allows one Data Pointer for all mem-
ory. When an FSR points to program memory, there is
one additional instruction cycle in instructions using
INDF to allow the data to be fetched. General purpose
memory can now also be addressed linearly, providing
the ability to access contiguous data larger than 80
bytes. There are also new instructions to support the
FSRs. See Section 4.5 “Indirect Addressing” for
more details.
3.4
Instruction Set
There are 48 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 34.0 “Instruction Set Summary” for more
details.
DS40001839B-page 26
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4.0
MEMORY ORGANIZATION
These devices contain the following types of memory:
• Program Memory
- Configuration Words
- Device ID
- Revision ID
- User ID
- Program Flash Memory
• Data Memory
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
• Data EEPROM
The following features are associated with access and
control of program memory and data memory:
• PCL and PCLATH
• Stack
• Indirect Addressing
• NVMREG Access
4.1
Program Memory Organization
The enhanced mid-range core has a 15-bit program
counter capable of addressing 32K x 14 program
memory space. Table 4-1 shows the memory sizes
implemented. Accessing
a location above these
boundaries will cause a wrap-around within the
implemented memory space. The Reset vector is at
0000h and the interrupt vector is at 0004h (see
Figure 4-1).
TABLE 4-1:
DEVICE SIZES AND ADDRESSES
Device Program Memory Size (Words)
Last Program Memory Address
PIC16(L)F18326/18346
16384
3FFFh
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PIC16(L)F18326/18346
FIGURE 4-1:
PROGRAM MEMORY MAP
AND STACK FOR
4.1.1
READING PROGRAM MEMORY AS
DATA
PIC16(L)F18326/18346
There are three methods of accessing constants in
program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory. The third method
is to use the NVMCON registers to access the program
memory.
PC<14:0>
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
15
Stack Level 0
Stack Level 1
4.1.1.1
RETLWInstruction
The RETLWinstruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 4-1.
Stack Level 15
Reset Vector
0000h
EXAMPLE 4-1:
RETLW INSTRUCTION
constants
BRW
;Add Index in W to
;program counter to
;select data
;Index0 data
;Index1 data
Interrupt Vector
Page 0-3
0004h
0005h
On-chip
Program
Memory
RETLW DATA0
RETLW DATA1
RETLW DATA2
RETLW DATA3
3FFFh
4000h
Rollover to Page 0
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
call constants
;… THE CONSTANT IS IN W
The BRW instruction makes this type of table very
simple to implement. If your code must remain portable
with previous generations of microcontrollers, the
computed GOTO method must be used because the
BRWinstruction is not available in some devices, such
as the PIC16F6XX, PIC16F7XX, PIC16F8XX, and
PIC16F9XX devices.
Rollover to Page 0
7FFFh
DS40001839B-page 28
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Data memory uses a 12-bit address. The upper five bits
of the address define the Bank address and the lower
seven bits select the registers/RAM in that bank.
4.1.1.2
Indirect Read with FSR
The program memory can be accessed as data by
setting bit 7 of an FSRxH register and reading the
matching INDFx register. The MOVIW instruction will
place the lower eight bits of the addressed word in the
W register. Writes to the program memory cannot be
performed via the INDF registers. Instructions that read
the program memory via the FSR require one extra
FIGURE 4-2:
BANKED-MEMORY
PARTITIONING
Memory Region
7-bit Bank Offset
00h
instruction
cycle
to
complete.
Example 4-2
demonstrates accessing the program memory via an
FSR.
Core Registers
(12 bytes)
The HIGH directive will set bit 7 if a label points to a
location in the program memory.
0Bh
0Ch
Special Function Registers
EXAMPLE 4-2:
ACCESSING PROGRAM
MEMORY VIA FSR
1Fh
20h
constants
RETLW DATA0
RETLW DATA1
RETLW DATA2
RETLW DATA3
my_function
;Index0 data
;Index1 data
General Purpose RAM
(80 bytes maximum)
;… LOTS OF CODE…
MOVLW
MOVWF
MOVLW
MOVWF
MOVIW
LOW constants
FSR1L
HIGH constants
FSR1H
0[FSR1]
6Fh
70h
;THE PROGRAM MEMORY IS IN W
Common RAM
(16 bytes)
4.1.1.3
NVMREG Access
7Fh
The NVMREG interface allows read/write access to all
locations accessible by the FSRs, User ID locations,
and EEPROM. The NVMREG interface also provides
read-only access to Device ID, Revision ID, and
Configuration data. See Section 11.4 “NVMREG
Access” for more information.
4.2.2
CORE REGISTERS
The core registers contain the registers that directly
affect basic operation. The core registers occupy the
first 12 addresses of every data memory bank
(addresses x00h/x80h through x0Bh/x8Bh). These
registers are listed below in Table 4-2. For detailed
information, see Table 4-4.
4.2
Data Memory Organization
The data memory is partitioned into 32 memory banks
with 128 bytes in each bank. Each bank consists of
(Figure 4-2):
TABLE 4-2:
Addresses
x00h or x80h
CORE REGISTERS
• 12 core registers
BANKx
• Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
x01h or x81h
x02h or x82h
x03h or x83h
x04h or x84h
x05h or x85h
x06h or x86h
x07h or x87h
x08h or x88h
x09h or x89h
x0Ah or x8Ah
x0Bh or x8Bh
4.2.1
BANK SELECTION
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 4.5 “Indirect
Addressing”” for more information.
WREG
PCLATH
INTCON
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For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u= unchanged).
4.2.2.1
STATUS Register
The STATUS register, shown in Register 4-1, contains:
• The arithmetic status of the ALU
• The Reset status
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 4.0
“Memory Organization”).
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: The C and DC bits operate as Borrow
and Digit Borrow out bits, respectively, in
subtraction.
REGISTER 4-1:
STATUS: STATUS REGISTER
U-0
—
U-0
—
U-0
—
R-1/q
TO
R-1/q
PD
R/W-0/u
Z
R/W-0/u
DC(1)
R/W-0/u
C(1)
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-5
bit 4
Unimplemented: Read as ‘0’
TO: Time-Out bit
1= After power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT Time-out occurred
bit 3
bit 2
bit 1
bit 0
PD: Power-Down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWFinstructions)(1)
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
DS40001839B-page 30
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
4.2.3
SPECIAL FUNCTION REGISTERS
4.2.4
GENERAL PURPOSE RAM
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The Special Function
Registers occupy the 20 bytes after the core registers of
every data memory bank (addresses x0Ch/x8Ch
through x1Fh/x9Fh), with the exception of banks 27, 28,
and 29 (PPS and CLC registers). The registers
associated with the operation of the peripherals are
described in the appropriate peripheral chapter of this
data sheet.
There are up to 80 bytes of GPR in each data memory
bank. The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 4.5.2
“Linear Data Memory” for more information.
4.2.5
COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
4.2.6
DEVICE MEMORY MAPS
The memory maps for PIC16(L)F18326/18346 are as
shown in Table 4-4.
TABLE 4-3:
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (ALL BANKS)(1)
Value on all
other
Resets
Bank
Offset
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Banks
000h
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a
physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
001h
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a
physical register)
002h
003h
004h
005h
006h
007h
008h
009h
00Ah
00Bh
Legend:
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR4
BSR3
BSR2
BSR1
—
BSR0
WREG
PCLATH
INTCON
Working Register
—
Write Buffer for the upper 7 bits of the Program Counter
PEIE
GIE
—
—
—
—
INTEDG 00-- ---1 00-- ---1
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented,
read as ‘0’.
Note 1: These registers can be accessed from any bank.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 31
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0
CPU CORE REGISTERS; see Table 4-2 for specifics
00Ch
00Dh
PORTA
PORTB
—
—
RA5
RA4
RA3
RA2
RA1
RA0
--xx xxxx --uu uuuu
X
—
Unimplemented
—
—
— X
RB7
—
RB6
—
RB5
RC5
RC5
RB4
RC4
RC4
—
—
—
—
xxxx ---- uuuu ----
--xx xxxx --uu uuuu
xxxx xxxx uuuu uuuu
00Eh
PORTC
X
—
RC3
RC3
RC2
RC2
RC1
RC1
RC0
RC0
— X
—
RC7
RC6
00Fh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
—
Unimplemented
—
—
PIR0
—
—
TMR0IF
RCIF
IOCIF
TXIF
—
—
—
INTF
--00 ---0 --00 ---0
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx xxxx xxxx
1111 1111 1111 1111
0-00 0000 0-00 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 00-0 uuuu uu-u
PIR1
TMR1GIF
TMR6IF
OSFIF
ADIF
SSP1IF
SSP2IF
CLC4IF
CCP4IF
BCL1IF
BCL2IF
CLC3IF
CCP3IF
TMR2IF
TMR4IF
CLC2IF
CCP2IF
TMR1IF
NCO1IF
CLC1IF
CCP1IF
PIR2
C2IF
C1IF
NVMIF
TMR3IF
TMR5IF
PIR3
CSWIF
CWG1IF
TMR3GIF
TMR5GIF
PIR4
CWG2IF
TMR0L
TMR0H
T0CON0
T0CON1
TMR1L
TMR1H
T1CON
TMR0L<7:0>
TMR0H<7:0>
T016BIT
T0ASYNC
TMR1L<7:0>
TMR1H<7:0>
T1SOSC
T0EN
—
T0OUT
T0OUTPS<3:0>
T0CKPS<3:0>
T0CS<2:0>
TMR1CS<1:0>
T1CKPS<1:0>
T1GTM T1GSPM
T1SYNC
—
TMR1ON
T1GGO/
DONE
01Ch
T1GCON
TMR1GE
T1GPOL
T1GVAL
T1GSS<1:0>
0000 0x00 uuuu uxuu
01Dh
01Eh
01Fh
TMR2
PR2
TMR2<7:0>
PR2<7:0>
0000 0000 0000 0000
1111 1111 1111 1111
-000 0000 -000 0000
T2CON
—
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 1
CPU CORE REGISTERS; see Table 4-2 for specifics
08Ch
08Dh
TRISA
TRISB
—
—
TRISA5
TRISA4
—
TRISA2
TRISA1
TRISA0
--11 -111 --11 -111
X
—
Unimplemented
—
—
— X
TRISB7
—
TRISB6
—
TRISB5
TRISC5
TRISC5
TRISB4
TRISC4
TRISC4
—
—
—
—
1111 ---- 1111 ----
--11 1111 --11 1111
1111 1111 1111 1111
08Eh
TRISC
X
—
TRISC3
TRISC3
TRISC2
TRISC2
TRISC1
TRISC1
TRISC0
TRISC0
— X
—
TRISC7
TRISC6
08Fh
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
09Fh
—
Unimplemented
—
—
PIE0
—
―
TMR0IE
RCIE
IOCIE
TXIE
—
—
—
INTE
--00 ---0 --00 ---0
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
PIE1
TMR1GIE
TMR6IE
OSFIE
ADIE
SSP1IE
SSP2IE
CLC4IE
CCP4IE
BCL1IE
BCL2IE
CLC3IE
CCP3IE
TMR2IE
TMR4IE
CLC2IE
CCP2IE
TMR1IE
NCO1IE
CLC1IE
CCP1IE
PIE2
C2IE
C1IE
NVMIE
TMR3IE
TMR5IE
PIE3
CSWIE
CWG1IE
TMR3GIE
TMR5GIE
PIE4
CWG2IE
—
—
—
Unimplemented
Unimplemented
WDTPS<4:0>
—
—
—
—
—
WDTCON
—
—
—
SWDTEN
--01 0110 --01 0110
—
—
—
Unimplemented
Unimplemented
Unimplemented
ADRES<7:0>
ADRES<9:8>
—
—
—
—
—
—
—
—
ADRESL
ADRESH
ADCON0
ADCON1
ADACT
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 -000 0000 -000
---0 0000 ---0 0000
CHS<5:0>
GO/DONE
ADON
ADFM
—
ADCS<2:0>
—
—
ADNREF
ADPREF<1:0>
—
ADACT<4:0>
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 2
CPU CORE REGISTERS; see Table 4-2 for specifics
10Ch
10Dh
LATA
LATB
—
—
LATA5
LATA4
—
LATA2
LATA1
LATA0
--xx -xxx --uu -uuu
X
—
Unimplemented
—
—
— X
LATB7
—
LATB6
—
LATB5
LATC5
LATC5
LATB4
LATC4
LATC4
—
—
—
—
xxxx ---- uuuu ----
--xx xxxx --uu uuuu
xxxx xxxx uuuu uuuu
10Eh
LATC
X
—
LATC3
LATC3
LATC2
LATC2
LATC1
LATC1
LATC0
LATC0
— X
—
LATC7
LATC6
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
—
Unimplemented
Unimplemented
C1POL
—
—
—
—
—
—
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
FVRCON
DACCON0
DACCON1
C1ON
C1INTP
C2ON
C2INTP
—
C1OUT
C1INTN
C2OUT
C2INTN
—
—
—
—
C1SP
C2SP
C1HYS
C1NCH<2:0>
C2HYS
C1SYNC
C2SYNC
00-0 -100 00-0 -100
0000 0000 0000 0000
00-0 -100 00-0 -100
0000 0000 0000 0000
---- --00 ---- --00
1--- ---q u--- ---u
0q00 0000 0q00 0000
0-0- 00-0 0-0- 00-0
---0 0000 ---0 0000
C1PCH<2:0>
C2POL
—
C2PCH<2:0>
C2NCH<2:0>
MC2OUT
—
—
—
—
—
—
—
—
—
MC1OUT
BORRDY
SBOREN
FVREN
DAC1EN
—
—
FVRRDY
—
TSEN
DAC1OE
—
TSRNG
—
CDAFVR<1:0>
DAC1PSS<1:0>
DAC1R<4:0>
ADFVR<1:0>
—
DAC1NSS
—
11Ah to
11Fh
—
—
Unimplemented
—
—
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 3
CPU CORE REGISTERS; see Table 4-2 for specifics
18Ch
18Dh
ANSELA
ANSELB
―
―
ANSA5
ANSA4
―
ANSA2
ANSA1
ANSA0
--xx -xxx --uu -uuu
X
―
Unimplemented
—
—
― X
X
ANSB7
―
ANSB6
―
ANSB5
ANSC5
ANSC5
ANSB4
ANSC4
ANSC4
―
―
―
―
xxxx ---- uuuu ----
--xx xxxx --uu uuuu
xxxx xxxx uuuu uuuu
18Eh
ANSELC
ANSC3
ANSC3
ANSC2
ANSC2
ANSC1
ANSC1
ANSC0
ANSC0
― X
―
ANSC7
ANSC6
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
―
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
―
―
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
―
―
―
―
―
―
―
―
―
―
―
―
(1)
VREGCON
―
―
―
―
―
―
―
VREGPM
Reserved
---- --01 ---- --01
―
Unimplemented
RC1REG<7:0>
TX1REG<7:0>
SP1BRG<7:0>
SP1BRG<15:8>
—
—
RC1REG
TX1REG
SP1BRGL
SP1BRGH
RC1STA
TX1STA
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 000x 0000 000x
0000 0010 0000 0010
01-0 0-00 01-0 0-00
SPEN
CSRC
RX9
TX9
SREN
TXEN
—
CREN
ADDEN
SENDB
BRG16
FERR
BRGH
—
OERR
TMRT
WUE
RX9D
TX9D
SYNC
SCKP
BAUD1CON
ABDOVF
RCIDL
ABDEN
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 4
CPU CORE REGISTERS; see Table 4-2 for specifics
20Ch
20Dh
WPUA
WPUB
―
―
WPUA5
WPUA4
WPUA3
WPUA2
WPUA1
WPUA0
--00 0000 --00 0000
X
―
Unimplemented
―
―
― X
WPUB7
―
WPUB6
―
WPUB5
WPUC5
WPUC5
WPUB4
WPUC4
WPUC4
―
―
―
―
0000 ---- 0000 ----
--00 0000 --00 0000
0000 0000 0000 0000
20Eh
WPUC
X
―
WPUC3
WPUC3
WPUC2
WPUC2
WPUC1
WPUC1
WPUC0
WPUC0
― X
―
WPUC7
WPUC6
20Fh
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
―
Unimplemented
―
―
―
―
―
―
Unimplemented
SSP1BUF<7:0>
SSP1ADD<7:0>
SSP1MSK<7:0>
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON1
SSP1CON2
SSP1CON3
―
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
SMP
WCOL
GCEN
ACKTIM
CKE
SSPOV
ACKSTAT
PCIE
D/A
P
S
R/W
UA
BF
SSPEN
ACKDT
SCIE
CKP
ACKEN
BOEN
SSPM<3:0>
RCEN
PEN
RSEN
AHEN
SEN
SDAHT
SBCDE
DHEN
―
Unimplemented
―
―
SSP2BUF
SSP2ADD
SSP2MSK
SSP2STAT
SSP2CON1
SSP2CON2
SSP2CON3
SSP2BUF<7:0>
SSP2ADD<7:0>
SSP2MSK<7:0>
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
SMP
WCOL
GCEN
ACKTIM
CKE
SSPOV
ACKSTAT
PCIE
D/A
P
S
R/W
UA
BF
SSPEN
ACKDT
SCIE
CKP
ACKEN
BOEN
SSPM<3:0>
RCEN
PEN
RSEN
AHEN
SEN
SDAHT
SBCDE
DHEN
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 5
CPU CORE REGISTERS; see Table 4-2 for specifics
28Ch
28Dh
ODCONA
ODCONB
―
―
ODCA5
ODCA4
―
ODCA2
ODCA1
ODCA0
--00 -000 --00 -000
X
―
Unimplemented
―
―
― X
ODCB7
―
ODCB6
―
ODCB5
ODCC5
ODCC5
ODCB4
ODCC4
ODCC4
―
―
―
―
0000 ---- 0000 ----
--00 0000 --00 0000
0000 0000 0000 0000
28Eh
ODCONC
X
―
ODCC3
ODCC3
ODCC2
ODCC2
ODCC1
ODCC1
ODCC0
ODCC0
― X
—
ODCC7
ODCC6
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
―
Unimplemented
―
―
―
―
―
―
Unimplemented
CCPR1<7:0>
CCPR1<15:8>
CCPR1L
CCPR1H
CCP1CON
CCP1CAP
CCPR2L
CCPR2H
CCP2CON
CCP2CAP
―
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0-x0 0000 0-x0 0000
---- 0000 ---- xxxx
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0-x0 0000 0-x0 0000
---- 0000 ---- xxxx
CCP1EN
―
CCP1OUT
CCP1FMT
CCP1MODE<3:0>
―
―
―
CCP1CTS<3:0>
CCPR2<7:0>
CCPR2<15:8>
CCP2FMT
CCP2EN
―
―
CCP2OUT
CCP2MODE<3:0>
CCP2CTS<3:0>
―
―
―
―
―
―
―
―
―
Unimplemented
―
―
―
―
―
―
―
―
―
―
―
―
―
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
―
―
―
―
CCPTMRS
C4TSEL<1:0>
C3TSEL<1:0>
C2TSEL<1:0>
C1TSEL<1:0>
0101 0101 0101 0101
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 6
CPU CORE REGISTERS; see Table 4-2 for specifics
30Ch
30Dh
SLRCONA
SLRCONB
―
―
SLRA5
SLRA4
―
SLRA2
SLRA1
SLRA0
--11 -111 --11 -111
X
―
Unimplemented
―
―
― X
SLRB7
―
SLRB6
―
SLRB5
SLRC5
SLRC5
SLRB4
SLRC4
SLRC4
―
―
―
―
1111 ---- 1111 ----
--11 1111 --11 1111
1111 1111 1111 1111
30Eh
SLRCONC
X
―
SLRC3
SLRC3
SLRC2
SLRC2
SLRC1
SLRC1
SLRC0
SLRC0
― X
―
SLRC7
SLRC6
30Fh
310h
311h
312h
313h
314h
315h
316h
317h
318h
―
Unimplemented
―
―
―
―
―
―
Unimplemented
CCPR3<7:0>
CCPR3<15:8>
CCPR3L
CCPR3H
CCP3CON
CCP3CAP
CCPR4L
CCPR4H
CCP4CON
CCP4CAP
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0-x0 0000 0-x0 0000
---- 0000 ---- xxxx
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0-x0 0000 0-x0 0000
---- 0000 ---- xxxx
CCP3EN
―
―
CCP3OUT
CCP3FMT
CCP3MODE<3:0>
―
―
―
CCP3CTS<3:0>
CCPR4<7:0>
CCPR4<15:8>
CCP4FMT
CCP4EN
―
―
CCP4OUT
CCP4MODE<3:0>
CCP4CTS<3:0>
―
―
―
319h to
31Fh
―
―
Unimplemented
―
―
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 7
CPU CORE REGISTERS; see Table 4-2 for specifics
38Ch
38Dh
INLVLA
INLVLB
―
―
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
--11 1111 --11 1111
X
―
Unimplemented
―
―
― X
INLVLB7
―
INLVLB6
―
INLVLB5
INLVLC5
INLVLC5
INLVLB4
INLVLC4
INLVLC4
―
―
―
―
1111 ---- 1111 ----
--11 1111 --11 1111
1111 1111 1111 1111
38Eh
INLVLC
X
―
INLVLC3
INLVLC3
INLVLC2
INLVLC2
INLVLC1
INLVLC1
INLVLC0
INLVLC0
― X
―
INLVLC7
INLVLC6
38Fh
390h
391h
392h
393h
394h
―
Unimplemented
Unimplemented
―
―
―
―
―
―
IOCAP
IOCAN
IOCAF
IOCBP
―
―
―
―
―
―
IOCAP5
IOCAN5
IOCAF5
IOCAP4
IOCAP3
IOCAN3
IOCAF3
IOCAP2
IOCAN2
IOCAF2
IOCAP1
IOCAN1
IOCAF1
IOCAP0
IOCAN0
IOCAF0
--00 0000 --00 0000
--00 0000 --00 0000
--00 0000 --00 0000
IOCAN4
IOCAF4
X
―
Unimplemented
―
―
― X
IOCBP7
IOCBN7
IOCBP6
IOCBN6
IOCBP5
IOCBN5
IOCBP4
―
―
―
―
―
―
―
―
0000 ---- 0000 ----
395h
396h
397h
398h
399h
IOCBN
IOCBF
IOCCP
IOCCN
IOCCF
X
―
Unimplemented
―
―
― X
IOCBN4
0000 ---- 0000 ----
X
―
Unimplemented
―
―
― X
IOCBF7
―
IOCBF6
―
IOCBF5
IOCCP5
IOCCP5
IOCCN5
IOCCN5
IOCCF5
IOCCF5
IOCBF4
IOCCP4
IOCCP4
IOCCN4
IOCCN4
IOCCF4
IOCCF4
―
―
―
―
0000 ---- 0000 ----
--00 0000 --00 0000
0000 0000 0000 0000
--00 0000 --00 0000
0000 0000 0000 0000
--00 0000 --00 0000
0000 0000 0000 0000
X
―
IOCCP3
IOCCP3
IOCCN3
IOCCN3
IOCCF3
IOCCF3
IOCCP2
IOCCP2
IOCCN2
IOCCN2
IOCCF2
IOCCF2
IOCCP1
IOCCP1
IOCCN1
IOCCN1
IOCCF1
IOCCF1
IOCCP0
IOCCP0
IOCCN0
IOCCN0
IOCCF0
IOCCF0
― X
IOCCP7
―
IOCCP6
―
X
―
― X
IOCCN7
―
IOCCN6
―
X
―
― X
IOCCF7
IOCCF6
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 7
CPU CORE REGISTERS; see Table 4-2 for specifics
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
CLKRCON
―
CLKREN
―
―
CLKRDC<1:0>
Unimplemented
CLKRDIV<2:0>
0--1 0000 0--1 0001
―
―
―
MDCON
MDSRC
MDCARH
MDCARL
MDEN
―
―
―
MDOPOL
MDOUT
―
―
MDBIT
0--0 0--0 0--0 0--0
---- xxxx 0--- uuuu
-xx- xxxx -uu- uuuu
-xx- xxxx -uu- uuuu
―
―
―
―
―
MDMS<3:0>
―
MDCHPOL
MDCLPOL
MDCHSYNC
MDCLSYNC
MDCH<3:0>
MDCL<3:0>
―
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 8
CPU CORE REGISTERS; see Table 4-2 for specifics
40Ch to
―
―
Unimplemented
―
―
410h
411h
412h
413h
TMR3L
TMR3H
TMR3L<7:0>
TMR3H<7:0>
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 00-0 uuuu uu-u
T3CON
TMR3CS<1:0>
T3CKPS<1:0>
T3SOSC
T3SYNC
T3GVAL
―
TMR3ON
T3GGO/
DONE
414h
T3GCON
TMR3GE
T3GPOL
T3GTM T3GSPM
T3GSS<1:0>
0000 0x00 uuuu uxuu
415h
416h
417h
418h
419h
41Ah
TMR4
TMR4<7:0>
0000 0000 0000 0000
1111 1111 1111 1111
-000 0000 -000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 00-0 uuuu uu-u
PR4
PR4<7:0>
T4CON
TMR5L
TMR5H
T5CON
―
T4OUTPS<3:0>
T5CKPS<1:0>
TMR4ON
T4CKPS<1:0>
TMR5L<7:0>
TMR5H<7:0>
TMR5CS<1:0>
T5SOSC
T5SYNC
T5GVAL
―
TMR5ON
T5GGO/
DONE
41Bh
T5GCON
TMR5GE
T5GPOL
T5GTM
T5GSPM
T5GSS<1:0>
0000 0x00 uuuu uxuu
41Ch
41Dh
41Eh
41Fh
TMR6
PR6
TMR6<7:0>
0000 0000 0000 0000
1111 1111 1111 1111
-000 0000 -000 0000
PR6<7:0>
T6CON
―
―
T6OUTPS<3:0>
TMR6ON
T6CKPS<1:0>
―
Unimplemented
―
―
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 9
CPU CORE REGISTERS; see Table 4-2 for specifics
48Ch to
―
―
Unimplemented
―
―
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
49Fh
NCO1ACCL
NCO1ACCH
NCO1ACCU
NCO1INCL
NCO1INCH
NCO1INCU
NCO1CON
NCO1CLK
NCO1ACC<7:0>
NCO1ACC<15:8>
0000 0000 0000 0000
0000 0000 0000 0000
---- 0000 ---- 0000
0000 0001 0000 0001
0000 0000 0000 0000
---- 0000 ---- 0000
0-00 ---0 0-00 ---0
000- --00 000- --00
—
―
―
―
NCO1ACC<19:16>
NCO1INC<19:16>
NCO1INC<7:0>
NCO1INC<15:8>
―
―
―
―
―
N1EN
N1OUT
N1POL
―
―
―
―
―
N1PFM
N1PWS<2:0>
―
N1CKS<1:0>
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 10-11
CPU CORE REGISTERS; see Table 4-2 for specifics
50Ch to
―
―
―
Unimplemented
Unimplemented
―
―
―
―
51Fh
58Ch to
―
59Fh
Bank 12
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
PWM5DCL
PWM5DCH
PWM5CON
PWM6DCL
PWM6DCH
PWM6CON
PWM5DC<1:0>
―
―
―
―
―
―
xx-- ---- uu-- ----
xxxx xxxx uuuu uuuu
0-00 ---- 0-00 ----
xx-- ---- uu-- ----
xxxx xxxx uuuu uuuu
0-00 ---- 0-00 ----
PWM5DC<9:2>
PWM5EN
―
PWM5OUT
PWM5POL
―
―
―
―
―
―
―
―
PWM6DC<1:0>
―
―
PWM6DC<9:2>
PWM6EN
―
―
PWM6OUT
PWM6POL
―
―
―
―
61Dh to
61Eh
―
―
Unimplemented
―
―
61Fh
PWMTMRS
―
―
―
P6TSEL<1:0>
P5TSEL<1:0>
---- 0101 ---- 0101
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 13
CPU CORE REGISTERS; see Table 4-2 for specifics
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
―
―
―
―
―
―
―
―
―
―
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
―
―
―
―
―
―
―
―
―
―
CWG1CLKCON
CWG1DAT
CWG1DBR
CWG1DBF
CWG1CON0
CWG1CON1
CWG1AS0
―
―
―
―
―
―
―
―
―
―
CS
---- ---0 ---- ---0
---- 0000 ---- 0000
--00 0000 --00 0000
--00 0000 --00 0000
00-- -000 00-- -000
--x- 0000 --x- 0000
0001 01-- 0001 01--
---0 0000 ---0 0000
0000 0000 0000 0000
―
DAT<3:0>
―
―
DBR<5:0>
DBF<5:0>
―
―
EN
―
LD
―
―
―
―
MODE<2:0>
POLB
―
―
IN
POLD
POLC
POLA
―
SHUTDOWN
―
REN
―
LSBD<1:0>
LSAC<1:0>
AS3E
STRD
CWG1AS1
―
AS4E
AS2E
STRC
AS1E
AS0E
STRA
CWG1STR
OVRD
OVRC
OVRB
OVRA
STRB
69Ah to
69Fh
―
―
Unimplemented
―
―
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 14
CPU CORE REGISTERS; see Table 4-2 for specifics
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
―
―
―
―
―
―
―
―
―
―
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
―
―
―
―
―
―
―
―
―
―
CWG2CLKCON
CWG2DAT
CWG2DBR
CWG2DBF
CWG2CON0
CWG2CON1
CWG2AS0
―
―
―
―
―
―
―
―
―
―
CS
---- ---0 ---- ---0
---- 0000 ---- 0000
--00 0000 --00 0000
--00 0000 --00 0000
00-- -000 00-- -000
--x- 0000 --x- 0000
0001 01-- 0001 01--
---0 0000 ---0 0000
0000 0000 0000 0000
―
DAT<3:0>
―
―
DBR<5:0>
DBF<5:0>
―
―
EN
―
LD
―
―
―
―
MODE<2:0>
POLB
―
―
IN
POLD
POLC
POLA
―
SHUTDOWN
―
REN
―
LSBD<1:0>
LSAC<1:0>
AS3E
STRD
CWG2AS1
―
AS4E
AS2E
STRC
AS1E
AS0E
STRA
CWG2STR
OVRD
OVRC
OVRB
OVRA
STRB
71Ah to
71Fh
―
―
Unimplemented
―
―
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Banks 15-16
CPU CORE REGISTERS; see Table 4-2 for specifics
78Ch to
―
―
―
Unimplemented
Unimplemented
―
―
―
―
79FH
80Ch to
―
81Fh
Bank 17
88Ch
88Dh
88Eh
88Fh
890h
891h
892h
893h
894h
895h
896h
897h
898h
899h
89Ah
89Bh
―
―
―
―
―
―
―
―
―
―
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
NVMADR<7:0>
NVMADR<14:8>
NVMDAT<7:0>
―
―
―
―
―
―
―
―
―
―
NVMADRL
NVMADRH
NVMDATL
NVMDATH
NVMCON1
NVMCON2
―
0000 0000 0000 0000
1000 0000 1000 0000
00000000 0000 0000
--00 0000 --00 0000
-000 x000 -000 q000
0000 0000 0000 0000
―
―
―
―
NVMDAT<13:8>
WRERR WREN
NVMCON2
NVMREGS
LWLO
FREE
WR
RD
―
―
―
―
Unimplemented
Unimplemented
Unimplemented
Unimplemented
―
―
―
―
―
―
―
―
―
―
―
PCON0
STKOVF
STKUNF
―
RWDT
RMCLR
RI
POR
BOR
00-1 110q qq-q qquu
89Ch to
89Fh
―
―
Unimplemented
―
―
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 18
CPU CORE REGISTERS; see Table 4-2 for specifics
90Ch
90Dh
90Eh
90Fh
910h
911h
912h
913h
914h
915h
916h
917h
918h
919h
91Ah
91Bh
91Ch
91Dh
91Eh
91Fh
―
―
―
―
―
―
―
―
―
―
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
―
―
―
―
―
―
―
―
―
―
PMD0
SYSCMD
NCOMD
―
FVRMD
TMR6MD
DACMD
CWG1MD
―
―
―
TMR4MD
―
―
TMR3MD
―
NVMMD
TMR2MD
CMP2MD
CCP3MD
MSSP2MD
CLC2MD
CLKRMD
TMR1MD
CMP1MD
CCP2MD
MSSP1MD
CLC1MD
IOCMD
TMR0MD
―
00-- -000 00-- -000
0--- -000 0--- -000
-00- --0- -00- --0-
-000 --00 -000 --00
--0- --0- --0- --0-
---- -000 ---- -000
PMD1
TMR5MD
ADCMD
PWM6MD
UART1MD
―
PMD2
PMD3
CWG2MD
―
PWM5MD
―
CCP4MD
―
CCP1MD
―
PMD4
PMD5
―
―
CLC4MD
CLC3MD
DSMMD
―
―
Unimplemented
―
―
CPUDOZE
OSCCON1
OSCCON2
OSCCON3
OSCSTAT1
OSCEN
OSCTUNE
OSCFRQ
IDLEN
―
DOZEN
ROI
NOSC<2:0>
COSC<2:0>
SOSCBE
―
DOE
―
DOZE<2:0>
000- -000 000- -000
-qqq 0000 -qqq 0000
-qqq 0000 -qqq 0000
0000 0--- 0000 0---
qq-q qq-q qq-q qq-q
00-0 00-- 00-0 00--
--10 0000 --10 0000
---- -qqq ---- -qqq
NDIV<3:0>
CDIV<3:0>
―
CSWHOLD
EXTOR
EXTOEN
―
SOSCPWR
HFOR
HFOEN
―
ORDY
LFOR
NOSCR
SOR
―
―
―
―
―
PLLR
―
ADOR
―
LFOEN
SOSCEN
ADOEN
HFTUN<5:0>
―
―
―
―
HFFRQ<3:0>
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Banks 19-27
CPU CORE REGISTERS; see Table 4-2 for specifics
98Ch to
—
—
—
—
—
—
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9EFh
A0Ch to
—
A6Fh
A8Ch to
—
AEFh
B0Ch to
—
B6Fh
B8Ch to
—
BEFh
C0Ch to
—
C6Fh
C8Ch to
—
CEFh
D0Ch to
—
D6Fh
D8Ch to
—
DEFh
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 28
CPU CORE REGISTERS; see Table 4-2 for specifics
E0Ch
E0Dh
E0Eh
E0Fh
E10h
E11h
E12h
E13h
E14h
E15h
E16h
E17h
―
―
―
―
―
―
Unimplemented
Unimplemented
Unimplemented
―
―
―
―
―
―
PPSLOCK
INTPPS
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
PPSLOCKED ---- ---0 ---- ---0
---0 0010 ---u uuuu
---0 0010 ---u uuuu
---0 0101 ---u uuuu
---0 0100 ---u uuuu
---1 0011 ---u uuuu
---1 0101 ---u uuuu
---0 0010 ---u uuuu
---1 0001 ---u uuuu
---0 0100 ---u uuuu
---0 0010 ---u uuuu
---0 0010 ---u uuuu
---1 0010 ---u uuuu
---1 0101 ---u uuuu
---1 0011 ---u uuuu
---1 0100 ---u uuuu
---0 1111 ---u uuuu
---1 0101 ---u uuuu
---0 1101 ---u uuuu
---0 0000 ---u uuuu
---0 0001 ---u uuuu
---1 0000 ---u uuuu
---0 1110 ---u uuuu
INTPPS<4:0>
T0CKIPPS
T1CKIPPS
T1GPPS
T0CKIPPS<4:0>
T1CKIPPS<4:0>
T1GPPS<4:0>
CCP1PPS
CCP2PPS
CCP3PPS
CCP4PPS
CCP1PPS<4:0>
CCP2PPS<4:0>
CCP3PPS<4:0>
CCP4PPS<4:0>
CCP4PPS<4:0>
CWG1PPS<4:0>
CWG2PPS<4:0>
MDCIN1PPS<4:0>
MDCIN2PPS<4:0>
MDMINPPS<4:0>
SSP2CLKPPS<4:0>
SSP2CLKPPS<4:0>
SSP2DATPPS<4:0>
SSP2DATPPS<4:0>
SSP2SSPPS<4:0>
SSP2SSPPS<4:0>
SSP1CLKPPS<4:0>
SSP1CLKPPS<4:0>
X
―
― X
E18h
E19h
E1Ah
E1Bh
E1Ch
E1Dh
CWG1PPS
CWG2PPS
MDCIN1PPS
MDCIN2PPS
MDMINPPS
SSP2CLKPPS
X
―
― X
E1Eh
E1Fh
E20h
SSP2DATPPS
SSP2SSPPS
SSP1CLKPPS
X
―
― X
X
―
― X
X
―
― X
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 28
CPU CORE REGISTERS; see Table 4-2 for specifics
E21h
E22h
SSP1DATPPS
SSP1SSPPS
X
―
―
―
―
―
―
―
―
―
―
―
―
―
SSP1DATPPS<4:0>
SSP1DATPPS<4:0>
SSP1SSPPS<4:0>
SSP1SSPPS<4:0>
---1 0001 ---u uuuu
---0 1100 ---u uuuu
---1 0011 ---u uuuu
---1 0100 ---u uuuu
― X
X
―
― X
―
E23h
E24h
―
Unimplemented
―
―
RXPPS
X
―
―
―
―
―
―
―
―
―
―
―
―
―
RXPPS<4:0>
RXPPS<4:0>
TXPPS<4:0>
TXPPS<4:0>
---1 0101 ---u uuuu
---0 1101 ---u uuuu
---1 0100 ---u uuuu
---0 1111 ---u uuuu
― X
E25h
TXPPS
X
―
― X
―
E26h
E27h
E28h
―
Unimplemented
Unimplemented
―
―
―
―
―
―
CLCIN0PPS
X
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
CLCIN0PPS<4:0>
CLCIN0PPS<4:0>
CLCIN1PPS<4:0>
CLCIN1PPS<4:0>
CLCIN2PPS<4:0>
CLCIN2PPS<4:0>
CLCIN3PPS<4:0>
CLCIN3PPS<4:0>
T3CKIPPS<4:0>
T3CKIPPS<4:0>
T3GPPS<4:0>
---1 0011 ---u uuuu
---0 0010 ---u uuuu
---0 0100 ---u uuuu
---1 0011 ---u uuuu
---1 0001 ---u uuuu
---0 1100 ---u uuuu
---0 0101 ---u uuuu
---0 1101 ---u uuuu
---1 0001 ---u uuuu
---0 0101 ---u uuuu
---1 0001 ---u uuuu
---1 0100 ---u uuuu
---1 0001 ---u uuuu
---0 0101 ---u uuuu
---1 0001 ---u uuuu
---1 0100 ---u uuuu
― X
E29h
E2Ah
E2Bh
E2Ch
E2Dh
E2Eh
E2Fh
CLCIN1PPS
CLCIN2PPS
CLCIN3PPS
T3CKIPPS
T3GPPS
X
―
― X
X
―
― X
X
―
― X
X
―
― X
X
―
― X
T3GPPS<4:0>
T5CKIPPS
T5GPPS
X
―
T5CKIPPS<4:0>
T5CKIPPS<4:0>
T5GPPS<4:0>
― X
X
―
― X
T5GPPS<4:0>
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 29
CPU CORE REGISTERS; see Table 4-2 for specifics
E8Dh
E8Eh
E8Fh
E90h
E91h
E92h
E93h
E94h
E95h
E96h
E97h
E98h
E99h
E9Ah
E9Bh
E9Ch
―
―
―
―
―
―
Unimplemented
Unimplemented
Unimplemented
―
―
―
―
―
―
RA0PPS
RA1PPS
RA2PPS
―
―
―
―
―
―
―
―
―
―
RA0PPS<4:0>
RA1PPS<4:0>
RA2PPS<4:0>
---0 0000 ---u uuuu
---0 0000 ---u uuuu
---0 0000 ---u uuuu
―
Unimplemented
―
―
RA4PPS
RA5PPS
―
―
―
―
―
―
―
RA4PPS<4:0>
RA5PPS<4:0>
---0 0000 ---u uuuu
---0 0000 ---u uuuu
―
―
―
―
―
―
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
RB4PPS
X ―
― X
―
―
―
―
―
―
―
―
―
―
―
―
RB4PPS<4:0>
RB5PPS<4:0>
RB6PPS<4:0>
RB7PPS<4:0>
---0 0000 ---u uuuu
E9Dh
E9Eh
E9Fh
RB5PPS
RB6PPS
RB7PPS
X
―
Unimplemented
Unimplemented
Unimplemented
―
―
― X
---0 0000 ---u uuuu
X
―
―
―
― X
---0 0000 ---u uuuu
X
―
―
―
― X
---0 0000 ---u uuuu
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 29
CPU CORE REGISTERS; see Table 4-2 for specifics
EA0h
EA1h
EA2h
EA3h
EA4h
EA5h
EA6h
RC0PPS
RC1PPS
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
RC0PPS<4:0>
RC1PPS<4:0>
RC2PPS<4:0>
RC3PPS<4:0>
RC4PPS<4:0>
RC5PPS<4:0>
---0 0000 ---u uuuu
---0 0000 ---u uuuu
---0 0000 ---u uuuu
---0 0000 ---u uuuu
---0 0000 ---u uuuu
---0 0000 ---u uuuu
RC2PPS
RC3PPS
RC4PPS
RC5PPS
RC6PPS
X
―
Unimplemented
Unimplemented
―
―
― X
―
―
―
―
―
―
RC6PPS<4:0>
RC7PPS<4:0>
---0 0000 ---u uuuu
EA7h
RC7PPS
X
―
―
―
― X
---0 0000 ---u uuuu
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 30
CPU CORE REGISTERS; see Table 4-2 for specifics
F0Ch
F0Dh
F0Eh
F0Fh
F10h
F11h
F12h
F13h
F14h
F15h
F16h
F17h
F18h
F19h
F1Ah
F1Bh
F1Ch
F1Dh
F1Eh
F1Fh
―
―
―
―
―
―
Unimplemented
Unimplemented
Unimplemented
―
―
―
―
―
―
CLCDATA
CLC1CON
CLC1POL
CLC1SEL0
CLC1SEL1
CLC1SEL2
CLC1SEL3
CLC1GLS0
CLC1GLS1
CLC1GLS2
CLC1GLS3
CLC2CON
CLC2POL
CLC2SEL0
CLC2SEL1
CLC2SEL2
CLC2SEL3
―
LC1EN
LC1POL
―
―
―
LC1OUT
―
―
LC1INTP
―
MLC4OUT
LC1INTN
MLC3OUT
LC1G3POL
MLC2OUT
LC1MODE<2:0>
LC1G2POL
MLC1OUT
LC1G1POL
---- 0000 ---- 0000
0-00 0000 0-00 0000
0--- xxxx 0--- uuuu
--xx xxxx --uu uuuu
--xx xxxx --uu uuuu
--xx xxxx --uu uuuu
--xx xxxx --uu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0-00 0000 0-00 0000
0--- xxxx 0--- uuuu
--xx xxxx --uu uuuu
--xx xxxx --uu uuuu
--xx xxxx --uu uuuu
--xx xxxx --uu uuuu
―
―
LC1G4POL
―
LC1D1S<5:0>
―
―
LC1D2S<5:0>
LC1D3S<5:0>
LC1D4S<5:0>
―
―
―
―
LC1G1D4T
LC1G2D4T
LC1G3D4T
LC1G4D4T
LC2EN
LC2POL
―
LC1G1D4N
LC1G1D3T
LC1G2D3T
LC1G3D3T
LC1G4D3T
LC2OUT
―
LC1G1D3N
LC1G2D3N
LC1G3D3N
LC1G4D3N
LC2INTP
―
LC1G1D2T
LC1G1D2N
LC1G2D2N
LC1G3D2N
LC1G4D2N
LC1G1D1T
LC1G2D1T
LC1G1D1N
LC1G2D1N
LC1G3D1N
LC1G4D1N
LC1G2D4N
LC1G2D2T
LC1G3D2T
LC1G4D2T
LC2INTN
LC1G3D4N
LC1G3D1T
LC1G4D4N
LC1G4D1T
―
―
―
―
―
―
LC2MODE<2:0>
LC2G2POL
LC2G4POL
LC2G3POL
LC2G1POL
LC2D1S<5:0>
―
LC2D2S<5:0>
LC2D3S<5:0>
LC2D4S<5:0>
―
―
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 30
CPU CORE REGISTERS; see Table 4-2 for specifics
F20h
F21h
F22h
F23h
F24h
F25h
F26h
F27h
F28h
F29h
F2Ah
F2Bh
F2Ch
F2Dh
F2Eh
F2Fh
F30h
F31h
F32h
F33h
F34h
F35h
F36h
F37h
CLC2GLS0
CLC2GLS1
CLC2GLS2
CLC2GLS3
CLC3CON
CLC3POL
CLC3SEL0
CLC3SEL1
CLC3SEL2
CLC3SEL3
CLC3GLS0
CLC3GLS1
CLC3GLS2
CLC3GLS3
CLC4CON
CLC4POL
CLC4SEL0
CLC4SEL1
CLC4SEL2
CLC4SEL3
CLC4GLS0
CLC4GLS1
CLC4GLS2
CLC4GLS3
LC2G1D4T
LC2G2D4T
LC2G3D4T
LC2G4D4T
LC3EN
LC3POL
―
LC2G1D4N
LC2G1D3T
LC2G2D3T
LC2G3D3T
LC2G4D3T
LC3OUT
―
LC2G1D3N
LC2G2D3N
LC2G3D3N
LC2G4D3N
LC3INTP
―
LC2G1D2T
LC2G2D2T
LC2G3D2T
LC2G4D2T
LC3INTN
LC2G1D2N
LC2G2D2N
LC2G3D2N
LC2G4D2N
LC2G1D1T
LC2G2D1T
LC2G1D1N
LC2G2D1N
LC2G3D1N
LC2G4D1N
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0-00 0000 0-00 0000
0--- xxxx 0--- uuuu
--xx xxxx --uu uuuu
--xx xxxx --uu uuuu
--xx xxxx --uu uuuu
--xx xxxx --uu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0-00 0000 0-00 0000
0--- xxxx 0--- uuuu
--xx xxxx --uu uuuu
--xx xxxx --uu uuuu
--xx xxxx --uu uuuu
--xx xxxx --uu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
LC2G2D4N
LC2G3D4N
LC2G3D1T
LC2G4D4N
LC2G4D1T
―
LC3MODE<2:0>
LC3G2POL
―
LC3G4POL
LC3G3POL
LC3G1POL
―
LC3D1S<5:0>
―
―
LC3D2S<5:0>
LC3D3S<5:0>
LC3D4S<5:0>
―
―
―
―
LC3G1D4T
LC3G2D4T
LC3G3D4T
LC3G4D4T
LC4EN
LC4POL
―
LC3G1D4N
LC3G2D4N
LC3G3D4N
LC3G4D4N
―
LC3G1D3T
LC3G2D3T
LC3G3D3T
LC3G4D3T
LC4OUT
―
LC3G1D3N
LC3G2D3N
LC3G3D3N
LC3G4D3N
LC4INTP
―
LC3G1D2T
LC3G1D2N
LC3G2D2N
LC3G3D2N
LC3G4D2N
LC3G1D1T
LC3G2D1T
LC3G1D1N
LC3G2D1N
LC3G3D1N
LC3G4D1N
LC3G2D2T
LC3G3D2T
LC3G4D2T
LC4INTN
LC3G3D1T
LC3G4D1T
LC4MODE<2:0>
LC4G2POL
―
LC4G4POL
LC4G3POL
LC4G1POL
―
LC4D1S<5:0>
―
―
LC4D2S<5:0>
LC4D3S<5:0>
LC4D4S<5:0>
―
―
―
―
LC4G1D4T
LC4G2D4T
LC4G3D4T
LC4G4D4T
LC4G1D4N
LC4G2D4N
LC4G3D4N
LC4G4D4N
LC4G1D3T
LC4G2D3T
LC4G3D3T
LC4G4D3T
LC4G1D3N
LC4G2D3N
LC4G3D3N
LC4G4D3N
LC4G1D2T
LC4G1D2N
LC4G2D2N
LC4G3D2N
LC4G4D2N
LC4G1D1T
LC4G2D1T
LC4G3D1T
LC4G4D1T
LC4G1D1N
LC4G2D1N
LC4G3D1N
LC4G4D1N
LC4G2D2T
LC4G3D2T
LC4G4D2T
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
TABLE 4-4:
SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Value on
all other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 31 — only accessible from Debug Executive, unless otherwise specified
CPU CORE REGISTERS; see Table 4-2 for specifics
F8Ch to
FE3h
—
— —
Unimplemented
—
—
(2)
FE4h
STATUS_SHAD
WREG_SHAD
BSR_SHAD
PCLATH_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
—
—
—
—
—
—
—
—
Z
DC
C
---- -xxx ---- -uuu
xxxx xxxx uuuu uuuu
---x xxxx ---u uuuu
-xxx xxxx -uuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
(2)
FE5h
Working Register Normal (Non-ICD) Shadow
(2)
FE6h
—
—
Bank Select Register Normal (Non-ICD) Shadow
(2)
FE7h
Program Counter Latch High Register Normal (Non-ICD) Shadow
(2)
FE8h
Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow
Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow
Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow
Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow
Unimplemented
(2)
FE9h
(2)
FEAh
(2)
FEBh
FECh
—
—
—
(2)
FEDh
—
—
—
—
Current Stack pointer
---x xxxx ---1 1111
xxxx xxxx xxxx xxxx
-xxx xxxx -xxx xxxx
STKPTR
TOSL
(2)
FEEh
Top of Stack Low byte
Top of Stack High byte
(2)
FEFh
TOSH
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= depends on condition, - = unimplemented, read as ‘0’, r= reserved. Shaded locations unimplemented, read as ‘0’.
Only on PIC16F18326/18346.
Register accessible from both User and ICD Debugger.
PIC16(L)F18326/18346
4.3.2
COMPUTED GOTO
4.3
PCL and PCLATH
A computed GOTOis accomplished by adding an offset to
the program counter (ADDWF PCL). When performing a
table read using a computed GOTOmethod, care should
be exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to Application
Note AN556, Implementing a Table Read (DS00556).
The Program Counter (PC) is 15 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<14:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 4-3 shows the five
situations for the loading of the PC.
4.3.3
COMPUTED FUNCTION CALLS
FIGURE 4-3:
LOADING OF PC IN
A computed function CALLallows programs to maintain
tables of functions and provide another way to execute
state machines or look-up tables. When performing a
table read using a computed function CALL, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block).
DIFFERENT SITUATIONS
Instruction with
14
0
PCH
7
PCL
PCL as
PC
Destination
8
6
0
PCLATH
ALU Result
If using the CALLinstruction, the PCH<2:0> and PCL
registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.
14
0
PCH
PCL
GOTO, CALL
PC
The CALLW instruction enables computed calls by
combining PCLATH and W to form the destination
address. A computed CALLW is accomplished by
loading the W register with the desired address and
executing CALLW. The PCL register is loaded with the
value of W and PCH is loaded with PCLATH.
11
4
6
0
PCLATH
OPCODE <10:0>
14
0
0
0
PCH
7
PCL
CALLW
PC
8
6
0
4.3.4
BRANCHING
PCLATH
W
The branching instructions add an offset to the PC.
This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
crossed.
14
PCH
PCL
PC
BRW
BRA
15
PC + W
14
PCH
PCL
If using BRW, load the W register with the desired
unsigned address and execute BRW. The entire PC will
be loaded with the address PC + 1 + W.
PC
15
PC + OPCODE <8:0>
If using BRA, the entire PC will be loaded with
PC + 1 + the signed value of the operand of the BRA
instruction.
4.3.1
MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<14:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by
writing the desired upper seven bits to the PCLATH
register. When the lower eight bits are written to the
PCL register, all 15 bits of the program counter will
change to the values contained in the PCLATH register
and those being written to the PCL register.
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4.4.1
ACCESSING THE STACK
4.4
Stack
The stack is accessible through the TOSH, TOSL and
STKPTR registers. STKPTR is the current value of the
Stack Pointer. TOSH:TOSL register pair points to the
TOP of the stack. Both registers are read/writable. TOS
is split into TOSH and TOSL due to the 15-bit size of the
PC. To access the stack, adjust the value of STKPTR,
which will position TOSH:TOSL, then read/write to
TOSH:TOSL. STKPTR is five bits to allow detection of
Overflow and Underflow.
All devices have a 16-level x 15-bit wide hardware
stack (refer to Figure 4-4 through Figure 4-7). The
stack space is not part of either program or data space.
The PC is PUSHed onto the stack when CALL or
CALLWinstructions are executed or an interrupt causes
a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
The stack operates as a circular buffer and does not
cause a Reset when either a Stack Overflow or
Underflow occur if the STVREN bit is programmed to
‘0‘ (Configuration Words). This means that after the
stack has been PUSHed sixteen times, the
seventeenth PUSH overwrites the value that was
stored from the first PUSH. The eighteenth PUSH
overwrites the second PUSH (and so on). The
STKOVF and STKUNF flag bits will be set on an
Overflow/Underflow, regardless of whether the Reset is
enabled.
Note:
Care should be taken when modifying the
STKPTR while interrupts are enabled.
During normal program operation, CALL, CALLWand
Interrupts will increment STKPTR while RETLW,
RETURN, and RETFIEwill decrement STKPTR. At any
time, STKPTR can be read to see how much stack is
left. The STKPTR always points at the currently used
place on the stack. Therefore, a CALL or CALLW will
increment the STKPTR and then write the PC, and a
return will unload the PC and then decrement the
STKPTR.
If the STVREN bit in Configuration Words is
programmed to ‘1’, the device will be Reset if the stack
is PUSHed beyond the sixteenth level or POPed
beyond the first level, setting the appropriate bits
(STKOVF or STKUNF, respectively) in the PCON
register.
Reference Figure 4-4 through Figure 4-7 for examples
of accessing the stack.
Note 1: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, CALLW, RETURN, RETLW and
RETFIE instructions or the vectoring to
an interrupt address.
FIGURE 4-4:
ACCESSING THE STACK EXAMPLE 1
Stack Reset Disabled
STKPTR = 0x1F
TOSH:TOSL
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
0x1F
(STVREN = 0)
Initial Stack Configuration:
After Reset, the stack is empty. The
empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL registers will return ‘0’. If
the Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.
Stack Reset Enabled
STKPTR = 0x1F
TOSH:TOSL
0x0000
(STVREN = 1)
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FIGURE 4-5:
ACCESSING THE STACK EXAMPLE 2
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
This figure shows the stack configuration
after the first CALLor a single interrupt.
If a RETURN instruction is executed, the
return address will be placed in the
Program Counter and the Stack Pointer
decremented to the empty state (0x1F).
TOSH:TOSL
0x00
Return Address
STKPTR = 0x00
FIGURE 4-6:
ACCESSING THE STACK EXAMPLE 3
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
After seven CALLs or six CALLs and an
interrupt, the stack looks like the figure
on the left. A series of RETURNinstructions
will repeatedly place the return addresses
into the Program Counter and pop the stack.
STKPTR = 0x06
TOSH:TOSL
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
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FIGURE 4-7:
ACCESSING THE STACK EXAMPLE 4
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
When the stack is full, the next CALLor
an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00
so the stack will wrap and overwrite the
return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
Reset will occur and location 0x00 will
not be overwritten.
TOSH:TOSL
STKPTR = 0x10
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4.5.1
TRADITIONAL/BANKED DATA
MEMORY
4.5
Indirect Addressing
The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.
The traditional data memory is a region from FSR
address 0x000 to FSR address 0xFFF. The addresses
correspond to the absolute addresses of all SFR, GPR
and common registers.
The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into four memory regions:
• Traditional/Banked Data Memory
• Linear Data Memory
• Program Flash Memory
• EEPROM
FIGURE 4-8:
INDIRECT ADDRESSING PIC16(L)F18326/18346
Rev. 10-000044A
7/30/2013
0x0000
0x0000
Traditional
Data Memory
0x0FFF
0x1000
0x0FFF
Reserved
0x1FFF
0x2000
Linear
Data Memory
0x29AF
0x29B0
Reserved
0x0000
0x7FFF
0x8000
FSR
Address
Range
Program
Flash Memory
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FIGURE 4-9:
TRADITIONAL/BANKED DATA MEMORY MAP
Direct Addressing
From Opcode
Indirect Addressing
4
BSR
6
7
FSRxH
0
7
FSRxL
0
0
0
0
0
0
0
Location Select
Bank Select
Bank Select
Location Select
00000 00001 00010
11111
0x00
0x7F
Bank 0 Bank 1 Bank 2
Bank 31
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4.5.2
LINEAR DATA MEMORY
4.5.4
PROGRAM FLASH MEMORY
The linear data memory is the region from FSR
address 0x2000 to FSR address 0x29AF. This region is
a virtual region that points back to the 80-byte blocks of
GPR memory in all the banks.
To make constant data access easier, the entire
Program Flash Memory is mapped to the upper half of
the FSR address space. When the MSB of FSRnH is
set, the lower 15 bits are the address in program
memory which will be accessed through INDF. Only the
lower eight bits of each memory location are accessible
via INDF. Writing to the Program Flash Memory cannot
be accomplished via the FSR/INDF interface. All
instructions that access Program Flash Memory via the
FSR/INDF interface will require one additional
instruction cycle to complete.
Unimplemented memory reads as 0x00. Use of the
linear data memory region allows buffers to be larger
than 80 bytes because incrementing the FSR beyond
one bank will go directly to the GPR memory of the next
bank.
The 16 bytes of common memory are not included in
the linear data memory region.
FIGURE 4-11:
PROGRAM FLASH
MEMORY MAP
FIGURE 4-10:
LINEAR DATA MEMORY
MAP
7
7
0
0
FSRnH
FSRnL
7
1
7
0
0
FSRnH
FSRnL
0
0 1
Location Select
0x8000
0x0000
Location Select
0x2000
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
0x120
Program
Flash
Memory
(low 8
bits)
Bank 2
0x16F
0xF20
Bank 30
0x7FFF
0xFFFF
0xF6F
0x29AF
4.5.3
DATA EEPROM MEMORY
The EEPROM memory can be read or written through
the NVMCON register interface (see Section 11.2
“Data EEPROM”). However, to make access to the
EEPROM easier, read-only access to the EEPROM
contents are also available through indirect addressing
via an FSR. When the MSP of the FSR (ex: FSRxH) is
set to 0x70, the lower 8-bit address value (in FSRxL)
determines the EEPROM location that may be read via
the INDF register). In other words, the EEPROM
address range 0x00-0xFF is mapped into the FSR
address space between 0x7000 and 0x70FF. Writing to
the EEPROM cannot be accomplished via the
FSR/INDF interface. Reads from the EEPROM through
the FSR/INDF interface will require one additional
instruction cycle to complete.
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5.0
DEVICE CONFIGURATION
Device configuration consists of Configuration Words,
Code Protection and Device ID.
5.1
Configuration Words
There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1 at
8007h, Configuration Word 2 at 8008h, Configuration
Word 3 at 8009h, and Configuration Word 4 at 800Ah.
Note:
The DEBUG bit in Configuration Words is
managed automatically by device
development tools including debuggers
and programmers. For normal device
operation, this bit should be maintained as
a ‘1’.
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5.2
Register Definitions: Configuration Words
REGISTER 5-1:
CONFIGURATION WORD 1: OSCILLATORS
R/P-1
U-1
—
R/P-1
U-1
—
U-1
—
R/P-1
CLKOUTEN
bit 8
FCMEN
CSWEN
bit 13
U-1
R/P-1
RSTOSC2
R/P-1
R/P-1
U-1
—
R/P-1
R/P-1
R/P-1
—
RSTOSC1
RSTOSC0
FEXTOSC2 FEXTOSC1 FEXTOSC0
bit 0
bit 7
Legend:
R = Readable bit
‘0’ = Bit is cleared
P = Programmable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘1’
n = Value when blank or after Bulk Erase
bit 13
FCMEN: Fail-Safe Clock Monitor Enable bit
1 = ON FSCM timer enabled
0 = OFF FSCM timer disabled
Unimplemented: Read as ‘1’
CSWEN: Clock Switch Enable bit
bit 12
bit 11
1 = ON
Writing to NOSC and NDIV is allowed
0 = OFF The NOSC and NDIV bits cannot be changed by user software
bit 10-9
bit 8
Unimplemented: Read as ‘1’
CLKOUTEN: Clock Out Enable bit
If FEXTOSC = EC, HS, HT or LP, then this bit is ignored; otherwise:
1 = OFF CLKOUT function is disabled; I/O or oscillator function on OSC2
0 = ON
CLKOUT function is enabled; FOSC/4 clock appears at OSC2
bit 7
Unimplemented: Read as ‘1’
bit 6-4
RSTOSC<2:0>: Power-up Default Value for COSC bits
This value is the Reset default value for COSC, and selects the oscillator first used by user software
111 = EXT1X
EXTOSC operating per FEXTOSC<2:0> bits
110 = HFINT1 HFINTOSC (1 MHz)
101 = Reserved
100 = LFINT
011 = SOSC
LFINTOSC
SOSC (32.768 kHz)
010 = Reserved
001 = EXT4X
EXTOSC with 4x PLL; EXTOSC operating per FEXTOSC<2:0> bits
000 = HFINT32 HFINTOSC (32 MHz)
bit 3
Unimplemented: Read as ‘1’
bit 2-0
FEXTOSC<2:0>: FEXTOSC External Oscillator Mode Selection bits
111 = ECH EC(External Clock) above 8 MHz
110 = ECM EC(External Clock) for 100 kHz to 8 MHz
101 = ECL EC(External Clock) below 100 kHz
100 = OFF Oscillator not enabled
011 = Unimplemented
010 = HS HS(Crystal oscillator) above 8 MHz
001 = XT HT(Crystal oscillator) above 100 kHz, below 8 MHz
000 = LP LP(Crystal oscillator) optimized for 32.768 kHz
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REGISTER 5-2:
CONFIGURATION WORD 2: SUPERVISORS
R/P-1
R/P-1
R/P-1
U-1
—
R/P-1
U-1
—
DEBUG
STVREN
PPS1WAY
BORV
bit 13
bit 8
R/P-1
BOREN1
bit 7
R/P-1
R/P-1
U-1
—
R/P-1
R/P-1
R/P-1
R/P-1
BOREN0
LPBOREN
WDTE1
WDTE0
PWRTE
MCLRE
bit 0
Legend:
R = Readable bit
‘0’ = Bit is cleared
P = Programmable bit
U = Unimplemented bit, read as ‘1’
n = Value when blank or after Bulk Erase
‘1’ = Bit is set
(1)
bit 13
bit 12
bit 11
DEBUG: Debugger Enable bit
1 = OFF
0 = ON
Background debugger disabled; ICSPCLK and ICSPDAT are general purpose I/O pins
Background debugger enabled; ICSPCLK and ICSPDAT are dedicated to the debugger
STVREN: Stack Overflow/Underflow Reset Enable bit
1 = ON
0 = OFF
Stack Overflow or Underflow will cause a Reset
Stack Overflow or Underflow will not cause a Reset
PPS1WAY: PPSLOCK One-Way Set Enable bit
1 = ON
The PPSLOCKED bit can be cleared and set only once; PPS registers remain locked after one
clear/set cycle
0 = OFF
The PPSLOCKED bit can be set and cleared repeatedly (subject to the unlock sequence)
bit 10
bit 9
Unimplemented: Read as ‘1’
(2)
BORV: Brown-out Reset Voltage Selection bit
1 = LOW
0 = HIGH
Brown-out Reset voltage (VBOR) set to 1.9V on LF, and 2.45V on F devices
Brown-out Reset voltage (VBOR) set to 2.7V
The higher voltage setting is recommended for operation at or above 16 MHz.
bit 8
Unimplemented: Read as ‘1’
bit 7-6
BOREN<1:0>: Brown-out Reset Enable bits
When enabled, Brown-out Reset Voltage (VBOR) is set by the BORV bit
11 = ON
Brown-out Reset is enabled; SBOREN bit is ignored
Brown-out Reset is enabled while running, disabled in Sleep; SBOREN bit is ignored
Brown-out Reset is enabled according to SBOREN
Brown-out Reset is disabled
10 = SLEEP
01 = SBOREN
00 = OFF
bit 5
LPBOREN: Low-Power BOR Enable bit
1 = OFF
0 = ON
ULPBOR is disabled
ULPBOR is enabled
bit 4
Unimplemented: Read as ‘1’
bit 3-2
WDTE<1:0>: Watchdog Timer Enable bit
11 = ON
WDT is enabled; SWDTEN is ignored
10 = SLEEP
01 = SWDTEN
00 = OFF
WDT is enabled while running and disabled in Sleep/Idle; SWDTEN is ignored
WDT is controlled by the SWDTEN bit in the WDTCON register
WDT is disabled; SWDTEN is ignored
bit 1
bit 0
PWRTE: Power-up Timer Enable bit
1 = OFF
0 = ON
PWRT is disabled
PWRT is enabled
MCLRE: Master Clear (MCLR) Enable bit
If LVP = 1:
RA3 pin function is MCLR.
If LVP = 0:
1 = ON
MCLR pin is MCLR.
0 = OFF
MCLR pin function is port-defined function.
Note 1: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers
and programmers. For normal device operation, this bit should be maintained as a ‘1’.
2: See VBOR parameter for specific trip point voltages.
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REGISTER 5-3:
CONFIGURATION WORD 3: MEMORY
R/P-1
LVP(1)
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 13
bit 8
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
R/P-1
WRT1
R/P-1
WRT0
bit 7
bit 0
Legend:
R = Readable bit
‘0’ = Bit is cleared
P = Programmable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘1’
n = Value when blank or after Bulk Erase
bit 13
LVP: Low-Voltage Programming Enable bit(1)
1 = ON
Low-Voltage Programming is enabled. MCLR/VPP pin function is MCLR. MCLRE
Configuration bit is ignored.
0 = OFF HV on MCLR/VPP must be used for programming.
bit 12-2
bit 1-0
Unimplemented: Read as ‘1’
WRT<1:0>: User NVM Self-Write Protection bits
11 = OFF Write protection off
10 = BOOT 0000h to 01FFh write-protected, 0200h to 3FFFh may be modified
01 = HALF 0000h to 1FFFh write-protected, 2000h to 3FFFh may be modified
00 = ALL 0000h to 3FFFh write-protected, no addresses may be modified
WRT applies only to the self-write feature of the device; writing through ICSP™ is never protected.
Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
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REGISTER 5-4:
CONFIGURATION WORD 4: CODE PROTECTION
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 13
bit 8
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
R/P-1
CPD
R/P-1
CP
bit 7
bit 0
Legend:
R = Readable bit
‘0’ = Bit is cleared
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘1’ = Bit is set
n = Value when blank or after Bulk Erase
bit 13-2
bit 1
Unimplemented: Read as ‘1’
CPD: Data EEPROM Memory Code Protection bit
1 = OFF Data EEPROM code protection disabled
0 = ON
Data EEPROM code protection enabled
bit 0
CP: Program Memory Code Protection bit
1 = OFF Program Memory code protection disabled
0 = ON
Program Memory code protection enabled
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5.3
Code Protection
5.6
Device ID and Revision ID
Code protection allows the device to be protected from
unauthorized access. Program memory protection and
data memory are controlled independently. Internal
access to the program memory is unaffected by any
code protection setting.
The 14-bit Device ID word is located at 8006h and the
14-bit Revision ID is located at 8005h. These locations
are read-only and cannot be erased or modified. See
Section 11.4 “NVMREG Access” for more
information on accessing these memory locations.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.
5.3.1
PROGRAM MEMORY PROTECTION
The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Words. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Self-write
writing the program memory is dependent upon the
write protection setting. See Section 5.4 “Write
Protection” for more information.
5.3.2
DATA MEMORY PROTECTION
The entire data EEPROM is protected from external
reads and writes by the CPD bit in the Configuration
Words. When CPD = 0, external reads and writes of
EEPROM memory are inhibited and a read will return
all ‘0’s. The CPU can continue to read and write
EEPROM memory, regardless of the protection bit
settings.
5.4
Write Protection
Write protection allows the device to be protected from
unintended self-writes. Applications, such as boot
loader software, can be protected while allowing other
regions of the program memory to be modified.
The WRT<1:0> bits in Configuration Words define the
size of the program memory block that is protected.
5.5
User ID
Four memory locations (8000h-8003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
readable and writable during normal execution. See
Section 11.4.7 “NVMREG EEPROM, User ID, Device
ID and Configuration Word Access” for more
information on accessing these memory locations. For
more information on checksum calculation, see the
“PIC16(L)F183XX
Memory
Programming
Specification” (DS40001738).
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5.7
Register Definitions: Device and Revision
REGISTER 5-5:
DEVID: DEVICE ID REGISTER
R
R
R
R
R
R
R
R
R
R
DEV<13:8>
bit 13
bit 8
bit 0
R
R
R
R
DEV<7:0>
bit 7
Legend:
R = Readable bit
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 13-0
DEV<13:0>: Device ID bits
Device
DEVID<13:0> Values
PIC16F18326
PIC16LF18326
PIC16F18346
PIC16LF18346
11 0000 1010 0100 (30A4)
11 0000 1010 0110 (30A6)
11 0000 1010 0101 (30A5)
11 0000 1010 0111 (30A7)
REGISTER 5-6:
REVID: REVISION ID REGISTER
R-1
R-0
R
R
R
R
R
R
R
R
REV<13:8>
bit 13
bit 8
bit 0
R
R
R
R
REV<7:0>
bit 7
Legend:
R = Readable bit
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 13-0
REV<13:0>: Revision ID bits
The upper two bits of the Revision ID Register will always read ‘10’.
Note:
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6.0
RESETS
There are multiple ways to reset this device:
• Power-On Reset (POR)
• Brown-Out Reset (BOR)
• Low-Power Brown-Out Reset (LPBOR)
• MCLR Reset
• WDT Reset
• RESETinstruction
• Stack Overflow
• Stack Underflow
• Programming mode exit
To allow VDD to stabilize, an optional Power-up Timer
can be enabled to extend the Reset time after a BOR
or POR event.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 6-1.
FIGURE 6-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Rev. 10-000006A
8/14/2013
ICSP™ Programming Mode Exit
RESET Instruction
Stack Underflow
Stack Overlfow
MCLRE
Sleep
VPP/MCLR
WDT
Time-out
Device
Reset
Power-on
Reset
VDD
BOR
Active(1)
Brown-out
Reset
R
Power-up
Timer
LFINTOSC
PWRTE
LPBOR
Reset
Note 1: See Table 6-1 for BOR active conditions.
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PIC16(L)F18326/18346
6.1
Power-on Reset (POR)
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
6.2
Brown-out Reset (BOR)
The BOR circuit holds the device in Reset while VDD is
below a selectable minimum level. Between the POR
and BOR, complete voltage range coverage for execu-
tion protection can be implemented.
The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in
Configuration Words. The four operating modes are:
• BOR is always on
• BOR is off when in Sleep
• BOR is controlled by software
• BOR is always off
Refer to Table 6-1 for more information.
The Brown-out Reset voltage level is selectable by
configuring the BORV bit in Configuration Words.
A VDD noise rejection filter prevents the BOR from
triggering on small events. If VDD falls below VBOR for
a duration greater than parameter TBORDC, the device
will reset, and the BOR bit of the PCON0 register will
be cleared, indicating that a Brown-out Reset condition
occurred. See Figure 6-2 for more information.
TABLE 6-1:
BOREN<1:0>
11
BOR OPERATING MODES
Instruction Execution upon:
Release of POR or Wake-up from Sleep
SBOREN
Device Mode BOR Mode
X
X
Active
In these specific cases, “Release of POR” and
“Wake-up from Sleep”, there is no delay in start-up.
The BOR ready flag, (BORRDY = 1), will be set
before the CPU is ready to execute instructions
because the BOR circuit is forced on by the
BOREN<1:0> bits.
Awake
Sleep
X
Active
Disabled
Active
Waits for release of BOR (BORRDY = 1)
10
X
1
BOR ignored when asleep
In these specific cases, “Release of POR” and
“Wake-up from Sleep”, there is no delay in start-up.
The BOR ready flag, (BORRDY = 1), will be set
before the CPU is ready to execute instructions
because the BOR circuit is forced on by the
BOREN<1:0> bits
01
00
0
X
X
X
Disabled
Disabled
Begins immediately (BORRDY = x)
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6.2.1
BOR IS ALWAYS ON
6.2.3
BOR CONTROLLED BY SOFTWARE
When the BOREN bits of Configuration Words are
programmed to ‘11’, the BOR is always on. The device
start-up will be delayed until the BOR is ready and VDD
is higher than the BOR threshold.
When the BOREN bits of Configuration Words are
programmed to ‘01’, the BOR is controlled by the
SBOREN bit of the BORCON register. The device
wake from Sleep is not delayed by the BOR Ready
condition or the VDD level only when the SBOREN bit
is cleared in software and the device is starting up from
a non POR/BOR Reset event.
BOR protection is active during Sleep. The BOR does
not delay wake-up from Sleep.
6.2.2
BOR IS OFF IN SLEEP
BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register. BOR Protection
is unchanged by Sleep
When the BOREN bits of Configuration Words are
programmed to ‘10’, the BOR is on, except in Sleep.
The device start-up will be delayed until the BOR is
ready and VDD is higher than the BOR threshold.
BOR protection is not active during Sleep, but device
wake-up will be delayed until the BOR can determine
that VDD is higher than the BOR threshold. The device
wake-up will be delayed until the BOR is ready.
FIGURE 6-2:
BROWN-OUT SITUATIONS
VDD
VBOR
Internal
Reset
(1)
TPWRT
VDD
VBOR
Internal
Reset
< TPWRT
(1)
TPWRT
VDD
VBOR
Internal
Reset
(1)
TPWRT
Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.
6.2.4
BOR ALWAYS OFF
When the BOREN bits of Configuration Word 2 are
programmed to ‘00’, the BOR is always disable. In the
configuration, setting the SWBOREN bit will have no
affect on BOR operation.
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The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
6.3
Low-Power Brown-out Reset
(LPBOR)
Note:
A Reset does not drive the MCLR pin low.
The Low-Power Brown-Out Reset (LPBOR) circuit
provides alternative protection against Brown-out
conditions. When VDD falls below the LPBOR
threshold, the device is held in Reset. When this
occurs, the BOR bit of the PCON0 register is cleared to
indicate that a Brown-out Reset occurred. The BOR bit
will be cleared when either the BOR or the LPBOR
circuitry detects a BOR condition. The LPBOR feature
can be used with or without BOR enabled.
6.4.2
MCLR DISABLED
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See Section 12.2 “PORTA
Registers” for more information.
6.5
Watchdog Timer (WDT) Reset
When used while BOR is enabled, the LPBOR can be
used as a secondary protection circuit in case the BOR
circuit fails to detect the BOR condition. Additionally,
when BOR is enabled except while in Sleep
(BOREN<1:0> = 10), the LPBOR circuit will hold the
device in Reset while VDD is lower than the LPBOR
threshold, and will also re-arm the POR. (see
Figure 35-11 for LPBOR Reset voltage levels).
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDTinstruction within the time-out
period. The TO and PD bits in the STATUS register as
well as the RWDT bit in the PCON register, are changed
to indicate the WDT Reset. See Section 10.0
“Watchdog Timer (WDT)” for more information.
6.6
RESET Instruction
When used without BOR enabled, the LPBOR circuit
provides a single Reset trip point with the benefit of
reduced current consumption.
A RESETinstruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Table 6-4
for default conditions after a RESET instruction has
occurred.
6.3.1
ENABLING LPBOR
The LPBOR is controlled by the LPBOR bit of
Configuration Words. When the device is erased, the
LPBOR module defaults to disabled.
6.7
Stack Overflow/Underflow Reset
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration
Words. See Section 4.4 “Stack” for more information.
6.3.1.1
LPBOR Module Output
The output of the LPBOR module is a signal indicating
whether or not a Reset is to be asserted. This signal is
OR’d together with the Reset signal of the BOR
module to provide the generic BOR signal, which goes
to the PCON register and to the power control block.
6.8
Programming Mode Exit
Upon exit of Programming mode, the device will
behave as if a device Reset had just occurred.
6.4
MCLR
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE bit of Configuration Words and the LVP bit of
Configuration Words (Table 6-2).
6.9
Power-up Timer
The Power-up Timer provides a nominal 64 ms
time-out on POR or Brown-out Reset.
The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the VDD to
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in Configuration
Words.
TABLE 6-2:
MCLRE
MCLR CONFIGURATION
LVP
MCLR
0
1
x
0
0
1
Disabled
Enabled
Enabled
The Power-up Timer starts after the release of the POR
and BOR.
For additional information, refer to Application Note
AN607, Power-up Trouble Shooting (DS00607).
6.4.1
MCLR ENABLED
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up.
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The Power-up Timer and oscillator start-up timer run
independently of MCLR Reset. If MCLR is kept low
long enough, the Power-up Timer will expire. Upon
bringing MCLR high, the device will begin execution
after ten FOSC cycles (see Figure 6-3). This is useful for
testing purposes or to synchronize more than one
device operating in parallel.
6.10 Start-up Sequence
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1. Power-up Timer runs to completion (if enabled).
2. MCLR must be released (if enabled).
3. Oscillator start-up timer runs to completion (if
required for oscillator source).
The total time out will vary based on oscillator
configuration and Power-up Timer Configuration. See
Section 7.0, Oscillator Module for more information.
FIGURE 6-3:
RESET START-UP SEQUENCE
VDD
Internal POR
TPWRT
Power-up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Oscillator Start-up Timer
Oscillator
FOSC
Internal Oscillator
Oscillator
FOSC
External Clock (EC)
CLKIN
FOSC
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6.11 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON registers are updated to indicate the cause of
the Reset. Table 6-3 and Table 6-4 show the Reset
conditions of these registers.
TABLE 6-3:
RESET STATUS BITS AND THEIR SIGNIFICANCE
STKOVF STKUNF RWDT RMCLR
RI
POR
BOR TO PD
Condition
Power-on Reset
0
0
0
0
u
u
u
u
u
u
1
u
0
0
0
0
u
u
u
u
u
u
u
1
1
1
1
u
0
u
u
u
u
u
u
u
1
1
1
1
u
u
u
0
0
u
u
u
1
1
1
1
u
u
u
u
u
0
u
u
0
0
0
u
u
u
u
u
u
u
u
u
x
x
x
0
u
u
u
u
u
u
u
u
1
0
x
1
0
0
1
u
1
u
u
u
1
x
0
1
u
0
0
u
0
u
u
u
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up from Sleep
Interrupt Wake-up from Sleep
MCLR Reset during Normal Operation
MCLR Reset during Sleep
RESETInstruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
TABLE 6-4:
RESET CONDITION FOR SPECIAL REGISTERS
Program
STATUS
Register
PCON0
Register
Condition
Counter
Power-on Reset
0000h
---1 1000
---u uuuu
00-- 110x
uu-- 0uuu
MCLR Reset during Normal Operation
0000h
MCLR Reset during Sleep
WDT Reset
0000h
0000h
---1 0uuu
---0 uuuu
---0 0uuu
---1 1000
---1 0uuu
---u uuuu
---u uuuu
---u uuuu
uu-- 0uuu
uu-0 uuuu
uu-u uuuu
00-1 11u0
uu-u uuuu
uu-u u0uu
1u-u uuuu
u1-u uuuu
WDT Wake-up from Sleep
Brown-out Reset
PC + 1
0000h
PC + 1(1)
Interrupt Wake-up from Sleep
RESETInstruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
0000h
0000h
0000h
Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
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REGISTER 6-1:
R/W-1/u
SBOREN(1)
BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-0-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-q/u
Reserved
BORRDY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
‘1’ = Bit is set
bit 7
SBOREN: Software Brown-out Reset Enable bit(1)
If BOREN <1:0> in Configuration Words 01:
SBOREN is read/write, but has no effect on the BOR.
If BOREN <1:0> in Configuration Words = 01:
1= BOR Enabled
0= BOR Disabled
bit 6
Reserved: Bit must be maintained as ‘0’
Unimplemented: Read as ‘0’
bit 5-1
bit 0
BORRDY: Brown-out Reset Circuit Ready Status bit
1= The Brown-out Reset circuit is active
0= The Brown-out Reset circuit is inactive
Note 1: BOREN<1:0> bits are located in Configuration Words.
6.12 Power Control (PCON) Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• RESETInstruction Reset (RI)
• MCLR Reset (RMCLR)
• Watchdog Timer Reset (RWDT)
• Stack Underflow Reset (STKUNF)
• Stack Overflow Reset (STKOVF)
The PCON0 register bits are shown in Register 6-2.
Hardware will change the corresponding register bit
during the Reset process; if the Reset was not caused
by the condition, the bit remains unchanged
(Table 6-4).
Software should reset the bit to the inactive state after
the restart (hardware will not reset the bit).
Software may also set any PCON bit to the active state,
so that user code may be tested, but no Reset action
will be generated.
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6.13 Register Definitions: Power Control
REGISTER 6-2:
PCON0: POWER CONTROL REGISTER 0
R/W/HS-0/q R/W/HS-0/q
U-0
—
R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u
STKOVF
bit 7
STKUNF
RWDT
RMCLR
RI
POR
BOR
bit 0
Legend:
HC = Bit is cleared by hardware
HS = Bit is set by hardware
U = Unimplemented bit, read as ‘0’
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
-m/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
‘0’ = Bit is cleared
bit 7
bit 6
STKOVF: Stack Overflow Flag bit
1= A Stack Overflow occurred
0= A Stack Overflow has not occurred or has been cleared by firmware
STKUNF: Stack Underflow Flag bit
1= A Stack Underflow occurred
0= A Stack Underflow has not occurred or has been cleared by firmware
bit 5
bit 4
Unimplemented: Read as ‘0’
RWDT: Watchdog Timer Reset Flag bit
1= A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware
0= A Watchdog Timer Reset has occurred (cleared by hardware)
bit 3
bit 2
bit 1
bit 0
RMCLR: MCLR Reset Flag bit
1= A MCLR Reset has not occurred or set to ‘1’ by firmware
0= A MCLR Reset has occurred (cleared by hardware)
RI: RESETInstruction Flag bit
1= A RESETinstruction has not been executed or set to ‘1’ by firmware
0= A RESETinstruction has been executed (cleared by hardware)
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)
TABLE 6-5:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page
BORCON SBOREN
—
—
—
—
—
RWDT
TO
—
RMCLR
PD
—
RI
Z
—
POR
DC
BORRDY
BOR
76
77
PCON0
STKOVF STKUNF
STATUS
WDTCON
—
—
—
—
C
30
WDTPS<4:0>
SWDTEN
121
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.
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If an external clock source is selected, the FEXTOSC
bits of Configuration Word 1 must be used in
conjunction with the RSTOSC bits to select the
External Clock mode.
7.0
7.1
OSCILLATOR MODULE
Overview
The oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing
performance and minimizing power consumption.
Figure 7-1 illustrates a block diagram of the oscillator
module.
The external oscillator module can be configured in one
of the following clock modes by setting the
FEXTOSC<2:0> bits of Configuration Word 1:
1. ECL – External Clock Low-Power mode
(<= 100 kHz)
2. ECM – External Clock Medium-Power mode
(<= 8 MHz)
Clock sources can be supplied from external oscillators,
quartz-crystal resonators and ceramic resonators. In
addition, the system clock source can be supplied from
one of two internal oscillators and PLL circuits, with a
choice of speeds selectable via software. Additional
clock features include:
3. ECH – External Clock High-Power mode
(above 8 MHz)
4. LP – 32 kHz Low-Power Crystal mode.
5. XT – Medium Gain Crystal or Ceramic Resonator
Oscillator mode (between 100 kHz and 4 MHz)
• Selectable system clock source between external
or internal sources via software.
6. HS – High Gain Crystal or Ceramic Resonator
mode (above 4 MHz)
• Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the external clock source (LP,
XT, HS, ECH, ECM, ECL) and switch
The ECH, ECM, and ECL Clock modes rely on an
external logic level signal as the device clock source.
The LP, XT, and HS Clock modes require an external
crystal or resonator to be connected to the device.
Each mode is optimized for a different frequency range.
The INTOSC internal oscillator block produces low and
high-frequency clock sources, designated LFINTOSC
and HFINTOSC. (see Internal Oscillator Block,
Figure 7-1).
automatically to the internal oscillator.
• Oscillator Start-up Timer (OST) ensures stability
of crystal oscillator sources.
The RSTOSC bits of Configuration Word 1 determine
the type of oscillator that will be used when the device
is reset, including when it is first powered-up.
The internal clock modes, LFINTOSC, HFINTOSC (set
at 1 MHz), or HFINTOSC (set at 32 MHz) can be set
through the RSTOSC bits.
DS40001839B-page 78
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2016-2017 Microchip Technology Inc.
FIGURE 7-1:
SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
Rev. 10-000208J
12/13/2016
CLKIN
External
Oscillator
(EXTOSC)
CLKOUT
CDIV<4:0>
4x PLL Mode
COSC<2:0>
SOSCIN/SOSCI
Secondary
Oscillator
(SOSC)
512
PLLꢀBlock
1001
1000
0111
0110
0101
0100
0011
0010 Sleep
0001
0000
256
128
64
32
16
8
111
001
010
100
101
110
000
011
Sleep
2x PLL Mode
System Clock
SOSCO
LFINTOSC
31kHz
Oscillator
SYSCMD
Peripheral Clock
4
Reserved
2
Idle
1
HFINTOSC
HFFRQ<2:0>
1 – 32 MHz
Oscillator
MFINTOSC
FSCM
To Peripherals
To Peripherals
To Peripherals
To Peripherals
To Peripherals
500 kHz
31.25 kHz
PIC16(L)F18326/18346
7.2.1.1
EC Mode
7.2
Clock Source Types
The External Clock (EC) mode allows an externally
generated logic level signal to be the system clock
source. When operating in this mode, an external clock
source is connected to the CLKIN input.
OSC2/CLKOUT is available for general purpose I/O or
CLKOUT. Figure 7-2 shows the pin connections for EC
mode.
Clock sources can be classified as external or internal.
External clock sources rely on external circuitry for the
clock source to function. Examples are: oscillator
modules (ECH, ECM, ECL mode), quartz crystal
resonators or ceramic resonators (LP, XT and HS
modes).
There is also a secondary oscillator block which is
optimized for a 32.768 kHz external clock source,
which can be used as an alternate clock source.
EC mode has three power modes to select from through
Configuration Words:
• ECH – High power, <= 32 MHz
• ECM – Medium power, <= 8 MHz
• ECL – Low power, <= 0.1 MHz
There are two internal oscillator blocks:
- HFINTOSC
- LFINTOSC
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
The HFINTOSC can produce clock frequencies from
1-16 MHz. The LFINTOSC generates a 31 kHz clock
frequency.
There is a PLL that can be used by the external oscilla-
tor. See Section 7.2.1.4 “4x PLL” for more details.
Additionally, there is a PLL that can be used by the
HFINTOSC
at
certain
frequencies.
See
Section 7.2.2.2 “2x PLL” for more details.
FIGURE 7-2:
EXTERNAL CLOCK (EC)
MODE OPERATION
7.2.1
EXTERNAL CLOCK SOURCES
An external clock source can be used as the device
system clock by performing one of the following
actions:
OSC1/CLKIN
PIC® MCU
Clock from
Ext. System
• Program the RSTOSC<2:0> bits in the
Configuration Words to select an external clock
source that will be used as the default system
clock upon a device Reset.
OSC2/CLKOUT
(1)
FOSC/4 or
I/O
• Write the NOSC<2:0> and NDIV<3:0> bits in the
OSCCON1 register to switch the system clock
source.
Note 1: Output depends upon CLKOUTEN bit of the
Configuration Words.
See Section 7.3 “Clock Switching” for more
information.
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7.2.1.2
LP, XT, HS Modes
Note 1: Quartz
crystal
characteristics
vary
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 7-3). The three modes select
a low, medium or high gain setting of the internal
inverter-amplifier to support various resonator types
and speed.
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
• LP Oscillator mode selects the lowest gain setting
of the internal inverter-amplifier. LP mode current
consumption is the least of the three modes. This
mode is designed to drive only 32.768 kHz
tuning-fork type crystals (watch crystals) but can
operate up to 100 kHz.
• XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three
modes. This mode is best suited to crystals and
resonators with a frequency rang up to 4 MHz.
• HS Oscillator mode selects the highest gain
setting of the internal inverter-amplifier. HS mode
current consumption is the highest of the three
modes. This mode is best suited for resonators
that require operating frequencies up to 20 MHz.
3: For oscillator design assistance, reference
the following Microchip Application Notes:
• AN826, Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices (DS00826)
• AN849, Basic PIC® Oscillator Design
(DS00849)
• AN943, Practical PIC® Oscillator
Analysis and Design (DS00943)
• AN949, Making Your Oscillator Work
(DS00949)
FIGURE 7-4:
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
Figure 7-3 and Figure 7-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
PIC® MCU
FIGURE 7-3:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
OSC1/CLKIN
C1
To Internal
Logic
PIC® MCU
(3)
(2)
RP
RF
Sleep
OSC1/CLKIN
C1
To Internal
Logic
OSC2/CLKOUT
(1)
C2
RS
Ceramic
Resonator
Quartz
Crystal
(2)
Sleep
RF
Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
OSC2/CLKOUT
(1)
C2
RS
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
Note 1: A series resistor (RS) may be required for
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
quartz crystals with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
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7.2.1.3
Oscillator Start-up Timer (OST)
Note 1: Quartz
crystal
characteristics
vary
If the oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR), Brown-out Reset (BOR), or a
wake-up from Sleep. The OST ensures that the
oscillator circuit, using a quartz crystal resonator or
ceramic resonator, has started and is providing a stable
system clock to the oscillator module.
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
7.2.1.4
4x PLL
the following Microchip Application Notes:
The oscillator module contains a PLL that can be used
with external clock sources to provide a system clock
source. The input frequency for the PLL must fall within
specifications. See the PLL Clock Timing
Specifications in Table 35-9.
• AN826, Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices (DS00826)
• AN849, Basic PICmicro® Oscillator
Design (DS00849)
• AN943, Practical PICmicro® Oscillator
Analysis and Design (DS00943)
The PLL may be enabled for use by one of two
methods:
1. Program the RSTOSC bits in the Configuration
Word 1 to enable the EXTOSC with 4x PLL.
• AN949, Making Your Oscillator Work
(DS00949)
2. Write the NOSC<2:0> bits in the OSCCON1
register to enable the EXTOSC with 4x PLL.
• TB097, Interfacing a Micro Crystal
MS1V-T1K 32.768 kHz Tuning Fork
Crystal to a PIC16F690/SS (DS91097)
7.2.1.5
Secondary Oscillator
• AN1288, Design Practices for
Low-Power External Oscillators
(DS01288)
The secondary oscillator is a separate oscillator block
that can be used as an alternate system clock source.
The secondary oscillator is optimized for 32.768 kHz,
and can be used with an external crystal oscillator
connected to the SOSCI and SOSCO device pins, or
an external clock source connected to the SOSCIN pin.
The secondary oscillator can be selected during
run-time using clock switching. Refer to Section 7.3
“Clock Switching” for more information.
FIGURE 7-5:
QUARTZ CRYSTAL
OPERATION
(SECONDARY
OSCILLATOR)
PIC® MCU
SOSCI
C1
C2
To Internal
Logic
32.768 kHz
Quartz
Crystal
SOSCO
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7.2.2
INTERNAL CLOCK SOURCES
7.2.2.1
HFINTOSC
The device may be configured to use the internal
oscillator block as the system clock by performing one
of the following actions:
The High-Frequency Internal Oscillator (HFINTOSC) is
a precision digitally-controlled internal clock source
that produces a stable clock up to 32 MHz. The
HFINTOSC can be enabled through one of the
following methods:
• Program the RSTOSC<2:0> bits in Configuration
Words to select the INTOSC clock source, which
will be used as the default system clock upon a
device Reset.
• Write the NOSC<2:0> bits in the OSCCON1
register to switch the system clock source to the
internal oscillator during run-time. See
Section 7.3 “Clock Switching” for more
information.
• Programming the RSTOSC<2:0> bits in
Configuration Word 1 to ‘110’ (1 MHz) or ‘000’
(32 MHz) to set the oscillator upon device
Power-up or Reset
• Write to the NOSC<2:0> bits of the OSCCON1
register during run-time
The HFINTOSC frequency can be selected by setting
the HFFRQ<3:0> bits of the OSCFRQ register.
The function of the OSC2/CLKOUT pin is determined
by the CLKOUTEN bit in Configuration Words.
The NDIV<3:0> bits of the OSCCON1 register allow for
division of the output of the selected clock source by a
range between 1:1 and 1:512.
The internal oscillator block has two independent
oscillators that can produce two internal system clock
sources.
7.2.2.2
2x PLL
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory-calibrated and operates up
to 32 MHz.
The oscillator module contains a PLL that can be used
with the HFINTOSC clock source to provide a system
clock source. The input frequency to the PLL is limited
to 8, 12, or 16 MHz, which will yield a system clock
source of 16, 24, or 32 MHz, respectively.
2. The LFINTOSC (Low-Frequency Internal
Oscillator) is factory-calibrated and operates at
31 kHz.
The PLL may be enabled for use by one of two
methods:
1. Program the RSTOSC bits in the Configuration
Word 1 to ‘000’ to enable the HFINTOSC (32
MHz). This setting configures the HFFRQ<3:0>
bits to ‘110’ (16 MHz) and activates the 2x PLL.
2. Write ‘000’ to the NOSC<2:0> bits in the
OSCCON1 register to enable the 2x PLL, and
write the correct value into the HFFRQ<3:0> bits
of the OSCFRQ register to select the desired
system clock frequency. See Register 6-6 for
more information.
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7.2.2.3
Internal Oscillator Frequency
Adjustment
The HFINTOSC and LFINTOSC internal oscillators are
both factory-calibrated. TH HFINTOSC oscillator can
be adjusted in software by writing to the OSCTUNE
register (Register 7-3). OSCTUNE does not affect the
LFINTOSC frequency.
The default value of the OSCTUNE register is 00h. The
value is a 6-bit two’s complement number. A value of
1Fh will provide an adjustment to the maximum
frequency. A value of 20h will provide an adjustment to
the minimum frequency.
When the OSCTUNE register is modified, the
HFINTOSC oscillator frequency will begin shifting to the
new frequency. Code execution continues during this
shift. There is no indication that the shift has occurred.
7.2.2.4
LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is
a factory-calibrated 31 kHz internal clock source.
The LFINTOSC is the clock source for the Power-up
Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe
Clock Monitor (FSCM). The LFINTOSC can also be
used as the system clock, or as a clock or input source
to certain peripherals.
The LFINTOSC is selected as the clock source through
one of the following methods:
• Programming the RSTOSC<2:0> bits of
Configuration Word 1 to enable LFINTOSC.
• Write to the NOSC<2:0> bits of the OSCCON1
register.
7.2.2.5
Oscillator Status and Manual Enable
The ‘ready’ status of each oscillator is displayed in the
OSCSTAT1 register (Register 7-4). The oscillators can
also be manually enabled through the OSCEN register
(Register 7-5). Manual enables make it possible to
verify the operation of the EXTOSC or SOSC crystal
oscillators. This can be achieved by enabling the
selected oscillator, then watching the corresponding
‘ready’ state of the oscillator in the OSCSTAT1 register.
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If DOZE is in effect, the switch occurs on the next clock
cycle, whether or not the CPU is operating during that
cycle.
7.3
Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the New Oscillator Source (NOSC) and New Divider
Selection Request (NDIV) bits of the OSCCON1
register. The following clock sources can be selected:
Changing the clock post-divider without changing the
clock source (i.e., changing FOSC from 1 MHz to 2
MHz) is handled in the same manner as a clock source
change, as described previously. The clock source will
already be active, so the switch is relatively quick.
CSWHOLD must be clear (CSWHOLD = 0) for the
switch to complete.
• External Oscillator (EXTOSC)
• High-Frequency Internal Oscillator (HFINTOSC)
• Low-Frequency Internal Oscillator (LFINTOSC)
• Secondary Oscillator (SOSC)
• EXTOSC with 4x PLL
• HFINTOSC with 2x PLL
The current COSC and CDIV are indicated in the
OSCCON2 register up to the moment when the switch
actually occurs, at which time OSCCON2 is updated
and ORDY is set. NOSCR is cleared by hardware to
indicate that the switch is complete.
7.3.1
NEW OSCILLATOR SOURCE
(NOSC) AND NEW DIVIDER
SELECTION REQUEST (NDIV) BITS
7.3.2
PLL INPUT SWITCH
The New Oscillator Source (NOSC) and New Divider
Selection Request (NDIV) bits of the OSCCON1
register select the system clock source and frequencies
that are used for the CPU and peripherals.
Switching between the PLL and any non-PLL source is
managed as described above. The input to the PLL is
established when NOSC<2:0> selects the PLL, and
maintained by the COSC setting.
When the new values of NOSC<2:0> and NDIV<3:0>
are written to OSCCON1, the current oscillator
selection will continue to operate as the system clock
while waiting for the new source to indicate that it is
stable and ready. In some cases, the newly requested
source may already be in use, and is ready
immediately. In the case of a divider-only change, the
new and old sources are the same and are ready
immediately. The device may enter Sleep while waiting
for the switch as described in Section 7.3.3 “Clock
Switch and Sleep”.
When NOSC<2:0> and COSC select the PLL with
different input sources, the system continues to run
using the COSC setting, and the new source is enabled
per NOSC<2:0>. When the new oscillator is ready (and
CSWHOLD = 0), system operation is suspended while
the PLL input is switched and the PLL acquires lock.
7.3.3
CLOCK SWITCH AND SLEEP
If OSCCON1 is written with a new value and the device
is put to Sleep before the switch completes, the switch
will not take place and the device will enter Sleep
mode.
When the new oscillator is ready, the New Oscillator is
Ready (NOSCR) bit of OSCCON3 and the Clock
Switch Interrupt Flag (CSWIF) bit of PIR3 become set
(CSWIF = 1). If Clock Switch Interrupts are enabled
(CSWIE = 1), an interrupt will be generated at that time.
The Oscillator Ready (ORDY) bit of OSCCON3 can
also be polled to determine when the oscillator is ready
in lieu of an interrupt.
When the device wakes from Sleep and the
CSWHOLD bit is clear, the device will wake with the
‘new’ clock active, and the Clock Switch Interrupt Flag
bit (CSWIF) will be set.
When the device wakes from Sleep and the
CSWHOLD bit is set, the device will wake with the ‘old’
clock active and the new clock will be requested again.
If the Clock Switch Hold (CSWHOLD) bit of OSCCON3
is clear, the oscillator switch will occur when the New
Oscillator Ready bit (NOSCR) is set and the interrupt (if
enabled) will be serviced at the new oscillator setting.
If CSWHOLD is set, the oscillator switch is suspended,
while execution continues using the current (old) clock
source. When the NOSCR bit is set, software should:
• Set CSWHOLD = 0so the switch can complete,
or
• Copy COSC into NOSC<2:0> to abandon the
switch.
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FIGURE 7-6:
CLOCK SWITCH (CSWHOLD = 0)
OSCCON1
WRITTEN
OSC #1
OSC #2
ORDY
Note 2
NOSCR
Note 1
CSWIF
USER
CLEAR
CSWHOLD
Note 1: CSWIF is asserted coincident with NOSCR; interrupt is serviced at OSC#2 speed.
2: The assertion of NOSCR is hidden from the user because it appears only for the duration of the switch.
FIGURE 7-7:
CLOCK SWITCH (CSWHOLD = 1)
OSCCON1
WRITTEN
OSC #1
OSC #2
ORDY
NOSCR
Note 1
CSWIF
USER
CLEAR
CSWHOLD
Note 1: CSWIF is asserted coincident with NOSCR, and may be cleared before or after clearing CSWHOLD = 0.
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FIGURE 7-8:
CLOCK SWITCH ABANDONED
OSCCON1
WRITTEN
OSCCON1
WRITTEN
OSC #1
ORDY
Note 2
NOSCR
Note 1
CSWIF
CSWHOLD
Note 1: CSWIF may be cleared before or after rewriting OSCCON1; CSWIF is not automatically cleared.
2: ORDY = 0if OSCCON1 does not match OSCCON2; a new switch will begin.
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7.4.2
FAIL-SAFE OPERATION
7.4
Fail-Safe Clock Monitor
When the external clock fails, the FSCM switches the
device clock to the HFINTOSC at 1 MHz clock
frequency and sets the bit flag OSFIF of the PIR3
register. Setting this flag will generate an interrupt if the
OSFIE bit of the PIE3 register is also set. The device
firmware can then take steps to mitigate the problems
that may arise from a failed clock. The system clock will
continue to be sourced from the internal clock source
until the device firmware successfully restarts the
external oscillator and switches back to external
operation, by writing to the NOSC<2:0> and
NDIV<3:0>bits of the OSCCON1 register.
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue operating should the external oscillator fail.
The FSCM is enabled by setting the FCMEN bit in the
Configuration Words. The FSCM is applicable to all
external Oscillator modes (LP, XT, HS, ECL, ECM,
ECH, and Secondary Oscillator).
FIGURE 7-9:
FSCM BLOCK DIAGRAM
Clock Monitor
Latch
External
Clock
S
Q
7.4.3
The Fail-Safe condition is cleared after a Reset,
executing SLEEP instruction or changing the
FAIL-SAFE CONDITION CLEARING
LFINTOSC
Oscillator
÷ 64
R
Q
a
NOSC<2:0> and NDIV<3:0> bits of the OSCCON1
register. When switching to the external oscillator or
external oscillator with PLL, the OST is restarted. While
the OST is running, the device continues to operate
from the INTOSC selected in OSCCON1. When the
OST times out, the Fail-Safe condition is cleared after
successfully switching to the external clock source. The
OSFIF bit should be cleared prior to switching to the
external clock source. If the Fail-Safe condition still
exists, the OSFIF flag will again be set by hardware.
31 kHz
(~32 s)
488 Hz
(~2 ms)
Sample Clock
Clock
Failure
Detected
7.4.1
FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64 (see Figure 7-9). Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
external clock goes low.
7.4.4
RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC
Clock modes so that the external clock signal can be
stopped if required. Therefore, the device will always
be executing code while the OST is operating when
using one of the EC modes.
FIGURE 7-10:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Test
Test
Note:
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
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7.5
Register Definitions: Oscillator Control
REGISTER 7-1:
OSCCON1: OSCILLATOR CONTROL REGISTER 1
U-0
—
R/W-f/f(1)
R/W-f/f(1)
R/W-f/f(1)
R/W-q/q(4)
R/W-q/q(4)
R/W-q/q(4)
R/W-q/q(4)
NOSC<2:0>(2,3)
NDIV<3:0>(2,3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
f = determined by fuse setting
q = Reset value is determined by hardware
bit 7
Unimplemented: Read as ‘0’
bit 6-4
NOSC<2:0>: New Oscillator Source Request bits
The setting requests a source oscillator and PLL combination per Table 7-1.
POR value = RSTOSC (Register 5-2).
bit 3-0
NDIV<3:0>: New Divider Selection Request bits
The setting determines the new postscaler division ratio per Table 7-2.
Note 1: The default value (f/f) is set equal to the RSTOSC Configuration bits.
2: If NOSC is written with a reserved value (Table 7-1), the HFINTOSC will be automatically selected as the
clock source.
3: When CSWEN = 0, this register is read-only and cannot be changed from the POR value.
4: When RSTOSC = 110(HFINTOSC 1 MHz) the NDIV bits will default to '0010' upon Reset; for all other
NOSC settings, the NVID bits will default to '0000' upon Reset.
REGISTER 7-2:
OSCCON2: OSCILLATOR CONTROL REGISTER 2
U-0
—
R-q/q(1)
R-q/q(1)
R-q/q(1)
R-q/q(1)
R-q/q(1)
R-q/q(1)
R-q/q(1)
COSC<2:0>
CDIV<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Reset value is determined by hardware
bit 7
Unimplemented: Read as ‘0’
bit 6-4
COSC<2:0>: Current Oscillator Source Select bits (read-only)
Indicates the current source oscillator and PLL combination per Table 7-1.
bit 3-0
CDIV<3:0>: Current Divider Select bits (read-only)
Indicates the current postscaler division ratio per Table 7-2.
Note 1: The Reset value (q/q) will match the NOSC<2:0>/NDIV<3:0> bits.
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TABLE 7-1:
NOSC/COSC BIT SETTINGS
Clock Source
TABLE 7-2:
NDIV<3:0>
CDIV<3:0>
NDIV/CDIV BIT SETTINGS
NOSC<2:0>
COSC<2:0>
Clock Divider
111
110
101
100
011
010
001
000
EXTOSC(1)
HFINTOSC (1 MHz)
Reserved
1111–1010
1001
Reserved
512
256
128
64
32
16
8
1000
LFINTOSC
0111
SOSC
0110
Reserved
EXTOSC with 4xPLL(1)
0101
0100
HFINTOSC with 2x PLL
(32 MHz)
0011
0010
4
0001
2
Note 1: EXTOSC configured by the FEXTOSC
bits of Configuration Word 1
(Register 5-1).
0000
1
REGISTER 7-3:
OSCCON3: OSCILLATOR CONTROL REGISTER 3
R/W/HC-0/0
R/W-0/0
SOSCPWR
R/W-0/0
R-0/0
R-0/0
U-0
—
U-0
U-0
—
CSWHOLD
bit 7
SOSCBE
ORDY
NOSCR
—
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Reset value is determined by hardware
bit 7
CSWHOLD: Clock Switch Hold bit
1= Clock switch will hold (with interrupt) when the oscillator selected by NOSC is ready
0= Clock switch may proceed when the oscillator selected by NOSC is ready; if this bit
is set at the time that NOSCR becomes ‘1’, the switch and interrupt will occur.
bit 6
SOSCPWR: Secondary Oscillator Power Mode Select bit
If SOSCBE = 0
1= Secondary oscillator operating in High-Power mode
0= Secondary oscillator operating in Low-Power mode
If SOSCBE = 1
x= Bit is ignored
bit 5
SOSCBE: Secondary Oscillator Bypass Enable bit
1= Secondary oscillator SOSCI is configured as an external clock input (ST-buffer); SOSCO is not
used.
0= Secondary oscillator is configured as a crystal oscillator using SOSCO and SOSCI pins.
bit 4
ORDY: Oscillator Ready bit (read-only)
1= OSCCON1 = OSCCON2; the current system clock is the clock specified by NOSC
0= A clock switch is in progress
bit 3
NOSCR: New Oscillator is Ready bit (read-only)
1= A clock switch is in progress and the oscillator selected by NOSC indicates a Ready condition
0= A clock switch is not in progress, or the NOSC-selected oscillator is not yet ready
bit 2-0
Unimplemented: Read as ‘0’
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REGISTER 7-4:
R-q/q
OSCSTAT1: OSCILLATOR STATUS REGISTER 1
R-q/q
U-0
—
R-q/q
LFOR
R-q/q
SOR
R-q/q
U-0
—
R-q/q
PLLR
EXTOR
HFOR
ADOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
q = Reset value is determined by hardware
bit 7
bit 6
EXTOR: EXTOSC (external) Oscillator Ready bit
1= The oscillator is ready to be used
0= The oscillator is not enabled, or is not yet ready to be used.
HFOR: HFINTOSC Oscillator Ready bit
1= The oscillator is ready to be used
0= The oscillator is not enabled, or is not yet ready to be used.
bit 5
bit 4
Unimplemented: Read as ‘0’
LFOR: LFINTOSC Oscillator Ready bit
1= The oscillator is ready to be used
0= The oscillator is not enabled, or is not yet ready to be used.
bit 3
bit 2
SOR: Secondary Oscillator Ready bit
1= The oscillator is ready to be used
0= The oscillator is not enabled, or is not yet ready to be used.
ADOR: ADCRC Oscillator Ready bit
1= The oscillator is ready to be used
0= The oscillator is not enabled, or is not yet ready to be used
bit 1
bit 0
Unimplemented: Read as ‘0’
PLLR: PLL is Ready bit
1= The PLL is ready to be used
0= The PLL is not enabled, the required input source is not ready, or the PLL is not ready.
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REGISTER 7-5:
R/W-0/0
OSCEN: OSCILLATOR MANUAL ENABLE REGISTER
R/W-0/0
HFOEN
U-0
—
R/W-0/0
LFOEN
R/W-0/0
R/W-0/0
ADOEN
U-0
—
U-0
—
EXTOEN
bit 7
SOSCEN
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
EXTOEN: External Oscillator Manual Request Enable bit
1= EXTOSC is explicitly enabled, operating as specified by FEXTOSC
0= EXTOSC could be enabled by another module
HFOEN: HFINTOSC Oscillator Manual Request Enable bit
1= HFINTOSC is explicitly enabled, operating as specified by OSCFRQ (Register 7-6)
0= HFINTOSC could be enabled by another module
bit 5
bit 4
Unimplemented: Read as ‘0’
LFOEN: LFINTOSC (31 kHz) Oscillator Manual Request Enable bit
1= LFINTOSC is explicitly enabled
0= LFINTOSC could be enabled by another module
bit 3
SOSCEN: Secondary Oscillator Manual Request Enable bit
1= Secondary Oscillator is explicitly enabled
0= Secondary Oscillator could be enabled by another module
bit 2
ADOEN: ADOSC (600 kHz) Oscillator Manual Request Enable bit
1= ADOSC is explicitly enabled
0= ADOSC could be enabled by another module
bit 1-0
Unimplemented: Read as ‘0’
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REGISTER 7-6:
OSCFRQ: HFINTOSC FREQUENCY SELECTION REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-1/1
R/W-1/1
R/W-0/0
bit 0
HFFRQ<3:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
HFFRQ<3:0>: HFINTOSC Frequency Selection bits
Nominal Freq. (MHz)
HFFRQ<3:0>
2x PLL Freq. (MHz)
(NOSC = 110)
(NOSC = 000)
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
1
2
Reserved
Reserved
4
8
16
24
12
16
32
32
32
Reserved
Reserved
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REGISTER 7-7:
OSCTUNE: HFINTOSC TUNING REGISTER
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
HFTUN<5:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
HFTUN<5:0>: HFINTOSC Frequency Tuning bits
01 1111= Maximum frequency
01 1110
•
•
•
00 0001
00 0000= Center frequency. Oscillator module is running at the calibrated frequency (default value).
11 1111
•
•
•
10 0000= Minimum frequency.
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TABLE 7-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OSCCON1
OSCCON2
—
—
NOSC<2:0>
COSC<2:0>
NDIV<3:0>
CDIV<3:0>
89
89
90
91
92
93
94
OSCCON3 CWSHOLD SOSCPWR SOSCBE ORDY
NOSCR
SOR
—
—
—
—
—
OSCSTAT1
OSCEN
EXTOR
EXTOEN
—
HFOR
HFOEN
—
ADOR
PLLR
—
—
—
LFOR
LFOEN
—
SOSCEN ADOEN
—
OSCFRQ
OSCTUNE
HFFRQ<3:0>
HFTUN<5:0>
—
—
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
TABLE 7-4:
SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES
Register
on Page
Name
Bits Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
—
—
—
—
CSWEN
—
—
—
CLKOUTEN
13:8
7:0
FCMEN
CONFIG1
64
RSTOSC2 RSTOSC1 RSTOSC0
FEXTOSC2 FEXTOSC1 FEXTOSC0
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
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8.0
INTERRUPTS
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
Many peripherals produce interrupts. Refer to the
corresponding chapters for details.
A block diagram of the interrupt logic is shown in
Figure 8-1.
FIGURE 8-1:
INTERRUPT LOGIC
TMR0IF
TMR0IE
Wake-up
(If in Sleep mode)
INTF
INTE
Peripheral Interrupts
(TMR1IF) PIR1<0>
IOCIF
IOCIE
Interrupt
to CPU
(TMR1IE) PIE1<0>
PEIE
GIE
PIRn<7>
PIEn<7>
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8.1
Operation
8.2
Interrupt Latency
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is three or four instruction cycles. The
interrupt is sampled during Q1 of the instruction cycle.
The actual interrupt latency then depends on the
instruction that is executing at the time the interrupt is
detected. See Figure 8-2 and Figure 8-3 for more
details.
• GIE bit of the INTCON register
• Interrupt Enable bit(s) for the specific interrupt
event(s)
• PEIE bit of the INTCON register (if the Interrupt
Enable bit of the interrupt event is contained in the
PIEx registers).
The PIR1, PIR2, PIR3 and PIR4 registers record
individual interrupts via interrupt flag bits. Interrupt flag
bits will be set, regardless of the status of the GIE, PEIE
and individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• Critical registers are automatically saved to the
shadow registers (See “Section 8.5 “Automatic
Context Saving”)
• PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
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FIGURE 8-2:
INTERRUPT LATENCY
Rev. 10-000269E
8/31/2016
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKOUT
INT
pin
Valid Interrupt
window(1)
PC
1 Cycle Instruction at PC
PC = 0x0004
PC - 1
PC - 2
PC + 1
PC = 0x0005 PC = 0x0006
PC = 0x0004 PC = 0x0005
Fetch
PC - 1
PC
123
123
Execute
Indeterminate
Latency(2)
Latency
Note 1: An interrupt may occur at any time during the interrupt window.
2: Since an interrupt may occur any time during the interrupt window, the actual latency can vary.
FIGURE 8-3:
INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(3)
CLKOUT
(4)
INT pin
INTF
(1)
(1)
(2)
(5)
Interrupt Latency
GIE
INSTRUCTION FLOW
PC
PC + 1
—
0004h
0005h
PC
Inst (PC)
PC + 1
Instruction
Fetched
Inst (PC + 1)
Inst (0004h)
Inst (0005h)
Inst (0004h)
Instruction
Executed
Forced NOP
Forced NOP
Inst (PC)
Inst (PC – 1)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT not available in all oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 35.0 “Electrical Specifications””.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
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8.3
Interrupts During Sleep
All interrupts can be used to wake from Sleep. To wake
from Sleep, the peripheral must be able to operate
without the system clock. The interrupt source must
have the appropriate Interrupt Enable bit(s) set prior to
entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEPinstruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to Section 9.0
“Power-Saving Operation Modes” for more details.
8.4
INT Pin
The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the PIE0 register. The INTEDG bit
of the INTCON register determines on which edge the
interrupt will occur. When the INTEDG bit is set, the
rising edge will cause the interrupt. When the INTEDG
bit is clear, the falling edge will cause the interrupt. The
INTF bit of the PIR0 register will be set when a valid
edge appears on the INT pin. If the GIE and INTE bits
are also set, the processor will redirect program
execution to the interrupt vector.
8.5
Automatic Context Saving
Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the shadow registers:
• W register
• STATUS register (except for TO and PD)
• BSR register
• FSR registers
• PCLATH register
Upon exiting the Interrupt Service Routine, these
registers are automatically restored. Any modifications
to these registers during the ISR will be lost. If
modifications to any of these registers are desired, the
corresponding shadow register should be modified and
the value will be restored when exiting the ISR. The
shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s
application, other registers may also need to be saved.
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8.6
Register Definitions: Interrupt Control
REGISTER 8-1:
R/W/HS/HC
GIE
INTCON: INTERRUPT CONTROL REGISTER
R/W-0/0
PEIE
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-1/1
INTEDG
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
HS = Hardware set
HC = Hardware clear
bit 7
bit 6
GIE: Global Interrupt Enable bit
1= Enables all active interrupts
0= Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1= Enables all active peripheral interrupts
0= Disables all peripheral interrupts
bit 5-1
bit 0
Unimplemented: Read as ‘0’
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of INT pin
0= Interrupt on falling edge of INT pin
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
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REGISTER 8-2:
PIE0: PERIPHERAL INTERRUPT ENABLE REGISTER 0
U-0
—
U-0
—
R/W/HS-0/0
TMR0IE
R/W-0/0
IOCIE
U-0
—
U-0
—
U-0
—
R/W/HS-0/0
INTE
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware set
bit 7-6
bit 5
Unimplemented: Read as ‘0’
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
bit 4
IOCIE: Interrupt-on-Change Interrupt Enable bit
1= Enables the IOC change interrupt
0= Disables the IOC change interrupt
bit 3-1
bit 0
Unimplemented: Read as ‘0’
INTE: INT External Interrupt Flag bit(1)
1= Enables the INT external interrupt
0= Disables the INT external interrupt
Note 1: The external interrupt GPIO pin is selected by INTPPS (Register 13-1).
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REGISTER 8-3:
R/W-0/0
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0/0
ADIE
R/W-0/0
RCIE
R/W-0/0
TXIE
R/W-0/0
SSP1IE
R/W-0/0
BCL1IE
R/W-0/0
TMR2IE
R/W-0/0
TMR1IE
TMR1GIE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR1GIE: Timer1 Gate Interrupt Enable bit
1= Enables the Timer1 gate acquisition interrupt
0= Disables the Timer1 gate acquisition interrupt
ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit
1= Enables the ADC interrupt
0= Disables the ADC interrupt
RCIE: EUSART Receive Interrupt Enable bit
1= Enables the EUSART receive interrupt
0= Disables the EUSART receive interrupt
TXIE: EUSART Transmit Interrupt Enable bit
1= Enables the EUSART transmit interrupt
0= Disables the EUSART transmit interrupt
SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit
1= Enables the MSSP interrupt
0= Disables the MSSP interrupt
BCL1IE: MSSP1 Bus Collision Interrupt Enable bit
1= MSSP bus collision interrupt enabled
0= MSSP bus collision interrupt not enabled
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the Timer2 to PR2 match interrupt
0= Disables the Timer2 to PR2 match interrupt
TMR1IE: Timer1 Overflow Interrupt Enable bit
1= Enables the Timer1 overflow interrupt
0= Disables the Timer1 overflow interrupt
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
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REGISTER 8-4:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0/0
R/W-0/0
C2IE
R/W-0/0
C1IE
R/W-0/0
NVMIE
R/W-0/0
SSP2IE
R/W-0/0
BCL2IE
R/W-0/0
TMR4IE
R/W-0/0
NCO1IE
TMR6IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
TMR6IE: TMR6 to PR6 Match Interrupt Enable bit
1= TMR6 to PR6 match interrupt is enabled
0= TMR6 to PR6 match is not enabled
bit 6
bit 5
C2IE: Comparator C2 Interrupt Enable bit
1= Enables the Comparator C2 interrupt
0= Disables the Comparator C2 interrupt
C1IE: Comparator C1 Interrupt Enable bit
1= Enables the Comparator C1 interrupt
0= Disables the Comparator C1 interrupt
bit 4
bit 3
bit 2
bit 1
bit 0
NVMIE: NVM Interrupt Enable Bit
1= ENVM task complete interrupt enabled
0= NVM interrupt not enabled
SSP2IE: Master Synchronous Serial Port (MSSP2) Interrupt Enable bit
1= Enables the MSSP2 interrupt
0= Disables the MSSP2 interrupt
BCL2IE: MSSP2 Bus Collision Interrupt Enable bit
1= MSSP bus collision interrupt enabled
0= MSSP bus collision interrupt not enabled
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1= TMR4 to PR4 match interrupt is enabled
0= TMR4 to PR4 match is not enabled
NCO1IE: NCO Interrupt Enable bit
1= NCO rollover interrupt enabled
0= NCO rollover interrupt not enabled
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
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REGISTER 8-5:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TMR3IE
R/W-0/0
CLC4IE
R/W-0/0
CLC3IE
R/W-0/0
CLC2IE
R/W-0/0
CLC1IE
TMR3GIE
OSFIE
bit 7
CSWIE
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
OSFIE: Oscillator Fail Interrupt Enable bit
1= Enables the Oscillator Fail interrupt
0= Disables the Oscillator Fail interrupt
CSWIE: Clock Switch Complete Interrupt Enable bit
1= The clock switch module interrupt is enabled
0= The clock switch module interrupt is not enabled
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR3GIE: Timer3 Gate Interrupt Enable bit
1= Timer3 Gate interrupt is enabled
0= Timer3 Gate interrupt is not enabled
TMR3IE: TMR3 Overflow Interrupt Enable bit
1= TMR3 overflow interrupt is enabled
0= TMR3 overflow interrupt is not enabled
CLC4IE: CLC4 Interrupt Flag bit
1= CLC4 interrupt is enabled
0= CLC4 interrupt is not enabled
CLC3IE: CLC3 Interrupt Flag bit
1= CLC3 interrupt is enabled
0= CLC3 interrupt is not enabled
CLC2IE: CLC2 Interrupt Enable bit
1= CLC2 interrupt enabled
0= CLC2 interrupt disabled
CLC1IE: CLC1 Interrupt Enable bit
1= CLC1 interrupt enabled
0= CLC1 interrupt disabled
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
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REGISTER 8-6:
R/W-0/0
PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4
R/W-0/0
CWG1IE
R/W-0/0
R/W-0/0
TMR5IE
R/W-0/0
CCP4IE
R/W-0/0
CCP3IE
R/W-0/0
CCP2IE
R/W-0/0
CCP1IE
CWG2IE
TMR5GIE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware set
bit 7
CWG2IE: CWG 2 Interrupt Enable bit
1= CWG2 interrupt enabled
0= CWG2 interrupt not enabled
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CWG1IE: CWG 1 Interrupt Enable bit
1= CWG1 interrupt enabled
0= CWG1 interrupt not enabled
TMR5GIE: Timer5 Gate Interrupt Enable bit
1= TMR5 Gate interrupt is enabled
0= TMR5 Gate interrupt is not enabled
TMR5IE: TMR5 Overflow Interrupt Enable bit
1= TMR5 overflow interrupt is enabled
0= TMR5 overflow interrupt is not enabled
CCP4IE: CCP4 Interrupt Enable bit
1= CCP4 interrupt is enabled
0= CCP4 interrupt is not enabled
CCP3IE: CCP3 Interrupt Enable bit
1= CCP3 interrupt is enabled
0= CCP3 interrupt is not enabled
CCP2IE: CCP2 Interrupt Enable bit
1= CCP2 interrupt is enabled
0= CCP2 interrupt is not enabled
CCP1IE: CCP1 Interrupt Enable bit
1= CCP1 interrupt is enabled
0= CCP1 interrupt is not enabled
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
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REGISTER 8-7:
PIR0: PERIPHERAL INTERRUPT REQUEST REGISTER 0
U-0
—
U-0
—
R/W/HS-0/0
TMR0IF
R-0
IOCIF(1)
U-0
—
U-0
—
U-0
—
R/W/HS-0/0
INTF
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HS= Hardware Set
bit 7-6
bit 5
Unimplemented: Read as ‘0’
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
bit 4
IOCIF: Interrupt-on-Change Interrupt Flag bit (read-only)
1= An enabled edge was detected by the IOC module. One of the IOCF bits is set.
0= No enabled edge is was detected by the IOC module. None of the IOCF bits is set.
Pins are individually masked via IOCxP and IOCxN.
bit 3-1
bit 0
Unimplemented: Read as ‘0’
INTF: INT External Interrupt Flag bit
1= The INT external interrupt occurred (must be cleared in software)
0= The INT external interrupt did not occur
Note 1: The IOCIF bit is the logical OR of all the IOCAF-IOCCF flags. Therefore, to clear the IOCIF flag,
application firmware must clear all of the IOCAF-IOCCF register bits.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
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REGISTER 8-8:
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W/HS-0/0 R/W/HS-0/0 R/HS/HC-0
R-0
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
SSP1IF BCL1IF TMR2IF TMR1IF
bit 0
TMR1GIF
bit 7
ADIF
RCIF
TXIF
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware set
bit 7
bit 6
TMR1GIF: Timer1 Gate Interrupt Flag bit
1= The Timer1 gate has gone inactive (the gate is closed)
0= The Timer1 gate has not gone inactive.
ADIF: Analog-to-Digital Converter (ADC) Interrupt Flag bit
1= The A/D conversion completed
0= The A/D conversion is not completed
bit 5
RCIF: EUSART Receive Interrupt Flag bit (read-only)
1= The EUSART1 receive buffer is not empty
0= The EUSART1 receive buffer is empty
bit 4
bit 3
bit 2
TXIF: EUSART Transmit Interrupt Flag bit (read-only)
1= The EUSART1 transmit buffer is empty
0= The EUSART1 transmit buffer is not empty
SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit
1= The Transmission/Reception/Bus Condition is complete (must be cleared in software)
0= Waiting for the Transmission/Reception/Bus Condition in progress
BCL1IF: MSSP Bus Collision Interrupt Flag bit
1= A bus collision was detected (must be cleared in software)
0= No bus collision was detected
bit 1
bit 0
TMR2IF: Timer2 to PR2 Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: Timer1 Overflow Interrupt Flag bit
1= TMR1 overflow occurred (must be cleared in software)
0= No TMR1 overflow occurred
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
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REGISTER 8-9:
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
TMR6IF
bit 7
C2IF
C1IF
NVMIF
SSP2IF
BCL2IF
TMR4IF
NCO1IF
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware set
bit 7
bit 6
TMR6IF: TMR6 to PR6 Match Interrupt Flag bit
1= TMR6 to PR6 match occurred (must be cleared in software)
0= No TMR6 to PR6 match occurred
C2IF: Comparator C2 Interrupt Flag bit
1= Comparator 2 interrupt asserted
0= Comparator 2 interrupt not asserted
bit 5
C1IF: Comparator C1 Interrupt Flag bit
1= Comparator 1 interrupt asserted
0= Comparator 1 interrupt not asserted
bit 4
bit 3
bit 2
bit 1
bit 0
NVMIF: NVM Interrupt Flag bit
1= The NVM has completed a programming task
0= NVM interrupt not asserted
SSP2IF: Master Synchronous Serial Port (MSSP2) Interrupt Flag bit
1= The Transmission/Reception/Bus Condition is complete (must be cleared in software)
0= Waiting for the Transmission/Reception/Bus Condition in progress
BCL2IF: MSSP2 Bus Collision Interrupt Flag bit
1= A bus collision was detected (must be cleared in software)
0= No bus collision was detected
TMR4IF: TMR4 to PR4 Match Interrupt Flag bit
1= TMR4 to PR4 match occurred (must be cleared in software)
0= No TMR4 to PR4 match occurred
NCO1IF: NCO Interrupt Flag bit
1= The NCO has rolled over.
0= No NCO interrupt is asserted.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
DS40001839B-page 108
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PIC16(L)F18326/18346
REGISTER 8-10: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
OSFIF
bit 7
CSWIF
TMR3GIF
TMR3IF
CLC4IF
CLC3IF
CLC2IF
CLC1IF
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware set
bit 7
bit 6
bit 5
OSFIF: Oscillator Fail-Safe Interrupt Flag bit
1= Fail-Safe Clock Monitor module has detected a failed oscillator
0= External oscillator operating normally
CSWIF: Clock Switch Complete Interrupt Flag bit
1= The clock switch module has completed the clock switch; new oscillator is ready
0= The clock switch module has not completed clock switch
TMR3GIF: Timer3 Gate Interrupt Flag bit
1= The TMR3 gate has gone inactive
0= The TMR3 gate has not gone inactive
TMR3IF: TMR3 Overflow Interrupt Flag bit
1= TMR3 overflow occurred (must be cleared in software)
0= No TMR3 overflow occurred
bit 4
bit 3
bit 2
CLC4IF: CLC4 Interrupt Flag bit
1= The CLC4OUT interrupt condition has been met
0= No CLC4 interrupt
CLC3IF: CLC3 Interrupt Flag bit
1= The CLC3OUT interrupt condition has been met
0= No CLC3 interrupt
bit 1
bit 0
CLC2IF: CLC2 Interrupt Flag bit
1= The CLC2OUT interrupt condition has been met
0= No CLC2 interrupt
CLC1IF: CLC1 Interrupt Flag bit
1= The CLC1OUT interrupt condition has been met
0= No CLC1 interrupt
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
2016-2017 Microchip Technology Inc.
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DS40001839B-page 109
PIC16(L)F18326/18346
REGISTER 8-11: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
CWG2IF
bit 7
CWG1IF
TMR5GIF
TMR5IF
CCP4IF
CCP3IF
CCP2IF
CCP1IF
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware set
bit 7
bit 6
CWG2IF: CWG 2 Interrupt Flag bit
1= CWG2 has gone into shutdown
0= CWG2 is operating normally, or interrupt cleared
CWG1IF: CWG1 Interrupt Flag bit
1= CWG1 has gone into shutdown
0= CWG1 is operating normally, or interrupt cleared
bit 5
bit 4
bit 3
TMR5GIF: Timer5 Gate Interrupt Flag bit
1= The TMR5 gate has gone inactive (the gate is closed).
0= The TMR5 gate has not gone inactive.
TMR5IF: Timer5 Overflow Interrupt Flag bit
1= TMR5 overflow occurred (must be cleared in software)
0= No TMR5 overflow occurred
CCP4IF: CCP4 Interrupt Flag bit
CCPM Mode
Value
Capture
Compare
PWM
Capture occurred
Compare match occurred
Output trailing edge occurred
1
0
(must be cleared in software) (must be cleared in software) (must be cleared in software)
Compare match did not
occur
Output trailing edge did not
occur
Capture did not occur
bit 2
CCP3IF: CCP3 Interrupt Flag bit
CCPM Mode
Value
Capture
Compare
PWM
Capture occurred
Compare match occurred
Output trailing edge occurred
1
(must be cleared in software) (must be cleared in software) (must be cleared in software)
Compare match did not
occur
Output trailing edge did not
occur
0
Capture did not occur
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PIC16(L)F18326/18346
REGISTER 8-11: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4 (CONTINUED)
bit 1
CCP2IF: CCP2 Interrupt Flag bit
CCPM Mode
Value
Capture
Compare
PWM
Capture occurred
Compare match occurred
Output trailing edge occurred
1
(must be cleared in software) (must be cleared in software) (must be cleared in software)
Compare match did not
occur
Output trailing edge did not
occur
0
Capture did not occur
bit 0
CCP1IF: CCP1 Interrupt Flag bit
CCPM Mode
Value
Capture
Compare
PWM
Capture occurred
Compare match occurred
Output trailing edge occurred
1
(must be cleared in software) (must be cleared in software) (must be cleared in software)
Compare match did not
occur
Output trailing edge did not
occur
0
Capture did not occur
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
TABLE 8-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIE0
PIE1
PIE2
PIE3
PIE4
PIR0
PIR1
PIR2
PIR3
PIR4
GIE
—
PEIE
—
—
—
—
—
—
—
INTEDG
INTE
100
101
102
103
104
105
106
107
108
109
110
TMR0IE
RCIE
IOCIE
TXIE
—
—
TMR1GIE
TMR6IE
OSFIE
ADIE
C2IE
CSWIE
SSP1IE
SSP2IE
CLC4IE
BCL1IE
BCL2IE
CLC3IE
TMR2IE TMR1IE
TMR4IE NCO1IE
C1IE
NVMIE
TMR3GIE TMR3IE
CLC2IE
CLC1IE
CWG2IE CWG1IE TMR5GIE TMR5IE CCP4IE CCP3IE CCP2IE CCP1IE
—
—
TMR0IF
RCIF
IOCIF
TXIF
—
—
—
INTF
TMR1GIF
TMR6IF
OSFIF
ADIF
C2IF
SSP1IF
SSP2IF
CLC4IF
CCP4IF
BCL1IF
BCL2IF
CLC3IF
CCP3IF
TMR2IF TMR1IF
TMR4IF NCO1IF
C1IF
NVMIF
CSWIF
TMR3GIF TMR3IF
CLC2IF
CCP2IF
CLC1IF
CCP1IF
CWG2IF CWG1IF TMR5GIF TMR5IF
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts.
2016-2017 Microchip Technology Inc.
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DS40001839B-page 111
PIC16(L)F18326/18346
9.0
POWER-SAVING OPERATION
MODES
The purpose of the Power-Down modes is to reduce
power consumption. There are three Power-Down
modes: Doze mode, IDLE mode and Sleep mode.
9.1
DOZE Mode
Doze mode allows for power savings by reducing CPU
operation and program memory access, without
affecting peripheral operation. Doze mode differs from
Sleep mode because the system oscillators continue to
operate, while only the CPU and program memory are
affected. The reduced execution saves power by
eliminating unnecessary operations within the CPU
and memory.
When the Doze Enable (DOZEN) bit is set
(DOZEN = 1), the CPU executes only one instruction
cycle out of every N cycles as defined by the
DOZE<2:0> bits of the CPUDOZE register. For
example, if DOZE<2:0> = 100, the instruction cycle
ratio is 1:32. The CPU and memory execute for one
instruction cycle and then lay idle for 31 instruction
cycles. During the unused cycles, the peripherals
continue to operate at the system clock speed.
FIGURE 9-1:
DOZE MODE OPERATION EXAMPLE
System
Clock
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
/ŶƐƚƌƵĐƚŝŽŶꢀ
WĞƌŝŽĚƐ
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
1
2
3
4
1
2
3
4
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
CPU Clock
PFM Op’s
Fetch
Exec
Fetch
Exec
Push
0004h
NOP
Fetch
Exec
Fetch
Exec
Exec(1,2)
Exec
CPU Op’s
Interrupt
Here
(ROI = 1)
DS40001839B-page 112
Preliminary
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PIC16(L)F18326/18346
9.1.1
DOZE OPERATION
9.1.3
IDLE MODE
The Doze operation is illustrated in Figure 9-1. For this
example:
When the IDLE Enable (IDLEN) bit is clear
(IDLEN = 0), the SLEEPinstruction will put the device
into full Sleep mode (see Section 9.2 “Sleep Mode”).
When IDLEN is set (IDLEN = 1), the SLEEPinstruction
will put the device into Idle mode. In IDLE mode, the
CPU and memory operations are halted, but the
peripheral clocks continue to run. This mode is similar
to DOZE mode, except that in IDLE both the CPU and
program memory are shut off.
• Doze enable (DOZEN) bit set (DOZEN = 1)
• DOZE<2:0> = 001(1:4) ratio
• Recover-on-Interrupt (ROI) bit set (ROI = 1)
As with normal operation, the program memory fetches
for the next instruction cycle. The instruction clocks to
the peripherals continue throughout.
9.1.2
INTERRUPTS DURING DOZE
Note:
Note:
Peripherals using FOSC will continue
running while in IDLE (but not in Sleep).
If an interrupt occurs and the Recover-on-Interrupt
(ROI) bit is clear (ROI = 0) at the time of the interrupt,
the Interrupt Service Routine (ISR) continues to exe-
cute at the rate selected by DOZE<2:0>. Interrupt
latency is extended by the DOZE<2:0> ratio.
If CLKOUT is enabled (CLKOUT = 0,
Configuration Word 1), the output will
continue operating while in IDLE.
If an interrupt occurs and the ROI bit is set (ROI = 1) at
the time of the interrupt, the DOZEN bit is cleared and
the CPU executes at full speed. The prefetched instruc-
tion is executed and then the interrupt vector sequence
is executed. In Figure 9-1, the interrupt occurs during
the 2nd instruction cycle of the Doze period, and imme-
diately brings the CPU out of Doze. If the Doze-on-Exit
(DOE) bit is set (DOE = 1) when the RETFIE operation
is executed, DOZEN is set, and the CPU executes at
the reduced rate based on the DOZE<2:0> ratio.
9.1.3.1
IDLE and Interrupts
IDLE mode ends when an interrupt occurs (even if
GIE = 0), but IDLEN is not changed. The device can
re-enter IDLE by executing the SLEEPinstruction.
If Recover-on-Interrupt is enabled (ROI = 1), the
interrupt that brings the device out of Idle also restores
full-speed CPU execution when DOZE is also enabled.
9.1.3.2
IDLE and WDT
When in IDLE, the WDT Reset is blocked and will
instead wake the device. The WDT wake-up is not an
interrupt, therefore ROI does not apply.
Note:
The WDT can bring the device out of
IDLE, in the same way it brings the device
out of Sleep. The DOZEN bit is not
affected.
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PIC16(L)F18326/18346
9.2.1
WAKE-UP FROM SLEEP
9.2
Sleep Mode
The device can wake-up from Sleep through one of the
following events:
Sleep mode is entered by executing the SLEEP
instruction, while the Idle Enable (IDLEN) bit of the
CPUDOZE register is clear (IDLEN = 0). If the SLEEP
instruction is executed while the IDLEN bit is set
(IDLEN = 1), the CPU will enter the Idle mode
(Section 9.2.3 “Low-Power Sleep Mode”).
1. External Reset input on MCLR pin, if enabled
2. BOR Reset, if enabled.
3. POR Reset.
4. Watchdog Timer, if enabled
Upon entering Sleep mode, the following conditions
exist:
5. Interrupts by peripherals capable of running
during Sleep (see individual peripheral for more
information).
1. Resets other than WDT are not affected by
Sleep mode; WDT will be cleared but keeps
running if enabled for operation during Sleep
The first three events will cause a device Reset. The
last two events are considered a continuation of
program execution. To determine whether a device
Reset or wake-up event occurred, refer to Section 6.11
“Determining the Cause of a Reset”.
2. The PD bit of the STATUS register is cleared
3. The TO bit of the STATUS register is set
4. The CPU and System clocks are disabled
5. 31 kHz LFINTOSC, HFINTOSC and SOSC will
remain enabled if any peripheral has requested
them as a clock source or if the HFOEN,
LFOEN, or SOSCEN bits of the OSCEN register
are set.
The WDT is cleared when the device wakes-up from
Sleep, regardless of the source of wake-up.
9.2.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
6. ADC is unaffected if the dedicated ADCRC
oscillator is selected. When the ADC clock is
something other than ADCRC,
a SLEEP
• If the interrupt occurs before the execution of a
SLEEPinstruction
instruction causes the present conversion to be
aborted and the ADC module is turned off,
although the ADON bit remains active.
- SLEEPinstruction will execute as a NOP
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
- PD bit of the STATUS register will not be
cleared
7. I/O ports maintain the status they had before
SLEEP was executed (driving high, low, or
high-impedance) only if no peripheral connected
to the I/O port is active.
• If the interrupt occurs during or after the execu-
tion of a SLEEPinstruction
Refer to individual chapters for more details on
peripheral operation during Sleep.
- SLEEPinstruction will be completely
executed
To minimize current consumption, the following
conditions should be considered:
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared
- I/O pins should not be floating
- External circuitry sinking current from I/O pins
- Internal circuitry sourcing current from I/O
pins
- Current draw from pins with internal weak
pull-ups
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
- Modules using any oscillator
I/O pins that are high-impedance inputs should be
pulled to VDD or VSS externally to avoid switching
currents caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include modules such as the DAC and FVR
modules. See Section 24.0 “5-bit Digital-to-Analog
Converter (DAC1) Module” and Section 16.0 “Fixed
Voltage Reference (FVR)” for more information on
these modules.
DS40001839B-page 114
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PIC16(L)F18326/18346
FIGURE 9-2:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
(3)
CLKOUT(2)
TOST
Interrupt Latency(4)
Interrupt flag
GIE bit
(INTCON reg.)
Processor in
Sleep
Instruction Flow
PC
PC
PC + 1
PC + 2
PC + 2
PC + 2
0004h
0005h
Instruction
Fetched
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = Sleep
Instruction
Executed
Forced NOP
Forced NOP
Sleep
Inst(PC + 1)
Inst(PC - 1)
Inst(0004h)
Note 1:
External clock. High, Medium, Low mode assumed.
CLKOUT is shown here for timing reference.
TOST = 1024 TOSC. This delay does not apply to EC and INTOSC Oscillator modes.
GIE = 1assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
2:
3:
4:
2016-2017 Microchip Technology Inc.
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DS40001839B-page 115
PIC16(L)F18326/18346
9.2.3
LOW-POWER SLEEP MODE
The PIC16F18326/18346 device contains an internal
Low Dropout (LDO) voltage regulator, which allows the
device I/O pins to operate at voltages up to 5.5V while
the internal device logic operates at a lower voltage.
The LDO and its associated reference circuitry must
remain active when the device is in Sleep mode.
The PIC16F18326/18346 allows the user to optimize
the operating current in Sleep, depending on the
application requirements.
Low-Power Sleep mode can be selected by setting the
VREGPM bit of the VREGCON register. Depending on
the configuration of this bit, the LDO and reference cir-
cuitry are placed in a low-power state when the device
is in Sleep.
9.2.3.1
Sleep Current vs. Wake-up Time
In the default operating mode, the LDO and reference
circuitry remain in the normal configuration while in
Sleep. The device is able to exit Sleep mode quickly
since all circuits remain active. In Low-Power Sleep
mode, when waking-up from Sleep, an extra delay time
is required for these circuits to return to the normal
configuration and stabilize.
The Low-Power Sleep mode is beneficial for
applications that stay in Sleep mode for long periods of
time. The Normal mode is beneficial for applications
that need to wake from Sleep quickly and frequently.
9.2.3.2
Peripheral Usage in Sleep
Some peripherals that can operate in Sleep mode will
not operate properly with the Low-Power Sleep mode
selected. The Low-Power Sleep mode is intended for
use with these peripherals:
• Brown-out Reset (BOR)
• Watchdog Timer (WDT)
• External interrupt pin/Interrupt-on-change pins
• Timer 1 (with external clock source)
It is the responsibility of the end user to determine what
is acceptable for their application when setting the
VREGPM settings in order to ensure operation in
Sleep.
Note:
The PIC16LF18326/18346 does not have
a configurable Low-Power Sleep mode.
PIC16LF18326/18346 is an unregulated
device and is always in the lowest power
state when in Sleep, with no wake-up time
penalty. This device has a lower maximum
VDD and I/O voltage than the
PIC16F18326/18346. See Section 35.0
“Electrical Specifications” for more
information.
DS40001839B-page 116
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PIC16(L)F18326/18346
9.3
Register Definitions: Voltage Regulator Control
REGISTER 9-1:
VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-1/1
VREGPM
Reserved
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
bit 1
Unimplemented: Read as ‘0’
VREGPM: Voltage Regulator Power Mode Selection bit
1= Low-Power Sleep mode enabled in Sleep(2); Draws lowest current in Sleep, slower wake-up
0= Normal-Power Sleep mode enabled in Sleep(2); Draws higher current in Sleep, faster wake-up
bit 0
Reserved: Read as ‘1’. Maintain this bit set.
Note 1: PIC16F18326/18346 only.
2: See Section 35.0 “Electrical Specifications”.
REGISTER 9-2:
CPUDOZE: DOZE AND IDLE REGISTER
R/W-0/u
R/W/HC/HS-0/0
DOZEN(1,2)
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
IDLEN
ROI
DOE
—
DOZE<2:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
IDLEN: Idle Enable bit
1= A SLEEPinstruction inhibits the CPU clock, but not the peripheral clock(s)
0= A SLEEPinstruction places the device into Full-Sleep mode
DOZEN: Doze Enable bit(1,2)
1= The CPU executes instruction cycles according to DOZE setting
0= The CPU executes all instruction cycles (fastest, highest power operation)
ROI: Recover-on-Interrupt bit
1= Entering the Interrupt Service Routine (ISR) makes DOZEN = 0bit, bringing the CPU to full-speed operation.
0= Interrupt entry does not change DOZEN
DOE: Doze-on-Exit bit
1= Executing RETFIE makes DOZEN = 1, bringing the CPU to reduced speed operation.
0= RETFIE does not change DOZEN
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DOZE<2:0>: Ratio of CPU Instruction Cycles to Peripheral Instruction Cycles
111= 1:256
110= 1:128
101= 1:64
100= 1:32
011= 1:16
010= 1:8
001= 1:4
000= 1:2
Note 1: When ROI = 1or DOE = 1, DOZEN is changed by hardware interrupt entry and/or exit.
2: Entering ICD overrides DOZEN, returning the CPU to full execution speed; this bit is not affected.
2016-2017 Microchip Technology Inc.
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PIC16(L)F18326/18346
TABLE 9-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIE0
GIE
—
PEIE
—
—
—
—
—
—
—
—
—
INTEDG
INTE
100
101
102
103
104
105
106
107
108
109
110
174
174
175
175
176
176
177
177
178
30
TMR0IE
IOCIE
PIE1
TMR1GIE
TMR6IE
OSFIE
CWG2IE
—
ADIE
C2IE
RCIE
C1IE
TXIE
SSP1IE BCL1IE TMR2IE
TMR1IE
NCO1IE
CLC1IE
CCP1IE
INTF
PIE2
NVMIE SSP2IE BCL2IE TMR4IE
PIE3
CSWIE TMR3GIE TMR3IE CLC4IE CLC3IE
CLC2IE
CCP2IE
—
TMR5GIE TMR5IE CCP4IE CCP3IE
PIE4
CWG1IE
—
TMR0IF
RCIF
IOCIF
TXIF
PIR0
—
—
PIR1
TMR1GIF
TMR6IF
OSFIF
ADIF
C2IF
SSP1IF BCL1IF
TMR2IF
TMR4IF
CLC2IF
TMR1IF
NCO1IF
CLC1IF
PIR2
C1IF
NVMIF SSP2IF BCL2IF
PIR3
CSWIF TMR3GIF TMR3IF CLC4IF CLC3IF
PIR4
CWG2IF CWG1IF TMR5GIF TMR5IF CCP4IF CCP3IF CCP2IF
CCP1IF
IOCAP0
IOCAN0
IOCAF0
—
IOCAP
IOCAN
IOCAF
IOCBP(1)
IOCBN(1)
IOCBF(1)
IOCCP
IOCCN
IOCCF
STATUS
VREGCON(2)
CPUDOZE
WDTCON
—
—
—
—
IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1
IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1
IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1
—
—
—
—
—
—
—
—
—
—
—
IOCBP7
IOCBN7
IOCBF7
IOCBP6
IOCBN6
IOCBF6
IOCBP5 IOCBP4
IOCBN5 IOCBN4
IOCBF5 IOCBF4
—
—
IOCCP7(1) IOCCP6(1) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1
IOCCN7(1) IOCCN6(1) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1
IOCCF7(1) IOCCF6(1) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1
IOCCP0
IOCCN0
IOCCF0
C
—
—
—
—
—
—
TO
—
PD
Z
DC
—
—
—
VREGPM
DOZE<2:0>
—
117
117
121
IDLEN
—
DOZEN
—
ROI
DOE
WDTPS<4:0>
SWDTEN
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode.
Note 1: PIC16(L)F18346 only.
2: PIC16F18326/18346 only.
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10.0 WATCHDOG TIMER (WDT)
The Watchdog Timer is a system timer that generates
a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.
The WDT has the following features:
• Independent clock source
• Multiple operating modes
- WDT is always ON
- WDT is OFF when in Sleep
- WDT is controlled by software
- WDT is always OFF
• Configurable time-out period is from 1 ms to 256
seconds (nominal)
• Multiple WDT clearing conditions
• Operation during Sleep
FIGURE 10-1:
WATCHDOG TIMER BLOCK DIAGRAM
WDTE<1:0> = 01
SWDTEN
23-bit Programmable
WDTE<1:0> = 11
LFINTOSC
WDT Time-out
Prescaler WDT
WDTE<1:0> = 10
Sleep
WDTPS<4:0>
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10.1 Independent Clock Source
10.3 Time-out Period
The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator. Time intervals in this
chapter are based on a nominal interval of 1 ms. See
Table 35-8 for the LFINTOSC specification.
The WDTPS<4:0> bits of the WDTCON register set the
time-out period from 1 ms to 256 seconds (nominal).
After a Reset, the default time-out period is two
seconds.
10.2 WDT Operating Modes
10.4 Clearing the WDT
The Watchdog Timer module has four operating modes
controlled by the WDTE<1:0> bits in Configuration
Words (see Table 10-1).
The WDT is cleared when any of the following
conditions occur:
• Any Reset
• CLRWDTinstruction is executed
• Device enters Sleep
10.2.1
WDT IS ALWAYS ON
When the WDTE bits of Configuration Words are set to
‘11’, the WDT is always ON.
• Device wakes up from Sleep due to an interrupt
• Oscillator fail
• WDT is disabled
• Oscillator Start-up Timer (OST) is running
WDT protection is active during Sleep.
10.2.2
WDT IS OFF IN SLEEP
See Table 10-2 for more information.
When the WDTE bits of Configuration Words are set to
‘10’, the WDT is on, except in Sleep.
10.5 Operation During Sleep
WDT protection is not active during Sleep.
When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting.
10.2.3
WDT CONTROLLED BY SOFTWARE
When the WDTE bits of Configuration Words are set to
‘01’, the WDT is controlled by the SWDTEN bit of the
WDTCON register.
When the device exits Sleep, the WDT is cleared
again. The WDT remains clear until the OST, if
enabled, completes. See Section 7.0 “Oscillator
Module” for more information on the OST.
WDT protection is unchanged by Sleep. See
Table 10-1 for more details.
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. See STATUS Register (Register 4-1) for more
information.
10.2.4
WDT IS ALWAYS OFF
When the WDTE bits are set to ‘00’, the WDT is
disabled, and the SWDTEN bit of the WDTCON is
ignored.
TABLE 10-1: WDT OPERATING MODES
Device
Mode
WDTE<1:0>
SWDTEN
WDT Mode
11
10
X
X
X
Active
Awake
Sleep
Active
Disabled
Active
1
0
X
01
00
X
X
Disabled
Disabled
TABLE 10-2: WDT CLEARING CONDITIONS
Conditions
WDT
WDTE = 00
Cleared and Disabled
WDTE = 01 and SWDTEN = 0
Exit Sleep due to a Reset + System Clock = XT, HS, LP
Exit Sleep due to a Reset + System Clock = HFINTOSC, LFINTOSC, EC, SOSC
Exit Sleep due to an interrupt
Cleared until the end of OST
Enter Sleep
CLRWDTCommand
Cleared
Oscillator Failure (see Section 7.4 “Fail-Safe Clock Monitor”)
System Reset
Any clock switch or divider change (see Section 7.3 “Clock Switching”)
Unaffected
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10.6 Register Definitions: Watchdog Control
REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
—
U-0
—
R/W-0/0
R/W-1/1
R/W-0/0
WDTPS<4:0>(1)
R/W-1/1
R/W-1/1
R/W-0/0
SWDTEN
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-m/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-1
Unimplemented: Read as ‘0’
WDTPS<4:0>: Watchdog Timer Period Select bits(1)
Bit Value = Prescale Rate
11111 = Reserved. Results in minimum interval (1:32)
•
•
•
10011 = Reserved. Results in minimum interval (1:32)
10010 = 1:8388608 (223) (Interval 256s nominal)
10001 = 1:4194304 (222) (Interval 128s nominal)
10000 = 1:2097152 (221) (Interval 64s nominal)
01111 = 1:1048576 (220) (Interval 32s nominal)
01110 = 1:524288 (219) (Interval 16s nominal)
01101 = 1:262144 (218) (Interval 8s nominal)
01100 = 1:131072 (217) (Interval 4s nominal)
01011 = 1:65536 (Interval 2s nominal) (Reset value)
01010 = 1:32768 (Interval 1s nominal)
01001 = 1:16384 (Interval 512 ms nominal)
01000 = 1:8192 (Interval 256 ms nominal)
00111 = 1:4096 (Interval 128 ms nominal)
00110 = 1:2048 (Interval 64 ms nominal)
00101 = 1:1024 (Interval 32 ms nominal)
00100 = 1:512 (Interval 16 ms nominal)
00011 = 1:256 (Interval 8 ms nominal)
00010 = 1:128 (Interval 4 ms nominal)
00001 = 1:64 (Interval 2 ms nominal)
00000 = 1:32 (Interval 1 ms nominal)
bit 0
SWDTEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 1x:
This bit is ignored.
If WDTE<1:0> = 01:
1= WDT is turned on
0= WDT is turned off
If WDTE<1:0> = 00:
This bit is ignored.
Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.
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TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STATUS
—
—
—
—
—
TO
PD
Z
DC
C
30
WDTCON
WDTPS<4:0>
SWDTEN
121
Legend: x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
Watchdog Timer.
TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER
Register
on Page
Name
Bits Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2 Bit 9/1 Bit 8/0
—
—
STVREN PPS1WAY
WDTE1
—
BORV
—
13:8
7:0
DEBUG
CONFIG2
65
BOREN1 BOREN0 LPBOREN
—
WDTE0 PWRTE MCLRE
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.
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11.0 NONVOLATILE MEMORY
(NVM) CONTROL
TABLE 11-1: FLASH MEMORY
ORGANIZATION BY DEVICE
NVM is separated into two types: Program Flash
Memory and Data EEPROM.
Write
Latches
(words)
Row Erase
(words)
Device
NVM is accessible by using both the FSR and INDF
registers, or through the NVMREG register interface.
PIC16(L)F18326
PIC16(L)F18346
32
32
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump rated to operate over the operating
voltage range of the device.
It is important to understand the Program Flash
Memory structure for erase and programming
operations. Program Flash Memory is arranged in
rows. A row consists of 32 14-bit program memory
words. A row is the minimum size that can be erased
by user software.
NVM can be protected in two ways; by either code
protection or write protection.
Code protection (CP and CPD bits in Configuration
Word 4) disables access, reading and writing, to both
the Program Flash Memory and EEPROM via external
device programmers. Code protection does not affect
the self-write and erase functionality. Code protection
can only be Reset by a device programmer performing
a Bulk Erase to the device, clearing all nonvolatile
memory, Configuration bits, and User IDs.
All or a portion of a row can be programmed. Data to be
written into the program memory row is written to 14-bit
wide data write latches. These latches are not directly
accessible to the user, but may be loaded via
sequential writes to the NVMDATH:NVMDATL register
pair.
Write protection prohibits self-write and erase to a
portion or all of the Program Flash Memory, as defined
by the WRT<1:0> bits of Configuration Word 3. Write
protection does not affect a device programmer’s ability
to read, write, or erase the device.
Note:
To modify only a portion of a previously
programmed row, then the contents of the
entire row must be read and saved in
RAM prior to the erase. Then, the new
data and retained data can be written into
the write latches to reprogram the row of
11.1 Program Flash Memory
Program
Flash
Memory.
Any
Program Flash Memory consists of 16,384 14-bit words
as user memory, with additional words for User ID
information, Configuration Words, and interrupt
vectors. Program Flash Memory provides storage
locations for:
unprogrammed locations can be written
without first erasing the row. In this case,
it is not necessary to save and rewrite the
other previously programmed locations
11.1.1
PROGRAM MEMORY VOLTAGES
• User program instructions
• User defined data
The Program Flash Memory is readable and writable
during normal operation over the full VDD range.
Program Flash Memory data can be read and/or written
to through:
11.1.1.1
Programming Externally
• CPU instruction fetch (read-only)
• FSR/INDF indirect access (read-only)
(Section 11.3 “FSR and INDF Access”)
• NVMREG access (Section 11.4 “NVMREG
Access”
The program memory cell and control logic support
write and Bulk Erase operations down to the minimum
device operating voltage.
11.1.1.2
Self-Programming
• In-Circuit Serial Programming™ (ICSP™)
The program memory cell and control logic will support
write and row erase operations across the entire VDD
range. Bulk Erase is not supported when
self-programming.
Read operations return a single word of memory. When
write and erase operations are done on a row basis, the
row size is defined in Table 11-1. Program Flash
Memory will erase to a logic ‘1’ and program to a logic
‘0’.
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11.2 Data EEPROM
11.4 NVMREG Access
Data EEPROM consists of 256 bytes of user data
memory. The EEPROM provides storage locations for
8-bit user defined data.
The NVMREG interface allows read/write access to all
the locations accessible by FSRs, and also read/write
access to the User ID locations and EEPROM, and
read-only access to the device identification, revision,
and Configuration data.
EEPROM can be read and/or written through:
• FSR/INDF indirect access (Section 11.3 “FSR
and INDF Access”)
• NVMREG access (Section 11.4 “NVMREG
Access”)
Reading, writing, or erasing of NVM via the NVMREG
interface is prevented when the device is
code-protected.
• In-Circuit Serial Programming (ICSP)
11.4.1
NVMREG READ OPERATION
Unlike Program Flash Memory, which must be written
to by row, EEPROM can be written to byte-by-byte.
To read a NVM location using the NVMREG interface,
the user must:
1. Clear the NVMREGS bit of the NVMCON1
register if the user intends to access Program
Flash Memory locations, or set NVMREGS if the
user intends to access User ID, Configuration,
or EEPROM locations.
11.3 FSR and INDF Access
The FSR and INDF registers allow indirect access to
the Program Flash Memory or EEPROM.
11.3.1
FSR READ
2. Write the desired address into the
With the intended address loaded into an FSR register,
a MOVIWinstruction or read of INDF will read data from
the Program Flash Memory or EEPROM. The CPU
operation is suspended during the read, and resumes
immediately after. Read operations return a single word
of memory. When the MSB of the FSR (ex: FSRxH) is
set to 0x70, the lower 8-bit address value (in FSRxL)
determines the EEPROM location that may be read
from (through the INDF register). In other words, the
EEPROM address range 0x00-0xFF is mapped into the
FSR address space between 0x7000-0x70FF. Writing
to the EEPROM cannot be accomplished via the
FSR/INDF interface.
NVMADRH:NVMADRL
(Table 11-2).
register
pair
3. Set the RD bit of the NVMCON1 register to
initiate the read.
Once the read control bit is set, the CPU operation is
suspended during the read, and resumes immediately
after. The data is available in the very next cycle, in the
NVMDATH:NVMDATL register pair; therefore, it can be
read as two bytes in the following instructions.
NVMDATH:NVMDATL register pair will hold this value
until another read or until it is written to by the user.
Upon completion, the RD bit is cleared by hardware.
11.3.2
FSR WRITE
Writing/erasing the NVM through the FSR registers (ex.
MOVWI instruction) is not supported in the
PIC16(L)F18326/18346 devices.
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FIGURE 11-1:
PROGRAM FLASH
MEMORY READ
FLOWCHART
Start Read Operation
Select Memory:
Program Flash Memory, EEPROM,
Config. Words, User ID (NVMREGS)
Select Word Address
(NVMADRH:NVMADRL)
Initiate Read Operation
(RD = 1)
Data read now in
NVMDATH:NVMDATL
End Read Operation
EXAMPLE 11-1:
PROGRAM FLASH MEMORY READ
* This code block will read 1 word of program
* memory at the memory address:
PROG_ADDR_HI : PROG_ADDR_LO
*
*
data will be returned in the variables;
PROG_DATA_HI, PROG_DATA_LO
BANKSEL NVMADRL
; Select Bank for NVMCON registers
MOVLW
MOVWF
MOVLW
MOVWF
PROG_ADDR_LO
NVMADRL
PROG_ADDR_HI
NVMADRH
;
; Store LSB of address
;
; Store MSB of address
BCF
BSF
NVMCON1,NVMREGS ; Do not select Configuration Space
NVMCON1,RD
; Initiate read
MOVF
NVMDATL,W
; Get LSB of word
MOVWF
MOVF
PROG_DATA_LO
NVMDATH,W
; Store in user location
; Get MSB of word
MOVWF
PROG_DATA_HI
; Store in user location
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11.4.2
NVM UNLOCK SEQUENCE
FIGURE 11-2:
NVM UNLOCK
SEQUENCE FLOWCHART
The unlock sequence is a mechanism that protects the
NVM from unintended self-write programming or
erasing. The sequence must be executed and
completed without interruption to successfully
complete any of the following operations:
Start Unlock Sequence
Write 55h to NVMCON2
Write AAh to NVMCON2
• Program Flash Memory Row Erase
• Load of Program Flash Memory write latches
• Write of Program Flash Memory write latches to
Program Flash Memory memory
• Write of Program Flash Memory write latches to
User IDs
• Write to EEPROM
The unlock sequence consists of the following steps
and must be completed in order:
• Write 55h to NVMCON2
• Write AAh to NMVCON2
• Set the WR bit of NVMCON1
Initiate Write or Erase Operation
(WR = 1)
Once the WR bit is set, the processor will stall internal
operations until the operation is complete and then
resume with the next instruction.
NOPInstruction
(not required for
PIC16(L)F18326/18346 devices)
Note:
The two NOPinstructions after setting the
WR bit, which were required in previous
devices,
are
not
required
for
PIC16(L)F18326/18346 devices. See
Figure 11-2.
NOPInstruction
(not required for
PIC16(L)F18326/18346 devices)
Since the unlock sequence must not be interrupted,
global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is
completed.
End Unlock Operation
EXAMPLE 11-2:
NVM UNLOCK SEQUENCE
BANKSEL
BSF
MOVLW
BCF
NVMCON1
NVMCON1,WREN
55h
; Enable write/erase
; Load 55h
; Recommended so sequence is not interrupted
INTCON,GIE
MOVWF
MOVLW
MOVWF
BSF
NVMCON2
AAh
NVMCON2
NVMCON1,WR
; Step 1: Load 55h into NVMCON2
; Step 2: Load W with AAh
; Step 3: Load AAh into NVMCON2
; Step 4: Set WR bit to begin write/erase
BSF
INTCON,GIE
; Re-enable interrupts
Note 1: Sequence begins when NVMCON2 is written; steps 1-4 must occur in the cycle-accurate order shown.
2: Opcodes shown are illustrative; any instruction that has the indicated effect may be used.
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11.4.3
NVMREG WRITE TO EEPROM
FIGURE 11-3:
NVM ERASE
FLOWCHART
Writing to the EEPROM is accomplished by the
following steps:
Start Erase Operation
1. Set the NVMREGS and WREN bits of the
NVMCON1 register.
2. Write the desired address (address +7000h) into
the NVMADRH:NVMADRL register pair
(Table 11-2).
Select Memory:
Program Flash Memory, Config.
Words, User ID (NVMREGS)
3. Perform the unlock sequence as described in
Section 11.4.2 “NVM Unlock Sequence”.
Select Word Address
A single EEPROM byte is written with NVMDATA. The
operation includes an implicit erase cycle for that byte
(it is not necessary to set the FREE bit), and requires
many instruction cycles to finish. CPU execution
continues in parallel and, when complete, WR is
cleared by hardware, NVMIF is set, and an interrupt will
occur if NVMIE is also set. Software must poll the WR
bit to determine when writing is complete, or wait for the
interrupt to occur. WREN will remain unchanged.
(NVMADRH:NVMADRL)
Select Erase Operation
(FREE = 1)
Enable Write/Erase Operation
(WREN = 1)
Once the EEPROM write operation begins, clearing the
WR bit will have no effect; the operation will continue to
run to completion.
Disable Interrupts
(GIE = 0)
11.4.4
NVMREG ERASE OF PROGRAM
FLASH MEMORY
Unlock Sequence
(Figure 11-2)
Program Flash Memory can only be erased one row at
a time. No automatic erase occurs upon the initiation of
the write to Program Flash Memory.
CPU stalls while Erase operation
completes (2 ms typical)
To erase a Program Flash Memory row:
1. Clear the NVMREGS bit of the NVMCON1
register to erase Program Flash Memory
locations, or set the NVMREGS bit to erase
User ID locations.
Enable Interrupts
(GIE = 1)
2. Write the desired address into the
NVMADRH:NVMADRL
(Table 11-2).
register
pair
Disable Write/Erase Operation
(WREN = 0)
3. Set the FREE and WREN bits of the NVMCON1
register.
4. Perform the unlock sequence as described in
End Erase Operation
Section 11.4.2 “NVM Unlock Sequence”.
If the Program Flash Memory address is write-pro-
tected, the WR bit will be cleared and the erase opera-
tion will not take place.
While erasing Program Flash Memory, CPU operation
is suspended, and resumes when the operation is
complete. Upon completion, the NVMIF is set, and an
interrupt will occur if the NVMIE bit is also set.
Write latch data is not affected by erase operations,
and WREN will remain unchanged.
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EXAMPLE 11-3:
ERASING ONE ROW OF PROGRAM FLASH MEMORY
; This sample row erase routine assumes the following:
; 1.A valid address within the erase row is loaded in variables ADDRH:ADDRL
; 2.ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)
BANKSEL
MOVF
NVMADRL
ADDRL,W
MOVWF
MOVF
NVMADRL
; Load lower 8 bits of erase address boundary
ADDRH,W
MOVWF
BCF
BSF
NVMADRH
; Load upper 6 bits of erase address boundary
; Choose Program Flash Memory area
; Specify an erase operation
NVMCON1,NVMREGS
NVMCON1,FREE
BSF
BCF
NVMCON1,WREN
INTCON,GIE
; Enable writes
; Disable interrupts during unlock sequence
; -------------------------------REQUIRED UNLOCK SEQUENCE:------------------------------
MOVLW
MOVWF
MOVLW
55h
; Load 55h to get ready for unlock sequence
; First step is to load 55h into NVMCON2
; Second step is to load AAh into W
NVMCON2
AAh
MOVWF
BSF
NVMCON2
NVMCON1,WR
; Third step is to load AAh into NVMCON2
; Final step is to set WR bit
; --------------------------------------------------------------------------------------
BSF
BCF
INTCON,GIE
; Re-enable interrupts, erase is complete
; Disable writes
NVMCON1,WREN
TABLE 11-2: NVM ORGANIZATION AND ACCESS INFORMATION
Master Values
NVMREG Access
FSR Access
FSR
Program
Counter (PC),
ICSP™ Address
NVMREGS
Memory
Function
Memory
Type
NVMADR
<14:0>
Allowed
FSR
bit
Programming
Address
Operations Address
(NVMCON1)
Reset Vector
User Memory
0000h
0001h
0003h
0004h
0005h
3FFFh
0
0
0000h
0001h
0003h
0004h
0005h
3FFFh
0000h
0003h
8000h
8001h
Program
Flash
Memory
8003h
8004h
8005h
BFFFh
READ
WRITE
READ-ONLY
INT Vector
0
0
User Memory
User ID
Program
Flash
Memory
1
READ
—
Reserved
Rev ID
—
—
1
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
7000h
70FFh
No Access
Device ID
CONFIG1
CONFIG2
CONFIG3
CONFIG4
User Memory
1
No PC Address
Program
Flash
Memory
1
READ
1
1
EEPROM
1
READ
7000h
70FFh
READ-ONLY
WRITE
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1. Set the WREN bit of the NVMCON1 register.
11.4.5
NVMREG WRITE TO PROGRAM
FLASH MEMORY
2. Clear the NVMREGS bit of the NVMCON1
register.
Program memory is programmed using the following
steps:
3. Set the LWLO bit of the NVMCON1 register.
When the LWLO bit of the NVMCON1 register is
‘1’, the write sequence will only load the write
latches and will not initiate the write to Flash
program memory.
1. Load the address of the row to be programmed
into NVMADRH:NVMADRL.
2. Load each write latch with data.
3. Initiate a programming operation.
4. Load the NVMADRH:NVMADRL register pair
with the address of the location to be written.
4. Repeat steps 1 through 3 until all data is written.
5. Load the NVMDATH:NVMDATL register pair
with the program memory data to be written.
Before writing to program memory, the word(s) to be
written must be erased or previously unwritten.
Program memory can only be erased one row at a time.
No automatic erase occurs upon the initiation of the
write.
6. Execute the unlock sequence (Section 11.4.2
“NVM Unlock Sequence”). The write latch is
now loaded.
7. Increment the NVMADRH:NVMADRL register
pair to point to the next location.
Program memory can be written one or more words at
a time. The maximum number of words written at one
time is equal to the number of write latches. See
Figure 11-4 (row writes to program memory with 32
write latches) for more details.
8. Repeat steps 5 through 7 until all but the last
write latch has been loaded.
9. Clear the LWLO bit of the NVMCON1 register.
When the LWLO bit of the NVMCON1 register is
‘0’, the write sequence will initiate the write to
Flash program memory.
The write latches are aligned to the Flash row address
boundary defined by the upper ten bits of
NVMADRH:NVMADRL, (NVMADRH<6:0>:NVMADRL<7:5>)
with the lower five bits of NVMADRL, (NVMADRL<4:0>)
determining the write latch being loaded. Write opera-
tions do not cross these boundaries. At the completion
of a program memory write operation, the data in the
write latches is reset to contain 0x3FFF.
10. Load the NVMDATH:NVMDATL register pair
with the program memory data to be written.
11. Execute the unlock sequence (Section 11.4.2
“NVM Unlock Sequence”). The entire program
memory latch content is now written to Flash
program memory.
The following steps should be completed to load the
write latches and program a row of program memory.
These steps are divided into two parts. First, each write
Note:
The program memory write latches are
reset to the blank state (0x3FFF) at the
completion of every write or erase
operation. As a result, it is not necessary
to load all the program memory write
latches. Unloaded latches will remain in
the blank state.
latch
is
loaded
with
data
from
the
NVMDATH:NVMDATL using the unlock sequence with
LWLO = 1. When the last word to be loaded into the
write latch is ready, the LWLO bit is cleared and the
unlock sequence executed. This initiates the
programming operation, writing all the latches into
Flash program memory.
An example of the complete write sequence is shown in
Example 11-4. The initial address is loaded into the
NVMADRH:NVMADRL register pair; the data is loaded
using indirect addressing.
Note:
The special unlock sequence is required
to load a write latch with data or initiate a
Flash programming operation. If the
unlock sequence is interrupted, writing to
the latches or program memory will not be
initiated.
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FIGURE 11-4:
BLOCK WRITES TO PROGRAM FLASH MEMORY WITH 32 WRITE LATCHES
7
6
0 7
5 4
0
7
5
0
7
0
-
-
NVMADRH
NVMADRL
NVMDATH
NVMDATL
-
r9
r8
r7
r6
r5
r4
r3
r2
r1
r0
c4
c3
c2
c1
c0
6
8
14
Program Memory Write Latches
14 14
5
10
14
14
Write Latch #0 Write Latch #1
00h 01h
Write Latch #30
1Eh
Write Latch #31
1Fh
NVMADRL<4:0>
14
14
14
14
Addr
Addr
Row
Addr
Addr
000h
001h
002h
0000h
0020h
0040h
0001h
0021h
0041h
001Eh
003Eh
005Eh
001Fh
003Fh
005Fh
NVMREGS = 0
3FEh
3FFh
7FC0h
7FE0h
7FC1h
7FE1h
7FDEh
7FFEh
7FDFh
7FFFh
Row
Address
Decode
NVMADRH<6:0>
NVMADRL<7:5>
Program Flash Memory
400h 8000h - 8003h
USER ID 0 - 3
8004h
reserved
8005h -8006h
8007h – 800Ah
800Bh - 801Fh
reserved
DEVICE ID
Dev / Rev
Configuration
Words
NVMREGS = 1
Configuration Memory
PIC16(L)F18326/18346
FIGURE 11-5:
PROGRAM FLASH MEMORY WRITE FLOWCHART
Start Write Operation
Load the value to write
(NVMDATH:NVMDATL)
Determine number of
words to be written into
PFM or Configuration
Memory. The number of
words cannot exceed the
number of words per row
(word_cnt)
Update the word counter
(word_cnt--)
Write Latches to PFM
(LWLO = 0)
Select
PFM or Config. Memory
(NVMREGS)
Yes
Last word to write?
No
Disable Interrupts
(GIE = 0)
Select Row Address
(NVMADRH:NVMADRL)
Disable Interrupts
(GIE = 0)
Unlock Sequence
(Figure 11-2)
Select Write Operation
(FREE = 0)
Unlock Sequence
(Figure 11-2)
CPU stalls while Write
operation completes
(2 ms typical)
Load Write Latches Only
(LWLO = 1)
No delay when writing to
PFM Latches
Enable Write/Erase
Re-enable Interrupts
Operation (WREN = 1)
(GIE = 1)
Re-enable Interrupts
(GIE = 1)
Disable Write/Erase
Operation (WREN = 0)
Increment Address
(NVMADRH:NVMADRL++)
End Write Operation
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EXAMPLE 11-4:
WRITING TO PROGRAM FLASH MEMORY
; This write routine assumes the following:
; 1. 32 words of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
;
stored in little endian format
; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)
; 5. NVM interrupts are not taken into account
BANKSEL
MOVF
NVMADRH
ADDRH,W
MOVWF
MOVF
NVMADRH
ADDRL,W
; Load initial address
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
NVMADRL
LOW DATA_ADDR
FSR0L
HIGH DATA_ADDR
FSR0H
NVMCON1,NVMREGS
; Load initial data address
; Set Program Flash Memory as write location
BSF
BSF
NVMCON1,WREN
NVMCON1,LWLO
; Enable writes
; Load only write latches
LOOP
MOVIW
MOVWF
MOVIW
MOVWF
FSR0++
NVMDATL
FSR0++
NVMDATH
; Load first data byte
; Load second data byte
MOVF
XORLW
ANDLW
NVMADRL,W
0x20
0x20
; Check if lower bits of address are 00000
; and if on last of 32 addresses
BTFSC
GOTO
STATUS,Z
START_WRITE
; Last of 32 words?
; If so, go write latches into memory
CALL
INCF
GOTO
UNLOCK_SEQ
NVMADRL,F
LOOP
; If not, go load latch
; Increment address
START_WRITE
BCF
NVMCON1,LWLO
; Latch writes complete, now write memory
CALL
BCF
UNLOCK_SEQ
NVMCON1,LWLO
; Perform required unlock sequence
; Disable writes
UNLOCK_SEQ
MOVLW
BCF
55h
INTCON,GIE
NVMCON2
AAh
NVMCON2
NVMCON1,WR
INTCON,GIE
; Disable interrupts
; Begin unlock sequence
MOVWF
MOVLW
MOVWF
BSF
BSF
; Unlock sequence complete, re-enable interrupts
return
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11.4.6
MODIFYING PROGRAM FLASH
MEMORY
When modifying existing data in a program memory
row, and data within that row must be preserved, it must
first be read and saved in a RAM image. Program
memory is modified using the following steps:
1. Load the starting address of the row to be
modified.
2. Read the existing data from the row into a RAM
image.
3. Modify the RAM image to contain the new data
to be written into program memory.
4. Load the starting address of the row to be
rewritten.
5. Erase the program memory row.
6. Load the write latches with data from the RAM
image.
7. Initiate a programming operation.
FIGURE 11-6:
PROGRAM FLASH
MEMORY MODIFY
FLOWCHART
Start
Modify Operation
Read Operation
Figure 11-1
An image of the entire row read
must be stored in RAM
Modify Image
The words to be modified are
changed in the RAM image
Erase Operation
Figure 11-3
Write Operation
use RAM image
Figure 11-5
End
Modify Operation
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11.4.7
NVMREG EEPROM, USER ID,
DEVICE ID AND CONFIGURATION
WORD ACCESS
Instead of accessing Program Flash Memory, the
EEPROM, the User ID’s, Device ID/Revision ID and
Configuration Words can be accessed when
NVMREGS = 1 in the NVMCON1 register. This is the
region that would be pointed to by PC<15> = 1, but not
all addresses are accessible. Different access may
exist for reads and writes. Refer to Table 11-3.
When read access is initiated on an address outside
the parameters listed in Table 11-3, the NVMDATH:
NVMDATL register pair is cleared, reading back ‘0’s.
TABLE 11-3: EEPROM, USER ID, DEV/REV ID AND CONFIGURATION WORD ACCESS
(NVMREGS = 1)
Address
Function
Read Access
Write Access
8000h-8003h
8005h-8006h
8007h-800Ah
F000h-F0FFh
User IDs
Device ID/Revision ID
Configuration Words 1-4
EEPROM
Yes
Yes
Yes
Yes
Yes
No
No
Yes
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11.4.8
WRITE VERIFY
It is considered good programming practice to verify that
program memory writes agree with the intended value.
Since program memory is stored as a full row then the
stored program memory contents are compared with the
intended data stored in RAM after the last write is
complete.
FIGURE 11-7:
PROGRAM FLASH
MEMORY VERIFY
FLOWCHART
Start
Verify Operation
This routine assumes that the last row
of data written was from an image
saved in RAM. This image will be used
to verify the data currently stored in
Flash Program Memory.
Read Operation
Figure 11-1
No
NVMDAT =
RAM image?
Fail
Verify Operation
Yes
No
Last Word?
Yes
End
Verify Operation
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11.4.9
WRERR BIT
The WRERR bit can be used to determine if a write
error occurred.
WRERR will be set if one of the following conditions
occurs:
• If WR is set while the NVMADRH:NMVADRL
points to a write-protected address
• A Reset occurs while a self-write operation was in
progress
• An unlock sequence was interrupted
The WRERR bit is normally set by hardware, but can
be set by the user for test purposes. Once set, WRERR
must be cleared in software.
TABLE 11-4: ACTIONS FOR PROGRAM FLASH MEMORY WHEN WR = 1
Free
LWLO
Actions for Program Flash Memory when WR = 1
Comments
0
0
Write the write latch data to Program Flash Memory • If WP is enabled, WR is cleared
row. See Section 11.4.4 “NVMREG Erase of Pro-
and WRERR is set
gram Flash Memory”
• Write latches are reset to 3FFh
• NVMDATH:NVMDATL is ignored
0
1
1
x
Copy NVMDATH:NVMDATL to the write latch corre- • Write protection is ignored
sponding to NVMADR LSBs. See Section 11.4.4
• No memory access occurs
“NVMREG Erase of Program Flash Memory”
Erase the 32-word row of NVMADRH:NVMADRL
location. See Section 11.4.3 “NVMREG Write to
EEPROM”
• If WP is enabled, WR is cleared
and WRERR is set
• All 32 words are erased
• NVMDATH:NVMDATL is ignored
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11.5 Register Definitions: Program Flash Memory Control
REGISTER 11-1: NVMDATL: NONVOLATILE MEMORY DATA LOW BYTE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NVMDAT<7:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
NVMDAT<7:0>: Read/Write Value for Least Significant bits of Program Memory
REGISTER 11-2: NVMDATH: NONVOLATILE MEMORY DATA HIGH BYTE REGISTER
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NVMDAT<13:8>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
NVMDAT<13:8>: Read/Write Value for Most Significant bits of Program Memory(1)
Note 1: This byte is ignored when writing to EEPROM.
REGISTER 11-3: NVMADRL: NONVOLATILE MEMORY ADDRESS LOW BYTE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NVMADR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
NVMADR<7:0>: Specifies the Least Significant bits for Program Memory Address
REGISTER 11-4: NVMADRH: NONVOLATILE MEMORY ADDRESS HIGH BYTE REGISTER
U-1
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NVMADR<14:8>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
Unimplemented: Read as ‘1’
NVMADR<14:8>: Specifies the Most Significant bits for Program Memory Address
bit 6-0
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REGISTER 11-5: NVMCON1: NONVOLATILE MEMORY CONTROL 1 REGISTER
U-0
—
R/W-0/0
R/W-0/0
LWLO
R/W/HC-0/0 R/W/HC-x/q
FREE WRERR
R/W-0/0
WREN
R/S/HC-0/0 R/S/HC-0/0
WR RD
NVMREGS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
S = Bit can only be set
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
HC = Bit is cleared by hardware
bit 7
bit 6
Unimplemented: Read as ‘0’
NVMREGS: Configuration Select bit
1= Access EEPROM, Configuration, User ID and Device ID registers
0= Access Program Flash Memory
bit 5
LWLO: Load Write Latches Only bit
When FREE = 0:
1= The next WR command updates the write latch for this word within the row; no memory operation
is initiated.
0= The next WR command writes data or erases
Otherwise: The bit is ignored.
bit 4
bit 3
FREE: Program Flash Memory Erase Enable bit
When NVMREGS:NVMADR points to a Program Flash Memory location:
1= Performs an erase operation with the next WR command; the row containing the indicated address
is erased (to all 1s) to prepare for writing.
0= All write operations have completed normally
WRERR: Program/Erase Error Flag bit (1,2,3)
This bit is normally set by hardware.
1= A write operation was interrupted by a Reset, interrupted unlock sequence, or WR was written to
one while NVMADR points to a write-protected address.
0= The program or erase operation completed normally
bit 2
bit 1
WREN: Program/Erase Enable bit
1= Allows program/erase cycles
0= Inhibits programming/erasing of program Flash
WR: Write Control bit(4,5,6)
When NVMREG:NVMADR points to a EEPROM location:
1= Initiates an erase/program cycle at the corresponding EEPROM location
0= NVM program/erase operation is complete and inactive
When NVMREG:NVMADR points to a Program Flash Memory location:
1= Initiates the operation indicated by Table 11-5
0= NVM program/erase operation is complete and inactive
bit 0
RD: Read Control bit(7)
1= Initiates a read at address = NVMADR1, and loads data to NVMDAT Read takes one instruction
cycle and the bit is cleared when the operation is complete. The bit can only be set (not cleared)
in software.
0= NVM read operation is complete and inactive.
Note 1: Bit may change while WR = 1(during the EEPROM write operation it may be ‘0’ or ‘1’).
2: Bit must be cleared by software; hardware will not clear this bit.
3: Bit may be written to ‘1’ by software in order to implement test sequences.
4: This bit can only be set by following the unlock sequence of Section 11.4.2 “NVM Unlock Sequence”.
5: Operations are self-timed, and the WR bit is cleared by hardware when complete.
6: Once a write operation is initiated, setting this bit to zero will have no effect.
7: Reading from EEPROM loads only NVMDATL<7:0> (Register 11-1).
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REGISTER 11-6: NVMCON2: NONVOLATILE MEMORY CONTROL 2 REGISTER
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
NVMCON2
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
S = Bit can only be set
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
NVMCON2<7:0>: Flash Memory Unlock Pattern bits
To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
NVMCON1 register. The value written to this register is used to unlock the writes.
TABLE 11-5: SUMMARY OF REGISTERS ASSOCIATED WITH NONVOLATILE MEMORY (NVM)
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR2
GIE
TMR6IF
TMR6IE
—
PEIE
C2IF
C2IE
—
—
—
—
—
INTEDG
NCO1IF
NCO1IE
RD
100
108
103
138
139
137
137
137
137
C1IF
C1IE
NVMIF
NVMIE
FREE
SSP2IF
SSP2IE
WRERR
BLC2IF
BLC2IE
WREN
TMR4IF
TMR4IE
WR
PIE2
NVMCON1
NVMCON2
NVMADRL
NVMREGS LWLO
NVMCON2
NVMADR<7:0>
NVMADR<14:8>
NVMDAT<7:0>
NVMDAT<13:8>
(1)
NVMADRH
NVMDATL
—
NVMDATH
—
—
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by NVM.
Note 1: Unimplemented, read as ‘1’.
TABLE 11-6: SUMMARY OF CONFIGURATION WORD WITH NONVOLATILE MEMORY (NVM)
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1
Bit 8/0
CONFIG3 13:8
—
—
—
—
—
—
—
—
LVP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
66
7:0
CONFIG4 13:8
7:0
WRT<1:0>
—
—
—
67
—
CPD
CP
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by NVM.
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Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 12-1.
12.0 I/O PORTS
TABLE 12-1: PORT AVAILABILITY PER
DEVICE
Device
FIGURE 12-1:
GENERIC I/O PORT
OPERATION
PIC16(L)F18326
PIC16(L)F18346
●
●
●
●
●
Read LATx
Each port has ten standard registers for its operation.
These registers are:
TRISx
D
Q
• PORTx registers (reads the levels on the pins of
the device)
Write LATx
Write PORTx
• LATx registers (output latch)
• TRISx registers (data direction)
• ANSELx registers (analog select)
• WPUx registers (weak pull-up)
• INLVLx (input level control)
CK
Data Register
VDD
Data Bus
Read PORTx
I/O pin
• SLRCONx registers (slew rate)
• ODCONx registers (open-drain)
To digital peripherals
To analog peripherals
VSS
Most port pins share functions with device peripherals,
both analog and digital. In general, when a peripheral
is enabled on a port pin, that pin cannot be used as a
general purpose output; however, the pin can still be
read.
ANSELx
12.1 I/O Priorities
The Data Latch (LATx registers) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
Each pin defaults to the PORT data latch after Reset.
Other functions are selected with the peripheral pin
select logic. See Section 13.0 “Peripheral Pin Select
(PPS) Module” for more information.
A write operation to the LATx register has the same
effect as a write to the corresponding PORTx register.
A read of the LATx register reads of the values held in
the I/O PORT latches, while a read of the PORTx
register reads the actual I/O pin value.
Analog input functions, such as ADC and comparator
inputs, are not shown in the peripheral pin select lists.
These inputs are active when the I/O pin is set for
Analog mode using the ANSELx register. Digital output
functions may continue to control the pin when it is in
Analog mode.
Ports that support analog inputs have an associated
ANSELx register. When an ANSEL bit is set, the digital
input buffer associated with that bit is disabled.
Analog outputs, when enabled, take priority over the
digital outputs and force the digital output driver to the
high-impedance state.
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12.2.3
OPEN-DRAIN CONTROL
12.2 PORTA Registers
12.2.1 DATA REGISTER
The ODCONA register (Register 12-6) controls the
open-drain feature of the port. Open-drain operation is
independently selected for each pin. When an
ODCONA bit is set, the corresponding port output
becomes an open-drain driver capable of sinking
current only. When an ODCONA bit is cleared, the
corresponding port output pin is the standard push-pull
drive capable of sourcing and sinking current.
PORTA is a 6-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register 12-2). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). The exception is RA3, which is
input-only and its TRIS bit will always read as ‘1’.
Example 12-1 shows how to initialize PORTA.
Note:
It is not necessary to set open-drain
control when using the pin for I2C; the I2C
module controls the pin and makes the pin
open-drain.
Reading the PORTA register (Register 12-1) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch (LATA).
12.2.4
SLEW RATE CONTROL
The SLRCONA register (Register 12-7) controls the
slew rate option for each port pin. Slew rate control is
independently selectable for each port pin. When an
SLRCONA bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONA bit is cleared,
The corresponding port pin drive slews at the maximum
rate available.
The PORT data latch LATA (Register 12-3) holds the
output port data, and contains the latest value of a
LATA or PORTA write.
EXAMPLE 12-1:
INITIALIZING PORTA
12.2.5
INPUT THRESHOLD CONTROL
; This code example illustrates
; initializing the PORTA register. The
; other ports are initialized in the same
; manner.
The INLVLA register (Register 12-8) controls the input
voltage threshold for each of the available PORTA input
pins. A selection between the Schmitt Trigger CMOS or
the TTL Compatible thresholds is available. The input
threshold is important in determining the value of a read
of the PORTA register and also the level at which an
interrupt-on-change occurs, if that feature is enabled.
See Table 35-4 for more information on threshold
levels.
BANKSEL PORTA
CLRF PORTA
BANKSEL LATA
CLRF LATA
BANKSEL ANSELA
CLRF ANSELA
BANKSEL TRISA
;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
Note:
Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the
threshold level during the time a module is
MOVLW
MOVWF
B'00111000' ;Set RA<5:3> as inputs
TRISA
;and set RA<2:0> as
;outputs
active may inadvertently generate
a
transition associated with an input pin,
regardless of the actual voltage level on
that pin.
12.2.2
DIRECTION CONTROL
The TRISA register (Register 12-2) controls the
PORTA pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISA register are maintained set when using
them as analog inputs. I/O pins configured as analog
inputs always read ‘0’.
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12.2.6
ANALOG CONTROL
The ANSELA register (Register 12-4) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELA bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
Note:
The ANSELA bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
12.2.7
WEAK PULL-UP CONTROL
The WPUA register (Register 12-5) controls the
individual weak pull-ups for each PORT pin.
PORTA pin RA3 includes the MCLR/VPP input. The
MCLR input allows the device to be reset, and can be
disabled by the MCLRE bit of Configuration Word 2. A
weak pull-up is present on the RA3 port pin. This weak
pull-up is enabled when MCLR is enabled (MCLRE = 1)
or the WPUA3 bit is set. The weak pull-up is disabled
when the MCLR is disabled and the WPUA3 bit is clear.
12.2.8
PORTA FUNCTIONS AND OUTPUT
PRIORITIES
Each PORTA pin is multiplexed with other functions.
Each pin defaults to the PORT latch data after Reset.
Other output functions are selected with the peripheral
pin select logic. See Section 13.0 “Peripheral Pin
Select (PPS) Module” for more information.
Analog input functions, such as ADC and comparator
inputs are not shown in the peripheral pin select lists.
Digital output functions may continue to control the pin
when it is in Analog mode.
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12.3 Register Definitions: PORTA
REGISTER 12-1: PORTA: PORTA REGISTER
U-0
—
U-0
—
R/W-x/u
RA5
R/W-x/u
RA4
R-x/u
RA3(2)
R/W-x/u
RA2
R/W-x/u
RA1
R/W-x/u
RA0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
RA<5:0>: PORTA I/O Value bits(1)
1= Port pin is > VIH
0= Port pin is < VIL
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
2: Bit RA3 is read-only, and will read ‘1’ when MCLRE = 1(master clear enabled).
REGISTER 12-2: TRISA: PORTA TRI-STATE REGISTER
U-0
—
U-0
—
R/W-1/1
TRISA5
R/W-1/1
TRISA4
U-1
—
R/W-1/1
TRISA2
R/W-1/1
TRISA1
R/W-1/1
TRISA0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
TRISA<5:4>: PORTA Tri-State Control bit
1= PORTA pin configured as an input (tri-stated)
0= PORTA pin configured as an output
bit 3
Unimplemented: Read as ‘1’
bit 2-0
TRISA<2:0>: PORTA Tri-State Control bit
1= PORTA pin configured as an input (tri-stated)
0= PORTA pin configured as an output
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REGISTER 12-3: LATA: PORTA DATA LATCH REGISTER
U-0
—
U-0
—
R/W-x/u
LATA5
R/W-x/u
LATA4
U-0
—
R/W-x/u
LATA2
R/W-x/u
LATA1
R/W-x/u
LATA0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-4
bit 3
Unimplemented: Read as ‘0’
LATA<5:4>: RA<5:4> Output Latch Value bits(1)
Unimplemented: Read as ‘0’
bit 2-0
LATA<2:0>: RA<2:0> Output Latch Value bits(1)
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 12-4: ANSELA: PORTA ANALOG SELECT REGISTER
U-0
—
U-0
—
R/W-1/1
ANSA5
R/W-1/1
ANSA4
U-0
—
R/W-1/1
ANSA2
R/W-1/1
ANSA1
R/W-1/1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
ANSA<5:4>: Analog Select between Analog or Digital Function on pins RA<5:4>, respectively
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0= Digital I/O. Pin is assigned to port or digital special function.
bit 3
Unimplemented: Read as ‘0’
bit 2-0
ANSA<2:0>: Analog Select between Analog or Digital Function on pins RA<2:0>, respectively
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0= Digital I/O. Pin is assigned to port or digital special function.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
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REGISTER 12-5: WPUA: WEAK PULL-UP PORTA REGISTER
U-0
—
U-0
—
R/W-0/0
WPUA5
R/W-0/0
WPUA4
R/W-0/0
WPUA3(1)
R/W-0/0
WPUA2
R/W-0/0
WPUA1
R/W-0/0
WPUA0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
WPUA<5:0>: Weak Pull-up Register bits(2)
1= Pull-up enabled
0= Pull-up disabled
Note 1: If MCLRE = 1, the weak pull-up in RA3 is always enabled; bit WPUA3 is not affected.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.
REGISTER 12-6: ODCONA: PORTA OPEN-DRAIN CONTROL REGISTER
U-0
—
U-0
—
R/W-0/0
ODCA5
R/W-0/0
ODCA4
U-0
—
R/W-0/0
ODCA2
R/W-0/0
ODCA1
R/W-0/0
ODCA0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
ODCA<5:4>: PORTA Open-Drain Enable bits
For RA<5:4> pins, respectively
1= Port pin operates as open-drain drive (sink current only)
0= Port pin operates as standard push-pull drive (source and sink current)
bit 3
Unimplemented: Read as ‘0’
bit 2-0
ODCA<2:0>: PORTA Open-Drain Enable bits
For RA<2:0> pins, respectively
1= Port pin operates as open-drain drive (sink current only)
0= Port pin operates as standard push-pull drive (source and sink current)
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REGISTER 12-7: SLRCONA: PORTA SLEW RATE CONTROL REGISTER
U-0
—
U-0
—
R/W-1/1
SLRA5
R/W-1/1
SLRA4
U-0
—
R/W-1/1
SLRA2
R/W-1/1
SLRA1
R/W-1/1
SLRA0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
SLRA<5:4>: PORTA Slew Rate Enable bits
For RA<5:4> pins, respectively
1= Port pin slew rate is limited
0= Port pin slews at maximum rate
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SLRA<2:0>: PORTA Slew Rate Enable bits
For RA<2:0> pins, respectively
1= Port pin slew rate is limited
0= Port pin slews at maximum rate
REGISTER 12-8: INLVLA: PORTA INPUT LEVEL CONTROL REGISTER
U-0
—
U-0
—
R/W-1/1
INLVLA5
R/W-1/1
INLVLA4
R/W-1/1
INLVLA3
R/W-1/1
INLVLA2
R/W-1/1
INLVLA1
R/W-1/1
INLVLA0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
INLVLA<5:0>: PORTA Input Level Select bits
For RA<5:0> pins, respectively
1= ST input used for PORT reads and interrupt-on-change
0= TTL input used for PORT reads and interrupt-on-change
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TABLE 12-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RA5
RA4
RA3
—
RA2
RA1
RA0
143
143
144
144
145
145
146
146
TRISA
TRISA5
LATA5
ANSA5
TRISA4
LATA4
ANSA4
TRISA2
LATA2
TRISA1
LATA1
ANSA1
TRISA0
LATA0
ANSA0
LATA
—
ANSELA
WPUA
—
ANSA2
WPUA2
ODCA2
SLRA2
WPUA1 WPUA0
WPUA5 WPUA4
WPUA3
—
ODCONA
SLRCONA
INLVLA
ODCA5
SLRA5
ODCA4
SLRA4
ODCA1
SLRA1
ODCA0
SLRA0
—
INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0
Legend: – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
TABLE 12-3: SUMMARY OF CONFIGURATION WORD WITH PORTA
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
—
—
STVREN PPS1WAY
WDTE1
—
BORV
—
13:8
7:0
DEBUG
CONFIG2
65
BOREN1 BOREN0 LPBOREN
—
WDTE0 PWRTE
MCLRE
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.
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12.4.4
OPEN-DRAIN CONTROL
12.4 PORTB Registers (PIC16(L)F18346
Only)
The ODCONB register (Register 12-14) controls the
open-drain feature of the port. Open-drain operation is
independently selected for each pin. When an
ODCONB bit is set, the corresponding port output
becomes an open-drain driver capable of sinking
current only. When an ODCONB bit is cleared, the
corresponding port output pin is the standard push-pull
drive capable of sourcing and sinking current.
12.4.1
DATA REGISTER
PORTB is a 4-bit wide bidirectional port and is only
available in the PIC16(L)F18346 devices. The
corresponding data direction register is TRISB
(Register 12-10). Setting a TRISB bit (= 1) will make
the corresponding PORTB pin an input (i.e., put the
corresponding output driver in a High-Impedance
mode). Clearing a TRISB bit (= 0) will make the
corresponding PORTB pin an output (i.e., enable the
output driver and put the contents of the output latch on
the selected pin). Example 12-1 shows how to initialize
an I/O port.
Note:
It is not necessary to set open-drain
control when using the pin for I2C; the I2C
module controls the pin and makes the pin
open-drain.
12.4.5
SLEW RATE CONTROL
Reading the PORTB register (Register 12-9) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read; this value is modified and then
written to the PORT data latch (LATB).
The SLRCONB register (Register 12-15) controls the
slew rate option for each port pin. Slew rate control is
independently selectable for each port pin. When an
SLRCONB bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONB bit is cleared,
the corresponding port pin drive slews at the maximum
rate possible.
The PORT data latch LATB (Register 12-11) holds the
output port data, and contains the latest value of a
LATB or PORTB write.
12.4.6
ANALOG CONTROL
The ANSELB register (Register 12-12) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELB bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
12.4.2
DIRECTION CONTROL
The TRISB register (Register 12-10) controls the
PORTB pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISB register are maintained set when using
them as analog inputs. I/O pins configured as analog
inputs always read ‘0’.
The state of the ANSELB bits has no effect on digital
output functions. A pin with TRIS clear and ANSELB
set will still operate as a digital output, but the Input
mode will be analog. This can cause unexpected
12.4.3
INPUT THRESHOLD CONTROL
behavior
when
executing
read-modify-write
The INLVLB register (Register 12-16) controls the input
voltage threshold for each of the available PORTB
input pins. A selection between the Schmitt Trigger
CMOS or the TTL Compatible thresholds is available.
The input threshold is important in determining the
value of a read of the PORTB register and also the level
at which an interrupt-on-change occurs, if that feature
is enabled. See Table 35-4 for more information on
threshold levels.
instructions on the affected port.
Note:
The ANSELB bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
12.4.7
WEAK PULL-UP CONTROL
The WPUB register (Register 12-13) controls the
individual weak pull-ups for each PORT pin.
Note:
Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the
threshold level during the time a module is
12.4.8
PORTB FUNCTIONS AND OUTPUT
PRIORITIES
active may inadvertently generate
a
transition associated with an input pin,
regardless of the actual voltage level on
that pin.
Each pin defaults to the PORT latch data after Reset.
Other output functions are selected with the peripheral
pin select logic. See Section 13.0 “Peripheral Pin
Select (PPS) Module” for more information.
Analog input functions, such as ADC and comparator
inputs, are not shown in the peripheral pin select lists.
Digital output functions may continue to control the pin
when it is in Analog mode.
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12.5 Register Definitions: PORTB
REGISTER 12-9: PORTB: PORTB REGISTER
R/W-x/x
RB7
R/W-x/x
RB6
R/W-x/x
RB5
R/W-x/x
RB4
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-4
RB<7:4>: PORTB I/O Value bits(1)
1= Port pin is > VIH
0= Port pin is < VIL
bit 3-0
Unimplemented: Read as ‘0’
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register return
actual I/O pin values.
REGISTER 12-10: TRISB: PORTB TRI-STATE REGISTER
R/W-1/1
TRISB7
R/W-1/1
TRISB6
R/W-1/1
TRISB5
R/W-1/1
TRISB4
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-4
bit 3-0
TRISB<7:4>: PORTB I/O Tri-State Control bits
1= PORTB pin configured as an output
0= PORTB pin configured as an input (tri-stated)
Unimplemented: Read as ‘0’
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REGISTER 12-11: LATB: PORTB DATA LATCH REGISTER
R/W-x/u
LATB7
R/W-x/u
LATB6
R/W-x/u
LATB5
R/W-x/u
LATB4
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-4
bit 3-0
LATB<7:4>: RB<5:4> Output Latch Value bits(1)
Unimplemented: Read as ‘0’
Note 1: Writes to LATB are equivalent with writes to the corresponding PORTB register.Reads from LATB register
return register values, not I/O pin values.
REGISTER 12-12: ANSELB: PORTB ANALOG SELECT REGISTER
R/W-1/1
ANSB7
R/W-1/1
ANSB6
R/W-1/1
ANSB5
R/W-1/1
ANSB4
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-4
ANSB<7:4>: Analog Select between Analog or Digital Function
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0= Digital I/O. Pin is assigned to port or digital special function.
bit 3-0
Unimplemented: Read as ‘0’
Note 1: Setting ANSB[n] = 1disables the digital input circuitry. Weak pull-ups, if available, are unaffected. The
corresponding TRIS bit must be set to Input mode by the user to allow external control of the voltage on
the pin.
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REGISTER 12-13: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-0/0
WPUB7
R/W-0/0
WPUB6
R/W-0/0
WPUB5
R/W-0/0
WPUB4
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-4
bit 3-0
WPUB<7:4>: Weak Pull-up Register bits
1= Weak Pull-up enabled
0= Weak Pull-up disabled
Unimplemented: Read as ‘0’
REGISTER 12-14: ODCONB: PORTB OPEN-DRAIN CONTROL REGISTER
R/W-0/0
ODCB7
R/W-0/0
ODCB6
R/W-0/0
ODCB5
R/W-0/0
ODCB4
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-4
ODCB<7:4>: PORTB Open-Drain Configuration bits
For RB<7:4> pins, respectively:
1= Port pin operates as open-drain drive (sink current only)
0= Port pin operates as standard push-pull drive (source and sink current)
bit 3-0
Unimplemented: Read as ‘0’
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REGISTER 12-15: SLRCONB: PORTB SLEW RATE CONTROL REGISTER
R/W-1/1
SLRB7
R/W-1/1
SLRB6
R/W-1/1
SLRB5
R/W-1/1
SLRB4
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-4
bit 3-0
SLRB<7:4>: PORTB Slew Rate Control on pins RB<7:4>, respectively
1= Slew rate enabled
0= Slew rate disabled
Unimplemented: Read as ‘0’
REGISTER 12-16: INLVLB: PORTB INPUT LEVEL CONTROL REGISTER
R/W-1/1
INLVLB7
R/W-1/1
INLVLB6
R/W-1/1
INLVLB5
R/W-1/1
INLVLB4
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-4
bit 3-0
INLVLB<7:4>: PORTB Input Level Select on pins RB<7:4>, respectively
1= ST input used for PORT reads
0= TTL input used for PORT reads
Unimplemented: Read as ‘0’
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TABLE 12-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTB
RB7
RB6
RB5
RB4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
149
149
150
150
151
151
152
152
TRISB
TRISB7
LATB7
ANSB7
WPUB7
ODCB7
SLRB7
TRISB6
LATB6
ANSB6
WPU6
ODCB6
SLRB6
TRISB5
LATB5
ANSB5
TRISB4
LATB4
ANSB4
LATB
ANSELB
WPUB
WPUB5 WPUB4
ODCONB
SLRCONB
INLVLB
ODCB5
SLRB5
ODCB4
SLRB4
INLVLB7 INLVLB6 INLVLB5 INLVLB4
Legend: x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTB.
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12.6.4
OPEN-DRAIN CONTROL
12.6 PORTC Registers
The ODCONC register (Register 12-22) controls the
open-drain feature of the port. Open-drain operation is
independently selected for each pin. When an
ODCONC bit is set, the corresponding port output
becomes an open-drain driver capable of sinking
current only. When an ODCONC bit is cleared, the
corresponding port output pin is the standard push-pull
drive capable of sourcing and sinking current.
12.6.1
DATA REGISTER
PORTC is a bidirectional port that is either 6-bit wide
(PIC16(L)F18326) or 8-bit wide (PIC16(L)F18346). The
corresponding data direction register is TRISC
(Register 12-18). Setting a TRISC bit (= 1) will make the
corresponding PORTC pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISC bit (= 0) will make the corresponding
PORTC pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 12-1 shows how to initialize an I/O port.
Note:
It is not necessary to set open-drain
control when using the pin for I2C; the I2C
module controls the pin and makes the pin
open-drain.
Reading the PORTC register (Register 12-17) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATC).
12.6.5
SLEW RATE CONTROL
The SLRCONC register (Register 12-23) controls the
slew rate option for each port pin. Slew rate control is
independently selectable for each port pin. When an
SLRCONC bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONC bit is cleared,
The corresponding port pin drive slews at the maximum
rate possible.
The PORT data latch LATC (Register 12-19) holds the
output port data, and contains the latest value of a LATC
or PORTC write.
12.6.2
DIRECTION CONTROL
12.6.6
ANALOG CONTROL
The TRISC register (Register 12-18) controls the
PORTC pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits in
the TRISC register are maintained set when using them
as analog inputs. I/O pins configured as analog inputs
always read ‘0’.
The ANSELC register (Register 12-20) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELC bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELC bits has no effect on digital out-
put functions. A pin with TRIS clear and ANSELC set will
still operate as a digital output, but the Input mode will be
analog. This can cause unexpected behavior when exe-
cuting read-modify-write instructions on the affected
port.
12.6.3
INPUT THRESHOLD CONTROL
The INLVLC register (Register 12-24) controls the input
voltage threshold for each of the available PORTC
input pins. A selection between the Schmitt Trigger
CMOS or the TTL Compatible thresholds is available.
The input threshold is important in determining the
value of a read of the PORTC register and also the
level at which an interrupt-on-change occurs, if that
feature is enabled. See Table 35-4 for more information
on threshold levels.
Note:
The ANSELC bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
Note:
Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the
threshold level during the time a module is
12.6.7
WEAK PULL-UP CONTROL
The WPUC register (Register 12-21) controls the
individual weak pull-ups for each PORT pin.
active may inadvertently generate
a
12.6.8
PORTC FUNCTIONS AND OUTPUT
PRIORITIES
transition associated with an input pin,
regardless of the actual voltage level on
that pin.
Each pin defaults to the PORT latch data after Reset.
Other functions are selected with the peripheral pin
select logic. See Section 13.0 “Peripheral Pin Select
(PPS) Module” for more information.
Analog output functions, such as ADC and comparator
inputs, are not shown in the peripheral pin select lists.
Digital output functions may continue to control the pin
when it is in Analog mode.
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12.7 Register Definitions: PORTC
REGISTER 12-17: PORTC: PORTC REGISTER
R/W-x/u
RC7(1)
R/W-x/u
RC6(1)
R/W-x/u
RC5
R/W-x/u
RC4
R/W-x/u
RC3
R/W-x/u
RC2
R/W-x/u
RC1
R/W-x/u
RC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
RC<7:6>: PORTC I/O Value bits(1,2)
1= Port pin is > VIH
0= Port pin is < VIL
RC<5:0>: PORTC General Purpose I/O Pin bits(2)
1= Port pin is > VIH
0= Port pin is < VIL
Note 1: PIC16(L)F18346 only; otherwise read as ‘0’.
2: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.
REGISTER 12-18: TRISC: PORTC TRI-STATE REGISTER
R/W-1/1
TRISC7(1)
R/W-1/1
TRISC6(1)
R/W-1/1
TRISC5
R/W-1/1
TRISC4
R/W-1/1
TRISC3
R/W-1/1
TRISC2
R/W-1/1
TRISC1
R/W-1/1
TRISC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
TRISC<7:6>: PORTC Tri-State Control bits(1)
1= PORTC pin configured as an input (tri-stated)
0= PORTC pin configured as an output
TRISC<5:0>: PORTC Tri-State Control bits
1= PORTC pin configured as an input (tri-stated)
0= PORTC pin configured as an output
Note 1: PIC16(L)F18346 only; otherwise read as ‘0’.
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REGISTER 12-19: LATC: PORTC DATA LATCH REGISTER
R/W-x/u
LATC7(1)
R/W-x/u
LATC6(1)
R/W-x/u
LATC5
R/W-x/u
LATC4
R/W-x/u
LATC3
R/W-x/u
LATC2
R/W-x/u
LATC1
R/W-x/u
LATC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
LATC<7:6>: PORTC Output Latch Value bits(1)
LATC<5:0>: PORTC Output Latch Value bits
Note 1: PIC16(L)F18346 only; otherwise read as ‘0’.
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REGISTER 12-20: ANSELC: PORTC ANALOG SELECT REGISTER
R/W-1/1
ANSC7(1)
R/W-1/1
ANSC6(1)
R/W-1/1
ANSC5
R/W-1/1
ANSC4
R/W-1/1
ANSC3
R/W-1/1
ANSC2
R/W-1/1
ANSC1
R/W-1/1
ANSC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
ANSC<7:6>: Analog Select between Analog or Digital Function on pins RC<7:6>, respectively(1)
1= Analog input. Pin is assigned as analog input(2). Digital input buffer disabled.
0= Digital I/O. Pin is assigned to port or digital special function.
ANSC<5:0>: Analog Select between Analog or Digital Function on pins RC<5:0>, respectively
1= Analog input. Pin is assigned as analog input(2). Digital input buffer disabled.
0= Digital I/O. Pin is assigned to port or digital special function.
Note 1: PIC16(L)F18346 only; otherwise read as ‘0’.
2: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
REGISTER 12-21: WPUC: WEAK PULL-UP PORTC REGISTER
R/W-0/0
WPUC7(1)
R/W-0/0
WPUC6(1)
R/W-0/0
WPUC5
R/W-0/0
WPUC4
R/W-0/0
WPUC3
R/W-0/0
WPUC2
R/W-0/0
WPUC1
R/W-0/0
WPUC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
WPUC<7:6>(1): Weak Pull-up Register bits(2)
1= Pull-up enabled
0= Pull-up disabled
WPUC<5:0>: Weak Pull-up Register bits(2)
1= Pull-up enabled
0= Pull-up disabled
Note 1: PIC16(L)F18346 only; otherwise read as ‘0’.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.
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REGISTER 12-22: ODCONC: PORTC OPEN-DRAIN CONTROL REGISTER
R/W-0/0
ODCC7(1)
R/W-0/0
ODCC6(1)
R/W-0/0
ODCC5
R/W-0/0
ODCC4
R/W-0/0
ODCC3
R/W-0/0
ODCC2
R/W-0/0
ODCC1
R/W-0/0
ODCC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
ODCC<7:6>: PORTC Open-Drain Enable bits(1)
For RC<7:6> pins, respectively
1= Port pin operates as open-drain drive (sink current only)
0= Port pin operates as standard push-pull drive (source and sink current)
bit 5-0
ODCC<5:0>: PORTC Open-Drain Enable bits
For RC<5:0> pins, respectively
1= Port pin operates as open-drain drive (sink current only)
0= Port pin operates as standard push-pull drive (source and sink current)
Note 1: PIC16(L)F18346 only; otherwise read as ‘0’.
REGISTER 12-23: SLRCONC: PORTC SLEW RATE CONTROL REGISTER
R/W-1/1
SLRC7(1)
R/W-1/1
SLRC6(1)
R/W-1/1
SLRC5
R/W-1/1
SLRC4
R/W-1/1
SLRC3
R/W-1/1
SLRC2
R/W-1/1
SLRC1
R/W-1/1
SLRC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
SLRC<7:6>: PORTC Slew Rate Enable bits(1)
For RC<7:6> pins, respectively
1= Port pin slew rate is limited
0= Port pin slews at maximum rate
bit 5-0
SLRC<5:0>: PORTC Slew Rate Enable bits
For RC<5:0> pins, respectively
1= Port pin slew rate is limited
0= Port pin slews at maximum rate
Note 1: PIC16(L)F18346 only; otherwise read as ‘0’.
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REGISTER 12-24: INLVLC: PORTC INPUT LEVEL CONTROL REGISTER
R/W-1/1
INLVLC7(1)
R/W-1/1
INLVLC6(1)
R/W-1/1
INLVLC5
R/W-1/1
INLVLC4
R/W-1/1
INLVLC3
R/W-1/1
INLVLC2
R/W-1/1
INLVLC1
R/W-1/1
INLVLC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
INLVLC<7:6>: PORTC Input Level Select bits(1)
For RC<7:6> pins, respectively
1= ST input used for PORT reads and interrupt-on-change
0= TTL input used for PORT reads and interrupt-on-change
bit 5-0
INLVLC<5:0>: PORTC Input Level Select bits
For RC<5:0> pins, respectively
1= ST input used for PORT reads and interrupt-on-change
0= TTL input used for PORT reads and interrupt-on-change
Note 1: PIC16(L)F18346 only; otherwise read as ‘0’.
TABLE 12-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RC7(1)
RC6(1)
PORTC
TRISC
RC5
RC4
RC3
RC2
RC1
RC0
155
155
156
157
157
158
158
159
TRISC7(1)
LATC7(1)
ANSC7(1)
WPUC7(1)
ODCC7(1)
TRISC6(1)
LATC6(1)
ANSC6(1)
WPUC6(1)
ODCC6(1)
SLRC6(1)
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
LATC
LATC5
LATC4
ANSC4
LATC3
ANSC3
LATC2
ANSC2
LATC1
ANSC1
LATC0
ANSC0
ANSELC
WPUC
ANSC5
WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0
ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0
ODCONC
SLRCONC SLRC7(1)
INLVLC
Note 1: PIC16(L)F18346 only.
SLRC5
SLRC4
SLRC3
SLRC2
SLRC1
SLRC0
INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0
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13.2 PPS Outputs
13.0 PERIPHERAL PIN SELECT
(PPS) MODULE
Each I/O pin has a PPS register with which the pin
output source is selected. With few exceptions, the port
TRIS control associated with that pin retains control
over the pin output driver. Peripherals that control the
pin output driver as part of the peripheral operation will
override the TRIS control as needed. These
peripherals are:
The Peripheral Pin Select (PPS) module connects
peripheral inputs and outputs to the device I/O pins.
Only digital signals are included in the selections. All
analog inputs and outputs remain fixed to their
assigned pins. Input and output selections are
independent as shown in the simplified block diagram
Figure 13-1.
• EUSART1 (synchronous operation)
• MSSP (I2C)
13.1 PPS Inputs
Although every pin has its own PPS peripheral
selection register, the selections are identical for every
pin as shown in Register 13-2.
Each peripheral has a PPS register with which the
inputs to the peripheral are selected. Inputs include the
device pins.
Note:
The notation “Rxy” is a place holder for the
pin identifier. For example, RA0PPS.
Although every peripheral has its own PPS input selec-
tion register, the selections are identical for every
peripheral as shown in Register 13-1.
Note:
The notation “xxx” in the register name is
a place holder for the peripheral identifier.
For example, CLC1PPS.
FIGURE 13-1:
SIMPLIFIED PPS BLOCK DIAGRAM
PPS Outputs
RA0PPS
PPS Inputs
abcPPS
RA0
Rxy
RA0
Peripheral abc
RxyPPS
Peripheral xyz
RC7PPS(1)
RC7(1)
RC7(1)
xyzPPS
Note 1: RB<7:4> and RC<7:6> are available on PIC16(L)F18346 only.
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13.3 Bidirectional Pins
13.5 PPS1WAY Bit
PPS selections for peripherals with bidirectional
signals on a single pin must be made so that the PPS
input and PPS output select the same pin. This
requires configuring both the appropriate xxxPPS input
and RxyPPS output registers. For example, if the SCL1
line is routed to pin RC0, the SSP1SCLPPS input
register would be set to '10000' (routes to RC0) and the
RC0PPS output register would be set to '11000'
(routes the SCL1 internal connection to RC0).
Peripherals that have bidirectional signals are:
The PPS can be locked by setting the PPS1WAY bit of
Configuration Word 2.
When the PPS1WAY bit is set, the PPSLOCKED bit of
the PPSLOCK register can be cleared and set only one
time after a device Reset. Once the PPS registers are
configured, user software sets the PPSLOCKED bit,
preventing any further writes to the PPS registers. the
PPS registers can be read at any time, regardless of
the PPS1WAY or PPSLOCKED settings.
When the PPS1WAY bit is clear, the PPSLOCKED bit
of the PPSLOCK register can be cleared and set
multiple times during code execution, but requires the
PPS lock/unlock sequence to be performed each time
modifications to the PPS registers are made.
• EUSART1 (synchronous operation)
• MSSP (I2C)
Note:
The I2C default input pins are I2C and
SMBus compatible and are the only pins
on the PIC16(L)F18326 with this compati-
bility. For the PIC16(L)F18346, in addition
to the default pins as described above,
RC0, RC1, RC4, and RC5 are also I2C
and SMBus compatible. Clock and data
signals can be routed to any pin, however
pins without I2C compatibility will operate
at standard TTL/ST logic levels as
selected by the INVLV register.
13.6 Operation During Sleep
PPS input and output selections are unaffected by
Sleep.
13.7 Effects of a Reset
A device Power-On-Reset (POR) clears all PPS input
and output selections to their default values, and clears
the PPSLOCKED bit of the PPSLOCK register. All other
Resets leave the selections unchanged. Default input
selections are shown in pin allocation Table 2 and
Table 3.
13.4 PPSLOCKED Bit
The PPS includes a mode in which all input and output
selections can be locked to prevent inadvertent
changes. PPS selections are locked by setting the
PPSLOCKED bit of the PPSLOCK register. Setting and
clearing this bit requires a special sequence as an extra
precaution against inadvertent changes. Examples of
setting and clearing the PPSLOCKED bit are shown in
Example 13-1.
EXAMPLE 13-1:
PPS LOCK/UNLOCK
SEQUENCE
; suspend interrupts
bcf INTCON,GIE
; BANKSELPPSLOCK
; set bank
; required sequence, next 5 instructions
movlw 0x55
movwf PPSLOCK
movlw 0xAA
movwf PPSLOCK
; Set PPSLOCKED bit to disable writes or
; Clear PPSLOCKED bit to enable writes
bsf
; restore interrupts
bsf INTCON,GIE
PPSLOCK,PPSLOCKED
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13.8 Register Definitions: PPS Input Selection
REGISTER 13-1: xxxPPS: PERIPHERAL xxx INPUT SELECTION
U-0
—
U-0
—
U-0
—
R/W-q/u
R/W-q/u
R/W-q/u
R/W-q/u
R/W-q/u
bit 0
xxxPPS<4:0>
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = value depends on peripheral
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
xxxPPS<4:0>: Peripheral xxx Input Selection bits
11xxx= Reserved. Do not use.
10111= Peripheral input is RC7(1)
10110= Peripheral input is RC6(1)
10101= Peripheral input is RC5
10100= Peripheral input is RC4
10011= Peripheral input is RC3
10010= Peripheral input is RC2
10001= Peripheral input is RC1
10000= Peripheral input is RC0
...
01111= Peripheral input is RB7(1)
01110= Peripheral input is RB6(1)
01101= Peripheral input is RB5(1)
01100= Peripheral input is RB4(1)
...
0011x= Reserved. Do not use.
00101= Peripheral input is RA5
00100= Peripheral input is RA4
00011= Peripheral input is RA3
00010= Peripheral input is RA2
00001= Peripheral input is RA1
00000= Peripheral input is RA0
Note 1: PIC16(L)F18346 only.
DS40001839B-page 162
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REGISTER 13-2: RxyPPS: PIN Rxy OUTPUT SOURCE SELECTION REGISTER
U-0
—
U-0
—
U-0
—
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
RxyPPS<4:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RxyPPS<4:0>: Pin Rxy Output Source Selection bits
11111= Rxy source is DSM
11110= Rxy source is CLKR
11101= Rxy source is NCO1
11100= Rxy source is TMR0
11011= Rxy source is SDO2/SDA2(1)
11010= Rxy source is SCK2/SCL2(1)
11001= Rxy source is SDO1/SDA1
11000= Rxy source is SCK1/SCL1(1)
10111= Rxy source is C2
10110= Rxy source is C1
10101= Rxy source is DT(1)
10100= Rxy source is TX/CK(1)
10011= Rxy source is CWG2D(1)
10010= Rxy source is CWG2C(1)
10001= Rxy source is CWG2B(1)
10000= Rxy source is CWG2A(1)
01111= Rxy source is CCP4
01110= Rxy source is CCP3
01101= Rxy source is CCP2
01100= Rxy source is CCP1
01011= Rxy source is CWG1D(1)
01010= Rxy source is CWG1C(1)
01001= Rxy source is CWG1B(1)
01000= Rxy source is CWG1A(1)
00111= Rxy source is CLC4OUT
00110= Rxy source is CLC3OUT
00101= Rxy source is CLC2OUT
00100= Rxy source is CLC1OUT
00011= Rxy source is PWM6
00010= Rxy source is PWM5
00001= Reserved
00000= Reserved
Note 1: TRIS control is overridden by the peripheral as required.
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REGISTER 13-3: PPSLOCK: PPS LOCK REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
PPSLOCKED
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-1
bit 0
Unimplemented: Read as ‘0’
PPSLOCKED: PPS Locked bit
1= PPS is locked. PPS selections can not be changed.
0= PPS is not locked. PPS selections can be changed.
TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE
Register
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PPSLOCK
INTPPS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PPSLOCKED
164
162
162
162
162
162
162
162
162
162
162
162
162
162
162
162
162
162
162
162
162
162
162
162
INTPPS<4:0>
T0CKIPPS<4:0>
T1CKIPPS<4:0>
T1GPPS<4:0>
T0CKIPPS
T1CKIPPS
T1GPPS
T3CKIPPS
T3GPPS
T3CKIPPS<4:0>
T3GPPS<4:0>
T5CKIPPS
T5GPPS
T5CKIPPS<4:0>
T5GPPS<4:0>
CCP1PPS
CCP2PPS
CCP3PPS
CCP4PPS
CWG1PPS
CWG2PPS
MDCIN1PPS
MDCIN2PPS
MDMINPPS
SSP1CLKPPS
SSP1DATPPS
SSP1SSPPS
SSP2CLKPPS
SSP2DATPPS
SSP2SSPPS
CCP1PPS<4:0>
CCP2PPS<4:0>
CCP3PPS<4:0>
CCP4PPS<4:0>
CWG1PPS<4:0>
CWG2PPS<4:0>
MDCIN1PPS<4:0>
MDCIN2PPS<4:0>
MDMINPPS<4:0>
SSP1CLKPPS<4:0>
SSP1DATPPS<4:0>
SSP1SSPPS<4:0>
SSP2CLKPPS<4:0>
SSP2DATPPS<4:0>
SSP2SSPPS<4:0>
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the PPS module.
Note 1: PIC16(L)F18346 only.
DS40001839B-page 164
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE (CONTINUED)
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on page
RXPPS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RXPPS<4:0>
CLCIN0PPS<4:0>
CLCIN1PPS<4:0>
CLCIN2PPS<4:0>
CLCIN3PPS<4:0>
RA0PPS<4:0>
RA1PPS<4:0>
RA2PPS<4:0>
RA4PPS<4:0>
RA5PPS<4:0>
RB4PPS<4:0>
RB5PPS<4:0>
RB6PPS<4:0>
RB7PPS<4:0>
RC0PPS<4:0>
RC1PPS<4:0>
RC2PPS<4:0>
RC3PPS<4:0>
RC4PPS<4:0>
RC5PPS<4:0>
RC6PPS<4:0>
RC7PPS<4:0>
162
162
162
162
162
163
163
163
163
163
163
163
163
163
163
163
163
163
163
163
163
163
CLCIN0PPS
CLCIN1PPS
CLCIN2PPS
CLCIN3PPS
RA0PPS
RA1PPS
RA2PPS
RA4PPS
RA5PPS
RB4PPS(1)
RB5PPS(1)
RB6PPS(1)
RB7PPS(1)
RC0PPS
RC1PPS
RC2PPS
RC3PPS
RC4PPS
RC5PPS
RC6PPS(1)
RC7PPS(1)
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the PPS module.
Note 1: PIC16(L)F18346 only.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 165
PIC16(L)F18326/18346
14.2 Enabling a Module
14.0 PERIPHERAL MODULE
DISABLE
When the register bit is cleared, the module is re-
enabled and will be in its Reset state; SFR data will
reflect the POR Reset values.
The PIC16(L)F18326/18346 provides the ability to
disable selected modules, placing them into the lowest
possible power mode.
Depending on the module, it may take up to one full
instruction cycle for the module to become active.
There should be no interaction with the module (e.g.,
writing to registers) for at least one instruction after it
has been re-enabled.
For legacy reasons, all modules are ON by default
following any Reset.
14.1 Disabling a Module
Disabling a module has the following effects:
14.3 System Clock Disable
• All clock and control inputs to the module are sus-
pended; there are no logic transitions, and the
module will not function.
• The module is held in Reset.
- Writing to the SFRs is disabled
- Reads return 00h
Setting SYSCMD (PMD0, Register 14-1) disables the
system clock (FOSC) distribution network to the
peripherals. Not all peripherals make use of SYSCLK,
so not all peripherals are affected. Refer to the specific
peripheral description to see if it will be affected by this
bit.
• Analog outputs are disabled; Digital outputs read
‘0’
REGISTER 14-1: PMD0: PMD CONTROL REGISTER 0
R/W-0/0
R/W-0/0
FVRMD
U-0
—
U-0
—
U-0
—
R/W-0/0
NVMMD
R/W-0/0
R/W-0/0
IOCMD
SYSCMD
CLKRMD
7
0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
‘1’ = Bit is set
bit 7
bit 6
SYSCMD: Disable Peripheral System Clock Network bit
See description in Section 14.3 “System Clock Disable”.
1= System Clock network disabled (a.k.a. FOSC)
0= System Clock network enabled
FVRMD: Disable Fixed Voltage Reference FVR bit
1= FVR module disabled
0= FVR module enabled
bit 5-3
bit 2
Unimplemented: Read as ‘0’
NVMMD: NVM Module Disable bit(1)
1= Data EEPROM (a.k.a. user memory, EEPROM) reading and writing is disabled; NVMCON
registers cannot be written; FSR access to EEPROM returns zero.
0= NVM module enabled
bit 1
bit 0
CLKRMD: Disable Clock Reference CLKR bit
1= CLKR module disabled
0= CLKR module enabled
IOCMD: Disable Interrupt-on-Change bit, All Ports
1= IOC module(s) disabled
0= IOC module(s) enabled
Note 1: When enabling NVM, a delay of up to 1 µs may be required before accessing data.
DS40001839B-page 166
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
REGISTER 14-2: PMD1: PMD CONTROL REGISTER 1
R/W-0/0
NCOMD
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TMR6MD
TMR5MD
TMR4MD
TMR3MD
TMR2MD
TMR1MD
TMR0MD
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
NCOMD: Disable Numerically Control Oscillator bit
1= NCO1 module disabled
0= NCO1 module enabled
TMR6MD: Disable Timer TMR6 bit
1= TMR6 module disabled
0= TMR6 module enabled
TMR5MD: Disable Timer TMR5 bit
1= TMR5 module disabled
0= TMR5 module enabled
TMR4MD: Disable Timer TMR4 bit
1= TMR4 module disabled
0= TMR4 module enabled
TMR3MD: Disable Timer TMR3 bit
1= TMR3 module disabled
0= TMR3 module enabled
TMR2MD: Disable Timer TMR2 bit
1= TMR2 module disabled
0= TMR2 module enabled
TMR1MD: Disable Timer TMR1 bit
1= TMR1 module disabled
0= TMR1 module enabled
TMR0MD: Disable Timer TMR0 bit
1= TMR0 module disabled
0= TMR0 module enabled
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 167
PIC16(L)F18326/18346
REGISTER 14-3: PMD2: PMD CONTROL REGISTER 2
U-0
—
R/W-0/0
DACMD
R/W-0/0
ADCMD
U-0
—
U-0
—
R/W-0/0
R/W-0/0
U-0
—
CMP2MD
CMP1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
Unimplemented: Read as ‘0’
DACMD: Disable DAC bit
1= DAC module disabled
0= DAC module enabled
bit 5
ADCMD: Disable ADC bit
1= ADC module disabled
0= ADC module enabled
bit 4-3
bit 2
Unimplemented: Read as ‘0’
CMP2MD: Disable Comparator C2 bit
1= C2 module disabled
0= C2 module enabled
bit 1
bit 0
CMP1MD: Disable Comparator C1 bit
1= C1 module disabled
0= C1 module enabled
Unimplemented: Read as ‘0’
DS40001839B-page 168
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
REGISTER 14-4: PMD3: PMD CONTROL REGISTER 3
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CWG2MD
CWG1MD
PWM6MD
PWM5MD
CCP4MD
CCP3MD
CCP2MD
CCP1MD
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CWG2MD: Disable CWG2 bit
1= CWG2 module disabled
0= CWG2 module enabled
CWG1MD: Disable CWG1 bit
1= CWG1 module disabled
0= CWG1 module enabled
PWM6MD: Disable PWM6 bit
1= PWM6 module disabled
0= PWM6 module enabled
PWM5MD: Disable PWM5 bit
1= PWM5 module disabled
0= PWM5 module enabled
CCP4MD: Disable CCP4 bit
1= CCP4 module disabled
0= CCP4 module enabled
CCP3MD: Disable CCP3 bit
1= CCP3 module disabled
0= CCP3 module enabled
CCP2MD: Disable CCP2 bit
1= CCP2 module disabled
0= CCP2 module enabled
CCP1MD: Disable CCP1 bit
1= CCP1 module disabled
0= CCP1 module enabled
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 169
PIC16(L)F18326/18346
REGISTER 14-5: PMD4: PMD CONTROL REGISTER 4
U-0
—
U-0
—
R/W-0/0
U-0
—
U-0
—
R/W-0/0
R/W-0/0
U-0
—
UART1MD
MSSP2MD MSSP1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-6
bit 5
Unimplemented: Read as ‘0’
UART1MD: Disable EUSART1 bit
1= EUSART1 module disabled
0= EUSART1 module enabled
bit 4-3
bit 2
Unimplemented: Read as ‘0’
MSSP2MD: Disable MSSP2 bit
1= MSSP2 module disabled
0= MSSP2 module enabled
bit 1
bit 0
MSSP1MD: Disable MSSP1 bit
1= MSSP1 module disabled
0= MSSP1 module enabled
Unimplemented: Read as ‘0’
DS40001839B-page 170
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
REGISTER 14-6: PMD5: PMD CONTROL REGISTER 5
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
DSMMD
CLC4MD
CLC3MD
CLC2MD
CLC1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-5
bit 4
Unimplemented: Read as ‘0’
CLC4MD: Disable CLC4 bit
1= CLC4 module disabled
0= CLC4 module enabled
bit 3
bit 2
bit 1
bit 0
CLC3MD: Disable CLC3 bit
1= CLC3 module disabled
0= CLC3 module enabled
CLC2MD: Disable CLC2 bit
1= CLC2 module disabled
0= CLC2 module enabled
CLC1MD: Disable CLC1 bit
1= CLC1 module disabled
0= CLC1 module enabled
DSMMD: Disable Data Signal Modulator bit
1= DSM module disabled
0= DSM module enabled
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 171
PIC16(L)F18326/18346
15.3 Interrupt Flags
15.0 INTERRUPT-ON-CHANGE
The bits located in the IOCxF registers are status flags
that correspond to the interrupt-on-change pins of each
port. If an expected edge is detected on an appropriately
enabled pin, then the status flag for that pin will be set,
and an interrupt will be generated if the IOCIE bit is set.
The IOCIF bit of the PIR0 register reflects the status of
all IOCxF bits.
All pins on all ports can be configured to operate as
Interrupt-On-Change (IOC) pins. An interrupt can be
generated by detecting a signal that has either a rising
edge or a falling edge. Any individual pin, or combination
of pins, can be configured to generate an interrupt. The
interrupt-on-change module has the following features:
• Interrupt-on-Change enable
- Rising and falling edge detection
• Individual pin configuration
• Individual pin interrupt flags
15.4 Clearing Interrupt Flags
The individual status flags, (IOCxF register bits), can be
cleared by resetting them to zero. If another edge is
detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
regardless of the value actually being written.
Figure 15-1 is a block diagram of the IOC module.
15.1 Enabling the Module
To allow individual pins to generate an interrupt, the
IOCIE bit of the PIE0 register must be set. If the IOCIE
bit is disabled, the edge detection on the pin will still
occur, but an interrupt will not be generated.
In order to ensure that no detected edge is lost while
clearing flags, only AND operations masking out known
changed bits should be performed. The following
sequence is an example of what should be performed.
EXAMPLE 15-1:
CLEARING INTERRUPT
FLAGS
(PORTA EXAMPLE)
15.2 Individual Pin Configuration
For each pin, a rising edge detector and a falling edge
detector are present. To enable a pin to detect a rising
edge, the associated bit of the IOCxP register is set. To
enable a pin to detect a falling edge, the associated bit
of the IOCxN register is set.
MOVLW 0xff
XORWF IOCAF, W
ANDWF IOCAF, F
A pin can be configured to detect rising and falling
edges simultaneously by setting the associated bits in
both of the IOCxP and IOCxN registers.
15.5 Operation in Sleep
The interrupt-on-change interrupt event will wake the
device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the affected
IOCxF register will be updated prior to the first instruction
executed out of Sleep.
DS40001839B-page 172
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
FIGURE 15-1:
INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE)
Rev. 10-000 037A
6/2/201 4
D
Q
IOCANx
R
Q4Q1
edge
detect
RAx
to data bus
IOCAFx
S
data bus =
0 or 1
D
Q
D
Q
IOCAPx
write IOCAFx
R
IOCIE
Q2
IOC interrupt
to CPU core
from all other
IOCnFx individual
pin detectors
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 173
PIC16(L)F18326/18346
15.6 Register Definitions: Interrupt-on-Change Control
REGISTER 15-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER
U-0
—
U-0
—
R/W-0/0
IOCAP5
R/W-0/0
IOCAP4
R/W-0/0
IOCAP3
R/W-0/0
IOCAP2
R/W-0/0
IOCAP1
R/W-0/0
IOCAP0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
IOCAP<5:0>: Interrupt-on-Change PORTA Positive Edge Enable bits
1= Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will
be set upon detecting an edge.
0= Interrupt-on-change disabled for the associated pin
REGISTER 15-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER
U-0
—
U-0
—
R/W-0/0
IOCAN5
R/W-0/0
IOCAN4
R/W-0/0
IOCAN3
R/W-0/0
IOCAN2
R/W-0/0
IOCAN1
R/W-0/0
IOCAN0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
IOCAN<5:0>: Interrupt-on-Change PORTA Negative Edge Enable bits
1= Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will
be set upon detecting an edge.
0= Interrupt-on-Change disabled for the associated pin
DS40001839B-page 174
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
REGISTER 15-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER
U-0
—
U-0
—
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HS - Bit is set in hardware
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
IOCAF<5:0>: Interrupt-on-Change PORTA Flag bits
1= An enabled change was detected on the associated pin
Set when IOCAPx = 1and a rising edge was detected on RAx, or when IOCANx = 1and a falling
edge was detected on RAx.
0= No change was detected, or the user cleared the detected change.
REGISTER 15-4: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER(1)
R/W-0/0
IOCBP7
R/W-0/0
IOCBP6
R/W-0/0
IOCBP5
R/W-0/0
IOCBP4
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-4
IOCBP<7:4>: Interrupt-on-Change PORTB Positive Edge Enable bits
1= Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will
be set upon detecting an edge.
0= Interrupt-on-Change disabled for the associated pin
bit 3-0
Unimplemented: Read as ‘0’
Note 1: PIC16(L)F18346 only.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 175
PIC16(L)F18326/18346
REGISTER 15-5: IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER(1)
R/W-0/0
IOCBN7
R/W-0/0
IOCBN6
R/W-0/0
IOCBN5
R/W-0/0
IOCBN4
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-4
IOCBN<7:4>: Interrupt-on-Change PORTB Negative Edge Enable bits
1= Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will
be set upon detecting an edge.
0= Interrupt-on-Change disabled for the associated pin
bit 3-0
Unimplemented: Read as ‘0’
Note 1: PIC16(L)F18346 only.
REGISTER 15-6: IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER(1)
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
U-0
—
U-0
—
U-0
—
U-0
—
IOCBF7
bit 7
IOCBF6
IOCBF5
IOCBF4
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HS - Bit is set in hardware
bit 7-4
IOCBF<7:4>: Interrupt-on-Change PORTB Flag bits
1= An enabled change was detected on the associated pin
Set when IOCBPx = 1and a rising edge was detected on RBx, or when IOCBNx = 1and a falling
edge was detected on RBx.
0= No change was detected, or the user cleared the detected change.
bit 3-0
Unimplemented: Read as ‘0’
Note 1: PIC16(L)F18346 only.
DS40001839B-page 176
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
REGISTER 15-7: IOCCP: INTERRUPT-ON-CHANGE PORTC POSITIVE EDGE REGISTER
R/W-0/0
IOCCP7(1)
R/W-0/0
IOCCP6(1)
R/W-0/0
IOCCP5
R/W-0/0
IOCCP4
R/W-0/0
IOCCP3
R/W-0/0
IOCCP2
R/W-0/0
IOCCP1
R/W-0/0
IOCCP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
IOCCP<7:6>: Interrupt-on-change PORTC Positive Edge Enable bits(1)
1= Interrupt-on-change enabled on the pin for a positive going edge. IOCCFx bit and IOCIF flag
will be set upon detecting an edge.
0= Interrupt-on-change disabled for the associated pin
bit 5-0
IOCCP<5:0>: Interrupt-on-change PORTC Positive Edge Enable bits
1= Interrupt-on-change enabled on the pin for a positive going edge. IOCCFx bit and IOCIF flag
will be set upon detecting an edge.
0= Interrupt-on-change disabled for the associated pin
Note 1: PIC16(L)F18346 only.
REGISTER 15-8: IOCCN: INTERRUPT-ON-CHANGE PORTC NEGATIVE EDGE REGISTER
R/W-0/0
IOCCN7(1)
R/W-0/0
IOCCN6(1)
R/W-0/0
IOCCN5
R/W-0/0
IOCCN4
R/W-0/0
IOCCN3
R/W-0/0
IOCCN2
R/W-0/0
IOCCN1
R/W-0/0
IOCCN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
IOCCN<7:6>: Interrupt-on-change PORTC Negative Edge Enable bits(1)
1= Interrupt-on-change enabled on the pin for a negative going edge. IOCCFx bit and IOCIF flag will
be set upon detecting an edge.
0= Interrupt-on-change disabled for the associated pin
bit 5-0
IOCCN<5:0>: Interrupt-on-change PORTC Negative Edge Enable bits
1= Interrupt-on-Change enabled on the pin for a negative going edge. IOCCFx bit and IOCIF flag will
be set upon detecting an edge.
0= Interrupt-on-Change disabled for the associated pin
Note 1: PIC16(L)F18346 only.
2016-2017 Microchip Technology Inc.
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PIC16(L)F18326/18346
REGISTER 15-9: IOCCF: INTERRUPT-ON-CHANGE PORTC FLAG REGISTER
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
IOCCF7(1)
IOCCF6(1)
IOCCF5
IOCCF4
IOCCF3
IOCCF2
IOCCF1
IOCCF0
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HS - Bit is set in hardware
bit 7-6
bit 5-0
IOCCF<7:6>: Interrupt-on-Change PORTC Flag bits
1= An enabled change was detected on the associated pin.
Set when IOCCPx = 1 and a rising edge was detected on RCx, or when IOCCNx = 1 and a
falling edge was detected on RCx.
0= No change was detected, or the user cleared the detected change.
IOCCF<5:0>: Interrupt-on-Change PORTC Flag bits
1= An enabled change was detected on the associated pin.
Set when IOCCPx = 1 and a rising edge was detected on RCx, or when IOCCNx = 1 and a
falling edge was detected on RCx.
0= No change was detected, or the user cleared the detected change.
Note 1: PIC16(L)F18346 only.
TABLE 15-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
ANSELB(1)
ANSELC
TRISA
—
—
ANSA4
ANSB5
ANSC5
TRISA5
TRISB5
ANSA4
ANSB4
ANSC4
TRISA4
TRISB4
—
—
ANSA2
—
ANSA1
—
ANSA0
—
144
150
157
143
149
155
100
101
174
174
175
175
176
176
177
177
178
ANSB7
ANSC7(1) ANSC6(1)
ANSB6
ANSC3
ANSC2
TRISA2
—
ANSC1
TRISA1
—
ANSC0
TRISA0
—
(2)
—
—
—
TRISB(1)
TRISB7
TRISB6
—
TRISC
TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
INTCON
PIE0
GIE
—
PEIE
—
—
—
—
—
—
—
—
—
INTEDG
INTE
TMR0IE
IOCIE
IOCAP
IOCAN
IOCAF
IOCBP(1)
IOCBN(1)
IOCBF(1)
IOCCP
IOCCN
IOCCF
—
—
IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0
IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0
—
—
—
—
IOCAF5 IOCAF4
IOCBP5 IOCBP4
IOCBN5 IOCBN4
IOCBF5 IIOCBF4
IOCAF3
IOCAF2 IOCAF1 IOCAF0
IOCBP7
IOCBN7
IOCBF7
IOCBP6
IOCBN6
IOCBF6
—
—
—
—
—
—
—
—
—
—
—
—
IOCCP7(1) IOCCP6(1) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0
IOCCN7(1) IOCCN6(1) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0
IOCCF7(1) IOCCF6(1) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change.
Note 1: PIC16(L)F18346 only.
2: Unimplemented, read as ‘1’.
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16.1 Independent Gain Amplifiers
16.0 FIXED VOLTAGE REFERENCE
(FVR)
The output of the FVR, which is supplied to the ADC,
Comparators and DAC, is routed through two
independent programmable gain amplifiers. Each
amplifier can be programmed for a gain of 1x, 2x or 4x,
to produce the three possible voltage levels.
The Fixed Voltage Reference, or FVR, is a stable
voltage reference, independent of VDD, with 1.024V,
2.048V or 4.096V selectable output levels. The output
of the FVR subsystem can be configured to supply a
reference voltage to the following:
The ADFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module.
• ADC input channel
• ADC positive reference
• Comparator positive input
• Digital-to-Analog Converter (DAC)
Reference
Section 22.0
“Analog-to-Digital
Converter (ADC) Module” for additional information.
The CDAFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the DAC and comparator
The FVR can be enabled by setting the FVREN bit of
the FVRCON register.
module.
Reference
Section 24.0
“5-bit
Digital-to-Analog Converter (DAC1) Module” and
Section 18.0 “Comparator Module” for additional
information.
Note:
Fixed Voltage Reference output cannot
exceed VDD.
16.2 FVR Stabilization Period
When the Fixed Voltage Reference module is enabled, it
requires time for the reference and amplifier circuits to
stabilize. See Table 35-16 for FVR start-up times.
FIGURE 16-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
Rev. 10-000 053C
12/9/201 3
2
2
ADFVR<1:0>
1x
2x
4x
FVR_buffer1
(To ADC Module)
CDAFVR<1:0>
FVR_buffer2
(To Comparators
and DAC)
1x
2x
4x
FVREN
Note 1
+
FVRRDY
_
Note:
Any peripheral requiring the fixed reference (see Table 16-1).
2016-2017 Microchip Technology Inc.
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16.3 Register Definitions: FVR Control
REGISTER 16-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R/W-0/0
FVREN
R-q/q
FVRRDY(1)
R/W-0/0
TSEN(3)
R/W-0/0
TSRNG(3)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CDAFVR<1:0>
ADFVR<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
bit 5
bit 4
bit 3-2
FVREN: Fixed Voltage Reference Enable bit
1= Fixed Voltage Reference is enabled
0= Fixed Voltage Reference is disabled
FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
1= Fixed Voltage Reference output is ready for use
0= Fixed Voltage Reference output is not ready or not enabled
TSEN: Temperature Indicator Enable bit(3)
1= Temperature Indicator is enabled
0= Temperature Indicator is disabled
TSRNG: Temperature Indicator Range Selection bit(3)
1= VOUT = VDD - 4VT (High Range)
0= VOUT = VDD - 2VT (Low Range)
CDAFVR<1:0>: Comparator FVR Buffer Gain Selection bits
11= Comparator FVR Buffer Gain is 4x, (4.096V)(2)
10= Comparator FVR Buffer Gain is 2x, (2.048V)(2)
01= Comparator FVR Buffer Gain is 1x, (1.024V)
00= Comparator FVR Buffer is off
bit 1-0
ADFVR<1:0>: ADC FVR Buffer Gain Selection bit
11= ADC FVR Buffer Gain is 4x, (4.096V)(2)
10= ADC FVR Buffer Gain is 2x, (2.048V)(2)
01= ADC FVR Buffer Gain is 1x, (1.024V)
00= ADC FVR Buffer is off
Note 1: FVRRDY is always ‘1’.
2: Fixed Voltage Reference output cannot exceed VDD.
3: See Section 17.0 “Temperature Indicator Module” for additional information.
DS40001839B-page 180
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PIC16(L)F18326/18346
TABLE 16-1: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on page
FVRCON
ADCON0
ADCON1
CMxCON1
FVREN FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
ADFVR<1:0>
180
244
245
191
263
CHS<5:0>
ADCS<2:0>
CxPCH<2:0>
DAC1OE
GO/DONE
ADON
ADFM
—
ADNREF
ADPREF<1:0>
CxINTP CxINTN
CxNCH<2:0>
—
DAC1CON0 DAC1EN
—
—
DAC1PPS<1:0>
DAC1NSS
Legend: Shaded cells are not used with the Fixed Voltage Reference.
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PIC16(L)F18326/18346
FIGURE 17-1:
TEMPERATURE CIRCUIT
DIAGRAM
17.0 TEMPERATURE INDICATOR
MODULE
This family of devices is equipped with a temperature
circuit designed to measure the operating temperature
of the silicon die. The circuit’s range of operating
temperature falls between -40°C and +85°C. The
output is a voltage that is proportional to the device
temperature. The output of the temperature indicator is
internally connected to the device ADC.
VDD
TSEN
TSRNG
The circuit may be used as a temperature threshold
detector or a more accurate temperature indicator,
depending on the level of calibration performed. A one-
point calibration allows the circuit to indicate a
temperature closely surrounding that point. A two-point
calibration allows the circuit to sense the entire range
of temperature more accurately. Reference Application
Note AN2092, “Using the Temperature Indicator
Module” (DS00002092) for more details regarding the
calibration process.
VOUT
To ADC
Temp. Indicator
17.1 Circuit Operation
17.2 Minimum Operating VDD
Figure 17-1 shows a simplified block diagram of the
temperature circuit. The proportional voltage output is
achieved by measuring the forward voltage drop across
multiple silicon junctions.
When the temperature circuit is operated in low range,
the device may be operated at any operating voltage
that is within specifications.
When the temperature circuit is operated in high range,
the device operating voltage, VDD, must be high
enough to ensure that the temperature circuit is
correctly biased.
Equation 17-1 describes the output characteristics of
the temperature indicator.
EQUATION 17-1: VOUT RANGES
Table 17-1 shows the recommended minimum VDD vs.
range setting.
High Range: VOUT = VDD - 4VT
Low Range: VOUT = VDD - 2VT
TABLE 17-1: RECOMMENDED VDD VS.
RANGE
The temperature sense circuit is integrated with the
Fixed Voltage Reference (FVR) module. See
Section 16.0 “Fixed Voltage Reference (FVR)” for
more information.
Min. VDD, TSRNG = 1
Min. VDD, TSRNG = 0
3.6V
1.8V
The circuit is enabled by setting the TSEN bit of the
FVRCON register. When disabled, the circuit draws no
current.
17.3 Temperature Output
The output of the circuit is measured using the internal
Analog-to-Digital Converter. A channel is provided for
the temperature circuit output. Refer to Section 22.0
“Analog-to-Digital Converter (ADC) Module” for
detailed information.
The circuit operates in either high or low range. The high
range, selected by setting the TSRNG bit of the
FVRCON register, provides a wider output voltage. This
provides more resolution over the temperature range.
This range requires a higher bias voltage to operate and
thus, a higher VDD is needed.
The low range is selected by clearing the TSRNG bit of
the FVRCON register. The low range generates a lower
voltage drop and thus, a lower VDD voltage is needed to
operate the circuit. The low range is provided for low
voltage operation.
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17.4 ADC Acquisition Time
To ensure accurate temperature measurements, the
user must wait at least 200 s after the ADC input
multiplexer is connected to the temperature indicator
output before the conversion is performed.
TABLE 17-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on page
FVRCON
FVREN FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
ADFVR<1:0>
180
Legend: Shaded cells are unused by the temperature indicator module.
2016-2017 Microchip Technology Inc.
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DS40001839B-page 183
PIC16(L)F18326/18346
18.0 COMPARATOR MODULE
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
Comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of program execution. The analog
comparator module includes the following features:
• Programmable input selection
- Selectable voltage reference
• Programmable output polarity
• Rising/falling output edge interrupts
• Wake-up from Sleep
• CWG Auto-shutdown source
18.1
Comparator Overview
A single comparator is shown in Figure 18-1 along with
the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
The comparators available for this device are located in
Table 18-1.
TABLE 18-1: AVAILABLE COMPARATORS
Device
PIC16(L)F18326
C1
C2
●
●
●
●
PIC16(L)F18346
FIGURE 18-1:
SINGLE COMPARATOR
VIN+
VIN-
+
Output
–
VIN-
VIN+
Output
Note:
The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
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PIC16(L)F18326/18346
FIGURE 18-2:
COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM
Rev. 10-000027M
9/20/2016
3
CxNCH<2:0>
CxON(1)
CxINTP
CxINTN
Interrupt
Rising
Edge
set bit
CxIF
CxIN0-
CxIN1-
000
001
010
011
100
101
110
111
Interrupt
Falling
Edge
CxON(1)
Cx
CxIN2-
CxIN3-
CxVN
CxVP
CxOUT
-
D
Q
Reserved
Reserved
FVR_buffer2
MCxOUT
+
Q1
CxSP CxHYS
CxPOL
CxOUT_sync
to
peripherals
CxSYNC
CxIN0+
Reserved
Reserved
Reserved
Reserved
DAC_output
FVR_buffer2
000
001
010
011
100
101
110
111
TRIS bit
0
1
CxOUT
PPS
D
Q
RxyPPS
(From Timer1 Module) T1CLK
CxPCH<2:0>
CxON(1)
2
Note 1:
When CxON = 0, all multiplexer inputs are disconnected and the Comparator will produce a ‘0’ at the output.
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18.2.3
COMPARATOR OUTPUT POLARITY
18.2 Comparator Control
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a non-inverted output.
Each comparator has two control registers: CMxCON0
and CMxCON1.
The CMxCON0 register (see Register 18-1) contains
Control and Status bits for the following:
• Enable
• Output
• Output polarity
• Hysteresis enable
• Timer1 output synchronization
Table 18-2 shows the output state versus input
conditions, including polarity control.
TABLE 18-2: COMPARATOR OUTPUT
STATE VS. INPUT
CONDITIONS
The CMxCON1 register (see Register 18-2) contains
Control bits for the following:
Input Condition
CxPOL
CxOUT
• Interrupt on positive/negative edge enables
• Positive input channel selection
• Negative input channel selection
CxVN > CxVP
CxVN < CxVP
CxVN > CxVP
CxVN < CxVP
0
0
1
1
0
1
1
0
18.2.1
COMPARATOR ENABLE
Setting the CxON bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
18.3 Comparator Hysteresis
A selectable amount of separation voltage can be
added to the input pins of each comparator to provide a
hysteresis function to the overall operation. Hysteresis
is enabled by setting the CxHYS bit of the CMxCON0
register.
18.2.2
COMPARATOR OUTPUT
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CMOUT register.
See Comparator Specifications in Table 35-14 for more
information.
The comparator output can also be routed to an
external pin through the RxyPPS register
(Register 13-2). The corresponding TRIS bit must be
clear to enable the pin as an output.
18.4 Timer1 Gate Operation
The output resulting from a comparator operation can
be used as a source for gate control of Timer1. See
Section 27.5 “Timer1 Gate” for more information.
This feature is useful for timing the duration or interval
of an analog event.
Note 1: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
It is recommended that the comparator output be
synchronized to Timer1. This ensures that Timer1 does
not increment while a change in the comparator is
occurring.
18.4.1
COMPARATOR OUTPUT
SYNCHRONIZATION
The output from a comparator can be synchronized
with Timer1 by setting the CxSYNC bit of the
CMxCON0 register.
Once enabled, the comparator output is latched on the
falling edge of the Timer1 source clock.This allows the
timer/counter to synchronize with the CxOUT bit so that
the software sees no ambiguity due to timing. See the
Comparator Block Diagram (Figure 18-2) and the
Timer1 Block Diagram (Figure 27-1) for more
information.
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18.5 Comparator Interrupt
18.7 Comparator Negative Input
Selection
An interrupt can be generated when either the rising
edge or falling edge detector detects a change in the
output value of each comparator.
The CxNCH<2:0> bits of the CMxCON1 register direct
an analog input pin and internal reference voltage or
analog ground to the inverting input of the comparator:
When either edge detector is triggered and its
associated enable bit is set (CxINTP and/or CxINTN
bits of the CMxCON1 register), the Corresponding
Interrupt Flag bit (CxIF bit of the PIR2 register) will be
set.
• CxIN- pin
• FVR (Fixed Voltage Reference)
• Analog Ground
To enable the interrupt, you must set the following bits:
Note:
To use CxINy+ and CxINy- pins as analog
input, the appropriate bits must be set in
• CxON bit of the CMxCON0 register
• CxIE bit of the PIE2 register
• CxINTP bit of the CMxCON1 register (for a rising
edge detection)
• CxINTN bit of the CMxCON1 register (for a falling
edge detection)
the
ANSEL
register
and
the
corresponding TRIS bits must also be set
to disable the output drivers.
• PEIE and GIE bits of the INTCON register
18.8 Comparator Response Time
The associated interrupt flag bit, CxIF bit of the PIR2
register, must be cleared in software. If another edge is
detected while this flag is being cleared, the flag will still
be set at the end of the sequence.
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the comparator
differs from the settling time of the voltage reference.
Therefore, both of these times must be considered when
determining the total response time to a comparator
input change. See the Comparator and Voltage
Reference Specifications in Table 35-14 for more
details.
Note:
Although a comparator is disabled, an
interrupt can be generated by changing
the output polarity with the CxPOL bit of
the CMxCON0 register, or by switching
the comparator on or off with the CxON bit
of the CMxCON0 register.
18.6 Comparator Positive Input
Selection
Configuring the CxPCH<2:0> bits of the CMxCON1
register directs an internal voltage reference or an
analog pin to the non-inverting input of the comparator:
• CxIN0+ analog pin
• DAC output
• FVR (Fixed Voltage Reference)
• VSS (Ground)
See Section 16.0 “Fixed Voltage Reference (FVR)”
for more information on the Fixed Voltage Reference
module.
See Section 24.0 “5-bit Digital-to-Analog Converter
(DAC1) Module” for more information on the DAC
input signal.
Any time the comparator is disabled (CxON = 0), all
comparator inputs are disabled.
2016-2017 Microchip Technology Inc.
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PIC16(L)F18326/18346
18.9 Analog Input Connection
Considerations
Note 1: When reading a PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
provide an input based on their level as
either a TTL or ST input buffer.
A simplified circuit for an analog input is shown in
Figure 18-3. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is
forward biased and a latch-up may occur.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, may have very little leakage current to
minimize inaccuracies introduced.
FIGURE 18-3:
ANALOG INPUT MODEL
VDD
Analog
Input
pin
VT 0.6V
RIC
Rs < 10K
To Comparator
(1)
ILEAKAGE
CPIN
5 pF
VA
VT 0.6V
Vss
Legend: CPIN
= Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
RS
VA
= Interconnect Resistance
= Source Impedance
= Analog Voltage
VT
= Threshold Voltage
Note 1: See I/O Ports in Table 35-4.
DS40001839B-page 188
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18.10 CWG Auto-shutdown Source
The output of the comparator module can be used as
an auto-shutdown source for the CWG module. When
the output of the comparator is active and the
corresponding ASxE is enabled, the CWG operation
will be suspended immediately (Section 20.7.1.2
“External Input Source Shutdown”).
18.11 Operation in Sleep Mode
The comparator module can operate during Sleep. The
comparator clock source is based on the Timer1 clock
source. If the Timer1 clock source is either the system
clock (FOSC) or the instruction clock (FOSC/4), Timer1
will not operate during Sleep, and synchronized
comparator outputs will not operate.
A comparator interrupt will wake the device from Sleep.
The CxIE bits of the PIE2 register must be set to enable
comparator interrupts.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 189
PIC16(L)F18326/18346
18.12 Register Definitions: Comparator Control
REGISTER 18-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0
R/W-0/0
CxON
R-0/0
U-0
—
R/W-0/0
CxPOL
U-0
—
R/W-1/1
CxSP
R/W-0/0
CxHYS
R/W-0/0
CxSYNC
CxOUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
CxON: Comparator Enable bit
1= Comparator is enabled
0= Comparator is disabled and consumes no active power
CxOUT: Comparator Output bit
If CxPOL = 1(inverted polarity):
1= CxVP < CxVN
0= CxVP > CxVN
If CxPOL = 0(non-inverted polarity):
1= CxVP > CxVN
0= CxVP < CxVN
bit 5
bit 4
Unimplemented: Read as ‘0’
CxPOL: Comparator Output Polarity Select bit
1= Comparator output is inverted
0= Comparator output is not inverted
bit 3
bit 2
Unimplemented: Read as ‘0’
CxSP: Comparator Speed/Power Select bit
1= Comparator operates in Normal-Power, High-Speed mode
0= Reserved. (do not use)
bit 1
bit 0
CxHYS: Comparator Hysteresis Enable bit
1= Comparator hysteresis enabled
0= Comparator hysteresis disabled
CxSYNC: Comparator Output Synchronous Mode bit
1= Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.
Output updated on the falling edge of Timer1 clock source.
0= Comparator output to Timer1 and I/O pin is asynchronous
DS40001839B-page 190
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
REGISTER 18-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1
R/W-0/0
CxINTP
R/W-0/0
CxINTN
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CxPCH<2:0>
CxNCH<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7
CxINTP: Comparator Interrupt on Positive Going Edge Enable bits
1= The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit
0= No interrupt flag will be set on a positive going edge of the CxOUT bit
bit 6
CxINTN: Comparator Interrupt on Negative Going Edge Enable bits
1= The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit
0= No interrupt flag will be set on a negative going edge of the CxOUT bit
bit 5-3
CxPCH<2:0>: Comparator Positive Input Channel Select bits
111= CxVP connects to VSS
110= CxVP connects to FVR Buffer 2
101= CxVP connects to DAC output
100= CxVP unconnected
011= CxVP unconnected
010= CxVP unconnected
001= CxVN unconnected
000= CxVP connects to CxIN0+ pin
bit 2-0
CxNCH<2:0>: Comparator Negative Input Channel Select bits
111= CxVN connects to VSS
110= CxVN connects to FVR Buffer 2
101= CxVN unconnected
100= CxVN unconnected
011= CxVN connects to CxIN3- pin
010= CxVN connects to CxIN2- pin
001= CxVN connects to CxIN1- pin
000= CxVN connects to CxIN0- pin
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 191
PIC16(L)F18326/18346
REGISTER 18-3: CMOUT: COMPARATOR OUTPUT REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-0/0
R-0/0
MC2OUT
MC1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-2
bit 1
Unimplemented: Read as ‘0’
MC2OUT: Mirror Copy of C2OUT bit
MC1OUT: Mirror Copy of C1OUT bit
bit 0
TABLE 18-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
ANSELB(1)
ANSELC
TRISA
―
―
ANSA5
ANSB5
ANSC5
TRISA5
TRISB5
TRISC5
―
ANSA4
ANSB4
ANSC4
TRISA4
TRISB4
TRISC4
CxPOL
CxPCH<2:0>
―
―
―
ANSA2
―
ANSA1
―
ANSA0
―
144
150
157
143
149
155
190
191
192
180
263
264
100
103
108
162
162
162
218
ANSB7
ANSC7(1)
―
ANSB6
ANSC6(1)
―
ANSC3
―
ANSC2
TRISA2
―
ANSC1
TRISA1
―
ANSC0
TRISA0
―
TRISB(1)
TRISB7
TRISB6
―
TRISC
TRISC7(1) TRISC6(1)
TRISC3
―
TRISC2
CxSP
TRISC1
CxHYS
CxNCH<2:0>
MC2OUT
TRISC0
CxSYNC
CMxCON0
CMxCON1
CMOUT
CxON
CxINTP
―
CxOUT
CxINTN
―
―
TSEN
DAC1OE
―
―
―
MC1OUT
FVRCON
DACCON0
DACCON1
INTCON
PIE2
FVREN
DAC1EN
―
FVRRDY
―
TSRNG
―
CDAFVR<1:0>
DAC1PSS<1:0>
DAC1R<4:0>
ADFVR<1:0>
―
DAC1NSS
―
GIE
PEIE
―
―
―
―
―
INTEDG
NCO1IE
NCO1IF
C2IE
C2IF
―
C1IE
C1IF
―
NVMIE
NVMIF
TMR6IE
TMR6IF
―
SSP2IE
SSP2IF
BLC2IE
BLC2IF
TMR4IE
TMR4IF
PIR2
CLCINxPPS
MDMINPPS
T1GPPS
CWGxAS1
Legend:
CLCINxPPS<4:0>
MDMINPPS<4:0>
T1GPPS<4:0>
AS2E
―
―
―
―
―
―
―
―
―
AS4E
AS3E
AS1E
AS0E
— = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.
Note 1: PIC16(L)F18346 only.
DS40001839B-page 192
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
19.1 Standard PWM Mode
19.0 PULSE-WIDTH MODULATION
(PWM)
The standard PWM mode generates a Pulse-Width
Modulation (PWM) signal on the PWMx pin with up to
ten bits of resolution. The period, duty cycle, and
resolution are controlled by the following registers:
The PWMx modules generate Pulse-Width Modulated
(PWM) signals of varying frequency and duty cycle.
In
addition
to
the
CCP
modules,
the
• TMR2, TMR4 or TMR6 registers
• PR2, PR4 or PR6 registers
• PWMxCON registers
PIC16(L)F18326/18346 devices contain two PWM
modules.
Pulse-Width Modulation (PWM) is a scheme that
provides power to a load by switching quickly between
fully on and fully off states. The PWM signal resembles
a square wave where the high portion of the signal is
considered the ON state (pulse width), and the low
portion of the signal is considered the OFF state. The
term duty cycle describes the proportion of the ON time
to the OFF time and is expressed in percentages,
where 0% is fully OFF and 100% is fully ON. A lower
duty cycle corresponds to less power applied and a
higher duty cycle corresponds to more power applied.
The PWM period is defined as the duration of one
complete cycle or the total amount of on and off time
combined.
• PWMxDCH registers
• PWMxDCL registers
Figure 29-2 shows a simplified block diagram of the
PWM operation.
If PWMPOL = 0, the default state of the output is ‘0‘. If
PWMPOL = 1, the default state is ‘1’. If PWMEN = 0,
the output will be the default state.
Note:
Note:
The corresponding TRIS bit must be
cleared to enable the PWM output on the
PWMx pin
The formulas and text refer to TMR2 and
PR2, for simplicity. The same formulas
and text apply to TMR4/6 and PR4/6. The
timer sources can be selected in
Register 19-4. For additional information
on TMR2/4/6, refer to Section 28.0
“Timer 2/4/6 Module”
PWM resolution defines the maximum number of steps
that can be present in a single PWM period. A higher
resolution allows for more precise control of the
pulse-width time and in turn the power that is applied to
the load.
Figure 19-1 shows a typical waveform of the PWM
signal.
FIGURE 19-1:
PWM OUTPUT
Period
Pulse
Width
TMR2 = PR2
TMR2 = PWMDC
TMR2 = 0
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 193
PIC16(L)F18326/18346
FIGURE 19-2:
SIMPLIFIED PWM BLOCK DIAGRAM
Duty Cycle registers
PWMDCL<7:6>
PWMDCH
PWMx
R
S
Q
Q
Comparator
R
TMR2
Output Polarity
(PWMPOL)
Comparator
PR2
19.1.1
PWM PERIOD
19.1.2
PWM DUTY CYCLE
Referring to Figure 19-1, the PWM output has a period
and a pulse width. The frequency of the PWM is the
inverse of the period (1/period).
The PWM duty cycle is specified by writing a 10-bit
value to the PWMxDC register. The PWMxDCH
contains the eight MSbs and bits <7:6> of the
PWMxDCL register contain the two LSbs.
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
The PWMDC register is double-buffered and can be
updated at any time. This double buffering is essential
for glitch-free PWM operation. New values take effect
when TMR2 = PR2. Note that PWMDC is left-justified.
EQUATION 19-1: PWM PERIOD
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or two bits
of the prescaler, to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to
1:1.
PWM Period = PR2 + 1 4 TOSC
(TMR2 Prescale Value)
Note:
TOSC = 1/FOSC
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
Equation 19-2 is used to calculate the PWM pulse
width.
• TMR2 is cleared
• The PWMx pin is set (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
Equation 19-3 is used to calculate the PWM duty cycle
ratio.
• The PWM pulse width is latched from PWMxDC.
EQUATION 19-2: PULSE WIDTH
Pulse Width = PWMxDC TOSC
Note:
If the pulse-width value is greater than the
period, the assigned PWM pin(s) will
remain unchanged.
(TMR2 Prescale Value)
EQUATION 19-3: DUTY CYCLE RATIO
PWMxDC
Duty Cycle Ratio = ------------------------------
4PR2 + 1
DS40001839B-page 194
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
19.1.3
PWM RESOLUTION
19.1.7
SETUP FOR PWM OPERATION
PWM resolution, expressed in number of bits, defines
the maximum number of discrete steps that can be
present in a single PWM period. For example, a 10-bit
resolution will result in 1024 discrete steps, whereas an
8-bit resolution will result in 256 discrete steps.
The following steps will be taken when configuring the
module for using the PWMx outputs:
1. Disable the PWMx pin output driver(s) by setting
the associated TRIS bit(s).
2. Configure the PWM output polarity by
configuring the PWMxPOL bit of the PWMxCON
register.
The maximum PWM resolution is ten bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 19-4.
3. Load the PR2 register with the PWM period
value, as determined by Equation 19-1.
EQUATION 19-4: PWM RESOLUTION
4. Load the PWMxDCH register and bits <7:6> of
the PWMxDCL register with the PWM duty cycle
value, as determined by Equation 19-2.
log4PR2 + 1
Resolution = ----------------------------------------- bits
log2
5. Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the
PIR1 register.
• Select the Timer2 prescale value by
configuring the T2CKPS bit of the T2CON
register.
• Enable Timer2 by setting the TMR2ON bit of
the T2CON register.
Note:
If the pulse-width value is greater than the
period, the assigned PWM pin(s) will
remain unchanged.
19.1.4
OPERATION IN SLEEP MODE
6. Wait until the TMR2IF is set.
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the
PWMx pin is driving a value, it will continue to drive that
value. When the device wakes up, TMR2 will continue
from its previous state.
7. When the TMR2IF flag bit is set:
• Clear the associated TRIS bit(s) to enable
the output driver.
• Route the signal to the desired pin by
configuring the RxyPPS register.
• Enable the PWMx module by setting the
PWMxEN bit of the PWMxCON register.
19.1.5
CHANGES IN SYSTEM CLOCK
FREQUENCY
In order to send a complete duty cycle and period on
the first PWM output, the above steps must be followed
in the order given. If it is not critical to start with a
complete PWM signal, then the PWM module can be
enabled during Step 2 by setting the PWMxEN bit of the
PWMxCON register.
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 7.0, Oscillator Module for additional details.
19.1.6
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
PWMx registers to their Reset states.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 195
PIC16(L)F18326/18346
19.2 Register Definitions: PWM Control
REGISTER 19-1: PWMxCON: PWM CONTROL REGISTER
R/W-0/0
U-0
—
R-0
R/W-0/0
U-0
—
U-0
—
U-0
—
U-0
—
PWMxEN
PWMxOUT PWMxPOL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7
PWMxEN: PWM Module Enable bit
1= PWM module is enabled
0= PWM module is disabled
bit 6
bit 5
bit 4
Unimplemented: Read as ‘0’
PWMxOUT: PWM Module Output Level when bit is read.
PWMxPOL: PWMx Output Polarity Select bit
1= PWM output is active-low.
0= PWM output is active-high.
bit 3-0
Unimplemented: Read as ‘0’
REGISTER 19-2: PWMxDCH: PWM DUTY CYCLE HIGH BITS
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 0
PWMxDC<9:2>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
PWMxDC<9:2>: PWM Duty Cycle Most Significant bits
These bits are the MSbs of the PWM duty cycle. The two LSbs are found in PWMxDCL Register.
REGISTER 19-3: PWMxDCL: PWM DUTY CYCLE LOW BITS
R/W-x/u
R/W-x/u
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
PWMxDC<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5-0
PWMxDC<1:0>: PWM Duty Cycle Least Significant bits
These bits are the LSbs of the PWM duty cycle. The MSbs are found in PWMxDCH Register.
Unimplemented: Read as ‘0’
DS40001839B-page 196
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
TABLE 19-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
Timer Prescale
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
PR2 Value
0xFF
10
0xFF
10
0x17
6.6
Maximum Resolution (bits)
TABLE 19-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
Timer Prescale
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz 153.85 kHz 200.0 kHz
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
PR2 Value
0xFF
10
0xFF
10
0x17
6.6
Maximum Resolution (bits)
REGISTER 19-4: PWMTMRS: PWM TIMERS CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-1/1
R/W-0/0
R/W-1/1
P6TSEL<1:0>
P5TSEL<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-4
bit 3-2
Unimplemented: Read as ‘0’
P6TSEL<1:0>: PWM6 Mode Timer Selection bits
00=
01=
10=
11=
Reserved
PWM6 is based on TMR2
PWM6 is based on TMR4
PWM6 is based on TMR6
bit 1-0
P5TSEL<1:0>: PWM5 Mode Timer Selection bits
00=
01=
10=
11=
Reserved
PWM5 is based on TMR2
PWM5 is based on TMR4
PWM5 is based on TMR6
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 197
PIC16(L)F18326/18346
TABLE 19-3: SUMMARY OF REGISTERS ASSOCIATED WITH PWMx
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(2)
143
144
TRISA
—
—
TRISA5
ANSA5
TRISB5
ANSB5
TRISC5
TRISA4
ANSA4
TRISB4
ANSB4
TRISC4
—
TRISA2
ANSA2
TRISA1
ANSA1
TRISA0
ANSA0
ANSELA
—
—
—
—
—
(1)
TRISB
TRISB7
ANSB7
TRISB6
ANSB6
—
—
—
—
—
—
149
150
(1)
ANSELB
TRISC
(1)
(1)
TRISC7
TRISC6
TRISC3 TRISC2 TRISC1 TRISC0
155
157
(1)
(1)
ANSELC
ANSC7
ANSC6
—
ANSC5
ANSC4
ANSC3
—
ANSC2
—
ANSC1
—
ANSC0
—
PWM5CON PWM5EN
PWM5DCH
PWM5OUT PWM5POL
196
196
196
196
196
196
197
100
107
108
102
103
298
292
292
299
299
299
299
299
299
215
229
272
273
274
PWM5DC<9:2>
PWM5DCL
PWM5DC<1:0>
—
—
—
—
—
—
—
—
—
—
PWM6CON PWM6EN
PWM6DCH
—
PWM6OUT PWM6POL
PWM6DC<9:2>
PWM6DCL
PWMTMRS
INTCON
PIR1
PWM6DC<1:0>
—
—
—
—
—
—
—
—
GIE
—
—
—
P6TSEL<1:0>
P5TSEL<1:0>
PEIE
ADIF
C2IF
ADIE
C2IE
—
—
—
—
INTEDG
TMR1GIF
TMR6IF
TMR1GIE
TMR6IE
—
RCIF
C1IF
RCIE
C1IE
TXIF
NVMIF
TXIE
NVMIE
SSP1IF
SSP2IF
SSP1IE
SSP2IE
BCL1IF
BCL2IF
TMR2IF TMR1IF
TMR4IF NCO1IF
PIR2
PIE1
BCL1IE TMR2IE TMR1IE
BCL2IE TMR4IE NCO1IE
PIE2
T2CON
T4CON
T6CON
TMR2
T2OUTPS<3:0>
T4OUTPS<3:0>
T6OUTPS<3:0>
TMR2ON
TMR4ON
TMR6ON
T2CKPS<1:0>
T4CKPS<1:0>
T6CKPS<1:0>
—
—
TMR2<7:0>
TMR4
TMR4<7:0>
TMR6<7:0>
PR2<7:0>
PR4<7:0>
PR6<7:0>
—
TMR6
PR2
PR4
PR6
CWGxDAT
CLCxSELy
MDSRC
MDCARH
MDCARL
—
—
—
—
—
—
—
—
—
—
DAT<3:0>
LCxDyS<5:0>
MDMS<3:0>
MDCH<3:0>
MDCL<3:0>
—
—
—
MDCHPOL MDCHSYNC
MDCLPOL MDCLSYNC
Legend: -= Unimplemented locations, read as ‘0’. Shaded cells are not used by the PWM module.
Note 1: PIC16(L)F18346 only.
2: Unimplemented, read as ‘1’.
DS40001839B-page 198
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
20.2 Operating Modes
20.0 COMPLEMENTARY WAVEFORM
GENERATOR (CWG) MODULE
The CWGx module can operate in six different modes,
as specified by the MODE<2:0> bits of the
CWGxCON0 register:
The Complementary Waveform Generator (CWGx)
produces complementary waveforms with dead-band
delay from a selection of input sources.
• Half-Bridge mode
• Push-Pull mode
The CWGx module has the following features:
• Asynchronous Steering mode
• Synchronous Steering mode
• Full-Bridge mode, Forward
• Full-Bridge mode, Reverse
• Selectable dead-band clock source control
• Selectable input sources
• Output enable control
• Output polarity control
All modes accept a single pulse data input, and
provide up to four outputs as described in the following
sections.
• Dead-band control with independent 6-bit rising
and falling edge dead-band counters
• Auto-shutdown control with:
- Selectable shutdown sources
- Auto-restart enable
All modes include auto-shutdown control as described
in Section 20.11 “Register Definitions: CWG
Control”
- Auto-shutdown pin override control
20.1 Fundamental Operation
Note:
Except as noted for Full-bridge mode
(Section 20.2.4 “Full-Bridge Modes”),
mode changes may only be performed
while EN = 0(Register 20-1).
The CWG generates two output waveforms from the
selected input source.
The off-to-on transition of each output can be delayed
from the on-to-off transition of the other output, thereby,
creating a time delay immediately where neither output
is driven. This is referred to as dead time and is covered
in Section 20.6 “Dead-Band Control”.
20.2.1
HALF-BRIDGE MODE
In Half-Bridge mode, two output signals are generated
as true and inverted versions of the input as illustrated
in Figure 20-1. A non-overlap (dead-band) time is
inserted between the two outputs as described in
Section 20.6 “Dead-Band Control”. Steering modes
are not used in Half-Bridge mode.
It may be necessary to guard against the possibility of
circuit faults or a feedback event arriving too late or not
at all. In this case, the active drive must be terminated
before the Fault condition causes damage. This is
referred to as auto-shutdown and is covered in
Section 20.7 “Auto-Shutdown Control”.
The unused outputs, CWGxC and CWGxD, drive
similar signals with polarity independently controlled by
POLC and POLD, respectively.
FIGURE 20-1:
CWGx HALF-BRIDGE MODE OPERATION
CWG[
clock
Input
source
Rising Event
Dead Band
Rising Event
Dead Band
Rising Event
Dead Band
CWG[A
CWG[B
Falling Event
Dead Band
Falling Event
Dead Band
Falling Event
Dead Band
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20.2.2
PUSH-PULL MODE
In Push-Pull mode, two output signals are generated,
alternating copies of the input as illustrated in
Figure 20-2. This alternation creates the push-pull
effect required for driving some transformer based
power supply designs. Dead-band control is not used in
Push-Pull mode. Steering modes are not used in
Push-Pull mode.
The push-pull sequencer is reset whenever EN = 0or
if an auto-shutdown event occurs. The sequencer is
clocked by the first input pulse, and the first output
appears on CWGxA.
The unused outputs CWGxC and CWGxD drive copies
of CWGxA and CWGxB, respectively, but with polarity
controlled by POLC and POLD.
FIGURE 20-2:
CWGx PUSH-PULL MODE OPERATION
CWG[
clock
Input
source
CWG[A
CWG[B
20.2.3
STEERING MODES
In both Synchronous and Asynchronous Steering
modes, the modulated input signal can be steered to
any combination of four CWG outputs and a fixed-value
will be presented on all the outputs not used for the
PWM output. Each output has independent polarity,
steering, and shutdown options. Dead-band control is
not used in either Steering mode.
When STRy = 0(Register 20-5), the corresponding pin
is held at the level defined by SDATy (Register 20-5).
When STRy = 1, the pin is driven by the modulated
input signal.
The POLy bits (Register 20-2) control the signal
polarity only when STRy = 1.
The CWG auto-shutdown operation also applies to
Steering modes as described in Section 20.11
“Register Definitions: CWG Control”.
Note:
Only the WGSTRy bits are synchronized;
the WGSDATy (data) bits are not
synchronized.
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20.2.3.1
Synchronous Steering Mode
In Synchronous Steering mode (MODE<2:0> bits
= 001, Register 20-1), changes to steering selection
registers take effect on the next rising edge of the
modulated data input (Figure 20-3). In Synchronous
Steering mode, the output will always produce a
complete waveform.
FIGURE 20-3:
EXAMPLE OF SYNCHRONOUS STEERING (MODE<2:0> = 001)
Rising edge
of input
Rising edge
of input
CWG[
INPUT
WGSTRA
CWG[A
CWG[A follows CWG[ input
20.2.3.2
Asynchronous Steering Mode
In Asynchronous mode (MODE<2:0> bits = 000,
Register 20-1), steering takes effect at the end of the
instruction cycle that writes to WGxSTR. In
Asynchronous Steering mode, the output signal may
be an incomplete waveform (Register 20-4). This
operation may be useful when the user firmware needs
to immediately remove a signal from the output pin.
FIGURE 20-4:
EXAMPLE OF ASYNCHRONOUS STEERING (MODE<2:0> = 000)
CWG[
INPUT
End of Instruction Cycle
End of Instruction Cycle
WGSTRA
CWG[A
CWG[A follows CWG[ input
20.2.3.3
Start-up Considerations
The application hardware must use the proper external
pull-up and/or pull-down resistors on the CWG output
pins. This is required because all I/O pins are forced to
high-impedance at Reset.
The POLy bits (Register 20-2) allow the user to choose
whether the output signals are active-high or active-
low.
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20.2.4
FULL-BRIDGE MODES
In Forward and Reverse Full-Bridge modes, three out-
puts drive static values while the fourth is modulated by
the data input. Dead-band control is described in
Section 20.2.3 “Steering Modes” and Section 20.6
“Dead-Band Control”. Steering modes are not used
with either of the Full-Bridge modes.
The mode selection may be toggled between forward
and reverse (changing MODE<2:0>) without clearing
EN.
When connected as shown in Figure 20-5, the outputs
are appropriate for a full-bridge motor driver. Each
CWG output signal has independent polarity control, so
the circuit can be adapted to high-active and low-active
drivers.
FIGURE 20-5:
EXAMPLE OF FULL-BRIDGE APPLICATION
V+
QA
QC
FET
Driver
FET
Driver
CWG[A
CWG[B
Load
FET
Driver
FET
Driver
CWG[C
CWG[D
QB
QD
V-
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20.2.4.1
Full-Bridge Forward Mode
20.2.4.2
Full-Bridge Reverse Mode
In Full-Bridge Forward mode (MODE<2:0> = 010),
CWGxA is driven to its active state and CWGxD is
modulated while CWGxB and CWGxC are driven to
their inactive state, as illustrated at the top
of Figure 20-6.
In Full-Bridge Reverse mode (MODE<2:0> = 011),
CWGxC is driven to its active state and CWGxB is
modulated while CWGxA and CWGxD are driven to
their inactive state, as illustrated at the bottom of
Figure 20-6.
FIGURE 20-6:
EXAMPLE OF FULL-BRIDGE OUTPUT
Forward
Mode
Period
CWG1A(2)
CWG1B(2)
CWG1C(2)
CWG1D(2)
Pulse Width
(1)
(1)
Reverse
Mode
Period
CWG1A(2)
Pulse Width
CWG1B(2)
CWG1C(2)
CWG1D(2)
(1)
(1)
Note 1:
A rising CWG1 data input creates a rising event on the modulated output.
Output signals shown as active-high; all WGPOLy bits are clear.
2:
• The associated active output CWGxA and the
inactive output CWGxC are switched to drive in
the opposite direction.
• The previously modulated output CWGxD is
switched to the inactive state, and the previously
inactive output CWGxB begins to modulate.
• CWG modulation resumes after the
direction-switch dead band has elapsed.
20.2.4.3
Direction Change in Full-Bridge
Mode
In Full-Bridge mode, changing MODE<2:0> controls
the forward/reverse direction. Changes to MODE<2:0>
change to the new direction on the next rising edge of
the modulated input.
A direction change is initiated in software by changing
the MODE<2:0> bits of the WGxCON0 register. The
sequence is illustrated in Figure 20-7.
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Figure 20-7 shows an example of the CWG outputs
changing directions from forward to reverse, at near
100% duty cycle. In this example, at time t1, the output
of CWGxA and CWGxD become inactive, while output
CWGxC becomes active. Since the turn-off time of the
power devices is longer than the turn-on time, a shoot-
through current will flow through power devices QC and
QD for the duration of ‘t’. The same phenomenon will
occur to power devices QA and QB for the CWG
direction change from reverse to forward.
20.2.4.4
Dead-Band Delay in Full-Bridge
Mode
Dead-band delay is important when either of the
following conditions is true:
1. The direction of the CWG output changes when
the duty cycle of the data input is at or near
100%, or
2. The turn-off time of the power switch, including
the power device and driver circuit, is greater
than the turn-on time.
If changing the CWG direction at high duty cycle is
required for an application, two possible solutions for
eliminating the shoot-through current are:
The dead-band delay is inserted only when changing
directions, and only the modulated output is affected.
The statically-configured outputs (CWGxA and
CWGxC) are not afforded dead band, and switch
essentially simultaneously.
1. Reduce the CWG duty cycle for one period
before changing directions.
2. Use switch drivers that can drive the switches off
faster than they can drive them on.
FIGURE 20-7:
EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
t1
Forward Period
Reverse Period
CWG1A
CWG1B
CWG1C
CWG1D
Pulse Width
Pulse Width
TON
External Switch C
External Switch D
TOFF
Potential Shoot-
Through Current
T = TOFF - TON
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FIGURE 20-8:
SIMPLIFIED CWGx BLOCK DIAGRAM (HALF-BRIDGE MODE, MODE<2:0> = 100)
Rev. 10-000209A
10/16/2014
LSAC<1:0>
00
01
10
11
‘1’
‘0’
High-Z
Rising Dead-Band Block
clock
1
0
CWG CLOCK
cwg data
cwg data A
data out
CWGxA
CWGxB
CWGxC
CWGxD
data in
POLA
POLB
POLC
POLD
LSBD<1:0>
‘1’
‘0’
00
01
10
11
High-Z
Falling Dead-Band Block
1
0
clock
cwg data B
cwg data
data out
data in
LSAC<1:0>
CWG DATA
INPUT
00
01
10
11
‘1’
‘0’
Q
D
E
High-Z
EN
1
0
AS0E
CWGxPPS
LSBD<1:0>
AS1E
C1OUT
Auto-
shutdown
source
00
01
10
11
‘1’
‘0’
AS2E
C2OUT
AS3E
CLC2
High-Z
AS4E
CLC4
S
R
Q
SHUTDOWN = 1
1
0
REN
SHUTDOWN = 0
SHUTDOWN
FREEZE
D
Q
cwg data
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FIGURE 20-9:
SIMPLIFIED CWG BLOCK DIAGRAM (PUSH-PULL MODE, MODE <2:0> = 101)
Rev. 10-000210A
10/16/2014
LSAC<1:0>
00
01
10
11
‘1’
‘0’
High-Z
1
0
cwg data A
cwg data
CWGxA
CWGxB
CWGxC
CWGxD
POLA
POLB
POLC
POLD
LSBD<1:0>
‘1’
‘0’
00
01
10
11
D
Q
Q
High-Z
1
0
cwg data B
LSAC<1:0>
cwg data
CWG DATA
INPUT
00
01
10
11
‘1’
‘0’
Q
D
E
High-Z
EN
1
0
AS0E
CWGxPPS
LSBD<1:0>
AS1E
C1OUT
Auto-
shutdown
source
00
01
10
11
‘1’
‘0’
AS2E
C2OUT
AS3E
CLC2
High-Z
AS4E
CLC4
S
R
Q
SHUTDOWN = 1
1
0
REN
SHUTDOWN = 0
SHUTDOWN
FREEZE
D
Q
cwg data
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FIGURE 20-10:
SIMPLIFIED CWG BLOCK DIAGRAM (OUTPUT STEERING MODES)
Rev. 10-000211A
10/16/2014
MODE<2:0> = 000: Asynchronous
LSAC<1:0>
MODE<2:0> = 001: Synchronous
00
01
10
11
‘1’
‘0’
High-Z
cwg data A
POLA
1
0
1
0
CWGxA
CWGxB
CWGxC
CWGxD
DATA
STRA
LSBD<1:0>
‘1’
‘0’
00
01
10
11
High-Z
cwg data B
POLB
1
0
1
0
DATB
STRB
cwg data
LSAC<1:0>
CWG DATA
INPUT
00
01
10
11
‘1’
‘0’
Q
D
E
High-Z
EN
cwg data C
POLC
1
0
1
0
DATC
STRC
AS0E
CWGxPPS
LSBD<1:0>
Auto-
shutdown
source
AS1E
00
01
10
11
C1OUT
‘1’
‘0’
AS2E
C2OUT
High-Z
AS3E
CLC2
AS4E
CLC4
S
R
Q
cwg data D
POLD
1
0
SHUTDOWN = 1
1
0
REN
DATD
SHUTDOWN = 0
SHUTDOWN
FREEZE
STRD
D
Q
cwg data
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FIGURE 20-11:
SIMPLIFIED CWG BLOCK DIAGRAM (FORWARD AND REVERSE FULL-BRIDGE
MODES)
Rev. 10-000212A
10/16/2014
MODE<2:0> = 010: Forward
MODE<2:0> = 011: Reverse
LSAC<1:0>
00
01
10
11
‘1’
‘0’
Rising Dead-Band Block
clock
CWG CLOCK
High-Z
signal out
signal in
1
0
cwg data A
POLA
CWGxA
CWGxB
CWGxC
CWGxD
cwg data
MODE<2:0>
cwg data
LSBD<1:0>
D
Q
Q
‘1’
‘0’
00
01
10
11
cwg data
High-Z
signal in
signal out
1
0
cwg data B
POLB
CWG CLOCK
clock
Falling Dead-Band Block
LSAC<1:0>
cwg data
CWGx DATA
INPUT
00
01
10
11
‘1’
‘0’
Q
D
E
High-Z
EN
1
0
cwg data C
POLC
LSBD<1:0>
AS0E
CWGxPPS
AS1E
C1OUT
Auto-
shutdown
source
00
01
10
11
‘1’
‘0’
AS2E
C2OUT
AS3E
CLC2
High-Z
AS4E
CLC4
S
R
Q
SHUTDOWN = 1
1
0
cwg data D
POLD
REN
SHUTDOWN = 0
SHUTDOWN
FREEZE
D
Q
cwg data
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20.5.2
POLARITY CONTROL
20.3 Clock Source
The polarity of each CWG output can be selected
independently. When the output polarity bit is set, the
corresponding output is active-low. Clearing the output
polarity bit configures the corresponding output as
active-high. However, polarity does not affect the
override levels. Output polarity is selected with the
POLy bits of the CWGxCON1 register.
The clock source is used to drive the dead-band timing
circuits. The CWGx module allows the following clock
sources to be selected:
• FOSC (system clock)
• HFINTOSC (16 MHz only)
When the HFINTOSC is selected the HFINTOSC will
be kept running during Sleep. Therefore, CWG modes
requiring dead band can operate in Sleep provided that
the CWG data input is also active during Sleep. The
clock sources are selected using the CS bit of the
CWGxCLKCON register (Register 20-3).
20.6 Dead-Band Control
Dead-band control provides for non-overlapping output
signals to prevent current shoot-through in power
switches. The CWGx modules contain two 6-bit
dead-band counters. These counters can be loaded
with values that will determine the length of the dead
band initiated on either the rising or falling edges of the
input source. Dead-band control is used in either Half-
Bridge or Full-Bridge modes.
20.4 Selectable Input Sources
The CWG generates the output waveforms from the
input sources in Table 20-1.
The rising-edge dead-band delay is determined by the
rising dead-band count register (Register 20-8,
CWGxDBR) and the falling-edge dead-band delay is
determined by the falling dead-band count register
(Register 20-9, CWGxDBF). Dead-band duration is
established by counting the CWG clock periods from
zero up to the value loaded into either the rising or fall-
ing dead-band counter registers. The dead-band
counters are incremented on every rising edge of the
CWG clock source.
TABLE 20-1: SELECTABLE INPUT
SOURCES
Source
Signal Name
Peripheral
CWGxPPS CWG PPS input connection
C1OUT
C2OUT
CCP1
CCP2
CCP3
CCP4
PWM5
PWM6
NCO1
Comparator 1 output
Comparator 2 output
Capture/Compare/PWM output
Capture/Compare/PWM output
Capture/Compare/PWM output
Capture/Compare/PWM output
PWM5 output
20.6.1
RISING EDGE AND REVERSE
DEAD BAND
In Half-Bridge mode, the rising edge dead band delays
the turn-on of the CWGxA output after the rising edge
of the CWG data input. In Full-Bridge mode, the
reverse dead-band delay is only inserted when
changing directions from Forward mode to Reverse
mode, and only the modulated output CWGxB is
affected.
PWM6 output
Numerically Controlled Oscillator (NCO)
output
CLC1
CLC2
CLC3
CLC4
Configurable Logic Cell 1 output
Configurable Logic Cell 2 output
Configurable Logic Cell 3 output
Configurable Logic Cell 4 output
The CWGxDBR register determines the duration of the
dead-band interval on the rising edge of the input
source signal. This duration is from 0 to 64 periods of
the CWG clock.
The input sources are selected using the DAT<3:0>
bits in the CWGxDAT register (Register 20-4).
Dead band is always initiated on the edge of the input
source signal. A count of zero indicates that no dead
band is present.
20.5 Output Control
If the input source signal reverses polarity before the
dead-band count is completed then no output will be
seen on the respective output.
Immediately after the CWG module is enabled, the
complementary drive is configured with all output
drives cleared.
The CWGxDBR register value is double-buffered. If
EN = 0 (Register 20-1), the buffer is loaded when
CWGxDBR is written. If EN = 1, then the buffer will be
loaded at the rising edge, following the first falling edge
of the data input after the LD bit (Register 20-1) is set.
20.5.1
CWGx OUTPUTS
Each CWG output can be routed to a Peripheral Pin
Select (PPS) output via the RxyPPS register (see
Section 13.0 “Peripheral Pin Select (PPS)
Module”).
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20.6.2
FALLING EDGE AND FORWARD
DEAD BAND
EQUATION 20-1: DEAD-BAND DELAY TIME
CALCULATION
In Half-Bridge mode, the falling edge dead band delays
the turn-on of the CWGxB output at the falling edge of
the CWGx data input. In Full-Bridge mode, the forward
dead-band delay is only inserted when changing direc-
tions from Reverse mode to Forward mode, and only
the modulated output CWGxD is affected.
1
TDEAD – BAND_MIN = -------------------------------- DBx 4:0>
FCWG_CLOCK
1
TDEAD – BAND_MAX = -------------------------------- DBx 4:0> + 1
FCWG_CLOCK
The CWGxDBF register determines the duration of the
dead-band interval on the falling edge of the input
source signal. This duration is from zero to 64 periods
of the CWG clock.
TJITTER = TDEAD – BAND_MAX – TDEAD – BAND_MIN
Dead band is always initiated on the edge of the input
source signal. A count of zero indicates that no dead
band is present.
1
TJITTER = --------------------------------
FCWG_CLOCK
If the input source signal reverses polarity before the
dead-band count is completed, then no output will be
seen on the respective output.
TDEAD – BAND_MAX = TDEAD – BAND_MIN + TJITTER
The CWGxDBF register value is double-buffered.
When EN = 0 (Register 20-1), the buffer is loaded when
CWGxDBF is written. If EN = 1, then the buffer will be
loaded at the rising edge following the first falling edge
of the data input after the LD (Register 20-1) is set.
Example:
DBR 4:0> = 0x0A = 10
20.6.3
DEAD-BAND JITTER
FCWG_CLOCK = 8 MHz
The CWG input data signal may be asynchronous to
the CWG input clock, so some jitter may occur in the
observed dead band in each cycle. The maximum jitter
is equal to one CWG clock period. See Equation 20-1
for details and an example.
1
TJITTER = -----------------
8 MHz
TDEAD – BAND_MIN = 125 ns 10 = 1.25 s
TDEAD – BAND_MAX = 1.25 s + 0.125 s = 1.37 s
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20.7.1.3
Pin Override Levels
20.7 Auto-Shutdown Control
The levels driven to the CWG outputs during an auto-
shutdown event are controlled by the LSBD<1:0> and
LSAC<1:0> bits of the CWGxAS0 register
(Register 20-6). The LSBD<1:0> bits control CWGxB/D
output levels, while the LSAC<1:0> bits control the
CWGxA/C output levels.
Auto-shutdown is a method to immediately override the
CWG output levels with specific overrides that allow for
safe shutdown of the circuit. The shutdown state can
be either cleared automatically or held until cleared by
software.
20.7.1
SHUTDOWN
20.7.1.4
Auto-Shutdown Interrupts
The shutdown state can be entered by either of the
following two methods:
When an auto-shutdown event occurs, either by
software or hardware setting SHUTDOWN, the CWGxIF
flag bit of the PIR4 register is set (Register 8-11).
• Software generated
• External input
The SHUTDOWN bit indicates when a Shutdown
condition exists. The bit may be set or cleared in
software or by hardware.
20.8 Auto-Shutdown Restart
After an auto-shutdown event has occurred, there are
two ways to resume operation:
20.7.1.1
Software-Generated Shutdown
• Software controlled
• Auto-restart
Setting the SHUTDOWN bit of the CWGxAS0 register
will force the CWG into the Shutdown state.
In either case, the shutdown source must be cleared
before the restart can take place. That is, either the
Shutdown condition must be removed, or the
corresponding WGASxE bit must be cleared.
When auto-restart is disabled, the Shutdown state will
persist as long as the SHUTDOWN bit is set.
When auto-restart is enabled, the SHUTDOWN bit will
clear automatically and resume operation on the next
rising edge event.
20.8.1
SOFTWARE-CONTROLLED
RESTART
If the REN bit of the CWGxASD0 register is clear
(REN = 0), the CWGx module must be restarted after
an auto-shutdown event through software.
20.7.1.2
External Input Source Shutdown
Any of the auto-shutdown external inputs can be
selected to suspend the CWG operation. These
sources are individually enabled by the ASxE bits of the
CWGxAS1 register (Register 20-7). When any of the
selected inputs goes active (pins are active-low), the
CWG outputs will immediately switch to the override
levels selected by the LSBD<1:0> and LSAC<1:0> bits
without any software delay (Section 20.7.1.3 “Pin
Override Levels”). Any of the following external input
sources can be selected to cause a Shutdown
condition:
Once all auto-shutdown conditions are removed, the
software must clear SHUTDOWN. Once SHUTDOWN
is cleared, the CWG module will resume operation
upon the first rising edge of the CWG data input.
Note:
SHUTDOWN bit cannot be cleared in
software if the auto-shutdown condition is
still present.
• Comparator C1
• Comparator C2
• CLC2
20.8.2
AUTO-RESTART
If the REN bit of the CWGxASD0 register is set
(REN = 1), the CWGx module will restart from the
shutdown state automatically.
• CWGxPPS
Once all auto-shutdown conditions are removed, the
hardware will automatically clear SHUTDOWN. Once
SHUTDOWN is cleared, the CWG module will resume
operation upon the first rising edge of the CWG data
input.
Note:
Shutdown inputs are level sensitive, not
edge sensitive. The shutdown state
cannot be cleared, except by disabling
auto-shutdown, as long as the shutdown
input level persists.
Note:
SHUTDOWN bit cannot be cleared in
software if the auto-shutdown condition is
still present.
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20.9 Operation During Sleep
The CWGx module will operate during Sleep, provided
that the input sources remain active.
If the HFINTOSC is selected as the module clock
source, dead-band generation will remain active. This
will have a direct effect on the Sleep mode current.
20.10 Configuring the CWG
1. Ensure that the TRIS control bits corresponding
to CWG outputs are set so that all are
configured as inputs, ensuring that the outputs
are inactive during setup. External hardware
may ensure that pin levels are held to safe
levels.
2. Clear the EN bit, if not already cleared.
3. Configure the MODE<2:0> bits of the
CWGxCON0 register to set the output operating
mode.
4. Configure the POLy bits of the CWGxCON1
register to set the output polarities.
5. Configure the DAT<3:0> bits of the CWGxDAT
register to select the data input source.
6. If a Steering mode is selected, configure the
STRy bits to select the desired output on the
CWG outputs.
7. Configure the LSBD<1:0> and LSAC<1:0> bits
of the CWGxAS0 register to select the auto-
shutdown output override states (this is
necessary even if not using auto-shutdown
because start-up will be from a shutdown state).
8. If auto-restart is desired, set the REN bit of
CWGxAS0.
9. If auto-shutdown is desired, configure the ASxE
bits of the CWGxAS1 register to select the
shutdown source.
10. Set the desired rising and falling dead-band
times with the CWGxDBR and CWGxDBF
registers.
11. Select the clock source in the CWGxCLKCON
register.
12. Set the EN bit to enable the module.
13. Clear the TRIS bits that correspond to the CWG
outputs to set them as outputs.
14. If auto-restart is to be used, set the REN bit and
the SHUTDOWN bit will be cleared
automatically.
Otherwise,
clear
the
SHUTDOWN bit in software to start the CWG.
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20.11 Register Definitions: CWG Control
REGISTER 20-1: CWGxCON0: CWGx CONTROL REGISTER 0
R/W-0/0
EN
R/W/HC-0/0
LD(1)
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
MODE<2:0>
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS/HC = Bit is set/cleared by hardware
bit 7
bit 6
EN: CWGx Enable bit
1= CWGx is enabled
0= CWGx is disabled
LD: CWG Load Buffers bit(1)
1= Dead-band count buffers to be loaded on CWG data rising edge following first falling edge after
this bit is set.
0= Buffers remain unchanged
bit 5-3
bit 2-0
Unimplemented: Read as ‘0’
MODE<2:0>: CWGx Mode bits
111= Reserved
110= Reserved
101= CWG outputs operate in Push-Pull mode
100= CWG outputs operate in Half-Bridge mode
011= CWG outputs operate in Reverse Full-Bridge mode
010= CWG outputs operate in Forward Full-Bridge mode
001= CWG outputs operate in Synchronous Steering mode
000= CWG outputs operate in Asynchronous Steering mode
Note 1: This bit can only be set after EN = 1; it cannot be set in the same cycle when EN is set.
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REGISTER 20-2: CWGxCON1: CWGx CONTROL REGISTER 1
U-0
—
U-0
—
R-x
IN
U-0
—
R/W-0/0
POLD
R/W-0/0
POLC
R/W-0/0
POLB
R/W-0/0
POLA
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-6
bit 5
Unimplemented: Read as ‘0’
IN: CWGx Data Input Signal (read-only)
Unimplemented: Read as ‘0’
bit 4
bit 3
POLD: WGxD Output Polarity bit
1= Signal output is inverted polarity
0= Signal output is normal polarity
bit 2
bit 1
bit 0
POLC: WGxC Output Polarity bit
1= Signal output is inverted polarity
0= Signal output is normal polarity
POLB: WGxB Output Polarity bit
1= Signal output is inverted polarity
0= Signal output is normal polarity
POLA: WGxA Output Polarity bit
1= Signal output is inverted polarity
0= Signal output is normal polarity
REGISTER 20-3: CWGxCLKCON: CWGx CLOCK INPUT SELECTION REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
CS
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-1
bit 0
Unimplemented: Read as ‘0’
CS: CWG Clock Source Selection Select bits
WGCLK
Clock Source
0
1
FOSC
HFINTOSC (remains operating during Sleep)
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REGISTER 20-4: CWGxDAT: CWGx DATA INPUT SELECTION REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
DAT<3:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
DAT<3:0>: CWG Data Input Selection bits
DAT
Data Source
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CWGxPPS
C1OUT
C2OUT
CCP1
CCP2
CCP3
CCP4
PWM5
PWM6
NCO1
CLC1
CLC2
CLC3
CLC4
Reserved
Reserved
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PIC16(L)F18326/18346
(1)
REGISTER 20-5: CWGxSTR : CWG STEERING CONTROL REGISTER
R/W-0/0
OVRD
R/W-0/0
OVRC
R/W-0/0
OVRB
R/W-0/0
OVRA
R/W-0/0
STRD(2)
R/W-0/0
STRC(2)
R/W-0/0
STRB(2)
R/W-0/0
STRA(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
bit 5
bit 4
bit 3
OVRD: Steering Data D bit
OVRC: Steering Data C bit
OVRB: Steering Data B bit
OVRA: Steering Data A bit
STRD: Steering Enable bit D(2)
1= CWGxD output has the CWGx data input waveform with polarity control from POLD bit
0= CWGxD output is assigned to value of OVRD bit
bit 2
bit 1
bit 0
STRC: Steering Enable bit C(2)
1= CWGxC output has the CWGx data input waveform with polarity control from POLC bit
0= CWGxC output is assigned to value of OVRC bit
STRB: Steering Enable bit B(2)
1= CWGxB output has the CWGx data input waveform with polarity control from POLB bit
0= CWGxB output is assigned to value of OVRB bit
STRA: Steering Enable bit A(2)
1= CWGxA output has the CWGx data input waveform with polarity control from POLA bit
0= CWGxA output is assigned to value of OVRA bit
Note 1: The bits in this register apply only when MODE<2:0> = 00x(Register 20-1, steering modes).
2: This bit is double-buffered when MODE<2:0> = 001.
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REGISTER 20-6: CWGxAS0: CWG AUTO-SHUTDOWN CONTROL REGISTER 0
R/W/HS/SC-0/0
SHUTDOWN
bit 7
R/W-0/0
REN
R/W-0/0
R/W-1/1
R/W-0/0
R/W-1/1
U-0
—
U-0
—
LSBD<1:0>
LSAC<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
SHUTDOWN: Auto-Shutdown Event Status bit(1,2)
1= An auto-shutdown state is in effect
0= No auto-shutdown event has occurred
bit 6
REN: Auto-Restart Enable bit
1= Auto-restart is enabled
0= Auto-restart is disabled
bit 5-4
LSBD<1:0>: CWGxB and CWGxD Auto-Shutdown State Control bits
11= A logic ‘1’ is placed on CWGxB/D when an auto-shutdown event occurs.
10= A logic ‘0’ is placed on CWGxB/D when an auto-shutdown event occurs.
01= Pin is tri-stated on CWGxB/D when an auto-shutdown event occurs.
00= The inactive state of the pin, including polarity, is placed on CWGxB/D after the required
dead-band interval when an auto-shutdown event occurs.
bit 3-2
LSAC<1:0>: CWGxA and CWGxC Auto-Shutdown State Control bits
11= A logic ‘1’ is placed on CWGxA/C when an auto-shutdown event occurs.
10= A logic ‘0’ is placed on CWGxA/C when an auto-shutdown event occurs.
01= Pin is tri-stated on CWG1A/C when an auto-shutdown event occurs.
00= The inactive state of the pin, including polarity, is placed on CWGxA/C after the required
dead-band interval when an auto-shutdown event occurs.
bit 1-0
Unimplemented: Read as ‘0’
Note 1: This bit may be written while EN = 0(Register 20-1), to place the outputs into the shutdown configuration.
2: The outputs will remain in auto-shutdown state until the next rising edge of the CWG data input after this
bit is cleared.
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REGISTER 20-7: CWGxAS1: CWG AUTO-SHUTDOWN CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0/0
AS4E
R/W-0/0
AS3E
R/W-0/0
AS2E
R/W-0/0
AS1E
R/W-0/0
AS0E
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-5
bit 4
Unimplemented: Read as ‘0’
AS4E: CWG Auto-Shutdown Source 4 (CLC4) Enable bit
1= Auto-shutdown for CLC4 is enabled
0= Auto-shutdown for CLC4 is disabled
bit 3
bit 2
bit 1
bit 0
AS3E: CWG Auto-Shutdown Source 3 (CLC2) Enable bit
1= Auto-shutdown from CLC2 is enabled
0= Auto-shutdown from CLC2 is disabled
AS2E: CWG Auto-Shutdown Source 2 (C2) Enable bit
1= Auto-shutdown from Comparator 2 is enabled
0= Auto-shutdown from Comparator 2 is disabled
AS1E: CWG Auto-Shutdown Source 1 (C1) Enable bit
1= Auto-shutdown from Comparator 1 is enabled
0= Auto-shutdown from Comparator 1 is disabled
AS0E: CWG Auto-Shutdown Source 0 (CWGxPPS) Enable bit
1= Auto-shutdown from CWGxPPS is enabled
0= Auto-shutdown from CWGxPPS is disabled
REGISTER 20-8: CWGxDBR: CWGx RISING DEAD-BAND COUNT REGISTER
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
DBR<5:0>
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
DBR<5:0>: CWG Rising Edge Triggered Dead-Band Count bits
11 1111= 63-64 CWG clock periods
11 1110= 62-63 CWG clock periods
.
.
.
00 0010= 2-3 CWG clock periods
00 0001= 1-2 CWG clock periods
00 0000= 0 CWG clock periods. Dead-band generation is bypassed.
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REGISTER 20-9: CWGxDBF: CWGx FALLING DEAD-BAND COUNT REGISTER
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
DBF<5:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
DBF<5:0>: CWG Falling Edge Triggered Dead-Band Count bits
11 1111= 63-64 CWG clock periods
11 1110= 62-63 CWG clock periods
.
.
.
00 0010= 2-3 CWG clock periods
00 0001= 1-2 CWG clock periods
00 0000= 0 CWG clock periods. Dead-band generation is bypassed.
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TABLE 20-2: SUMMARY OF REGISTERS ASSOCIATED WITH CWGx
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(2)
TRISA
―
―
TRISA5 TRISA4
ANSA5 ANSA4
TRISB5 TRISB4
ANSB5 ANSB4
―
TRISA2 TRISA1 TRISA0
ANSA2 ANSA1 ANSA0
143
144
149
150
155
157
110
ANSELA
TRISB(1)
ANSELB(1)
―
―
―
―
―
TRISB7
ANSB7
TRISB6
ANSB6
―
―
―
―
―
―
TRISC
TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
ANSELC
ANSC7(1)
ANSC6(1) ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0
CWG1IF TMR5GIF TMR5IF CCP4IF CCP3IF CCP2IF CCP1IF
CWG1IE TMR5GIE TMR5IE CCP4IE CCP3IE CCP2IE CCP1IE
PIR4
CWG2IF
PIE4
CWG2IE
105
213
214
214
215
216
217
218
218
219
162
213
214
214
215
216
217
218
218
219
162
CWG1CON0
CWG1CON1
CWG1CLKCON
CWG1DAT
CWG1STR
CWG1AS0
CWG1AS1
CWG1DBR
CWG1DBF
CWG1PPS
CWG2CON0
CWG2CON1
CWG2CLKCON
CWG2DAT
CWG2STR
CWG2AS0
CWG2AS1
CWG2DBR
CWG2DBF
CWG2PPS
EN
LD
―
―
IN
―
―
―
POLD
―
MODE<2:0>
POLB
―
POLC
POLA
CS
―
―
―
―
―
―
―
―
―
―
DAT<3:0>
OVRD
OVRC
REN
―
OVRB
OVRA
STRD
STRC
STRB
―
STRA
―
SHUTDOWN
LSBD<1:0>
LSAC<1:0>
―
―
AS4E
AS3E
AS2E
AS1E
AS0E
―
―
DBR<5:0>
DBF<5:0>
CWG1PPS<4:0>
MODE<2:0>
―
―
―
―
―
―
EN
LD
―
―
―
―
POLD
―
―
IN
POLC
POLB
POLA
CS
―
―
―
―
―
―
―
―
―
―
DAT<3:0>
OVRD
OVRC
REN
―
OVRB
OVRA
STRD
STRC
STRB
―
STRA
―
SHUTDOWN
LSBD<1:0>
LSAC<1:0>
―
―
―
―
―
―
AS4E
AS3E
AS2E
AS1E
AS0E
―
DBR<5:0>
DBF<5:0>
CWG2PPS<4:0>
―
―
Note 1: PIC16(L)F18346 only.
2: Unimplemented, read as ‘0’.
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Refer to Figure 21-1 for a simplified diagram showing
signal flow through the CLCx.
21.0 CONFIGURABLE LOGIC CELL
(CLC)
Possible configurations include:
The Configurable Logic Cell (CLCx) provides
programmable logic that operates outside the speed
limitations of software execution. The logic cell takes up
to 36 input signals and, through the use of configurable
gates, reduces the 36 inputs to four logic lines that drive
one of eight selectable single-output logic functions.
•
Combinatorial Logic
- AND
- NAND
- AND-OR
- AND-OR-INVERT
- OR-XOR
Input sources are a combination of the following:
- OR-XNOR
• Latches
• I/O pins
- S-R
• Internal clocks
• Peripherals
• Register bits
- Clocked D with Set and Reset
- Transparent D with Set and Reset
- Clocked J-K with Reset
The output can be directed internally to peripherals and
to an output pin.
FIGURE 21-1:
CLCx SIMPLIFIED BLOCK DIAGRAM
Rev. 10-000025C
3/6/2014
LCxOUT
MLCxOUT
D
Q
Q1
LCx_in[0]
LCx_in[1]
LCx_in[2]
to Peripherals
CLCx
LCxEN
lcxq
.
.
.
lcxg1
lcxg2
lcxg3
lcxg4
Logic
LCx_out
PPS
Module
Function
(2)
LCxPOL
LCxMODE<2:0>
Interrupt
LCx_in[29]
LCx_in[30]
LCx_in[35]
det
LCXINTP
LCXINTN
set bit
CLCxIF
Interrupt
det
Note 1: See Figure 21-2.
2: See Figure 21-3.
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TABLE 21-1:
CLCx DATA INPUT SELECTION
CLCx Input Source
21.1 CLCx Setup
LCxDyS<5:0>
Value
Programming the CLCx module is performed by
configuring the four stages in the logic signal flow. The
four stages are:
100011[35]
100010 [34]
100001 [33]
100000 [32]
11111 [31]
11110 [30]
11101 [29]
11100 [28]
11011 [27]
11010 [26]
11001 [25]
11000 [24]
10111 [23]
10110 [22]
10101 [21]
10100 [20]
10011 [19]
10010 [18]
10001 [17]
10000 [16]
01111 [15]
01110 [14]
01101 [13]
01100 [12]
01011 [11]
01010 [10]
01001 [9]
01000 [8]
00111 [7]
00110 [6]
00101 [5]
00100 [4]
00011 [3]
00010 [2]
00001 [1]
00000 [0]
TMR6/PR6 match
TMR5 overflow
TMR4/PR4 match
TMR3 overflow
FOSC
• Data selection
• Data gating
• Logic function selection
• Output polarity
Each stage is setup at run time by writing to the
corresponding CLCx Special Function Registers. This
has the added advantage of permitting logic
reconfiguration on-the-fly during program execution.
HFINTOSC
LFINTOSC
ADCRC
IOCIF int flag bit
TMR2/PR2 match
TMR1 overflow
TMR0 overflow
EUSART1 (DT) output
EUSART1 (TX/CK) output
SDA2
21.1.1
DATA SELECTION
There are 36 signals available as inputs to the
configurable logic.
Data selection is through four multiplexers as indicated
on the left side of Figure 21-2. Data inputs in the figure
are identified by ‘LCx_in’ signal name.
Table 21-1 correlates the input number to the actual
signal for each CLC module. The column labeled
‘LCxDyS<5:0> Value’ indicates the MUX selection code
for the selected data input. LCxDyS is an abbreviation for
the MUX select input codes: LCxD1S<5:0> through
LCxD4S<5:0>.
SCL2
SDA1
SCL1
PWM6 output
PWM5 output
CCP4 output
CCP3 output
CCP2 output
CCP1 output
CLKR output
DSM output
C2 output
Data inputs are selected with CLCxSEL0 through
CLCxSEL3
registers
(Register 21-3
through
Register 21-6).
C1 output
CLC4 output
CLC3 output
CLC2 output
CLC1 output
CLCIN3PPS
CLCIN2PPS
CLCIN1PPS
CLCIN0PPS
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21.1.2
INPUT DATA SELECTION GATES
21.1.3
LOGIC FUNCTION
Outputs from the input multiplexers are directed to the
desired logic function input through the data gating
stage. Each data gate can direct any combination of the
four selected inputs.
There are eight available logic functions, including:
• AND-OR
• OR-XOR
• AND
The gate can be configured to direct each input signal
as inverted or non-inverted data. The output of each
gate can be inverted before going on to the logic func-
tion stage.
• S-R Latch
• D Flip-Flop with Set and Reset
• D Flip-Flop with Reset
• J-K Flip-Flop with Reset
• Transparent Latch with Set and Reset
The gating is in essence
a
1-to-4 input
AND/NAND/OR/NOR gate. When every input is
inverted and the output is inverted, the gate is an OR of
all enabled data inputs. When the inputs and output are
not inverted, the gate is an AND of all enabled inputs.
Logic functions are shown in Figure 21-3. Each logic
function has four inputs and one output. The four inputs
are the four data gate outputs of the previous stage.
The output is fed to the inversion stage and from there
to other peripherals, an output pin, and back to the
CLCx itself.
Table 21-2 summarizes the basic logic that can be
obtained in gate 1 by using the gate logic select bits
and gate polarity bits. The table shows the logic of four
input variables, but each gate can be configured to
use less than four. If no inputs are selected, the output
will be zero or one, depending on the gate output
polarity bit.
21.1.4
OUTPUT POLARITY
The last stage in the configurable logic cell is the output
polarity. Setting the LCxPOL bit of the CLCxPOL
register inverts the output signal from the logic stage.
Changing the polarity while the interrupts are enabled
will cause an interrupt for the resulting output transition.
TABLE 21-2: DATA GATING LOGIC
CLCxGLSy
LCxGyPOL
Gate Logic
0x55
0x55
0xAA
0xAA
0x00
0x00
1
0
1
0
0
1
4-input AND
4-input NAND
4-input NOR
4-input OR
Logic 0
Logic 1
It is possible (but not recommended) to select both the
true and negated values of an input. When this is done,
the gate output is zero, regardless of the other inputs,
but may emit logic glitches (transient-induced pulses).
If the output of the channel must be zero or one, the
recommended method is to set all gate bits to zero and
use the gate polarity bit to set the desired level.
Data gating is configured with the logic gate select
registers as follows:
• Gate 1: CLCxGLS0 (Register 21-7)
• Gate 2: CLCxGLS1 (Register 21-8)
• Gate 3: CLCxGLS2 (Register 21-9)
• Gate 4: CLCxGLS3 (Register 21-10)
Register number suffixes are different than the gate
numbers because other variations of this module have
multiple gate selections in the same register.
Data gating is indicated in the right side of Figure 21-2.
Only one gate is shown in detail. The remaining three
gates are configured identically with the exception that
the data enables correspond to the enables for that
gate.
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21.2 CLCx Interrupts
21.6 CLCx Setup Steps
An interrupt will be generated upon a change in the
output value of the CLCx when the appropriate interrupt
enables are set. A rising edge detector and a falling
edge detector are present in each CLC for this purpose.
The following steps will be followed when setting up the
CLCx:
• Disable CLCx by clearing the LCxEN bit.
• Select desired inputs using CLCxSEL0 through
CLCxSEL3 registers (See Table 21-1).
• Clear any associated ANSEL bits.
• Set all TRIS bits associated with external CLC
inputs.
• Enable the chosen inputs through the four gates
using CLCxGLS0, CLCxGLS1, CLCxGLS2, and
CLCxGLS3 registers.
The CLCxIF bit of the associated PIR3 register will be
set when either edge detector is triggered and its
associated enable bit is set. The LCxINTP bit enables
rising edge interrupts and the LCxINTN bit enables fall-
ing edge interrupts. Both are located in the CLCxCON
register.
To fully enable the interrupt, set the following bits:
• Select the gate output polarities with the
LCxGyPOL bits of the CLCxPOL register.
• Select the desired logic function with the
LCxMODE<2:0> bits of the CLCxCON register.
• Select the desired polarity of the logic output with
the LCxPOL bit of the CLCxPOL register. (This
step may be combined with the previous gate
output polarity step).
• CLCxIE bit of the PIE3 register
• LCxINTP bit of the CLCxCON register (for a rising
edge detection)
• LCxINTN bit of the CLCxCON register (for a
falling edge detection)
• PEIE and GIE bits of the INTCON register
The CLCxIF bit of the PIR3 register, must be cleared in
software as part of the interrupt service. If another edge
is detected while this flag is being cleared, the flag will
still be set at the end of the sequence.
• If driving a device pin, set the desired pin PPS
control register and also clear the TRIS bit
corresponding to that output.
• If interrupts are desired, configure the following
bits:
- Set the LCxINTP bit in the CLCxCON register
for rising event.
- Set the LCxINTN bit in the CLCxCON
register for falling event.
- Set the CLCxIE bit of the PIE3 register.
- Set the GIE and PEIE bits of the INTCON
register.
21.3 Output Mirror Copies
Mirror copies of all LCxCON output bits are contained
in the CLCDATA register. Reading this register
samples the outputs of all CLCs simultaneously. This
prevents any timing skew introduced by testing or
reading the LCxOUT bits in the individual CLCxCON
registers.
• Enable the CLCx by setting the LCxEN bit of the
CLCxCON register.
21.4 Effects of a Reset
The CLCxCON register is cleared to zero as the result
of a Reset. All other selection and gating values remain
unchanged.
21.5 Operation During Sleep
The CLC module operates independently from the
system clock and will continue to run during Sleep,
provided that the input sources selected remain active.
The HFINTOSC remains active during Sleep when the
CLC module is enabled and the HFINTOSC is
selected as an input source, regardless of the system
clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and as a CLC input
source, when the CLC is enabled, the CPU will go idle
during Sleep, but the CLC will continue to operate and
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.
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FIGURE 21-2:
INPUT DATA SELECTION AND GATING
Data Selection
LCx_in[0]
000000
Data GATE 1
lcxd1T
lcxd1N
LCxD1G1T
LCxD1G1N
LCxD2G1T
LCxD2G1N
LCxD3G1T
LCxD3G1N
LCxD4G1T
LCxD4G1N
100011
000000
LCx_in[35]
LCx_in[0]
LCxD1S<5:0>
lcxg1
LCxG1POL
lcxd2T
lcxd2N
100011
000000
LCx_in[35]
LCx_in[0]
LCxD2S<5:0>
LCxD3S<5:0>
LCxD4S<5:0>
Data GATE 2
lcxg2
lcxd3T
lcxd3N
(Same as Data GATE 1)
100011
000000
LCx_in[35]
LCx_in[0]
lcxg3
lcxg4
Data GATE 4
(Same as Data GATE 1)
lcxd4T
lcxd4N
LCx_in[35]
100011
Note:
All controls are undefined at power-up.
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FIGURE 21-3:
PROGRAMMABLE LOGIC FUNCTIONS
Rev. 10-000122A
7/30/2013
AND-OR
OR-XOR
lcxg1
lcxg2
lcxg1
lcxg2
lcxq
lcxq
lcxg3
lcxg4
lcxg3
lcxg4
LCxMODE<2:0> = 000
LCxMODE<2:0> = 001
4-input AND
S-R Latch
lcxg1
lcxg1
lcxq
S
R
Q
lcxg2
lcxg2
lcxg3
lcxq
lcxg3
lcxg4
lcxg4
LCxMODE<2:0> = 010
LCxMODE<2:0> = 011
1-Input D Flip-Flop with S and R
2-Input D Flip-Flop with R
lcxg4
lcxg4
lcxg2
S
D
Q
D
Q
lcxg2
lcxq
lcxq
lcxg1
lcxg3
lcxg1
R
R
lcxg3
LCxMODE<2:0> = 100
LCxMODE<2:0> = 101
J-K Flip-Flop with R
1-Input Transparent Latch with S and R
lcxg4
J
Q
lcxg2
lcxq
S
D
Q
lcxg2
lcxq
lcxg1
lcxg4
K
R
LE
lcxg3
lcxg1
R
lcxg3
LCxMODE<2:0> = 110
LCxMODE<2:0> = 111
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21.7 Register Definitions: CLC Control
REGISTER 21-1: CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER
R/W-0/0
LCxEN
U-0
—
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
LCxOUT
LCxINTP
LCxINTN
LCxMODE<2:0>
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
LCxEN: Configurable Logic Cell Enable bit
1= Configurable logic cell is enabled and mixing input signals
0= Configurable logic cell is disabled and has logic zero output
bit 6
bit 5
Unimplemented: Read as ‘0’
LCxOUT: Configurable Logic Cell Data Output bit
Read-only: logic cell output data, after LCPOL; sampled from CLCxOUT.
LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit
bit 4
1= CLCxIF will be set when a rising edge occurs on CLCxOUT
0= CLCxIF will not be set
bit 3
LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit
1= CLCxIF will be set when a falling edge occurs on CLCxOUT
0= CLCxIF will not be set
bit 2-0
LCxMODE<2:0>: Configurable Logic Cell Functional Mode bits
111= Cell is 1-input transparent latch with S and R
110= Cell is J-K flip-flop with R
101= Cell is 2-input D flip-flop with R
100= Cell is 1-input D flip-flop with S and R
011= Cell is S-R latch
010= Cell is 4-input AND
001= Cell is OR-XOR
000= Cell is AND-OR
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REGISTER 21-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER
R/W-0/0
LCxPOL
U-0
—
U-0
—
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG4POL LCxG3POL
LCxG2POL LCxG1POL
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
LCxPOL: CLCxOUT Output Polarity Control bit
1= The output of the logic cell is inverted
0= The output of the logic cell is not inverted
bit 6-4
bit 3
Unimplemented: Read as ‘0’
LCxG4POL: Gate 3 Output Polarity Control bit
1= The output of gate 3 is inverted when applied to the logic cell
0= The output of gate 3 is not inverted
bit 2
bit 1
bit 0
LCxG3POL: Gate 2 Output Polarity Control bit
1= The output of gate 2 is inverted when applied to the logic cell
0= The output of gate 2 is not inverted
LCxG2POL: Gate 1 Output Polarity Control bit
1= The output of gate 1 is inverted when applied to the logic cell
0= The output of gate 1 is not inverted
LCxG1POL: Gate 0 Output Polarity Control bit
1= The output of gate 0 is inverted when applied to the logic cell
0= The output of gate 0 is not inverted
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REGISTER 21-3: CLCxSEL0: GENERIC CLCx DATA 0 SELECT REGISTER
U-0
—
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxD1S<5:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
LCxD1S<5:0>: CLCx Data1 Input Selection bits
See Table 21-1.
REGISTER 21-4: CLCxSEL1: GENERIC CLCx DATA 1 SELECT REGISTER
U-0
—
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 0
LCxD2S<5:0>
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
LCxD2S<5:0>: CLCx Data 2 Input Selection bits
See Table 21-1.
REGISTER 21-5: CLCxSEL2: GENERIC CLCx DATA 2 SELECT REGISTER
U-0
—
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 0
LCxD3S<5:0>
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
LCxD3S<5:0>: CLCx Data 3 Input Selection bits
See Table 21-1.
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REGISTER 21-6: CLCxSEL3: GENERIC CLCx DATA 3 SELECT REGISTER
U-0
—
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxD4S<5:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
LCxD4S<5:0>: CLCx Data 4 Input Selection bits
See Table 21-1.
REGISTER 21-7: CLCxGLS0: GATE 0 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG1D4T
LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T
LCxG1D2N
LCxG1D1T LCxG1D1N
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LCxG1D4T: Gate 0 Data 4 True (non-inverted) bit
1= CLCIN3 (true) is gated into CLCx Gate 0
0= CLCIN3 (true) is not gated into CLCx Gate 0
LCxG1D4N: Gate 0 Data 4 Negated (inverted) bit
1= CLCIN3 (inverted) is gated into CLCx Gate 0
0= CLCIN3 (inverted) is not gated into CLCx Gate 0
LCxG1D3T: Gate 0 Data 3 True (non-inverted) bit
1= CLCIN2 (true) is gated into CLCx Gate 0
0= CLCIN2 (true) is not gated into CLCx Gate 0
LCxG1D3N: Gate 0 Data 3 Negated (inverted) bit
1= CLCIN2 (inverted) is gated into CLCx Gate 0
0= CLCIN2 (inverted) is not gated into CLCx Gate 0
LCxG1D2T: Gate 0 Data 2 True (non-inverted) bit
1= CLCIN1 (true) is gated into CLCx Gate 0
0= CLCIN1 (true) is not gated into CLCx Gate 0
LCxG1D2N: Gate 0 Data 2 Negated (inverted) bit
1= CLCIN1 (inverted) is gated into CLCx Gate 0
0= CLCIN1 (inverted) is not gated into CLCx Gate 0
LCxG1D1T: Gate 0 Data 1 True (non-inverted) bit
1= CLCIN0 (true) is gated into CLCx Gate 0
0= CLCIN0 (true) is not gated into CLCx Gate 0
LCxG1D1N: Gate 0 Data 1 Negated (inverted) bit
1= CLCIN0 (inverted) is gated into CLCx Gate 0
0= CLCIN0 (inverted) is not gated into CLCx Gate 0
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REGISTER 21-8: CLCxGLS1: GATE 1 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG2D4T
LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T
LCxG2D2N
LCxG2D1T LCxG2D1N
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LCxG2D4T: Gate 1 Data 4 True (non-inverted) bit
1= CLCIN3 (true) is gated into CLCx Gate 1
0= CLCIN3 (true) is not gated into CLCx Gate 1
LCxG2D4N: Gate 1 Data 4 Negated (inverted) bit
1= CLCIN3 (inverted) is gated into CLCx Gate 1
0= CLCIN3 (inverted) is not gated into CLCx Gate 1
LCxG2D3T: Gate 1 Data 3 True (non-inverted) bit
1= CLCIN2 (true) is gated into CLCx Gate 1
0= CLCIN2 (true) is not gated into CLCx Gate 1
LCxG2D3N: Gate 1 Data 3 Negated (inverted) bit
1= CLCIN2 (inverted) is gated into CLCx Gate 1
0= CLCIN2 (inverted) is not gated into CLCx Gate 1
LCxG2D2T: Gate 1 Data 2 True (non-inverted) bit
1= CLCIN1 (true) is gated into CLCx Gate 1
0= CLCIN1 (true) is not gated into CLCx Gate 1
LCxG2D2N: Gate 1 Data 2 Negated (inverted) bit
1= CLCIN1 (inverted) is gated into CLCx Gate 1
0= CLCIN1 (inverted) is not gated into CLCx Gate 1
LCxG2D1T: Gate 1 Data 1 True (non-inverted) bit
1= CLCIN0 (true) is gated into CLCx Gate 1
0= CLCIN0 (true) is not gated into CLCx Gate 1
LCxG2D1N: Gate 1 Data 1 Negated (inverted) bit
1= CLCIN0 (inverted) is gated into CLCx Gate 1
0= CLCIN0 (inverted) is not gated into CLCx Gate 1
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REGISTER 21-9: CLCxGLS2: GATE 2 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG3D4T
LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T
LCxG3D2N
LCxG3D1T LCxG3D1N
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LCxG3D4T: Gate 2 Data 4 True (non-inverted) bit
1= CLCIN3 (true) is gated into CLCx Gate 2
0= CLCIN3 (true) is not gated into CLCx Gate 2
LCxG3D4N: Gate 2 Data 4 Negated (inverted) bit
1= CLCIN3 (inverted) is gated into CLCx Gate 2
0= CLCIN3 (inverted) is not gated into CLCx Gate 2
LCxG3D3T: Gate 2 Data 3 True (non-inverted) bit
1= CLCIN2 (true) is gated into CLCx Gate 2
0= CLCIN2 (true) is not gated into CLCx Gate 2
LCxG3D3N: Gate 2 Data 3 Negated (inverted) bit
1= CLCIN2 (inverted) is gated into CLCx Gate 2
0= CLCIN2 (inverted) is not gated into CLCx Gate 2
LCxG3D2T: Gate 2 Data 2 True (non-inverted) bit
1= CLCIN1 (true) is gated into CLCx Gate 2
0= CLCIN1 (true) is not gated into CLCx Gate 2
LCxG3D2N: Gate 2 Data 2 Negated (inverted) bit
1= CLCIN1 (inverted) is gated into CLCx Gate 2
0= CLCIN1 (inverted) is not gated into CLCx Gate 2
LCxG3D1T: Gate 2 Data 1 True (non-inverted) bit
1= CLCIN0 (true) is gated into CLCx Gate 2
0= CLCIN0 (true) is not gated into CLCx Gate 2
LCxG3D1N: Gate 2 Data 1 Negated (inverted) bit
1= CLCIN0 (inverted) is gated into CLCx Gate 2
0= CLCIN0 (inverted) is not gated into CLCx Gate 2
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REGISTER 21-10: CLCxGLS3: GATE 3 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG4D4T
LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T
LCxG4D2N
LCxG4D1T LCxG4D1N
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LCxG4D4T: Gate 3 Data 4 True (non-inverted) bit
1= CLCIN3 (true) is gated into CLCx Gate 3
0= CLCIN3 (true) is not gated into CLCx Gate 3
LCxG4D4N: Gate 3 Data 4 Negated (inverted) bit
1= CLCIN3 (inverted) is gated into CLCx Gate 3
0= CLCIN3 (inverted) is not gated into CLCx Gate 3
LCxG4D3T: Gate 3 Data 3 True (non-inverted) bit
1= CLCIN2 (true) is gated into CLCx Gate 3
0= CLCIN2 (true) is not gated into CLCx Gate 3
LCxG4D3N: Gate 3 Data 3 Negated (inverted) bit
1= CLCIN2 (inverted) is gated into CLCx Gate 3
0= CLCIN2 (inverted) is not gated into CLCx Gate 3
LCxG4D2T: Gate 3 Data 2 True (non-inverted) bit
1= CLCIN1 (true) is gated into CLCx Gate 3
0= CLCIN1 (true) is not gated into CLCx Gate 3
LCxG4D2N: Gate 3 Data 2 Negated (inverted) bit
1= CLCIN1 (inverted) is gated into CLCx Gate 3
0= CLCIN1 (inverted) is not gated into CLCx Gate 3
LCxG4D1T: Gate 3 Data 1 True (non-inverted) bit
1= CLCIN0 (true) is gated into CLCx Gate 3
0= CLCIN0 (true) is not gated into CLCx Gate 3
LCxG4D1N: Gate 3 Data 1 Negated (inverted) bit
1= CLCIN0 (inverted) is gated into CLCx Gate 3
0= CLCIN0 (inverted) is not gated into CLCx Gate 3
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REGISTER 21-11: CLCDATA: CLC DATA OUTPUT
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
MLC4OUT
MLC3OUT
MLC2OUT
MLC1OUT
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
MLC4OUT: Mirror copy of LC4OUT bit
MLC3OUT: Mirror copy of LC3OUT bit
MLC2OUT: Mirror copy of LC2OUT bit
MLC1OUT: Mirror copy of LC1OUT bit
TABLE 21-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx
Register
on Page
Name
Bit7
Bit6
Bit5
Bit4
BIt3
Bit2
Bit1
Bit0
ANSELA
―
―
―
―
ANSA5
TRISA5
ANSB5
TRISB5
ANSC5
TRISC5
―
ANSA4
TRISA4
ANSB4
TRISB4
ANSC4
TRISC4
―
―
ANSA2
TRISA2
―
ANSA1
TRISA1
―
ANSA0
TRISA0
―
144
143
150
149
157
155
100
109
104
227
228
229
229
229
230
230
231
232
233
227
228
229
229
229
230
(2)
TRISA
―
ANSELB(1)
TRISB(1)
ANSB7
TRISB7
ANSC7(1)
TRISC7(1)
GIE
ANSB6
TRISB6
ANSC6(1)
TRISC6(1)
PEIE
CSWIF
CSWIE
―
―
―
―
―
―
ANSELC
ANSC3
TRISC3
―
ANSC2
TRISC2
―
ANSC1
TRISC1
―
ANSC0
TRISC0
INTEDG
CLC1IF
CLC1IE
TRISC
INTCON
PIR3
OSFIF
OSFIE
LC1EN
LC1POL
―
TMR3GIF
TMR3GIE
LC1OUT
―
TMR3IF
TMR3IE
LC1INTP
―
CLC4IF
CLC4IE
LC1INTN
CLC3IF
CLC3IE
CLC2IF
CLC2IE
LC1MODE<2:0>
PIE3
CLC1CON
CLC1POL
CLC1SEL0
CLC1SEL1
CLC1SEL2
CLC1SEL3
CLC1GLS0
CLC1GLS1
CLC1GLS2
CLC1GLS3
CLC2CON
CLC2POL
CLC2SEL0
CLC2SEL1
CLC2SEL2
CLC2SEL3
―
LC1G4POL LC1G3POL LC1G2POL LC1G1POL
―
LC1D1S<5:0>
LC1D2S<5:0>
LC1D3S<5:0>
LC1D4S<5:0>
―
―
―
―
―
―
LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N
LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N
LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N
LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N
LC2EN
―
―
―
―
―
―
LC2OUT
LC2INTP
LC2INTN
LC2MODE<2:0>
LC2POL
―
―
LC2G4POL LC2G3POL LC2G2POL LC2G1POL
―
―
―
―
LC2D1S<5:0>
LC2D2S<5:0>
LC2D3S<5:0>
LC2D4S<5:0>
DS40001839B-page 234
Preliminary
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PIC16(L)F18326/18346
TABLE 21-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx (CONTINUED)
Register
on Page
Name
Bit7
Bit6
Bit5
Bit4
BIt3
Bit2
Bit1
Bit0
CLC2GLS0
CLC2GLS1
CLC2GLS2
CLC2GLS3
CLC3CON
CLC3POL
LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N
LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N
LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N
LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N
230
231
232
233
227
228
229
229
229
230
230
231
232
233
227
228
229
229
229
230
230
231
232
233
234
162
162
162
162
162
162
162
162
LC3EN
―
―
―
―
―
―
LC3OUT
LC3INTP
LC3INTN
LC3MODE<2:0>
LC3POL
―
―
LC3G4POL LC3G3POL LC3G2POL LC3G1POL
CLC3SEL0
CLC3SEL1
CLC3SEL2
CLC3SEL3
CLC3GLS0
CLC3GLS1
CLC3GLS2
CLC3GLS3
CLC4CON
CLC4POL
―
―
―
―
LC3D1S<5:0>
LC3D2S<5:0>
LC3D3S<5:0>
LC3D4S<5:0>
LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N
LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N
LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N
LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N
LC4EN
―
―
―
―
―
―
LC4OUT
LC4INTP
LC4INTN
LC4MODE<2:0>
LC4POL
―
―
LC4G4POL LC4G3POL LC4G2POL LC4G1POL
CLC4SEL0
CLC4SEL1
CLC4SEL2
CLC4SEL3
CLC4GLS0
CLC4GLS1
CLC4GLS2
CLC4GLS3
CLCDATA
―
―
―
―
LC4D1S<5:0>
LC4D2S<5:0>
LC4D3S<5:0>
LC4D4S<5:0>
LC4G1D4T LC4G1D4N LC4G1D3T LC4G1D3N LC4G1D2T LC4G1D2N LC4G1D1T LC4G1D1N
LC4G2D4T LC4G2D4N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N
LC4G3D4T LC4G3D4N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N
LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
MLC4OUT MLC3OUT MLC2OUT MLC1OUT
CLCIN0PPS<4:0>
CLCIN0PPS
CLCIN1PPS
CLCIN2PPS
CLCIN3PPS
CLC1OUTPPS
CLC2OUTPPS
CLC3OUTPPS
CLC4OUTPPS
CLCIN1PPS<4:0>
CLCIN2PPS<4:0>
CLCIN3PPS<4:0>
CLC1OUTPPS<4:0>
CLC2OUTPPS<4:0>
CLC3OUTPPS<4:0>
CLC4OUTPPS<4:0>
Legend:
— = unimplemented, read as ‘0’. Shaded cells are unused by the CLC module.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 235
PIC16(L)F18326/18346
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
22.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESH:ADRESL register pair).
Figure 22-1 shows the block diagram of the ADC.
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
FIGURE 22-1:
ADC BLOCK DIAGRAM
Rev. 10-000033E
VDD
ADPREF<1:0>
6/11/2015
Positive
Reference
Select
VDD
RESERVED
VREF+ pin
ADNREF
FVR BUFFER
Negative
Reference
Select
VREF- pin
ADCS<2:0>
VSS
AN0
ANa
ANb
VRNEG VRPOS
External
Channel
Inputs
Fosc
FOSC/n
FOSC
FRC
Divider
ADC
Clock
Select
ADC_clk
sampled
input
FRC
ANz
Temp Indicator
DACx_output
FVR_buffer1
Internal
Channel
Inputs
ADC CLOCK SOURCE
ADFM
ADC
Sample Circuit
CHS<4:0>
set bit ADIF
10
complete
start
10-bit Result
16
Write to bit
GO/DONE
GO/DONE
Q1
Q4
ADRESH
ADRESL
Q2
Enable
Trigger Select
TRIGSEL<5:0>
ADON
. . .
VSS
Trigger Sources
AUTO CONVERSION
TRIGGER
DS40001839B-page 236
Preliminary
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22.1.3
ADC VOLTAGE REFERENCE
22.1 ADC Configuration
The ADPREF<1:0> bits of the ADCON1 register
provides control of the positive voltage reference. The
positive voltage reference can be:
When configuring and using the ADC the following
functions must be considered:
• Port configuration
• Channel selection
• ADC voltage reference selection
• ADC conversion clock source
• Interrupt control
• VREF+ pin
• VDD
• FVR 2.048V
• FVR 4.096V (Not available on LF devices)
• Result formatting
The ADNREF bit of the ADCON1 register provides
control of the negative voltage reference. The negative
voltage reference can be:
22.1.1
PORT CONFIGURATION
The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin will be configured for analog by setting the
associated TRIS and ANSEL bits. Refer to
Section 12.0 “I/O Ports” for more information.
• VREF- pin
• VSS
See Section 22.0 “Analog-to-Digital Converter
(ADC) Module” for more details on the Fixed Voltage
Reference.
Note:
Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
22.1.4
CONVERSION CLOCK
The source of the conversion clock is software
selectable via the ADCS<2:0> bits of the ADCON1
register. There are seven possible clock options:
22.1.2
CHANNEL SELECTION
There are several channel selections available:
• FOSC/2
• FOSC/4
• FOSC/8
• FOSC/16
• FOSC/32
• FOSC/64
• ADCRC (dedicated RC oscillator)
• Five PORTA pins (RA0-RA2, RA4-RA5)
• Four PORTB pins (RB4-RB7, PIC16(L)F18346
only)
• Six PORTC pins (RC0-RC5, PIC16(L)F18326)
• Eight PORTC pins (RC0-RC7, PIC16(L)F18346
only)
• Temperature Indicator
• DAC output
• Fixed Voltage Reference (FVR)
• VSS (ground)
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 12 TAD periods
as shown in Figure 22-2.
For correct conversion, the appropriate TAD specification
must be met. Refer to Table 35-13 for more information.
Table 22-1 gives examples of appropriate ADC clock
selections.
The CHS<5:0> bits of the ADCON0 register
(Register 22-1) determine which channel is connected
to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 22.2
“ADC Operation” for more information.
Note:
Unless using the ADCRC, any changes in
the system clock frequency will change
the ADC clock frequency, which may
adversely affect the ADC result.
Note:
It is recommended that when switching
from an ADC channel of a higher voltage
to a channel of a lower voltage, that the
user selects the Vss channel before
connecting to the channel with the lower
voltage. If the ADC does not have a
dedicated VSS input channel, the VSS
selection (DAC1R<4:0> = b'00000')
through the DAC output channel can be
used. If the DAC is in use, a free input
channel can be connected to Vss, and can
be used in place of the DAC.
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TABLE 22-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD)
Device Frequency (FOSC)
ADC
ADCS<2:0>
Clock Source
32 MHz
20 MHz
16 MHz 8 MHz
4 MHz
1 MHz
(2)
(2)
(2)
(2)
(2)
FOSC/2
FOSC/4
000
100
001
101
010
110
x11
62.5ns
125 ns
0.5 s
100 ns
200 ns
400 ns
125 ns
250 ns
250 ns
500 ns
500 ns
1.0 s
2.0 s
4.0 s
2.0 s
4.0 s
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
FOSC/8
0.5 s
1.0 s
2.0 s
4.0 s
8.0 s
16.0 s
32.0 s
64.0 s
(3)
FOSC/16
FOSC/32
FOSC/64
ADCRC
800 ns
1.0 s
800 ns
1.6 s
3.2 s
1.0 s
2.0 s
(3)
(2)
8.0 s
(3)
(2)
(2)
2.0 s
4.0 s
8.0 s
16.0 s
(1,4)
(1,4)
(1,4)
(1,4)
(1,4)
(1,4)
1.0-6.0 s
1.0-6.0 s
1.0-6.0 s
1.0-6.0 s
1.0-6.0 s
1.0-6.0 s
Legend: Shaded cells are outside of recommended range.
Note 1: See TAD parameter for ADCRC source typical TAD value.
2: These values violate the required TAD time.
3: Outside the recommended TAD time.
4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived
from the system clock FOSC. However, the ADCRC oscillator source must be used when conversions are to be
performed with the device in Sleep mode.
FIGURE 22-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TAD1
TAD2
TAD3
TAD4
TAD5
TAD6
TAD7
TAD8
b3
TAD9
b2
TAD10
b1
TAD11
b0
b9
b8
b7
b6
b5
b4
THCD
Conversion Starts
TACQ
On the following cycle:
Holding capacitor disconnected
from analog input (THCD).
ADRESH:ADRESL is loaded,
GO bit is cleared,
Set GO bit
ADIF bit is set,
holding capacitor is reconnected to analog input.
Enable ADC (ADON bit)
and
Select channel (ACS bits)
DS40001839B-page 238
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PIC16(L)F18326/18346
22.1.5
INTERRUPTS
22.1.6
RESULT FORMATTING
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
The 10-bit ADC conversion result can be supplied in
two formats, left justified or right justified. The ADFM bit
of the ADCON1 register controls the output format.
Figure 22-3 shows the two output formats.
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the ADCRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the ADIE bit of the PIE1 register and the
PEIE bit of the INTCON register must both be set and
the GIE bit of the INTCON register must be cleared. If
all three of these bits are set, the execution will switch
to the Interrupt Service Routine (ISR).
FIGURE 22-3:
10-BIT ADC CONVERSION RESULT FORMAT
ADRESH
ADRESL
LSB
(ADFM = 0)
MSB
bit 7
bit 0
bit 0
bit 7
bit 7
bit 0
10-bit ADC Result
Unimplemented: Read as ‘0’
(ADFM = 1)
MSB
LSB
bit 0
bit 7
Unimplemented: Read as ‘0’
10-bit ADC Result
2016-2017 Microchip Technology Inc.
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22.2.3
ADC OPERATION DURING SLEEP
22.2 ADC Operation
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the ADCRC
option. When the ADCRC oscillator source is selected,
the ADC waits one additional instruction before starting
the conversion. This allows the SLEEPinstruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
22.2.1
STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the
GO/DONE bit of the ADCON0 register to a ‘1’ will start
the Analog-to-Digital conversion.
Note:
The GO/DONE bit will not be set in the
same instruction that turns on the ADC.
Refer to Section 22.2.5 “ADC Conver-
sion Procedure”.
When the ADC clock source is something other than
ADCRC, a SLEEP instruction causes the present
conversion to be aborted and the ADC module is
turned off, although the ADON bit remains set.
22.2.2
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF Interrupt Flag bit
• Update the ADRESH and ADRESL registers with
new conversion result
22.2.4
AUTO-CONVERSION TRIGGER
The Auto-conversion Trigger allows periodic ADC
measurements without software intervention. When a
rising edge of the selected source occurs, the
GO/DONE bit is set by hardware.
Note:
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
The Auto-conversion Trigger source is selected with
the ADACT<4:0> bits of the ADACT register.
See Table 22-2 for auto-conversion sources.
TABLE 22-2:
ADC AUTO-CONVERSION
TABLE
Source
Peripheral
Description
TMR0
TMR1
TMR3
TMR5
TMR2
TMR4
TMR6
C1
Timer0 Overflow condition
Timer1 Overflow condition
Timer3 Overflow condition
Timer5 Overflow condition
Match between Timer2 and PR2
Match between Timer4 and PR4
Match between Timer6 and PR6
Comparator C1 output
Comparator C2 output
CLC1 output
C2
CLC1
CLC2
CLC3
CLC4
CCP1
CCP2
CCP3
CCP4
CLC2 output
CLC3 output
CLC4 output
CCP1 output
CCP2 output
CCP3 output
CCP4 output
DS40001839B-page 240
Preliminary
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PIC16(L)F18326/18346
22.2.5
ADC CONVERSION PROCEDURE
EXAMPLE 22-1:
ADC CONVERSION
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
;This code block configures the ADC
;for polling, Vdd and Vss references, ADCRC
;oscillator and AN0 input.
1. Configure Port:
;
;Conversion start & polling for completion ;
are included.
;
• Disable pin output driver (Refer to the TRIS
register)
BANKSEL
MOVLW
ADCON1
B’11110000’
;
• Configure pin as analog (Refer to the ANSEL
register)
;Right justify, ADCRC
;oscillator
MOVWF
BANKSEL
BSF
BANKSEL
BSF
BANKSEL
MOVLW
MOVWF
CALL
BSF
BTFSC
GOTO
BANKSEL
MOVF
MOVWF
BANKSEL
MOVF
ADCON1
TRISA
TRISA,0
ANSELA
ANSELA,0
ADCON0
B’00000001’
ADCON0
SampleTime
ADCON0,ADGO
ADCON0,ADGO
$-1
;Vdd and Vss Vref
;
;Set RA0 to input
;
;Set RA0 to analog
;
;Select channel AN0
;Turn ADC On
;Acquisiton delay
;Start conversion
;Is conversion done?
;No, test again
;
;Read upper 2 bits
;store in GPR space
;
2. Configure the ADC module:
• Select ADC conversion clock
• Select voltage reference
• Select ADC input channel
• Turn on ADC module
3. Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
ADRESH
• Enable peripheral interrupt
• Enable global interrupt(1)
4. Wait the required acquisition time(2)
ADRESH,W
RESULTHI
ADRESL
ADRESL,W
RESULTLO
.
;Read lower 8 bits
;Store in GPR space
MOVWF
5. Start conversion by setting the GO/DONE bit.
6. Wait for ADC conversion to complete by one of
the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt
7. Read ADC Result.
8. Clear the ADC interrupt flag (required if interrupt
is enabled).
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 22.3 “ADC Acquisi-
tion Requirements”.
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As the source impedance is decreased, the acquisition
time may be decreased. After the analog input channel
is selected (or changed), an ADC acquisition must be
done before the conversion can be started. To calculate
the minimum acquisition time, Equation 22-1 may be
used. This equation assumes that 1/2 LSb error is used
(1,024 steps for the ADC). The 1/2 LSb error is the
maximum error allowed for the ADC to meet its
specified resolution.
22.3 ADC Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 22-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), refer
to Figure 22-4. The maximum recommended
impedance for analog sources is 10 k.
EQUATION 22-1: ACQUISITION TIME EXAMPLE
Temperature = 50°C and external impedance of 10k 5.0V VDD
Assumptions:
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
= 2µs + TC + Temperature - 25°C0.05µs/°C
The value for TC can be approximated with the following equations:
1
;[1] VCHOLD charged to within 1/2 lsb
VAPPLIED1 – -------------------------- = VCHOLD
2n + 1 – 1
–TC
---------
RC
VAPPLIED 1 – e
= VCHOLD
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
–Tc
--------
RC
1
= VAPPLIED1 – --------------------------
2n + 1 – 1
VAPPLIED 1 – e
Note: Where n = number of bits of the ADC.
Solving for TC:
TC = –CHOLDRIC + RSS + RS ln(1/2047)
= –10pF1k + 7k + 10k ln(0.0004885)
= 1.37µs
Therefore:
TACQ = 2µs + 892ns + 50°C- 25°C0.05µs/°C
= 4.62µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
DS40001839B-page 242
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
FIGURE 22-4:
ANALOG INPUT MODEL
VDD
Analog
Input
pin
Sampling
Switch
VT 0.6V
SS
RIC 1k
Rss
Rs
(1)
CPIN
5 pF
VA
I LEAKAGE
CHOLD = 10 pF
Ref-
VT 0.6V
6V
5V
RSS
VDD 4V
3V
Legend:
CHOLD
CPIN
= Sample/Hold Capacitance
= Input Capacitance
2V
I LEAKAGE = Leakage current at the pin due to
various junctions
5 6 7 8 9 1011
Sampling Switch
RIC
RSS
SS
VT
= Interconnect Resistance
= Resistance of Sampling Switch
= Sampling Switch
(k)
= Threshold Voltage
Rs
= External series resistance
Note 1: Refer to Table 35-4 (parameter D060).
FIGURE 22-5:
ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
3FBh
03h
02h
01h
00h
Analog Input Voltage
1.5 LSB
0.5 LSB
Zero-Scale
Transition
Ref-
Full-Scale
Transition
Ref+
2016-2017 Microchip Technology Inc.
Preliminary
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PIC16(L)F18326/18346
22.4 Register Definitions: ADC Control
REGISTER 22-1: ADCON0: ADC CONTROL REGISTER 0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ADON
CHS<5:0>
GO/DONE
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
CHS<5:0>: Analog Channel Select bits
111111= FVR (Fixed Voltage Reference)(2)
111110= DAC1 output(1)
111101= Temperature Indicator(3)
111100= VSS
111011= Reserved. No channel connected.
•
•
•
010111= ANC7(4)
010110= ANC6(4)
010101= ANC5
010100= ANC4
010011= ANC3
010010= ANC2
010001= ANC1
010000= ANC0
001111= ANB7(4)
001110= ANB6(4)
001101= ANB5(4)
001100= ANB4(4)
001011= Reserved. No channel connected.
•
•
•
000101= ANA5
000100= ANA4
000011= Reserved. No channel connected.
000010= ANA2
000001= ANA1
000000= ANA0
bit 1
bit 0
GO/DONE: ADC Conversion Status bit
1= ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle.
This bit is automatically cleared by hardware when the ADC conversion has completed.
0= ADC conversion completed/not in progress
ADON: ADC Enable bit
1= ADC is enabled
0= ADC is disabled and consumes no operating current
Note 1: See Section 24.0 “5-bit Digital-to-Analog Converter (DAC1) Module” for more information.
2: See Section 16.0 “Fixed Voltage Reference (FVR)” for more information.
3: See Section 17.0 “Temperature Indicator Module” for more information.
4: PIC16(L)F18346 only.
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2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
REGISTER 22-2: ADCON1: ADC CONTROL REGISTER 1
R/W-0/0
ADFM
R/W-0/0
R/W-0/0
R/W-0/0
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
ADCS<2:0>
ADNREF
ADPREF<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
ADFM: ADC Result Format Select bit
1= Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is
loaded.
0= Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is
loaded.
bit 6-4
ADCS<2:0>: ADC Conversion Clock Select bits
111= ADCRC (dedicated RC oscillator)
110= FOSC/64
101= FOSC/16
100= FOSC/4
011= ADCRC (dedicated RC oscillator)
010= FOSC/32
001= FOSC/8
000= FOSC/2
bit 3
bit 2
Unimplemented: Read as ‘0’
ADNREF: A/D Negative Voltage Reference Configuration bit
When ADON = 0, all multiplexer inputs are disconnected.
0= VREF- is connected to AVSS
1= VREF- is connected to external VREF-
bit 1-0
ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits
11= VREF+ is connected to internal Fixed Voltage Reference (FVR) module(1)
10= VREF+ is connected to external VREF+ pin(1)
01= Reserved
00= VREF+ is connected to VDD
Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage
specification exists. See Table 35-13 for details.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 245
PIC16(L)F18326/18346
REGISTER 22-3: ADACT: A/D AUTO-CONVERSION TRIGGER
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ADACT<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
ADACT<4:0>: Auto-Conversion Trigger Selection bits(1)
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
CCP4
CCP3
CCP2
CCP1
CLC4
CLC3
CLC2
CLC1
Comparator C2
Comparator C1
Timer2-PR2 match
Timer1 overflow(2)
Timer0 overflow(2)
Timer6-PR6 match
Timer4-PR4 match
No auto-conversion trigger selected
10000 = Timer3 overflow(2)
10001 = Timer5 overflow(2)
Note 1: This is a rising edge sensitive input for all sources.
2: Trigger corresponds to when the peripheral’s interrupt flag is set.
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PIC16(L)F18326/18346
REGISTER 22-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<9:2>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
ADRES<9:2>: ADC Result Register bits
Upper eight bits of 10-bit conversion result
REGISTER 22-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x/u
R/W-x/u
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
ADRES<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
ADRES<1:0>: ADC Result Register bits
Lower two bits of 10-bit conversion result
Reserved: Do not use.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 247
PIC16(L)F18326/18346
REGISTER 22-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
R/W-x/u
ADRES<9:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-2
bit 1-0
Reserved: Do not use.
ADRES<9:8>: ADC Result Register bits
Upper two bits of 10-bit conversion result
REGISTER 22-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 0
ADRES<7:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
ADRES<7:0>: ADC Result Register bits
Lower eight bits of 10-bit conversion result
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PIC16(L)F18326/18346
TABLE 22-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
TMR1GIE
TMR1GIF
—
PEIE
—
—
—
—
—
INTEDG
100
102
107
143
149
155
144
150
157
244
245
246
PIE1
ADIE
ADIF
—
RCIE
RCIF
TXIE
TXIF
SSP1IE BCL1IE
TMR2IE
TMR2IF
TRISA1
—
TMR1IE
TMR1IF
TRISA0
—
PIR1
SSP1IF BCL1IF
(2)
TRISA
TRISB(1)
TRISA5 TRISA4
—
TRISA2
TRISB7
TRISB6
TRISB5 TRISB4
—
—
TRISC
TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2
TRISC1
ANSA1
—
TRISC0
ANSA0
—
ANSELA
ANSELB(1)
ANSELC
—
—
ANSA5
ANSA4
ANSB4
ANSC4
—
—
ANSA2
—
ANSB7
ANSB6
ANSB5
ANSC7(1) ANSC6(1) ANSC5
ANSC3
ANSC2
ANSC1
ANSC0
ADCON0
ADCON1
ADACT
CHS<5:0>
ADCS<2:0>
GO/DONE
ADON
ADFM
—
—
ADNREF
ADPREF<1:0>
ADACT<4:0>
—
—
ADRESH
ADRESH<7:0>
ADRESL<7:0>
247
247
180
264
91
ADRESL
FVRCON
FVREN
—
FVRRDY
—
TSEN
—
TSRNG
CDAFVR<1:0>
ADFVR<1:0>
— PLLR
DAC1CON1
OSCSTAT1
DAC1R<4:0>
ADOR
EXTOR
HFOR
—
LFOR
SOR
Legend: —= unimplemented read as ‘0’. Shaded cells are not used for the ADC module.
Note 1: PIC16(L)F18346 only.
2: Unimplemented, read as ‘1’.
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23.0 NUMERICALLY CONTROLLED
OSCILLATOR (NCO1) MODULE
The Numerically Controlled Oscillator (NCO1) module
is a timer that uses the overflow from the addition of an
increment value to divide the input frequency. The
advantage of the addition method over simple
counter-driven timer is that the output frequency
resolution does not vary with the divider value. The
NCO1 is most useful for applications that require
frequency accuracy and fine resolution at a fixed duty
cycle.
Features of the NCO1 include:
• 20-bit increment function
• Fixed Duty Cycle (FDC) mode
• Pulse Frequency (PF) mode
• Output pulse-width control
• Multiple clock input sources
• Output polarity control
• Interrupt capability
Figure 23-1 is a simplified block diagram of the NCO1
module.
DS40001839B-page 250
Preliminary
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FIGURE 23-1:
NUMERICALLY CONTROLLED OSCILLATOR MODULE SIMPLIFIED BLOCK DIAGRAM
1&2ꢀINCU
1&2ꢀINCH
1&2ꢀINCL
INCBUFU(1)
INCBUFH(1)
INCBUFL(1)
1&2ꢀIF
1&2BLnterrupt
Adder
00
01
10
11
HFINTOSC
Peripherals
D
Q
Q
FOSC
Overflow
1&2ꢀACCU
1&2ꢀACCH
1&2ꢀACCL
LC1BRXW
1&2ꢀBRXW bit
1&2PPS
5HVHUYHG
1ꢀEN
0
1
1&2ꢀBFON
1ꢀCKS<1:0>
Overflow
S
R
Q
Q
1&2ꢀPOL
1ꢀ3)0
1ꢀPWS<2:0>
1&2ꢀBFON
Reset
Ripple Counter
Note 1: The increment registers are double-buffered to allow for value changes to be made without first disabling the NCO1 module. They are shown for
reference only and are not user accessible.
PIC16(L)F18326/18346
23.1 NCO1 Operation
The NCO1 operates by repeatedly adding a fixed value
to an accumulator. Additions occur at the input clock
rate. The accumulator will overflow with a carry
periodically, which is the raw NCO1 output
(NCO_overflow). This effectively reduces the input
clock by the ratio of the addition value to the maximum
accumulator value. See Equation 23-1.
The NCO1 output can be further modified by stretching
the pulse or toggling a flip-flop. The modified NCO1
output is then distributed internally to other peripherals
and can optionally be output to a pin. The accumulator
overflow also generates an interrupt (NCO_interrupt).
The NCO1 period changes in discrete steps to create
an average frequency.
EQUATION 23-1: NCO1 OPERATION
NCO1 Clock Frequency Increment Value
FOVERFLOW= -------------------------------------------------------------------------------------------------------------------
20
2
23.1.1
NCO1 CLOCK SOURCES
23.1.4
INCREMENT REGISTERS
Clock sources available to the NCO1 include:
The increment value is stored in three registers making
up a 20-bit increment. In order of LSB to MSB they are:
• HFINTOSC
• FOSC
• LC1_out
• NCO1INCL
• NCO1INCH
• NCO1INCU
The NCO1 clock source is selected by configuring the
N1CKS<1:0> bits in the NCO1CLK register.
When the NCO1 module is enabled, the NCO1INCU
and NCO1INCH registers should be written first, then
the NCO1INCL register. Writing to the NCO1INCL
register initiates the increment buffer registers to be
loaded simultaneously on the second rising edge of the
NCO_clk signal.
23.1.2
ACCUMULATOR
The accumulator is a 20-bit register. Read and write
access to the accumulator is available through three
registers:
The registers are readable and writable. The increment
registers are double-buffered to allow value changes to
be made without first disabling the NCO1 module.
• NCO1ACCL
• NCO1ACCH
• NCO1ACCU
When the NCO1 module is disabled, the increment
buffers are loaded immediately after a write to the
increment registers.
23.1.3
ADDER
The NCO1 adder is a full adder, which operates
independently from the system clock. The addition of
the previous result and the increment value replaces
the accumulator value on the rising edge of each input
clock.
Note:
The increment buffer registers are not
user-accessible.
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23.2 Fixed Duty Cycle (FDC) Mode
23.4 Output Polarity Control
In Fixed Duty Cycle (FDC) mode, every time the
accumulator overflows (NCO_overflow), the output is
toggled. This provides a 50% duty cycle with a constant
frequency, provided that the increment value remains
constant.
The last stage in the NCO1 module is the output
polarity. The N1POL bit in the NCO1CON register
selects the output polarity. Changing the polarity while
the interrupts are enabled will cause an interrupt for the
resulting output transition.
The FDC frequency can be calculated using
Equation 23-2.The FDC frequency is half of the
overflow frequency since it takes two overflow events
to generate one FDC clock period. For more
information, see Figure 23-2.
The NCO1 output can be used internally by source
code or other peripherals. Accomplish this by reading
the N1OUT (read-only) bit of the NCO1CON register.
The NCO1 output signal is available to the following
peripherals:
• CWG
EQUATION 23-2: FDC FREQUENCY
F
= F
2
fdc
overflow
The FDC mode is selected by clearing the N1PFM bit
in the NCO1CON register.
23.3 Pulse Frequency (PF) Mode
In Pulse Frequency (PF) mode, every time the
accumulator overflows (NCO_overflow), the output
becomes active for one or more clock periods. Once
the clock period expires, the output returns to an
inactive state. This provides a pulsed output. The
output becomes active on the rising clock edge
immediately following the overflow event. For more
information, see Figure 23-2.
The value of the active and inactive states depends on
the polarity bit, N1POL, in the NCO1CON register.
The PF mode is selected by setting the N1PFM bit in
the NCO1CON register.
23.3.1
OUTPUT PULSE-WIDTH CONTROL
When operating in PF mode, the active state of the
output can vary in width by multiple clock periods.
Various pulse widths are selected with the
N1PWS<2:0> bits in the NCO1CLK register.
When the selected pulse width is greater than the
accumulator overflow time frame, the output of the
NCO1 does not toggle.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 253
FIGURE 23-2:
FDC OUTPUT MODE OPERATION DIAGRAM
Rev. 10-000029A
11/7/2013
NCOx
Clock
Source
NCOx
Increment
Value
4000h
4000h
4000h
NCOx
Accumulator
Value
00000h 04000h 08000h
FC000h 00000h 04000h 08000h
FC000h 00000h 04000h 08000h
NCO_overflow
NCO_interrupt
NCOx Output
FDC Mode
NCOx Output
PF Mode
NCOxPWS =
000
NCOx Output
PF Mode
NCOxPWS =
PIC16(L)F18326/18346
23.5 Interrupts
When the accumulator overflows (NCO_overflow), the
NCO1 Interrupt Flag bit, NCO1IF, of the PIR2 register
is set. To enable the interrupt event (NCO_interrupt),
the following bits must be set:
• N1EN bit of the NCO1CON register
• NCO1IE bit of the PIE2 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
The interrupt must be cleared by software by clearing
the NCO1IF bit in the Interrupt Service Routine.
23.6 Effects of a Reset
All of the NCO1 registers are cleared to zero as the
result of a Reset.
23.7 Operation in Sleep
The NCO1 module operates independently from the
system clock and will continue to run during Sleep,
provided that the clock source selected remains active.
The HFINTOSC remains active during Sleep when the
NCO1 module is enabled and the HFINTOSC is
selected as the clock source, regardless of the system
clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and the NCO1 clock
source, when the NCO1 is enabled, the CPU will go
idle during Sleep, but the NCO1 will continue to operate
and the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.
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PIC16(L)F18326/18346
23.8 NCO1 Control Registers
REGISTER 23-1: NCO1CON: NCO1 CONTROL REGISTER
R/W-0/0
N1EN
U-0
—
R-0/0
R/W-0/0
N1POL
U-0
—
U-0
—
U-0
—
R/W-0/0
N1PFM
N1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
N1EN: NCO1 Enable bit
1= NCO1 module is enabled
0= NCO1 module is disabled
bit 6
bit 5
Unimplemented: Read as ‘0’
N1OUT: NCO1 Output bit
Displays the current output value of the NCO1 module
bit 4
N1POL: NCO1 Polarity bit
1= NCO1 output signal is inverted
0= NCO1 output signal is not inverted
bit 3-1
bit 0
Unimplemented: Read as ‘0’
N1PFM: NCO1 Output Divider mode bit
1= NCO1 operates in Pulse Frequency mode
0= NCO1 operates in Fixed Duty Cycle mode, divide by 2
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REGISTER 23-2: NCO1CLK: NCO1 INPUT CLOCK CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
N1PWS<2:0>
N1CKS<1:0>
bit 7
Legend:
bit 0
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-5
N1PWS<2:0>: NCO1 Output Pulse Width Select bits(1, 2)
111= NCO1 output is active for 128 input clock periods
110= NCO1 output is active for 64 input clock periods
101= NCO1 output is active for 32 input clock periods
100= NCO1 output is active for 16 input clock periods
011= NCO1 output is active for 8 input clock periods
010= NCO1 output is active for 4 input clock periods
001= NCO1 output is active for 2 input clock periods
000= NCO1 output is active for 1 input clock period
bit 4-2
bit 1-0
Unimplemented: Read as ‘0’
N1CKS<1:0>: NCO1 Clock Source Select bits
11=Reserved
10= CLC1OUT
01= FOSC
00= HFINTOSC (16 MHz)
Note 1: N1PWS applies only when operating in Pulse Frequency mode.
2: If NCO1 pulse width is greater than NCO1 overflow period, the NCO1 output does not toggle.
REGISTER 23-3: NCO1ACCL: NCO1 ACCUMULATOR REGISTER – LOW BYTE
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCO1ACC<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
NCO1ACC<7:0>: NCO1 Accumulator, low byte
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REGISTER 23-4: NCO1ACCH: NCO1 ACCUMULATOR REGISTER – HIGH BYTE
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCO1ACC<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-0
NCO1ACC<15:8>: NCO1 Accumulator, high byte
(1)
REGISTER 23-5: NCO1ACCU: NCO1 ACCUMULATOR REGISTER – UPPER BYTE
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCO1ACC<19:16>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
NCO1ACC<19:16>: NCO1 Accumulator, upper byte
Note 1: The accumulator spans registers NCO1ACCU:NCO1ACCH:NCO1ACCL. The 24 bits are reserved but not all
are used.This register updates in real-time, asynchronously to the CPU; there is no provision to ensure
atomic access to this 24-bit space using an 8-bit bus. Writing to this register while the module is operating will
produce undefined results.
(1,2)
REGISTER 23-6: NCO1INCL
: NCO1 INCREMENT REGISTER – LOW BYTE
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-1/1
NCO1INC<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
NCO1INC<7:0>: NCO1 Increment, low byte
Note 1: The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL.
2: NCO1INC is double-buffered as INCBUF; INCBUF is updated on the next falling edge of NCOCLK after
writing to NCO1INCL;NCO1INCU and NCO1INCH should be written prior to writing NCO1INCL.
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(1)
REGISTER 23-7: NCO1INCH : NCO1 INCREMENT REGISTER – HIGH BYTE
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCO1INC<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
NCO1INC<15:8>: NCO1 Increment, high byte
Note 1: The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL.
(1)
REGISTER 23-8: NCO1INCU : NCO1 INCREMENT REGISTER – UPPER BYTE
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
NCO1INC<19:16>
bit 7
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
NCO1INC<19:16>: NCO1 Increment, upper byte
Note 1: The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL.
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TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH NCO1
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(2)
TRISA
—
—
TRISA5
ANSA5
TRISB5
ANSB5
TRISC5
ANSC5
C1IF
TRISA4
ANSA4
TRISB4
ANSB4
—
TRISA2 TRISA1 TRISA0
ANSA2 ANSA1 ANSA0
143
144
149
150
155
157
108
103
100
ANSELA
TRISB(1)
ANSELB(1)
TRISC
—
—
—
—
—
TRISB7
TRISB6
—
—
—
—
—
—
ANSB7
ANSB6
TRISC7(1) TRISC6(1)
ANSC7(1) ANSC6(1)
TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
ANSC4 ANSC3 ANSC2 ANSC1 ANSC0
NVMIF SSP2IF BCL2IF TMR4IF NCO1IF
NVMIE SSP2IE BCL2IE TMR4IE NCO1IE
ANSELC
PIR2
TMR6IF
TMR6IE
GIE
C2IF
C2IE
PIE2
C1IE
—
INTCON
PEIE
INTEDG
N1PFM
—
—
—
—
—
—
—
—
—
N1EN
—
N1OUT
N1POL
256
NCO1CON
NCO1CLK
NCO1ACCL
NCO1ACCH
NCO1ACCU
NCO1INCL
NCO1INCH
NCO1INCU
CWG1DAT
MDSRC
N1PWS<2:0>
—
N1CKS<1:0>
257
257
258
258
258
259
259
215
272
273
274
NCO1ACC <7:0>
NCO1ACC <15:8>
—
—
—
—
NCO1ACC <19:16>
NCO1INC<7:0>
NCO1INC<15:8>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
NCO1INC<19:16>
DAT<3:0>
MDMS<3:0>
MDCH<3:0>
MDCL<3:0>
MDCARH
MDCHPOL MDCHSYNC
MDCLPOL MDCLSYNC
—
—
—
MDCARL
CCPxCAP
CCPxCTS<3:0>
—
—
309
Legend: —= unimplemented read as ‘0’. Shaded cells are not used for NCO1 module.
Note 1: PIC16(L)F18346 only.
2: Unimplemented, read as ‘1’.
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24.1 Output Voltage Selection
24.0 5-BIT DIGITAL-TO-ANALOG
CONVERTER (DAC1) MODULE
The DAC has 32 voltage level ranges. The 32 levels
are set with the DAC1R<4:0> bits of the DAC1CON1
register.
The Digital-to-Analog Converter supplies a variable
voltage reference, ratiometric with the input source,
with 32 selectable output levels.
The DAC output voltage is determined by Equation 24-1:
The input of the DAC can be connected to:
• External VREF pins
• VDD supply voltage
• FVR (Fixed Voltage Reference)
The output of the DAC can be configured to supply a
reference voltage to the following:
• Comparator positive input
• ADC input channel
• DAC1OUT pin
The Digital-to-Analog Converter (DAC) is enabled by
setting the DAC1EN bit of the DAC1CON0 register.
EQUATION 24-1: DAC OUTPUT VOLTAGE
DAC1R4:0
V
=
V
– V
--------------------------------- + V
OUT
SOURCE+
SOURCE-
SOURCE-
5
2
V
or
FVR
V
= V
or
REF+
REF-
SOURCE+
DD
V
V
= V or
SOURCE-
SS
24.2 Ratiometric Output Level
The DAC output value is derived using a resistor ladder
with each end of the ladder tied to a positive and
negative voltage reference input source. If the voltage
of either input source fluctuates, a similar fluctuation will
result in the DAC output value.
The value of the individual resistors within the ladder
can be found in Table 35-15.
24.3 DAC Voltage Reference Output
The DAC voltage can be output to the DAC1OUT pin by
setting the DAC1OE bit of the DAC1CON0 register.
Selecting the DAC reference voltage for output on the
DAC1OUT pin automatically overrides the digital
output buffer and digital input threshold detector
functions, it disables the weak pull-up and the
constant-current drive function of that pin. Reading the
DAC1OUT pin when it has been configured for DAC
reference voltage output will always return a ‘0’.
Due to the limited current drive capability, a buffer must
be used on the DAC voltage reference output for
external connections to the DAC1OUT pin. Figure 24-2
shows an example buffering technique.
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FIGURE 24-1:
DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
VDD
00
01
10
11
VREF+
FVR_buffer2
VSOURCE+
DAC1R<4:0>
5
Reserved
DAC1PSS
DAC1EN
R
R
R
R
DAC1_output
32
Steps
To Peripherals
R
R
R
DAC1OUT (1)
DAC1OE
DAC1NSS
VSS
VREF-
1
0
VSOURCE-
Note 1: The unbuffered DAC1_output is provided on the DAC1OUT pin(s).
FIGURE 24-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC® MCU
DAC
Module
R
+
–
Buffered DAC Output
DAC1OUT
Voltage
Reference
Output
Impedance
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24.4 Operation During Sleep
24.5 Effects of a Reset
The DAC continues to function during Sleep. When the
device wakes up from Sleep through an interrupt or a
Watchdog Timer time-out, the contents of the
DAC1CON0 register are not affected.
A device Reset affects the following:
• DAC is disabled.
• DAC output voltage is removed from the
DAC1OUT pin.
• The DAC1R<4:0> range select bits are cleared.
24.6 Register Definitions: DAC Control
REGISTER 24-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0
R/W-0/0
U-0
—
R/W-0/0
U-0
—
R/W-0/0
R/W-0/0
U-0
—
R/W-0/0
DAC1EN
DAC1OE
DAC1PSS<1:0>
DAC1NSS
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
DAC1EN: DAC1 Enable bit
1= DAC is enabled
0= DAC is disabled
bit 6
bit 5
Unimplemented: Read as ‘0’
DAC1OE: DAC1 Voltage Output 1 Enable bit
1= DAC voltage level is output on the DAC1OUT pin
0= DAC voltage level is disconnected from the DAC1OUT pin
bit 4
Unimplemented: Read as ‘0’
bit 3-2
DAC1PSS<1:0>: DAC1 Positive Source Select bits
11= Reserved, do not use
10= FVR output
01= VREF+ pin
00= VDD
bit 1
bit 0
Unimplemented: Read as ‘0’
DAC1NSS: DAC1 Negative Source Select bits
1= VREF- pin
0= VSS
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REGISTER 24-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
DAC1R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
DAC1R<4:0>: DAC1 Voltage Output Select bits
VOUT = (VSRC+ - VSRC-)*(DAC1R<4:0>/32) + VSRC
TABLE 24-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC1 MODULE
Register
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DACCON0
DACCON1
CMxCON1
ADCON0
Legend:
DAC1EN
—
—
—
DAC1OE
—
—
DAC1PSS<1:0>
DAC1R<4:0>
—
DAC1NSS
263
264
191
244
CxINTP
CxINTN
CxPCH<2:0>
CxNCH<2:0>
GO/DONE
CHS<5:0>
ADON
— = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module.
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25.0 DATA SIGNAL MODULATOR
(DSM) MODULE
The Data Signal Modulator (DSM) is a peripheral which
allows the user to mix a data stream, also known as a
modulator signal, with a carrier signal to produce a
modulated output.
Both the carrier and the modulator signals are supplied
to the DSM module either internally from the output of
a peripheral, or externally through an input pin.
The modulated output signal is generated by
performing a logical “AND” operation of both the carrier
and modulator signals and then provided to the MDOUT
pin.
The carrier signal is comprised of two distinct and
separate signals. A carrier high (CARH) signal and a
carrier low (CARL) signal. During the time in which the
modulator (MOD) signal is in a logic high state, the
DSM mixes the carrier high signal with the modulator
signal. When the modulator signal is in a logic low
state, the DSM mixes the carrier low signal with the
modulator signal.
Using this method, the DSM can generate the following
types of key modulation schemes:
• Frequency-Shift Keying (FSK)
• Phase-Shift Keying (PSK)
• On-Off Keying (OOK)
Additionally, the following features are provided within
the DSM module:
• Carrier Synchronization
• Carrier Source Polarity Select
• Carrier Source Pin Disable
• Programmable Modulator Data
• Modulator Source Pin Disable
• Modulated Output Polarity Select
• Slew Rate Control
Figure 25-1 shows a simplified block diagram of the
Data Signal Modulator peripheral.
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FIGURE 25-1:
SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR
MDCH<3:0>
Data Signal Modulator
VSS
0000
0001
0010
0011
MDCIN1
MDCIN2
CLKR
CCP1
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CCP2
CARH
PWM5
PWM6
1&2ꢀ
RHVHUYHG
FOSC
HFINTOSC
CLC1
MDCHPOL
CLC2
D
CLC3
SYNC
Q
CLC4
1
0
MDMS<3:0>
MDBIT
0000
0001
0010
0011
0100
0101
0110
MDMIN
CCP1
CCP2
PWM5
PWM6
C1
MDCHSYNC
C2
0111 MOD
SDO1
SDO2
1000
1001
EUSARTꢀ TX
1&2ꢀ
1010
DSM
1011
CLC1
1100
CLC2
1101
MDOPOL
1110
CLC3
1111
CLC4
MDCL<3:0>
VSS
D
SYNC
Q
0000
0001
0010
0011
0100
0101
0110
0111
MDCIN1
MDCIN2
CLKR
1
0
CCP1
CCP2
PWM5
PWM6
1&2ꢀ
1000
CARL
1001
1010
1011
1100
1101
1110
1111
RHVHUYHG
MDCLSYNC
FOSC
HFINTOSC
CLC1
CLC2
CLC3
CLC4
MDCLPOL
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25.1 DSM Operation
25.3 Carrier Signal Sources
The DSM module can be enabled by setting the MDEN
bit in the MDCON register. Clearing the MDEN bit in the
MDCON register, disables the DSM module by auto-
matically switching the carrier high and carrier low sig-
nals to the VSS signal source. The modulator signal
source is also switched to the MDBIT in the MDCON
register. This not only assures that the DSM module is
inactive, but that it is also consuming the least amount
of current.
The carrier high signal and carrier low signal can be
supplied from the following sources:
• CCP1 Output
• CCP2 Output
• PWM5 Output
• PWM6 Output
• NCO1 Output
• FOSC (System Clock)
• HFINTOSC
The values used to select the carrier high, carrier low,
and modulator sources held by the Modulation Source,
Modulation High Carrier, and Modulation Low Carrier
control registers are not affected when the MDEN bit is
cleared and the DSM module is disabled. The values
inside these registers remain unchanged while the
DSM is inactive. The sources for the carrier high, car-
rier low and modulator signals will once again be
selected when the MDEN bit is set and the DSM
module is again enabled and active.
• CLC1 Output
• CLC2 Output
• CLC3 Output
• CLC4 Output
• CLKR
• External Signal on MDCIN1 pin
• External Signal on MDCIN2 pin
• Vss
The carrier high signal is selected by configuring the
MDCH <3:0> bits in the MDCARH register. The carrier
low signal is selected by configuring the MDCL <3:0>
bits in the MDCARL register.
The modulated output signal can be disabled without
shutting down the DSM module. The DSM module will
remain active and continue to mix signals, but the out-
put value will not be sent to the DSM pin. During the
time that the output is disabled, the DSM pin will remain
low. The modulated output can be disabled by clearing
the MDEN bit in the MDCON register.
25.4 Carrier Synchronization
During the time when the DSM switches between
carrier high and carrier low signal sources, the carrier
data in the modulated output signal can become
truncated. To prevent this, the carrier signal can be
synchronized to the modulator signal. When the
modulator signal transitions away from the
synchronized carrier, the unsynchronized carrier
source is immediately active, while the synchronized
carrier remains active until its next falling edge. When
the modulator signal transitions back to the
synchronized carrier, the unsynchronized carrier is
immediately disabled, and the modulator waits until the
next falling edge of the synchronized carrier before the
synchronized carrier becomes active.
25.2 Modulator Signal Sources
The modulator signal can be supplied from the
following sources:
• CCP1 Output
• CCP2 Output
• PWM5 Output
• PWM6 Output
• MSSP1 SDO1 (SPI mode only)
• MSSP2 SDO2 (SPI mode only)
• Comparator C1 Output
• Comparator C2 Output
• EUSART1 TX Output
• External Signal on MDMIN pin
• NCO1 Output
Synchronization is enabled separately for the carrier
high and carrier low signal sources. Synchronization for
the carrier high signal is enabled by setting the
MDCHSYNC bit in the MDCARH register.
Synchronization for the carrier low signal is enabled by
setting the MDCLSYNC bit in the MDCARL register.
• CLC1 Output
• CLC2 Output
• CLC3 Output
• CLC4 Output
• MDBIT bit in the MDCON register
Figure 25-1 through Figure 25-6 show timing diagrams
of using various synchronization methods.
The modulator signal is selected by configuring the
MDMS <3:0> bits in the MDSRC register.
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FIGURE 25-2:
ON OFF KEYING (OOK) SYNCHRONIZATION
Carrier Low (CARL)
Carrier High (CARH)
Modulator (MOD)
MDCHSYNC = 1
MDCLSYNC = 0
MDCHSYNC = 1
MDCLSYNC = 1
MDCHSYNC = 0
MDCLSYNC = 0
MDCHSYNC = 0
MDCLSYNC = 1
FIGURE 25-3:
NO SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 0)
Carrier High (CARH)
Carrier Low (CARL)
Modulator (MOD)
MDCHSYNC = 0
MDCLSYNC = 0
CARH
CARL
CARH
CARL
Active Carrier
State
FIGURE 25-4:
CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0)
Carrier High (CARH)
Carrier Low (CARL)
Modulator (MOD)
MDCHSYNC = 1
MDCLSYNC = 0
Active Carrier
State
CARH
CARH
CARL
CARL
both
both
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FIGURE 25-5:
CARRIER LOW SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 1)
Carrier High (CARH)
Carrier Low (CARL)
Modulator (MOD)
MDCHSYNC = 0
MDCLSYNC = 1
Active Carrier
State
CARH
CARL
CARH
CARL
FIGURE 25-6:
FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1)
Carrier High (CARH)
Carrier Low (CARL)
Modulator (MOD)
Falling edges
used to sync
MDCHSYNC = 1
MDCLSYNC = 1
Active Carrier
State
CARH
CARH
CARL
CARL
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25.5 Carrier Source Polarity Select
The signal provided from any selected input source for
the carrier high and carrier low signals can be inverted.
Inverting the signal for the carrier high source is
enabled by setting the MDCHPOL bit of the MDCARH
register. Inverting the signal for the carrier low source is
enabled by setting the MDCLPOL bit of the MDCARL
register.
25.6 Programmable Modulator Data
The MDBIT of the MDCON register can be selected as
the source for the modulator signal. This gives the user
the ability to program the value used for modulation.
25.7 Modulated Output Polarity
The modulated output signal provided on the DSM pin
can also be inverted. Inverting the modulated output
signal is enabled by setting the MDOPOL bit of the
MDCON register.
25.8 Slew Rate Control
The slew rate limitation on the output port pin can be
disabled. The slew rate limitation can be removed by
clearing the SLR bit of the SLRCON register
associated with that pin. For example, clearing the slew
rate limitation for pin RA5 would require clearing the
SLRA5 bit of the SLRCONA register.
25.9 Operation in Sleep Mode
The DSM module is not affected by Sleep mode. The
DSM can still operate during Sleep, if the Carrier and
Modulator input sources are also still operable during
Sleep.
25.10 Effects of a Reset
Upon any device Reset, the DSM module is disabled.
The user’s firmware is responsible for initializing the
module before enabling the output. The registers are
reset to their default values.
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25.11 Register Definitions: Modulation Control
REGISTER 25-1: MDCON: MODULATION CONTROL REGISTER
R/W-0/0
MDEN
U-0
—
U-0
—
R/W-0/0
R-0/0
U-0
—
U-0
—
R/W-0/0
MDBIT(2)
MDOPOL
MDOUT
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
MDEN: Modulator Module Enable bit
1= Modulator module is enabled and mixing input signals
0= Modulator module is disabled and has no output
bit 6-5
bit 4
Unimplemented: Read as ‘0’
MDOPOL: Modulator Output Polarity Select bit
1= Modulator output signal is inverted; idle high output
0= Modulator output signal is not inverted; idle low output
bit 3
MDOUT: Modulator Output bit
Displays the current output value of the modulator module(1)
bit 2-1
bit 0
Unimplemented: Read as ‘0’
MDBIT: Allows software to manually set modulation source input to module(2)
Note 1: The modulated output frequency can be greater and asynchronous from the clock that updates this
register bit, the bit value may not be valid for higher speed modulator or carrier signals.
2: MDBIT must be selected as the modulation source in the MDSRC register for this operation.
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REGISTER 25-2: MDSRC: MODULATION SOURCE CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
MDMS<3:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
MDMS<3:0> Modulation Source Selection bits
1111= CLC4 output
1110= CLC3 output
1101= CLC2 output
1100= CLC1 output
1011= NCO1 output
1010= EUSART1 TX output
1001= MSSP2 SDO2 output
1000= MSSP1 SDO1 output
0111= C2 (Comparator 2) output
0110= C1 (Comparator 1) output
0101= PWM6 output
0100= PWM5 output
0011= CCP2 output (PWM Output mode only)
0010= CCP1 output (PWM Output mode only)
0001= MDMINPPS
0000= MDBIT bit of MDCON register is modulation source
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REGISTER 25-3: MDCARH: MODULATION HIGH CARRIER CONTROL REGISTER
U-0
—
R/W-x/u
R/W-x/u
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
MDCHPOL MDCHSYNC
MDCH<3:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
Unimplemented: Read as ‘0’
MDCHPOL: Modulator High Carrier Polarity Select bit
1= Selected high carrier signal is inverted
0= Selected high carrier signal is not inverted
bit 5
MDCHSYNC: Modulator High Carrier Synchronization Enable bit
1= Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the
low time carrier
0= Modulator output is not synchronized to the high time carrier signal(1)
bit 4
Unimplemented: Read as ‘0’
bit 3-0
MDCH<3:0> Modulator Data High Carrier Selection bits (1)
1111= CLC4 output
1110= CLC3 output
1101= CLC2 output
1100= CLC1 output
1011= HFINTOSC
1010= FOSC
1001= Reserved. No channel connected.
1000= NCO1 output
0111= PWM6 output
0110= PWM5 output
0101= CCP2 output (PWM Output mode only)
0100= CCP1 output (PWM Output mode only)
0011= Reference clock module signal (CLKR)
0010= MDCIN2PPS
0001= MDCIN1PPS
0000= VSS
Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
2016-2017 Microchip Technology Inc.
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PIC16(L)F18326/18346
REGISTER 25-4: MDCARL: MODULATION LOW CARRIER CONTROL REGISTER
U-0
—
R/W-x/u
R/W-x/u
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
MDCLPOL MDCLSYNC
MDCL<3:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
Unimplemented: Read as ‘0’
MDCLPOL: Modulator Low Carrier Polarity Select bit
1= Selected low carrier signal is inverted
0= Selected low carrier signal is not inverted
bit 5
MDCLSYNC: Modulator Low Carrier Synchronization Enable bit
1= Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high
time carrier
0= Modulator output is not synchronized to the low time carrier signal(1)
bit 4
Unimplemented: Read as ‘0’
bit 3-0
MDCL<3:0> Modulator Data High Carrier Selection bits (1)
1111= CLC4 output
1110= CLC3 output
1101= CLC2 output
1100= CLC1 output
1011= HFINTOSC
1010= FOSC
1001= Reserved. No channel connected.
1000= NCO1 output
0111= PWM6 output
0110= PWM5 output
0101= CCP2 output (PWM Output mode only)
0100= CCP1 output (PWM Output mode only)
0011= Reference clock module signal (CLKR)
0010= MDCIN2PPS
0001= MDCIN1PPS
0000= VSS
Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
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TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page
(2)
TRISA
―
―
―
―
TRISA5
ANSA5
SLRA5
INLVLA5
TRISB5
ANSB5
SLRB5
INLVLB5
TRISC5
ANSC5
SLRC5
INLVLC5
―
TRISA4
ANSA4
SLRA4
―
TRISA2 TRISA1 TRISA0
143
144
146
146
149
150
152
152
155
157
158
159
271
ANSELA
SLRCONA
INLVLA
―
―
ANSA2
SLRA2
ANSA1
SLRA1
ANSA0
SLRA0
―
―
―
―
INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0
(1)
TRISB
TRISB7
ANSB7
SLRB7
INLVLB7
TRISB6
ANSB6
SLRB6
INLVLB6
TRISB4
ANSB4
SLRB4
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
(1)
ANSELB
(1)
SLRCONB
(1)
INLVLB
INLVLB4
(1)
(1)
TRISC
TRISC7
TRISC6
TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
(1)
(1)
ANSELC
ANSC7
SLRC7
ANSC6
SLRC6
ANSC4
SLRC4
ANSC3 ANSC2 ANSC1 ANSC0
SLRC3 SLRC2 SLRC1 SLRC0
(1)
(1)
(1)
(1)
SLRCONC
INLVLC
INLVLC7
INLVLC6
INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0
MDCON
MDEN
―
―
―
MDOPOL MDOUT
―
―
MDBIT
MDSRC
―
―
―
―
MDMS<3:0>
MDCH<3:0>
MDCL<3:0>
272
273
274
162
162
162
MDCARH
MDCARL
MDCIN1PPS
MDCIN2PPS
MDMINPPS
―
MDCHPOL MDCHSYNC
MDCLPOL MDCLSYNC
―
―
―
―
―
―
―
―
MDCIN1PPS<4:0>
MDCIN2PPS<4:0>
MDMINPPS<4:0>
―
―
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in the Data Signal Modulator mode.
Note 1: PIC16(L)F18346 only.
2: Unimplemented. Read as ‘1’.
2016-2017 Microchip Technology Inc.
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26.1.2
8-BIT MODE
26.0 TIMER0 MODULE
In normal operation, TMR0 increments on the rising
edge of the clock source. A 15-bit prescaler on the
clock input gives several prescale options (see
prescaler control bits, T0CKPS<3:0> in the T0CON1
register).
The Timer0 module is an 8/16-bit timer/counter with the
following features:
• 16-bit timer/counter
• 8-bit timer/counter with programmable period
• Synchronous or asynchronous operation
• Selectable clock sources
In 8-bit mode, TMR0H no longer functions as the
Timer0 high byte, but instead functions as the Period
Register (PR). The value of TMR0L is compared to that
of TMR0H on each clock cycle. When the two values
match, the following events happen:
• Programmable
Watchdog Timer)
prescaler
(independent
of
• Programmable postscaler
• Operation during Sleep mode
• Interrupt on match or overflow
• TMR0_out goes high for one prescaled clock
period
• TMR0L is reset
• Output on I/O pin (via PPS) or to other peripherals
• The contents of TMR0H are copied to the period
buffer
26.1 Timer0 Operation
In 8-bit mode, the TMR0L and TMR0H registers are
both directly readable and writable. The TMR0L
register is cleared on any device Reset, while the
TMR0H register initializes at FFh.
Timer0 can operate as either an 8-bit timer/counter or
a 16-bit timer/counter. The mode is selected with the
T016BIT bit of the T0CON register.
When used with an FOSC/4 clock source, the module is
a timer and increments on every instruction cycle.
When used with any other clock source, the module
can be used as either a timer or a counter and
increments on every rising edge of the external source.
Both the prescaler and postscaler counters are cleared
on the following events:
• A write to the TMR0L register
• A write to either the T0CON0 or T0CON1
registers.
26.1.1
16-BIT MODE
• Any device Reset – Power-on Reset (POR),
MCLR Reset, Watchdog Timer Reset (WDTR) or
Brown-out Reset (BOR)
In normal operation, TMR0 increments on the rising
edge of the clock source. A 15-bit prescaler on the
clock input gives several prescale options (see
prescaler control bits, T0CKPS<3:0> in the T0CON1
register).
26.1.3
COUNTER MODE
In Counter mode, the prescaler is normally disabled by
setting the T0CKPS bits of the T0CON1 register to
‘0000’. Each rising edge of the clock input (or the
output of the prescaler if the prescaler is used)
increments the counter by ‘1’.
26.1.1.1
Timer0 Reads and Writes in 16-bit
Mode
TMR0H is not the actual high byte of Timer0 in 16-bit
mode. It is actually a buffered version of the real high
byte of Timer0, which is neither directly readable nor
writable (see Figure 26-1). TMR0H is updated with the
contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte was valid, due to a rollover between
successive reads of the high and low byte.
26.1.4
TIMER MODE
In Timer mode, the Timer0 module will increment every
instruction cycle as long as there is a valid clock signal
and the T0CKPS bits of the T0CON1 register
(Register 26-4) are set to ‘0000’. When a prescaler is
added, the timer will increment at the rate based on the
prescaler value.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
26.1.5
ASYNCHRONOUS MODE
When the T0ASYNC bit of the T0CON1 register is set
(T0ASYNC = 1), the counter increments with each
rising edge of the input source (or output of the
prescaler, if used). Asynchronous mode allows the
counter to continue operation during Sleep mode
provided that the clock also continues to operate during
Sleep.
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26.1.6
SYNCHRONOUS MODE
26.6 Timer0 Interrupts
When the T0ASYNC bit of the T0CON1 register is clear
(T0ASYNC = 0), the counter clock is synchronized to
the system oscillator (FOSC/4). When operating in
Synchronous mode, the counter clock frequency
cannot exceed FOSC/4.
The Timer0 Interrupt Flag bit (TMR0IF) is set when
either of the following conditions occur:
• 8-bit TMR0L matches the TMR0H value
• 16-bit TMR0 rolls over from FFFFh
When the postscaler bits (T0OUTPS<3:0>) are set to
1:1 operation (no division), the T0IF Flag bit will be set
with every TMR0 match or rollover. In general, the
TMR0IF Flag bit will be set every T0OUTPS +1
matches or rollovers.
26.2 Clock Source Selection
The T0CS<2:0> bits of the T0CON1 register are used
to select the clock source for Timer0. Register 26-4
displays the clock source selections.
If Timer0 interrupts are enabled (TMR0IE bit of the
PIE0 register = 1), the CPU will be interrupted and the
device may wake from Sleep (see Section 26.5
“Operation During Sleep” for more details).
26.2.1
INTERNAL CLOCK SOURCE
When the internal clock source is selected, Timer0
operates as a timer and will increment on multiples of
the clock source, as determined by the Timer0
prescaler.
26.7 Timer0 Output
The Timer0 output can be routed to any I/O pin via the
RxyPPS output selection register (see Section 13.0
“Peripheral Pin Select (PPS) Module” for additional
information). The Timer0 output can also be used by
other peripherals, such as the auto-conversion trigger
of the Analog-to-Digital Converter. Finally, the Timer0
output can be monitored through software via the
Timer0 Output bit (T0OUT) of the T0CON0 register
(Register 26-3).
26.2.2
EXTERNAL CLOCK SOURCE
When an external clock source is selected, Timer0 can
operate as either a timer or a counter. Timer0 will
increment on multiples of the rising edge of the external
clock source, as determined by the Timer0 prescaler.
26.3 Programmable Prescaler
A software programmable prescaler is available for
exclusive use with Timer0. There are 16 prescaler
options for Timer0 ranging in powers of two from 1:1 to
1:32768. The prescaler values are selected using the
T0CKPS<3:0> bits of the T0CON1 register.
TMR0_out will be one postscaled clock period when a
match occurs between TMR0L and TMR0H in 8-bit
mode, or when TMR0 rolls over in 16-bit mode. When
a match condition occurs, the Timer0 output will toggle
every T0OUTPS + 1 match. The total Timer0 period
takes two match events to occur, and creates a 50%
duty cycle output.
The prescaler is not directly readable or writable.
Clearing the prescaler register can be done by writing
to the TMR0L register, the T0CON0 register, or the
T0CON1 register.
26.4 Programmable Postscaler
A software programmable postscaler (output divider) is
available for exclusive use with Timer0. There are 16
postscaler options for Timer0 ranging from 1:1 to 1:16.
The postscaler values are selected using the
T0OUTPS<3:0> bits of the T0CON0 register.
The postscaler is not directly readable or writable.
Clearing the postscaler register can be done by writing
to the TMR0L register, the T0CON0 register, or the
T0CON1 register.
26.5 Operation During Sleep
When operating synchronously, Timer0 will halt. When
operating asynchronously, Timer0 will continue to
increment and wake the device from Sleep (if Timer0
interrupts are enabled) provided that the input clock
source is active.
2016-2017 Microchip Technology Inc.
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PIC16(L)F18326/18346
FIGURE 26-1:
BLOCK DIAGRAM OF TIMER0
Rev. 10-000017B
4/6/2017
CLC1
111
110
SOSC
Reserved
LFINTOSC
HFINTOSC
FOSC/4
101
TMR0
BODY
T0CKPS<3:0>
Peripherals
T0IF
T0OUTPS<3:0>
100
1
0
Prescaler
011
IN
OUT
T0_out
Postscaler
SYNC
010
T0CKIPPS
(Inverted)
TMR0
F
OSC/4
T0ASYNC
T016BIT
001
000
D
Q
Q
PPS
RxyPPS
T0CKIPPS
CK
T0CS<2:0>
8-bit TMR0 Body Diagram (T016BIT = 0)
16-bit TMR0 Body Diagram (T016BIT = 1)
Clear
IN
TMR0 High
Byte(1)
OUT
IN
R
TMR0L
TMR0L
8
Read TMR0L
Write TMR0L
COMPARATOR
OUT
T0_match
8
8
TMR0H
TMR0 High
Byte(1)
Latch
Enable
8
TMR0H
8
Internal Data Bus
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26.8 Register Definitions: Timer0 Register
REGISTER 26-1: TMR0L: TIMER0 COUNT REGISTER
R/W-0/0
bit 7
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
TMR0L<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TMR0L<7:0>:TMR0 Counter bits 7..0
REGISTER 26-2: TMR0H: TIMER0 PERIOD REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
TMR0H<7:0> or TMR0<15:8>
R/W-1/1
R/W-1/1
R/W-1/1
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-0
When T016BIT = 0
TMR0H<7:0>:TMR0 Period Register Bits 7..0
When T016BIT = 1
TMR0<15:8>: TMR0 Counter bits 15..8
2016-2017 Microchip Technology Inc.
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REGISTER 26-3: T0CON0: TIMER0 CONTROL REGISTER 0
R/W-0/0
T0EN
U-0
—
R-0
R/W-0/0
T016BIT
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
T0OUT
T0OUTPS<3:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
T0EN:TMR0 Enable bit
1 = The module is enabled and operating
0 = The module is disabled and in the lowest power mode
bit 6
bit 5
Unimplemented: Read as ‘0’
T0OUT:TMR0 Output (read-only)
TMR0 output bit
bit 4
T016BIT: TMR0 Operating as 16-bit Timer Select bit
1 = TMR0 is a 16-bit timer
0 = TMR0 is an 8-bit timer
bit 3-0
T0OUTPS<3:0>: TMR0 Output Postscaler (divider) Select bits
1111= 1:16 Postscaler
1110= 1:15 Postscaler
1101= 1:14 Postscaler
1100= 1:13 Postscaler
1011= 1:12 Postscaler
1010= 1:11 Postscaler
1001= 1:10 Postscaler
1000= 1:9 Postscaler
0111= 1:8 Postscaler
0110= 1:7 Postscaler
0101= 1:6 Postscaler
0100= 1:5 Postscaler
0011= 1:4 Postscaler
0010= 1:3 Postscaler
0001= 1:2 Postscaler
0000= 1:1 Postscaler
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REGISTER 26-4: T0CON1: TIMER0 CONTROL REGISTER 1
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
T0CS<2:0>
T0ASYNC
T0CKPS<3:0>
bit 7
Legend:
bit 0
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-5
T0CS<2:0>:Timer0 Clock Source Select bits
111= CLC1
110= SOSC
101= Reserved
100= LFINTOSC
011= HFINTOSC
010= FOSC/4
001= T0CKIPPS (Inverted)
000= T0CKIPPS (True)
bit 4
T0ASYNC: TMR0 Input Asynchronization Enable bit
1 = The input to the TMR0 counter is not synchronized to system clocks
0 = The input to the TMR0 counter is synchronized to FOSC/4
bit 3-0
T0CKPS<3:0>: Prescaler Rate Select bit
1111= 1:32768
1110= 1:16384
1101= 1:8192
1100= 1:4096
1011= 1:2048
1010= 1:1024
1001= 1:512
1000= 1:256
0111= 1:128
0110= 1:64
0101= 1:32
0100= 1:16
0011= 1:8
0010= 1:4
0001= 1:2
0000= 1:1
2016-2017 Microchip Technology Inc.
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PIC16(L)F18326/18346
TABLE 26-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(2)
TRISA
―
―
―
―
TRISA5 TRISA4
ANSA5 ANSA4
―
TRISA2 TRISA1 TRISA0
ANSA2 ANSA1 ANSA0
143
144
149
150
155
157
279
279
280
281
162
162
246
229
293
100
106
101
ANSELA
TRISB(1)
ANSELB(1) ANSB7
―
―
TRISB7
TRISB6 TRISB5 TRISB4
ANSB6 ANSB5 ANSB4
TRISC7(1) TRISC6(1) TRISC5 TRISC4
ANSC7(1) ANSC6(1) ANSC5
ANSC4
―
―
―
―
―
―
―
TRISC
TRISC3
ANSC3
TRISC2 TRISC1 TRISC0
ANSC2 ANSC1 ANSC0
ANSELC
TMR0L
TMR0L<7:0>
TMR0H<7:0> or TMR0<15:8>
T0OUT T016BIT
T0ASYNC
TMR0H
T0CON0
T0CON1
T0CKIPPS
TMR0PPS
ADACT
CLCxSELy
T1GCON
INTCON
PIR0
T0EN
―
T0OUTPS<3:0>
T0CKPS<3:0>
T0CS<2:0>
―
―
―
―
―
―
―
―
―
―
―
T0CKIPPS<4:0>
TMR0PPS<4:0>
ADACT<4:0>
LCxDyS<5:0>
TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL
T1GSS<1:0>
GIE
―
PEIE
―
―
―
―
―
―
―
―
―
―
―
―
INTEDG
TMR0IF
TMR0IE
IOCIF
IOCIE
INTF
INTE
PIE0
―
―
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.
Note 1: PIC16(L)F18346 only.
2: Unimplemented, read as ‘1’.
DS40001839B-page 282
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27.0 TIMER1/3/5 MODULE WITH
GATE CONTROL
Timer1/3/5 modules are 16-bit timers/counters, each
with the following features:
• 16-bit timer/counter register pair (TMR1H:TMR1L)
• Programmable internal or external clock source
• 2-bit prescaler
• Clock source for optional comparator
synchronization
• Multiple Timer1 gate (count enable) sources
• Interrupt on overflow
• Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the Capture/Compare function with
the CCP modules
• Auto-Conversion Trigger (with CCP)
• Selectable Gate Source Polarity
• Gate Toggle mode
• Gate Single-Pulse mode
• Gate Value Status
• Gate Event Interrupt
Figure 27-1 is a block diagram of the Timer1 module.
Note 1: In devices with more than one Timer
module, it is very important to pay close
attention to the register names used. A
number placed after the module acronym
is used to distinguish between separate
modules. For example, the T1CON and
T3CON control the same operational
aspects of two completely different Timer
modules.
2: Throughout
this
section,
generic
references to Timer1 module in any of its
operating modes may be interpreted as
being equally applicable to Timerx
module. Register names, module
signals, I/O pins and bit names may use
the generic designator ‘x’ to indicate the
use of
a numeral to distinguish a
particular module, when required.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 283
PIC16(L)F18326/18346
FIGURE 27-1:
TIMER1 BLOCK DIAGRAM
T1GSS<1:0>
T1GSPM
T1G
00
01
10
11
T0_overflow
C1OUT_sync
C2OUT_sync
1
0
D
Q
T1GVAL
0
1
Single Pulse
Acq. Control
Q1
D
Q
T1GGO/DONE
T1GPOL
CK
R
Q
Interrupt
det
TMR1ON
T1GTM
set bit
TMR1GIF
TMR1GE
set flag bit
TMR1IF
TMR1ON
EN
D
TMR1(2)
TMR1H TMR1L
T1_overflow
Synchronized Clock Input
Q
0
1
T1CLK
T1SYNC
TMR1CS<1:0>
T1SOSC
LFINTOSC
Fosc
11
SOSC_clk
T1CKI
1
0
(1)
10
01
00
Prescaler
Synchronize(3)
1,2,4,8
Internal Clock
det
2
Fosc/4
Fosc/2
Internal
Clock
Internal Clock
T1CKPS<1:0>
Sleep
Input
Note 1: ST Buffer is high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
DS40001839B-page 284
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27.1 Timer1 Operation
27.2 Clock Source Selection
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
The TMR1CS<1:0> and T1OSC bits of the T1CON
register are used to select the clock source for Timer1.
Table 27-2 displays the clock source selections. The
TMR1H:TMR1L register pair will increment on
multiples of the clock source as determined by the
Timer1 prescaler.
The module can be used with either internal or external
clock sources, and has the Timer1 Gate Enable
function. When Timer1 is used with the Timer1 Gate
Enable, the timer can measure time intervals or count
signal pulses between two points of interest. When
used without the Timer1 Gate Enable, the timer simply
measures time intervals.
When either the FOSC or LFINTOSC clock source is
selected, the TMR1H:TMR1L register pair will
increment every rising clock edge. Reading from the
TMR1H:TMR1L register pair when either the FOSC or
LFINTOSC is the clock source will cause a 2 LSb loss
in resolution, which can be mitigated by using an
asynchronous input signal to gate the Timer1 clock
input (see Section 26.5 “Operation During Sleep” for
more information on the Timer1 Gate Enable).
Timer1 is enabled by configuring the TMR1ON and
TMR1GE bits in the T1CON and T1GCON registers,
respectively. Table 27-1 displays the Timer1 enable
selections.
When the FOSC/4 clock source is selected, the
TMR1H:TMR1L register pair increments every
instruction cycle (once every four FOSC pulses).
TABLE 27-1: TIMER1 ENABLE
SELECTIONS
In addition to the internal clock sources, Timer1 has a
dedicated external clock input pin, T1CKI. T1CKI can
be either synchronized to the system clock or can run
asynchronously via the T1SYNC bit of the T1CON
register. When the T1CKI pin is used as the clock
source, the TMR1H:TMR1L register pair increments on
the rising edge of the T1CKI clock input.
Timer1
Operation
TMR1ON
TMR1GE
0
0
1
1
0
1
0
1
Off
Off
Always On
Count Enabled
Note:
When using Timer1 to count events, a
falling edge must be registered by the
counter prior to the first incrementing
rising edge after any one or more of the
following conditions:
• Timer1 enabled after POR
• Write to TMR1H or TMR1L
• Timer1 is disabled
• Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON=1) when T1CKI is
low.
TABLE 27-2: CLOCK SOURCE SELECTIONS
TMR1CS<1:0>
Clock Source
11
10
01
00
LFINTOSC
External Clocking on T1CKI Pin
System Clock (FOSC)
Instruction Clock (FOSC/4)
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27.2.1
TIMER1 (SECONDARY)
OSCILLATOR
27.4.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS MODE
A dedicated low-power 32.768 kHz oscillator circuit is
built-in between pins SOSCI (input) and SOSCO
(amplifier output). This internal circuit is designed to be
used in conjunction with an external 32.768 kHz
crystal.
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
The oscillator circuit is enabled by setting the T1SOSC
bit of the T1CON register. The oscillator will continue to
run during Sleep.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TMR1L register pair.
Note:
The oscillator requires a start-up and
stabilization time before use. Thus,
T1SOSC should be set and a suitable
delay observed prior to using Timer1. A
suitable delay similar to the OST delay
can be implemented in software by
clearing the TMR1IF bit then presetting
the TMR1H:TMR1L register pair to
FC00h. The TMR1IF flag will be set when
1024 clock cycles have elapsed, thereby
indicating that the oscillator is running and
reasonably stable.
27.5 Timer1 Gate
Timer1 can be configured to count freely or the count
can be enabled and disabled using Timer1 gate
circuitry. This is also referred to as Timer1 Gate Enable.
Timer1 gate can also be driven by multiple selectable
sources.
27.5.1
TIMER1 GATE ENABLE
The Timer1 Gate Enable mode is enabled by setting
the TMR1GE bit of the T1GCON register. The polarity
of the Timer1 Gate Enable mode is configured using
the T1GPOL bit of the T1GCON register.
27.3 Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
source. When Timer1 Gate Enable mode is disabled,
no incrementing will occur and Timer1 will hold the
current count. See Figure 27-3 for timing details.
27.4 Timer1 Operation in
Asynchronous Mode
TABLE 27-3: TIMER1 GATE ENABLE
SELECTIONS
If the control bit T1SYNC of the T1CON register is set,
the external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If the external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 27.4.1 “Reading and Writing Timer1 in
Asynchronous Mode”).
T1CLK T1GPOL
T1G
Timer1 Operation
0
0
1
1
0
1
0
1
Counts
Holds Count
Holds Count
Counts
Note:
When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
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Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
27.5.2
TIMER1 GATE SOURCE
SELECTION
Timer1 gate source selections are shown in Table 27-4.
Source selection is controlled by the T1GSS bits of the
T1GCON register. The polarity of the selected input is
configurable. Polarity selection is controlled by the
T1GPOL bit of the T1GCON register.
Note:
Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
TABLE 27-4: TIMER1 GATE SOURCES
27.5.4
TIMER1 GATE SINGLE-PULSE
MODE
T1GSS
Timer1 Gate Source
Timer1 Gate Pin
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single-pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/DONE bit in the T1GCON register must be set.
The Timer1 will be fully enabled on the next
incrementing edge of the Timer1 gate signal. On the
next trailing edge of the Timer1 gate signal, the
T1GGO/DONE bit will automatically be cleared. No
other gate events will be allowed to increment Timer1
until the T1GGO/DONE bit is once again set in
software. See Figure 27-5 for timing details.
00
01
Overflow of Timer0
(TMR0 increments from FFh to 00h)
10
11
Comparator 1 Output
(optionally Timer1 synchronized output)
Comparator 2 Output
(optionally Timer1 synchronized output)
27.5.2.1
T1G Pin Gate Operation
The T1G pin is one source for Timer1 gate control. It
can be used to supply an external source to the Timer1
gate circuitry.
If the Single-Pulse Gate mode is disabled by clearing the
T1GSPM bit in the T1GCON register, the T1GGO/DONE
bit should also be cleared.
27.5.2.2
Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h,
low-to-high pulse will automatically be generated and
internally supplied to the Timer1 gate circuitry.
a
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the period of the Timer1 gate
source to be measured. See Figure 27-6 for timing
details.
27.5.2.3
Comparator C1 Gate Operation
The output resulting from a Comparator 1 operation can
be selected as a source for Timer1 gate control. The
Comparator 1 output can be synchronized to the Timer1
clock or left asynchronous. For more information see
27.5.5
TIMER1 GATE VALUE STATUS
When Timer1 Gate Value Status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T1GVAL bit in the T1GCON
register. The T1GVAL bit is valid even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
Section 18.4.1
“Comparator
Output
Synchronization”.
27.5.2.4
Comparator C2 Gate Operation
The output resulting from a Comparator 2 operation
can be selected as a source for Timer1 gate control.
The Comparator 2 output can be synchronized to the
Timer1 clock or left asynchronous. For more
information see Section 18.4.1 “Comparator Output
Synchronization”.
27.5.3
TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is
possible to measure the full period of a Timer1 gate
signal, as opposed to the duration of a single level
pulse.
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. See Figure 27-4 for timing details.
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27.6 Timer1 Interrupt
27.8 CCP Capture/Compare Time Base
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt on rollover, you must set
these bits:
The CCP modules use the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPR1H:CCPR1L
register pair on a configured event.
• TMR1ON bit of the T1CON register
• TMR1IE bit of the PIE1 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
In Compare mode, an event is triggered when the value
CCPR1H:CCPR1L register pair matches the value in
the TMR1H:TMR1L register pair. This event can be an
Auto-conversion Trigger.
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
For
more
information,
see
Section 29.0
“Capture/Compare/PWM Modules”.
Note:
The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
27.9 CCP Auto-Conversion Trigger
When any of the CCP’s are configured to trigger an
auto-conversion, the trigger will clear the
TMR1H:TMR1L register pair. This auto-conversion
does not cause a Timer1 interrupt. The CCP module
may still be configured to generate a CCP interrupt.
27.6.1
TIMER1 GATE EVENT INTERRUPT
When Timer1 Gate Event Interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of T1GVAL
occurs, the TMR1GIF flag bit in the PIR1 register will be
set. If the TMR1GIE bit in the PIE1 register is set, then
an interrupt will be recognized.
In this mode of operation, the CCPR1H:CCPR1L
register pair becomes the period register for Timer1.
Timer1 should be synchronized and FOSC/4 should be
selected as the clock source in order to utilize the
Auto-conversion Trigger. Asynchronous operation of
Timer1 can cause an Auto-conversion Trigger to be
missed.
The TMR1GIF flag bit operates even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
27.7 Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous mode. In this mode, an external crystal
or clock source can be used to increment the timer. To
set up the timer to wake the device:
In the event that a write to TMR1H or TMR1L coincides
with an Auto-conversion Trigger from the CCP, the
write will take precedence.
For
more
information,
see
Section 29.3.3
• TMR1ON bit of the T1CON register must be set
• TMR1IE bit of the PIE1 register must be set
• PEIE bit of the INTCON register must be set
• T1SYNC bit of the T1CON register must be set
• TMR1CS bits of the T1CON register must be con-
figured
“Auto-Conversion Trigger”.
• T1SOSC bit of the T1CON register must be con-
figured
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
Secondary oscillator will continue to operate in Sleep
regardless of the T1SYNC bit setting.
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FIGURE 27-2:
TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
FIGURE 27-3:
TIMER1 GATE ENABLE MODE
TMR1GE
T1GPOL
t1g_in
T1CKI
T1GVAL
Timer1
N
N + 1
N + 2
N + 3
N + 4
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FIGURE 27-4:
TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
t1g_in
T1CKI
T1GVAL
Timer1
N
N + 1 N + 2 N + 3 N + 4
N + 5 N + 6 N + 7 N + 8
FIGURE 27-5:
TIMER1 GATE SINGLE-PULSE MODE
TMR1GE
T1GPOL
T1GSPM
Cleared by hardware on
falling edge of T1GVAL
T1GGO/
DONE
Set by software
Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
Timer1
N
N + 1
N + 2
Cleared by
software
Set by hardware on
falling edge of T1GVAL
Cleared by software
TMR1GIF
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FIGURE 27-6:
TMR1GE
T1GPOL
TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
T1GSPM
T1GTM
Cleared by hardware on
falling edge of T1GVAL
T1GGO/
DONE
Set by software
Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
Timer1
N + 4
N + 2 N + 3
N
N + 1
Set by hardware on
falling edge of T1GVAL
Cleared by
software
Cleared by software
TMR1GIF
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27.10 Register Definitions: Timer1/3/5 Control
(1)
REGISTER 27-1: TxCON : TIMERx CONTROL REGISTER
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
TxSOSC
R/W-0/u
TxSYNC
U-0
—
R/W-0/u
TMRxCS<1:0>
TxCKPS<1:0>
TMRxON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
TMRxCS<1:0>: Timerx Clock Source Select bits
11= Timerx clock Source is LFINTOSC
10= Timerx clock source is pin or oscillator:
If TxSOSC = 0:
External clock from TxCKIPPS pin (on the rising edge)
If TxSOSC = 1:
Clock from SOSC, either crystal oscillator on TxSOSCI/TxSOSCO pins, or SOSCIN input
01= Timerx clock source is system clock (FOSC)
00= Timerx clock source is instruction clock (FOSC/4)
bit 5-4
TxCKPS<1:0>: Timerx Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
TxSOSC: LP Oscillator Enable Control bit
1= SOSC requested as the clock source
0= TxCKI enabled as the clock source
TxSYNC: Timer1 Synchronization Control bit
TMRxCS<1:0> = 1x
1= Do not synchronize external clock input
0= Synchronize external clock input with system clock
TMRxCS<1:0> = 0x
This bit is ignored. Timer1 uses the internal clock and no additional synchronization is performed.
bit 1
bit 0
Unimplemented: Read as ‘0’
TMRxON: Timer1 On bit
1= Enables Timerx
0= Stops Timerx and clears Timerx gate flip-flop
Note 1: ‘x’ refers to either ‘1’, ‘3’ or ‘5’ for the respective Timer1/3/5 registers.
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(1)
REGISTER 27-2: TxGCON : TIMERx GATE CONTROL REGISTER
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W/HC-0/u
R-x/x
R/W-0/u
R/W-0/u
TMRxGE
TxGPOL
TxGTM
TxGSPM
TxGGO/DONE
TxGVAL
TxGSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HC = Bit is cleared by hardware
bit 7
TMRxGE: Timer1 Gate Enable bit
If TMRxON = 0:
This bit is ignored
If TMRxON = 1:
1= Timerx counting is controlled by the Timer1 gate function
0= Timerx is always counting
bit 6
bit 5
TxGPOL: Timerx Gate Polarity bit
1= Timerx gate is active-high (Timerx counts when gate is high)
0= Timerx gate is active-low (Timerx counts when gate is low)
TxGTM: Timerx Gate Toggle Mode bit
1= Timerx Gate Toggle mode is enabled
0= Timerx Gate Toggle mode is disabled and toggle flip-flop is cleared
Timerx gate flip-flop toggles on every rising edge.
bit 4
bit 3
TxGSPM: Timerx Gate Single-Pulse Mode bit
1= Timerx Gate Single-Pulse mode is enabled and is controlling Timerx gate
0= Timerx Gate Single-Pulse mode is disabled
TxGGO/DONE: Timerx Gate Single-Pulse Acquisition Status bit
1= Timerx gate single-pulse acquisition is ready, waiting for an edge
0= Timerx gate single-pulse acquisition has completed or has not been started
This bit is automatically cleared when TxGSPM is cleared
bit 2
TxGVAL: Timerx Gate Value Status bit
Indicates the current state of the Timerx gate, latched at Q1, provided to TMRxH:TMRxL
Unaffected by Timerx Gate Enable (TMRxGE)
bit 1-0
TxGSS<1:0>: Timerx Gate Source Select bits
11= Comparator 2 optionally synchronized output
10= Comparator 1 optionally synchronized output
01= Timer0 overflow output
00= Timerx gate pin
Note 1: ‘x’ refers to either ‘1’, ‘3’ or ‘5’ for the respective Timer1/3/5 registers.
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(1)
REGISTER 27-3: TMRxL : TIMERx LOW BYTE REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
TMRxL<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TMRxL<7:0>: TMRx Low Byte bits
Note 1: ‘x’ refers to either ‘1’, ‘3’ or ‘5’ for the respective Timer1/3/5 registers.
(1)
REGISTER 27-4: TMRxH : TIMERx HIGH BYTE REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
TMRxH<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TMRxH<7:0>: TMRx High Byte bits
Note 1: ‘x’ refers to either ‘1’, ‘3’ or ‘5’ for the respective Timer1/3/5 registers.
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TABLE 27-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1/3/5
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(2)
TRISA
―
―
TRISA5
ANSA5
TRISB5
ANSB5
TRISC5
ANSC5
―
TRISA4
ANSA4
TRISB4
ANSB4
TRISC4
ANSC4
―
―
TRISA2
ANSA2
―
TRISA1
ANSA1
―
TRISA0
ANSA0
―
143
144
149
150
155
157
100
107
102
109
104
110
105
292
293
294
294
162
162
ANSELA
―
―
―
(1)
TRISB
TRISB7
ANSB7
TRISB6
ANSB6
―
(1)
ANSELB
TRISC
―
―
―
―
(1)
(1)
TRISC7
TRISC6
TRISC3
ANSC3
―
TRISC2
ANSC2
―
TRISC1
ANSC1
―
TRISC0
ANSC0
INTEDG
TMR1IF
(1)
(1)
ANSELC
INTCON
PIR1
ANSC7
GIE
ANSC6
PEIE
TMR1GIF
TMR1GIE
OSFIF
ADIF
RCIF
TXIF
SSP1IF
SSP1IE
CLC4IF
CLC4IE
CCP4IF
CCP4IE
T1SOSC
BCL1IF
BCL1IE
CLC3IF
CLC3IE
CCP3IF
CCP3IE
T1SYNC
TMR2IF
PIE1
ADIE
RCIE
TXIE
TMR2IE TMR1IE
PIR3
CSWIF
CSWIE
TMR3GIF
TMR3IF
CLC2IF
CLC2IE
CCP2IF
CCP2IE
―
CLC1IF
CLC1IE
CCP1IF
CCP1IE
TMR1ON
PIE3
OSFIE
TMR3GIE TMR3IE
CWG1IF TMR5GIF TMR5IF
PIR4
CWG2IF
PIE4
CWG2IE CWG1IE TMR5GIE TMR5IE
T1CON
T1GCON
TMR1L
TMR1H
T1CKIPPS
T1GPPS
TMR1CS<1:0>
T1CKPS<1:0>
TMR1GE T1GPOL
T1GTM
T1GSPM T1GGO/DONE T1GVAL
TMR1L<7:0>
T1GSS<1:0>
TMR1H<7:0>
―
―
―
―
―
―
T1CKIPPS<4:0>
T1GPPS<4:0>
T3CON
TMR3CS<1:0>
T3CKPS<1:0>
T3SOSC
T3SYNC
―
TMR3ON
292
T3GCON
TMR3L
TMR3GE T3GPOL
T3GTM
T3GSPM T3GGO/DONE T3GVAL
TMR3L<7:0>
T3GSS<1:0>
293
294
294
162
162
292
293
294
294
162
162
280
190
311
308
229
246
TMR3H
TMR3H<7:0>
T3CKIPPS
T3GPPS
T5CON
―
―
―
―
―
―
T3CKIPPS<4:0>
T3GPPS<4:0>
TMR5CS<1:0>
T5CKPS<1:0>
T5SOSC
T5SYNC
―
TMR5ON
T5GCON
TMR5L
TMR5GE T5GPOL
T5GTM
T5GSPM T5GGO/DONE T5GVAL
TMR5L<7:0>
T5GSS<1:0>
TMR5H
TMR5H<7:0>
T5CKIPPS
T5GPPS
T0CON0
CMxCON0
CCPTMRS
―
―
―
―
―
―
T5CKIPPS<4:0>
T5GPPS<4:0>
T0EN
CxON
―
T0OUT
―
T016BIT
CxPOL
T0OUTPS<3:0>
CxSP CxHYS
C2TSEL<1:0> C1TSEL<1:0>
CCPxMODE<3:0>
LCxDyS<5:0>
ADACT<4:0>
CxOUT
―
CxSYNC
C4TSEL<1:0>
C3TSEL<1:0>
CCPxCON CCPxEN
―
―
―
CCPxOUT CCPxFMT
CLCxSELy
ADACT
―
―
―
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module.
Note 1: PIC16(L)F18346 only.
2: Unimplemented, read as ‘1’.
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28.0 TIMER 2/4/6 MODULE
Note 1: In devices with more than one Timer
module, it is very important to pay close
attention to the register names used. A
number placed after the module acronym
is used to distinguish between separate
modules. For example, the T2CON and
T4CON control the same operational
aspects of two completely different Timer
modules.
Timer2/4/6 modules are 8-bit timers that incorporate
the following features:
• 8-bit Timer and Period registers (TMR2/4/6 and
PR2/4/6, respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16,
and 1:64)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2/4/6 match with PR2/4/6
• Optional use as the shift clock for the MSSPx
module
2: Throughout
this
section,
generic
references to Timer2 module in any of its
operating modes may be interpreted as
being equally applicable to Timerx
module. Register names, module
signals, I/O pins and bit names may use
the generic designator ‘x’ to indicate the
See Figure 28-1 for a block diagram of Timer2/4/6.
use of
a numeral to distinguish a
particular module, when required.
FIGURE 28-1:
TIMER2/4/6 BLOCK DIAGRAM
T[_match
To Peripherals
Prescaler
1:1, 1:4, 1:16, 1:64
R
Fosc/4
TMR2ꢁꢂꢁꢃꢄ
2
Postscaler
1:1 to 1:16
set bit
TMR[IF
Comparator
T[CKPS<1:0>
4
PR2ꢁꢂꢁꢃ
T[OUTPS<3:0>
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PIC16(L)F18326/18346
28.1 Timer2 Operation
28.3 Timer2 Output
The clock input to the Timer2 modules is the system
instruction clock (FOSC/4).
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
A 4-bit counter/prescaler on the clock input allows direct
input, divide-by-4 and divide-by-16 prescale options.
These options are selected by the prescaler control bits,
T2CKPS<1:0> of the T2CON register. The value of
TMR2 is compared to that of the Period register, PR2, on
each clock cycle. When the two values match, the
comparator generates a match signal as the timer
output. This signal also resets the value of TMR2 to 00h
on the next cycle and drives the output
Timer2 can be optionally used as the shift clock source
for the MSSPx module operating in SPI mode.
Additional information is provided in Section 30.0
“Master Synchronous Serial Port (MSSPx) Module”
28.4 Timer2 Operation During Sleep
The Timer2 timers cannot be operated while the
processor is in Sleep mode. The contents of the TMR2
and PR2 registers will remain unchanged while the
processor is in Sleep mode.
counter/postscaler
(see
Section 28.2
“Timer2
Interrupt”).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, whereas the PR2 register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
• A write to the TMR2 register
• A write to the T2CON register
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• MCLR Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESETInstruction
Note:
TMR2 is not cleared when T2CON is
written.
28.2 Timer2 Interrupt
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2-to-PR2 match)
provides the input for the 4-bit counter/postscaler. This
counter generates the TMR2 match interrupt flag which
is latched in TMR2IF of the PIR1 register. The interrupt
is enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE, of the PIE1 register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0>, of the T2CON register.
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28.5 Register Definitions: Timer2/4/6 Control
(1)
REGISTER 28-1: TxCON : TIMERx CONTROL REGISTER
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TxOUTPS<3:0>
TMRxON
TxCKPS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TxOUTPS<3:0>: Timerx Output Postscaler Select bits
1111= 1:16 Postscaler
1110= 1:15 Postscaler
1101= 1:14 Postscaler
1100= 1:13 Postscaler
1011= 1:12 Postscaler
1010= 1:11 Postscaler
1001= 1:10 Postscaler
1000= 1:9 Postscaler
0111= 1:8 Postscaler
0110= 1:7 Postscaler
0101= 1:6 Postscaler
0100= 1:5 Postscaler
0011= 1:4 Postscaler
0010= 1:3 Postscaler
0001= 1:2 Postscaler
0000= 1:1 Postscaler
bit 2
TMRxON: Timer2 On bit
1= Timerx is ON
0= Timerx is OFF
bit 1-0
TxCKPS<1:0>: Timerx Clock Prescale Select bits
11= Prescaler is 64
10= Prescaler is 16
01= Prescaler is 4
00= Prescaler is 1
Note 1: ‘x’ refers to either ‘2,’ 4’ or ‘6’ for the respective Timer2/4/6 registers.
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(1)
REGISTER 28-2: TMRx : TIMERx COUNT REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
TMRx<7:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TMRx<7:0>: TMRx Counter bits 7..0
Note 1: ‘x’ refers to either ‘2,’ 4’ or ‘6’ for the respective Timer2/4/6 registers.
(1)
REGISTER 28-3: PRx: TIMERx PERIOD REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
bit 0
PRx<7:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
PRx<7:0>: TMRx Counter bits 7..0
When TMRx = PRx, the next clock will reset the counter; counter period is (PRx+1)
Note 1: ‘x’ refers to either ‘2,’ 4’ or ‘6’ for the respective Timer2/4/6 registers.
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TABLE 28-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE
TMR1GIF
TMR1GIE
TMR6IF
TMR6IE
―
PEIE
ADIF
ADIE
C2IF
C2IE
―
―
―
―
―
INTEDG
100
107
102
108
103
298
RCIF
RCIE
C1IF
C1IE
TXIF
SSP1IF
SSP1IE
SSP2IF
SSP2IE
BCL1IF TMR2IF TMR1IF
BCL1IE TMR2IE TMR1IE
BCL2IF TMR4IF NCO1IF
BCL2IE TMR4IE NCO1IE
PIE1
TXIE
PIR2
NVMIF
NVMIE
PIE2
T2CON
TMR2
PR2
T2OUTPS<3:0>
TMR2<7:0>
PR2<7:0>
T4OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
T4CKPS<1:0>
T6CKPS<1:0>
299
299
298
299
299
298
299
299
246
197
229
T4CON
TMR4
PR4
―
―
TMR4ON
TMR4<7:0>
PR4<7:0>
T6CON
TMR6
PR6
T6OUTPS<3:0>
TMR6ON
TMR6<7:0>
PR6<7:0>
ADACT<4:0>
ADACT
PWMTMRS
CLCxSELy
―
―
―
―
―
―
―
―
―
P6TSEL<1:0>
LCxDyS<5:0>
P5TSEL<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2/4/6 module.
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29.2 Capture Mode
29.0 CAPTURE/COMPARE/PWM
MODULES
Capture mode makes use of either the 16-bit Timer0 or
Timer1 resource. When an event occurs on the capture
source, the 16-bit CCPRxH:CCPRxL register pair
captures and stores the 16-bit value of the
TMR0H:TMR0L or TMR1H:TMR1L register pair,
respectively. An event is defined as one of the following
and is configured by the CCPxMODE<3:0> bits of the
CCPxCON register:
The Capture/Compare/PWM module is a peripheral
that allows the user to time and control different events
and to generate Pulse-Width Modulation (PWM)
signals. In Capture mode, the peripheral allows the
timing of the duration of an event. The Compare mode
allows the user to trigger an external event when a
predetermined amount of time has expired. The PWM
mode can generate Pulse-Width Modulated signals of
varying frequency and duty cycle.
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
This family of devices contains four standard
Capture/Compare/PWM modules (CCP1, CCP2, CCP3
and CCP4).
When a capture is made, the Interrupt Request Flag bit
CCPxIF of the PIR4 register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPRxH, CCPRxL register pair
is read, the old captured value is overwritten by the new
captured value.
The Capture and Compare functions are identical for all
CCP modules.
29.1 CCP/PWM Clock Selection
The PIC16(L)F18326/18346 devices allow each
individual CCP and PWM module to select the timer
source that controls the module. Each module has an
independent selection.
Figure 29-1 shows a simplified diagram of the capture
operation.
29.2.1
CAPTURE SOURCES
As there are up to three 8-bit timers with auto-reload
(Timer2, Timer4, and Timer6), PWM mode on the CCP
and PWM modules can use any of these timers.
In Capture mode, the CCPx pin should be configured
as an input by setting the associated TRIS control bit.
Note:
If the CCPx pin is configured as an output,
a write to the port can cause a Capture
condition.
The CCPTMRS register is used to select which timer is
used.
Note 1: In devices with more than one CCP
module, it is very important to pay close
attention to the register names used. A
number placed after the module acronym
is used to distinguish between separate
modules. For example, the CCP1CON
and CCP2CON control the same
operational aspects of two completely
different CCP modules.
The capture source is selected by configuring the
CCPxCTS<3:0> bits of the CCPxCAP register. The
following sources can be selected:
• CCPxPPS input
• C1_output
• C2_output
• NCO_output
• IOC_interrupt
• LC1_output
• LC2_output
• LC3_output
• LC4_output
2: Throughout
this
section,
generic
references to a CCP module in any of its
operating modes may be interpreted as
being equally applicable to CCPx module.
Register names, module signals, I/O pins,
and bit names may use the generic
designator ‘x’ to indicate the use of a
numeral to distinguish a particular module,
when required.
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FIGURE 29-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Rev. 10-000158C
5/2/2014
CCPxCTS<3:0>
RxyPPS
CCPx
1001-
Reserved
TRIS Control
1111
LC4_output
LC3_output
LC2_output
LC1_output
IOC_interrupt
1000
0111
0110
0101
0100
0011
0010
0001
0000
CCPRxH
CCPRxL
16
set CCPxIF
Prescaler
1,4,16
and
Edge Detect
16
NCO
MODE <3:0>
TMR1H
TMR1L
C2OUT_sync
C1OUT_sync
CCPx
PIC16(L)F18326/18346
29.2.2
TIMER1/3/5 MODE RESOURCE
29.2.5
CAPTURE DURING SLEEP
Timer1/3/5 must be running in Timer mode or
Synchronized Counter mode for the CCP module to use
the capture feature. In Asynchronous Counter mode, the
capture operation may not work.
Capture mode depends upon the Timer1/3/5 module for
proper operation. There are two options for driving the
Timer1/3/5 module in Capture mode. It can be driven by
the instruction clock (FOSC/4), or by an external clock
source.
See Section 27.0 “Timer1/3/5 Module with Gate
Control” for more information on configuring
Timer1/3/5.
When Timer1/3/5 is clocked by FOSC/4, Timer1/3/5 will
not increment during Sleep. When the device wakes
from Sleep, Timer1/3/5 will continue from its previous
state.
Note:
Clocking Timer1/3/5 from the system clock
(FOSC) should not be used in Capture
mode. In order for Capture mode to
recognize the trigger event on the CCPx
pin, Timer1/3/5 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
Capture mode will operate during Sleep when
Timer1/3/5 is clocked by an external clock source.
29.2.3
SOFTWARE INTERRUPT MODE
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIE4 register clear to
avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIR4 register
following any change in Operating mode.
29.2.4
CCP PRESCALER
There are four prescaler settings specified by the
CCPxMODE<3:0> bits of the CCPxCON register.
Whenever the CCP module is turned off, or the CCP
module is not in Capture mode, the prescaler counter
is cleared. Any Reset will clear the prescaler counter.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCPxCON register before changing the
prescaler. Example 29-1 demonstrates the code to
perform this function.
EXAMPLE 29-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
BANKSELCCPxCON
;Set Bank bits to point
;to CCPxCON
CLRF
CCPxCON
;Turn CCP module off
MOVLW NEW_CAPT_PS;Load the W reg with
;the new prescaler
;move value and CCP ON
MOVWF CCPxCON
;Load CCPxCON with this
;value
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29.3.1
CCPX PIN CONFIGURATION
29.3 Compare Mode
The user must configure the CCPx pin as an output by
clearing the associated TRIS bit and defining the
appropriate output pin through the RxyPPS registers.
See Section 13.0 “Peripheral Pin Select (PPS)
Module” for more details.
Compare mode makes use of the 16-bit Timer1/3/5
resource. The 16-bit value of the CCPRxH:CCPRxL
register pair is constantly compared against the 16-bit
value of the TMR1/3/5H:TMR1/3/5L register pair. When
a match occurs, one of the following events can occur:
Note:
Clearing the CCPxCON register will force
the CCPx compare output latch to the
default low level. This is not the PORT I/O
data latch.
• Toggle the CCPx output
• Set the CCPx output
• Clear the CCPx output
• Generate an Auto-conversion Trigger
• Generate a Software Interrupt
29.3.2
TIMER1/3/5 MODE RESOURCE
The action on the pin is based on the value of the
CCPxMODE<3:0> control bits of the CCPxCON regis-
ter. At the same time, the interrupt flag CCPxIF bit is
set, and an ADC conversion can be triggered, if
selected.
In Compare mode, Timer1/3/5 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
See Section 27.0 “Timer1/3/5 Module with Gate
Control” for more information on configuring
Timer1/3/5.
All Compare modes can generate an interrupt and
trigger an ADC conversion.
Figure 29-2 shows a simplified diagram of the compare
operation.
Note:
Clocking Timer1/3/5 from the system clock
(FOSC) should not be used in Compare
mode. In order for Compare mode to
recognize the trigger event on the CCPx
pin, Timer1/3/5 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
Note:
When the CCP is configured in Compare
mode using the ‘toggle output on match’
setting (CCPxMODE<3:0> bits = 0010)
and the reference timer is set for an input
clock prescale other than 1:1, the output
of the CCP will toggle multiple times until
finally settling a ‘0’ logic level. To avoid
this, the timer input clock prescale select
29.3.3
AUTO-CONVERSION TRIGGER
All CCPx modes set the CCP interrupt flag
(CCPxIF). When this flag is set as a match occurs,
an auto-conversion trigger can occur if the CCP
module is selected as the conversion trigger source.
bits must be set to
(TxCKPS = 00).
a
1:1 ratio
FIGURE 29-2:
COMPARE MODE
Refer to Section 22.2.4 “Auto-Conversion Trigger”
for more information.
OPERATION BLOCK
DIAGRAM
Note:
Removing the Match condition by
changing the contents of the CCPRxH
and CCPRxL register pair, between the
CCPxMODE<3:0>
Mode Select
Set CCPxIF Interrupt Flag
clock
edge
that
generates
the
(PIRx)
Auto-conversion Trigger and the clock
edge that generates the Timer Reset, will
preclude the Reset from occurring.
4
CCPx
Pin
CCPRxH CCPRxL
Comparator
Q
S
R
Output
Logic
Match
29.3.4
COMPARE DURING SLEEP
TMR1H TMR1L
Since FOSC is shut down during Sleep mode, the
Compare mode will not function properly during Sleep,
unless the timer is running. The device will wake on
interrupt (if enabled).
TRIS
Output Enable
Auto-conversion Trigger
29.3.5
COMPARE INTERRUPTS
The CCPxIF interrupt flag will be set when a match
between the CCPRxH:CCPRxL register pair and the
TMR1/3/5H:TMR1/3/5L register pair occurs. If the
device is in Sleep and interrupts are enabled
(CCPxIE = 1), the device will wake up, assuming
Timer1 is operating during Sleep.
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29.4.1
STANDARD PWM OPERATION
29.4 PWM Overview
The standard PWM mode generates a Pulse-Width
Modulation (PWM) signal on the CCPx pin with up to 10
bits of resolution. The period, duty cycle, and resolution
are controlled by the following registers:
Pulse-Width Modulation (PWM) is a scheme that
provides power to a load by switching quickly between
fully on and fully off states. The PWM signal resembles
a square wave where the high portion of the signal is
considered the ON state and the low portion of the
signal is considered the OFF state. The high portion,
also known as the pulse width, can vary in time and is
defined in steps. A larger number of steps applied,
which lengthens the pulse width, also supplies more
power to the load. Lowering the number of steps
applied, which shortens the pulse width, supplies less
power. The PWM period is defined as the duration of
one complete cycle or the total amount of on and off
time combined.
• PR2/4/6 registers
• T2/4/6CON registers
• CCPRxL registers
• CCPxCON registers
Figure 29-4 shows a simplified block diagram of PWM
operation.
Note:
The corresponding TRIS bit must be
cleared to enable the PWM output on the
CCPx pin.
PWM resolution defines the maximum number of steps
that can be present in a single PWM period. A higher
resolution allows for more precise control of the
pulse-width time and in turn the power that is applied to
the load.
FIGURE 29-3:
CCP PWM OUTPUT SIGNAL
Period
The term duty cycle describes the proportion of the on
time to the off time and is expressed in percentages,
where 0% is fully off and 100% is fully on. A lower duty
cycle corresponds to less power applied and a higher
duty cycle corresponds to more power applied.
Pulse Width
TMR2 = PR2
TMR2/4/6 = CCPRxH:CCPRxL
TMR2/4/6 = 0
Figure 29-3 shows a typical waveform of the PWM
signal.
FIGURE 29-4:
SIMPLIFIED PWM BLOCK DIAGRAM
Rev. 10-000157B
2/27/2014
Duty cycle registers
CCPRxH CCPRxL
CCPx_out
To Peripherals
set CCPIF
10-bit Latch(2)
(Not accessible by user)
R
S
Q
Comparator
CCPx
TRIS Control
TMR2 Module
TMR2
R
(1)
ERS logic
CCPx_pset
Comparator
PR2
Notes:
1. 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to
create 10-bit time-base.
2. The alignment of the 10 bits from the CCPR register is determined by the CCPxFMT bit.
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29.4.2
SETUP FOR PWM OPERATION
29.4.4
PWM PERIOD
The following steps should be taken when configuring
the CCP module for standard PWM operation:
The PWM period is specified by the PRx register of
Timer2/4/6. The PWM period can be calculated using
the formula of Equation 29-1.
1. Use the desired output pin RxyPPS control to
select CCPx as the source and disable the
CCPx pin output driver by setting the associated
TRIS bit.
EQUATION 29-1: PWM PERIOD
PWM Period = PR2x + 1 4 TOSC
2. Load the PR2 register with the PWM period
value.
(TMR2/4/6 Prescale Value)
Note:
TOSC = 1/FOSC
3. Configure the CCP module for the PWM mode
by loading the CCPxCON register with the
appropriate values.
When TMR2/4/6 is equal to PR2/4/6, the following
three events occur on the next increment cycle:
4. Load the CCPRxL register and the CCPRxH
register bits, with the PWM duty cycle value and
configure the CCPxFMT bit of the CCPxCON
register to set the proper register alignment.
• TMR2/4/6 is cleared
• The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
• The PWM duty cycle is transferred from the
CCPRxL/H register pair into a 10-bit buffer.
5. Configure and start Timer2, 4 or 6.
• Clear the TMR2/4/6IF interrupt flag bits of
the PIR4 register. See Note below.
Note:
The Timer postscaler (see Section 28.1
“Timer2 Operation”) is not used in the
determination of the PWM frequency.
• Configure the T2/4/6CKPS bits of the
T2/4/6CON register with the Timer
prescale value.
• Enable the Timer by setting the
TMR2/4/6ON bit of the T2/4/6CON
register.
29.4.5
PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit
value to the CCPRxH:CCPRxL register pair. The
alignment of the 10-bit value is determined by the
CCPRxFMT bit of the CCPxCON register (see
Figure 29-5). The CCPRxH:CCPRxL register pair can
be written to at any time; however, the duty cycle value
is not latched into the 10-bit buffer until after a match
between PR2/4/6 and TMR2/4/6.
6. Enable PWM output pin:
• Wait until the Timer overflows and the
TMR2/4/6IF bits of the PIR4 register is set.
See Note below.
• Enable the CCPx pin output driver by
clearing the associated TRIS bit.
Equation 29-2 is used to calculate the PWM pulse
width.
Note:
In order to send a complete duty cycle and
period on the first PWM output, the above
steps must be included in the setup
sequence. If it is not critical to start with a
complete PWM signal on the first output,
then step 6 may be ignored.
Equation 29-3 is used to calculate the PWM duty cycle
ratio.
FIGURE 29-5:
PWM 10-BIT ALIGNMENT
BLOCK DIAGRAM
29.4.3
TIMER2/4/6 TIMER RESOURCE
Rev. 10-000 160A
12/9/201 3
The PWM standard mode makes use of the 8-bit
Timer2/4/6 timer resources to specify the PWM period.
CCPRxH
7 6 5 4 3 2 1 0
CCPRxL
7 6 5 4 3 2 1 0
FMT = 0
CCPRxH
7 6 5 4 3 2 1 0
CCPRxL
7 6 5 4 3 2 1 0
FMT = 1
10-bit Duty Cycle
9 8 7 6 5 4 3 2 1 0
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EQUATION 29-2: PULSE WIDTH
29.4.6
PWM RESOLUTION
PWM resolution, expressed in number of bits, defines
the maximum number of discrete steps that can be
present in a single PWM period. For example, a 10-bit
resolution will result in 1024 discrete steps, whereas an
8-bit resolution will result in 256 discrete steps.
Pulse Width = CCPRxH:CCPRxL register pair
TOSC (TMR2 Prescale Value)
The maximum PWM resolution is ten bits when PRx is
255. The resolution is a function of the PRx register
value as shown by Equation 29-4.
EQUATION 29-3: DUTY CYCLE RATIO
CCPRxH:CCPRxL register pair
Duty Cycle Ratio = ---------------------------------------------------------------------------------
4PR2 + 1
EQUATION 29-4: PWM RESOLUTION
The CCPRxH:CCPRxL register pair and a 2-bit internal
latch are used to double buffer the PWM duty cycle.
This double buffering provides glitchless PWM
operation.
log4PRx + 1
Resolution = ----------------------------------------- bits
log2
The 8-bit timer TMR2/4/6 register is concatenated with
either the 2-bit internal system clock (FOSC), or two bits
of the prescaler, to create the 10-bit time base. The
system clock is used if the Timer2/4/6 prescaler is set to
1:1.
Note:
If the pulse-width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
When the 10-bit time base matches the
CCPRxH:CCPRxL register pair, then the CCPx pin is
cleared (see Figure 29-4).
TABLE 29-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
Timer Prescale
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
PRx Value
0xFF
10
0xFF
10
0x17
6.6
Maximum Resolution (bits)
TABLE 29-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
Timer Prescale
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz 200.0 kHz
16
0x65
8
4
0x65
8
1
0x65
8
1
0x19
6
1
0x0C
5
1
0x09
5
PRx Value
Maximum Resolution (bits)
29.4.7
OPERATION IN SLEEP MODE
29.4.8
CHANGES IN SYSTEM CLOCK
FREQUENCY
In Sleep mode, the TMR2/4/6 register will not incre-
ment and the state of the module will not change. If the
CCPx pin is driving a value, it will continue to drive that
value. When the device wakes up, TMR2/4/6 will
continue from its previous state.
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 7.0 “Oscillator Module” for additional
details.
29.4.9
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
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29.5 Register Definitions: CCP Control
REGISTER 29-1: CCPxCON: CCPx CONTROL REGISTER
R/W-0/0
CCPxEN
U-0
—
R-x/x
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
CCPxOUT
CCPxFMT
CCPxMODE<3:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Reset
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
CCPxEN: CCP Module Enable bit
1= CCP is enabled
0= CCP is disabled
bit 6
bit 5
bit 4
Unimplemented: Read as ‘0’
CCPxOUT: CCPx Output Data (read-only) bit
CCPxFMT: CCPW (pulse width) Alignment bit
CCPxMODE = Capture mode
Unused
CCPxMODE = Compare mode
Unused
CCPxMODE = PWM mode
1= Left-aligned format
0= Right-aligned format
bit 3-0
CCPxMODE<3:0>: CCPx Mode Select bits(1)
1111= PWM mode
1110= Reserved
1101= Reserved
1100= Reserved
1011= Compare mode: output will pulse 0-1-0; Clears TMR1/3/5
1010= Compare mode: output will pulse 0-1-0
1001= Compare mode: clear output on compare match
1000= Compare mode: set output on compare match
0111= Capture mode: every 16th rising edge of CCPx input
0110= Capture mode: every 4th rising edge of CCPx input
0101= Capture mode: every rising edge of CCPx input
0100= Capture mode: every falling edge of CCPx input
0011= Capture mode: every edge of CCPx input
0010= Compare mode: toggle output on match
0001= Compare mode: toggle output on match; clear TMR1/3/5
0000= Capture/Compare/PWM off (resets CCPx module)
Note 1: All modes will set the CCPxIF bit and will trigger an ADC conversion if CCPx is selected as the ADC
trigger source.
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REGISTER 29-2: CCPxCAP: CAPTURE INPUT SELECTION REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/x
R/W-0/x
R/W-0/x
R/W-0/x
CCPxCTS<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Reset
u = Bit is unchanged
‘1’ = Bit is set
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
CCPxCTS<3:0>: CCPx Capture Mode Data Select bits
CCP1CAP
CCP2CAP
CCP3CAP
CCP4CAP
CCAP<3:0>
CAPTURE INPUT CAPTURE INPUT CAPTURE INPUT CAPTURE INPUT
0000
0001
0010
0011
0100
0101
0110
0111
1000
CCP1PPS
CCP2PPS
CCP3PPS
CCP4PPS
C1OUT
C2OUT
NCO1
IOC_interrupt
LC1_output
LC2_output
LC3_output
LC4_output
1001
…
Reserved
1111
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REGISTER 29-3: CCPRxL REGISTER: CCPx REGISTER LOW BYTE
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
CCPRxL<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Reset
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
CCPxMODE = Capture mode
CCPRxL<7:0>: Captured value of TMR1/3/5L
CCPxMODE = Compare mode
CCPRxL<7:0>: LS Byte compared to TMR1/3/5L
CCPxMODE = PWM modes when CCPxFMT = 0
CCPRxL<7:0>: CCPW<7:0> – Pulse-width Least Significant eight bits
CCPxMODE = PWM modes when CCPxFMT = 1
CCPRxL<7:6>: CCPW<1:0> – Pulse-width Least Significant two bits
CCPRxL<5:0>: Not used.
REGISTER 29-4: CCPRxH REGISTER: CCPx REGISTER HIGH BYTE
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
CCPRxH<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Reset
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
CCPxMODE = Capture mode
CCPRxH<7:0>: Captured value of TMR1/3/5H
CCPxMODE = Compare mode
CCPRxH<7:0>: MS Byte compared to TMR1/3/5H
CCPxMODE = PWM modes when CCPxFMT = 0
CCPRxH<7:2>: Not used
CCPRxH<1:0>: CCPW<9:8> – Pulse-width Most Significant two bits
CCPxMODE = PWM modes when CCPxFMT = 1
CCPRxH<7:0>: CCPW<9:2> – Pulse-width Most Significant eight bits
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REGISTER 29-5: CCPTMRS: CCP TIMERS CONTROL REGISTER
R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1
C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0>
R/W-0/0
R/W-1/1
C1TSEL<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Reset
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-4
bit 3-2
bit 1-0
C4TSEL<1:0>: CCP4 Capture, Compare and PWM mode Timer Selection bits
Selection as show in Table 29-4.
C3TSEL<1:0>: CCP3 Capture, Compare and PWM mode Timer Selection bits
Selection as show in Table 29-4.
C2TSEL<1:0>: CCP2 Capture, Compare and PWM mode Timer Selection bits
Selection as show in Table 29-4.
C1TSEL<1:0>: CCP1 Capture, Compare and PWM mode Timer Selection bits
Selection as show in Table 29-4.
TABLE 29-3: TIMER SELECTIONS
CxTSEL<1:0>
Operating mode based on CCPxMODE<3:0>
Capture Compare
PWM
00
01
10
11
TMR0
TMR1
TMR3
TMR5
TMR2
TMR4
TMR6
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TABLE 29-4: SUMMARY OF REGISTERS ASSOCIATED WITH CCPx
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(2)
TRISA
―
―
TRISA5
ANSA5
TRISB5
ANSB5
TRISC5
ANSC5
―
TRISA4
ANSA4
TRISB4
ANSB4
TRISC4
ANSC4
―
―
TRISA2
ANSA2
―
TRISA1
ANSA1
―
TRISA0
ANSA0
―
143
144
ANSELA
TRISB(1)
ANSELB(1)
TRISC
―
―
―
―
TRISB7
ANSB7
TRISB6
ANSB6
149
150
155
157
100
110
105
308
309
310
310
311
162
162
162
162
163
246
229
215
272
273
274
―
―
―
―
TRISC7(1) TRISC6(1)
TRISC3
ANSC3
―
TRISC2
ANSC2
―
TRISC1
ANSC1
―
TRISC0
ANSC0
INTEDG
CCP1IF
CCP1IE
ANSELC
INTCON
PIR4
ANSC7(1)
ANSC6(1)
GIE
PEIE
CWG2IF
CWG2IE
CCPxEN
―
CWG1IF
CWGIE
―
TMR5GIF
TMR5GIE
CCPxOUT
―
TMR5IF
TMR5IE
CCPxFMT
―
CCP4IF
CCP4IE
CCP3IF
CCP3IE
CCP2IF
CCP2IE
PIE4
CCPxCON
CCPxCAP
CCPRxL
CCPRxH
CCPTMRS
CCP1PPS
CCP2PPS
CCP3PPS
CCP4PPS
RxyPPS
ADACT
CCPxMODE<3:0>
CCPxCTS<3:0>
―
CCPRx<7:0>
CCPRx<15:8>
C4TSEL<1:0>
C3TSEL<1:0>
C2TSEL<1:0>
CCP1PPS<4:0>
C1TSEL<1:0>
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
CCP2PPS<4:0>
CCP3PPS<4:0>
CCP4PPS<4:0>
RxyPPS<4:0>
ADACT<4:0>
CLCxSELy
CWGxDAT
MDSRC
LCxDyS<5:0>
―
―
―
―
―
―
DAT<3:0>
MDMS<3:0>
MDCH<3:0>
MDCL<3:0>
MDCARH
MDCARL
Legend:
MDCHPOL MDCHSYNC
MDCLPOL MDCLSYNC
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the CCP module.
Note 1: PIC16(L)F18346 only.
2: Unimplemented, read as ‘1’.
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30.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSPx)
MODULE
Note 1: In devices with more than one MSSP
module, it is very important to pay close
attention to the register names used. A
number placed after the module acronym
is used to distinguish between separate
modules. For example, the SSP1STAT
and SSP2STAT control the same
operational aspects of two completely
different MSSP modules.
30.1 MSSPx Module Overview
The Master Synchronous Serial Port (MSSPx) module
is a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D Converters, etc. The MSSPx
module can operate in one of two modes:
2: Throughout
this
section,
generic
references to the MSSP1 module in any
of its operating modes may be interpreted
as being equally applicable to MSSPx
module. Register names, module
signals, I/O pins, and bit names may use
the generic designator ‘x’ to indicate the
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
The SPI interface supports the following modes and
features:
• Master mode
• Slave mode
• Clock Polarity
use of
a
numeral to distinguish
a
particular module, when required.
• Slave Select Synchronization (Slave mode only)
• Daisy-chain connection of slave devices
Figure 30-1 is a block diagram of the SPI interface
module.
FIGURE 30-1:
MSSP BLOCK DIAGRAM (SPI MODE)
Data Bus
Write
Read
SSPxBUF Reg
SSPxSR Reg
SDI
Shift
Clock
bit 0
SDO
SS
Control
Enable
SS
2 (CKP, CKE)
Clock Select
Edge
Select
SSPM<3:0>
4
T2_match
(
)
2
SCK
TOSC
Prescaler
4, 16, 64
Edge
Select
Baud Rate
Generator
(SSPxADD)
TRIS bit
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The I2C interface supports the following modes and
features:
• Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
• Address masking
• Selectable SDA hold times
Figure 30-2 is a block diagram of the I2C interface
module in Master mode. Figure 30-3 is a diagram of the
I2C interface module in Slave mode.
2
FIGURE 30-2:
MSSP BLOCK DIAGRAM (I C MASTER MODE)
Internal
data bus
[SSPM<3:0>]
Read
Write
SSPxBUF
SSPxSR
Baud Rate
Generator
(SSPxADD)
SDA
Shift
Clock
SDA in
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate (SSPxCON2)
SCL
Start bit detect,
Stop bit detect
SCL in
Bus Collision
Write collision detect
Clock arbitration
State counter for
Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV
Reset SEN, PEN (SSPxCON2)
Set SSPxIF, BCLxIF
end of XMIT/RCV
Address Match detect
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2
FIGURE 30-3:
MSSP BLOCK DIAGRAM (I C SLAVE MODE)
Internal
Data Bus
Read
Write
SSPxBUF Reg
SSPxSR Reg
SCL
SDA
Shift
Clock
MSb
LSb
SSPxMSK Reg
Match Detect
Addr Match
SSPxADD Reg
Set, Reset
S, P bits
(SSPxSTAT Reg)
Start and
Stop bit Detect
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During each SPI clock cycle, a full-duplex data
transmission occurs. This means that while the master
device is sending out the MSb from its shift register (on
its SDO pin) and the slave device is reading this bit and
saving it as the LSb of its shift register, that the slave
device is also sending out the MSb from its shift register
(on its SDO pin) and the master device is reading this
bit and saving it as the LSb of its shift register.
30.2 SPI Mode Overview
The Serial Peripheral Interface (SPI) bus is a
synchronous serial data communication bus that
operates in Full-Duplex mode. Devices communicate
in a master/slave environment where the master device
initiates the communication.
A slave device is
controlled through a Chip Select known as Slave
Select.
After eight bits have been shifted out, the master and
slave have exchanged register values.
The SPI bus specifies four signal connections:
• Serial Clock (SCK)
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Slave Select (SS)
If there is more data to exchange, the shift registers are
loaded with new data and the process repeats itself.
Whether the data is meaningful or not (dummy data),
depends on the application software. This leads to
three scenarios for data transmission:
Figure 30-1 shows the block diagram of the MSSPx
module when operating in SPI mode.
• Master sends useful data and slave sends dummy
data.
The SPI bus operates with a single master device and
one or more slave devices. When multiple slave
devices are used, an independent Slave Select
connection can be used to address each slave
individually.
• Master sends useful data and slave sends useful
data.
• Master sends dummy data and slave sends useful
data.
Figure 30-4 shows a typical connection between a
master device and multiple slave devices.
Transmissions must be performed in multiples of eight
clock pulses. When there is no more data to be
transmitted, the master stops sending the clock signal
and it deselects the slave.
The master selects only one slave at a time. Most slave
devices have tri-state outputs so their output signal
appears disconnected from the bus when they are not
selected.
Every slave device connected to the bus that has not
been selected through its slave select line must disre-
gard the clock and transmission signals and must not
transmit out any data of its own.
Transmissions involve two shift registers, eight bits in
size, one in the master and one in the slave. Data is
always shifted out one bit at a time, with the Most
Significant bit (MSb) shifted out first. At the same time,
a new Least Significant bit (LSb) is shifted into the
same register.
Figure 30-5 shows a typical connection between two
processors configured as master and slave devices.
Data is shifted out of both shift registers on the
programmed clock edge and latched on the opposite
edge of the clock.
The master device transmits information out on its SDO
output pin which is connected to, and received by, the
slave’s SDI input pin. The slave device transmits infor-
mation out on its SDO output pin, which is connected
to, and received by, the master’s SDI input pin.
To begin communication, the master device first sends
out the clock signal. Both the master and the slave
devices should be configured for the same clock polar-
ity.
The master device starts a transmission by sending out
the MSb from its shift register. The slave device reads
this bit from that same line and saves it into the LSb
position of its shift register.
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FIGURE 30-4:
SPI MASTER AND MULTIPLE SLAVE CONNECTION
SCK
SDO
SCK
SDI
SDO
SS
SPI Master
SPI Slave
#1
SDI
General I/O
General I/O
General I/O
SCK
SDI
SDO
SS
SPI Slave
#2
SCK
SDI
SDO
SS
SPI Slave
#3
30.2.1
SPI MODE REGISTERS
30.2.2
SPI MODE OPERATION
The MSSPx module has five registers for SPI mode
operation. These are:
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
• MSSPx STATUS register (SSPxSTAT)
• MSSPx Control register 1 (SSPxCON1)
• MSSPx Control register 3 (SSPxCON3)
• MSSPx Data Buffer register (SSPxBUF)
• MSSPx Address register (SSPxADD)
• MSSPx Shift register (SSPxSR)
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)
(Not directly accessible)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
SSPxCON1 and SSPSTAT are the control and
STATUS registers in SPI mode operation. The
SSPxCON1 register is readable and writable. The
lower six bits of the SSPxSTAT are read-only. The
upper two bits of the SSPxSTAT are read/write.
To enable the serial port, SSP Enable bit, SSPEN of the
SSPxCON1 register, must be set. To reset or reconfig-
ure SPI mode, clear the SSPEN bit, re-initialize the
SSPxCONy registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port
function, some must have their data direction bits (in
the TRIS register) appropriately programmed as
follows:
In one SPI Master mode, SSPxADD can be loaded
with a value used in the Baud Rate Generator. More
information on the Baud Rate Generator is available in
Section 30.7 “Baud Rate Generator”.
SSPxSR is the shift register used for shifting data in
and out. SSPxBUF provides indirect access to the
SSPxSR register. SSPxBUF is the buffer register to
which data bytes are written, and from which data
bytes are read.
• SDI must have corresponding TRIS bit set
• SDO must have corresponding TRIS bit cleared
• SCK (Master mode) must have corresponding
TRIS bit cleared
• SCK (Slave mode) must have corresponding
TRIS bit set
In receive operations, SSPxSR and SSPxBUF
together create a buffered receiver. When SSPxSR
receives a complete byte, it is transferred to SSPxBUF
and the SSPxIF interrupt is set.
• SS must have corresponding TRIS bit set
During transmission, the SSPxBUF is not buffered. A
write to SSPxBUF will write to both SSPxBUF and
SSPxSR.
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
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The MSSPx consists of a transmit/receive shift register
(SSPxSR) and a buffer register (SSPxBUF). The
SSPxSR shifts the data in and out of the device, MSb
first. The SSPxBUF holds the data that was written to
the SSPxSR until the received data is ready. Once the
eight bits of data have been received, that byte is
moved to the SSPxBUF register. Then, the Buffer Full
Detect bit, BF of the SSPxSTAT register, and the
interrupt flag bit, SSPxIF, are set. Any write to the
SSPxBUF register during transmission/reception of
data will be ignored and the write collision detect bit,
WCOL, of the SSPxCON1 register, will be set. User
software must clear the WCOL bit to allow the following
write(s) to the SSPxBUF register to complete
successfully.
When the application software is expecting to receive
valid data, the SSPxBUF should be read before the
next byte of data to transfer is written to the SSPxBUF.
The Buffer Full bit, BF of the SSPxSTAT register,
indicates when SSPxBUF has been loaded with the
received data (transmission is complete). When the
SSPxBUF is read, the BF bit is cleared. This data may
be irrelevant if the SPI is only a transmitter. Generally,
the MSSP interrupt is used to determine when the
transmission/reception has completed. If the interrupt
method is not going to be used, then software polling
can be done to ensure that a write collision does not
occur.
The SSPxSR is not directly readable or writable and
can only be accessed by addressing the SSPxBUF
register.
FIGURE 30-5:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xx
= 1010
SPI Slave SSPM<3:0> = 010x
SDO
SDI
Serial Input Buffer
Serial Input Buffer
(SSPxBUF)
(SSPxBUF)
SDI
SDO
Shift Register
(SSPxSR)
Shift Register
(SSPxSR)
LSb
MSb
MSb
LSb
Serial Clock
SCK
SCK
SS
Slave Select
(optional)
General I/O
Processor 2
Processor 1
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The clock polarity is selected by appropriately
programming the CKP bit of the SSPxCON1 register
and the CKE bit of the SSPxSTAT register. This then,
would give waveforms for SPI communication as
shown in Figure 30-6, Figure 30-8, Figure 30-9 and
Figure 30-10, where the MSB is transmitted first. In
Master mode, the SPI clock rate (bit rate) is user
programmable to be one of the following:
30.2.3
SPI MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK line. The master
determines when the slave (Processor 2, Figure 30-5)
is to broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPxBUF register is written to. If the SPI
is only going to receive, the SDO output could be
disabled (programmed as an input). The SSPxSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPxBUF register as
if a normal received byte (interrupts and Status bits
appropriately set).
• FOSC/4 (or TCY)
• FOSC/16 (or 4 * TCY)
• FOSC/64 (or 16 * TCY)
• Timer2 output/2
• FOSC/(4 * (SPPxADD + 1))
Figure 30-6 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPxBUF is loaded with the received
data is shown.
FIGURE 30-6:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SPPxBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
bit 6
bit 6
bit 2
bit 2
bit 5
bit 5
bit 4
bit 4
bit 1
bit 1
bit 0
bit 0
SDO
(CKE = 0)
bit 7
bit 7
bit 3
bit 3
SDO
(CKE = 1)
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPxIF
SSPxSR to
SSPxBUF
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30.2.4
SPI SLAVE MODE
30.2.5
SLAVE SELECT
SYNCHRONIZATION
In Slave mode, the data is transmitted and received as
external clock pulses appear on SCK. When the last
bit is latched, the SSPxIF interrupt flag bit is set.
The Slave Select can also be used to synchronize
communication. The Slave Select line is held high until
the master device is ready to communicate. When the
Slave Select line is pulled low, the slave knows that a
new transmission is starting.
Before enabling the module in SPI Slave mode, the clock
line must match the proper Idle state. The clock line can
be observed by reading the SCK pin. The Idle state is
determined by the CKP bit of the SSPxCON1 register.
If the slave fails to receive the communication properly,
it will be reset at the end of the transmission, when the
Slave Select line returns to a high state. The slave is
then ready to receive a new transmission when the
Slave Select line is pulled low again. If the Slave Select
line is not used, there is a risk that the slave will
eventually become out of sync with the master. If the
slave misses a bit, it will always be one bit off in future
transmissions. Use of the Slave Select line allows the
slave and master to align themselves at the beginning
of each transmission.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. The shift register is clocked from the SCK pin
input and when a byte is received, the device will
generate an interrupt. If enabled, the device will
wake-up from Sleep.
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPxCON1<3:0> = 0100).
30.2.4.1
Daisy-Chain Configuration
The SPI bus can sometimes be connected in a
daisy-chain configuration. The first slave output is
connected to the second slave input, the second slave
output is connected to the third slave input, and so on.
The final slave output is connected to the master input.
Each slave sends out, during a second group of clock
pulses, an exact copy of what was received during the
first group of clock pulses. The whole chain acts as
one large communication shift register. The
daisy-chain feature only requires a single Slave Select
line from the master device.
When the SS pin is low, transmission and reception are
enabled and the SDO pin is driven.
When the SS pin goes high, the SDO pin is no longer
driven, even if in the middle of a transmitted byte and
becomes a floating output. External pull-up/pull-down
resistors may be desirable depending on the applica-
tion.
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPxCON1<3:0>
0100), the SPI module will reset if the SS
pin is set to VDD.
=
Figure 30-7 shows the block diagram of a typical
daisy-chain connection when operating in SPI mode.
In a daisy-chain configuration, only the most recent
byte on the bus is required by the slave. Setting the
BOEN bit of the SSPxCON3 register will enable writes
to the SSPxBUF register, even if the previous byte has
not been read. This allows the software to ignore data
that may not apply to it.
2: When the SPI is used in Slave mode with
CKE set; the user must enable SS pin
control.
3: While operated in SPI Slave mode the
SMP bit of the SSPxSTAT register must
remain clear.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
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FIGURE 30-7:
SPI DAISY-CHAIN CONNECTION
SCK
SCK
SPI Master
SDO
SDI
SDI
SDO
SS
SPI Slave
#1
General I/O
SCK
SDI
SDO
SS
SPI Slave
#2
SCK
SDI
SDO
SS
SPI Slave
#3
FIGURE 30-8:
SLAVE SELECT SYNCHRONOUS WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Shift register SSPxSR
and bit count are reset
SSPxBUF to
SSPxSR
bit 6
bit 6
bit 7
bit 7
bit 0
SDO
SDI
bit 7
bit 0
bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
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FIGURE 30-9:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Valid
bit 6
bit 2
bit 5
bit 4
bit 3
bit 1
bit 0
SDO
bit 7
SDI
bit 0
bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
Write Collision
detection active
FIGURE 30-10:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPxBUF
Valid
bit 6
bit 3
bit 2
bit 5
bit 4
bit 1
bit 0
SDO
bit 7
bit 7
SDI
bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
Write Collision
detection active
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30.2.6
SPI OPERATION IN SLEEP MODE
FIGURE 30-11:
I C MASTER/
SLAVE CONNECTION
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the
module will resume transmitting and receiving data.
VDD
SCL
SCL
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all eight bits have been received, the
MSSP interrupt flag bit will be set and if enabled, will
wake the device.
VDD
Master
Slave
SDA
SDA
2
30.3 I C Mode Overview
On the last byte of data communicated, the master
device may end the transmission by sending a Stop bit.
If the master device is in Receive mode, it sends a
NACK in place of the last ACK bit. A Stop bit is
indicated by a low-to-high transition of the SDA line
while the SCL line is held high.
The Inter-Integrated Circuit (I2C) bus is a multi-master
serial data communication bus. Devices communicate
in a master/slave environment where the master
devices initiate the communication. A slave device is
controlled through addressing.
The I2C bus specifies two signal connections:
In some cases, the master may want to maintain
control of the bus and re-initiate another transmission.
If so, the master device may send a Restart condition
in place of the Stop bit or last ACK bit when it is in
Receive mode.
• Serial Clock (SCL)
• Serial Data (SDA)
Figure 30-11 shows the block diagram of the MSSPx
module when operating in I2C mode.
The I2C bus specifies three message protocols;
Both the SCL and SDA connections are bidirectional
open-drain lines, each requiring pull-up resistors for the
supply voltage. Pulling the line to ground is considered
a logical zero and letting the line float is considered a
logical one.
• Single message where a master writes data to a
slave.
• Single message where a master reads data from
a slave.
• Combined message where a master initiates a
minimum of two writes, or two reads, or a
combination of writes and reads, to one or more
slaves.
Figure 30-2 and Figure 30-3 show a typical connection
between two processors configured as master and
slave devices.
The I2C bus can operate with one or more master
devices and one or more slave devices.
30.3.1
CLOCK STRETCHING
When a slave device has not completed processing
data, it can delay the transfer of more data through the
process of clock stretching. An addressed slave device
may hold the SCL clock line low after receiving or send-
ing a bit, indicating that it is not yet ready to continue.
The master that is communicating with the slave will
attempt to raise the SCL line in order to transfer the
next bit, but will detect that the clock line has not yet
been released. Because the SCL connection is
open-drain, the slave has the ability to hold that line low
until it is ready to continue communicating.
There are four potential modes of operation for a given
device:
• Master Transmit mode
(master is transmitting data to a slave)
• Master Receive mode
(master is receiving data from a slave)
• Slave Transmit mode
(slave is transmitting data to a master)
• Slave Receive mode
(slave is receiving data from the master)
To begin communication, the master device sends out
a Start condition followed by the address byte of the
slave it intends to communicate with. This is followed
by a single Read/Write bit, which determines whether
the master intends to transmit to or receive data from
the slave device.
Clock stretching allows receivers that cannot keep up
with a transmitter to control the flow of incoming data.
If the requested slave exists on the bus, it will respond
with an Acknowledge bit, otherwise known as an ACK.
The master then continues in either transmit or receive
data from the slave device.
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30.3.2
ARBITRATION
Each master device must monitor the bus for Start and
Stop bits. If the device detects that the bus is busy, it
cannot begin a new message until the bus returns to an
Idle state.
However, two master devices may try to initiate a
transmission on or about the same time. When this
occurs, the process of arbitration begins. Each
transmitter checks the level of the SDA data line and
compares it to the level that it expects to find. The first
transmitter to observe that the two levels do not match,
loses arbitration, and must stop transmitting on the
SDA line.
For example, if one transmitter holds the SDA line to a
logical one (lets it float) and a second transmitter holds
it to a logical zero (pulls it low), the result is that the
SDA line will be low. The first transmitter then observes
that the level of the line is different than expected and
concludes that another transmitter is communicating.
The first transmitter to notice this difference is the one
that loses arbitration and must stop driving the SDA
line. If this transmitter is also a master device, it also
must stop driving the SCL line. It then can monitor the
lines for a Stop condition before trying to reissue its
transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDA line continues with its
original transmission.
Slave Transmit mode can also be arbitrated, when a
master addresses multiple slaves, but this is less
common.
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30.4.4
SDA HOLD TIME
30.4 I C MODE OPERATION
The hold time of the SDA pin is selected by the SDAHT
bit of the SSPxCON3 register. Hold time is the time
SDA is held valid after the falling edge of SCL. Setting
the SDAHT bit selects a longer 300 ns minimum hold
time and may help on buses with large capacitance.
All MSSP I2C communication is byte oriented and
shifted out MSb first. Six SFR registers and two
interrupt flags interface the module with the PIC®
microcontroller and user software. Two pins, SDA and
SCL, are exercised by the module to communicate
with other external I2C devices.
2
TABLE 30-1: I C BUS TERMS
30.4.1
BYTE FORMAT
TERM
Description
All communication in I2C is done in 9-bit segments. A
byte is sent from a master to a slave or vice-versa,
followed by an Acknowledge bit sent back. After the
eighth falling edge of the SCL line, the device output-
ting data on the SDA changes that pin to an input and
reads in an acknowledge value on the next clock
pulse.
Transmitter
The device which shifts data out
onto the bus.
Receiver
Master
The device which shifts data in
from the bus.
The device that initiates a transfer,
generates clock signals and
terminates a transfer.
The clock signal, SCL, is provided by the master. Data
is valid to change while the SCL signal is low, and
sampled on the rising edge of the clock. Changes on
the SDA line while the SCL line is high define special
conditions on the bus, explained below.
Slave
The device addressed by the
master.
Multi-master
Arbitration
A bus with more than one device
that can initiate data transfers.
2
Procedure to ensure that only one
master at a time controls the bus.
Winning arbitration ensures that
the message is not corrupted.
30.4.2
DEFINITION OF I C TERMINOLOGY
There is language and terminology in the description
of I2C communication that have definitions specific to
I2C. That word usage is defined below and may be
used in the rest of this document without explanation.
This table was adapted from the Philips I2C
specification.
Synchronization Procedure to synchronize the
clocks of two or more devices on
the bus.
Idle
No master is controlling the bus,
and both SDA and SCL lines are
high.
30.4.3
SDA AND SCL PINS
When selecting any I2C mode, the SCL and SDA pins
should be set by the user to inputs by setting the
appropriate TRIS bits.
Active
Any time one or more master
devices are controlling the bus.
Addressed
Slave
Slave device that has received a
matching address and is actively
being clocked by a master.
Note:
Any device pin can be selected for SDA
and SCL functions with the PPS
peripheral.
These
functions
are
bidirectional. The SDA input is selected
with the SSPDATPPS registers. The SCL
input is selected with the SSPCLKPPS
registers. Outputs are selected with the
RxyPPS registers. It is the user’s
responsibility to make the selections so
that both the input and the output for each
function is on the same pin.
Matching
Address
Address byte that is clocked into a
slave that matches the value
stored in SPPxADD.
Write Request
Read Request
Slave receives a matching
address with R/W bit clear, and is
ready to clock in data.
Master sends an address byte with
the R/W bit set, indicating that it
wishes to clock data out of the
Slave. This data is the next and all
following bytes until a Restart or
Stop.
Clock Stretching When a device on the bus hold
SCL low to stall communication.
Bus Collision
Any time the SDA line is sampled
low by the module while it is out-
putting and expected high state.
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30.4.5
START CONDITION
30.4.7
RESTART CONDITION
The I2C specification defines a Start condition as a
transition of SDA from a high to a low state while SCL
line is high. A Start condition is always generated by
the master and signifies the transition of the bus from
an Idle to an Active state. Figure 30-12 shows wave
forms for Start and Stop conditions.
A Restart is valid any time that a Stop would be valid.
A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address. The master may want to address the same or
another slave. Figure 30-13 shows the wave form for a
Restart condition.
30.4.6
STOP CONDITION
A Stop condition is a transition of the SDA line from
low-to-high state while the SCL line is high.
In 10-bit Addressing Slave mode a Restart is required
for the master to clock data out of the addressed
slave. Once a slave has been fully addressed, match-
ing both high and low address bytes, the master can
issue a Restart and the high address byte with the
R/W bit set. The slave logic will then hold the clock
and prepare to clock out data.
Note: At least one SCL low time must appear
before a Stop is valid, therefore, if the SDA
line goes low then high again while the SCL
line stays high, only the Start condition is
detected.
30.4.8
START/STOP CONDITION
INTERRUPT MASKING
The SCIE and PCIE bits of the SSPxCON3 register
can enable the generation of an interrupt in Slave
modes that do not typically support this function. Slave
modes where interrupt on Start and Stop detect are
already enabled, these bits will have no effect.
2
FIGURE 30-12:
I C START AND STOP CONDITIONS
SDA
SCL
S
P
Change of
Change of
Data Allowed
Data Allowed
Stop
Start
Condition
Condition
2
FIGURE 30-13:
I C RESTART CONDITION
Sr
Change of
Change of
Data Allowed
Data Allowed
Restart
Condition
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30.4.9
ACKNOWLEDGE SEQUENCE
30.5 I C SLAVE MODE OPERATION
The ninth SCL pulse for any transferred byte in I2C is
dedicated as an Acknowledge. It allows receiving
devices to respond back to the transmitter by pulling
the SDA line low. The transmitter must release control
of the line during this time to shift in the response. The
Acknowledge (ACK) is an active-low signal, pulling the
SDA line low indicates to the transmitter that the
device has received the transmitted data and is ready
to receive more.
The MSSP Slave mode operates in one of four modes
selected by the SSPM bits of SSPxCON1 register. The
modes can be divided into 7-bit and 10-bit Addressing
mode. 10-bit Addressing modes operate the same as
7-bit with some additional overhead for handling the
larger addresses.
Modes with Start and Stop bit interrupts operate the
same as the other modes with SSPxIF additionally
getting set upon detection of a Start, Restart, or Stop
condition.
The result of an ACK is placed in the ACKSTAT bit of
the SSPxCON2 register.
30.5.1
SLAVE MODE ADDRESSES
Slave software, when the AHEN and DHEN bits are
set, the clock is stretched, allowing the slave time to
change the ACK value before it is sent back to the
transmitter. The ACKDT bit of the SSPxCON2 register
is set/cleared to determine the response.
The SSPxADD register (Register 30-6) contains the
Slave mode address. The first byte received after a
Start or Restart condition is compared against the
value stored in this register. If the byte matches, the
value is loaded into the SSPxBUF register and an
interrupt is generated. If the value does not match, the
module goes idle and no indication is given to the
software that anything happened.
There are certain conditions where an ACK will not be
sent by the slave. If the BF bit of the SSPxSTAT
register or the SSPOV bit of the SSPxCON1 register
are set when a byte is received.
When the module is addressed, after the eighth falling
edge of SCL on the bus, the ACKTIM bit of the
SSPxCON3 register is set. The ACKTIM bit indicates
the acknowledge time of the active bus. The ACKTIM
Status bit is only active when the AHEN bit or DHEN
bit is enabled.
The SSP Mask register (Register 30-5) affects the
address matching process. See Section 30.5.9 “SSP
Mask Register” for more information.
2
30.5.1.1
I C Slave 7-bit Addressing Mode
In 7-bit Addressing mode, the LSb of the received data
byte is ignored when determining if there is an address
match.
2
30.5.1.2
I C Slave 10-bit Addressing Mode
In 10-bit Addressing mode, the first received byte is
compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9
and A8 are the two MSb’s of the 10-bit address and
stored in bits 2 and 1 of the SSPxADD register.
After the acknowledge of the high byte the UA bit is set
and SCL is held low until the user updates SSPxADD
with the low address. The low address byte is clocked
in and all eight bits are compared to the low address
value in SSPxADD. Even if there is not an address
match; SSPIF and UA are set, and SCL is held low
until SSPxADD is updated to receive a high byte
again. When SSPxADD is updated the UA bit is
cleared. This ensures the module is ready to receive
the high address byte on the next communication.
A high and low address match as a write request is
required at the start of all 10-bit addressing communi-
cation. A transmission can be initiated by issuing a
Restart once the slave is addressed, and clocking in
the high address with the R/W bit set. The slave
hardware will then acknowledge the read request and
prepare to clock out data. This is only valid for a slave
after it has received a complete high and low address
byte match.
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30.5.2
SLAVE RECEPTION
30.5.2.2
7-bit Reception with AHEN and
DHEN
When the R/W bit of a matching received address byte
is clear, the R/W bit of the SSPxSTAT register is
cleared. The received address is loaded into the
SSPxBUF register and acknowledged.
Slave device reception with AHEN and DHEN set
operate the same as without these options with extra
interrupts and clock stretching added after the eighth
falling edge of SCL. These additional interrupts allow
time for the slave software to decide whether it wants
to ACK the receive address or data byte.
When the Overflow condition exists for a received
address, then not Acknowledge is given. An Overflow
condition is defined as either bit BF of the SSPxSTAT
register is set, or bit SSPOV of the SSPxCON1 register
is set. The BOEN bit of the SSPxCON3 register modi-
fies this operation. For more information see
Register 30-4.
This list describes the steps that need to be taken by
slave software to use these options for I2C communi-
cation. Figure 30-16 displays a module using both
address and data holding. Figure 30-17 includes the
operation with the SEN bit of the SSPxCON2 register
set.
An MSSP interrupt is generated for each transferred
data byte. Flag bit, SSPxIF, must be cleared by
software.
1. S bit of SSPxSTAT is set; SSPxIF is set if
interrupt on Start detect is enabled.
When the SEN bit of the SSPxCON2 register is set,
SCL will be held low (clock stretch) following each
received byte. The clock must be released by setting
the CKP bit of the SSPxCON1 register.
2. Matching address with R/W bit clear is clocked
in. SSPxIF is set and CKP cleared after the
eighth falling edge of SCL.
3. Slave clears the SSPxIF.
30.5.2.1
7-bit Addressing Reception
4. Slave can look at the ACKTIM bit of the
SSPxCON3 register to determine if the SSPxIF
was after or before the ACK.
This section describes a standard sequence of events
for the MSSPx module configured as an I2C slave in
7-bit Addressing mode. Figure 30-14 and Figure 30-15
is used as a visual reference for this description.
5. Slave reads the address value from SSPxBUF,
clearing the BF flag.
This is a step-by-step process of what typically must
be done to accomplish I2C communication.
6. Slave sets ACK value clocked out to the master
by setting ACKDT.
7. Slave releases the clock by setting CKP.
1. Start bit detected.
8. SSPxIF is set after an ACK, not after a NACK.
2. S bit of SSPxSTAT is set; SSPxIF is set if inter-
rupt on Start detect is enabled.
9. If SEN = 1 the slave hardware will stretch the
clock after the ACK.
3. Matching address with R/W bit clear is received.
10. Slave clears SSPxIF.
4. The slave pulls SDA low sending an ACK to the
master, and sets SSPxIF bit.
Note: SSPxIF is still set after the ninth falling edge
of SCL even if there is no clock stretching
and BF has been cleared. Only if NACK is
sent to master is SSPIF not set
5. Software clears the SSPxIF bit.
6. Software reads received address from
SSPxBUF clearing the BF flag.
7. If SEN = 1; Slave software sets CKP bit to
11. SSPxIF set and CKP cleared after eighth falling
edge of SCL for a received data byte.
release the SCL line.
8. The master clocks out a data byte.
12. Slave looks at ACKTIM bit of SSPxCON3 to
determine the source of the interrupt.
9. Slave drives SDA low sending an ACK to the
master, and sets SSPxIF bit.
13. Slave reads the received data from SSPxBUF
clearing BF.
10. Software clears SSPxIF.
11. Software reads the received byte from
SSPxBUF clearing BF.
14. Steps 7-14 are the same for each received data
byte.
12. Steps 8-12 are repeated for all received bytes
from the master.
15. Communication is ended by either the slave
sending an ACK = 1, or the master sending a
Stop condition. If a Stop is sent and Interrupt on
Stop Detect is disabled, the slave will only know
by polling the P bit of the SSPxSTAT register.
13. Master sends Stop condition, setting P bit of
SSPxSTAT, and the bus goes idle.
DS40001839B-page 328
Preliminary
2016-2017 Microchip Technology Inc.
2
FIGURE 30-14:
I C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
Bus Master sends
Stop condition
From Slave to Master
Receiving Data
D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
Receiving Address
Receiving Data
ACK = 1
SDA
A7 A6 A5 A4 A3 A2 A1
ACK
9
SCL
S
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
P
SSPxIF
BF
SSPxIF set on 9th
falling edge of
SCL
Cleared by software
Cleared by software
First byte
of data is
available
SSPxBUF is read
in SSPxBUF
SSPOV
SSPOV set because
SSPxBUF is still full.
ACK is not sent.
2
FIGURE 30-15:
I C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
Bus Master sends
Stop condition
Receive Address
Receive Data
Receive Data
ACK
R/W=0
ACK
9
SDA
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
ACK
SCL
S
SEN
SEN
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
P
1
2
3
4
5
6
7
8
Clock is held low until CKP is set to ‘1’
SSPxIF
SSPxIF set on 9th
falling edge of SCL
Cleared by software
First byte
Cleared by software
SSPxBUF is read
BF
of data is
available
in SSPxBUF
SSPOV
SSPOV set because
SSPxBUF is still full.
ACK is not sent.
CKP
SCL is not held
low because
ACK= 1
CKP is written to ‘1’ in software,
releasing SCL
CKP is written to ‘1’ in software,
releasing SCL
2
FIGURE 30-16:
I C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
Master sends
Stop condition
Master Releases SDA
to slave for ACK sequence
Receiving Address
Receiving Data
Received Data
ACK
SDA
ACK=1
ACK
9
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SCL
S
P
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SSPxIF
If AHEN = 1:
SSPIF is set
SSPxIF is set on
9th falling edge of
No interrupt
Cleared by software
after not ACK
from Slave
SCL, after ACK
BF
Address is
read from
Data is read from SSPxBUF
SSPxBUF
ACKDT
Slave software
clears ACKDT to
Slave software
sets ACKDT to
not ACK
ACK the received
byte
CKP
When AHEN=1:
CKP is cleared by hardware
and SCL is stretched
When DHEN = 1:
CKP is cleared by
hardware on 8th falling
edge of SCL
CKP set by software,
SCL is released
ACKTIM
ACKTIM cleared by
hardware in 9th
rising edge of SCL
ACKTIM set by hardware
on 8th falling edge of SCL
ACKTIM set by hardware
on 8th falling edge of SCL
S
P
2
FIGURE 30-17:
I C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)
Master sends
Stop condition
Master releases
R/W = 0
SDA to slave for ACK sequence
ACK
Receiving Address
Receive Data
Receive Data
SDA
ACK
9
ACK
9
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SCL
S
P
1
2
1
2
3
4
3
4
5
6
7
8
1
2
4
5
6
7
8
5
6
7
8
9
3
SSPxIF
No interrupt after
if not ACK
Cleared by software
from Slave
BF
Received
address is loaded into
SSPxBUF
Received data is
available on SSPxBUF
SSPxBUF can be
read any time before
next byte is loaded
ACKDT
Slave software clears
ACKDT to ACK
the received byte
Slave sends
not ACK
CKP
CKP is not cleared
if not ACK
When AHEN = 1;
When DHEN = 1;
Set by software,
release SCL
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
on the 8th falling edge
of SCL of a received
data byte, CKP is cleared
ACKTIM
ACKTIM is set by hardware
on 8th falling edge of SCL
ACKTIM is cleared by hardware
on 9th rising edge of SCL
S
P
PIC16(L)F18326/18346
30.5.3
SLAVE TRANSMISSION
30.5.3.2
7-bit Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPxSTAT register is set. The received address is
loaded into the SSPxBUF register, and an ACK pulse is
sent by the slave on the ninth bit.
A master device can transmit a read request to a
slave, and then clock data out of the slave. The list
below outlines what software for a slave will need to
do to accomplish
a
standard transmission.
Figure 30-18 can be used as a reference to this list.
Following the ACK, slave hardware clears the CKP bit
and the SCL pin is held low (see Section 30.5.6
“Clock Stretching” for more detail). By stretching the
clock, the master will be unable to assert another clock
pulse until the slave is done preparing the transmit
data.
1. Master sends a Start condition on SDA and
SCL.
2. S bit of SSPxSTAT is set; SSPxIF is set if
interrupt on Start detect is enabled.
3. Matching address with R/W bit set is received by
the Slave setting SSPxIF bit.
The transmit data must be loaded into the SSPxBUF
register which also loads the SSPxSR register. Then
the SCL pin should be released by setting the CKP bit
of the SSPxCON1 register. The eight data bits are
shifted out on the falling edge of the SCL input. This
ensures that the SDA signal is valid during the SCL
high time.
4. Slave hardware generates an ACK and sets
SSPxIF.
5. SSPxIF bit is cleared by user.
6. Software reads the received address from
SSPxBUF, clearing BF.
7. R/W is set so CKP was automatically cleared
after the ACK.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. This ACK
value is copied to the ACKSTAT bit of the SSPxCON2
register. If ACKSTAT is set (not ACK), then the data
transfer is complete. When the not ACK is latched by the
slave, the slave goes idle and waits for another
occurrence of the Start bit. If the SDA line was low
(ACK), the next transmit data must be loaded into the
SSPxBUF register. Again, the SCL pin must be released
by setting bit CKP.
8. The slave software loads the transmit data into
SSPxBUF.
9. CKP bit is set releasing SCL, allowing the
master to clock the data out of the slave.
10. SSPxIF is set after the ACK response from the
master is loaded into the ACKSTAT register.
11. SSPxIF bit is cleared.
12. The slave software checks the ACKSTAT bit to
see if the master wants to clock out more data.
An MSSP interrupt is generated for each data transfer
byte. The SSPxIF bit must be cleared by software and
the SSPxSTAT register is used to determine the status
of the byte. The SSPxIF bit is set on the falling edge of
the ninth clock pulse.
Note 1: If the master ACKs the clock will be
stretched.
2: ACKSTAT is the only bit updated on the
rising edge of SCL (9th) rather than the
falling.
30.5.3.1
Slave Mode Bus Collision
13. Steps 9-13 are repeated for each transmitted
byte.
A slave receives a Read request and begins shifting
data out on the SDA line. If a bus collision is detected
and the SBCDE bit of the SSPxCON3 register is set,
the BCLIF bit of the PIR register is set. Once a bus col-
lision is detected, the slave goes idle and waits to be
addressed again. User software can use the BCLIF bit
to handle a slave bus collision.
14. If the master sends a not ACK; the clock is not
held, but SSPxIF is still set.
15. The master sends a Restart condition or a Stop.
16. The slave is no longer addressed.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 333
2
FIGURE 30-18:
I C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)
Master sends
Stop condition
ACK
9
Receiving Address
Automatic
Transmitting Data
Automatic
Transmitting Data
R/W = 1
ACK
SDA
A7 A6 A5 A4 A3 A2 A1
ACK
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
P
S
SSPxIF
BF
Cleared by software
BF is automatically
cleared after 8th falling
edge of SCL
Data to transmit is
loaded into SSPxBUF
Received address
is read from SSPxBUF
CKP
CKP is not
held for not
ACK
When R/W is set
SCL is always
held low after 9th SCL
Set by software
falling edge
ACKSTAT
Masters not ACK
is copied to
ACKSTAT
R/W
D/A
R/W is copied from the
matching address byte
Indicates an address
has been received
S
P
PIC16(L)F18326/18346
30.5.3.3
7-bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSPxCON3 register
enables additional clock stretching and interrupt
generation after the eighth falling edge of a received
matching address. Once a matching address has
been clocked in, CKP is cleared and the SSPxIF
interrupt is set.
Figure 30-19 displays a standard waveform of a 7-bit
address slave transmission with AHEN enabled.
1. Bus starts Idle.
2. Master sends Start condition; the S bit of
SSPxSTAT is set; SSPxIF is set if interrupt on
Start detect is enabled.
3. Master sends matching address with R/W bit
set. After the eighth falling edge of the SCL line
the CKP bit is cleared and SSPxIF interrupt is
generated.
4. Slave software clears SSPxIF.
5. Slave software reads ACKTIM bit of SSPxCON3
register, and R/W and D/A of the SSPxSTAT
register to determine the source of the interrupt.
6. Slave reads the address value from the
SSPxBUF register clearing the BF bit.
7. Slave software decides from this information if it
wishes to ACK or not ACK and sets the ACKDT
bit of the SSPxCON2 register accordingly.
8. Slave sets the CKP bit releasing SCL.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSPxIF after the ACK if the R/W bit is
set.
11. Slave software clears SSPxIF.
12. Slave loads value to transmit to the master into
SSPxBUF setting the BF bit.
Note: SSPxBUF cannot be loaded until after the
ACK.
13. Slave sets the CKP bit releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the ninth SCL pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSPxCON2 register.
16. Steps 10-15 are repeated for each byte transmit-
ted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note: Master must send a not ACK on the last
byte to ensure that the slave releases the
SCL line to receive a Stop.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 335
2
FIGURE 30-19:
I C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
Master sends
Stop condition
Master releases SDA
to slave for ACK sequence
Receiving Address
Automatic
Transmitting Data
Automatic
ACK
Transmitting Data
R/W = 1
ACK
9
SDA
SCL
ACK
9
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
S
P
SSPxIF
BF
Cleared by software
BF is automatically
cleared after 8th falling
edge of SCL
Received address
Data to transmit is
loaded into SSPxBUF
is read from SSPxBUF
ACKDT
Slave clears
ACKDT to ACK
address
ACKSTAT
CKP
Master’s ACK
response is copied
to SSPxSTAT
When AHEN = 1;
CKP is cleared by hardware
after receiving matching
address.
CKP not cleared
after not ACK
When R/W = 1;
CKP is always
cleared after ACK
Set by software,
releases SCL
ACKTIM
ACKTIM is set on 8th falling
edge of SCL
ACKTIM is cleared
on 9th rising edge of SCL
R/W
D/A
PIC16(L)F18326/18346
30.5.4
SLAVE MODE 10-BIT ADDRESS
RECEPTION
30.5.5
10-BIT ADDRESSING WITH
ADDRESS OR DATA HOLD
This section describes a standard sequence of events
for the MSSPx module configured as an I2C slave in
10-bit Addressing mode.
Reception using 10-bit addressing with AHEN or
DHEN set is the same as with 7-bit modes. The only
difference is the need to update the SSPxADD register
using the UA bit. All functionality, specifically when the
CKP bit is cleared and SCL line is held low are the
same. Figure 30-21 can be used as a reference of a
slave in 10-bit addressing with AHEN set.
Figure 30-20 is used as a visual reference for this
description.
This is a step-by-step process of what must be done
by slave software to accomplish I2C communication.
Figure 30-22 shows a standard waveform for a slave
transmitter in 10-bit Addressing mode.
1. Bus starts Idle.
2. Master sends Start condition; S bit of SSPxSTAT
is set; SSPxIF is set if interrupt on Start detect is
enabled.
3. Master sends matching high address with R/W
bit clear; UA bit of the SSPxSTAT register is set.
4. Slave sends ACK and SSPxIF is set.
5. Software clears the SSPxIF bit.
6. Software reads received address from
SSPxBUF clearing the BF flag.
7. Slave loads low address into SSPxADD,
releasing SCL.
8. Master sends matching low address byte to the
slave; UA bit is set.
Note: Updates to the SSPxADD register are not
allowed until after the ACK sequence.
9. Slave sends ACK and SSPxIF is set.
Note: If the low address does not match, SSPxIF
and UA are still set so that the slave
software can set SSPxADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.
10. Slave clears SSPxIF.
11. Slave reads the received matching address
from SSPxBUF clearing BF.
12. Slave loads high address into SSPxADD.
13. Master clocks a data byte to the slave and
clocks out the slaves ACK on the ninth SCL
pulse; SSPxIF is set.
14. If SEN bit of SSPxCON2 is set, CKP is cleared
by hardware and the clock is stretched.
15. Slave clears SSPxIF.
16. Slave reads the received byte from SSPxBUF
clearing BF.
17. If SEN is set the slave sets CKP to release the
SCL.
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 337
2
FIGURE 30-20:
I C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
Master sends
Stop condition
Receive Data
Receive Second Address Byte
A7 A6 A5 A4 A3 A2 A1 A0
Receive Data
Receive First Address Byte
SDA
0
ACK
9
A9 A8
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
ACK
ACK
9
ACK
9
1
1
1
1
SCL
S
9
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
P
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SCL is held low
while CKP =
0
SSPxIF
Set by hardware
on 9th falling edge
Cleared by software
BF
Data is read
from SSPxBUF
Receive address is
read from SSPxBUF
If address matches
SSPxADD it is loaded into
SSPxBUF
UA
Software updates SSPxADD
and releases SCL
When UA =
1;
SCL is held low
CKP
Set by software,
releasing SCL
When SEN =
CKP is cleared after
9th falling edge of received byte
1;
2
FIGURE 30-21:
I C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)
Receive First Address Byte
Receive Second Address Byte
Receive Data
Receive Data
D7 D6 D5
R/W = 0
SDA
SCL
1
1
1
1
0
A9 A8
ACK
9
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
ACK
9
ACK
9
1
2
3
4
5
6
7
8
UA
1
2
3
4
5
6
7
8
UA
1
2
3
4
5
6
7
8
1
2
S
SSPxIF
Set by hardware
on 9th falling edge
Cleared by software
Cleared by software
BF
ACKDT
UA
SSPxBUF can be
read anytime before
the next received byte
Received data
is read from
SSPxBUF
Slave software clears
ACKDT to ACK
the received byte
Update to SSPxADD is
not allowed until 9th
falling edge of SCL
Update of SSPxADD,
clears UA and releases
SCL
If when AHEN = 1;
CKP
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
Set CKP with software
releases SCL
ACKTIM
ACKTIM is set by hardware
on 8th falling edge of SCL
2
FIGURE 30-22:
I C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
Master sends
Stop condition
Master sends
Restart event
Master sends
not ACK
Receiving Address
Receiving Second Address Byte
Transmitting Data Byte
D7 D6 D5 D4 D3 D2 D1 D0
Receive First Address Byte
ACK = 1
R/W = 0
ACK
9
SDA
1
1
1
1
0
A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
1
1
1
1
0
A9 A8
ACK
ACK
SCL
S
1
6
7
8
9
2
3
4
5
1
1
1
6
7
8
7
8
9
2
3
4
5
2
3
4
5
6
6
7 8
9
2
3
4
5
P
Sr
SSPxIF
BF
Set by hardware
Set by hardware
Cleared by software
SSPxBUF loaded
with received address
Received address is
read from SSPxBUF
Data to transmit is
loaded into SSPxBUF
UA
High address is loaded
back into SSPxADD
UA indicates SSPxADD
must be updated
After SSPxADD is
updated, UA is cleared
and SCL is released
CKP
When R/W = 1;
CKP is cleared on
Set by software
releases SCL
ACKSTAT
9th falling edge of SCL
Masters not ACK
is copied
R/W
D/A
R/W is copied from the
matching address byte
Indicates an address
has been received
PIC16(L)F18326/18346
30.5.6
CLOCK STRETCHING
30.5.6.3
Byte NACKing
Clock stretching occurs when a device on the bus
holds the SCL line low, effectively pausing communi-
cation. The slave may stretch the clock to allow more
time to handle data or prepare a response for the
master device. A master device is not concerned with
stretching as anytime it is active on the bus and not
transferring data it is stretching. Any stretching done
by a slave is invisible to the master software and
handled by the hardware that generates SCL.
When the AHEN bit of SSPxCON3 is set; CKP is
cleared by hardware after the eighth falling edge of
SCL for a received matching address byte. When the
DHEN bit of SSPxCON3 is set; CKP is cleared after
the eighth falling edge of SCL for received data.
Stretching after the eighth falling edge of SCL allows
the slave to look at the received address or data and
decide if it wants to ACK the received data.
30.5.7
CLOCK SYNCHRONIZATION AND
THE CKP BIT
The CKP bit of the SSPxCON1 register is used to
control stretching in software. Any time the CKP bit is
cleared, the module will wait for the SCL line to go low
and then hold it. Setting CKP will release SCL and
allow more communication.
Any time the CKP bit is cleared, the module will wait
for the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
until the SCL output is already sampled low. There-
fore, the CKP bit will not assert the SCL line until an
external I2C master device has already asserted the
SCL line. The SCL output will remain low until the CKP
bit is set and all other devices on the I2C bus have
released SCL. This ensures that a write to the CKP bit
will not violate the minimum high time requirement for
SCL (see Figure 30-23).
30.5.6.1
Normal Clock Stretching
Following an ACK if the R/W bit of SSPxSTAT is set, a
read request, the slave hardware will clear CKP. This
allows the slave time to update SSPxBUF with data to
transfer to the master. If the SEN bit of SSPxCON2 is
set, the slave hardware will always stretch the clock
after the ACK sequence. Once the slave is ready; CKP
is set by software and communication resumes.
30.5.6.2
10-bit Addressing Mode
In 10-bit Addressing mode, when the UA bit is set, the
clock is always stretched. This is the only time the SCL
is stretched without CKP being cleared. SCL is
released immediately after a write to SSPxADD.
Note: Previous versions of the module did not
stretch the clock if the second address byte
did not match.
FIGURE 30-23:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
SCL
DX
DX ‚ – 1
Master device
asserts clock
CKP
Master device
releases clock
WR
SSPxCON1
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 341
PIC16(L)F18326/18346
the R/W bit clear, an interrupt is generated and slave
software can read SSPxBUF and respond.
30.5.8
GENERAL CALL ADDRESS
SUPPORT
Figure 30-24 shows
sequence.
a
general call reception
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually deter-
mines which device will be the slave addressed by the
master device. The exception is the general call
address which can address all devices. When this
address is used, all devices should, in theory, respond
with an acknowledge.
In 10-bit Address mode, the UA bit will not be set on
the reception of the general call address. The slave
will prepare to receive the second byte as data, just as
it would in 7-bit mode.
If the AHEN bit of the SSPxCON3 register is set, just
as with any other address reception, the slave hard-
ware will stretch the clock after the eighth falling edge
of SCL. The slave must then set its ACKDT value and
release the clock with communication progressing as it
would normally.
The general call address is a reserved address in the
I2C protocol, defined as address 0x00. When the
GCEN bit of the SSPxCON2 register is set, the slave
module will automatically ACK the reception of this
address regardless of the value stored in SSPxADD.
After the slave clocks in an address of all zeros with
FIGURE 30-24:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
Address is compared to General Call Address
after ACK, set interrupt
Receiving Data
D5 D4 D3 D2 D1
ACK
9
R/W = 0
ACK
General Call Address
SDA
SCL
D7 D6
D0
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
S
SSPxIF
BF (SSPxSTAT<0>)
Cleared by software
SSPxBUF is read
GCEN (SSPxCON2<7>)
’1’
30.5.9
SSP MASK REGISTER
An SSP Mask (SPPxMSK) register (Register 30-5) is
available in I2C Slave mode as a mask for the value
held in the SSPxSR register during an address
comparison operation. A zero (‘0’) bit in the SSPxMSK
register has the effect of making the corresponding bit
of the received address a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.
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30.6.1
I C MASTER MODE OPERATION
30.6 I C Master Mode
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
Master mode is enabled by setting and clearing the
appropriate SSPM<3:0> bits in the SSPxCON1 register
and by setting the SSPEN bit. In Master mode, the SDA
and SCK pins must be configured as inputs. The MSSP
peripheral hardware will override the output driver TRIS
controls when necessary to drive the pins low.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted eight bits at a time. After each byte is
transmitted, an Acknowledge bit is received. Start and
Stop conditions are output to indicate the beginning
and the end of a serial transfer.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSPx module is disabled.
Control of the I2C bus may be taken when the P bit is
set, or the bus is Idle.
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All
other communication is done by the user software
directly manipulating the SDA and SCL lines.
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received eight bits at a time.
After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
beginning and end of transmission.
The following events will cause the SSP Interrupt Flag
bit, SSPxIF, to be set (SSP interrupt, if enabled):
• Start condition generation
• Stop condition generation
• Data transfer byte transmitted/received
• Acknowledge transmitted/received
• Repeated Start generated
A Baud Rate Generator is used to set the clock
frequency output on SCL. See Section 30.7 “Baud
Rate Generator” for more detail.
Note 1: The MSSPx module, when configured in
I2C Master mode, does not allow queuing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register
to initiate transmission before the Start
condition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a
write to the SSPxBUF did not occur
2: When in Master mode, Start/Stop
detection is masked and an interrupt is
generated when the SEN/PEN bit is
cleared and the generation is complete.
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30.6.2
CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate
Generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPxADD<7:0> and begins count-
ing. This ensures that the SCL high time will always be
at least one BRG rollover count in the event that the
clock is held low by an external device (Figure 30-25).
FIGURE 30-25:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX ‚ – 1
SCL allowed to transition high
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
Reload
30.6.3
WCOL STATUS FLAG
If the user writes the SSPxBUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set it indicates that an action on SSPxBUF
was attempted while the module was not idle.
Note:
Because queuing of events is not allowed,
writing to the lower five bits of SSPxCON2
is disabled until the Start condition is
complete.
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30.6.4
I C MASTER MODE START
CONDITION TIMING
To initiate a Start condition (Figure 30-26), the user
sets the Start Enable bit, SEN bit of the SSPxCON2
register. If the SDA and SCL pins are sampled high,
the Baud Rate Generator is reloaded with the contents
of SSPxADD<7:0> and starts its count. If SCL and
SDA are both sampled high when the Baud Rate
Generator times out (TBRG), the SDA pin is driven low.
The action of the SDA being driven low while SCL is
high is the Start condition and causes the S bit of the
SSPxSTAT register to be set. Following this, the Baud
Rate Generator is reloaded with the contents of
SSPxADD<7:0> and resumes its count. When the
Baud Rate Generator times out (TBRG), the SEN bit of
the SSPxCON2 register will be automatically cleared
by hardware; the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
Note 1: If at the beginning of the Start condition,
the SDA and SCL pins are already
sampled low, or if during the Start condi-
tion, the SCL line is sampled low before
the SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLIF, is set, the Start condition is
aborted and the I2C module is reset into
its idle state.
2: The Philips I2C specification states that a
bus collision cannot occur on a Start.
FIGURE 30-26:
FIRST START BIT TIMING
Set S bit (SSPxSTAT<3>)
Write to SEN bit occurs here
At completion of Start bit,
hardware clears SEN bit
and sets SSPxIF bit
SDA = 1,
SCL = 1
TBRG
TBRG
Write to SSPxBUF occurs here
SDA
2nd bit
1st bit
TBRG
SCL
S
TBRG
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30.6.5
I C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition (Figure 30-27) occurs when
the RSEN bit of the SSPxCON2 register is
programmed high and the master state machine is no
longer active. When the RSEN bit is set, the SCL pin is
asserted low. When the SCL pin is sampled low, the
Baud Rate Generator is loaded and begins counting.
The SDA pin is released (brought high) for one Baud
Rate Generator count (TBRG). When the Baud Rate
Generator times out, if SDA is sampled high, the SCL
pin will be deasserted (brought high). When SCL is
sampled high, the Baud Rate Generator is reloaded
and begins counting. SDA and SCL must be sampled
high for one TBRG. This action is then followed by
assertion of the SDA pin (SDA = 0) for one TBRG while
SCL is high. SCL is asserted low. Following this, the
RSEN bit of the SSPxCON2 register will be
automatically cleared and the Baud Rate Generator will
not be reloaded, leaving the SDA pin held low. As soon
as a Start condition is detected on the SDA and SCL
pins, the S bit of the SSPxSTAT register will be set. The
SSPxIF bit will not be set until the Baud Rate Generator
has timed out.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
•
SDA is sampled low when SCL
goes from low-to-high.
•
SCL goes low before SDA is
asserted low. This may indicate
that another master is attempting
to transmit a data ‘1’.
FIGURE 30-27:
REPEATED START CONDITION WAVEFORM
S bit set by hardware
Write to SSPxCON2
occurs here
SDA = 1,
At completion of Start bit,
hardware clears RSEN bit
and sets SSPxIF
SDA = 1,
SCL = 1
SCL (no change)
TBRG
TBRG
TBRG
1st bit
SDA
SCL
Write to SSPxBUF occurs here
TBRG
Sr
Repeated Start
TBRG
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30.6.6
I C MASTER MODE
30.6.6.3
ACKSTAT Status Flag
TRANSMISSION
In Transmit mode, the ACKSTAT bit of the SSPxCON2
register is cleared when the slave has sent an
Acknowledge (ACK = 0) and is set when the slave
does not Acknowledge (ACK = 1). A slave sends an
Acknowledge when it has recognized its address
(including a general call), or when the slave has
properly received its data.
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPxBUF register. This action will
set the Buffer Full flag bit, BF, and allow the Baud Rate
Generator to begin counting and start the next
transmission. Each bit of address/data will be shifted
out onto the SDA pin after the falling edge of SCL is
asserted. SCL is held low for one Baud Rate Generator
rollover count (TBRG). Data should be valid before SCL
is released high. When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received
properly. The status of ACK is written into the
ACKSTAT bit on the rising edge of the ninth clock. If the
master receives an Acknowledge, the Acknowledge
Status bit, ACKSTAT, is cleared. If not, the bit is set.
After the ninth clock, the SSPIF bit is set and the master
clock (Baud Rate Generator) is suspended until the
next data byte is loaded into the SSPxBUF, leaving
SCL low and SDA unchanged (Figure 30-28).
30.6.6.4
Typical Transmit Sequence
1. The user generates a Start condition by setting
the SEN bit of the SSPxCON2 register.
2. SSPxIF is set by hardware on completion of the
Start.
3. SSPxIF is cleared by software.
4. The MSSPx module will wait the required start
time before any other operation takes place.
5. The user loads the SSPxBUF with the slave
address to transmit.
6. Address is shifted out the SDA pin until all eight
bits are transmitted. Transmission begins as
soon as SSPxBUF is written to.
7. The MSSPx module shifts in the ACK bit from
the slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
8. The MSSPx module generates an interrupt at
the end of the ninth clock cycle by setting the
SSPxIF bit.
After the write to the SSPxBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
release the SDA pin, allowing the slave to respond with
an Acknowledge. On the falling edge of the ninth clock,
the master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT Status bit of the SSPxCON2
register. Following the falling edge of the ninth clock
transmission of the address, the SSPxIF is set, the BF
flag is cleared and the Baud Rate Generator is turned
off until another write to the SSPxBUF takes place,
holding SCL low and allowing SDA to float.
9. The user loads the SSPxBUF with eight bits of
data.
10. Data is shifted out the SDA pin until all eight bits
are transmitted.
11. The MSSPx module shifts in the ACK bit from
the slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
12. Steps 8-11 are repeated for all transmitted data
bytes.
13. The user generates a Stop or Restart condition
by setting the PEN or RSEN bits of the
SSPxCON2 register. Interrupt is generated once
the Stop/Restart condition is complete.
30.6.6.1
BF Status Flag
In Transmit mode, the BF bit of the SSPxSTAT register
is set when the CPU writes to SSPxBUF and is cleared
when all eight bits are shifted out.
30.6.6.2
WCOL Status Flag
If the user writes the SSPxBUF when a transmit is
already in progress (i.e., SSPxSR is still shifting out a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
WCOL must be cleared by software before the next
transmission.
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FIGURE 30-28:
I C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
Write SSPxCON2<0> SEN =
Start condition begins
1
ACKSTAT in
SSPxCON2 = 1
From slave, clear ACKSTAT bit SSPxCON2<6>
Transmitting Data or Second Half
SEN =
0
Transmit Address to Slave
A7 A6 A5 A4 A3 A2 A1
R/W = 0
ACK
of 10-bit Address
SDA
SCL
ACK =
0
D7 D6 D5 D4 D3 D2 D1 D0
SSPxBUF written with 7-bit address and R/W
start transmit
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
P
S
SCL held low
while CPU
responds to SSPxIF
SSPxIF
Cleared by software service routine
from SSP interrupt
Cleared by software
Cleared by software
BF (SSPxSTAT<0>)
SEN
SSPxBUF is written by software
SSPxBUF written
After Start condition, SEN cleared by hardware
PEN
R/W
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30.6.7
I C MASTER MODE RECEPTION
30.6.7.4
Typical Receive Sequence:
Master mode reception (Figure 30-29) is enabled by
programming the Receive Enable bit, RCEN bit of the
SSPxCON2 register.
1. The user generates a Start condition by setting
the SEN bit of the SSPxCON2 register.
2. SSPxIF is set by hardware on completion of the
Start.
Note:
The MSSPx module must be in an Idle
state before the RCEN bit is set or the
RCEN bit will be disregarded.
3. SSPxIF is cleared by software.
4. User writes SSPxBUF with the slave address to
transmit and the R/W bit set.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPxSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the
contents of the SSPxSR are loaded into the SSPxBUF,
the BF flag bit is set, the SSPxIF flag bit is set and the
Baud Rate Generator is suspended from counting,
holding SCL low. The MSSPx is now in Idle state
awaiting the next command. When the buffer is read by
the CPU, the BF flag bit is automatically cleared. The
user can then send an Acknowledge bit at the end of
reception by setting the Acknowledge Sequence
Enable, ACKEN bit of the SSPxCON2 register.
5. Address is shifted out the SDA pin until all eight
bits are transmitted. Transmission begins as
soon as SSPxBUF is written to.
6. The MSSPx module shifts in the ACK bit from
the slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
7. The MSSPx module generates an interrupt at
the end of the ninth clock cycle by setting the
SSPxIF bit.
8. User sets the RCEN bit of the SSPxCON2 regis-
ter and the master clocks in a byte from the slave.
9. After the eighth falling edge of SCL, SSPxIF and
BF are set.
10. Master clears SSPxIF and reads the received
byte from SSPxBUF, clears BF.
30.6.7.1
BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPxBUF from SSPxSR. It
is cleared when the SSPxBUF register is read.
11. Master sets ACK value sent to slave in ACKDT
bit of the SSPxCON2 register and initiates the
ACK by setting the ACKEN bit.
12. Master’s ACK is clocked out to the slave and
SSPxIF is set.
30.6.7.2
SSPOV Status Flag
In receive operation, the SSPOV bit is set when eight
bits are received into the SSPxSR and the BF flag bit is
already set from a previous reception.
13. User clears SSPIF.
14. Steps 8-13 are repeated for each received byte
from the slave.
30.6.7.3
WCOL Status Flag
15. Master sends a not ACK or Stop to end
communication.
If the user writes the SSPxBUF when a receive is
already in progress (i.e., SSPxSR is still shifting in a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
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FIGURE 30-29:
I C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
Write to SSPxCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
Write to SSPxCON2<0>(SEN = 1),
begin Start condition
Set ACKEN, start Acknowledge sequence
ACK from Master
Master configured as a receiver
by programming SSPxCON2<3> (RCEN = 1)
SDA = ACKDT = 0
SDA = ACKDT = 1
SEN = 0
PEN bit = 1
RCEN = 1, start
next receive
RCEN cleared
written here
Write to SPPxBUF occurs here,
RCEN cleared
automatically
ACK from Slave
automatically
start XMIT
Transmit Address to Slave
A7 A6 A5 A4
Receiving Data from Slave
Receiving Data from Slave
ACK
A3 A2 A1
ACK
D5
3
D2
D5
D2
D0
SDA
D7 D6
D4 D3
D1
D7 D6
D4 D3
D1
D0
R/W
ACK
Bus master
terminates
transfer
ACK is not sent
9
7
3
6
9
6
7
8
9
1
2
4
8
5
5
7
8
5
4
1
2
3
4
6
1
2
SCL
S
P
Set SSPIF at end
of receive
Data shifted in on falling edge of CLK
Set SSPxIF interrupt
at end of Acknow-
ledge sequence
Set SSPxIF interrupt
at end of receive
Set SSPxIF interrupt
at end of Acknowledge
sequence
SSPxIF
Set P bit
(SSPxSTAT<4>)
and SSPxIF
Cleared by software
Cleared by software
Cleared by software
Cleared by software
SDA = 0, SCL = 1
while CPU
responds to SSPIF
Cleared in
software
BF
Last bit is shifted into SSPxSR and
contents are unloaded into SSPxBUF
(SSPxSTAT<0>)
SSPOV
SSPOV is set because
SSPxBUF is still full
ACKEN
RCEN
Master configured as a receiver
by programming SSPxCON2<3> (RCEN = 1)
RCEN cleared
automatically
ACK from Master
SDA = ACKDT = 0
RCEN cleared
automatically
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30.6.8
ACKNOWLEDGE SEQUENCE
TIMING
30.6.9
STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN bit of the SSPxCON2 register. At the end of a
receive/transmit, the SCL line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDA line low. When the SDA
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCL pin will be brought high
and one TBRG (Baud Rate Generator rollover count)
later, the SDA pin will be deasserted. When the SDA
pin is sampled high while SCL is high, the P bit of the
SSPxSTAT register is set. A TBRG later, the PEN bit is
cleared and the SSPxIF bit is set (Figure 30-31).
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN bit of the
SSPxCON2 register. When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The Baud
Rate Generator then counts for one rollover period
(TBRG) and the SCL pin is deasserted (pulled high).
When the SCL pin is sampled high (clock arbitration),
the Baud Rate Generator counts for TBRG. The SCL pin
is then pulled low. Following this, the ACKEN bit is auto-
matically cleared, the Baud Rate Generator is turned off
and the MSSPx module then goes into Idle mode
(Figure 30-30).
30.6.9.1
WCOL Status Flag
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
30.6.8.1
WCOL Status Flag
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 30-30:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPxCON2
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
ACK
TBRG
SDA
SCL
D0
8
9
SSPxIF
Cleared in
SSPxIF set at
the end of receive
software
Cleared in
software
SSPxIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
FIGURE 30-31:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1for TBRG, followed by SDA = 1for TBRG
after SDA sampled high. P bit (SSPxSTAT<4>) is set.
Write to SSPxCON2,
set PEN
PEN bit (SSPxCON2<2>) is cleared by
hardware and the SSPxIF bit is set
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
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30.6.10 SLEEP OPERATION
30.6.13 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
While in Sleep mode, the I2C slave module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 30-32).
30.6.11 EFFECTS OF A RESET
A Reset disables the MSSPx module and terminates
the current transfer.
30.6.12 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSPx module is disabled. Control of the I2C bus may
be taken when the P bit of the SSPxSTAT register is
set, or the bus is Idle, with both the S and P bits clear.
When the bus is busy, enabling the SSP interrupt will
generate the interrupt when the Stop condition occurs.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPxBUF can be written to. When the user services
the bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed by
hardware with the result placed in the BCL1IF bit.
If a Start, Repeated Start, Stop or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are deasserted and the respective control bits in
the SSPxCON2 register are cleared. When the user
services the bus collision Interrupt Service Routine and
if the I2C bus is free, the user can resume
communication by asserting a Start condition.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPxIF bit will be set.
A write to the SSPxBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the deter-
mination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPxSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 30-32:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high,
data does not match what is driven
by the master.
Data changes
while SCL = 0
SDA line pulled low
by another source
Bus collision has occurred.
SDA released
by master
SDA
SCL
Set bus collision
interrupt (BCL1IF)
BCL1IF
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If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 30-35). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to zero; if the SCL pin is sampled as ‘0’
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
30.6.13.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the Start condition (Figure 30-33).
b) SCL is sampled low before SDA is asserted low
(Figure 30-34).
During a Start condition, both the SDA and the SCL
pins are monitored.
Note:
The reason that bus collision is not a
factor during a Start condition is that no
two bus masters can assert a Start condi-
tion at the exact same time. Therefore,
one master will always assert SDA before
the other. This condition does not cause a
bus collision because the two masters
must be allowed to arbitrate the first
address following the Start condition. If the
address is the same, arbitration must be
allowed to continue into the data portion,
Repeated Start or Stop conditions.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCL1IF flag is set and
•
the MSSPx module is reset to its Idle state
(Figure 30-33).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded and counts down. If the
SCL pin is sampled low while SDA is high, a bus
collision occurs because it is assumed that another
master is attempting to drive a data ‘1’ during the Start
condition.
FIGURE 30-33:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCL1IF,
S bit and SSPxIF set because
SDA = 0, SCL = 1.
SDA
SCL
SEN
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.
SSP module Reset into Idle state.
SDA sampled low before
Start condition. Set BCL1IF.
S bit and SSPxIF set because
SDA = 0, SCL = 1.
BCL1IF
SSPxIF and BCL1IF are
cleared by software
S
SSPxIF
SSPxIF and BCL1IF are
cleared by software
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FIGURE 30-34:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL
SEN
SCL = 0before SDA = 0,
bus collision occurs. Set BCL1IF.
SCL = 0before BRG time-out,
bus collision occurs. Set BCL1IF.
BCL1IF
Interrupt cleared
by software
S
’0’
’0’
’0’
’0’
SSPxIF
FIGURE 30-35:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Set SSPxIF
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SDA
SCL
S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
’0’
BCL1IF
S
SSPxIF
Interrupts cleared
by software
SDA = 0, SCL = 1,
set SSPxIF
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If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 30-36).
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
30.6.13.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level (Case 1).
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition,
see Figure 30-37.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’ (Case 2).
When the user releases SDA and the pin is allowed to
float high, the BRG is loaded with SSPxADD and
counts down to zero. The SCL pin is then deasserted
and when sampled high, the SDA pin is sampled.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
FIGURE 30-36:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCL1IF and release SDA and SCL.
RSEN
BCL1IF
Cleared by software
’0’
S
’0’
SSPxIF
FIGURE 30-37:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
BCL1IF
RSEN
set BCL1IF. Release SDA and SCL.
Interrupt cleared
by software
’0’
S
SSPxIF
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The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPxADD and
counts down to zero. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 30-38). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 30-39).
30.6.13.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out (Case 1).
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high (Case 2).
FIGURE 30-38:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
low after TBRG,
set BCL1IF
TBRG
TBRG
TBRG
SDA
SDA asserted low
SCL
PEN
BCL1IF
P
’0’
’0’
SSPxIF
FIGURE 30-39:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high,
set BCL1IF
Assert SDA
SCL
PEN
BCL1IF
P
’0’
’0’
SSPxIF
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30.7 Baud Rate Generator
The MSSPx module has a Baud Rate Generator avail-
able for clock generation in both I2C and SPI Master
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSPxADD register (Register 30-6).
When a write occurs to SSPxBUF, the Baud Rate
Generator will automatically begin counting down.
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
An internal signal “Reload” in Figure 30-40 triggers the
value from SSPxADD to be loaded into the BRG
counter. This occurs twice for each oscillation of the
module clock line. The logic dictating when the reload
signal is asserted depends on the mode the MSSPx is
being operated in.
Table 30-4 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SPPxADD.
EQUATION 30-1: BAUD RATE GENERATOR
FOSC
FCLOCK = -------------------------------------------------
SSPxADD + 14
FIGURE 30-40:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
SSPxADD<7:0>
SSPM<3:0>
SCL
Reload
Control
Reload
BRG Down Counter
FOSC/2
SSPxCLK
Note: Values of 0x00, 0x01 and 0x02 are not valid
for SSPxADD when used as a Baud Rate
Generator for I2C. This is an implementation
limitation.
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TABLE 30-2: MSSP CLOCK RATE W/BRG
FCLOCK
(2 Rollovers of BRG)
FOSC
FCY
BRG Value
32 MHz
32 MHz
32 MHz
16 MHz
16 MHz
16 MHz
4 MHz
8 MHz
8 MHz
8 MHz
4 MHz
4 MHz
4 MHz
1 MHz
13h
19h
4Fh
09h
0Ch
27h
09h
400 kHz
308 kHz
100 kHz
400 kHz
308 kHz
100 kHz
100 kHz
Note:
Refer to the I/O port electrical specifications in Table 35-4 to ensure the system is designed to support IOL
requirements.
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30.8 Register Definitions: MSSP Control
REGISTER 30-1: SSPxSTAT: SSP STATUS REGISTER
R/W-0/0
R/W-0/0
CKE(1)
R/HS/HC-0/0 R/HS/HC-0/0 R/HS/HC-0/0 R/HS/HC-0/0
R/HS/HC-0/0 R/HS/HC-0/0
UA BF
SMP
D/A
P(2)
S(2)
R/W
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS/HC = Hardware set/clear
bit 7
SMP: SPI Data Input Sample bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2C Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
CKE: SPI Clock Edge Select bit (SPI mode only)(1)
bit 6
In SPI Master or Slave mode:
1= Transmit occurs on transition from active to Idle clock state
0= Transmit occurs on transition from Idle to active clock state
In I2C mode only:
1= Enable input logic so that thresholds are compliant with SMBus specification
0= Disable SMBus specific inputs
bit 5
bit 4
D/A: Data/Address bit (I2C mode only)
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
P: Stop bit(2)
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1= Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0= Stop bit was not detected last
bit 3
bit 2
S: Start bit (2)
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1= Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0= Start bit was not detected last
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address
match to the next Start bit, Stop bit, or not ACK bit.
In I2C Slave mode:
1= Read
0= Write
In I2C Master mode:
1= Transmit is in progress
0= Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode.
bit 1
bit 0
UA: Update Address bit (10-bit I2C mode only)
1= Indicates that the user needs to update the address in the SPPxADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I2C modes):
1= Receive complete, SSPxBUF is full
0= Receive not complete, SSPxBUF is empty
Transmit (I2C mode only):
1= Data transmit in progress (does not include the ACK and Stop bits), SPPxBUF is full
0= Data transmit complete (does not include the ACK and Stop bits), SPPxBUF is empty
Note 1: Polarity of clock state is set by the CKP bit of the SSPCON register.
2: This bit is cleared on Reset and when SSPEN is cleared.
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REGISTER 30-2: SSPxCON1: SSP CONTROL REGISTER 1
R/C/HS-0/0
WCOL
R/C/HS-0/0
SSPOV(1)
R/W-0/0
SSPEN
R/W-0/0
CKP
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
SSPM<3:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HS = Bit is set by hardware C = User cleared
bit 7
WCOL: Write Collision Detect bit (Transmit mode only)
1= The SPPxBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0= No collision
bit 6
SSPOV: Receive Overflow Indicator bit(1)
In SPI mode:
1= A new byte is received while the SPPxBUF register is still holding the previous data. In case of overflow,
the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read
the SPPxBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit
is not set since each new reception (and transmission) is initiated by writing to the SPPxBUF register
(must be cleared in software).
0= No overflow
In I2C mode:
1= A byte is received while the SPPxBUF register is still holding the previous byte. SSPOV is a “don’t
care” in Transmit mode (must be cleared in software).
0= No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, the following pins must be properly configured as input or output
In SPI mode:
1= Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2)
0= Disables serial port and configures these pins as I/O port pins
In I2C mode:
1= Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3)
0= Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1= Idle state for clock is a high level
0= Idle state for clock is a low level
In I2C Slave mode:
SCL release control
1= Enable clock
0= Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2C Master mode:
Unused in this mode
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REGISTER 30-2: SSPxCON1: SSP CONTROL REGISTER 1 (CONTINUED)
bit 3-0
SSPM<3:0>: Synchronous Serial Port Mode Select bits
1111= I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110= I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1101= Reserved
1100= Reserved
1011= I2C firmware controlled Master mode (slave idle)
1010= SPI Master mode, clock = FOSC/(4 * (SPPxADD+1))(5)
1001= Reserved
1000= I2C Master mode, clock = FOSC / (4 * (SPPxADD+1))(4)
0111= I2C Slave mode, 10-bit address
0110= I2C Slave mode, 7-bit address
0101= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100= SPI Slave mode, clock = SCK pin, SS pin control enabled
0011= SPI Master mode, clock = T2_match/2
0010= SPI Master mode, clock = FOSC/64
0001= SPI Master mode, clock = FOSC/16
0000= SPI Master mode, clock = FOSC/4
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SPPxBUF register.
2: When enabled, these pins must be properly configured as input or output. Use SSP1SSPPS,
SSP1CLKPPS, SSP1DATPPS, and RxyPPS to select the pins.
3: When enabled, the SDA and SCL pins must be configured as inputs. Use SSPxCLKPPS, SSPxDATPPS,
and RxyPPS to select the pins.
4: SPPxADD values of 0, 1 or 2 are not supported for I2C mode.
5: SPPxADD value of 0 is not supported. Use SSPM = 0000instead.
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2
(1)
REGISTER 30-3: SSPxCON2: SSPx CONTROL REGISTER 2 (I C MODE ONLY)
R/W-0/0
GCEN
R/HS/HC-0
ACKSTAT
R/W-0/0
ACKDT
R/S/HC-0/0 R/S/HC-0/0 R/S/HC-0/0
ACKEN RCEN PEN
R/S/HC-0/0 R/S/HC-0/0
RSEN SEN
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HC = Cleared by hardware S = User set
bit 7
bit 6
bit 5
GCEN: General Call Enable bit (in I2C Slave mode only)
1= Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR
0= General call address disabled
ACKSTAT: Acknowledge Status bit (in I2C mode only)
1= Acknowledge was not received
0= Acknowledge was received
ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1= Not Acknowledge
0= Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1= Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0= Acknowledge sequence idle
bit 3
bit 2
bit 1
bit 0
RCEN: Receive Enable bit (in I2C Master mode only)
1= Enables Receive mode for I2C
0= Receive idle
PEN: Stop Condition Enable bit (in I2C Master mode only)
1= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0= Stop condition Idle
RSEN: Repeated Start Condition Enable bit (in I2C Master mode only)
1= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Repeated Start condition Idle
SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Start condition Idle
In Slave mode:
1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0= Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the idle state, these bits may not be
set (no spooling) and the SPPxBUF may not be written.
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REGISTER 30-4: SSPxCON3: SSP CONTROL REGISTER 3
R-0/0
ACKTIM(3)
R/W-0/0
PCIE
R/W-0/0
SCIE
R/W-0/0
BOEN
R/W-0/0
SDAHT
R/W-0/0
SBCDE
R/W-0/0
AHEN
R/W-0/0
DHEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
ACKTIM: Acknowledge Time Status bit (I2C mode only)(3)
1= Indicates the I2C bus is in an Acknowledge sequence, set on eighth falling edge of SCL clock
0= Not an Acknowledge sequence, cleared on ninth rising edge of SCL clock
PCIE: Stop Condition Interrupt Enable bit (I2C mode only)
1= Enable interrupt on detection of Stop condition
0= Stop detection interrupts are disabled(2)
SCIE: Start Condition Interrupt Enable bit (I2C mode only)
1= Enable interrupt on detection of Start or Restart conditions
0= Start detection interrupts are disabled(2)
BOEN: Buffer Overwrite Enable bit
In SPI Slave mode:(1)
1= SPPxBUF updates every time that a new data byte is shifted in ignoring the BF bit
0 = If new byte is received with BF bit of the SSPSTAT register already set, SSPOV bit of the
SSPCON1 register is set, and the buffer is not updated
In I2C Master mode and SPI Master mode:
This bit is ignored.
In I2C Slave mode:
1= SPPxBUF is updated and ACK is generated for a received address/data byte, ignoring the
state of the SSPOV bit only if the BF bit = 0.
0= SPPxBUF is only updated when SSPOV is clear
bit 3
bit 2
SDAHT: SDA Hold Time Selection bit (I2C mode only)
1= Minimum of 300 ns hold time on SDA after the falling edge of SCL
0= Minimum of 100 ns hold time on SDA after the falling edge of SCL
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the
BCL1IF bit of the PIR1 register is set, and bus goes idle
1= Enable slave bus collision interrupts
0= Slave bus collision interrupts are disabled
bit 1
bit 0
AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the eighth falling edge of SCL for a matching received address byte; CKP bit of the
SSPCON1 register will be cleared and the SCL will be held low.
0= Address holding is disabled
DHEN: Data Hold Enable bit (I2C Slave mode only)
1= Following the eighth falling edge of SCL for a received data byte; slave hardware clears the CKP
bit of the SSPCON1 register and SCL is held low.
0= Data holding is disabled
Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to
SPPxBUF.
2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
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REGISTER 30-5: SSPxMSK: SSP MASK REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
SSPxMSK<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-1
bit 0
SSPxMSK<7:1>: Mask bits
1= The received address bit n is compared to SPPxADD<n> to detect I2C address match
0= The received address bit n is not used to detect I2C address match
SSPxMSK<0>: Mask bit for I2C Slave mode, 10-bit Address
I2C Slave mode, 10-bit address (SSPM<3:0> = 0111or 1111):
1= The received address bit 0 is compared to SPPxADD<0> to detect I2C address match
0= The received address bit 0 is not used to detect I2C address match
I2C Slave mode, 7-bit address:
MSK0 bit is ignored.
2
REGISTER 30-6: SSPxADD: MSSP ADDRESS AND BAUD RATE REGISTER (I C MODE)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SSPxADD<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
Master mode:
bit 7-0
SSPxADD<7:0>: Baud Rate Clock Divider bits
SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-bit Slave mode – Most Significant Address Byte:
bit 7-3
Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit
pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1
bit 0
SSPxADD<2:1>: Two Most Significant bits of 10-bit address
Not used: Unused in this mode. Bit state is a “don’t care”.
10-bit Slave mode – Least Significant Address Byte:
bit 7-0
SSPxADD<7:0>: Eight Least Significant bits of 10-bit address
7-bit Slave mode:
bit 7-1
bit 0
SSPxADD<7:1>: 7-bit address
Not used: Unused in this mode. Bit state is a “don’t care”.
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REGISTER 30-7: SSPxBUF: MSSP BUFFER REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
SSPxBUF<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
SSPxBUF<7:0>: MSSP Buffer bits
TABLE 30-3: SUMMARY OF REGISTERS ASSOCIATED WITH MSSPx
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(3)
TRISA
ANSELA
―
―
―
―
TRISA5
ANSA5
TRISA4
ANSA4
―
TRISA2
ANSA2
TRISA1
ANSA1
TRISA0
ANSA0
143
144
146
149
150
152
155
157
159
100
107
102
108
103
359
360
362
363
364
364
365
162
162
162
―
(1)
INLVLA
―
―
INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0
(2)
TRISB
TRISB7
ANSB7
INLVLB7
TRISB6
ANSB6
INLVLB6
TRISB5
ANSB5
TRISB4
ANSB4
―
―
―
―
―
―
―
―
(2)
ANSELB
(2)
INLVLB
TRISC
INLVLB5 INLVLB4
―
―
―
―
(2)
(2)
TRISC7
TRISC6
TRISC5
ANSC5
TRISC4
ANSC4
TRISC3
ANSC3
TRISC2
ANSC2
TRISC1
ANSC1
TRISC0
ANSC0
(2)
(2)
ANSELC
ANSC7
INLVLC7
GIE
ANSC6
INLVLC6
PEIE
(1)
(2)
(2)
INLVLC
INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0
INTCON
―
―
TXIF
―
―
―
INTEDG
TMR1IF
TMR1IE
NCO1IF
NCO1IE
BF
PIR1
TMR1GIF
TMR1GIE
TMR6IF
TMR6IE
SMP
ADIF
RCIF
RCIE
C1IF
SSP1IF
SSP1IE
SSP2IF
SSP2IE
S
BCL1IF
BCL1IE
BCL2IF
BCL2IE
R/W
TMR2IF
TMR2IE
TMR4IF
TMR4IE
UA
PIE1
ADIE
TXIE
NVMIF
NVMIE
P
PIR2
C2IF
PIE2
C2IE
C1IE
SSPxSTAT
SSPxCON1
SSPxCON2
SSPxCON3
SSPxMSK
SSPxADD
SSPxBUF
SSPxCLKPPS
SSPxDATPPS
SSPxSSPPS
CKE
D/A
WCOL
SSPOV
ACKSTAT
PCIE
SSPEN
ACKDT
SCIE
CKP
SSPM<3:0>
GCEN
ACKEN
BOEN
RCEN
PEN
RSEN
AHEN
SEN
ACKTIM
SDAHT
SBCDE
DHEN
SSPxMSK<7:0>
SSPxADD<7:0>
SSPxBUF<7:0>
―
―
―
―
―
―
―
―
―
SSPxCLKPPS<4:0>
SSPxDATPPS<4:0>
SSPxSSPPS<4:0>
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module
2
Note 1: When using designated I C pins, the associated pin values in INLVLx will be ignored.
2: PIC16(L)F18346 only.
3: Unimplemented, read as ‘1’.
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The EUSART1 module includes the following
capabilities:
31.0 ENHANCED UNIVERSAL
SYNCHRONOUS
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
• One-character output buffer
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART1)
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
• Programmable clock polarity in synchronous
modes
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART1) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART1, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
• Sleep operation
system.
Full-Duplex
mode
is
useful
for
The EUSART1 module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
• Automatic detection and calibration of the baud
rate
• Wake-up on Break reception
• 13-bit Break character transmit
Block diagrams of the EUSART1 transmitter and
receiver are shown in Figure 31-1 and Figure 31-2.
The EUSART1 transmit output (TX_out) is available to
the TX/CK pin and internally to the following peripherals:
• Configurable Logic Cell (CLC)
FIGURE 31-1:
EUSART1 TRANSMIT BLOCK DIAGRAM
Data Bus
TXIE
Interrupt
TXIF
TX1REG Register
8
TX/CK pin
MSb
(8)
LSb
0
Pin Buffer
and Control
• • •
Transmit Shift Register (TSR)
TX_out
TXEN
TRMT
Baud Rate Generator
BRG16
FOSC
÷ n
TX9
n
+ 1
Multiplier x4
x16 x64
TX9D
SYNC
BRGH
BRG16
1
X
X
X
1
1
X
1
0
X
0
1
X
0
0
SP1BRGH SP1BRGL
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FIGURE 31-2:
EUSART1 RECEIVE BLOCK DIAGRAM
SPEN
CREN
OERR
RCIDL
RX/DT pin
RSR Register
MSb
Stop (8)
LSb
Start
Pin Buffer
and Control
Data
Recovery
7
1
0
• • •
Baud Rate Generator
FOSC
RX9
÷ n
BRG16
n
+ 1
Multiplier
x4
x16 x64
SYNC
BRGH
BRG16
1
X
1
1
0
1
0
0
0
1
0
0
0
FIFO
SP1BRGH SP1BRGL
X
X
RX9D
FERR
RC1REG Register
8
Data Bus
RCIF
RCIE
Interrupt
The operation of the EUSART1 module is controlled
through three registers:
• Transmit Status and Control (TX1STA)
• Receive Status and Control (RC1STA)
• Baud Rate Control (BAUD1CON)
These registers are detailed in Register 31-1,
Register 31-2 and Register 31-3, respectively.
The RX and CK input pins are selected with the RXPPS
and CKPPS registers, respectively. TX, CK, and DT
output pins are selected with each pin’s RxyPPS register.
Since the RX input is coupled with the DT output in
Synchronous mode, it is the user’s responsibility to select
the same pin for both of these functions when operating
in Synchronous mode. The EUSART1 control logic will
control the data direction drivers automatically.
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31.1.1.2
Transmitting Data
31.1 EUSART1 Asynchronous Mode
A transmission is initiated by writing a character to the
TX1REG register. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TX1REG is immediately
transferred to the TSR register. If the TSR still contains
all or part of a previous character, the new character
data is held in the TX1REG until the Stop bit of the
previous character has been transmitted. The pending
character in the TX1REG is then transferred to the TSR
in one TCY immediately following the Stop bit
transmission. The transmission of the Start bit, data bits
and Stop bit sequence commences immediately
following the transfer of the data to the TSR from the
TX1REG.
The EUSART1 transmits and receives data using the
standard non-return-to-zero (NRZ) format. NRZ is
implemented with two levels: a VOH Mark state which
represents a ‘1’ data bit, and a VOL Space state which
represents a ‘0’ data bit. NRZ refers to the fact that
consecutively transmitted data bits of the same value
stay at the output level of that bit without returning to a
neutral level between each bit transmission. An NRZ
transmission port idles in the Mark state. Each character
transmission consists of one Start bit followed by eight
or nine data bits and is always terminated by one or
more Stop bits. The Start bit is always a space and the
Stop bits are always marks. The most common data
format is eight bits. Each transmitted bit persists for a
period of 1/(Baud Rate). An on-chip dedicated
8-bit/16-bit Baud Rate Generator is used to derive
standard baud rate frequencies from the system
oscillator. See Table 31-3 for examples of baud rate
configurations.
31.1.1.3
Transmit Data Polarity
The polarity of the transmit data can be controlled with
the SCKP bit of the BAUD1CON register. The default
state of this bit is ‘0’ which selects high true transmit idle
and data bits. Setting the SCKP bit to ‘1’ will invert the
transmit data resulting in low true idle and data bits. The
SCKP bit controls transmit data polarity in
Asynchronous mode only. In Synchronous mode, the
SCKP bit has a different function. See Section 31.4.1.2
“Clock Polarity”.
The EUSART1 transmits and receives the LSb first.
The EUSART1’s transmitter and receiver are function-
ally independent, but share the same data format and
baud rate. Parity is not supported by the hardware, but
can be implemented in software and stored as the ninth
data bit.
31.1.1.4
Transmit Interrupt Flag
31.1.1
EUSART1 ASYNCHRONOUS
TRANSMITTER
The TXIF interrupt flag bit of the PIR1 register is set
whenever the EUSART1 transmitter is enabled and no
character is being held for transmission in the TX1REG.
In other words, the TXIF bit is only clear when the TSR
is busy with a character and a new character has been
queued for transmission in the TX1REG. The TXIF flag
bit is not cleared immediately upon writing TX1REG.
TXIF becomes valid in the second instruction cycle
following the write execution. Polling TXIF immediately
following the TX1REG write will return invalid results.
The TXIF bit is read-only, it cannot be set or cleared by
software.
The EUSART1 transmitter block diagram is shown in
Figure 31-1. The heart of the transmitter is the serial
Transmit Shift Register (TSR), which is not directly
accessible by software. The TSR obtains its data from
the transmit buffer, which is the TX1REG register.
31.1.1.1
Enabling the Transmitter
The EUSART1 transmitter is enabled for asynchronous
operations by configuring the following three control
bits:
• TXEN = 1
• SYNC = 0
• SPEN = 1
The TXIF interrupt can be enabled by setting the TXIE
interrupt enable bit of the PIE1 register. However, the
TXIF flag bit will be set whenever the TX1REG is
empty, regardless of the state of TXIE enable bit.
All other EUSART1 control bits are assumed to be in
their default state.
To use interrupts when transmitting data, set the TXIE
bit only when there is more data to send. Clear the
TXIE interrupt enable bit upon writing the last character
of the transmission to the TX1REG.
Setting the TXEN bit of the TX1STA register enables the
transmitter circuitry of the EUSART1. Clearing the
SYNC bit of the TX1STA register configures the
EUSART1 for asynchronous operation. Setting the
SPEN bit of the RC1STA register enables the EUSART1
and automatically configures the TX/CK I/O pin as an
output. If the TX/CK pin is shared with an analog
peripheral, the analog I/O function must be disabled by
clearing the corresponding ANSEL bit.
Note:
The TXIF Transmitter Interrupt flag is set
when the TXEN enable bit is set.
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31.1.1.5
TSR Status
31.1.1.7
Asynchronous Transmission Setup
The TRMT bit of the TX1STA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TX1REG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user has to
poll this bit to determine the TSR status.
1. Initialize the SP1BRGH, SP1BRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 31.3 “EUSART1
Baud Rate Generator (BRG)”).
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If 9-bit transmission is desired, set the TX9
control bit. A set ninth data bit will indicate that
the eight Least Significant data bits are an
address when the receiver is set for address
detection.
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
4. Set SCKP bit if inverted transmit is desired.
31.1.1.6
Transmitting 9-bit Characters
5. Enable the transmission by setting the TXEN
control bit. This will cause the TXIF interrupt bit
to be set.
The EUSART1 supports 9-bit character transmissions.
When the TX9 bit of the TX1STA register is set, the
EUSART1 will shift nine bits out for each character
transmitted. The TX9D bit of the TX1STA register is the
ninth, and Most Significant data bit. When transmitting
9-bit data, the TX9D data bit must be written before
writing the eight Least Significant bits into the TX1REG.
All nine bits of data will be transferred to the TSR shift
register immediately after the TX1REG is written.
6. If interrupts are desired, set the TXIE interrupt
enable bit of the PIE1 register. An interrupt will
occur immediately provided that the GIE and
PEIE bits of the INTCON register are also set.
7. If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
8. Load 8-bit data into the TX1REG register. This
will start the transmission.
A special 9-bit Address mode is available for use with
multiple receivers. See Section 31.1.2.7 “Address
Detection” for more information on the Address mode.
FIGURE 31-3:
ASYNCHRONOUS TRANSMISSION
Write to TX1REG
Word 1
BRG Output
(Shift Clock)
TX/CK
pin
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
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FIGURE 31-4:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TX1REG
Word 2
Start bit
Word 1
SPR1BRG Output
(Shift Clock)
TX/CK
pin
Start bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
Stop bit
Word 2
1 TCY
Word 1
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Transmit Shift Reg.
Note:
This timing diagram shows two consecutive transmissions.
31.1.2
EUSART1 ASYNCHRONOUS
RECEIVER
31.1.2.2
Receiving Data
The receiver data recovery circuit initiates character
reception on the falling edge of the first bit. The first bit,
also known as the Start bit, is always a zero. The data
recovery circuit counts one-half bit time to the center of
the Start bit and verifies that the bit is still a zero. If it is
not a zero then the data recovery circuit aborts
character reception, without generating an error, and
resumes looking for the falling edge of the Start bit. If
the Start bit zero verification succeeds then the data
recovery circuit counts a full bit time to the center of the
next bit. The bit is then sampled by a majority detect
circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
This repeats until all data bits have been sampled and
shifted into the RSR. One final bit time is measured and
the level sampled. This is the Stop bit, which is always
a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
character, otherwise the framing error is cleared for this
character. See Section 31.1.2.4 “Receive Framing
Error” for more information on framing errors.
The Asynchronous mode is typically used in RS-232
systems. The receiver block diagram is shown in
Figure 31-2. The data is received on the RX/DT pin and
drives the data recovery block. The data recovery block
is actually a high-speed shifter operating at 16 times
the baud rate, whereas the serial Receive Shift
Register (RSR) operates at the bit rate. When all eight
or nine bits of the character have been shifted in, they
are immediately transferred to
a two character
First-In-First-Out (FIFO) memory. The FIFO buffering
allows reception of two complete characters and the
start of a third character before software must start
servicing the EUSART1 receiver. The FIFO and RSR
registers are not directly accessible by software.
Access to the received data is via the RC1REG
register.
31.1.2.1
Enabling the Receiver
The EUSART1 receiver is enabled for asynchronous
operation by configuring the following three control bits:
Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
to the EUSART1 receive FIFO and the RCIF interrupt
flag bit of the PIR1 register is set. The top character in
the FIFO is transferred out of the FIFO by reading the
RC1REG register.
• CREN = 1
• SYNC = 0
• SPEN = 1
All other EUSART1 control bits are assumed to be in
their default state.
Note:
If the receive FIFO is overrun, no additional
characters will be received until the
Overrun condition is cleared. See
Section 31.1.2.5 “Receive Overrun
Error” for more information on overrun
errors.
Setting the CREN bit of the RC1STA register enables
the receiver circuitry of the EUSART1. Clearing the
SYNC bit of the TX1STA register configures the
EUSART1 for asynchronous operation. Setting the
SPEN bit of the RC1STA register enables the
EUSART1. The programmer must set the
corresponding TRIS bit to configure the RX/DT I/O pin
as an input.
Note:
If the RX/DT function is on an analog pin,
the corresponding ANSEL bit must be
cleared for the receiver to function.
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31.1.2.3
Receive Interrupts
31.1.2.6
Receiving 9-bit Characters
The RCIF interrupt flag bit of the PIR1 register is set
whenever the EUSART1 receiver is enabled and there
is an unread character in the receive FIFO. The RCIF
interrupt flag bit is read-only, it cannot be set or cleared
by software.
The EUSART1 supports 9-bit character reception.
When the RX9 bit of the RC1STA register is set the
EUSART1 will shift nine bits into the RSR for each
character received. The RX9D bit of the RC1STA reg-
ister is the ninth and Most Significant data bit of the top
unread character in the receive FIFO. When reading
9-bit data from the receive FIFO buffer, the RX9D data
bit must be read before reading the eight Least Signifi-
cant bits from the RC1REG.
RCIF interrupts are enabled by setting all of the
following bits:
• RCIE, Interrupt Enable bit of the PIE1 register
• PEIE, Peripheral Interrupt Enable bit of the
INTCON register
• GIE, Global Interrupt Enable bit of the INTCON
register
31.1.2.7
Address Detection
A special Address Detection mode is available for use
when multiple receivers share the same transmission
line, such as in RS-485 systems. Address detection is
enabled by setting the ADDEN bit of the RC1STA
register.
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.
Address detection requires 9-bit character reception.
When address detection is enabled, only characters
with the ninth data bit set will be transferred to the
receive FIFO buffer, thereby setting the RCIF interrupt
bit. All other characters will be ignored.
31.1.2.4
Receive Framing Error
Each character in the receive FIFO buffer has a
corresponding framing error Status bit. A framing error
indicates that a Stop bit was not seen at the expected
time. The framing error status is accessed via the
FERR bit of the RC1STA register. The FERR bit
represents the status of the top unread character in the
receive FIFO. Therefore, the FERR bit must be read
before reading the RC1REG.
Upon receiving an address character, user software
determines if the address matches its own. Upon
address match, user software must disable address
detection by clearing the ADDEN bit before the next
Stop bit occurs. When user software detects the end of
the message, determined by the message protocol
used, software places the receiver back into the
Address Detection mode by setting the ADDEN bit.
The FERR bit is read-only and only applies to the top
unread character in the receive FIFO. A framing error
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN
bit of the RC1STA register which resets the EUSART1.
Clearing the CREN bit of the RC1STA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note:
If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RC1REG will not clear the FERR bit.
31.1.2.5
Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RC1STA register is
set. The characters already in the FIFO buffer can be
read but no additional characters will be received until
the error is cleared. The error must be cleared by either
clearing the CREN bit of the RC1STA register or by
resetting the EUSART1 by clearing the SPEN bit of the
RC1STA register.
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31.1.2.8
Asynchronous Reception Setup
31.1.2.9
9-bit Address Detection Mode Setup
1. Initialize the SP1BRGH, SP1BRGL register pair
and the BRGH and BRG16 bits to achieve the
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
desired baud rate (see
Section 31.3
“EUSART1 Baud Rate Generator (BRG)”).
1. Initialize the SP1BRGH, SP1BRGL register pair
and the BRGH and BRG16 bits to achieve the
2. Clear the ANSEL bit for the RX pin (if applicable).
3. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
desired baud
“EUSART1 Baud Rate Generator (BRG)”).
rate (see
Section 31.3
2. Clear the ANSEL bit for the RX pin (if applicable).
4. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
3. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
5. If 9-bit reception is desired, set the RX9 bit.
6. Enable reception by setting the CREN bit.
4. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
7. The RCIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCIE interrupt enable bit was also set.
5. Enable 9-bit reception by setting the RX9 bit.
6. Enable address detection by setting the ADDEN
bit.
8. Read the RC1STA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
7. Enable reception by setting the CREN bit.
8. The RCIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will be generated if the RCIE interrupt enable bit
was also set.
9. Get the received eight Least Significant data bits
from the receive buffer by reading the RC1REG
register.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
9. Read the RC1STA register to get the error flags.
The ninth data bit will always be set.
10. Get the received eight Least Significant data bits
from the receive buffer by reading the RC1REG
register. Software determines if this is the
device’s address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
FIGURE 31-5:
ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX/DT pin
bit 7/8
bit 7/8
bit 0 bit 1
Stop
bit
Stop
bit
Stop
bit
bit 0
bit 7/8
Rcv Shift
Reg
Rcv Buffer Reg.
Word 2
RC1REG
Word 1
RC1REG
RCIDL
Read Rcv
Buffer Reg.
RC1REG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RC1REG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
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EXAMPLE 31-1:
CALCULATING BAUD
RATE ERROR
31.2 Clock Accuracy with
Asynchronous Operation
For a device with FOSC of 16 MHz, desired baud rate
of 9600, Asynchronous mode, 8-bit SPR1BRG:
The factory calibrates the internal oscillator block
output (INTOSC). However, the INTOSC frequency
may drift as VDD or temperature changes, and this
directly affects the asynchronous baud rate. Two
methods may be used to adjust the baud rate clock, but
both require a reference clock source of some kind.
FOSC
Desired Baud Rate = -----------------------------------------------------------------------
64[SPBRGH:SPBRGL] + 1
Solving for SP1BRGH:SP1BRGL:
FOSC
---------------------------------------------
Desired Baud Rate
X = --------------------------------------------- – 1
64
The first (preferred) method uses the OSCTUNE
register to adjust the INTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See
Section 7.2.2.3 “Internal Oscillator Frequency
Adjustment” for more information.
16000000
-----------------------
9600
= ----------------------- – 1
64
= 25.042 = 25
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see Section 31.3.1
“Auto-Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
16000000
Calculated Baud Rate = --------------------------
6425 + 1
= 9615
Calc. Baud Rate – Desired Baud Rate
Error = --------------------------------------------------------------------------------------------
Desired Baud Rate
9615 – 9600
= ---------------------------------- = 0 . 1 6 %
9600
31.3 EUSART1 Baud Rate Generator
(BRG)
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART1 operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUD1CON register selects 16-bit
mode.
The SP1BRGH, SP1BRGL register pair determines the
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the
TX1STA register and the BRG16 bit of the BAUD1CON
register. In Synchronous mode, the BRGH bit is ignored.
Table 31-1 contains the formulas for determining the
baud rate. Example 31-1 provides a sample calculation
for determining the baud rate and baud rate error.
Typical baud rates and error values for various
asynchronous modes have been computed for your
convenience and are shown in Table 31-3. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
Writing a new value to the SP1BRGH, SP1BRGL reg-
ister pair causes the BRG timer to be reset (or cleared).
This ensures that the BRG does not wait for a timer
overflow before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is idle before
changing the system clock.
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1/8th the BRG base clock rate. The resulting byte mea-
surement is the average bit time when clocked at full
speed.
31.3.1
AUTO-BAUD DETECT
The EUSART1 module supports automatic detection
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Note 1: If the WUE bit is set with the ABDEN bit,
auto-baud detection will occur on the byte
following the Break character (see
Section 31.3.3
“Auto-Wake-up
on
Break”).
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART1 baud rates are not possible.
Setting the ABDEN bit of the BAUD1CON register
starts the auto-baud calibration sequence. While the
ABD sequence takes place, the EUSART1 state
machine is held in Idle. On the first rising edge of the
receive line, after the Start bit, the SPBRG begins
counting up using the BRG counter clock as shown in
Figure 31-6. The fifth rising edge will occur on the RX
pin at the end of the eighth bit period. At that time, an
accumulated value totaling the proper BRG period is
left in the SP1BRGH, SP1BRGL register pair, the
ABDEN bit is automatically cleared and the RCIF
interrupt flag is set. The value in the RC1REG needs to
be read to clear the RCIF interrupt. RC1REG content
should be discarded. When calibrating for modes that
do not use the SP1BRGH register the user can verify
that the SP1BRGL register did not overflow by
checking for 00h in the SP1BRGH register.
3: During the auto-baud process, the
auto-baud counter starts counting at one.
Upon completion of the auto-baud
sequence, to achieve maximum accuracy,
subtract 1 from the SP1BRGH:SP1BRGL
register pair.
TABLE 31-1:
BRG16 BRGH
BRG COUNTER CLOCK RATES
BRG Base
Clock
BRG ABD
Clock
0
0
0
1
FOSC/64
FOSC/16
FOSC/512
FOSC/128
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 31-1. During ABD,
both the SP1BRGH and SP1BRGL registers are used
as a 16-bit counter, independent of the BRG16 bit set-
ting. While calibrating the baud rate period, the
SP1BRGH and SP1BRGL registers are clocked at
1
1
0
1
FOSC/16
FOSC/4
FOSC/128
FOSC/32
Note:
During the ABD sequence, SP1BRGL and
SP1BRGH registers are both used as a
16-bit counter, independent of the BRG16
setting.
FIGURE 31-6:
AUTOMATIC BAUD RATE CALIBRATION
XXXXh
0000h
001Ch
SPR1BRG Value
Edge #1
bit 1
Edge #2
bit 3
Edge #3
bit 5
Edge #4
bit 7
bit 6
Edge #5
Stop bit
RX pin
Start
bit 0
bit 2
bit 4
SPR1BRG Clock
Auto Cleared
Set by User
ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RC1REG
XXh
XXh
1Ch
00h
SP1BRGL
SP1BRGH
Note 1: The ABD sequence requires the EUSART1 module to be configured in Asynchronous mode.
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31.3.2
AUTO-BAUD OVERFLOW
31.3.3.1
Special Considerations
During the course of automatic-baud detection, the
ABDOVF bit of the BAUDxCON register will be set if
the baud rate counter overflows before the fifth rising
edge is detected on the RX pin. The ABDOVF bit
indicates that the counter has exceeded the maximum
count that can fit in the 16 bits of the
SPxBRGH:SPxBRGL register pair. The Overflow
condition will set the RCIF flag. The counter continues
to count until the fifth rising edge is detected on the RX
pin. The RCIDL bit will remain false (‘0’) until the fifth
rising edge at which time the RCIDL bit will be set. If the
RCREG is read after the overflow occurs but before the
fifth rising edge, then the fifth rising edge will set the
RCIF again.
Break Character
To avoid character errors or character fragments during
a wake-up event, the wake-up character must be all
zeros.
When the wake-up is enabled the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Therefore, the initial character in the transmission must
be all ‘0’s. This must be ten or more bit times, 13-bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
Terminating the auto-baud process early to clear an
Overflow condition will prevent proper detection of the
sync character fifth rising edge. If any falling edges of
the sync character have not yet occurred when the
ABDEN bit is cleared, then those will be falsely
detected as Start bits. The following steps are
recommended to clear the Overflow condition:
Oscillator Start-up Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected oscillator
to start and provide proper initialization of the
EUSART1.
1. Read RCREG to clear RCIF
2. If RCIDL is zero, then wait for RCIF and repeat
step 1
3. Clear the ABDOVF bit
31.3.3
AUTO-WAKE-UP ON BREAK
WUE Bit
During Sleep mode, all clocks to the EUSART1 are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper character reception cannot be
performed. The Auto-Wake-up feature allows the
controller to wake-up due to activity on the RX/DT line.
This feature is available only in Asynchronous mode.
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared in
hardware by a rising edge on RX/DT. The Interrupt
condition is then cleared in software by reading the
RC1REG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
The Auto-Wake-up feature is enabled by setting the
WUE bit of the BAUD1CON register. Once set, the
normal receive sequence on RX/DT is disabled, and the
EUSART1 remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on the
RX/DT line. (This coincides with the start of a Sync Break
or a wake-up signal character for the LIN protocol.)
The EUSART1 module generates an RCIF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 31-7), and asynchronously if
the device is in Sleep mode (Figure 31-8). The Interrupt
condition is cleared by reading the RC1REG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART1 module is in Idle mode waiting to
receive the next character.
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FIGURE 31-7:
AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3Q4
OSC1
Auto Cleared
Bit set by user
WUE bit
RX/DT Line
RCIF
Cleared due to User Read of RC1REG
Note 1: The EUSART1 remains in Idle while the WUE bit is set.
FIGURE 31-8:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q4
Q1Q2Q3 Q4 Q1Q2 Q3Q4 Q1Q2Q3
Q1
Q2 Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4
Auto Cleared
OSC1
Bit Set by User
WUE bit
RX/DT Line
Note 1
RCIF
Cleared due to User Read of RC1REG
Sleep Command Executed
Sleep Ends
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposcsignal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART1 remains in Idle while the WUE bit is set.
31.3.4
BREAK CHARACTER SEQUENCE
31.3.4.1
Break and Sync Transmit Sequence
The EUSART1 module has the capability of sending
the special Break character sequences that are
required by the LIN bus standard. A Break character
consists of a Start bit, followed by 12 ‘0’ bits and a Stop
bit.
The following sequence will start a message frame
header made up of a Break, followed by an auto-baud
Sync byte. This sequence is typical of a LIN bus
master.
1. Configure the EUSART1 for the desired mode.
To send a Break character, set the SENDB and TXEN
bits of the TX1STA register. The Break character trans-
mission is then initiated by a write to the TX1REG. The
value of data written to TX1REG will be ignored and all
‘0’s will be transmitted.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TX1REG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TX1REG to load the Sync charac-
ter into the transmit FIFO buffer.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
5. After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
When the TX1REG becomes empty, as indicated by
the TXIF, the next data byte can be written to TX1REG.
The TRMT bit of the TX1STA register indicates when the
transmit operation is active or idle, just as it does during
normal transmission. See Figure 31-9 for the timing of
the Break character sequence.
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31.3.5
RECEIVING A BREAK CHARACTER
The Enhanced EUSART1 module can receive a Break
character in two ways.
The first method to detect a Break character uses the
FERR bit of the RC1STA register and the received data
as indicated by RC1REG. The Baud Rate Generator is
assumed to have been initialized to the expected baud
rate.
A Break character has been received when:
• RCIF bit is set
• FERR bit is set
• RC1REG = 00h
The second method uses the Auto-Wake-up feature
described in Section 31.3.3 “Auto-Wake-up on
Break”. By enabling this feature, the EUSART1 will
sample the next two transitions on RX/DT, cause an
RCIF interrupt, and receive the next data byte followed
by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Detect feature.
For both methods, the user can set the ABDEN bit of
the BAUD1CON register before placing the EUSART1
in Sleep mode.
FIGURE 31-9:
SEND BREAK CHARACTER SEQUENCE
Write to TX1REG
Dummy Write
SPR1BRG Output
(Shift Clock)
TX (pin)
Start bit
bit 0
bit 1
Break
bit 11
Stop bit
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB Sampled Here
Auto Cleared
SENDB
(send Break
control bit)
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31.4.1.2
Clock Polarity
31.4 EUSART1 Synchronous Mode
A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the SCKP
bit of the BAUD1CON register. Setting the SCKP bit
sets the clock Idle state as high. When the SCKP bit is
set, the data changes on the falling edge of each clock.
Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cleared, the data changes on the rising
edge of each clock.
Synchronous serial communications are typically used
in systems with a single master and one or more
slaves. The master device contains the necessary
circuitry for baud rate generation and supplies the clock
for all devices in the system. Slave devices can take
advantage of the master clock by eliminating the
internal clock generation circuitry.
There are two signal lines in Synchronous mode: a
bidirectional data line and a clock line. Slaves use the
external clock supplied by the master to shift the serial
data into and out of their respective receive and trans-
mit shift registers. Since the data line is bidirectional,
synchronous operation is half-duplex only. Half-duplex
refers to the fact that master and slave devices can
receive and transmit data but not both simultaneously.
The EUSART1 can operate as either a master or slave
device.
31.4.1.3
Synchronous Master Transmission
Data is transferred out of the device on the RX/DT pin.
The RX/DT and TX/CK pin output drivers are automat-
ically enabled when the EUSART1 is configured for
synchronous master transmit operation.
A transmission is initiated by writing a character to the
TX1REG register. If the TSR still contains all or part of
a previous character the new character data is held in
the TX1REG until the last bit of the previous character
has been transmitted. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TX1REG is immediately trans-
ferred to the TSR. The transmission of the character
commences immediately following the transfer of the
data to the TSR from the TX1REG.
Start and Stop bits are not used in synchronous
transmissions.
31.4.1
SYNCHRONOUS MASTER MODE
The following bits are used to configure the EUSART1
for synchronous master operation:
• SYNC = 1
• CSRC = 1
• SREN = 0(for transmit); SREN = 1(for receive)
• CREN = 0(for transmit); CREN = 1(for receive)
• SPEN = 1
Each data bit changes on the leading edge of the
master clock and remains valid until the subsequent
leading clock edge.
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
Setting the SYNC bit of the TX1STA register configures
the device for synchronous operation. Setting the CSRC
bit of the TX1STA register configures the device as a
master. Clearing the SREN and CREN bits of the
RC1STA register ensures that the device is in the
Transmit mode, otherwise the device will be configured
to receive. Setting the SPEN bit of the RC1STA register
enables the EUSART1.
31.4.1.4
Synchronous Master Transmission
Setup
1. Initialize the SP1BRGH, SP1BRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud
rate (see
Section 31.3
“EUSART1 Baud Rate Generator (BRG)”).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
31.4.1.1
Master Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device config-
ured as a master transmits the clock on the TX/CK line.
The TX/CK pin output driver is automatically enabled
when the EUSART1 is configured for synchronous
transmit or receive operation. Serial data bits change
on the leading edge to ensure they are valid at the
trailing edge of each clock. One clock cycle is gener-
ated for each data bit. Only as many clock cycles are
generated as there are data bits.
3. Disable Receive mode by clearing bits SREN
and CREN.
4. Enable Transmit mode by setting the TXEN bit.
5. If 9-bit transmission is desired, set the TX9 bit.
6. If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in the TX9D bit.
8. Start transmission by loading data to the
TX1REG register.
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FIGURE 31-10:
SYNCHRONOUS TRANSMISSION
RX/DT
pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
Word 1
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
TX1REG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’
‘1’
TXEN bit
Note:
Sync Master mode, SP1BRGL = 0, continuous transmission of two 8-bit words.
FIGURE 31-11:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX/DT pin
bit 0
bit 2
bit 1
bit 6
bit 7
TX/CK pin
Write to
TX1REG reg
TXIF bit
TRMT bit
TXEN bit
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
received into the RSR, the RCIF bit is set and the char-
acter is automatically transferred to the two character
receive FIFO. The Least Significant eight bits of the top
character in the receive FIFO are available in RC1REG.
The RCIF bit remains set as long as there are unread
characters in the receive FIFO.
31.4.1.5
Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT pin
output driver is automatically disabled when the
EUSART1 is configured for synchronous master
receive operation.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RC1STA register) or the Continuous Receive Enable
bit (CREN of the RC1STA register).
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character. The SREN bit is automatically cleared
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial charac-
ter is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.
Note:
If the RX/DT function is on an analog pin,
the corresponding ANSEL bit must be
cleared for the receiver to function.
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character received. The RX9D bit of the RC1STA
register is the ninth, and Most Significant, data bit of the
top unread character in the receive FIFO. When read-
ing 9-bit data from the receive FIFO buffer, the RX9D
data bit must be read before reading the eight Least
Significant bits from the RC1REG.
31.4.1.6
Slave Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a slave receives the clock on the TX/CK line. The
TX/CK pin output driver is automatically disabled when
the device is configured for synchronous slave transmit
or receive operation. Serial data bits change on the
leading edge to ensure they are valid at the trailing edge
of each clock. One data bit is transferred for each clock
cycle. Only as many clock cycles should be received as
there are data bits.
31.4.1.9
Synchronous Master Reception
Setup
1. Initialize the SP1BRGH, SP1BRGL register pair
for the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
Note:
If the device is configured as a slave and
the TX/CK function is on an analog pin, the
corresponding ANSEL bit must be cleared.
2. Clear the ANSEL bit for the RX pin (if applicable).
3. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
31.4.1.7
Receive Overrun Error
4. Ensure bits CREN and SREN are clear.
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RC1REG is read to access
the FIFO. When this happens the OERR bit of the
RC1STA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the Overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RC1REG. If the overrun occurred when the CREN bit is
set then the Error condition is cleared by either clearing
the CREN bit of the RC1STA register or by clearing the
SPEN bit which resets the EUSART1.
5. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
6. If 9-bit reception is desired, set bit RX9.
7. Start reception by setting the SREN bit or for
continuous reception, set the CREN bit.
8. Interrupt flag bit RCIF will be set when reception
of a character is complete. An interrupt will be
generated if the enable bit RCIE was set.
9. Read the RC1STA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RC1REG register.
11. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RC1STA
register or by clearing the SPEN bit which resets
the EUSART1.
31.4.1.8
Receiving 9-bit Characters
The EUSART1 supports 9-bit character reception.
When the RX9 bit of the RC1STA register is set the
EUSART1 will shift nine bits into the RSR for each
FIGURE 31-12:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
‘0’
‘0’
CREN bit
RCIF bit
(Interrupt)
Read
RC1REG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.
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31.4.2
SYNCHRONOUS SLAVE MODE
31.4.2.3
EUSART1 Synchronous Slave
Reception
The following bits are used to configure the EUSART1
for synchronous slave operation:
The operation of the Synchronous Master and Slave
modes is identical (Section 31.4.1.5 “Synchronous
Master Reception”), with the following exceptions:
• SYNC = 1
• CSRC = 0
• SREN = 0(for transmit); SREN = 1(for receive)
• CREN = 0(for transmit); CREN = 1(for receive)
• SPEN = 1
• Sleep
• CREN bit is always set, therefore the receiver is
never idle
• SREN bit, which is a “don’t care” in Slave mode
Setting the SYNC bit of the TX1STA register configures
the device for synchronous operation. Clearing the
CSRC bit of the TX1STA register configures the device
as a slave. Clearing the SREN and CREN bits of the
RC1STA register ensures that the device is in the
Transmit mode, otherwise the device will be configured to
receive. Setting the SPEN bit of the RC1STA register
enables the EUSART1.
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RC1REG register. If the RCIE enable bit is set,
the interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
31.4.2.1
EUSART1 Synchronous Slave
Transmit
31.4.2.4
Synchronous Slave Reception Setup
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
The operation of the Synchronous Master and Slave
modes are identical (see Section 31.4.1.3
“Synchronous Master Transmission”), except in the
2. Clear the ANSEL bit for both the CK and DT pins
(if applicable).
case of the Sleep mode.
3. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If two words are written to the TX1REG and then the
SLEEPinstruction is executed, the following will occur:
4. If 9-bit reception is desired, set the RX9 bit.
5. Set the CREN bit to enable reception.
1. The first character will immediately transfer to
the TSR register and transmit.
2. The second word will remain in the TX1REG
register.
6. The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
3. The TXIF bit will not be set.
7. If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RC1STA
register.
4. After the first character has been shifted out of
TSR, the TX1REG register will transfer the
second character to the TSR and the TXIF bit will
now be set.
8. Retrieve the eight Least Significant bits from the
receive FIFO by reading the RC1REG register.
5. If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RC1STA
register or by clearing the SPEN bit which resets
the EUSART1.
31.4.2.2
Synchronous Slave Transmission
Setup
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. Clear the ANSEL bit for the CK pin (if applicable).
3. Clear the CREN and SREN bits.
4. If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
5. If 9-bit transmission is desired, set the TX9 bit.
6. Enable transmission by setting the TXEN bit.
7. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
8. Start transmission by writing the Least
Significant eight bits to the TX1REG register.
2016-2017 Microchip Technology Inc.
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31.5.2
SYNCHRONOUS TRANSMIT
DURING SLEEP
31.5 EUSART1 Operation During Sleep
The EUSART1 will remain active during Sleep only in
the Synchronous Slave mode. All other modes require
the system clock and therefore cannot generate the
necessary signals to run the Transmit or Receive Shift
registers during Sleep.
To transmit during Sleep, all the following conditions
must be met before entering Sleep mode:
• The RC1STA and TX1STA Control registers must
be configured for synchronous slave transmission
(see Section 31.4.2.2 “Synchronous Slave
Transmission Setup”).
Synchronous Slave mode uses an externally generated
clock to run the Transmit and Receive Shift registers.
• The TXIF interrupt flag must be cleared by writing
the output data to the TX1REG, thereby filling the
TSR and transmit buffer.
• If interrupts are desired, set the TXIE bit of the
PIE1 register and the PEIE bit of the INTCON
register.
31.5.1
SYNCHRONOUS RECEIVE DURING
SLEEP
To receive during Sleep, all the following conditions
must be met before entering Sleep mode:
• RC1STA and TX1STA Control registers must be
configured for Synchronous Slave Reception (see
Section 31.4.2.4 “Synchronous Slave Recep-
tion Setup”).
• If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
• The RCIF interrupt flag must be cleared by read-
ing RC1REG to unload any pending characters in
the receive buffer.
• Interrupt enable bits TXIE of the PIE1 register and
PEIE of the INTCON register must set.
Upon entering Sleep mode, the device will be ready to
accept clocks on TX/CK pin and transmit data on the
RX/DT pin. When the data word in the TSR has been
completely clocked out by the external device, the
pending byte in the TX1REG will transfer to the TSR
and the TXIF flag will be set. Thereby, waking the pro-
cessor from Sleep. At this point, the TX1REG is avail-
able to accept another character for transmission,
which will clear the TXIF flag.
Upon entering Sleep mode, the device will be ready to
accept data and clocks on the RX/DT and TX/CK pins,
respectively. When the data word has been completely
clocked in by the external device, the RCIF interrupt
flag bit of the PIR1 register will be set. Thereby, waking
the processor from Sleep.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit is also set then the Interrupt
Service Routine at address 0004h will be called.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit of the INTCON register is
also set, then the Interrupt Service Routine at address
004h will be called.
DS40001839B-page 382
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PIC16(L)F18326/18346
31.6 Register Definitions: EUSART1 Control
REGISTER 31-1: TX1STA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0/0
CSRC
R/W-0/0
TX9
R/W-0/0
TXEN(1)
R/W-0/0
SYNC
R/W-0/0
SENDB
R/W-0/0
BRGH
R-1/1
R/W-0/0
TX9D
TRMT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Unused in this mode – value ignored
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
bit 4
bit 3
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit(1)
1= Transmit enabled
0= Transmit disabled
SYNC: EUSART1 Mode Select bit
1= Synchronous mode
0= Asynchronous mode
SENDB: Send Break Character bit
Asynchronous mode:
1= Send SYNCH BREAK on next transmission – Start bit, followed by 12 ‘0’ bits, followed by Stop
bit; cleared by hardware upon completion
0= SYNCH BREAK transmission disabled or completed
Synchronous mode:
Unused in this mode – value ignored
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode – value ignored
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
2016-2017 Microchip Technology Inc.
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REGISTER 31-2: RC1STA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0/0
SPEN(1)
R/W-0/0
RX9
R/W-0/0
SREN
R/W-0/0
CREN
R/W-0/0
ADDEN
R-0/0
R-0/0
R-x/x
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit(1)
1= Serial port enabled
0= Serial port disabled (held in Reset)
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Unused in this mode – value ignored
Synchronous mode – Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Unused in this mode – value ignored
CREN: Continuous Receive Enable bit
Asynchronous mode:
bit 4
1= Enables continuous receive until enable bit CREN is cleared
0= Disables continuous receive
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection – enable interrupt and load of the receive buffer when the ninth bit in
the receive buffer is set
0= Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Unused in this mode – value ignored
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RC1REG register and receive next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
Note 1: The EUSART1 module automatically changes the pin from tri-state to drive as needed. Configure the
associated TRIS bits for TX/CK and RX/DT to 1.
DS40001839B-page 384
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REGISTER 31-3: BAUD1CON: BAUD RATE CONTROL REGISTER
R-0/0
R-1/1
U-0
—
R/W-0/0
SCKP
R/W-0/0
BRG16
U-0
—
R/W-0/0
WUE
R/W-0/0
ABDEN
ABDOVF
RCIDL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
ABDOVF: Auto-Baud Detect Overflow bit
Asynchronous mode:
1= Auto-baud timer overflowed
0= Auto-baud timer did not overflow
Synchronous mode:
Don’t care
RCIDL: Receive Idle Flag bit
Asynchronous mode:
1= Receiver is Idle
0= Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care
bit 5
bit 4
Unimplemented: Read as ‘0’
SCKP: Clock/Transmit Polarity Select bit
Asynchronous mode:
1= Idle state for transmit (TX) is a low level
0= Idle state for transmit (TX) is a high level
Synchronous mode:
1= Idle state for clock (CK) is a high level
0= Idle state for clock (CK) is a low level
bit 3
BRG16: 16-bit Baud Rate Generator bit
1= 16-bit Baud Rate Generator is used
0= 8-bit Baud Rate Generator is used
bit 2
bit 1
Unimplemented: Read as ‘0’
WUE: Wake-up Enable bit
Asynchronous mode:
1= EUSART will continue to sample the Rx pin – interrupt generated on falling edge; bit cleared in
hardware on following rising edge.
0= RX pin not monitored nor rising edge detected
Synchronous mode:
Unused in this mode – value ignored
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
bit 0
1= Enable baud rate measurement on the next character – requires reception of a SYNCH field
(55h);cleared in hardware upon completion
0= Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode – value ignored
2016-2017 Microchip Technology Inc.
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PIC16(L)F18326/18346
(1)
REGISTER 31-4: RC1REG : RECEIVE DATA REGISTER
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RC1REG<7:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
RC1REG<7:0>: Lower eight bits of the received data; read-only; see also RX9D (Register 31-2)
Note 1: RC1REG (including the ninth bit) is double buffered, and data is available while new data is being
received.
(1)
REGISTER 31-5: TX1REG : TRANSMIT DATA REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TX1REG<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TX1REG<7:0>: Lower eight bits of the received data; read-only; see also RX9D (Register 31-1)
Note 1: TX1REG (including the ninth bit) is double buffered, and can be written when previous data has started
shifting.
(1)
REGISTER 31-6: SP1BRGL : BAUD RATE GENERATOR REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SP1BRG<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
SP1BRG<7:0>: Lower eight bits of the Baud Rate Generator
Note 1: Writing to SP1BRG resets the BRG counter.
DS40001839B-page 386
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PIC16(L)F18326/18346
(1, 2)
REGISTER 31-7: SP1BRGH
R/W-0 R/W-0
: BAUD RATE GENERATOR HIGH REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SP1BRG<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
SP1BRG<15:8>: Upper eight bits of the Baud Rate Generator
Note 1: SP1BRGH value is ignored for all modes unless BAUD1CON<BRG16> is active.
2: Writing to SP1BRGH resets the BRG counter.
TABLE 31-2: SUMMARY OF REGISTERS ASSOCIATED WITH EUSART1
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(2)
TRISA
―
―
TRISA5
ANSA5
TRISB5
ANSB5
TRISA4
ANSA4
TRISB4
ANSB4
TRISC4
ANSC4
―
―
TRISA2
ANSA2
―
TRISA1
ANSA1
―
TRISA0
ANSA0
―
143
ANSELA
TRISB(1)
ANSELB(1)
TRISC
―
―
―
144
149
150
155
157
100
107
102
384
383
385
386
386
386
387
162
229
272
TRISB7
TRISB6
―
ANSB7
ANSB6
―
―
―
―
TRISC7(1) TRISC6(1) TRISC5
ANSC7(1) ANSC6(1) ANSC5
TRISC3
ANSC3
―
TRISC2
ANSC2
―
TRISC1
ANSC1
―
TRISC0
ANSC0
INTEDG
TMR1IF
TMR1IE
RX9D
ANSELC
INTCON
PIR1
GIE
PEIE
ADIF
ADIE
RX9
―
TMR1GIF
TMR1GIE
SPEN
RCIF
RCIE
SREN
TXEN
―
TXIF
SSP1IF
SSP1IE
ADDEN
SENDB
BRG16
BCL1IF
BCL1IE
FERR
BRGH
―
TMR2IF
TMR2IE
OERR
TRMT
WUE
PIE1
TXIE
RC1STA
TX1STA
CREN
SYNC
SCKP
CSRC
TX9
TX9D
BAUD1CON ABDOVF
RC1REG
RCIDL
ABDEN
RC1REG<7:0>
TX1REG<7:0>
SP1BRG<7:0>
SP1BRG<15:8>
TX1REG
SP1BRGL
SP1BRGH
RXPPS
―
―
―
―
―
―
―
―
―
RXPPS<4:0>
LCxDyS<4:0>
CLCxSELy
MDSRC
―
MDMS<3:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the EUSART1 module.
Note 1: PIC16(L)F18346 only.
2: Unimplemented, read as ‘1’.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 387
PIC16(L)F18326/18346
TABLE 31-3: BAUD RATE FORMULAS
Configuration Bits
Baud Rate Formula
BRG/EUSART1 Mode
SYNC
BRG16
BRGH
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
x
x
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
FOSC/[64 (n+1)]
FOSC/[16 (n+1)]
FOSC/[4 (n+1)]
Legend: x= Don’t care, n = value of SP1BRGH, SP1BRGL register pair.
TABLE 31-4: BAUD RATE FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 32.000 MHz
FOSC = 20.000 MHz
FOSC = 18.432 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPBRG
SPBRG
SPBRG
SPBRG
value
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Error
value
(decimal)
value
(decimal)
value
(decimal)
Error
Error
Error
(decimal)
300
1200
—
—
—
—
—
—
—
—
255
129
32
—
—
—
239
119
29
—
—
—
143
71
17
16
8
—
1221
2404
9470
10417
19.53k
1.73
0.16
-1.36
0.00
1.73
1200
2400
9600
10286
19.20k
0.00
0.00
0.00
-1.26
0.00
0.00
—
1200
2400
9600
10165
19.20k
0.00
0.00
0.00
-2.42
0.00
0.00
—
2400
2404
9615
10417
19.23k
0.16
0.16
0.00
0.16
207
51
9600
10417
19.2k
57.6k
115.2k
47
29
27
25
15
14
2
55.55k
—
-3.55
—
3
—
—
—
—
—
—
57.60k
—
7
57.60k
—
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPBRG
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
0.00
0.00
0.00
0.00
—
300
1200
—
1202
2404
9615
10417
—
—
0.16
0.16
0.16
0.00
—
—
103
51
12
11
300
1202
2404
—
0.16
0.16
0.16
—
207
51
25
—
5
300
1200
2400
9600
—
191
47
23
5
300
1202
—
0.16
0.16
—
51
12
—
—
—
—
—
—
2400
9600
—
—
10417
19.2k
57.6k
115.2k
10417
—
0.00
—
—
2
—
—
—
—
—
—
19.20k
0.00
0.00
—
—
—
—
—
—
—
—
0
—
—
57.60k
—
—
—
—
—
—
—
—
—
DS40001839B-page 388
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
TABLE 31-4: BAUD RATE FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 20.000 MHz FOSC = 18.432 MHz
FOSC = 32.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPBRG
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
300
1200
2400
9600
10417
19.2k
57.6k
—
—
—
—
—
—
—
—
—
—
—
—
—
71
65
35
11
5
9615
10417
19.23k
57.14k
0.16
0.00
0.16
-0.79
2.12
207
191
103
34
9615
10417
19.23k
56.82k
0.16
0.00
0.16
-1.36
129
119
64
9600
10378
19.20k
57.60k
115.2k
0.00
-0.37
0.00
0.00
0.00
119
110
59
19
9
9600
0.00
0.53
0.00
0.00
0.00
10473
19.20k
57.60k
115.2k
21
115.2k 117.64k
16
113.64k -1.36
10
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPBRG
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
—
—
—
—
—
—
300
1200
—
1202
2404
9615
10417
19.23k
—
—
—
207
103
25
—
—
—
191
95
23
21
11
3
300
1202
2404
—
0.16
0.16
0.16
—
207
51
25
—
5
0.16
0.16
0.16
0.00
0.16
—
1200
0.00
0.00
0.00
0.53
0.00
0.00
0.00
2400
2404
9615
10417
19231
55556
—
0.16
0.16
0.00
0.16
-3.55
—
207
51
47
25
8
2400
9600
9600
10417
19.2k
57.6k
115.2k
23
10473
19.2k
57.60k
115.2k
10417
—
0.00
—
12
—
—
—
—
—
—
—
—
—
—
1
—
—
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 20.000 MHz FOSC = 18.432 MHz
FOSC = 32.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPBRG
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
300
1200
2400
9600
10417
19.2k
57.6k
300.0
1200
0.00
-0.02
-0.04
0.16
0.00
0.16
-0.79
6666
3332
832
207
191
103
34
300.0
1200
-0.01
-0.03
-0.03
0.16
0.00
0.16
-1.36
4166
1041
520
129
119
64
300.0
1200
0.00
0.00
0.00
0.00
-0.37
0.00
0.00
3839
959
479
119
110
59
300.0
1200
0.00
0.00
0.00
0.00
0.53
0.00
0.00
2303
575
287
71
2401
2399
2400
2400
9615
9615
9600
9600
10417
19.23k
57.14k
10417
19.23k
56.818
10378
19.20k
57.60k
10473
19.20k
57.60k
65
35
21
19
11
115.2k
117.6k
2.12
16
113.636 -1.36
10
115.2k
0.00
9
115.2k
0.00
5
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 389
PIC16(L)F18326/18346
TABLE 31-4: BAUD RATE FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 8.000 MHz
FOSC = 4.000 MHz
FOSC = 3.6864 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPBRG
SPBRG
SPBRG
SPBRG
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
value
(decimal)
value
(decimal)
value
(decimal)
value
(decimal)
Error
Error
Error
Error
300
1200
299.9
1199
-0.02
-0.08
0.16
0.16
0.00
0.16
-3.55
—
1666
416
207
51
300.1
1202
2404
9615
10417
19.23k
—
0.04
0.16
0.16
0.16
0.00
0.16
—
832
207
103
25
300.0
1200
0.00
0.00
0.00
0.00
0.53
0.00
0.00
0.00
767
191
95
23
21
11
3
300.5
1202
2404
—
0.16
0.16
0.16
—
207
51
25
—
5
2400
2404
9615
10417
19.23k
55556
—
2400
9600
9600
10417
19.2k
57.6k
115.2k
47
23
10473
19.20k
57.60k
115.2k
10417
—
0.00
—
25
12
—
—
—
8
—
—
—
—
—
—
—
1
—
—
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 20.000 MHz FOSC = 18.432 MHz
FOSC = 32.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPBRG
SPBRG
SPBRG
SPBRG
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
value
(decimal)
value
(decimal)
value
(decimal)
value
(decimal)
Error
Error
Error
Error
300
1200
300.0
1200
0.00
0.00
0.01
0.04
0.00
-0.08
-0.08
0.64
26666
6666
3332
832
300.0
1200
0.00
-0.01
0.02
-0.03
0.00
0.16
-0.22
0.94
16665
4166
2082
520
479
259
86
300.0
1200
0.00
0.00
0.00
0.00
0.08
0.00
0.00
0.00
15359
3839
1919
479
441
239
79
300.0
1200
0.00
0.00
0.00
0.00
0.16
0.00
0.00
0.00
9215
2303
1151
287
264
143
47
2400
2400
2400
2400
2400
9600
9604
9597
9600
9600
10417
19.2k
57.6k
115.2k
10417
19.18k
57.55k
115.9k
767
10417
19.23k
57.47k
116.3k
10425
19.20k
57.60k
115.2k
10433
19.20k
57.60k
115.2k
416
138
68
42
39
23
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPBRG
SPBRG
SPBRG
SPBRG
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
value
(decimal)
value
(decimal)
value
(decimal)
value
(decimal)
Error
Error
Error
Error
300
1200
300.0
1200
0.00
-0.02
0.04
0.16
0
6666
1666
832
207
191
103
34
300.0
1200
0.01
0.04
0.08
0.16
0.00
0.16
2.12
-3.55
3332
832
416
103
95
300.0
1200
0.00
0.00
0.00
0.00
0.53
0.00
0.00
0.00
3071
767
383
95
300.1
1202
2404
9615
10417
19.23k
—
0.04
0.16
0.16
0.16
0.00
0.16
—
832
207
103
25
2400
2401
2398
2400
9600
9615
9615
9600
10417
19.2k
57.6k
115.2k
10417
19.23k
57.14k
117.6k
10417
19.23k
58.82k
111.1k
10473
19.20k
57.60k
115.2k
87
23
0.16
-0.79
2.12
51
47
12
16
15
—
16
8
7
—
—
—
DS40001839B-page 390
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
32.3 Selectable Duty Cycle
32.0 REFERENCE CLOCK OUTPUT
MODULE
The CLKRDC<1:0> bits of the CLKRCON register can
be used to modify the duty cycle of the output clock. A
duty cycle of 25%, 50%, or 75% can be selected for all
clock rates, with the exception of the undivided base
FOSC value.
The Reference Clock Output module provides the
ability to send a clock signal to the clock reference
output pin (CLKR). The Reference Clock Output can
also be used as a signal for other peripherals, such as
the Data Signal Modulator (DSM).
The duty cycle can be changed while the module is
enabled; however, in order to prevent glitches on the
output, the CLKRDC<1:0> bits should only be changed
when the module is disabled (CLKREN = 0).
The Reference Clock Output module has the following
features:
• System clock is the module source clock
• Programmable clock divider
• Selectable duty cycle
Note:
The CLKRDC1 bit is reset to ‘1’. This
makes the default duty cycle 50%.
32.1 Clock Source
32.4 Operation in Sleep Mode
The Reference Clock Output module uses the system
clock (FOSC) as the clock source. Any device clock
switching will be reflected in the clock output.
The Reference Clock Output module clock is based on
the system clock. When the device goes to Sleep, the
module outputs will remain in their current state. This
will have a direct effect on peripherals using the
Reference Clock Output as an input signal.
32.1.1
CLOCK SYNCHRONIZATION
Once the reference clock enable (CLKREN) is set, the
module is ensured to be glitch-free at start-up.
When the Reference Clock Output is disabled, the
output signal will be disabled immediately.
Clock dividers and clock duty cycles can be changed
while the module is enabled, but glitches may occur on
the output. To avoid possible glitches, clock dividers
and clock duty cycles should be changed only when the
CLKREN is clear.
32.2 Programmable Clock Divider
The module takes the system clock input and divides it
based on the value of the CLKRDIV<2:0> bits of the
CLKRCON register (Register 32-1).
The following configurations can be made based on the
CLKRDIV<2:0> bits:
• Base FOSC value
• FOSC divided by 2
• FOSC divided by 4
• FOSC divided by 8
• FOSC divided by 16
• FOSC divided by 32
• FOSC divided by 64
• FOSC divided by 128
The clock divider values can be changed while the
module is enabled; however, in order to prevent
glitches on the output, the CLKRDIV<2:0> bits should
only be changed when the module is disabled
(CLKREN = 0).
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 391
PIC16(L)F18326/18346
FIGURE 32-1:
CLOCK REFERENCE BLOCK DIAGRAM
CLKRDIV<2:0>
FOSC
CLKREN
D
Q
000
001
010
011
100
101
110
111
FOSC/2
FOSC/4
FREEZE ENABLED(1)
CLKRDC<1:0>
Duty Cycle
EN
ICD FREEZE MODE(1)
CLKR
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FOSC/128
Clock Counter
To Peripherals
CLKREN
Counter Reset
Note 1:
Freeze is used in Debug Mode only; otherwise read as ‘0’
FIGURE 32-2:
CLOCK REFERENCE TIMING
P2
P1
FOSC
CLKREN
CLKR Output
CLKRDIV[2:0] = 001
CLKRDC[1:0] = 10
Duty Cycle
(50%)
FOSC / 2
CLKR Output
CLKRDIV[2:0] = 001
CLKRDC[1:0] = 01
Duty Cycle (25%)
DS40001839B-page 392
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
REGISTER 32-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER
R/W-0/0
U-0
U-0
R/W-1/1
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CLKREN
—
—
CLKRDC<1:0>
CLKRDIV<2:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
CLKREN: Reference Clock Module Enable bit
1 = Reference clock module enabled
0 = Reference clock module is disabled
bit 6-5
bit 4-3
Unimplemented: Read as ‘0’
CLKRDC<1:0>: Reference Clock Duty Cycle bits (1)
11= Clock outputs duty cycle of 75%
10= Clock outputs duty cycle of 50%
01= Clock outputs duty cycle of 25%
00= Clock outputs duty cycle of 0%
bit 2-0
CLKRDIV<2:0>: Reference Clock Divider bits
111= FOSC divided by 128
110= FOSC divided by 64
101= FOSC divided by 32
100= FOSC divided by 16
011= FOSC divided by 8
010= FOSC divided by 4
001= FOSC divided by 2
000= FOSC
Note 1: Bits are valid for Reference Clock divider values of two or larger, the base clock cannot be further divided.
TABLE 32-1: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK REFERENCE OUTPUT
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(2)
TRISA
―
TRISB7
TRISC7(1)
CLKREN
―
―
TRISB6
TRISC6(1)
―
TRISA5
TRISB5
TRISC5
―
TRISA4
TRISB4
―
TRISA2 TRISA1
TRISA0
―
143
149
155
227
229
273
274
TRISB(1)
TRISC
―
―
―
TRISC4 TRISC3 TRISC2 TRISC1
CLKRDC<1:0>
LCxDyS<5:0>
TRISC0
CLKRCON
CLCxSELy
MDCARH
MDCARL
Legend:
CLKRDIV<2:0>
―
―
MDCHPOL
MDCLPOL
MDCHSYNC
MDCLSYNC
―
―
MDCH<3:0>
MDCL<3:0>
―
— = unimplemented, read as ‘0’. Shaded cells are not used by the CLKR module.
Note 1: PIC16(L)F18346 only.
2: Unimplemented, read as ‘1’.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 393
PIC16(L)F18326/18346
33.3 Common Programming Interfaces
33.0 IN-CIRCUIT SERIAL
PROGRAMMING™ (ICSP™)
Connection to a target device is typically done through
an ICSP™ header. A commonly found connector on
development tools is the RJ-11 in the 6P6C (6-pin,
6-connector) configuration. See Figure 33-1.
ICSP™ programming allows customers to manufacture
circuit boards with unprogrammed devices. Programming
can be done after the assembly process, allowing the
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP
FIGURE 33-1:
ICD RJ-11 STYLE
CONNECTOR INTERFACE
programming:
• ICSPCLK
• ICSPDAT
• MCLR/VPP
• Vdd
• Vss
ICSPDAT
In Program/Verify mode the program memory, data
EEPROM, User IDs and the Configuration Words are
programmed through serial communications. The
ICSPDAT pin is a bidirectional I/O used for transferring
the serial data and the ICSPCLK pin is the clock input.
For more information on ICSP, refer to the
NC
2 4 6
VDD
ICSPCLK
1 3
5
Target
PC Board
Bottom Side
VPP/MCLR
VSS
“PIC16(L)F183XX
Memory
Programming
Specification” (DS40001738).
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
33.1 High-Voltage Programming Entry
Mode
The device is placed into High-Voltage Programming
Entry mode by holding the ICSPCLK and ICSPDAT
pins low then raising the voltage on MCLR/VPP to VIHH.
5 = ICSPCLK
6 = No Connect
33.2 Low-Voltage Programming Entry
Mode
Another connector often found in use with the PICkit™
programmers is a standard 6-pin header with 0.1 inch
spacing. Refer to Figure 33-2.
The Low-Voltage Programming Entry mode allows the
PIC® Flash MCUs to be programmed using VDD only,
without high voltage. When the LVP bit of Configuration
Words is set to ‘1’, the low-voltage ICSP programming
entry is enabled. To disable the Low-Voltage ICSP
mode, the LVP bit must be programmed to ‘0’. The LVP
bit can only be reprogrammed to ‘0’ by using the
High-Voltage Programming mode.
For additional interface recommendations, refer to your
specific device programmer manual prior to PCB
design.
It is recommended that isolation devices be used to
separate the programming pins from other circuitry.
The type of isolation is highly dependent on the specific
application and may include devices such as resistors,
diodes, or even jumpers. See Figure 33-3 for more
information.
Entry into the Low-Voltage Programming Entry mode
requires the following steps:
1. MCLR is brought to VIL.
2.
A
32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
If low-voltage programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and
cannot be disabled. See Section 6.4 “MCLR” for more
information.
DS40001839B-page 394
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
FIGURE 33-2:
PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE
Pin 1 Indicator
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
1
2
3
4
5
6
5 = ICSPCLK
6 = No Connect
*
The 6-pin header (0.100" spacing) accepts 0.025" square pins.
FIGURE 33-3:
TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
External
Programming
Signals
Device to be
Programmed
VDD
VDD
VDD
VPP
VSS
MCLR/VPP
VSS
Data
ICSPDAT
ICSPCLK
Clock
*
*
*
To Normal Connections
Isolation devices (as required).
*
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 395
PIC16(L)F18326/18346
34.1 Read-Modify-Write Operations
34.0 INSTRUCTION SET SUMMARY
Any WRITE instruction that specifies a file register as
part of the instruction performs a Read-Modify-Write
(R-M-W) operation. The register is read, the data is
modified, and the result is stored according to either the
working (W) register, or the originating file register,
depending on the state of the destination designator ‘d’
(see Table 34-1 for more information). A read operation
is performed on a register even if the instruction writes
to that register.
Each instruction is a 14-bit word containing the opera-
tion code (opcode) and all required operands. The
opcodes are broken into three broad categories.
• Byte Oriented
• Bit Oriented
• Literal and Control
The literal and control category contains the most
varied instruction word format.
Table 34-3 lists the instructions recognized by the
MPASM™ assembler.
TABLE 34-1: OPCODE FIELD
DESCRIPTIONS
All instructions are executed within a single instruction
cycle, with the following exceptions, which may take
two or three cycles:
Field
Description
f
W
b
Register file address (0x00 to 0x7F)
Working register (accumulator)
• Subroutine entry takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two
cycles (RETURN, RETLW, RETFIE)
• Program branching takes two cycles (GOTO, BRA,
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)
• One additional instruction cycle will be used when
any instruction references an indirect file register
and the file select register is pointing to program
memory.
Bit address within an 8-bit file register
Literal field, constant data or label
k
x
Don’t care location (= 0or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
n
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
One instruction cycle consists of 4 oscillator cycles; for
an oscillator frequency of 4 MHz, this gives a nominal
instruction execution rate of 1 MHz.
FSR or INDF number. (0-1)
mm Pre-post increment-decrement mode
selection
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
TABLE 34-2: ABBREVIATION
DESCRIPTIONS
Field
Description
PC Program Counter
TO Time-Out bit
C
Carry bit
DC Digit Carry bit
Zero bit
PD Power-Down bit
Z
DS40001839B-page 396
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
FIGURE 34-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8
7
6
0
OPCODE
d
f (FILE #)
d = 0for destination W
d = 1for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9
7 6
0
OPCODE
b (BIT #)
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
0
OPCODE
k (literal)
k = 8-bit immediate value
CALLand GOTOinstructions only
13 11 10
OPCODE
0
k (literal)
k = 11-bit immediate value
MOVLPinstruction only
13
7
6
0
0
OPCODE
k (literal)
k = 7-bit immediate value
MOVLBinstruction only
13
5 4
OPCODE
k (literal)
k = 5-bit immediate value
BRAinstruction only
13
9
8
0
OPCODE
k (literal)
k = 9-bit immediate value
FSR Offset instructions
13
7
6
5
0
0
OPCODE
n
k (literal)
n = appropriate FSR
k = 6-bit immediate value
FSRIncrement instructions
13
3
2
n
1
OPCODE
m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13
0
OPCODE
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 397
PIC16(L)F18326/18346
TABLE 34-3: PIC16(L)F18326/18346 INSTRUCTION SET
14-bit Opcode
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC f, d
ANDWF
ASRF
LSLF
f, d
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
00 0111 dfff ffff C, DC, Z
11 1101 dfff ffff C, DC, Z
00 0101 dfff ffff Z
11 0111 dfff ffff C, Z
11 0101 dfff ffff C, Z
11 0110 dfff ffff C, Z
2
2
2
2
2
2
2
f, d
f, d
f, d
f, d
f
LSRF
CLRF
CLRW
COMF
DECF
INCF
IORWF
MOVF
MOVWF
RLF
RRF
SUBWF
SUBWFB f, d
SWAPF
XORWF
00 0001 lfff ffff
00 0001 0000 00xx
00 1001 dfff ffff
00 0011 dfff ffff
00 1010 dfff ffff
00 0100 dfff ffff
00 1000 dfff ffff
00 0000 1fff ffff
00 1101 dfff ffff
00 1100 dfff ffff
Z
Z
Z
Z
Z
Z
Z
–
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
2
2
2
2
2
2
2
2
2
2
2
2
C
C
00 0010 dfff ffff C, DC, Z
11 1011 dfff ffff C, DC, Z
00 1110 dfff ffff
f, d
f, d
00 0110 dfff ffff
Z
BYTE ORIENTED SKIP OPERATIONS
f, d
f, d
Decrement f, Skip if 0
Increment f, Skip if 0
1(2)
1(2)
00
00
1011 dfff ffff
1111 dfff ffff
1, 2
1, 2
DECFSZ
INCFSZ
BIT-ORIENTED FILE REGISTER OPERATIONS
f, b
f, b
Bit Clear f
Bit Set f
1
1
01
01
00bb bfff ffff
01bb bfff ffff
2
2
BCF
BSF
BIT-ORIENTED SKIP OPERATIONS
BTFSC
BTFSS
f, b
f, b
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1 (2)
1 (2)
01
01
10bb bfff ffff
11bb bfff ffff
1, 2
1, 2
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Inclusive OR literal with W
Move literal to BSR
Move literal to PCLATH
Move literal to W
1
1
1
1
1
1
1
1
11
11
11
00
11
11
11
11
1110 kkkk kkkk C, DC, Z
1001 kkkk kkkk
1000 kkkk kkkk
0000 001k kkkk
0001 1kkk kkkk
0000 kkkk kkkk
Z
Z
Subtract W from literal
Exclusive OR literal with W
1100 kkkk kkkk C, DC, Z
1010 kkkk kkkk
Z
CONTROL OPERATIONS
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
–
k
–
k
k
k
–
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
2
2
2
2
2
2
2
2
11
00
10
00
10
00
11
00
001k kkkk kkkk
0000 0000 1011
0kkk kkkk kkkk
0000 0000 1010
1kkk kkkk kkkk
0000 0000 1001
0100 kkkk kkkk
0000 0000 1000
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Section 34.2 “Instruction Descriptions” for detailed MOVIWand MOVWIinstruction descriptions.
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TABLE 34-3: PIC16(L)F18326/18346 INSTRUCTION SET (CONTINUED)
14-bit Opcode
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
INHERENT OPERATIONS
CLRWDT
NOP
RESET
SLEEP
TRIS
–
–
–
–
f
Clear Watchdog Timer
No Operation
Software device Reset
Go into Standby mode
Load TRIS register with W
1
1
1
1
1
00
00
00
00
00
0000 0110 0100 TO, PD
0000 0000 0000
0000 0000 0001
0000 0110 0011 TO, PD
0000 0110 0fff
C-COMPILER OPTIMIZED
ADDFSR n, k
Add Literal k to FSRn
Move Indirect FSRn to W with pre/post inc/dec
modifier, mm
1
1
11 0001 0nkk kkkk
00 0000 0001 0nmm
MOVIW
n mm
Z
Z
2, 3
k[n]
n mm
Move INDFn to W, Indexed Indirect.
Move W to Indirect FSRn with pre/post inc/dec
modifier, mm
1
1
11 1111 0nkk kkkk
00 0000 0001 1nmm
2
2, 3
MOVWI
k[n]
Move W to INDFn, Indexed Indirect.
1
11 1111 1nkk kkkk
2
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Section 34.2 “Instruction Descriptions” for detailed MOVIWand MOVWIinstruction descriptions.
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34.2 Instruction Descriptions
ADDFSR
Add Literal to FSRn
ANDLW
AND literal with W
Syntax:
[ label ] ADDFSR FSRn, k
Syntax:
[ label ] ANDLW
0 k 255
k
Operands:
-32 k 31
n [ 0, 1]
Operands:
Operation:
Status Affected:
Description:
(W) .AND. (k) (W)
Operation:
FSR(n) + k FSR(n)
Z
Status Affected:
Description:
None
The contents of W register are
AND’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
The signed 6-bit literal ‘k’ is added to
the contents of the FSRnH:FSRnL
register pair.
FSRn is limited to the range
0000h-FFFFh. Moving beyond these
bounds will cause the FSR to
wrap-around.
ANDWF
AND W with f
ADDLW
Add literal and W
Syntax:
[ label ] ANDWF f,d
Syntax:
[ label ] ADDLW
0 k 255
k
Operands:
0 f 127
d 0,1
Operands:
Operation:
Status Affected:
Description:
Operation:
(W) .AND. (f) (destination)
(W) + k (W)
C, DC, Z
Status Affected:
Description:
Z
AND the W register with register ‘f’. If
‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
The contents of the W register are
added to the 8-bit literal ‘k’ and the
result is placed in the W register.
ASRF
Arithmetic Right Shift
ADDWF
Add W and f
Syntax:
[ label ] ASRF f {,d}
Syntax:
[ label ] ADDWF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d 0,1
Operation:
(f<7>) dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Operation:
(W) + (f) (destination)
Status Affected:
Description:
C, DC, Z
Status Affected:
Description:
C, Z
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
C
register f
ADDWFC
ADD W and CARRY bit to f
Syntax:
[ label ] ADDWFC
f {,d}
Operands:
0 f 127
d [0,1]
Operation:
(W) + (f) + (C) dest
Status Affected:
Description:
C, DC, Z
Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
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BTFSC
Bit Test f, Skip if Clear
BCF
Bit Clear f
Syntax:
[ label ] BTFSC f,b
Syntax:
[ label ] BCF f,b
Operands:
0 f 127
0 b 7
Operands:
0 f 127
0 b 7
Operation:
skip if (f<b>) = 0
Operation:
0 (f<b>)
Status Affected:
Description:
None
Status Affected:
Description:
None
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
Bit ‘b’ in register ‘f’ is cleared.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOPis
executed instead, making this a
2-cycle instruction.
BTFSS
Bit Test f, Skip if Set
BRA
Relative Branch
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] BRA label
[ label ] BRA $+k
Operands:
0 f 127
0 b < 7
Operands:
-256 label - PC + 1 255
-256 k 255
Operation:
skip if (f<b>) = 1
Operation:
(PC) + 1 + k PC
Status Affected:
Description:
None
Status Affected:
Description:
None
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next instruction
is discarded and a NOPis executed
instead, making this a 2-cycle
instruction.
Add the signed 9-bit literal ‘k’ to the
PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 1 + k. This instruction is a
2-cycle instruction. This branch has a
limited range.
BRW
Relative Branch with W
Syntax:
[ label ] BRW
None
Operands:
Operation:
Status Affected:
Description:
(PC) + (W) PC
None
Add the contents of W (unsigned) to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 1 + (W). This instruction is a
2-cycle instruction.
BSF
Bit Set f
Syntax:
[ label ] BSF f,b
Operands:
0 f 127
0 b 7
Operation:
1 (f<b>)
Status Affected:
Description:
None
Bit ‘b’ in register ‘f’ is set.
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CALL
Call Subroutine
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL
0 k 2047
k
Syntax:
[ label ] CLRWDT
Operands:
Operation:
Operands:
Operation:
None
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<6:3>) PC<14:11>
00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Affected:
Description:
None
Status Affected:
Description:
TO, PD
Call Subroutine. First, return address
(PC + 1) is pushed onto the stack.
The 11-bit immediate address is
loaded into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALLis a 2-cycle
instruction.
CLRWDTinstruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD
are set.
COMF
Complement f
CALLW
Subroutine Call With W
Syntax:
[ label ] COMF f,d
Syntax:
[ label ] CALLW
Operands:
0 f 127
d [0,1]
Operands:
Operation:
None
(PC) +1 TOS,
(W) PC<7:0>,
Operation:
(f) (destination)
(PCLATH<6:0>) PC<14:8>
Status Affected:
Description:
Z
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Status Affected:
Description:
None
Subroutine call with W. First, the
return address (PC + 1) is pushed
onto the return stack. Then, the
contents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLWis a 2-cycle
instruction.
DECF
Decrement f
CLRF
Clear f
Syntax:
[ label ] DECF f,d
Syntax:
[ label ] CLRF
0 f 127
f
Operands:
0 f 127
d [0,1]
Operands:
Operation:
00h (f)
1 Z
Operation:
(f) - 1 (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
The contents of register ‘f’ are cleared
and the Z bit is set.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
Operation:
None
00h (W)
1 Z
Status Affected:
Description:
Z
W register is cleared. Zero bit (Z) is
set.
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DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ] INCFSZ f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Operation:
(f) + 1 (destination),
skip if result = 0
Status Affected:
Description:
None
Status Affected:
Description:
None
The contents of register ‘f’ are decre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, then a
NOPis executed instead, making it a
2-cycle instruction.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, a NOPis
executed instead, making it a 2-cycle
instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR literal with W
Syntax:
[ label ] GOTO
0 k 2047
k
Syntax:
[ label ] IORLW
0 k 255
(W) .OR. k (W)
Z
k
Operands:
Operation:
Operands:
Operation:
Status Affected:
Description:
k PC<10:0>
PCLATH<6:3> PC<14:11>
Status Affected:
Description:
None
The contents of the W register are
OR’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
GOTOis an unconditional branch. The
11-bit immediate value is loaded into
PC bits <10:0>. The upper bits of PC
are loaded from PCLATH<4:3>. GOTO
is a 2-cycle instruction.
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ] INCF f,d
Syntax:
[ label ] IORWF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) + 1 (destination)
Operation:
(W) .OR. (f) (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
Inclusive OR the W register with regis-
ter ‘f’. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
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LSLF
Logical Left Shift
MOVF
Move f
Syntax:
[ label ] LSLF f {,d}
Syntax:
[ label ] MOVF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f<7>) C
Operation:
(f) (dest)
(f<6:0>) dest<7:1>
0 dest<0>
Status Affected:
Description:
Z
The contents of register f is moved to
a destination dependent upon the
status of d. If d = 0, destination is W
register. If d = 1, the destination is file
register f itself. d = 1is useful to test a
file register since status flag Z is
affected.
Status Affected:
Description:
C, Z
The contents of register ‘f’ are shifted
one bit to the left through the Carry flag.
A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,
the result is placed in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
Words:
1
1
C
register f
0
Cycles:
Example:
MOVF
FSR, 0
After Instruction
LSRF
Logical Right Shift
W
Z
=
= 1
value in FSR register
Syntax:
[ label ] LSRF f {,d}
Operands:
0 f 127
d [0,1]
Operation:
0 dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected:
Description:
C, Z
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
0
C
register f
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MOVIW
Move INDFn to W
MOVLP
Move literal to PCLATH
Syntax:
[ label ] MOVIW ++FSRn
[ label ] MOVIW --FSRn
[ label ] MOVIW FSRn++
[ label ] MOVIW FSRn--
[ label ] MOVIW k[FSRn]
Syntax:
[ label ] MOVLP
0 k 127
k PCLATH
None
k
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
n [0,1]
mm [00,01, 10, 11]
-32 k 31
The 7-bit literal ‘k’ is loaded into the
PCLATH register.
INDFn W
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
• FSR + 1 (all increments)
• FSR - 1 (all decrements)
• Unchanged
MOVLW
Move literal to W
Syntax:
[ label ] MOVLW
0 k 255
k (W)
k
Operands:
Operation:
Status Affected:
Description:
None
The 8-bit literal ‘k’ is loaded into W reg-
ister. The “don’t cares” will assemble as
‘0’s.
Status Affected:
Z
Words:
1
1
Cycles:
Example:
Mode
Syntax
mm
00
01
10
11
MOVLW
0x5A
Preincrement
Predecrement
Postincrement
Postdecrement
++FSRn
--FSRn
FSRn++
FSRn--
After Instruction
W
=
0x5A
MOVWF
Move W to f
[ label ] MOVWF
0 f 127
(W) (f)
Syntax:
f
Description:
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Operands:
Operation:
Status Affected:
Description:
None
Move data from W register to register
‘f’.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
Words:
1
Cycles:
Example:
1
MOVWF OPTION_REG
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
After Instruction
OPTION_REG = 0x4F
W = 0x4F
FSRn is limited to the range 0000h -
FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to
wrap-around.
MOVLB
Move literal to BSR
Syntax:
[ label ] MOVLB
0 k 31
k BSR
None
k
Operands:
Operation:
Status Affected:
Description:
The 5-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).
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NOP
No Operation
MOVWI
Move W to INDFn
Syntax:
[ label ] NOP
Syntax:
[ label ] MOVWI ++FSRn
[ label ] MOVWI --FSRn
[ label ] MOVWI FSRn++
[ label ] MOVWI FSRn--
[ label ] MOVWI k[FSRn]
Operands:
Operation:
Status Affected:
Description:
Words:
None
No operation
None
No operation.
Operands:
Operation:
n [0,1]
mm [00,01, 10, 11]
-32 k 31
1
Cycles:
1
W INDFn
Example:
NOP
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
RESET
Software Reset
• FSR + 1 (all increments)
• FSR - 1 (all decrements)
Unchanged
Syntax:
[ label ] RESET
Operands:
Operation:
None
Execute a device Reset. Resets the
RI flag of the PCON register.
Status Affected:
None
Status Affected:
Description:
None
Mode
Syntax
mm
00
01
10
11
This instruction provides a way to
execute a hardware Reset by
software.
Preincrement
Predecrement
Postincrement
Postdecrement
++FSRn
--FSRn
FSRn++
FSRn--
RETFIE
Syntax:
Return from Interrupt
[ label ] RETFIE k
None
Description:
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Operands:
Operation:
TOS PC,
1 GIE
Status Affected:
Description:
None
Return from Interrupt. Stack is POPed
and Top-of-Stack (TOS) is loaded in
the PC. Interrupts are enabled by
setting Global Interrupt Enable bit,
GIE (INTCON<7>). This is a 2-cycle
instruction.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
FSRn is limited to the range
0000h-FFFFh.
Incrementing/decrementing it beyond
these bounds will cause it to
wrap-around.
Words:
1
Cycles:
Example:
2
RETFIE
After Interrupt
PC
GIE = 1
=
TOS
The increment/decrement operation on
FSRn WILL NOT affect any Status bits.
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RLF
Rotate Left f through Carry
RETLW
Syntax:
Return with literal in W
Syntax:
Operands:
[ label ]
RLF f,d
[ label ] RETLW
0 k 255
k
0 f 127
d [0,1]
Operands:
Operation:
k (W);
TOS PC
Operation:
See description below
C
Status Affected:
Description:
Status Affected:
Description:
None
The contents of register ‘f’ are rotated
one bit to the left through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
The W register is loaded with the 8-bit
literal ‘k’. The program counter is
loaded from the top of the stack (the
return address). This is a 2-cycle
instruction.
C
Register f
Words:
1
2
Cycles:
Example:
Words:
1
1
CALL TABLE;W contains table
;offset value
• ;W now has table value
Cycles:
Example:
RLF
REG1,0
TABLE
•
•
Before Instruction
REG1
C
After Instruction
= 1110 0110
= 0
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
•
•
•
REG1
W
C
= 1110 0110
= 1100 1100
= 1
RETLW kn ; End of table
RRF
Rotate Right f through Carry
Before Instruction
Syntax:
[ label ] RRF f,d
W
=
0x07
After Instruction
Operands:
0 f 127
d [0,1]
W
=
value of k8
Operation:
See description below
C
Status Affected:
Description:
RETURN
Return from Subroutine
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
Syntax:
[ label ] RETURN
None
Operands:
Operation:
Status Affected:
Description:
TOS PC
None
C
Register f
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a 2-cycle instruction.
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SUBWF
Subtract W from f
Syntax:
[ label ] SUBWF f,d
SLEEP
Enter Sleep mode
[ label ] SLEEP
None
Operands:
0 f 127
d [0,1]
Syntax:
Operands:
Operation:
Operation:
(f) - (W) destination)
00h WDT,
0 WDT prescaler,
1 TO,
Status Affected:
Description:
C, DC, Z
Subtract (2’s complement method) W
register from register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f.
0 PD
Status Affected:
Description:
TO, PD
The power-down Status bit, PD is
cleared. Time-out Status bit, TO is
set. Watchdog Timer and its
prescaler are cleared.
See Section 9.2 “Sleep Mode” for
more information.
C = 0
W f
C = 1
W f
DC = 0
DC = 1
W<3:0> f<3:0>
W<3:0> f<3:0>
SUBWFB
Subtract W from f with Borrow
SUBWFB f {,d}
Syntax:
Operands:
0 f 127
d [0,1]
Operation:
(f) – (W) – (B) dest
Status Affected:
Description:
C, DC, Z
Subtract W and the BORROW flag
(CARRY) from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
SUBLW
Subtract W from literal
Syntax:
[ label ] SUBLW
0 k 255
k
Operands:
Operation:
Status Affected:
Description:
SWAPF
Swap Nibbles in f
k - (W) W)
C, DC, Z
Syntax:
[ label ] SWAPF f,d
Operands:
0 f 127
d [0,1]
The W register is subtracted (2’s
complement method) from the 8-bit
literal ‘k’. The result is placed in the W
register.
Operation:
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Affected:
Description:
None
C = 0
W k
The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is ‘0’,
the result is placed in the W register. If
‘d’ is ‘1’, the result is placed in register
‘f’.
C = 1
W k
DC = 0
DC = 1
W<3:0> k<3:0>
W<3:0> k<3:0>
DS40001839B-page 408
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PIC16(L)F18326/18346
TRIS
Load TRIS Register with W
XORLW
Exclusive OR literal with W
Syntax:
[ label ] TRIS f
5 f 7
Syntax:
[ label ] XORLW
0 k 255
k
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
Status Affected:
Description:
(W) TRIS register ‘f’
None
(W) .XOR. k W)
Z
Move data from W register to TRIS
register.
When ‘f’ = 5, TRISA is loaded.
When ‘f’ = 6, TRISB is loaded.
When ‘f’ = 7, TRISC is loaded.
The contents of the W register are
XOR’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
XORWF
Exclusive OR W with f
Syntax:
[ label ] XORWF f,d
Operands:
0 f 127
d [0,1]
Operation:
(W) .XOR. (f) destination)
Status Affected:
Description:
Z
Exclusive OR the contents of the W
register with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
2016-2017 Microchip Technology Inc.
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DS40001839B-page 409
PIC16(L)F18326/18346
35.0 ELECTRICAL SPECIFICATIONS
(†)
35.1 Absolute Maximum Ratings
Ambient temperature under bias...................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on pins with respect to VSS
on VDD pin
PIC16F18326/18346 ................................................................................................. -0.3V to +6.5V
PIC16LF18326/18346 ............................................................................................... -0.3V to +4.0V
on MCLR pin ........................................................................................................................... -0.3V to +9.0V
on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V)
Maximum current
on VSS pin(1)
-40°C TA +85°C .............................................................................................................. 250 mA
+85°C TA +125°C ............................................................................................................. 85 mA
on VDD pin(1)
-40°C TA +85°C .............................................................................................................. 250 mA
+85°C TA +125°C ............................................................................................................. 85 mA
on any I/O pin ..................................................................................................................................... 50 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA
Total power dissipation(2) .............................................................................................................................. 800 mW
Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations, see Table 35-3 to calculate device
specifications.
2: Power dissipation is calculated as follows:
PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
DS40001839B-page 410
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PIC16(L)F18326/18346
35.2 Standard Operating Conditions
The standard operating conditions for any device are defined as:
Operating Voltage:
Operating Temperature:
VDDMIN VDD VDDMAX
TA_MIN TA TA_MAX
VDD — Operating Supply Voltage(1)
PIC16LF18326/18346
VDDMIN (Fosc 16 MHz) ......................................................................................................... +1.8V
VDDMIN (Fosc 32 MHz) ......................................................................................................... +2.5V
VDDMAX .................................................................................................................................... +3.6V
PIC16F18326/18346
VDDMIN (Fosc 16 MHz) ......................................................................................................... +2.3V
VDDMIN (Fosc 32 MHz) ......................................................................................................... +2.5V
VDDMAX .................................................................................................................................... +5.5V
TA — Operating Ambient Temperature Range
Industrial Temperature
TA_MIN...................................................................................................................................... -40°C
TA_MAX.................................................................................................................................... +85°C
Extended Temperature
TA_MIN...................................................................................................................................... -40°C
TA_MAX.................................................................................................................................. +125°C
Note 1: See Parameter D002, DC Characteristics: Supply Voltage.
2016-2017 Microchip Technology Inc.
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DS40001839B-page 411
PIC16(L)F18326/18346
FIGURE 35-1:
VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C, PIC16F18326/18346 ONLY
5.5
2.5
2.3
0
4
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 35-7 for each Oscillator mode’s supported frequencies.
FIGURE 35-2:
VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C, PIC16LF18326/18346
ONLY
3.6
2.5
1.8
0
4
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 35-7 for each Oscillator mode’s supported frequencies.
DS40001839B-page 412
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PIC16(L)F18326/18346
35.3 DC Characteristics
TABLE 35-1: SUPPLY VOLTAGE
PIC16LF18326/18346
Standard Operating Conditions (unless otherwise stated)
Standard Operating Conditions (unless otherwise stated)
PIC16F18326/18346
Param.
Sym.
Characteristic
Min. Typ.† Max. Units
Conditions
No.
Supply Voltage
D002
VDD
1.8
2.5
—
—
3.6
3.6
V
V
FOSC 16 MHz
FOSC > 16 MHz
D002
VDD
2.3
2.5
—
—
5.5
5.5
V
V
FOSC 16 MHz:
FOSC > 16 MHz
RAM Data Retention(1)
D003
D003
VDR
1.5
1.7
—
—
—
—
V
V
Device in Sleep mode
Device in Sleep mode
VDR
Power-on Reset Release Voltage(2)
D004
VPOR
—
—
1.6
1.6
—
—
V
V
BOR and LPBOR disabled(3)
BOR and LPBOR disabled(3)
D004
VPOR
Power-on Reset ReARM Voltage(2)
D005
VPORR
—
—
0.8
1.5
—
—
V
V
BOR and LPBOR disabled(3)
BOR and LPBOR disabled(3)
D005
VPORR
VDD Rise Rate to ensure Internal Power-on Reset Signal(2)
D006
D006
SVDD
SVDD
0.05
0.05
—
—
—
—
V/ms BOR and LPBOR disabled(3)
V/ms BOR and LPBOR disabled(3)
†
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode or during a device Reset, without losing RAM
data.
2: See Figure 35-3.
3: See Table 35-11 for BOR and LPBOR trip point information.
2016-2017 Microchip Technology Inc.
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DS40001839B-page 413
PIC16(L)F18326/18346
FIGURE 35-3:
POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
SVDD
VSS
NPOR(1)
POR REARM
VSS
(3)
TPOR
(2)
TVLOW
Note 1: When NPOR is low, the device is held in Reset.
2: TPOR 1 s typical.
3: TVLOW 2.7 s typical.
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(1,2)
TABLE 35-2: SUPPLY CURRENT (IDD)
Standard Operating Conditions (unless otherwise stated)
PIC16LF18326/18346
PIC16F18326/18346
Standard Operating Conditions (unless otherwise stated)
Conditions
Note
Param.
Symbol
No.
Device Characteristics
XT = 4 MHz
Min. Typ.† Max. Units
VDD
IDDXT4
—
—
—
—
—
—
—
—
—
—
321 455
332 479
uA 3.0V
uA 3.0V
mA 3.0V
mA 3.0V
mA 3.0V
mA 3.0V
mA 3.0V
mA 3.0V
D100
D100
D101
D101
D102
D102
D103
D103
D104
D104
IDDXT4
XT = 4 MHz
IDDHFO16
IDDHFO16
IDDHFOPLL
IDDHFOPLL
HFINTOSC = 16 MHz
HFINTOSC = 16 MHz
HFINTOSC = 32 MHz
HFINTOSC = 32 MHz
1.3
1.4
2.2
2.3
2.2
2.3
1.8
1.9
2.8
2.9
2.8
2.9
IDDHSPLL32 HS+PLL = 32 MHz
IDDHSPLL32 HS+PLL = 32 MHz
IDDIDLE
IDDIDLE
IDLE Mode, HFINTOSC = 16 MHz
804 1283 uA 3.0V
816 1284 uA 3.0V
IDLE Mode, HFINTOSC = 16 MHz
DOZE mode, HFINTOSC = 16 MHz,
DOZE Ratio = 16
(3)
(3)
D105
D105
IDDDOZE
—
—
863
875
—
—
uA 3.0V
uA 3.0V
DOZE mode, HFINTOSC = 16 MHz,
DOZE Ratio = 16
IDDDOZE
†
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.
3: IDDDOZE = [IDDIDLE*(N-1)/N] + IDDHFO16/N where N = DOZE Ration (see Register 9-2).
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DS40001839B-page 415
PIC16(L)F18326/18346
(1,2,3)
TABLE 35-3: POWER-DOWN CURRENTS (IPD)
PIC16LF18326/18346
Standard Operating Conditions (unless otherwise stated)
Standard Operating Conditions (unless otherwise stated)
VREGPM = 1
PIC16F18326/18346
Conditions
Param.
Symbol
No.
Max.
+85°C +125°C
Max.
Device Characteristics
IPD Base
Min. Typ.†
Units
VDD
Note
D200
D200
IPD
IPD
—
—
—
—
0.05
0.8
13
2
4
9
A 3.0V
A 3.0V
IPD Base
12
27
13
22
5
A 3.0V VREGPM = 0
A 3.0V
D201
D201
IPD_WDT
IPD_WDT
Low-Frequency Internal
Oscillator/WDT
0.8
Low-Frequency Internal
Oscillator/WDT
—
0.9
5
13
A 3.0V
D202
D202
D203
D203
D204
D204
D205
IPD_SOSC Secondary Oscillator (SOSC)
IPD_SOSC Secondary Oscillator (SOSC)
—
—
—
—
—
—
—
0.6
0.8
40
33
12
12
3
5
9
13
15
47
44
19
20
13
A 3.0V
A 3.0V
A 3.0V
A 3.0V
A 3.0V
A 3.0V
A 3.0V
IPD_FVR
IPD_FVR
IPD_BOR
IPD_BOR
FVR
47
44
17
18
5
FVR
Brown-out Reset (BOR)
Brown-out Reset (BOR)
IPD_LPBOR Low Power Brown-out Reset
(LPBOR)
D205
IPD_LPBOR Low Power Brown-out Reset
(LPBOR)
—
4
5
13
A 3.0V
D207
D207
D208
D208
IPD_ADCA ADC - Active
IPD_ADCA ADC - Active
—
—
—
—
0.9
0.9
32
5
5
13
13
45
44
A 3.0V ADC is converting(4)
A 3.0V ADC is converting(4)
A 3.0V
IPD_CMP
IPD_CMP
Comparator
Comparator
43
42
31
A 3.0V
*
These parameters are characterized but not tested.
†
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The peripheral current is the sum of the base IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit.
Max values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.
3: All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is
available.
4: ADC clock source is ADCRC.
DS40001839B-page 416
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TABLE 35-4: I/O PORTS
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min.
Typ.†
Max.
Units
Conditions
VIL
Input Low Voltage
I/O PORT:
D300
D301
D302
D303
D304
D305
with TTL buffer
—
—
—
—
—
—
—
—
—
—
—
—
0.8
V
V
V
V
V
V
4.5V VDD 5.5V
1.8V VDD 4.5V
2.0V VDD 5.5V
0.15 VDD
0.2 VDD
0.3 VDD
0.8
with Schmitt Trigger buffer
2
with I C levels
with SMBus levels
MCLR
2.7V VDD 5.5V
0.2 VDD
VIH
Input High Voltage
I/O PORT:
D320
D321
D322
D323
D324
D325
with TTL buffer
2.0
0.25 VDD + 0.8
0.8 VDD
0.7 VDD
2.1
—
—
—
—
—
—
—
—
—
—
—
—
V
V
V
V
V
V
4.5V VDD 5.5V
1.8V VDD 4.5V
2.0V VDD 5.5V
with Schmitt Trigger buffer
2
with I C levels
with SMBus levels
MCLR
2.7V VDD 5.5V
0.7 VDD
(2)
IIL
Input Leakage Current
D340
D341
D342
I/O Ports
—
—
—
± 5
± 5
± 125
± 1000
± 200
nA
nA
nA
VSS VPIN VDD,
Pin at high-impedance, 85°C
VSS VPIN VDD,
Pin at high-impedance, 125°C
(2)
MCLR
± 50
VSS VPIN VDD,
Pin at high-impedance, 85°C
IPUR Weak Pull-up Current
D350
D360
25
—
120
—
200
0.6
A VDD = 3.0V, VPIN = VSS
(3)
VOL
VOH
CIO
Output Low Voltage
I/O ports
V
IOL = 10.0 mA, VDD = 3.0V
IOH = 6.0 mA, VDD = 3.0V
(3)
Output High Voltage
I/O ports
D370
D380
VDD - 0.7
—
—
5
—
V
All I/O pins
50
pF
*
These parameters are characterized but not tested.
†
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Negative current is defined as current sourced by the pin.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Excluding OSC2 in CLKOUT mode.
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DS40001839B-page 417
PIC16(L)F18326/18346
TABLE 35-5: I/O AND CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Param.
Sym.
Characteristic
Min. Typ.† Max. Units
Conditions
No.
High Voltage Entry Programming Mode Specifications
Voltage on MCLR/VPP pin to
MEM01 VIHH
8
—
—
9
V
Note 2
enter Programming mode
Current on MCLR/VPP pin during
MEM02 IPPGM
—
600
uA Note 2
Programming mode
Programming Mode Specifications
MEM10 VBE
VDD for Bulk Erase
—
—
2.7
—
—
3
V
Supply Current during
Programming Operation
MEM11 IDDPGM
mA
Data EEPROM Memory Specifications
MEM20 ED DataEE Byte Endurance
100k
—
—
—
—
E/W -40°C TA 85°C
Provided no other
Year
MEM21 TD_RET Characteristic Retention
40
specifications are violated
Total Erase/Write Cycles before
MEM22 ND_REF
Refresh
—
—
100k
E/W
VDD for Read or Erase/Write
MEM23 VD_RW
Operation
VDDMIN
—
—
VDDMAX
5.0
V
MEM24 TD_BEW Byte Erase and Write Cycle Time
4.0
ms
Program Flash Memory Specifications
-40°C TA 85°C
(Note 1)
MEM30 EP
Flash Memory Cell Endurance
10k
—
—
—
—
E/W
High-Endurance Flash Memory
Cell Endurance
MEM31 EPHEF
100k
E/W TBD
Provided no other
specifications are violated
MEM32 TP_RET Characteristic Retention
—
40
—
—
—
Year
V
MEM33 VP_RD
MEM34 VP_REW
VDD for Read Operation
VDDMIN
VDDMIN
VDDMAX
VDDMAX
VDD for Row Erase or Write
Operation
V
Self-Timed Row Erase or
Self-Timed Write
MEM35 TP_REW
—
2.0
2.5
ms
†
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Flash Memory Cell Endurance for the Flash memory is defined as: One Row Erase operation and one
Self-Timed Write.
2: Required only if CONFIG3.LVP is disabled.
DS40001839B-page 418
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PIC16(L)F18326/18346
TABLE 35-6: THERMAL CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
JA
Characteristic
Typ. Units
Conditions
70.0
95.3
C/W 14-pin PDIP package
C/W 14-pin SOIC package
TH01
Thermal Resistance Junction to
Ambient
100.0 C/W 14-pin TSSOP package
51.5
62.2
87.3
77.7
43.0
C/W 16-pin UQFN 4x4mm package
C/W 20-pin PDIP package
C/W 20-pin SSOP package
C/W 20-pin SOIC package
C/W 20-pin UQFN 4x4mm package
TH02
JC
Thermal Resistance Junction to
Case
32.75 C/W 14-pin PDIP package
31.0
24.4
5.4
C/W 14-pin SOIC package
C/W 14-pin TSSOP package
C/W 16-pin UQFN 4x4mm package
C/W 20-pin PDIP package
C/W 20-pin SSOP package
C/W 20-pin SOIC package
C/W 20-pin UQFN 4x4mm package
C
27.5
31.1
23.1
5.3
TH03
TH04
TH05
TH06
TH07
TJMAX
PD
Maximum Junction Temperature
Power Dissipation
150
0.800
—
W
W
W
W
PD = PINTERNAL + PI/O
PINTERNAL = IDD x VDD
(1)
PINTERNAL Internal Power Dissipation
PI/O
I/O Power Dissipation
Derated Power
—
PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
(2)
PDER
—
PDER = PDMAX (TJ - TA)/JA
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature, TJ = Junction Temperature
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PIC16(L)F18326/18346
35.4 AC Characteristics
FIGURE 35-4:
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
Note:
CL = 50 pF for all pins.
FIGURE 35-5:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
CLKIN
OS2
OS20
OS2
OS1
CLKOUT
(CLKOUT Mode)
Note:
See Table 35-10.
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(1)
TABLE 35-7: EXTERNAL CLOCK/OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
Sym.
Characteristic
Min.
Typ.†
Max.
Units
Conditions
No.
ECL Oscillator
OS1
OS2
FECL
Clock Frequency
—
—
—
500
60
kHz
%
TECL_DC
Clock Duty Cycle
40
ECM Oscillator
OS3
OS4
FECM
Clock Frequency
Clock Duty Cycle
—
—
—
4
MHz Note 4
TECM_DC
40
60
%
ECH Oscillator
OS5
OS6
FECH
Clock Frequency
Clock Duty Cycle
—
—
—
32
60
MHz
%
TECH_DC
40
LP Oscillator
OS7
XT Oscillator
OS8
HS Oscillator
OS9
System Clock
FLP
Clock Frequency
Clock Frequency
Clock Frequency
—
—
—
—
—
—
100
4
kHz
Note 4
FXT
MHz Note 4
MHz Note 4
FHS
20
OS20
OS21
OS22
FOSC
FCY
TCY
System Clock Frequency
Instruction Frequency
Instruction Period
—
—
—
32
—
—
MHz Note 2, Note 3
FOSC/4
1/FCY
MHz
ns
125
*
These parameters are characterized but not tested.
†
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “min”
values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle
time limit is “DC” (no clock) for all devices.
2: The system clock frequency (FOSC) is selected by the “main clock switch controls” as described in
Section 7.3 “Clock Switching”.
3: The system clock frequency (FOSC) must meet the voltage requirements defined in the Section 35.2
“Standard Operating Conditions”. LP, XT and HS oscillator modes require an appropriate crystal or
resonator to be connected to the device.
4: For clocking the device with an external square wave, one of the EC mode selections must be used.
2016-2017 Microchip Technology Inc.
Preliminary
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(1)
TABLE 35-8: OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min. Typ.† Max. Units
Conditions
OS20
FHFOSC
Precision Calibrated HFINTOSC
Frequency
3.92
—
4
4.08 MHz 25°C
MHz -40°C to 125°C (2)
OS20
FHFOSC
Precision Calibrated HFINTOSC
Frequency
4
8
—
12
16
32
OS21
FHFOSCLP Low-Power Optimized HFINTOSC
Frequency
0.93
1.86
1
2
1.07 MHz
2.14 MHz
OS23
OS24
FLFOSC
Internal LFINTOSC Frequency
—
—
31
—
kHz
THFOSCST HFINTOSC Wake-up from Sleep
Start-up Time
11
50
20
—
s
s
VREGPM = 0
VREGPM = 1
OS26
*
TLFOSCST LFINTOSC Wake-up from Sleep
Start-up Time
—
0.2
—
ms
These parameters are characterized but not tested.
†
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 F and 0.01 F values in parallel are recommended.
2: See Figure 35-6.
FIGURE 35-6:
PRECISION CALIBRATED HFINTOSC FREQUENCY ACCURACY OVER DEVICE
VDD AND TEMPERATURE
125
± 5%
± 3%
85
60
± 2%
0
± 5%
-40
1.8
2.0
2.3
3.5
4.0
VDD (V)
4.5
5.0
5.5
3.0
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TABLE 35-9: PLL CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Param.
Sym.
Characteristic
Min.
Typ.†
Max.
Units Conditions
No.
PLL01 FPLLIN
PLL Input Frequency Range
4
16
—
—
8
32
MHz
MHz
s
PLL02 FPLLOUT PLL Output Frequency Range
PLL03 TPLLST
PLL04 FPLLJIT
PLL Lock Time from Start-up
—
200
—
—
PLL Output Frequency Stability (Jitter)
-0.25
0.25
%
*
These parameters are characterized but not tested.
†
Data in “Typ.” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 35-7:
CLKOUT AND I/O TIMING
Cycle
Write
Q4
Fetch
Q1
Read
Q2
Execute
Q3
FOSC
IO2
IO1
IO10
IO12
CLKOUT
IO8
IO7
IO4
IO5
I/O pin
(Input)
IO3
I/O pin
(Output)
New Value
Old Value
IO7, IO8
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TABLE 35-10: CLKOUT AND I/O TIMING SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min. Typ.† Max. Units
Conditions
IO1
TCLKOUTH
CLKOUT rising edge delay
(rising edge FOSC (Q1 cycle) to
falling edge CLKOUT
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
IO2
IO3
IO4
IO5
TCLKOUTL
TIO_VALID
TIO_SETUP
TIO_HOLD
CLKOUT falling edge delay
(rising edge FOSC (Q3 cycle) to
rising edge CLKOUT
Port output valid time
(rising edge FOSC (Q1 cycle) to
port valid)
Port input setup time
(Setup time before rising edge
FOSC - Q2 cycle)
Port input hold time
(Hold time after rising edge
FOSC - Q2 cycle)
IO6
TIOR_SLREN Port I/O rise time, slew rate
enabled
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
VDD = 3.0V, Load conditions
VDD = 3.0V, Load conditions
VDD = 3.0V, Load conditions
VDD = 3.0V, Load conditions
IO7
TIOR_SLRDIS Port I/O rise time, slew rate
disabled
IO8
TIOF_SLREN Port I/O fall time, slew rate
enabled
IO9
TIOF_SLRDIS Port I/O fall time, slew rate
disabled
IO10
IO11
TINT
INT pin high or low time to trigger
an interrupt
TIOC
Interrupt-on-Change minimum
high or low time to trigger interrupt
*
†
These parameters are characterized but not tested.
Data in “Typ.” column is at 3.0V, 25C unless otherwise stated.
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FIGURE 35-8:
RESET, WATCHDOG TIMER, OSCILLATOR, START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
RST01
Internal
POR
RST04
RST05
PWRT
Time-out
OSC
Start-up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
RST03
RST02
RST02
I/O pins
Note 1: Asserted low.
FIGURE 35-9:
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR and VHYST
VBOR
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset
33(1)
(due to BOR)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. 2 ms delay if
PWRTE = 0.
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TABLE 35-11: RESET, WATCHDOG TIMER, OSCILLATOR, START-UP TIMER, POWER-UP TIMER,
BROWN-OUT RESET AND LOW POWER BROWN-OUT RESET SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min. Typ.† Max. Units
Conditions
RST01 TMCLR
RST02 TIOZ
RST03 TWDT
MCLR Pulse Width Low to
ensure Reset
2
—
—
16
—
2
s
s
I/O high-impedance from
Reset detection
—
10
Watchdog Timer Time-out
Period
27
ms 16 ms Nominal Reset Time
RST04* TPWRT
RST05 TOST
Power-up Timer Period
40
—
65
140
—
ms
Oscillator Start-up Timer
Period(1,2)
1024
TOSC (Note3)
RST06 VBOR
Brown-out Reset Voltage(4)
2.55 2.70 2.85
2.30 2.45 2.60
1.80 1.90 2.10
V
V
V
BORV = 0
BORV = 1(PIC16F18326/18346)
BORV = 1(PIC16LF18326/18346)
RST07 VBORHYS Brown-out Reset Hysteresis
0
1
25
3
75
35
mV
RST08 TBORDC
Brown-out Reset Response
Time
s
RST09 VLPBOR
Low-Power Brown-out Reset
Voltage
1.8
2.1
2.5
V
PIC16LF18326/18346
*
These parameters are characterized but not tested.
†
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator opera-
tion and/or higher than expected current consumption. All devices are tested to operate at “min” values
with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time
limit is “DC” (no clock) for all devices.
2: By design.
3: Period of the slower clock.
4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
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TABLE 35-12: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
Param.
Sym.
Characteristic
Resolution
Min. Typ.†
Max. Units
Conditions
No.
AD01
AD02
AD03
AD04
AD05
AD06
NR
—
—
—
—
—
1.8
—
±0.1
±0.1
0.5
10
±1.0
±1.0
2
bit
EIL
Integral Error
Differential Error
Offset Error
LSb ADCREF+ = 3.0V, ADCREF- = 0V
LSb ADCREF+ = 3.0V, ADCREF-= 0V
LSb ADCREF+ = 3.0V, ADCREF- = 0V
LSb ADCREF+ = 3.0V, ADCREF- = 0V
V
EDL
EOFF
EGN
Gain Error
±0.2
—
±1.0
VDD
VADREF ADC Reference Voltage
(ADREF+)(3)
AD07
AD06
VAIN
Full-Scale Range
VSS
1.8
—
—
ADREF+
VDD
V
V
VADREF ADC Reference Voltage
(ADREF+ - ADREF-)(3)
AD07
AD08
VAIN
ZAIN
Full-Scale Range
ADREF-
—
—
ADREF+
—
V
RecommendedImpedance
of Analog Voltage Source
10
k
AD09
RVREF ADC Voltage Reference
Ladder Impedance
—
—
—
k
*
These parameters are characterized but not tested.
†
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Total Absolute Error is the sum of the offset, gain and integral non-linearity (INL) errors.
2: The ADC conversion result never decreases with an increase in the input and has no missing codes.
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TABLE 35-13: ANALOG-TO DIGITAL CONVERTER (ADC) CONVERSION TIMING SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
TAD
Characteristic
ADC Clock Period
Min.
Typ.†
Max.
Units
Conditions
AD20
1
—
9
us
Using FOSC as the ADC
clock source;
ADCS ! = x11
AD21
AD22
1
2
6
us
Using ADCRC as the
ADC clock source;
ADCS = x11
TCNV Conversion Time
TACQ Acquisition Time
—
11
—
TAD Set of GO/DONE bit to
Clear of GO/DONE bit
AD23
AD24
—
—
—
2
—
—
—
us
THCD Sample and Hold Capacitor
Disconnect Time
—
—
us
us
FOSC based clock source
ADCRC based clock
source
*
These parameters are characterized but not tested.
†
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 35-10:
ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED)
BSF ADCON0, GO
AD133
Q4
1 TCY
AD131
AD130
ADC_clk
9
8
7
6
3
2
1
0
ADC Data
NEW_DATA
1 TCY
OLD_DATA
ADRES
ADIF
GO
DONE
Sampling Stopped
AD132
Sample
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FIGURE 35-11:
ADC CONVERSION TIMING (ADC CLOCK FROM ADCRC)
BSF ADCON0, GO
AD133
Q4
1 TCY
AD131
AD130
ADC_clk
9
8
7
3
2
1
0
6
ADC Data
NEW_DATA
1 TCY
OLD_DATA
ADRES
ADIF
GO
DONE
Sampling Stopped
AD132
Sample
Note:
If the ADC clock source is selected as ADCRC, a time of TCY is added before the ADC clock starts. This
allows the SLEEPinstruction to be executed.
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TABLE 35-14: COMPARATOR SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
See Section 36.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
Param
No.
Sym.
Characteristics
Input Offset Voltage
Min.
Typ.
Max. Units
Comments
CM01
CM02
CM03
VIOFF
—
GND
—
—
—
50
±50
VDD
—
mV VICM = VDD/2
VICM
Input Common Mode Voltage
V
CMRR
Common Mode Input Rejection
Ratio
dB
CM04
CM05
CHYST
Comparator Hysteresis
15
—
—
—
25
300
220
—
35
600
500
10
mV
ns
(1)
TRESP
Response Time, Rising Edge
Response Time, Falling Edge
Mode Change to Valid Output
ns
(2)
CM06*
TMCV2VO
us
*
These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS
to VDD.
2: A mode change includes changing any of the control register values, including module enable.
TABLE 35-15: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
Param
No.
Sym.
Characteristics
Step Size
Min.
Typ.†
Max.
Units
Comments
DSB01
DSB01
DSB03*
DSB04*
VLSB
—
—
—
—
VDD/32
—
—
0.5
—
V
LSb
VACC
RUNIT
TST
Absolute Accuracy
Unit Resistor Value
Settling Time(1)
6000
—
10
s
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Settling time measured while DACR<4:0> transitions from ‘00000’ to ‘01111’.
TABLE 35-16: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol
Characteristic
Min. Typ. Max. Units
Conditions
-4
4
%
FVR01 VFVR1
FVR02 VFVR2
FVR03 VFVR4
FVR04 TFVRST
1x Gain (1.024V nominal)
2x Gain (2.048V nominal)
4x Gain (4.096V nominal)
FVR Start-up Time
—
—
—
—
VDD 2.5V, -40°C to 85°C
VDD 2.5V, -40°C to 85°C
VDD 4.75V, -40°C to 85°C
-4
-5
—
4
5
%
%
—
s
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FIGURE 35-12:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
45
46
49
47
TMR0 or
TMR1
TABLE 35-17: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
Sym.
TT0H
Characteristic
Min.
Typ.†
Max. Units
Conditions
No.
40*
T0CKI High Pulse Width
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
10
0.5 TCY + 20
10
41*
42*
TT0L
TT0P
T0CKI Low Pulse Width
T0CKI Period
Greater of:
20 or TCY + 40
N
N = prescale
value
45*
46*
47*
TT1H
TT1L
TT1P
T1CKI High Time Synchronous, No Prescaler
Synchronous, with Prescaler
Asynchronous
0.5 TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
15
30
T1CKI Low Time Synchronous, No Prescaler
Synchronous, with Prescaler
Asynchronous
0.5 TCY + 20
15
30
T1CKI Input
Period
Synchronous
Greater of:
30 or TCY + 40
N
N = prescale
value
Asynchronous
60
—
—
ns
48
FT1
Secondary Oscillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN)
32.4
32.768 33.1
kHz
49*
TCKEZTMR1 Delay from External Clock Edge to Timer
Increment
2 TOSC
—
7 TOSC
—
Timers in Sync
mode
*
These parameters are characterized but not tested.
†
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
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FIGURE 35-13:
CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCPx
(Capture mode)
CC01
CC02
CC03
Note: Refer to Figure 35-4 for Load conditions.
TABLE 35-18: CAPTURE/COMPARE/PWM CHARACTERISTICS (CCP)
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min.
Typ.† Max. Units
Conditions
CC01* TccL CCPx Input Low Time No Prescaler
0.5TCY +
20
—
—
ns
With Prescaler
20
—
—
—
—
ns
ns
CC02* TccH CCPx Input High
Time
No Prescaler
0.5TCY +
20
With Prescaler
20
—
—
—
—
ns
CC03* TccP CCPx Input Period
3TCY + 40
N
ns N = prescale value
*
These parameters are characterized but not tested.
†
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
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FIGURE 35-14:
CLC PROPAGATION TIMING
LCx_in[n](1)
CLC
Input time
CLC
Module
CLC
Output time
CLCxINn
CLCx
CLCx
LCx_out(1)
LCx_out(1)
CLC
CLC
Module
CLC
Output time
CLCxINn
LCx_in[n](1)
Input time
CLC01
CLC02
CLC03
Note 1: See Figure 21-1, "CLCx Simplified Block Diagram" to identify specific CLC signals.
TABLE 35-19: CONFIGURABLE LOGIC CELL (CLC) CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min. Typ.† Max. Units
Conditions
CLC01* TCLCIN
CLC02* TCLC
CLC input time
—
7
OS17 ns (Note 1)
CLC module input to output propagation
time
—
—
24
12
—
—
ns VDD = 1.8V
ns VDD > 3.6V
CLC03* TCLCOUT CLC output time
Rise Time
Fall Time
—
—
—
OS18
OS19
32
—
—
—
—
(Note 1)
(Note 1)
CLC04* FCLCMAX CLC maximum switching frequency
FOSC MHz
*
These parameters are characterized but not tested.
†
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: See Table 35-10 for OS17, OS18 and OS19 rise and fall times.
FIGURE 35-15:
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
CK
DT
US121
US121
US122
US120
Refer to Figure 35-4 for Load conditions.
Note:
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TABLE 35-20: EUSART SYNCHRONOUS TRANSMISSION CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
Conditions
US120 TCKH2DTV
US121 TCKRF
US122 TDTRF
SYNC XMIT (Master and Slave)
Clock high to data-out valid
—
—
—
—
—
—
80
100
45
ns 3.0V VDD 5.5V
ns 1.8V VDD 5.5V
ns 3.0V VDD 5.5V
ns 1.8V VDD 5.5V
ns 3.0V VDD 5.5V
ns 1.8V VDD 5.5V
Clock out rise time and fall time
(Master mode)
50
Data-out rise time and fall time
45
50
FIGURE 35-16:
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
CK
DT
US125
US126
Refer to Figure 35-4 for Load conditions.
Note:
TABLE 35-21: EUSART SYNCHRONOUS RECEIVE CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
Conditions
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-setup before CK (DT hold time)
10
15
—
—
ns
ns
US126 TCKL2DTL Data-hold after CK (DT hold time)
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FIGURE 35-17:
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SS
SP81
SCK
(CKP = 0)
SP71
SP72
SP78
SP79
SP79
SCK
(CKP = 1)
SP78
LSb
SP80
MSb
bit 6 - - - - - -1
SDO
SDI
SP75, SP76
bit 6 - - - -1
MSb In
LSb In
SP74
SP73
Note:
Refer to Figure 35-4 for Load conditions.
FIGURE 35-18:
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
SP81
SCK
(CKP = 0)
SP71
SP73
SP72
SP79
SCK
(CKP = 1)
SP80
SP78
LSb
MSb
bit 6 - - - - - -1
SDO
SP75, SP76
bit 6 - - - -1
SDI
MSb In
SP74
Refer to Figure 35-4 for Load conditions.
LSb In
Note:
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FIGURE 35-19:
SPI SLAVE MODE TIMING (CKE = 0)
SS
SP70
SCK
(CKP = 0)
SP83
SP71
SP72
SP78
SP79
SP79
SCK
(CKP = 1)
SP78
LSb
SP80
MSb
SDO
SDI
bit 6 - - - - - -1
SP75, SP76
bit 6 - - - -1
SP77
MSb In
SP74
SP73
LSb In
Note:
Refer to Figure 35-4 for Load conditions.
FIGURE 35-20:
SPI SLAVE MODE TIMING (CKE = 1)
SP82
SP70
SS
SP83
SCK
(CKP = 0)
SP72
SP71
SCK
(CKP = 1)
SP80
MSb
bit 6 - - - - - -1
LSb
SDO
SDI
SP77
SP75, SP76
bit 6 - - - -1
MSb In
SP74
LSb In
Note:
Refer to Figure 35-4 for Load conditions.
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TABLE 35-22: SPI MODE CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol
Characteristic
Min.
Typ.† Max. Units
Conditions
SP70* TSSL2SCH, SS to SCK or SCK input
2.25*TCY
—
—
ns
TSSL2SCL
SP71* TSCH
SP72* TSCL
SCK input high time (Slave mode)
SCK input low time (Slave mode)
TCY + 20
TCY + 20
100
—
—
—
—
—
—
ns
ns
ns
SP73* TDIV2SCH, Setup time of SDI data input to SCK
TDIV2SCL
edge
SP74* TSCH2DIL,
TSCL2DIL
Hold time of SDI data input to SCK
edge
100
—
—
ns
SP75* TDOR
SDO data output rise time
—
—
10
25
10
—
10
25
10
—
—
—
25
50
25
50
25
50
25
50
145
—
ns 3.0V VDD 5.5V
ns 1.8V VDD 5.5V
SP76* TDOF
SDO data output fall time
—
ns
SP77* TSSH2DOZ SS to SDO output high-impedance
10
ns
SP78* TSCR
SCK output rise time
(Master mode)
—
ns 3.0V VDD 5.5V
ns 1.8V VDD 5.5V
ns
—
SP79* TSCF
SCK output fall time (Master mode)
—
SP80* TSCH2DOV, SDO data output valid after SCK
TSCL2DOV edge
—
ns 3.0V VDD 5.5V
ns 1.8V VDD 5.5V
ns
—
SP81* TDOV2SCH, SDO data output setup to SCK
TDOV2SCL edge
1 Tcy
SP82* TSSL2DOV
SDO data output valid after SS
edge
—
—
—
50
—
ns
ns
SP83* TSCH2SSH, SS after SCK edge
1.5 TCY + 40
TSCL2SSH
*
These parameters are characterized but not tested.
†
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 437
PIC16(L)F18326/18346
2
FIGURE 35-21:
I C BUS START/STOP BITS TIMING
SCL
SP93
SP91
SP90
SP92
SDA
Stop
Condition
Start
Condition
Note:
Refer to Figure 35-4 for Load conditions.
2
TABLE 35-23: I C BUS START/STOP BITS CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol
Characteristic
Min. Typ. Max. Units
Conditions
SP90*
TSU:STA Start condition
Setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for Repeated
Start condition
SP91*
SP92*
SP93
THD:STA Start condition
Hold time
4000
600
ns After this period, the first
clock pulse is generated
TSU:STO Stop condition
Setup time
4700
600
ns
THD:STO Stop condition
Hold time
4000
600
ns
*
These parameters are characterized but not tested.
2
FIGURE 35-22:
I C BUS DATA TIMING
SP100
SP102
SP103
SP101
SCL
SP90
SP91
SP106
SP107
SP92
SDA
In
SP110
SP109
SP109
SDA
Out
Note:
Refer to Figure 35-4 for Load conditions.
DS40001839B-page 438
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
2
TABLE 35-24: I C BUS DATA CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol
Characteristic
Min.
Max. Units
Conditions
SP100*
THIGH
Clock high time
Clock low time
100 kHz mode
4.0
—
—
s
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
Device must operate at a
minimum of 10 MHz
SSP module
1.5TCY
4.7
—
—
SP101*
TLOW
100 kHz mode
s
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
Device must operate at a
minimum of 10 MHz
SSP module
1.5TCY
—
—
SP102*
SP103*
TR
TF
SDA and SCL rise 100 kHz mode
1000
300
ns
ns
time
400 kHz mode
20 +
CB is specified to be from
10-400 pF
0.1CB
SDA and SCL fall
time
100 kHz mode
400 kHz mode
—
250
250
ns
ns
20 +
0.1CB
CB is specified to be from
10-400 pF
SP106*
SP107*
SP109*
SP110*
THD:DAT Data input hold
time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
0
—
0.9
—
ns
s
ns
ns
ns
ns
s
s
0
TSU:DAT Data input setup
time
250
100
—
(Note 2)
(Note 1)
—
TAA
Output valid from
clock
3500
—
—
TBUF
Bus free time
4.7
1.3
—
Time the bus must be free
before a new transmission
can start
—
SP111
CB
Bus capacitive loading
—
400
pF
*
These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the
requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not
stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it
must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
Standard mode I2C bus specification), before the SCL line is released.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 439
PIC16(L)F18326/18346
36.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS
Charts and graphs are not available at this time.
DS40001839B-page 440
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
37.1 MPLAB X Integrated Development
Environment Software
37.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for high-
performance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
• Integrated Development Environment
- MPLAB® X IDE Software
- MPLAB Xpress IDE Software
- Microchip Code Configurator (MCC)
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Automatic code formatting based on user-defined
rules
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Live parsing
User-Friendly, Customizable Interface:
• Third-party development tools
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 441
PIC16(L)F18326/18346
37.2 MPLAB XC Compilers
37.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other relo-
catable object files and archives to create an execut-
able file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assem-
bler include:
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
37.5 MPLAB Assembler, Linker and
Librarian for Various Device
Families
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
37.3 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
DS40001839B-page 442
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
37.6 MPLAB X SIM Software Simulator
37.8 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a high-
speed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
37.9 PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and program-
ming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a full-
speed USB interface and can be connected to the tar-
get via a Microchip debug (RJ-11) connector (compati-
ble with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
37.7 MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
37.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a mod-
ular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
The emulator is field upgradeable through future firm-
ware downloads in MPLAB X IDE. MPLAB REAL ICE
offers significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 443
PIC16(L)F18326/18346
37.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
37.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide applica-
tion firmware and source code for examination and
modification.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstra-
®
tion software for analog filter design, KEELOQ security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS40001839B-page 444
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
38.0 PACKAGING INFORMATION
38.1 Package Marking Information
14-Lead PDIP (300 mil)
Example
PIC16LF18326
e
3
P
1519017
14-Lead SOIC (3.90 mm)
Example
PIC16F18326
e
3
SL
1519017
14-Lead TSSOP (4.4 mm)
Example
XXXXXXXX
YYWW
F18326ST
1519
017
NNN
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 445
PIC16(L)F18326/18346
Package Marking Information (Continued)
16-Lead UQFN (4x4x0.5mm)
Example
PIC16
PIN 1
PIN 1
F18326
e
3
ML
519017
20-Lead PDIP (300 mil)
Example
PIC16LF18346
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
P
e3
1519017
YYWWNNN
20-Lead SOIC (7.50 mm)
Example
PIC16LF18346
e
3
SO
1519017
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS40001839B-page 446
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
Package Marking Information (Continued)
20-Lead SSOP (5.30 mm)
Example
16F18346
SS
e
3
1405017
20-Lead UQFN (4x4x0.5 mm)
Example
PIC16
PIN 1
PIN 1
F18346
e
3
ML
519017
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 447
PIC16(L)F18326/18346
38.2 Package Details
The following sections give the technical details of the packages.
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ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ!"ꢇꢈꢅꢃꢄ#ꢉ$ꢅ%ꢉꢇ&"ꢊꢉꢅ'ꢇꢋꢅꢆꢇꢊꢋ*ꢅ;"&ꢅ'"!&ꢅ;ꢉꢅꢈꢌꢍꢇ&ꢉ#ꢅ?ꢃ&ꢎꢅ&ꢎꢉꢅꢎꢇ&ꢍꢎꢉ#ꢅꢇꢊꢉꢇꢁ
ꢏꢁ ꢐꢅꢑꢃꢒꢄꢃ%ꢃꢍꢇꢄ&ꢅGꢎꢇꢊꢇꢍ&ꢉꢊꢃ!&ꢃꢍꢁ
Jꢁ ꢓꢃ'ꢉꢄ!ꢃꢌꢄ!ꢅꢓꢅꢇꢄ#ꢅXꢀꢅ#ꢌꢅꢄꢌ&ꢅꢃꢄꢍꢈ"#ꢉꢅ'ꢌꢈ#ꢅ%ꢈꢇ!ꢎꢅꢌꢊꢅꢔꢊꢌ&ꢊ"!ꢃꢌꢄ!ꢁꢅꢕꢌꢈ#ꢅ%ꢈꢇ!ꢎꢅꢌꢊꢅꢔꢊꢌ&ꢊ"!ꢃꢌꢄ!ꢅ!ꢎꢇꢈꢈꢅꢄꢌ&ꢅꢉ$ꢍꢉꢉ#ꢅꢁꢖꢀꢖYꢅꢔꢉꢊꢅ!ꢃ#ꢉꢁ
ꢗꢁ ꢓꢃ'ꢉꢄ!ꢃꢌꢄꢃꢄꢒꢅꢇꢄ#ꢅ&ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢒꢅꢔꢉꢊꢅꢘꢑꢕXꢅ[ꢀꢗꢁ\ꢕꢁ
]ꢑG^ꢅ]ꢇ!ꢃꢍꢅꢓꢃ'ꢉꢄ!ꢃꢌꢄꢁꢅꢙꢎꢉꢌꢊꢉ&ꢃꢍꢇꢈꢈꢋꢅꢉ$ꢇꢍ&ꢅꢆꢇꢈ"ꢉꢅ!ꢎꢌ?ꢄꢅ?ꢃ&ꢎꢌ"&ꢅ&ꢌꢈꢉꢊꢇꢄꢍꢉ!ꢁ
ꢕꢃꢍꢊꢌꢍꢎꢃꢔ ꢙꢉꢍꢎꢄꢌꢈꢌꢒꢋ ꢓꢊꢇ?ꢃꢄꢒ Gꢖꢗꢟꢖꢖ\]
DS40001839B-page 448
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 449
PIC16(L)F18326/18346
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001839B-page 450
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
ꢝꢙꢋꢄ! `ꢌꢊꢅ&ꢎꢉꢅ'ꢌ!&ꢅꢍ"ꢊꢊꢉꢄ&ꢅꢔꢇꢍjꢇꢒꢉꢅ#ꢊꢇ?ꢃꢄꢒ!*ꢅꢔꢈꢉꢇ!ꢉꢅ!ꢉꢉꢅ&ꢎꢉꢅꢕꢃꢍꢊꢌꢍꢎꢃꢔꢅꢂꢇꢍjꢇꢒꢃꢄꢒꢅꢑꢔꢉꢍꢃ%ꢃꢍꢇ&ꢃꢌꢄꢅꢈꢌꢍꢇ&ꢉ#ꢅꢇ&ꢅ
ꢎ&&ꢔ^{{???ꢁ'ꢃꢍꢊꢌꢍꢎꢃꢔꢁꢍꢌ'{ꢔꢇꢍjꢇꢒꢃꢄꢒ
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 451
PIC16(L)F18326/18346
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001839B-page 452
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 453
PIC16(L)F18326/18346
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001839B-page 454
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
E
N
NOTE 1
1
2
(DATUM B)
(DATUM A)
2X
0.20 C
2X
TOP VIEW
0.20 C
0.10 C
A1
C
A
SEATING
PLANE
16X
(A3)
0.08 C
C A B
SIDE VIEW
0.10
D2
0.10
C A B
E2
2
1
e
2
NOTE 1
K
N
L
16X b
0.10
C A B
e
BOTTOM VIEW
Microchip Technology Drawing C04-257A Sheet 1 of 2
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 455
PIC16(L)F18326/18346
16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Pins
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Width
Exposed Pad Width
Overall Length
Exposed Pad Length
Terminal Width
Terminal Length
N
16
0.65 BSC
0.50
e
A
A1
A3
E
E2
D
D2
b
L
0.45
0.00
0.55
0.05
0.02
0.127 REF
4.00 BSC
2.60
4.00 BSC
2.60
2.50
2.70
2.50
0.25
0.30
0.20
2.70
0.35
0.50
-
0.30
0.40
-
Terminal-to-Exposed-Pad
K
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-257A Sheet 2 of 2
DS40001839B-page 456
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body
[UQFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
16
1
2
C2 Y2
Y1
X1
E
SILK SCREEN
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
MILLIMETERS
NOM
0.65 BSC
MIN
MAX
Contact Pitch
Optional Center Pad Width
Optional Center Pad Length
Contact Pad Spacing
Contact Pad Spacing
Contact Pad Width (X16)
Contact Pad Length (X16)
X2
Y2
C1
C2
X1
Y1
2.70
2.70
4.00
4.00
0.35
0.80
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2257A
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 457
PIC16(L)F18326/18346
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ꢝꢙꢋꢄꢊ!
ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ!"ꢇꢈꢅꢃꢄ#ꢉ$ꢅ%ꢉꢇ&"ꢊꢉꢅ'ꢇꢋꢅꢆꢇꢊꢋ*ꢅ;"&ꢅ'"!&ꢅ;ꢉꢅꢈꢌꢍꢇ&ꢉ#ꢅ?ꢃ&ꢎꢃꢄꢅ&ꢎꢉꢅꢎꢇ&ꢍꢎꢉ#ꢅꢇꢊꢉꢇꢁ
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]ꢑG^ ]ꢇ!ꢃꢍꢅꢓꢃ'ꢉꢄ!ꢃꢌꢄꢁꢅꢙꢎꢉꢌꢊꢉ&ꢃꢍꢇꢈꢈꢋꢅꢉ$ꢇꢍ&ꢅꢆꢇꢈ"ꢉꢅ!ꢎꢌ?ꢄꢅ?ꢃ&ꢎꢌ"&ꢅ&ꢌꢈꢉꢊꢇꢄꢍꢉ!ꢁ
ꢕꢃꢍꢊꢌꢍꢎꢃꢔ ꢙꢉꢍꢎꢄꢌꢈꢌꢒꢋ ꢓꢊꢇ?ꢃꢄꢒ Gꢖꢗꢟꢖꢀꢜ]
DS40001839B-page 458
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 459
PIC16(L)F18326/18346
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001839B-page 460
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 461
PIC16(L)F18326/18346
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]ꢑG^ ]ꢇ!ꢃꢍꢅꢓꢃ'ꢉꢄ!ꢃꢌꢄꢁꢅꢙꢎꢉꢌꢊꢉ&ꢃꢍꢇꢈꢈꢋꢅꢉ$ꢇꢍ&ꢅꢆꢇꢈ"ꢉꢅ!ꢎꢌ?ꢄꢅ?ꢃ&ꢎꢌ"&ꢅ&ꢌꢈꢉꢊꢇꢄꢍꢉ!ꢁ
ꢞX`^ ꢞꢉ%ꢉꢊꢉꢄꢍꢉꢅꢓꢃ'ꢉꢄ!ꢃꢌꢄ*ꢅ"!"ꢇꢈꢈꢋꢅ?ꢃ&ꢎꢌ"&ꢅ&ꢌꢈꢉꢊꢇꢄꢍꢉ*ꢅ%ꢌꢊꢅꢃꢄ%ꢌꢊ'ꢇ&ꢃꢌꢄꢅꢔ"ꢊꢔꢌ!ꢉ!ꢅꢌꢄꢈꢋꢁ
ꢕꢃꢍꢊꢌꢍꢎꢃꢔ ꢙꢉꢍꢎꢄꢌꢈꢌꢒꢋ ꢓꢊꢇ?ꢃꢄꢒ Gꢖꢗꢟꢖꢝꢏ]
DS40001839B-page 462
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
20-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.65
0.45
SILK SCREEN
c
Y1
G
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Contact Pitch
Contact Pad Spacing
Contact Pad Width (X20)
E
C
X1
0.65 BSC
7.20
0.45
1.75
Contact Pad Length (X20)
Distance Between Pads
Y1
G
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2072B
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 463
PIC16(L)F18326/18346
20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
E
N
NOTE 1
1
2
(DATUM B)
(DATUM A)
2X
0.20 C
2X
TOP VIEW
0.20 C
0.10 C
A1
C
A
SEATING
PLANE
20X
(A3)
0.08 C
C A B
SIDE VIEW
0.10
D2
L
0.10
C A B
E2
2
1
K
N
NOTE 1
20X b
0.10
C A B
e
BOTTOM VIEW
Microchip Technology Drawing C04-255A Sheet 1 of 2
DS40001839B-page 464
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Width
Exposed Pad Width
Overall Length
Exposed Pad Length
Terminal Width
Terminal Length
N
20
0.50 BSC
0.50
e
A
A1
A3
E
E2
D
D2
b
L
0.45
0.00
0.55
0.05
0.02
0.127 REF
4.00 BSC
2.70
4.00 BSC
2.70
2.60
2.80
2.60
0.20
0.30
0.20
2.80
0.30
0.50
-
0.25
0.40
-
Terminal-to-Exposed-Pad
K
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-255A Sheet 2 of 2
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 465
PIC16(L)F18326/18346
20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
20
1
2
C2 Y2
G1
Y1
X1
E
SILK SCREEN
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
MILLIMETERS
NOM
0.50 BSC
MIN
MAX
Contact Pitch
Optional Center Pad Width
Optional Center Pad Length
Contact Pad Spacing
X2
Y2
C1
C2
X1
Y1
G1
2.80
2.80
4.00
4.00
Contact Pad Spacing
Contact Pad Width (X20)
Contact Pad Length (X20)
Contact Pad to Center Pad (X20)
0.30
0.80
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2255A
DS40001839B-page 466
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A (04/2016)
Initial release of the document.
Revision B (04/2017)
Updated pin diagrams; Minor corrections to Table 1-1;
Added “Guidelines for Getting Started With
PIC16(L)F183XX” chapter; updated Figure 2-1; Added
section 4.1.1.3 NVMREG Access; Section 4.2.1. BANK
SELECTION; Updated ADACT Register; Added new
Figure 4-8; Section 4.5.4 DATA EEPROM MEMORY;
Updated Figure 18-2; Minor changes to all chapters.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 467
PIC16(L)F18326/18346
THE MICROCHIP WEBSITE
CUSTOMER SUPPORT
Microchip provides online support via our website at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the website
at: http://www.microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
DS40001839B-page 468
Preliminary
2016-2017 Microchip Technology Inc.
PIC16(L)F18326/18346
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
[X](1)
PART NO.
X
/XX
XXX
-
Examples:
Device Tape and Reel
Option
Temperature
Range
Package
Pattern
a)
PIC16LF18326- E/P
Extended temperature
PDIP package
b)
PIC16LF18346- E/SO
Extended temperature,
SOIC package
Device:
PIC16F18326, PIC16LF18326,
PIC16F18346, PIC16LF18346.
Tape and Reel
Option:
Blank = Standard packaging (tube or tray)
T
= Tape and Reel(1)
Temperature
Range:
I
E
=
=
-40C to +85C (Industrial)
-40C to +125C (Extended)
Package:(2)
JQ
GZ
P
ST
SL
SO
SS
= 16-lead UQFN (4x4)
= 20-lead UQFN (4x4)
= PDIP
Note 1:
Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package.
Check with your Microchip Sales Office
for package availability with the Tape and
Reel option.
= TSSOP
= 14-lead SOIC
= 20-lead SOIC
= SSOP
2:
Small form-factor packaging options may
be available. Check
Pattern:
QTP, SQTP, Code or Special Requirements
(blank otherwise)
www.microchip.com/packaging for
small-form factor package availability, or
contact your local Sales Office.
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 469
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT
logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR,
Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK
MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST
logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32
logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,
SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are
registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoCompanion, CryptoController,
dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,
ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-
Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi,
MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix,
RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial
Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II,
Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2016-2017, Microchip Technology Incorporated, All Rights
Reserved.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
ISBN: 978-1-5224-1575-6
== ISO/TS 16949 ==
DS40001839B-page 470
Preliminary
2016-2017 Microchip Technology Inc.
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Finland - Espoo
Tel: 358-9-4520-820
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
www.microchip.com
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
France - Saint Cloud
Tel: 33-1-30-60-70-00
India - Pune
Tel: 91-20-3019-1500
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Austin, TX
Tel: 512-257-3370
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Boston
Tel: 49-2129-3766400
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Germany - Heilbronn
Tel: 49-7131-67-3636
China - Dongguan
Tel: 86-769-8702-9880
Germany - Karlsruhe
Tel: 49-721-625370
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Guangzhou
Tel: 86-20-8755-8029
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
Korea - Seoul
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Germany - Rosenheim
Tel: 49-8031-354-560
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Israel - Ra’anana
Tel: 972-9-744-7705
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Detroit
Novi, MI
Tel: 248-848-4000
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Houston, TX
Tel: 281-894-5983
Italy - Padova
Tel: 39-049-7625286
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
China - Shanghai
Tel: 86-21-3326-8000
Fax: 86-21-3326-8021
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Norway - Trondheim
Tel: 47-7289-7561
Los Angeles
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Poland - Warsaw
Tel: 48-22-3325737
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Romania - Bucharest
Tel: 40-21-407-87-50
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Raleigh, NC
Tel: 919-844-7510
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
New York, NY
Tel: 631-435-6000
Sweden - Gothenberg
Tel: 46-31-704-60-40
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Sweden - Stockholm
Tel: 46-8-5090-4654
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
2016-2017 Microchip Technology Inc.
Preliminary
DS40001839B-page 471
11/07/16
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