PIC16F1939T-I/SP [MICROCHIP]
28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology; 28 /40/ 44引脚基于闪存的8位CMOS微控制器与LCD驱动器和纳瓦技术
| 型号： | PIC16F1939T-I/SP |
| 厂家： | 
MICROCHIP |
| 描述： | 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology |
| 文件： | 总418页 (文件大小：6693K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC16F193X/LF193X
Data Sheet
28/40/44-Pin Flash-Based, 8-Bit
CMOS Microcontrollers with
LCD Driver and nanoWatt Technology
© 2008 Microchip Technology Inc.
Preliminary
DS41364A
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
32
PICDEM.net, PICtail, PIC logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS41364A-page ii
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers
Devices Included In This Data Sheet:
Low-Power Features:
• Standby Current:
PIC16F193X Devices:
- 100 nA @ 2.0V, typical (PIC16LF193X)
• Operating Current:
- 6.0 μA @ 32 kHz, 2.0V, typical (PIC16LF193X)
- 54 μA @ 1 MHz, 2.0V, typical (PIC16LF193X)
• Low-Power Watchdog Timer Current:
- 1.0 μA @ 2.0V, typical (PIC16LF193X)
• PIC16F1933
• PIC16F1936
• PIC16F1938
• PIC16F1934
• PIC16F1937
• PIC16F1939
PIC16LF193X Devices:
• PIC16LF1933
• PIC16LF1936
• PIC16LF1938
• PIC16LF1934
• PIC16LF1937
• PIC16LF1939
Peripheral Features:
• Up to 35 I/O Pins and 1 Input-only pin:
- High-current source/sink for direct LED drive
- Individually programmable Interrupt-on-pin
change pins
High-Performance RISC CPU:
- Individually programmable weak pull-ups
• A/D Converter:
- 10-bit resolution and up to 14 channels
- Can operate during Sleep
- Selectable 1.024/2.048/4.096V voltage
reference
• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
• Only 49 Instructions to Learn:
- All single-cycle instructions except branches
• Operating Speed:
- DC – 32 MHz oscillator/clock input
- DC – 125 ns instruction cycle
• Up to 16K x 14 Words of Flash Program Memory
• Up to 1024 Bytes of Data Memory (RAM)
• Interrupt Capability
• Enhanced Timer1
• 16-Level Deep Hardware Stack
- Dedicated low-power 32 kHz oscillator
- 16-bit timer/counter with prescaler
- External Gate Input mode with toggle and
single shot modes
• Direct, Indirect and Relative Addressing modes
• Processor Read Access to Program Memory
• Pinout Compatible to other 28/40-pin PIC16CXXX
and PIC16FXXX Microcontrollers
- Interrupt-on-gate completion
• Timer2, 4, 6: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Two Capture, Compare, PWM Modules (CCP)
- 16-bit Capture, max. resolution 12.5 ns
- 16-bit Compare, max. resolution 200 ns
- 10-bit PWM, max. frequency 20 kHz
• Three Enhanced Capture, Compare, PWM
modules (ECCP)
Special Microcontroller Features:
• Precision Internal Oscillator:
- Factory calibrated to ±1%, typical
- Software selectable frequency range from
32 MHz to 31 kHz
• Power-Saving Sleep mode
• Industrial and Extended Temperature Range
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Brown-out Reset (BOR)
- Selectable between two trip points
- Disable in Sleep option
- Software selectable time-bases
- Auto-shutdown and auto-restart
- PWM steering
• Master Synchronous Serial Port (SSP) with SPI
and I2CTM with:
- 7-bit address masking
• Multiplexed Master Clear with Pull-up/Input Pin
• Programmable Code Protection
• High Endurance Flash/EEPROM cell:
- 100,000 write Flash endurance
- 1,000,000 write EEPROM endurance
- Flash/Data EEPROM retention: > 40 years
• Wide Operating Voltage Range:
- 1.8V-5.5V (PIC16F193X)
- SMBUS/PMBUSTM compatibility
• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART)
- RS-232, RS 485 and LIN compatible
- Auto-Baud Detect
- Auto-wake-up on start
- 1.8V-3.6V (PIC16LF193X)
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 1
PIC16F193X/LF193X
Peripheral Features (Continued):
• SR Latch (555 Timer):
- Multiple Set/Reset input options
• Integrated LCD Controller:
- Up to 96 segments
- Variable clock input
- Contrast control
- Internal voltage reference selections
• 2 Comparators:
- Rail-to-rail inputs/outputs
- Power mode control
- Software enable hysteresis
• Voltage Reference module:
- Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V output levels
- 5-bit rail-to-rail resistive DAC with positive
and negative reference selection
PIC16F193X/LF193X Family Types
Program
Memory
Flash
Data
EEPROM
(bytes)
10-bit
A/D Comparators
(ch)
ECCP
Full
Bridge Bridge
ECCP
Half
2
SRAM
(bytes)
Timers
8/16-bit
MI C/
Device
I/Os
EUSART
CCP LCD
(1)
SPI
(words)
PIC16F1933
PIC16LF1933
4096
4096
256
256
256
256
256
256
256
256
25
36
25
36
25
36
11
14
11
14
14
14
2
2
2
2
2
2
4/1
4/1
4/1
4/1
4/1
4/1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1
2
1
2
1
2
2
1
2
1
2
1
2
2
2
2
2
2
16 /4
PIC16F1934
PIC16LF1934
24/4
PIC16F1936
PIC16LF1936
(1)
8192
512
16 /4
PIC16F1937
PIC16LF1937
8192
512
24/4
PIC16F1938
PIC16LF1938
(1)
16384
16384
1024
1024
16 /4
PIC16F1939
PIC16LF1939
24/4
Note 1:
COM3 and SEG15 share the same physical pin on PIC16F1933/1936/1938/PIC16LF1933/1936/1938, therefore, SEG15 is not
available when using 1/4 multiplex displays.
DS41364A-page 2
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
Pin Diagram – 28-Pin SPDIP/SOIC/SSOP (PIC16F1933/1936/1938, PIC16LF1933/1936/1938)
28-pin SPDIP, SOIC, SSOP
RB7/ICSPDAT/ICDDAT/SEG13
28
27
26
25
24
23
1
2
3
4
5
VPP/MCLR/RE3
SEG12/VCAP(2)/SS(1)/SRNQ(1)/C2OUT(1)/C12IN0-/AN0/RA0
SEG7/C12IN1-/AN1/RA1
RB6/ICSPCLK/ICDCLK/SEG14
RB5/AN13/CPS5/P2B(1)/CCP3(1)/P3A(1)/T1G(1)/COM1
RB4/AN11/CPS4/P1D/COM0
RB3/AN9/C12IN2-/CPS3/CCP2(1)/P2A(1)/VLCD3
COM2/CVREF/VREF-/C2IN+/AN2/RA2
SEG15/COM3/VREF+/C1IN+/AN3/RA3
RB2/AN8/CPS2/P1B/VLCD2
6
7
8
9
SEG4/CCP5/SRQ/T0CKI/CPS6/C1OUT/RA4
SEG5/VCAP(2)/SS(1)/SRNQ(1)/CPS7/C2OUT(1)/AN4/RA5
RB1/AN10/C12IN3-/CPS1/P1C/VLCD1
RB0/AN12/CPS0/CCP4/SRI/INT/SEG0
22
21
VSS
VDD
20
19
18
17
16
15
SEG2/CLKIN/OSC1/RA7
VSS
SEG1/VCAP(2)/CLKOUT/OSC2/RA6
P2B(1)/T1CKI/T1OSO/RC0
10
11
RC7/RX/DT/P3B/SEG8
RC6/TX/CK/CCP3(1)/P3A(1)/SEG9
RC5/SDO/SEG10
RC4/SDI/SDA/T1G(1)/SEG11
P2A(1)/CCP2(1)/T1OSI/RC1
SEG3/P1A/CCP1/RC2
SEG6/SCL/SCK/RC3
12
13
14
Note 1: Pin function is selectable via the APFCON register.
2: PIC16F193X devices only.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 3
PIC16F193X/LF193X
Pin Diagram – 28-Pin QFN (PIC16F1933/1936/1938, PIC16LF1933/1936/1938)
28-pin QFN
RB3/AN9/C12IN2-/CPS3/CCP2(1)/P2A(1)/VLCD3
RB2/AN8/CPS2/P1B/VLCD2
1
2
3
4
5
6
7
21
20
19
18
17
16
15
COM2/CVREF/VREF-/C2IN+/AN2/RA2
SEG15/COM3/VREF+/C1IN+/AN3/RA3
SEG4/CCP5/SRQ/T0CKI/CPS6/C1OUT/RA4
SEG5(1)/VCAP(2)/SS(1)/SRNQ/CPS7/C2OUT(1)/AN4/RA5
VSS
RB1/AN10/C12IN3-/CPS1/P1C/VLCD1
RB0/AN12/CPS0/CCP4/SRI/INT/SEG0
PIC16F1933/1936/1938
PIC16LF1933/1936/1938
VDD
SEG2/CLKIN/OSC1/RA7
SEG1/VCAP(2)/CLKOUT/OSC2/RA6
VSS
RC7/RX/DT/P3B/SEG8
Note 1: Pin function is selectable via the APFCON register.
2: PIC16F193X devices only.
DS41364A-page 4
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 1:
28-PIN SUMMARY (PIC16F1933/1936/1938, PIC16LF1933/1936/1938)
(2)
RA0
2
27 AN0
28 AN1
—
C12IN0-/
C2OUT(1)
—
—
—
SEG12
—
—
VCAP
SRNQ(1)
SS(1)
RA1
RA2
3
4
—
—
C12IN1-
—
—
—
—
—
—
—
—
—
—
SEG7
COM2
—
—
—
—
—
—
1
AN2/
C2IN+/
CVREF
VREF-
RA3
5
2
AN3/
VREF+
—
C1IN+
—
—
—
—
—
SEG15/
COM3
—
—
—
RA4
RA5
RA6
6
7
3
4
7
—
AN4
—
CPS6
C1OUT
SRQ
T0CKI
—
CCP5
—
—
—
—
—
SS(1)
—
SEG4
SEG5
SEG1
—
—
—
—
—
—
—
CPS7 C2OUT(1) SRNQ(1)
VCAP
(2)
10
—
—
—
—
—
OSC2/
CLKOUT
(2)
VCAP
RA7
RB0
9
6
—
—
—
—
—
—
—
—
—
—
—
—
SEG2
SEG0
—
—
Y
OSC1/
CLKIN
21 18 AN12 CPS0
SRI
CCP4
INT/
IOC
—
RB1
RB2
RB3
22 19 AN10 CPS1
C12IN3-
—
—
—
—
—
—
—
P1C
P1B
—
—
—
—
—
—
VLCD1
VLCD2
VLCD3
IOC
IOC
IOC
Y
Y
Y
—
—
—
23 20 AN8
24 21 AN9
CPS2
CPS3
C12IN2-
CCP2(1)
/
/
P2A(1)
RB4
RB5
25 22 AN11 CPS4
26 23 AN13 CPS5
—
—
—
—
—
T1G(1)
P1D
—
—
—
—
COM0
COM1
IOC
IOC
Y
Y
—
—
P2B(1)
CCP3(1)
P3A(1)
RB6
RB7
RC0
27 24
28 25
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SEG14
SEG13
—
IOC
IOC
—
Y
Y
ICSPCLK/
ICDCLK
—
ICSPDAT/
ICDDAT
11
8
9
T1OSO/
T1CKI
P2B(1)
—
—
—
—
—
—
RC1 12
T1OSI
CCP2(1)
P2A(1)
/
—
—
RC2 13 10
—
CCP1/
SEG3
—
P1A
RC3 14 11
RC4 15 12
RC5 16 13
RC6 17 14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T1G(1)
—
—
—
—
—
—
SCK/SCL
SDI/SDA
SDO
SEG6
SEG11
SEG10
SEG9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CCP3(1)
TX/CK
—
P3A(1)
RC7 18 15
—
—
—
—
—
P3B
RX/DT
—
SEG8
—
—
—
RE3
VDD
Vss
1
26
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Y
MCLR/VPP
VDD
20 17
—
—
8, 5,
19 16
VSS
Note 1:
2:
Pin functions can be moved using the APFCON register.
PIC16F193X devices only.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 5
PIC16F193X/LF193X
Pin Diagram – 40-Pin PDIP (PIC16F1934/1937/1939, PIC16LF1934/1937/1939)
40-Pin PDIP
RB7/ICSPDAT/ICDDAT/SEG13
1
2
3
4
5
6
40
39
38
37
36
35
VPP/MCLR/RE3
SEG12/VCAP(2)/SS(1)/SRNQ(1)/C2OUT(1)/C12IN0-/AN0/RA0
SEG7/C12IN1-/AN1/RA1
RB6/ICSPCLK/ICDCLK/SEG14
RB5/AN13/CPS5/CCP3(1)/P3A(1)/T1G(1)/COM1
RB4/AN11/CPS4/COM0
COM2/CVREF/VREF-/C2IN+/AN2/RA2
RB3/AN9/C12IN2-/CPS3/CCP2(1)/P2A(1)/VLCD3
SEG15/VREF+/C1IN+/AN3/RA3
RB2/AN8/CPS2/VLCD2
SEG4/SRQ/T0CKI/CPS6/C1OUT/RA4
SEG5/VCAP(2)/SS(1)/SRNQ(1)/CPS7/C2OUT(1)/AN4/RA5
SEG21/CCP3(1)/P3A(1)/AN5/RE0
34
33
32
RB1/AN10/C12IN3-/CPS1/VLCD1
RB0/AN12/CPS0/SRI/INT/SEG0
7
8
9
VDD
SEG22/P3B/AN6/RE1
VSS
SEG23/CCP5/AN7/RE2
31
30
10
11
RD7/CPS15/P1D/SEG20
RD6/CPS14/P1C/SEG19
VDD
VSS
29
12
RD5/CPS13/P1B/SEG18
RD4/CPS12/P2D/SEG17
RC7/RX/DT/SEG8
SEG2/CLKIN/OSC1/RA7
28
27
26
25
13
14
15
16
SEG1/VCAP(2)/CLKOUT/OSC2/RA6
P2B(1)/T1CKI/T1OSO/RC0
P2A(1)/CCP2(1)/T1OSI/RC1
RC6/TX/CK/SEG9
RC5/SDO/SEG10
24
23
SEG3/P1A/CCP1/RC2
SEG6/SCK/SCL/RC3
17
18
RC4/SDI/SDA/T1G(1)/SEG11
RD3/CPS11/P2C/SEG16
RD2/CPS10/P2B(1)
COM3/CPS8/RD0
CCP4/CPS9/RD1
22
21
19
20
Note 1: Pin function is selectable via the APFCON register.
2: PIC16F193X devices only.
DS41364A-page 6
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
Pin Diagram – 44-Pin QFN (PIC16F1934/1937/1939, PIC16LF1934/1937/1939)
44-pin QFN
RA6/OSC2/CLKOUT/VCAP(2)/SEG1
RA7/OSC1/CLKIN/SEG2
VSS
VSS
NC
VDD
SEG8/DT/RX/RC7
SEG17/P2D/CPS12/RD4
SEG18/P1B/CPS13/RD5
SEG19/P1C/CPS14/RD6
SEG20/P1D/CPS15/RD7
VSS
1
2
3
4
5
6
7
8
9
33
32
31
30
29
28
27
26
PIC16F1934/1937/1939
PIC16LF1934/1937/1939
VDD
VDD
RE2/AN7/CCP5/SEG23
RE1/AN6/P3B/SEG22
RE0/AN5/CCP3(1)/P3A(1)/SEG21
RA5/AN4/C2OUT(1)/CPS7/SRNQ(1)/SS(1)/VCAP(2)/SEG5
RA4/C1OUT/CPS6/T0CKI/SRQ/SEG4
SEG0/INT/SRI/CPS0/AN12/RB0
VLCD1/CPS1/C12IN3-/AN10/RB1
VLCD2/CPS2/AN8/RB2
25
24
23
10
11
Note 1: Pin function is selectable via the APFCON register.
2: PIC16F193X devices only.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 7
PIC16F193X/LF193X
Pin Diagram – 44-Pin TQFP (PIC16F1934/1937/1939, PIC16LF1934/1937/1939)
44-pin TQFP
SEG8/DT/RX/RC7
SEG17/P2D/CPS12/RD4
SEG18/P1B/CPS13/RD5
SEG19/P1C/CPS14/RD6
SEG20/P1D/CPS15/RD7
NC
1
2
3
4
5
6
7
8
9
33
32
31
30
29
28
27
26
25
24
23
RC0/T1OSO/T1CKI/P2B(1)
RA6/OSC2/CLKOUT/VCAP(2)/SEG1
RA7/OSC1/CLKIN/SEG2
VSS
VDD
PIC16F1934/1937/1939
PIC16LF1934/1937/1939
VSS
VDD
RE2/AN7/CCP5/SEG23
RE1/AN6/P3B/SEG22
SEG0/INT/SRI/CPS0/AN12/RB0
VLCD1/CPS1/C12IN3-/AN10/RB1
RE0/AN5/CCP3(1)/P3A(1)/SEG21
RA5/AN4/C2OUT(1)/CPS7/SRNQ(1)/SS(1)/VCAP(2)/SEG5
RA4/C1OUT/CPS6/T0CKI/SRQ/SEG4
10
11
VLCD2/CPS2/AN8/RB2
VLCD3/P2A(1)/CCP2(1)/CPS3/C12IN2-/AN9/RB3
Note 1: Pin function is selectable via the APFCON register.
2: PIC16F193X devices only.
DS41364A-page 8
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 2:
40/44-PIN SUMMARY(PIC16F1934/1937/1939, PIC16LF1934/1937/1939)
RA0
2
19
19
AN0
AN1
—
C12IN0-/
C2OUT(1)
—
—
—
SEG12
—
—
VCAP
SRNQ(1)
SS(1)
RA1
RA2
3
4
20
21
20
21
—
—
C12IN1-
—
—
—
—
—
—
—
—
—
—
SEG7
COM2
—
—
—
—
—
—
AN2/
VREF-
C2IN+/
CVREF
RA3
5
22
22
AN3/
—
C1IN+
—
—
—
—
—
SEG15
—
—
—
VREF+
RA4
RA5
6
7
23
24
23
24
33
—
AN4
—
CPS6
C1OUT
SRQ
T0CKI
—
—
—
—
—
SS(1)
—
SEG4
SEG5
SEG1
—
—
—
—
—
—
—
CPS7 C2OUT(1) SRNQ(1)
—
—
VCAP
RA6 14 31
—
—
—
—
OSC2/
CLKOUT
VCAP
RA7 13 30
32
9
—
—
—
—
—
—
—
—
—
—
—
—
—
SEG2
SEG0
—
—
Y
OSC1/
CLKIN
RB0 33
RB1 34
8
9
AN12 CPS0
AN10 CPS1
SRI
INT/
IOC
—
10
11
12
C12IN3-
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VLCD1
VLCD2
VLCD3
IOC
IOC
IOC
Y
Y
Y
—
—
—
RB2 35 10
RB3 36 11
AN8
AN9
CPS2
CPS3
C12IN2-
CCP2(1)
/
/
P2A(1)
RB4 37 14
RB5 38 15
14
15
AN11 CPS4
AN13 CPS5
—
—
—
—
—
T1G(1)
—
—
—
—
—
COM0
COM1
IOC
IOC
Y
Y
—
—
CCP3(1)
P3A(1)
RB6 39 16
RB7 40 17
RC0 15 32
RC1 16 35
RC2 17 36
16
17
34
35
36
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SEG14
SEG13
—
IOC
IOC
—
Y
Y
ICSPCLK/
ICDCLK
ICSPDAT/
ICDDAT
T1OSO/
T1CKI
P2B(1)
—
—
—
—
—
—
T1OSI
CCP2(1)
P2A(1)
/
—
—
—
CCP1/
SEG3
—
P1A
RC3 18 37
RC4 23 42
RC5 24 43
RC6 25 44
37
42
43
44
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T1G(1)
—
—
—
—
—
SCK/SCL
SEG6
SEG11
SEG10
SEG9
SEG8
COM3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDI/SDA
SDO
—
—
—
—
—
—
—
—
—
TX/CK
RX/DT
—
RC7 26
1
—
—
—
—
—
RD0 19 38
RD1 20 39
RD2 21 40
RD3 22 41
38
39
40
41
2
—
CPS8
CPS9
CPS10
CPS11
CPS12
CPS13
CPS14
CPS15
—
—
—
—
—
—
CCP4
P2B(1)
P2C
P2D
P1B
P1C
P1D
—
—
—
—
—
—
—
—
—
—
—
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
RD4 27
RD5 28
RD6 29
RD7 30
2
3
—
—
—
—
3
—
—
—
—
4
4
—
—
—
—
5
5
—
—
—
—
RE0
8
25
25
AN5
—
CCP3(1)
—
—
P3A(1)
RE1
9
26
26
27
AN6
AN7
—
—
—
—
—
—
—
—
P3B
—
—
—
—
SEG22
SEG23
—
—
—
—
—
—
RE2 10 27
RE3 18
CCP5
1
18
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Y
MCLR/VPP
VDD
VDD 11, 7, 7,8,
32 28 28
—
Vss 12, 6, 6,30,
31 29 31
—
—
—
—
—
—
—
—
—
—
—
VSS
Note 1: Pin functions can be moved using the APFCON register.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 9
PIC16F193X/LF193X
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 Memory Organization................................................................................................................................................................. 19
3.0 Resets ........................................................................................................................................................................................ 55
4.0 Interrupts .................................................................................................................................................................................... 67
5.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 79
6.0 I/O Ports ..................................................................................................................................................................................... 81
7.0 Interrupt-on-Change................................................................................................................................................................. 101
8.0 Oscillator Module (With Fail-Safe Clock Monitor)..................................................................................................................... 105
9.0 SR Latch................................................................................................................................................................................... 119
10.0 Device Configuration ................................................................................................................................................................ 123
11.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 129
12.0 Comparator Module.................................................................................................................................................................. 141
13.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 149
14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 153
15.0 Timer0 Module ......................................................................................................................................................................... 155
16.0 Timer1 Module ......................................................................................................................................................................... 159
17.0 Timer2/4/6 Modules.................................................................................................................................................................. 171
18.0 Capacitive Sensing Module...................................................................................................................................................... 175
19.0 Capture/Compare/PWM (ECCP1, ECCP2, ECCP3, CCP4, CCP5) Modules.......................................................................... 181
20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 211
21.0 Liquid Crystal Display (LCD) Driver Module............................................................................................................................. 239
22.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 273
23.0 Data EEPROM and Flash Program Memory Control............................................................................................................... 321
24.0 Power-Down Mode (Sleep) ...................................................................................................................................................... 333
25.0 In-Circuit Serial Programming™ (ICSP™) ................................................................................................................................ 335
26.0 Instruction Set Summary.......................................................................................................................................................... 337
27.0 Development Support............................................................................................................................................................... 351
28.0 Electrical Specifications............................................................................................................................................................ 355
29.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 389
30.0 Packaging Information.............................................................................................................................................................. 391
Appendix A: Revision History............................................................................................................................................................. 403
Appendix B: Device Differences......................................................................................................................................................... 403
Index .................................................................................................................................................................................................. 405
The Microchip Web Site..................................................................................................................................................................... 413
Customer Change Notification Service .............................................................................................................................................. 413
Customer Support.............................................................................................................................................................................. 413
Reader Response .............................................................................................................................................................................. 414
Product Identification System............................................................................................................................................................. 415
DS41364A-page 10
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.
We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 11
PIC16F193X/LF193X
NOTES:
DS41364A-page 12
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
1.0
DEVICE OVERVIEW
The PIC16F193X/LF193X devices are described within
this data sheet. They are available in 28/40/44-pin
packages. Figure 1-1 shows a block diagram of the
PIC16F193X/LF193X devices. Table 1-1 shows the
pinout descriptions.
FIGURE 1-1:
PIC16F193X/LF193X BLOCK DIAGRAM
15
Configuration
PORTA
8
15
Data Bus
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
Program Counter
Flash
Program
Memory
16-LevelStack
(15-bit)
RAM
Program
Bus
14
RAM Addr
Program Memory
Read (PMR)
9
PORTB
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
Addr MUX
InstructionReg
Indirect
Addr
7
Direct Addr
12
15
FSR0 Reg
FSR1 Reg
15
STATUSReg
MUX
PORTC
8
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
3
Power-up
Timer
Oscillator
Start-up Timer
Instruction
Decodeand
Control
ALU
Power-on
Reset
PORTD
OSC1/CLKIN
8
RD0
RDC1
RD2
Timing
Generation
Watchdog
Timer
WReg
OSC2/CLKOUT
Brown-out
Reset
RD3
RD4
RD5
RD6
RD7
Internal
Oscillator
Block
PORTE
RE0
RE1
VDD
VSS
RE2
RE3/MCLR
Data EEPROM
256 bytes
Timer0
Timer1
Timer2/4/6
Timer1
Addressable
EUSART
LCD
Comparators
CCP4/5
ECCP1/2/3
MSSP
SR Latch
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 13
PIC16F193X/LF193X
1.1
Enhanced Mid-range CPU
PIC16F193X/LF193X devices contain an enhanced
mid-range 8-bit CPU core. The CPU has 49
instructions. Interrupt capability includes automatic
context saving. The hardware stack is 16 levels deep
and has Overflow and Underflow Reset capability.
Direct, indirect, and relative addressing modes are
available. Two File Select Registers (FSRs) provide the
ability to read program and data memory.
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 4.5 “Context Saving”, for more
information.
1.1.1
16-LEVEL STACK WITH OVERFLOW
AND UNDERFLOW RESET
The PIC16F193X/LF193X devices have an external
stack memory 15 bits wide and 16 deep. During normal
operation, the stack is assumed to be 16 words deep.
If enabled, a Stack Overflow or Underflow will set the
appropriate bit (STKOVF or STKUNF) in the PCON
register, and cause a software Reset. See section
Section 2.4 “Stack” for more details.
1.1.2
FILE SELECT REGISTERS
There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one data pointer for all memory. When an
FSR points to program memory, there is 1 additional
instruction cycle in instructions using INDF to allow the
data to be fetched. There are also new instructions to
support the FSRs. See Section 2.5 “Indirect
Addressing, INDF and FSR Registers” for more
details.
1.1.3
INSTRUCTION SET
There are 48 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 26.0 “Instruction Set Summary” for more
details.
DS41364A-page 14
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 1-1:
PIC16F193X/LF193X PINOUT DESCRIPTION
Input Output
Name
Function
Description
Type
Type
(1)
RA0/AN0/C12IN0-/C2OUT
/
RA0
AN0
TTL
AN
AN
—
CMOS General purpose I/O.
(1)
(1)
(2)
SRNQ /SS /VCAP /SEG12
—
—
A/D Channel 0 input.
Comparator C1 or C2 negative input.
C12IN0-
C2OUT
SRNQ
SS
CMOS Comparator C2 output.
CMOS SR Latch inverting output.
—
ST
—
Slave Select input.
VCAP
Power Power Filter capacitor for Voltage Regulator (PIC16F193X only).
SEG12
RA1
—
TTL
AN
AN
—
AN
LCD Analog output.
RA1/AN1/C12IN1-/SEG7
CMOS General purpose I/O.
AN1
—
—
A/D Channel 1 input.
C12IN1-
SEG7
RA2
Comparator C1 or C2 negative input.
LCD Analog output.
AN
RA2/AN2/C2IN+/VREF-/CVREF/
COM2
TTL
AN
AN
AN
—
CMOS General purpose I/O.
AN2
—
—
A/D Channel 2 input.
Comparator C2 positive input.
A/D Negative Voltage Reference input.
Comparator Voltage Reference output.
LCD Analog output.
C2IN+
VREF-
CVREF
COM2
RA3
—
AN
AN
—
RA3/AN3/C1IN+/VREF+/
TTL
AN
AN
AN
—
CMOS General purpose I/O.
(3)
COM3 /SEG15
AN3
—
—
A/D Channel 3 input.
Comparator C1 positive input.
A/D Voltage Reference input.
LCD Analog output.
C1IN+
VREF+
—
(3)
COM3
AN
AN
SEG15
RA4
—
LCD Analog output.
RA4/C1OUT/CPS6/T0CKI/SRQ/
CCP5/SEG4
TTL
—
CMOS General purpose I/O.
C1OUT
CPS6
T0CKI
SRQ
CMOS Comparator C1 output.
AN
ST
—
—
—
Capacitive sensing input 6.
Timer0 clock input.
CMOS SR Latch non-inverting output.
CMOS Capture/Compare/PWM5.
CCP5
SEG4
RA5
ST
—
AN
CMOS General purpose I/O.
A/D Channel 4 input.
CMOS Comparator C2 output.
Capacitive sensing input 7.
CMOS SR Latch inverting output.
Slave Select input.
LCD Analog output.
(1)
RA5/AN4/C2OUT /CPS7/
TTL
AN
—
(1)
(1)
(2)
SRNQ /SS /VCAP /SEG5
AN4
—
C2OUT
CPS7
SRNQ
SS
AN
—
—
ST
—
VCAP
Power Power Filter capacitor for Voltage Regulator (PIC16F193X only).
AN LCD Analog output.
SEG5
—
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
OD = Open Drain
2
2
TTL = TTL compatible input ST
HV = High Voltage
= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C
levels
XTAL = Crystal
Note 1: Pin function is selectable via the APFCON register.
2: PIC16F193X devices only.
3: PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices only.
4: PORTD is available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only.
5: RE<2:0> are available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 15
PIC16F193X/LF193X
TABLE 1-1:
PIC16F193X/LF193X PINOUT DESCRIPTION (CONTINUED)
Input Output
Name
Function
Description
Type
Type
(2)
RA6/OSC2/CLKOUT/VCAP
SEG1
/
RA6
OSC2
CLKOUT
VCAP
TTL
—
CMOS General purpose I/O.
XTAL Crystal/Resonator (LP, XT, HS modes).
CMOS FOSC/4 output.
—
Power Power Filter capacitor for Voltage Regulator (PIC16F193X only).
SEG1
RA7
—
TTL
AN
LCD Analog output.
RA7/OSC1/CLKIN/SEG2
CMOS General purpose I/O.
OSC1
CLKIN
SEG2
RB0
XTAL
CMOS
—
—
—
Crystal/Resonator (LP, XT, HS modes).
External clock input (EC mode).
LCD Analog output.
AN
RB0/AN12/CPS0/CCP4/SRI/INT/
SEG0
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN12
CPS0
CCP4
SRI
AN
AN
ST
—
—
—
A/D Channel 12 input.
Capacitive sensing input 0.
CMOS Capture/Compare/PWM4.
ST
—
SR Latch input.
INT
ST
—
External interrupt.
LCD analog output.
SEG0
RB1
AN
RB1/AN10/C12IN3-/CPS1/P1C/
VLCD1
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN10
C12IN3-
CPS1
P1C
AN
AN
AN
—
—
—
—
A/D Channel 10 input.
Comparator C1 or C2 negative input.
Capacitive sensing input 1.
CMOS PWM output.
VLCD1
RB2
AN
TTL
—
LCD analog input.
RB2/AN8/CPS2/P1B/VLCD2
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN8
CPS2
P1B
AN
AN
—
—
—
A/D Channel 8 input.
Capacitive sensing input 2.
CMOS PWM output.
VLCD2
RB3
AN
TTL
—
LCD analog input.
RB3/AN9/C12IN2-/CPS3/
CCP2 /P2A /VLCD3
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
(1)
(1)
AN9
C12IN2-
CPS3
CCP2
P2A
AN
AN
AN
ST
—
—
—
—
A/D Channel 9 input.
Comparator C1 or C2 negative input.
Capacitive sensing input 3.
CMOS Capture/Compare/PWM2.
CMOS PWM output.
VLCD3
AN
—
LCD analog input.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
OD = Open Drain
2
2
TTL = TTL compatible input ST
HV = High Voltage
= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C
levels
XTAL = Crystal
Note 1: Pin function is selectable via the APFCON register.
2: PIC16F193X devices only.
3: PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices only.
4: PORTD is available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only.
5: RE<2:0> are available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only
DS41364A-page 16
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 1-1:
PIC16F193X/LF193X PINOUT DESCRIPTION (CONTINUED)
Input Output
Name
RB4/AN11/CPS4/P1D/COM0
Function
Description
Type
Type
RB4
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN11
CPS4
P1D
AN
AN
—
—
—
A/D Channel 11 input.
Capacitive sensing input 4.
CMOS PWM output.
COM0
RB5
—
AN
LCD Analog output.
(1)
RB5/AN13/CPS5/P2B/CCP3
P3A /T1G /COM1
/
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
(1)
(1)
AN13
CPS5
P2B
AN
AN
—
—
—
A/D Channel 13 input.
Capacitive sensing input 5.
CMOS PWM output.
CCP3
P3A
ST
—
CMOS Capture/Compare/PWM3.
CMOS PWM output.
T1G
ST
—
—
Timer1 Gate input.
LCD Analog output.
COM1
RB6
AN
RB6/ICSPCLK/ICDCLK/SEG14
RB7/ICSPDAT/ICDDAT/SEG13
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
ICSPCLK
ICDCLK
SEG14
RB7
ST
ST
—
—
—
Serial Programming Clock.
In-Circuit Debug Clock.
LCD Analog output.
AN
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
ICSPDAT
ICDDAT
SEG13
RC0
ST
ST
—
CMOS ICSP™ Data I/O.
CMOS In-Circuit Data I/O.
AN
LCD Analog output.
(1)
RC0/T1OSO/T1CKI/P2B
ST
XTAL
ST
—
CMOS General purpose I/O.
T1OSO
T1CKI
P2B
XTAL Timer1 oscillator connection.
—
Timer1 clock input.
CMOS PWM output.
(1)
(1)
RC1/T1OSI/CCP2 /P2A
RC1
ST
XTAL
ST
—
CMOS General purpose I/O.
XTAL Timer1 oscillator connection.
CMOS Capture/Compare/PWM2.
CMOS PWM output.
T1OSI
CCP2
P2A
RC2/CCP1/P1A/SEG3
RC3/SCK/SCL/SEG6
RC2
ST
ST
—
CMOS General purpose I/O.
CMOS Capture/Compare/PWM1.
CMOS PWM output.
CCP1
P1A
SEG3
RC3
—
AN
LCD Analog output.
ST
ST
CMOS General purpose I/O.
SCK
CMOS SPI clock.
2
2
SCL
I C
OD
AN
I C™ clock.
SEG6
—
LCD Analog output.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
OD = Open Drain
2
2
TTL = TTL compatible input ST
HV = High Voltage
= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C
levels
XTAL = Crystal
Note 1: Pin function is selectable via the APFCON register.
2: PIC16F193X devices only.
3: PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices only.
4: PORTD is available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only.
5: RE<2:0> are available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 17
PIC16F193X/LF193X
TABLE 1-1:
PIC16F193X/LF193X PINOUT DESCRIPTION (CONTINUED)
Input Output
Name
Function
Description
Type
Type
(1)
RC4/SDI/SDA/T1G /SEG11
RC4
SDI
ST
ST
CMOS General purpose I/O.
—
OD
—
SPI data input.
2
2
SDA
I C
I C™ data input/output.
T1G
ST
—
Timer1 Gate input.
LCD Analog output.
SEG11
RC5
AN
RC5/SDO/SEG10
ST
—
CMOS General purpose I/O.
CMOS SPI data output.
SDO
SEG10
RC6
—
AN
LCD Analog output.
RC6/TX/CK/CCP3/P3A/SEG9
ST
—
CMOS General purpose I/O.
TX
CMOS USART asynchronous transmit.
CMOS USART synchronous clock.
CMOS Capture/Compare/PWM3.
CMOS PWM output.
CK
ST
ST
—
CCP3
P3A
SEG9
RC7
—
AN
LCD Analog output.
RC7/RX/DT/P3B/SEG8
ST
ST
ST
—
CMOS General purpose I/O.
RX
—
USART asynchronous input.
DT
CMOS USART synchronous data.
CMOS PWM output.
P3B
SEG8
RD0
—
AN
LCD Analog output.
(4)
RD0 /CPS8/COM3
ST
AN
—
CMOS General purpose I/O.
CPS8
COM3
RD1
—
Capacitive sensing input 8.
LCD analog output.
AN
(4)
RD1 /CPS9/CCP4
ST
AN
ST
ST
AN
—
CMOS General purpose I/O.
Capacitive sensing input 9.
CPS9
CCP4
RD2
—
CMOS Capture/Compare/PWM4.
CMOS General purpose I/O.
(4)
RD2 /CPS10/P2B
CPS10
P2B
—
Capacitive sensing input 10.
CMOS PWM output.
(4)
RD3 /CPS11/P2C/SEG16
RD3
ST
AN
—
CMOS General purpose I/O.
CPS11
P2C
—
Capacitive sensing input 11.
CMOS PWM output.
SEG16
RD4
—
AN
LCD analog output.
(4)
RD4 /CPS12/P2D/SEG17
ST
AN
—
CMOS General purpose I/O.
CPS12
P2D
—
Capacitive sensing input 12.
CMOS PWM output.
SEG17
RD5
—
AN
LCD analog output.
(4)
RD5 /CPS13/P1B/SEG18
ST
AN
—
CMOS General purpose I/O.
CPS13
P1D
—
Capacitive sensing input 13.
CMOS PWM output.
SEG18
—
AN
LCD analog output.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
OD = Open Drain
2
2
TTL = TTL compatible input ST
HV = High Voltage
= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C
levels
XTAL = Crystal
Note 1: Pin function is selectable via the APFCON register.
2: PIC16F193X devices only.
3: PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices only.
4: PORTD is available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only.
5: RE<2:0> are available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only
DS41364A-page 18
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 1-1:
PIC16F193X/LF193X PINOUT DESCRIPTION (CONTINUED)
Input Output
Name
Function
Description
Type
Type
(4)
RD6 /CPS14/P1C/SEG19
RD6
CPS14
P1C
ST
AN
—
CMOS General purpose I/O.
—
Capacitive sensing input 14.
CMOS PWM output.
SEG19
RD7
—
AN
LCD analog output.
(4)
RD7 /CPS15/P1D/SEG20
ST
AN
—
CMOS General purpose I/O.
CPS15
P1D
—
Capacitive sensing input 15.
CMOS PWM output.
SEG20
RE0
—
AN
LCD analog output.
(5)
(1)
(1)
RE0 /AN5/P3A /CCP3
SEG21
/
ST
AN
—
CMOS General purpose I/O.
AN5
—
A/D Channel 5 input.
P3A
CMOS PWM output.
CCP3
SEG21
RE1
ST
—
CMOS Capture/Compare/PWM3.
AN
CMOS General purpose I/O.
A/D Channel 6 input.
CMOS PWM output.
LCD analog output.
(5)
RE1 /AN6/P3B/SEG22
ST
AN
—
AN6
—
P3B
SEG22
RE2
—
AN
LCD analog output.
(5)
RE2 /AN7/CCP5/SEG23
RE3/MCLR/VPP
ST
AN
ST
—
CMOS General purpose I/O.
AN7
—
A/D Channel 7 input.
CCP5
SEG23
RE3
CMOS Capture/Compare/PWM5.
AN
—
—
—
—
—
LCD analog output.
TTL
ST
HV
Power
Power
General purpose input.
MCLR
VPP
Master Clear with internal pull-up.
Programming voltage.
Positive supply.
VDD
VSS
VDD
VSS
Ground reference.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
OD = Open Drain
2
2
TTL = TTL compatible input ST
HV = High Voltage
= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C
levels
XTAL = Crystal
Note 1: Pin function is selectable via the APFCON register.
2: PIC16F193X devices only.
3: PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices only.
4: PORTD is available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only.
5: RE<2:0> are available on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 19
PIC16F193X/LF193X
NOTES:
DS41364A-page 20
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
2.0
2.1
MEMORY ORGANIZATION
Program Memory Organization
The enhanced mid-range core has a 15-bit program
counter capable of addressing 32K x 14 program
memory space. Table 2-1 shows the memory sizes
implemented for the PIC16F193X/LF193X device family.
Accessing a location above these boundaries will cause
a wrap-around within the implemented memory space.
The Reset vector is at 0000h and the interrupt vector is
at 0004h (see Figures 2-1, 2-2 and 2-3).
TABLE 2-1:
DEVICE SIZES AND ADDRESSES
Device Program Memory Space (Words)
PIC16F1933/PIC16LF1933
Last Program Memory Address
4,096
4,096
8,192
8,192
16,384
16,384
0FFFh
0FFFh
1FFFh
1FFFh
3FFFh
3FFFh
PIC16F1934/PIC16LF1934
PIC16F1936/PIC16LF1936
PIC16F1937/PIC16LF1937
PIC16F1938/PIC16LF1938
PIC16F1939/PIC16LF1939
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 21
PIC16F193X/LF193X
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
FIGURE 2-2:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F1933/PIC16LF1933/
PIC16F1934/PIC16LF1934
PIC16F1936/PIC16LF1936/
PIC16F1937/PIC16LF1937
PC<14:0>
PC<14:0>
CALL, CALLW
RETURN, RETLW
INTERRUPT, RETFIE
15
CALL, CALLW
RETURN, RETLW
INTERRUPT, RETFIE
15
Stack Level 0
Stack Level 1
Stack Level 0
Stack Level 1
Stack Level 15
Reset Vector
Stack Level 15
Reset Vector
0000h
0000h
Interrupt Vector
Page 0
0004h
0005h
Interrupt Vector
Page 0
0004h
0005h
On-chip
Program
Memory
07FFh
0800h
07FFh
0800h
Page 1
Page 1
Page 2
On-chip
Program
Memory
0FFFh
1000h
0FFFh
1000h
Rollover to Page 0
17FFh
1800h
Page 3
1FFFh
2000h
Rollover to Page 0
Rollover to Page 3
Rollover to Page 1
7FFFh
7FFFh
DS41364A-page 22
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 2-3:
PROGRAM MEMORY MAP
AND STACK FOR THE
2.1.1
READING PROGRAM MEMORY AS
DATA
PIC16F1938/PIC16LF1938/
PIC16F1939/PIC16LF1939
There are two methods of accessing constants in pro-
gram memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.
PC<14:0>
2.1.1.1
RETLWInstruction
CALL, CALLW
RETURN, RETLW
INTERRUPT, RETFIE
15
The RETLWinstruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 2-1.
Stack Level 0
Stack Level 1
EXAMPLE 2-1:
RETLW INSTRUCTION
constants
brw
Stack Level 15
Reset Vector
retlw DATA1
retlw DATA2
retlw DATA3
retlw DATA4
0000h
Interrupt Vector
Page 0
0004h
0005h
my_function
On-chip
Program
Memory
;… LOTS OF CODE…
movlw DATA_INDEX
call constants
07FFh
0800h
Page 1
Page 2
;… THE CONSTANT IS IN W
0FFFh
1000h
The BRWinstruction makes this type of table very sim-
ple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.
17FFh
1800h
Page 3
Page 4
1FFFh
2000h
2.1.1.2
Indirect Read with FSR
The program memory can be accessed as data by set-
ting bit 7 of the FSRxH register and reading the match-
ing INDFx register. The MOVIWinstruction will place the
lower 8 bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the pro-
gram memory via the FSR require one extra instruction
cycle to complete. Example 2-2 demonstrates access-
ing the program memory via an FSR.
Page 7
3FFFh
4000h
Rollover to Page 0
Rollover to Page 7
7FFFh
EXAMPLE 2-2:
ACCESSING PROGRAM
MEMORY VIA FSR
bsf FSR1H,7
moviw 0[INDF1]
;THE PROGRAM MEMORY IS IN W
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 23
PIC16F193X/LF193X
2.2
Data Memory Organization
The data memory is partitioned in up to 32 memory
banks with up to 128 bytes in a bank. Each bank
consists of 12 core registers, 20 Special Function
Registers (SFR), 16 common registers, and up to 80
bytes of General Purpose Registers (GPR). The active
bank is selected by writing the bank number into the
Bank Select Register (BSR). Unimplemented memory
will read as ‘0’. All banks contain the core SFRs and
common registers. Unimplemented SFRs or GPRs will
read as ‘0’. All data memory can be accessed either
directly (via instructions that use the file registers) or
indirectly via the two File Select Registers (FSR). See
Section 2.5 “Indirect Addressing, INDF and FSR
Registers” for more information.
2.2.1
GENERAL PURPOSE REGISTER
FILE
The general purpose register file is an 8-bit RAM
memory for use by your application. There are up to
80 bytes of GPR in each data memory bank.
2.2.2
SPECIAL FUNCTION REGISTER
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The Special Function
Registers can be classified into two sets: core and
peripheral. The Special Function Registers associated
with the “core” are described in the following sections.
The registers associated with the operation of the
peripherals are described in the appropriate peripheral
chapter of this data sheet.
DS41364A-page 24
Preliminary
© 2008 Microchip Technology Inc.
TABLE 2-2:
PIC16F1933/1934 MEMORY MAP, BANKS 0-7
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
000h
001h
002h
003h
004h
005h
006h
007h
008h
009h
00Ah
00Bh
00Ch
00Dh
00Eh
INDF0
INDF1
080h
081h
082h
083h
084h
085h
086h
087h
088h
089h
08Ah
08Bh
08Ch
08Dh
08Eh
INDF0
INDF1
PCL
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
INDF0
INDF1
PCL
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
INDF0
INDF1
PCL
200h
201h
202h
203h
204h
205h
206h
207h
208h
209h
20Ah
20Bh
20Ch
20Dh
20Eh
INDF0
INDF1
PCL
280h
281h
282h
283h
284h
285h
286h
287h
288h
289h
28Ah
28Bh
28Ch
28Dh
28Eh
INDF0
INDF1
PCL
300h
301h
302h
303h
304h
305h
306h
307h
308h
309h
30Ah
30Bh
30Ch
30Dh
30Eh
INDF0
INDF1
PCL
380h
381h
382h
383h
384h
385h
386h
387h
388h
389h
38Ah
38Bh
38Ch
38Dh
38Eh
INDF0
INDF1
PCL
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
PORTA
PORTB
PORTC
WREG
PCLATH
INTCON
TRISA
TRISB
TRISC
WREG
PCLATH
INTCON
LATA
WREG
PCLATH
INTCON
ANSELA
ANSELB
—
WREG
PCLATH
INTCON
—
WREG
PCLATH
INTCON
—
WREG
PCLATH
INTCON
—
WREG
PCLATH
INTCON
—
LATB
WPUB
—
—
—
—
LATC
—
—
—
00Fh
PORTD(1)
08Fh
TRISD(1)
10Fh
LATD(1)
18Fh
ANSELD(1)
20Fh
—
28Fh
—
30Fh
—
38Fh
—
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
PORTE
PIR1
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
TRISE
PIE1
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
LATE(1)
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
FVRCON
DACCON0
DACCON1
SRCON0
SRCON1
—
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
ANSELE(1)
EEADRL
EEADRH
EEDATL
EEDATH
EECON1
EECON2
—
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
WPUE
SSPBUF
SSPADD
SSPMSK
SSPSTAT
SSPCON1
SSPCON2
SSPCON3
—
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
—
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
—
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
—
—
CCPR1L
CCPR1H
CCP1CON
PWM1CON
CCP1AS
PSTR1CON
—
CCPR3L
CCPR3H
CCP3CON
PWM3CON
CCP3AS
PSTR3CON
—
PIR2
PIE2
—
PIR3
PIE3
—
—
—
IOCBP
IOCBN
IOCBF
—
TMR0
TMR1L
TMR1H
T1CON
T1GCON
TMR2
PR2
OPTION
PCON
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
—
CCPR2L
CCPR2H
CCP2CON
PWM2CON
CCP2AS
PSTR2CON
CCPTMRS0
CCPR4L
CCPR4H
CCP4CON
—
—
RCREG
TXREG
SPBRGL
SPBRGH
RCSTA
TXSTA
—
—
—
—
—
—
T2CON
—
—
CCPR5L
CCPR5H
CCP5CON
—
APFCON
—
—
—
CPSCON0
—
—
01Fh
020h
CPSCON1
09Fh
0A0h
—
11Fh
120h
—
19Fh
1A0h
BAUDCTR
21Fh
220h
—
29Fh
2A0h
CCPTMRS1
31Fh
320h
—
39Fh
3A0h
—
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
General
Purpose
Register
96 Bytes
36Fh
370h
3EFh
3F0h
06Fh
070h
0EFh
0F0h
16Fh
170h
1EFh
1F0h
26Fh
270h
2EFh
2F0h
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
07Fh
0FFh
17Fh
1FFh
27Fh
2FFh
37Fh
3FFh
Legend:
Note 1:
= Unimplemented data memory locations, read as ‘0’.
Not available on PIC16F1933/1936/1938/PIC16LF1933/1936/1938.
TABLE 2-3:
PIC16F1933/1934 MEMORY MAP, BANKS 8-15
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
BANK 13
BANK 14
BANK 15
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
400h
401h
402h
403h
404h
405h
406h
407h
408h
409h
40Ah
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
480h
481h
482h
483h
484h
485h
486h
487h
488h
489h
48Ah
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
500h
501h
502h
503h
504h
505h
506h
507h
508h
509h
50Ah
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
580h
581h
582h
583h
584h
585h
586h
587h
588h
589h
58Ah
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
600h
601h
602h
603h
604h
605h
606h
607h
608h
609h
60Ah
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
680h
681h
682h
683h
684h
685h
686h
687h
688h
689h
68Ah
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
700h
701h
702h
703h
704h
705h
706h
707h
708h
709h
70Ah
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
780h
781h
782h
783h
784h
785h
786h
787h
788h
789h
78Ah
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TMR4
PR4
T4CON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
See Table 2-10 or
Table 2-11
—
—
—
—
—
—
—
TMR6
PR6
T6CON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
41Fh
420h
49Fh
4A0h
51Fh
520h
59Fh
5A0h
61Fh
620h
69Fh
6A0h
71Fh
720h
79Fh
7A0h
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
46Fh
470h
4EFh
4F0h
56Fh
570h
5EFh
5F0h
66Fh
670h
6EFh
6F0h
76Fh
770h
7EFh
7F0h
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
4FFh
57Fh
47Fh
5FFh
67Fh
6FFh
77Fh
7FFh
Legend:
= Unimplemented data memory locations, read as ‘0’.
TABLE 2-4:
PIC16F1936/1937 MEMORY MAP, BANKS 0-7
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
000h
001h
002h
003h
004h
005h
006h
007h
008h
009h
00Ah
00Bh
00Ch
00Dh
00Eh
INDF0
INDF1
080h
081h
082h
083h
084h
085h
086h
087h
088h
089h
08Ah
08Bh
08Ch
08Dh
08Eh
INDF0
INDF1
PCL
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
INDF0
INDF1
PCL
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
INDF0
INDF1
PCL
200h
201h
202h
203h
204h
205h
206h
207h
208h
209h
20Ah
20Bh
20Ch
20Dh
20Eh
INDF0
INDF1
PCL
280h
281h
282h
283h
284h
285h
286h
287h
288h
289h
28Ah
28Bh
28Ch
28Dh
28Eh
INDF0
INDF1
PCL
300h
301h
302h
303h
304h
305h
306h
307h
308h
309h
30Ah
30Bh
30Ch
30Dh
30Eh
INDF0
INDF1
PCL
380h
381h
382h
383h
384h
385h
386h
387h
388h
389h
38Ah
38Bh
38Ch
38Dh
38Eh
INDF0
INDF1
PCL
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
PORTA
PORTB
PORTC
WREG
PCLATH
INTCON
TRISA
TRISB
TRISC
WREG
PCLATH
INTCON
LATA
WREG
PCLATH
INTCON
ANSELA
ANSELB
—
WREG
PCLATH
INTCON
—
WREG
PCLATH
INTCON
—
WREG
PCLATH
INTCON
—
WREG
PCLATH
INTCON
—
LATB
WPUB
—
—
—
—
LATC
—
—
—
00Fh
PORTD(1)
08Fh
TRISD(1)
10Fh
LATD(1)
18Fh
ANSELD(1)
20Fh
—
28Fh
—
30Fh
—
38Fh
—
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
PORTE
PIR1
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
TRISE
PIE1
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
LATE(1)
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
FVRCON
DACCON0
DACCON1
SRCON0
SRCON1
—
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
ANSELE(1)
EEADRL
EEADRH
EEDATL
EEDATH
EECON1
EECON2
—
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
WPUE
SSPBUF
SSPADD
SSPMSK
SSPSTAT
SSPCON1
SSPCON2
SSPCON3
—
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
—
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
—
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
—
—
CCPR1L
CCPR1H
CCP1CON
PWM1CON
CCP1AS
PSTR1CON
—
CCPR3L
CCPR3H
CCP3CON
PWM3CON
CCP3AS
PSTR3CON
—
PIR2
PIE2
—
PIR3
PIE3
—
—
—
IOCBP
IOCBN
IOCBF
—
TMR0
TMR1L
TMR1H
T1CON
T1GCON
TMR2
PR2
OPTION
PCON
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
—
CCPR2L
CCPR2H
CCP2CON
PWM2CON
CCP2AS
PSTR2CON
CCPTMRS0
CCPR4L
CCPR4H
CCP4CON
—
—
RCREG
TXREG
SPBRGL
SPBRGH
RCSTA
TXSTA
—
—
—
—
—
—
TxCON
—
—
CCPR5L
CCPR5H
CCP5CON
—
APFCON
—
—
—
CPSCON0
—
—
01Fh
020h
CPSCON1
09Fh
0A0h
—
11Fh
120h
—
19Fh
1A0h
BAUDCON
21Fh
220h
—
29Fh
2A0h
CCPTMRS1
31Fh
320h
—
39Fh
3A0h
—
General Purpose
Register
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
16 Bytes
32Fh
330h
Unimplemented
Read as ‘0’
General
Purpose
Register
96 Bytes
Unimplemented
Read as ‘0’
36Fh
370h
3EFh
3F0h
06Fh
070h
0EFh
0F0h
16Fh
170h
1EFh
1F0h
26Fh
270h
2EFh
2F0h
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
07Fh
0FFh
17Fh
1FFh
27Fh
2FFh
37Fh
3FFh
Legend:
Note 1:
= Unimplemented data memory locations, read as ‘0’.
Not available on PIC16F1933/1936/1938/PIC16LF1933/1936/1938.
TABLE 2-5:
PIC16F1936/1937 MEMORY MAP, BANKS 8-15
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
BANK 13
BANK 14
BANK 15
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
400h
401h
402h
403h
404h
405h
406h
407h
408h
409h
40Ah
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
480h
481h
482h
483h
484h
485h
486h
487h
488h
489h
48Ah
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
500h
501h
502h
503h
504h
505h
506h
507h
508h
509h
50Ah
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
580h
581h
582h
583h
584h
585h
586h
587h
588h
589h
58Ah
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
600h
601h
602h
603h
604h
605h
606h
607h
608h
609h
60Ah
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
680h
681h
682h
683h
684h
685h
686h
687h
688h
689h
68Ah
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
700h
701h
702h
703h
704h
705h
706h
707h
708h
709h
70Ah
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
780h
781h
782h
783h
784h
785h
786h
787h
788h
789h
78Ah
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TMR4
PR4
T4CON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
See Table 2-10 or
Table 2-11
—
—
—
—
—
—
—
TMR6
PR6
T6CON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
41Fh
420h
49Fh
4A0h
51Fh
520h
59Fh
5A0h
61Fh
620h
69Fh
6A0h
71Fh
720h
79Fh
7A0h
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
46Fh
470h
4EFh
4F0h
56Fh
570h
5EFh
5F0h
66Fh
670h
6EFh
6F0h
76Fh
770h
7EFh
7F0h
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
4FFh
57Fh
47Fh
5FFh
67Fh
6FFh
77Fh
7FFh
Legend:
= Unimplemented data memory locations, read as ‘0’.
TABLE 2-6:
PIC16F1938/1939 MEMORY MAP, BANKS 0-7
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
000h
001h
002h
003h
004h
005h
006h
007h
008h
009h
00Ah
00Bh
00Ch
00Dh
00Eh
INDF0
INDF1
080h
081h
082h
083h
084h
085h
086h
087h
088h
089h
08Ah
08Bh
08Ch
08Dh
08Eh
INDF0
INDF1
PCL
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
INDF0
INDF1
PCL
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
INDF0
INDF1
PCL
200h
201h
202h
203h
204h
205h
206h
207h
208h
209h
20Ah
20Bh
20Ch
20Dh
20Eh
INDF0
INDF1
PCL
280h
281h
282h
283h
284h
285h
286h
287h
288h
289h
28Ah
28Bh
28Ch
28Dh
28Eh
INDF0
INDF1
PCL
300h
301h
302h
303h
304h
305h
306h
307h
308h
309h
30Ah
30Bh
30Ch
30Dh
30Eh
INDF0
INDF1
PCL
380h
381h
382h
383h
384h
385h
386h
387h
388h
389h
38Ah
38Bh
38Ch
38Dh
38Eh
INDF0
INDF1
PCL
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
PORTA
PORTB
PORTC
WREG
PCLATH
INTCON
TRISA
TRISB
TRISC
WREG
PCLATH
INTCON
LATA
WREG
PCLATH
INTCON
ANSELA
ANSELB
—
WREG
PCLATH
INTCON
—
WREG
PCLATH
INTCON
—
WREG
PCLATH
INTCON
—
WREG
PCLATH
INTCON
—
LATB
WPUB
—
—
—
—
LATC
—
—
—
00Fh
PORTD(1)
08Fh
TRISD(1)
10Fh
LATD(1)
18Fh
ANSELD(1)
20Fh
—
28Fh
—
30Fh
—
38Fh
—
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
PORTE
PIR1
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
TRISE
PIE1
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
LATE(1)
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
FVRCON
DACCON0
DACCON1
SRCON0
SRCON1
—
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
ANSELE(1)
EEADRL
EEADRH
EEDATL
EEDATH
EECON1
EECON2
—
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
WPUE
SSPBUF
SSPADD
SSPMSK
SSPSTAT
SSPCON1
SSPCON2
SSPCON3
—
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
—
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
—
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
—
—
CCPR1L
CCPR1H
CCP1CON
PWM1CON
CCP1AS
PSTR1CON
—
CCPR3L
CCPR3H
CCP3CON
PWM3CON
CCP3AS
PSTR3CON
—
PIR2
PIE2
—
PIR3
PIE3
—
—
—
IOCBP
IOCBN
IOCBF
—
TMR0
TMR1L
TMR1H
T1CON
T1GCON
TMR2
PR2
OPTION
PCON
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
—
CCPR2L
CCPR2H
CCP2CON
PWM2CON
CCP2AS
PSTR2CON
CCPTMRS0
CCPR4L
CCPR4H
CCP4CON
—
—
RC1REG
TX1REG
SPBRGL1
SPBRGH1
RCSTA1
TXSTA1
—
—
—
—
—
—
T2CON
—
—
CCPR5L
CCPR5H
CCP5CON
—
APFCON
—
—
—
CPSCON0
—
—
01Fh
020h
CPSCON1
09Fh
0A0h
—
11Fh
120h
—
19Fh
1A0h
BAUDCTL1
21Fh
220h
—
29Fh
2A0h
CCPTMRS1
31Fh
320h
—
39Fh
3A0h
—
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
32Fh
330h
General
Purpose
Register
96 Bytes
36Fh
370h
3EFh
3F0h
06Fh
070h
0EFh
0F0h
16Fh
170h
1EFh
1F0h
26Fh
270h
2EFh
2F0h
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
07Fh
0FFh
17Fh
1FFh
27Fh
2FFh
37Fh
3FFh
Legend:
Note 1:
= Unimplemented data memory locations, read as ‘0’.
Not available on PIC16F1933/1936/1938/PIC16LF1933/1936/1938.
TABLE 2-7:
PIC16F1938/1939 MEMORY MAP, BANKS 8-15
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
BANK 13
BANK 14
BANK 15
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
INDF0
INDF1
PCL
400h
401h
402h
403h
404h
405h
406h
407h
408h
409h
40Ah
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
480h
481h
482h
483h
484h
485h
486h
487h
488h
489h
48Ah
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
500h
501h
502h
503h
504h
505h
506h
507h
508h
509h
50Ah
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
580h
581h
582h
583h
584h
585h
586h
587h
588h
589h
58Ah
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
600h
601h
602h
603h
604h
605h
606h
607h
608h
609h
60Ah
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
680h
681h
682h
683h
684h
685h
686h
687h
688h
689h
68Ah
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
700h
701h
702h
703h
704h
705h
706h
707h
708h
709h
70Ah
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
780h
781h
782h
783h
784h
785h
786h
787h
788h
789h
78Ah
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TMR4
PR4
T4CON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
See Table 2-10 or
Table 2-11
—
—
—
—
—
—
—
TMR6
PR6
T6CON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
41Fh
420h
49Fh
4A0h
51Fh
520h
59Fh
5A0h
61Fh
620h
69Fh
6A0h
71Fh
720h
79Fh
7A0h
General Purpose
Register
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
48 Bytes
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
46Fh
470h
4EFh
4F0h
56Fh
570h
5EFh
5F0h
66Fh
670h
6EFh
6F0h
76Fh
770h
7EFh
7F0h
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
4FFh
57Fh
47Fh
5FFh
67Fh
6FFh
77Fh
7FFh
Legend:
= Unimplemented data memory locations, read as ‘0’.
TABLE 2-8:
PIC16F193X/LF193X MEMORY MAP, BANKS 16-23
BANK 16
BANK 17
BANK 18
BANK 19
BANK 20
BANK 21
BANK 22
BANK 23
800h
801h
802h
803h
804h
805h
806h
807h
808h
809h
80Ah
80Bh
80Ch
80Dh
80Eh
80Fh
810h
811h
812h
813h
814h
815h
816h
817h
818h
819h
81Ah
81Bh
81Ch
81Dh
81Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
880h
881h
882h
883h
884h
885h
886h
887h
888h
889h
88Ah
88Bh
88Ch
88Dh
88Eh
88Fh
890h
891h
892h
893h
894h
895h
896h
897h
898h
899h
89Ah
89Bh
89Ch
89Dh
89Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
900h
901h
902h
903h
904h
905h
906h
907h
908h
909h
90Ah
90Bh
90Ch
90Dh
90Eh
90Fh
910h
911h
912h
913h
914h
915h
916h
917h
918h
919h
91Ah
91Bh
91Ch
91Dh
91Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
980h
981h
982h
983h
984h
985h
986h
987h
988h
989h
98Ah
98Bh
98Ch
98Dh
98Eh
98Fh
990h
991h
992h
993h
994h
995h
996h
997h
998h
999h
99Ah
99Bh
99Ch
99Dh
99Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
A00h
A01h
A02h
A03h
A04h
A05h
A06h
A07h
A08h
A09h
A0Ah
A0Bh
A0Ch
A0Dh
A0Eh
A0Fh
A10h
A11h
A12h
A13h
A14h
A15h
A16h
A17h
A18h
A19h
A1Ah
A1Bh
A1Ch
A1Dh
A1Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
A80h
A81h
A82h
A83h
A84h
A85h
A86h
A87h
A88h
A89h
A8Ah
A8Bh
A8Ch
A8Dh
A8Eh
A8Fh
A90h
A91h
A92h
A93h
A94h
A95h
A96h
A97h
A98h
A99h
A9Ah
A9Bh
A9Ch
A9Dh
A9Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
B00h
B01h
B02h
B03h
B04h
B05h
B06h
B07h
B08h
B09h
B0Ah
B0Bh
B0Ch
B0Dh
B0Eh
B0Fh
B10h
B11h
B12h
B13h
B14h
B15h
B16h
B17h
B18h
B19h
B1Ah
B1Bh
B1Ch
B1Dh
B1Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
B80h
B81h
B82h
B83h
B84h
B85h
B86h
B87h
B88h
B89h
B8Ah
B8Bh
B8Ch
B8Dh
B8Eh
B8Fh
B90h
B91h
B92h
B93h
B94h
B95h
B96h
B97h
B98h
B99h
B9Ah
B9Bh
B9Ch
B9Dh
B9Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
81Fh
820h
—
89Fh
8A0h
—
91Fh
920h
—
99Fh
9A0h
—
A1Fh
A20h
—
A9Fh
AA0h
—
B1Fh
B20h
—
B9Fh
BA0h
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
9EFh
9F0h
AEFh
AF0h
BEFh
BF0h
86Fh
870h
8EFh
8F0h
96Fh
970h
A6Fh
A70h
B6Fh
B70h
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
87Fh
8FFh
97Fh
9FFh
A7Fh
AFFh
B7Fh
BFFh
Legend:
= Unimplemented data memory locations, read as ‘0’.
TABLE 2-9:
PIC16F193X/LF193X MEMORY MAP, BANKS 24-31
BANK 24
BANK 25
BANK 26
BANK 27
BANK 28
BANK 29
BANK 30
BANK 31
C00h
C01h
C02h
C03h
C04h
C05h
C06h
C07h
C08h
C09h
C0Ah
C0Bh
C0Ch
C0Dh
C0Eh
C0Fh
C10h
C11h
C12h
C13h
C14h
C15h
C16h
C17h
C18h
C19h
C1Ah
C1Bh
C1Ch
C1Dh
C1Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
C80h
C81h
C82h
C83h
C84h
C85h
C86h
C87h
C88h
C89h
C8Ah
C8Bh
C8Ch
C8Dh
C8Eh
C8Fh
C90h
C91h
C92h
C93h
C94h
C95h
C96h
C97h
C98h
C99h
C9Ah
C9Bh
C9Ch
C9Dh
C9Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
D00h
D01h
D02h
D03h
D04h
D05h
D06h
D07h
D08h
D09h
D0Ah
D0Bh
D0Ch
D0Dh
D0Eh
D0Fh
D10h
D11h
D12h
D13h
D14h
D15h
D16h
D17h
D18h
D19h
D1Ah
D1Bh
D1Ch
D1Dh
D1Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
D80h
D81h
D82h
D83h
D84h
D85h
D86h
D87h
D88h
D89h
D8Ah
D8Bh
D8Ch
D8Dh
D8Eh
D8Fh
D90h
D91h
D92h
D93h
D94h
D95h
D96h
D97h
D98h
D99h
D9Ah
D9Bh
D9Ch
D9Dh
D9Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
E00h
E01h
E02h
E03h
E04h
E05h
E06h
E07h
E08h
E09h
E0Ah
E0Bh
E0Ch
E0Dh
E0Eh
E0Fh
E10h
E11h
E12h
E13h
E14h
E15h
E16h
E17h
E18h
E19h
E1Ah
E1Bh
E1Ch
E1Dh
E1Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
E80h
E81h
E82h
E83h
E84h
E85h
E86h
E87h
E88h
E89h
E8Ah
E8Bh
E8Ch
E8Dh
E8Eh
E8Fh
E90h
E91h
E92h
E93h
E94h
E95h
E96h
E97h
E98h
E99h
E9Ah
E9Bh
E9Ch
E9Dh
E9Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
F00h
F01h
F02h
F03h
F04h
F05h
F06h
F07h
F08h
F09h
F0Ah
F0Bh
F0Ch
F0Dh
F0Eh
F0Fh
F10h
F11h
F12h
F13h
F14h
F15h
F16h
F17h
F18h
F19h
F1Ah
F1Bh
F1Ch
F1Dh
F1Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
F80h
F81h
F82h
F83h
F84h
F85h
F86h
F87h
F88h
F89h
F8Ah
F8Bh
F8Ch
F8Dh
F8Eh
F8Fh
F90h
F91h
F92h
F93h
F94h
F95h
F96h
F97h
F98h
F99h
F9Ah
F9Bh
F9Ch
F9Dh
F9Eh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
See Table 2-12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C1Fh
C20h
—
C9Fh
CA0h
—
D1Fh
D20h
—
D9Fh
DA0h
—
E1Fh
E20h
—
E9Fh
EA0h
—
F1Fh
F20h
—
F9Fh
FA0h
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
C6Fh
C70h
CEFh
CF0h
D6Fh
D70h
DEFh
DF0h
E6Fh
E70h
EEFh
EF0h
F6Fh
F70h
FEFh
FF0h
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
CFFh
D7Fh
DFFh
E7Fh
EFFh
F7Fh
FFFh
CFFh
Legend:
= Unimplemented data memory locations, read as ‘0’.
PIC16F193X/LF193X
TABLE 2-10: PIC16F1933/1936/1938
MEMORY MAP, BANK 15
TABLE 2-11: PIC16F1934/1937/1939
MEMORY MAP, BANK 15
Bank 15
Bank 15
LCDCON
LCDPS
LCDREF
LCDCST
LCDRL
—
LCDCON
LCDPS
LCDREF
LCDCST
LCDRL
—
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
—
—
LCDSE0
LCDSE1
—
LCDSE0
LCDSE1
LCDSE2
—
—
—
—
—
—
—
—
—
—
79Fh
7A0h
7A1h
79Fh
7A0h
7A1h
7A2h
7A3h
7A4h
7A5h
7A6h
7A7h
7A8h
7A9h
7AAh
7ABh
LCDDATA0
LCDDATA1
LCDDATA0
LCDDATA1
LCDDATA2
LCDDATA3
LCDDATA4
LCDDATA5
LCDDATA6
LCDDATA7
LCDDATA8
LCDDATA9
LCDDATA10
LCDDATA11
—
—
7A2h
7A3h
7A4h
LCDDATA3
LCDDATA4
—
7A5h
7A6h
7A7h
LCDDATA6
LCDDATA7
—
LCDDATA9
LCDDATA10
—
7A8h
7A9h
7AAh
7ABh
7ACh
7ADh
7AEh
7AFh
7B0h
7B1h
7B2h
7B3h
7B4h
7B5h
7B6h
7B7h
7B8h
7ACh
7ADh
7AEh
7AFh
7B0h
7B1h
7B2h
7B3h
7B4h
7B5h
7B6h
7B7h
7B8h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
7EFh
7EFh
Legend:
= Unimplemented data memory locations,
Legend:
= Unimplemented data memory locations,
read as ‘0’.
read as ‘0’.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 33
PIC16F193X/LF193X
TABLE 2-12: PIC16F193X/LF193X MEMORY
MAP, BANK 31
Bank 31
F8Ch
Unimplemented
Read as ‘0’
FE3h
STATUS_SHAD
WREG_SHAD
BSR_SHAD
PCLATH_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
—
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
FECh
FEDh
FEEh
FEFh
STKPTR
TOSL
TOSH
Legend:
= Unimplemented data memory locations,
read as ‘0’.
DS41364A-page 34
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 2-13: SPECIAL FUNCTION REGISTER SUMMARY
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0
000h(2)
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
001h(2)
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
002h(2)
003h(2)
004h(2)
005h(2)
006h(2)
007h(2)
008h(2)
009h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR4
BSR3
BSR2
BSR1
INTF
BSR0
IOCIF
WREG
Working Register
00Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
00Bh(2)
00Ch
00Dh
00Eh
00Fh(3)
010h
011h
INTCON
PORTA
PORTB
PORTC
PORTD
PORTE
PIR1
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
—
TMR1GIF
OSFIF
—
—
—
—
RE3
SSPIF
BCLIF
TMR6IF
RE2(3)
CCP1IF
LCDIF
—
RE1(3)
TMR2IF
—
RE0(3) ---- xxxx ---- uuuu
TMR1IF 0000 0000 0000 0000
CCP2IF 0000 00-0 0000 00-0
ADIF
RCIF
TXIF
012h
013h
014h
015h
016h
017h
018h
019h
PIR2
C2IF
C1IF
EEIF
PIR3
CCP5IF
CCP4IF
CCP3IF
TMR4IF
—
-000 0-0- -000 0-0-
PIR4
Unimplemented
—
—
TMR0
Timer0 Module Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR1L
TMR1H
T1CON
T1GCON
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
—
TMR1ON 0000 00-0 uuuu uu-u
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS1 T1GSS0 0000 0x00 uuuu uxuu
01Ah
01Bh
01Ch
01Dh
01Eh
01Fh
TMR2
Timer 2 Module Register
Timer 2 Period Register
0000 0000 0000 0000
1111 1111 1111 1111
PR2
T2CON
—
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Unimplemented
CPSON
—
—
—
CPSCON0
CPSCON1
—
—
—
—
—
—
CPSRNG1 CPSRNG0 CPSOUT T0XCS 0--- 0000 0--- 0000
CPSCH3 CPSCH2 CPSCH1 CPSCH0 ---- 0000 ---- 0000
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 35
PIC16F193X/LF193X
TABLE 2-13: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 1
080h(2)
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
081h(2)
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
082h(2)
083h(2)
084h(2)
085h(2)
086h(2)
087h(2)
088h(2)
089h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR4
BSR3
BSR2
BSR1
INTF
BSR0
IOCIF
WREG
Working Register
08Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
08Bh(2)
08Ch
08Dh
08Eh
08Fh(3)
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
09Fh
Legend:
INTCON
TRISA
TRISB
TRISC
TRISD
TRISE
PIE1
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
PORTA Data Direction Register
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
—
TMR1GIE
OSFIE
—
—
—
—
TRISE3
SSPIE
TRISE2(3) TRISE1(3) TRISE0(3) ---- 1111 ---- 1111
ADIE
RCIE
TXIE
CCP1IE
LCDIE
—
TMR2IE
—
TMR1IE 0000 0000 0000 0000
CCP2IE 0000 00-0 0000 00-0
PIE2
C2IE
C1IE
EEIE
BCLIE
PIE3
CCP5IE
CCP4IE
CCP3IE
TMR6IE
TMR4IE
—
-000 0-0- -000 0-0-
—
Unimplemented
—
—
OPTION_REG WPUEN
INTEDG
STKUNF
—
T0CS
—
T0SE
—
PSA
RMCLR
WDTPS2
TUN3
PS2
RI
PS1
PS0
1111 1111 1111 1111
00-- 11qq qq-- qquu
PCON
STKOVF
—
POR
BOR
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
—
WDTPS4
TUN5
IRCF2
OSTS
WDTPS3
TUN4
WDTPS1 WDTPS0 SWDTEN --01 0110 --01 0110
—
—
TUN2
—
TUN1
SCS1
TUN0
SCS0
--00 0000 --00 0000
0011 1-00 0011 1-00
SPLLEN
T1OSCR
IRCF3
PLLR
IRCF1
HFIOFR
IRCF0
HFIOFL
MFIOFR
LFIOFR
HFIOFR 00q0 0q0- qqqq qq0-
xxxx xxxx uuuu uuuu
A/D Result Register Low
A/D Result Register High
xxxx xxxx uuuu uuuu
—
CHS4
CHS3
CHS2
CHS1
—
CHS0
GO/DONE
ADON
-000 0000 -000 0000
ADFM
ADCS2
ADCS1
ADCS0
ADNREF ADPREF1 ADPREF0 0000 -000 0000 -000
Unimplemented
—
—
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
DS41364A-page 36
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 2-13: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 2
100h(2)
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
101h(2)
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
102h(2)
103h(2)
104h(2)
105h(2)
106h(2)
107h(2)
108h(2)
109h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR4
BSR3
BSR2
BSR1
INTF
BSR0
IOCIF
WREG
Working Register
10Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
10Bh(2)
10Ch
10Dh
10Eh
10Fh(3)
110h
INTCON
LATA
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
PORTA Data Latch
PORTB Data Latch
PORTC Data Latch
PORTD Data Latch
LATB
LATC
LATD
LATE
—
—
—
C1OE
C1PCH1
C2OE
C2PCH1
—
—
LATE3
—
LATE2(3) LATE1(3) LATE0(3) ---- -xxx ---- -uuu
111h
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
FVRCON
DACCON0
DACCON1
SRCON0
SRCON1
—
C1ON
C1INTP
C2ON
C2INTP
—
C1OUT
C1INTN
C2OUT
C2INTN
—
C1POL
C1PCH0
C2POL
C2PCH0
—
C1SP
—
C1HYS C1SYNC 0000 -100 0000 -100
C1NCH1 C1NCH0 0000 --00 0000 --00
C2HYS C2SYNC 0000 -100 0000 -100
C2NCH1 C2NCH0 0000 --00 0000 --00
MC2OUT MC1OUT ---- --00 ---- --00
112h
—
113h
—
C2SP
—
114h
—
115h
—
—
116h
SBOREN
FVREN
DACEN
---
—
—
—
—
—
—
BORRDY 1--- ---q u--- ---u
117h
FVRRDY
DACLPS
---
TSEN
DACOE
---
TSRNG
---
CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 0q00 0000 0q00 0000
118h
DACPSS1 DACPSS0
---
DACNSS 000- 00-0 000- 00-0
DACR0 ---0 0000 ---0 0000
119h
DACR4
SRCLK0
SRSC1E
DACR3
SRQEN
SRRPE
DACR2
DACR1
SRPS
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
Legend:
SRLEN
SRSPE
SRCLK2
SRSCKE
SRCLK1
SRSC2E
SRNQEN
SRPR
0000 0000 0000 0000
SRRCKE SRRC2E SRRC1E 0000 0000 0000 0000
Unimplemented
—
—
APFCON
—
—
CCP3SEL
T1GSEL
P2BSEL
SRNQSEL C2OUTSEL SSSEL CCP2SEL -000 0000 -000 0000
Unimplemented
Unimplemented
—
—
—
—
—
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 37
PIC16F193X/LF193X
TABLE 2-13: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 3
180h(2)
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
181h(2)
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
182h(2)
183h(2)
184h(2)
185h(2)
186h(2)
187h(2)
188h(2)
189h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR4
BSR3
BSR2
BSR1
BSR0
IOCIF
WREG
Working Register
18Ah(1, 2) PCLATH
—
GIE
—
Write Buffer for the upper 7 bits of the Program Counter
18Bh(2)
18Ch
18Dh
18Eh
18Fh(3)
190h(3)
191h
INTCON
ANSELA
ANSELB
—
PEIE
—
TMR0IE
ANSA5
ANSB5
INTE
IOCIE
ANSA3
ANSB3
TMR0IF
ANSA2
ANSB2
INTF
ANSA4
ANSB4
ANSA1
ANSB1
ANSA0 --11 1111 --11 1111
ANSB0 --11 1111 --11 1111
—
—
Unimplemented
—
—
ANSELD
ANSELE
EEADRL
EEADRH
EEDATL
EEDATH
EECON1
EECON2
—
ANSD7
—
ANSD6
ANSD5
—
ANSD4
—
ANSD3
—
ANSD2
ANSE2
ANSD1
ANSE1
ANSD0 1111 1111 1111 1111
ANSE0 ---- -111 ---- -111
0000 0000 0000 0000
—
EEPROM / Program Memory Address Register Low Byte
EEPROM / Program Memory Address Register High Byte
EEPROM / Program Memory Read Data Register Low Byte
192h
—
-000 0000 -000 0000
193h
xxxx xxxx uuuu uuuu
194h
—
—
EEPROM / Program Memory Read Data Register High Byte
--xx xxxx --uu uuuu
195h
EEPGD
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
0000 x000 0000 q000
0000 0000 0000 0000
196h
EEPROM control register 2
Unimplemented
197h
—
—
—
—
198h
—
Unimplemented
199h
RCREG
TXREG
SPBRGL
SPBRGH
RCSTA
TXSTA
USART Receive Data Register
USART Transmit Data Register
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 000x 0000 000x
0000 0010 0000 0010
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
Legend:
BRG7
BRG15
SPEN
BRG6
BRG14
RX9
BRG5
BRG13
SREN
TXEN
—
BRG4
BRG12
CREN
SYNC
SCKP
BRG3
BRG11
ADDEN
SENDB
BRG16
BRG2
BRG10
FERR
BRGH
—
BRG1
BRG9
OERR
TRMT
WUE
BRG0
BRG8
RX9D
TX9D
CSRC
TX9
BAUDCON
ABDOVF
RCIDL
ABDEN 01-0 0-00 01-0 0-00
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
DS41364A-page 38
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 2-13: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 4
200h(2)
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
201h(2)
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
202h(2)
203h(2)
204h(2)
205h(2)
206h(2)
207h(2)
208h(2)
209h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR4
BSR3
BSR2
BSR1
BSR0
IOCIF
WREG
Working Register
20Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
20Bh(2)
20Ch
20Dh
20Eh
20Fh
210h
211h
INTCON
—
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
Unimplemented
—
—
WPUB
—
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0 1111 1111 1111 1111
Unimplemented
Unimplemented
—
—
—
—
—
—
WPUE
SSPBUF
SSPADD
SSPMSK
—
—
—
WPUE3
—
—
—
---- 1--- ---- 1---
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
1111 1111 1111 1111
Synchronous Serial Port Receive Buffer/Transmit Register
212h
213h
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
MSK7
SMP
MSK6
CKE
MSK5
D/A
MSK4
P
MSK3
S
MSK2
R/W
MSK1
UA
MSK0
BF
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
Legend:
SSPSTAT
0000 0000 0000 0000
SSPCON1
WCOL
GCEN
ACKTIM
SSPOV
ACKSTAT
PCIE
SSPEN
ACKDT
SCIE
CKP
SSPM3
RCEN
SDAHT
SSPM2
PEN
SSPM1
RSEN
AHEN
SSPM0 0000 0000 0000 0000
SSPCON2
ACKEN
BOEN
SEN
0000 0000 0000 0000
0000 0000 0000 0000
SSPCON3
SBCDE
DHEN
—
—
—
—
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 39
PIC16F193X/LF193X
TABLE 2-13: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 5
280h(2)
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
281h(2)
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
282h(2)
283h(2)
284h(2)
285h(2)
286h(2)
287h(2)
288h(2)
289h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR4
BSR3
BSR2
BSR1
INTF
BSR0
IOCIF
WREG
Working Register
28Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
28Bh(2)
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
Legend:
INTCON
—
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CCPR1L
CCPR1H
CCP1CON
PWM1CON
CCP1AS
PSTR1CON
—
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
P1M1
P1M0
DC1B1
P1DC5
DC1B0
P1DC4
CCP1M3
P1DC3
CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
P1DC2 P1DC1 P1DC0 0000 0000 0000 0000
P1RSEN
P1DC6
CCP1ASE CCP1AS2 CCP1AS1 CCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 0000 0000
—
—
—
STR1SYNC
STR1D
STR1C
STR1B
STR1A ---0 0001 ---0 0001
Unimplemented
—
—
CCPR2L
CCPR2H
CCP2CON
PWM2CON
CCP2AS
PSTR2CON
CCPTMRS0
CCPTMRS1
Capture/Compare/PWM Register 2 (LSB)
Capture/Compare/PWM Register 2 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
P2M1
P2M0
DC2B1
P2DC5
DC2B0
P2DC4
CCP2M3
P2DC3
CCP2M2 CCP2M1 CCP2M0 0000 0000 0000 0000
P2DC2 P2DC1 P2DC0 0000 0000 0000 0000
P2RSEN
P2DC6
CCP2ASE CCP2AS2 CCP2AS1 CCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 0000 0000
—
—
—
C3TSEL1
—
STR2SYNC
C3TSEL0
—
STR2D
C2TSEL1 C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000
C5TSEL1 C5TSEL0 ---- --00 ---- --00
STR2C
STR2B
STR2A ---0 0001 ---0 0001
C4TSEL1 C4TSEL0
—
—
—
—
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
DS41364A-page 40
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 2-13: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 6
300h(2)
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
301h(2)
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
302h(2)
303h(2)
304h(2)
305h(2)
306h(2)
307h(2)
308h(2)
309h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR4
BSR3
BSR2
BSR1
INTF
BSR0
IOCIF
WREG
Working Register
30Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
30Bh(2)
30Ch
30Dh
30Eh
30Fh
310h
311h
INTCON
—
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CCPR3L
CCPR3H
CCP3CON
PWM3CON
CCP3AS
PSTR3CON
—
Capture/Compare/PWM Register 3 (LSB)
Capture/Compare/PWM Register 3 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
31Fh
Legend:
P3M1
P3M0
DC3B1
P3DC5
DC3B0
P3DC4
CCP3M3
P3DC3
CCP3M2 CCP3M1 CCP3M0 0000 0000 0000 0000
P3DC2 P3DC1 P3DC0 0000 0000 0000 0000
P3RSEN
P3DC6
CCP3ASE CCP3AS2 CCP3AS1 CCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 0000 0000
—
—
—
STR3SYNC
STR3D
CCP4M3
CCP5M3
STR3C
STR3B
STR3A ---0 0001 ---0 0001
Unimplemented
—
—
CCPR4L
CCPR4H
CCP4CON
—
Capture/Compare/PWM Register 4 (LSB)
Capture/Compare/PWM Register 4 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
DC4B1
DC4B0
CCP4M2 CCP4M1 CCP4M0 --00 0000 --00 0000
Unimplemented
—
—
CCPR5L
CCPR5H
CCP5CON
—
Capture/Compare/PWM Register 5 (LSB)
Capture/Compare/PWM Register 5 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
DC5B1
DC5B0
CCP5M2 CCP5M1 CCP5M0 --00 0000 --00 0000
Unimplemented
—
—
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 41
PIC16F193X/LF193X
TABLE 2-13: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 7
380h(2)
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
381h(2)
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
382h(2)
383h(2)
384h(2)
385h(2)
386h(2)
387h(2)
388h(2)
389h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR4
BSR3
BSR2
BSR1
INTF
BSR0
IOCIF
WREG
Working Register
38Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
38Bh(2)
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
Legend:
INTCON
—
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOCBP
IOCBN
IOCBF
—
IOCBP7
IOCBN7
IOCBF7
IOCBP6
IOCBP5
IOCBN5
IOCBF5
IOCBP4
IOCBN4
IOCBF4
IOCBP3
IOCBN3
IOCBF3
IOCBP2
IOCBN2
IOCBF2
IOCBP1
IOCBP0 0000 0000 0000 0000
IOCBN6
IOCBF6
IOCBN1 IOCBN0 0000 0000 0000 0000
IOCBF1 IOCBF0 0000 0000 0000 0000
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
DS41364A-page 42
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 2-13: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 8
400h(2)
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
401h(2)
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
402h(2)
403h(2)
404h(2)
405h(2)
406h(2)
407h(2)
408h(2)
409h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR4
BSR3
BSR2
BSR1
INTF
BSR0
IOCIF
WREG
Working Register
40Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
PEIE TMR0IE INTE IOCIE TMR0IF
40Bh(2)
40Ch
40Dh
40Eh
40Fh
410h
411h
INTCON
—
GIE
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Timer 4 Module Register
Timer 4 Period Register
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh
Legend:
—
—
—
TMR4
PR4
T4CON
—
0000 0000 0000 0000
1111 1111 1111 1111
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0
—
TMR4ON T4CKPS1 T4CKPS0 -000 0000 -000 0000
Unimplemented
—
—
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
—
Unimplemented
TMR6
PR6
T6CON
—
Timer 6 Module Register
Timer 6 Period Register
0000 0000 0000 0000
1111 1111 1111 1111
T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0
—
TMR6ON T6CKPS1 T6CKPS0 -000 0000 -000 0000
Unimplemented
—
—
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 43
PIC16F193X/LF193X
TABLE 2-13: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Banks 9-14
x00h/
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
x80h(2)
x00h/
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
x81h(2)
x02h/
PCL
Program Counter (PC) Least Significant Byte
x82h(2)
x03h/
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
x83h(2)
x04h/
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
x84h(2)
x05h/
x85h(2)
x06h/
x86h(2)
x07h/
x87h(2)
x08h/
—
—
—
BSR4
BSR3
BSR2
BSR1
INTF
BSR0
IOCIF
x88h(2)
x09h/
WREG
PCLATH
INTCON
—
Working Register
x89h(2)
x0Ah/
—
Write Buffer for the upper 7 bits of the Program Counter
PEIE TMR0IE INTE IOCIE TMR0IF
x8Ah(1),(2)
x0Bh/
GIE
x8Bh(2)
x0Ch/
x8Ch
—
Unimplemented
—
—
x1Fh/
x9Fh
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
DS41364A-page 44
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 2-13: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 15
780h(2)
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
781h(2)
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
782h(2)
783h(2)
784h(2)
785h(2)
786h(2)
787h(2)
788h(2)
789h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR4
BSR3
BSR2
BSR1
INTF
BSR0
IOCIF
WREG
Working Register
78Ah(1, 2) PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
78Bh(2)
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LCDCON
LCDPS
LCDREF
LCDCST
LCDRL
—
LCDEN
WFT
SLPEN
WERR
LCDA
LCDIRI
—
—
WA
CS1
LP3
CS0
LP2
LMUX1
LP1
LMUX0 000- 0011 000- 0011
BIASMD
LCDIRS
—
LP0
—
0000 0000 0000 0000
000- 000- 000- 000-
LCDIRE
—
—
VLCD3PE VLCD2PE VLCD1PE
—
—
—
LCDCST2 LCDCST1 LCDCST0 ---- -000 ---- -000
LRLAP1
LRLAP0
LRLBP1
LRLBP0
LRLAT2
LRLAT1
LRLAT0 0000 -000 0000 -000
Unimplemented
Unimplemented
SE7
—
—
—
—
—
LCDSE0
LCDSE1
LCDSE2(3)
—
SE6
SE5
SE13
SE21
SE4
SE12
SE20
SE3
SE11
SE19
SE2
SE10
SE18
SE1
SE9
SE0
SE8
0000 0000 uuuu uuuu
0000 0000 uuuu uuuu
0000 0000 uuuu uuuu
SE15
SE23
SE14
SE22
SE17
SE16
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LCDDATA0
SEG7
COM0
SEG6
COM0
SEG5
COM0
SEG4
COM0
SEG3
COM0
SEG2
COM0
SEG1
COM0
SEG0
COM0
xxxx xxxx uuuu uuuu
7A1h
7A2h
7A3h
7A4h
7A5h
Legend:
LCDDATA1
LCDDATA2(3)
LCDDATA3
LCDDATA4
LCDDATA5(3)
SEG15
COM0
SEG14
COM0
SEG13
COM0
SEG12
COM0
SEG11
COM0
SEG10
COM0
SEG9
COM0
SEG8
COM0
xxxx xxxx uuuu uuuu
SEG23
COM0
SEG22
COM0
SEG21
COM0
SEG20
COM0
SEG19
COM0
SEG18
COM0
SEG17
COM0
SEG16 xxxx xxxx uuuu uuuu
COM0
SEG7
COM1
SEG6
COM1
SEG5
COM1
SEG4
COM1
SEG3
COM1
SEG2
COM1
SEG1
COM1
SEG0
COM1
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
SEG15
COM1
SEG14
COM1
SEG13
COM1
SEG12
COM1
SEG11
COM1
SEG10
COM1
SEG9
COM1
SEG8
COM1
SEG23
COM1
SEG22
COM1
SEG21
COM1
SEG20
COM1
SEG19
COM1
SEG18
COM1
SEG17
COM1
SEG16 xxxx xxxx uuuu uuuu
COM1
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 45
PIC16F193X/LF193X
TABLE 2-13: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 15 (Continued)
7A6h
LCDDATA6
LCDDATA7
LCDDATA8(3)
LCDDATA9
LCDDATA10
LCDDATA11(3)
—
SEG7
COM2
SEG6
COM2
SEG5
COM2
SEG4
COM2
SEG3
COM2
SEG2
COM2
SEG1
COM2
SEG0
COM2
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
7A7h
7A8h
7A9h
7AAh
7ABh
SEG15
COM2
SEG14
COM2
SEG13
COM2
SEG12
COM2
SEG11
COM2
SEG10
COM2
SEG9
COM2
SEG8
COM2
SEG23
COM2
SEG22
COM2
SEG21
COM2
SEG20
COM2
SEG19
COM2
SEG18
COM2
SEG17
COM2
SEG16 xxxx xxxx uuuu uuuu
COM2
SEG7
COM3
SEG6
COM3
SEG5
COM3
SEG4
COM3
SEG3
COM3
SEG2
COM3
SEG1
COM3
SEG0
COM3
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
SEG15
COM3
SEG14
COM3
SEG13
COM3
SEG12
COM3
SEG11
COM3
SEG10
COM3
SEG9
COM3
SEG8
COM3
SEG23
COM3
SEG22
COM3
SEG21
COM3
SEG20
COM3
SEG19
COM3
SEG18
COM3
SEG17
COM3
SEG16 xxxx xxxx uuuu uuuu
COM3
7ACh
—
Unimplemented
—
—
7EFh
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
DS41364A-page 46
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 2-13: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Banks 16-30
x00h/
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
x80h(2)
x00h/
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
x81h(2)
x02h/
PCL
Program Counter (PC) Least Significant Byte
x82h(2)
x03h/
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
x83h(2)
x04h/
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
x84h(2)
x05h/
x85h(2)
x06h/
x86h(2)
x07h/
x87h(2)
x08h/
—
—
—
BSR4
BSR3
BSR2
BSR1
INTF
BSR0
IOCIF
x88h(2)
x09h/
WREG
PCLATH
INTCON
—
Working Register
x89h(2)
x0Ah/
—
Write Buffer for the upper 7 bits of the Program Counter
PEIE TMR0IE INTE IOCIE TMR0IF
x8Ah(1),(2)
x0Bh/
GIE
x8Bh(2)
x0Ch/
x8Ch
—
Unimplemented
—
—
x1Fh/
x9Fh
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 47
PIC16F193X/LF193X
TABLE 2-13: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 31
F80h(2)
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
F81h(2)
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
F82h(2)
F83h(2)
F84h(2)
F85h(2)
F86h(2)
F87h(2)
F88h(2)
F89h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
—
—
—
BSR4
BSR3
BSR2
BSR1
BSR0
WREG
Working Register
F8Ah(1),(2 PCLATH
—
Write Buffer for the upper 7 bits of the Program Counter
)
F8Bh(2)
INTCON
—
GIE
PEIE TMR0IE INTE IOCIE TMR0IF
INTF
DC
IOCIF
C
0000 000x 0000 000u
F8Ch
—
FE3h
Unimplemented
—
—
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
STATUS_
Z
---- -xxx ---- -uuu
xxxx xxxx uuuu uuuu
---x xxxx ---u uuuu
-xxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
SHAD
WREG_
SHAD
BSR_
Working Register Normal (Non-ICD) Shadow
Bank Select Register Normal (Non-ICD) Shadow
Program Counter Latch High Register Normal (Non-ICD) Shadow
Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow
Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow
Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow
Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow
Unimplemented
SHAD
PCLATH_
SHAD
FSR0L_
SHAD
FSR0H_
SHAD
FSR1L_
SHAD
FSR1H_
SHAD
FECh
FEDh
FEEh
FEFh
—
—
—
—
—
—
Current Stack pointer
---1 1111 ---1 1111
xxxx xxxx uuuu uuuu
-xxx xxxx -uuu uuuu
STKPTR
TOSL
Top of Stack Low byte
Top of Stack High byte
—
TOSH
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
2: These registers can be addressed from any bank.
3: These registers/bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
DS41364A-page 48
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
2.2.3
CORE REGISTERS
The core registers contain the registers that directly
affect the basic operation of the PIC16F193X/LF193X.
These registers are listed below:
• INDF0
• INDF1
• PCL
• STATUS
• FSR0 Low
• FSR0 High
• FSR1 Low
• FSR1 High
• BSR
• WREG
• PCLATH
• INTCON
Note:
The core registers are the first 12
addresses of every data memory bank.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 49
PIC16F193X/LF193X
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u= unchanged).
2.2.3.1
STATUS Register
The STATUS register, shown in Register 2-1, contains:
• the arithmetic status of the ALU
• the Reset status
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 26.0
“Instruction Set Summary”).
• the bank select bits for data memory (SRAM)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: The C and DC bits operate as Borrow and
Digit Borrow out bits, respectively, in
subtraction.
REGISTER 2-1:
STATUS: STATUS REGISTER
U-0
—
U-0
—
U-0
—
R-1/q
TO
R-1/q
PD
R/W-x/x
Z
R/W-x/x
DC(1)
R/W-x/x
C(1)
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-5
bit 4
Unimplemented: Read as ‘0’
TO: Time-out bit
1= After power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
bit 3
bit 2
bit 1
bit 0
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)(1)
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
DS41364A-page 50
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
2.2.3.2
OPTION register
The OPTION register, shown in Register 2-2, is a
readable and writable register, which contains various
control bits to configure:
• External INT interrupt
• Timer0
• Weak pull-ups
REGISTER 2-2:
OPTION_REG: OPTION REGISTER
R/W-1/1
WPUEN
bit 7
R/W-1/1
INTEDG
R/W-1/1
T0CS
R/W-1/1
T0SE
R/W-1/1
PSA
R/W-1/1
PS2
R/W-1/1
PS1
R/W-1/1
PS0
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
WPUEN: Weak Pull-up Enable bit
1= All weak pull-ups are disabled (except MCLR, if it is enabled)
0= Weak pull-ups are enabled by individual WPUx latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
T0CS: Timer0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (FOSC/4)
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is inactive and has no effect on the Timer0 interrupt rate
0= Prescaler is active and affects the Timer0 interrupt rate
PS<2:0>: Prescaler Rate Select bits
Bit Value
Timer0 Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 51
PIC16F193X/LF193X
2.3.3
COMPUTED FUNCTION CALLS
2.3
PCL and PCLATH
A computed function CALLallows programs to maintain
tables of functions and provide another way to execute
state machines or look-up tables. When performing a
table read using a computed function CALL, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block).
The Program Counter (PC) is 15 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<14:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 2-4 shows the five
situations for the loading of the PC.
If using the CALLinstruction, the PCH<2:0> and PCL
registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.
FIGURE 2-4:
LOADING OF PC IN
DIFFERENT SITUATIONS
The CALLWinstruction enables computed calls by com-
bining PCLATH and W to form the destination address.
A computed CALLWis accomplished by loading the W
register with the desired address and executing CALLW.
The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.
14
0
Instruction with
PCL as
Destination
PCH
PCL
PC
8
7
6
0
ALU Result
PCLATH
14
0
PCH
PCL
2.3.4
BRANCHING
GOTO, CALL
PC
The branching instructions add an offset to the PC.
This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
crossed.
4
11
6
0
0
PCLATH
OPCODE <10:0>
14
0
PCH
PCL
CALLW
PC
7
8
6
W
PCLATH
If using BRW, load the W register with the desired
unsigned address and execute BRW. The entire PC will
be loaded with the address PC + 1 + W.
14
0
0
PCH
PCH
PCL
BRW
PC
If using BRA, the entire PC will be loaded with PC + 1 +,
the signed value of the operand of the BRAinstruction.
15
PC + W
14
PCL
2.4
Stack
BRA
PC
All devices have a 16-level x 15-bit wide hardware
stack (refer to Figures 2-1 and 2-3). The stack space is
not part of either program or data space. The PC is
PUSHed onto the stack when CALLor CALLWinstruc-
tions are executed or an interrupt causes a branch. The
stack is POPed in the event of a RETURN, RETLWor a
RETFIEinstruction execution. PCLATH is not affected
by a PUSH or POP operation.
15
PC + OPCODE <8:0>
2.3.1
MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program Coun-
ter PC<14:8> bits (PCH) to be replaced by the contents
of the PCLATH register. This allows the entire contents
of the program counter to be changed by writing the
desired upper 7 bits to the PCLATH register. When the
lower 8 bits are written to the PCL register, all 15 bits of
the program counter will change to the values con-
tained in the PCLATH register and those being written
to the PCL register.
The stack operates as a circular buffer, if the STVREN
bit = 0 (Configuration Word 2). This means that after
the stack has been PUSHed sixteen times, the seven-
teenth PUSH overwrites the value that was stored from
the first PUSH. The eighteenth PUSH overwrites the
second PUSH (and so on).
Note 1: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, CALLW, RETURN, RETLW and
RETFIE instructions or the vectoring to
an interrupt address.
2.3.2
COMPUTED GOTO
A computed GOTOis accomplished by adding an offset to
the program counter (ADDWF PCL). When performing a
table read using a computed GOTOmethod, care should
be exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to the Application
Note AN556, “Implementing a Table Read” (DS00556).
DS41364A-page 52
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
2.4.1
ACCESSING THE STACK
2.5
Indirect Addressing, INDF and
FSR Registers
The stack is available through the TOSH, TOSL and
STKPTR registers. STKPTR is the current value of the
Stack Pointer. TOSH:TOSL register pair points to the
TOP of the stack. Both registers are read/writable. TOS
is split into TOSH and TOSL due to the 15-bit size of the
PC. To access the stack, adjust the value of STKPTR,
which will position TOSH:TOSL, then read/write to
TOSH:TOSL. STKPTR is 5 bits to allow detection of
overflow and underflow.
The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.
During normal program operation, CALL, CALLWand
Interrupts will increment STKPTR while RETURN and
RETFIEwill decrement STKPTR. At any time STKPTR
can be inspected to see how much stack is left. The
STKPTR always points at the currently used place on
the stack. Therefore, a CALL or CALLW will write the
PC and then increment the STKPTR, and a return will
decrement the PC and then unload the PC.
The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:
• Traditional Data Memory
• Linear Data Memory
• Program Flash Memory
2.4.2
OVERFLOW/UNDERFLOW RESET
If the STVREN bit in Configuration Word 2 is
programmed, the device will be reset if the stack is
PUSHed beyond the sixteenth level or POPed beyond
the first level, setting the appropriate bits (STKOVF or
STKUNF, respectively) in the PCON register.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 53
PIC16F193X/LF193X
FIGURE 2-5:
INDIRECT ADDRESSING
0x0000
0x0000
Traditional
Data Memory
0x0FFF
0x0FFF
0x1000
0x1FFF
0x2000
Reserved
Linear
Data Memory
0x29AF
0x29B0
Reserved
0x0000
FSR
Address
Range
0x7FFF
0x8000
Program
Flash Memory
0x7FFF
0xFFFF
Note:
Not all memory regions are completely implemented. Consult device memory tables for
memory limits.
DS41364A-page 54
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
2.5.1
TRADITIONAL DATA MEMORY
The traditional data memory is a region from FSR
address 0x000 to FSR address 0xFFF. The addresses
correspond to the absolute addresses of all SFR, GPR
and common registers.
FIGURE 2-6:
TRADITIONAL DATA MEMORY MAP
Direct Addressing
From Opcode
Indirect Addressing
4
BSR
6
7
FSRxH
0
7
FSRxL
0
0
0
0
0
0
0
Location Select
Bank Select
Bank Select
Location Select
0000 0001 0010
1111
0x00
0x7F
Bank 0 Bank 1 Bank 2
Bank 31
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 55
PIC16F193X/LF193X
2.5.2
LINEAR DATA MEMORY
2.5.3
PROGRAM FLASH MEMORY
The linear data memory is the region from FSR
address 0x2000 to FSR address 0x29AF. This region is
a virtual region that points back to the 80-byte blocks of
GPR memory in all the banks.
To make constant data access easier, the entire
program Flash memory is mapped to the upper half of
the FSR address space. When the MSB of FSRnH is
set, the lower 15 bits are the address in program
memory which will be accessed through INDF. Only the
lower 8 bits of each memory location is accessible via
INDF. Writing to the program Flash memory cannot be
accomplished via the FSR/INDF interface. All
instructions that access program Flash memory via the
FSR/INDF interface will require one additional
instruction cycle to complete.
Unimplemented memory reads as 0x00. Use of the
linear data memory region allows buffers to be larger
than 80 bytes because incrementing the FSR beyond
one bank will go directly to the GPR memory of the next
bank.
The 16 bytes of common memory are not included in
the linear data memory region.
FIGURE 2-8:
PROGRAM FLASH
MEMORY MAP
FIGURE 2-7:
LINEAR DATA MEMORY
MAP
7
7
0
0
FSRnH
FSRnL
7
1
7
0
0
FSRnH
FSRnL
0
0 1
Location Select
0x8000
0x0000
Location Select
0x2000
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
0x120
Program
Flash
Memory
(low 8
bits)
Bank 2
0x16F
0xF20
Bank 30
0x7FFF
0xFFFF
0xF6F
0x29AF
DS41364A-page 56
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
Most registers are not affected by a WDT wake-up
since this is viewed as the resumption of normal
operation. TO and PD bits are set or cleared differently
in different Reset situations, as indicated in Table 3-6.
These bits are used in software to determine the nature
of the Reset.
3.0
RESETS
The PIC16F193X/LF193X differentiates between
various kinds of Reset:
a) Power-on Reset (POR)
b) WDT Reset during normal operation
c) MCLR Reset
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
d) Brown-out Reset (BOR)
e) RESETinstruction
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 28.0 “Electrical
Specifications” for pulse width specifications.
f) Stack Overflow
g) Stack Underflow
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:
• Power-on Reset (POR)
• MCLR Reset
• WDT Reset
• Brown-out Reset (BOR)
FIGURE 3-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack Full/Underflow Reset
Stack
Pointer
External Reset
MCLRE
MCLR
Sleep
WDT
Time-out
VDD Rise
Detect
POR Pulse
VDD
Brown-out
Reset
S
BOR
Enable
OST/PWRT
OST
(2)
1024 Cycles
Chip_Reset
10-bit Ripple Counter
R
Q
OSC1
(2)
64 ms
PWRT
LFINTOSC
11-bit Ripple Counter
Enable PWRT
(1)
Enable OST
Note 1: See Table 3-5 for time-out situations.
2: PWRT and OST counters are reset by POR and BOR.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 57
PIC16F193X/LF193X
TABLE 3-1:
STATUS BITS AND THEIR SIGNIFICANCE
STKOVF STKUNF RMCLR
RI
POR
BOR
TO
PD
Condition
0
0
0
0
u
u
u
u
u
u
1
u
0
0
0
0
u
u
u
u
u
u
u
1
1
1
1
1
u
u
u
0
0
u
u
u
1
1
1
1
u
u
u
u
u
0
u
u
0
0
0
u
u
u
u
u
u
u
u
u
x
x
x
0
u
u
u
u
u
u
u
u
1
0
x
1
0
0
1
u
1
u
u
u
1
x
0
1
u
0
0
u
0
u
u
u
Power-on Reset or LDO Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up from Sleep
Interrupt Wake-up from Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
RESETInstruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
TABLE 3-2:
RESET CONDITION FOR SPECIAL REGISTERS(2)
Program
STATUS
Register
PCON
Register
Condition
Counter
Power-on Reset
0000h
---1 1000
---u uuuu
00-- 110x
uu-- 0uuu
MCLR Reset during normal operation
0000h
MCLR Reset during Sleep
WDT Reset
0000h
0000h
---1 0uuu
---0 uuuu
---0 0uuu
---1 1uuu
---1 0uuu
---u uuuu
---u uuuu
---u uuuu
uu-- 0uuu
uu-- uuuu
uu-- uuuu
00-- 11u0
uu-- uuuu
uu-- u0uu
1u-- uuuu
u1-- uuuu
WDT Wake-up from Sleep
Brown-out Reset
PC + 1
0000h
Interrupt Wake-up from Sleep
RESETInstruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
PC + 1(1)
0000h
0000h
0000h
Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
2: If a Status bit is not implemented, that bit will be read as ‘0’.
DS41364A-page 58
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
3.1
MCLR
The PIC16F193X/LF193X has a noise filter in the
MCLR Reset path. The filter will detect and ignore
small pulses.
3.3
Power-up Timer (PWRT)
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from the WDT
oscillator. For more information, see Section 8.5
“Internal Clock Modes”. The chip is kept in Reset as
long as PWRT is active. The PWRT delay allows the
VDD to rise to an acceptable level. A Configuration bit,
PWRTE, can disable (if set) or enable (if cleared or pro-
grammed) the Power-up Timer. The Power-up Timer
should be enabled when Brown-out Reset is enabled,
although it is not required.
It should be noted that a Reset does not drive the
MCLR pin low.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to VDD. The use of an RC
network, as shown in Figure 3-2, is suggested.
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
MCLRE = 0, the Reset signal to the chip is generated
internally. When the MCLRE = 1, the RE3/MCLR pin
becomes an external Reset input. In this mode, the
RE3/MCLR pin has a weak pull-up to VDD. In-Circuit
Serial Programming is not affected by selecting the
internal MCLR option.
The Power-up Timer delay will vary from chip-to-chip
and vary due to:
• VDD variation
• Temperature variation
• Process variation
Low-voltage programming (LVP) mode will override
MCLRE.
See DC parameters for details (Section 28.0
“Electrical Specifications”).
Note:
The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word.
FIGURE 3-2:
RECOMMENDED MCLR
CIRCUIT
3.4
Watchdog Timer (WDT)
VDD
R1
The WDT has the following features:
• Independent prescaler from Timer0
PIC® MCU
10 kΩ
• Time-out period is from 1.024 ms to 268 seconds,
typical
MCLR
• Enabled by Configuration bits WDTE<1:0>
• Can be disabled during Sleep
C1
0.1 μF
• Controlled by WDTCON register
WDT is cleared under certain conditions described in
Table 3-3.
3.4.1
WDT OSCILLATOR
The WDT derives its time base from the 31 kHz internal
oscillator.
3.2
Power-on Reset (POR)
The on-chip POR circuit holds the chip in Reset until VDD
has reached a high enough level for proper operation. A
maximum rise time for VDD is required. See
Section 28.0 “Electrical Specifications” for details. If
the BOR is enabled, the maximum rise time specification
does not apply. The BOR circuitry will keep the device in
Reset until VDD reaches VBOR (see Section 3.5
“Brown-Out Reset (BOR)”).
Note:
When the Oscillator Start-up Timer (OST)
is invoked, the WDT is held in Reset.
When the OST count has expired, the
WDT will begin counting (if enabled).
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 59
PIC16F193X/LF193X
3.4.2
WDT CONTROL
The WDTE<1:0> bits are located in the Configuration
Word Register 1. When set to ‘11’, the WDT runs
continuously. When entering Sleep the WDT is always
cleared. When set to ‘10’, the WDT is enabled while
running, and disabled during Sleep. When ‘01’ the
WDT is under control of the SWDTEN bit, and when
‘00’ the WDT is always disabled.
The WDTCON register contains the SWDTEN bit and
WDTPS<4:0> bits. When the WDTE<1:0> bits in the
Configuration Word 1 register are anything but ‘01’, the
SWDTEN bit has no effect. When WDTE = 01, the
SWDTEN bit can be used to enable and disable the
WDT. Setting the bit will enable the WDT and clearing
the bit will disable the WDT.
The WDTPS<4:0> bits control the prescaler. See
Register 3-1. The Reset value of WDTCON gives a
nominal WDT interval of ~2s. Upon Reset, the
SWDTEN value will leave the WDT disabled if
WDTE<1:0> is ‘01’ in the Configuration Word. The
prescaler will always be cleared on a Reset.
FIGURE 3-3:
WATCHDOG TIMER BLOCK DIAGRAM
WDTE<1:0> = 00
23-bit Programmable
Prescaler WDT
LFINTOSC
WDT Time-out
WDTE<1:0> = 01
SWDTEN
WDTPS<4:0>
WDTE<1:0> = 11
WDTE<1:0> = 10
Sleep
TABLE 3-3:
WDT STATUS
Conditions
WDT
Cleared
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDTCommand
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
Cleared until the end of OST
Unaffected
Change INTOSC divider (IRCF bits)
DS41364A-page 60
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
REGISTER 3-1:
WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
—
U-0
—
R/W-0/0
R/W-1/1
R/W-0/0
R/W-1/1
R/W-1/1
R/W-0/0
WDTPS4
WDTPS3
WDTPS2
WDTPS1
WDTPS0
SWDTEN
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-1
Unimplemented: Read as ‘0’
WDTPS<4:0>: Watchdog Timer Period Select bits
Bit Value = Prescale Rate
00000 = 1:32 (Interval 1 ms typ)
00001 = 1:64 (Interval 2 ms typ)
00010 = 1:128 (Interval 4 ms typ)
00011 = 1:256 (Interval 8 ms typ)
00100 = 1:512 (Interval 16 ms typ)
00101 = 1:1024 (Interval 32 ms typ)
00110 = 1:2048 (Interval 64 ms typ)
00111 = 1:4096 (Interval 128 ms typ)
01000 = 1:8192 (Interval 256 ms typ)
01001 = 1:16384 (Interval 512 ms typ)
01010 = 1:32768 (Interval 1s typ)
01011 = 1:65536 (Interval 2s typ) (Reset value)
01100 = 1:131072 (217) (Interval 4s typ)
01101 = 1:262144 (218) (Interval 8s typ)
01110 = 1:524288 (219) (Interval 16s typ)
01111 = 1:1048576 (220) (Interval 32s typ)
10000 = 1:2097152 (221) (Interval 64s typ)
10001 = 1:4194304 (222) (Interval 128s typ)
10010 = 1:8388608 (223) (Interval 256s typ)
10011 = Reserved. Results in minimum interval (1:32)
•
•
•
11111 = Reserved. Results in minimum interval (1:32)
bit 0
SWDTEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 00:
This bit is ignored.
If WDTE<1:0> = 01:
1= WDT is turned on
0= WDT is turned off
If WDTE<1:0> = 1x:
This bit is ignored.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 61
PIC16F193X/LF193X
Sleep. When BOREN = 01, the BOR is controlled by
the SBOREN bit of the BORCON register. When
BOREN = 00, the BOR is disabled.
3.5
Brown-Out Reset (BOR)
Brown-out Reset is enabled by programming the
BOREN<1:0> bits in the Configuration register. The
brown-out trip point is selectable from two trip points
via the BORV bit in the Configuration register.
If VDD falls below VBOR for greater than parameter
(TBOR) (see Section 28.0 “Electrical Specifica-
tions”), the Brown-out situation will reset the device.
This will occur regardless of VDD slew rate. A Reset is
not ensured to occur if VDD falls below VBOR for more
than parameter (TBOR).
Between the POR and BOR, complete voltage range
coverage for execution protection can be imple-
mented.
Two bits are used to enable the BOR. When
BOREN = 11, the BOR is always enabled. When
BOREN = 10, the BOR is enabled, but disabled during
If VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above VBOR, the Power-up Timer will execute a
64 ms Reset.
TABLE 3-4:
BOREN
BOR OPERATING MODES
Device
Device
Operation upon
SBOREN
Device Mode
BOR Mode
Operation upon
release of POR
Config bits
wake- up from
Sleep
BOR_ON (11)
BOR_NSLEEP (10)
BOR_NSLEEP (10)
BOR_SBOREN (01)
BOR_SBOREN (01)
BOR_OFF (00)
X
X
X
1
0
X
X
Awake
Sleep
X
Active
Active
Waits for BOR ready(1)
Waits for BOR ready
Disabled
Active
Begins immediately
Begins immediately
Begins immediately
X
Disabled
Disabled
X
Note 1: Even though this case specifically waits for the BOR, the BOR is already operating, so there is no delay in
startup.
FIGURE 3-4:
BROWN-OUT SITUATIONS
VDD
VBOR
Internal
Reset
(1)
64 ms
VDD
VBOR
Internal
Reset
< 64 ms
(1)
64 ms
VDD
VBOR
Internal
Reset
(1)
64 ms
Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.
DS41364A-page 62
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
REGISTER 3-2:
BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-1/u
SBOREN
bit 7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-q/u
BORRDY
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
SBOREN: Software Brown-out Reset Enable bit
If BOREN ≠ 01:
SBOREN is read/write, but has no effect on the BOR.
If BOREN = 01:
1= BOR Enabled
0= BOR Disabled
bit 6-1
bit 0
Unimplemented: Read as ‘0’
BORRDY: Brown-out Reset Circuit Ready Status bit
1= The Brown-out Reset circuit is active and armed
0= The Brown-out Reset circuit is disabled or is warming up
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 63
PIC16F193X/LF193X
3.5.1
BOR HIBERNATE/REARM
The BOR circuit has an output that feeds into the POR
circuit and rearms the POR within the operating range
of the BOR. This early rearming of the POR ensures
that the device will remain in Reset in the event that
VDD falls below the operating range of the BOR
circuitry.
3.6
Reset Instruction
A RESETinstruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Table 3-6
for default conditions after a RESET instruction has
occurred.
3.7
Stack Overflow/Underflow
Device Resets on Stack Overflow and Stack Underflow
conditions are enabled by setting the STVREN bit in
Configuration Word 2. When STVREN is set, an overflow
or underflow condition will set the appropriate STKOVF
or STKUNF bit in the PCON register and then cause a
device Reset. When STVREN is cleared, an overflow or
underflow condition will set the appropriate STKOVF or
STKUNF bit, but not cause a device Reset. The STKOVF
or STKUNF bit is cleared by user software or a Power-on
Reset.
3.8
Power-Up Time-out Sequence
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR or BOR has
expired, then OST is activated after the PWRT time-out
has expired. The total time-out will vary based on oscil-
lator configuration and PWRTE bit status. For example,
in EC mode with PWRTE bit = 1 (PWRT disabled),
there will be no time out at all. Figure 3-5, Figure 3-6
and Figure 3-7 depict time-out sequences.
Since the time outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then,
bringing MCLR high will begin execution immediately
(see Figure 3-6). This is useful for testing purposes or
to synchronize more than one PIC16F193X/LF193X
device operating in parallel.
Table 3-7 shows the Reset conditions for some special
registers.
DS41364A-page 64
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
The PCON register also controls the software enable of
the BOR.
3.9
Power Control (PCON) Register
The Power Control (PCON) register has six Status bits
to indicate what type of Reset that last occurred.
The PCON register bits are shown in Register 3-3.
3.9.1
PCON REGISTER
The Power Control (PCON) register contains flag bits
(refer to Table 3-6) to differentiate between a:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Reset Instruction Reset (RI)
• Stack Overflow Reset (STKOVF)
• Stack Underflow Reset (STKUVF)
REGISTER 3-3:
PCON: POWER CONTROL REGISTER
R/W-0/q
STKOVF
R/W-0/q
STKUNF
U-0
—
U-0
—
R/W-1/q
RMCLR
R/W-1/q
RI
R/W-q/u
POR
R/W-q/u
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
STKOVF: Stack Overflow Flag bit
1= A Stack Overflow occurred (more CALLs than fit on the stack)
0= A Stack Overflow has not occurred or set to ‘0’ by firmware
STKUNF: Stack Underflow Flag bit
1= A Stack Underflow occurred (more RETURNs than CALLs)
0= A Stack Underflow has not occurred or set to ‘0’ by firmware
bit 5-4
bit 3
Unimplemented: Read as ‘0’
RMCLR: MCLR Reset Flag bit
1= A MCLR Reset has not occurred or set to ‘1’ by firmware
0= A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs)
bit 2
bit 1
bit 0
RI: RESETInstruction Flag bit
1= A RESETinstruction has not been executed or set to ‘1’ by firmware
0= A RESETinstruction has been executed (set to ‘0’ in hardware upon executing a RESETinstruction)
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 65
PIC16F193X/LF193X
TABLE 3-5:
TIME-OUT IN VARIOUS SITUATIONS
Power-up and Brown-out Reset
Wake-up from Sleep
or Oscillator Switch
Oscillator Configuration
PWRTE = 0
PWRTE = 1
64 ms + 1024 • TOSC
1024 • TOSC
1024 • TOSC
XT, HS, LP
External RC
EC
64 ms
64 ms
64 ms
—
—
—
—
INTOSC
1 μs
1 μs
Note 1: LP mode with T1OSC disabled.
TABLE 3-6:
RESET BITS AND THEIR SIGNIFICANCE
STKOVF STKUNF RMCLR
RI
POR
BOR
TO
PD
Condition
0
0
0
0
0
u
u
u
u
u
u
u
1
1
1
1
1
u
u
u
0
0
u
u
u
1
1
1
u
u
u
u
u
u
0
u
u
0
0
0
u
u
u
u
u
u
u
u
u
x
x
x
0
u
u
u
u
u
u
u
u
1
0
x
1
0
0
1
u
1
u
u
u
1
x
0
1
u
0
0
u
0
u
u
u
Power-on Reset
Illegal, TO is set on POR
0
0
Illegal, PD is set on POR
0
Brown-out Reset
u
WDT Reset
u
WDT Wake-up from Sleep
Interrupt Wake-up from Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
RESETinstruction executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
u
u
u
u
1
u
Legend:
u= unchanged, x= unknown
FIGURE 3-5:
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
OST Time-out
Internal Reset
TOST
DS41364A-page 66
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 3-6:
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
OST Time-out
Internal Reset
TOST
FIGURE 3-7:
TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
OST Time-out
Internal Reset
TOST
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 67
PIC16F193X/LF193X
TABLE 3-7:
RESET CONDITION FOR SPECIAL REGISTERS(2)
Program
Counter
STATUS
Register
PCON
Register
Condition
Power-on Reset
0000h
0000h
---1 1000
---u uuuu
00-- 110x
uu-- 0uuu
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Reset
0000h
0000h
---1 0uuu
---0 uuuu
---0 0uuu
---1 1uuu
---1 0uuu
uu-- 0uuu
uu-- uuuu
uu-- uuuu
00-- 11u0
uu-- uuuu
uu-- u0uu
WDT Wake-up from Sleep
Brown-out Reset
PC + 1
0000h
PC + 1(1)
Interrupt Wake-up from Sleep
RESETInstruction Executed
0000h
0000h
0000h
---u uuuu
---u uuuu
---u uuuu
1u-- uuuu
u1-- uuuu
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with
the interrupt vector (0004h) after execution of PC + 1.
2: If a Status bit is not implemented, that bit will be read as ‘0’.
TABLE 3-8:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BORCON SBOREN
—
—
—
—
—
—
—
RMCLR
PD
—
RI
Z
—
POR
DC
BORRDY
BOR
63
65
50
61
PCON
STKOVF STKUNF
STATUS
WDTCON
—
—
—
—
TO
C
WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN
Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’, q= value depends on condition.
Shaded cells are not used by Resets.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
DS41364A-page 68
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
• Timer0 Overflow Interrupt
• Timer1 Gate Interrupt
4.0
INTERRUPTS
The PIC16F193X/LF193X device family features an
interruptible core, allowing certain events to preempt
normal program flow. An Interrupt Service Routine
(ISR) is used to determine the source of the interrupt
and act accordingly. Some interrupts can be configured
to wake the MCU from Sleep mode.
• Timer1 Overflow Interrupt
• Timer2 Match with PR2 Interrupt
• Timer4 Match with PR4 Interrupt
• Timer6 Match with PR6 Interrupt
• Comparator C1 Interrupt
• Comparator C2 Interrupt
• CCP1 Event Interrupt
The PIC16F193X/LF193X device family has 23 inter-
rupt sources, differentiated by corresponding interrupt
enable and flag bits:
• CCP2 Event Interrupt
• External Edge Detect on INT Pin Interrupt
• Interrupt-on-Change Interrupt
• A/D Conversion Complete Interrupt
• EEPROM Write Complete Interrupt
• EUSART Receive Interrupt
• CCP3 Event Interrupt
• CCP4 Event Interrupt
• CCP5 Event Interrupt
• MSSP Event Interrupt
• MSSP Bus Collision Interrupt
• EUSART Transmit Interrupt
• LCD Module Interrupt
A block diagram of the interrupt logic is shown in
Figure 4-1.
• Oscillator Fail Interrupt
FIGURE 4-1:
INTERRUPT LOGIC
Wake-up (If in Sleep mode)
TMR0IF
TMR0IE
INTF
INTE
Interrupt to CPU
IOCIF
IOCIE
From Peripheral Interrupt
Logic (Figure 4-2)
PEIE
GIE
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 69
PIC16F193X/LF193X
FIGURE 4-2:
PERIPHERAL INTERRUPT LOGIC
TMR1GIF
TMR1GIE
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
•
•
•
•
•
•
CCP5IF
CCP5IE
OSFIF
OSFIE
TMR1IF
TMR1IE
To Interrupt Logic
(Figure 4-1)
•
•
•
•
•
•
TMR6IF
TMR6IE
C2IF
C2IE
C1IF
C1IE
EEIF
EEIE
BCLIF
BCLIE
LCDIF
LCDIE
DS41364A-page 70
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
4.1
Operation
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
• GIE bit of the INTCON register
• Interrupt Enable bit(s) for the specific interrupt
event(s)
• PEIE bit of the INTCON register (if the Interrupt
Enable bit of the interrupt event is contained in the
PIE1, PIE2 and PIE3 registers)
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
The INTCON, PIR1, PIR2 and PIR3 registers record
individual interrupts via interrupt flag bits. Interrupt flag
bits will be set, regardless of the status of the GIE, PEIE
and individual interrupt enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
4.2
Interrupt Latency
• Current Program Counter (PC) is pushed onto the
stack
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is 3 or 4 instruction cycles. For asynchronous
interrupts, the latency is 3 to 5 instruction cycles,
depending on when the interrupt occurs. See Figure 4-3
for timing details.
• PC is loaded with the interrupt vector 0004h
The ISR determines the source of the interrupt by
polling the interrupt flag bits. The interrupt flag bits must
be cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
FIGURE 4-3:
INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(3)
CLKOUT
(4)
INT pin
(1)
(1)
(2)
(5)
Interrupt Latency
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC + 1
—
0004h
0005h
PC
Inst (PC)
PC + 1
Instruction
Fetched
Inst (PC + 1)
Inst (0004h)
Inst (0005h)
Inst (0004h)
Instruction
Executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC – 1)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 28.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 71
PIC16F193X/LF193X
4.3
Interrupts During Sleep
4.5
Context Saving
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the shadow registers:
• W register
• STATUS register (except for TO and PD)
• BSR register
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEPinstruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to the Section 24.0
“Power-Down Mode (Sleep)” for more details.
• FSR registers
• PCLATH register
Upon exit from the Interrupt Service Routine, these reg-
isters are automatically restored. Any modifications to
these registers during the ISR will be lost. Depending
on the user’s application, other registers may also need
to be saved.
4.4
INT Pin
The external interrupt, INT pin, causes an
asynchronous, edge-triggered interrupt. The INTEDG bit
of the OPTION register determines on which edge the
interrupt will occur. When the INTEDG bit is set, the
rising edge will cause the interrupt. When the INTEDG
bit is clear, the falling edge will cause the interrupt. The
INTF bit of the INTCON register will be set when a valid
edge appears on the INT pin. If the GIE and INTE bits
are also set, the processor will redirect program
execution to the interrupt vector. This interrupt is
disabled by clearing the INTE bit of the INTCON register.
DS41364A-page 72
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
4.5.1
INTCON REGISTER
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, interrupt-on-change and
external INT pin interrupts.
REGISTER 4-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0/0
GIE
R/W-0/0
PEIE
R/W-0/0
TMR0IE
R/W-0/0
INTE
R/W-0/0
IOCIE
R/W-0/0
TMR0IF(1)
R/W-0/0
INTF
R-0/0
IOCIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
GIE: Global Interrupt Enable bit
1= Enables all unmasked interrupts
0= Disables all interrupts
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PEIE: Peripheral Interrupt Enable bit
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
TMR0IE: Timer0 Overflow Interrupt Enable bit
1= Enables the Timer0 interrupt
0= Disables the Timer0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1= Enables the RB0/INT external interrupt
0= Disables the RB0/INT external interrupt
IOCIE: Interrupt-on-Change Enable bit(1)
1= Enables the interrupt-on-change
0= Disables the interrupt-on-change
TMR0IF: Timer0 Overflow Interrupt Flag bit(2)
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: INT External Interrupt Flag bit
1= The INT external interrupt occurred (must be cleared in software)
0= The INT external interrupt did not occur
IOCIF: Interrupt-on-Change Interrupt Flag bit
1= When at least one of the interrupt-on-change pins changed state (must be cleared in software)
0= None of the interrupt-on-change pins have changed state
Note 1: TMR0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before
clearing TMR0IF bit.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 73
PIC16F193X/LF193X
4.5.2
PIE1 REGISTER
The PIE1 register contains the interrupt enable bits, as
shown in Register 4-2.
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 4-2:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0/0
TMR1GIE
bit 7
R/W-0/0
ADIE
R/W-0/0
RCIE
R/W-0/0
TXIE
R/W-0/0
SSPIE
R/W-0/0
CCP1IE
R/W-0/0
TMR2IE
R/W-0/0
TMR1IE
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR1GIE: Timer1 Gate Interrupt Enable bit
1= Enable the Timer1 Gate Acquisition complete interrupt
0= Disable the Timer1 Gate Acquisition complete interrupt
ADIE: A/D Converter (ADC) Interrupt Enable bit
1= Enables the ADC interrupt
0= Disables the ADC interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit
1= Enables the SSP interrupt
0= Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the Timer2 to PR2 match interrupt
0= Disables the Timer2 to PR2 match interrupt
TMR1IE: Timer1 Overflow Interrupt Enable bit
1= Enables the Timer1 overflow interrupt
0= Disables the Timer1 overflow interrupt
DS41364A-page 74
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
4.5.3
PIE2 REGISTER
The PIE2 register contains the interrupt enable bits, as
shown in Register 4-3.
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 4-3:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0/0
OSFIE
bit 7
R/W-0/0
C2IE
R/W-0/0
C1IE
R/W-0/0
EEIE
R/W-0/0
BCLIE
R/W-0/0
LCDIE
U-0
—
R/W-0/0
CCP2IE
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
OSFIE: Oscillator Fail Interrupt Enable bit
1= Enables the Oscillator Fail interrupt
0= Disables the Oscillator Fail interrupt
C2IE: Comparator C2 Interrupt Enable bit
1= Enables the Comparator C2 interrupt
0= Disables the Comparator C2 interrupt
C1IE: Comparator C1 Interrupt Enable bit
1= Enables the Comparator C1 interrupt
0= Disables the Comparator C1 interrupt
EEIE: EEPROM Write Completion Interrupt Enable bit
1= Enables the EEPROM Write Completion interrupt
0= Disables the EEPROM Write Completion interrupt
BCLIE: MSSP Bus Collision Interrupt Enable bit
1= Enables the MSSP Bus Collision Interrupt
0= Disables the MSSP Bus Collision Interrupt
LCDIE: LCD Module Interrupt Enable bit
1= Enables the LCD module interrupt
0= Disables the LCD module interrupt
bit 1
bit 0
Unimplemented: Read as ‘0’
CCP2IE: CCP2 Interrupt Enable bit
1= Enables the CCP2 interrupt
0= Disables the CCP2 interrupt
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 75
PIC16F193X/LF193X
4.5.4
PIE3 REGISTER
The PIE3 register contains the interrupt enable bits, as
shown in Register 4-4.
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 4-4:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0
—
R/W-0/0
CCP5IE
R/W-0/0
CCP4IE
R/W-0/0
CCP3IE
R/W-0/0
TMR6IE
U-0
—
R/W-0/0
TMR4IE
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
Unimplemented: Read as ‘0’
CCP5IE: CCP5 Interrupt Enable bit
1= Enables the CCP5 interrupt
0= Disables the CCP5 interrupt
bit 5
bit 4
bit 3
CCP4IE: CCP4 Interrupt Enable bit
1= Enables the CCP4 interrupt
0= Disables the CCP4 interrupt
CCP3IE: CCP3 Interrupt Enable bit
1= Enables the CCP3 interrupt
0= Disables the CCP3 interrupt
TMR6IE: TMR6 to PR6 Match Interrupt Enable bit
1= Enables the TMR6 to PR6 Match interrupt
0= Disables the TMR6 to PR6 Match interrupt
bit 2
bit 1
Unimplemented: Read as ‘0’
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1= Enables the TMR4 to PR4 Match interrupt
0= Disables the TMR4 to PR4 Match interrupt
bit 0
Unimplemented: Read as ‘0’
DS41364A-page 76
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
4.5.5
PIR1 REGISTER
The PIR1 register contains the interrupt flag bits, as
shown in Register 4-5.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 4-5:
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0/0
TMR1GIF
bit 7
R/W-0/0
ADIF
R-0/0
RCIF
R-0/0
TXIF
R/W-0/0
SSPIF
R/W-0/0
CCP1IF
R/W-0/0
TMR2IF
R/W-0/0
TMR1IF
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
TMR1GIF: Timer1 Gate Interrupt Flag bit
1= Timer1 Gate is inactive
0= Timer1 Gate is active
ADIF: A/D Converter Interrupt Flag bit
1= A/D conversion complete (must be cleared in software)
0= A/D conversion has not completed or has not been started
RCIF: USART Receive Interrupt Flag bit
1= The USART receive buffer is full (cleared by reading RCREG)
0= The USART receive buffer is not full
TXIF: USART Transmit Interrupt Flag bit
1= The USART transmit buffer is empty (cleared by writing to TXREG)
0= The USART transmit buffer is full
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1= The Transmission/Reception is complete (must be cleared in software)
0= Waiting to Transmit/Receive
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
bit 0
TMR2IF: Timer2 to PR2 Interrupt Flag bit
1= A Timer2 to PR2 match occurred (must be cleared in software)
0= No Timer2 to PR2 match occurred
TMR1IF: Timer1 Overflow Interrupt Flag bit
1= The TMR1 register overflowed (must be cleared in software)
0= The TMR1 register did not overflow
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 77
PIC16F193X/LF193X
4.5.6
PIR2 REGISTER
The PIR2 register contains the interrupt flag bits, as
shown in Register 4-6.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 4-6:
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0/0
OSFIF
R/W-0/0
C2IF
R/W-0/0
C1IF
R/W-0/0
EEIF
R/W-0/0
BCLIF
R/W-0/0
LCDIF
U-0
—
R/W-0/0
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
OSFIF: Oscillator Fail Interrupt Flag
1= System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0= No oscillator failure has been detected
C2IF: Comparator C2 Interrupt Flag
1= An enabled edge was detected on Comparator C2 (must be cleared in software)
0= No enabled edge was detected on Comparator C2
C1IF: Comparator C1 Interrupt Flag
1= An enabled edge was detected on Comparator C1 (must be cleared in software)
0= No enabled edge was detected on Comparator C1
EEIF: EEPROM Write Completion Interrupt Flag bit
1= The EEPROM Write operation has completed (must be cleared in software)
0= The EEPROM Write operation has not completed or has not been started
BCLIF: MSSP Bus Collision Interrupt Flag bit
1= A Bus Collision was detected (must be cleared in software)
0= No Bus collision was detected
LCDIF: LCD Module Interrupt Flag bit
1= The LCD module has completed displaying a frame (must be cleared in software).
0= The LCD module has not completed displaying a frame
bit 1
bit 0
Unimplemented: Read as ‘0’
CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare Mode
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM Mode
Unused in this mode
DS41364A-page 78
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
4.5.7
PIR3 REGISTER
The PIR3 register contains the interrupt enable bits, as
shown in Register 4-7.
REGISTER 4-7:
PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3
R/W-0/0
R/W-0/0
CCP5IF
R/W-0/0
CCP4IF
R/W-0/0
CCP3IF
R/W-0/0
TMR6IF
R/W-0/0
—
R/W-0/0
TMR4IF
R/W-0/0
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
Unimplemented: Read as ‘0’
CCP5IF: CCP5 Interrupt Flag bit
Capture Mode
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare Mode
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 5
bit 4
bit 3
CCP4IF: CCP4 Interrupt Flag bit
Capture Mode
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare Mode
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM Mode
Unused in this mode
CCP3IF: CCP3 Interrupt Flag bit
Capture Mode
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare Mode
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM Mode
Unused in this mode
TMR6IF: TMR6 to PR6 Match Interrupt Flag bit
1= TMR6 to PR6 post-scaled match occurred (must be cleared in software)
0= No TMR6 to PR6 match occurred
bit 2
bit 1
Unimplemented: Read as ‘0’
TMR4IF: TMR4 to PR4 Match Interrupt Flag bit
1= TMR4 to PR4 post-scaled match occurred (must be cleared in software)
0= No TMR4 to PR4 match occurred
bit 0
Unimplemented: Read as ‘0’
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 79
PIC16F193X/LF193X
TABLE 4-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
PEIE
TMR0IE
T0CS
RCIE
INTE
T0SE
TXIE
EEIE
IOCIE
PSA
TMR0IF
PS2
INTF
PS1
IOCIF
PS0
73
51
74
75
76
77
78
79
OPTION_REG WPUEN INTEDG
PIE1
PIE2
PIE3
PIR1
PIR2
PIR3
TMR1GIE
OSFIE
—
ADIE
C2IE
SSPIE
BCLIE
CCP1IE TMR2IE TMR1IE
C1IE
LCDIE
—
—
CCP2IE
—
CCP5IE CCP4IE CCP3IE TMR6IE
TMR4IE
TMR1GIF
OSFIF
—
ADIF
C2IF
RCIF
C1IF
TXIF
EEIF
SSPIF
BCLIF
CCP1IF TMR2IF TMR1IF
LCDIF
—
—
CCP2IF
—
CCP5IF CCP4IF CCP3IF TMR6IF
TMR4IF
Legend: x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
Interrupts.
DS41364A-page 80
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
5.0
LOW DROPOUT (LDO)
VOLTAGE REGULATOR
The PIC16F193X devices differ from the PIC16LF193X
devices due to an internal Low Dropout (LDO) voltage
regulator. The PIC16F193X contain an internal LDO,
while the PIC16LF193X do not.
The lithography of the die allows a maximum operating
voltage of 3.6V on the internal digital logic. In order to
continue to support 5.0V designs, a LDO voltage
regulator is integrated on the die. The LDO voltage
regulator allows for the internal digital logic to operate
at 3.2V, while I/O’s operate at 5.0V (VDD).
The LDO voltage regulator requires an external bypass
capacitor for stability. One of three pins, denoted as
VCAP, can be configured for the external bypass
capacitor. It is recommended that the capacitor be a
ceramic cap between 0.1 to 1.0 µF.
On power-up, the external capacitor will look like a
large load on the LDO voltage regulator. To prevent
erroneous operation, the device is held in Reset while
a constant current source charges the external
capacitor. After the cap is fully charged, the device is
released from Reset. For more information, refer to
Section 28.0 “Electrical Specifications”.
See Configuration Word 2 register (Register 10-2) for
VCAP enable bits.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 81
PIC16F193X/LF193X
NOTES:
DS41364A-page 82
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
6.0
I/O PORTS
Depending on the device selected and peripherals
enabled, there are up to five ports available. In general,
when a peripheral is enabled, that pin may not be used
as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRISx registers (data direction register)
• PORTx registers (reads the levels on the pins of
the device)
• LATx registers (output latch)
The Data Latch (LATx registers) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
Ports with analog functions also have an ANSELx
register which can disable the digital input and save
power. A simplified model of a generic I/O port, without
the interfaces to other peripherals, is shown in
Figure 6-1.
FIGURE 6-1:
GENERIC I/O PORT
OPERATION
Read LATx
TRISx
D
Q
Write LATx
Write PORTx
CK
Data Register
VDD
Data Bus
I/O pin
Read PORTx
To peripherals
VSS
ANSELx
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 83
PIC16F193X/LF193X
These bits have no effect on the values of any TRIS
register. PORT and TRIS overrides will be routed to the
correct pin. The unselected pin will be unaffected.
6.1
Alternate Pin Function
The Alternate Pin Function Control (APFCON) register
is used to steer specific peripheral input and output
functions between different pins. The APFCON register
is shown in Register 6-1. For this device family, the
following functions can be moved between different
pins.
• SS (Slave Select)
• CCP2
• CCP3
• Timer1 Gate
• SR Latch SRNQ output
• Comparator C2 output
REGISTER 6-1:
APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
U-0
—
R/W-0/0
R/W-0/0
T1GSEL
R/W-0/0
P2BSEL
R/W-0/0
R/W-0/0
R/W-0/0
SSSEL
R/W-0/0
CCP3SEL
SRNQSEL
C2OUTSEL
CCP2SEL
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
Unimplemented: Read as ‘0’.
CCP3SEL: CCP3 Input/Output Pin Selection bit
For 28-Pin Devices (PIC16F1933/1936/1938):
0= CCP3/P3A function is on RC6/TX/CK/CCP3/P3A/SEG9
1= CCP3/P3A function is on RB5/AN13/CPS5/CCP3/P3A/T1G/COM1
For 40-Pin Devices (PIC16F1934/1937/1939):
0= CCP3/P3A function is on RE0/AN5/CCP3/P3A/SEG21
1= CCP3/P3A function is on RB5/AN13/CPS5/CCP3/P3A/T1G/COM1
bit 5
bit 4
T1GSEL: Timer1 Gate Input Pin Selection bit
0= T1G function is on RB5/AN13/CPS5/CCP3/P3A/T1G/COM1
1= T1G function is on RC4/SDI/SDA/T1G/SEG11
P2BSEL: CCP2 PWM B Output Pin Selection bit
For 28-Pin Devices (PIC16F1933/1936/1938):
0= P2B function is on RC0/T1OSO/T1CKI/P2B
1= P2B function is on RB5/AN13/P2B/CPS5/T1G/COM1
For 40-Pin Devices (PIC16F1934/1937/1939):
0= P2B function is on RC0/T1OSO/T1CKI/P2B
1= P2B function is on RD2/CPS10/P2B
bit 3
bit 2
bit 1
bit 0
SRNQSEL: SR Latch nQ Output Pin Selection bit
0= SRnQ function is on RA5/AN4/C2OUT/SRnQ/SS/CPS7/SEG5/VCAP
1= SRnQ function is on RA0/AN0/C12IN0-/C2OUT/SRnQ/SS/SEG12/VCAP
C2OUTSEL: Comparator C2 Output Pin Selection bit
0= C2OUT function is on RA5/AN4/C2OUT/SRnQ/SS/CPS7/SEG5/VCAP
1= C2OUT function is on RA0/AN0/C12IN0-/C2OUT/SRnQ/SS/SEG12/VCAP
SSSEL: SS Input Pin Selection bit
0= SS function is on RA5/AN4/C2OUT/SRNQ/SS/CPS7/SEG5/VCAP
1= SS function is on RA0/AN0/C12IN0-/C2OUT/SRNQ/SS/SEG12/VCAP
CCP2SEL: CCP2 Input/Output Pin Selection bit
0= CCP2/P2A function is on RC1/T1OSI/CCP2/P2A
1= CCP2/P2A function is on RB3/AN9/C12IN2-/CPS3/CCP2/P2A/VLCD3
DS41364A-page 84
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TRISA register are maintained set when using them as
analog inputs. I/O pins configured as analog input
always read ‘0’.
6.2
PORTA Registers
PORTA is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register 6-4). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). Example 6-1 shows how to
initialize PORTA.
Note:
The ANSELA register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’.
EXAMPLE 6-1:
INITIALIZING PORTA
BANKSELPORTA
;
CLRF
BANKSELLATA
CLRF LATA
BANKSELANSELA
CLRF ANSELA
BANKSELTRISA
PORTA
;Init PORTA
;Data Latch
;
;
;digital I/O
;
Reading the PORTA register (Register 6-2) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch (LATA).
MOVLW
MOVWF
0Ch
TRISA
;Set RA<3:2> as inputs
;and set RA<7:4,1:0>
;as outputs
The TRISA register (Register 6-4) controls the PORTA
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
REGISTER 6-2:
PORTA: PORTA REGISTER
R/W-x/u
RA7
R/W-x/u
RA6
R/W-x/u
RA5
R/W-x/u
RA4
R/W-x/u
RA3
R/W-x/u
RA2
R/W-x/u
RA1
R/W-x/u
RA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
RA<7:0>: PORTA I/O Value bits(1)
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 6-3:
LATA: PORTA DATA LATCH REGISTER
R/W-x/u
LATA7
R/W-x/u
LATA6
R/W-x/u
LATA5
R/W-x/u
LATA4
R/W-x/u
LATA3
R/W-x/u
LATA2
R/W-x/u
LATA1
R/W-x/u
LATA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
LATA<7:0>: PORTA Output Latch Value bits(1)
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 85
PIC16F193X/LF193X
6.2.1
ANSELA REGISTER
The ANSELA register (Register 6-5) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELA bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
REGISTER 6-4:
TRISA: PORTA TRI-STATE REGISTER
R/W-1/1
TRISA7
bit 7
R/W-1/1
TRISA6
R/W-1/1
TRISA5
R/W-1/1
TRISA4
R/W-1/1
TRISA3
R/W-1/1
TRISA2
R/W-1/1
TRISA1
R/W-1/1
TRISA0
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TRISA<7:0>: PORTA Tri-State Control bit
1= PORTA pin configured as an input (tri-stated)
0= PORTA pin configured as an output
REGISTER 6-5:
ANSELA: PORTA ANALOG SELECT REGISTER
U-0
—
U-0
—
R/W-1/1
ANSA5
R/W-1/1
ANSA4
R/W-1/1
ANSA3
R/W-1/1
ANSA2
R/W-1/1
ANSA1
R/W-1/1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
ANSA<5:0>: Analog Select between Analog or Digital Function on pins RA<5:0>, respectively
0= Digital I/O. Pin is assigned to port or digital special function.
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
DS41364A-page 86
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
RA4
6.2.2
PORTA FUNCTIONS AND OUTPUT
PRIORITIES
1. SEG4 (LCD)
Each PORTA pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are briefly described here. For additional information,
refer to the appropriate section in this data sheet.
2. SRQ (SR Latch)
3. C1OUT (Comparator)
4. CCP5 (CCP), 28-pin only
5. RA4
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the lowest number in
the following lists.
RA5
1. VCAP (enabled by Configuration Word)
2. SEG5 (LCD)
RA0
3. SRNQ (SR Latch)
4. C2OUT (Comparator)
5. RA5
1. VCAP (enabled by Configuration Word)
2. SEG12 (LCD)
3. SRNQ (SR Latch)
4. C2OUT (Comparator)
5. RA0
RA6
1. VCAP (enabled by Configuration Word)
2. OSC2 (enabled by Configuration Word)
3. CLKOUT (enabled by Configuration Word)
4. SEG1 (LCD)
RA1
1. SEG7 (LCD)
2. RA1
5. RA6
RA2
RA7
1. COM2 (LCD)
2. DACOUT (DAC)
3. RA2
1. OSC1/CLKIN (enabled by Configuration Word)
2. SEG2 (LCD)
3. RA7
RA3
1. COM3 (LCD), 28-pin only
2. SEG15 (LCD)
3. RA3
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 87
PIC16F193X/LF193X
TABLE 6-1:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADCON0
ADCON1
ANSELA
—
ADFM
—
CHS4
ADCS2
—
CHS3
ADCS1
ANSA5
CHS2
ADCS0
ANSA4
CHS1
—
CHS0
ADREF
ANSA2
ADON
ADREF0
ANSA0
GO/DONE
ADREF1
ANSA1
137
138
86
ANSA3
APFCON
CM1CON0
CM2CON0
CPSCON0
CPSCON1
—
CCP3SEL T1GSEL
P2BSEL SRNQSEL C2OUTSEL
SSSEL
C1HYS
C2HYS
CCP2SEL
C1SYNC
C2SYNC
T0XCS
84
C1ON
C2ON
CPSON
—
C1OUT
C2OUT
—
C1OE
C2OE
—
C1POL
C2POL
—
—
—
C1SP
C2SP
148
148
180
181
128
153
85
CPSRNG1 CPSRNG0 CPSOUT
—
—
—
CPSCH3
—
CPSCH2
—
CPSCH1
CPSCH0
(1)
CONFIG2
VCAPEN1 VCAPEN0
—
—
—
---
—
DACNSS
LATA0
LMUX0
SE0
DACCON0
LATA
DACEN
LATA7
LCDEN
SE7
DACLPS
LATA6
SLPEN
SE6
DACOE
LATA5
WERR
SE5
---
LATA4
—
DACPSS1 DACPSS0
LATA3
CS1
LATA2
CS0
LATA1
LMUX1
SE1
LCDCON
LCDSE0
LCDSE1
OPTION_REG
PORTA
243
247
247
51
SE4
SE3
SE2
SE15
SE14
SE13
SE12
TMR0SE
RA4
SE11
SE10
SE9
SE8
WPUEN
RA7
INTEDG
RA6
TMR0CS
RA5
PSA
PS2
PS1
PS0
RA3
RA2
RA1
RA0
85
SRCON0
SSPCON1
TRISA
SRLEN
WCOL
TRISA7
SRCLK2
SSPOV
TRISA6
SRCLK1
SSPEN
TRISA5
SRCLK0
CKP
SRQEN
SSPM3
TRISA3
SRNQEN
SSPM2
TRISA2
SRPS
SSPM1
TRISA1
SRPR
SSPM0
TRISA0
122
277
86
TRISA4
Legend:
x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note 1: PIC16F193X only.
DS41364A-page 88
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
6.3.1
WEAK PULL-UPS
6.3
PORTB and TRISB Registers
Each of the PORTB pins has an individually configurable
internal weak pull-up. Control bits WPUB<7:0> enable or
disable each pull-up (see Register 6-8). Each weak
pull-up is automatically turned off when the port pin is
configured as an output. All pull-ups are disabled on a
Power-on Reset by the WPUEN bit of the OPTION
register.
PORTB is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISB
(Register 6-9). Setting a TRISB bit (= 1) will make the
corresponding PORTB pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISB bit (= 0) will make the corresponding
PORTB pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 6-2 shows how to initialize PORTB.
6.3.2
INTERRUPT-ON-CHANGE
All of the PORTB pins are individually configurable as an
interrupt-on-change pin. Control bits IOCB<7:0> enable
or disable the interrupt function for each pin. The
interrupt-on-change feature is disabled on a Power-on
Reset. Reference Section 7.0 “Interrupt-On-Change”
for more information.
Reading the PORTB register (Register 6-6) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch.
The TRISB register (Register 6-9) controls the PORTB
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISB register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’. Example 6-2 shows how to initialize PORTB.
EXAMPLE 6-2:
INITIALIZING PORTB
BANKSEL PORTB
;
CLRF
BANKSEL ANSELB
CLRF ANSELB
BANKSEL TRISB
PORTB
;Init PORTB
;Make RB<7:0> digital
;
MOVLW
B’11110000’ ;Set RB<7:4> as inputs
;and RB<3:0> as outputs
MOVWF
TRISB
;
Note:
The ANSELB register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 89
PIC16F193X/LF193X
REGISTER 6-6:
PORTB: PORTB REGISTER
R/W-x/u
RB7
R/W-x/u
RB6
R/W-x/u
RB5
R/W-x/u
RB4
R/W-x/u
RB3
R/W-x/u
RB2
R/W-x/u
RB1
R/W-x/u
RB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
RB<7:0>: PORTB I/O Pin bit
1= Port pin is > VIH
0= Port pin is < VIL
REGISTER 6-7:
LATB: PORTB DATA LATCH REGISTER
R/W-x/u
LATB7
bit 7
R/W-x/u
LATB6
R/W-x/u
LATB5
R/W-x/u
LATB4
R/W-x/u
LATB3
R/W-x/u
LATB2
R/W-x/u
LATB1
R/W-x/u
LATB0
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
LATB<7:0>: PORTB Output Latch Value bits(1)
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
REGISTER 6-8:
WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1/1
WPUB7
bit 7
R/W-1/1
WPUB6
R/W-1/1
WPUB5
R/W-1/1
WPUB4
R/W-1/1
WPUB3
R/W-1/1
WPUB2
R/W-1/1
WPUB1
R/W-1/1
WPUB0
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
WPUB<7:0>: Weak Pull-up Register bits
1= Pull-up enabled
0= Pull-up disabled
Note 1: Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
DS41364A-page 90
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
6.3.3
ANSELB REGISTER
The ANSELB register (Register 6-10) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELB bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELB bits has no affect on digital
output functions. A pin with TRIS clear and ANSELB set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
REGISTER 6-9:
TRISB: PORTB TRI-STATE REGISTER
R/W-1/1
TRISB7
bit 7
R/W-1/1
TRISB6
R/W-1/1
TRISB5
R/W-1/1
TRISB4
R/W-1/1
TRISB3
R/W-1/1
TRISB2
R/W-1/1
TRISB1
R/W-1/1
TRISB0
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TRISB<7:0>: PORTB Tri-State Control bit
1= PORTB pin configured as an input (tri-stated)
0= PORTB pin configured as an output
REGISTER 6-10: ANSELB: PORTB ANALOG SELECT REGISTER
U-0
—
U-0
—
R/W-1/1
ANSB5
R/W-1/1
ANSB4
R/W-1/1
ANSB3
R/W-1/1
ANSB2
R/W-1/1
ANSB1
R/W-1/1
ANSB0
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
ANSB<5:0>: Analog Select between Analog or Digital Function on Pins RB<5:0>, respectively
0= Digital I/O. Pin is assigned to port or digital special function.
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 91
PIC16F193X/LF193X
RB3
6.3.4
PORTB FUNCTIONS AND OUTPUT
PRIORITIES
1. CCP2/P2A
2. RB3
Each PORTB pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are briefly described here. For additional information,
refer to the appropriate section in this data sheet.
RB4
1. COM0
2. P1D, 28-pin only
3. RB4
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the lowest number in
the following lists.
RB5
RB0
1. COM1
2. P2B, 28-pin only
3. P3A
1. SEG0 (LCD)
2. CCP4, 28-pin only
3. RB0
4. RB5
RB6
RB1
1. ICSPCLK (Programming)
2. ICDCLK (enabled by Configuration Word)
3. SEG14 (LCD)
1. P1C (ECCP1), 28-pin only
2. RB1
RB2
4. RB6
1. P1B (ECCP1), 28-pin only
2. RB2
RB7
1. ICSPDAT (Programming)
2. ICDDAT (enabled by Configuration Word)
3. SEG13 (LCD)
4. RB7
TABLE 6-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADCON0
ANSELB
APFCON
CCPxCON
CPSCON0
CPSCON1
INTCON
IOCBP
—
—
CHS4
—
CHS3
CHS2
ANSB4
P2BSEL
DCxB0
—
CHS1
ANSB3
SRNQSEL
CCPxM3
CPSRNG1
CPSCH3
IOCIE
CHS0
ANSB2
GO/DONE
ANSB1
ADON
ANSB0
CCP2SEL
CCPxM0
T0XCS
CPSCH0
IOCIF
137
91
ANSB5
—
CCP3SEL T1GSEL
C2OUTSEL
CCPxM2
SSSEL
84
PxM1
CPSON
—
PxM0
—
DCxB1
—
CCPxM1
184
180
181
73
CPSRNG0 CPSOUT
—
—
—
CPSCH2
TMR0IF
IOCBP2
IOCBN2
IOCBF2
LATB2
CS0
CPSCH1
INTF
GIE
PEIE
TMR0IE
IOCBP5
IOCBN5
IOCBF5
LATB5
WERR
SE5
INTE
IOCBP7
IOCBN7
IOCBF7
LATB7
LCDEN
SE7
IOCBP6
IOCBN6
IOCBF6
LATB6
SLPEN
SE6
IOCBP4
IOCBN4
IOCBF4
LATB4
—
IOCBP3
IOCBN3
IOCBF3
LATB3
IOCBP1
IOCBN1
IOCBF1
LATB1
LMUX1
SE1
IOCBP0
IOCBN0
IOCBF0
LATB0
104
104
104
90
IOCBN
IOCBF
LATB
LCDCON
LCDSE0
LCDSE1
CS1
LMUX0
SE0
243
247
247
51
SE4
SE3
SE2
SE15
SE14
SE13
SE12
SE11
SE10
SE9
SE8
OPTION_REG WPUEN
INTEDG
RB6
TMR0CS TMR0SE
PSA
RB3
PS2
RB2
PS1
RB1
PS0
RB0
PORTB
T1GCON
TRISB
RB7
RB5
RB4
90
TMR1GE T1GPOL
T1GTM
TRISB5
WPUB5
T1GSPM T1GGO/DONE T1GVAL
T1GSS1
TRISB1
WPUB1
T1GSS0
TRISB0
WPUB0
170
91
TRISB7
WPUB7
TRISB6
WPUB6
TRISB4
WPUB4
TRISB3
WPUB3
TRISB2
WPUB2
WPUB
90
Legend:
x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.
DS41364A-page 92
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
The TRISC register (Register 6-13) controls the PORTC
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISC register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
6.4
PORTC and TRISC Registers
PORTC is
a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISC
(Register 6-13). Setting a TRISC bit (= 1) will make the
corresponding PORTC pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISC bit (= 0) will make the corresponding
PORTC pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 6-3 shows how to initialize PORTC.
EXAMPLE 6-3:
INITIALIZING PORTC
BANKSELPORTC
;
CLRF
BANKSELTRISC
PORTC
;Init PORTC
;
Reading the PORTC register (Register 6-11) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch.
MOVLW
MOVWF
B‘00001100’ ;Set RC<3:2> as inputs
TRISC
;and set RC<7:4,1:0>
;as outputs
The location of the CCP2 function is controlled by the
CCP2SEL bit in the APFCON register (refer to
Register 6-1).
REGISTER 6-11: PORTC: PORTC REGISTER
R/W-x/u
RC7
R/W-x/u
RC6
R/W-x/u
RC5
R/W-x/u
RC4
R/W-x/u
RC3
R/W-x/u
RC2
R/W-x/u
RC1
R/W-x/u
RC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
RC<7:0>: PORTC General Purpose I/O Pin bits
1= Port pin is > VIH
0= Port pin is < VIL
REGISTER 6-12: LATC: PORTC DATA LATCH REGISTER
R/W-x/u
LATC7
R/W-x/u
LATC6
R/W-x/u
LATC5
R/W-x/u
LATC4
R/W-x/u
LATC3
R/W-x/u
LATC2
R/W-x/u
LATC1
R/W-x/u
LATC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
LATC<7:0>: PORTC Output Latch Value bits(1)
Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 93
PIC16F193X/LF193X
REGISTER 6-13: TRISC: PORTC TRI-STATE REGISTER
R/W-1/1
TRISC7
R/W-1/1
TRISC6
R/W-1/1
TRISC5
R/W-1/1
TRISC4
R/W-1/1
TRISC3
R/W-1/1
TRISC2
R/W-1/1
TRISC1
R/W-1/1
TRISC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TRISC<7:0>: PORTC Tri-State Control bits
1= PORTC pin configured as an input (tri-stated)
0= PORTC pin configured as an output
DS41364A-page 94
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
RC5
6.4.1
PORTC FUNCTIONS AND OUTPUT
PRIORITIES
1. SEG10 (LCD)
2. SDL (MSSP)
3. RC5
Each PORTC pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are briefly described here. For additional information,
refer to the appropriate section in this data sheet.
RC6
1. SEG9 (LCD)
2. TX (EUSART)
3. CK (EUSART)
4. P3A (CCP), 28-pin only
5. RC6
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the lowest number in
the following lists.
RC0
1. T1OSO (Timer1 Oscillator)
2. P2B (CCP)
RC7
1. SEG8 (LCD)
2. DT (EUSART)
3. P3B (CCP), 28 pin only
4. RC7
3. RC0
RC1
1. T1OSI (Timer1 Oscillator)
2. P2A (CCP)
3. RC1
RC1
1. SEG3 (LCD)
2. P1A (CCP)
3. RC2
RC3
1. SEG6 (LCD)
2. SCL (MSSP)
3. SCK (MSSP)
4. RC3
RC4
1. SEG11 (LCD)
2. SDA (MSSP)
3. RC4
TABLE 6-3:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APFCON
CCPxCON
LATC
—
CCP3SEL
PxM0
T1GSEL
DCxB1
LATC5
WERR
SE5
P2BSEL SRNQSEL C2OUTSEL
SSSEL
CCPxM1
LATC1
LMUX1
SE1
CCP2SEL
CCPxM0
LATC0
LMUX0
SE0
84
184
93
PxM1
LATC7
LCDEN
SE7
DCxB0
LATC4
—
CCPxM3
LATC3
CS1
CCPxM2
LATC2
CS0
LATC6
SLPEN
SE6
LCDCON
LCDSE0
LCDSE1
243
247
247
93
SE4
SE3
SE2
SE15
SE14
SE13
SE12
SE11
SE10
SE9
SE8
PORTC
RCSTA
RC7
SPEN
WCOL
SMP
RC6
RX9
RC5
SREN
SSPEN
D/A
RC4
CREN
CKP
P
RC3
ADDEN
SSPM3
S
RC2
FERR
SSPM2
R/W
RC1
OERR
SSPM1
UA
RC0
RX9D
223
277
276
169
222
94
SSPCON1
SSPSTAT
T1CON
TXSTA
SSPOV
CKE
SSPM0
BF
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
—
TMR1ON
TX9D
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TRISC1
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC0
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 95
PIC16F193X/LF193X
The TRISD register (Register 6-16) controls the
PORTD pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISD register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read ‘0’.
6.5
PORTD and TRISD Registers
PORTD(1) is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISD
(Register 6-16). Setting a TRISD bit (= 1) will make the
corresponding PORTD pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISD bit (= 0) will make the corresponding
PORTD pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 6-4 shows how to initialize PORTD.
EXAMPLE 6-4:
INITIALIZING PORTD
BANKSELPORTD
;
CLRF
BANKSELANSELD
CLRF ANSELD
BANKSELTRISD
PORTD
;Init PORTD
Reading the PORTD register (Register 6-14) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch.
;Make PORTD digital
;
MOVLW
MOVWF
B‘00001100’ ;Set RD<3:2> as inputs
TRISD
;and set RD<7:4,1:0>
;as outputs
Note 1: PORTD is available on PIC16F1936 and
PIC16F1938 only.
REGISTER 6-14: PORTD: PORTD REGISTER(1)
R/W-x/u
RD7
R/W-x/u
RD6
R/W-x/u
RD5
R/W-x/u
RD4
R/W-x/u
RD3
R/W-x/u
RD2
R/W-x/u
RD1
R/W-x/u
RD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
RD<7:0>: PORTD General Purpose I/O Pin bits
1= Port pin is > VIH
0= Port pin is < VIL
Note 1: PORTD is not implemented on PIC16F1933/1936/1938 devices, read as ‘0’.
REGISTER 6-15: LATD: PORTD DATA LATCH REGISTER
R/W-x/u
LATD7
R/W-x/u
LATD6
R/W-x/u
LATD5
R/W-x/u
LATD4
R/W-x/u
LATD3
R/W-x/u
LATD2
R/W-x/u
LATD1
R/W-x/u
LATD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
LATD<7:0>: PORTD Output Latch Value bits(1,2)
Note 1: Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is
return of actual I/O pin values.
2: PORTD implemented on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only.
DS41364A-page 96
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
6.5.1
ANSELD REGISTER
The ANSELD register (Register 6-17) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELD bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
Note:
The ANSELD register must be initialized
to configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’.
The state of the ANSELD bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
REGISTER 6-16: TRISD: PORTD TRI-STATE REGISTER(1)
R/W-1/1
TRISD7
R/W-1/1
TRISD6
R/W-1/1
TRISD5
R/W-1/1
TRISD4
R/W-1/1
TRISD3
R/W-1/1
TRISD2
R/W-1/1
TRISD1
R/W-1/1
TRISD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TRISD<7:0>: PORTD Tri-State Control bits
1= PORTD pin configured as an input (tri-stated)
0= PORTD pin configured as an output
Note 1: TRISD is not implemented on PIC16F1933/1936/1938 devices, read as ‘0’.
2: PORTD implemented on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only.
REGISTER 6-17: ANSELD: PORTD ANALOG SELECT REGISTER(2)
R/W-1/1
ANSD7
R/W-1/1
ANSD6
R/W-1/1
ANSD5
R/W-1/1
ANSD4
R/W-1/1
ANSD3
R/W-1/1
ANSD2
R/W-1/1
ANSD1
R/W-1/1
ANSD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
ANSD<7:0>: Analog Select between Analog or Digital Function on Pins RD<7:0>, respectively
0= Digital I/O. Pin is assigned to port or digital special function.
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
2: ANSELD register is not implemented on the PIC16F1933/1936/1938. Read as ‘0’.
3: PORTD implemented on PIC16F1934/1937/1939/PIC16LF1934/1937/1939 devices only.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 97
PIC16F193X/LF193X
RD4
6.5.2
PORTD FUNCTIONS AND OUTPUT
PRIORITIES
1. SEG17 (LCD)
2. P2D (CCP)
3. RD4
Each PORTD pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are briefly described here. For additional information,
refer to the appropriate section in this data sheet.
RD5
1. SEG18 (LCD)
2. P1B (CCP)
3. RD5
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the lowest number in
the following lists.
RD6
RD0
1. SEG19 (LCD)
2. P1C (CCP)
3. RD6
1. COM3 (LCD)
2. RD0
RD1
RD7
1. CCP4 (CCP)
2. RD1
1. SEG20 (LCD)
2. P1D (CCP)
3. RD7
RD2
1. P2B (CCP)
2. RD2
RD3
1. SEG16 (LCD)
2. P2C (CCP)
3. RD3
TABLE 6-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD(1)
Registeron
Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELD
CCPxCON
CPSCON0
CPSCON1
LATD
ANSD7
PxM1
CPSON
—
ANSD6
PxM0
—
ANSD5
DCxB1
—
ANSD4
DCxB0
—
ANSD3
ANSD2
ANSD1
ANSD0
CCPxM0
T0XCS
CPSCH0
LATD0
LMUX0
SE16
97
184
180
181
96
CCPxM3
CCPxM2
CCPxM1
CPSRNG1 CPSRNG0 CPSOUT
—
—
—
CPSCH3
LATD3
CS1
CPSCH2
LATD2
CS0
CPSCH1
LATD1
LMUX1
SE17
LATD7
LCDEN
SE23
LATD6
SLPEN
SE22
RD6
LATD5
WERR
SE21
RD5
LATD4
—
LCDCON
LCDSE2
PORTD
243
247
96
SE20
RD4
SE19
SE18
RD7
RD3
RD2
RD1
RD0
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
97
Legend:
x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD.
Note 1: These registers are not implemented on the PIC16F1933/1936/1938 devices, read as ‘0’.
DS41364A-page 98
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
port pins are read, this value is modified and then
written to the PORT data latch. RE3 reads ‘0’ when
MCLRE = 1.
6.6
PORTE and TRISE Registers
PORTE(1) is a 4-bit wide, bidirectional port. The
corresponding data direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISE bit (= 0) will
make the corresponding PORTE pin an output (i.e.,
enable the output driver and put the contents of the
output latch on the selected pin). The exception is RE3,
which is input only and its TRIS bit will always read as
‘1’. Example 6-5 shows how to initialize PORTE.
Note 1: RE<2:0> and TRISE<2:0> pins are
available
on
PIC16F1936
and
PIC16F1938 only.
EXAMPLE 6-5:
INITIALIZING PORTE
BANKSELPORTE
;
CLRF
BANKSELANSELE
CLRF ANSELE
BANKSELTRISE
PORTE
;Init PORTE
;
;digital I/O
;
Reading the PORTE register (Register 6-18) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
MOVLW
MOVWF
B‘00001100’ ;Set RE<3:2> as inputs
TRISE
;and set RE<1:0>
;as outputs
REGISTER 6-18: PORTE: PORTE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R-x/u
RE3
R/W-x/u
RE2(1)
R/W-x/u
RE1(1)
R/W-x/u
RE0(1)
bit 0
bit 7
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
RE<3:0>: PORTE I/O Pin bits(1)
1= Port pin is > VIH
0= Port pin is < VIL
Note 1: RE<2:0> are not implemented on the PIC16F1933/1936/1938. Read as ‘0’.
REGISTER 6-19: LATE: PORTE DATA LATCH REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x/u
LATE3
R/W-x/u
LATE2
R/W-x/u
LATE1
R/W-x/u
LATE0
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
LATE<3:0>: PORTE Output Latch Value bits(1)
Note 1: Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is
return of actual I/O pin values.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 99
PIC16F193X/LF193X
REGISTER 6-20: WPUE: WEAK PULL-UP PORTE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1/1
WPUE3
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3
Unimplemented: Read as ‘0’
WPUE: Weak Pull-up Register bit
1= Pull-up enabled
0= Pull-up disabled
bit 2-0
Unimplemented: Read as ‘0’
Note 1: Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
DS41364A-page 100
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
The TRISE register (Register 6-21) controls the PORTE
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISE register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
6.6.1
ANSELE REGISTER
The ANSELE register (Register 6-22) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELE bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
Note:
The ANSELE register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’.
The state of the ANSELE bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
REGISTER 6-21: TRISE: PORTE TRI-STATE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R-1
R/W-1
R/W-1
R/W-1
(1)
(1)
(1)
TRISE3
TRISE2
TRISE1
TRISE0
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3
Unimplemented: Read as ‘0’
TRISE3: RE3 Port Tri-state Control bit
This bit is always ‘1’ as RE3 is an input only
(1)
bit 2-0
TRISE<2:0>: RE<2:0> Tri-State Control bits
1= PORTE pin configured as an input (tri-stated)
0= PORTE pin configured as an output
Note 1: TRISE<2:0> are not implemented on the PIC16F1933/1936/1938/PIC16LF1933/1936/1938. Read as ‘0’.
REGISTER 6-22: ANSELE: PORTE ANALOG SELECT REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
(2)
(2)
(2)
ANSE2
ANSE1
ANSE0
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’
ANSE<2:0>: Analog Select between Analog or Digital Function on Pins RE<2:0>, respectively
0= Digital I/O. Pin is assigned to port or digital special function.
1= Analog input. Pin is assigned as analog input . Digital input buffer disabled.
(1)
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external
control of the voltage on the pin.
2: ANSELE register is not implemented on the PIC16F1933/1936/1938/PIC16LF1933/1936/1938. Read as ‘0’
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 101
PIC16F193X/LF193X
6.6.2
PORTE FUNCTIONS AND OUTPUT
PRIORITIES
Each PORTE pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are briefly described here. For additional information,
refer to the appropriate section in this data sheet.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the lowest number in
the following lists.
RE0
1. SEG21 (LCD)
2. CCP3/P3A (CCP)
3. RE0
RE1
1. SEG22 (LCD)
2. P3B (CCP)
3. RE1
RE2
1. SEG23 (LCD)
2. CCP5 (CCP)
3. RE2
TABLE 6-5:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE(1)
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
137
ADCON0
ANSELE
CCPxCON
LATE
—
—
CHS4
—
CHS3
—
CHS2
—
CHS1
—
CHS0 GO/DONE ADON
ANSE2 ANSE1 ANSE0
101
184
99
PxM1
—
PxM0
—
DCxB1
—
DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0
—
—
LATE3
CS1
LATE2
CS0
LATE1
LMUX1
SE17
LATE0
LMUX0
SE16
LCDCON
LCDSE2
PORTE
LCDEN
SE23
—
SLPEN
SE22
—
WERR
SE21
—
243
247
SE20
—
SE19
RE3
SE18
RE2
RE1
RE0
99
TRISE
WPUE
—
—
—
—
—
—
—
—
TRISE3 TRISE2
WPUE3
TRISE1
—
TRISE0
—
101
100
—
Legend: x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTE.
Note 1: These registers are not implemented on the PIC16F1933/1936/1938 devices, read as ‘0’.
DS41364A-page 102
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
7.4
Clearing Interrupt Flags
7.0
INTERRUPT-ON-CHANGE
The individual status flags, (IOCBFx bits), can be
cleared by resetting them to zero. If another edge is
detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
regardless of the value actually being written.
The PORTB pins can be configured to operate as
Interrupt-On-Change (IOC) pins. An interrupt can be
generated by detecting a signal that has either a rising
edge or a falling edge. Any individual PORTB pin, or
combination of PORTB pins, can be configured to
generate an interrupt. The interrupt-on-change module
has the following features:
In order to ensure that no detected edge is lost while
clearing flags, only AND operations masking out known
changed bits should be performed. The following
sequence is an example of what should be performed.
• Interrupt-on-Change enable (Master Switch)
• Individual pin configuration
• Rising and falling edge detection
• Individual pin interrupt flags
EXAMPLE 7-1:
MOVLW 0xff
XORWF IOCBF, W
ANDWF IOCBF, F
Figure 7-1 is a block diagram of the IOC module.
7.1
Enabling the Module
To allow individual PORTB pins to generate an interrupt,
the IOCIE bit of the INTCON register must be set. If the
IOCIE bit is disabled, the edge detection on the pin will
still occur, but an interrupt will not be generated.
7.5
Operation in Sleep
The Interrupt-on-change interrupt sequence will wake
the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the IOCBF
register will be updated prior to the first instruction
executed out of Sleep.
7.2
Individual Pin Configuration
For each PORTB pin, a rising edge detector and a falling
edge detector are present. To enable a pin to detect a
rising edge, the associated IOCBPx bit of the IOCBP
register is set. To enable a pin to detect a falling edge,
the associated IOCBNx bit of the IOCBN register is set.
A pin can be configured to detect rising and falling
edges simultaneously by setting both the IOCBPx bit
and the IOCBNx bit of the IOCBP and IOCBN registers,
respectively.
7.3
Interrupt Flags
The IOCBFx bits located in the IOCBF register are
status flags that correspond to the Interrupt-on-change
pins of PORTB. If an expected edge is detected on an
appropriately enabled pin, then the status flag for that pin
will be set, and an interrupt will be generated if the IOCIE
bit is set. The IOCIF bit of the INTCON register reflects
the status of all IOCBFx bits.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 103
PIC16F193X/LF193X
REGISTER 7-1:
IOCBP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER
R/W-0/0
IOCBP7
bit 7
R/W-0/0
IOCBP6
R/W-0/0
IOCBP5
R/W-0/0
IOCBP4
R/W-0/0
IOCBP3
R/W-0/0
IOCBP2
R/W-0/0
IOCBP1
R/W-0/0
IOCBP0
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
IOCBP<7:0>: Interrupt-on-Change Positive Edge Enable bits
1= Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and
interrupt flag will be set upon detecting an edge.
0= Interrupt-on-Change disabled for the associated pin.
REGISTER 7-2:
IOCBN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER
R/W-0/0
IOCBN7
bit 7
R/W-0/0
IOCBN6
R/W-0/0
IOCBN5
R/W-0/0
IOCBN4
R/W-0/0
IOCBN3
R/W-0/0
IOCBN2
R/W-0/0
IOCBN1
R/W-0/0
IOCBN0
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
IOCBN<7:0>: Interrupt-on-Change Negative Edge Enable bits
1= Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and
interrupt flag will be set upon detecting an edge.
0= Interrupt-on-Change disabled for the associated pin.
REGISTER 7-3:
IOCBF: INTERRUPT-ON-CHANGE FLAG REGISTER
R/W-0/0
IOCBF7
bit 7
R/W-0/0
IOCBF6
R/W-0/0
IOCBF5
R/W-0/0
IOCBF4
R/W-0/0
IOCBF3
R/W-0/0
IOCBF2
R/W-0/0
IOCBF1
R/W-0/0
IOCBF0
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
IOCBF<7:0>: Interrupt-on-Change Flag bits
1= An enabled change was detected on the associated pin.
Set when IOCBPx = 1and a rising edge was detected on RBx, or when IOCBNx = 1and a falling
edge was detected on RBx.
0= No change was detected, or the user cleared the detected change.
DS41364A-page 104
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 7-1:
INTERRUPT-ON-CHANGE BLOCK DIAGRAM
IOCIE
IOCBFx
IOCBNx
D
Q
From all other IOCBFx
individual pin detectors
CK
R
IOC Interrupt to
CPU Core
RBx
IOCBPx
D
Q
CK
R
Q2 Clock Cycle
TABLE 7-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELB
INTCON
IOCBF
—
—
ANSB5
ANSB4
INTE
ANSB3
IOCIE
ANSB2
ANSB1
INTF
ANSB0
IOCIF
91
73
GIE
PEIE
TMR0IE
TMR0IF
IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0
IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0
IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
104
104
104
91
IOCBN
IOCBP
TRISB
Legend: x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
Interrupt-on-Change.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 105
PIC16F193X/LF193X
NOTES:
DS41364A-page 106
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
The oscillator module can be configured in one of six
clock modes.
8.0
8.1
OSCILLATOR MODULE (WITH
FAIL-SAFE CLOCK MONITOR)
1. EC – External clock.
2. LP – 32 kHz Low-Power Crystal mode.
Overview
3. XT – Medium Gain Crystal or Ceramic Resonator
Oscillator mode.
The oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing perfor-
mance and minimizing power consumption. Figure 8-1
illustrates a block diagram of the oscillator module.
4. HS – High Gain Crystal or Ceramic Resonator
mode.
5. RC – External Resistor-Capacitor (RC).
6. INTOSC – Internal oscillator.
Clock sources can be configured from external
oscillators, quartz crystal resonators, ceramic resonators
and Resistor-Capacitor (RC) circuits. In addition, the
system clock source can be configured from one of three
internal oscillators, with a choice of speeds selectable via
software. Additional clock features include:
Clock Source modes are configured by the FOSC<2:0>
bits in the Configuration Word Register 1 (CONFIG1).
The internal clock can be generated from two internal
oscillators. The HFINTOSC is
high-frequency oscillator. The MFINTOSC is
calibrated medium-frequency oscillator. The
a
calibrated
a
• Selectable system clock source between external
or internal via software.
LFINTOSC is an uncalibrated low-frequency oscillator.
• Two-Speed Start-up mode, which minimizes
latency between external oscillator start-up and
code execution.
• Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch
automatically to the internal oscillator.
FIGURE 8-1:
SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
External
Oscillator
LP, XT, HS, RC, EC
OSC2
Sleep
4 x PLL
Sleep
OSC1
Timer1
CPU and
Oscillator
T1OSC
FOSC<2:0> = 100
T1OSO
Peripherals
T1OSCEN
Enable
Oscillator
IRCF<3:0>
T1OSI
Internal Oscillator
16 MHz
8 MHz
4 MHz
Internal
Oscillator
Block
16 MHz
Source
2 MHz
1 MHz
Clock
Control
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
16 MHz
(HFINTOSC)
31 kHz
Source
FOSC<2:0> SCS<1:0>
Clock Source Option
for other modules
500 kHz
Source
500 kHz
(MFINTOSC)
31 kHz
31 kHz (LFINTOSC)
WDT, PWRT, Fail-Safe Clock Monitor
Two-Speed Start-up and other modules
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 107
PIC16F193X/LF193X
8.2
Oscillator Control
The Oscillator Control (OSCCON) register (Figure 8-1)
controls the system clock and frequency selection
options. The OSCCON register contains the following
bits:
• Frequency selection bits (IRCF)
• System clock select bits (SCS)
• Software PLL enable bit (SPLLEN)
REGISTER 8-1:
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0/0
SPLLEN
bit 7
R/W-0/0
IRCF3
R/W-1/1
IRCF2
R/W-1/1
IRCF1
R/W-1/1
IRCF0
U-0
—
R/W-0/0
SCS1
R/W-0/0
SCS0
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
SPLLEN: Software PLL Enable bit
If PLLEN = 1:
SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements)
If PLLEN = 0:
1= 4x PLL Is enabled
0 = 4x PLL is disabled
bit 6-3
IRCF<3:0>: Internal Oscillator Frequency Select bits
000x= 31 kHz LF
0010= 31.25 kHz MF
(2)
0011= 31.25 kHz HF
0100= 62.5 kHz MF
0101= 125 kHz MF
0110= 250 kHz MF
0111= 500 kHz MF (default upon Reset)
(2)
1000= 125 kHz HF
1001= 250 kHz HF
1010= 500 kHz HF
(2)
(2)
1011= 1 MHz HF
1100= 2 MHz HF
1101= 4 MHz HF
1110= 8 MHz HF
1111= 16 MHz HF
bit 2
Unimplemented: Read as ‘0’
bit 1-0
SCS<1:0>: System Clock Select bits
1x= Internal oscillator block
01= Timer1 oscillator
00= Clock determined by CONFIG1[FOSC<2:0>].
Note 1: Reset state depends on state of the IESO Configuration bit.
2: Duplicate frequency derived from HFINTOSC.
DS41364A-page 108
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
8.3
Clock Source Modes
8.4
External Clock Modes
Clock Source modes can be classified as external or
internal.
8.4.1 OSCILLATOR START-UP TIMER (OST)
If the oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and
is providing a stable system clock to the oscillator
module.
• External Clock modes rely on external circuitry for
the clock source. Examples are: oscillator mod-
ules (EC mode), quartz crystal resonators or
ceramic resonators (LP, XT and HS modes) and
Resistor-Capacitor (RC) mode circuits.
• Internal clock sources are contained internally
within the oscillator module. The oscillator module
has two internal oscillators: the 16 MHz
High-Frequency Internal Oscillator (HFINTOSC),
500 kHZ (MFINTOSC) and the 31 kHz
Low-Frequency Internal Oscillator (LFINTOSC).
In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 8.6.3
“Timer1 Oscillator Ready (T1OSCR) Bit”).
The system clock can be selected between external or
internal clock sources via the System Clock Select
(SCS) bit of the OSCCON register. See Section 8.6
“Clock Switching” for additional information. When
switching between clock sources, a delay is required to
allow the new clock to stabilize. These oscillator delays
are shown in Table 8-1.
TABLE 8-1:
Switch From
OSCILLATOR SWITCHING DELAYS
Switch To
Frequency
Oscillator Delay
LFINTOSC(1)
MFINTOSC(1)
HFINTOSC(1)
31 kHz
31.25 kHz-500 kHz
31.25 kHz-16 MHz
Sleep/POR
Oscillator Warm-up Delay (TWARM)
Sleep/POR
LFINTOSC
EC, RC(1)
EC, RC(1)
DC – 32 MHz
DC – 32 MHz
2 cycles
1 cycle of each
Timer1 Oscillator
LP, XT, HS(1)
Sleep/POR
32 kHz-20 MHz
1024 Clock Cycles (OST)
MFINTOSC(1)
31.25 kHz-500 kHz
31.25 kHz-16 MHz
Any clock source
2 μs (approx.)
HFINTOSC(1)
Any clock source
Any clock source
PLL inactive
LFINTOSC(1)
Timer1 Oscillator
PLL active
31 kHz
1 cycle of each
32 kHz
1024 Clock Cycles (OST)
2 ms (approx.)
16-32 MHz
Note 1: PLL inactive.
8.4.2
EC MODE
FIGURE 8-2:
EXTERNAL CLOCK (EC)
MODE OPERATION
The External Clock (EC) mode allows an externally
generated logic level as the system clock source. When
operating in this mode, an external clock source is
connected to the OSC1 input. OSC2/CLKOUT is
available for general purpose I/O or CLKOUT.
Figure 8-2 shows the pin connections for EC mode.
OSC1/CLKIN
Clock from
Ext. System
PIC® MCU
FOSC/4 or
(1)
(1)
OSC2/CLKOUT
I/O
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
Note 1: Output depends upon CLKOUTEN bit of the
Configuration Word 1.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 109
PIC16F193X/LF193X
8.4.3
LP, XT, HS MODES
Note 1: Quartz crystal characteristics vary according
to type, package and manufacturer. The
user should consult the manufacturer data
sheets for specifications and recommended
application.
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 8-3). The mode selects a low,
medium or high gain setting of the internal
inverter-amplifier to support various resonator types
and speed.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
is the least of the three modes. This mode is designed to
drive only 32.768 kHz tuning-fork type crystals (watch
crystals).
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.
Analysis and Design” (DS00943)
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting.
• AN949, “Making Your Oscillator Work”
(DS00949)
FIGURE 8-4:
CERAMIC RESONATOR
OPERATION
Figure 8-3 and Figure 8-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
(XT OR HS MODE)
FIGURE 8-3:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
PIC® MCU
OSC1/CLKIN
C1
PIC® MCU
To Internal
Logic
OSC1/CLKIN
(3)
(2)
RP
RF
Sleep
C1
To Internal
Logic
Quartz
Crystal
(2)
OSC2/CLKOUT
(1)
C2
RF
Sleep
RS
Ceramic
Resonator
Note 1: A series resistor (RS) may be required for
OSC2/CLKOUT
(1)
C2
RS
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 MΩ to 10 MΩ).
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level.
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 MΩ to 10 MΩ).
DS41364A-page 110
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
8.4.4
EXTERNAL RC MODE
8.5
Internal Clock Modes
The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required.
The oscillator module has three independent, internal
oscillators that can be configured or selected as the
system clock source.
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
16 MHz. The frequency of the HFINTOSC can
be user-adjusted via software using the
OSCTUNE register (Register 8-3).
The RC circuit connects to OSC1. OSC2/CLKOUT is
available for general purpose I/O or CLKOUT.
Figure 8-5 shows the external RC mode connections.
2. The MFINTOSC (Medium-Frequency Internal
Oscillator) is factory calibrated and operates at
500 kHz. The frequency of the MFINTOSC can
be user-adjusted via software using the
OSCTUNE register (Register 8-3).
FIGURE 8-5:
EXTERNAL RC MODES
VDD
PIC® MCU
REXT
3. The LFINTOSC (Low-Frequency Internal
Oscillator) is uncalibrated and operates at
31 kHz.
OSC1/CLKIN
Internal
Clock
CEXT
VSS
The system clock speed can be selected via software
using the Internal Oscillator Frequency Select bits
IRCF<2:0> of the OSCCON register.
FOSC/4 or
OSC2/CLKOUT
(1)
The system clock can be selected between external or
internal clock sources via the System Clock Selection
(SCS) bits of the OSCCON register. See Section 8.6
“Clock Switching” for more information.
I/O
Recommended values: 10 kΩ ≤ REXT ≤ 100 kΩ, <3V
3 kΩ ≤ REXT ≤ 100 kΩ, 3-5V
CEXT > 20 pF, 2-5V
8.5.1 INTOSC MODE
Note 1: Output depends upon CLKOUTEN bit of the
The INTOSC mode configures the internal oscillators
as the system clock source when the device is
programmed using the oscillator selection or the
FOSC<2:0> bits in the Configuration Word Register 1
(CONFIG1).
Configuration Word 1.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) values
and the operating temperature. Other factors affecting
the oscillator frequency are:
In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT is available for general
purpose I/O or CLKOUT.
• threshold voltage variation
• component tolerances
• packaging variations in capacitance
The user also needs to take into account variation due
to tolerance of external RC components used.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 111
PIC16F193X/LF193X
8.5.2
HFINTOSC
8.5.4
LFINTOSC
The High-Frequency Internal Oscillator (HFINTOSC) is
a factory calibrated 16 MHz internal clock source. The
frequency of the HFINTOSC can be altered via
software using the OSCTUNE register (Register 8-3).
The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source.
The output of the LFINTOSC connects to a postscaler
and multiplexer (see Figure 8-1). Select 31 kHz, via
software, using the IRCF<2:0> bits of the OSCCON
register. See Section 8.5.7 “Frequency Select Bits
(IRCF)” for more information. The LFINTOSC is also the
frequency for the Power-up Timer (PWRT), Watchdog
Timer (WDT) and Fail-Safe Clock Monitor (FSCM).
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 8-1). One of nine
frequencies derived from the HFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 8.5.7 “Frequency
Select Bits (IRCF)” for more information.
The LFINTOSC is enabled by selecting 31 kHz
(IRCF<3:0> bits of the OSCCON register = 000)as the
system clock source (SCS bits of the OSCCON
register = 1x), or when any of the following are
enabled:
The HFINTOSC is enabled by:
• Configure the IRCF<3:0> bits for the desired HF
frequency (see Register 8-1), and
• FOSC<2:0> = 100, or
• Configure the IRCF<3:0> bits for the desired LF
frequency (see Register 8-1), and
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’
• FOSC<2:0> = 100, or
The High Frequency Internal Oscillator Ready bit
(HFIOFR) of the OSCSTAT register indicates when the
HFINTOSC is running and can be utilized.
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’
Peripherals that use the LFINTOSC are:
The High Frequency Internal Oscillator Status Locked
bit (HFIOFL) of the OSCSTAT register indicates when
the HFINTOSC is running within 2% of its final value.
• LCD
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor (FSCM)
The High Frequency Internal Oscillator Status Stable
bit (HFIOFS) of the OSCSTAT register indicates when
the HFINTOSC is running within 0.5% of its final value.
The Low Frequency Internal Oscillator Ready bit
(LFIOFR) of the OSCSTAT register indicates when the
LFINTOSC is running and can be utilized.
8.5.3
The
MFINTOSC
Medium-Frequency
Internal
Oscillator
(MFINTOSC) is a factory calibrated 500 kHz internal
clock source. The frequency of the MFINTOSC can be
altered via software using the OSCTUNE register
(Register 8-3).
The output of the MFINTOSC connects to a postscaler
and multiplexer (see Figure 8-1). One of nine
frequencies derived from the MFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 8.5.7 “Frequency
Select Bits (IRCF)” for more information.
The MFINTOSC is enabled by:
• Configure the IRCF<3:0> bits for the desired HF
frequency (see Register 8-1), and
• FOSC<2:0> = 100, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’
The Medium Frequency Internal Oscillator Ready bit
(MFIOFR) of the OSCSTAT register indicates when the
MFINTOSC is running and can be utilized.
DS41364A-page 112
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
8.5.5
OSCSTAT REGISTER
The OSCSTAT register contains flags that represent
the current status of the oscillators module.
REGISTER 8-2:
OSCSTAT: OSCILLATOR STATUS REGISTER
R-0/q
T1OSCR
bit 7
R-0/q
PLLR
R-q/q
R-0/q
R-0/q
R-q/q
R-0/0
R-0/q
OSTS
HFIOFR
HFIOFL
MFIOFR
LFIOFR
HFIOFS
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
T1OSCR: Timer1 Oscillator Ready bit
If the Timer1 oscillator is enabled (T1OSCEN = 1)
1= Timer1 oscillator is ready and can be switched to
0= Timer1 oscillator is not ready
else Timer1 oscillator is disabled - clock source is T1CKI
1= Timer1 oscillator is always ready
bit 6
bit 5
PLLR 4x PLL Ready bit
1= 4x PLL is ready and can be switched to
0= 4x PLL oscillator is not ready
OSTS: Oscillator Start-up Time-out Status bit
1= Device running from the clock defined by FOSC<3:0> of the CONFIG1 register
0= Device running from the internal oscillator (HFINTOSC, MFINTOSC or LFINTOSC)
bit 4
bit 3
bit 2
bit 1
bit 0
HFIOFR: High Frequency Internal Oscillator Ready bit
1= 16 MHz Internal Oscillator (HFINTOSC) is ready and can be switched to
0= 16 MHz Internal Oscillator (HFINTOSC) is not ready
HFIOFL: High Frequency Internal Oscillator Status Locked bit (2% Stable)
1= 16 MHz Internal Oscillator (HFINTOSC) is in lock
0= 16 MHz Internal Oscillator (HFINTOSC) has not yet locked
MFIOFR: Medium Frequency Internal Oscillator (500 kHz HFINTOSC Output) Ready bit
1= 500 kHz Internal Oscillator (MFINTOSC) is ready and can be switched to
0= 500 kHz Internal Oscillator (MFINTOSC) is not ready
LFIOFR: Low Frequency Internal Oscillator Ready bit
1= 31 kHz Internal Oscillator (LFINTOSC) is ready and can be switched to
0= 31 kHz Internal Oscillator (LFINTOSC) is not ready
HFIOFS: High Frequency Internal Oscillator Stable bit (0.5% Stable)
1= 16 MHz Internal Oscillator (HFINTOSC) is in communications stable
0= 16 MHz Internal Oscillator (HFINTOSC) is not yet communications stable
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 113
PIC16F193X/LF193X
OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
Monitor (FSCM) and peripherals, are not affected by the
change in frequency.
8.5.6
OSCTUNE REGISTER
The HFINTOSC and MFINTOSC are factory calibrated
but can be adjusted in software by writing to the
OSCTUNE register (Register 8-3).
The default value of the OSCTUNE register is ‘0’. The
value is a 5-bit two’s complement number.
When the OSCTUNE register is modified, the oscillator
frequency will begin shifting to the new frequency. Code
execution continues during this shift. There is no
indication that the shift has occurred.
The OSCTUNE register applies the same adjustment to
both
the
HFINTOSC
and
the
MFINTOSC
simultaneously.
REGISTER 8-3:
OSCTUNE: OSCILLATOR TUNING REGISTER
U-0
—
U-0
—
R/W-0/0
TUN5
R/W-0/0
TUN4
R/W-0/0
TUN3
R/W-0/0
TUN2
R/W-0/0
TUN1
R/W-0/0
TUN0
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
TUN<4:0>: Frequency Tuning bits
011111= Maximum frequency
011110=
•
•
•
000001=
000000= Oscillator module is running at the factory-calibrated frequency.
111111=
•
•
•
100000= Minimum frequency
DS41364A-page 114
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
8.5.7
FREQUENCY SELECT BITS (IRCF)
8.5.8
INTERNAL OSCILLATOR CLOCK
SWITCH TIMING
The output of the 16 MHz HFINTOSC and 31 kHz
LFINTOSC connects to a postscaler and multiplexer
(see Figure 8-1). The Internal Oscillator Frequency
Select bits IRCF<2:0> of the OSCCON register select
the frequency output of the internal oscillators. One of
eight frequencies can be selected via software:
When switching between the HFINTOSC, MFINTOSC
and the LFINTOSC, the new oscillator may already be
shut down to save power (see Figure 8-6). If this is the
case, there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC,
MFINTOSC and LFINTOSC oscillators. The sequence
of a frequency selection is as follows:
• 16 MHz
• 8 MHz
• 4 MHz
• 2 MHz
1. IRCF<3:0> bits of the OSCCON register are
modified.
• 1 MHz
• 500 kHz (Default after Reset)
• 250 kHz
2. If the new clock is shut down, a clock start-up
delay is started.
• 125 kHz
3. Clock switch circuitry waits for a falling edge of
the current clock.
• 31 kHz (LFINTOSC)
4. The current clock is held low and the clock
switch circuitry waits for a rising edge in the new
clock.
Note:
Following any Reset, the IRCF<2:0> bits of
the OSCCON register are set to ‘110’ and
the frequency selection is set to 4 MHz.
The user can modify the IRCF bits to
select a different frequency.
5. The new clock is now active.
6. The OSCSTAT register is updated as required.
7. Clock switch is complete.
See Figure 8-6 for more details.
If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected. Clock switching
time delays are shown in Table 8-1.
Start-up delay specifications are located in the
oscillator tables of Section 28.0 “Electrical
Specifications”.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 115
PIC16F193X/LF193X
FIGURE 8-6:
INTERNAL OSCILLATOR SWITCH TIMING
HFINTOSC/
MFINTOSC
LFINTOSC (FSCM and WDT disabled)
HFINTOSC/
MFINTOSC
Start-up Time
2-cycle Sync
Running
LFINTOSC
≠ 0
= 0
IRCF <3:0>
System Clock
HFINTOSC/
MFINTOSC
LFINTOSC (Either FSCM or WDT enabled)
HFINTOSC/
MFINTOSC
2-cycle Sync
Running
LFINTOSC
IRCF <3:0>
≠ 0
= 0
System Clock
LFINTOSC
HFINTOSC/MFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
Running
LFINTOSC
Start-up Time 2-cycle Sync
HFINTOSC/
MFINTOSC
= 0
≠ 0
IRCF <3:0>
System Clock
DS41364A-page 116
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
8.6
Clock Switching
8.7
Two-Speed Clock Start-up Mode
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bits of the OSCCON
register.
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device.
8.6.1
SYSTEM CLOCK SELECT (SCS) BIT
The System Clock Select (SCS) bits of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.
This mode allows the application to wake-up from
Sleep, perform a few instructions using the INTOSC
as the clock source and go back to Sleep without
waiting for the external oscillator to become stable.
• When the SCS bits of the OSCCON register = 00,
the system clock source is determined by
configuration of the FOSC<2:0> bits in the
Configuration Word Register 1 (CONFIG1).
Note:
Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCSTAT register to
remain clear.
• When the SCS bits of the OSCCON register = 01,
the system clock source is the Timer1 oscillator.
• When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bit of the OSCCON register is always
cleared.
When the oscillator module is configured for LP, XT or
HS modes, the Oscillator Start-up Timer (OST) is
enabled (see Section 8.4.1 “Oscillator Start-up
Timer (OST)”). The OST will suspend program execu-
tion until 1024 oscillations are counted. Two-Speed
Start-up mode minimizes the delay in code execution
by operating from the internal oscillator as the OST is
counting. When the OST count reaches 1024 and the
OSTS bit of the OSCSTAT register is set, program exe-
cution switches to the external oscillator.
Note:
Any automatic clock switch, which may
occur from Two-Speed Start-up or Fail-Safe
Clock Monitor, does not update the SCS
bits of the OSCCON register. The user can
monitor the OSTS bit of the OSCSTAT
register to determine the current system
clock source.
8.7.1
TWO-SPEED START-UP MODE
CONFIGURATION
Two-Speed Start-up mode is configured by the
following settings:
8.6.2
OSCILLATOR START-UP TIME-OUT
STATUS (OSTS) BIT
• IESO (of the Configuration Word Register 1) = 1;
Internal/External Switchover bit (Two-Speed
Start-up mode enabled).
The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCSTAT register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<2:0> bits in the Configuration
Word Register 1 (CONFIG1), or from the internal clock
source. In particular, OSTS indicates that the Oscillator
Start-up Timer (OST) has timed out for LP, XT or HS
modes.
• SCS (of the OSCCON register) = 00.
• FOSC<2:0> bits in the Configuration Word
Register 1 (CONFIG1) configured for LP, XT or
HS mode.
Two-Speed Start-up mode is entered after:
• Power-on Reset (POR) and, if enabled, after
Power-up Timer (PWRT) has expired, or
8.6.3
TIMER1 OSCILLATOR READY
(T1OSCR) BIT
• Wake-up from Sleep.
The Timer1 Oscillator Ready (T1OSCR) bit of the
OSCSTAT register indicates whether the Timer1
oscillator is ready to be used. After the T1OSCR bit is
set, the SCS bits can be configured to select the Timer1
oscillator.
If the external clock oscillator is configured to be
anything other than LP, XT or HS mode, then
Two-speed Start-up is disabled. This is because the
external clock oscillator does not require any
stabilization time after POR or an exit from Sleep.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 117
PIC16F193X/LF193X
8.7.2
TWO-SPEED START-UP
SEQUENCE
8.7.3
CHECKING TWO-SPEED CLOCK
STATUS
1. Wake-up from Power-on Reset or Sleep.
Checking the state of the OSTS bit of the OSCSTAT
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in the Configuration Word Register 1
(CONFIG1), or the internal oscillator.
2. Instructions begin execution by the internal
oscillator at the frequency set in the IRCF<3:0>
bits of the OSCCON register.
3. OST enabled to count 1024 clock cycles.
4. OST timed out, wait for falling edge of the
internal oscillator.
5. OSTS is set.
6. System clock held low until the next falling edge
of new clock (LP, XT or HS mode).
7. System clock is switched to external clock
source.
FIGURE 8-7:
TWO-SPEED START-UP
INTOSC
TOST
OSC1
0
1
1022 1023
OSC2
Program Counter
PC - N
PC + 1
PC
System Clock
DS41364A-page 118
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
8.8.3
FAIL-SAFE CONDITION CLEARING
8.8
Fail-Safe Clock Monitor
The Fail-Safe condition is cleared after a Reset,
executing a SLEEPinstruction or changing the SCS bits
of the OSCCON register. When the SCS bits are
changed, the OST is restarted. While the OST is
running, the device continues to operate from the
INTOSC selected in OSCCON. When the OST times
out, the Fail-Safe condition is cleared and the device
will be operating from the external clock source. The
Fail-Safe condition must be cleared before the OSFIF
flag can be cleared.
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue operating should the external oscillator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
Configuration Word Register 1 (CONFIG1). The FSCM
is applicable to all external Oscillator modes (LP, XT,
HS, EC, Timer1 Oscillator and RC).
FIGURE 8-8:
FSCM BLOCK DIAGRAM
8.8.4
RESET OR WAKE-UP FROM SLEEP
Clock Monitor
Latch
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled. Therefore, the device will always be executing
code while the OST is operating.
External
Clock
S
Q
LFINTOSC
Oscillator
÷ 64
R
Q
31 kHz
(~32 μs)
488 Hz
(~2 ms)
Sample Clock
Note:
Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
Status bits in the OSCSTAT register to
verify the oscillator start-up and that the
system clock switchover has successfully
completed.
Clock
Failure
Detected
8.8.1
FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 8-8. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
external clock goes low.
8.8.2
FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.
The internal clock source chosen by the FSCM is
determined by the IRCF<3:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 119
PIC16F193X/LF193X
FIGURE 8-9:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Test
Test
Note:
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
TABLE 8-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page
CONFIG1(2)
OSCCON
CPD
SPLLEN
T1OSCR
—
CP
IRCF3
PLLR
—
MCLRE PWRTE
WDTE
IRCF0
HFIOFL
TUN3
FOSC2
—
FOSC1
SCS1
FOSC0
SCS0
126
108
113
114
75
IRCF2
OSTS
TUN5
C1IE
IRCF1
HFIOFR
TUN4
EEIE
OSCSTAT
OSCTUNE
PIE2
MFIOFR
TUN2
LFIOFR
TUN1
—
HFIOFS
TUN0
OSFIE
OSFIF
C2IE
C2IF
BCLIE
BCLIF
LCDIE
CCP2IE
CCP2IF
TMR1ON
PIR2
C1IF
EEIF
LCDIF
—
78
T1CON
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN
T1SYNC
—
169
Legend: x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
oscillators.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: See Configuration Word Register 1 (Register 10-1) for operation of all register bits.
DS41364A-page 120
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
9.2
Latch Output
9.0
SR LATCH
The SRQEN and SRNQEN bits of the SRCON0 regis-
ter control the Q and Q latch outputs. Both of the SR
latch outputs may be directly output to an I/O pin at the
same time.
The module consists of a single SR Latch with multiple
Set and Reset inputs as well as separate latch outputs.
The SR Latch module includes the following features:
• Programmable input selection
• SR Latch output is available internally/externally
• Separate Q and Q outputs
The applicable TRIS bit of the corresponding port must
be cleared to enable the port pin output driver.
• Firmware Set and Reset
9.3
Effects of a Reset
Upon any device Reset, the SR latch is not initialized.
The user’s firmware is responsible to initialize the latch
output before enabling it to the output pins.
9.1
Latch Operation
The latch is a Set-Reset latch that does not depend on a
clock source. Each of the Set and Reset inputs are
active-high. The latch can be Set or Reset by CxOUT,
SRI pin, or variable clock. Additionally the SRPS and the
SRPR bits of the SRCON0 register may be used to Set
or Reset the SR Latch, respectively. The latch is
Reset-dominant, therefore, if both Set and Reset inputs
are high the latch will go to the Reset state. Both the
SRPS and SRPR bits are self resetting which means
that a single write to either of the bits is all that is
necessary to complete a latch Set or Reset operation.
FIGURE 9-1:
SR LATCH SIMPLIFIED BLOCK DIAGRAM
SRLEN
SRQEN
SRPS
Pulse
(2)
Gen
SRI
S
Q
SRSPE
SRCLK
SRQ
SRSCKE
(3)
SYNCC2OUT
SRSC2E
(3)
SYNCC1OUT
SRSC1E
SR
(1)
Latch
SRPR
Pulse
(2)
Gen
SRI
R
Q
SRRPE
SRCLK
SRNQ
SRRCKE
SRLEN
(3)
SYNCC2OUT
SRNQEN
SRRC2E
(3)
SYNCC1OUT
SRRC1E
Note 1: If R = 1and S = 1simultaneously, Q = 0, Q = 1
2: Pulse generator causes a 1 Q-state pulse width.
3: Name denotes the connection point at the comparator output.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 121
PIC16F193X/LF193X
TABLE 9-1:
SRCLK
SRCLK FREQUENCY TABLE
Divider
FOSC = 32 MHz FOSC = 20 MHz FOSC = 16 MHz FOSC = 4 MHz
FOSC = 1 MHz
111
110
101
100
011
010
001
000
512
256
128
64
32
16
8
62.5 kHz
125 kHz
250 kHz
500 kHz
1 MHz
39.0 kHz
78.1 kHz
156 kHz
313 kHz
625 kHz
1.25 MHz
2.5 MHz
5 MHz
31.3 kHz
62.5 kHz
125 kHz
250 kHz
500 kHz
1 MHz
7.81 kHz
15.6 kHz
31.25 kHz
62.5 kHz
125 kHz
250 kHz
500 kHz
1 MHz
1.95 kHz
3.90 kHz
7.81 kHz
15.6 kHz
31.3 kHz
62.5 kHz
125 kHz
250 kHz
2 MHz
4 MHz
2 MHz
4
8 MHz
4 MHz
REGISTER 9-1:
SRCON0: SR LATCH CONTROL 0 REGISTER
R/W-0/0
SRLEN
bit 7
R/W-0/0
SRCLK2
R/W-0/0
SRCLK1
R/W-0/0
SRCLK0
R/W-0/0
SRQEN
R/W-0/0
R/S-0/0
SRPS
R/S-0/0
SRPR
bit 0
SRNQEN
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
S = Bit is set only -
bit 7
SRLEN: SR Latch Enable bit
1= SR latch is enabled
0= SR latch is disabled
SRCLK<2:0>: SR Latch Clock Divider bits
bit 6-4
000= Generates a 1 FOSC wide pulse every 4th FOSC cycle clock
001= Generates a 1 FOSC wide pulse every 8th FOSC cycle clock
010= Generates a 1 FOSC wide pulse every 16th FOSC cycle clock
011= Generates a 1 FOSC wide pulse every 32th FOSC cycle clock
100= Generates a 1 FOSC wide pulse every 64th FOSC cycle clock
101= Generates a 1 FOSC wide pulse every 128th FOSC cycle clock
110= Generates a 1 FOSC wide pulse every 256th FOSC cycle clock
111= Generates a 1 FOSC wide pulse every 512th FOSC cycle clock
bit 3
bit 2
SRQEN: SR Latch Q Output Enable bit
If SRLEN = 1:
1= Q is present on the SRQ pin
0= Q is internal only
If SRLEN = 0:
SR latch is disabled
SRNQEN: SR Latch Q Output Enable bit
If SRLEN = 1:
1= Q is present on the SRnQ pin
0= Q is internal only
If SRLEN = 0:
SR latch is disabled
bit 1
bit 0
SRPS: Pulse Set Input of the SR Latch bit
1= Pulse input for 1 Q-clock period
0= Do not generate pulse. Always reads back ‘0’.
SRPR: Pulse Reset Input of the SR Latch bit
1= Pulse input for 1 Q-clock period
0= Do not generate pulse. Always reads back ‘0’.
DS41364A-page 122
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
REGISTER 9-2:
SRCON1: SR LATCH CONTROL 1 REGISTER
R/W-0/0
SRSPE
bit 7
R/W-0/0
R/W-0/0
SRSC2E
R/W-0/0
SRSC1E
R/W-0/0
SRRPE
R/W-0/0
R/W-0/0
R/W-0/0
SRSCKE
SRRCKE
SRRC2E
SRRC1E
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SRSPE: SR Latch Peripheral Set Enable bit
1= SRI pin status sets SR Latch
0= SRI pin status has no effect on SR Latch
SRSCKE: SR Latch Set Clock Enable bit
1= Set input of SR latch is pulsed with SRCLK
0= Set input of SR latch is not pulsed with SRCLK
SRSC2E: SR Latch C2 Set Enable bit
1= C2 Comparator output sets SR Latch
0= C2 Comparator output has no effect on SR Latch
SRSC1E: SR Latch C1 Set Enable bit
1= C1 Comparator output sets SR Latch
0= C1 Comparator output has no effect on SR Latch
SRRPE: SR Latch Peripheral Reset Enable bit
1= SRI pin resets SR Latch
0= SRI pin has no effect on SR Latch
SRRCKE: SR Latch Reset Clock Enable bit
1= Reset input of SR latch is pulsed with SRCLK
0= Reset input of SR latch is not pulsed with SRCLK
SRRC2E: SR Latch C2 Reset Enable bit
1= C2 Comparator output resets SR Latch
0= C2 Comparator output has no effect on SR Latch
SRRC1E: SR Latch C1 Reset Enable bit
1= C1 Comparator output resets SR Latch
0= C1 Comparator output has no effect on SR Latch
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 123
PIC16F193X/LF193X
NOTES:
DS41364A-page 124
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
10.0 DEVICE CONFIGURATION
Device Configuration consists of Configuration Word 1
and Configuration Word 2 registers, Code Protection
and Device ID.
10.1 Configuration Words
There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1
register at 8007h and Configuration Word 2 register at
8008h.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 125
PIC16F193X/LF193X
REGISTER 10-1: CONFIGURATION WORD 1
R/P-1/1
FCMEN
R/P-1/1
IESO
R/P-1/1
R/P-1/1
R/P-1/1
R/P-1/1
CPD
R/P-1/1
CP
CLKOUTEN
BOREN1
BOREN0
bit 13
bit 7
bit 0
R/P-1/1
MCLRE
R/P-1/1
PWRTE
R/P-1/1
WDTE1
R/P-1/1
WDTE0
R/P-1/1
FOSC2
R/P-1/1
FOSC1
R/P-1/1
FOSC0
bit 6
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 13
bit 12
bit 11
FCMEN: Fail-Safe Clock Monitor Enable bit
1= Fail-Safe Clock Monitor is enabled
0= Fail-Safe Clock Monitor is disabled
IESO: Internal External Switchover bit
1= Internal/External Switchover mode is enabled
0= Internal/External Switchover mode is disabled
CLKOUTEN: Clock Out Enable bit
1= CLKOUT function is disabled. I/O or oscillator function on RA6/CLKOUT
0= CLKOUT function is enabled on RA6/CLKOUT
(1)
bit 10-9
BOREN<1:0>: Brown-out Reset Enable bits
11= BOR enabled
10= BOR enabled during operation and disabled in Sleep
01= BOR controlled by SBOREN bit of the PCON register
00= BOR disabled
(2)
bit 8
bit 7
bit 6
CPD: Data Code Protection bit
1= Data memory code protection is disabled
0= Data memory code protection is enabled
(3)
CP: Code Protection bit
1= Program memory code protection is disabled
0= Program memory code protection is enabled
MCLRE: RE3/MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1= RE3/MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0= RE3/MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3
bit..
(1)
bit 5
PWRTE: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
bit 4-3
WDTE<1:0>: Watchdog Timer Enable bit
11= WDT enabled
10= WDT enabled while running and disabled in Sleep
01= WDT controlled by the SWDTEN bit in the WDTCON register
00= WDT disabled
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire data EEPROM will be erased when the code protection is turned off during an erase.
3: The entire program memory will be erased when the code protection is turned off.
DS41364A-page 126
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
REGISTER 10-1: CONFIGURATION WORD 1 (CONTINUED)
bit 2-0
FOSC<2:0>: Oscillator Selection bits
111= ECH: External Clock, High-Power mode: CLKIN on RA7/OSC1/CLKIN
110= ECM: External Clock, Medium-Power mode: CLKIN on RA7/OSC1/CLKIN
101= ECL: External Clock, Low-Power mode: CLKIN on RA7/OSC1/CLKIN
100= INTOSC oscillator: I/O function on RA7/OSC1/CLKIN
011= EXTRC oscillator: RC function on RA7/OSC1/CLKIN
010= HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN
001= XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN
000= LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire data EEPROM will be erased when the code protection is turned off during an erase.
3: The entire program memory will be erased when the code protection is turned off.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 127
PIC16F193X/LF193X
REGISTER 10-2: CONFIGURATION WORD 2
R/P-1/1
LVP
R/P-1/1
DEBUG
U-1
—
R/P-1/1
BORV
R/P-1/1
R/P-1/1
PLLEN
U-1
—
STVREN
bit 13
bit 7
bit 0
U-1
—
R/P-1/1
R/P-1/1
U-1
—
U-1
—
R/P-1/1
WRT1
R/P-1/1
WRT0
VCAPEN1
VCAPEN0
bit 6
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
(1)
bit 13
bit 12
LVP: Low-Voltage Programming Enable bit
1= Low-voltage programming enabled
0= High-voltage on MCLR/VPP must be used for programming
DEBUG: In-Circuit Debugger Mode bit
1= In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins
0= In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger
bit 11
bit 10
Unimplemented: Read as ‘1’
BORV: Brown-out Reset Voltage Selection bit
1= Brown-out Reset voltage set to 1.9V
0= Brown-out Reset voltage set to 2.7V
bit 9
bit 8
STVREN: Stack Overflow/Underflow Reset Enable bit
1= Stack Overflow or Underflow will cause a Reset
0= Stack Overflow or Underflow will not cause a Reset
PLLEN: PLL Enable bit
1= 4xPLL enabled
0= 4xPLL disabled
bit 7-6
bit 5-4
Unimplemented: Read as ‘1’
(2)
VCAPEN<1:0>: Voltage Regulator Capacitor Enable bits
00= VCAP functionality is enabled on RA0
01= VCAP functionality is enabled on RA5
10= VCAP functionality is enabled on RA6
11= No capacitor on VCAP pin
bit 3-2
bit 1-0
Unimplemented: Read as ‘1’
WRT<1:0>: Flash Memory Self-Write Protection bits
4 kW FLASH memory (PIC16F1933/PIC16LF1933 and PIC16F1934/PIC16LF1934 only):
11= Write protection off
10= 000h to 1FFh write-protected, 200h to FFFh may be modified by EECON control
01= 000h to 7FFh write-protected, 800h to FFFh may be modified by EECON control
00= 000h to FFFh write-protected, no addresses may be modified by EECON control
8 kW FLASH memory (PIC16F1936/PIC16LF1936 and PIC16F1937/PIC16LF1937 only):
11= Write protection off
10= 000h to 1FFh write-protected, 200h to 1FFFh may be modified by EECON control
01= 000h to FFFh write-protected, 1000h to 1FFFh may be modified by EECON control
00= 000h to 1FFFh write-protected, no addresses may be modified by EECON control
16 kW FLASH memory (PIC16F1938/PIC16LF1938 and PIC16F1939/PIC16LF1939 only):
11= Write protection off
10= 000h to 1FFh write-protected, 200h to 3FFFh may be modified by EECON control
01= 000h to 1FFFh write-protected, 2000h to 3FFFh may be modified by EECON control
00= 000h to 3FFFh write-protected, no addresses may be modified by EECON control
Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
2: Reads as ‘11’ on PIC16LF193X only.
DS41364A-page 128
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
10.2 Code Protection
Code protection is controlled using the CP bit in
Configuration Word 1. When code protection is
enabled, all program memory locations (0000h-7FFFh)
read as all ‘0’. Further programming is disabled for the
program memory (0000h-7FFFh).
Data memory is protected with its own Code-Protect bit
(CPD). When data code protection is enabled (CPD = 0),
all data memory locations read as ‘0’. Further
programming is disabled for the data memory. Data
memory can still be programmed and read during
program execution.
The user ID locations and Configuration Words can be
programmed and read out regardless of the code
protection settings.
10.3 User ID
Four memory locations (8000h-8003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during Program/Verify mode. Only
the Least Significant 7 bits of the ID locations are
reported when using MPLAB® IDE. See the
“PIC16193X/PIC16LF193X Memory Programming
Specification” (DS41360A) for more information.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 129
PIC16F193X/LF193X
NOTES:
DS41364A-page 130
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
11.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result register (ADRES). Figure 11-1 shows the
block diagram of the ADC.
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
FIGURE 11-1:
ADC BLOCK DIAGRAM
ADNREF = 1
VREF-
ADNREF = 0
AVSS
AVDD
ADPREF = 0X
ADPREF = 11
ADPREF = 10
VREF+
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
11101
11110
11111
ADC
10
GO/DONE
0= Left Justify
ADFM
1= Right Justify
ADON
16
ADRESH ADRESL
Temp Sens
VSS
(2)
DAC
FVR Buffer1
CHS<4:0>
Note 1: When ADON = 0, all multiplexer inputs are disconnected.
2: See Section 10.0 “Fixed Voltage Reference” for more information.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 131
PIC16F193X/LF193X
11.1.4
CONVERSION CLOCK
11.1 ADC Configuration
The source of the conversion clock is software select-
able via the ADCS bits of the ADCON1 register. There
are seven possible clock options:
When configuring and using the ADC the following
functions must be considered:
• Port configuration
• FOSC/2
• Channel selection
• FOSC/4
• ADC voltage reference selection
• ADC conversion clock source
• Interrupt control
• FOSC/8
• FOSC/16
• FOSC/32
• Results formatting
• FOSC/64
11.1.1
PORT CONFIGURATION
• FRC (dedicated internal oscillator)
The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the
associated TRIS and ANSEL bits. Refer to Section 6.0
“I/O Ports” for more information.
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11.5 TAD peri-
ods as shown in Figure 11-2.
For correct conversion, the appropriate TAD specifica-
tion must be met. Refer to the A/D conversion require-
ments in Section 28.0 “Electrical Specifications” for
more information. Table 11-1 gives examples of appro-
priate ADC clock selections.
Note:
Analog voltages on any pin that is defined
as a digital input may cause the input buf-
fer to conduct excess current.
Note:
Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
11.1.2
CHANNEL SELECTION
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 11.2
“ADC Operation” for more information.
11.1.3
ADC VOLTAGE REFERENCE
The ADPREF bits of the ADCON1 register provides
control of the positive voltage reference. The positive
voltage reference can be:
• VREF+
• AVDD
• FVR (Fixed Voltage Reference)
The ADNREF bits of the ADCON1 register provides
control of the negative voltage reference. The negative
voltage reference can be:
• VREF-
• AVSS
See Section 14.0 “Fixed Voltage Reference” for
more details on the fixed voltage reference.
DS41364A-page 132
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 11-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
Device Frequency (FOSC)
Device Frequency (FOSC)
ADC Clock Period (TAD)
ADC
ADCS<2:0>
Clock Source
32 MHz
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
(2)
(2)
(2)
(2)
(2)
Fosc/2
Fosc/4
Fosc/8
Fosc/16
Fosc/32
Fosc/64
FRC
000
100
001
101
010
110
x11
62.5ns
125 ns
0.5 μs
100 ns
200 ns
400 ns
125 ns
250 ns
250 ns
500 ns
500 ns
1.0 μs
2.0 μs
4.0 μs
2.0 μs
4.0 μs
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
0.5 μs
1.0 μs
2.0 μs
4.0 μs
8.0 μs
16.0 μs
32.0 μs
64.0 μs
(3)
(3)
(3)
800 ns
1.0 μs
800 ns
1.6 μs
1.0 μs
2.0 μs
(3)
8.0 μs
(3)
(3)
2.0 μs
3.2 μs
4.0 μs
8.0 μs
16.0 μs
(1,4)
(1,4)
(1,4)
(1,4)
(1,4)
(1,4)
1.0-6.0 μs
1.0-6.0 μs
1.0-6.0 μs
1.0-6.0 μs
1.0-6.0 μs
1.0-6.0 μs
Legend:
Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 1.6 μs for VDD.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be
performed during Sleep.
FIGURE 11-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY - TAD
TAD8 TAD9 TAD10 TAD11
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7
b4
b1
b0
b9
b8
b7
b6
b5
b3
b2
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 133
PIC16F193X/LF193X
11.1.5
INTERRUPTS
11.1.6
RESULT FORMATTING
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON1 register controls the output format.
Figure 11-3 shows the two output formats.
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEPinstruc-
tion is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execu-
tion, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the
INTCON register are enabled, execution will switch to
the Interrupt Service Routine.
Please refer to Section 11.1.5 “Interrupts” for more
information.
FIGURE 11-3:
10-BIT A/D CONVERSION RESULT FORMAT
ADRESH
ADRESL
LSB
(ADFM = 0)
MSB
bit 7
bit 0
bit 0
bit 7
bit 7
bit 0
10-bit A/D Result
Unimplemented: Read as ‘0’
(ADFM = 1)
MSB
LSB
bit 0
bit 7
Unimplemented: Read as ‘0’
10-bit A/D Result
DS41364A-page 134
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
11.2.4
ADC OPERATION DURING SLEEP
11.2 ADC Operation
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
11.2.1
STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will start the
Analog-to-Digital conversion.
Note:
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 11.2.6 “A/D Conversion
Procedure”.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conver-
sion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
11.2.2
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF Interrupt Flag bit
11.2.5
SPECIAL EVENT TRIGGER
• Update the ADRESH and ADRESL registers with
new conversion result
The Special Event Trigger of the CCP5 module allows
periodic ADC measurements without software inter-
vention. When this trigger occurs, the GO/DONE bit is
set by hardware and the Timer1 counter resets to zero.
11.2.3
TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRESH and ADRESL registers will be updated with
the partially complete Analog-to-Digital conversion
sample. Incomplete bits will match the last bit
converted.
Using the Special Event Trigger does not assure proper
ADC timing. It is the user’s responsibility to ensure that
the ADC timing requirements are met.
Refer to Section 19.0 “Capture/Compare/PWM Mod-
ules (ECCP1, ECCP2, ECCP3, CCP4, CCP5)” for
more information.
Note:
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 135
PIC16F193X/LF193X
11.2.6
A/D CONVERSION PROCEDURE
EXAMPLE 11-1:
A/D CONVERSION
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
;This code block configures the ADC
;for polling, Vdd reference, Frc clock
;and AN0 input.
;
1. Configure Port:
• Disable pin output driver (Refer to the TRIS
register)
;Conversion start & polling for completion
; are included.
;
• Configure pin as analog (Refer to the ANSEL
register)
BANKSEL
MOVLW
MOVWF
BANKSEL
BSF
BANKSEL
BSF
BANKSEL
MOVLW
MOVWF
CALL
BSF
BTFSC
GOTO
BANKSEL
MOVF
MOVWF
BANKSEL
MOVF
ADCON1
;
B’01110000’ ;ADC Frc clock
ADCON1
TRISA
TRISA,0
ANSEL
ANSEL,0
ADCON0
B’10000001’ ;Right justify,
ADCON0
SampleTime
ADCON0,GO
ADCON0,GO
$-1
2. Configure the ADC module:
• Select ADC conversion clock
• Configure voltage reference
• Select ADC input channel
• Turn on ADC module
;
;
;Set RA0 to input
;
;Set RA0 to analog
;
3. Configure ADC interrupt (optional):
• Clear ADC interrupt flag
;Vdd Vref, AN0, On
;Acquisiton delay
;Start conversion
;Is conversion done?
;No, test again
;
;Read upper 2 bits
;store in GPR space
;
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
ADRESH
4. Wait the required acquisition time(2)
.
ADRESH,W
RESULTHI
ADRESL
ADRESL,W
RESULTLO
5. Start conversion by setting the GO/DONE bit.
6. Wait for ADC conversion to complete by one of
the following:
;Read lower 8 bits
;Store in GPR space
MOVWF
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result.
8. Clear the ADC interrupt flag (required if interrupt
is enabled).
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 11.3 “A/D Acquisition
Requirements”.
DS41364A-page 136
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
11.2.7
ADC REGISTER DEFINITIONS
The following registers are used to control the
operation of the ADC.
REGISTER 11-1: ADCON0: A/D CONTROL REGISTER 0
U-0
—
R/W-0/0
CHS4
R/W-0/0
CHS3
R/W-0/0
CHS2
R/W-0/0
CHS1
R/W-0/0
CHS0
R/W-0/0
R/W-0/0
ADON
GO/DONE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-2
CHS<4:0>: Analog Channel Select bits
00000= AN0
00001= AN1
00010= AN2
00011= AN3
00100= AN4
00101= AN5
00110= AN6
00111= AN7
01000= AN8
01001= AN9
01010= AN10
01011= AN11
01100= AN12
01101= AN13
01110= Reserved. No channel connected.
.
.
.
11100= Reserved. No channel connected.
11101= Temperature Reference from band gap
11110= DAC output (aka CVREF output)
11111=Fixed Voltage Reference (FVR) Buffer 1 Output
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
1= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0= A/D conversion completed/not in progress
ADON: ADC Enable bit
1= ADC is enabled
0= ADC is disabled and consumes no operating current
Note 1: See Section 10.0 “Fixed Voltage Reference” for more information.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 137
PIC16F193X/LF193X
REGISTER 11-2: ADCON1: A/D CONTROL REGISTER 1
R/W-0/0
ADFM
R/W-0/0
ADCS2
R/W-0/0
ADCS1
R/W-0/0
ADCS0
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
ADNREF
ADPREF1
ADPREF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
ADFM: A/D Result Format Select bit
1= Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is
loaded.
0= Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is
loaded.
bit 6-4
ADCS<2:0>: A/D Conversion Clock Select bits
000=FOSC/2
001=FOSC/8
010=FOSC/32
011=FRC (clock supplied from a dedicated RC oscillator)
100=FOSC/4
101=FOSC/16
110=FOSC/64
111=FRC (clock supplied from a dedicated RC oscillator)
bit 3
bit 2
Unimplemented: Read as ‘0’
ADNREF: A/D Negative Voltage Reference Configuration bit
0= VREF- is connected to AVSS
1= VREF- is connected to external VREF-
bit 1-0
ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits
00= VREF+ is connected to AVDD
01= Reserved
10= VREF+ is connected to external VREF+
11= VREF+ is connected to internal fixed voltage reference
REGISTER 11-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES9
ADRES8
ADRES7
ADRES6
ADRES5
ADRES4
ADRES3
ADRES2
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
ADRES<9:2>: ADC Result Register bits
Upper 8 bits of 10-bit conversion result
DS41364A-page 138
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
REGISTER 11-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x/u
R/W-x/u
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
ADRES1
ADRES0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
ADRES<1:0>: ADC Result Register bits
Lower 2 bits of 10-bit conversion result
Reserved: Do not use.
REGISTER 11-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
R/W-x/u
ADRES9
ADRES8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-2
bit 1-0
Reserved: Do not use.
ADRES<9:8>: ADC Result Register bits
Upper 2 bits of 10-bit conversion result
REGISTER 11-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES7
ADRES6
ADRES5
ADRES4
ADRES3
ADRES2
ADRES1
ADRES0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
ADRES<7:0>: ADC Result Register bits
Lower 8 bits of 10-bit conversion result
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 139
PIC16F193X/LF193X
source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
selected (or changed), an A/D acquisition must be
done before the conversion can be started. To calculate
the minimum acquisition time, Equation 11-1 may be
used. This equation assumes that 1/2 LSb error is used
(256 steps for the ADC). The 1/2 LSb error is the
maximum error allowed for the ADC to meet its
specified resolution.
11.3 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 11-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), refer
to Figure 11-4. The maximum recommended
impedance for analog sources is 10 kΩ. As the
EQUATION 11-1: ACQUISITION TIME EXAMPLE
Temperature = 50°C and external impedance of 10kΩ 5.0V VDD
Assumptions:
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
= 2µs + TC + [(Temperature - 25°C)(0.05µs/°C)]
The value for TC can be approximated with the following equations:
1
⎛
⎞
;[1] VCHOLD charged to within 1/2 lsb
VAPPLIED 1 – -------------------------- = VCHOLD
(2n + 1) – 1
⎝
⎠
–TC
---------
⎛
⎞
VAPPLIED 1 – e RC = VCHOLD
⎜
⎝
⎟
⎠
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
–Tc
--------
⎛
⎞
1
VAPPLIED 1 – eRC = VAPPLIED 1 – --------------------------
⎛
⎞
⎠
⎜
⎝
⎟
⎠
(2n + 1) – 1
⎝
Note: Where n = number of bits of the ADC.
Solving for TC:
TC = –CHOLD(RIC + RSS + RS) ln(1/511)
= –10pF(1kΩ + 7kΩ + 10kΩ) ln(0.001957)
= 1.12µs
Therefore:
TACQ = 2ΜS + 1.12ΜS + [(50°C- 25°C)(0.05ΜS/°C)]
= 4.42ΜS
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin
leakage specification.
DS41364A-page 140
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 11-4:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT ≈ 0.6V
ANx
SS
RIC ≤ 1k
Rss
Rs
(1)
CPIN
5 pF
VA
I LEAKAGE
CHOLD = 10 pF
VSS/VREF-
VT ≈ 0.6V
6V
5V
RSS
VDD 4V
3V
Legend:
CHOLD
CPIN
= Sample/Hold Capacitance
= Input Capacitance
2V
I LEAKAGE = Leakage current at the pin due to
various junctions
5 6 7 8 9 1011
Sampling Switch
RIC
RSS
SS
VT
= Interconnect Resistance
= Resistance of Sampling Switch
= Sampling Switch
(kΩ)
= Threshold Voltage
Note 1: Refer to Section 28.0 “Electrical Specifications”.
FIGURE 11-5:
ADC TRANSFER FUNCTION
Full-Scale Range
FFh
FEh
FDh
FCh
FBh
1 LSB ideal
Full-Scale
Transition
04h
03h
02h
01h
00h
Analog Input Voltage
1 LSB ideal
Zero-Scale
Transition
VREF
VSS
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 141
PIC16F193X/LF193X
TABLE 11-2: SUMMARY OF ASSOCIATED ADC REGISTERS
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
137
138
138
139
86
ADCON0
ADCON1
ADRESH
—
CHS4
CHS3
CHS2
CHS1
—
CHS0
GO/DONE
ADON
ADFM
ADCS2
ADCS1
ADCS0
ADNREF ADPREF1 ADPREF0
A/D Result Register High
A/D Result Register Low
ADRESL
ANSELA
ANSELB
ANSELE
CCP2CON
—
—
—
—
ANSA5
ANSB5
—
ANSA4
ANSB4
—
ANSA3
ANSB3
—
ANSA2
ANSB2
ANSE2
CCP1M2
TMR0IF
CCP1IE
CCP1IF
TRISA2
TRISB2
TRISE2
ANSA1
ANSB1
ANSE1
CCP1M1
INTF
ANSA0
ANSB0
ANSE0
CCP1M0
91
—
—
101
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
RBIE
184
73
INTCON
PIE1
GIE
TMR1GIE
TMR1GIF
TRISA7
TRISB7
—
PEIE
ADIE
TMR0IE
RCIE
RCIF
INTE
TXIE
RBIF
SSPIE
SSPIF
TRISA3
TRISB3
TRISE3
TMR2IE
TMR2IF
TRISA1
TRISB1
TRISE1
TMR1IE
TMR1IF
TRISA0
TRISB0
TRISE0
ADFVR0
DACNSS
DACR0
74
PIR1
ADIF
TXIF
77
TRISA
TRISA6
TRISB6
—
TRISA5
TRISB5
—
TRISA4
TRISB4
—
86
TRISB
91
TRISE
101
156
153
153
FVRCON
DACCON0
DACCON1
Legend:
FVREN
DACEN
---
FVRRDY
DACLPS
---
TSEN
DACOE
---
TSRNG
---
CDAFVR1 CDAFVR0 ADFVR1
DACPSS1 DACPSS0
DACR3 DACR2
---
DACR4
DACR1
x= unknown, u= unchanged, —= unimplemented read as ‘0’, q= value depends on condition. Shaded cells are not
used for ADC module.
DS41364A-page 142
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 12-1:
SINGLE COMPARATOR
12.0 COMPARATOR MODULE
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
Comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of program execution. The analog
comparator module includes the following features:
VIN+
VIN-
+
Output
–
VIN-
VIN+
• Independent comparator control
• Programmable input selection
• Comparator output is available internally/externally
• Programmable output polarity
• Interrupt-on-change
Output
• Wake-up from Sleep
• Programmable Speed/Power optimization
• PWM shutdown
Note:
The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
• Programmable and fixed voltage reference
12.1
Comparator Overview
A single comparator is shown in Figure 12-1 along with
the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 143
PIC16F193X/LF193X
FIGURE 12-2:
COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM
CxNCH<1:0>
CxON(1)
2
CxINTP
Interrupt
det
0
CXIN0-
CXIN1-
CXIN2-
CXIN3-
Set CxIF
1
CxINTN
Interrupt
det
MUX
2
(2)
CXPOL
3
CxVN
CxVP
-
CXOUT
To Data Bus
D
Q
Cx(3)
MCXOUT
+
Q1
EN
0
CXIN+
CxHYS
MUX
DAC
1
(2)
CxSP
To ECCP PWM Logic
CXOE
2
3
FVR Buffer2
CXSYNC
CxON
VSS
TRIS bit
CXOUT
CXPCH<1:0>
0
1
2
D
Q
(from Timer1)
T1CLK
To Timer1
SYNCCXOUT
Note 1:
When CxON = 0, the Comparator will produce a ‘0’ at the output
When CxON = 0, all multiplexer inputs are disconnected.
Output of comparator can be frozen during debugging.
2:
3:
DS41364A-page 144
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
12.2.3
COMPARATOR OUTPUT POLARITY
12.2 Comparator Control
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a non-inverted output.
Each comparator has 2 control registers: CMxCON0 and
CMxCON1.
The CMxCON0 registers (see Register 12-1) contain
Control and Status bits for the following:
• Enable
Table 12-1 shows the output state versus input
conditions, including polarity control.
• Output selection
• Output polarity
TABLE 12-1: COMPARATOR OUTPUT
STATE VS. INPUT
• Speed/Power selection
• Hysteresis enable
• Output synchronization
CONDITIONS
Input Condition
CxPOL
CxOUT
The CMxCON1 registers (see Register 12-2) contain
Control bits for the following:
CxVN > CxVP
CxVN < CxVP
CxVN > CxVP
CxVN < CxVP
0
0
1
1
0
1
0
1
• Interrupt enable
• Interrupt edge polarity
• Positive input channel selection
• Negative input channel selection
12.2.4
COMPARATOR SPEED/POWER
SELECTION
12.2.1
COMPARATOR ENABLE
The trade-off between speed or power can be opti-
mized during program execution with the CxSP control
bit. The default state for this bit is ‘1’ which selects the
normal speed mode. Device power consumption can
be optimized at the cost of slower comparator propaga-
tion delay by clearing the CxSP bit to ‘0’.
Setting the CxON bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
12.2.2
COMPARATOR OUTPUT
SELECTION
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CMOUT register. In order to
make the output available for an external connection,
the following conditions must be true:
• CxOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set
Note 1: The CxOE bit overrides the PORT data
latch. Setting the CxON has no impact on
the port override.
2: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 145
PIC16F193X/LF193X
To enable the interrupt, you must set the following bits:
12.3 Comparator Hysteresis
• CxON, CxPOL and CxSP bits of the CMxCON0
register
A selectable amount of separation voltage can be
added to the input pins of each comparator to provide
a hysteresis function to the overall operation.
• CxIE bit of the PIE2 register
• CxINTP bit of the CMxCON1 register (for a rising
edge detection)
These hysteresis levels change as a function of the
comparator’s Speed/Power mode selection.
• CxINTN bit of the CMxCON1 register (for a falling
edge detection)
Table 12-2 shows the hysteresis levels.
• PEIE and GIE bits of the INTCON register
TABLE 12-2: HYSTERESIS LEVELS
The associated interrupt flag bit, CxIF bit of the PIR2
register, must be cleared in software. If another edge is
detected while this flag is being cleared, the flag will still
be set at the end of the sequence.
CxSP
CxHYS Enabled CxHYS Disabled
0
1
± 3mV
<< ± 1mV
± 3mV
± 20mV
Note:
Although a comparator is disabled, an
interrupt can be generated by changing
the output polarity with the CxPOL bit of
the CMxCON0 register, or by switching the
comparator on or off with the CxON bit of
the CMxCON0 register.
These levels are approximate.
See Section 28.0 “Electrical Specifications” for
more information.
12.4 Timer1 Gate Operation
The output resulting from a comparator operation can
be used as a source for gate control of Timer1. See
Section 16.6 “Timer1 Gate” for more information.
This feature is useful for timing the duration or interval
of an analog event.
12.6 Comparator Positive Input
Selection
Configuring the CxPCH<1:0> bits of the CMxCON1
register directs an internal voltage reference or an
analog pin to the non-inverting input of the comparator:
It is recommended that the comparator output be syn-
chronized to Timer1. This ensures that Timer1 does not
increment while a change in the comparator is occur-
ring.
• CxIN+ analog pin
• DAC
• FVR (Fixed Voltage Reference)
• AVSS (Analog Ground)
12.4.1
COMPARATOR OUTPUT
SYNCHRONIZATION
See Section 14.0 “Fixed Voltage Reference” for
more information on the fixed voltage reference
module.
The output from either comparator, C1 or C2, can be
synchronized with Timer1 by setting the CxSYNC bit of
the CMxCON0 register.
See Section 11.0 “Analog-to-Digital Converter
(ADC) Module” for more information on the CVDAC
input signal.
Once enabled, the comparator output is latched on the
falling edge of the Timer1 source clock. If a prescaler is
used with Timer1, the comparator output is latched after
the prescaling function. To prevent a race condition, the
comparator output is latched on the falling edge of the
Timer1 clock source and Timer1 increments on the
rising edge of its clock source. See the Comparator
Block Diagram (Figure 12-2) and the Timer1 Block
Diagram (Figure 16-1) for more information.
Any time the comparator is disabled (CxON = 0), all
comparator inputs are disabled.
12.7 Comparator Negative Input
Selection
The CxNCH<1:0> bits of the CMxCON0 register direct
one of four analog pins to the comparator inverting
input.
12.5 Comparator Interrupt
Note:
To use CxIN+ and CxINx- pins as analog
input, the appropriate bits must be set in
the ANSEL register and the corresponding
TRIS bits must also be set to disable the
output drivers.
An interrupt can be generated upon a change in the
output value of the comparator for each comparator, a
rising edge detector and a Falling edge detector are
present.
When either edge detector is triggered and its associ-
ated enable bit is set (CxINTP and/or CxINTN bits of
the CMxCON1 register), the Corresponding Interrupt
Flag bit (CxIF bit of the PIR2 register) will be set.
DS41364A-page 146
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
12.8 Comparator Response Time
12.10 Analog Input Connection
Considerations
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the comparator
differs from the settling time of the voltage reference.
Therefore, both of these times must be considered when
determining the total response time to a comparator
input change. See the Comparator and Voltage Refer-
ence Specifications in Section 28.0 “Electrical Specifi-
cations” for more details.
A simplified circuit for an analog input is shown in
Figure 12-3. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is for-
ward biased and a latch-up may occur.
A maximum source impedance of 10 kΩ is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
12.9 Interaction with ECCP Logic
The C1 and C2 comparators can be used as general
purpose comparators. Their outputs can be brought
out to the C1OUT and C2OUT pins. However, when
the ECCP Auto-Shutdown is active it can use one or
both comparators. If auto-restart is also enabled the
comparators can be configured as a closed loop
analog feedback to the ECCP thereby, creating an
analog controlled PWM.
Note 1: When reading a PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.
FIGURE 12-3:
ANALOG INPUT MODEL
VDD
VT ≈ 0.6V
RIC
Rs < 10K
To Comparator
AIN
(1)
ILEAKAGE
CPIN
5 pF
VA
VT ≈ 0.6V
Vss
Legend: CPIN
= Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
RS
VA
= Interconnect Resistance
= Source Impedance
= Analog Voltage
VT
= Threshold Voltage
Note 1: See Section 28.0 “Electrical Specifications”
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 147
PIC16F193X/LF193X
REGISTER 12-1: CMxCON0: COMPARATOR X CONTROL REGISTER 0
R/W-0/0
CxON
R-0/0
R/W-0/0
CxOE
R/W-0/0
CxPOL
U-0
—
R/W-1/1
CxSP
R/W-0/0
CxHYS
R/W-0/0
CxSYNC
CxOUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
CxON: Comparator Enable bit
1= Comparator is enabled and consumes no active power
0= Comparator is disabled
CxOUT: Comparator Output bit
If CxPOL = 1 (inverted polarity):
1= CxVP < CxVN
0= CxVP > CxVN
If CxPOL = 0 (non-inverted polarity):
1= CxVP > CxVN
0= CxVP < CxVN
bit 5
bit 4
CxOE: Comparator Output Enable bit
1= CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually
drive the pin. Not affected by CxON.
0= CxOUT is internal only
CxPOL: Comparator Output Polarity Select bit
1= Comparator output is inverted
0= Comparator output is not inverted
bit 3
bit 2
Unimplemented: Read as ‘0’
CxSP: Comparator Speed/Power Select bit
1= Comparator operates in normal power, higher speed mode
0= Comparator operates in low-power, low-speed mode
bit 1
bit 0
CxHYS: Comparator Hysteresis Enable bit
1= Comparator hysteresis enabled
0= Comparator hysteresis disabled
CxSYNC: Comparator Output Synchronous Mode bit
1= Comparator output to Timer1 and I/O pin is synchronous to changes on tmr1_clk. Output updated
on the falling edge of tmr1_clk.
0= Comparator output to Timer1 and I/O pin is asynchronous.
Refer to Figure 12-2.
DS41364A-page 148
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
REGISTER 12-2: CMxCON1: COMPARATOR CX CONTROL REGISTER 1
R/W-0/0
CxINTP
R/W-0/0
CxINTN
R/W-0/0
CxPCH1
R/W-0/0
CxPCH0
U-0
—
U-0
—
R/W-0/0
CxNCH1
R/W-0/0
CxNCH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
CxINTP: Comparator Interrupt on Positive Going Edge Enable bits
1= The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit
0= No interrupt flag will be set on a positive going edge of the CxOUT bit
bit 6
CxINTN: Comparator Interrupt on Negative Going Edge Enable bits
1= The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit
0= No interrupt flag will be set on a negative going edge of the CxOUT bit
bit 5-4
CxPCH<1:0>: Comparator Positive Input Channel Select bits
00= CxVP connects to CxIN+ pin
01= CxVP connects to CVDAC
10= CxVP connects to FVR Voltage Reference
11= CxVP connects to AVSS
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
CxNCH<1:0>: Comparator Negative Input Channel Select bits
00= CxVN connects to CxIN0- pin
01= CxVN connects to CxIN1- pin
10= CxVN connects to CxIN2- pin
11= CxVN connects to CxIN3- pin
Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1and corresponding port
TRIS bit = 0.
REGISTER 12-3: CMOUT: COMPARATOR OUTPUT REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
MC2OUT
MC1OUT
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
bit 1
Unimplemented: Read as ‘0’
MC2OUT: Mirror Copy of C2OUT bit
MC1OUT: Mirror Copy of C1OUT bit
bit 0
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 149
PIC16F193X/LF193X
TABLE 12-3: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CM1CON0
CM2CON0
CM1CON1
CM2CON1
CMOUT
FVRCON
DACCON0
DACCON1
INTCON
PIR2
C1ON
C2ON
C1NTP
C2NTP
—
C1OUT
C2OUT
C1INTN
C2INTN
—
C1OE
C2OE
C1PCH1
C2PCH1
—
C1POL
C2POL
C1PCH0
C2PCH0
—
---
—
—
—
—
C1SP
C2SP
—
C1HYS
C2HYS
C1SYNC
C2SYNC
C1NCH0
C2NCH0
148
148
149
149
149
156
153
153
73
C1NCH1
C2NCH1
—
—
MC2OUT MC1OUT
FVREN
DACEN
—
FVRRDY
DACLPS
—
TSEN
DACOE
—
TSRNG
—
CDAFVR1 CDAFVR0 ADFVR1
ADFVR0
DACNSS
DACR0
IOCIF
DACPSS1 DACPSS0
—
DACR1
INTF
DACR4
INTE
DACR3
IOCIE
DACR2
TMR0IF
LCDIF
LCDIE
RC2
GIE
PEIE
TMR0IE
C1IF
OSFIF
OSFIE
RC7
C2IF
EEIF
BCLIF
BCLIE
RC3
—
CCP2IF
CCP2IE
RC0
78
PIE2
C2IE
C1IE
EEIE
—
75
PORTC
RC6
RC5
RC4
RC1
93
LATC
LATC7
TRISC7
—
LATC6
TRISC6
—
LATC5
TRISC5
ANSA5
ANSB5
LATC4
TRISC4
ANSA4
ANSB4
LATC3
TRISC3
ANSA3
ANSB3
LATC2
TRISC2
ANSA2
ANSB2
LATC1
TRISC1
ANSA1
ANSB1
LATC0
TRISC0
ANSA0
ANSB0
93
TRISC
94
ANSELA
ANSELB
Legend:
86
—
—
91
— = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
DS41364A-page 150
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
Due to the limited current drive capability, a buffer must
be used on the voltage reference output for external
connections to DACOUT. Figure 13-1 shows an exam-
ple buffering technique.
13.0 DIGITAL-TO-ANALOG
CONVERTER (DAC) MODULE
The Digital-to-Analog Converter supplies a variable
voltage reference, ratiometric with VDD, with 32 select-
able output levels. The output of the DAC can be con-
figured to supply a reference voltage to the following:
13.5 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the DACCON0 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
• Comparator positive input
• ADC input channel
• DACOUT device pin
The Digital-to-Analog Converter (DAC) can be enabled
by setting the DACEN bit of the DACCON0 register.
13.6 Effects of a Reset
13.1 Output Voltage Selection
A device Reset affects the following:
The DAC has 32 voltage level ranges. The 32 levels
are set with the DACR<4:0> bits of the DACCON1
register.
• Voltage reference is disabled
• Fixed voltage reference is disabled
• DAC is removed from the DACOUT pin
• The DACR<4:0> range select bits are cleared
The DAC output voltage is determined by the following
equations:
EQUATION 13-1:
DACR<4:0>
⎛
⎞
⎠
VOUT = (VSOURCE+ – VSOURCE-) × ------------------------------
⎝
2 ∧ 5
+ VSOURCE-
VSOURCE+ = VDD, VREF+ or FVR1
VSOURCE+ = VSS or VREF-
13.2 Output Clamped to VSS
The DAC output voltage can be set to Vss with no
power consumption by setting the DACEN bit of the
DACCON0 register to ‘0’: This allows the comparator to
detect a zero-crossing while not consuming additional
current from the DAC.
13.3 Output Ratiometric to VDD
The DAC is VDD derived and therefore, the DAC output
changes with fluctuations in VDD. The tested absolute
accuracy of the DAC can be found in Section 28.0
“Electrical Specifications”.
13.4 Voltage Reference Output
The DAC can be output to the device DACOUT pin by
setting the DACOE bit of the DACCON0 register to ‘1’.
Selecting the reference voltage for output on the
DACOUT pin automatically overrides the digital output
buffer and digital input threshold detector functions of
that pin. Reading the DACOUT pin when it has been
configured for reference voltage output will always
return a ‘0’.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 151
PIC16F193X/LF193X
FIGURE 13-1:
DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
FVR_BUFFER2
Digital-to-Analog Converter (DAC)
VDD
VREF+
DACR<4:0>
4
R
DACPSS<1:0>
DACEN
2
R
R
R
32
Steps
DAC
(To Comparator and
ADC Modules)
R
R
R
CVREF
DACOE
DACNSS<1:0>
2
VREF-
DS41364A-page 152
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
REGISTER 13-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0
R/W-0/0
DACEN
R/W-0/0
DACLPS
R/W-0/0
DACOE
U-0
---
R/W-0/0
R/W-0/0
U-0
---
R/W-0/0
DACPSS1
DACPSS0
DACNSS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
DACEN: DAC Enable bit
0= DAC is disabled
1= DAC is enabled
DACLPS: DAC Low-Power Voltage State Select bit
0= VDAC = DAC Negative reference source selected
1= VDAC = DAC Positive reference source selected
DACOE: DAC Voltage Output Enable bit
1= DAC voltage level is also an output on the DACOUT pin
0= DAC voltage level is disconnected from the DACOUT pin
bit 4
Unimplemented: Read as ‘0’
bit 3-2
DACPSS<1:0>: DAC Positive Source Select bits
00= VDD
01= VREF+
10= FVR1 output
11= Reserved, do not use
bit 1
bit 0
Unimplemented: Read as ‘0’
DACNSS: DAC Negative Source Select bits
0= VSS
1= VREF-
REGISTER 13-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1
U-0
---
U-0
---
U-0
---
R/W-0/0
DACR4
R/W-0/0
DACR3
R/W-0/0
DACR2
R/W-0/0
DACR1
R/W-0/0
DACR0
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
DACR<4:0>: DAC Voltage Output Select bits
VOUT = ((VSOURCE+) - (VSOURCE-))*(DACR<4:0>/(2^5)) + VSOURCE-
Note 1: The output select bits are always right justified to ensure that any number of bits can be used without
affecting the register layout.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 153
PIC16F193X/LF193X
TABLE 13-1: REGISTERS ASSOCIATED WITH THE DIGITAL-TO-ANALOG CONVERTER
Register
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FVRCON
DACCON0
DACCON1
Legend:
FVREN
DACEN
---
FVRRDY
DACLPS
---
TSEN
DACOE
---
TSRNG
---
CDAFVR1 CDAFVR0
DACPSS1 DACPSS0
ADFVR1
---
ADFVR0
DACNSS
DACR0
156
153
153
DACR4
DACR3
DACR2
DACR1
Shaded cells are not used with the DAC.
DS41364A-page 154
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
The ADFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module. Refer-
ence Section 11.0 “Analog-to-Digital Converter
(ADC) Module” for additional information on selecting
the appropriate input channel.
14.0 FIXED VOLTAGE REFERENCE
The Fixed Voltage Reference, or FVR, is a stable
voltage reference, independent of VDD, with 1.024V,
2.048V or 4.096V selectable output levels. The output
of the FVR can be configured to supply a reference
voltage to the following:
The CDAFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the comparator module.
Reference Section 12.0 “Comparator Module” for
additional information on selecting the appropriate
input channel.
• ADC input channel
• ADC positive reference
• Comparator positive input
• Programmable voltage reference
• LCD bias generator
The FVR can be enabled by setting the FVREN bit of
the FVRCON register.
14.2 FVR Stabilization Period
When the fixed voltage reference module is enabled, it
requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for use,
the FVRRDY bit of the FVRCON register will be set. See
Section 28.0 “Electrical Specifications” for the
minimum delay requirement.
14.1 Independent Gain Amplifiers
The output of the FVR supplied to the ADC and
comparator modules is routed through two
independent programmable gain amplifiers. Each
amplifier can be configured to amplify the reference
voltage by 1x, 2x or 4x.
FIGURE 14-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
ADFVR<1:0>
2
X1
X2
X4
FVR_BUFFER1
(To ADC Module)
CDAFVR<1:0>
2
X1
X2
X4
FVR_BUFFER2
(To Comparators, DAC)
FVR_VREF
(To LCD Bias Generator)
+
_
FVREN
FVRRDY
1.024V Fixed
Reference
FIGURE 14-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC16F193X/
PIC16LF193X
CVREF
Module
R
+
–
Buffered CVREF Output
CVREF
Voltage
Reference
Output
Impedance
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 155
PIC16F193X/LF193X
REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R/W-0/0
FVREN
R-q/q
FVRRDY(1)
R/W-0/0
—
R/W-0/0
—
R/W-0/0
R/W-0/0
R/W-0/0
ADFVR1
R/W-0/0
ADFVR0
CDAFVR1
CDAFVR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
FVREN: Fixed Voltage Reference Enable bit
0= Fixed Voltage Reference is disabled
1= Fixed Voltage Reference is enabled
FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
0= Fixed Voltage Reference output is not active or stable
1= Fixed Voltage Reference output is ready for use
bit 5-4
bit 3-2
Reserved: Read as ‘0’. Maintain these bits clear.
CDAFVR<1:0>: Comparator and D/A Converter Fixed Voltage Reference Selection bit
00= Comparator and D/A Converter Fixed Voltage Reference Peripheral output is off.
01= Comparator and D/A Converter Fixed Voltage Reference Peripheral output is 1x (1.024V)
10= Comparator and D/A Converter Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
11= Comparator and D/A Converter Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)
bit 1-0
ADFVR<1:0>: A/D Converter Fixed Voltage Reference Selection bit
00= A/D Converter Fixed Voltage Reference Peripheral output is off.
01= A/D Converter Fixed Voltage Reference Peripheral output is 1x (1.024V)
10= A/D Converter Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
11= A/D Converter Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)
Note 1: FVRRDY is always ‘1’ on regulated parts (PIC16F193X).
2: Fixed Voltage Reference output cannot exceed VDD.
TABLE 14-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Register
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR1 CDAFVR0
ADFVR1
ADFVR0
156
Legend:
Shaded cells are not used with the voltage reference.
DS41364A-page 156
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
15.0 TIMER0 MODULE
The Timer0 module is an 8-bit timer/counter with the
following features:
Note:
The value written to the TMR0 register can
be adjusted, in order to account for the two
instruction cycle delay when TMR0 is
written.
• 8-bit timer/counter register (TMR0)
• 8-bit prescaler (independent of Watchdog Timer)
• Programmable internal or external clock source
• Programmable external clock edge selection
• Interrupt on overflow
15.1.2
8-BIT COUNTER MODE
In 8-Bit Counter mode, the Timer0 module will increment
on every rising or falling edge of the T0CKI pin or the
Capacitive Sensing Oscillator (CPSCLK) signal.
• TMR0 can be used to gate Timer1
Figure 15-1 is a block diagram of the Timer0 module.
8-Bit Counter mode using the T0CKI pin is selected by
setting the TMR0CS bit in the OPTION register to ‘1’
and resetting the T0XCS bit in the CPSCON0 register to
‘0’.
15.1 Timer0 Operation
The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
8-Bit Counter Mode using the Capacitive Sensing
Oscillator (CPSCLK) signal is selected by setting the
TMR0CS bit in the OPTION register to ‘1’ and setting
the T0XCS bit in the CPSCON0 register to ‘1’.
15.1.1
8-BIT TIMER MODE
The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-Bit Timer mode is
selected by clearing the TMR0CS bit of the OPTION
register.
The rising or falling transition of the incrementing edge
for either input source is determined by the TMR0SE bit
in the OPTION register.
FIGURE 15-1:
BLOCK DIAGRAM OF THE TIMER0
FOSC/4
Data Bus
0
1
8
T0CKI
1
Sync
0
1
TMR0
2 TCY
0
Set Flag bit TMR0IF
From CPSCLK
on Overflow
TMR0CS
TMR0SE
8-bit
Prescaler
PSA
Overflow to Timer1
T0XCS
8
PS<2:0>
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 157
PIC16F193X/LF193X
15.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
A software programmable prescaler is available for
exclusive use with Timer0. The prescaler is enabled by
clearing the PSA bit of the OPTION register.
Note:
The Watchdog Timer (WDT) uses its own
independent prescaler.
There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION register.
In order to have a 1:1 prescaler value for the Timer0
module, the prescaler must be disabled by setting the
PSA bit of the OPTION register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.
15.1.4
TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The Timer0
interrupt enable is the TMR0IE bit of the INTCON
register.
Note:
The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
15.1.5
8-BIT COUNTER MODE
SYNCHRONIZATION
When in 8-Bit Counter mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Section 28.0 “Electrical
Specifications”.
15.1.6
OPERATION DURING SLEEP
Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.
DS41364A-page 158
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
REGISTER 15-1: OPTION_REG: OPTION REGISTER
R/W-1/1
WPUEN
R/W-1/1
INTEDG
R/W-1/1
R/W-1/1
R/W-1/1
PSA
R/W-1/1
PS2
R/W-1/1
PS1
R/W-1/1
PS0
TMR0CS
TMR0SE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
WPUEN: Weak Pull-up Enable bit
1= All weak pull-ups are disabled (except MCLR, if it is enabled)
0= Weak pull-ups are enabled by individual WPUx latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
TMR0CS: Timer0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (FOSC/4)
TMR0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
Bit Value
Timer0 Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
TABLE 15-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPSCON0
INTCON
CPSON
GIE
—
—
—
CPSRNG1 CPSRNG0 CPSOUT T0XCS
180
73
PEIE
TMR0IE
INTE
RBIE
PSA
TMR0IF
PS2
INTF
PS1
RBIF
PS0
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE
51
TMR0
TRISA
Timer0 Module Register
157*
86
TRISA7 TRISA6 TRISA5 TRISA4
TRISA3
TRISA2
TRISA1 TRISA0
Legend: – = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the
Timer0 module.
*
Page provides register information.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 159
PIC16F193X/LF193X
NOTES:
DS41364A-page 160
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
• Gate Toggle Mode
• Gate Single-pulse Mode
• Gate Value Status
16.0 TIMER1 MODULE WITH GATE
CONTROL
The Timer1 module is a 16-bit timer/counter with the
following features:
• Gate Event Interrupt
Figure 16-1 is a block diagram of the Timer1 module.
• 16-bit timer/counter register pair (TMR1H:TMR1L)
• Programmable internal or external clock source
• 3-bit prescaler
• Dedicated LP oscillator circuit
• Optionally synchronized comparator out
• Multiple Timer1 gate (count enable) sources
• Interrupt on overflow
• Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the Capture/Compare function
• Special Event Trigger (with CCP)
• Selectable Gate Source Polarity
FIGURE 16-1:
TIMER1 BLOCK DIAGRAM
T1GSS<1:0>
T1G
T1GSPM
00
From Timer0
Overflow
0
01
10
11
T1G_IN
D
Data Bus
T1GVAL
0
1
D
Q
Comparator 1
SYNCC1OUT
Single Pulse
Acq. Control
RD
1
T1GCON
Q1 EN
Q
Q
Comparator 2
SYNCC2OUT
Interrupt
Set
T1GGO/DONE
CK
R
TMR1ON
T1GTM
TMR1GIF
det
T1GPOL
TMR1GE
Set flag bit
TMR1IF on
Overflow
TMR1ON
To Comparator Module
TMR1(2)
EN
D
Synchronized
clock input
0
T1CLK
TMR1H
TMR1L
Q
1
TMR1CS<1:0>
T1SYNC
T1OSO
OUT
Cap. Sensing
Oscillator
11
10
Synchronize(3)
det
T1OSC
EN
Prescaler
1, 2, 4, 8
1
0
T1OSI
2
T1CKPS<1:0>
FOSC
Internal
Clock
01
00
FOSC/2
Internal
Clock
T1OSCEN
T1CKI
Sleep input
FOSC/4
Internal
Clock
(1)
To LCD and Clock Switching Modules
Note 1: ST Buffer is high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 161
PIC16F193X/LF193X
16.1 Timer1 Operation
16.2 Clock Source Selection
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
The TMR1CS<1:0> and T1OSCEN bits of the T1CON
register are used to select the clock source for Timer1.
Table 16-2 displays the clock source selections.
16.2.1
INTERNAL CLOCK SOURCE
When used with an internal clock source, the module is
a timer and increments on every instruction cycle.
When used with an external clock source, the module
can be used as either a timer or counter and incre-
ments on every selected edge of the external source.
When the internal clock source is selected the
TMR1H:TMR1L register pair will increment on multiples
of FOSC as determined by the Timer1 prescaler.
16.2.2
EXTERNAL CLOCK SOURCE
Timer1 is enabled by configuring the TMR1ON and
TMR1GE bits in the T1CON and T1GCON registers,
respectively. Table 16-1 displays the Timer1 enable
selections.
When the external clock source is selected, the Timer1
module may work as a timer or a counter.
When enabled to count, Timer1 is incremented on the
rising edge of the external clock input T1CKI or the
capacitive sensing oscillator signal. Either of these
external clock sources can be synchronized to the
microcontroller system clock or they can run
asynchronously.
TABLE 16-1: TIMER1 ENABLE
SELECTIONS
Timer1
Operation
TMR1ON
TMR1GE
When used as a timer with a clock oscillator, an
external 32.768 kHz crystal can be used in conjunction
with the dedicated internal oscillator circuit.
0
0
1
1
0
1
0
1
Off
Off
Note:
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
Always On
Count Enabled
• Timer1 enabled after POR
• Write to TMR1H or TMR1L
• Timer1 is disabled
• Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON=1) when T1CKI is
low.
TABLE 16-2: CLOCK SOURCE SELECTIONS
TMR1CS1
TMR1CS0
T1OSCEN
Clock Source
0
0
1
1
1
1
0
1
0
0
x
x
x
0
1
System Clock (FOSC)
Instruction Clock (FOSC/4)
Capacitive Sensing Oscillator
External Clocking on T1CKI Pin
Osc.Circuit On T1OSI/T1OSO Pins
DS41364A-page 162
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
16.3 Timer1 Prescaler
16.6 Timer1 Gate
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
Timer1 can be configured to count freely or the count
can be enabled and disabled using Timer1 Gate
circuitry. This is also referred to as Timer1 Gate Enable.
Timer1 Gate can also be driven by multiple selectable
sources.
16.6.1
TIMER1 GATE ENABLE
16.4 Timer1 Oscillator
The Timer1 Gate Enable mode is enabled by setting
the TMR1GE bit of the T1GCON register. The polarity
of the Timer1 Gate Enable mode is configured using
the T1GPOL bit of the T1GCON register.
A dedicated low-power 32.768 kHz oscillator circuit is
built-in between pins T1OSI (input) and T1OSO
(amplifier output). This internal circuit is to be used in
conjunction with an external 32.768 kHz crystal.
When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
source. When Timer1 Gate Enable mode is disabled,
no incrementing will occur and Timer1 will hold the
current count. See Figure 16-3 for timing details.
The oscillator circuit is enabled by setting the
T1OSCEN bit of the T1CON register. The oscillator will
continue to run during Sleep.
Note:
The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1.
TABLE 16-3: TIMER1 GATE ENABLE
SELECTIONS
T1CLK T1GPOL
T1G
Timer1 Operation
16.5 Timer1 Operation in
Asynchronous Counter Mode
↑
↑
↑
↑
0
0
1
1
0
1
0
1
Counts
Holds Count
Holds Count
Counts
If control bit T1SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 16.5.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
16.6.2
TIMER1 GATE SOURCE
SELECTION
The Timer1 Gate source can be selected from one of
four different sources. Source selection is controlled by
the T1GSS bits of the T1GCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the T1GPOL bit of the
T1GCON register.
Note:
When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
TABLE 16-4: TIMER1 GATE SOURCES
T1GSS
Timer1 Gate Source
Timer1 Gate Pin
00
01
Overflow of Timer0
16.5.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
(TMR0 increments from FFh to 00h)
10
11
Comparator 1 Output SYNCC1OUT
(optionally synchronized out)
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
Comparator 2 Output SYNCC2OUT
(optionally synchronized out)
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TMR1L register pair.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 163
PIC16F193X/LF193X
16.6.2.1
T1G Pin Gate Operation
16.6.4
TIMER1 GATE SINGLE-PULSE
MODE
The T1G pin is one source for Timer1 Gate Control. It
can be used to supply an external source to the Timer1
Gate circuitry.
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/DONE bit in the T1GCON register must be set.
The Timer1 will be fully enabled on the next
incrementing edge. On the next trailing edge of the
pulse, the T1GGO/DONE bit will automatically be
cleared. No other gate events will be allowed to
increment Timer1 until the T1GGO/DONE bit is once
again set in software.
16.6.2.2
Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h,
low-to-high pulse will automatically be generated and
internally supplied to the Timer1 Gate circuitry.
a
16.6.2.3
Comparator C1 Gate Operation
The output resulting from a Comparator 1 operation can
be selected as a source for Timer1 Gate Control. The
Clearing the T1GSPM bit of the T1GCON register will
also clear the T1GGO/DONE bit. See Figure 16-5 for
timing details.
Comparator
1
output (SYNCC1OUT) can be
synchronized to the Timer1 clock or left asynchronous.
For more information see Section 12.4.1 “Comparator
Output Synchronization”.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1
Gate source to be measured. See Figure 16-6 for
timing details.
16.6.2.4
Comparator C2 Gate Operation
The output resulting from a Comparator 2 operation
can be selected as a source for Timer1 Gate Control.
The Comparator 2 output (SYNCC2OUT) can be
synchronized to the Timer1 clock or left asynchronous.
For more information see Section 12.4.1 “Comparator
Output Synchronization”.
16.6.5
TIMER1 GATE VALUE STATUS
When Timer1 Gate Value Status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T1GVAL bit in the T1GCON
register. The T1GCON bit is valid even when the
Timer1 Gate is not enabled (TMR1GE bit is cleared).
16.6.3
TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is possi-
ble to measure the full-cycle length of a Timer1 gate
signal, as opposed to the duration of a single level
pulse.
16.6.6
TIMER1 GATE EVENT INTERRUPT
When Timer1 Gate Event Interrupt is enabled, it is pos-
sible to generate an interrupt upon the completion of a
gate event. When the falling edge of T1GVAL occurs,
the TMR1GIF flag bit in the PIR1 register will be set. If
the TMR1GIE bit in the PIE1 register is set, then an
interrupt will be recognized.
The Timer1 Gate source is routed through a flip-flop
that changes state on every incrementing edge of the
signal. See Figure 16-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
The TMR1GIF flag bit operates even when the Timer1
Gate is not enabled (TMR1GE bit is cleared).
Note:
Enabling Toggle mode at the same time as
changing the gate polarity may result in
indeterminate operation.
DS41364A-page 164
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
16.7 Timer1 Interrupt
16.9 ECCP/CCP Capture/Compare Time
Base
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt on rollover, you must set
these bits:
The CCP modules uses the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPR1H:CCPR1L
register pair on a configured event.
• TMR1ON bit of the T1CON register
• TMR1IE bit of the PIE1 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
In Compare mode, an event is triggered when the value
CCPR1H:CCPR1L register pair matches the value in
the TMR1H:TMR1L register pair. This event can be a
Special Event Trigger.
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
For
more
information,
see
Section 19.0
Note:
The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
“Capture/Compare/PWM Modules (ECCP1, ECCP2,
ECCP3, CCP4, CCP5)”.
16.10 ECCP/CCP Special Event Trigger
16.8 Timer1 Operation During Sleep
When any of the CCP’s are configured to trigger a spe-
cial event, the trigger will clear the TMR1H:TMR1L reg-
ister pair. This special event does not cause a Timer1
interrupt. The CCP module may still be configured to
generate a CCP interrupt.
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
• TMR1ON bit of the T1CON register must be set
• TMR1IE bit of the PIE1 register must be set
• PEIE bit of the INTCON register must be set
• T1SYNC bit of the T1CON register must be set
In this mode of operation, the CCPR1H:CCPR1L
register pair becomes the period register for Timer1.
Timer1 should be synchronized to the FOSC/4 to utilize
the Special Event Trigger. Asynchronous operation of
Timer1 can cause a Special Event Trigger to be
missed.
• TMR1CS bits of the T1CON register must be
configured
• T1OSCEN bit of the T1CON register must be
configured
In the event that a write to TMR1H or TMR1L coincides
with a Special Event Trigger from the CCP, the write will
take precedence.
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine (0004h).
For more information, see Section 11.2.5 “Special
Event Trigger”.
Timer1 oscillator will continue to operate in Sleep
regardless of the T1SYNC bit setting.
FIGURE 16-2:
TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 165
PIC16F193X/LF193X
FIGURE 16-3:
TIMER1 GATE ENABLE MODE
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
TIMER1
N
N + 1
N + 2
N + 3
N + 4
FIGURE 16-4:
TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
TIMER1
N
N + 1 N + 2 N + 3 N + 4
N + 5 N + 6 N + 7 N + 8
DS41364A-page 166
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 16-5:
TIMER1 GATE SINGLE-PULSE MODE
TMR1GE
T1GPOL
T1GSPM
Cleared by hardware on
falling edge of T1GVAL
T1GGO/
DONE
Set by software
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
TIMER1
N
N + 1
N + 2
Cleared by
software
Set by hardware on
falling edge of T1GVAL
Cleared by software
TMR1GIF
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 167
PIC16F193X/LF193X
FIGURE 16-6:
TMR1GE
T1GPOL
TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
T1GSPM
T1GTM
Cleared by hardware on
falling edge of T1GVAL
T1GGO/
DONE
Set by software
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
TIMER1
N + 4
N + 2 N + 3
N
N + 1
Set by hardware on
falling edge of T1GVAL
Cleared by
software
Cleared by software
TMR1GIF
DS41364A-page 168
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
16.11 Timer1 Control Register
The Timer1 Control register (T1CON), shown in
Register 16-1, is used to control Timer1 and select the
various features of the Timer1 module.
REGISTER 16-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
T1SYNC
U-0
—
R/W-0/u
TMR1CS1
TMR1CS0
T1CKPS1
T1CKPS0
T1OSCEN
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
TMR1CS<1:0>: Timer1 Clock Source Select bits
11=Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC)
10=Timer1 clock source is pin or oscillator:
If T1OSCEN = 0:
External clock from T1CKI pin (on the rising edge)
If T1OSCEN = 1:
Crystal oscillator on T1OSI/T1OSO pins
01=Timer1 clock source is system clock (FOSC)
00=Timer1 clock source is instruction clock (FOSC/4)
bit 5-4
T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: LP Oscillator Enable Control bit
1= Dedicated Timer1 oscillator circuit enabled
0= Dedicated Timer1 oscillator circuit disabled
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS<1:0> = 1X
1= Do not synchronize external clock input
0= Synchronize external clock input with system clock (FOSC)
TMR1CS<1:0> = 0X
This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X.
bit 1
bit 0
Unimplemented: Read as ‘0’
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Clears Timer1 Gate flip-flop
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 169
PIC16F193X/LF193X
16.12 Timer1 Gate Control Register
The Timer1 Gate Control register (T1GCON), shown in
Register 16-2, is used to control Timer1 Gate.
REGISTER 16-2: T1GCON: TIMER1 GATE CONTROL REGISTER
R/W-0/u
R/W-0/u
T1GPOL
R/W-0/u
T1GTM
R/W-0/u
R/W-0/u
R-x/x
R/W-0/u
T1GSS1
R/W-0/u
T1GSS0
TMR1GE
T1GSPM
T1GGO/
DONE
T1GVAL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
TMR1GE: Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1= Timer1 counting is controlled by the Timer1 gate function
0= Timer1 counts regardless of Timer1 gate function
bit 6
bit 5
T1GPOL: Timer1 Gate Polarity bit
1= Timer1 gate is active-high (Timer1 counts when gate is high)
0= Timer1 gate is active-low (Timer1 counts when gate is low)
T1GTM: Timer1 Gate Toggle Mode bit
1= Timer1 Gate Toggle mode is enabled
0= Timer1 Gate Toggle mode is disabled and toggle flip flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4
bit 3
T1GSPM: Timer1 Gate Single-Pulse Mode bit
1= Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate
0= Timer1 gate Single-Pulse mode is disabled
T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1= Timer1 gate single-pulse acquisition is ready, waiting for an edge
0= Timer1 gate single-pulse acquisition has completed or has not been started
This bit is automatically cleared when T1GSPM is cleared.
bit 2
T1GVAL: Timer1 Gate Current State bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.
Unaffected by Timer1 Gate Enable (TMR1GE).
bit 1-0
T1GSS<1:0>: Timer1 Gate Source Select bits
00= Timer1 Gate pin
01= Timer0 overflow output
10= Comparator 1 optionally synchronized output (SYNCC1OUT)
11= Comparator 2 optionally synchronized output (SYNCC2OUT)
DS41364A-page 170
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 16-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELB
CCP1CON
CCP2CON
INTCON
PIE1
—
—
—
—
ANSB5
DC1B1
DC2B1
TMR0IE
RCIE
ANSB4
DC1B0
DC2B0
INTE
ANSB3
ANSB2
ANSB1
ANSB0
91
184
184
73
CCP1M3 CCP1M2 CCP1M1 CCP1M0
CCP2M3 CCP2M2 CCP2M1 CCP2M0
—
—
GIE
PEIE
ADIE
ADIF
RB6
RBIE
SSPIE
SSPIF
RB3
TMR0IF
INTF
RBIF
TMR1GIE
TMR1GIF
RB7
TXIE
CCP1IE TMR2IE TMR1IE
CCP1IF TMR2IF TMR1IF
74
PIR1
RCIF
TXIF
77
PORTB
TMR1H
TMR1L
TRISB
RB5
RB4
RB2
RB1
RB0
90
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
165*
165*
91
TRISB7
TRISC7
TRISB6
TRISC6
TRISB5
TRISC5
TRISB4
TRISC4
TRISB3
TRISC3
TRISB2 TRISB1 TRISB0
TRISC2 TRISC1 TRISC0
TRISC
94
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
—
TMR1ON
T1CON
169
170
TMR1GE T1GPOL
T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0
DONE
T1GCON
Legend: x= unknown, u= unchanged, —= unimplemented, read as ‘0’. Shaded cells are not used by the Timer1
module.
*
Page provides register information.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 171
PIC16F193X/LF193X
NOTES:
DS41364A-page 172
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
17.0 TIMER2/4/6 MODULES
There are three identical Timer2-type modules
available. To maintain pre-existing naming conventions,
the Timers are called Timer2, Timer4 and Timer6 (also
Timer2/4/6).
The Timer2/4/6 modules incorporate the following
features:
• 8-bit Timer and Period registers (TMRx and PRx,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16,
and 1:64)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMRx match with PRx, respectively
• Optional use as the shift clock for the MSSPx
modules (Timer2 only)
See Figure 17-1 for a block diagram of Timer2/4/6.
FIGURE 17-1:
TIMER2/4/6 BLOCK DIAGRAM
Sets Flag
bit TMRxIF
Output
TMRx
Prescaler
TMRx
Reset
FOSC/4
1:1, 1:4, 1:16, 1:64
Postscaler
1:1 to 1:16
2
Comparator
EQ
TxCKPS<1:0>
PRx
4
TxOUTPS<3:0>
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 173
PIC16F193X/LF193X
17.1 Timer2/4/6 Operation
17.3 Timer2/4/6 Output
The clock input to the Timer2/4/6 modules is the
system instruction clock (FOSC/4).
The unscaled output of TMRx is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
TMRx increments from 00h on each clock edge.
Timer2 can be optionally used as the shift clock source
for the MSSPx modules operating in SPI mode.
Additional information is provided in Section 17.0
“SSP Module Overview”
A 4-bit counter/prescaler on the clock input allows direct
input, divide-by-4 and divide-by-16 prescale options.
These options are selected by the prescaler control bits,
TxCKPS<1:0> of the TxCON register. The value of
TMRx is compared to that of the Period register, PRx, on
each clock cycle. When the two values match, the
comparator generates a match signal as the timer
output. This signal also resets the value of TMRx to 00h
on the next cycle and drives the output
counter/postscaler (see Section 17.2 “Timer2/4/6
Interrupt”).
17.4 Timer2/4/6 Operation During Sleep
The Timerx timers cannot be operated while the
processor is in Sleep mode. The contents of the TMRx
and PRx registers will remain unchanged while the
processor is in Sleep mode.
The TMRx and PRx registers are both directly readable
and writable. The TMRx register is cleared on any
device Reset, whereas the PRx register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
• a write to the TMRx register
• a write to the TxCON register
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• MCLR Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESETInstruction
Note:
TMRx is not cleared when TxCON is written.
17.2 Timer2/4/6 Interrupt
Timer2/4/6 can also generate an optional device
interrupt. The Timer2/4/6 output signal (TMRx-to-PRx
match)
provides
the
input
for
the
4-bit
counter/postscaler. This counter generates the TMRx
match interrupt flag which is latched in TMRxIF of the
PIRx register. The interrupt is enabled by setting the
TMRx Match Interrupt Enable bit, TMRxIE of the PIEx
register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, TxOUTPS<3:0>, of the TxCON register.
DS41364A-page 174
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
REGISTER 17-1: TXCON: TIMER2-TYPE TIMER CONTROL REGISTER
U-0
—
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMRxON
TxCKPS1
TxCKPS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TOUTPS<3:0>: Timer Output Postscaler Select bits
0000= 1:1 Postscaler
0001= 1:2 Postscaler
0010= 1:3 Postscaler
0011= 1:4 Postscaler
0100= 1:5 Postscaler
0101= 1:6 Postscaler
0110= 1:7 Postscaler
0111= 1:8 Postscaler
1000= 1:9 Postscaler
1001= 1:10 Postscaler
1010= 1:11 Postscaler
1011= 1:12 Postscaler
1100= 1:13 Postscaler
1101= 1:14 Postscaler
1110= 1:15 Postscaler
1111= 1:16 Postscaler
bit 2
TMRxON: Timerx On bit
1= Timerx is on
0= Timerx is off
bit 1-0
TxCKPS<1:0>: Timer2-type Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
10= Prescaler is 16
11= Prescaler is 64
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 175
PIC16F193X/LF193X
TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CCP1CON
CCP2CON
INTCON
PIE1
—
—
—
—
DC1B1
DC2B1
TMR0IE
DC1B0
DC2B0
INTE
CCP1M3 CCP1M2 CCP1M1 CCP1M0
CCP2M3 CCP2M2 CCP2M1 CCP2M0
184
184
73
GIE
PEIE
RBIE
TMR0IF
INTF
RBIF
TMR1GIE
TMR1GIF
—
ADIE
ADIF
RCIE
RCIF
TXIE
TXIF
SSPIE
SSPIF
CCP1IE TMR2IE
TMR1IE
TMR1IF
—
74
PIR1
CCP1IF
TMR2IF
TMR4IE
TMR4IF
77
PIE3
CCP5IE
CCP5IF
CCP4IE
CCP4IF
CCP3IE
CCP3IF
TMR6IE
TMR6IF
—
—
76
PIR3
—
—
79
PR2
Timer2 Module Period Register
Holding Register for the 8-bit TMR2 Register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
173*
173*
175
TMR2
T2CON
—
Legend: x= unknown, u= unchanged, -= unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.
Page provides register information.
*
DS41364A-page 176
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
18.0 CAPACITIVE SENSING
MODULE
The capacitive sensing module allows for an interaction
with an end user without a mechanical interface. In a
typical application, the capacitive sensing module is
attached to a pad on a Printed Circuit Board (PCB),
which is electrically isolated from the end user. When the
end user places their finger over the PCB pad, a
capacitive load is added, causing a frequency shift in the
capacitive sensing module. The capacitive sensing
module requires software and at least one timer
resource to determine the change in frequency. Key
features of this module include:
• Analog MUX for monitoring multiple inputs
• Capacitive sensing oscillator
• Multiple timer resources
• Software control
• Operation during Sleep
FIGURE 18-1:
CAPACITIVE SENSING BLOCK DIAGRAM
Timer0 Module
Set
TMR0IF
TMR0CS
T0XCS
T0CKI
FOSC/4
0
1
Overflow
0
1
TMR0
CPSCH<3:0>(2)
CPSON(3)
CPS0
CPS1
CPS2
CPS3
Timer1 Module
CPS4
CPSON
T1CS<1:0>
CPS5
FOSC
CPS6
Capacitive
Sensing
Oscillator
FOSC/4
CPS7
CPSCLK
CPS8(1)
CPS9(1)
CPS10(1)
CPS11(1)
CPS12(1)
CPS13(1)
CPS14(1)
CPS15(1)
CPS16(1)
TMR1H:TMR1L
EN
T1OSC/
T1CKI
CPSOSC
CPSOUT
T1GSEL<1:0>
T1G
CPSRNG<1:0>
Timer1 Gate
Control Logic
SYNCC1OUT
SYNCC2OUT
Note 1: Reference Register 18-2 for channels implemented on each device
2: CPSCH3 is not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938.
3: If CPSON = 0, disabling capacitive sensing, no channel is selected.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 177
PIC16F193X/LF193X
18.4.1
TIMER0
18.1 Analog MUX
To select Timer0 as the timer resource for the capacitive
sensing module:
The capacitive sensing module can monitor up to 16
inputs. The capacitive sensing inputs are defined as
CPS<15:0>. To determine if a frequency change has
occurred the user must:
• Set the T0XCS bit of the CPSCON0 register
• Clear the TMR0CS bit of the OPTION register
• Select the appropriate CPS pin by setting the
CPSCH<3:0> bits of the CPSCON1 register
When Timer0 is chosen as the timer resource, the
capacitive sensing oscillator will be the clock source for
Timer0. Refer to Section 15.0 “Timer0 Module” for
additional information.
• Set the corresponding ANSEL bit
• Set the corresponding TRIS bit
• Run the software algorithm
18.4.2
TIMER1
Selection of the CPSx pin while the module is enabled
will cause the capacitive sensing oscillator to be on the
CPSx pin. Failure to set the corresponding ANSEL and
TRIS bits can cause the capacitive sensing oscillator to
stop, leading to false frequency readings.
To select Timer1 as the timer resource for the
capacitive sensing module, set the TMR1CS<1:0> of
the T1CON register to ‘11’. When Timer1 is chosen as
the timer resource, the capacitive sensing oscillator will
be the clock source for Timer1. Because the Timer1
module has a gate control, developing a time base for
the frequency measurement can be simplified by using
the Timer0 overflow flag.
18.2 Capacitive Sensing Oscillator
The capacitive sensing oscillator consists of a constant
current source and a constant current sink, to produce
It is recommend that the Timer0 overflow flag, in con-
junction with the Toggle mode of the Timer1 Gate, be
used to develop the fixed time base required by the
software portion of the capacitive sensing module.
Refer to Section 16.12 “Timer1 Gate Control Regis-
ter” for additional information.
a
triangle waveform. The CPSOUT bit of the
CPSCON0 register shows the status of the capacitive
sensing oscillator, whether it is a sinking or sourcing
current. The oscillator is designed to drive a capacitive
load (single PCB pad) and at the same time, be a clock
source to either Timer0 or Timer1. The oscillator has
three different current settings as defined by
CPSRNG<1:0> of the CPSCON0 register. The different
current settings for the oscillator serve two purposes:
TABLE 18-1: TIMER1 ENABLE FUNCTION
TMR1ON
TMR1GE
Timer1 Operation
0
0
1
0
1
0
Off
Off
On
• Maximize the number of counts in a timer for a
fixed time base
• Maximize the count differential in the timer during
a change in frequency
1
1
Count Enabled by input
18.3 Timer resources
To measure the change in frequency of the capacitive
sensing oscillator, a fixed time base is required. For the
period of the fixed time base, the capacitive sensing
oscillator is used to clock either Timer0 or Timer1. The
frequency of the capacitive sensing oscillator is equal
to the number of counts in the timer divided by the
period of the fixed time base.
18.4 Fixed Time Base
To measure the frequency of the capacitive sensing
oscillator, a fixed time base is required. Any timer
resource or software loop can be used to establish the
fixed time base. It is up to the end user to determine the
method in which the fixed time base is generated.
Note:
The fixed time base can not be generated
by the timer resource that the capacitive
sensing oscillator is clocking.
DS41364A-page 178
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
18.5.3
FREQUENCY THRESHOLD
18.5 Software Control
The frequency threshold should be placed midway
between the value of nominal frequency and the
reduced frequency of the capacitive sensing oscillator.
Refer to Application Note AN1103, “Software Handling
for Capacitive Sensing” (DS01103) for more detailed
information on the software required for capacitive
sensing module.
The software portion of the capacitive sensing module
is required to determine the change in frequency of the
capacitive sensing oscillator. This is accomplished by
the following:
• Setting a fixed time base to acquire counts on
Timer0 or Timer1
• Establishing the nominal frequency for the
capacitive sensing oscillator
Note:
For more information on general capacitive
sensing refer to Application Notes:
• Establishing the reduced frequency for the
capacitive sensing oscillator due to an additional
capacitive load
• AN1101, “Introduction to Capacitive
Sensing” (DS01101)
• AN1102, “Layout and Physical Design
Guidelines for Capacitive Sensing”
(DS01102)
• Set the frequency threshold
18.5.1
NOMINAL FREQUENCY
(NO CAPACITIVE LOAD)
18.6 Operation during Sleep
To determine the nominal frequency of the capacitive
sensing oscillator:
The capacitive sensing oscillator will continue to run as
long as the module is enabled, independent of the part
being in Sleep. In order for the software to determine if
a frequency change has occurred, the part must be
awake. However, the part does not have to be awake
when the timer resource is acquiring counts.
• Remove any extra capacitive load on the selected
CPSx pin
• At the start of the fixed time base, clear the timer
resource
• At the end of the fixed time base save the value in
the timer resource
Note:
Timer0 does not operate when in Sleep,
and therefore cannot be used for
capacitive sense measurements in Sleep.
The value of the timer resource is the number of
oscillations of the capacitive sensing oscillator for the
given time base. The frequency of the capacitive
sensing oscillator is equal to the number of counts on
in the timer divided by the period of the fixed time base.
18.5.2
REDUCED FREQUENCY
(ADDITIONAL CAPACITIVE LOAD)
The extra capacitive load will cause the frequency of the
capacitive sensing oscillator to decrease. To determine
the reduced frequency of the capacitive sensing
oscillator:
• Add a typical capacitive load on the selected
CPSx pin
• Use the same fixed time base as the nominal
frequency measurement
• At the start of the fixed time base, clear the timer
resource
• At the end of the fixed time base save the value in
the timer resource
The value of the timer resource is the number of oscil-
lations of the capacitive sensing oscillator with an addi-
tional capacitive load. The frequency of the capacitive
sensing oscillator is equal to the number of counts on
in the timer divided by the period of the fixed time base.
This frequency should be less than the value obtained
during the nominal frequency measurement.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 179
PIC16F193X/LF193X
REGISTER 18-1: CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0
R/W-0/0
CPSON
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R-0/0
R/W-0/0
T0XCS
CPSRNG1
CPSRNG0
CPSOUT
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
CPSON: Capacitive Sensing Module Enable bit
1= Capacitive sensing module is operating
0= Capacitive sensing module is shut off and consumes no operating current
bit 6-4
bit 3-2
Unimplemented: Read as ‘0’
CPSRNG<1:0>: Capacitive Sensing Oscillator Range bits
00= Oscillator is off
01= Oscillator is in low range. Charge/discharge current is nominally 0.1 µA.
10= Oscillator is in medium range. Charge/discharge current is nominally 1.2 µA.
11= Oscillator is in high range. Charge/discharge current is nominally 18 µA.
bit 1
bit 0
CPSOUT: Capacitive Sensing Oscillator Status bit
1= Oscillator is sourcing current (Current flowing out the pin)
0= Oscillator is sinking current (Current flowing into the pin)
T0XCS: Timer0 External Clock Source Select bit
If TMR0CS = 1
The T0XCS bit controls which clock external to the core/Timer0 module supplies Timer0:
1= Timer0 clock source is the capacitive sensing oscillator
0= Timer0 clock source is the T0CKI pin
If TMR0CS = 0
Timer0 clock source is controlled by the core/Timer0 module and is FOSC/4
DS41364A-page 180
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
REGISTER 18-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1
(1, 2)
(1)
U-0
—
U-0
—
U-0
—
R/W-0/0
CPSCH4
R/W-0/0
CPSCH3
R/W-0/0
R/W-0/0
R/W-0/0
CPSCH2
CPSCH1
CPSCH0
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
CPSCH<3:0>: Capacitive Sensing Channel Select bits
If CPSON = 0:
These bits are ignored. No channel is selected.
If CPSON = 1:
0000= channel 0, (CPS0)
0001= channel 1, (CPS1)
0010= channel 2, (CPS2)
0011= channel 3, (CPS3)
0100= channel 4, (CPS4)
0101= channel 5, (CPS5)
0110= channel 6, (CPS6)
0111= channel 7, (CPS7)
(1)
1000= channel 8, (CPS8
1001= channel 9, (CPS9
)
)
(1)
(1)
1010= channel 10, (CPS10
)
(1)
1011= channel 11, (CPS11
1100= channel 12, (CPS12
1101= channel 13, (CPS13
1110= channel 14, (CPS14
1111= channel 15, (CPS15
)
(1)
(1)
(1)
(1)
)
)
)
)
Note 1: These channels are not implemented on the PIC16F1933/1936/1938/PIC16LF1933/1936/1938.
2: This bit is not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938, read as ‘0’
TABLE 18-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
—
—
—
—
ANSA5
ANSB5
ANSD5
TMR0IE
ANSA4
ANSB4
ANSD4
INTE
ANSA3
ANSB3
ANSD3
IOCIE
ANSA2
ANSB2
ANSD2
TMR0IF
ANSA1
ANSB1
ANSD1
INTF
ANSA0
ANSB0
ANSD0
IOCIF
86
91
ANSELB
ANSELD
INTCON
ANSD7
GIE
ANSD6
PEIE
97
73
OPTION_REG WPUEN
INTEDG
ADIE
TMR0CS
RCIE
TMR0SE
TXIE
PSA
PS2
PS1
PS0
51
PIE1
TMR1GIE
TMR1GIF
SSPIE
SSPIF
CCP1IE
CCP1IF
TMR2IE
TMR2IF
TMR1IE
TMR1IF
74
PIR1
ADIF
RCIF
TXIF
77
T1CON
TxCON
TRISA
TRISB
TRISD
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
—
TMR1ON
169
175
86
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMRXON TXCKPS1 TXCKPS0
TRISA7
TRISB7
TRISD7
TRISA6
TRISB6
TRISD6
TRISA5
TRISB5
TRISD5
TRISA4
TRISB4
TRISD4
TRISA3
TRISB3
TRISD3
TRISA2
TRISB2
TRISD2
TRISA1
TRISB1
TRISD1
TRISA0
TRISB0
TRISD0
91
97
Legend: -= Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the capacitive
sensing module.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 181
PIC16F193X/LF193X
NOTES:
DS41364A-page 182
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
19.0 CAPTURE/COMPARE/PWM
MODULES (ECCP1, ECCP2,
ECCP3, CCP4, CCP5)
This
device
contains
three
Enhanced
Capture/Compare/PWM (ECCP1, ECCP2, ECCP3)
and two standard Capture/Compare/PWM module
(CCP4 and CCP5). The CCP4 and CCP5 modules are
identical in operation. The ECCP1, ECCP2 and ECCP3
modules may also be referred to as CCP1, CCP2,
CCP3, as required.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 183
PIC16F193X/LF193X
TABLE 19-1: REQUIRED TIMER
RESOURCES
19.1 Capture/Compare/PWM
The Capture/Compare/PWM module is a peripheral
which allows the user to time and control different
events. In Capture mode, the peripheral allows the
timing of the duration of an event. The Compare mode
allows the user to trigger an external event when a
predetermined amount of time has expired. The PWM
mode can generate a Pulse-Width Modulated signal of
varying frequency and duty cycle.
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2 or 4 or 6
Table 19-1 shows the timer resources required by the
CCP module.
REGISTER 19-1: CCPXCON: CCPX CONTROL REGISTER
R/W-00
R/W-0/0
R/W-0/0
DCxB1
R/W-0/0
DCxB0
R/W-0/0
CCPxM3
R/W-0/0
CCPxM2
R/W-0/0
CCPxM1
R/W-0/0
CCPxM0
(1)
(1)
PxM1
PxM0
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Reset
(1)
bit 7-6
PxM<1:0>: Enhanced PWM Output Configuration bits
If CCPxM<3:2> = 00, 01, 10:
xx= PxA assigned as Capture/Compare input; PxB, PxC, PxD assigned as port pins
If CCPxM<3:2> = 11:
00= Single output; PxA modulated; PxB, PxC, PxD assigned as port pins
01= Full-Bridge output forward; P1D modulated; P1A active; P1B, P1C inactive
10= Half-Bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins
11= Full-Bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive
bit 5-4
DCxB<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0
CCPxM<3:0>: ECCPx Mode Select bits
0000= Capture/Compare/PWM off (resets ECCPx module)
0001= Reserved
0010= Compare mode: toggle output on match
0011= Capture mode
0100= Capture mode: every falling edge
0101= Capture mode: every rising edge
0110= Capture mode: every 4th rising edge
0111= Capture mode: every 16th rising edge
1000= Compare mode: initialize ECCPx pin low; set output on compare match (set CCPxIF)
1001= Compare mode: initialize ECCPx pin high; clear output on compare match (set CCPxIF)
1010= Compare mode: generate software interrupt only; ECCPx pin reverts to I/O state
1011= Compare mode: trigger special event (ECCPx resets TMR1 or TMR3, sets CCPxIF bit, ECCP2
(1)
trigger also starts A/D conversion if A/D module is enabled)
CCP<5:4> only:
11xx= PWM mode
ECCP<3:1> only:
1100= PWM mode: PxA, PxC active-high; PxB, PxD active-high
1101= PWM mode: PxA, PxC active-high; PxB, PxD active-low
1110= PWM mode: PxA, PxC active-low; PxB, PxD active-high
1111= PWM mode: PxA, PxC active-low; PxB, PxD active-low
Note 1: These bits are not implemented on CCP<5:4>.
DS41364A-page 184
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
timers with auto-reload (Timer2, Timer4 and Timer6),
PWM mode on the CCP modules can use any of these
timers.
19.2 CCP Clock Selection
The PIC16F193X/LF193X allows each individual CCP
module to select the timer source that controls the CCP
module. Each module has an independent selection.
The following registers are used to select which timer is
used:
As the PIC16F193X/LF193X has only one 16-bit timer
(Timer1), the Capture and Compare modes of the CCP
modules always uses Timer1. As there are three 8-bit
• CCP Timers Control Register 0 (CCPTMRS0)
• CCP Timers Control Register 1 (CCPTMRS1)
REGISTER 19-2: CCPTMRS0: CCP TIMERS CONTROL REGISTER 0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
C4TSEL1
C4TSEL0
C3TSEL1
C3TSEL0
C2TSEL1
C2TSEL0
C1TSEL1
C1TSEL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-4
bit 3-2
bit 1-0
C4TSEL<1:0>: CCP4 Timer Selection
00= CCP4 is based off Timer 2 in PWM Mode
01= CCP4 is based off Timer 4 in PWM Mode
10= CCP4 is based off Timer 6 in PWM Mode
11= Reserved
C3TSEL<1:0>: CCP3 Timer Selection
00= CCP3 is based off Timer 2 in PWM Mode
01= CCP3 is based off Timer 4 in PWM Mode
10= CCP3 is based off Timer 6 in PWM Mode
11= Reserved
C2TSEL<1:0>: CCP2 Timer Selection
00= CCP2 is based off Timer 2 in PWM Mode
01= CCP2 is based off Timer 4 in PWM Mode
10= CCP2 is based off Timer 6 in PWM Mode
11= Reserved
C1TSEL<1:0>: CCP1 Timer Selection
00= CCP1 is based off Timer 2 in PWM Mode
01= CCP1 is based off Timer 4 in PWM Mode
10= CCP1 is based off Timer 6 in PWM Mode
11= Reserved
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 185
PIC16F193X/LF193X
REGISTER 19-3: CCPTMRS1: CCP TIMERS CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
C5TSEL1
C5TSEL0
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
bit 1-0
Unimplemented: Read as ‘0’
C5TSEL<1:0>: CCP5 Timer Selection
00= CCP5 is based off Timer 2 in PWM Mode
01= CCP5 is based off Timer 4 in PWM Mode
10= CCP5 is based off Timer 6 in PWM Mode
11= Reserved
DS41364A-page 186
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
19.3.2
TIMER1 MODE SELECTION
19.3 Capture Mode
Timer1 must be running in Timer mode or Synchronized
Counter mode for the CCP module to use the capture
feature. In Asynchronous Counter mode, the capture
operation may not work.
In Capture mode, the CCPRxH, CCPRxL register pair
captures the 16-bit value of the TMR1 register when an
event occurs on pin CCPx. An event is defined as one
of the following and is configured by the CCPxM<3:0>
bits of the CCPxCON register:
19.3.3
SOFTWARE INTERRUPT MODE
• Every falling edge
• Every rising edge
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIEx register clear to
avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIRx register
following any change in Operating mode.
• Every 4th rising edge
• Every 16th rising edge
When a capture is made, the Interrupt Request Flag bit
CCPxIF of the PIRx register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPRxH, CCPRxL register pair
is read, the old captured value is overwritten by the new
captured value (see Figure 19-1).
Note:
Clocking Timer1 from the system clock
(FOSC) should not be used in Capture
mode. In order for Capture mode to
recognize the trigger event on the CCPx
pin, TImer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
19.3.1
CCPX PIN CONFIGURATION
In Capture mode, the CCPx pin should be configured
as an input by setting the associated TRIS control bit.
19.3.4
CCP PRESCALER
Also, the CCPx pin function can be moved to
alternative pins using the APFCON register. Refer to
Section 6.1 “Alternate Pin Function” for more
details.
There are four prescaler settings specified by the
CCPxM<3:0> bits of the CCPxCON register. Whenever
the CCP module is turned off, or the CCP module is not
in Capture mode, the prescaler counter is cleared. Any
Reset will clear the prescaler counter.
Note:
If the CCPx pin is configured as an output,
a write to the port can cause a capture
condition.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCPxCON register before changing the
prescaler (see Example 19-1).
FIGURE 19-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Set Flag bit CCPxIF
(PIRx register)
EXAMPLE 19-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
Prescaler
÷ 1, 4, 16
BANKSELCCP1CON
;Set Bank bits to point
;to CCP1CON
CCPx
pin
CCPRxH
CCPRxL
CLRF
MOVLW
CCP1CON
;Turn CCP module off
Capture
Enable
and
Edge Detect
NEW_CAPT_PS;Load the W reg with
;the new prescaler
TMR1H
TMR1L
;move value and CCP ON
CCPxCON<3:0>
System Clock (FOSC)
MOVWF
CCP1CON
;Load CCP1CON with this
;value
19.3.5
CAPTURE DURING SLEEP
Capture mode depends upon the Timer1 module for
proper operation. There are two options for driving the
Timer1 module in Capture mode. It can be driven by the
instruction clock (FOSC/4), or by an external clock source.
If Timer1 is clocked by FOSC/4, then Timer1 will not
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
If Timer1 is clocked by an external clock source, then
Capture mode will operate as defined in Section 19.1
“Capture/Compare/PWM”.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 187
PIC16F193X/LF193X
TABLE 19-2: REGISTERS ASSOCIATED WITH CAPTURE
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
(1)
CCPxCON
CCPRxL
CCPRxH
CM1CON0
CM1CON1
CM2CON0
CM2CON1
INTCON
PIE1
PxM1
PxM0
DCxB1
DCxB0
CCPxM3
CCPxM2 CCPxM1 CCPxM0
184
187
187
148
149
148
149
73
Capture/Compare/PWM Register x Low Byte (LSB)
Capture/Compare/PWM Register x High Byte (MSB)
C1ON
C1INTP
C2ON
C2INTP
GIE
C1OUT
C1INTN
C2OUT
C2INTN
PEIE
C1OE
C1PCH1 C1PCH0
C2OE C2POL
C2PCH1 C2PCH0
C1POL
—
—
C1SP
—
C1HYS
C1NCH1 C1NCH0
C2HYS C2SYNC
C2NCH1 C2NCH0
C1SYNC
—
C2SP
—
—
TMR0IE
RCIE
INTE
TXIE
IOCIE
SSPIE
BCLIE
TMR6IE
SSPIF
BCLIF
TMR6IF
T1OSCEN
TMR0IF
CCP1IE
LCDIE
—
INTF
TMR2IE
—
IOCIF
TMR1IE
CCP2IE
—
TMR1GIE
OSFIE
—
ADIE
74
PIE2
C2IE
C1IE
EEIE
75
PIE3
CCP5IE
ADIF
CCP4IE
RCIF
CCP3IE
TXIF
TMR4IE
TMR2IF
—
76
PIR1
TMR1GIF
OSFIF
—
CCP1IF
LCDIF
—
TMR1IF
CCP2IF
—
77
PIR2
C2IF
C1IF
EEIF
78
PIR3
CCP5IF
CCP4IF
CCP3IF
TMR4IF
—
79
T1CON
T1GCON
TMR1L
TMR1H
TRISA
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0
TMR1GE T1GPOL T1GTM
T1SYNC
TMR1ON
T1GSS0
169
170
165
165
86
T1GSPM T1GGO/DONE T1GVAL
T1GSS1
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TRISA7
TRISB7
TRISC7
TRISD7
—
TRISA6
TRISB6
TRISC6
TRISD6
—
TRISA5
TRISB5
TRISC5
TRISD5
—
TRISA4
TRISB4
TRISC4
TRISD4
—
TRISA3
TRISB3
TRISC3
TRISD3
TRISE3
TRISA2
TRISB2
TRISC2
TRISD2
TRISA1
TRISB1
TRISC1
TRISD1
TRISA0
TRISB0
TRISC0
TRISD0
TRISB
91
TRISC
94
TRISD
97
(2)
(2)
(2)
TRISE
TRISE2
TRISE1
TRISE0
101
Legend: – = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the Capture
and Compare.
Note 1: Applies to ECCP modules only.
DS41364A-page 188
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
19.4.2
TIMER1 MODE SELECTION
19.4 Compare Mode
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
In Compare mode, the 16-bit CCPRx register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCPx module may:
• Toggle the CCPx output
• Set the CCPx output
Note:
Clocking Timer1 from the system clock
(FOSC) should not be used in Capture
mode. In order for Capture mode to
recognize the trigger event on the CCPx
pin, TImer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
• Clear the CCPx output
• Generate a Special Event Trigger
• Generate a Software Interrupt
The action on the pin is based on the value of the
CCPxM<3:0> control bits of the CCPxCON register. At
the same time, the interrupt flag CCPxIF bit is set.
19.4.3
SOFTWARE INTERRUPT MODE
All Compare modes can generate an interrupt.
When Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the CCPx module does not
assert control of the CCPx pin (see the CCP1CON
register).
FIGURE 19-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
19.4.4
SPECIAL EVENT TRIGGER
CCPxCON<3:0>
Mode Select
When Special Event Trigger mode is chosen
(CCPxM<3:0> = 1011), the CCPx module does the
following:
Set CCPxIF Interrupt Flag
(PIRx)
4
CCPx
Pin
CCPRxH CCPRxL
Comparator
• Resets Timer1
• Starts an ADC conversion if ADC is enabled
(CCP5 only)
Q
S
R
Output
Logic
Match
The CCPx module does not assert control of the CCPx
pin in this mode (see the CCPxCON register).
TMR1H TMR1L
TRIS
Output Enable
The Special Event Trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPRxH, CCPRxL
register pair. The TMR1H, TMR1L register pair is not
reset until the next rising edge of the Timer1 clock. The
Special Event Trigger output starts an A/D conversion
(if the A/D module is enabled). This feature is only
available on CCP5). This allows the CCPRxH,
CCPRxL register pair to effectively provide a 16-bit
programmable period register for Timer1.
Special Event Trigger
Special Event Trigger will:
•
•
CCP<4:1>: Reset Timer1, but not set interrupt flag bit
TMR1IF.
CCP5: Reset Timer1, but not set interrupt flag bit and set bit
GO/DONE (ADCON0<1>).
19.4.1
CCPX PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the associated TRIS bit.
Note 1: The Special Event Trigger from the CCP
module does not set interrupt flag bit
TMR1IF of the PIR1 register.
Also, the CCPx pin function can be moved to
alternative pins using the APFCON register. Refer to
Section 6.1 “Alternate Pin Function” for more
details.
2: Removing the match condition by
changing the contents of the CCPRxH
and CCPRxL register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1 Reset, will preclude
the Reset from occurring.
Note:
Clearing the CCPxCON register will force
the CCPx compare output latch to the
default low level. This is not the PORT I/O
data latch.
19.4.5
COMPARE DURING SLEEP
The Compare mode is dependent upon the system
clock (FOSC) for proper operation. Since FOSC is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 189
PIC16F193X/LF193X
TABLE 19-3: REGISTERS ASSOCIATED WITH COMPARE
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
(1)
CCPxCON
CCPRxL
CCPRxH
CM1CON0
CM1CON1
CM2CON0
CM2CON1
INTCON
PIE1
PxM1
PxM0
DCxB1
DCxB0
CCPxM3
CCPxM2 CCPxM1 CCPxM0
184
187
187
148
149
148
149
73
Capture/Compare/PWM Register x Low Byte (LSB)
Capture/Compare/PWM Register x High Byte (MSB)
C1ON
C1INTP
C2ON
C2INTP
GIE
C1OUT
C1INTN
C2OUT
C2INTN
PEIE
C1OE
C1PCH1 C1PCH0
C2OE C2POL
C2PCH1 C2PCH0
C1POL
—
—
C1SP
—
C1HYS
C1NCH1 C1NCH0
C2HYS C2SYNC
C2NCH1 C2NCH0
C1SYNC
—
C2SP
—
—
TMR0IE
RCIE
INTE
TXIE
IOCIE
SSPIE
BCLIE
TMR6IE
SSPIF
BCLIF
TMR6IF
T1OSCEN
TMR0IF
CCP1IE
LCDIE
—
INTF
TMR2IE
—
IOCIF
TMR1IE
CCP2IE
—
TMR1GIE
OSFIE
—
ADIE
74
PIE2
C2IE
C1IE
EEIE
75
PIE3
CCP5IE
ADIF
CCP4IE
RCIF
CCP3IE
TXIF
TMR4IE
TMR2IF
—
76
PIR1
TMR1GIF
OSFIF
—
CCP1IF
LCDIF
—
TMR1IF
CCP2IF
—
77
PIR2
C2IF
C1IF
EEIF
78
PIR3
CCP5IF
CCP4IF
CCP3IF
TMR4IF
—
79
T1CON
T1GCON
TMR1L
TMR1H
TRISA
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0
TMR1GE T1GPOL T1GTM
T1SYNC
TMR1ON
T1GSS0
169
170
165
165
86
T1GSPM T1GGO/DONE T1GVAL
T1GSS1
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TRISA7
TRISB7
TRISC7
TRISD7
—
TRISA6
TRISB6
TRISC6
TRISD6
—
TRISA5
TRISB5
TRISC5
TRISD5
—
TRISA4
TRISB4
TRISC4
TRISD4
—
TRISA3
TRISB3
TRISC3
TRISD3
TRISE3
TRISA2
TRISB2
TRISC2
TRISD2
TRISA1
TRISB1
TRISC1
TRISD1
TRISA0
TRISB0
TRISC0
TRISD0
TRISB
91
TRISC
94
TRISD
97
(2)
(2)
(2)
TRISE
TRISE2
TRISE1
TRISE0
101
Legend: – = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the Capture
and Compare.
Note 1: Applies to ECCP modules only.
2: These bits are not implemented on PIC16F1933/1936/1938/PIC16LF1933/1936/1938 devices, read as ‘0’.
DS41364A-page 190
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 19-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
19.5 PWM Mode
The PWM mode generates a Pulse-Width Modulated
signal on the CCPx pin. The duty cycle, period and
resolution are determined by the following registers:
CCPxCON<5:4>
Duty Cycle Registers
CCPRxL
• PRx
• TxCON
• CCPRxL
• CCPxCON
CCPRxH(2) (Slave)
Comparator
CCPx
The ECCP modules have the following additional
registers:
R
S
Q
• ECCPxAS
• PSTRxCON
• PWMxCON
(1)
TMRx
TRIS
In Pulse-Width Modulation (PWM) mode, the CCPx
module produces up to a 10-bit resolution PWM output
on the CCPx pin. Since the CCPx pin is multiplexed
with the PORT data latch, the TRIS for that pin must be
cleared to enable the CCPx pin output driver.
Comparator
PRx
Clear Timerx,
toggle CCPx pin and
latch duty cycle
Note 1: The 8-bit timer TMR2 register is concatenated
with the 2-bit internal system clock (FOSC), or
2 bits of the prescaler, to create the 10-bit time
base.
Note:
Clearing the CCPxCON register will
relinquish CCPx control of the CCPx pin.
The CCPx module in PWM mode can have the PWM
based off of either Timer2, Timer4 or TImer6. This is
controlled by the CCPTMRS0 and CCPTMRS1
registers. Reference Section 19.2 “CCP Clock
Selection” for more information.
2: In PWM mode, CCPRxH is a read-only register.
The PWM output (Figure 19-4) has a time base
(period) and a time that the output stays high (duty
cycle).
Figure 19-3 shows a simplified block diagram of PWM
operation.
FIGURE 19-4:
CCP PWM OUTPUT
Figure 19-4 shows a typical waveform of the PWM
signal.
Period
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 19.5.7
“Setup for PWM Operation”.
Pulse Width
TMRx = PRx
TMRx\2 = CCPRxH:CCPxCON<5:4>
TMRX = 0
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 191
PIC16F193X/LF193X
19.5.1
PWM PERIOD
19.5.2
PWM DUTY CYCLE
The PWM period is specified by the PRx register of
Timerx. The PWM period can be calculated using the
formula of Equation 19-1.
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPRxL register and
DCxB<1:0> bits of the CCPxCON register. The
CCPRxL contains the eight MSbs and the DCxB<1:0>
bits of the CCPxCON register contain the two LSbs.
CCPRxL and DCxB<1:0> bits of the CCPxCON
register can be written to at any time. The duty cycle
value is not latched into CCPRxH until after the period
completes (i.e., a match between PRx and TMRx
registers occurs). While using the PWM, the CCPRxH
register is read-only.
EQUATION 19-1: PWM PERIOD
PWM Period = [(PR2x) + 1] • 4 • TOSC •
(TMRx Prescale Value)
Note 1: TOSC = 1/FOSC
Equation 19-2 is used to calculate the PWM pulse
width.
When TMRx is equal to PRx, the following three events
occur on the next increment cycle:
Equation 19-3 is used to calculate the PWM duty cycle
ratio.
• TMRx is cleared
• The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
EQUATION 19-2: PULSE WIDTH
• The PWM duty cycle is latched from CCPRxL into
CCPRxH.
Pulse Width = (CCPRxL:CCPxCON<5:4>) •
TOSC • (TMRx Prescale Value)
Note:
The Timerx postscaler (see Section 17.1
“Timer2/4/6 Operation”) is not used in the
determination of the PWM frequency.
EQUATION 19-3: DUTY CYCLE RATIO
(CCPRxL:CCPxCON<5:4>)
Duty Cycle Ratio = ----------------------------------------------------------------------
4(PRx + 1)
The CCPRxH register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
The 8-bit timer TMRx register is concatenated with either
the 2-bit internal system clock (FOSC), or 2 bits of the
prescaler, to create the 10-bit time base. The system
clock is used if the Timerx prescaler is set to 1:1.
When the 10-bit time base matches the CCPRxH and
2-bit latch, then the CCPx pin is cleared (see
Figure 19-3).
DS41364A-page 192
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
19.5.3
PWM RESOLUTION
EQUATION 19-4: PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
log[4(PRx + 1)]
Resolution = ----------------------------------------- bits
log(2)
The maximum PWM resolution is 10 bits when PRx is
255. The resolution is a function of the PRx register
value as shown by Equation 19-4.
Note:
If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
TABLE 19-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 32 MHz)
PWM Frequency
1.95 kHz
7.81 kHz
31.25 kHz
125 kHz
250 kHz
333.3 kHz
Timer Prescale (1, 4, 16)
PRx Value
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
0xFF
10
0xFF
10
0x17
6.6
Maximum Resolution (bits)
TABLE 19-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
Timer Prescale (1, 4, 16)
PRx Value
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
0xFF
10
0xFF
10
0x17
6.6
Maximum Resolution (bits)
TABLE 19-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz 200.0 kHz
Timer Prescale (1, 4, 16)
PRx Value
16
0x65
8
4
0x65
8
1
0x65
8
1
0x19
6
1
0x0C
5
1
0x09
5
Maximum Resolution (bits)
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 193
PIC16F193X/LF193X
19.5.4
OPERATION IN SLEEP MODE
19.5.7
SETUP FOR PWM OPERATION
In Sleep mode, the TMRx register will not increment
and the state of the module will not change. If the CCPx
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMRx will continue from its
previous state.
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Disable the PWM pin (CCPx) output driver(s) by
setting the associated TRIS bit(s).
2. Load the PRx register with the PWM period value.
3. Configure the CCP module for the PWM mode
by loading the CCPxCON register with the
appropriate values.
19.5.5
CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 8.0 “Oscillator Module (With Fail-Safe
Clock Monitor)” for additional details.
4. Load the CCPRxL register and the DCxBx bits of
the CCPxCON register, with the PWM duty cycle
value.
5. Configure and start Timerx:
• Clear the TMRxIF interrupt flag bit of the PIRx
register. See Note below.
19.5.6
EFFECTS OF RESET
• Configure the TxCKPS bits of the TxCON
register with the Timerx prescale value.
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
• Enable Timerx by setting the TMRxON bit of
the T2CON register.
6. Enable PWM output pin:
• Wait until Timerx overflows, TMRxIF bit of the
PIR1 register is set. See Note below.
• Enable the PWM pin (CCPx) output driver(s) by
clearing the associated TRIS bit(s).
Note:
In order to send a complete duty cycle and
period on the first PWM output, the above
steps must be included in the setup
sequence. If it is not critical to start with a
complete PWM signal on the first output,
then step 6 may be ignored.
DS41364A-page 194
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
The PWM outputs are multiplexed with I/O pins and are
designated P1A, P1B, P1C and P1D. The polarity of the
PWM pins is configurable and is selected by setting the
CCP1M bits in the CCP1CON register appropriately.
19.6 PWM (Enhanced Mode)
The Enhanced PWM mode can generate a PWM signal
on up to four different output pins with up to 10-bits of
resolution. It can do this through four different PWM
output modes:
Table 19-7 shows the pin assignments for each
Enhanced PWM mode.
• Single PWM
Figure 19-5 shows an example of a simplified block
diagram of the Enhanced PWM module.
• Half-Bridge PWM
• Full-Bridge PWM, Forward mode
• Full-Bridge PWM, Reverse mode
Note:
To prevent the generation of an
incomplete waveform when the PWM is
first enabled, the ECCP module waits until
the start of a new PWM period before
generating a PWM signal.
To select an Enhanced PWM mode, the P1M bits of the
CCP1CON register must be set appropriately.
Note:
The PWM Enhanced mode is available on
the Enhanced Capture/Compare/PWM
module (CCP1) only.
FIGURE 19-5:
EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
DCxB<1:0>
PxM<1:0>
CCPxM<3:0>
4
Duty Cycle Registers
2
CCPRxL
CCPx/P1A
CCPx/P1A
P1B
TRISx
TRISx
TRISx
TRISx
CCPRxH (Slave)
Comparator
P1B
Output
Controller
R
S
Q
P1C
P1C
(1)
TMRx
P1D
P1D
Comparator
PRx
Clear Timerx,
toggle PWM pin and
latch duty cycle
PWMxCON
Note 1: The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit
time base.
Note 1: The TRIS register value for each PWM output must be configured appropriately.
2: Clearing the CCPxCON register will relinquish ECCP control of all PWM output pins.
3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.
TABLE 19-7: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES
ECCP Mode
PxM<1:0>
CCPx/P1A
P1B
P1C
P1D
Single
00
10
01
11
Yes(1)
Yes
Yes(1)
Yes
Yes(1)
No
Yes(1)
No
Half-Bridge
Full-Bridge, Forward
Full-Bridge, Reverse
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Note 1: Pulse Steering enables outputs in Single mode.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 195
PIC16F193X/LF193X
FIGURE 19-6:
EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH
STATE)
PRX+1
Pulse
Width
0
Signal
PxM<1:0>
Period
P1A Modulated
(Single Output)
00
10
Delay(1)
Delay(1)
P1A Modulated
P1B Modulated
P1A Active
(Half-Bridge)
P1B Inactive
(Full-Bridge,
Forward)
01
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
(Full-Bridge,
Reverse)
11
P1D Inactive
Relationships:
•
•
•
Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)
Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)
Delay = 4 * TOSC * (PWMxCON<6:0>)
Note 1: Dead-band delay is programmed using the PWMxCON register (Section 19.6.6 “Programmable Dead-Band Delay
Mode”).
DS41364A-page 196
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 19-7:
EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
PRx+1
Pulse
Width
0
Signal
PxM<1:0>
Period
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
(Single Output)
00
10
Delay(1)
Delay(1)
(Half-Bridge)
(Full-Bridge,
Forward)
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
01
(Full-Bridge,
Reverse)
11
P1D Inactive
Relationships:
•
•
•
Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)
Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)
Delay = 4 * TOSC * (PWMxCON<6:0>)
Note 1: Dead-band delay is programmed using the PWMxCON register (Section 19.6.6 “Programmable Dead-Band Delay
Mode”).
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 197
PIC16F193X/LF193X
Since the P1A and P1B outputs are multiplexed with
the PORT data latches, the associated TRIS bits must
be cleared to configure P1A and P1B as outputs.
19.6.1
HALF-BRIDGE MODE
In Half-Bridge mode, two pins are used as outputs to
drive push-pull loads. The PWM output signal is output
on the CCPx/P1A pin, while the complementary PWM
output signal is output on the P1B pin (see
Figure 19-9). This mode can be used for Half-Bridge
applications, as shown in Figure 19-9, or for Full-Bridge
applications, where four power switches are being
modulated with two PWM signals.
FIGURE 19-8:
EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
Period
Period
Pulse Width
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in
Half-Bridge power devices. The value of the PDC<6:0>
bits of the PWMxCON register sets the number of
instruction cycles before the output is driven active. If the
value is greater than the duty cycle, the corresponding
output remains inactive during the entire cycle. See
Section 19.6.6 “Programmable Dead-Band Delay
Mode” for more details of the dead-band delay
operations.
(2)
(2)
P1A
td
td
P1B
(1)
(1)
(1)
td = Dead-Band Delay
Note 1: At this time, the TMRx register is equal to the
PRx register.
2: Output signals are shown as active-high.
FIGURE 19-9:
EXAMPLE OF HALF-BRIDGE APPLICATIONS
Standard Half-Bridge Circuit (“Push-Pull”)
FET
Driver
+
-
P1A
Load
FET
Driver
+
-
P1B
Half-Bridge Output Driving a Full-Bridge Circuit
V+
FET
Driver
FET
Driver
P1A
Load
FET
FET
Driver
Driver
P1B
DS41364A-page 198
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
19.6.2
FULL-BRIDGE MODE
In Full-Bridge mode, all four pins are used as outputs.
An example of Full-Bridge application is shown in
Figure 19-10.
In the Forward mode, pin CCPx/P1A is driven to its active
state, pin P1D is modulated, while P1B and P1C will be
driven to their inactive state as shown in Figure 19-11.
In the Reverse mode, P1C is driven to its active state,
pin P1B is modulated, while P1A and P1D will be driven
to their inactive state as shown Figure 19-11.
P1A, P1B, P1C and P1D outputs are multiplexed with
the PORT data latches. The associated TRIS bits must
be cleared to configure the P1A, P1B, P1C and P1D
pins as outputs.
FIGURE 19-10:
EXAMPLE OF FULL-BRIDGE APPLICATION
V+
QC
QA
FET
Driver
FET
Driver
P1A
P1B
Load
FET
Driver
FET
Driver
P1C
P1D
QD
QB
V-
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 199
PIC16F193X/LF193X
FIGURE 19-11:
EXAMPLE OF FULL-BRIDGE PWM OUTPUT
Forward Mode
Period
(2)
P1A
Pulse Width
(2)
P1B
(2)
P1C
(2)
P1D
(1)
(1)
Reverse Mode
Period
Pulse Width
(2)
P1A
(2)
P1B
(2)
P1C
(2)
P1D
(1)
(1)
Note 1: At this time, the TMRx register is equal to the PRx register.
2: Output signal is shown as active-high.
DS41364A-page 200
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
The Full-Bridge mode does not provide dead-band
delay. As one output is modulated at a time, dead-band
delay is generally not required. There is a situation
where dead-band delay is required. This situation
occurs when both of the following conditions are true:
19.6.2.1
Direction Change in Full-Bridge
Mode
In the Full-Bridge mode, the PxM1 bit in the CCPxCON
register allows users to control the forward/reverse
direction. When the application firmware changes this
direction control bit, the module will change to the new
direction on the next PWM cycle.
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn off time of the power switch, including
the power device and driver circuit, is greater
than the turn on time.
A direction change is initiated in software by changing
the PxM1 bit of the CCPxCON register. The following
sequence occurs four Timerx cycles prior to the end of
the current PWM period:
Figure 19-13 shows an example of the PWM direction
changing from forward to reverse, at a near 100% duty
cycle. In this example, at time t1, the output P1A and
P1D become inactive, while output P1C becomes
active. Since the turn off time of the power devices is
longer than the turn on time, a shoot-through current
will flow through power devices QC and QD (see
Figure 19-10) for the duration of ‘t’. The same
phenomenon will occur to power devices QA and QB
for PWM direction change from reverse to forward.
• The modulated outputs (P1B and P1D) are placed
in their inactive state.
• The associated unmodulated outputs (P1A and
P1C) are switched to drive in the opposite
direction.
• PWM modulation resumes at the beginning of the
next period.
See Figure 19-12 for an illustration of this sequence.
If changing PWM direction at high duty cycle is required
for an application, two possible solutions for eliminating
the shoot-through current are:
1. Reduce PWM duty cycle for one PWM period
before changing directions.
2. Use switch drivers that can drive the switches off
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
FIGURE 19-12:
EXAMPLE OF PWM DIRECTION CHANGE
(1)
Period
Period
Signal
P1A (Active-High)
P1B (Active-High)
Pulse Width
P1C (Active-High)
P1D (Active-High)
(2)
Pulse Width
Note 1: The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The
modulated P1B and P1D signals are inactive at this time. The length of this time is four Timerx counts.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 201
PIC16F193X/LF193X
FIGURE 19-13:
EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
Forward Period
Reverse Period
t1
P1A
P1B
PW
P1C
P1D
PW
TON
External Switch C
External Switch D
TOFF
Potential
T = TOFF – TON
Shoot-Through Current
Note 1: All signals are shown as active-high.
2: TON is the turn on delay of power switch QC and its driver.
3: TOFF is the turn off delay of power switch QD and its driver.
DS41364A-page 202
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
The enabled PWM pins are asynchronously placed in
their shutdown states. The PWM output pins are
grouped into pairs [P1A/P1C] and [P1B/P1D]. The state
of each pin pair is determined by the PSSxAC and
PSSxBD bits of the CCPxAS register. Each pin pair may
be placed into one of three states:
19.6.3
START-UP CONSIDERATIONS
When any PWM mode is used, the application
hardware must use the proper external pull-up and/or
pull-down resistors on the PWM output pins.
Note:
When the microcontroller is released from
Reset, all of the I/O pins are in the
high-impedance state. The external cir-
cuits must keep the power switch devices
in the Off state until the microcontroller
drives the I/O pins with the proper signal
levels or activates the PWM output(s).
• Drive logic ‘1’
• Drive logic ‘0’
• Tri-state (high-impedance)
The CCPxM<1:0> bits of the CCPxCON register allow
the user to choose whether the PWM output signals are
active-high or active-low for each pair of PWM output pins
(P1A/P1C and P1B/P1D). The PWM output polarities
must be selected before the PWM pin output drivers are
enabled. Changing the polarity configuration while the
PWM pin output drivers are enable is not recommended
since it may result in damage to the application circuits.
The P1A, P1B, P1C and P1D output latches may not be
in the proper states when the PWM module is
initialized. Enabling the PWM pin output drivers at the
same time as the Enhanced PWM modes may cause
damage to the application circuit. The Enhanced PWM
modes must be enabled in the proper Output mode and
complete a full PWM cycle before enabling the PWM
pin output drivers. The completion of a full PWM cycle
is indicated by the TMRxIF bit of the PIRx register
being set as the second PWM period begins.
19.6.4
ENHANCED PWM
AUTO-SHUTDOWN MODE
The PWM mode supports an Auto-Shutdown mode that
will disable the PWM outputs when an external
shutdown event occurs. Auto-Shutdown mode places
the PWM output pins into a predetermined state. This
mode is used to help prevent the PWM from damaging
the application.
The auto-shutdown sources are selected using the
CCPxAS<2:0> bits of the CCPxAS register. A shutdown
event may be generated by:
• A logic ‘0’ on the INT pin
• Comparator Cx
• Setting the CCPxASE bit in firmware
A shutdown condition is indicated by the CCPxASE
(Auto-Shutdown Event Status) bit of the CCPxAS
register. If the bit is a ‘0’, the PWM pins are operating
normally. If the bit is a ‘1’, the PWM outputs are in the
shutdown state.
When a shutdown event occurs, two things happen:
The CCPxASE bit is set to ‘1’. The CCPxASE will
remain set until cleared in firmware or an auto-restart
occurs (see Section 19.6.5 “Auto-Restart Mode”).
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 203
PIC16F193X/LF193X
REGISTER 19-4: CCPXAS: CCPX AUTO-SHUTDOWN CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CCPxASE
CCPxAS2
CCPxAS1
CCPxAS0
PSSxAC1
PSSxAC0
PSSxBD1
PSSxBD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
CCPxASE: CCPx Auto-Shutdown Event Status bit
1= A shutdown event has occurred; CCPx outputs are in shutdown state
0= CCPx outputs are operating
bit 6-4
CCxPAS<2:0>: CCPx Auto-Shutdown Source Select bits
000= Auto-shutdown is disabled
001= Comparator C1 output low(1)
010= Comparator C2 output low(1)
011= Either Comparator C1 or C2 low(1)
100= VIL on INT pin
101= VIL on INT pin or Comparator C1 low(1)
110= VIL on INT pin or Comparator C2 low(1)
111= VIL on INT pin or Comparator C1 or Comparator C2 low(1)
bit 3-2
bit 1-0
PSSxACx: Pins P1A and P1C Shutdown State Control bits
00= Drive pins P1A and P1C to ‘0’
01= Drive pins P1A and P1C to ‘1’
1x= Pins P1A and P1C tri-state
PSSxBDx: Pins P1B and P1D Shutdown State Control bits
00= Drive pins P1B and P1D to ‘0’
01= Drive pins P1B and P1D to ‘1’
1x= Pins P1B and P1D tri-state
Note 1: If CxSYNC is enabled, the shutdown will be delayed by Timer1.
Note 1: The auto-shutdown condition is
a
level-based signal, not an edge-based
signal. As long as the level is present, the
auto-shutdown will persist.
2: Writing to the CCPxASE bit is disabled
while an auto-shutdown condition
persists.
3: Once the auto-shutdown condition has
been removed and the PWM restarted
(either through firmware or auto-restart)
the PWM signal will always restart at the
beginning of the next PWM period.
DS41364A-page 204
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 19-14:
PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PXRSEN = 0)
Missing Pulse
(Auto-Shutdown)
Missing Pulse
(CCPxASE not clear)
Timer
Overflow
Timer
Overflow
Timer
Overflow
Timer
Overflow
Timer
Overflow
PWM Period
PWM Activity
Start of
PWM Period
Shutdown Event
CCPxASE bit
PWM
Resumes
Shutdown
Event Occurs
Shutdown
Event Clears
CCPxASE
Cleared by
Firmware
If auto-restart is enabled, the CCPxASE bit will remain
set as long as the auto-shutdown condition is active.
When the auto-shutdown condition is removed, the
CCPxASE bit will be cleared via hardware and normal
operation will resume.
19.6.5
AUTO-RESTART MODE
The Enhanced PWM can be configured to automati-
cally restart the PWM signal once the auto-shutdown
condition has been removed. Auto-restart is enabled by
setting the PxRSEN bit in the PWMxCON register.
FIGURE 19-15:
PWM AUTO-SHUTDOWN WITH AUTO-RESTART (PXRSEN = 1)
Missing Pulse
(Auto-Shutdown)
Missing Pulse
(CCPxASE not clear)
Timer
Overflow
Timer
Overflow
Timer
Overflow
Timer
Overflow
Timer
Overflow
PWM Period
PWM Activity
Start of
PWM Period
Shutdown Event
CCPxASE bit
PWM
Resumes
Shutdown
Event Occurs
Shutdown
Event Clears
CCPxASE
Cleared by
Hardware
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 205
PIC16F193X/LF193X
19.6.6
PROGRAMMABLE DEAD-BAND
DELAY MODE
FIGURE 19-16:
EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
In Half-Bridge applications where all power switches
are modulated at the PWM frequency, the power
switches normally require more time to turn off than to
turn on. If both the upper and lower power switches are
switched at the same time (one turned on, and the
other turned off), both switches may be on for a short
period of time until one switch completely turns off.
Period
Period
Pulse Width
(2)
(2)
P1A
td
td
During this brief interval,
a very high current
P1B
(shoot-through current) will flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from
flowing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
(1)
(1)
(1)
td = Dead-Band Delay
Note 1: At this time, the TMRx register is equal to the
PRx register.
In Half-Bridge mode,
a
digitally programmable
2: Output signals are shown as active-high.
dead-band delay is available to avoid shoot-through
current from destroying the bridge power switches. The
delay occurs at the signal transition from the non-active
state to the active state. See Figure 19-16 for
illustration. The lower seven bits of the associated
PWMxCON register (Register 19-5) sets the delay
period in terms of microcontroller instruction cycles
(TCY or 4 TOSC).
FIGURE 19-17:
EXAMPLE OF HALF-BRIDGE APPLICATIONS
V+
Standard Half-Bridge Circuit (“Push-Pull”)
FET
Driver
+
V
-
P1A
Load
FET
Driver
+
V
-
P1B
V-
DS41364A-page 206
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
REGISTER 19-5: PWMxCON: ENHANCED PWM CONTROL REGISTER
R/W-0/0
PxRSEN
R/W-0/0
PxDC6
R/W-0/0
PxDC5
R/W-0/0
PxDC4
R/W-0/0
PxDC3
R/W-0/0
PxDC2
R/W-0/0
PxDC1
R/W-0/0
PxDC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
PxRSEN: PWM Restart Enable bit
1= Upon auto-shutdown, the CCPxASE bit clears automatically once the shutdown event goes away;
the PWM restarts automatically
0= Upon auto-shutdown, CCPxASE must be cleared in software to restart the PWM
bit 6-0
PxDC<6:0>: PWM Delay Count bits
PxDCx = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal
should transition active and the actual time it transitions active
Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 207
PIC16F193X/LF193X
19.6.7
PULSE STEERING MODE
In Single Output mode, pulse steering allows any of the
PWM pins to be the modulated signal. Additionally, the
same PWM signal can be simultaneously available on
multiple pins.
Note:
The associated TRIS bits must be set to
output (‘0’) to enable the pin output driver
in order to see the PWM signal on the pin.
While the PWM Steering mode is active, CCPxM<1:0>
bits of the CCPxCON register select the PWM output
polarity for the P1<D:A> pins.
Once the Single Output mode is selected
(CCPxM<3:2> = 11 and PxM<1:0> = 00 of the
CCPxCON register), the user firmware can bring out
the same PWM signal to one, two, three or four output
pins by setting the appropriate STRx<D:A> bits of the
PSTRxCON register, as shown in Table 19-7.
The PWM auto-shutdown operation also applies to
PWM Steering mode as described in Section 19.6.4
“Enhanced PWM Auto-shutdown mode”. An
auto-shutdown event will only affect pins that have
PWM outputs enabled.
REGISTER 19-6: PSTRXCON: PULSE STEERING CONTROL REGISTER(1)
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
STRxD
R/W-0/0
STRxC
R/W-0/0
STRxB
R/W-1/1
STRxA
STRxSYNC
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-5
bit 4
Unimplemented: Read as ‘0’
STRxSYNC: Steering Sync bit
1= Output steering update occurs on next PWM period
0= Output steering update occurs at the beginning of the instruction cycle boundary
bit 3
bit 2
bit 1
bit 0
STRxD: Steering Enable bit D
1= P1D pin has the PWM waveform with polarity control from CCPxM<1:0>
0= P1D pin is assigned to port pin
STRxC: Steering Enable bit C
1= P1C pin has the PWM waveform with polarity control from CCPxM<1:0>
0= P1C pin is assigned to port pin
STRxB: Steering Enable bit B
1= P1B pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = P1B pin is assigned to port pin
STRxA: Steering Enable bit A
1= P1A pin has the PWM waveform with polarity control from CCPxM<1:0>
0= P1A pin is assigned to port pin
Note 1: The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2> = 11and
PxM<1:0> = 00.
DS41364A-page 208
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 19-18:
SIMPLIFIED STEERING
BLOCK DIAGRAM
STRxA
P1A Signal
CCPxM1
P1A pin
1
PORT Data
STRxB
0
TRIS
P1B pin
CCPxM0
1
PORT Data
STRxC
0
TRIS
P1C pin
1
CCPxM1
PORT Data
0
TRIS
STRxD
P1D pin
1
CCPxM0
PORT Data
0
TRIS
Note 1: Port outputs are configured as shown when
the CCPxCON register bits PxM<1:0> = 00
and CCPxM<3:2> = 11.
2: Single PWM output requires setting at least
one of the STRx bits.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 209
PIC16F193X/LF193X
Figures 19-19 and 19-20 illustrate the timing diagrams
of the PWM steering depending on the STRXSYNC
setting.
19.6.7.1
Steering Synchronization
The STRxSYNC bit of the PSTRxCON register gives
the user two selections of when the steering event will
happen. When the STRxSYNC bit is ‘0’, the steering
event will happen at the end of the instruction that
writes to the PSTRxCON register. In this case, the
output signal at the P1<D:A> pins may be an
incomplete PWM waveform. This operation is useful
when the user firmware needs to immediately remove
a PWM signal from the pin.
When the STRxSYNC bit is ‘1’, the effective steering
update will happen at the beginning of the next PWM
period. In this case, steering on/off the PWM output will
always produce a complete PWM waveform.
FIGURE 19-19:
EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRXSYNC = 0)
PWM Period
PWM
STRx
P1<D:A>
PORT Data
PORT Data
P1n = PWM
FIGURE 19-20:
EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION
(STRXSYNC = 1)
PWM
STRx
P1<D:A>
PORT Data
PORT Data
P1n = PWM
DS41364A-page 210
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 19-8: REGISTERS ASSOCIATED WITH PWM
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
(1)
CCPxCON
CCPxAS
PxM1
PxM0
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
CCPxM0
184
204
185
186
73
CCPxASE CCPxAS2 CCPxAS1 CCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0
CCPTMRS0 C4TSEL1
C4TSEL0
—
C3TSEL1
—
C3TSEL0
—
C2TSEL1
—
C2TSEL0
—
C1TSEL1
C5TSEL1
INTF
C1TSEL0
C5TSEL0
IOCIF
CCPTMRS1
INTCON
PRx
—
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
Timerx Period Register
173*
208
207
175
173
91
PSTRxCON
PWMxCON
TxCON
—
PxRSEN
—
—
—
STRxSYNC
PxDC4
STRxD
PxDC3
STRxC
PxDC2
STRxB
PxDC1
STRxA
PxDC0
PxDC6
PxDC5
TxOUTPS3 TxOUTPS2 TxOUTPS1 TxOUTPS0 TMRxON
TxCKPS1 TxCKPS0
TMRx
Timerx Module Register
TRISB
TRISB7
TRISC7
TRISD7
TRISB6
TRISC6
TRISD6
TRISB5
TRISC5
TRISD5
TRISB4
TRISC4
TRISD4
TRISB3
TRISC3
TRISD3
TRISB2
TRISC2
TRISD2
TRISB1
TRISC1
TRISD1
TRISB0
TRISC0
TRISD0
TRISC
94
TRISD
97
Legend: – = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the PWM.
Note 1: Applies to ECCP modules only.
*
Page provides register information.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 211
PIC16F193X/LF193X
NOTES:
DS41364A-page 212
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
The EUSART module includes the following capabilities:
20.0 ENHANCED UNIVERSAL
SYNCHRONOUS
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
• One-character output buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
• Programmable clock polarity in synchronous
modes
• Sleep operation
system.
Full-Duplex
mode
is
useful
for
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
• Automatic detection and calibration of the baud rate
• Wake-up on Break reception
• 13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 20-1 and Figure 20-2.
FIGURE 20-1:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIE
Interrupt
TXIF
TXREG Register
8
TX/CK pin
MSb
(8)
LSb
0
Pin Buffer
and Control
• • •
Transmit Shift Register (TSR)
TXEN
TRMT
SPEN
Baud Rate Generator
BRG16
FOSC
÷ n
TX9
n
+ 1
Multiplier x4
x16 x64
TX9D
SYNC
BRGH
BRG16
1
X
X
X
1
1
0
1
0
0
0
1
0
0
0
SPBRGH
SPBRG
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 213
PIC16F193X/LF193X
FIGURE 20-2:
EUSART RECEIVE BLOCK DIAGRAM
SPEN
CREN
OERR
RCIDL
RX/DT pin
RSR Register
MSb
Stop (8)
LSb
0
START
Pin Buffer
and Control
Data
Recovery
7
1
• • •
Baud Rate Generator
FOSC
RX9
÷ n
BRG16
n
+ 1
Multiplier
x4
x16 x64
SYNC
BRGH
BRG16
1
X
1
1
0
1
0
0
0
1
0
0
0
FIFO
SPBRGH
SPBRG
X
X
RX9D
FERR
RCREG Register
8
Data Bus
RCIF
RCIE
Interrupt
The operation of the EUSART module is controlled
through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCON)
These registers are detailed in Register 20-1,
Register 20-2 and Register 20-3, respectively.
When the receiver or transmitter section is not enabled
then the corresponding RX or TX pin may be used for
general purpose input and output.
DS41364A-page 214
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
20.1.1.2
Transmitting Data
20.1 EUSART Asynchronous Mode
A transmission is initiated by writing a character to the
TXREG register. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXREG is immediately
transferred to the TSR register. If the TSR still contains
all or part of a previous character, the new character
data is held in the TXREG until the Stop bit of the
previous character has been transmitted. The pending
character in the TXREG is then transferred to the TSR
in one TCY immediately following the Stop bit
transmission. The transmission of the Start bit, data bits
and Stop bit sequence commences immediately
following the transfer of the data to the TSR from the
TXREG.
The EUSART transmits and receives data using the
standard non-return-to-zero (NRZ) format. NRZ is
implemented with two levels: a VOH mark state which
represents a ‘1’ data bit, and a VOL space state which
represents a ‘0’ data bit. NRZ refers to the fact that
consecutively transmitted data bits of the same value
stay at the output level of that bit without returning to a
neutral level between each bit transmission. An NRZ
transmission port idles in the mark state. Each character
transmission consists of one Start bit followed by eight
or nine data bits and is always terminated by one or
more Stop bits. The Start bit is always a space and the
Stop bits are always marks. The most common data
format is 8 bits. Each transmitted bit persists for a period
of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud
Rate Generator is used to derive standard baud rate
frequencies from the system oscillator. See Table 20-5
for examples of baud rate configurations.
20.1.1.3
Transmit Interrupt Flag
The TXIF interrupt flag bit of the PIR1 register is set
whenever the EUSART transmitter is enabled and no
character is being held for transmission in the TXREG.
In other words, the TXIF bit is only clear when the TSR
is busy with a character and a new character has been
queued for transmission in the TXREG. The TXIF flag bit
is not cleared immediately upon writing TXREG. TXIF
becomes valid in the second instruction cycle following
the write execution. Polling TXIF immediately following
the TXREG write will return invalid results. The TXIF bit
is read-only, it cannot be set or cleared by software.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent, but share the same data format and baud
rate. Parity is not supported by the hardware, but can
be implemented in software and stored as the ninth
data bit.
20.1.1
EUSART ASYNCHRONOUS
TRANSMITTER
The TXIF interrupt can be enabled by setting the TXIE
interrupt enable bit of the PIE1 register. However, the
TXIF flag bit will be set whenever the TXREG is empty,
regardless of the state of TXIE enable bit.
The EUSART transmitter block diagram is shown in
Figure 20-1. The heart of the transmitter is the serial
Transmit Shift Register (TSR), which is not directly
accessible by software. The TSR obtains its data from
the transmit buffer, which is the TXREG register.
To use interrupts when transmitting data, set the TXIE
bit only when there is more data to send. Clear the
TXIE interrupt enable bit upon writing the last character
of the transmission to the TXREG.
20.1.1.1
Enabling the Transmitter
The EUSART transmitter is enabled for asynchronous
operations by configuring the following three control
bits:
• TXEN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the TXEN bit of the TXSTA register enables the
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART and automatically
configures the TX/CK I/O pin as an output.
Note 1: The TXIF Transmitter Interrupt flag is set
when the TXEN enable bit is set.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 215
PIC16F193X/LF193X
20.1.1.4
TSR Status
20.1.1.6
Asynchronous Transmission Set-up:
The TRMT bit of the TXSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user has to
poll this bit to determine the TSR status.
1. Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the desired
baud rate (see Section 20.3 “EUSART Baud
Rate Generator (BRG)”).
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If 9-bit transmission is desired, set the TX9 con-
trol bit. A set ninth data bit will indicate that the 8
Least Significant data bits are an address when
the receiver is set for address detection.
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
4. Enable the transmission by setting the TXEN
control bit. This will cause the TXIF interrupt bit
to be set.
20.1.1.5
Transmitting 9-Bit Characters
The EUSART supports 9-bit character transmissions.
When the TX9 bit of the TXSTA register is set the
EUSART will shift 9 bits out for each character transmit-
ted. The TX9D bit of the TXSTA register is the ninth,
and Most Significant, data bit. When transmitting 9-bit
data, the TX9D data bit must be written before writing
the 8 Least Significant bits into the TXREG. All nine bits
of data will be transferred to the TSR shift register
immediately after the TXREG is written.
5. If interrupts are desired, set the TXIE interrupt
enable bit of the PIE1 register. An interrupt will
occur immediately provided that the GIE and
PEIE bits of the INTCON register are also set.
6. If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
7. Load 8-bit data into the TXREG register. This
will start the transmission.
A special 9-bit Address mode is available for use with
multiple receivers. See Section 20.1.2.7 “Address
Detection” for more information on the address mode.
FIGURE 20-3:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX/CK
pin
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 20-4:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG
Word 2
Start bit
Word 1
BRG Output
(Shift Clock)
TX/CK
pin
Start bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
Stop bit
1 TCY
Word 1
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 2
Transmit Shift Reg.
Note:
This timing diagram shows two consecutive transmissions.
DS41364A-page 216
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 20-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUDCON
INTCON
PIE1
ABDOVF
GIE
RCIDL
PEIE
—
SCKP
INTE
BRG16
IOCIE
—
WUE
INTF
ABDEN
IOCIF
224
73
TMR0IE
RCIE
TMR0IF
TMR1GIE
TMR1GIF
SPEN
ADIE
ADIF
TXIE
SSPIE
SSPIF
ADDEN
BRG3
CCP1IE TMR2IE TMR1IE
CCP1IF TMR2IF TMR1IF
74
PIR1
RCIF
TXIF
77
RCSTA
SPBRG
SPBRGH
TRISC
RX9
SREN
BRG5
BRG13
CREN
BRG4
BRG12
FERR
BRG2
OERR
BRG1
BRG9
RX9D
BRG0
BRG8
223
225*
225*
94
BRG7
BRG6
BRG14
BRG15
TRISC7
BRG11
BRG10
TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
TXREG
TXSTA
EUSART Transmit Data Register
CSRC TX9 TXEN
215*
222
SYNC
SENDB
BRGH
TRMT
TX9D
Legend: x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Transmission.
Page provides register information.
*
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 217
PIC16F193X/LF193X
20.1.2
EUSART ASYNCHRONOUS
RECEIVER
20.1.2.2
Receiving Data
The receiver data recovery circuit initiates character
reception on the falling edge of the first bit. The first bit,
also known as the Start bit, is always a zero. The data
recovery circuit counts one-half bit time to the center of
the Start bit and verifies that the bit is still a zero. If it is
not a zero then the data recovery circuit aborts
character reception, without generating an error, and
resumes looking for the falling edge of the Start bit. If
the Start bit zero verification succeeds then the data
recovery circuit counts a full bit time to the center of the
next bit. The bit is then sampled by a majority detect
circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
This repeats until all data bits have been sampled and
shifted into the RSR. One final bit time is measured and
the level sampled. This is the Stop bit, which is always
a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
character, otherwise the framing error is cleared for this
character. See Section 20.1.2.4 “Receive Framing
Error” for more information on framing errors.
The Asynchronous mode is typically used in RS-232
systems. The receiver block diagram is shown in
Figure 20-2. The data is received on the RX/DT pin and
drives the data recovery block. The data recovery block
is actually a high-speed shifter operating at 16 times
the baud rate, whereas the serial Receive Shift
Register (RSR) operates at the bit rate. When all 8 or 9
bits of the character have been shifted in, they are
immediately transferred to
a
two character
First-In-First-Out (FIFO) memory. The FIFO buffering
allows reception of two complete characters and the
start of a third character before software must start
servicing the EUSART receiver. The FIFO and RSR
registers are not directly accessible by software.
Access to the received data is via the RCREG register.
20.1.2.1
Enabling the Receiver
The EUSART receiver is enabled for asynchronous
operation by configuring the following three control bits:
Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
to the EUSART receive FIFO and the RCIF interrupt
flag bit of the PIR1 register is set. The top character in
the FIFO is transferred out of the FIFO by reading the
RCREG register.
• CREN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the CREN bit of the RCSTA register enables the
receiver circuitry of the EUSART. Clearing the SYNC bit
of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART and automatically
configures the RX/DT I/O pin as an input.
Note:
If the receive FIFO is overrun, no additional
characters will be received until the overrun
condition is cleared. See Section 20.1.2.5
“Receive Overrun Error” for more
information on overrun errors.
20.1.2.3
Receive Interrupts
Note:
When the SPEN bit is set the TX/CK I/O
pin is automatically configured as an
output, regardless of the state of the
corresponding TRIS bit and whether or not
the EUSART transmitter is enabled. The
PORT latch is disconnected from the
output driver so it is not possible to use the
TX/CK pin as a general purpose output.
The RCIF interrupt flag bit of the PIR1 register is set
whenever the EUSART receiver is enabled and there is
an unread character in the receive FIFO. The RCIF
interrupt flag bit is read-only, it cannot be set or cleared
by software.
RCIF interrupts are enabled by setting all of the
following bits:
• RCIE interrupt enable bit of the PIE1 register
• PEIE peripheral interrupt enable bit of the
INTCON register
• GIE global interrupt enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.
DS41364A-page 218
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
20.1.2.4
Receive Framing Error
20.1.2.7
Address Detection
Each character in the receive FIFO buffer has a
corresponding framing error Status bit. A framing error
indicates that a Stop bit was not seen at the expected
time. The framing error status is accessed via the
FERR bit of the RCSTA register. The FERR bit
represents the status of the top unread character in the
receive FIFO. Therefore, the FERR bit must be read
before reading the RCREG.
A special Address Detection mode is available for use
when multiple receivers share the same transmission
line, such as in RS-485 systems. Address detection is
enabled by setting the ADDEN bit of the RCSTA
register.
Address detection requires 9-bit character reception.
When address detection is enabled, only characters
with the ninth data bit set will be transferred to the
receive FIFO buffer, thereby setting the RCIF interrupt
bit. All other characters will be ignored.
The FERR bit is read-only and only applies to the top
unread character in the receive FIFO. A framing error
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
Upon receiving an address character, user software
determines if the address matches its own. Upon
address match, user software must disable address
detection by clearing the ADDEN bit before the next
Stop bit occurs. When user software detects the end of
the message, determined by the message protocol
used, software places the receiver back into the
Address Detection mode by setting the ADDEN bit.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCSTA register which resets the EUSART.
Clearing the CREN bit of the RCSTA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note:
If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCREG will not clear the FERR bit.
20.1.2.5
Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCSTA register is set.
The characters already in the FIFO buffer can be read
but no additional characters will be received until the
error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCSTA register.
20.1.2.6
Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9 bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCREG.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 219
PIC16F193X/LF193X
20.1.2.8
Asynchronous Reception Set-up:
20.1.2.9
9-bit Address Detection Mode Set-up
1. Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 20.3 “EUSART
Baud Rate Generator (BRG)”).
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 20.3 “EUSART
Baud Rate Generator (BRG)”).
2. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
3. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
2. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
4. If 9-bit reception is desired, set the RX9 bit.
5. Enable reception by setting the CREN bit.
3. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
6. The RCIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCIE interrupt enable bit was also set.
4. Enable 9-bit reception by setting the RX9 bit.
5. Enable address detection by setting the ADDEN
bit.
7. Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
6. Enable reception by setting the CREN bit.
7. The RCIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will be generated if the RCIE interrupt enable bit
was also set.
8. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register.
9. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
8. Read the RCSTA register to get the error flags.
The ninth data bit will always be set.
9. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
FIGURE 20-5:
ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX/DT pin
bit 7/8
bit 7/8
bit 0 bit 1
Stop
bit
Stop
bit
Stop
bit
bit 0
bit 7/8
Rcv Shift
Reg
Rcv Buffer Reg.
Word 2
RCREG
Word 1
RCREG
RCIDL
Read Rcv
Buffer Reg.
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
DS41364A-page 220
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 20-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUDCON
INTCON
PIE1
ABDOVF
GIE
RCIDL
PEIE
ADIE
ADIF
—
SCKP
INTE
TXIE
TXIF
BRG16
IOCIE
SSPIE
SSPIF
—
WUE
INTF
ABDEN
IOCIF
224
73
TMR0IE
RCIE
TMR0IF
TMR1GIE
TMR1GIF
CCP1IE TMR2IE TMR1IE
CCP1IF TMR2IF TMR1IF
74
PIR1
RCIF
77
RCREG
RCSTA
SPBRG
SPBRGH
TRISC
EUSART Receive Data Register
218*
223
225*
225*
94
SPEN
BRG7
RX9
BRG6
BRG14
SREN
BRG5
CREN
BRG4
ADDEN
BRG3
FERR
BRG2
OERR
BRG1
BRG9
RX9D
BRG0
BRG8
BRG15
TRISC7
CSRC
BRG13
BRG12
BRG11
BRG10
TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
TX9 TXEN SYNC SENDB BRGH TRMT TX9D
TXSTA
222
Legend: x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Reception.
Page provides register information.
*
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 221
PIC16F193X/LF193X
The first (preferred) method uses the OSCTUNE
register to adjust the INTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See Section 8.5
“Internal Clock Modes” for more information.
20.2 Clock Accuracy with
Asynchronous Operation
The factory calibrates the internal oscillator block out-
put (INTOSC). However, the INTOSC frequency may
drift as VDD or temperature changes, and this directly
affects the asynchronous baud rate. Two methods may
be used to adjust the baud rate clock, but both require
a reference clock source of some kind.
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see Section 20.3.1
“Auto-Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
REGISTER 20-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-/0
CSRC
R/W-0/0
TX9
R/W-0/0
R/W-0/0
SYNC
R/W-0/0
SENDB
R/W-0/0
BRGH
R-1/1
R/W-0/0
TX9D
(1)
TXEN
TRMT
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
bit 4
bit 3
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
(1)
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
SYNC: EUSART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
SENDB: Send Break Character bit
Asynchronous mode:
1= Send Sync Break on next transmission (cleared by hardware upon completion)
0= Sync Break transmission completed
Synchronous mode:
Don’t care
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
DS41364A-page 222
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
REGISTER 20-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)
R/W-0/0
SPEN
R/W-0/0
RX9
R/W-0/0
SREN
R/W-0/0
CREN
R/W-0/0
ADDEN
R-0/0
R-0/0
R-x/x
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0= Serial port disabled (held in Reset)
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Don’t care
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables receiver
0= Disables receiver
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0= Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREG register and receive next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 223
PIC16F193X/LF193X
REGISTER 20-3: BAUDCON: BAUD RATE CONTROL REGISTER
R-0/0
R-1/1
U-0
—
R/W-0/0
SCKP
R/W-0/0
BRG16
U-0
—
R/W-0/0
WUE
R/W-0/0
ABDEN
ABDOVF
RCIDL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
ABDOVF: Auto-Baud Detect Overflow bit
Asynchronous mode:
1= Auto-baud timer overflowed
0= Auto-baud timer did not overflow
Synchronous mode:
Don’t care
RCIDL: Receive Idle Flag bit
Asynchronous mode:
1= Receiver is Idle
0= Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care
bit 5
bit 4
Unimplemented: Read as ‘0’
SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1= Transmit inverted data to the RB7/TX/CK pin
0= Transmit non-inverted data to the RB7/TX/CK pin
Synchronous mode:
1= Data is clocked on rising edge of the clock
0= Data is clocked on falling edge of the clock
bit 3
BRG16: 16-bit Baud Rate Generator bit
1= 16-bit Baud Rate Generator is used
0= 8-bit Baud Rate Generator is used
bit 2
bit 1
Unimplemented: Read as ‘0’
WUE: Wake-up Enable bit
Asynchronous mode:
1= Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE
will automatically clear after RCIF is set.
0= Receiver is operating normally
Synchronous mode:
Don’t care
bit 0
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1= Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0= Auto-Baud Detect mode is disabled
Synchronous mode:
Don’t care
DS41364A-page 224
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
EXAMPLE 20-1:
CALCULATING BAUD
RATE ERROR
20.3 EUSART Baud Rate Generator
(BRG)
For a device with FOSC of 16 MHz, desired baud rate
of 9600, Asynchronous mode, 8-bit BRG:
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDCON register selects 16-bit
mode.
FOSC
Desired Baud Rate = --------------------------------------------------------------------
64([SPBRGH:SPBRG] + 1)
Solving for SPBRGH:SPBRG:
FOSC
---------------------------------------------
Desired Baud Rate
X = --------------------------------------------- – 1
64
The SPBRGH, SPBRG register pair determines the
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the TXSTA
register and the BRG16 bit of the BAUDCON register. In
Synchronous mode, the BRGH bit is ignored.
16000000
-----------------------
9600
= ----------------------- – 1
64
= [25.042] = 25
Table 20-3 contains the formulas for determining the
baud rate. Example 20-1 provides a sample calculation
for determining the baud rate and baud rate error.
16000000
Calculated Baud Rate = --------------------------
64(25 + 1)
Typical baud rates and error values for various
asynchronous modes have been computed for your
convenience and are shown in Table 20-3. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
= 9615
Calc. Baud Rate – Desired Baud Rate
Error = --------------------------------------------------------------------------------------------
Desired Baud Rate
(9615 – 9600)
= ---------------------------------- = 0 . 1 6 %
9600
Writing a new value to the SPBRGH, SPBRG register
pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is Idle before
changing the system clock.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 225
PIC16F193X/LF193X
TABLE 20-3: BAUD RATE FORMULAS
Configuration Bits
Baud Rate Formula
BRG/EUSART Mode
SYNC
BRG16
BRGH
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
x
x
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
FOSC/[64 (n+1)]
FOSC/[16 (n+1)]
FOSC/[4 (n+1)]
Legend:
x= Don’t care, n = value of SPBRGH, SPBRG register pair
TABLE 20-4: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUDCON
RCSTA
ABDOVF RCIDL
—
SCKP
CREN
BRG4
BRG12
SYNC
BRG16
ADDEN
BRG3
—
WUE
OERR
BRG1
BRG9
TRMT
ABDEN
RX9D
BRG0
BRG8
TX9D
224
223
SPEN
BRG7
BRG15
CSRC
RX9
BRG6
BRG14
TX9
SREN
BRG5
BRG13
TXEN
FERR
BRG2
BRG10
BRGH
SPBRG
SPBRGH
TXSTA
225*
225*
222
BRG11
SENDB
Legend: x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator.
Page provides register information.
*
DS41364A-page 226
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 20-5: BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 20.000 MHz FOSC = 18.432 MHz
FOSC = 32.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPBRG
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
300
1200
—
—
—
—
—
—
—
—
255
129
32
—
—
—
239
119
29
—
—
—
143
71
17
16
8
—
1221
2404
9470
10417
19.53k
1.73
0.16
-1.36
0.00
1.73
1200
2400
9600
10286
19.20k
0.00
0.00
0.00
-1.26
0.00
0.00
—
1200
2400
9600
10165
19.20k
0.00
0.00
0.00
-2.42
0.00
0.00
—
2400
2404
9615
10417
19.23k
0.16
0.16
0.00
0.16
207
51
47
25
9600
10417
19.2k
57.6k
115.2k
29
27
15
14
2
55.55k
—
-3.55
—
3
—
—
—
—
—
—
57.60k
—
7
57.60k
—
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPBRG
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
0.00
0.00
0.00
0.00
—
300
1200
—
1202
2404
9615
10417
—
—
0.16
0.16
0.16
0.00
—
—
103
51
12
11
300
1202
2404
—
0.16
0.16
0.16
—
207
51
25
—
5
300
1200
2400
9600
—
191
47
23
5
300
1202
—
0.16
0.16
—
51
12
—
—
—
—
—
—
2400
9600
—
—
10417
19.2k
57.6k
115.2k
10417
—
0.00
—
—
2
—
—
—
—
—
—
19.20k
0.00
0.00
—
—
—
—
—
—
—
—
0
—
—
57.60k
—
—
—
—
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 20.000 MHz FOSC = 18.432 MHz
FOSC = 32.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPBRG
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
300
1200
2400
9600
10417
19.2k
57.6k
—
—
—
—
—
—
—
—
—
—
—
—
—
71
65
35
11
5
9615
10417
19.23k
57.14k
0.16
0.00
0.16
-0.79
2.12
207
191
103
34
9615
10417
19.23k
56.82k
0.16
0.00
0.16
-1.36
129
119
64
9600
10378
19.20k
57.60k
115.2k
0.00
-0.37
0.00
0.00
0.00
119
110
59
19
9
9600
0.00
0.53
0.00
0.00
0.00
10473
19.20k
57.60k
115.2k
21
115.2k 117.64k
16
113.64k -1.36
10
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 227
PIC16F193X/LF193X
TABLE 20-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 8.000 MHz
FOSC = 4.000 MHz
FOSC = 3.6864 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPBRG
SPBRG
SPBRG
SPBRG
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
value
(decimal)
value
(decimal)
value
(decimal)
value
(decimal)
Error
Error
Error
Error
—
—
—
—
—
—
300
1200
—
1202
2404
9615
10417
19.23k
—
—
—
207
103
25
—
—
—
191
95
23
21
11
3
300
1202
2404
—
0.16
0.16
0.16
—
207
51
25
—
5
0.16
0.16
0.16
0.00
0.16
—
1200
0.00
0.00
0.00
0.53
0.00
0.00
0.00
2400
2404
9615
10417
19231
55556
—
0.16
0.16
0.00
0.16
-3.55
—
207
51
47
25
8
2400
9600
9600
10417
19.2k
57.6k
115.2k
23
10473
19.2k
57.60k
115.2k
10417
—
0.00
—
12
—
—
—
—
—
—
—
—
—
—
1
—
—
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 20.000 MHz FOSC = 18.432 MHz
FOSC = 32.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPBRG
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
300
1200
300.0
1200
0.00
-0.02
-0.04
0.16
0.00
0.16
-0.79
2.12
6666
3332
832
207
191
103
34
300.0
1200
-0.01
-0.03
-0.03
0.16
0.00
0.16
-1.36
4166
1041
520
129
119
64
300.0
1200
0.00
0.00
0.00
0.00
-0.37
0.00
0.00
0.00
3839
959
479
119
110
59
300.0
1200
0.00
0.00
0.00
0.00
0.53
0.00
0.00
0.00
2303
575
287
71
2400
2401
2399
2400
2400
9600
9615
9615
9600
9600
10417
19.2k
57.6k
115.2k
10417
19.23k
57.14k
117.6k
10417
19.23k
56.818
10378
19.20k
57.60k
115.2k
10473
19.20k
57.60k
115.2k
65
35
21
19
11
16
113.636 -1.36
10
9
5
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPBRG
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
300
1200
299.9
1199
-0.02
-0.08
0.16
0.16
0.00
0.16
-3.55
—
1666
416
207
51
300.1
1202
2404
9615
10417
19.23k
—
0.04
0.16
0.16
0.16
0.00
0.16
—
832
207
103
25
300.0
1200
0.00
0.00
0.00
0.00
0.53
0.00
0.00
0.00
767
191
95
23
21
11
3
300.5
1202
2404
—
0.16
0.16
0.16
—
207
51
25
—
5
2400
2404
9615
10417
19.23k
55556
—
2400
9600
9600
10417
19.2k
57.6k
115.2k
47
23
10473
19.20k
57.60k
115.2k
10417
—
0.00
—
25
12
—
—
—
8
—
—
—
—
—
—
—
1
—
—
DS41364A-page 228
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 20-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 20.000 MHz FOSC = 18.432 MHz
FOSC = 32.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPBRG
SPBRG
SPBRG
SPBRG
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
value
(decimal)
value
(decimal)
value
(decimal)
value
(decimal)
Error
Error
Error
Error
300
1200
300.0
1200
0.00
0.00
0.01
0.04
0.00
-0.08
-0.08
0.64
26666
6666
3332
832
300.0
1200
0.00
-0.01
0.02
-0.03
0.00
0.16
-0.22
0.94
16665
4166
2082
520
479
259
86
300.0
1200
0.00
0.00
0.00
0.00
0.08
0.00
0.00
0.00
15359
3839
1919
479
441
239
79
300.0
1200
0.00
0.00
0.00
0.00
0.16
0.00
0.00
0.00
9215
2303
1151
287
264
143
47
2400
2400
2400
2400
2400
9600
9604
9597
9600
9600
10417
19.2k
57.6k
115.2k
10417
19.18k
57.55k
115.9k
767
10417
19.23k
57.47k
116.3k
10425
19.20k
57.60k
115.2k
10433
19.20k
57.60k
115.2k
416
138
68
42
39
23
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPBRG
SPBRG
SPBRG
SPBRG
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
value
(decimal)
value
(decimal)
value
(decimal)
value
(decimal)
Error
Error
Error
Error
300
1200
300.0
1200
0.00
-0.02
0.04
0.16
0
6666
1666
832
207
191
103
34
300.0
1200
0.01
0.04
0.08
0.16
0.00
0.16
2.12
-3.55
3332
832
416
103
95
300.0
1200
0.00
0.00
0.00
0.00
0.53
0.00
0.00
0.00
3071
767
383
95
300.1
1202
2404
9615
10417
19.23k
—
0.04
0.16
0.16
0.16
0.00
0.16
—
832
207
103
25
2400
2401
2398
2400
9600
9615
9615
9600
10417
19.2k
57.6k
115.2k
10417
19.23k
57.14k
117.6k
10417
19.23k
58.82k
111.1k
10473
19.20k
57.60k
115.2k
87
23
0.16
-0.79
2.12
51
47
12
16
15
—
16
8
7
—
—
—
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 229
PIC16F193X/LF193X
and SPBRG registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
average bit time when clocked at full speed.
20.3.1
AUTO-BAUD DETECT
The EUSART module supports automatic detection
and calibration of the baud rate.
Note 1: If the WUE bit is set with the ABDEN bit,
auto-baud detection will occur on the byte
following the Break character (see
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Section 20.3.3
“Auto-Wake-up
on
Break”).
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
Setting the ABDEN bit of the BAUDCON register starts
the auto-baud calibration sequence (Figure 20-6).
While the ABD sequence takes place, the EUSART
state machine is held in Idle. On the first rising edge of
the receive line, after the Start bit, the SPBRG begins
counting up using the BRG counter clock as shown in
Table 20-6. The fifth rising edge will occur on the RX pin
at the end of the eighth bit period. At that time, an
accumulated value totaling the proper BRG period is
left in the SPBRGH, SPBRG register pair, the ABDEN
bit is automatically cleared and the RCIF interrupt flag
is set. The value in the RCREG needs to be read to
clear the RCIF interrupt. RCREG content should be
discarded. When calibrating for modes that do not use
the SPBRGH register the user can verify that the
SPBRG register did not overflow by checking for 00h in
the SPBRGH register.
3: During the auto-baud process, the
auto-baud counter starts counting at 1.
Upon completion of the auto-baud
sequence, to achieve maximum accuracy,
subtract 1 from the SPBRGH:SPBRG
register pair.
TABLE 20-6:
BRG16 BRGH
BRG COUNTER CLOCK RATES
BRG Base
Clock
BRG ABD
Clock
0
0
0
1
FOSC/64
FOSC/16
FOSC/512
FOSC/128
1
1
0
1
FOSC/16
FOSC/4
FOSC/128
FOSC/32
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 20-6. During ABD,
both the SPBRGH and SPBRG registers are used as a
16-bit counter, independent of the BRG16 bit setting.
While calibrating the baud rate period, the SPBRGH
Note:
During the ABD sequence, SPBRG and
SPBRGH registers are both used as a 16-bit
counter, independent of BRG16 setting.
FIGURE 20-6:
AUTOMATIC BAUD RATE CALIBRATION
XXXXh
0000h
001Ch
BRG Value
Edge #1
bit 1
Edge #2
bit 3
Edge #3
bit 5
Edge #4
bit 7
bit 6
Edge #5
Stop bit
RX pin
Start
bit 0
bit 2
bit 4
BRG Clock
Auto Cleared
Set by User
ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
XXh
XXh
1Ch
00h
SPBRG
SPBRGH
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
DS41364A-page 230
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
20.3.2
AUTO-BAUD OVERFLOW
20.3.3.1
Special Considerations
During the course of automatic baud detection, the
ABDOVF bit of the BAUDCON register will be set if the
baud rate counter overflows before the fifth rising edge
is detected on the RX pin. The ABDOVF bit indicates
that the counter has exceeded the maximum count that
can fit in the 16 bits of the SPBRGH:SPBRG register
pair. After the ABDOVF has been set, the counter con-
tinues to count until the fifth rising edge is detected on
the RX pin. Upon detecting the fifth RX edge, the hard-
ware will set the RCIF interrupt flag and clear the
ABDEN bit of the BAUDCON register. The RCIF flag
can be subsequently cleared by reading the RCREG
register. The ABDOVF flag of the BAUDCON register
can be cleared by software directly.
Break Character
To avoid character errors or character fragments during
a wake-up event, the wake-up character must be all
zeros.
When the wake-up is enabled the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Therefore, the initial character in the transmission must
be all ‘0’s. This must be 10 or more bit times, 13-bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
To terminate the auto-baud process before the RCIF
flag is set, clear the ABDEN bit then clear the ABDOVF
bit of the BAUDCON register. The ABDOVF bit will
remain set if the ABDEN bit is not cleared first.
Oscillator Startup Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected oscillator
to start and provide proper initialization of the EUSART.
20.3.3
AUTO-WAKE-UP ON BREAK
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper character reception cannot be
performed. The Auto-Wake-up feature allows the
controller to wake-up due to activity on the RX/DT line.
This feature is available only in Asynchronous mode.
WUE Bit
The Auto-Wake-up feature is enabled by setting the
WUE bit of the BAUDCON register. Once set, the normal
receive sequence on RX/DT is disabled, and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on the
RX/DT line. (This coincides with the start of a Sync Break
or a wake-up signal character for the LIN protocol.)
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared in
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared in software by reading the
RCREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
The EUSART module generates an RCIF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 20-7), and asynchronously if
the device is in Sleep mode (Figure 20-8). The interrupt
condition is cleared by reading the RCREG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 231
PIC16F193X/LF193X
FIGURE 20-7:
AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3Q4
OSC1
Auto Cleared
Bit set by user
WUE bit
RX/DT Line
RCIF
Cleared due to User Read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
FIGURE 20-8:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q4
Q1Q2Q3 Q4 Q1Q2 Q3Q4 Q1Q2Q3
Q1
Q2 Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4
Auto Cleared
OSC1
Bit Set by User
WUE bit
RX/DT Line
Note 1
RCIF
Cleared due to User Read of RCREG
Sleep Command Executed
Sleep Ends
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposcsignal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
DS41364A-page 232
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
5. After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
20.3.4
BREAK CHARACTER SEQUENCE
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. A Break character consists of a
Start bit, followed by 12 ‘0’ bits and a Stop bit.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
To send a Break character, set the SENDB and TXEN
bits of the TXSTA register. The Break character trans-
mission is then initiated by a write to the TXREG. The
value of data written to TXREG will be ignored and all
‘0’s will be transmitted.
20.3.5
RECEIVING A BREAK CHARACTER
The Enhanced EUSART module can receive a Break
character in two ways.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
The first method to detect a Break character uses the
FERR bit of the RCSTA register and the Received data
as indicated by RCREG. The Baud Rate Generator is
assumed to have been initialized to the expected baud
rate.
The TRMT bit of the TXSTA register indicates when the
transmit operation is active or Idle, just as it does during
normal transmission. See Figure 20-9 for the timing of
the Break character sequence.
A Break character has been received when;
• RCIF bit is set
• FERR bit is set
• RCREG = 00h
20.3.4.1
Break and Sync Transmit Sequence
The second method uses the Auto-Wake-up feature
described in Section 20.3.3 “Auto-Wake-up on
Break”. By enabling this feature, the EUSART will
sample the next two transitions on RX/DT, cause an
RCIF interrupt, and receive the next data byte followed
by another interrupt.
The following sequence will start a message frame
header made up of a Break, followed by an auto-baud
Sync byte. This sequence is typical of a LIN bus
master.
1. Configure the EUSART for the desired mode.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Detect feature.
For both methods, the user can set the ABDEN bit of
the BAUDCON register before placing the EUSART in
Sleep mode.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
FIGURE 20-9:
SEND BREAK CHARACTER SEQUENCE
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
TX (pin)
Start bit
bit 0
bit 1
Break
bit 11
Stop bit
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB Sampled Here
Auto Cleared
SENDB
(send Break
control bit)
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 233
PIC16F193X/LF193X
Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cleared, the data changes on the rising
edge of each clock.
20.4 EUSART Synchronous Mode
Synchronous serial communications are typically used
in systems with a single master and one or more
slaves. The master device contains the necessary cir-
cuitry for baud rate generation and supplies the clock
for all devices in the system. Slave devices can take
advantage of the master clock by eliminating the inter-
nal clock generation circuitry.
20.4.1.3
Synchronous Master Transmission
Data is transferred out of the device on the RX/DT pin.
The RX/DT and TX/CK pin output drivers are automat-
ically enabled when the EUSART is configured for syn-
chronous master transmit operation.
There are two signal lines in Synchronous mode: a bidi-
rectional data line and a clock line. Slaves use the
external clock supplied by the master to shift the serial
data into and out of their respective receive and trans-
mit shift registers. Since the data line is bidirectional,
synchronous operation is half-duplex only. Half-duplex
refers to the fact that master and slave devices can
receive and transmit data but not both simultaneously.
The EUSART can operate as either a master or slave
device.
A transmission is initiated by writing a character to the
TXREG register. If the TSR still contains all or part of a
previous character the new character data is held in the
TXREG until the last bit of the previous character has
been transmitted. If this is the first character, or the pre-
vious character has been completely flushed from the
TSR, the data in the TXREG is immediately transferred
to the TSR. The transmission of the character com-
mences immediately following the transfer of the data
to the TSR from the TXREG.
Start and Stop bits are not used in synchronous trans-
missions.
Each data bit changes on the leading edge of the mas-
ter clock and remains valid until the subsequent leading
clock edge.
20.4.1
SYNCHRONOUS MASTER MODE
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
The following bits are used to configure the EUSART
for Synchronous Master operation:
• SYNC = 1
20.4.1.4
Synchronous Master Transmission
Set-up:
• CSRC = 1
• SREN = 0(for transmit); SREN = 1(for receive)
• CREN = 0(for transmit); CREN = 1(for receive)
• SPEN = 1
1. Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 20.3 “EUSART
Baud Rate Generator (BRG)”).
Setting the SYNC bit of the TXSTA register configures
the device for synchronous operation. Setting the CSRC
bit of the TXSTA register configures the device as a
master. Clearing the SREN and CREN bits of the RCSTA
register ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Disable Receive mode by clearing bits SREN
and CREN.
4. Enable Transmit mode by setting the TXEN bit.
5. If 9-bit transmission is desired, set the TX9 bit.
6. If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
20.4.1.1
Master Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device config-
ured as a master transmits the clock on the TX/CK line.
The TX/CK pin output driver is automatically enabled
when the EUSART is configured for synchronous
transmit or receive operation. Serial data bits change
on the leading edge to ensure they are valid at the trail-
ing edge of each clock. One clock cycle is generated
for each data bit. Only as many clock cycles are gener-
ated as there are data bits.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in the TX9D bit.
8. Start transmission by loading data to the TXREG
register.
20.4.1.2
Clock Polarity
A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the SCKP
bit of the BAUDCON register. Setting the SCKP bit sets
the clock Idle state as high. When the SCKP bit is set,
the data changes on the falling edge of each clock.
DS41364A-page 234
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 20-10:
SYNCHRONOUS TRANSMISSION
RX/DT
pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
Word 1
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’
‘1’
TXEN bit
Note:
Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
FIGURE 20-11:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX/DT pin
bit 0
bit 2
bit 1
bit 6
bit 7
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 20-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUDCON
INTCON
PIE1
ABDOVF
GIE
RCIDL
PEIE
—
SCKP
INTE
BRG16
IOCIE
—
WUE
INTF
ABDEN
IOCIF
224
73
TMR0IE
RCIE
TMR0IF
CCP1IE
CCP1IF
FERR
TMR1GIE
TMR1GIF
SPEN
ADIE
TXIE
SSPIE
SSPIF
ADDEN
BRG3
TMR2IE
TMR2IF
OERR
BRG1
TMR1IE
TMR1IF
RX9D
74
PIR1
ADIF
RCIF
TXIF
77
RCSTA
SPBRG
SPBRGH
TRISC
RX9
SREN
BRG5
BRG13
TRISC5
CREN
BRG4
BRG12
TRISC4
223
225*
225*
94
BRG7
BRG6
BRG14
TRISC6
BRG2
BRG0
BRG15
TRISC7
BRG11
TRISC3
BRG10
TRISC2
BRG9
BRG8
TRISC1
TRISC0
TXREG
TXSTA
EUSART Transmit Data Register
CSRC TX9 TXEN
215*
222
SYNC
SENDB
BRGH
TRMT
TX9D
Legend:
x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Transmission.
*
Page provides register information.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 235
PIC16F193X/LF193X
set then the error condition is cleared by either clearing
the CREN bit of the RCSTA register or by clearing the
SPEN bit which resets the EUSART.
20.4.1.5
Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT pin
output driver is automatically disabled when the
EUSART is configured for synchronous master receive
operation.
20.4.1.8
Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9-bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth, and Most Significant, data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCREG.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RCSTA register) or the Continuous Receive Enable bit
(CREN of the RCSTA register).
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character. The SREN bit is automatically cleared
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial charac-
ter is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.
20.4.1.9
Synchronous Master Reception
Set-up:
1. Initialize the SPBRGH, SPBRG register pair for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
received into the RSR, the RCIF bit is set and the char-
acter is automatically transferred to the two character
receive FIFO. The Least Significant eight bits of the top
character in the receive FIFO are available in RCREG.
The RCIF bit remains set as long as there are unread
characters in the receive FIFO.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
5. If 9-bit reception is desired, set bit RX9.
6. Start reception by setting the SREN bit or for
continuous reception, set the CREN bit.
20.4.1.6
Slave Clock
7. Interrupt flag bit RCIF will be set when reception
of a character is complete. An interrupt will be
generated if the enable bit RCIE was set.
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a slave receives the clock on the TX/CK line. The
TX/CK pin output driver is automatically disabled when
the device is configured for synchronous slave transmit
or receive operation. Serial data bits change on the
leading edge to ensure they are valid at the trailing edge
of each clock. One data bit is transferred for each clock
cycle. Only as many clock cycles should be received as
there are data bits.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
20.4.1.7
Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCREG is read to access
the FIFO. When this happens the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCREG. If the overrun occurred when the CREN bit is
DS41364A-page 236
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 20-12:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
‘0’
‘0’
CREN bit
RCIF bit
(Interrupt)
Read
RXREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.
TABLE 20-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUDCON
INTCON
PIE1
ABDOVF
GIE
RCIDL
PEIE
ADIE
ADIF
—
SCKP
INTE
TXIE
TXIF
BRG16
IOCIE
SSPIE
SSPIF
—
WUE
INTF
ABDEN
IOCIF
224
73
TMR0IE
RCIE
TMR0IF
TMR1GIE
TMR1GIF
CCP1IE TMR2IE TMR1IE
CCP1IF TMR2IF TMR1IF
74
PIR1
RCIF
77
RCREG
RCSTA
SPBRG
EUSART Receive Data Register
218*
223
225*
225*
94
RX9
BRG6
BRG14
SREN
BRG5
CREN
BRG4
ADDEN
BRG3
FERR
BRG2
OERR
BRG1
BRG9
RX9D
BRG0
BRG8
SPEN
BRG7
SPBRGH
TRISC
BRG15
TRISC7
CSRC
BRG13
BRG12
BRG11
BRG10
TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
TX9 TXEN SYNC SENDB BRGH TRMT TX9D
TXSTA
222
Legend: x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master
Reception.
*
Page provides register information.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 237
PIC16F193X/LF193X
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
20.4.2
SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART
for Synchronous slave operation:
1. The first character will immediately transfer to
the TSR register and transmit.
• SYNC = 1
2. The second word will remain in TXREG register.
3. The TXIF bit will not be set.
• CSRC = 0
• SREN = 0(for transmit); SREN = 1(for receive)
• CREN = 0(for transmit); CREN = 1(for receive)
• SPEN = 1
4. After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART.
5. If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
20.4.2.2
Synchronous Slave Transmission
Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
20.4.2.1
EUSART Synchronous Slave
Transmit
2. Clear the CREN and SREN bits.
The operation of the Synchronous Master and Slave
modes are identical (see Section 20.4.1.3
“Synchronous Master Transmission”), except in the
3. If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
case of the Sleep mode.
4. If 9-bit transmission is desired, set the TX9 bit.
5. Enable transmission by setting the TXEN bit.
6. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
7. Start transmission by writing the Least
Significant 8 bits to the TXREG register.
TABLE 20-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUDCON
INTCON
PIE1
ABDOVF
GIE
RCIDL
PEIE
ADIE
ADIF
RX9
—
SCKP
INTE
TXIE
BRG16
IOCIE
—
WUE
INTF
ABDEN
IOCIF
224
73
TMR0IE
RCIE
TMR0IF
TMR1GIE
TMR1GIF
SSPIE
SSPIF
ADDEN
CCP1IE TMR2IE TMR1IE
CCP1IF TMR2IF TMR1IF
74
PIR1
RCIF
TXIF
77
SREN
CREN
FERR
OERR
RX9D
RCSTA
TRISC
TXREG
SPEN
223
94
TRISC7
TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
EUSART Transmit Data Register
CSRC TX9 TXEN
215*
222
TXSTA
SYNC
SENDB
BRGH
TRMT
TX9D
Legend: x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave
Transmission.
*
Page provides register information.
DS41364A-page 238
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
20.4.2.3
EUSART Synchronous Slave
Reception
20.4.2.4
Synchronous Slave Reception
Set-up:
The operation of the Synchronous Master and Slave
modes is identical (Section 20.4.1.5 “Synchronous
Master Reception”), with the following exceptions:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
• Sleep
• CREN bit is always set, therefore the receiver is
never Idle
3. If 9-bit reception is desired, set the RX9 bit.
4. Set the CREN bit to enable reception.
• SREN bit, which is a “don’t care” in Slave mode
5. The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
6. If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
7. Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
8. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUDCON
INTCON
PIE1
ABDOVF
GIE
RCIDL
PEIE
ADIE
ADIF
—
SCKP
INTE
TXIE
TXIF
BRG16
IOCIE
SSPIE
SSPIF
—
WUE
INTF
ABDEN
IOCIF
224
73
TMR0IE
RCIE
TMR0IF
TMR1GIE
TMR1GIF
CCP1IE TMR2IE TMR1IE
CCP1IF TMR2IF TMR1IF
74
PIR1
RCIF
77
RCREG
RCSTA
TRISC
TXSTA
EUSART Receive Data Register
218*
223
94
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
SPEN
TRISC7
CSRC
TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
TX9 TXEN SYNC SENDB BRGH TRMT TX9D
222
Legend: x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave
Reception.
*
Page provides register information.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 239
PIC16F193X/LF193X
20.5.2
SYNCHRONOUS TRANSMIT
DURING SLEEP
20.5 EUSART Operation During Sleep
The EUSART will remain active during Sleep only in the
Synchronous Slave mode. All other modes require the
system clock and therefore cannot generate the neces-
sary signals to run the Transmit or Receive Shift regis-
ters during Sleep.
To transmit during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCSTA and TXSTA Control registers must be
configured for Synchronous Slave Transmission
(see Section 20.4.2.2 “Synchronous Slave
Transmission Set-up:”).
Synchronous Slave mode uses an externally generated
clock to run the Transmit and Receive Shift registers.
•
The TXIF interrupt flag must be cleared by writing
the output data to the TXREG, thereby filling the
TSR and transmit buffer.
20.5.1
SYNCHRONOUS RECEIVE DURING
SLEEP
• If interrupts are desired, set the TXIE bit of the
PIE1 register and the PEIE bit of the INTCON reg-
ister.
To receive during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCSTA and TXSTA Control registers must be
configured for Synchronous Slave Reception (see
Section 20.4.2.4 “Synchronous Slave
Reception Set-up:”).
• Interrupt enable bits TXIE of the PIE1 register and
PEIE of the INTCON register must set.
Upon entering Sleep mode, the device will be ready to
accept clocks on TX/CK pin and transmit data on the
RX/DT pin. When the data word in the TSR has been
completely clocked out by the external device, the
pending byte in the TXREG will transfer to the TSR and
the TXIF flag will be set. Thereby, waking the processor
from Sleep. At this point, the TXREG is available to
accept another character for transmission, which will
clear the TXIF flag.
• If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
• The RCIF interrupt flag must be cleared by read-
ing RCREG to unload any pending characters in
the receive buffer.
Upon entering Sleep mode, the device will be ready to
accept data and clocks on the RX/DT and TX/CK pins,
respectively. When the data word has been completely
clocked in by the external device, the RCIF interrupt
flag bit of the PIR1 register will be set. Thereby, waking
the processor from Sleep.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the GIE global
interrupt enable bit is also set then the Interrupt Service
Routine at address 0004h will be called.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the GIE global
interrupt enable bit of the INTCON register is also set,
then the Interrupt Service Routine at address 004h will
be called.
DS41364A-page 240
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
• Segment pins up to:
21.0 LIQUID CRYSTAL DISPLAY
(LCD) DRIVER MODULE
- 16 (PIC16F1933/1936/1938/
PIC16LF1933/1936/1938)
The Liquid Crystal Display (LCD) driver module
generates the timing control to drive a static or
multiplexed LCD panel. In the PIC16F193X/LF193X
device, the module drives the panels of up to four
commons and up to 24 segments. The LCD module
also provides control of the LCD pixel data.
- 24 (PIC16F1934/1937/1939/
PIC16LF1934/1937/1939)
• Static, 1/2 or 1/3 LCD Bias
Note:
COM3 and SEG15 share the same physical
pin on the PIC16F1933/1936/1938/
PIC16LF1933/1936/1938, therefore SEG15
is not available when using 1/4 multiplex
displays.
The LCD driver module supports:
• Direct driving of LCD panel
• Three LCD clock sources with selectable prescaler
• Up to four common pins:
21.1 LCD Registers
- Static (1 common)
The module contains the following registers:
- 1/2 multiplex (2 commons)
- 1/3 multiplex (3 commons)
- 1/4 multiplex (4 commons)
• LCD Control register (LCDCON)
• LCD Phase register (LCDPS)
• LCD Reference Ladder register (LCDRL)
• LCD Contrast Control register (LCDCST)
• LCD Reference Voltage Control register
(LCDREF)
• Up to 3 LCD Segment Enable registers (LCDSEn)
• Up to 12 LCD data registers (LCDDATAn)
FIGURE 21-1:
LCD DRIVER MODULE BLOCK DIAGRAM
(1, 3)
SEG<23:0>
LCDDATAx
Registers
Data Bus
(1)
MUX
To I/O Pads
Timing Control
LCDCON
LCDPS
(3)
COM<3:0>
(1)
To I/O Pads
LCDSEn
FOSC/256
Clock Source
Select and
Prescaler
T1OSC
LFINTOSC
Note 1: These are not directly connected to the I/O pads, but may be tri-stated, depending on the configuration of
the LCD module.
2: SEG<23:0> on PIC16F1934/1937/1939, SEG<15:0> on PIC16F1933/1936/1938/
PIC16LF1933/1936/1938.
3: COM3 and SEG15 share the same physical pin on the PIC16F1933/1936/1938/PIC16LF1933/1936/1938,
therefore SEG15 is not available when using 1/4 multiplex displays.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 241
PIC16F193X/LF193X
TABLE 21-1: LCD SEGMENT AND DATA
REGISTERS
# of LCD Registers
Device
Segment
Enable
Data
PIC16F1933/1936/1938/
PIC16LF1933/1936/1938
2
3
8
PIC16F1934/1937/1939/
PIC16LF1934/1937/1939
12
The LCDCON register (Register 21-1) controls the
operation of the LCD driver module. The LCDPS regis-
ter (Register 21-2) configures the LCD clock source
prescaler and the type of waveform; Type-A or Type-B.
The LCDSE registers (Register 21-5) configure the
functions of the port pins.
The following LCDSE registers are available:
• LCDSE0 SE<7:0>
• LCDSE1 SE<15:8>
• LCDSE2 SE<23:16>(1)
Note 1: PIC16F1934/1937/1939/
PIC16LF1934/1937/1939 only.
Once the module is initialized for the LCD panel, the
individual bits of the LCDDATA<11:0> registers are
cleared/set to represent a clear/dark pixel, respectively:
• LCDDATA0 SEG<7:0>COM0
• LCDDATA1 SEG<15:8>COM0
• LCDDATA2 SEG<23:16>COM0(1)
• LCDDATA3 SEG<7:0>COM1
• LCDDATA4 SEG<15:8>COM1
• LCDDATA5 SEG<23:16>COM1(1)
• LCDDATA6 SEG<7:0>COM2
• LCDDATA7 SEG<15:8>COM2
• LCDDATA8 SEG<23:16>COM2(1)
• LCDDATA9 SEG<7:0>COM3
• LCDDATA10 SEG<15:8>COM3
• LCDDATA11 SEG<23:16>COM3(1)
Note 1: PIC16F1934/1937/1939/
PIC16LF1934/1937/1939 only.
As an example, LCDDATAx is detailed in
Register 21-6.
Once the module is configured, the LCDEN bit of the
LCDCON register is used to enable or disable the LCD
module. The LCD panel can also operate during Sleep
by clearing the SLPEN bit of the LCDCON register.
DS41364A-page 242
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
REGISTER 21-1: LCDCON: LIQUID CRYSTAL DISPLAY (LCD) CONTROL REGISTER
R/W-0/0
LCDEN
R/W-0/0
SLPEN
R/C-0/0
WERR
U-0
—
R/W-0/0
CS1
R/W-0/0
CS0
R/W-1/1
LMUX1
R/W-1/1
LMUX0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
C = Only clearable bit
bit 7
bit 6
bit 5
LCDEN: LCD Driver Enable bit
1= LCD driver module is enabled
0= LCD driver module is disabled
SLPEN: LCD Driver Enable in Sleep Mode bit
1= LCD driver module is disabled in Sleep mode
0= LCD driver module is enabled in Sleep mode
WERR: LCD Write Failed Error bit
1 = LCDDATAx register written while the WA bit of the LCDPS register = 0 (must be cleared in
software)
0= No LCD write error
bit 4
Unimplemented: Read as ‘0’
bit 3-2
CS<1:0>: Clock Source Select bits
00= FOSC/256
01= T1OSC (Timer1)
1x= LFINTOSC (31 kHz)
bit 1-0
LMUX<1:0>: Commons Select bits
Maximum Number of Pixels
LMUX<1:0>
Multiplex
Bias
PIC16F1933/1936/1938/
PIC16F1934/1937/1939/
PIC16LF1933/1936/1938 PIC16LF1934/1937/1939
00
01
10
11
Static (COM0)
1/2 (COM<1:0>)
1/3 (COM<2:0>)
1/4 (COM<3:0>)
16
32
24
48
72
96
Static
1/2 or 1/3
1/2 or 1/3
1/3
48
60(1)
Note 1: On these devices, COM3 and SEG15 are shared on one pin, limiting the device from driving 64 pixels.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 243
PIC16F193X/LF193X
REGISTER 21-2: LCDPS: LCD PHASE REGISTER
R/W-0/0
WFT
R/W-0/0
BIASMD
R-0/0
LCDA
R-0/0
WA
R/W-0/0
LP3
R/W-0/0
LP2
R/W-1/1
LP1
R/W-1/1
LP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
C = Only clearable bit
bit 7
bit 6
WFT: Waveform Type bit
1= Type-B phase changes on each frame boundary
0= Type-A phase changes within each common type
BIASMD: Bias Mode Select bit
When LMUX<1:0> = 00:
0= Static Bias mode (do not set this bit to ‘1’)
When LMUX<1:0> = 01:
1= 1/2 Bias mode
0= 1/3 Bias mode
When LMUX<1:0> = 10:
1= 1/2 Bias mode
0= 1/3 Bias mode
When LMUX<1:0> = 11:
0= 1/3 Bias mode (do not set this bit to ‘1’)
LCDA: LCD Active Status bit
bit 5
1= LCD driver module is active
0= LCD driver module is inactive
bit 4
WA: LCD Write Allow Status bit
1= Write into the LCDDATAx registers is allowed
0= Write into the LCDDATAx registers is not allowed
bit 3-0
LP<3:0>: LCD Prescaler Selection bits
1111= 1:16
1110= 1:15
1101= 1:14
1100= 1:13
1011= 1:12
1010= 1:11
1001= 1:10
1000= 1:9
0111= 1:8
0110= 1:7
0101= 1:6
0100= 1:5
0011= 1:4
0010= 1:3
0001= 1:2
0000= 1:1
DS41364A-page 244
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
REGISTER 21-3: LCDREF: LCD REFERENCE VOLTAGE CONTROL REGISTER
R/W-0/0
LCDIRE
R/W-0/0
LCDIRS
R/W-0/0
LCDIRI
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
U-0
—
VLCD3PE
VLCD2PE
VLCD1PE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
C = Only clearable bit
bit 7
bit 6
LCDIRE: LCD Internal Reference Enable bit
1= Internal LCD Reference is enabled and connected to the Internal Contrast Control circuit
0= Internal LCD Reference is disabled
LCDIRS: LCD Internal Reference Source bit
If LCDIRE = 1:
0= Internal LCD Contrast Control is powered by VDD
1= Internal LCD Contrast Control is powered by a 3.072V output of the FVR.
If LCDIRE = 0:
Internal LCD Contrast Control is unconnected. LCD bandgap buffer is disabled.
bit 5
LCDIRI: LCD Internal Reference Ladder Idle Enable bit
Allows the Internal FVR buffer to shut down when the LCD Reference Ladder is in power mode ‘B’
1= When the LCD Reference Ladder is in power mode ‘B’, the LCD Internal FVR buffer is disabled.
0= The LCD Internal FVR Buffer ignores the LCD Reference Ladder Power mode.
bit 4
bit 3
Unimplemented: Read as ‘0’
VLCD3PE: VLCD3 Pin Enable bit
1= The VLCD3 pin is connected to the internal bias voltage LCDBIAS3(1)
0= The VLCD3 pin is not connected
bit 2
bit 1
bit 0
VLCD2PE: VLCD2 Pin Enable bit
1= The VLCD2 pin is connected to the internal bias voltage LCDBIAS2(1)
0= The VLCD2 pin is not connected
VLCD1PE: VLCD1 Pin Enable bit
1= The VLCD1 pin is connected to the internal bias voltage LCDBIAS1(1)
0= The VLCD1 pin is not connected
Unimplemented: Read as ‘0’
Note 1: Normal pin controls of TRISx and ANSELx are unaffected.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 245
PIC16F193X/LF193X
REGISTER 21-4: LCDCST: LCD CONTRAST CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
LCDCST2
LCDCST1
LCDCST0
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
C = Only clearable bit
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’
LCDCST<2:0>: LCD Contrast Control bits
Selects the resistance of the LCD contrast control resistor ladder
Bit Value = Resistor ladder
000= Minimum Resistance (Maximum contrast). Resistor ladder is shorted.
001= Resistor ladder is at 1/7th of maximum resistance
010= Resistor ladder is at 2/7th of maximum resistance
011= Resistor ladder is at 3/7th of maximum resistance
100= Resistor ladder is at 4/7th of maximum resistance
101= Resistor ladder is at 5/7th of maximum resistance
110= Resistor ladder is at 6/7th of maximum resistance
111= Resistor ladder is at maximum resistance (Minimum contrast).
DS41364A-page 246
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
REGISTER 21-5: LCDSEn: LCD SEGMENT ENABLE REGISTERS
R/W-0/0
SEn
R/W-0/0
SEn
R/W-0/0
SEn
R/W-0/0
SEn
R/W-0/0
SEn
R/W-0/0
SEn
R/W-0/0
SEn
R/W-0/0
SEn
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
SEn: Segment Enable bits
1= Segment function of the pin is enabled
0= I/O function of the pin is enabled
REGISTER 21-6: LCDDATAx: LCD DATA REGISTERS
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy
R/W-x/u
R/W-x/u
R/W-x/u
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
SEGx-COMy: Pixel On bits
1= Pixel on (dark)
0= Pixel off (clear)
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 247
PIC16F193X/LF193X
Using bits CS<1:0> of the LCDCON register can select
any of these clock sources.
21.2 LCD Clock Source Selection
The LCD module has 3 possible clock sources:
21.2.1
LCD PRESCALER
• FOSC/256
• T1OSC
A 4-bit counter is available as a prescaler for the LCD
clock. The prescaler is not directly readable or writable;
its value is set by the LP<3:0> bits of the LCDPS register,
which determine the prescaler assignment and prescale
ratio.
• LFINTOSC
The first clock source is the system clock divided by
256 (FOSC/256). This divider ratio is chosen to provide
about 1 kHz output when the system clock is 8 MHz.
The divider is not programmable. Instead, the LCD
prescaler bits LP<3:0> of the LCDPS register are used
to set the LCD frame clock rate.
The prescale values are selectable from 1:1 through
1:16.
The second clock source is the T1OSC. This also gives
about 1 kHz when a 32.768 kHz crystal is used with the
Timer1 oscillator. To use the Timer1 oscillator as a
clock source, the T1OSCEN bit of the T1CON register
should be set.
The third clock source is the 31 kHz LFINTOSC, which
provides approximately 1 kHz output.
The second and third clock sources may be used to
continue running the LCD while the processor is in
Sleep.
FIGURE 21-2:
LCD CLOCK GENERATION
To Reference
Ladder Control
FOSC
÷256
Static
÷4
÷2
5
T1OSC 32 kHz
Crystal Osc.
÷1, 2, 3, 4
Ring Counter
4-bit Prog
Prescaler
÷32
1/2
1/3,
1/4
LFINTOSC
Nominal = 31 kHz
LP<3:0>
LMUX<1:0>
(LCDPS<3:0>)
(LCDCON<1:0>)
CS<1:0>
LMUX<1:0>
(LCDCON<3:2>)
(LCDCON<1:0>)
DS41364A-page 248
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 21-2: LCD BIAS VOLTAGES
21.3 LCD Bias Voltage Generation
Static Bias
1/2 Bias
1/3 Bias
The LCD module can be configured for one of three
bias types:
LCD Bias 0
LCD Bias 1
LCD Bias 2
LCD Bias 3
VSS
—
VSS
VSS
1/2 VDD
1/2 VDD
VLCD3
1/3 VDD
2/3 VDD
VLCD3
• Static Bias (2 voltage levels: VSS and VLCD)
—
• 1/2 Bias (3 voltage levels: VSS, 1/2 VLCD and
VLCD)
VLCD3
• 1/3 Bias (4 voltage levels: VSS, 1/3 VLCD,
2/3 VLCD and VLCD)
So that the user is not forced to place external compo-
nents and use up to three pins for bias voltage generation,
internal contrast control and an internal reference ladder
are provided internally to the PIC16F193X/LF193X. Both
of these features may be used in conjunction with the
external VLCD<3:1> pins, to provide maximum flexibility.
Refer to Figure 21-3.
FIGURE 21-3:
LCD BIAS VOLTAGE GENERATION BLOCK DIAGRAM
LCDIRE
LCDIRS
LCDA
VDD
1.024V from
FVR
3.072V
x 3
LCDRLP1
LCDRLP0
LCDIRE
LCDIRS
LCDA
LCDCST<2:0>
VLCD3PE
LCDA
VLCD3
lcdbias3
VLCD2PE
VLCD2
lcdbias2
BIASMD
VLCD1PE
VLCD1
lcdbias1
lcdbias0
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 249
PIC16F193X/LF193X
21.4.2
POWER MODES
21.4 LCD Bias Internal Reference
Ladder
The internal reference ladder may be operated in one of
three power modes. This allows the user to trade off LCD
contrast for power in the specific application. The larger
the LCD glass, the more capacitance is present on a
physical LCD segment, requiring more current to
maintain the same contrast level.
The internal reference ladder can be used to divide the
LCD bias voltage two or three equally spaced voltages
that will be supplied to the LCD segment pins. To create
this, the reference ladder consists of three matched
resistors. Refer to Figure 21-3.
Three different power modes are available, LP, MP and
HP. The internal reference ladder can also be turned off
for applications that wish to provide an external ladder
or to minimize power consumption. Disabling the
internal reference ladder results in all of the ladders
being disconnected, allowing external voltages to be
supplied.
21.4.1
BIAS MODE INTERACTION
When in 1/2 Bias mode (BIASMD = 1), then the middle
resistor of the ladder is shorted out so that only two
voltages are generated. The current consumption of the
ladder is higher in this mode, with the one resistor
removed.
Whenever the LCD module is inactive (LCDA = 0), the
internal reference ladder will be turned off.
TABLE 21-3:
LCD INTERNAL LADDER
POWER MODES (1/3 BIAS)
Power
Mode
Nominal Resistance of
Entire Ladder
Nominal
IDD
Low
3 Mohm
300 kohm
30 kohm
1 µA
10 µA
100 µA
Medium
High
DS41364A-page 250
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
The LCDLAD register allows switching between two
power modes, designated ‘A’ and ‘B’. ‘A’ Power mode
is active for a programmable time, beginning at the
time win the LCD segments transition. ‘B’ Power mode
is the remaining time before the segments or com-
mons change again. The LRLAT<2:0> bits select how
long, if any, that the ‘A’ Power mode is active. Refer
to Figure 21-4.
21.4.3
AUTOMATIC POWER MODE
SWITCHING
As an LCD segment is electrically only a capacitor, cur-
rent is drawn only during the interval where the voltage
is switching. To minimize total device current, the LCD
internal reference ladder can be operated in a different
power mode for the transition portion of the duration.
This is controlled by the LCDRL Register
(Register 21-7).
To implement this, the 5-bit prescaler used to divide
the 32 kHz clock down to the LCD controller’s 1 kHz
base rate is used to select the power mode.
FIGURE 21-4:
LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM –
TYPE A
Single Segment Time
32kHz_clk
cnt[4:0]
lcd_clk
‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07
‘H0E ‘H0F ‘H00 ‘H01
LRLAT[2:0]
Segment Data
‘H3
LRLAT<2:0>
Power Mode
Power Mode A
Power Mode B
Mode A
FIGURE 21-5:
LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM –
TYPE B
Single Segment Time
32kHz_clk
cnt[4:0]
lcd_clk
‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07
‘H1E ‘H1F ‘H00 ‘H01
LRLAT[2:0]
Segment Data
‘H3
LRLAT<2:0>
Power Mode
Power Mode A
Power Mode B
Mode A
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 251
PIC16F193X/LF193X
REGISTER 21-7: LCDRL: LCD REFERENCE LADDER CONTROL REGISTERS
R/W-0/0
LRLAP1
R/W-0/0
LRLAP0
R/W-0/0
LRLBP1
R/W-0/0
LRLBP0
U-0
—
R/W-0/0
LRLAT2
R/W-0/0
LRLAT1
R/W-0/0
LRLAT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-4
LRLAP<1:0>: LCD Reference Ladder A Time Power Control bits
During Time interval A (Refer to Figure 21-4):
00= Internal LCD Reference Ladder is powered down and unconnected
01= Internal LCD Reference Ladder is powered in low-power mode
10= Internal LCD Reference Ladder is powered in medium-power mode
11= Internal LCD Reference Ladder is powered in high-power mode
LRLBP<1:0>: LCD Reference Ladder B Time Power Control bits
During Time interval B (Refer to Figure 21-4):
00= Internal LCD Reference Ladder is powered down and unconnected
01= Internal LCD Reference Ladder is powered in low-power mode
10= Internal LCD Reference Ladder is powered in medium-power mode
11= Internal LCD Reference Ladder is powered in high-power mode
bit 3
Unimplemented: Read as ‘0’
bit 2-0
LRLAT<2:0>: LCD Reference Ladder A Time interval control bits
Sets the number of 32 kHz clocks that the A Time interval power mode is active
For type A waveforms (WFT = 0):
000= Internal LCD Reference Ladder is always in ‘B’ power mode
001= Internal LCD Reference Ladder is in ‘A’ power mode for 1 clock and ‘B’ power mode for 15 clocks
010= Internal LCD Reference Ladder is in ‘A’ power mode for 2 clocks and ‘B’ power mode for 14 clocks
011= Internal LCD Reference Ladder is in ‘A’ power mode for 3 clocks and ‘B’ power mode for 13 clocks
100= Internal LCD Reference Ladder is in ‘A’ power mode for 4 clocks and ‘B’ power mode for 12 clocks
101= Internal LCD Reference Ladder is in ‘A’ power mode for 5 clocks and ‘B’ power mode for 11 clocks
110= Internal LCD Reference Ladder is in ‘A’ power mode for 6 clocks and ‘B’ power mode for 10 clocks
111= Internal LCD Reference Ladder is in ‘A’ power mode for 7 clocks and ‘B’ power mode for 9 clocks
For type B waveforms (WFT = 1):
000= Internal LCD Reference Ladder is always in ‘B’ power mode.
001= Internal LCD Reference Ladder is in ‘A’ power mode for 1 clock and ‘B’ power mode for 31 clocks
010= Internal LCD Reference Ladder is in ‘A’ power mode for 2 clocks and ‘B’ power mode for 30 clocks
011= Internal LCD Reference Ladder is in ‘A’ power mode for 3 clocks and ‘B’ power mode for 29 clocks
100= Internal LCD Reference Ladder is in ‘A’ power mode for 4 clocks and ‘B’ power mode for 28 clocks
101= Internal LCD Reference Ladder is in ‘A’ power mode for 5 clocks and ‘B’ power mode for 27 clocks
110= Internal LCD Reference Ladder is in ‘A’ power mode for 6 clocks and ‘B’ power mode for 26 clocks
111= Internal LCD Reference Ladder is in ‘A’ power mode for 7 clocks and ‘B’ power mode for 25 clocks
DS41364A-page 252
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
The contrast control circuit is used to decrease the
output voltage of the signal source by a total of
approximately 10%, when LCDCST = 111.
21.4.4
CONTRAST CONTROL
The LCD contrast control circuit consists of a
seven-tap resistor ladder, controlled by the LCDCST
bits. Refer to Figure 21-6.
Whenever the LCD module is inactive (LCDA = 0), the
contrast control ladder will be turned off (open).
FIGURE 21-6:
INTERNAL REFERENCE AND CONTRAST CONTROL BLOCK DIAGRAM
VDDIO
7 Stages
R
R
R
R
3.072V
Analog
MUX
From FVR
Buffer
7
0
To top of
Reference Ladder
LCDCST<2:0>
3
Internal Reference
Contrast control
21.4.5
INTERNAL REFERENCE
21.4.6
VLCD<3:1> PINS
Under firmware control, an internal reference for the
LCD bias voltages can be enabled. When enabled, the
source of this voltage can be either VDDIO or a voltage
3 times the main fixed voltage reference (3.072V).
When no internal reference is selected, the LCD con-
trast control circuit is disabled and LCD bias must be
provided externally.
The VLCD<3:1> pins provide the ability for an external
LCD bias network to be used instead of the internal lad-
der. Use of the VLCD<3:1> pins does not prevent use
of the internal ladder. Each VLCD pin has an indepen-
dent control in the LCDREF register (Register 21-3),
allowing access to any or all of the LCD Bias signals.
This architecture allows for maximum flexibility in differ-
ent applications
Whenever the LCD module is inactive (LCDA = 0), the
internal reference will be turned off.
For example, the VLCD<3:1> pins may be used to add
capacitors to the internal reference ladder, increasing
the drive capacity.
When the internal reference is enabled and the Fixed
Voltage Reference is selected, the LCDIRI bit can be
used to minimize power consumption by tieing into the
LCD reference ladder automatic power mode switch-
ing. When LCDIRI = 1, the power mode that the inter-
nal LCD reference ladder enables the buffer when in
power mode ‘A’ and disables it when in power mode ‘B’.
For applications where the internal contrast control is
insufficient, the firmware can choose to only enable the
VLCD3 pin, allowing an external contrast control circuit
to use the internal reference divider.
.
Note:
The LCD module automatically turns on the
fixed voltage reference when needed.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 253
PIC16F193X/LF193X
TABLE 21-5: FRAME FREQUENCY
FORMULAS
21.5 LCD Multiplex Types
The LCD driver module can be configured into one of
four multiplex types:
Multiplex
Frame Frequency =
• Static (only COM0 is used)
Static
1/2
Clock source/(4 x 1 x (LP<3:0> + 1))
Clock source/(2 x 2 x (LP<3:0> + 1))
Clock source/(1 x 3 x (LP<3:0> + 1))
Clock source/(1 x 4 x (LP<3:0> + 1))
• 1/2 multiplex (COM<1:0> are used)
• 1/3 multiplex (COM<2:0> are used)
• 1/4 multiplex (COM<3:0> are used)
1/3
1/4
The LMUX<1:0> bit setting of the LCDCON register
decides which of the LCD common pins are used (see
Table 21-4 for details).
Note:
Clock source is FOSC/256, T1OSC or
LFINTOSC.
If the pin is a digital I/O, the corresponding TRIS bit
controls the data direction. If the pin is a COM drive,
then the TRIS setting of that pin is overridden.
TABLE 21-6: APPROXIMATE FRAME
FREQUENCY (IN Hz) USING
FOSC @ 8 MHz, TIMER1 @
32.768 kHz OR LFINTOSC
TABLE 21-4: COMMON PIN USAGE
LMUX
LP<3:0>
Static
1/2
1/3
1/4
Multiplex
COM3
COM2
COM1
2
3
4
5
6
7
85
64
51
43
37
32
85
64
51
43
37
32
114
85
68
57
49
43
85
64
51
43
37
32
<1:0>
Static
1/2
00
01
10
11
Unused
Unused
Unused
Active
Unused
Unused
Active
Unused
Active
Active
Active
1/3
1/4
Active
21.6 Segment Enables
The LCDSEn registers are used to select the pin
function for each segment pin. The selection allows
each pin to operate as either an LCD segment driver or
as one of the pin’s alternate functions. To configure the
pin as a segment pin, the corresponding bits in the
LCDSEn registers must be set to ‘1’.
If the pin is a digital I/O, the corresponding TRIS bit
controls the data direction. Any bit set in the LCDSEn
registers overrides any bit settings in the corresponding
TRIS register.
Note:
On a Power-on Reset, these pins are
configured as normal I/O, not LCD pins.
21.7 Pixel Control
The LCDDATAx registers contain bits which define the
state of each pixel. Each bit defines one unique pixel.
Register 21-6 shows the correlation of each bit in the
LCDDATAx registers to the respective common and
segment signals.
Any LCD pixel location not being used for display can
be used as general purpose RAM.
21.8 LCD Frame Frequency
The rate at which the COM and SEG outputs change is
called the LCD frame frequency.
DS41364A-page 254
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 21-7: LCD SEGMENT MAPPING WORKSHEET
LCD
Function
COM0
LCDDATAx
COM1
LCDDATAx
COM2
LCDDATAx
COM3
LCDDATAx
LCD
LCD
LCD
LCD
Address
Segment
Address
Segment
Address
Segment
Address
Segment
SEG0
LCDDATA0, 0
LCDDATA0, 1
LCDDATA0, 2
LCDDATA0, 3
LCDDATA0, 4
LCDDATA0, 5
LCDDATA0, 6
LCDDATA0, 7
LCDDATA1, 0
LCDDATA1, 1
LCDDATA1, 2
LCDDATA1, 3
LCDDATA1, 4
LCDDATA1, 5
LCDDATA1, 6
LCDDATA1, 7
LCDDATA2, 0
LCDDATA2, 1
LCDDATA2, 2
LCDDATA2, 3
LCDDATA2, 4
LCDDATA2, 5
LCDDATA2, 6
LCDDATA2, 7
LCDDATA3, 0
LCDDATA3, 1
LCDDATA3, 2
LCDDATA3, 3
LCDDATA3, 4
LCDDATA3, 5
LCDDATA3, 6
LCDDATA3, 7
LCDDATA4, 0
LCDDATA4, 1
LCDDATA4, 2
LCDDATA4, 3
LCDDATA4, 4
LCDDATA4, 5
LCDDATA4, 6
LCDDATA4, 7
LCDDATA5, 0
LCDDATA5, 1
LCDDATA5, 2
LCDDATA5, 3
LCDDATA5, 4
LCDDATA5, 5
LCDDATA5, 6
LCDDATA5, 7
LCDDATA6, 0
LCDDATA6, 1
LCDDATA6, 2
LCDDATA6, 3
LCDDATA6, 4
LCDDATA6, 5
LCDDATA6, 6
LCDDATA6, 7
LCDDATA7, 0
LCDDATA7, 1
LCDDATA7, 2
LCDDATA7, 3
LCDDATA7, 4
LCDDATA7, 5
LCDDATA7, 6
LCDDATA7, 7
LCDDATA8, 0
LCDDATA8, 1
LCDDATA8, 2
LCDDATA8, 3
LCDDATA8, 4
LCDDATA8, 5
LCDDATA8, 6
LCDDATA8, 7
LCDDATA9, 0
LCDDATA9, 1
LCDDATA9, 2
LCDDATA9, 3
LCDDATA9, 4
LCDDATA9, 5
LCDDATA9, 6
LCDDATA9, 7
LCDDATA10, 0
LCDDATA10, 1
LCDDATA10, 2
LCDDATA10, 3
LCDDATA10, 4
LCDDATA10, 5
LCDDATA10, 6
LCDDATA10, 7
LCDDATA11, 0
LCDDATA11, 1
LCDDATA11, 2
LCDDATA11, 3
LCDDATA11, 4
LCDDATA11, 5
LCDDATA11, 6
LCDDATA11, 7
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 255
PIC16F193X/LF193X
The LCDs can be driven by two types of waveform:
Type-A and Type-B. In Type-A waveform, the phase
changes within each common type, whereas in Type-B
waveform, the phase changes on each frame
boundary. Thus, Type-A waveform maintains 0 VDC
over a single frame, whereas Type-B waveform takes
two frames.
21.9 LCD Waveform Generation
LCD waveforms are generated so that the net AC
voltage across the dark pixel should be maximized and
the net AC voltage across the clear pixel should be
minimized. The net DC voltage across any pixel should
be zero.
The COM signal represents the time slice for each
common, while the SEG contains the pixel data.
Note 1: If Sleep has to be executed with LCD
Sleep disabled (LCDCON<SLPEN> is
‘1’), then care must be taken to execute
Sleep only when VDC on all the pixels is
‘0’.
The pixel signal (COM-SEG) will have no DC
component and it can take only one of the two RMS
values. The higher RMS value will create a dark pixel
and a lower RMS value will create a clear pixel.
2: When the LCD clock source is FOSC/256,
if Sleep is executed, irrespective of the
LCDCON<SLPEN> setting, the LCD
immediately goes into Sleep. Thus, take
care to see that VDC on all pixels is ‘0’
when Sleep is executed.
As the number of commons increases, the delta
between the two RMS values decreases. The delta
represents the maximum contrast that the display can
have.
Figure 21-7 through Figure 21-17 provide waveforms
for static, half-multiplex, 1/3-multiplex and 1/4-multiplex
drives for Type-A and Type-B waveforms.
FIGURE 21-7:
TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE
V1
COM0
SEG0
SEG1
V0
V1
COM0
V0
V1
V0
V1
V0
COM0-SEG0
COM0-SEG1
-V1
V0
1 Frame
DS41364A-page 256
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 21-8:
TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE
V2
V1
V0
COM0
COM1
COM1
COM0
V2
V1
V0
V2
V1
V0
SEG0
SEG1
V2
V1
V0
V2
V1
V0
COM0-SEG0
-V1
-V2
V2
V1
V0
COM0-SEG1
-V1
-V2
1 Frame
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 257
PIC16F193X/LF193X
FIGURE 21-9:
TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE
V2
V1
V0
COM0
COM1
COM0
V2
V1
V0
COM1
SEG0
V2
V1
V0
V2
V1
V0
SEG1
V2
V1
V0
COM0-SEG0
-V1
-V2
V2
V1
V0
COM0-SEG1
-V1
-V2
2 Frames
DS41364A-page 258
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 21-10:
TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
COM0
COM1
COM0
COM1
SEG0
SEG1
V3
V2
V1
V0
COM0-SEG0
-V1
-V2
-V3
V3
V2
V1
V0
COM0-SEG1
-V1
-V2
-V3
1 Frame
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 259
PIC16F193X/LF193X
FIGURE 21-11:
TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
COM0
COM1
COM0
COM1
SEG0
SEG1
V3
V2
V1
V0
COM0-SEG0
-V1
-V2
-V3
V3
V2
V1
V0
COM0-SEG1
-V1
-V2
-V3
2 Frames
DS41364A-page 260
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 21-12:
TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE
V2
V1
V0
COM0
V2
V1
V0
COM2
COM1
COM2
COM1
COM0
V2
V1
V0
V2
V1
V0
SEG0
SEG2
V2
V1
V0
SEG1
V2
V1
V0
COM0-SEG0
-V1
-V2
V2
V1
V0
COM0-SEG1
-V1
-V2
1 Frame
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 261
PIC16F193X/LF193X
FIGURE 21-13:
TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE
V2
V1
V0
COM0
COM1
COM2
SEG0
SEG1
COM2
V2
V1
V0
COM1
COM0
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
COM0-SEG0
-V1
-V2
V2
V1
V0
COM0-SEG1
-V1
-V2
2 Frames
DS41364A-page 262
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 21-14:
TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
-V1
-V2
-V3
V3
V2
V1
V0
-V1
-V2
-V3
COM0
COM1
COM2
COM2
COM1
COM0
SEG0
SEG2
SEG1
COM0-SEG0
COM0-SEG1
1 Frame
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 263
PIC16F193X/LF193X
FIGURE 21-15:
TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
-V1
-V2
-V3
V3
V2
V1
V0
-V1
-V2
-V3
COM0
COM1
COM2
SEG0
SEG1
COM2
COM1
COM0
COM0-SEG0
COM0-SEG1
2 Frames
DS41364A-page 264
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 21-16:
COM3
TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE
V
V
V
V
3
2
1
0
COM2
COM0
COM1
V
V
V
V
3
2
1
0
COM1
COM0
V
V
V
V
3
2
1
0
COM2
COM3
SEG0
SEG1
V
V
V
V
3
2
1
0
V
V
V
V
3
2
1
0
V
V
V
V
3
2
1
0
V
V
V
V
-V
-V
-V
3
2
1
0
COM0-SEG0
COM0-SEG1
1
2
3
V
V
V
V
3
2
1
0
-V
-V
-V
1
2
3
1 Frame
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 265
PIC16F193X/LF193X
FIGURE 21-17:
COM3
TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE
V
V
V
V
3
2
1
0
COM2
COM0
COM1
V
V
V
V
3
2
1
0
COM1
COM0
V
V
V
V
3
2
1
0
COM2
COM3
SEG0
SEG1
V
V
V
V
3
2
1
0
V
V
V
V
3
2
1
0
V
V
V
V
3
2
1
0
V
V
V
V
-V
-V
-V
3
2
1
0
COM0-SEG0
COM0-SEG1
1
2
3
V
V
V
V
3
2
1
0
-V
-V
-V
1
2
3
2 Frames
DS41364A-page 266
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
21.10 LCD Interrupts
The LCD module provides an interrupt in two cases. An
interrupt when the LCD controller goes from active to
inactive controller. An interrupt also provides unframe
boundaries for Type B waveform. The LCD timing gen-
eration provides an interrupt that defines the LCD
frame timing.
21.10.1 LCD INTERRUPT ON MODULE
SHUTDOWN
An LCD interrupt is generated when the module com-
pletes shutting down (LCDA goes from ‘1’ to ‘0’).
21.10.2 LCD FRAME INTERRUPTS
A new frame is defined to begin at the leading edge of
the COM0 common signal. The interrupt will be set
immediately after the LCD controller completes access-
ing all pixel data required for a frame. This will occur at
a fixed interval before the frame boundary (TFINT), as
shown in Figure 21-18. The LCD controller will begin to
access data for the next frame within the interval from
the interrupt to when the controller begins to access
data after the interrupt (TFWR). New data must be writ-
ten within TFWR, as this is when the LCD controller will
begin to access the data for the next frame.
When the LCD driver is running with Type-B waveforms
and the LMUX<1:0> bits are not equal to ‘00’ (static
drive), there are some additional issues that must be
addressed. Since the DC voltage on the pixel takes two
frames to maintain zero volts, the pixel data must not
change between subsequent frames. If the pixel data
were allowed to change, the waveform for the odd
frames would not necessarily be the complement of the
waveform generated in the even frames and a DC
component would be introduced into the panel.
Therefore, when using Type-B waveforms, the user
must synchronize the LCD pixel updates to occur within
a subframe after the frame interrupt.
To correctly sequence writing while in Type-B, the
interrupt will only occur on complete phase intervals. If
the user attempts to write when the write is disabled,
the WERR bit of the LCDCON register is set and the
write does not occur.
Note: The LCD frame interrupt is not generated
when the Type-A waveform is selected and
when the Type-B with no multiplex (static)
is selected.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 267
PIC16F193X/LF193X
FIGURE 21-18:
WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE
(EXAMPLE – TYPE-B, NON-STATIC)
LCD
Interrupt
Occurs
Controller Accesses
Next Frame Data
V
V
V
V
3
2
1
0
COM0
COM1
V
V
V
V
3
2
1
0
V
V
V
V
3
2
1
0
COM2
COM3
V
V
V
V
3
2
1
0
2 Frames
TFINT
TFWR
Frame
Frame
Frame
Boundary
Boundary
Boundary
TFWR = TFRAME/2*(LMUX<1:0> + 1) + TCY/2
TFINT = (TFWR/2 – (2 TCY + 40 ns)) → minimum = 1.5(TFRAME/4) – (2 TCY + 40 ns)
(TFWR/2 – (1 TCY + 40 ns)) → maximum = 1.5(TFRAME/4) – (1 TCY + 40 ns)
DS41364A-page 268
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
Table 21-8 shows the status of the LCD module during
a Sleep while using each of the three available clock
sources.
21.11 Operation During Sleep
The LCD module can operate during Sleep. The
selection is controlled by bit SLPEN of the LCDCON
register. Setting the SLPEN bit allows the LCD module
to go to Sleep. Clearing the SLPEN bit allows the
module to continue to operate during Sleep.
Note:
When the LCDEN bit is cleared, the LCD
module will be disabled at the completion
of frame. At this time, the port pins will
revert to digital functionality. To minimize
power consumption due to floating digital
inputs, the LCD pins should be driven low
using the PORT and TRIS registers.
If a SLEEPinstruction is executed and SLPEN = 1, the
LCD module will cease all functions and go into a very
low-current Consumption mode. The module will stop
operation immediately and drive the minimum LCD
voltage on both segment and common lines.
Figure 21-19 shows this operation.
If a SLEEPinstruction is executed and SLPEN = 0, the
module will continue to display the current contents of
the LCDDATA registers. To allow the module to
continue operation while in Sleep, the clock source
must be either the LFINTOSC or T1OSC external
oscillator. While in Sleep, the LCD data cannot be
changed. The LCD module current consumption will
not decrease in this mode; however, the overall
consumption of the device will be lower due to shut
down of the core and other peripheral functions.
The LCD module can be configured to operate during
Sleep. The selection is controlled by bit SLPEN of the
LCDCON register. Clearing SLPEN and correctly con-
figuring the LCD module clock will allow the LCD mod-
ule to operate during Sleep. Setting SLPEN and
correctly executing the LCD module shutdown will dis-
able the LCD module during Sleep and save power.
If a SLEEPinstruction is executed and SLPEN = 1, the
LCD module will immediately cease all functions, drive
the outputs to Vss and go into a very low-current mode.
The SLEEP instruction should only be executed after
the LCD module has been disabled and the current
cycle completed, thus ensuring that there are no DC
voltages on the glass. To disable the LCD module,
clear the LCDEN bit. The LCD module will complete the
disabling process after the current frame, clear the
LCDA bit and optionally cause an interrupt.
Table 21-8 shows the status of the LCD module during
Sleep while using each of the three available clock
sources:
TABLE 21-8: LCD MODULE STATUS
DURING SLEEP
Operational
During Sleep
Clock Source
T1OSC
SLPEN
0
1
0
1
0
1
Yes
No
Yes
No
No
No
The steps required to properly enter Sleep with the
LCD disabled are:
• Clear LCDEN
LFINTOSC
FOSC/4
• Wait for LCDA = 0either by polling or by interrupt
• Execute SLEEP
If SLPEN = 0 and SLEEP is executed while the LCD
module clock source is FOSC/4, then the LCD module
will halt with the pin driving the last LCD voltage pat-
tern. Prolonged exposure to a fixed LCD voltage pat-
tern will cause damage to the LCD glass. To prevent
LCD glass damage, either perform the proper LCD
module shutdown prior to Sleep, or change the LCD
module clock to allow the LCD module to continue
operation during Sleep.
Note:
The LFINTOSC or external T1OSC
oscillator must be used to operate the LCD
module during Sleep.
If LCD interrupts are being generated (Type-B wave-
form with a multiplex mode not static) and LCDIE = 1,
the device will awaken from Sleep on the next frame
boundary.
If a SLEEPinstruction is executed and SLPEN = 0and
the LCD module clock is either T1OSC or LFINTOSC,
the module will continue to display the current contents
of the LCDDATA registers. While in Sleep, the LCD
data cannot be changed. If the LCDIE bit is set, the
device will wake from Sleep on the next LCD frame
boundary. The LCD module current consumption will
not decrease in this mode; however, the overall device
power consumption will be lower due to the shutdown
of the CPU and other peripherals.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 269
PIC16F193X/LF193X
FIGURE 21-19:
SLEEP ENTRY/EXIT WHEN SLPEN = 1
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
COM0
COM1
COM2
SEG0
2 Frames
Wake-up
SLEEPInstruction Execution
DS41364A-page 270
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
21.12 Configuring the LCD Module
21.14 LCD Current Consumption
The following is the sequence of steps to configure the
LCD module.
When using the LCD module the current consumption
consists of the following three factors:
1. Select the frame clock prescale using bits
LP<3:0> of the LCDPS register.
• Oscillator Selection
• LCD Bias Source
2. Configure the appropriate pins to function as
segment drivers using the LCDSEn registers.
• Capacitance of the LCD segments
The current consumption of just the LCD module can
be considered negligible compared to these other
factors.
3. Configure the LCD module for the following
using the LCDCON register:
- Multiplex and Bias mode, bits LMUX<1:0>
- Timing source, bits CS<1:0>
- Sleep mode, bit SLPEN
21.14.1 OSCILLATOR SELECTION
The current consumed by the clock source selected
must be considered when using the LCD module. See
Section 28.0 “Electrical Specifications” for oscillator
current consumption information.
4. Write initial values to pixel data registers,
LCDDATA0 through LCDDATA11 (LCDDATA23
on PIC16F1938).
5. Clear LCD Interrupt Flag, LCDIF bit of the PIR2
register and if desired, enable the interrupt by
setting bit LCDIE of the PIE2 register.
21.14.2 LCD BIAS SOURCE
The LCD bias source, internal or external, can contrib-
ute significantly to the current consumption. Use the
highest possible resistor values while maintaining
contrast to minimize current.
6. Configure bias voltages by setting the LCDRL,
LCDREF and the associated ANSELx
registers as needed.
7. Enable the LCD module by setting bit LCDEN of
the LCDCON register.
21.14.3 CAPACITANCE OF THE LCD
SEGMENTS
The LCD segments which can be modeled as capaci-
tors which must be both charged and discharged every
frame. The size of the LCD segment and its technology
determines the segment’s capacitance.
21.13 Disabling the LCD Module
To disable the LCD module, write all ‘0’s to the
LCDCON register.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 271
PIC16F193X/LF193X
TABLE 21-9: REGISTERS ASSOCIATED WITH LCD OPERATION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
LCDEN
—
PEIE
SLPEN
—
TMR0IE
WERR
—
INTE
—
IOCIE
CS1
—
TMR0IF
CS0
INTF
IOCIF
73
LCDCON
LCDCST
LMUX1
LMUX0
243
246
247
—
LCDCST2 LCDCST1 LCDCST0
LCDDATA0
SEG7
COM0
SEG6
COM0
SEG5
COM0
SEG4
COM0
SEG3
COM0
SEG2
COM0
SEG1
COM0
SEG0
COM0
LCDDATA1
LCDDATA2
LCDDATA3
LCDDATA4
LCDDATA5
LCDDATA6
LCDDATA7
LCDDATA8
LCDDATA9
LCDDATA10
LCDDATA11
SEG15
COM0
SEG14
COM0
SEG13
COM0
SEG12
COM0
SEG11
COM0
SEG10
COM0
SEG9
COM0
SEG8
COM0
247
247
247
247
247
247
247
247
247
247
247
SEG23
COM0
SEG22
COM0
SEG21
COM0
SEG20
COM0
SEG19
COM0
SEG18
COM0
SEG17
COM0
SEG16
COM0
SEG7
COM1
SEG6
COM1
SEG5
COM1
SEG4
COM1
SEG3
COM1
SEG2
COM1
SEG1
COM1
SEG0
COM1
SEG15
COM1
SEG14
COM1
SEG13
COM1
SEG12
COM1
SEG11
COM1
SEG10
COM1
SEG9
COM1
SEG8
COM1
SEG23
COM1
SEG22
COM1
SEG21
COM1
SEG20
COM1
SEG19
COM1
SEG18
COM1
SEG17
COM1
SEG16
COM1
SEG7
COM2
SEG6
COM2
SEG5
COM2
SEG4
COM2
SEG3
COM2
SEG2
COM2
SEG1
COM2
SEG0
COM2
SEG15
COM2
SEG14
COM2
SEG13
COM2
SEG12
COM2
SEG11
COM2
SEG10
COM2
SEG9
COM2
SEG8
COM2
SEG23
COM2
SEG22
COM2
SEG21
COM2
SEG20
COM2
SEG19
COM2
SEG18
COM2
SEG17
COM2
SEG16
COM2
SEG7
COM3
SEG6
COM3
SEG5
COM3
SEG4
COM3
SEG3
COM3
SEG2
COM3
SEG1
COM3
SEG0
COM3
SEG15
COM3
SEG14
COM3
SEG13
COM3
SEG12
COM3
SEG11
COM3
SEG10
COM3
SEG9
COM3
SEG8
COM3
SEG23
COM3
SEG22
COM3
SEG21
COM3
SEG20
COM3
SEG19
COM3
SEG18
COM3
SEG17
COM3
SEG16
COM3
LCDPS
LCDREF
LCDRL
LCDSE0
LCDSE1
LCDSE2
PIE2
WFT
LCDIRE
LRLAP1
SE7
BIASMD
LCDIRS
LRLAP0
SE6
LCDA
LCDIRI
LRLBP1
SE5
WA
—
LP3
LP2
LP1
LP0
—
244
245
252
247
247
247
75
VLCD3PE VLCD2PE VLCD1PE
LRLBP0
SE4
—
LRLAT2
SE2
LRLAT1
SE1
SE9
SE17
—
LRLAT0
SE0
SE3
SE15
SE14
SE13
SE21
C1IE
SE12
SE20
EEIE
EEIF
SE11
SE19
BCLIE
BCLIF
SE10
SE8
SE23
SE22
SE18
SE16
OSFIE
OSFIF
C2IE
LCDIE
LCDIF
CCP2IE
CCP2IF
TMR1ON
PIR2
C2IF
C1IF
—
78
T1CON
Legend:
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
—
169
x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by the LCD module.
DS41364A-page 272
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
Figure 22-1 is a block diagram of the SPI interface
module.
22.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
22.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C™)
The SPI interface supports the following modes and
features:
• Master mode
• Slave mode
• Clock Parity
• Slave Select Synchronization (Slave mode only)
• Daisy chain connection of Slave devices
FIGURE 22-1:
MSSP BLOCK DIAGRAM (SPI MODE)
Data Bus
Write
Read
SSPBUF Reg
SDI
SSPSR Reg
Shift
Clock
bit 0
SDO
SS
Control
Enable
SS
2 (CKP, CKE)
Clock Select
Edge
Select
SSPM<3:0>
4
TMR2 Output
(
)
2
SCK
Edge
Select
TOSC
Prescaler
4, 16, 64
Baud rate
generator
(SSPADD)
TRIS bit
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 273
PIC16F193X/LF193X
The I2C interface supports the following modes and
features:
• Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited Multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
• Address masking
• Address Hold and Data Hold modes
• Selectable SDA hold times
Figure 22-2 is a block diagram of the I2C interface mod-
ule in Master mode. Figure 22-3 is a diagram of the I2C
interface module in Slave mode.
FIGURE 22-2:
MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)
Internal
data bus
[SSPM 3:0]
Read
Write
SSPBUF
SSPSR
Baud rate
generator
(SSPADD)
SDA
Shift
Clock
SDA in
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate (SSPCON2)
SCL
Start bit detect,
Stop bit detect
SCL in
Bus Collision
Write collision detect
Clock arbitration
State counter for
Set/Reset: S, P, SSPSTAT, WCOL, SSPOV
Reset SEN, PEN (SSPCON2)
Set SSPIF, BCLIF
end of XMIT/RCV
Address Match detect
DS41364A-page 274
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 22-3:
MSSP BLOCK DIAGRAM (I2C™ SLAVE MODE)
Internal
Data Bus
Read
Write
SSPBUF Reg
SSPSR Reg
SCL
SDA
Shift
Clock
MSb
LSb
SSPMSK Reg
Match Detect
SSPADD Reg
Addr Match
Set, Reset
S, P bits
(SSPSTAT Reg)
Start and
Stop bit Detect
22.2 MSSP Control Registers
The MSSP module has seven associated registers:
• MSSP STATUS register (SSPSTAT)
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Control Register 3 (SSPCON3)
• MSSP Address Masking register (SSPMSK)
• MSSP Data Buffer register (SSPBUF)
• MSSP Address register (SSPADD)
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 275
PIC16F193X/LF193X
REGISTER 22-1: SSPSTAT: SSP STATUS REGISTER
R/W-0/0
SMP
R/W-0/0
CKE
R-0/0
D/A
R-0/0
P
R-0/0
S
R-0/0
R/W
R-0/0
UA
R-0/0
BF
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
SMP: SPI Data Input Sample bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
2
In I C Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high speed mode (400 kHz)
bit 6
CKE: SPI Clock Edge Select bit (SPI mode only)
CKP = 0:
1= Data transmitted on rising edge of SCK
0= Data transmitted on falling edge of SCK
CKP = 1:
1= Data transmitted on falling edge of SCK
0= Data transmitted on rising edge of SCK
2
bit 5
bit 4
D/A: Data/Address bit (I C mode only)
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
P: Stop bit
2
(I C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1= Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0= Stop bit was not detected last
bit 3
bit 2
S: Start bit
2
(I C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1= Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0= Start bit was not detected last
2
R/W: Read/Write bit information (I C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match
to the next Start bit, Stop bit, or not ACK bit.
2
In I C Slave mode:
1= Read
0= Write
2
In I C Master mode:
1= Transmit is in progress
0= Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode.
2
bit 1
bit 0
UA: Update Address bit (10-bit I C mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
2
Receive (SPI and I C modes):
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
2
Transmit (I C mode only):
1= Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0= Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
DS41364A-page 276
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
REGISTER 22-2: SSPCON1: SSP CONTROL REGISTER 1
R/W-0/0
WCOL
R/W-0/0
SSPOV
R/W-0/0
SSPEN
R/W-0/0
CKP
R/W-0/0
SSPM3
R/W-0/0
SSPM2
R/W-0/0
SSPM1
R/W-0/0
SSPM0
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
WCOL: Write Collision Detect bit
Master mode:
1= A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started
0= No collision
Slave mode:
1= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
0= No collision
bit 6
SSPOV: Receive Overflow Indicator bit(1)
In SPI mode:
1= A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost.
Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid
setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPBUF register (must be cleared in software).
0= No overflow
In I2C mode:
1= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode
(must be cleared in software).
0= No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1= Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2)
0= Disables serial port and configures these pins as I/O port pins
In I2C mode:
1= Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3)
0= Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1= Idle state for clock is a high level
0= Idle state for clock is a low level
In I2C Slave mode:
SCK release control
1= Enable clock
0= Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2C Master mode:
Unused in this mode
bit 3-0
SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000= SPI Master mode, clock = FOSC/4
0001= SPI Master mode, clock = FOSC/16
0010= SPI Master mode, clock = FOSC/64
0011= SPI Master mode, clock = TMR2 output/2
0100= SPI Slave mode, clock = SCK pin, SS pin control enabled
0101= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0110= I2C Slave mode, 7-bit address
0111= I2C Slave mode, 10-bit address
1000= I2C Master mode, clock = FOSC / (4 * (SSPADD+1))(4)
1001= Reserved
1010= SPI Master mode, clock = FOSC/(4 * (SSPADD+1))
1011= I2C firmware controlled Master mode (Slave idle)
1100= Reserved
1101= Reserved
1110= I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111= I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
Note 1:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register.
When enabled, these pins must be properly configured as input or output.
When enabled, the SDA and SCL pins must be configured as inputs.
SSPADD values of 0, 1 or 2 are not supported for I2C Mode.
2:
3:
4:
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 277
PIC16F193X/LF193X
REGISTER 22-3: SSPCON2: SSP CONTROL REGISTER 2
R/W-0/0
GCEN
R-0/0
R/W-0/0
ACKDT
R/W-0/0
ACKEN
R/W-0/0
RCEN
R/W-0/0
PEN
R/W-0/0
RSEN
R/W-0/0
SEN
ACKSTAT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
GCEN: General Call Enable bit (in I2C Slave mode only)
1= Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR
0= General call address disabled
ACKSTAT: Acknowledge Status bit (in I2C mode only)
1= Acknowledge was not received
0= Acknowledge was received
ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1= Not Acknowledge
0= Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1= Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0= Acknowledge sequence idle
bit 3
bit 2
RCEN: Receive Enable bit (in I2C Master mode only)
1= Enables Receive mode for I2C
0= Receive idle
PEN: Stop Condition Enable bit (in I2C Master mode only)
SCK Release Control:
1= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0= Stop condition Idle
bit 1
bit 0
RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only)
1= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Repeated Start condition Idle
SEN: Start Condition Enabled bit (in I2C Master mode only)
In Master mode:
1= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Start condition Idle
In Slave mode:
1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0= Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
DS41364A-page 278
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
REGISTER 22-4: SSPCON3: SSP CONTROL REGISTER 3
R-0/0
R/W-0/0
PCIE
R/W-0/0
SCIE
R/W-0/0
BOEN
R/W-0/0
SDAHT
R/W-0/0
SBCDE
R/W-0/0
AHEN
R/W-0/0
DHEN
ACKTIM
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
ACKTIM: Acknowledge Time Status bit (I2C mode only)
1= Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCL clock
0= Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock
PCIE: Stop Condition Interrupt Enable bit (I2C mode only)
1= Enable interrupt on detection of Stop condition
0= Stop detection interrupts are disabled(2)
SCIE: Start Condition Interrupt Enable bit (I2C mode only)
1= Enable interrupt on detection of Start or Restart conditions
0= Start detection interrupts are disabled(2)
BOEN: Buffer Overwrite Enable bit
In SPI Slave mode:(1)
1= SSPBUF updates every time that a new data byte is shifted in ignoring the BF bit
0 = If new byte is received with BF bit of the SSPSTAT register already set, SSPOV bit of the
SSPCON1 register is set, and the buffer is not updated
In I2C Master mode:
This bit is ignored.
In I2C Slave mode:
1= SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state
of the SSPOV bit only if the BF bit = 0.
0= SSPBUF is only updated when SSPOV is clear
bit 3
bit 2
SDAHT: SDA Hold Time Selection bit (I2C mode only)
1= Minimum of 300 ns hold time on SDA after the falling edge of SCL
0= Minimum of 100 ns hold time on SDA after the falling edge of SCL
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCLIF
bit of the PIR2 register is set, and bus goes idle
1= Enable slave bus collision interrupts
0= Slave bus collision interrupts are disabled
bit 1
bit 0
AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the
SSPCON1 register will be cleared and the SCL will be held low.
0= Address holding is disabled
DHEN: Data Hold Enable bit (I2C Slave mode only)
1= Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit
of the SSPCON1 register and SCL is held low.
0= Data holding is disabled
Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPBUF.
2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 279
PIC16F193X/LF193X
REGISTER 22-5: SSPMSK: SSP MASK REGISTER
R/W-1/1
MSK7
R/W-1/1
MSK6
R/W-1/1
MSK5
R/W-1/1
MSK4
R/W-1/1
MSK3
R/W-1/1
MSK2
R/W-1/1
MSK1
R/W-1/1
(2)
MSK0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-1
bit 0
MSK<7:1>: Mask bits
2
1= The received address bit n is compared to SSPADD<n> to detect I C address match
0= The received address bit n is not used to detect I C address match
2
2
MSK<0>: Mask bit for I C Slave mode, 10-bit Address
2
I C Slave mode, 10-bit address (SSPM<3:0> = 0111or 1111):
2
1= The received address bit 0 is compared to SSPADD<0> to detect I C address match
2
0= The received address bit 0 is not used to detect I C address match
2
I C Slave mode, 7-bit address, the bit is ignored
REGISTER 22-6: SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0/0
ADD7
R/W-0/0
ADD6
R/W-0/0
ADD5
R/W-0/0
ADD4
R/W-0/0
ADD3
R/W-0/0
ADD2
R/W-0/0
ADD1
R/W-0/0
ADD0
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
Master mode:
bit 7-0
ADD<7:0>: Baud Rate Clock Divider bits
SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-Bit Slave mode — Most Significant Address byte:
bit 7-3
Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pat-
tern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are
compared by hardware and are not affected by the value in this register.
bit 2-1
bit 0
ADD<2:1>: Two Most Significant bits of 10-bit address
Not used: Unused in this mode. Bit state is a “don’t care”.
10-Bit Slave mode — Least Significant Address byte:
bit 7-0
ADD<7:0>: Eight Least Significant bits of 10-bit address
7-Bit Slave mode:
bit 7-1
bit 0
ADD<7:1>: 7-bit address
Not used: Unused in this mode. Bit state is a “don’t care”.
DS41364A-page 280
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
22.3.2 OPERATIONS
22.3 SPI Mode
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four clock
modes of SPI are supported in both Master and Slave
modes. To accomplish communication, typically three
pins are used:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
• Data Input Sample Phase (middle or end of data
output time)
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Clock Edge (output data on rising/falling edge of
SCK)
• Slave Select (SS)
• Clock Rate (Master mode only)
Figure 22-1 shows the block diagram of the MSSP
module when operating in SPI mode.
• Slave Select mode (Slave mode only)
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then, the Buffer Full Detect bit, BF of the
SSPSTAT register, and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored and the write collision detect bit WCOL
of the SSPCON1 register, will be set. User software
must clear the WCOL bit to allow the following write(s)
to the SSPBUF register to complete successfully.
22.3.1 REGISTERS
The MSSP module has five registers for SPI mode
operation. These are:
• MSSP STATUS register (SSPSTAT)
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 3 (SSPCON3)
• MSSP Data Buffer register (SSPBUF)
• MSSP Address register (SSPADD)
• MSSP Shift register (SSPSR)
(Not directly accessible)
SSPCON1 and SSPSTAT are the control and STATUS
registers in SPI mode operation. The SSPCON1 regis-
ter is readable and writable. The lower 6 bits of the
SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF of the SSPSTAT register, indicates
when SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to
be used, then software polling can be done to ensure
that a write collision does not occur.
In one SPI master mode, SSPADD can be loaded with
a value used in the Baud Rate Generator. More infor-
mation on the Baud Rate Generator is available in
Section 22.7 “Baud Rate Generator”.
SSPSR is the shift register used for shifting data in and
out. SSPBUF provides indirect access to the SSPSR
register. SSPBUF is the buffer register to which data
bytes are written, and from which data bytes are read.
In receive operations, SSPSR and SSPBUF together
create a buffered receiver. When SSPSR receives a
complete byte, it is transferred to SSPBUF and the
SSPIF interrupt is set.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the SSPSTAT register indicates the
various Status conditions.
During transmission, the SSPBUF is not buffered. A
write to SSPBUF will write to both SSPBUF and
SSPSR.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 281
PIC16F193X/LF193X
22.3.3 ENABLING SPI I/O
22.3.4
TYPICAL CONNECTION
Figure 22-4 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
To enable the serial port, SSP Enable bit, SSPEN of the
SSPCON1 register, must be set. To reset or reconfig-
ure SPI mode, clear the SSPEN bit, re-initialize the
SSPCONx registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
• SDI must have corresponding TRIS bit set
• SDO must have corresponding TRIS bit cleared
• SCK (Master mode) must have corresponding
TRIS bit cleared
• Master sends data (Slave sends dummy data)
• Master sends data (Slave sends data)
• SCK (Slave mode) must have corresponding
TRIS bit set
• Master sends dummy data (Slave sends data)
• SS must have corresponding TRIS bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 22-4:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xx
= 1010
SPI Slave SSPM<3:0> = 010x
SDO
SDI
Serial Input Buffer
Serial Input Buffer
(SSPBUF)
(SSPBUF)
SDI
SDO
Shift Register
(SSPSR)
Shift Register
(SSPSR)
LSb
MSb
MSb
LSb
Serial Clock
SCK
SCK
SS
Slave Select
(optional)
General I/O
Processor 2
Processor 1
DS41364A-page 282
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
The clock polarity is selected by appropriately
programming the CKP bit of the SSPCON1 register
and the CKE bit of the SSPSTAT register. This then,
would give waveforms for SPI communication as
shown in Figure 22-5, Figure 22-6 and Figure 22-7,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
22.3.5
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 22-4) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and Status bits
appropriately set).
• FOSC/4 (or TCY)
• FOSC/16 (or 4 * TCY)
• FOSC/64 (or 16 * TCY)
• Timer2 output/2
• Fosc/(4 * (SSPADD + 1))
Figure 22-5 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
FIGURE 22-5:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
bit 6
bit 6
bit 2
bit 2
bit 5
bit 5
bit 4
bit 4
bit 1
bit 1
bit 0
bit 0
SDO
(CKE = 0)
bit 7
bit 7
bit 3
bit 3
SDO
(CKE = 1)
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 283
PIC16F193X/LF193X
22.3.6
SLAVE MODE
22.3.7 SLAVE SELECT SYNCHRONIZATION
In Slave mode, the data is transmitted and received as
external clock pulses appear on SCK. When the last
bit is latched, the SSPIF interrupt flag bit is set.
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPCON1<3:0> = 0100).
Before enabling the module in SPI Slave mode, the clock
line must match the proper Idle state. The clock line can
be observed by reading the SCK pin. The Idle state is
determined by the CKP bit of the SSPCON1 register.
When the SS pin is low, transmission and reception are
enabled and the SDO pin is driven.
When the SS pin goes high, the SDO pin is no longer
driven, even if in the middle of a transmitted byte and
becomes a floating output. External pull-up/pull-down
resistors may be desirable depending on the applica-
tion.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
Note 1: When the SPI is in Slave mode with SS pin
While in Sleep mode, the slave can transmit/receive
data. The shift register is clocked from the SCK pin
input and when a byte is received, the device will gen-
erate an interrupt. If enabled, the device will wake-up
from Sleep.
control enabled (SSPCON1<3:0>
=
0100), the SPI module will reset if the SS
pin is set to VDD.
2: When the SPI is used in Slave mode with
CKE set; the user must enable SS pin
control.
22.3.6.1 Buffer Overwrite Enable
3: While operated in SPI Slave mode the
SMP bit of the SSPSTAT register must
remain clear.
In SPI daisy-chained configurations only the most
recent byte on the bus is required by the slave. Setting
the BOEN bit of the SSPCON3 register will enable
writes to the SSPBUF register, even if the previous
byte has not been read. Allowing the software to
ignore data that may not apply to it.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
FIGURE 22-6:
SLAVE SELECT SYNCRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
Shift register SSPSR
and bit count are reset
SSPBUF to
SSPSR
bit 6
bit 6
bit 7
bit 7
bit 0
SDO
SDI
bit 7
bit 0
bit 7
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
DS41364A-page 284
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 22-7:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
Valid
bit 6
bit 2
bit 5
bit 4
bit 3
bit 1
bit 0
SDO
bit 7
SDI
bit 0
bit 7
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Write Collision
detection active
FIGURE 22-8:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
Valid
bit 6
bit 3
bit 2
bit 5
bit 4
bit 1
bit 0
SDO
bit 7
bit 7
SDI
bit 0
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Write Collision
detection active
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 285
PIC16F193X/LF193X
22.3.8 OPERATION IN POWER-MANAGED
MODES
If an exit from Sleep or Idle mode is not desired, MSSP
interrupts should be disabled.
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the MSSP
clock is much faster than the system clock.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI
Transmit/Receive Shift register. When all 8 bits have
been received, the MSSP interrupt flag bit will be set
and if enabled, will wake the device.
When MSSP interrupts are enabled, after the master
completes sending data, an MSSP interrupt will wake
the controller:
• from Sleep, in Slave mode
• from Idle, in Slave or Master mode
TABLE 22-1: REGISTERS ASSOCIATED WITH SPI OPERATION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APFCON
INTCON
PIE1
—
CCP3SEL
PEIE
T1GSEL
TMR0IE
RCIE
P2BSEL
INTE
SRNQSEL C2OUTSEL
SSSEL
INTF
CCP2SEL
IOCIF
84
73
GIE
IOCIE
SSPIE
SSPIF
TMR0IF
CCP1IE
CCP1IF
TMR1GIE
TMR1GIf
ADIE
TXIE
TMR2IE
TMR2IF
TMR1IE
TMR1IF
74
PIR1
ADIF
RCIF
TXIF
77
SSPBUF
SSPCON1
SSPCON3
Synchronous Serial Port Receive Buffer/Transmit Register
281*
277
279
276
86
WCOL
SSPOV
PCIE
SSPEN
SCIE
CKP
SSPM3
SDAHT
SSPM2
SBCDE
SSPM1
AHEN
SSPM0
DHEN
ACKTIM
BOEN
SSPSTAT
TRISA
SMP
CKE
D/A
P
S
R/W
UA
BF
TRISA7
TRISC7
TRISA6
TRISC6
TRISA5
TRISC5
TRISA4
TRISC4
TRISA3
TRISC3
TRISA2
TRISC2
TRISA1
TRISC1
TRISA0
TRISC0
TRISC
94
Legend:
Shaded cells are not used by the MSSP in SPI mode.
Page provides register information.
*
DS41364A-page 286
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 22-2: I2C BUS TERMS
22.4 I2C MODE
TERM
Description
All MSSP I2C communication is byte oriented and
shifted out MSb first. Six SFR registers and 2 interrupt
flags interface the module with the PIC® microcon-
troller and user software. Two pins, SDA and SCL, are
exercised by the module to communicate with other
external I2C devices.
Transmitter
The device which shifts data out
onto the bus.
Receiver
Master
The device which shifts data in
from the bus.
The device that initiates a transfer,
generates clock signals and termi-
nates a transfer.
22.4.1 SDA AND SCL PINS
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain. These
pins should be set by the user to inputs by setting the
appropriate TRIS bits.
Slave
The device addressed by the mas-
ter.
Multi-master
Arbitration
A bus with more than one device
that can initiate data transfers.
Note: Data is tied to output zero when an I2C mode
Procedure to ensure that only one
master at a time controls the bus.
Winning arbitration ensures that
the message is not corrupted.
is enabled.
22.4.2 BYTE FORMAT
All communication in I2C is done in 9-bit segments. A
byte is sent from a Master to a Slave or vice-versa, fol-
lowed by an Acknowledge bit sent back. After the 8th
falling edge of the SCL line, the device outputting data
on the SDA changes that pin to an input and reads in
an acknowledge value on the next clock pulse.
Synchronization Procedure to synchronize the
clocks of two or more devices on
the bus.
Idle
No master is controlling the bus,
and both SDA and SCL lines are
high.
Active
Any time one or more master
devices are controlling the bus.
The clock signal, SCL, is provided by the master. Data
is valid to change while the SCL signal is low, and
sampled on the rising edge of the clock. Changes on
the SDA line while the SCL line is high define special
conditions on the bus, explained below.
Addressed
Slave
Slave device that has received a
matching address and is actively
being clocked by a master.
Matching
Address
Address byte that is clocked into a
slave that matches the value
stored in SSPADD.
22.4.3 DEFINITION OF I2C TERMINOLOGY
There is language and terminology in the description
of I2C communication that have definitions specific to
I2C. That word usage is defined below and may be
used in the rest of this document without explana-
tion. This table was adapted from the Phillips I2C
specification.
Write Request
Read Request
Slave receives a matching
address with R/W bit clear, and is
ready to clock in data.
Master sends an address byte with
the R/W bit set, indicating that it
wishes to clock data out of the
Slave. This data is the next and all
following bytes until a Restart or
Stop.
Clock Stretching When a device on the bus hold
SCL low to stall communication.
Bus Collision
Any time the SDA line is sampled
low by the module while it is out-
putting and expected high state.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 287
PIC16F193X/LF193X
22.4.4 START CONDITION
22.4.6 RESTART CONDITION
The I2C specification defines a Start condition as a
transition of SDA from a high to a low state while SCL
line is high. A Start condition is always generated by
the master and signifies the transition of the bus from
an Idle to an Active state. Figure 22-8 shows wave
forms for Start and Stop conditions.
A Restart is valid any time that a Stop would be valid.
A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address. The master may want to address the same or
another slave.
A bus collision can occur on a Start condition if the
module samples the SDA line low before asserting it
low. This does not conform to the I2C Specification that
states no bus collision can occur on a Start.
In 10-bit Addressing Slave mode a Restart is required
for the master to clock data out of the addressed
slave. Once a slave has been fully address, matching
both high and low address bytes, the master can issue
a Restart and the high address byte with the R/W bit
set. The slave logic will then hold the clock and pre-
pare to clock out data.
Note: The Philips I2C Specification states that a
bus collision cannot occur on a Start, and
should occur during the address sequence.
22.4.5 STOP CONDITION
After a full match with R/W clear in 10-bit mode, a prior
match flag is set and maintained. Until a Stop condi-
tion, a high address with R/W clear, or high address
match fails.
A Stop condition is a transition of the SDA line from
low to high state while the SCL line is high.
Note: At least one SCL low time must appear
before a Stop is valid, therefore, if the SDA
line goes low then high again while the SCL
line stays high, only the Start condition is
detected.
22.4.7 START/STOP CONDITION INTERRUPT
MASKING
The SCIE and PCIE bits of the SSPCON3 register can
enable the generation of an interrupt in Slave mode.
Slave modes where interrupt on Start and Stop detect
are already enabled, these bits will have no effect.
FIGURE 22-9:
I2C START AND STOP CONDITIONS
SDA
SCL
S
P
Change of
Change of
Data Allowed
Data Allowed
Stop
Start
Condition
Condition
DS41364A-page 288
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 22-10:
I2C RESTART CONDITION
Sr
Change of
Change of
Data Allowed
Data Allowed
Restart
Condition
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 289
PIC16F193X/LF193X
22.5 I2C SLAVE MODE OPERATION
22.4.8 ACKNOWLEDGE SEQUENCE
The 9th SCL pulse for any transferred byte in I2C is
dedicated as an Acknowledge. It allows receiving
devices to respond back to the transmitter by pulling
the SDA line low. The transmitter must release control
of the line during this time to shift in the response. The
Acknowledge (ACK) is an active-low signal, pulling the
SDA line low indicated to the transmitter that the
device has received the transmitted data and is ready
to receive more.
The MSSP Slave mode operates in one of four modes
selected in the SSPM bits of SSPCON1 register. The
modes can be divided into 7-bit and 10-bit Addressing
mode. 10-bit Addressing modes operate the same as
7-bit with some additional overhead for handling the
larger addresses.
Modes with Start and Stop bit interrupts operated the
same as the other modes with SSPIF additionally get-
ting set upon detection of a Start, Restart, or Stop
condition.
The result of an ACK is placed in the ACKSTAT bit of
the SSPCON2 register.
22.5.1 SLAVE MODE ADDRESSES
Slave software, when the AHEN and DHEN bits are
set, allow the user to set the ACK value sent back to
the transmitter. The ACKDT bit of the SSPCON2 regis-
ter is set/cleared to determine the response.
The SSPADD register (Register 22-6) contains the
Slave mode address. The first byte received after a
Start or Restart condition is compared against the
value stored in this register. If the byte matches the
value is loaded into the SSPBUF register and an inter-
rupt is generated. If the value does not match, the
module goes idle and no indication is given to the soft-
ware that anything happened.
Slave hardware will generate an ACK response if the
AHEN and DHEN bits of the SSPCON3 register are
clear.
There are certain conditions where an ACK will not be
sent by the slave. If the BF bit of the SSPSTAT register
or the SSPOV bit of the SSPCON1 register are set
when a byte is received.
The SSP Mask register (Register 22-5) affects the
address matching process. See Section 22.5.9 “SSP
Mask Register” for more information.
22.5.1.1 I2C Slave 7-bit Addressing Mode
In 7-bit Addressing mode, the LSb of the received data
byte is ignored when determining if there is an address
match.
22.5.1.2 I2C Slave 10-bit Addressing Mode
In 10-bit Addressing mode, the first received byte is
compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9
and A8 are the two MSb of the 10-bit address and
stored in bits 2 and 1 of the SSPADD register.
After the acknowledge of the high byte the UA bit is set
and SCL is held low until the user updates SSPADD
with the low address. The low address byte is clocked
in and all 8 bits are compared to the low address value
in SSPADD. Even if there is not an address match;
SSPIF and UA are set, and SCL is held low until
SSPADD is updated to receive a high byte again.
When SSPADD is updated the UA bit is cleared. This
ensures the module is ready to receive the high
address byte on the next communication.
A high and low address match as a write request is
required at the start of all 10-bit addressing communi-
cation. A transmission can be initiated by issuing a
Restart once the slave is addressed, and clocking in
the high address with the R/W bit set. The slave hard-
ware will then acknowledge the read request and pre-
pare to clock out data. This is only valid for a slave
after it has received a complete high and low address
byte match.
DS41364A-page 290
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
22.5.2 SLAVE RECEPTION
22.5.2.2 7-bit Reception with AHEN and DHEN
When the R/W bit of a matching received address byte
is clear, the R/W bit of the SSPSTAT register is cleared.
The received address is loaded into the SSPBUF reg-
ister and acknowledged.
Slave device reception with AHEN and DHEN set
operate the same as without these options with extra
interrupts and clock stretching added after the 8th fall-
ing edge of SCL. These additional interrupts allow the
slave software to decide whether it wants to ACK the
receive address or data byte, rather than the hard-
ware. This functionality adds support for PMBus™ that
was not present on previous versions of this module.
When the overflow condition exists for a received
address, then not Acknowledge is given. An overflow
condition is defined as either bit BF bit of the SSPSTAT
register is set, or bit SSPOV bit of the SSPCON1 reg-
ister is set. The BOEN bit of the SSPCON3 register
modifies this operation. For more information see
Register 22-4.
This list describes the steps that need to be taken by
slave software to use these options for I2C commun-
cation. Figure 22-12 displays a module using both
address and data holding. Figure 22-13 includes the
operation with the SEN bit of the SSPCON2 register
set.
An MSSP interrupt is generated for each transferred
data byte. Flag bit, SSPIF, must be cleared by software.
When the SEN bit of the SSPCON2 register is set, SCL
will be held low (clock stretch) following each received
byte. The clock must be released by setting the CKP
bit of the SSPCON1 register, except sometimes in
10-bit mode. See Section 22.3.5 “Master Mode” for
more detail.
1. S bit of SSPSTAT is set; SSPIF is set if interrupt
on Start detect is enabled.
2. Matching address with R/W bit clear is clocked
in. SSPIF is set and CKP cleared after the 8th
falling edge of SCL.
3. Slave clears the SSPIF.
22.5.2.1 7-bit Addressing Reception
4. Slave can look at the ACKTIM bit of the
SSPCON3 register to determine if the SSPIF
was after or before the ACK.
This section describes a standard sequence of events
for the MSSP module configured as an I2C Slave in
7-bit Addressing mode. All decisions made by hard-
ware or software and their effect on reception.
Figure 22-10 and Figure 22-11 is used as a visual
reference for this description.
5. Slave reads the address value from SSPBUF,
clearing the BF flag.
6. Slave sets ACK value clocked out to the master
by setting ACKDT.
This is a step by step process of what typically must
be done to accomplish I2C communication.
7. Slave releases the clock by setting CKP.
8. SSPIF is set after an ACK, not after a NACK.
1. Start bit detected.
9. If SEN = 1 the slave hardware will stretch the
clock after the ACK.
2. S bit of SSPSTAT is set; SSPIF is set if interrupt
on Start detect is enabled.
10. Slave clears SSPIF.
3. Matching address with R/W bit clear is received.
Note: SSPIF is still set after the 9th falling edge of
SCL even if there is no clock stretching and
BF has been cleared. Only if NACK is sent to
Master is SSPIF not set
4. The slave pulls SDA low sending an ACK to the
master, and sets SSPIF bit.
5. Software clears the SSPIF bit.
6. Software reads received address from SSPBUF
clearing the BF flag.
11. SSPIF set and CKP cleared after 8th falling
edge of SCL for a received data byte.
7. If SEN = 1; Slave software sets CKP bit to
12. Slave looks at ACKTIM bit of SSPCON3 to
determine the source of the interrupt.
release the SCL line.
8. The master clocks out a data byte.
13. Slave reads the received data from SSPBUF
clearing BF.
9. Slave drives SDA low sending an ACK to the
master, and sets SSPIF bit.
14. Steps 7-14 are the same for each received data
byte.
10. Software clears SSPIF.
15. Communication is ended by either the slave
sending an ACK = 1, or the master sending a
Stop condition. If a Stop is sent and Interrupt on
Stop Detect is disabled, the slave will only know
by polling the P bit of the SSTSTAT register.
11. Software reads the received byte from SSPBUF
clearing BF.
12. Steps 8-12 are repeated for all received bytes
from the Master.
13. Master sends Stop condition, setting P bit of
SSPSTAT, and the bus goes idle.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 291
PIC16F193X/LF193X
FIGURE 22-11:
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
DS41364A-page 292
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 22-12:
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 293
PIC16F193X/LF193X
FIGURE 22-13:
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
DS41364A-page 294
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 22-14:
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 295
PIC16F193X/LF193X
22.5.3 SLAVE TRANSMISSION
22.5.3.1 7-bit Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register, and an ACK pulse is
sent by the slave on the ninth bit.
A Master device can transmit a read request to a
slave, and then clock data out of the slave. The list
below outlines what software for a slave will need to
do to accomplish
a
standard transmission.
Figure 22-14 can be used as a reference to this list.
Following the ACK, slave hardware clears the CKP bit
and the SCL pin is held low (see Section 22.5.6
“Clock Stretching” for more detail). By stretching the
clock, the master will be unable to assert another clock
pulse until the slave is done preparing the transmit
data.
1. Master sends a Start condition on SDA and
SCL.
2. S bit of SSPSTAT is set; SSPIF is set if interrupt
on Start detect is enabled.
3. Matching address with R/W bit set is received by
the Slave setting SSPIF bit.
The transmit data must be loaded into the SSPBUF
register which also loads the SSPSR register. Then the
SCL pin should be released by setting the CKP bit of
the SSPCON1 register. The eight data bits are shifted
out on the falling edge of the SCL input. This ensures
that the SDA signal is valid during the SCL high time.
4. Slave hardware generates an ACK and sets
SSPIF.
5. SSPIF bit is cleared by user.
6. Software reads the received address from SSP-
BUF, clearing BF.
7. R/W is set so CKP was automatically cleared
after the ACK.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. This ACK
value is copied to the ACKSTAT bit of the SSPCON2
register. If ACKSTAT is set (not ACK), then the data
transfer is complete. In this case, when the not ACK is
latched by the slave, the slave goes idle and waits for
another occurrence of the Start bit. If the SDA line was
low (ACK), the next transmit data must be loaded into
the SSPBUF register. Again, the SCL pin must be
released by setting bit CKP.
8. The slave software loads the transmit data into
SSPBUF.
9. CKP bit is set releasing SCL, allowing the mas-
ter to clock the data out of the slave.
10. SSPIF is set after the ACK response from the
master is loaded into the ACKSTAT register.
11. SSPIF bit is cleared.
12. The slave software checks the ACKSTAT bit to
see if the master wants to clock out more data.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared by software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
Note 1: If the master ACKs the clock will be
stretched.
2: ACKSTAT is the only bit updated on the
rising edge of SCL (9th) rather than the
falling.
13. Steps 9-13 are repeated for each transmitted
byte.
14. If the master sends a not ACK; the clock is not
held, but SSPIF is still set.
15. The master sends a Restart condition or a Stop.
16. The slave is no longer addressed.
DS41364A-page 296
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 22-15:
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 297
PIC16F193X/LF193X
22.5.3.2 7-bit TRANSMISSION WITH Address Hold
Enabled
Setting the AHEN bit of the SSPCON3 register
enables additional clock stretching and interrupt gen-
eration after the 8th falling edge of a received match-
ing address. Once a matching address has been
clocked in, CKP is cleared and the SSPIF interrupt is
set.
Figure 22-15 displays a standard waveform of a 7-bit
Address Slave Transmission with AHEN enabled.
1. Bus starts Idle.
2. Master sends Start condition; the S bit of
SSPSTAT is set; SSPIF is set if interrupt on Start
detect is enabled.
3. Master sends matching address with R/W bit
set. After the 8th falling edge of the SCL line the
CKP bit is cleared and SSPIF interrupt is gener-
ated.
4. Slave software clears SSPIF.
5. Slave software reads ACKTIM bit of SSPCON3
register, and R/W and D/A of the SSPSTAT reg-
ister to determine the source of the interrupt.
6. Slave reads the address value from the
SSPBUF register clearing the BF bit.
7. Slave software decides from this information if it
wishes to ACK or not ACK and sets ACKDT bit
of the SSPCON2 register accordingly.
8. Slave sets the CKP bit releasing SCL.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSPIF after the ACK if the R/W bit is
set.
11. Slave software clears SSPIF.
12. Slave loads value to transmit to the master into
SSPBUF setting the BF bit.
Note: SSPBUF cannot be loaded until after the
ACK.
13. Slave sets CKP bit releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the 9th SCL pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSPCON2 register.
16. Steps 10-15 are repeated for each byte transmit-
ted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note: Master must send a not ACK on the last byte
to ensure that the slave releases the SCL
line to receive a Stop.
DS41364A-page 298
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 22-16:
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 299
PIC16F193X/LF193X
22.5.4 SLAVE MODE 10-BIT ADDRESS
RECEPTION
22.5.5 10-BIT ADDRESSING WITH ADDRESS OR
DATA HOLD
This section describes a standard sequence of events
for the MSSP module configured as an I2C Slave in
10-bit Addressing mode.
Reception using 10-bit addressing with AHEN or
DHEN set is the same as with 7-bit modes. The only
difference is the need to update the SSPADD register
using the UA bit. All functionality, specifically when the
CKP bit is cleared and SCL line is held low are the
same. Figure 22-17 can be used as a reference of a
slave in 10-bit addressing with AHEN set.
Figure 22-16 and is used as a visual reference for this
description.
This is a step by step process of what must be done by
slave software to accomplish I2C communication.
Figure 22-18 shows a standard waveform for a slave
transmitter in 10-bit Addressing mode.
1. Bus starts Idle.
2. Master sends Start condition; S bit of SSPSTAT
is set; SSPIF is set if interrupt on Start detect is
enabled.
3. Master sends matching high address with R/W
bit clear; UA bit of the SSPSTAT register is set.
4. Slave sends ACK and SSPIF is set.
5. Software clears the SSPIF bit.
6. Software reads received address from SSPBUF
clearing the BF flag.
7. Slave loads low address into SSPADD,
releasing SCL.
8. Master sends matching low address byte to the
Slave; UA bit is set.
Note: Updates to the SSPADD register are not
allowed until after the ACK sequence.
9. Slave sends ACK and SSPIF is set.
Note: If the low address does not match, SSPIF
and UA are still set so that the slave software
can set SSPADD back to the high address.
BF is not set because there is no match.
CKP is unaffected.
10. Slave clears SSPIF.
11. Slave reads the received matching address
from SSPBUF clearing BF.
12. Slave loads high address into SSPADD.
13. Master clocks a data byte to the slave and
clocks out the slaves ACK on the 9th SCL pulse;
SSPIF is set.
14. If SEN bit of SSPCON2 is set, CKP is cleared by
hardware and the clock is stretched.
15. Slave clears SSPIF.
16. Slave reads the received byte from SSPBUF
clearing BF.
17. If SEN is set the slave sets CKP to release the
SCL.
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.
DS41364A-page 300
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 22-17:
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 301
PIC16F193X/LF193X
FIGURE 22-18:
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)
DS41364A-page 302
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 22-19:
I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 303
PIC16F193X/LF193X
22.5.6 CLOCK STRETCHING
22.5.6.2 10-bit Addressing Mode
Clock stretching occurs when a device on the bus
holds the SCL line low effectively pausing communica-
tion. The slave may stretch the clock to allow more
time to handle data or prepare a response for the mas-
ter device. A master device is not concerned with
stretching as anytime it is active on the bus and not
transferring data it is stretching. Any stretching done
by a slave is invisible to the master software and han-
dled by the hardware that generates SCL.
In 10-bit Addressing mode, when the UA bit is set the
clock is always stretched. This is the only time the SCL
is stretched without CKP being cleared. SCL is
releases immediately after a write to SSPADD.
Note: Previous versions of the module did not
stretch the clock if the second address byte
did not match.
22.5.6.3 Byte NACKing
The CKP bit of the SSPCON1 register is used to con-
trol stretching in software. Any time the CKP bit is
cleared, the module will wait for the SCL line to go low
and then hold it. Setting CKP will release SCL and
allow more communication.
When AHEN bit of SSPCON3 is set; CKP is cleared by
hardware after the 8th falling edge of SCL for a
received matching address byte. When DHEN bit of
SSPCON3 is set; CKP is cleared after the 8th falling
edge of SCL for received data.
22.5.6.1 Normal Clock Stretching
Stretching after the 8th falling edge of SCL allows the
slave to look at the received address or data and
decide if it wants to ACK the received data.
Following an ACK if the R/W bit of SSPSTAT is set, a
read request, the slave hardware will clear CKP. This
allows the slave time to update SSPBUF with data to
transfer to the master. If the SEN bit of SSPCON2 is
set, the slave hardware will always stretch the clock
after the ACK sequence. Once the slave is ready; CKP
is set by software and communication resumes.
22.5.7 CLOCK SYNCHRONIZATION AND
THE CKP BIT
Any time the CKP bit is cleared, the module will wait
for the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
until the SCL output is already sampled low. There-
fore, the CKP bit will not assert the SCL line until an
external I2C master device has already asserted the
SCL line. The SCL output will remain low until the CKP
bit is set and all other devices on the I2C bus have
released SCL. This ensures that a write to the CKP bit
will not violate the minimum high time requirement for
SCL (see Figure 22-19).
Note 1: The BF bit has no effect on if the clock will
be stretched or not. This is different than
previous versions of the module that
would not stretch the clock, clear CKP, if
SSPBUF was read before the 9th falling
edge of SCL.
2: Previous versions of the module did not
stretch the clock for a transmission if
SSPBUF was loaded before the 9th falling
edge of SCL. It is now always cleared for
read requests.
FIGURE 22-20:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
SCL
DX
DX ‚ – 1
Master device
asserts clock
CKP
Master device
releases clock
WR
SSPCON1
DS41364A-page 304
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
22.5.8 GENERAL CALL ADDRESS SUPPORT
In 10-bit Address mode, the UA bit will not be set on
the reception of the general call address. The slave
will prepare to receive the second byte as data, just as
it would in 7-bit mode.
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually deter-
mines which device will be the slave addressed by the
master device. The exception is the general call
address which can address all devices. When this
address is used, all devices should, in theory, respond
with an acknowledge.
If the AHEN bit of the SSPCON3 register is set, just as
with any other address reception, the slave hardware
will stretch the clock after the 8th falling edge of SCL.
The slave must then set its ACKDT value and release
the clock with communication progressing as it would
normally.
The general call address is a reserved address in the
I2C protocol, defined as address 0x00. When the
GCEN bit of the SSPCON2 register is set, the slave
module will automatically ACK the reception of this
address regardless of the value stored in SSPADD.
After the slave clocks in an address of all zeros with
the R/W bit clear, an interrupt is generated and slave
software can read SSPBUF and respond.
Figure 22-20 shows
sequence.
a
General Call reception
FIGURE 22-21:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
Address is compared to General Call Address
after ACK, set interrupt
Receiving Data
D5 D4 D3 D2 D1
ACK
R/W = 0
ACK
General Call Address
SDA
D7 D6
D0
8
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
9
S
SSPIF
BF (SSPSTAT<0>)
Cleared by software
SSPBUF is read
GCEN (SSPCON2<7>)
’1’
22.5.9 SSP MASK REGISTER
An SSP Mask (SSPMSK) register (Register 22-5) is
available in I2C Slave mode as a mask for the value
held in the SSPSR register during an address
comparison operation. A zero (‘0’) bit in the SSPMSK
register has the effect of making the corresponding bit
of the received address a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 305
PIC16F193X/LF193X
22.6.1 I2C MASTER MODE OPERATION
2
22.6 I C MASTER MODE
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
Master mode is enabled by setting and clearing the
appropriate SSPM bits in the SSPCON1 register and
by setting the SSPEN bit. In Master mode, the SCL and
SDA lines are set as inputs and are manipulated by the
MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con-
ditions. The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I2C bus may be taken when the P bit is set, or the
bus is Idle.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All
other communication is done by the user software
directly manipulating the SDA and SCL lines.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received 8 bits at a time. After
each byte is received, an Acknowledge bit is transmit-
ted. Start and Stop conditions indicate the beginning
and end of transmission.
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP interrupt, if enabled):
• Start condition detected
• Stop condition detected
• Data transfer byte transmitted/received
• Acknowledge transmitted/received
• Repeated Start generated
A Baud Rate Generator is used to set the clock fre-
quency output on SCL. See Section 22.7 “Baud Rate
Generator” for more detail.
Note 1: The MSSP module, when configured in
I2C Master mode, does not allow queue-
ing of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start con-
dition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur
2: When in Master mode, Start/Stop detec-
tion is masked and an interrupt is gener-
ated when the SEN/PEN bit is cleared and
the generation is complete.
DS41364A-page 306
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
22.6.2 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate Gen-
erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam-
pled high, the Baud Rate Generator is reloaded with
the contents of SSPADD<7:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count in the event that the clock
is held low by an external device (Figure 22-22).
FIGURE 22-22:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX ‚ – 1
SCL allowed to transition high
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
Reload
22.6.3 WCOL STATUS FLAG
If the user writes the SSPBUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL is set and the contents of the buffer are
unchanged (the write doesn’t occur). Any time the
WCOL bit is set it indicates that an action on SSPBUF
was attempted while the module was not Idle.
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 307
PIC16F193X/LF193X
2
22.6.4 I C MASTER MODE START
ister will be automatically cleared by hardware; the
Baud Rate Generator is suspended, leaving the SDA
line held low and the Start condition is complete.
CONDITION TIMING
To initiate a Start condition, the user sets the Start
Enable bit, SEN bit of the SSPCON2 register. If the
SDA and SCL pins are sampled high, the Baud Rate
Generator is reloaded with the contents of
SSPADD<7:0> and starts its count. If SCL and SDA
are both sampled high when the Baud Rate Generator
times out (TBRG), the SDA pin is driven low. The action
of the SDA being driven low while SCL is high is the
Start condition and causes the S bit of the SSPSTAT1
register to be set. Following this, the Baud Rate Gen-
erator is reloaded with the contents of SSPADD<7:0>
and resumes its count. When the Baud Rate Genera-
tor times out (TBRG), the SEN bit of the SSPCON2 reg-
Note 1: If at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low, or if during the Start condition,
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLIF, is set, the Start condition is aborted
and the I2C module is reset into its Idle
state.
2: The Philips I2C Specification states that a
bus collision cannot occur on a Start.
FIGURE 22-23:
FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
Write to SEN bit occurs here
At completion of Start bit,
hardware clears SEN bit
and sets SSPIF bit
SDA = 1,
SCL = 1
TBRG
TBRG
Write to SSPBUF occurs here
SDA
2nd bit
1st bit
TBRG
SCL
S
TBRG
DS41364A-page 308
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
2
22.6.5 I C MASTER MODE REPEATED
SSPCON2 register will be automatically cleared and
the Baud Rate Generator will not be reloaded, leaving
the SDA pin held low. As soon as a Start condition is
detected on the SDA and SCL pins, the S bit of the
SSPSTAT register will be set. The SSPIF bit will not be
set until the Baud Rate Generator has timed out.
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
of the SSPCON2 register is programmed high and the
Master state machine is no longer active. When the
RSEN bit is set, the SCL pin is asserted low. When the
SCL pin is sampled low, the Baud Rate Generator is
loaded and begins counting. The SDA pin is released
(brought high) for one Baud Rate Generator count
(TBRG). When the Baud Rate Generator times out, if
SDA is sampled high, the SCL pin will be deasserted
(brought high). When SCL is sampled high, the Baud
Rate Generator is reloaded and begins counting. SDA
and SCL must be sampled high for one TBRG. This
action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. SCL is
asserted low. Following this, the RSEN bit of the
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL
goes from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
FIGURE 22-24:
REPEAT START CONDITION WAVEFORM
S bit set by hardware
Write to SSPCON2
occurs here
SDA = 1,
At completion of Start bit,
hardware clears RSEN bit
and sets SSPIF
SDA = 1,
SCL = 1
SCL (no change)
TBRG
TBRG
TBRG
1st bit
SDA
SCL
Write to SSPBUF occurs here
TBRG
Sr
Repeated Start
TBRG
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 309
PIC16F193X/LF193X
22.6.6 I2C MASTER MODE TRANSMISSION
22.6.6.3
ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit of the SSPCON2
register is cleared when the slave has sent an Acknowl-
edge (ACK = 0) and is set when the slave does not
Acknowledge (ACK = 1). A slave sends an Acknowl-
edge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit, BF and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted. SCL is held low for one Baud Rate Generator
rollover count (TBRG). Data should be valid before SCL
is released high. When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received prop-
erly. The status of ACK is written into the ACKSTAT bit
on the rising edge of the ninth clock. If the master
receives an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 22-24).
22.6.6.4 Typical transmit sequence:
1. The user generates a Start condition by setting
the SEN bit of the SSPCON2 register.
2. SSPIF is set by hardware on completion of the
Start.
3. SSPIF is cleared by software.
4. The MSSP module will wait the required start
time before any other operation takes place.
5. The user loads the SSPBUF with the slave
address to transmit.
6. Address is shifted out the SDA pin until all 8 bits
are transmitted. Transmission begins as soon
as SSPBUF is written to.
7. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
8. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
After the write to the SSPBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
release the SDA pin, allowing the slave to respond with
an Acknowledge. On the falling edge of the ninth clock,
the master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT Status bit of the SSPCON2
register. Following the falling edge of the ninth clock
transmission of the address, the SSPIF is set, the BF
flag is cleared and the Baud Rate Generator is turned
off until another write to the SSPBUF takes place, hold-
ing SCL low and allowing SDA to float.
9. The user loads the SSPBUF with eight bits of
data.
10. Data is shifted out the SDA pin until all 8 bits are
transmitted.
11. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
12. Steps 8-11 are repeated for all transmitted data
bytes.
13. The user generates a Stop or Restart condition
by setting the PEN or RSEN bits of the
SSPCON2 register. Interrupt is generated once
the Stop/Restart condition is complete.
22.6.6.1
BF Status Flag
In Transmit mode, the BF bit of the SSPSTAT register
is set when the CPU writes to SSPBUF and is cleared
when all 8 bits are shifted out.
22.6.6.2
WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the buf-
fer are unchanged (the write doesn’t occur).
WCOL must be cleared by software before the next
transmission.
DS41364A-page 310
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
2
FIGURE 22-25:
I C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 311
PIC16F193X/LF193X
I2C MASTER MODE RECEPTION
22.6.7.4 Typical Receive Sequence:
22.6.7
Master mode reception is enabled by programming the
Receive Enable bit, RCEN bit of the SSPCON2
register.
1. The user generates a Start condition by setting
the SEN bit of the SSPCON2 register.
2. SSPIF is set by hardware on completion of the
Start.
Note:
The MSSP module must be in an Idle state
before the RCEN bit is set or the RCEN bit
will be disregarded.
3. SSPIF is cleared by software.
4. User writes SSPBUF with the slave address to
transmit and the R/W bit set.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the con-
tents of the SSPSR are loaded into the SSPBUF, the
BF flag bit is set, the SSPIF flag bit is set and the Baud
Rate Generator is suspended from counting, holding
SCL low. The MSSP is now in Idle state awaiting the
next command. When the buffer is read by the CPU,
the BF flag bit is automatically cleared. The user can
then send an Acknowledge bit at the end of reception
by setting the Acknowledge Sequence Enable, ACKEN
bit of the SSPCON2 register.
5. Address is shifted out the SDA pin until all 8 bits
are transmitted. Transmission begins as soon
as SSPBUF is written to.
6. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
7. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
8. User sets the RCEN bit of the SSPCON2 register
and the Master clocks in a byte from the slave.
9. After the 8th falling edge of SCL, SSPIF and BF
are set.
10. Master clears SSPIF and reads the received
byte from SSPUF, clears BF.
22.6.7.1
BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
11. Master sets ACK value sent to slave in ACKDT
bit of the SSPCON2 register and initiates the
ACK by setting the ACKEN bit.
22.6.7.2
SSPOV Status Flag
12. Masters ACK is clocked out to the Slave and
SSPIF is set.
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
13. User clears SSPIF.
14. Steps 8-13 are repeated for each received byte
from the slave.
22.6.7.3
WCOL Status Flag
15. Master sends a not ACK or Stop to end
communication.
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
DS41364A-page 312
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
2
FIGURE 22-26:
I C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 313
PIC16F193X/LF193X
22.6.8
ACKNOWLEDGE SEQUENCE
TIMING
22.6.9
STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN bit of the SSPCON2 register. At the end of a
receive/transmit, the SCL line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDA line low. When the SDA
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCL pin will be brought high
and one TBRG (Baud Rate Generator rollover count)
later, the SDA pin will be deasserted. When the SDA
pin is sampled high while SCL is high, the P bit of the
SSPSTAT register is set. A TBRG later, the PEN bit is
cleared and the SSPIF bit is set (Figure 22-27).
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN bit of the
SSPCON2 register. When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 22-26).
22.6.9.1
WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
22.6.8.1
WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 22-27:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPCON2
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
ACK
TBRG
SDA
SCL
D0
8
9
SSPIF
Cleared in
SSPIF set at
the end of receive
software
Cleared in
software
SSPIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
FIGURE 22-28:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1for TBRG, followed by SDA = 1for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
Write to SSPCON2,
set PEN
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
DS41364A-page 314
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
22.6.10 SLEEP OPERATION
22.6.13 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
While in Sleep mode, the I2C slave module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 22-28).
22.6.11 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
22.6.12 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit of the SSPSTAT register is set,
or the bus is Idle, with both the S and P bits clear. When
the bus is busy, enabling the SSP interrupt will gener-
ate the interrupt when the Stop condition occurs.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed by
hardware with the result placed in the BCLIF bit.
If a Start, Repeated Start, Stop or Acknowledge condi-
tion was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are deas-
serted and the respective control bits in the SSPCON2
register are cleared. When the user services the bus col-
lision Interrupt Service Routine and if the I2C bus is free,
the user can resume communication by asserting a Start
condition.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
• A Repeated Start Condition
• An Acknowledge Condition
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the deter-
mination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 22-29:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master.
Data changes
while SCL = 0
SDA line pulled low
by another source
Bus collision has occurred.
SDA released
by master
SDA
SCL
Set bus collision
interrupt (BCLIF)
BCLIF
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 315
PIC16F193X/LF193X
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 22-31). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to zero; if the SCL pin is sampled as ‘0’
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
22.6.13.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the Start condition (Figure 22-29).
b) SCL is sampled low before SDA is asserted low
(Figure 22-30).
During a Start condition, both the SDA and the SCL
pins are monitored.
Note:
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus colli-
sion because the two masters must be
allowed to arbitrate the first address fol-
lowing the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCLIF flag is set and
•
the MSSP module is reset to its Idle state
(Figure 22-29).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded and counts down. If the
SCL pin is sampled low while SDA is high, a bus colli-
sion occurs because it is assumed that another master
is attempting to drive a data ‘1’ during the Start
condition.
FIGURE 22-30:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
SEN
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.
SSP module reset into Idle state.
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
BCLIF
SSPIF and BCLIF are
cleared by software
S
SSPIF
SSPIF and BCLIF are
cleared by software
DS41364A-page 316
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 22-31:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL
SEN
SCL = 0before SDA = 0,
bus collision occurs. Set BCLIF.
SCL = 0before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
by software
S
’0’
’0’
’0’
’0’
SSPIF
FIGURE 22-32:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Set SSPIF
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SDA
SCL
S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
’0’
BCLIF
S
SSPIF
Interrupts cleared
by software
SDA = 0, SCL = 1,
set SSPIF
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 317
PIC16F193X/LF193X
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 22-32).
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
22.6.13.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition,
see Figure 22-33.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user releases SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD and counts
down to zero. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
FIGURE 22-33:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared by software
’0’
S
’0’
SSPIF
FIGURE 22-34:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
BCLIF
RSEN
set BCLIF. Release SDA and SCL.
Interrupt cleared
by software
’0’
S
SSPIF
DS41364A-page 318
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD and
counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 22-34). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 22-35).
22.6.13.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
FIGURE 22-35:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
low after TBRG,
set BCLIF
TBRG
TBRG
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
’0’
’0’
SSPIF
FIGURE 22-36:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high,
set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
’0’
’0’
SSPIF
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 319
PIC16F193X/LF193X
clock line. The logic dictating when the reload signal is
asserted depends on the mode the MSSP is being
operated in.
22.7 BAUD RATE GENERATOR
The MSSP module has a Baud Rate Generator avail-
able for clock generation in both I2C and SPI Master
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSPADD register (Register 22-6).
When a write occurs to SSPBUF, the Baud Rate Gen-
erator will automatically begin counting down.
Table 22-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
EQUATION 22-1:
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
FOSC
FCLOCK = ----------------------------------------------
(SSPADD + 1)(4)
An internal signal “Reload” in Figure 22-36 triggers the
value from SSPADD to be loaded into the BRG counter.
This occurs twice for each oscillation of the module
FIGURE 22-37:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
SSPADD<7:0>
SSPM<3:0>
SCL
Reload
Control
Reload
BRG Down Counter
SSPCLK
FOSC/2
Note: Values of 0x00, 0x01 and 0x02 are not valid
for SSPADD when used as a Baud Rate
Generator for I2C. This is an implementation
limitation.
TABLE 22-3: MSSP CLOCK RATE W/BRG
FCLOCK
(2 Rollovers of BRG)
FOSC
FCY
BRG Value
32 MHz
32 MHz
32 MHz
16 MHz
16 MHz
16 MHz
4 MHz
8 MHz
8 MHz
8 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
13h
19h
4Fh
09h
0Ch
27h
09h
00h
400 kHz(1)
308 kHz
100 kHz
400 kHz(1)
308 kHz
100 kHz
100 kHz
250 kHz(2)
4 MHz
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
2: SPI mode only.
DS41364A-page 320
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
23.1 EEADRL and EEADRH Registers
23.0 DATA EEPROM AND FLASH
PROGRAM MEMORY
CONTROL
The EEADRL and EEADRH registers can address up
to a maximum of 256 bytes of data EEPROM or up to a
maximum of 32K words of program memory.
The Data EEPROM and Flash program memory are
readable and writable during normal operation (full VDD
range). These memories are not directly mapped in the
register file space. Instead, they are indirectly
addressed through the Special Function Registers
(SFRs). There are six SFRs used to access these
memories:
When selecting a program address value, the MSB of
the address is written to the EEADRH register and the
LSB is written to the EEADRL register. When selecting
a EEPROM address value, only the LSB of the address
is written to the EEADRL register.
23.1.1
EECON1 AND EECON2 REGISTERS
• EECON1
• EECON2
• EEDATL
• EEDATH
• EEADRL
• EEADRH
EECON1 is the control register for EE memory
accesses.
Control bit EEPGD determines if the access will be a
program or data memory access. When clear, any
subsequent operations will operate on the EEPROM
memory. When set, any subsequent operations will
operate on the program memory. On Reset, EEPROM is
selected by default.
When interfacing the data memory block, EEDATL
holds the 8-bit data for read/write, and EEADRL holds
the address of the EEDATL location being accessed.
These devices have 256 bytes of data EEPROM with
an address range from 0h to 0FFh.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
When accessing the program memory block of the
PIC16F1936/PIC16F1937 devices, the EEDATL and
EEDATH registers form a 2-byte word that holds the
14-bit data for read/write, and the EEADRL and
EEADRH registers form a 2-byte word that holds the
15-bit address of the program memory location being
read.
The WREN bit, when set, will allow a write operation to
occur. On power-up, the WREN bit is clear. The
WRERR bit is set when a write operation is interrupted
by a Reset during normal operation. In these situations,
following Reset, the user can check the WRERR bit
and execute the appropriate error handling routine.
The EEPROM data memory allows byte read and write.
An EEPROM byte write automatically erases the loca-
tion and writes the new data (erase before write).
Interrupt flag bit EEIF of the PIR2 register is set when
write is complete. It must be cleared in the software.
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range of
the device for byte or word operations.
Reading EECON2 will read all ‘0’s. The EECON2 reg-
ister is used exclusively in the data EEPROM write
sequence. To enable writes, a specific pattern must be
written to EECON2.
Depending on the setting of the Flash Program
Memory Self Write Enable bits WRT<1:0> of the
Configuration Word Register 2, the device may or may
not be able to write certain blocks of the program
memory. However, reads from the program memory
are always allowed.
When the device is code-protected, the device
programmer can no longer access data or program
memory. When code-protected, the CPU may continue
to read and write the data EEPROM memory and Flash
program memory.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 321
PIC16F193X/LF193X
REGISTER 23-1: EEDATL: EEPROM DATA REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
EEDATL7
EEDATL6
EEDATL5
EEDATL4
EEDATL3
EEDATL2
EEDATL1
EEDATL0
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
EEDATL<7:0>: 8 Least Significant data bits of data EEPROM or Read from program memory
REGISTER 23-2: EEDATH: EEPROM DATA HIGH BYTE REGISTER
U-0
—
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
EEDATH0
bit 0
EEDATH5
EEDATH4
EEDATH3
EEDATH2
EEDATH1
bit 7
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
EEDATH<5:0>: 6 Most Significant Data bits from program memory
REGISTER 23-3: EEADRL: EEPROM ADDRESS REGISTER
R/W-0/0
EEADR7
R/W-0/0
EEADR6
R/W-0/0
EEADR5
R/W-0/0
EEADR4
R/W-0/0
EEADR3
R/W-0/0
EEADR2
R/W-0/0
EEADR1
R/W-0/0
EEADR0
bit 0
bit 7
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
EEADRL<7:0>: 8 Least Significant Address bits for EEPROM or program memory
REGISTER 23-4: EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
EEADRH0
bit 0
EEADRH6
EEADRH5
EEADRH4
EEADRH3
EEADRH2
EEADRH1
bit 7
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
Unimplemented: Read as ‘0’
EEADRH<6:0>: Specifies the 7 Most Significant Address bits or high bits for program memory reads
bit 6-0
DS41364A-page 322
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
REGISTER 23-5: EECON1: EEPROM CONTROL 1 REGISTER
R/W-0/0
EEPGD
R/W-0/0
CFGS
R/W-0/0
LWLO
R/W/HC-0/0
FREE
R/W-x/q
WRERR
R/W-0/0
WREN
R/S/HC-0/0 R/S/HC-0/0
WR RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
S = Bit can only be set
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
HC = bit is cleared by hardware
bit 7
bit 6
bit 5
EEPGD: Flash Program/Data EEPROM Memory Select bit
1= Accesses program space Flash memory
0= Accesses data EEPROM memory
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1= Accesses Configuration, User ID and Device ID Registers
0= Accesses Flash Program or data EEPROM Memory
LWLO: Load Write Latches Only bit
If EEPGD = 1or CFGS = 1: (accessing program Flash)
1= The next WR command does not initiate a write to the PFM; only the program memory
latches are updated.
0= The next WR command writes a value from EEDATH:EEDATL into program memory latches
and initiates a write to the PFM of all the data stored in the program memory latches.
If EEPGD = 0and CFGS = 1: (Accessing data EEPROM)
LWLO is ignored. The next WR command initiates a write to the data EEPROM.
bit 4
FREE: Program Flash Erase Enable bit
If EEPGD = 1or CFGS = 1: (accessing program Flash)
1= Perform an program Flash erase operation on the next WR command (cleared by hardware
after completion of erase).
0= Perform a program Flash write operation on the next WR command.
If EEPGD = 0 and CFGS = 0: (Accessing data EEPROM)
FREE is ignored. The next WR command will initiate both a erase cycle and a write cycle.
bit 3
WRERR: EEPROM Error Flag bit
1= Condition could indicate an improper program or erase sequence attempt or termination (bit is set
automatically on any set attempt (write ‘1’) of the WR bit.
0= The program or erase operation completed normally.
bit 2
bit 1
WREN: Program/Erase Enable bit
1= Allows program/erase cycles
0= Inhibits programming/erasing of program Flash and data EEPROM
WR: Write Control bit
1= Initiates a program Flash or data EEPROM program/erase operation.
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0= Program/erase operation to the Flash or data EEPROM is complete and inactive.
bit 0
RD: Read Control bit
1= Initiates an program Flash or data EEPROM read. Read takes one cycle. RD is cleared in
hardware. The RD bit can only be set (not cleared) in software.
0= Does not initiate a program Flash or data EEPROM data read.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 323
PIC16F193X/LF193X
REGISTER 23-6: EECON2: EEPROM CONTROL 2 REGISTER
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
EEUNLK7
EEUNLK6
EEUNLK5
EEUNLK4
EEUNLK3
EEUNLK2
EEUNLK1
EEUNLK0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
S = Bit can only be set
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
EEUNLK<7:0>: Data EEPROM Unlock Pattern bits
To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
EECON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes. Refer to Section 23.1.3 “Writing to the Data EEPROM
Memory” for more information.
DS41364A-page 324
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
23.1.2
READING THE DATA EEPROM
MEMORY
23.1.3
WRITING TO THE DATA EEPROM
MEMORY
To read a data memory location, the user must write the
address to the EEADRL register, clear the EEPGD and
CFGS control bits of the EECON1 register, and then
set control bit RD. The data is available at the very next
cycle, in the EEDATL register; therefore, it can be read
in the next instruction. EEDATL will hold this value until
another read or until it is written to by the user (during
a write operation).
To write an EEPROM data location, the user must first
write the address to the EEADRL register and the data
to the EEDATL register. Then the user must follow a
specific sequence to initiate the write for each byte.
The write will not initiate if the above sequence is not
followed exactly (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. Interrupts
should be disabled during this code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
EXAMPLE 23-1:
DATA EEPROM READ
BANKSELEEADRL
;
MOVLW
MOVWF
DATA_EE_ADDR ;
EEADRL
;Data Memory
;Address to read
BCF
BCF
BSF
MOVF
BCF
EECON1, CFGS ;Deselect Config space
EECON1, EEPGD;Point to DATA memory
EECON1, RD
EEDATL, W
;EE Read
;W = EEDATL
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
STATUS, RP1 ;Bank 0
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
Note:
Data EEPROM can be read regardless of
the setting of the CPD bit.
EXAMPLE 23-2:
DATA EEPROM WRITE
BANKSEL EEADRL
;
;
MOVLW
MOVWF
MOVLW
MOVWF
BCF
DATA_EE_ADDR
EEADRL
DATA_EE_DATA
EEDATL
;Data Memory Address to write
;
;Data Memory Value to write
;Deselect Configuration space
EECON1, CFGS
BCF
EECON1, EEPGD ;Point to DATA memory
BSF
EECON1, WREN
;Enable writes
BCF
INTCON, GIE
INTCON, GIE
$-2
55h
EECON2
AAh
EECON2
EECON1, WR
;Disable INTs.
;SEE AN576
BTFSC
GOTO
MOVLW
MOVWF
MOVLW
MOVWF
BSF
;
;Write 55h
;
;Write AAh
;Set WR bit to begin write
BCF
BTFSC
GOTO
EECON1, WREN
EECON1, WR
$-2
;Disable writes
;Wait for write to complete
;Done
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 325
PIC16F193X/LF193X
EEDATL and EEDATH registers will hold this value until
another read or until it is written to by the user.
23.1.4
READING THE FLASH PROGRAM
MEMORY
To read a program memory location, the user must:
Note 1: The two instructions following a program
memory read are required to be NOPs.
This prevents the user from executing a
two-cycle instruction on the next
instruction after the RD bit is set.
1. Write the Least and Most Significant address
bits to the EEADRL and EEADRH registers.
2. Clear the CFGS bit of the EECON1 register.
3. Set the EEPGD control bit of the EECON1
register.
2: Data EEPROM can be read regardless of
the setting of the CPD bit.
4. Then, set control bit RD of the EECON1 register.
Once the read control bit is set, the program memory
Flash controller will use the second instruction cycle to
read the data. This causes the second instruction
immediately following the “BSF EECON1,RD” instruction
to be ignored. The data is available in the very next cycle,
in the EEDATL and EEDATH registers; therefore, it can
be read as two bytes in the following instructions.
EXAMPLE 23-3:
FLASH PROGRAM READ
BANKSELEEADRL
;
;
MOVLW
MOVWF
MOVLW
MOVWF
MS_PROG_EE_ADDR
EEADRH
LS_PROG_EE_ADDR
EEADRL
;MS Byte of Program Address to read
;
;LS Byte of Program Address to read
BANKSELEECON1
;
BSF
BSF
EECON1, EEPGD
EECON1, RD
;Point to PROGRAM memory
;EE Read
;
;
;First instruction after BSF EECON1,RD executes normally
NOP
NOP
;Any instructions here are ignored as program
;memory is read in second cycle after BSF EECON1,RD
BANKSELEEDATL
;
MOVF
EEDATL, W
;W = LS Byte of Program Memory
MOVWF
MOVF
MOVWF
LOWPMBYTE
EEDATH, W
HIGHPMBYTE
;
;W = MS Byte of Program EEDATL
;
BCF STATUS, RP1
;Bank 0
DS41364A-page 326
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
EXAMPLE 23-4:
FLASH PROGRAM MEMORY READ
* This code block will read 1 word of program
* memory at the memory address:
PROG_ADDR_HI : PROG_ADDR_LO
*
*
data will be returned in the variables;
PROG_DATA_HI, PROG_DATA_LO
BANKSEL EEADRL
; Select Bank for EEPROM registers
MOVLW
MOVWF
MOVLW
MOVWL
PROG_ADDR_LO
EEADRL
PROG_ADDR_HI
EEADRH
;
; Store LSB of address
;
; Store MSB of address
BCF
BSF
BCF
BSF
NOP
NOP
BSF
EECON1,CFGS
EECON1,EEPGD
INTCON,GIE
EECON1,RD
; Select Configuration Space
; Select Program Memory
; Disable interrupts
; Initiate read
; Executed (Figure 23-1)
; Ignored (Figure 23-1)
; Restore interrupts
INTCON,GIE
MOVF
EEDATL,W
; Get LSB of word
MOVWF
MOVF
PROG_DATA_LO
EEDATH,W
; Store in user location
; Get MSB of word
MOVWF
PROG_DATA_HI
; Store in user location
FIGURE 23-1:
FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
PC + 1
EEADRH,EEADRL
PC + 3
PC + 4
PC + 5
Flash ADDR
Flash Data
INSTR (PC)
INSTR (PC + 1)
EEDATH,EEDATL
INSTR (PC + 3)
INSTR (PC + 4)
BSF EECON1,RD
executed here
INSTR(PC - 1)
executed here
INSTR(PC + 1)
executed here
Forced NOP
executed here
INSTR(PC + 3)
executed here
INSTR(PC + 4)
executed here
RD bit
EEDATH
EEDATL
Register
EERHLT
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 327
PIC16F193X/LF193X
Up to eight buffer register locations can be written to
with correct data. If less than eight words are being writ-
ten to in the block of eight words, then the data for the
unprogrammed words should be set to all ones.
23.2 Erasing Program Memory
While executing code, program memory can only be
erased by rows. A row consists of 32 words where the
EEADRL<4:0> = 0000. To erase a row:
After the “BSF EECON1,WR” instruction, the processor
requires two cycles to set up the erase/write operation.
The user must place two NOPinstructions after the WR
bit is set. Since data is being written to buffer registers,
the writing of the first seven words of the block appears
to occur immediately. The processor will halt internal
operations for the typical 2 ms, only during the cycle in
which the erase takes place (i.e., the last word of the
sixteen-word block erase). This is not Sleep mode as
the clocks and peripherals will continue to run. After the
eight-word write cycle, the processor will resume oper-
ation with the third instruction after the EECON1 write
instruction.
1. Load the EEADRH and EEADRL registers with
the address of new row to be erased.
2. Clear the CFGS bit of the EECON1 register.
3. Set the EEPGD bit of the EECON1 register.
4. Set the FREE bit of the EECON1 register.
5. Write 55h, then AAh, to EECON2 (Flash
programming unlock sequence).
6. Set control bit WR of the EECON1 register to
begin the write operation.
23.3 Writing to Flash Program Memory
An example of the complete eight-word write sequence
is shown in Example 23-5. The initial address is loaded
into the EEADRH and EEADRL register pair; the eight
words of data are loaded using indirect addressing.
Before writing, program memory should be erased
using the Erase Program Memory command.
No automatic erase occurs upon the initiation of the
write; if the program Flash needs to be erased before
writing, the row (32 words) must be erased previously.
Flash program memory may only be written to if the
destination address is in a segment of memory that is
not write-protected, as defined in bits WRT<1:0> of the
Configuration Word Register 2. Flash program memory
must be written in eight-word blocks. See Figure 23-2
for more details. A block consists of eight words with
sequential addresses, with a lower boundary defined
by an address, where EEADRL<2:0> = 000. All block
writes to program memory are done as 32-word erase
by eight-word write operations. The write operation is
edge-aligned and cannot occur across boundaries.
When the LWLO bit is ‘1’, the write sequence will only
load the buffer register and will not actually initiate the
write to program Flash:
1. Set the EEPGD, WREN and LWLO bits of the
EECON1 register.
2. Write 55h, then AAh, to EECON2 (Flash
programming unlock sequence).
3. Set control bit WR of the EECON1 register to
begin the write operation.
To write program data, it must first be loaded into the
buffer registers (see Figure 23-1). This is accomplished
by first writing the destination address to EEADRL and
EEADRH and then writing the data to EEDATA and
EEDATH. After the address and data have been set up,
then the following sequence of events must be executed:
1. Set the EEPGD control bit of the EECON1
register.
2. Set the LWLO bit of the EECON1 register.
3. Write 55h, then AAh, to EECON2 (Flash
programming sequence).
4. Set the WR control bit of the EECON1 register.
DS41364A-page 328
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 23-2:
BLOCK WRITES TO 8K FLASH PROGRAM MEMORY
7
5
0
0 7
EEDATH
6
EEDATA
8
First word of block
to be written
14
14
14
14
EEADRL<2:0> = 000
EEADRL<2:0> = 001
Buffer Register
EEADRL<2:0> = 010
Buffer Register
EEADRL<2:0> = 111
Buffer Register
Buffer Register
Program Memory
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 329
PIC16F193X/LF193X
EXAMPLE 23-5:
WRITING TO FLASH PROGRAM MEMORY
; This write routine assumes the following:
; 1. A valid starting address (the least significant bits = 00)is loaded in ADDRH:ADDRL
; 2. The 8 bytes of data are loaded, starting at the address in DATADDR
; 3. ADDRH, ADDRL and DATADDR are all located in shared data memory 0x70 - 0x7f
;
BANKSELEEADRH
; Bank 3
MOVF
MOVWF
MOVF
MOVWF
MOVF
MOVWF
MOVF
ADDRH,W
EEADRH
ADDRL,W
EEADRL
DATAADDRL,W
FSR0L
DATAADDRH,W
FSR0H
; Load initial address
;
;
;
; Load initial data address
;
; Load initial data address
;
MOVWF
LOOP
MOVIW
MOVWF
MOVIW
MOVWF
BSF
BCF
BSF
BSF
INDF0++
EEDATL
INDF0++
EEDATH
EECON1,EEPGD
EECON1,CFGS
EECON1,WREN
EECON1,LWLO
; Load first data byte into lower
;
; Load second data byte into upper
;
; Point to program memory
; Not configuration space
; Enable writes
; Only Load Write Latches
MOVLW
MOVWF
MOVLW
MOVWF
BSF
55h
EECON2
AAh
EECON2
EECON1,WR
; Start of required write sequence:
; Write 55h
;
; Write AAh
; Set WR bit to begin write
NOP
NOP
; Any instructions here are ignored as processor
; halts to begin write sequence
; processor will stop here and wait for write complete
; after write processor continues with 3rd instruction
MOVF
EEADR,W
; Check if lower two bits of address are ‘00’
XORLW
ANDLW
BTFSC
GOTO
0x08
0x08
STATUS,Z
START_WRITE
; Check if we’re on the last of 8 addresses
;
; Exit if last of eight words,
;
INCF
GOTO
EEADR,F
LOOP
; Still loading latches Increment address
; Write next latches
START_WRITE
BCF
EECON1,LWLO
; No more Latches only; Actually start write
MOVLW
55h
; Start of required write sequence:
MOVWF
MOVLW
MOVWF
BSF
EECON2
AAh
EECON2
EECON1,WR
; Write 55h
;
; Write AAh
; Set WR bit to begin write
NOP
NOP
BCF
; Any instructions here are ignored as processor
; halts to begin write sequence
; processor will stop here and wait for write complete
; after write processor continues with 3rd instruction
; Disable writes
EECON1,WREN
DS41364A-page 330
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
When read access is initiated on an unallowed
address, the EEDATH:EEDATL registers are cleared.
23.4 Configuration Word and Device ID
Access
Writes can be disabled via the WRT Configuration bits.
Refer to the Configuration Word 2 register.
Instead of accessing program memory or EEPROM
data memory, the User ID’s, Device ID/Revision ID and
Configuration Words can be accessed when
CFGS = 1. This is the region that would be pointed to
by PC<15> = 1, but not all addresses are accessible.
Different access may exist for reads and writes. Refer
to Table 23-1.
TABLE 23-1: PFM AND FUSE ACCESS VIA EECON1/EEDATH:EEDATL REGISTERS
(WHEN CFGS = 1)
Address
Function
Read Access
Write Access
8000h-8003h
8006h
User IDs
Yes
Yes
Yes
Yes
No
No
Device ID/Revision ID
Configuration Words 1 and 2
8007h-8008h
EXAMPLE 23-3: CONFIGURATION WORD AND DEVICE ID ACCESS
* This code block will read 1 word of program
* memory at the memory address:
PROG_ADDR_HI : PROG_ADDR_LO
*
*
data will be returned in the variables;
PROG_DATA_HI, PROG_DATA_LO
BANKSEL EEADRL
; Select Bank 2
MOVLW
MOVWF
MOVLW
MOVWL
PROG_ADDR_LO
EEADRL
PROG_ADDR_HI
EEADRH
;
; Store LSB of address
;
; Store MSB of address
BCF
BSF
BCF
BSF
NOP
NOP
BSF
EECON1,CFGS
EECON1,EEPGD
INTCON,GIE
EECON1,RD
; Deselect Configuration Space
; Select Program Memory
; Disable interrupts
; Initiate read
; Executed (Figure 23-1)
; Ignored (Figure 23-1)
; Restore interrupts
INTCON,GIE
MOVF
EEDATL,W
; Get LSB of word
MOVWF
MOVF
PROG_DATA_LO
EEDATH,W
; Store in user location
; Get MSB of word
MOVWF
PROG_DATA_HI
; Store in user location
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 331
PIC16F193X/LF193X
23.5 Write Verify
23.6 Protection Against Spurious Write
Depending on the application, good programming
practice may dictate that the value written to the data
EEPROM or program memory should be verified (see
Example 23-6) to the desired value to be written.
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, WREN is cleared. Also, the
Power-up
Timer
(64 ms
duration)
prevents
EEPROM write.
EXAMPLE 23-6:
WRITE VERIFY
The write initiate sequence and the WREN bit together
help prevent an accidental write during:
BANKSELEEDATL
;
MOVF
EEDATL, W ;EEDATL not changed
;from previous write
• Brown-out
BSF
EECON1, RD ;YES, Read the
;value written
• Power Glitch
XORWF
BTFSS
GOTO
:
EEDATL, W
;
• Software Malfunction
STATUS, Z ;Is data the same
WRITE_ERR ;No, handle error
;Yes, continue
23.7 Data EEPROM Operation During
Code-Protect
Data memory can be code-protected by programming
the CPD bit in the Configuration Word Register 1
(Register 10-1) to ‘0’.
23.5.1
USING THE DATA EEPROM
The data EEPROM is
a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated often).
When variables in one section change frequently, while
variables in another section do not change, it is possible
to exceed the total number of write cycles to the
EEPROM (specification D124) without exceeding the
When the data memory is code-protected, only the
CPU is able to read and write data to the data
EEPROM. It is recommended to code-protect the
program memory when code-protecting data memory.
This prevents anyone from replacing your program with
a program that will access the contents of the data
EEPROM.
total number of write cycles to
a single byte
(specifications D120 and D120A). If this is the case,
then a refresh of the array must be performed. For this
reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.
TABLE 23-2: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EECON1 EEPGD
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
323
324*
322
322
322
322
73
EECON2 EEPROM Control Register 2 (not a physical register)
EEADRL EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0
EEADRH EEADRH6 EEADRH5 EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0
EEDATL EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDALT1 EEDATL0
—
EEDATH
INTCON
PIE2
—
—
EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0
GIE
PEIE
C2IE
C2IF
TMR0IE
C1IE
INTE
EEIE
EEIF
IOCIE
BCLIE
BCLIF
TMR0IF
LCDIE
LCDIF
INTF
—
IOCIF
CCP2IE
CCP2IF
OSFIE
OSFIF
75
PIR2
C1IF
—
78
Legend: x= unknown, u= unchanged, —= unimplemented read as ‘0’, q= value depends upon condition.
Shaded cells are not used by data EEPROM module.
*
Page provides register information.
DS41364A-page 332
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
address (0004h). In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOPafter the SLEEPinstruction.
24.0 POWER-DOWN MODE (SLEEP)
The Power-down mode is entered by executing a
SLEEPinstruction.
Note:
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from Sleep. The
SLEEPinstruction is completely executed.
If the Watchdog Timer is enabled:
• WDT will be cleared but keeps running.
• PD bit of the STATUS register is cleared.
• TO bit of the STATUS register is set.
• Oscillator driver is turned off.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
• Timer1 oscillator is unaffected
• I/O ports maintain the status they had before
SLEEPwas executed (driving high, low or high-
impedance).
For lowest current consumption in this mode, all I/O
pins should be either at VDD or VSS, with no external
circuitry drawing current from the I/O pin. I/O pins that
are high-impedance inputs should be pulled high or low
externally to avoid switching currents caused by float-
ing inputs. The T0CKI input should also be at VDD or
VSS for lowest current consumption. The contribution
from on-chip pull-ups on PORTB should be considered.
Enabled Resets remain functional during Sleep.
24.1 Wake-up from Sleep
The device can wake-up from Sleep through one of the
following events:
1. External Reset input on MCLR pin, if enabled.
2. BOR Reset, if enabled.
3. Watchdog Timer wake-up (if WDT was
enabled).
4. Any external interrupt.
5. Certain peripheral interrupts (see individual
peripheral for more information).
The first two events will cause a device Reset. The last
three events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device Reset.
The PD bit, which is set on power-up, is cleared when
Sleep is invoked. TO bit is cleared if WDT wake-up
occurred.
Certain peripherals cannot generate interrupts since
during Sleep, no on-chip clocks are present.
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction, then branches to the interrupt
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 333
PIC16F193X/LF193X
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
24.2 Wake-up Using Interrupts
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEPinstruction, the SLEEPinstruction will
complete as a NOP. Therefore, the WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
• If the interrupt occurs during or after the
execution of a SLEEPinstruction, the device will
immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT prescaler
and postscaler (if enabled) will be cleared, the TO
bit will be set and the PD bit will be cleared.
FIGURE 24-1:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1(1)
CLKOUT(4)
INT pin
(2)
TOST
INTF flag
(INTCON reg.)
Interrupt Latency(3)
GIE bit
(INTCON reg.)
Processor in
Sleep
Instruction Flow
PC
PC
PC + 1
PC + 2
PC + 2
PC + 2
0004h
0005h
Instruction
Fetched
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = Sleep
Instruction
Executed
Dummy Cycle
Dummy Cycle
Sleep
Inst(PC + 1)
Inst(PC - 1)
Inst(0004h)
Note 1:
XT, HS or LP Oscillator mode assumed.
TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes.
GIE = 1assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.
2:
3:
4:
CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference.
TABLE 24-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Register on
Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOCBF
IOCBN
IOCBP
INTCON
PIE1
IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0
IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0
IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0
104
104
104
73
GIE
PEIE
ADIE
C2IE
ADIF
C2IE
TMR0IE
RCIE
C1IE
INTE
TXIE
EEIE
TXIF
EEIE
IOCIE
SSPIE
BCLIE
SSPIF
BCLIE
TMR0IF
CCP1IE TMR2IE TMR1IE
LCDIE CCP2IE
CCP1IF TMR2IF TMR1IF
LCDIE CCP2IE
INTF
IOCIF
TMR1GIE
OSFIE
74
PIE2
—
75
PIR1
TMR1GIF
OSFIE
RCIF
77
PIR2
C1IE
—
78
Legend: x= unknown, u= unchanged, –= unimplemented, read as ‘0’. Shaded cells are not used in Power-down
mode.
DS41364A-page 334
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
25.0 IN-CIRCUIT SERIAL
PROGRAMMING™ (ICSP™)
Note:
The ICD 2 produces a VPP voltage greater
than the maximum VPP specification of the
PIC16F193X/LF193X. When using this
programmer, an external circuit is required
to keep the VPP voltage within the device
specifications.
ICSP™ programming allows customers to manufacture
circuit boards with unprogrammed devices. Programming
can be done after the assembly process allowing the
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP™
programming:
• ICSPCLK
• ICSPDAT
• MCLR/VPP
• VDD
25.2 Low-Voltage Programming Mode
The Low-Voltage Programming mode allows the
PIC16F193X/LF193X devices to be programmed using
VDD only, without high voltage. When the LVP bit of the
Configuration Word 2 register is set to ‘1’, the
low-voltage ICSP programming entry is enabled. To
disable the Low-Voltage ICSP mode, the LVP bit must
be programmed to ‘0’.
• VSS
In Program/Verify mode the Program Memory, User
IDs and the Configuration Words are programmed
through serial communications. The ICSPDAT pin is a
bidirectional I/O used for transferring the serial data
and the ICSPCLK pin is the clock input. For more infor-
Entry into the Low-Voltage ICSP Program/Verify modes
requires the following steps:
mation
on
ICSP™
refer
to
the
1. MCLR is brought to VIL.
“PIC16193X/PIC16LF193X Memory Programming
Specification” (DS41360A)
2.
A
32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
25.1 High-voltage Programming Mode
The device is placed into high-voltage Program/Verify
mode by holding the ICSPCLK and ICSPDAT pins low
then raising the voltage on MCLR/VPP to VIHH.
FIGURE 25-1:
TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
External
Programming
Signals
Device to be
Programmed
VDD
VDD
VDD
10k
VPP
VSS
MCLR/VPP
VSS
Data
ICSPDAT
ICSPCLK
Clock
*
*
*
To Normal Connections
Isolation devices (as required).
*
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 335
PIC16F193X/LF193X
NOTES:
DS41364A-page 336
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
26.1 Read-Modify-Write Operations
26.0 INSTRUCTION SET SUMMARY
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
Each PIC16 instruction is a 14-bit word containing the
operation code (opcode) and all required operands.
The opcodes are broken into three broad categories.
• Byte Oriented
• Bit Oriented
• Literal and Control
The literal and control category contains the most var-
ied instruction word format.
TABLE 26-1: OPCODE FIELD
DESCRIPTIONS
Table 26-3 lists the instructions recognized by the
MPASMTM assembler.
Field
Description
All instructions are executed within a single instruction
cycle, with the following exceptions, which may take
two or three cycles:
f
W
b
Register file address (0x00 to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
• Subroutine takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two
cycles (RETURN, RETLW, RETFIE)
k
x
Don’t care location (= 0or 1).
• Program branching takes two cycles (GOTO, BRA,
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)
• One additional instruction cycle will be used when
any instruction references an indirect file register
and the MSb of the appropriate file select register
is set.
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
One instruction cycle consists of 4 oscillator cycles; for
an oscillator frequency of 4 MHz, this gives a nominal
instruction execution rate of 1 MHz.
n
FSR or INDF number. (0-1)
mm
Pre-post increment-decrement mode
selection
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
TABLE 26-2: ABBREVIATION
DESCRIPTIONS
Field
Description
PC
TO
C
Program Counter
Time-out bit
Carry bit
DC
Z
Digit carry bit
Zero bit
PD
Power-down bit
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 337
PIC16F193X/LF193X
FIGURE 26-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8
7
6
0
OPCODE
d
f (FILE #)
d = 0for destination W
d = 1for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9
7 6
0
OPCODE
b (BIT #)
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
0
OPCODE
k (literal)
k = 8-bit immediate value
CALLand GOTOinstructions only
13 11 10
OPCODE
0
k (literal)
k = 11-bit immediate value
MOVLPinstruction only
13
7
6
0
0
OPCODE
k (literal)
k = 7-bit immediate value
MOVLBinstruction only
13
5 4
OPCODE
k (literal)
k = 5-bit immediate value
BRAinstruction only
13
9
8
0
OPCODE
k (literal)
k = 9-bit immediate value
FSR Offset instructions
13
7
6
5
0
0
OPCODE
n
k (literal)
n = appropriate FSR
k = 6-bit immediate value
FSRIncrement instructions
13
3
2
n
1
OPCODE
m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13
0
OPCODE
DS41364A-page 338
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 26-3: PIC16F193X/LF193X ENHANCED INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC f, d
ANDWF
ASRF
LSLF
f, d
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
00 0111 dfff ffff C, DC, Z
11 1101 dfff ffff C, DC, Z
00 0101 dfff ffff Z
11 0111 dfff ffff C, Z
11 0101 dfff ffff C, Z
11 0110 dfff ffff C, Z
2
2
2
2
2
2
2
f, d
f, d
f, d
f, d
f
LSRF
CLRF
CLRW
COMF
DECF
INCF
IORWF
MOVF
MOVWF
RLF
RRF
SUBWF
SUBWFB f, d
SWAPF
XORWF
00 0001 lfff ffff
00 0001 0000 00xx
00 1001 dfff ffff
00 0011 dfff ffff
00 1010 dfff ffff
00 0100 dfff ffff
00 1000 dfff ffff
00 0000 1fff ffff
00 1101 dfff ffff
00 1100 dfff ffff
Z
Z
Z
Z
Z
Z
Z
–
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
2
2
2
2
2
2
2
2
2
2
2
2
C
C
00 0010 dfff ffff C, DC, Z
11 1011 dfff ffff C, DC, Z
00 1110 dfff ffff
f, d
f, d
00 0110 dfff ffff
Z
BYTE ORIENTED SKIP OPERATIONS
f, d
f, d
Decrement f, Skip if 0
Increment f, Skip if 0
1(2)
1(2)
00
00
1011 dfff ffff
1111 dfff ffff
1, 2
1, 2
DECFSZ
INCFSZ
BIT-ORIENTED FILE REGISTER OPERATIONS
f, b
f, b
Bit Clear f
Bit Set f
1
1
01
01
00bb bfff ffff
01bb bfff ffff
2
2
BCF
BSF
BIT-ORIENTED SKIP OPERATIONS
BTFSC
BTFSS
f, b
f, b
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1 (2)
1 (2)
01
01
10bb bfff ffff
11bb bfff ffff
1, 2
1, 2
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Inclusive OR literal with W
Move literal to BSR
Move literal to PCLATH
Move literal to W
1
1
1
1
1
1
1
1
11
11
11
00
11
11
11
11
1110 kkkk kkkk C, DC, Z
1001 kkkk kkkk
1000 kkkk kkkk
0000 001k kkkk
0001 1kkk kkkk
0000 kkkk kkkk
Z
Z
Subtract W from literal
Exclusive OR literal with W
1100 kkkk kkkk C, DC, Z
1010 kkkk kkkk
Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one
additional instruction cycle.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 339
PIC16F193X/LF193X
TABLE 26-3: PIC16F193X/LF193X ENHANCED INSTRUCTION SET (CONTINUED)
14-Bit Opcode
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
CONTROL OPERATIONS
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
–
k
–
k
k
k
–
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
2
2
2
2
2
2
2
2
11
00
10
00
10
00
11
00
001k kkkk kkkk
0000 0000 1011
0kkk kkkk kkkk
0000 0000 1010
1kkk kkkk kkkk
0000 0000 1001
0100 kkkk kkkk
0000 0000 1000
INHERENT OPERATIONS
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
–
–
–
–
–
f
Clear Watchdog Timer
No Operation
Load OPTION_REG register with W
Software device Reset
Go into Standby mode
Load TRIS register with W
1
1
1
1
1
1
00
00
00
00
00
00
0000 0110 0100 TO, PD
0000 0000 0000
0000 0110 0010
0000 0000 0001
0000 0110 0011 TO, PD
0000 0110 01kk
C-COMPILER OPTIMIZED
ADDFSR n, k
Add Literal to FSRn
1
11 0001 0nkk kkkk
00 0000 0001 0mmn
00 0000 0001 0nmm
11 1111 0nkk kkkk
00 0000 0001 1mmn
00 0000 0001 1nmm
11 1111 1nkk kkkk
MOVIW
mm n
Move INDFn to W, with pre/post inc/dec
Move INDFn to W, with pre/post inc/dec
Move INDFn to W, Indexed Indirect.
Move W to INDFn, with pre/post inc/dec
Move W to INDFn, with pre/post inc/dec
Move W to INDFn, Indexed Indirect.
1
1
1
1
1
1
Z
Z
Z
2
n mm
k[n]
2
2
2
2
2
MOVWI
mm n
n mm
k[n]
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
DS41364A-page 340
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
26.2 Instruction Descriptions
ADDFSR
Add Literal to FSRn
ANDLW
AND literal with W
Syntax:
[ label ] ADDFSR n, k
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
k
Operands:
-32 ≤ k ≤ 31
n ∈ [ 0, 1]
Operands:
Operation:
Status Affected:
Description:
(W) .AND. (k) → (W)
Operation:
FSR(n) + k → FSR(n)
Z
Status Affected:
Description:
None
The contents of W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W register.
The signed 6-bit literal ‘k’ is added to
the contents of the FSRnH:FSRnL
register pair.
FSRn is limited to the range 0000h -
FFFFh. Moving beyond these bounds
will cause the FSR to wrap around.
ANDWF
AND W with f
ADDLW
Add literal and W
Syntax:
[ label ] ANDWF f,d
Syntax:
[ label ] ADDLW
0 ≤ k ≤ 255
k
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
Status Affected:
Description:
(W) + k → (W)
C, DC, Z
Operation:
(W) .AND. (f) → (destination)
Status Affected:
Description:
Z
The contents of the W register are
added to the eight-bit literal ‘k’ and the
result is placed in the W register.
AND the W register with register ‘f’. If
‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
ASRF
Arithmetic Right Shift
ADDWF
Add W and f
Syntax:
[ label ] ASRF f {,d}
Syntax:
[ label ] ADDWF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f<7>)→ dest<7>
(f<7:1>) → dest<6:0>,
(f<0>) → C,
Operation:
(W) + (f) → (destination)
Status Affected:
Description:
C, DC, Z
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
Status Affected:
Description:
C, Z
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in reg-
ister ‘f’.
ADDWFC
ADD W and CARRY bit to f
C
register f
Syntax:
[ label ] ADDWFC
f {,d}
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) + (f) + (C) → dest
Status Affected:
Description:
C, DC, Z
Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 341
PIC16F193X/LF193X
BTFSC
Bit Test f, Skip if Clear
BCF
Bit Clear f
Syntax:
[ label ] BTFSC f,b
Syntax:
[ label ] BCF f,b
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
skip if (f<b>) = 0
Operation:
0→ (f<b>)
Status Affected:
Description:
None
Status Affected:
Description:
None
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
Bit ‘b’ in register ‘f’ is cleared.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOPis
executed instead, making this a
2-cycle instruction.
BTFSS
Bit Test f, Skip if Set
BRA
Relative Branch
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] BRA
-256 ≤ k ≤ 255
(PC) + k → PC
None
k
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
Status Affected:
Description:
Operation:
skip if (f<b>) = 1
Status Affected:
Description:
None
Add the signed 9-bit literal ‘k’ to the
PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + k.
This instruction is a two-cycle instruc-
tion.
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next
instruction is discarded and a NOPis
executed instead, making this a
2-cycle instruction.
BRW
Relative Branch with W
Syntax:
[ label ] BRW
None
Operands:
Operation:
Status Affected:
Description:
(PC) + (W) → PC
None
Add the contents of W (unsigned) to
the PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + (W).
This instruction is a two-cycle instruc-
tion.
BSF
Bit Set f
Syntax:
[ label ] BSF f,b
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
1→ (f<b>)
Status Affected:
Description:
None
Bit ‘b’ in register ‘f’ is set.
DS41364A-page 342
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
CALL
Call Subroutine
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL
0 ≤ k ≤ 2047
k
Syntax:
[ label ] CLRWDT
Operands:
Operation:
Operands:
Operation:
None
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
00h → WDT
0→ WDT prescaler,
1→ TO
1→ PD
Status Affected:
Description:
None
Status Affected:
Description:
TO, PD
Call Subroutine. First, return address
(PC + 1) is pushed onto the stack.
The eleven-bit immediate address is
loaded into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALLis a two-cycle instruc-
tion.
CLRWDTinstruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT.
Status bits TO and PD are set.
COMF
Complement f
CALLW
Subroutine Call With W
Syntax:
[ label ] COMF f,d
Syntax:
[ label ] CALLW
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
None
(PC) +1 → TOS,
(W) → PC<7:0>,
Operation:
(f) → (destination)
(PCLATH<6:0>) → PC<14:8>
Status Affected:
Description:
Z
The contents of register ‘f’ are com-
plemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Status Affected:
Description:
None
Subroutine call with W. First, the
return address (PC + 1) is pushed
onto the return stack. Then, the con-
tents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLWis a two-cycle
instruction.
DECF
Decrement f
CLRF
Clear f
Syntax:
[ label ] DECF f,d
Syntax:
[ label ] CLRF
0 ≤ f ≤ 127
f
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
00h → (f)
1→ Z
Operation:
(f) - 1 → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W
The contents of register ‘f’ are cleared
and the Z bit is set.
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
Operation:
None
00h → (W)
1→ Z
Status Affected:
Description:
Z
W register is cleared. Zero bit (Z) is
set.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 343
PIC16F193X/LF193X
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ] INCFSZ f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (destination);
skip if result = 0
Operation:
(f) + 1 → (destination),
skip if result = 0
Status Affected:
Description:
None
Status Affected:
Description:
None
The contents of register ‘f’ are decre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, then a
NOPis executed instead, making it a
2-cycle instruction.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, a NOPis
executed instead, making it a 2-cycle
instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR literal with W
Syntax:
[ label ] GOTO
0 ≤ k ≤ 2047
k
Syntax:
[ label ] IORLW
0 ≤ k ≤ 255
(W) .OR. k → (W)
Z
k
Operands:
Operation:
Operands:
Operation:
Status Affected:
Description:
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Status Affected:
Description:
None
The contents of the W register are
OR’ed with the eight-bit literal ‘k’. The
result is placed in the W register.
GOTOis an unconditional branch. The
eleven-bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTOis a two-cycle instruction.
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ] INCF f,d
Syntax:
[ label ] IORWF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) + 1 → (destination)
Operation:
(W) .OR. (f) → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
Inclusive OR the W register with regis-
ter ‘f’. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
DS41364A-page 344
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
LSLF
Logical Left Shift
MOVF
Move f
Syntax:
[ label ] LSLF f {,d}
Syntax:
[ label ] MOVF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f<7>) → C
Operation:
(f) → (dest)
(f<6:0>) → dest<7:1>
0 → dest<0>
Status Affected:
Description:
Z
The contents of register f is moved to
a destination dependent upon the
status of d. If d = 0,
destination is W register. If d = 1, the
destination is file register f itself. d = 1
is useful to test a file register since
status flag Z is affected.
Status Affected:
Description:
C, Z
The contents of register ‘f’ are shifted
one bit to the left through the Carry flag.
A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,
the result is placed in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
Words:
1
1
C
register f
0
Cycles:
Example:
MOVF
FSR, 0
After Instruction
LSRF
Logical Right Shift
W
Z
=
=
value in FSR register
1
Syntax:
[ label ] LSLF f {,d}
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
0 → dest<7>
(f<7:1>) → dest<6:0>,
(f<0>) → C,
Status Affected:
Description:
C, Z
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
0
C
register f
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 345
PIC16F193X/LF193X
MOVIW
Move INDFn to W
MOVLP
Move literal to PCLATH
Syntax:
[ label ] MOVIW ++INDFn
[ label ] MOVIW --INDFn
[ label ] MOVIW INDFn++
[ label ] MOVIW INDFn--
[ label ] MOVIW [k]INDFn
[ label ] MOVIW INDFn
Syntax:
[ label ] MOVLP
0 ≤ k ≤ 127
k → PCLATH
None
k
Operands:
Operation:
Status Affected:
Description:
The seven-bit literal ‘k’ is loaded into the
PCLATH register.
Operands:
Operation:
n ∈ [0,1]
mm ∈ [00, 01, 10, 11].
-32 ≤ k ≤ 31
If not present, k = 0.
MOVLW
Move literal to W
INDFn → W
Effective address is determined by
Syntax:
[ label ] MOVLW
0 ≤ k ≤ 255
k → (W)
k
•
•
•
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
Operands:
Operation:
Status Affected:
Description:
None
After the Move, the FSR value will be
either:
The eight-bit literal ‘k’ is loaded into W
register. The “don’t cares” will assem-
ble as ‘0’s.
•
•
•
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
Words:
1
1
Status Affected:
Z
Cycles:
Example:
MOVLW
0x5A
mm
00
01
10
11
Mode
Syntax
After Instruction
Preincrement
Predecrement
Postincrement
Postdecrement
++INDFn
--INDFn
INDFn++
INDFn--
W
=
0x5A
MOVWF
Move W to f
[ label ] MOVWF
0 ≤ f ≤ 127
(W) → (f)
Syntax:
f
Operands:
Operation:
Status Affected:
Description:
Description:
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
None
Move data from W register to register
‘f’.
Words:
1
1
FSRn is limited to the range 0000h -
FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to wrap
around.
Cycles:
Example:
MOVWF
Before Instruction
OPTION =
OPTION
0xFF
0x4F
The increment/decrement operation on
FSRn WILL NOT affect any Status bits.
W
=
After Instruction
OPTION =
0x4F
0x4F
W
=
MOVLB
Move literal to BSR
Syntax:
[ label ] MOVLB
0 ≤ k ≤ 15
k → BSR
None
k
Operands:
Operation:
Status Affected:
Description:
The five-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).
DS41364A-page 346
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
MOVWI
Move W to INDFn
NOP
No Operation
Syntax:
[ label ] MOVWI ++INDFn
[ label ] MOVWI --INDFn
[ label ] MOVWI INDFn++
[ label ] MOVWI INDFn--
[ label ] MOVWI [k]INDFn
[ label ] MOVWI INDFn
Syntax:
[ label ] NOP
Operands:
Operation:
Status Affected:
Description:
Words:
None
No operation
None
No operation.
Operands:
Operation:
n ∈ [0,1]
mm ∈ [00, 01, 10, 11].
-32 ≤ k ≤ 31
1
Cycles:
1
If not present, k = 0.
Example:
NOP
W → INDFn
Effective address is determined by
•
•
•
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
Load OPTION_REG Register
with W
OPTION
After the Move, the FSR value will be
either:
Syntax:
[ label ] OPTION
None
•
•
FSR + 1 (all increments)
FSR - 1 (all decrements)
Operands:
Operation:
Status Affected:
Description:
Unchanged
(W) → OPTION_REG
None
Status Affected:
None
Move data from W register to
OPTION_REG register.
mm
00
01
10
11
Mode
Syntax
Preincrement
Predecrement
Postincrement
Postdecrement
++INDFn
--INDFn
INDFn++
INDFn--
RESET
Software Reset
Syntax:
[ label ] RESET
Operands:
Operation:
None
Description:
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Execute a device Reset. Resets the
nRI flag of the PCON register.
Status Affected:
Description:
None
This instruction provides a way to
execute a hardware Reset by soft-
ware.
FSRn is limited to the range 0000h -
FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to wrap
around.
The increment/decrement operation on
FSRn WILL NOT affect any Status bits.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 347
PIC16F193X/LF193X
RETURN
Return from Subroutine
RETFIE
Syntax:
Return from Interrupt
[ label ] RETFIE
None
Syntax:
[ label ] RETURN
None
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
TOS → PC
None
TOS → PC,
1→ GIE
Status Affected:
Description:
None
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a two-cycle instruction.
Return from Interrupt. Stack is POPed
and Top-of-Stack (TOS) is loaded in
the PC. Interrupts are enabled by
setting Global
Interrupt Enable bit, GIE
(INTCON<7>). This is a two-cycle
instruction.
Words:
1
Cycles:
Example:
2
RETFIE
After Interrupt
PC
=
TOS
GIE =
1
RLF
Rotate Left f through Carry
RETLW
Syntax:
Return with literal in W
Syntax:
Operands:
[ label ]
RLF f,d
[ label ] RETLW
0 ≤ k ≤ 255
k
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
k → (W);
TOS → PC
Operation:
See description below
C
Status Affected:
Description:
Status Affected:
Description:
None
The contents of register ‘f’ are rotated
one bit to the left through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
The W register is loaded with the eight
bit literal ‘k’. The program counter is
loaded from the top of the stack (the
return address). This is a two-cycle
instruction.
C
Register f
Words:
1
2
Cycles:
Example:
Words:
1
1
CALL TABLE;W contains table
;offset value
Cycles:
Example:
•
•
•
;W now has table value
RLF
REG1,0
TABLE
Before Instruction
REG1
C
=
=
1110 0110
0
ADDWF PC ;W = offset
RETLW k1 ;Begin table
After Instruction
RETLW k2
;
REG1
W
C
=
=
=
1110 0110
1100 1100
1
•
•
•
RETLW kn ; End of table
Before Instruction
W
=
0x07
After Instruction
W
=
value of k8
DS41364A-page 348
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
SUBLW
Subtract W from literal
RRF
Rotate Right f through Carry
Syntax:
[ label ] SUBLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] RRF f,d
Operands:
Operation:
Status Affected:
Description:
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
k - (W) → (W)
C, DC, Z
Operation:
See description below
C
The W register is subtracted (2’s com-
plement method) from the eight-bit
literal ‘k’. The result is placed in the W
register.
Status Affected:
Description:
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
C = 0
W > k
C = 1
W ≤ k
C
Register f
DC = 0
DC = 1
W<3:0> > k<3:0>
W<3:0> ≤ k<3:0>
SUBWF
Subtract W from f
SLEEP
Enter Sleep mode
[ label ] SLEEP
None
Syntax:
[ label ] SUBWF f,d
Syntax:
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
00h → WDT,
0→ WDT prescaler,
1→ TO,
Operation:
(f) - (W) → (destination)
Status Affected:
Description:
C, DC, Z
0→ PD
Subtract (2’s complement method) W
register from register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f.
Status Affected:
Description:
TO, PD
The power-down Status bit, PD is
cleared. Time-out Status bit, TO is
set. Watchdog Timer and its pres-
caler are cleared.
C = 0
W > f
The processor is put into Sleep mode
with the oscillator stopped.
C = 1
W ≤ f
DC = 0
DC = 1
W<3:0> > f<3:0>
W<3:0> ≤ f<3:0>
SUBWFB
Subtract W from f with Borrow
Syntax:
SUBWFB f {,d}
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) – (W) – (B) → dest
Status Affected:
Description:
C, DC, Z
Subtract W and the BORROW flag
(CARRY) from register ‘f’ (2’s comple-
ment method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 349
PIC16F193X/LF193X
SWAPF
Swap Nibbles in f
XORLW
Exclusive OR literal with W
Syntax:
[ label ] SWAPF f,d
Syntax:
[ label ] XORLW
0 ≤ k ≤ 255
k
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
Status Affected:
Description:
(W) .XOR. k → (W)
Z
Operation:
(f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
The contents of the W register are
XOR’ed with the eight-bit
literal ‘k’. The result is placed in the
W register.
Status Affected:
Description:
None
The upper and lower nibbles of regis-
ter ‘f’ are exchanged. If ‘d’ is ‘0’, the
result is placed in the W register. If ‘d’
is ‘1’, the result is placed in register ‘f’.
XORWF
Exclusive OR W with f
TRIS
Load TRIS Register with W
Syntax:
[ label ] XORWF f,d
Syntax:
[ label ] TRIS f
5 ≤ f ≤ 7
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
Status Affected:
Description:
(W) → TRIS register ‘f’
None
Operation:
(W) .XOR. (f) → (destination)
Status Affected:
Description:
Z
Move data from W register to TRIS
register.
When ‘f’ = 5, TRISA is loaded.
When ‘f’ = 6, TRISB is loaded.
When ‘f’ = 7, TRISC is loaded.
Exclusive OR the contents of the W
register with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in regis-
ter ‘f’.
DS41364A-page 350
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
27.1 MPLAB Integrated Development
Environment Software
27.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• A single graphical interface to all debugging tools
- Simulator
- MPLAB C18 and MPLAB C30 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
• Emulators
• Customizable data windows with direct edit of
contents
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debugger
• High-level source code debugging
• Visual device initializer for easy register
initialization
- MPLAB ICD 2
• Mouse over variable inspection
• Device Programmers
• Drag and drop variables from source to watch
windows
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
• Extensive on-line help
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 351
PIC16F193X/LF193X
27.2 MPASM Assembler
27.5 MPLAB ASM30 Assembler, Linker
and Librarian
The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• User-defined macros to streamline
assembly code
• Rich directive set
• Conditional assembly for multi-purpose
source files
• Flexible macro language
• MPLAB IDE compatibility
• Directives that allow complete control over the
assembly process
27.6 MPLAB SIM Software Simulator
27.3 MPLAB C18 and MPLAB C30
C Compilers
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI
C
compilers for
Microchip’s PIC18 and PIC24 families of microcon-
trollers and the dsPIC30 and dsPIC33 family of digital
signal controllers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
27.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS41364A-page 352
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
27.7 MPLAB ICE 2000
High-Performance
27.9 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers cost-
effective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by setting breakpoints, single step-
ping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC
microcontrollers. Software control of the MPLAB ICE
2000 In-Circuit Emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitor-
ing features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
27.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
27.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be supported,
and new features will be added, such as software break-
points and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 353
PIC16F193X/LF193X
27.11 PICSTART Plus Development
Programmer
27.13 Demonstration, Development and
Evaluation Boards
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
27.12 PICkit 2 Development Programmer
The PICkit™ 2 Development Programmer is a low-cost
programmer and selected Flash device debugger with
an easy-to-use interface for programming many of
Microchip’s baseline, mid-range and PIC18F families of
Flash memory microcontrollers. The PICkit 2 Starter Kit
includes a prototyping development board, twelve
sequential lessons, software and HI-TECH’s PICC™
Lite C compiler, and is designed to help get up to speed
quickly using PIC® microcontrollers. The kit provides
everything needed to program, evaluate and develop
applications using Microchip’s powerful, mid-range
Flash memory family of microcontrollers.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS41364A-page 354
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
28.0 ELECTRICAL SPECIFICATIONS
(†)
Absolute Maximum Ratings
Ambient temperature under bias....................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on VDD with respect to VSS, PIC16F193X ............................................................................. -0.3V to +6.5V
Voltage on VDD with respect to VSS, PIC16LF193X ........................................................................... -0.3V to +4.0V
Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ...............................................................................................................................800 mW
Maximum current out of VSS pin ...................................................................................................................... 95 mA
Maximum current into VDD pin......................................................................................................................... 70 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD)................................................................................................................± 20 mA
Maximum output current sunk by any I/O pin....................................................................................................25 mA
Maximum output current sourced by any I/O pin .............................................................................................. 25 mA
Maximum current sunk by all ports(2), -40°C ≤ TA ≤ +85°C for industrial ........................................................ 200 mA
Maximum current sunk by all ports(2), -40°C ≤ TA ≤ +125°C for extended........................................................ 90 mA
Maximum current sourced by all ports(2), 40°C ≤ TA ≤ +85°C for industrial ................................................... 140 mA
Maximum current sourced by all ports(2), -40°C ≤ TA ≤ +125°C for extended................................................... 65 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 355
PIC16F193X/LF193X
FIGURE 28-1:
PIC16F193X VOLTAGE FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C
5.5
3.6
2.5
2.3
2.0
1.8
0
4
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 28-1 for each Oscillator mode’s supported frequencies.
FIGURE 28-2:
PIC16LF193X VOLTAGE FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C
3.6
2.5
2.3
2.0
1.8
0
4
10
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 28-1 for each Oscillator mode’s supported frequencies.
DS41364A-page 356
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
+ 5%
FIGURE 28-3:
125
85
60
25
± 2%
0
-20
+ 5%
3.5
-40
1.8
2.0
2.5
4.0
VDD (V)
4.5
5.0
5.5
3.0
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 357
PIC16F193X/LF193X
28.1 DC Characteristics: PIC16F193X/LF193X-I/E (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
PIC16LF193X
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Standard Operating Conditions (unless otherwise stated)
PIC16F193X
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param.
No.
Sym.
Characteristic
Supply Voltage
Min.
Typ† Max. Units
Conditions
D001
VDD
PIC16LF193X
1.8
2.3
—
—
3.6
3.6
V
V
FOSC ≤ 16 MHz:
FOSC ≤ 32 MHz (NOTE 2)
D001
PIC16F193X
1.8
2.3
—
—
5.5
5.5
V
V
FOSC ≤ 16 MHz:
FOSC ≤ 32 MHz (NOTE 2)
D002*
VDR
RAM Data Retention Voltage(1)
PIC16LF193X
PIC16F193X
Power-on Reset Release Voltage
Power-on Reset Rearm Voltage
PIC16LF193X
PIC16F193X
1.5
1.7
—
—
—
—
—
—
V
V
V
Device in Sleep mode
Device in Sleep mode
D002*
VPOR*
1.6
VPORR*
—
—
0.8
1.7
—
—
V
V
V
Device in Sleep mode
Device in Sleep mode
VADFVR
Fixed Voltage Reference Voltage for 0.984 1.024 1.064
ADC (calibrated) 0.974 1.064
1.968 2.048 2.158
1.938 2.148
3.966 4.096 4.226
3.936 4.226
Fixed Voltage Reference Voltage for 0.984 1.024 1.064
Comparator and DAC 0.974 1.064
1.968 2.048 2.158
1.938 2.148
3.966 4.096 4.226
3.936 4.226
VFVR_REF Fixed Voltage Reference Voltage for 0.984 1.024 1.064
FVRV = 00 (1x), VDD ≥ 2.5V
125°C
FVRV = 01 (2x), VDD ≥ 2.5V
125°C
FVRV = 10 (4x), VDD ≥ 4.75V
125°C
VCDAFVR
V
V
FVRV = 00 (1x), VDD ≥ 2.5V
125°C
FVRV = 01 (2x), VDD ≥ 2.5V
125°C
FVRV = 10 (4x), VDD ≥ 4.75V
125°C
FVRV = 00 (1x), VDD ≥ 2.5V
LCD Bias
0.974
1.064
125°C
D004*
SVDD
VDD Rise Rate to ensure internal
Power-on Reset signal
0.05
—
—
V/ms See Section 3.2 “Power-on Reset
(POR)” for details.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: PLL required for 32 MHz operation.
DS41364A-page 358
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 28-4:
POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
VSS
NPOR
POR REARM
VSS
(3)
(2)
TPOR
TVLOW
Note 1: When NPOR is low, the device is held in Reset.
2: TPOR 1 μs typical.
3: TVLOW 2.7 μs typical.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 359
PIC16F193X/LF193X
28.2 DC Characteristics: PIC16F193X/LF193X-I/E (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
PIC16LF193X
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Standard Operating Conditions (unless otherwise stated)
PIC16F193X
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Conditions
Param
No.
Device
Characteristics
Min.
Typ†
Max.
Units
VDD
Note
(1, 2)
Supply Current (IDD)
LDO Regulator
D009
—
350
TBD
μA
—
HS, EC OR INTOSC/INTOSCIO (8-16 MHZ)
Clock modes with all VCAP pins disabled
—
—
—
50
30
5
μA
μA
μA
—
—
—
All VCAP pins disabled
TBD
TBD
TBD
VCAP enabled on RA0, RA5 or RA6
LP Clock mode and Sleep (requires FVR and
BOR to be disabled)
D010
D010
—
—
7.0
9.0
TBD
TBD
μA
μA
1.8
3.0
FOSC = 32 kHz
LP Oscillator mode (Note 4),
-40°C ≤ TA ≤ +85°C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9.5
12.5
13.5
7.0
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
1.8
3.0
FOSC = 32 kHz
LP Oscillator mode (Note 4),
-40°C ≤ TA ≤ +85°C
D011*
D011*
FOSC = 32 kHz
LP Oscillator mode
9.0
9.5
FOSC = 32 kHz
LP Oscillator mode (Note 4)
12.5
13.5
150
270
160
280
390
430
750
450
770
930
180
350
D011A*
D011A*
FOSC = 1 MHz
XT Oscillator mode
FOSC = 1 MHz
XT Oscillator mode (Note 5)
D012
D012
FOSC = 4 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode (Note 5)
D013*
FOSC = 1 MHz
EC Oscillator mode
*
These parameters are characterized but not tested.
TBD = To Be Determined
Legend:
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in kΩ.
4: FVR and BOR are disabled.
5: 0.1 μF capacitor on VCAP (RA0).
DS41364A-page 360
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
28.2 DC Characteristics: PIC16F193X/LF193X-I/E (Industrial, Extended) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC16LF193X
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Standard Operating Conditions (unless otherwise stated)
PIC16F193X
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Conditions
Param
No.
Device
Characteristics
Min.
Typ†
Max.
Units
VDD
Note
D013*
—
—
—
200
370
450
TBD
TBD
TBD
μA
μA
μA
1.8
3.0
5.0
FOSC = 1 MHz
EC Oscillator mode (Note 5)
(1, 2)
Supply Current (IDD)
D014
D014
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
450
830
475
850
980
130
190
150
210
270
980
1780
1.0
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
mA
mA
mA
mA
mA
mA
mA
mA
μA
μA
μA
μA
μA
mA
mA
1.8
3.0
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
3.0
3.6
FOSC = 4 MHz
EC Oscillator mode
FOSC = 4 MHz
EC Oscillator mode (Note 5)
D015
D015
FOSC = 500 kHz
MFINTOSC mode
FOSC = 500 kHz
MFINTOSC mode (Note 5)
D016*
D016*
FOSC = 8 MHz
HFINTOSC mode
FOSC = 8 MHz
HFINTOSC mode (Note 5)
1.8
2.0
D017
D017
1.5
FOSC = 16 MHz
HFINTOSC mode
2.8
1.7
FOSC = 16 MHz
HFINTOSC mode (Note 5)
2.9
3.1
D018
D018
410
710
430
730
860
5.3
FOSC = 4 MHz
EXTRC mode (Note 3, Note 5)
FOSC = 4 MHz
EXTRC mode (Note 3, Note 5)
D019
FOSC = 32 MHz
HS Oscillator mode
6.0
*
These parameters are characterized but not tested.
TBD = To Be Determined
Legend:
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in kΩ.
4: FVR and BOR are disabled.
5: 0.1 μF capacitor on VCAP (RA0).
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 361
PIC16F193X/LF193X
28.2 DC Characteristics: PIC16F193X/LF193X-I/E (Industrial, Extended) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC16LF193X
PIC16F193X
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Conditions
Param
No.
Device
Characteristics
Min.
Typ†
Max.
Units
VDD
Note
D019
—
—
5.3
6.0
TBD
TBD
mA
mA
3.0
5.0
FOSC = 32 MHz
HS Oscillator mode (Note 5)
*
These parameters are characterized but not tested.
TBD = To Be Determined
Legend:
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in kΩ.
4: FVR and BOR are disabled.
5: 0.1 μF capacitor on VCAP (RA0).
DS41364A-page 362
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
28.3 DC Characteristics: PIC16F193X/LF193X-I/E (Power-Down)
Standard Operating Conditions (unless otherwise stated)
PIC16LF193X
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Standard Operating Conditions (unless otherwise stated)
PIC16F193X
Param
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Conditions
Max.
Max.
Device Characteristics
Min.
Typ†
Units
No.
+85°C +125°C
VDD
Note
(2)
Power-down Base Current (IPD)
D020
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.06
0.08
3.1
3.6
4.5
0.5
0.8
3.8
4.3
5.3
8.5
8.5
32
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
mA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
1.8
3.0
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
WDT, BOR, FVR, and T1OSC
disabled, all Peripherals Inactive
D020
WDT, BOR, FVR, and T1OSC
disabled, all Peripherals Inactive
D021
D021
LPWDT Current (Note 1)
LPWDT Current (Note 1)
D021A
D021A
FVR current (Note 3)
FVR current (Note 3, Note 5)
39
70
D022
D022
—
BOR Current (Note 1, Note 3)
7.5
—
BOR Current (Note 1, Note 3,
Note 5)
34
67
D026
D026
0.6
1.8
4.5
6
T1OSC Current (Note 1)
T1OSC Current (Note 1)
7
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Legend:
TBD = To Be Determined
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled.
4: A/D oscillator source is FRC.
5: 0.1 μF capacitor on VCAP (RA0).
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 363
PIC16F193X/LF193X
28.3 DC Characteristics: PIC16F193X/LF193X-I/E (Power-Down) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC16LF193X
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Standard Operating Conditions (unless otherwise stated)
PIC16F193X
Param
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Conditions
Max.
Max.
Device Characteristics
Min.
Typ†
Units
No.
+85°C +125°C
VDD
Note
(2)
Power-down Base Current (IPD)
D027
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.1
0.1
3.5
4
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
1.8
3.0
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
1.8
3.0
1.8
3.0
5.0
3.6
3.6
3.6
5.0
5.0
5.0
A/D Current (Note 1, Note 4), no
conversion in progress
D027
A/D Current (Note 1, Note 4), no
conversion in progress
4.5
250
250
280
280
280
3.5
7
D027A
D027A
A/D Current (Note 1, Note 4),
conversion in progress
A/D Current (Note 1, Note 4,
Note 5), conversion in progress
D028
D028
Cap Sense
Cap Sense
3.5
7
32
D029
D029
1
LCD Bias Ladder, Low-power
LCD Bias Ladder, Medium-power
LCD Bias Ladder, High-power
LCD Bias Ladder, Low-power
LCD Bias Ladder, Medium-power
LCD Bias Ladder, High-power
10
100
1
10
100
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Legend:
TBD = To Be Determined
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled.
4: A/D oscillator source is FRC.
5: 0.1 μF capacitor on VCAP (RA0).
DS41364A-page 364
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
28.4 DC Characteristics: PIC16F193X/LF193X-I/E
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
VIL
Input Low Voltage
I/O PORT:
D030
D030A
D031
with TTL buffer
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.8
V
V
V
V
V
V
V
4.5V ≤ VDD ≤ 5.5V
0.15 VDD
0.2 VDD
0.3 VDD
0.8
1.8V ≤ VDD ≤ 4.5V
2.0V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
2
with I C™ levels
with SMBus™ levels
2.7V ≤ VDD ≤ 5.5V
(1)
D032
MCLR, OSC1 (RC mode)
0.2 VDD
0.3 VDD
D033A
OSC1 (HS mode)
Input High Voltage
I/O ports:
VIH
—
—
—
—
—
—
D040
with TTL buffer
2.0
V
V
4.5V ≤ VDD ≤ 5.5V
1.8V ≤ VDD ≤ 4.5V
D040A
0.25 VDD +
0.8
D041
with Schmitt Trigger buffer
0.8 VDD
0.7 VDD
2.1
—
—
—
—
—
—
—
—
—
—
—
—
V
V
V
V
V
V
2.0V ≤ VDD ≤ 5.5V
2.7V ≤ VDD ≤ 5.5V
2
with I C™ levels
with SMBus™ levels
MCLR
D042
0.8 VDD
0.7 VDD
0.9 VDD
D043A
D043B
OSC1 (HS mode)
OSC1 (RC mode)
(Note 1)
(2)
IIL
Input Leakage Current
D060
I/O ports
—
± 5
± 100
nA
VSS ≤ VPIN ≤ VDD, Pin at high-
impedance
± 5
± 1000
± 200
± 100
nA 125°C
(3)
D061
D063
MCLR
—
—
± 50
± 50
nA
nA
VSS ≤ VPIN ≤ VDD
OSC1
VSS ≤ VPIN ≤ VDD, XT, HS and LP
oscillator configuration
IPUR
VOL
Weak Pull-up Current
D070*
D080
25
25
100
140
200
300
VDD = 3.3V, VPIN = VSS
VDD = 5.0V, VPIN = VSS
μA
(4)
Output Low Voltage
I/O ports
IOH = 8mA, VDD = 5V
IOH = 6mA, VDD = 3.3V
IOH = 3mA, VDD = 1.8V
—
—
0.6
V
Legend:
TBD = To Be Determined
These parameters are characterized but not tested.
*
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Including OSC2 in CLKOUT mode.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 365
PIC16F193X/LF193X
28.4 DC Characteristics: PIC16F193X/LF193X-I/E (Continued)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
(4)
VOH
Output High Voltage
D090
I/O ports
IOH = 3.5mA, VDD = 5V
IOH = 3mA, VDD = 3.3V
IOH = 2mA, VDD = 1.8V
VDD - 0.7
—
—
V
Capacitive Loading Specs on Output Pins
D101*
COSC2 OSC2 pin
—
—
—
15
50
pF
pF
In XT, HS and LP modes when
external clock is used to drive
OSC1
D101A* CIO
All I/O pins
—
VCAP Capacitor Charging
Charging current
D102
—
—
200
0.0
—
—
μA
mA
D102A
Source/sink capability when
charging complete
Legend:
TBD = To Be Determined
These parameters are characterized but not tested.
*
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Including OSC2 in CLKOUT mode.
DS41364A-page 366
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
28.5 Memory Programming Requirements
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +125°C
DC CHARACTERISTICS
Param
Sym.
No.
Characteristic
Program Memory
Min.
Typ†
Max.
Units
Conditions
Programming Specifications
D110
D111
VIHH
IDDP
Voltage on MCLR/VPP/RE3 pin
8.0
—
—
—
9.0
10
V
(Note 3, Note 4)
Supply Current during
Programming
mA
D112
D113
VDD for Bulk Erase
2.7
—
—
VDD
max.
V
V
VPEW
VDD for Write or Row Erase
VDD
min.
VDD
max.
D114
D115
IPPPGM Current on MCLR/VPP during Erase/
Write
—
—
1.0
mA
mA
IDDPGM Current on VDD during Erase/Write
—
5.0
Data EEPROM Memory
D116
D117
ED
Byte Endurance
—
100K
—
—
E/W -40°C to +85°C
VDD
min.
VDD
max.
VDRW VDD for Read/Write
V
D118
D119
TDEW Erase/Write Cycle Time
TRETD Characteristic Retention
—
4.0
—
5.0
—
ms
40
Year Provided no other
specifications are violated
D120
TREF
Number of Total Erase/Write
Cycles before Refresh
1M
—
10M
—
—
E/W -40°C to +85°C
(2)
Program Flash Memory
Cell Endurance
D121
D122
EP
10K
—
E/W -40°C to +85°C (Note 1)
VDD
min.
VDD
max.
VPR
VDD for Read
V
D123
D124
TIW
Self-timed Write Cycle Time
—
2
2.5
—
ms
TRETD Characteristic Retention
40
—
Year Provided no other
specifications are violated
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Self-write and Block Erase.
2: Refer to Section 23.5.1 “Using the Data EEPROM” for a more detailed discussion on data EEPROM
endurance.
3: Required only if single-supply programming is disabled.
4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be
placed between the ICD 2 and target system when programming or debugging with the ICD 2.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 367
PIC16F193X/LF193X
28.6 Thermal Considerations
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +125°C
Param
No.
Sym.
Characteristic
Typ.
Units
Conditions
28-pin SPDIP package
TH01
θJA
Thermal Resistance Junction to Ambient
60
80
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
28-pin SOIC package
90
28-pin SSOP package
28-pin QFN 6x6mm package
40-pin PDIP package
27.5
47.2
46
44-pin TQFP package
44-pin QFN 8x8mm package
28-pin SPDIP package
28-pin SOIC package
24.4
31.4
24
TH02
θJC
Thermal Resistance Junction to Case
24
28-pin SSOP package
28-pin QFN 6x6mm package
40-pin PDIP package
24
24.7
14.5
20
44-pin TQFP package
44-pin QFN 8x8mm package
TH03
TH04
TH05
TH06
TH07
TJMAX
PD
Maximum Junction Temperature
Power Dissipation
150
—
W
PD = PINTERNAL + PI/O
(1)
PINTERNAL Internal Power Dissipation
—
W
PINTERNAL = IDD x VDD
PI/O
I/O Power Dissipation
Derated Power
—
W
PI/O = Σ (IOL * VOL) + Σ (IOH * (VDD - VOH))
(2)
PDER
—
W
PDER = PDMAX (TJ - TA)/θJA
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature
3: TJ = Junction Temperature
DS41364A-page 368
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
28.7
Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
T
Time
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O PORT
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (High-impedance)
Low
Valid
L
High-impedance
FIGURE 28-5:
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
Legend: CL = 50 pF for all pins, 15 pF for
OSC2 output
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 369
PIC16F193X/LF193X
28.8 AC Characteristics: PIC16F193X/LF193X-I/E
FIGURE 28-6:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1/CLKIN
OS02
OS04
OS04
OS03
OSC2/CLKOUT
(LP,XT,HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
TABLE 28-1: CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +125°C
Param
Sym.
No.
Characteristic
Min.
Typ†
Max.
Units
Conditions
(1)
OS01
FOSC
TOSC
TCY
External CLKIN Frequency
DC
DC
DC
—
—
—
1
4
MHz EC Oscillator mode (low)
MHz EC Oscillator mode (medium)
MHz EC Oscillator mode (high)
—
32
—
4
(1)
Oscillator Frequency
32.768
—
kHz
LP Oscillator mode
0.1
1
MHz XT Oscillator mode
—
4
MHz HS Oscillator mode, VDD ≤ 2.3V
MHz HS Oscillator mode, VDD > 2.3V
MHz RC Oscillator mode
1
—
20
4
DC
27
—
(1)
OS02
External CLKIN Period
—
∞
μs
ns
ns
ns
μs
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
LP Oscillator mode
XT Oscillator mode
HS Oscillator mode
EC Oscillator mode
LP Oscillator mode
XT Oscillator mode
HS Oscillator mode
RC Oscillator mode
TCY = 4/FOSC
250
50
—
∞
—
∞
31.25
—
—
∞
(1)
Oscillator Period
30.5
—
—
10,000
1,000
—
DC
—
—
—
∞
250
50
—
250
200
2
—
(1)
OS03
Instruction Cycle Time
TCY
—
OS04*
TosH,
TosL
External CLKIN High,
External CLKIN Low
LP oscillator
100
20
—
XT oscillator
—
HS oscillator
OS05*
TosR,
TosF
External CLKIN Rise,
External CLKIN Fall
0
—
LP oscillator
0
—
∞
XT oscillator
0
—
∞
HS oscillator
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external
clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
DS41364A-page 370
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 28-2: OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C ≤ TA ≤ +125°C
Param
Sym.
No.
Freq.
Tolerance
Characteristic
Min. Typ† Max. Units
Conditions
OS08
HFOSC
Internal Calibrated HFINTOSC
Frequency
±2%
±5%
±2%
±5%
—
—
—
—
—
—
—
—
16.0
16.0
500
500
5
—
—
—
—
7
MHz 0°C ≤ TA ≤ +85°C
MHz -40°C ≤ TA ≤ +125°C
kHz 0°C ≤ TA ≤ +85°C
kHz -40°C ≤ TA ≤ +125°C
(2)
OS08A MFOSC
Internal Calibrated MFINTOSC
(2)
Frequency
OS10* TIOSC ST HFINTOSC and MFINTOSC
Wake-up from Sleep Start-up Time
μs
μs
μs
VDD = 2.0V, -40°C to +85°C
—
5
7
VDD = 3.0V, -40°C to +85°C
VDD = 5.0V, -40°C to +85°C
—
5
7
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an
external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 μF and 0.01 μF values in parallel are recommended.
3: By design.
TABLE 28-3: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.7V TO 5.5V)
Param
Sym.
Characteristic
Min.
Typ†
Max.
Units Conditions
No.
F10
FOSC Oscillator Frequency Range
4
16
—
—
—
—
8
32
MHz
MHz
ms
F11
FSYS On-Chip VCO System Frequency
F12
F13*
TRC
PLL Start-up Time (Lock Time)
—
2
ΔCLK CLKOUT Stability (Jitter)
-0.25%
+0.25%
%
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 371
PIC16F193X/LF193X
FIGURE 28-7:
CLKOUT AND I/O TIMING
Cycle
Write
Q4
Fetch
Q1
Read
Q2
Execute
Q3
FOSC
OS12
OS11
OS20
OS21
CLKOUT
OS19
OS13
OS18
OS16
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
DS41364A-page 372
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 28-4: CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C ≤ TA ≤ +125°C
Param
No.
Sym.
Characteristic
Min.
Typ† Max. Units
Conditions
OS11 TosH2ckL FOSC↑ to CLKOUT↓ (1)
OS12 TosH2ckH FOSC↑ to CLKOUT↑ (1)
OS13 TckL2ioV CLKOUT↓ to Port out valid(1)
—
—
—
—
—
—
70
72
20
ns VDD = 3.3-5.0V
ns VDD = 3.3-5.0V
ns
OS14 TioV2ckH Port input valid before CLKOUT↑(1)
OS15 TosH2ioV Fosc↑ (Q1 cycle) to Port out valid
TOSC + 200 ns
—
50
—
—
70*
—
ns
—
ns VDD = 3.3-5.0V
ns VDD = 3.3-5.0V
OS16 TosH2ioI
Fosc↑ (Q2 cycle) to Port input invalid
50
(I/O in hold time)
OS17 TioV2osH Port input valid to Fosc↑ (Q2 cycle)
20
—
—
ns
(I/O in setup time)
OS18 TioR
OS19 TioF
Port output rise time(2)
—
—
40
15
72
32
ns
ns
VDD = 1.8V
VDD = 3.3-5.0V
Port output fall time(2)
—
—
28
15
55
30
VDD = 1.8V
VDD = 3.3-5.0V
OS20* Tinp
OS21* Tioc
INT pin input high or low time
25
25
—
—
—
—
ns
ns
Interrupt-on-change new input level
time
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
2: Includes OSC2 in CLKOUT mode.
FIGURE 28-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Start-Up Time
(1)
Internal Reset
Watchdog Timer
(1)
Reset
31
34
34
I/O pins
Note 1: Asserted low.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 373
PIC16F193X/LF193X
FIGURE 28-9:
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR and VHYST
VBOR
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset
(1)
33
(due to BOR)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.
2 ms delay if PWRTE = 0and VREGEN = 1.
DS41364A-page 374
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 28-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C ≤ TA ≤ +125°C
Param
No.
Sym.
TMCL
Characteristic
Min. Typ† Max. Units
Conditions
30
MCLR Pulse Width (low)
2
5
—
—
—
—
μs VDD = 3.3-5V, -40°C to +85°C
μs VDD = 3.3-5V
31
TWDTLP Low-Power Watchdog Timer
Time-out Period (No Prescaler)
10
10
18
18
27
33
ms VDD = 3.3V-5V, -40°C to +85°C
ms VDD = 3.3V-5V
32
TOST
Oscillator Start-up Timer Period(1), (2)
—
1024
65
—
140
2.0
Tosc (Note 3)
33*
34*
TPWRT Power-up Timer Period, PWRTE = 0 40
ms
TIOZ
I/O high-impedance from MCLR Low
or Watchdog Timer Reset
—
—
μs
35
VBOR
VHYST
Brown-out Reset Voltage
2.40
1.80
2.5
1.9
2.60
2.00
V
BORV=2.5V
BORV=1.9V
36*
37*
Brown-out Reset Hysteresis
25
50
75
100
mV -40°C to +85°C
-40°C to 125°C
TBORDC Brown-out Reset DC Response
Time
1
3
5
10
μs VDD ≤ VBOR, -40°C to +85°C
VDD ≤ VBOR
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no
clock) for all devices.
2: By design.
3: Period of the slower clock.
4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 μF and 0.01 μF values in parallel are recommended.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 375
PIC16F193X/LF193X
FIGURE 28-10:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
45
46
49
47
TMR0 or
TMR1
TABLE 28-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C ≤ TA ≤ +125°C
Param
No.
Sym.
TT0H
Characteristic
T0CKI High Pulse Width
Min.
Typ†
Max.
Units
Conditions
40*
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
10
0.5 TCY + 20
10
41*
42*
TT0L
TT0P
T0CKI Low Pulse Width
T0CKI Period
Greater of:
20 or TCY + 40
N
ns N = prescale value
(2, 4, ..., 256)
45*
TT1H
T1CKI High Synchronous, No Prescaler
0.5 TCY + 20
15
—
—
—
—
ns
ns
Time
Synchronous,
with Prescaler
Asynchronous
30
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
46*
47*
TT1L
TT1P
T1CKI Low Synchronous, No Prescaler
0.5 TCY + 20
Time
Synchronous, with Prescaler
Asynchronous
15
30
T1CKI Input Synchronous
Period
Greater of:
30 or TCY + 40
N
ns N = prescale value
(1, 2, 4, 8)
Asynchronous
60
—
—
ns
48
FT1
Timer1 Oscillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN)
32.4
32.768
33.1
kHz
49*
TCKEZTMR1 Delay from External Clock Edge to Timer
Increment
2 TOSC
—
7 TOSC
—
Timers in Sync
mode
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS41364A-page 376
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 28-11:
CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCPx
(Capture mode)
CC01
CC02
CC03
Note: Refer to Figure 28.5 for load conditions.
TABLE 28-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C ≤ TA ≤ +125°C
Param
No.
Sym.
Characteristic
Min.
Typ† Max. Units
Conditions
CC01* TccL CCPx Input Low Time
CC02* TccH CCPx Input High Time
CC03* TccP CCPx Input Period
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
20
0.5TCY + 20
20
3TCY + 40
N
N = prescale value (1, 4 or 16)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
TABLE 28-8: PIC16F193X/LF193X A/D CONVERTER (ADC) CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +125°C
Param
No.
Sym.
Characteristic
Min.
Typ†
Max. Units
Conditions
AD01 NR
AD02 EIL
AD03 EDL
Resolution
—
—
—
—
—
—
10
±1
±1
bit
Integral Error
LSb VREF = 3.0V
Differential Error
LSb No missing codes
VREF = 3.0V
AD04 EOFF Offset Error
—
—
—
—
—
—
—
±3
±3
LSb VREF = 3.0V
AD05 EGN Gain Error
LSb VREF = 3.0V
(3)
AD06 VREF Reference Voltage
AD07 VAIN Full-Scale Range
1.8
VSS
—
VDD
VREF
50
V
V
AD08 ZAIN Recommended Impedance of
Analog Voltage Source
kΩ Can go higher if external 0.01μF capacitor is
present on input pin.
(3)
AD09* IREF VREF Input Current
10
—
—
—
1000
10
μA During VAIN acquisition.
Based on differential of VHOLD to VAIN.
μA During A/D conversion cycle.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
3: ADC VREF is from external VREF, VDD pin or FVREF, whichever is selected as reference input.
4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification
includes any such leakage from the ADC module.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 377
PIC16F193X/LF193X
TABLE 28-9: PIC16F193X/LF193X A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +125°C
Param
Sym.
No.
Characteristic
Min.
Typ†
Max. Units
Conditions
AD130* TAD
A/D Clock Period
1.0
1.0
—
9.0
6.0
μs
μs
TOSC-based
ADCS<1:0> = 11(ADRC mode)
A/D Internal RC Oscillator
Period
1.6
AD131 TCNV Conversion Time (not including
—
—
10.5
9.5
—
—
TAD Set GO/DONE bit to conversion
complete
(1)
Acquisition Time)
AD132* TACQ Acquisition Time
μs
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The ADRES register may be read on the following TCY cycle.
FIGURE 28-12:
PIC16F193X/LF193X A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
1 TCY
(1)
(TOSC/2
AD134
Q4
)
AD131
AD130
A/D CLK
7
6
5
4
3
2
1
0
A/D Data
ADRES
NEW_DATA
1 TCY
OLD_DATA
ADIF
GO
DONE
Sampling Stopped
AD132
Sample
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
DS41364A-page 378
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 28-13:
PIC16F193X/LF193X A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
AD134
(1)
(TOSC/2 + TCY
1 TCY
)
AD131
Q4
AD130
A/D CLK
A/D Data
7
6
5
3
2
1
0
4
NEW_DATA
1 TCY
OLD_DATA
ADRES
ADIF
GO
DONE
Sampling Stopped
AD132
Sample
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 379
PIC16F193X/LF193X
TABLE 28-10: COMPARATOR SPECIFICATIONS
Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated).
Param
No.
Sym.
Characteristics
Input Offset Voltage
Min.
Typ.
Max.
Units
Comments
CM01
VIOFF
—
0
±7.5
—
±15
VDD
—
mV
V
CM02
CM03
CM04
CM05
VICM
Input Common Mode Voltage
Common Mode Rejection Ratio
Response Time
CMRR
TRESP
55
—
—
—
dB
ns
μs
150
—
400
10
Note 1
TMC2OV Comparator Mode Change to
Output Valid*
*
These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions
from VSS to VDD.
TABLE 28-11: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS
Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated).
Param
No.
Sym.
Characteristics
Step Size(2)
Min.
Typ.
Max.
Units
Comments
DAC01*
DAC02*
DAC03*
DAC04*
*
CLSB
—
—
—
—
VDD/32
—
—
± 1/2
—
V
LSb
Ω
CACC
CR
Absolute Accuracy
Unit Resistor Value (R)
Settling Time(1)
TBD
—
CST
10
μs
These parameters are characterized but not tested.
Legend: TBD = To Be Determined
Note 1: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’.
TABLE 28-12: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS
Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated).
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C
VR Voltage Reference Specifications
Param
Sym.
Characteristics
Min.
Typ.
1.024
2.048
4.096
Max.
Units
Comments
No.
VR01
VFVR
Fixed Voltage Reference
Voltage
0.984
0.974
1.968
1.938
3.966
3.936
1.064
1.064
2.158
2.148
4.226
4.226
V
FVRV = 00 (1x), VDD ≥ 2V
125°C
(calibrated)
FVRV = 01 (2x), VDD ≥
2.5V
125°C
FVRV = 10 (4x), VDD ≥
4.75V
125°C
VR02
VR03
VR04
TCVOUT Voltage drift temperature
coefficient
—
—
—
TBD
TBD
TBD
TBD
—
ppm/°C
μV/V
μs
ΔVROUT/ Voltage drift with respect to
ΔVDD
VDD regulation
TSTABLE Settling Time
TBD
Legend: TBD = To Be Determined
These parameters are characterized but not tested.
*
DS41364A-page 380
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 28-14:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
CK
DT
US121
US121
US122
US120
Refer to Figure 28-5 for load conditions.
Note:
TABLE 28-13: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C ≤ TA ≤ +125°C
Param.
Symbol
No.
Characteristic
Min.
Max.
Units Conditions
US120 TCKH2DTV SYNC XMIT (Master and Slave)
Clock high to data-out valid
3.0-5.5V
1.8-5.5V
3.0-5.5V
1.8-5.5V
3.0-5.5V
1.8-5.5V
—
—
—
—
—
—
80
100
45
ns
ns
ns
ns
ns
ns
US121 TCKRF
Clock out rise time and fall time
(Master mode)
50
US122 TDTRF
Data-out rise time and fall time
45
50
FIGURE 28-15:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
CK
DT
US125
US126
Note: Refer to Figure 28-5 for load conditions.
TABLE 28-14: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C ≤ TA ≤ +125°C
Param.
Symbol
No.
Characteristic
Min.
Max. Units
Conditions
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-hold before CK ↓ (DT hold time)
10
15
—
—
ns
ns
US126 TCKL2DTL Data-hold after CK ↓ (DT hold time)
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 381
PIC16F193X/LF193X
FIGURE 28-16:
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SS
SP70
SCK
(CKP = 0)
SP71
SP72
SP78
SP79
SP79
SCK
(CKP = 1)
SP78
LSb
SP80
MSb
bit 6 - - - - - -1
SDO
SDI
SP75, SP76
bit 6 - - - -1
MSb In
LSb In
SP74
SP73
Note: Refer to Figure 28-5 for load conditions.
FIGURE 28-17:
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
SP81
SCK
(CKP = 0)
SP71
SP73
SP72
SP79
SCK
(CKP = 1)
SP80
SP78
LSb
MSb
bit 6 - - - - - -1
SDO
SDI
SP75, SP76
bit 6 - - - -1
MSb In
SP74
Note: Refer to Figure 28-5 for load conditions.
LSb In
DS41364A-page 382
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 28-18:
SPI SLAVE MODE TIMING (CKE = 0)
SS
SP70
SCK
(CKP = 0)
SP83
SP71
SP72
SP78
SP79
SP79
SCK
(CKP = 1)
SP78
LSb
SP80
MSb
SDO
SDI
bit 6 - - - - - -1
SP77
SP75, SP76
bit 6 - - - -1
MSb In
SP74
SP73
LSb In
Note: Refer to Figure 28-5 for load conditions.
FIGURE 28-19:
SPI SLAVE MODE TIMING (CKE = 1)
SP82
SP70
SS
SP83
SCK
(CKP = 0)
SP72
SP71
SCK
(CKP = 1)
SP80
MSb
bit 6 - - - - - -1
LSb
SDO
SDI
SP77
SP75, SP76
bit 6 - - - -1
MSb In
SP74
LSb In
Note: Refer to Figure 28-5 for load conditions.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 383
PIC16F193X/LF193X
TABLE 28-15: SPI MODE REQUIREMENTS
Param
No.
Symbol
Characteristic
Min.
Typ† Max. Units Conditions
SP70* TSSL2SCH, SS↓ to SCK↓ or SCK↑ input
TCY
—
—
ns
TSSL2SCL
SP71* TSCH
SP72* TSCL
SCK input high time (Slave mode)
SCK input low time (Slave mode)
TCY + 20
TCY + 20
100
—
—
—
—
—
—
ns
ns
ns
SP73* TDIV2SCH, Setup time of SDI data input to SCK edge
TDIV2SCL
SP74* TSCH2DIL, Hold time of SDI data input to SCK edge
TSCL2DIL
100
—
—
ns
SP75* TDOR
SDO data output rise time
3.0-5.5V
1.8-5.5V
—
—
—
10
—
—
—
—
—
Tcy
10
25
10
—
10
25
10
—
—
—
25
50
25
50
25
50
25
50
145
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SP76* TDOF
SDO data output fall time
SP77* TSSH2DOZ SS↑ to SDO output high-impedance
SP78* TSCR
SCK output rise time
(Master mode)
3.0-5.5V
1.8-5.5V
SP79* TSCF
SCK output fall time (Master mode)
SP80* TSCH2DOV, SDO data output valid after
TSCL2DOV SCK edge
3.0-5.5V
1.8-5.5V
SP81* TDOV2SCH, SDO data output setup to SCK edge
TDOV2SCL
SP82* TSSL2DOV SDO data output valid after SS↓ edge
—
—
—
50
—
ns
ns
SP83* TSCH2SSH, SS ↑ after SCK edge
1.5TCY + 40
TSCL2SSH
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 28-20:
I2C™ BUS START/STOP BITS TIMING
SCL
SP93
SP91
SP90
SP92
SDA
Stop
Condition
Start
Condition
Note: Refer to Figure 28-5 for load conditions.
DS41364A-page 384
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 28-16: I2C™ BUS START/STOP BITS REQUIREMENTS
Param
No.
Symbol
Characteristic
Min. Typ Max. Units
Conditions
SP90* TSU:STA Start condition
Setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for Repeated
Start condition
SP91* THD:STA Start condition
Hold time
4000
600
ns After this period, the first
clock pulse is generated
SP92* TSU:STO Stop condition
Setup time
4700
600
ns
SP93 THD:STO Stop condition
Hold time
4000
600
ns
*
These parameters are characterized but not tested.
FIGURE 28-21:
I2C™ BUS DATA TIMING
SP100
SP103
SP102
SP101
SCL
SP90
SP106
SP107
SP92
SP91
SDA
In
SP110
SP109
SP109
SDA
Out
Note: Refer to Figure 28-5 for load conditions.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 385
PIC16F193X/LF193X
TABLE 28-17: I2C™ BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min.
Max. Units
Conditions
SP100* THIGH
Clock high time
100 kHz mode
4.0
—
—
μs
μs
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
Device must operate at a
minimum of 10 MHz
SSP module
1.5TCY
4.7
—
—
SP101* TLOW
Clock low time
100 kHz mode
μs
μs
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
SSP module
1.3
—
Device must operate at a
minimum of 10 MHz
1.5TCY
—
—
SP102* TR
SP103* TF
SDA and SCL rise 100 kHz mode
time
1000
ns
ns
400 kHz mode
20 + 0.1CB 300
CB is specified to be from
10-400 pF
SDA and SCL fall
time
100 kHz mode
400 kHz mode
—
250
ns
ns
20 + 0.1CB 250
CB is specified to be from
10-400 pF
SP90* TSU:STA Start condition
setup time
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
μs
μs
μs
μs
ns
μs
ns
ns
μs
μs
ns
ns
μs
μs
Only relevant for
Repeated Start condition
SP91* THD:STA Start condition hold 100 kHz mode
—
After this period the first
clock pulse is generated
time
400 kHz mode
—
SP106* THD:DAT Data input hold time 100 kHz mode
400 kHz mode
—
0
0.9
—
SP107* TSU:DAT Data input setup
time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
(Note 2)
—
SP92* TSU:STO Stop condition
setup time
—
—
SP109* TAA
Output valid from
clock
3500
—
(Note 1)
—
SP110* TBUF
Bus free time
4.7
1.3
—
Time the bus must be free
before a new transmission
can start
—
SP111 CB
Bus capacitive loading
—
400
pF
*
These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but
the requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does
not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal,
it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to
the Standard mode I2C bus specification), before the SCL line is released.
DS41364A-page 386
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 28-18: CAP SENSE OSCILLATOR SPECIFICATIONS
Param.
No.
Symbol
Characteristic
Min.
Typ†
Max. Units
Conditions
CS01
ISRC
Current Source
High
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
μs
μs
μs
μs
μs
μs
μs
μs
-5.8
-1.1
-0.2
6.6
Medium
Low
CS02
ISNK
Current Sink
High
Medium
Low
1.3
0.24
0.8
CS03 VCTH
CS04 VCTL
Cap Threshold
Cap Threshold
High
Low
0.4
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 28-22:
CAP SENSE OSCILLATOR
VCTH
VCTL
ISRC
Enabled
ISNK
Enabled
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 387
PIC16F193X/LF193X
NOTES:
DS41364A-page 388
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
29.0 DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
Graphs and charts are not available at this time.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 389
PIC16F193X/LF193X
NOTES:
DS41364A-page 390
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
30.0 PACKAGING INFORMATION
30.1 Package Marking Information
28-Lead SPDIP
Example
PIC16F1936
-I/SP
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
e
3
YYWWNNN
0810017
40-Lead PDIP
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
PIC16F1937
-I/P
e
3
0810017
Example
28-Lead QFN
16F1936
XXXXXXXX
XXXXXXXX
YYWWNNN
e
3
-I/ML
0810017
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
*
Standard PICmicro® device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 391
PIC16F193X/LF193X
Package Marking Information (Continued)
44-Lead QFN
Example
-I/ML
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC16F1937
e
3
0810017
28-Lead SOIC
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
PIC16F1936
-I/SO
e
3
0810017
YYWWNNN
28-Lead SSOP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16F1936
-I/SS
e
3
YYWWNNN
0810017
44-Lead TQFP
Example
-I/PT
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
PIC16F1937
e
3
0810017
DS41364A-page 392
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
30.2 Package Details
The following sections give the technical details of the packages.
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢊꢋꢋꢌꢇꢍꢎꢅꢏꢐꢊꢑꢇꢒꢓꢅꢎꢇꢔꢋꢂꢃꢊꢋꢄꢇꢕꢈꢍꢖꢇMꢇꢗꢘꢘꢇꢙꢊꢎꢇꢚꢛꢆꢌꢇꢜꢈꢍꢒꢔꢍ
!ꢛꢐꢄ" 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
N
NOTE 1
E1
1
2 3
D
E
A2
A
L
c
b1
A1
b
e
eB
6ꢄꢃ&!
ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢅ9ꢃ'ꢃ&!
ꢚ7,8.ꢐ
7:ꢔ
ꢎ<
ꢁꢀꢕꢕꢅ1ꢐ,
M
ꢔꢚ7
ꢔꢗ;
7"')ꢈꢉꢅꢋ%ꢅꢂꢃꢄ!
ꢂꢃ&ꢌꢍ
7
ꢈ
ꢗ
ꢙꢋꢓꢅ&ꢋꢅꢐꢈꢆ&ꢃꢄꢑꢅꢂꢇꢆꢄꢈ
M
ꢁꢎꢕꢕ
ꢁꢀꢘꢕ
M
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅꢙꢍꢃꢌ4ꢄꢈ!!
1ꢆ!ꢈꢅ&ꢋꢅꢐꢈꢆ&ꢃꢄꢑꢅꢂꢇꢆꢄꢈ
ꢐꢍꢋ"ꢇ#ꢈꢉꢅ&ꢋꢅꢐꢍꢋ"ꢇ#ꢈꢉꢅ>ꢃ#&ꢍ
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅ9ꢈꢄꢑ&ꢍ
ꢙꢃꢓꢅ&ꢋꢅꢐꢈꢆ&ꢃꢄꢑꢅꢂꢇꢆꢄꢈ
9ꢈꢆ#ꢅꢙꢍꢃꢌ4ꢄꢈ!!
6ꢓꢓꢈꢉꢅ9ꢈꢆ#ꢅ>ꢃ#&ꢍ
ꢗꢎ
ꢗꢀ
.
.ꢀ
ꢒ
9
ꢌ
)ꢀ
)
ꢈ1
ꢁꢀꢎꢕ
ꢁꢕꢀꢘ
ꢁꢎꢛꢕ
ꢁꢎꢖꢕ
ꢀꢁ-ꢖꢘ
ꢁꢀꢀꢕ
ꢁꢕꢕ<
ꢁꢕꢖꢕ
ꢁꢕꢀꢖ
M
ꢁꢀ-ꢘ
M
ꢁ-ꢀꢕ
ꢁꢎ<ꢘ
ꢀꢁ-?ꢘ
ꢁꢀ-ꢕ
ꢁꢕꢀꢕ
ꢁꢕꢘꢕ
ꢁꢕꢀ<
M
ꢁ--ꢘ
ꢁꢎꢛꢘ
ꢀꢁꢖꢕꢕ
ꢁꢀꢘꢕ
ꢁꢕꢀꢘ
ꢁꢕꢜꢕ
ꢁꢕꢎꢎ
ꢁꢖ-ꢕ
9ꢋ*ꢈꢉꢅ9ꢈꢆ#ꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅꢝꢋ*ꢅꢐꢓꢆꢌꢃꢄꢑꢅꢅꢏ
!ꢛꢐꢄꢏ"
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢏꢅꢐꢃꢑꢄꢃ%ꢃꢌꢆꢄ&ꢅ,ꢍꢆꢉꢆꢌ&ꢈꢉꢃ!&ꢃꢌꢁ
-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢒꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢔꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢁꢕꢀꢕ/ꢅꢓꢈꢉꢅ!ꢃ#ꢈꢁ
ꢖꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕꢜꢕ1
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 393
PIC16F193X/LF193X
#ꢘꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇꢒꢓꢅꢎꢇꢔꢋꢂꢃꢊꢋꢄꢇꢕꢍꢖꢇMꢇ$ꢘꢘꢇꢙꢊꢎꢇꢚꢛꢆꢌꢇꢜꢍꢒꢔꢍ
!ꢛꢐꢄ" 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
N
NOTE 1
E1
1 2 3
D
E
A2
A
L
c
b1
b
A1
e
eB
6ꢄꢃ&!
ꢚ7,8.ꢐ
ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢅ9ꢃ'ꢃ&!
ꢔꢚ7
7:ꢔ
ꢔꢗ;
7"')ꢈꢉꢅꢋ%ꢅꢂꢃꢄ!
ꢂꢃ&ꢌꢍ
7
ꢈ
ꢖꢕ
ꢁꢀꢕꢕꢅ1ꢐ,
ꢙꢋꢓꢅ&ꢋꢅꢐꢈꢆ&ꢃꢄꢑꢅꢂꢇꢆꢄꢈ
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅꢙꢍꢃꢌ4ꢄꢈ!!
1ꢆ!ꢈꢅ&ꢋꢅꢐꢈꢆ&ꢃꢄꢑꢅꢂꢇꢆꢄꢈ
ꢐꢍꢋ"ꢇ#ꢈꢉꢅ&ꢋꢅꢐꢍꢋ"ꢇ#ꢈꢉꢅ>ꢃ#&ꢍ
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅ9ꢈꢄꢑ&ꢍ
ꢙꢃꢓꢅ&ꢋꢅꢐꢈꢆ&ꢃꢄꢑꢅꢂꢇꢆꢄꢈ
9ꢈꢆ#ꢅꢙꢍꢃꢌ4ꢄꢈ!!
6ꢓꢓꢈꢉꢅ9ꢈꢆ#ꢅ>ꢃ#&ꢍ
ꢗ
M
M
M
M
M
M
M
M
M
M
M
M
ꢁꢎꢘꢕ
ꢁꢀꢛꢘ
M
ꢗꢎ
ꢗꢀ
.
.ꢀ
ꢒ
9
ꢌ
)ꢀ
)
ꢈ1
ꢁꢀꢎꢘ
ꢁꢕꢀꢘ
ꢁꢘꢛꢕ
ꢁꢖ<ꢘ
ꢀꢁꢛ<ꢕ
ꢁꢀꢀꢘ
ꢁꢕꢕ<
ꢁꢕ-ꢕ
ꢁꢕꢀꢖ
M
ꢁ?ꢎꢘ
ꢁꢘ<ꢕ
ꢎꢁꢕꢛꢘ
ꢁꢎꢕꢕ
ꢁꢕꢀꢘ
ꢁꢕꢜꢕ
ꢁꢕꢎ-
ꢁꢜꢕꢕ
9ꢋ*ꢈꢉꢅ9ꢈꢆ#ꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅꢝꢋ*ꢅꢐꢓꢆꢌꢃꢄꢑꢅꢅꢏ
!ꢛꢐꢄꢏ"
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢏꢅꢐꢃꢑꢄꢃ%ꢃꢌꢆꢄ&ꢅ,ꢍꢆꢉꢆꢌ&ꢈꢉꢃ!&ꢃꢌꢁ
-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢒꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢔꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢁꢕꢀꢕ/ꢅꢓꢈꢉꢅ!ꢃ#ꢈꢁ
ꢖꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕꢀ?1
DS41364A-page 394
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
ꢀꢁꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇ%ꢓꢅꢆꢇ&ꢎꢅꢐ'ꢇ!ꢛꢇꢃꢄꢅꢆꢇꢍꢅꢑꢉꢅ(ꢄꢇꢕ)ꢃꢖꢇMꢇ$*$ꢇꢙꢙꢇꢚꢛꢆꢌꢇꢜ%&!
+ꢊꢐ,ꢇꢘ-..ꢇꢙꢙꢇ/ꢛꢋꢐꢅꢑꢐꢇꢃꢄꢋ(ꢐ,
!ꢛꢐꢄ" 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
D
D2
EXPOSED
PAD
e
E
b
E2
2
1
2
1
K
N
N
NOTE 1
L
BOTTOM VIEW
TOP VIEW
A
A3
A1
6ꢄꢃ&!
ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢅ9ꢃ'ꢃ&!
ꢔꢚ99ꢚꢔ.ꢙ.ꢝꢐ
7:ꢔ
ꢔꢚ7
ꢔꢗ;
7"')ꢈꢉꢅꢋ%ꢅꢂꢃꢄ!
ꢂꢃ&ꢌꢍ
: ꢈꢉꢆꢇꢇꢅ8ꢈꢃꢑꢍ&
ꢐ&ꢆꢄ#ꢋ%%ꢅ
,ꢋꢄ&ꢆꢌ&ꢅꢙꢍꢃꢌ4ꢄꢈ!!
: ꢈꢉꢆꢇꢇꢅ>ꢃ#&ꢍ
.$ꢓꢋ!ꢈ#ꢅꢂꢆ#ꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅ9ꢈꢄꢑ&ꢍ
.$ꢓꢋ!ꢈ#ꢅꢂꢆ#ꢅ9ꢈꢄꢑ&ꢍ
,ꢋꢄ&ꢆꢌ&ꢅ>ꢃ#&ꢍ
,ꢋꢄ&ꢆꢌ&ꢅ9ꢈꢄꢑ&ꢍ
,ꢋꢄ&ꢆꢌ&ꢞ&ꢋꢞ.$ꢓꢋ!ꢈ#ꢅꢂꢆ#
7
ꢈ
ꢗ
ꢗꢀ
ꢗ-
.
.ꢎ
ꢒ
ꢎ<
ꢕꢁ?ꢘꢅ1ꢐ,
ꢕꢁꢛꢕ
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ꢕꢁꢕꢕ
ꢀꢁꢕꢕ
ꢕꢁꢕꢘ
ꢕꢁꢕꢎ
ꢕꢁꢎꢕꢅꢝ.3
?ꢁꢕꢕꢅ1ꢐ,
-ꢁꢜꢕ
?ꢁꢕꢕꢅ1ꢐ,
-ꢁꢜꢕ
ꢕꢁ-ꢕ
ꢕꢁꢘꢘ
M
-ꢁ?ꢘ
ꢖꢁꢎꢕ
ꢒꢎ
)
9
-ꢁ?ꢘ
ꢕꢁꢎ-
ꢕꢁꢘꢕ
ꢕꢁꢎꢕ
ꢖꢁꢎꢕ
ꢕꢁ-ꢘ
ꢕꢁꢜꢕ
M
@
!ꢛꢐꢄꢏ"
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢂꢆꢌ4ꢆꢑꢈꢅꢃ!ꢅ!ꢆ*ꢅ!ꢃꢄꢑ"ꢇꢆ&ꢈ#ꢁ
-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢀꢕꢘ1
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 395
PIC16F193X/LF193X
ꢀꢁꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇ%ꢓꢅꢆꢇ&ꢎꢅꢐ'ꢇ!ꢛꢇꢃꢄꢅꢆꢇꢍꢅꢑꢉꢅ(ꢄꢇꢕ)ꢃꢖꢇMꢇ$*$ꢇꢙꢙꢇꢚꢛꢆꢌꢇꢜ%&!
+ꢊꢐ,ꢇꢘ-..ꢇꢙꢙꢇ/ꢛꢋꢐꢅꢑꢐꢇꢃꢄꢋ(ꢐ,
!ꢛꢐꢄ" 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
DS41364A-page 396
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
##ꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇ%ꢓꢅꢆꢇ&ꢎꢅꢐ'ꢇ!ꢛꢇꢃꢄꢅꢆꢇꢍꢅꢑꢉꢅ(ꢄꢇꢕ)ꢃꢖꢇMꢇꢁ*ꢁꢇꢙꢙꢇꢚꢛꢆꢌꢇꢜ%&!
!ꢛꢐꢄ" 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
D2
D
EXPOSED
PAD
e
b
K
E
E2
2
1
2
1
N
N
NOTE 1
L
TOP VIEW
BOTTOM VIEW
A
A3
A1
6ꢄꢃ&!
ꢔꢚ99ꢚꢔ.ꢙ.ꢝꢐ
ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢅ9ꢃ'ꢃ&!
ꢔꢚ7
7:ꢔ
ꢖꢖ
ꢕꢁ?ꢘꢅ1ꢐ,
ꢕꢁꢛꢕ
ꢔꢗ;
7"')ꢈꢉꢅꢋ%ꢅꢂꢃꢄ!
ꢂꢃ&ꢌꢍ
: ꢈꢉꢆꢇꢇꢅ8ꢈꢃꢑꢍ&
ꢐ&ꢆꢄ#ꢋ%%ꢅ
,ꢋꢄ&ꢆꢌ&ꢅꢙꢍꢃꢌ4ꢄꢈ!!
: ꢈꢉꢆꢇꢇꢅ>ꢃ#&ꢍ
7
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.ꢎ
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ꢕꢁꢕꢕ
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ꢕꢁꢕꢎ
ꢕꢁꢎꢕꢅꢝ.3
<ꢁꢕꢕꢅ1ꢐ,
?ꢁꢖꢘ
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ꢕꢁ-ꢕ
ꢕꢁꢖꢕ
M
.$ꢓꢋ!ꢈ#ꢅꢂꢆ#ꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅ9ꢈꢄꢑ&ꢍ
.$ꢓꢋ!ꢈ#ꢅꢂꢆ#ꢅ9ꢈꢄꢑ&ꢍ
,ꢋꢄ&ꢆꢌ&ꢅ>ꢃ#&ꢍ
,ꢋꢄ&ꢆꢌ&ꢅ9ꢈꢄꢑ&ꢍ
,ꢋꢄ&ꢆꢌ&ꢞ&ꢋꢞ.$ꢓꢋ!ꢈ#ꢅꢂꢆ#
?ꢁ-ꢕ
?ꢁ<ꢕ
ꢒꢎ
)
9
?ꢁ-ꢕ
ꢕꢁꢎꢘ
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ꢕꢁ-<
ꢕꢁꢘꢕ
M
@
!ꢛꢐꢄꢏ"
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢂꢆꢌ4ꢆꢑꢈꢅꢃ!ꢅ!ꢆ*ꢅ!ꢃꢄꢑ"ꢇꢆ&ꢈ#ꢁ
-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢀꢕ-1
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 397
PIC16F193X/LF193X
##ꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇ%ꢓꢅꢆꢇ&ꢎꢅꢐ'ꢇ!ꢛꢇꢃꢄꢅꢆꢇꢍꢅꢑꢉꢅ(ꢄꢇꢕ)ꢃꢖꢇMꢇꢁ*ꢁꢇꢙꢙꢇꢚꢛꢆꢌꢇꢜ%&!
!ꢛꢐꢄ" 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
DS41364A-page 398
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
ꢀꢁꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇꢈꢙꢅꢎꢎꢇ0ꢓꢐꢎꢊꢋꢄꢇꢕꢈ0ꢖꢇMꢇ1ꢊꢆꢄ'ꢇ2-.ꢘꢇꢙꢙꢇꢚꢛꢆꢌꢇꢜꢈ0ꢔ/
!ꢛꢐꢄ" 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
D
N
E
E1
NOTE 1
1
2
3
e
b
h
α
h
c
φ
A2
A
L
A1
L1
β
6ꢄꢃ&!
ꢔꢚ99ꢚꢔ.ꢙ.ꢝꢐ
ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢅ9ꢃ'ꢃ&!
ꢔꢚ7
7:ꢔ
ꢔꢗ;
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ꢂꢃ&ꢌꢍ
7
ꢈ
ꢎ<
ꢀꢁꢎꢜꢅ1ꢐ,
: ꢈꢉꢆꢇꢇꢅ8ꢈꢃꢑꢍ&
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅꢙꢍꢃꢌ4ꢄꢈ!!
ꢐ&ꢆꢄ#ꢋ%%ꢅꢅꢏ
ꢗ
M
ꢎꢁꢕꢘ
ꢕꢁꢀꢕ
M
M
M
ꢎꢁ?ꢘ
M
ꢕꢁ-ꢕ
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ꢗꢀ
.
: ꢈꢉꢆꢇꢇꢅ>ꢃ#&ꢍ
ꢀꢕꢁ-ꢕꢅ1ꢐ,
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅ9ꢈꢄꢑ&ꢍ
,ꢍꢆ'%ꢈꢉꢅAꢋꢓ&ꢃꢋꢄꢆꢇB
3ꢋꢋ&ꢅ9ꢈꢄꢑ&ꢍ
.ꢀ
ꢒ
ꢍ
ꢜꢁꢘꢕꢅ1ꢐ,
ꢀꢜꢁꢛꢕꢅ1ꢐ,
ꢕꢁꢎꢘ
ꢕꢁꢖꢕ
M
M
ꢕꢁꢜꢘ
ꢀꢁꢎꢜ
9
3ꢋꢋ&ꢓꢉꢃꢄ&
9ꢀ
ꢀ
ꢀꢁꢖꢕꢅꢝ.3
3ꢋꢋ&ꢅꢗꢄꢑꢇꢈꢅꢙꢋꢓ
9ꢈꢆ#ꢅꢙꢍꢃꢌ4ꢄꢈ!!
9ꢈꢆ#ꢅ>ꢃ#&ꢍ
ꢔꢋꢇ#ꢅꢒꢉꢆ%&ꢅꢗꢄꢑꢇꢈꢅꢙꢋꢓ
ꢔꢋꢇ#ꢅꢒꢉꢆ%&ꢅꢗꢄꢑꢇꢈꢅ1ꢋ&&ꢋ'
ꢕꢟ
ꢕꢁꢀ<
ꢕꢁ-ꢀ
ꢘꢟ
M
M
M
M
M
<ꢟ
ꢌ
)
ꢁ
ꢕꢁ--
ꢕꢁꢘꢀ
ꢀꢘꢟ
ꢂ
ꢘꢟ
ꢀꢘꢟ
!ꢛꢐꢄꢏ"
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢏꢅꢐꢃꢑꢄꢃ%ꢃꢌꢆꢄ&ꢅ,ꢍꢆꢉꢆꢌ&ꢈꢉꢃ!&ꢃꢌꢁ
-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢒꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢔꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢕꢁꢀꢘꢅ''ꢅꢓꢈꢉꢅ!ꢃ#ꢈꢁ
ꢖꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕꢘꢎ1
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 399
PIC16F193X/LF193X
ꢀꢁꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇꢈ,3ꢊꢋꢉꢇꢈꢙꢅꢎꢎꢇ0ꢓꢐꢎꢊꢋꢄꢇꢕꢈꢈꢖꢇMꢇ.-ꢗꢘꢇꢙꢙꢇꢚꢛꢆꢌꢇꢜꢈꢈ0ꢍ
!ꢛꢐꢄ" 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
D
N
E
E1
1
2
b
NOTE 1
e
c
A2
A
φ
A1
L
L1
6ꢄꢃ&!
ꢔꢚ99ꢚꢔ.ꢙ.ꢝꢐ
ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢅ9ꢃ'ꢃ&!
ꢔꢚ7
7:ꢔ
ꢔꢗ;
7"')ꢈꢉꢅꢋ%ꢅꢂꢃꢄ!
ꢂꢃ&ꢌꢍ
7
ꢈ
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1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
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DS41364A-page 400
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
##ꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇ4,ꢊꢋꢇ%ꢓꢅꢆꢇ&ꢎꢅꢐ5ꢅꢑꢉꢇꢕꢍ4ꢖꢇMꢇ6ꢘ*6ꢘ*6ꢇꢙꢙꢇꢚꢛꢆꢌ'ꢇꢀ-ꢘꢘꢇꢙꢙꢇꢜ4%&ꢍ
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ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕꢜ?1
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 401
PIC16F193X/LF193X
##ꢂꢃꢄꢅꢆꢇꢍꢎꢅꢏꢐꢊꢑꢇ4,ꢊꢋꢇ%ꢓꢅꢆꢇ&ꢎꢅꢐ5ꢅꢑꢉꢇꢕꢍ4ꢖꢇMꢇ6ꢘ*6ꢘ*6ꢇꢙꢙꢇꢚꢛꢆꢌ'ꢇꢀ-ꢘꢘꢇꢙꢙꢇꢜ4%&ꢍ
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ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
DS41364A-page 402
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
APPENDIX A: DATA SHEET
REVISION HISTORY
APPENDIX B: MIGRATING FROM
OTHER PIC®
DEVICES
Revision A
This discusses some of the issues in migrating from
other PIC® devices to the PIC16F193X/LF193X family
of devices.
Original release (12/2008)
B.1
TABLE B-1:
Feature
PIC16F917 to PIC16F193X/LF193X
FEATURE COMPARISON
PIC16F917 PIC16F1937
Max. Operating Speed
20 MHz
8K
32 MHz
8K
Max. Program
Memory (Words)
Max. SRAM (Bytes)
A/D Resolution
368
512
10-bit
10-bit
Timers (8/16-bit)
Oscillator Modes
Brown-out Reset
Internal Pull-ups
Interrupt-on-change
Comparator
2/1
4/1
4
8
Y
Y
RB<7:0>
RB<7:0>
RB<7:4>
RB<7:0>
2
1/0
Y
2
0/1
Y
AUSART/EUSART
Extended WDT
Software Control
N
Y
Option of WDT/BOR
INTOSC Frequencies
30 kHz -
8 MHz
500 kHz -
32 MHz
Clock Switching
Capacitive Sensing
CCP/ECCP
Y
N
Y
Y
2/0
N
2/3
Y
Enhanced PIC16 CPU
MSSP/SSP
0/1
Y
1/0
Y
LCD
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 403
PIC16F193X/LF193X
NOTES:
DS41364A-page 404
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
INDEX
Digital-to-Analog Converter (DAC) ........................... 152
EUSART Receive..................................................... 214
EUSART Transmit.................................................... 213
External RC Mode .................................................... 111
Fail-Safe Clock Monitor (FSCM)............................... 119
Generic I/O Port.......................................................... 83
Interrupt Logic............................................................. 69
LCD Bias Voltage Generation .................................. 249
LCD Clock Generation.............................................. 248
MCLR Circuit .............................................................. 59
On-Chip Reset Circuit................................................. 57
Peripheral Interrupt Logic ........................................... 70
PIC16F193X/LF193X ................................................. 13
PWM (Enhanced) ..................................................... 195
Resonator Operation ................................................ 110
Timer0 ...................................................................... 157
Timer1 ...................................................................... 161
Timer1 Gate.............................................. 166, 167, 168
Timer2/4/6 ................................................................ 173
Voltage Reference.................................................... 155
Voltage Reference Output Buffer Example .............. 155
BORCON Register.............................................................. 63
BRA .................................................................................. 342
Break Character (12-bit) Transmit and Receive ............... 233
Brown-out Reset (BOR)...................................................... 62
Specifications ........................................................... 375
Timing and Characteristics....................................... 374
A
A/D
Specifications.................................................... 377, 378
Absolute Maximum Ratings .............................................. 355
AC Characteristics
Industrial and Extended ............................................ 370
Load Conditions........................................................ 369
ACKSTAT ......................................................................... 310
ACKSTAT Status Flag ...................................................... 310
ADC .................................................................................. 131
Acquisition Requirements ......................................... 140
Associated registers.................................................. 142
Block Diagram........................................................... 131
Calculating Acquisition Time..................................... 140
Channel Selection..................................................... 132
Configuration............................................................. 132
Configuring Interrupt ................................................. 136
Conversion Clock...................................................... 132
Conversion Procedure .............................................. 136
Internal Sampling Switch (RSS) Impedance.............. 140
Interrupts................................................................... 134
Operation .................................................................. 135
Operation During Sleep ............................................ 135
Port Configuration..................................................... 132
Reference Voltage (VREF)......................................... 132
Source Impedance.................................................... 140
Special Event Trigger................................................ 135
Starting an A/D Conversion ...................................... 134
ADCON0 Register....................................................... 36, 137
ADCON1 Register....................................................... 36, 138
ADDFSR ........................................................................... 341
ADDWFC .......................................................................... 341
ADRESH Register............................................................... 36
ADRESH Register (ADFM = 0)......................................... 138
ADRESH Register (ADFM = 1)......................................... 139
ADRESL Register (ADFM = 0).......................................... 139
ADRESL Register (ADFM = 1).......................................... 139
Alternate Pin Function......................................................... 84
Analog-to-Digital Converter. See ADC
C
C Compilers
MPLAB C18.............................................................. 352
MPLAB C30.............................................................. 352
CALL................................................................................. 343
CALLW ............................................................................. 343
Capacitive Sensing........................................................... 177
Associated registers w/ Capacitive Sensing............. 181
Specifications ........................................................... 387
Capture Module. See Enhanced Capture/Compare/
PWM(ECCP)
Capture/Compare/PWM ................................................... 183
Capture/Compare/PWM (CCP) ........................................ 185
Associated Registers w/ Capture ............................. 188
Associated Registers w/ Compare ........................... 190
Associated Registers w/ PWM ................................. 211
Capture Mode........................................................... 187
CCPx Pin Configuration............................................ 187
Clock Selection......................................................... 185
Compare Mode......................................................... 189
CCPx Pin Configuration.................................... 189
Software Interrupt Mode........................... 187, 189
Special Event Trigger....................................... 189
Timer1 Mode Selection............................. 187, 189
Prescaler .................................................................. 187
PWM Mode............................................................... 191
Duty Cycle ........................................................ 192
Effects of Reset................................................ 194
Example PWM Frequencies and
ANSELA Register ............................................................... 86
ANSELB Register ............................................................... 91
ANSELD Register ............................................................... 97
ANSELE Register ............................................................. 101
APFCON Register............................................................... 84
Assembler
MPASM Assembler................................................... 352
B
BAUDCON Register.......................................................... 224
BF ............................................................................. 310, 312
BF Status Flag .......................................................... 310, 312
Block Diagram
Capacitive Sensing ................................................... 177
Block Diagrams
(CCP) Capture Mode Operation ............................... 187
ADC .......................................................................... 131
ADC Transfer Function ............................................. 141
Analog Input Model........................................... 141, 147
CCP PWM................................................................. 191
Clock Source............................................................. 107
Comparator............................................................... 144
Compare ................................................................... 189
Crystal Operation...................................................... 110
Resolutions, 20 MHZ................................ 193
Example PWM Frequencies and
Resolutions, 32 MHZ................................ 193
Example PWM Frequencies and
Resolutions, 8 MHz .................................. 193
Operation in Sleep Mode.................................. 194
Resolution ........................................................ 193
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 405
PIC16F193X/LF193X
Setup for Operation...........................................194
System Clock Frequency Changes...................194
PWM Period..............................................................192
Setup for PWM Operation.........................................194
CCP1CON Register ...................................................... 40, 41
CCPR1H Register......................................................... 40, 41
CCPR1L Register.......................................................... 40, 41
CCPTMRS0 Register........................................................185
CCPTMRS1 Register........................................................186
CCPxAS Register..............................................................204
CCPxCON (ECCPx) Register ...........................................184
Clock Accuracy with Asynchronous Operation .................222
Clock Sources
External Modes.........................................................109
EC.....................................................................109
HS.....................................................................110
LP......................................................................110
OST...................................................................109
RC.....................................................................111
XT .....................................................................110
Internal Modes ..........................................................111
Frequency Selection .........................................115
HFINTOSC........................................................112
Internal Oscillator Clock Switch Timing.............115
INTOSC ............................................................111
INTOSCIO.........................................................111
LFINTOSC ........................................................112
MFINTOSC .......................................................112
Clock Switching.................................................................117
CMOUT Register...............................................................149
CMxCON0 Register ..........................................................148
CMxCON1 Register ..........................................................149
Code Examples
A/D Conversion.........................................................136
Changing Between Capture Prescalers....................187
Initializing PORTA.......................................................85
Initializing PORTB.......................................................89
Initializing PORTC.......................................................93
Initializing PORTD.......................................................96
Initializing PORTE.....................................................101
Write Verify ...............................................................332
Writing to Flash Program Memory ............................330
Comparator
Associated Registers ................................................150
Operation ..................................................................143
Comparator Module ..........................................................143
Cx Output State Versus Input Conditions .................145
Comparator Specifications................................................380
Comparator Voltage Reference (CVREF)
DACCON1 (Digital-to-Analog Converter Control 1)
Register .................................................................... 153
Data EEPROM Memory.................................................... 321
Associated Registers................................................ 332
Code Protection........................................................ 332
Reading .................................................................... 325
Writing ...................................................................... 325
Data Memory ...................................................................... 24
DC and AC Characteristics............................................... 389
DC Characteristics
Extended and Industrial............................................ 365
Industrial and Extended............................................ 358
Development Support....................................................... 351
Device Configuration ........................................................ 125
Code Protection........................................................ 129
Configuration Word................................................... 125
User ID ..................................................................... 129
Device Overview................................................................. 13
Digital-to-Analog Converter (DAC) ................................... 151
Associated Registers................................................ 154
Effects of a Reset ..................................................... 151
Operation During Sleep ............................................ 151
Specifications ........................................................... 380
E
ECCP/CCP. See Enhanced Capture/Compare/PWM
EEADR Registers ............................................................. 321
EEADRH Registers........................................................... 321
EEADRL Register............................................................. 322
EEADRL Registers ........................................................... 321
EECON1 Register..................................................... 321, 323
EECON2 Register..................................................... 321, 324
EEDATH Register............................................................. 322
EEDATL Register ............................................................. 322
EEPROM Data Memory
Avoiding Spurious Write ........................................... 332
Write Verify............................................................... 332
Effects of Reset
PWM mode............................................................... 194
Electrical Specifications.................................................... 355
Enhanced Capture/Compare/PWM
Timer Resources ...................................................... 184
Enhanced Capture/Compare/PWM (ECCP)..................... 184
Enhanced PWM Mode.............................................. 195
Auto-Restart ..................................................... 205
Auto-shutdown.................................................. 203
Direction Change in Full-Bridge Output Mode.. 201
Full-Bridge Application...................................... 199
Full-Bridge Mode .............................................. 199
Half-Bridge Application..................................... 198
Half-Bridge Application Examples .................... 206
Half-Bridge Mode.............................................. 198
Output Relationships (Active-High and
Associated Registers ................................................156
Comparators
C2OUT as T1 Gate ...................................................163
Compare Module. See Enhanced Capture/
Active-Low)............................................... 196
Compare/PWM (ECCP)
Output Relationships Diagram.......................... 197
Programmable Dead Band Delay..................... 206
Shoot-through Current...................................... 206
Start-up Considerations.................................... 203
Specifications ........................................................... 377
Enhanced Mid-range CPU.................................................. 14
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) .............................. 213
Errata.................................................................................. 11
EUSART ........................................................................... 213
Associated Registers
CONFIG1 Register............................................................126
CONFIG2 Register............................................................128
Core Registers ....................................................................49
CPSCON0 Register ..........................................................180
CPSCON1 Register ..........................................................181
Customer Change Notification Service .............................413
Customer Notification Service...........................................413
Customer Support.............................................................413
D
DACCON0 (Digital-to-Analog Converter Control 0) Register..
153
Baud Rate Generator ....................................... 226
DS41364A-page 406
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
Asynchronous Mode ................................................. 215
12-bit Break Transmit and Receive .................. 233
Associated Registers
Sleep Operation........................................................ 315
Stop Condition Timing .............................................. 314
INDF Register35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 47, 48
Indirect Addressing, INDF and FSR Registers ................... 53
Instruction Format............................................................. 338
Instruction Set................................................................... 337
ADDLW..................................................................... 341
ADDWF .................................................................... 341
ADDWFC.................................................................. 341
ANDLW..................................................................... 341
ANDWF .................................................................... 341
BRA .......................................................................... 342
CALL......................................................................... 343
CALLW ..................................................................... 343
LSLF......................................................................... 345
LSRF ........................................................................ 345
MOVF ....................................................................... 345
MOVIW..................................................................... 346
MOVLB..................................................................... 346
MOVWI..................................................................... 347
OPTION.................................................................... 347
RESET...................................................................... 347
SUBWFB .................................................................. 349
TRIS ......................................................................... 350
BCF .......................................................................... 342
BSF........................................................................... 342
BTFSC...................................................................... 342
BTFSS...................................................................... 342
CALL......................................................................... 343
CLRF ........................................................................ 343
CLRW....................................................................... 343
CLRWDT .................................................................. 343
COMF....................................................................... 343
DECF........................................................................ 343
DECFSZ ................................................................... 344
GOTO....................................................................... 344
INCF ......................................................................... 344
INCFSZ..................................................................... 344
IORLW...................................................................... 344
IORWF...................................................................... 344
MOVLW.................................................................... 346
MOVWF.................................................................... 346
NOP.......................................................................... 347
RETFIE..................................................................... 348
RETLW..................................................................... 348
RETURN................................................................... 348
RLF........................................................................... 348
RRF .......................................................................... 349
SLEEP...................................................................... 349
SUBLW..................................................................... 349
SUBWF..................................................................... 349
SWAPF..................................................................... 350
XORLW .................................................................... 350
XORWF .................................................................... 350
INTCON Register................................................................ 73
Internal Oscillator Block
Receive..................................................... 221
Transmit.................................................... 217
Auto-Wake-up on Break ................................... 231
Baud Rate Generator (BRG) ............................ 225
Clock Accuracy................................................. 222
Receiver............................................................ 218
Setting up 9-bit Mode with Address Detect....... 220
Transmitter........................................................ 215
Baud Rate Generator (BRG)
Auto Baud Rate Detect..................................... 230
Baud Rate Error, Calculating ............................ 225
Baud Rates, Asynchronous Modes .................. 227
Formulas........................................................... 226
High Baud Rate Select (BRGH Bit) .................. 225
Synchronous Master Mode............................... 234, 238
Associated Registers
Receive..................................................... 237
Transmit.................................................... 235
Reception.......................................................... 236
Transmission .................................................... 234
Synchronous Slave Mode
Associated Registers
Receive..................................................... 239
Transmit.................................................... 238
Reception.......................................................... 239
Transmission .................................................... 238
Extended Instruction Set
ADDFSR ................................................................... 341
F
Fail-Safe Clock Monitor..................................................... 119
Fail-Safe Condition Clearing..................................... 119
Fail-Safe Detection ................................................... 119
Fail-Safe Operation................................................... 119
Reset or Wake-up from Sleep................................... 119
Firmware Instructions........................................................ 337
Fixed Voltage Reference (FVR)
Specifications............................................................ 380
Flash Program Memory .................................................... 321
Erasing...................................................................... 328
Writing....................................................................... 328
FSR Register35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 47, 48
FVRCON (Fixed Voltage Reference Control) Register..... 156
I
2
I C Mode (MSSP)
Acknowledge Sequence Timing................................ 314
Bus Collision
During a Repeated Start Condition................... 318
During a Stop Condition.................................... 319
Effects of a Reset...................................................... 315
2
I C Clock Rate w/BRG.............................................. 320
Master Mode
Operation .......................................................... 306
Reception.......................................................... 312
Start Condition Timing .............................. 308, 309
Transmission .................................................... 310
Multi-Master Communication, Bus Collision
and Arbitration .................................................. 315
Multi-Master Mode .................................................... 315
Read/Write Bit Information (R/W Bit) ........................ 291
Slave Mode
INTOSC
Specifications ................................................... 371
Internal Sampling Switch (RSS) Impedance ..................... 140
Internet Address ............................................................... 413
Interrupt-On-Change......................................................... 103
Associated Registers................................................ 105
Interrupts ............................................................................ 69
ADC.......................................................................... 136
Associated registers w/ Interrupts .............................. 80
Transmission .................................................... 296
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 407
PIC16F193X/LF193X
TMR1 ........................................................................165
INTOSC Specifications .....................................................371
IOCBF Register.................................................................104
IOCBN Register ................................................................104
IOCBP Register.................................................................104
O
OPCODE Field Descriptions............................................. 337
OPTION............................................................................ 347
OPTION Register........................................................ 51, 159
OSCCON Register............................................................ 108
Oscillator
L
Associated Registers................................................ 120
Oscillator Module.............................................................. 107
EC............................................................................. 107
HFINTOSC ............................................................... 107
HS............................................................................. 107
INTOSC .................................................................... 107
LFINTOSC................................................................ 107
LP ............................................................................. 107
MFINTOSC............................................................... 107
RC ............................................................................ 107
XT ............................................................................. 107
Oscillator Parameters ....................................................... 371
Oscillator Specifications.................................................... 370
Oscillator Start-up Timer (OST)
Specifications ........................................................... 375
Oscillator Switching
Fail-Safe Clock Monitor ............................................ 119
Two-Speed Clock Start-up........................................ 117
OSCSTAT Register .......................................................... 113
OSCTUNE Register.......................................................... 114
LATA Register............................................................... 85, 93
LATB Register.....................................................................90
LATD Register.....................................................................96
LATE Register.....................................................................99
LCD
Associated Registers ................................................272
Bias Voltage Generation ................................... 249, 250
Clock Source Selection.............................................248
Configuring the Module.............................................271
Disabling the Module ................................................271
Frame Frequency......................................................254
Interrupts...................................................................267
LCDCON Register ....................................................241
LCDPS Register........................................................241
Multiplex Types.........................................................254
Operation During Sleep ............................................269
Pixel Control..............................................................254
Prescaler...................................................................248
Segment Enables......................................................254
Waveform Generation...............................................256
LCDCON Register..................................................... 241, 243
LCDCST Register .............................................................246
LCDDATAx Registers ............................................... 247, 252
LCDPS Register........................................................ 241, 244
LP Bits.......................................................................248
LCDREF Register .............................................................245
LCDRL Register................................................................252
LCDSEn Registers............................................................247
Liquid Crystal Display (LCD) Driver ..................................241
Load Conditions ................................................................369
LSLF..................................................................................345
LSRF.................................................................................345
P
P1A/P1B/P1C/P1D.See Enhanced Capture/
Compare/PWM (ECCP)............................................ 195
Packaging......................................................................... 391
Marking............................................................. 391, 392
PDIP Details ............................................................. 393
PCL and PCLATH............................................................... 52
PCL Register35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 47, 48
PCLATH Register35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 47,
48
PCON Register............................................................. 36, 65
PICSTART Plus Development Programmer..................... 354
PIE1 Register................................................................ 36, 74
PIE2 Register................................................................ 36, 75
PIE3 Register...................................................................... 76
Pin Diagram
M
Master Synchronous Serial Port. See MSSP
MCLR..................................................................................59
Internal ........................................................................59
Memory Organization..........................................................21
Data ............................................................................24
Program ......................................................................21
Microchip Internet Web Site..............................................413
Migrating from other PIC Microcontroller Devices.............403
MOVIW..............................................................................346
MOVLB..............................................................................346
MOVWI..............................................................................347
MPLAB ASM30 Assembler, Linker, Librarian ...................352
MPLAB ICD 2 In-Circuit Debugger....................................353
MPLAB ICE 2000 High-Performance Universal
PIC16F1933/1936/1938, PICLF1933/1936/1938,
28-pin PDIP/SOIC/SSOP ..................................... 3
PIC16F1933/1936/1938, PICLF1933/1936/1938,
28-pin QFN........................................................... 4
PICF1934/1937/1939, PICLF1934/1937/1939,
44-pin QFN........................................................... 7
PICF1934/1937/1939, PICLF1934/1937/1939,
44-pin TQFP......................................................... 8
PICF1934/1937/1939,PICLF1934/1937/1939,
40-pin PDIP .......................................................... 6
Pinout Descriptions
PIC16F193X/PIC16LF193X........................................ 15
PIR1 Register ............................................................... 35, 77
PIR2 Register ............................................................... 35, 78
PIR3 Register ..................................................................... 79
PORTA ............................................................................... 85
ANSELA Register ....................................................... 86
Associated Registers.................................................. 88
PORTA Register................................................... 35, 37
Specifications ........................................................... 373
PORTA Register................................................................. 85
PORTB ............................................................................... 89
In-Circuit Emulator ....................................................353
MPLAB Integrated Development Environment Software ..351
MPLAB PM3 Device Programmer.....................................353
MPLAB REAL ICE In-Circuit Emulator System.................353
MPLINK Object Linker/MPLIB Object Librarian ................352
MSSP................................................................................273
SSPBUF Register .....................................................283
SSPSR Register .......................................................283
DS41364A-page 408
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
Additional Pin Functions
ADCON0 (ADC Control 0)........................................ 137
ADCON1 (ADC Control 1)........................................ 138
ADRESH (ADC Result High) with ADFM = 0) .......... 138
ADRESH (ADC Result High) with ADFM = 1) .......... 139
ADRESL (ADC Result Low) with ADFM = 0)............ 139
ADRESL (ADC Result Low) with ADFM = 1)............ 139
ANSELA (PORTA Analog Select) .............................. 86
ANSELB (PORTB Analog Select) .............................. 91
ANSELD (PORTD Analog Select).............................. 97
ANSELE (PORTE Analog Select) ............................ 101
APFCON (Alternate Pin Function Control) ................. 84
BAUDCON (Baud Rate Control)............................... 224
BORCON Brown-out Reset Control) .......................... 63
CCPTMRS0 (CCP Timers Control 0) ....................... 185
CCPTMRS1 (CCP Timers Control 1) ....................... 186
CCPxAS (CCPx Auto-Shutdown Control) ................ 204
CCPxCON (ECCPx Control) .................................... 184
CMOUT (Comparator Output) .................................. 149
CMxCON0 (Cx Control)............................................ 148
CMxCON1 (Cx Control 1)......................................... 149
Configuration Word 1................................................ 126
Configuration Word 2................................................ 128
CPSCON0 (Capacitive Sensing Control Register 0) 180
CPSCON1 (Capacitive Sensing Control Register 1) 181
DACCON0................................................................ 153
DACCON1................................................................ 153
EEADRL (EEPROM Address).................................. 322
EECON1 (EEPROM Control 1) ................................ 323
EECON2 (EEPROM Control 2) ................................ 324
EEDATH (EEPROM Data) ....................................... 322
EEDATL (EEPROM Data)........................................ 322
FVRCON .................................................................. 156
INTCON (Interrupt Control) ........................................ 73
IOCBF (Interrupt-on-Change Flag)........................... 104
IOCBN (Interrupt-on-Change Negative Edge).......... 104
IOCBP (Interrupt-on-Change Positive Edge)............ 104
LATA (Data Latch PORTA) ........................................ 85
LATB (Data Latch PORTB) ........................................ 90
LATC (Data Latch PORTC)........................................ 93
LATD (Data Latch PORTD)........................................ 96
LATE (Data Latch PORTE) ........................................ 99
LCDCON (LCD Control) ........................................... 243
LCDCST (LCD Contrast Control) ............................. 246
LCDDATAx (LCD Data).................................... 247, 252
LCDPS (LCD Phase)................................................ 244
LCDREF (LCD Reference Voltage Control) ............. 245
LCDRL (LCD Reference Voltage Control)................ 252
LCDSEn (LCD Segment Enable) ............................. 247
OPTION_REG (OPTION)................................... 51, 159
OSCCON (Oscillator Control)................................... 108
OSCSTAT (Oscillator Status)................................... 113
OSCTUNE (Oscillator Tuning).................................. 114
PCON (Power Control Register)................................. 65
PCON (Power Control)............................................... 65
PIE1 (Peripheral Interrupt Enable 1) .......................... 74
PIE2 (Peripheral Interrupt Enable 2) .......................... 75
PIE3 (Peripheral Interrupt Enable 3) .......................... 76
PIR1 (Peripheral Interrupt Register 1)........................ 77
PIR2 (Peripheral Interrupt Request 2)........................ 78
PIR3 (Peripheral Interrupt Request 3)........................ 79
PORTA ....................................................................... 85
PORTB ....................................................................... 90
PORTC....................................................................... 93
PORTD....................................................................... 96
PORTE ....................................................................... 99
Weak Pull-up ...................................................... 89
ANSELB Register ....................................................... 91
Associated Registers .................................................. 92
Interrupt-on-Change.................................................... 89
P1B/P1C/P1D.See Enhanced Capture/
Compare/PWM+ (ECCP+).................................. 89
Pin Descriptions and Diagrams................................... 92
PORTB Register ................................................... 35, 37
PORTB Register ................................................................. 90
PORTC ............................................................................... 93
Associated Registers .................................................. 95
P1A.See Enhanced Capture/Compare/
PWM+ (ECCP+) ................................................. 93
Pin Descriptions and Diagrams................................... 95
PORTC Register................................................... 35, 37
Specifications............................................................ 373
PORTC Register................................................................. 93
PORTD ............................................................................... 96
Additional Pin Functions
ANSELD Register............................................... 97
Associated Registers .................................................. 98
P1B/P1C/P1D.See Enhanced Capture/
Compare/PWM+ (ECCP+).................................. 96
Pin Descriptions and Diagrams................................... 98
PORTD Register................................................... 35, 37
PORTD Register................................................................. 96
PORTE................................................................................ 99
ANSELE Register ..................................................... 101
Associated Registers ................................................ 102
Pin Descriptions and Diagrams................................. 102
PORTE Register ................................................... 35, 37
PORTE Register ................................................................. 99
Power-Down Mode (Sleep)............................................... 333
Associated Registers ................................................ 334
Power-on Reset .................................................................. 59
Power-up Time-out Sequence ............................................ 64
Power-up Timer (PWRT) .................................................... 59
Specifications............................................................ 375
PR2 Register................................................................. 35, 43
Precision Internal Oscillator Parameters........................... 371
Program Memory ................................................................ 21
Map and Stack (PIC16F1933/LF1933,
PIC16F1934/LF1934) ......................................... 22
Map and Stack (PIC16F1936/LF1936,
PIC16F1937/LF1937) ......................................... 22
Map and Stack (PIC16F1938/LF1938,
PIC16F1939/LF1939) ......................................... 23
Programming, Device Instructions .................................... 337
PSTRxCON Register ........................................................ 208
Pulse Steering................................................................... 208
PWM (ECCP Module)
Pulse Steering........................................................... 208
Steering Synchronization.......................................... 210
PWM Mode. See Enhanced Capture/Compare/PWM ...... 195
PWMxCON Register ......................................................... 207
R
RCREG............................................................................. 220
RCREG Register................................................................. 38
RCSTA Register ......................................................... 38, 223
Reader Response............................................................. 414
Read-Modify-Write Operations ......................................... 337
Register
RCREG Register....................................................... 230
Registers
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 409
PIC16F193X/LF193X
PSTRxCON (Pulse Steering Control) .......................208
PWMxCON (Enhanced PWM Control) .....................207
RCSTA (Receive Status and Control).......................223
Special Function, Summary........................................35
SRCON0 (SR Latch Control 0) .................................122
SRCON1 (SR Latch Control 1) .................................123
SSPADD (MSSP Address and Baud Rate,
SSPOV ............................................................................. 312
SSPOV Status Flag .......................................................... 312
SSPSTAT Register..................................................... 39, 276
R/W Bit ..................................................................... 291
Stack................................................................................... 52
Accessing ................................................................... 53
Reset .......................................................................... 53
Stack Overflow/Underflow .................................................. 64
STATUS Register ............................................................... 50
SUBWFB .......................................................................... 349
2
I C Mode)..........................................................280
SSPCON1 (MSSP Control 1)....................................277
SSPCON2 (SSP Control 2).......................................278
SSPCON3 (SSP Control 3).......................................279
SSPMSK (SSP Mask)...............................................280
SSPSTAT (SSP Status)............................................276
STATUS......................................................................50
T1CON (Timer1 Control)...........................................169
T1GCON (Timer1 Gate Control)...............................170
TRISA (Tri-State PORTA)...........................................86
TRISB (Tri-State PORTB)...........................................91
TRISC (Tri-State PORTC) ..........................................94
TRISD (Tri-State PORTD) ..........................................97
TRISE (Tri-State PORTE).........................................101
TxCON ......................................................................175
TXSTA (Transmit Status and Control) ......................222
WDTCON (Watchdog Timer Control)..........................61
WPUB (Weak Pull-up PORTB)...................................90
RESET ..............................................................................347
Reset...................................................................................57
Reset Instruction .................................................................64
Resets.................................................................................57
Associated Registers ..................................................68
Revision History ................................................................403
T
T1CON Register ......................................................... 35, 169
T1GCON Register ............................................................ 170
T2CON Register ........................................................... 35, 43
Thermal Considerations.................................................... 368
Timer0............................................................................... 157
Associated Registers................................................ 159
Operation.................................................................. 157
Specifications ........................................................... 376
Timer1............................................................................... 161
Associated registers ................................................. 171
Asynchronous Counter Mode ................................... 163
Reading and Writing......................................... 163
Clock Source Selection............................................. 162
Interrupt .................................................................... 165
Operation.................................................................. 162
Operation During Sleep ............................................ 165
Oscillator................................................................... 163
Prescaler .................................................................. 163
Specifications ........................................................... 376
Timer1 Gate
S
Selecting Source .............................................. 163
TMR1H Register....................................................... 161
TMR1L Register........................................................ 161
Timer2
Associated registers ................................................. 176
Timer2/4/6......................................................................... 173
Associated registers ................................................. 176
Timers
SCK...................................................................................281
SDI ....................................................................................281
SDO ..................................................................................281
Serial Clock, SCK..............................................................281
Serial Data In (SDI)...........................................................281
Serial Data Out (SDO) ......................................................281
Shoot-through Current ......................................................206
Slave Select (SS)..............................................................281
Software Simulator (MPLAB SIM).....................................352
SPBRG..............................................................................225
SPBRG Register ........................................................... 37, 38
SPBRGH...........................................................................225
Special Event Trigger........................................................135
Special Function Registers (SFRs).....................................35
SPI Mode (MSSP)
Associated Registers ................................................286
Serial Clock...............................................................281
Serial Data In ............................................................281
Serial Data Out .........................................................281
Slave Select..............................................................281
SPI Clock ..................................................................283
Typical Connection ...................................................282
SR Latch ...........................................................................121
SRCON0 Register.............................................................122
SRCON1 Register.............................................................123
SS .....................................................................................281
SSPADD Register....................................................... 39, 280
SSPBUF Register ...............................................................39
SSPCON 1 Register..........................................................277
SSPCON Register...............................................................39
SSPCON2 Register...........................................................278
SSPCON3 Register...........................................................279
SSPMSK Register.............................................................280
Timer1
T1CON ............................................................. 169
T1GCON........................................................... 170
Timer2/4/6
TxCON.............................................................. 175
Timing Diagrams
A/D Conversion......................................................... 378
A/D Conversion (Sleep Mode).................................. 379
Acknowledge Sequence ........................................... 314
Asynchronous Reception.......................................... 220
Asynchronous Transmission..................................... 216
Asynchronous Transmission (Back to Back) ............ 216
Auto Wake-up Bit (WUE) During Normal Operation. 232
Auto Wake-up Bit (WUE) During Sleep .................... 232
Automatic Baud Rate Calibration.............................. 230
Baud Rate Generator with Clock Arbitration............. 307
BRG Reset Due to SDA Arbitration During
Start Condition.................................................. 317
Brown-out Reset (BOR)............................................ 374
Brown-out Reset Situations ........................................ 62
Bus Collision During a Repeated Start Condition
(Case 1)........................................................... 318
Bus Collision During a Repeated Start Condition
(Case 2)........................................................... 318
Bus Collision During a Start Condition (SCL = 0)..... 317
Bus Collision During a Stop Condition (Case 1)....... 319
DS41364A-page 410
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
Bus Collision During a Stop Condition (Case 2) ....... 319
Bus Collision During Start Condition (SDA only) ...... 316
Bus Collision for Transmit and Acknowledge............ 315
CLKOUT and I/O....................................................... 372
Clock Synchronization .............................................. 304
Clock Timing ............................................................. 370
Comparator Output ................................................... 143
Enhanced Capture/Compare/PWM (ECCP)............. 377
Fail-Safe Clock Monitor (FSCM)............................... 120
First Start Bit Timing ................................................. 308
Full-Bridge PWM Output........................................... 200
Half-Bridge PWM Output .................................. 198, 206
TMR0 Register.................................................................... 35
TMR1H Register................................................................. 35
TMR1L Register.................................................................. 35
TMR2 Register.............................................................. 35, 43
TRIS ................................................................................. 350
TRISA Register............................................................. 36, 86
TRISB ................................................................................. 89
TRISB Register............................................................. 36, 91
TRISC................................................................................. 93
TRISC Register............................................................. 36, 94
TRISD................................................................................. 96
TRISD Register............................................................. 36, 97
TRISE ................................................................................. 99
TRISE Register........................................................... 36, 101
Two-Speed Clock Start-up Mode...................................... 117
TXCON (Timer2/4/6) Register .......................................... 175
TxCON Register ............................................................... 211
TXREG ............................................................................. 215
TXREG Register................................................................. 38
TXSTA Register.......................................................... 38, 222
BRGH Bit.................................................................. 225
2
I C Bus Data............................................................. 385
2
I C Bus Start/Stop Bits.............................................. 384
2
I C Master Mode (7 or 10-Bit Transmission) ............ 311
2
I C Master Mode (7-Bit Reception)........................... 313
2
I C Stop Condition Receive or Transmit Mode......... 314
INT Pin Interrupt.......................................................... 71
Internal Oscillator Switch Timing............................... 116
LCD Interrupt Timing in Quarter-Duty Cycle Drive.... 268
LCD Sleep Entry/Exit when SLPEN = 1 or CS = 00 . 270
PWM Auto-shutdown ................................................ 205
Firmware Restart .............................................. 205
PWM Direction Change ............................................ 201
PWM Direction Change at Near 100% Duty Cycle... 202
PWM Output (Active-High)........................................ 196
PWM Output (Active-Low) ........................................ 197
Repeat Start Condition.............................................. 309
Reset, WDT, OST and Power-up Timer ................... 373
Send Break Character Sequence ............................. 233
SPI Master Mode (CKE = 1, SMP = 1) ..................... 382
SPI Mode (Master Mode).......................................... 283
SPI Slave Mode (CKE = 0) ....................................... 383
SPI Slave Mode (CKE = 1) ....................................... 383
Synchronous Reception (Master Mode, SREN) ....... 237
Synchronous Transmission....................................... 235
Synchronous Transmission (Through TXEN) ........... 235
Time-out Sequence
U
USART
Synchronous Master Mode
Requirements, Synchronous Receive .............. 381
Requirements, Synchronous Transmission...... 381
Timing Diagram, Synchronous Receive ........... 381
Timing Diagram, Synchronous Transmission... 381
V
VREF. SEE ADC Reference Voltage
W
Wake-up on Break............................................................ 231
Wake-up Using Interrupts................................................. 334
Watchdog Timer (WDT)...................................................... 59
Clock Source .............................................................. 59
Modes......................................................................... 60
Period ......................................................................... 59
Specifications ........................................................... 375
WCOL....................................................... 307, 310, 312, 314
WCOL Status Flag.................................... 307, 310, 312, 314
WDTCON Register ............................................................. 61
WPUB Register................................................................... 90
WWW Address ................................................................. 413
WWW, On-Line Support ..................................................... 11
Case 1 ................................................................ 66
Case 2 ................................................................ 67
Case 3 ................................................................ 67
Timer0 and Timer1 External Clock ........................... 376
Timer1 Incrementing Edge........................................ 165
Two Speed Start-up.................................................. 118
Type-A in 1/2 Mux, 1/2 Bias Drive ............................ 257
Type-A in 1/2 Mux, 1/3 Bias Drive ............................ 259
Type-A in 1/3 Mux, 1/2 Bias Drive ............................ 261
Type-A in 1/3 Mux, 1/3 Bias Drive ............................ 263
Type-A in 1/4 Mux, 1/3 Bias Drive ............................ 265
Type-A/Type-B in Static Drive................................... 256
Type-B in 1/2 Mux, 1/2 Bias Drive ............................ 258
Type-B in 1/2 Mux, 1/3 Bias Drive ............................ 260
Type-B in 1/3 Mux, 1/2 Bias Drive ............................ 262
Type-B in 1/3 Mux, 1/3 Bias Drive ............................ 264
Type-B in 1/4 Mux, 1/3 Bias Drive ............................ 266
USART Synchronous Receive (Master/Slave) ......... 381
USART Synchronous Transmission (Master/Slave). 381
Wake-up from Interrupt............................................. 334
Timing Diagrams and Specifications
PLL Clock.................................................................. 371
Timing Parameter Symbology........................................... 369
Timing Requirements
2
I C Bus Data............................................................. 386
I2C Bus Start/Stop Bits ............................................. 385
SPI Mode .................................................................. 384
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 411
PIC16F193X/LF193X
NOTES:
DS41364A-page 412
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 413
PIC16F193X/LF193X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
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FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
PIC16F193X/LF193X
DS41364A
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41364A-page 414
Preliminary
© 2008 Microchip Technology Inc.
PIC16F193X/LF193X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
b)
PIC16LF1937 - I/P = Industrial temp., Plastic
DIP package, low-voltage VDD limits.
PIC16F1934 - I/PT = Industrial temp., TQFP
package, standard VDD limits.
c)
PIC16F1933 - E/ML = Extended temp., QFN
package, standard VDD limits.
Device:
PIC16F1933, PIC16LF1933, PIC16F1933T, PIC16LF1933T(1)
PIC16F1934, PIC16LF1934, PIC16F1934T, PIC16LF1934T(1)
PIC16F1936, PIC16LF1936, PIC16F1936T, PIC16LF1936T(1)
PIC16F1937, PIC16LF1937, PIC16F1937T, PIC16LF1937T(1)
PIC16F1938, PIC16LF1938, PIC16F1938T, PIC16LF1938T(1)
PIC16F1939, PIC16LF1939, PIC16F1939T, PIC16LF1939T(1)
Temperature
Range:
I
E
=
=
-40°C to +85°C
-40°C to +125°C
Package:
ML
P
PT
SO
SP
SS
=
=
=
=
=
=
Micro Lead Frame (QFN)
Plastic DIP
TQFP (Thin Quad Flatpack)
SOIC
Skinny Plastic DIP
SSOP
Note 1:
2:
F
LF
T
=
=
=
Standard Voltage Range
Low Voltage Range
In tape and reel for QFN, TQFP,
SOIC and SSOP packages only.
Pattern:
3-Digit Pattern Code for QTP (blank otherwise)
© 2008 Microchip Technology Inc.
Preliminary
DS41364A-page 415
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
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Tel: 852-2401-1200
Fax: 852-2401-3431
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Fax: 91-80-4182-8422
Austria - Wels
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Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
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Fax: 61-2-9868-6755
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Tel: 49-89-627-144-0
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Japan - Yokohama
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Fax: 852-2401-3431
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
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Dallas
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Fax: 63-2-634-9069
Kokomo
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Fax: 765-864-8387
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Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
01/02/08
DS41364A-page 416
Preliminary
© 2008 Microchip Technology Inc.
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