PIC16F508-I/MC_技术文档

PIC12F508/509/16F505

Data Sheet

8/14-Pin, 8-Bit Flash Microcontrollers

DS41236E

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

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Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

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Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

rfPIC and UNI/O are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

32

PICtail, PIC logo, REAL ICE, rfLAB, Select Mode, Total

Endurance, TSHARC, UniWinDriver, WiperLock and ZENA

are trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS41236E-page 2

PIC12F508/509/16F505

8/14-Pin, 8-Bit Flash Microcontrollers

Devices Included In This Data Sheet:

Low-Power Features/CMOS Technology:

• Operating Current:

• PIC12F508

• PIC12F509

• PIC16F505

- < 175 μA @ 2V, 4 MHz, typical

• Standby Current:

High-Performance RISC CPU:

- 100 nA @ 2V, typical

• Only 33 Single-Word Instructions to Learn

• Low-Power, High-Speed Flash Technology:

- 100,000 Flash endurance

- > 40 year retention

• All Single-Cycle Instructions Except for Program

Branches, which are Two-Cycle

• 12-Bit Wide Instructions

• Fully Static Design

• 2-Level Deep Hardware Stack

• Wide Operating Voltage Range: 2.0V to 5.5V

• Wide Temperature Range:

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

• Direct, Indirect and Relative Addressing modes

for Data and Instructions

• 8-Bit Wide Data Path

• 8 Special Function Hardware Registers

• Operating Speed:

Peripheral Features (PIC12F508/509):

- DC – 20 MHz clock input (PIC16F505 only)

- DC – 200 ns instruction cycle (PIC16F505

only)

• 6 I/O Pins:

- 5 I/O pins with individual direction control

- 1 input only pin

- DC – 4 MHz clock input

- DC – 1000 ns instruction cycle

- High current sink/source for direct LED drive

- Wake-on-change

Special Microcontroller Features:

- Weak pull-ups

• 4 MHz Precision Internal Oscillator:

- Factory calibrated to ±1%

• 8-Bit Real-Time Clock/Counter (TMR0) with 8-Bit

Programmable Prescaler

• In-Circuit Serial Programming™ (ICSP™)

• In-Circuit Debugging (ICD) Support

• Power-On Reset (POR)

Peripheral Features (PIC16F505):

• 12 I/O Pins:

• Device Reset Timer (DRT)

- 11 I/O pins with individual direction control

- 1 input only pin

• Watchdog Timer (WDT) with Dedicated On-Chip

RC Oscillator for Reliable Operation

- High current sink/source for direct LED drive

- Wake-on-change

• Programmable Code Protection

• Multiplexed MCLR Input Pin

- Weak pull-ups

• Internal Weak Pull-Ups on I/O Pins

• Power-Saving Sleep mode

• 8-Bit Real-Time Clock/Counter (TMR0) with 8-Bit

Programmable Prescaler

• Wake-Wp from Sleep on Pin Change

• Selectable Oscillator Options:

- INTRC: 4 MHz precision Internal oscillator

- EXTRC: External low-cost RC oscillator

- XT:

- HS:

Standard crystal/resonator

High-speed crystal/resonator

(PIC16F505 only)

- LP:

- EC:

Power-saving, low-frequency crystal

High-speed external clock input

(PIC16F505 only)

DS41236E-page 3

PIC12F508/509/16F505

Pin Diagrams

PDIP, SOIC, TSSOP

PDIP, SOIC, MSOP

14

13

12

VDD

RB5/OSC1/CLKIN

RB4/OSC2/CLKOUT

VSS

1

2

3

8

7

6

5

VDD

GP5/OSC1/CLKIN

GP4/OSC2

VSS

1

2

3

4

RB0/ICSPDAT

RB1/ICSPCLK

GP0/ICSPDAT

GP1/ICSPCLK

GP2/T0CKI

RB3/MCLR/VPP

RC5/T0CKI

4

5

11

10

RB2

RC0

GP3/MCLR/VPP

6

7

9

8

RC4

RC3

RC1

RC2

DFN

VDD

1

2

3

4

8

7

6

5

VSS

GP0/ICSPDAT

GP1/ICSPCLK

GP2/T0CKI

GP5/OSC1/CLKIN

GP4/OSC2

GP3/MCLR/VPP

PIC16F505 16-Pin Diagram (QFN)

RB5/OSC1/CLKIN

RB4/OSC2/CLKOUT

RB3/MCLR/VPP

RC5/TOCKI

RB0/ICSPDAT

RB1/ICSPCLK

RB2

12

11

1

2

3

4

PIC16F505

10

9

RC0

DS41236E-page 4

PIC12F508/509/16F505

Program Memory

Flash (words)

Data Memory

Timers

Device

PIC12F508

I/O

8-bit

SRAM (bytes)

512

1024

25

41

72

6

1

PIC12F509

PIC16F505

12

DS41236E-page 5

PIC12F508/509/16F505

Table of Contents

1.0 General Description...................................................................................................................................................................... 7

2.0 PIC12F508/509/16F505 Device Varieties ................................................................................................................................... 9

3.0 Architectural Overview ............................................................................................................................................................... 11

4.0 Memory Organization................................................................................................................................................................. 17

5.0 I/O Port....................................................................................................................................................................................... 31

6.0 Timer0 Module and TMR0 Register ........................................................................................................................................... 35

7.0 Special Features Of The CPU.................................................................................................................................................... 41

8.0 Instruction Set Summary............................................................................................................................................................ 57

9.0 Development Support................................................................................................................................................................. 65

10.0 Electrical Characteristics ............................................................................................................................................................ 69

11.0 DC and AC Characteristics Graphs and Charts......................................................................................................................... 81

12.0 Packaging Information................................................................................................................................................................ 91

Index .................................................................................................................................................................................................. 105

The Microchip Web Site..................................................................................................................................................................... 107

Customer Change Notification Service .............................................................................................................................................. 107

Customer Support.............................................................................................................................................................................. 107

Reader Response .............................................................................................................................................................................. 108

Product Identification System............................................................................................................................................................. 109

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DS41236E-page 6

PIC12F508/509/16F505

1.1

Applications

1.0

GENERAL DESCRIPTION

The PIC12F508/509/16F505 devices fit in applications

ranging from personal care appliances and security

systems to low-power remote transmitters/receivers.

The Flash technology makes customizing application

programs (transmitter codes, appliance settings,

receiver frequencies, etc.) extremely fast and conve-

nient. The small footprint packages, for through hole or

surface mounting, make these microcontrollers perfect

for applications with space limitations. Low cost, low

power, high performance, ease-of-use and I/O flexibil-

ity make the PIC12F508/509/16F505 devices very ver-

satile even in areas where no microcontroller use has

been considered before (e.g., timer functions, logic and

PLDs in larger systems and coprocessor applications).

The PIC12F508/509/16F505 devices from Microchip

Technology are low-cost, high-performance, 8-bit,

fully-static, Flash-based CMOS microcontrollers. They

employ a RISC architecture with only 33 single-word/

single-cycle instructions. All instructions are single

cycle (200 μs) except for program branches, which

take two cycles. The PIC12F508/509/16F505 devices

deliver performance an order of magnitude higher than

their competitors in the same price category. The 12-bit

wide instructions are highly symmetrical, resulting in a

typical 2:1 code compression over other 8-bit

microcontrollers in its class. The easy to use and easy

to remember instruction set reduces development time

significantly.

The PIC12F508/509/16F505 products are equipped

with special features that reduce system cost and

power requirements. The Power-on Reset (POR) and

Device Reset Timer (DRT) eliminate the need for exter-

nal Reset circuitry. There are four oscillator configura-

tions to choose from (six on the PIC16F505), including

INTRC Internal Oscillator mode and the power-saving

LP (Low-Power) Oscillator mode. Power-Saving Sleep

mode, Watchdog Timer and code protection features

improve system cost, power and reliability.

The PIC12F508/509/16F505 devices are available in

the cost-effective Flash programmable version, which

is suitable for production in any volume. The customer

can take full advantage of Microchip’s price leadership

in Flash programmable microcontrollers, while

benefiting from the Flash programmable flexibility.

The PIC12F508/509/16F505 products are supported

by a full-featured macro assembler, a software simula-

tor, an in-circuit emulator, a ‘C’ compiler, a low-cost

development programmer and a full featured program-

mer. All the tools are supported on IBM^®PC and

compatible machines.

TABLE 1-1:

PIC12F508/509/16F505 DEVICES

PIC12F508

PIC12F509

PIC16F505

Clock

Maximum Frequency of Operation (MHz)

Flash Program Memory (words)

Data Memory (bytes)

Timer Module(s)

4

512

25

4

1024

41

20

1024

72

Memory

Peripherals

Features

TMR0

Yes

5

TMR0

Yes

5

TMR0

Yes

11

Wake-up from Sleep on Pin Change

I/O Pins

Input Pins

1

Internal Pull-ups

Yes

33

Yes

33

Yes

33

In-Circuit Serial Programming

Number of Instructions

Packages

8-pin PDIP, SOIC,

MSOP, DFN

8-pin PDIP, SOIC,

MSOP, DFN

14-pin PDIP, SOIC,

TSSOP

The PIC12F508/509/16F505 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current

capability and precision internal oscillator.

The PIC12F508/509/16F505 devices use serial programming with data pin RB0/GP0 and clock pin RB1/GP1.

DS41236E-page 7

PIC12F508/509/16F505

NOTES:

DS41236E-page 8

PIC12F508/509/16F505

2.2

Serialized Quick Turn

Programming^SM(SQTP^SM) Devices

2.0

PIC12F508/509/16F505 DEVICE

VARIETIES

Microchip offers a unique programming service, where

a few user-defined locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or

sequential.

A variety of packaging options are available. Depend-

ing on application and production requirements, the

proper device option can be selected using the

information in this section. When placing orders, please

use the PIC12F508/509/16F505 Product Identification

System at the back of this data sheet to specify the

correct part number.

Serial programming allows each device to have a

unique number, which can serve as an entry code,

password or ID number.

2.1

Quick Turn Programming (QTP)

Devices

Microchip offers a QTP programming service for

factory production orders. This service is made

available for users who choose not to program

medium-to-high quantity units and whose code

patterns have stabilized. The devices are identical to

the Flash devices but with all Flash locations and fuse

options already programmed by the factory. Certain

code and prototype verification procedures do apply

before production shipments are available. Please

contact your local Microchip Technology sales office for

more details.

DS41236E-page 9

PIC12F508/509/16F505

NOTES:

DS41236E-page 10

PIC12F508/509/16F505

The PIC12F508/509/16F505 devices contain an 8-bit

ALU and working register. The ALU is a general

purpose arithmetic unit. It performs arithmetic and

Boolean functions between data in the working register

and any register file.

3.0

ARCHITECTURAL OVERVIEW

The high performance of the PIC12F508/509/16F505

devices can be attributed to a number of architectural

features commonly found in RISC microprocessors.

To begin with, the PIC12F508/509/16F505 devices

use a Harvard architecture in which program and data

are accessed on separate buses. This improves

bandwidth over traditional von Neumann architec-

tures where program and data are fetched on the

same bus. Separating program and data memory fur-

ther allows instructions to be sized differently than the

8-bit wide data word. Instruction opcodes are 12 bits

wide, making it possible to have all single-word

instructions. A 12-bit wide program memory access

bus fetches a 12-bit instruction in a single cycle. A

two-stage pipeline overlaps fetch and execution of

instructions. Consequently, all instructions (33)

execute in a single cycle (200 ns @ 20 MHz, 1 μs @

4 MHz) except for program branches.

The ALU is 8 bits wide and capable of addition, sub-

traction, shift and logical operations. Unless otherwise

mentioned, arithmetic operations are two’s comple-

ment in nature. In two-operand instructions, one

operand is typically the W (working) register. The other

operand is either a file register or an immediate

constant. In single operand instructions, the operand is

either the W register or a file register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC) and

Zero (Z) bits in the STATUS register. The C and DC bits

operate as a borrow and digit borrow out bit, respec-

tively, in subtraction. See the SUBWF and ADDWF

instructions for examples.

Table 3-1 below lists program memory (Flash) and data

memory (RAM) for the PIC12F508/509/16F505

devices.

Simplified block diagrams are shown in Figure 3-1 and

Figure 3-2, with the corresponding pin described in

Table 3-2 and Table 3-3.

TABLE 3-1:

PIC12F508/509/16F505

MEMORY

Memory

Device

Program

Data

PIC12F508

PIC12F509

PIC16F505

512 x 12

1024 x 12

25 x 8

41 x 8

72 x 8

The PIC12F508/509/16F505 devices can directly or

indirectly address its register files and data memory. All

Special Function Registers (SFR), including the PC,

are mapped in the data memory. The PIC12F508/509/

16F505 devices have a highly orthogonal (symmetri-

cal) instruction set that makes it possible to carry out

any operation, on any register, using any addressing

mode. This symmetrical nature and lack of “special

optimal situations” make programming with the

PIC12F508/509/16F505 devices simple, yet efficient.

In addition, the learning curve is reduced significantly.

DS41236E-page 11

PIC12F508/509/16F505

FIGURE 3-1:

PIC12F508/509 BLOCK DIAGRAM

12

8

GPIO

Data Bus

Program Counter

Flash

GP0/ISCPDAT

GP1/ISCPCLK

GP2/T0CKI

GP3/MCLR/VPP

GP4/OSC2

512 x 12 or

1024 x 12

RAM

Program

Memory

25 x 8 or

Stack 1

Stack 2

File

Registers

GP5/OSC1/CLKIN

Program

Bus

12

RAM Addr

9

Addr MUX

Instruction Reg

Indirect

Addr

5

Direct Addr

5-7

FSR Reg

Status Reg

8

3

MUX

Device Reset

Timer

Instruction

Decode and

Control

ALU

Power-on

Reset

8

Timing

Generation

Watchdog

Timer

OSC1/CLKIN

OSC2

W Reg

Internal RC

OSC

Timer0

MCLR

VDD, VSS

DS41236E-page 12

PIC12F508/509/16F505

TABLE 3-2:

Name

PIC12F508/509 PINOUT DESCRIPTION

Input Output

Function

Description

Type

GP0/ICSPDAT

GP0

TTL

CMOS Bidirectional I/O pin. Can be software programmed for internal

weak pull-up and wake-up from Sleep on pin change.

ICSPDAT

GP1

ST

CMOS In-Circuit Serial Programming™ data pin.

GP1/ICSPCLK

TTL

CMOS Bidirectional I/O pin. Can be software programmed for internal

weak pull-up and wake-up from Sleep on pin change.

ICSPCLK

GP2

ST

TTL

ST

CMOS In-Circuit Serial Programming clock pin.

CMOS Bidirectional I/O pin.

GP2/T0CKI

T0CKI

GP3

—

Clock input to TMR0.

GP3/MCLR/VPP

TTL

Input pin. Can be software programmed for internal weak

pull-up and wake-up from Sleep on pin change.

MCLR

ST

—

Master Clear (Reset). When configured as MCLR, this pin is

an active-low Reset to the device. Voltage on MCLR/VPP must

not exceed VDD during normal device operation or the device

will enter Programming mode. Weak pull-up always on if

configured as MCLR.

VPP

GP4

HV

TTL

—

Programming voltage input.

GP4/OSC2

CMOS Bidirectional I/O pin.

OSC2

XTAL Oscillator crystal output. Connections to crystal or resonator in

Crystal Oscillator mode (XT and LP modes only, GPIO in other

modes).

GP5/OSC1/CLKIN

GP5

OSC1

CLKIN

VDD

TTL

XTAL

ST

CMOS Bidirectional I/O pin.

—

P

Oscillator crystal input.

External clock source input.

VDD

VSS

—

Positive supply for logic and I/O pins.

Ground reference for logic and I/O pins.

VSS

—

P

Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,

ST = Schmitt Trigger input, HV = High Voltage

DS41236E-page 13

PIC12F508/509/16F505

FIGURE 3-2:

PIC16F505 BLOCK DIAGRAM

12

8

PORTB

Data Bus

RAM

Program Counter

RB0/ICSPCLK

RB1/ICSPDAT

RB2

Flash

1K x 12

Program

Stack 1

Memory

RB3/MCLR/VPP

RB4/OSC2/CLKOUT

RB5/OSC1/CLKIN

File

Stack 2

Registers

Program

Bus

12

RAM Addr

9

PORTC

Addr MUX

Instruction Reg

RC0

RC1

RC2

Indirect

Addr

5

Direct Addr

5-7

RC3

RC4

FSR Reg

RC5/T0CKI

Status Reg

8

3

MUX

Device Reset

Timer

Power-on

Reset

ALU

Instruction

Decode and

Control

8

Watchdog

Timer

W Reg

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

Internal RC

OSC

Timer0

MCLR

VDD, VSS

DS41236E-page 14

PIC12F508/509/16F505

TABLE 3-3:

Name

PIC16F505 PINOUT DESCRIPTION

Input Output

Function

Description

Type

RB0/ICSPDAT

RB0

TTL

CMOS Bidirectional I/O pin. Can be software programmed for internal

weak pull-up and wake-up from Sleep on pin change.

ICSPDAT

RB1

ST

CMOS In-Circuit Serial Programming™ data pin.

RB1/ICSPCLK

TTL

CMOS Bidirectional I/O pin. Can be software programmed for internal

weak pull-up and wake-up from Sleep on pin change.

ICSPCLK

RB2

ST

CMOS In-Circuit Serial Programming clock pin.

CMOS Bidirectional I/O pin.

RB2

TTL

RB3/MCLR/VPP

RB3

—

Input port. Can be software programmed for internal weak

pull-up and wake-up from Sleep on pin change.

MCLR

ST

—

Master Clear (Reset). When configured as MCLR, this pin is

an active-low Reset to the device. Voltage on MCLR/VPP must

not exceed VDD during normal device operation or the device

will enter Programming mode. Weak pull-up always on if

configured as MCLR.

VPP

HV

—

Programming voltage input.

RB4/OSC2/CLKOUT

RB4

TTL

CMOS Bidirectional I/O pin. Can be software programmed for internal

weak pull-up and wake-up from Sleep on pin change.

OSC2

—

XTAL Oscillator crystal output. Connections to crystal or resonator in

Crystal Oscillator mode (XT, HS and LP modes only).

CLKOUT

CMOS In EXTRC and INTRC modes, the pin output can be

configured for CLKOUT, which has 1/4 the frequency of OSC1

and denotes the instruction cycle rate.

RB5/OSC1/CLKIN

RB5

OSC1

CLKIN

RC0

TTL

XTAL

ST

CMOS Bidirectional I/O pin.

—

Crystal input.

External clock source input.

RC0

TTL

ST

CMOS Bidirectional I/O pin.

RC1

RC2

RC3

RC4

RC5/T0CKI

RC5

T0CKI

VDD

—

P

Clock input to TMR0.

VDD

VSS

—

Positive supply for logic and I/O pins.

Ground reference for logic and I/O pins.

VSS

—

P

Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,

ST = Schmitt Trigger input, HV = High Voltage

DS41236E-page 15

PIC12F508/509/16F505

3.1

Clocking Scheme/Instruction

Cycle

3.2

Instruction Flow/Pipelining

An instruction cycle consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle,

while decode and execute take another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the PC to change (e.g., GOTO), then two cycles

are required to complete the instruction (Example 3-1).

The clock input (OSC1/CLKIN pin) is internally divided

by four to generate four non-overlapping quadrature

clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC

is incremented every Q1 and the instruction is fetched

from program memory and latched into the instruction

register in Q4. It is decoded and executed during the

following Q1 through Q4. The clocks and instruction

execution flow is shown in Figure 3-3 and Example 3-1.

A fetch cycle begins with the PC incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the Instruction Register (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3 and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-3:

CLOCK/INSTRUCTION CYCLE

Q2

Q3

Q4

Q2

Q3

Q4

Q2

Q3

Q4

Q1

OSC1

Q1

Q2

Q3

Q4

PC

Internal

phase

clock

PC

PC + 1

PC + 2

Fetch INST (PC)

Execute INST (PC – 1)

Fetch INST (PC + 1)

Execute INST (PC)

Fetch INST (PC + 2)

Execute INST (PC + 1)

EXAMPLE 3-1:

INSTRUCTION PIPELINE FLOW

1. MOVLW 03H

Fetch 1

Execute 1

Fetch 2

2. MOVWF PORTB

3. CALL SUB_1

Execute 2

Fetch 3

Execute 3

Fetch 4

4. BSF

PORTB, BIT1

Flush

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction

is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

DS41236E-page 16

PIC12F508/509/16F505

FIGURE 4-1:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC12F508/509

4.0

MEMORY ORGANIZATION

The PIC12F508/509/16F505 memories are organized

into program memory and data memory. For devices

with more than 512 bytes of program memory, a paging

scheme is used. Program memory pages are accessed

using one STATUS register bit. For the PIC12F509 and

PIC16F505, with data memory register files of more

than 32 registers, a banking scheme is used. Data

memory banks are accessed using the File Select

Register (FSR).

PC<11:0>

12

CALL, RETLW

Stack Level 1

Stack Level 2

(1)

Reset Vector

0000h

4.1

Program Memory Organization for

the PIC12F508/509

On-chip Program

Memory

The PIC12F508 device has a 10-bit Program Counter

(PC) and PIC12F509 has a 11-bit Program Counter

(PC) capable of addressing a 2K x 12 program memory

space.

512 Word

01FFh

0200h

Only the first 512 x 12 (0000h-01FFh) for the

PIC12F508, and 1K x 12 (0000h-03FFh) for the

PIC12F509 are physically implemented (see

On-chip Program

Memory

Figure 4-1). Accessing

a location above these

boundaries will cause a wrap-around within the first

512 x 12 space (PIC12F508) or 1K x 12 space

(PIC12F509). The effective Reset vector is a 0000h

(see Figure 4-1). Location 01FFh (PIC12F508) and

location 03FFh (PIC12F509) contain the internal

clock oscillator calibration value. This value should

never be overwritten.

1024 Word

03FFh

0400h

7FFh

Note 1: Address 0000h becomes the

effective Reset vector. Location

01FFh, 03FFh (PIC12F508,

PIC12F509) contains the MOVLW XX

internal oscillator calibration value.

DS41236E-page 17

PIC12F508/509/16F505

4.2

Program Memory Organization

For The PIC16F505

4.3

Data Memory Organization

Data memory is composed of registers or bytes of

RAM. Therefore, data memory for a device is specified

by its register file. The register file is divided into two

functional groups: Special Function Registers (SFR)

and General Purpose Registers (GPR).

The PIC16F505 device has a 11-bit Program Counter

(PC) capable of addressing a 2K x 12 program memory

space.

The 1K x 12 (0000h-03FFh) for the PIC16F505 are

physically implemented. Refer to Figure 4-2.

Accessing a location above this boundary will cause a

wrap-around within the first 1K x 12 space. The

effective Reset vector is at 0000h (see Figure 4-2).

Location 03FFh contains the internal oscillator

calibration value. This value should never be

overwritten.

The Special Function Registers include the TMR0

register, the Program Counter (PCL), the STATUS

register, the I/O registers (ports) and the File Select

Register (FSR). In addition, Special Function Registers

are used to control the I/O port configuration and

prescaler options.

The General Purpose Registers are used for data and

control information under command of the instructions.

FIGURE 4-2:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F505

For the PIC12F508/509, the register file is composed of

7 Special Function Registers, 9 General Purpose

Registers and 16 or 32 General Purpose Registers

accessed by banking (see Figure 4-3 and Figure 4-4).

PC<11:0>

12

For the PIC16F505, the register file is composed of 8

CALL, RETLW

Special Function Registers,

Registers and 64 General Purpose Registers accessed

by banking (Figure 4-5).

8 General Purpose

Stack Level 1

Stack Level 2

4.3.1

GENERAL PURPOSE REGISTER

FILE

(1)

Reset Vector

0000h

The General Purpose Register file is accessed, either

directly or indirectly, through the File Select Register

(FSR). See Section 4.9 “Indirect Data Addressing:

INDF and FSR Registers”.

01FFh

0200h

On-chip Program

Memory

1024 Words

03FFh

0400h

7FFh

Note 1: Address 0000h becomes the

effective Reset vector. Location

03FFh contains the MOVLW XX

internal oscillator calibration value.

DS41236E-page 18

PIC12F508/509/16F505

FIGURE 4-3:

PIC12F508 REGISTER

FILE MAP

FIGURE 4-4:

PIC12F509 REGISTER

FILE MAP

FSR<5>

File Address

00h

0

1

File Address

(1)

INDF

00h

01h

02h

03h

04h

05h

06h

07h

(1)

20h

INDF

TMR0

PCL

TMR0

PCL

01h

02h

03h

04h

05h

STATUS

FSR

Addresses map

back to

addresses

in Bank 0.

STATUS

FSR

OSCCAL

GPIO

OSCCAL

GPIO

06h

07h

General

Purpose

Registers

General

Purpose

Registers

2Fh

0Fh

10h

30h

General

Purpose

Registers

General

Purpose

Registers

1Fh

3Fh

Bank 0

Bank 1

Note 1: Not a physical register. See Section 4.9

“Indirect Data Addressing: INDF and FSR

Registers”.

Note 1: Not a physical register. See Section 4.9

“Indirect Data Addressing: INDF and

FSR Registers”.

FIGURE 4-5:

PIC16F505 REGISTER FILE MAP

FSR<6:5>

00

01

10

11

File Address

00h

(1)

20h

40h

60h

INDF

01h

02h

03h

04h

05h

06h

TMR0

PCL

Addresses map back to

addresses in Bank 0.

STATUS

FSR

OSCCAL

PORTB

PORTC

07h

08h

General

Purpose

Registers

2Fh

30h

4Fh

50h

6Fh

0Fh

70h

10h

1Fh

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

3Fh

5Fh

7Fh

Bank 1

Bank 2

Bank 3

Bank 0

Note 1: Not a physical register. See Section 4.9 “Indirect Data Addressing: INDF and FSR Registers”.

DS41236E-page 19

PIC12F508/509/16F505

4.3.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral functions to control the

operation of the device (Table 4-1).

The Special Function Registers can be classified into

two sets. The Special Function Registers associated

with the “core” functions are described in this section.

Those related to the operation of the peripheral

features are described in the section for each

peripheral feature.

TABLE 4-1:

Address

SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC12F508/509)

Value on

Power-On

Reset⁽²⁾

Name

INDF

TMR0

Bit 7

Bit 6 Bit 5 Bit 4

Bit 3

Bit 2

Bit 1 Bit 0

Page #

00h

Uses Contents of FSR to Address Data Memory (not a physical

register)

xxxx xxxx

28

01h

8-bit Real-Time Clock/Counter

xxxx xxxx

1111 1111

0-01 1xxx⁽³⁾

111x xxxx

110x xxxx

1111 111-

--xx xxxx

--11 1111

1111 1111

35

27

22

28

26

31

24

02h⁽¹⁾

PCL

Low-order 8 bits of PC

03h

STATUS

FSR

GPWUF

—

PA0⁽⁵⁾

TO

PD

Z

DC

C

04h

Indirect Data Memory Address Pointer

04h⁽⁴⁾

FSR

05h

OSCCAL

GPIO

CAL6

—

CAL5 CAL4 CAL3 CAL2

CAL1 CAL0

—

06h

—

GP5

I/O Control Register

PSA

GP4

GP3

GP2

GP1 GP0

N/A

TRISGPIO

OPTION

—

N/A

GPWU GPPU TOCS TOSE

PS2

PS1 PS0

Legend: – = unimplemented, read as ‘0’, x= unknown, u= unchanged, q= value depends on condition.

Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.7 “Program Counter”

for an explanation of how to access these bits.

2: Other (non Power-up) Resets include external Reset through MCLR, Watchdog Timer and wake-up on pin

change Reset.

3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

4: PIC12F509 only.

5: This bit is used on the PIC12F509. For code compatibility do not use this bit on the PIC12F508.

DS41236E-page 20

PIC12F508/509/16F505

TABLE 4-2:

Address

SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC16F505)

Value on

Bit 1 Bit 0 Power-On

Reset⁽²⁾

Name

INDF

TMR0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Page #

00h

Uses Contents of FSR to Address Data Memory (not a physical

register)

xxxx xxxx

28

01h

02h⁽¹⁾

03h

04h

05h

06h

07h

N/A

8-bit Real-Time Clock/Counter

Low-order 8 bits of PC

xxxx xxxx

1111 1111

0-01 1xxx

100x xxxx

1111 111-

35

27

22

28

26

31

25

PCL

STATUS

FSR

RBWUF

—

PA0

TO

PD

Z

DC

C

Indirect Data Memory Address Pointer

OSCCAL

PORTB

PORTC

TRISB

TRISC

OPTION

CAL6

—

CAL5 CAL4 CAL3

CAL2

RB3

CAL1 CAL0

—

RB5

RC5

RB4

RC4

RB2

RC2

RB1 RB0 --xxxxxx

RC1 RC0 --xx xxxx

--11 1111

—

RC3

—

I/O Control Register

—

--11 1111

RBWU RBPU TOCS TOSE

PSA

PS2

PS1 PS0 1111 1111

Legend: – = unimplemented, read as ‘0’, x= unknown, u= unchanged, q= value depends on condition.

Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

2: Other (non Power-up) Resets include external reset through MCLR, Watchdog Timer and wake-up on pin

change Reset.

DS41236E-page 21

PIC12F508/509/16F505

For example, CLRF STATUS,will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu(where u= unchanged).

4.4

STATUS Register

This register contains the arithmetic status of the ALU,

the Reset status and the page preselect bit.

Therefore, it is recommended that only BCF, BSF and

MOVWFinstructions be used to alter the STATUS regis-

ter. These instructions do not affect the Z, DC or C bits

from the STATUS register. For other instructions which

do affect Status bits, see Section 8.0 “Instruction Set

Summary”.

The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

REGISTER 4-1:

STATUS REGISTER (ADDRESS: 03h) (PIC12F508/509)

R/W-0

GPWUF

bit 7

R/W-0

—

R/W-0

PA0

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC

R/W-x

C

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

GPWUF: GPIO Reset bit

1= Reset due to wake-up from Sleep on pin change

0= After power-up or other Reset

bit 6

bit 5

Reserved: Do not use

(1)

PA0: Program Page Preselect bits

1= Page 1 (200h-3FFh)

0= Page 0 (000h-1FFh)

Each page is 512 bytes.

Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is

not recommended, since this may affect upward compatibility with future products.

bit 4

bit 3

bit 2

bit 1

TO: Time-Out bit

1= After power-up, CLRWDTinstruction, or SLEEPinstruction

0= A WDT time-out occurred

PD: Power-Down bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit Carry/Borrow bit (for ADDWFand SUBWFinstructions)

ADDWF:

1= A carry from the 4th low-order bit of the result occurred

0= A carry from the 4th low-order bit of the result did not occur

SUBWF:

1= A borrow from the 4th low-order bit of the result did not occur

0= A borrow from the 4th low-order bit of the result occurred

bit 0

C: Carry/Borrow bit (for ADDWF, SUBWFand RRF, RLFinstructions)

ADDWF:

SUBWF:

RRFor RLF:

1= A carry occurred

0= A carry did not occur

1= A borrow did not occur

0= A borrow occurred

Load bit with LSb or MSb, respectively

Note 1: This bit is used on the PIC12F509. For code compatibility do not use this bit on the PIC12F508.

DS41236E-page 22

PIC12F508/509/16F505

REGISTER 4-2:

STATUS REGISTER (ADDRESS: 03h) (PIC16F505)

R/W-x

C

R/W-0

RBWUF

bit 7

R/W-0

—

R/W-0

PA0

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

RBWUF: PORTB Reset bit

1= Reset due to wake-up from Sleep on pin change

0= After power-up or other Reset

bit 6

bit 5

Reserved: Do not use

PA0: Program Page Preselect bits

1= Page 1 (200h-3FFh)

0= Page 0 (000h-1FFh)

Each page is 512 bytes.

Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page

preselect is not recommended, since this may affect upward compatibility with future products.

bit 4

bit 3

bit 2

bit 1

TO: Time-Out bit

1= After power-up, CLRWDTinstruction, or SLEEPinstruction

0= A WDT time-out occurred

PD: Power-Down bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit Carry/Borrow bit (for ADDWFand SUBWFinstructions)

ADDWF:

1= A carry from the 4th low-order bit of the result occurred

0= A carry from the 4th low-order bit of the result did not occur

SUBWF:

1= A borrow from the 4th low-order bit of the result did not occur

0= A borrow from the 4th low-order bit of the result occurred

bit 0

C: Carry/Borrow bit (for ADDWF, SUBWFand RRF, RLFinstructions)

ADDWF:

SUBWF:

RRFor RLF:

1= A carry occurred

1= A borrow did not occur Load bit with LSb or MSb, respectively

0= A carry did not occur 0= A borrow occurred

DS41236E-page 23

PIC12F508/509/16F505

4.5

OPTION Register

The OPTION register is a 8-bit wide, write-only register,

which contains various control bits to configure the

Timer0/WDT prescaler and Timer0.

Note:

If TRIS bit is set to ‘0’, the wake-up on

change and pull-up functions are disabled

for that pin (i.e., note that TRIS overrides

Option control of GPPU/RBPU and

GPWU/RBWU).

By executing the OPTION instruction, the contents of

the W register will be transferred to the OPTION regis-

ter. A Reset sets the OPTION<7:0> bits.

If the T0CS bit is set to ‘1’, it will override

the TRIS function on the T0CKI pin.

REGISTER 4-3:

OPTION REGISTER (PIC12F508/509)

W-1

PS0

W-1

GPWU

bit 7

W-1

PSA

W-1

PS2

W-1

PS1

GPPU

T0CS

T0SE

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

GPWU: Enable Wake-up on Pin Change bit (GP0, GP1, GP3)

1= Disabled

0= Enabled

GPPU: Enable Weak Pull-ups bit (GP0, GP1, GP3)

1= Disabled

0= Enabled

T0CS: Timer0 Clock Source Select bit

1= Transition on T0CKI pin (overrides TRIS on the T0CKI pin)

0= Transition on internal instruction cycle clock, FOSC/4

T0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on the T0CKI pin

0= Increment on low-to-high transition on the T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler assigned to the WDT

0= Prescaler assigned to Timer0

PS<2:0>: Prescaler Rate Select bits

Bit Value Timer0 Rate WDT Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

DS41236E-page 24

PIC12F508/509/16F505

REGISTER 4-4:

OPTION REGISTER (PIC16F505)

W-1

PS0

W-1

RBWU

bit 7

W-1

PS2

W-1

PS1

RBPU

T0CS

T0SE

PSA

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

RBWU: Enable Wake-up on Pin Change bit (RB0, RB1, RB3, RB4)

1= Disabled

0= Enabled

RBPU: Enable Weak Pull-ups bit (RB0, RB1, RB3, RB4)

1= Disabled

0= Enabled

T0CS: Timer0 clock Source Select bit

1= Transition on T0CKI pin (overrides TRIS on the T0CKI pin)

0= Transition on internal instruction cycle clock, FOSC/4

T0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on the T0CKI pin

0= Increment on low-to-high transition on the T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler assigned to the WDT

0= Prescaler assigned to Timer0

PS<2:0>: Prescaler Rate Select bits

Bit Value Timer0 Rate WDT Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

DS41236E-page 25

PIC12F508/509/16F505

After you move in the calibration constant, do not

change the value. See Section 7.2.5 “Internal 4 MHz

RC Oscillator”.

4.6

OSCCAL Register

The Oscillator Calibration (OSCCAL) register is used to

calibrate the internal precision 4 MHz oscillator. It

contains seven bits for calibration.

Note:

Erasing the device will also erase the pre-

programmed internal calibration value for

the internal oscillator. The calibration

value must be read prior to erasing the

part so it can be reprogrammed correctly

later.

REGISTER 4-5:

OSCCAL REGISTER (ADDRESS: 05h)

R/W-0

—

R/W-1

CAL6

R/W-1

CAL5

R/W-1

CAL4

R/W-1

CAL3

R/W-1

CAL2

R/W-1

CAL1

R/W-1

CAL0

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-1

CAL<6:0>: Oscillator Calibration bits

0111111= Maximum frequency

•

0000001

0000000= Center frequency

1111111

•

1000000= Minimum frequency

bit 0

Unimplemented: Read as ‘0’

DS41236E-page 26

PIC12F508/509/16F505

4.7.1

EFFECTS OF RESET

4.7

Program Counter

The PC is set upon a Reset, which means that the PC

addresses the last location in the last page (i.e., the

oscillator calibration instruction). After executing

MOVLW XX, the PC will roll over to location 00h and

begin executing user code.

As a program instruction is executed, the Program

Counter (PC) will contain the address of the next

program instruction to be executed. The PC value is

increased by one every instruction cycle, unless an

instruction changes the PC.

The STATUS register page preselect bits are cleared

upon a Reset, which means that page 0 is pre-selected.

For a GOTOinstruction, bits 8:0 of the PC are provided

by the GOTO instruction word. The Program Counter

(PCL) is mapped to PC<7:0>. Bit 5 of the STATUS

register provides page information to bit 9 of the PC

(Figure 4-6).

Therefore, upon a Reset, a GOTO instruction will

automatically cause the program to jump to page 0 until

the value of the page bits is altered.

For a CALL instruction, or any instruction where the

PCL is the destination, bits 7:0 of the PC again are

provided by the instruction word. However, PC<8>

does not come from the instruction word, but is always

cleared (Figure 4-6).

4.8

Stack

The PIC12F508/509/16F505 devices have a 2-deep,

12-bit wide hardware PUSH/POP stack.

A CALLinstruction will PUSH the current value of Stack

1 into Stack 2 and then PUSH the current PC value,

incremented by one, into Stack Level 1. If more than two

sequential CALLs are executed, only the most recent two

return addresses are stored.

Instructions where the PCL is the destination, or modify

PCL instructions, include MOVWF PC, ADDWF PCand

BSF PC,5.

Note:

Because PC<8> is cleared in the CALL

instruction or any modify PCL instruction,

all subroutine calls or computed jumps are

limited to the first 256 locations of any

program memory page (512 words long).

A RETLW instruction will POP the contents of Stack

Level 1 into the PC and then copy Stack Level 2

contents into Stack Level 1. If more than two sequential

RETLWs are executed, the stack will be filled with the

address previously stored in Stack Level 2. Note that

the W register will be loaded with the literal value

specified in the instruction. This is particularly useful for

the implementation of data look-up tables within the

program memory.

FIGURE 4-6:

LOADING OF PC

BRANCH INSTRUCTIONS

GOTOInstruction

11 10 9 8 7

0

Note 1: There are no Status bits to indicate stack

PC

PCL

overflows or stack underflow conditions.

2: There are no instruction mnemonics

called PUSH or POP. These are actions

that occur from the execution of the CALL

and RETLWinstructions.

Instruction Word

PA0

7

0

Status

CALLor Modify PCL Instruction

11 10 9 8 7

0

PC

PCL

Instruction Word

Reset to ‘0’

PA0

7

0

Status

DS41236E-page 27

PIC12F508/509/16F505

EXAMPLE 4-1:

HOW TO CLEAR RAM

USING INDIRECT

ADDRESSING

4.9

Indirect Data Addressing: INDF

and FSR Registers

The INDF register is not

a physical register.

MOVLW

MOVWF

0x10

;initialize pointer

;to RAM

Addressing INDF actually addresses the register

whose address is contained in the FSR register (FSR

is a pointer). This is indirect addressing.

FSR

INDF

;clear INDF

;register

INCF

BTFSC

GOTO

FSR,F

FSR,4

;all done?

;NO, clear next

4.9.1

INDIRECT ADDRESSING

• Register file 07 contains the value 10h

• Register file 08 contains the value 0Ah

• Load the value 07 into the FSR register

CONTINUE

:

;YES, continue

• A read of the INDF register will return the value

of 10h

The FSR is a 5-bit wide register. It is used in conjunction

with the INDF register to indirectly address the data

memory area.

• Increment the value of the FSR register by one

(FSR = 08)

• A read of the INDR register now will return the

value of 0Ah.

The FSR<4:0> bits are used to select data memory

addresses 00h to 1Fh.

Reading INDF itself indirectly (FSR = 0) will produce

00h. Writing to the INDF register indirectly results in a

no operation (although Status bits may be affected).

PIC12F508 – Does not use banking. FSR <7:5> are

unimplemented and read as ‘1’s.

PIC12F509 – Uses FSR<5>. Selects between bank 0

and bank 1. FSR<7:6> are unimplemented, read as

‘1’.

A simple program to clear RAM locations 10h-1Fh

using indirect addressing is shown in Example 4-1.

PIC16F505 – Uses FSR<6:5>. Selects from bank 0 to

bank 3. FSR<7> is unimplemented, read as ‘1’.

FIGURE 4-7:

DIRECT/INDIRECT ADDRESSING (PIC12F508/509)

Direct Addressing

Indirect Addressing

(FSR)

4

(opcode)

0

5

(FSR)

0

6

4

5

6

Location Select

Bank Select

Location Select

Bank

00

01

00h

Addresses

map back to

addresses

in Bank 0.

Data

Memory

0Fh

10h

(1)

1Fh

Bank 0

3Fh

Bank 1

(2)

Note 1: For register map detail, see Section 4.3 “Data Memory Organization”.

2: PIC12F509.

DS41236E-page 28

PIC12F508/509/16F505

FIGURE 4-8:

DIRECT/INDIRECT ADDRESSING (PIC16F505)

Direct Addressing

Indirect Addressing

(FSR) 0

(FSR)

6

5

4

(opcode)

0

6

5

4

Bank Select

Location Select

00h

Bank

Location Select

00

01

10

11

Addresses

map back to

addresses

in Bank 0.

0Fh

10h

Data

Memory

(1)

1Fh

3Fh

Bank 1

5Fh

Bank 2

7Fh

Bank 0

Bank 3

Note 1: For register map detail, see Section 4.3 “Data Memory Organization”.

DS41236E-page 29

PIC12F508/509/16F505

NOTES:

DS41236E-page 30

PIC12F508/509/16F505

5.4

I/O Interfacing

5.0

I/O PORT

The equivalent circuit for an I/O port pin is shown in

Figure 5-2. All port pins, except RB3/GP3 which is

input only, may be used for both input and output oper-

ations. For input operations, these ports are non-latch-

ing. Any input must be present until read by an input

instruction (e.g., MOVF PORTB, W). The outputs are

latched and remain unchanged until the output latch is

rewritten. To use a port pin as output, the correspond-

ing direction control bit in TRIS must be cleared (= 0).

For use as an input, the corresponding TRIS bit must

be set. Any I/O pin (except RB3/GP3) can be

programmed individually as input or output.

As with any other register, the I/O register(s) can be

written and read under program control. However, read

instructions (e.g., MOVF PORTB,W) always read the I/O

pins independent of the pin’s Input/Output modes. On

Reset, all I/O ports are defined as input (inputs are at

high-impedance) since the I/O control registers are all

set.

Note:

On the PIC12F508/509, I/O PORTB is ref-

erenced as GPIO. On the PIC16F505, I/O

PORTB is referenced as PORTB.

5.1

PORTB/GPIO

FIGURE 5-1:

PIC12F508/509/16F505

EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

PORTB/GPIO is an 8-bit I/O register. Only the low-

order 6 bits are used (RB/GP<5:0>). Bits 7 and 6 are

unimplemented and read as ‘0’s. Please note that RB3/

GP3 is an input only pin. The Configuration Word can

set several I/O’s to alternate functions. When acting as

alternate functions, the pins will read as ‘0’ during a port

read. Pins RB0/GP0, RB1/GP1, RB3/GP3 and RB4

can be configured with weak pull-ups and also for

wake-up on change. The wake-up on change and weak

pull-up functions are not pin selectable. If RB3/GP3/

MCLR is configured as MCLR, weak pull-up is always

on and wake-up on change for this pin is not enabled.

Data

Bus

D

Q

Data

Latch

VDD

P

VDD

WR

Port

CK

N

I/O

W

Reg

D

Q

TRIS

Latch

5.2

PORTC (PIC16F505 Only)

VSS VSS

TRIS ‘f’

PORTC is an 8-bit I/O register. Only the low-order 6 bits

are used (RC<5:0>). Bits 7 and 6 are unimplemented

and read as ‘0’s.

CK

Reset

Note:

On power-up, TOCKI functionality is

enabled in the OPTION register and must

be disabled to allow RC5 to be used as

general purpose I/O.

(1)

RD Port

5.3

TRIS Registers

Note 1: See Table 3-3 for buffer type.

The Output Driver Control register is loaded with the

contents of the W register by executing the TRIS f

instruction. A ‘1’ from a TRIS register bit puts the corre-

sponding output driver in a High-Impedance mode. A

‘0’ puts the contents of the output data latch on the

selected pins, enabling the output buffer. The excep-

tions are RB3/GP3, which is input only and the T0CKI

pin, which may be controlled by the OPTION register.

See Register 4-3 and Register 4-4.

Note:

A read of the ports reads the pins, not the

output data latches. That is, if an output

driver on a pin is enabled and driven high,

but the external system is holding it low, a

read of the port will indicate that the pin is

low.

The TRIS registers are “write-only” and are set (output

drivers disabled) upon Reset.

DS41236E-page 31

PIC12F508/509/16F505

TABLE 5-1:

SUMMARY OF PORT REGISTERS

Value on

Power-On

Reset

Value on

All Other

Resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1 Bit 0

(1)

N/A

TRISGPIO

—

I/O Control Register

--11 1111

1111 1111

--11 1111

1111 1111

(2)

N/A

TRISB

(2)

N/A

TRISC

—

(1)

N/A

OPTION

GPWU

RBWU

GPWUF

RBWUF

—

GPPU

RBPU

—

TOCS

PAO

GP5

TOSE

TO

PSA

PD

PS2

Z

PS1

DC

PS0

C

(2)

N/A

OPTION

(1)

(3)

03h

STATUS

0-01 1xxx q00q quuu

(2)

(3)

03h

STATUS

—

TO

PD

Z

DC

C

(1)

06h

GPIO

—

GP4

RB4

RC4

GP3

RB3

RC3

GP2

RB2

RC2

GP1

RB1

RC1

GP0

RB0

RC0

--xxxxxx

--xx xxxx

--uu uuuu

(2)

06h

PORTB

—

RB5

--uu uuuu

(2)

07h

PORTC

—

RC5

Legend:

Shaded cells are not used by Port registers, read as ‘0’. – = unimplemented, read as ‘0’, x= unknown, u= unchanged,

q= depends on condition.

Note 1: PIC12F508/509 only.

2: PIC16F505 only.

3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

DS41236E-page 32

PIC12F508/509/16F505

EXAMPLE 5-1:

READ-MODIFY-WRITE

INSTRUCTIONS ON AN

I/O PORT(e.g., PIC16F505)

5.5

I/O Programming Considerations

5.5.1

BIDIRECTIONAL I/O PORTS

Some instructions operate internally as read followed

by write operations. The BCFand BSFinstructions, for

example, read the entire port into the CPU, execute the

bit operation and re-write the result. Caution must be

used when these instructions are applied to a port

where one or more pins are used as input/outputs. For

example, a BSFoperation on bit 5 of PORTB/GPIO will

cause all eight bits of PORTB/GPIO to be read into the

CPU, bit 5 to be set and the PORTB/GPIO value to be

written to the output latches. If another bit of PORTB/

GPIO is used as a bidirectional I/O pin (say bit 0) and it

is defined as an input at this time, the input signal pres-

ent on the pin itself would be read into the CPU and

rewritten to the data latch of this particular pin, overwrit-

ing the previous content. As long as the pin stays in the

Input mode, no problem occurs. However, if bit 0 is

switched into Output mode later on, the content of the

data latch may now be unknown.

;Initial PORTB Settings

;PORTB<5:3> Inputs

;PORTB<2:0> Outputs

;

PORTB latch PORTB pins

----------

PORTB, 5 ;--01 -ppp

PORTB, 4 ;--10 -ppp

----------

--11 pppp

BCF

MOVLW 007h;

TRIS PORTB

;--10 -ppp

--11 pppp

;

Note 1: The user may have expected the pin values to

be ‘--00 pppp’. The 2nd BCFcaused RB5 to

be latched as the pin value (High).

5.5.2

SUCCESSIVE OPERATIONS ON

I/O PORTS

The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be

valid at the beginning of the instruction cycle (Figure 5-2).

Therefore, care must be exercised if a write followed by

a read operation is carried out on the same I/O port. The

sequence of instructions should allow the pin voltage to

stabilize (load dependent) before the next instruction

causes that file to be read into the CPU. Otherwise, the

previous state of that pin may be read into the CPU rather

than the new state. When in doubt, it is better to separate

these instructions with a NOP or another instruction not

accessing this I/O port.

Example 5-1 shows the effect of two sequential

Read-Modify-Write instructions (e.g., BCF, BSF, etc.)

on an I/O port.

A pin actively outputting a high or a low should not be

driven from external devices at the same time in order

to change the level on this pin (“wired OR”, “wired

AND”). The resulting high output currents may damage

the chip.

FIGURE 5-2:

SUCCESSIVE I/O OPERATION (PIC16F505 Shown)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC + 3

PC

MOVWFPORTB

PC + 1

PC + 2

This example shows a write to PORTB

followed by a read from PORTB.

Instruction

Fetched

MOVFPORTB, W

NOP

Data setup time = (0.25 TCY – TPD)

where: TCY = instruction cycle

TPD = propagation delay

RB<5:0>

Port pin

written here

Port pin

sampled here

Therefore, at higher clock frequencies, a

write followed by a read may be problematic.

Instruction

Executed

MOVWF PORTB

MOVF PORTB,W

NOP

(Write to PORTB)

(Read PORTB)

DS41236E-page 33

PIC12F508/509/16F505

NOTES:

DS41236E-page 34

PIC12F508/509/16F505

Counter mode is selected by setting the T0CS bit

(OPTION<5>). In this mode, Timer0 will increment

either on every rising or falling edge of pin T0CKI. The

T0SE bit (OPTION<4>) determines the source edge.

Clearing the T0SE bit selects the rising edge. Restric-

tions on the external clock input are discussed in detail

in Section 6.1 “Using Timer0 with an External

Clock”.

6.0

TIMER0 MODULE AND TMR0

REGISTER

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select:

- Edge select for external clock

The prescaler may be used by either the Timer0

module or the Watchdog Timer, but not both. The

prescaler assignment is controlled in software by the

control bit, PSA (OPTION<3>). Clearing the PSA bit

will assign the prescaler to Timer0. The prescaler is not

readable or writable. When the prescaler is assigned to

the Timer0 module, prescale values of 1:2, 1:4,...,

1:256 are selectable. Section 6.2 “Prescaler” details

the operation of the prescaler.

Figure 6-1 is a simplified block diagram of the Timer0

module.

Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In Timer mode, the Timer0 module will

increment every instruction cycle (without prescaler). If

TMR0 register is written, the increment is inhibited for

the following two cycles (Figure 6-2 and Figure 6-3).

The user can work around this by writing an adjusted

value to the TMR0 register.

A summary of registers associated with the Timer0

module is found in Table 6-1.

FIGURE 6-1:

TIMER0 BLOCK DIAGRAM

Data Bus

(GP2/RC5)/T0CKI FOSC/4

0

1

PSOUT

8

1

0

Sync with

Internal

Clocks

TMR0 Reg

Programmable

PSOUT

Sync

(2)

Prescaler

(2 TCY delay)

T0SE

3

(1)

PS2, PS1, PS0

PSA

(1)

T0CS

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer (Figure 6-5).

FIGURE 6-2:

TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

PC

(Program

Counter)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Instruction

Fetch

T0

NT0 + 1

T0 + 1

T0 + 2

NT0

NT0 + 2

Timer0

Instruction

Executed

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 2

Write TMR0

executed

DS41236E-page 35

PIC12F508/509/16F505

FIGURE 6-3:

TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

PC

(Program

Counter)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC – 1

PC

PC + 1

PC + 2

PC + 3

PC + 4

PC + 5

PC + 6

Instruction

Fetch

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

T0

T0 + 1

NT0

NT0 + 1

Timer0

Instruction

Executed

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 2

Write TMR0

executed

TABLE 6-1:

REGISTERS ASSOCIATED WITH TIMER0

Value on

Power-On

Reset

Value on

All Other

Resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3 Bit 2

Bit 1

Bit 0

01h

TMR0

Timer0 – 8-bit Real-Time Clock/Counter

GPWU GPPU T0CS T0SE PSA

PSA

I/O Control Register

RC5 RC4 RC3

xxxx xxxx

1111 1111

--11 1111

uuuu uuuu

1111 1111

--11 1111

(1)

(2)

N/A

OPTION

PS2

PS1

PS0

N/A

RBWU

—

RBPU

—

T0CS T0SE

(1), (3)

N/A

TRISGPIO

(2), (3)

N/A

TRISC

—

RC2

RC1

RC0

Legend:

Shaded cells are not used by Timer0. – = unimplemented, x = unknown, u= unchanged.

Note 1: PIC12F508/509 only.

2: PIC16F505 only.

3: The TRIS of the T0CKI pin is overridden when T0CS = 1.

DS41236E-page 36

PIC12F508/509/16F505

When a prescaler is used, the external clock input is

divided by the asynchronous ripple counter-type

prescaler, so that the prescaler output is symmetrical.

For the external clock to meet the sampling require-

ment, the ripple counter must be taken into account.

Therefore, it is necessary for T0CKI to have a period of

at least 4 TOSC (and a small RC delay of 4 Tt0H)

divided by the prescaler value. The only requirement

on T0CKI high and low time is that they do not violate

the minimum pulse width requirement of Tt0H. Refer to

parameters 40, 41 and 42 in the electrical specification

of the desired device.

6.1

Using Timer0 with an External

Clock

When an external clock input is used for Timer0, it must

meet certain requirements. The external clock require-

ment is due to internal phase clock (TOSC) synchroni-

zation. Also, there is a delay in the actual incrementing

of Timer0 after synchronization.

6.1.1

EXTERNAL CLOCK

SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks (Figure 6-4).

Therefore, it is necessary for T0CKI to be high for at

least 2 TOSC (and a small RC delay of 2 Tt0H) and low

for at least 2 TOSC (and a small RC delay of 2 Tt0H).

Refer to the electrical specification of the desired

device.

6.1.2

TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0

module is actually incremented. Figure 6-4 shows the

delay from the external clock edge to the timer

incrementing.

FIGURE 6-4:

TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Small pulse

misses sampling

External Clock Input or

(2)

Prescaler Output

(1)

External Clock/Prescaler

Output After Sampling

(3)

Increment Timer0 (Q4)

Timer0

T0

T0 + 1

T0 + 2

Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC). Therefore, the error

in measuring the interval between two edges on Timer0 input = ±4 TOSC max.

2: External clock if no prescaler selected; prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

DS41236E-page 37

PIC12F508/509/16F505

EXAMPLE 6-1:

CHANGING PRESCALER

(TIMER0 → WDT)

;Clear WDT

6.2

Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module or as a postscaler for the Watchdog

Timer (WDT), respectively (see Section 7.6 “Watch-

dog Timer (WDT)”). For simplicity, this counter is

being referred to as “prescaler” throughout this data

sheet.

CLRWDT

CLRF

TMR0

;Clear TMR0 & Prescaler

MOVLW ‘00xx1111’b;These 3 lines (5, 6, 7)

OPTION

;are required only if

;desired

;PS<2:0> are 000 or 001

CLRWDT

MOVLW ‘00xx1xxx’b;Set Postscaler to

OPTION ;desired WDT rate

Note:

The prescaler may be used by either the

Timer0 module or the WDT, but not both.

Thus, a prescaler assignment for the

Timer0 module means that there is no

prescaler for the WDT and vice versa.

To change the prescaler from the WDT to the Timer0

module, use the sequence shown in Example 6-2. This

sequence must be used even if the WDT is disabled. A

CLRWDT instruction should be executed before

switching the prescaler.

The PSA and PS<2:0> bits (OPTION<3:0>) determine

prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,

BSF 1, x, etc.) will clear the prescaler. When assigned

to WDT, a CLRWDT instruction will clear the prescaler

along with the WDT. The prescaler is neither readable

nor writable. On a Reset, the prescaler contains all ‘0’s.

EXAMPLE 6-2:

CHANGING PRESCALER

(WDT → TIMER0)

;Clear WDT and

;prescaler

CLRWDT

MOVLW ‘xxxx0xxx’ ;Select TMR0, new

;prescale value and

;clock source

6.2.1

SWITCHING PRESCALER

ASSIGNMENT

OPTION

The prescaler assignment is fully under software control

(i.e., it can be changed “on-the-fly” during program

execution). To avoid an unintended device Reset, the

following instruction sequence (Example 6-1) must be

executed when changing the prescaler assignment

from Timer0 to the WDT.

DS41236E-page 38

PIC12F508/509/16F505

FIGURE 6-5:

BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER^{(1), (2)}

TCY (= FOSC/4)

Data Bus

8

0

1

(GP2/RC5)/T0CKI

M

U

X

1

0

M

U

X

Sync

2

Cycles

TMR0 Reg

T0SE

T0CS

PSA

0

1

8-bit Prescaler

M

U

X

8

Watchdog

Timer

8-to-1 MUX

PS<2:0>

PSA

1

0

WDT Enable bit

MUX

PSA

WDT

Time-out

Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.

2: T0CKI is shared with pin RC5 on the PIC16F505 and pin GP2 on the PIC12F508/509.

DS41236E-page 39

PIC12F508/509/16F505

NOTES:

DS41236E-page 40

PIC12F508/509/16F505

The PIC12F508/509/16F505 devices have a Watchdog

Timer, which can be shut off only through Configuration

bit WDTE. It runs off of its own RC oscillator for added

reliability. If using HS (PIC16F505), XT or LP selectable

oscillator options, there is always an 18 ms (nominal)

delay provided by the Device Reset Timer (DRT),

intended to keep the chip in Reset until the crystal

oscillator is stable. If using INTRC or EXTRC, there is

an 18 ms delay only on VDD power-up. With this timer

on-chip, most applications need no external Reset

circuitry.

7.0

SPECIAL FEATURES OF THE

CPU

What sets

a

microcontroller apart from other

processors are special circuits that deal with the needs

of real-time applications. The PIC12F508/509/16F505

microcontrollers have a host of such features intended

to maximize system reliability, minimize cost through

elimination of external components, provide power-

saving operating modes and offer code protection.

These features are:

The Sleep mode is designed to offer a very low-current

Power-Down mode. The user can wake-up from Sleep

through a change on input pins or through a Watchdog

Timer time-out. Several oscillator options are also

made available to allow the part to fit the application,

including an internal 4 MHz oscillator. The EXTRC

oscillator option saves system cost while the LP crystal

option saves power. A set of Configuration bits are

used to select various options.

• Oscillator Selection

• Reset:

- Power-on Reset (POR)

- Device Reset Timer (DRT)

- Wake-up from Sleep on Pin Change

• Watchdog Timer (WDT)

• Sleep

• Code Protection

• ID Locations

7.1

Configuration Bits

• In-Circuit Serial Programming™

• Clock Out

The PIC12F508/509/16F505 Configuration Words

consist of 12 bits. Configuration bits can be

programmed to select various device configurations.

Three bits are for the selection of the oscillator type;

(two bits on the PIC12F508/509), one bit is the

Watchdog Timer enable bit, one bit is the MCLR enable

bit and one bit is for code protection (Register 7-1,

Register 7-2).

DS41236E-page 41

PIC12F508/509/16F505

REGISTER 7-1:

CONFIGURATION WORD FOR PIC12F508/509⁽¹⁾

—

MCLRE

CP

WDTE FOSC1 FOSC0

bit 0

bit 11

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 11-5 Unimplemented: Read as ‘0’

bit 4

MCLRE: GP3/MCLR Pin Function Select bit

1= GP3/MCLR pin function is MCLR

0= GP3/MCLR pin function is digital input, MCLR internally tied to VDD

bit 3

CP: Code Protection bit

1= Code protection off

0= Code protection on

bit 2

WDTE: Watchdog Timer Enable bit

1= WDT enabled

0= WDT disabled

bit 1-0

FOSC<1:0>: Oscillator Selection bits

11= EXTRC = external RC oscillator

10= INTRC = internal RC oscillator

01= XT oscillator

00= LP oscillator

Note 1: Refer to the “PIC12F508/509 Memory Programming Specifications” (DS41227) to determine how to

access the Configuration Word. The Configuration Word is not user addressable during device operation.

DS41236E-page 42

PIC12F508/509/16F505

REGISTER 7-2:

CONFIGURATION WORD FOR PIC16F505⁽¹⁾

—

MCLRE

CP

WDTE FOSC2 FOSC1 FOSC0

bit 0

bit 11

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Unimplemented: Read as ‘0’

bit 11-6

bit 5

MCLRE: RB3/MCLR Pin Function Select bit

1= RB3/MCLR pin function is MCLR

0= RB3/MCLR pin function is digital input, MCLR internally tied to VDD

bit 4

CP: Code Protection bit

1= Code protection off

0= Code protection on

bit 3

WDTE: Watchdog Timer Enable bit

1= WDT enabled

0= WDT disabled

bit 2-0

FOSC<1:0>: Oscillator Selection bits

111= External RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin

110= External RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin

101= Internal RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin

100= Internal RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin

011= EC oscillator/RB4 function on RB4/OSC2/CLKOUT pin

010= HS oscillator

001= XT oscillator

000= LP oscillator

Note 1: Refer to the “PIC16F505 Memory Programming Specifications” (DS41226) to determine how to access

the Configuration Word. The Configuration Word is not user addressable during device operation.

DS41236E-page 43

PIC12F508/509/16F505

FIGURE 7-1:

CRYSTAL OPERATION

(OR CERAMIC

RESONATOR)

7.2

Oscillator Configurations

7.2.1

OSCILLATOR TYPES

(HS, XT OR LP OSC

CONFIGURATION)

The PIC12F508/509/16F505 devices can be operated

in up to six different oscillator modes. The user can

program up to three Configuration bits (FOSC<1:0>

[PIC12F508/509], FOSC<2:0> [PIC16F505]). To select

one of these modes:

(1)

C1

PIC12F508/509

PIC16F505

OSC1

OSC2

Sleep

• LP:

• XT:

• HS:

Low-Power Crystal

Crystal/Resonator

XTAL

(3)

RF

To internal

logic

High-Speed Crystal/Resonator

(PIC16F505 only)

(2)

RS

(1)

C2

• INTRC: Internal 4 MHz Oscillator

• EXTRC: External Resistor/Capacitor

Note 1: See Capacitor Selection tables for

recommended values of C1 and C2.

2: A series resistor (RS) may be required for AT

strip cut crystals.

• EC:

External High-Speed Clock Input

(PIC16F505 only)

3: RF approx. value = 10 MΩ.

7.2.2

CRYSTAL OSCILLATOR/CERAMIC

RESONATORS

In HS (PIC16F505), XT or LP modes, a crystal or

ceramic resonator is connected to the (GP5/RB5)/

OSC1/(CLKIN) and (GP4/RB4)/OSC2/(CLKOUT) pins

to establish oscillation (Figure 7-1). The PIC12F508/

509/16F505 oscillator designs require the use of a

parallel cut crystal. Use of a series cut crystal may give

FIGURE 7-2:

EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR

LP OSC

CONFIGURATION)

a

frequency out of the crystal manufacturers

OSC1

Clock from

ext. system

specifications. When in HS (PIC16F505), XT or LP

modes, the device can have an external clock source

drive the (GP5/RB5)/OSC1/CLKIN pin (Figure 7-2).

When the part is used in this fashion, the output drive

levels on the OSC2 pin are very weak. This pin should

be left open and unloaded. Also, when using this mode,

the external clock should observe the frequency limits

for the clock mode chosen (HS, XT or LP).

PIC12F508/509

PIC16F505

OSC2

Open

TABLE 7-1:

CAPACITOR SELECTION FOR

CERAMIC RESONATORS –

PIC12F508/509/16F505⁽¹⁾

Note 1: This device has been designed to per-

form to the parameters of its data sheet.

It has been tested to an electrical

specification designed to determine its

conformance with these parameters.

Due to process differences in the

manufacture of this device, this device

may have different performance charac-

teristics than its earlier version. These

differences may cause this device to

perform differently in your application

than the earlier version of this device.

Osc

Type

Resonator Cap. Range Cap. Range

Freq.

C1

C2

XT

HS⁽²⁾

4.0 MHz

16 MHz

30 pF

10-47 pF

Note 1: These values are for design guidance

only. Since each resonator has its own

characteristics, the user should consult

the resonator manufacturer for

appropriate values of external

components.

2: PIC16F505 only.

2: The user should verify that the device

oscillator starts and performs as

expected. Adjusting the loading capacitor

values and/or the Oscillator mode may

be required.

DS41236E-page 44

PIC12F508/509/16F505

TABLE 7-2:

CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR –

PIC12F508/509/16F505⁽²⁾

FIGURE 7-3:

EXTERNAL PARALLEL

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

+5V

Osc

Type

Resonator Cap. Range Cap. Range

To Other

Devices

Freq.

C1

C2

10k

32 kHz⁽¹⁾

15 pF

4.7k

74AS04

LP

XT

200 kHz

1 MHz

4 MHz

47-68 pF

15 pF

47-68 pF

15 pF

CLKIN

74AS04

PIC16F505

PIC12F508

PIC12F509

(3)

10k

HS

20 MHz

15-47 pF

XTAL

Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is

recommended.

10k

2: These values are for design guidance

only. Rs may be required to avoid over-

driving crystals with low drive level specifi-

cation. Since each crystal has its own

characteristics, the user should consult

the crystal manufacturer for appropriate

values of external components.

20 pF

Figure 7-4 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental

frequency of the crystal. The inverter performs a 180-

degree phase shift in a series resonant oscillator

circuit. The 330 Ω resistors provide the negative

feedback to bias the inverters in their linear region.

3: PIC16F505 only.

7.2.3

EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

FIGURE 7-4:

EXTERNAL SERIES

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

Either a prepackaged oscillator or a simple oscillator

circuit with TTL gates can be used as an external

crystal oscillator circuit. Prepackaged oscillators

provide a wide operating range and better stability. A

well-designed crystal oscillator will provide good perfor-

mance with TTL gates. Two types of crystal oscillator

circuits can be used: one with parallel resonance, or

one with series resonance.

To Other

Devices

330

74AS04

CLKIN

0.1 mF

XTAL

PIC16F505

PIC12F508

PIC12F509

Figure 7-3 shows implementation of a parallel resonant

oscillator circuit. The circuit is designed to use the fun-

damental frequency of the crystal. The 74AS04 inverter

performs the 180-degree phase shift that a parallel

oscillator requires. The 4.7 kΩ resistor provides the

negative feedback for stability. The 10 kΩ potentiome-

ters bias the 74AS04 in the linear region. This circuit

could be used for external oscillator designs.

7.2.4

EXTERNAL RC OSCILLATOR

For timing insensitive applications, the RC device

option offers additional cost savings. The RC oscillator

frequency is a function of the supply voltage, the resis-

tor (REXT) and capacitor (CEXT) values, and the operat-

ing temperature. In addition to this, the oscillator

frequency will vary from unit-to-unit due to normal pro-

cess parameter variation. Furthermore, the difference

in lead frame capacitance between package types will

also affect the oscillation frequency, especially for low

CEXT values. The user also needs to take into account

variation due to tolerance of external R and C

components used.

Figure 7-5 shows how the R/C combination is

connected to the PIC12F508/509/16F505 devices. For

REXT values below 3.0 kΩ, the oscillator operation may

become unstable, or stop completely. For very high

REXT values (e.g., 1 MΩ), the oscillator becomes

sensitive to noise, humidity and leakage. Thus, we

recommend keeping REXT between 5.0 kΩ and

100 kΩ.

DS41236E-page 45

PIC12F508/509/16F505

Although the oscillator will operate with no external

capacitor (CEXT = 0pF), we recommend using values

above 20 pF for noise and stability reasons. With no or

small external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or

package lead frame capacitance.

In addition, a calibration instruction is programmed into

the last address of memory, which contains the

calibration value for the internal RC oscillator. This

location is always uncode protected, regardless of the

code-protect settings. This value is programmed as a

MOVLW XXinstruction where XXis the calibration value,

and is placed at the Reset vector. This will load the W

register with the calibration value upon Reset and the

PC will then roll over to the users program at address

0x000. The user then has the option of writing the value

to the OSCCAL Register (05h) or ignoring it.

Section 10.0 “Electrical Characteristics” shows RC

frequency variation from part-to-part due to normal

process variation. The variation is larger for larger val-

ues of R (since leakage current variation will affect RC

frequency more for large R) and for smaller values of C

(since variation of input capacitance will affect RC

frequency more).

OSCCAL, when written to with the calibration value, will

“trim” the internal oscillator to remove process variation

from the oscillator frequency.

Also, see the Electrical Specifications section for

variation of oscillator frequency due to VDD for given

REXT/CEXT values, as well as frequency variation due

to operating temperature for given R, C and VDD

values.

Note:

Erasing the device will also erase the pre-

programmed internal calibration value for

the internal oscillator. The calibration

value must be read prior to erasing the

part so it can be reprogrammed correctly

later.

FIGURE 7-5:

EXTERNAL RC

OSCILLATOR MODE

For the PIC12F508/509/16F505 devices, only bits

<7:1> of OSCCAL are implemented. Bits CAL6-CAL0

are used for calibration. Adjusting CAL6-CAL0 from

‘0000000’ to ‘1111111’ changes the clock speed. See

Register 4-5 for more information.

VDD

REXT

Internal

clock

OSC1

N

Note:

The 0 bit of OSCCAL is unimplemented

and should be written as ‘0’ when

modifying OSCCAL for compatibility with

future devices.

CEXT

VSS

PIC16F505

PIC12F508

PIC12F509

OSC2/CLKOUT

FOSC/4

7.2.5

INTERNAL 4 MHz RC OSCILLATOR

The internal RC oscillator provides a fixed 4 MHz

(nominal) system clock at VDD = 5V and 25°C, (see

Section 10.0 “Electrical Characteristics” for

information on variation over voltage and temperature).

DS41236E-page 46

PIC12F508/509/16F505

Some registers are not reset in any way, they are

unknown on POR and unchanged in any other Reset.

Most other registers are reset to “Reset state” on

Power-on Reset (POR), MCLR, WDT or Wake-up on

pin change Reset during normal operation. They are

not affected by a WDT Reset during Sleep or MCLR

Reset during Sleep, since these Resets are viewed as

resumption of normal operation. The exceptions to this

are TO, PD and RBWUF/GPWUF bits. They are set or

cleared differently in different Reset situations. These

bits are used in software to determine the nature of

Reset. See Table 7-4 for a full description of Reset

states of all registers.

7.3

Reset

The device differentiates between various kinds of

Reset:

• Power-on Reset (POR)

• MCLR Reset during normal operation

• MCLR Reset during Sleep

• WDT time-out Reset during normal operation

• WDT time-out Reset during Sleep

• Wake-up from Sleep on pin change

TABLE 7-3:

Register

RESET CONDITIONS FOR REGISTERS – PIC12F508/509

MCLR Reset, WDT Time-out,

Address

Power-on Reset

Wake-up On Pin Change

W

—

qqqq qqqu⁽¹⁾

xxxx xxxx

1111 1111

qqqq qqqu⁽¹⁾

uuuu uuuu

1111 1111

INDF

TMR0

PC

00h

01h

02h

STATUS

FSR⁽⁴⁾

03h

04h

0001 1xxx

110x xxxx

q00q quuu^{(2), (3)}

11uu uuuu

FSR⁽⁵⁾

OSCCAL

GPIO

04h

05h

06h

—

111x xxxx

1111 111-

--xx xxxx

1111 1111

--11 1111

111u uuuu

uuuu uuu-

--uu uuuu

1111 1111

--11 1111

OPTION

TRIS

—

Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’, q= value depends on condition.

Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XXinstruction at top of

memory.

2: See Table 7-5 for Reset value for specific conditions.

3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

4: PIC12F509 only.

5: PIC12F508 only.

DS41236E-page 47

PIC12F508/509/16F505

TABLE 7-4:

Register

RESET CONDITIONS FOR REGISTERS – PIC16F505

MCLR Reset, WDT Time-out,

Wake-up On Pin Change

Address

Power-on Reset

W

—

qqqq qqqu⁽¹⁾

xxxx xxxx

1111 1111

qqqq qqqu⁽¹⁾

uuuu uuuu

1111 1111

INDF

TMR0

PC

00h

01h

02h

STATUS

FSR

03h

04h

05h

06h

07h

—

0001 1xxx

100x xxxx

1111 111-

--xx xxxx

1111 1111

--11 1111

q00q quuu^{(2), (3)}

1uuu uuuu

uuuu uuu-

--uu uuuu

1111 1111

--11 1111

OSCCAL

PORTB

PORTC

OPTION

TRISB

—

TRISC

—

Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’, q= value depends on condition.

Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XXinstruction at top of

memory.

2: See Table 7-5 for Reset value for specific conditions.

3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

TABLE 7-5:

RESET CONDITION FOR SPECIAL REGISTERS

STATUS Addr: 03h

PCL Addr: 02h

Power-on Reset

0001 1xxx

1111 1111

MCLR Reset during normal operation

MCLR Reset during Sleep

000u uuuu

0001 0uuu

0000 0uuu

0000 uuuu

1001 0uuu

WDT Reset during Sleep

WDT Reset normal operation

Wake-up from Sleep on pin change

Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’.

DS41236E-page 48

PIC12F508/509/16F505

The Power-on Reset circuit and the Device Reset

Timer (see Section 7.5 “Device Reset Timer (DRT)”)

circuit are closely related. On power-up, the Reset latch

is set and the DRT is reset. The DRT timer begins

counting once it detects MCLR to be high. After the

time-out period, which is typically 18 ms, it will reset the

Reset latch and thus end the on-chip Reset signal.

7.3.1

MCLR ENABLE

This Configuration bit, when unprogrammed (left in the

‘1’ state), enables the external MCLR function. When

programmed, the MCLR function is tied to the internal

VDD and the pin is assigned to be an input only. See

Figure 7-6.

A power-up example where MCLR is held low is shown

in Figure 7-8. VDD is allowed to rise and stabilize before

bringing MCLR high. The chip will actually come out of

Reset TDRT msec after MCLR goes high.

FIGURE 7-6:

MCLR SELECT

GPWU/RBWU

(GP3/RB3)/MCLR/VPP

In Figure 7-9, the on-chip Power-on Reset feature is

being used (MCLR and VDD are tied together or the pin

is programmed to be (GP3/RB3). The VDD is stable

before the start-up timer times out and there is no prob-

lem in getting a proper Reset. However, Figure 7-10

depicts a problem situation where VDD rises too slowly.

The time between when the DRT senses that MCLR is

high and when MCLR and VDD actually reach their full

value, is too long. In this situation, when the start-up

timer times out, VDD has not reached the VDD (min)

value and the chip may not function correctly. For such

situations, we recommend that external RC circuits be

used to achieve longer POR delay times (Figure 7-9).

Internal MCLR

MCLRE

7.4

Power-on Reset (POR)

The PIC12F508/509/16F505 devices incorporate an

on-chip Power-on Reset (POR) circuitry, which

provides an internal chip Reset for most power-up

situations.

The on-chip POR circuit holds the chip in Reset until

VDD has reached a high enough level for proper

operation. To take advantage of the internal POR,

program the (GP3/RB3)/MCLR/VPP pin as MCLR and

tie through a resistor to VDD, or program the pin as

(GP3/RB3). An internal weak pull-up resistor is

implemented using a transistor (refer to Table 10-2 for

the pull-up resistor ranges). This will eliminate external

RC components usually needed to create a Power-on

Reset. A maximum rise time for VDD is specified. See

Section 10.0 “Electrical Characteristics” for details.

Note:

When the devices start normal operation

(exit the Reset condition), device operat-

ing parameters (voltage, frequency, tem-

perature, etc.) must be met to ensure

operation. If these conditions are not met,

the device must be held in Reset until the

operating conditions are met.

For additional information, refer to Application Notes

AN522 “Power-Up Considerations” (DS00522) and

AN607 “Power-up Trouble Shooting” (DS00607).

When the devices start normal operation (exit the

Reset condition), device operating parameters

(voltage, frequency, temperature,...) must be met to

ensure operation. If these conditions are not met, the

devices must be held in Reset until the operating

parameters are met.

A simplified block diagram of the on-chip Power-on

Reset circuit is shown in Figure 7-7.

DS41236E-page 49

PIC12F508/509/16F505

FIGURE 7-7:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

VDD

Power-up

Detect

POR (Power-on Reset)

MCLR Reset

(GP3/RB3)/MCLR/VPP

S

R

Q

MCLRE

WDT Reset

WDT Time-out

Start-up Timer

CHIP Reset

(10 μs or 18 ms)

Pin Change

Sleep

Wake-up on pin Change Reset

FIGURE 7-8:

TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)

VDD

MCLR

Internal POR

TDRT

DRT Time-out

Internal Reset

FIGURE 7-9:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE

TIME

VDD

MCLR

Internal POR

TDRT

DRT Time-out

Internal Reset

DS41236E-page 50

PIC12F508/509/16F505

FIGURE 7-10:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE

TIME

V1

VDD

MCLR

Internal POR

TDRT

DRT Time-out

Internal Reset

Note:

When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final

value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.

DS41236E-page 51

PIC12F508/509/16F505

TABLE 7-6:

DRT (DEVICE RESET TIMER

PERIOD)

7.5

Device Reset Timer (DRT)

On the PIC12F508/509/16F505 devices, the DRT runs

any time the device is powered up. DRT runs from

Reset and varies based on oscillator selection and

Reset type (see Table 7-6).

Oscillator

Configuration

Subsequent

POR Reset

Resets

INTOSC, EXTRC 18 ms (typical) 10 μs (typical)

The DRT operates on an internal RC oscillator. The

processor is kept in Reset as long as the DRT is active.

The DRT delay allows VDD to rise above VDD min. and

for the oscillator to stabilize.

HS⁽¹⁾, XT, LP

18 ms (typical) 18 ms (typical)

EC⁽¹⁾

18 ms (typical) 10 μs (typical)

Note 1: PIC16F505 only.

Oscillator circuits based on crystals or ceramic resona-

tors require a certain time after power-up to establish a

stable oscillation. The on-chip DRT keeps the devices in

a Reset condition for approximately 18 ms after MCLR

7.6.1 WDT PERIOD

The WDT has a nominal time-out period of 18 ms, (with

no prescaler). If a longer time-out period is desired, a

prescaler with a division ratio of up to 1:128 can be

assigned to the WDT (under software control) by

writing to the OPTION register. Thus, a time-out period

of a nominal 2.3 seconds can be realized. These

periods vary with temperature, VDD and part-to-part

process variations (see DC specs).

has reached

a

logic high (VIH MCLR) level.

Programming (GP3/RB3)/MCLR/VPP as MCLR and

using an external RC network connected to the MCLR

input is not required in most cases. This allows savings

in cost-sensitive and/or space restricted applications, as

well as allowing the use of the (GP3/RB3)/MCLR/VPP

pin as a general purpose input.

Under worst case conditions (VDD = Min., Temperature

= Max., max. WDT prescaler), it may take several

seconds before a WDT time-out occurs.

The Device Reset Time delays will vary from chip-to-

chip due to VDD, temperature and process variation.

See AC parameters for details.

7.6.2

WDT PROGRAMMING

CONSIDERATIONS

The DRT will also be triggered upon a Watchdog Timer

time-out from Sleep. This is particularly important for

applications using the WDT to wake from Sleep mode

automatically.

The CLRWDT instruction clears the WDT and the

postscaler, if assigned to the WDT, and prevents it from

timing out and generating a device Reset.

Reset sources are POR, MCLR, WDT time-out and

wake-up on pin change. See Section 7.9.2 “Wake-up

from Sleep”, Notes 1, 2 and 3.

The SLEEP instruction resets the WDT and the post-

scaler, if assigned to the WDT. This gives the maximum

Sleep time before a WDT wake-up Reset.

7.6

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip

RC oscillator, which does not require any external

components. This RC oscillator is separate from the

external RC oscillator of the (GP5/RB5)/OSC1/CLKIN

pin and the internal 4 MHz oscillator. This means that

the WDT will run even if the main processor clock has

been stopped, for example, by execution of a SLEEP

instruction. During normal operation or Sleep, a WDT

Reset or wake-up Reset, generates a device Reset.

The TO bit (STATUS<4>) will be cleared upon a

Watchdog Timer Reset.

The WDT can be permanently disabled by

programming the configuration WDTE as a ‘0’ (see

Section 7.1 “Configuration Bits”). Refer to the

PIC12F508/509/16F505 Programming Specifications

to determine how to access the Configuration Word.

DS41236E-page 52

PIC12F508/509/16F505

FIGURE 7-11:

WATCHDOG TIMER BLOCK DIAGRAM

From Timer0 Clock Source

(Figure 6-5)

0

M

U

X

Postscaler

8-to-1 MUX

1

Watchdog

Time

PS<2:0>

PSA

WDT Enable

Configuration

(Figure 6-4)

To Timer0

Bit

0

1

MUX

PSA

WDT Time-out

Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.

TABLE 7-7:

Address

SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Value on

All Other

Resets

Name

Bit 7

Bit 6

Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On

Reset

N/A

OPTION⁽¹⁾GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

OPTION⁽²⁾RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: Shaded boxes = Not used by Watchdog Timer. – = unimplemented, read as ‘0’, u= unchanged.

Note 1: PIC12F508/509 only.

2: PIC16F505 only.

DS41236E-page 53

PIC12F508/509/16F505

FIGURE 7-13:

BROWN-OUT

PROTECTION CIRCUIT 2

7.7

Time-out Sequence, Power-down

and Wake-up from Sleep Status

Bits (TO, PD, GPWUF/RBWUF)

VDD

The TO, PD and (GPWUF/RBWUF) bits in the

STATUS register can be tested to determine if a Reset

condition has been caused by a Power-up condition, a

MCLR or Watchdog Timer (WDT) Reset.

R1

R2

PIC16F505

PIC12F508

PIC12F509

Q1

(2)

MCLR

(1)

40k

TABLE 7-8:

TO/PD/(GPWUF/RBWUF)

STATUS AFTER RESET

GPWUF/

RBWUF

TO PD

Reset Caused By

Note 1: This brown-out circuit is less expensive,

although less accurate. Transistor Q1 turns

off when VDD is below a certain level such

that:

0

u

WDT wake-up from Sleep

WDT time-out (not from

Sleep)

R1

= 0.7V

VDD •

0

1

u

1

0

1

u

0

MCLR wake-up from Sleep

Power-up

R1 + R2

2: Pin must be confirmed as MCLR.

MCLR not during Sleep

Wake-up from Sleep on pin

change

FIGURE 7-14:

BROWN-OUT

PROTECTION CIRCUIT 3

Legend: u= unchanged

VDD

Note 1: The TO, PD and GPWUF/RBWUF bits

maintain their status (u) until a Reset

occurs. A low-pulse on the MCLR input

does not change the TO, PD and

MCP809

VDD

Bypass

Capacitor

VSS

VDD

GPWUF/RBWUF Status bits.

RST

MCLR

PIC16F505

PIC12F508

PIC12F509

7.8

Reset on Brown-out

A brown-out is a condition where device power (VDD)

dips below its minimum value, but not to zero, and then

recovers. The device should be reset in the event of a

brown-out.

Note:

This brown-out protection circuit employs

Microchip Technology’s MCP809 micro-

controller supervisor. There are 7 different

trip point selections to accommodate 5V to

3V systems.

To reset PIC12F508/509/16F505 devices when a

brown-out occurs, external brown-out protection

circuits may be built, as shown in Figure 7-12 and

Figure 7-13.

FIGURE 7-12:

BROWN-OUT

PROTECTION CIRCUIT 1

VDD

33k

PIC16F505

PIC12F508

PIC12F509

Q1

(2)

MCLR

10k

(1)

40k

Note 1: This circuit will activate Reset when VDD goes

below Vz + 0.7V (where Vz = Zener voltage).

2: Pin must be confirmed as MCLR.

DS41236E-page 54

PIC12F508/509/16F505

7.9

Power-down Mode (Sleep)

7.10 Program Verification/Code

Protection

A device may be powered down (Sleep) and later

powered up (wake-up from Sleep).

If the code protection bit has not been programmed, the

on-chip program memory can be read out for

verification purposes.

7.9.1

SLEEP

The Power-Down mode is entered by executing a

SLEEPinstruction.

The first 64 locations and the last location (OSCCAL)

can be read, regardless of the code protection bit

setting.

If enabled, the Watchdog Timer will be cleared but

keeps running, the TO bit (STATUS<4>) is set, the PD

bit (STATUS<3>) is cleared and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, driving low or high-impedance).

The last memory location can be read regardless of the

code protection bit setting on the PIC12F508/509/

16F505 devices.

7.11 ID Locations

Note:

A Reset generated by a WDT time-out

does not drive the MCLR pin low.

Four memory locations are designated as ID locations

where the user can store checksum or other code

identification numbers. These locations are not

accessible during normal execution, but are readable

and writable during Program/Verify.

For lowest current consumption while powered down,

the T0CKI input should be at VDD or VSS and the

(GP3/RB3)/MCLR/VPP pin must be at a logic high

level if MCLR is enabled.

Use only the lower 4 bits of the ID locations and always

program the upper 8 bits as ‘0’s.

7.9.2

WAKE-UP FROM SLEEP

The device can wake-up from Sleep through one of

the following events:

7.12 In-Circuit Serial Programming™

The PIC12F508/509/16F505 microcontrollers can be

serially programmed while in the end application circuit.

This is simply done with two lines for clock and data,

and three other lines for power, ground and the

programming voltage. This allows customers to manu-

facture boards with unprogrammed devices and then

program the microcontroller just before shipping the

product. This also allows the most recent firmware, or

a custom firmware, to be programmed.

1. An external Reset input on (GP3/RB3)/MCLR/

VPP pin, when configured as MCLR.

2. A Watchdog Timer time-out Reset (if WDT was

enabled).

3. A change on input pin GP0/RB0, GP1/RB1,

GP3/RB3 or RB4 when wake-up on change is

enabled.

These events cause a device Reset. The TO, PD and

GPWUF/RBWUF bits can be used to determine the

cause of device Reset. The TO bit is cleared if a WDT

time-out occurred (and caused wake-up). The PD bit,

which is set on power-up, is cleared when SLEEP is

invoked. The GPWUF/RBWUF bit indicates a change

in state while in Sleep at pins GP0/RB0, GP1/RB1,

GP3/RB3 or RB4 (since the last file or bit operation on

GP/RB port).

The devices are placed into a Program/Verify mode by

holding the GP1/RB1 and GP0/RB0 pins low while

raising the MCLR (VPP) pin from VIL to VIHH (see

programming specification). GP1/RB1 becomes the

programming clock and GP0/RB0 becomes the

programming data. Both GP1/RB1 and GP0/RB0 are

Schmitt Trigger inputs in this mode.

After Reset, a 6-bit command is then supplied to the

device. Depending on the command, 14 bits of program

data are then supplied to or from the device, depending

if the command was a Load or a Read. For complete

details of serial programming, please refer to the

PIC12F508/509/16F505 Programming Specifications.

Note:

Caution: Right before entering Sleep,

read the input pins. When in Sleep, wake-

up occurs when the values at the pins

change from the state they were in at the

last reading. If a wake-up on change

occurs and the pins are not read before re-

entering Sleep, a wake-up will occur

immediately even if no pins change while

in Sleep mode.

A typical In-Circuit Serial Programming connection is

shown in Figure 7-15.

The WDT is cleared when the device wakes from

Sleep, regardless of the wake-up source.

DS41236E-page 55

PIC12F508/509/16F505

FIGURE 7-15:

TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING

CONNECTION

To Normal

Connections

PIC16F505

PIC12F508

PIC12F509

External

Connector

Signals

+5V

0V

VDD

VSS

VPP

MCLR/VPP

GP1/RB1

GP0/RB0

CLK

Data I/O

VDD

To Normal

Connections

DS41236E-page 56

PIC12F508/509/16F505

All instructions are executed within a single instruction

cycle, unless a conditional test is true or the program

counter is changed as a result of an instruction. In this

case, the execution takes two instruction cycles. One

instruction cycle consists of four oscillator periods.

Thus, for an oscillator frequency of 4 MHz, the normal

instruction execution time is 1 μs. If a conditional test is

true or the program counter is changed as a result of an

instruction, the instruction execution time is 2 μs.

8.0

INSTRUCTION SET SUMMARY

The PIC16 instruction set is highly orthogonal and is

comprised of three basic categories.

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations

Each PIC16 instruction is a 12-bit word divided into an

opcode, which specifies the instruction type, and one

or more operands which further specify the operation

of the instruction. The formats for each of the catego-

ries is presented in Figure 8-1, while the various

opcode fields are summarized in Table 8-1.

Figure 8-1 shows the three general formats that the

instructions can have. All examples in the figure use

the following format to represent a hexadecimal

number:

0xhhh

For byte-oriented instructions, ‘f’ represents a file

register designator and ‘d’ represents a destination

designator. The file register designator specifies which

file register is to be used by the instruction.

where ‘h’ signifies a hexadecimal digit.

FIGURE 8-1:

GENERAL FORMAT FOR

INSTRUCTIONS

The destination designator specifies where the result of

the operation is to be placed. If ‘d’ is ‘0’, the result is

placed in the W register. If ‘d’ is ‘1’, the result is placed

in the file register specified in the instruction.

Byte-oriented file register operations

11

6

5

d

4

0

OPCODE

f (FILE #)

For bit-oriented instructions, ‘b’ represents a bit field

designator which selects the number of the bit affected

by the operation, while ‘f’ represents the number of the

file in which the bit is located.

d = 0for destination W

d = 1for destination f

f = 5-bit file register address

Bit-oriented file register operations

11 8 7

b (BIT #)

For literal and control operations, ‘k’ represents an

8 or 9-bit constant or literal value.

5

4

0

OPCODE

f (FILE #)

b = 3-bit bit address

f = 5-bit file register address

TABLE 8-1:

OPCODE FIELD

DESCRIPTIONS

Literal and control operations (except GOTO)

11

Field

Description

8

7

0

f

W

b

Register file address (0x00 to 0x7F)

Working register (accumulator)

OPCODE

k (literal)

Bit address within an 8-bit file register

Literal field, constant data or label

k = 8-bit immediate value

k

Literal and control operations – GOTOinstruction

11

x

Don’t care location (= 0or 1)

The assembler will generate code with x = 0. It is

the recommended form of use for compatibility with

all Microchip software tools.

9

8

0

OPCODE

k (literal)

d

Destination select;

k = 9-bit immediate value

d = 0(store result in W)

d = 1(store result in file register ‘f’)

Default is d = 1

label

TOS

PC

Label name

Top-of-Stack

Program Counter

Watchdog Timer counter

Time-out bit

WDT

TO

PD

Power-down bit

dest

Destination, either the W register or the specified

register file location

[ ]

( )

→

< >

∈

Options

Contents

Assigned to

Register bit field

In the set of

italics User defined term (font is courier)

DS41236E-page 57

PIC12F508/509/16F505

TABLE 8-2:

INSTRUCTION SET SUMMARY

Description

12-Bit Opcode

MSb LSb

Mnemonic,

Operands

Status

Affected

Cycles

Notes

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

f, d

f

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate left f through Carry

Rotate right f through Carry

Subtract W from f

Swap f

1

0001 11df ffff C, DC, Z 1, 2, 4

0001 01df ffff

0000 011f ffff

0000 0100 0000

0010 01df ffff

0000 11df ffff

0010 11df ffff

0010 10df ffff

0011 11df ffff

0001 00df ffff

0010 00df ffff

0000 001f ffff

0000 0000 0000

0011 01df ffff

0011 00df ffff

Z

None

Z

None

Z

2, 4

4

—

f, d

f

1

2, 4

1, 4

1⁽²⁾

1

1⁽²⁾

1

Z

None

C

—

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

2, 4

C

0000 10df ffff C, DC, Z 1, 2, 4

0011 10df ffff

0001 10df ffff

None

Z

2, 4

Exclusive OR W with f

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1

0100 bbbf ffff

None

2, 4

0101 bbbf ffff

0110 bbbf ffff

0111 bbbf ffff

1⁽²⁾

LITERAL AND CONTROL OPERATIONS

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

OPTION

RETLW

SLEEP

TRIS

k

—

k

—

k

—

f

k

AND literal with W

Call Subroutine

1

2

1

2

1

2

1

1110 kkkk kkkk

1001 kkkk kkkk

0000 0000 0100 TO, PD

101k kkkk kkkk

1101 kkkk kkkk

1100 kkkk kkkk

0000 0000 0010

1000 kkkk kkkk

Z

None

1

3

Clear Watchdog Timer

Unconditional branch

Inclusive OR literal with W

Move literal to W

Load OPTION register

Return, place literal in W

Go into Standby mode

Load TRIS register

None

Z

None

0000 0000 0011 TO, PD

0000 0000 0fff

1111 kkkk kkkk

None

Z

XORLW

Exclusive OR literal to W

Note 1: The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for

GOTO. See Section 4.7 “Program Counter”.

2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that

value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and

is driven low by an external device, the data will be written back with a ‘0’.

3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state

latches of PORTB. A ‘1’ forces the pin to a high-impedance state and disables the output buffers.

4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be

cleared (if assigned to TMR0).

DS41236E-page 58

PIC12F508/509/16F505

ADDWF

Add W and f

BCF

Bit Clear f

Syntax:

[ label ] ADDWF f,d

Syntax:

[ label ] BCF f,b

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operation:

(W) + (f) → (dest)

Operation:

0 → (f<b>)

Status Affected: C, DC, Z

Status Affected: None

Description:

Add the contents of the W register

Description:

Bit ‘b’ in register ‘f’ is cleared.

and register ‘f’. If ‘d’ is’0’, the result

is stored in the W register. If ‘d’ is

‘1’, the result is stored back in

register ‘f’.

ANDLW

AND literal with W

BSF

Bit Set f

Syntax:

[ label ] ANDLW

0 ≤ k ≤ 255

k

Syntax:

[ label ] BSF f,b

Operands:

Operation:

Operands:

0 ≤ f ≤ 31

0 ≤ b ≤ 7

(W).AND. (k) → (W)

Operation:

1 → (f<b>)

Status Affected: Z

Status Affected: None

Description:

The contents of the W register are

AND’ed with the eight-bit literal ‘k’.

The result is placed in the W

register.

Description: Bit ‘b’ in register ‘f’ is set.

BTFSC

Bit Test f, Skip if Clear

ANDWF

AND W with f

Syntax:

[ label ] BTFSC f,b

Syntax:

[ label ] ANDWF f,d

Operands:

0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

skip if (f<b>) = 0

Operation:

(W) .AND. (f) → (dest)

Status Affected: None

Status Affected: Z

Description: If bit ‘b’ in register ‘f’ is ‘0’, then the

Description: The contents of the W register are

next instruction is skipped.

AND’ed with register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W register.

If ‘d’ is ‘1’, the result is stored back

in register ‘f’.

If bit ‘b’ is ‘0’, then the next instruc-

tion fetched during the current

instruction execution is discarded,

and a NOPis executed instead,

making this a two-cycle instruction.

DS41236E-page 59

PIC12F508/509/16F505

CLRW

Clear W

BTFSS

Bit Test f, Skip if Set

Syntax:

[ label ] CLRW

None

Syntax:

[ label ] BTFSS f,b

Operands:

Operation:

Operands:

0 ≤ f ≤ 31

0 ≤ b < 7

00h → (W);

1 → Z

Operation:

skip if (f<b>) = 1

Status Affected:

Description:

Z

Status Affected: None

The W register is cleared. Zero bit

(Z) is set.

Description:

If bit ‘b’ in register ‘f’ is ‘1’, then the

next instruction is skipped.

If bit ‘b’ is ‘1’, then the next instruc-

tion fetched during the current

instruction execution, is discarded

and a NOPis executed instead,

making this a two-cycle instruction.

CLRWDT

Syntax:

Clear Watchdog Timer

[ label ] CLRWDT

None

CALL

Subroutine Call

[ label ] CALL k

0 ≤ k ≤ 255

Syntax:

Operands:

Operation:

Operands:

Operation:

00h → WDT;

0 → WDT prescaler (if assigned);

1 → TO;

1 → PD

(PC) + 1→ Top-of-Stack;

k → PC<7:0>;

(STATUS<6:5>) → PC<10:9>;

0 → PC<8>

Status Affected: TO, PD

Status Affected: None

Description:

The CLRWDTinstruction resets the

Description:

Subroutine call. First, return

WDT. It also resets the prescaler, if

the prescaler is assigned to the

WDT and not Timer0. Status bits

TO and PD are set.

address (PC + 1) is PUSHed onto

the stack. The eight-bit immediate

address is loaded into PC

bits <7:0>. The upper bits

PC<10:9> are loaded from

STATUS<6:5>, PC<8> is cleared.

CALLis a two-cycle instruction.

CLRF

Clear f

COMF

Complement f

Syntax:

[ label ] CLRF

0 ≤ f ≤ 31

f

Syntax:

Operands:

[ label ] COMF f,d

Operands:

Operation:

0 ≤ f ≤ 31

d ∈ [0,1]

00h → (f);

1 → Z

Operation:

(f) → (dest)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

The contents of register ‘f’ are

cleared and the Z bit is set.

The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the

result is stored in the W register. If

‘d’ is ‘1’, the result is stored back in

register ‘f’.

DS41236E-page 60

PIC12F508/509/16F505

DECF

Decrement f

INCF

Increment f

Syntax:

Operands:

[ label ] DECF f,d

Syntax:

Operands:

[ label ] INCF f,d

0 ≤ f ≤ 31

d ∈ [0,1]

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

(f) – 1 → (dest)

Operation:

(f) + 1 → (dest)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

INCFSZ

Syntax:

Increment f, Skip if 0

DECFSZ

Syntax:

Decrement f, Skip if 0

[ label ] INCFSZ f,d

[ label ] DECFSZ f,d

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

(f) + 1 → (dest), skip if result = 0

Operation:

(f) – 1 → d; skip if result = 0

Status Affected: None

Description:

The contents of register ‘f’ are

Description:

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

decremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

If the result is ‘0’, then the next

instruction, which is already

fetched, is discarded and a NOPis

executed instead making it a

two-cycle instruction.

If the result is ‘0’, the next instruc-

tion, which is already fetched, is

discarded and a NOPis executed

instead making it a two-cycle

instruction.

IORLW

Inclusive OR literal with W

[ label ] IORLW k

0 ≤ k ≤ 255

GOTO

Unconditional Branch

[ label ] GOTO k

0 ≤ k ≤ 511

Syntax:

Operands:

Operation:

Status Affected:

Description:

Operands:

Operation:

(W) .OR. (k) → (W)

Z

k → PC<8:0>;

STATUS<6:5> → PC<10:9>

Status Affected: None

The contents of the W register are

OR’ed with the eight-bit literal ‘k’.

The result is placed in the

W register.

Description: GOTOis an unconditional branch.

The 9-bit immediate value is

loaded into PC bits <8:0>. The

upper bits of PC are loaded from

STATUS<6:5>. GOTOis a two-

cycle instruction.

DS41236E-page 61

PIC12F508/509/16F505

IORWF

Inclusive OR W with f

MOVWF

Syntax:

Move W to f

[ label ] MOVWF

0 ≤ f ≤ 31

Syntax:

[ label ] IORWF f,d

f

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

Operation:

(W) → (f)

Operation:

(W).OR. (f) → (dest)

Status Affected: None

Status Affected:

Description:

Z

Description:

Move data from the W register to

register ‘f’.

Inclusive OR the W register with

register ‘f’. If ‘d’ is ‘0’, the result is

placed in the W register. If ‘d’ is ‘1’,

the result is placed back in register

‘f’.

MOVF

Move f

NOP

No Operation

[ label ] NOP

None

Syntax:

Operands:

[ label ] MOVF f,d

Syntax:

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

Operation:

No operation

Operation:

(f) → (dest)

Status Affected: None

Status Affected:

Description:

Z

Description:

No operation.

The contents of register ‘f’ are

moved to destination ‘d’. If ‘d’ is ‘0’,

destination is the W register. If ‘d’

is ‘1’, the destination is file

register ‘f’. ‘d’ = 1is useful as a

test of a file register, since status

flag Z is affected.

MOVLW

Syntax:

Move Literal to W

[ label ] MOVLW k

0 ≤ k ≤ 255

OPTION

Syntax:

Load OPTION Register

[ label ] OPTION

None

Operands:

Operation:

Operands:

Operation:

(W) → OPTION

k → (W)

Status Affected: None

Description: The content of the W register is

Description:

The eight-bit literal ‘k’ is loaded

into the W register. The “don’t

loaded into the OPTION register.

cares” will assembled as ‘0’s.

DS41236E-page 62

PIC12F508/509/16F505

RETLW

Return with Literal in W

[ label ] RETLW k

0 ≤ k ≤ 255

SLEEP

Enter SLEEP Mode

Syntax:

[label ]

SLEEP

Operands:

Operation:

Operands:

Operation:

None

k → (W);

TOS → PC

00h → WDT;

0 → WDT prescaler;

1 → TO;

Status Affected: None

0 → PD

Description:

The W register is loaded with the

Status Affected: TO, PD, RBWUF

eight-bit literal ‘k’. The program

counter is loaded from the top of

the stack (the return address). This

is a two-cycle instruction.

Description:

Time-out Status bit (TO) is set. The

Power-down Status bit (PD) is

cleared.

RBWUF is unaffected.

The WDT and its prescaler are

cleared.

The processor is put into Sleep

mode with the oscillator stopped.

See Section 7.9 “Power-down

Mode (Sleep)” on Sleep for more

details.

RLF

Rotate Left f through Carry

SUBWF

Subtract W from f

Syntax:

Operands:

[ label ]

RLF f,d

Syntax:

[label ] SUBWF f,d

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

See description below

C

Operation:

(f) – (W) → (dest)

Status Affected:

Description:

Status Affected: C, DC, Z

The contents of register ‘f’ are

rotated one bit to the left through

the Carry flag. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is stored back in

register ‘f’.

Description:

Subtract (2’s complement method)

the W register from register ‘f’. If ‘d’

is ‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

register ‘f’

C

RRF

Rotate Right f through Carry

SWAPF

Syntax:

Swap Nibbles in f

Syntax:

Operands:

[ label ] RRF f,d

[ label ] SWAPF f,d

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

See description below

C

Operation:

(f<3:0>) → (dest<7:4>);

(f<7:4>) → (dest<3:0>)

Status Affected:

Description:

Status Affected: None

The contents of register ‘f’ are

rotated one bit to the right through

the Carry flag. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

Description: The upper and lower nibbles of

register ‘f’ are exchanged. If ‘d’ is

‘0’, the result is placed in W

register. If ‘d’ is ‘1’, the result is

placed in register ‘f’.

register ‘f’

C

DS41236E-page 63

PIC12F508/509/16F505

TRIS

Load TRIS Register

XORWF

Syntax:

Exclusive OR W with f

Syntax:

[ label ] TRIS

f

[ label ] XORWF f,d

Operands:

Operation:

f = 6

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

(W) → TRIS register f

Status Affected: None

Operation:

(W) .XOR. (f) → (dest)

Description:

TRIS register ‘f’ (f = 6 or 7) is

loaded with the contents of the W

register

Status Affected:

Description:

Z

Exclusive OR the contents of the

W register with register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

XORLW

Exclusive OR literal with W

Syntax:

[label ] XORLW k

0 ≤ k ≤ 255

Operands:

Operation:

(W) .XOR. k → (W)

Z

Status Affected:

Description:

The contents of the W register are

XOR’ed with the eight-bit literal ‘k’.

The result is placed in the W

register.

DS41236E-page 64

PIC12F508/509/16F505

9.1

MPLAB Integrated Development

Environment Software

9.0

DEVELOPMENT SUPPORT

The PIC^®microcontrollers are supported with a full

range of hardware and software development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• Assemblers/Compilers/Linkers

- MPASM^TMAssembler

• A single graphical interface to all debugging tools

- Simulator

- MPLAB C18 and MPLAB C30 C Compilers

- MPLINK^TMObject Linker/

- Programmer (sold separately)

- Emulator (sold separately)

MPLIB^TMObject Librarian

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

• Emulators

• Customizable data windows with direct edit of

contents

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debugger

• High-level source code debugging

• Visual device initializer for easy register

initialization

- MPLAB ICD 2

• Mouse over variable inspection

• Device Programmers

• Drag and drop variables from source to watch

windows

- PICSTART^®Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Extensive on-line help

• Integration of select third party tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

The MPLAB IDE allows you to:

• Edit your source files (either assembly or C)

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools

(automatically updates all project information)

• Debug using:

- Source files (assembly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

DS41236E-page 65

PIC12F508/509/16F505

9.2

MPASM Assembler

9.5

MPLAB ASM30 Assembler, Linker

and Librarian

The MPASM Assembler is a full-featured, universal

macro assembler for all PIC MCUs.

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• User-defined macros to streamline

assembly code

• Rich directive set

• Conditional assembly for multi-purpose

source files

• Flexible macro language

• MPLAB IDE compatibility

• Directives that allow complete control over the

assembly process

9.6

MPLAB SIM Software Simulator

9.3

MPLAB C18 and MPLAB C30

C Compilers

The MPLAB SIM Software Simulator allows code

development in PC-hosted environment by

a

simulating the PIC MCUs and dsPIC^®DSCs on an

instruction level. On any given instruction, the data

areas can be examined or modified and stimuli can be

applied from a comprehensive stimulus controller.

Registers can be logged to files for further run-time

analysis. The trace buffer and logic analyzer display

extend the power of the simulator to record and track

program execution, actions on I/O, most peripherals

and internal registers.

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI compilers for

C

Microchip’s PIC18 and PIC24 families of microcon-

trollers and the dsPIC30 and dsPIC33 family of digital

signal controllers. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

9.4

MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

DS41236E-page 66

PIC12F508/509/16F505

9.7

MPLAB ICE 2000

High-Performance

In-Circuit Emulator

9.9

MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash PIC

MCUs and can be used to develop for these and other

PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes

the in-circuit debugging capability built into the Flash

devices. This feature, along with Microchip’s In-Circuit

Serial Programming^TM(ICSP^TM) protocol, offers cost-

effective, in-circuit Flash debugging from the graphical

user interface of the MPLAB Integrated Development

Environment. This enables a designer to develop and

debug source code by setting breakpoints, single step-

ping and watching variables, and CPU status and

peripheral registers. Running at full speed enables

testing hardware and applications in real time. MPLAB

ICD 2 also serves as a development programmer for

selected PIC devices.

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PIC

microcontrollers. Software control of the MPLAB ICE

2000 In-Circuit Emulator is advanced by the MPLAB

Integrated Development Environment, which allows

editing, building, downloading and source debugging

from a single environment.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing features. Interchangeable processor modules allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PIC microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft^®Windows^®32-bit operating system were

chosen to best make these features available in a

simple, unified application.

9.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an SD/MMC card for

file storage and secure data applications.

9.8

MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC^®Flash MCUs and dsPIC^®Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated Development Environment (IDE),

included with each kit.

The MPLAB REAL ICE probe is connected to the design

engineer’s PC using a high-speed USB 2.0 interface and

is connected to the target with either a connector

compatible with the popular MPLAB ICD 2 system

(RJ11) or with the new high-speed, noise tolerant, Low-

Voltage Differential Signal (LVDS) interconnection

(CAT5).

MPLAB REAL ICE is field upgradeable through future

firmware downloads in MPLAB IDE. In upcoming

releases of MPLAB IDE, new devices will be supported,

and new features will be added, such as software break-

points and assembly code trace. MPLAB REAL ICE

offers significant advantages over competitive emulators

including low-cost, full-speed emulation, real-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables.

DS41236E-page 67

PIC12F508/509/16F505

9.11 PICSTART Plus Development

Programmer

9.13 Demonstration, Development and

Evaluation Boards

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PIC devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76X, may be supported with an adapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

9.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer and selected Flash device debugger with

an easy-to-use interface for programming many of

Microchip’s baseline, mid-range and PIC18F families

of Flash memory microcontrollers. The PICkit 2 Starter

Kit includes a prototyping development board, twelve

sequential lessons, software and HI-TECH’s PICC™

Lite C compiler, and is designed to help get up to speed

quickly using PIC^®microcontrollers. The kit provides

everything needed to program, evaluate and develop

applications using Microchip’s powerful, mid-range

Flash memory family of microcontrollers.

In addition to the PICDEM™ and dsPICDEM™

demonstration/development board series of circuits,

Microchip has

a

line of evaluation kits and

demonstration software for analog filter design,

®

KEELOQ security ICs, CAN, IrDA^®, PowerSmart

battery management, SEEVAL^®evaluation system,

Sigma-Delta ADC, flow rate sensing, plus many more.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

DS41236E-page 68

PIC12F508/509/16F505

10.0 ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

Ambient temperature under bias..........................................................................................................-40°C to +125°C

Storage temperature ............................................................................................................................-65°C to +150°C

Voltage on VDD with respect to VSS ...............................................................................................................0 to +6.5V

Voltage on MCLR with respect to VSS..........................................................................................................0 to +13.5V

Voltage on all other pins with respect to VSS ............................................................................... -0.3V to (VDD + 0.3V)

Total power dissipation⁽¹⁾..................................................................................................................................800 mW

Max. current out of VSS pin ................................................................................................................................200 mA

Max. current into VDD pin...................................................................................................................................150 mA

Input clamp current, IIK (VI < 0 or VI > VDD)................................................................................................................... 20 mA

Output clamp current, IOK (VO < 0 or VO > VDD) ........................................................................................................... 20 mA

Max. output current sunk by any I/O pin ..............................................................................................................25 mA

Max. output current sourced by any I/O pin.........................................................................................................25 mA

Max. output current sourced by I/O port ..............................................................................................................75 mA

Max. output current sunk by I/O port ...................................................................................................................75 mA

Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)

^†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above

those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions

for extended periods may affect device reliability.

DS41236E-page 69

PIC12F508/509/16F505

FIGURE 10-1:

6.0

PIC12F508/509/16F505 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C

5.5

(PIC16F505 only)

5.0

4.5

4.0

3.5

VDD

(Volts)

3.0

2.5

2.0

0

4

8

10

20

25

Frequency (MHz)

FIGURE 10-2:

MAXIMUM OSCILLATOR FREQUENCY TABLE

LP

XT

INTOSC

EXTRC

EC⁽¹⁾

HS⁽¹⁾

0

200 kHz

4 MHz

20 MHz

Frequency (MHz)

Note 1: For PIC16F505 only.

DS41236E-page 70

PIC12F508/509/16F505

10.1 DC Characteristics: PIC12F508/509/16F505 (Industrial)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)

DC Characteristics

Param

Sym.

No.

Characteristic

Min. Typ⁽¹⁾Max. Units

Conditions

D001

D002

D003

VDD Supply Voltage

VDR RAM Data Retention Voltage⁽²⁾

2.0

—

5.5

—

V

See Figure 10-1

1.5*

Vss

Device in Sleep mode

VPOR VDD Start Voltage to ensure

—

See Section 7.4 "Power-on

Reset (POR)" for details

Power-on Reset

D004

D010

SVDD VDD Rise Rate to ensure

Power-on Reset

IDD Supply Current^(3,4)

0.05*

—

V/ms See Section 7.4 "Power-on

Reset (POR)" for details

—

175

0.625 1.1

275

μA

FOSC = 4 MHz, VDD = 2.0V

FOSC = 4 MHz, VDD = 5.0V

mA

—

500

1.5

650

2.2

μA

mA

FOSC = 10 MHz, VDD = 3.0V

FOSC = 20 MHz, VDD = 5.0V

(PIC16F505 only)

—

11

38

20

54

μA

FOSC = 32 kHz, VDD = 2.0V

FOSC = 32 kHz, VDD = 5.0V

D020

D022

IPD Power-down Current⁽⁵⁾

IWDT WDT Current⁽⁵⁾

—

0.1

0.35

1.2

2.4

μA

VDD = 2.0V

VDD = 5.0V

—

1.0

7.0

3.0

16.0

μA

VDD = 2.0V

VDD = 5.0V

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design

guidance only and is not tested.

2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current consumption.

4: The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR =

VDD; WDT enabled/disabled as specified.

5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep

mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep.

DS41236E-page 71

PIC12F508/509/16F505

10.2 DC Characteristics: PIC12F508/509/16F505 (Extended)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +125°C (extended)

DC Characteristics

Param

Sym.

No.

Characteristic

Min. Typ⁽¹⁾Max. Units

Conditions

D001

D002

D003

VDD Supply Voltage

VDR RAM Data Retention Voltage⁽²⁾

2.0

—

5.5

—

V

See Figure 10-1

1.5*

Vss

Device in Sleep mode

VPOR VDD Start Voltage to ensure

—

See Section 7.4 "Power-on

Reset (POR)" for details

Power-on Reset

D004

D010

SVDD VDD Rise Rate to ensure

Power-on Reset

IDD Supply Current^(3,4)

0.05*

—

V/ms See Section 7.4 "Power-on

Reset (POR)" for details

—

175

0.625 1.1

275

μA

FOSC = 4 MHz, VDD = 2.0V

FOSC = 4 MHz, VDD = 5.0V

mA

—

500

1.5

650

2.2

μA

mA

FOSC = 10 MHz, VDD = 3.0V

FOSC = 20 MHz, VDD = 5.0V

(PIC16F515 only)

—

11

38

26

110

μA

FOSC = 32 kHz, VDD = 2.0V

FOSC = 32 kHz, VDD = 5.0V

D020

D022

IPD Power-down Current⁽⁵⁾

IWDT WDT Current⁽⁵⁾

—

0.1

0.35 15.0

9.0

μA

VDD = 2.0V

VDD = 5.0V

—

1.0

7.0

18

22

μA

VDD = 2.0V

VDD = 5.0V

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design

guidance only and is not tested.

2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current consumption.

4: The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR =

VDD; WDT enabled/disabled as specified.

5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep

mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep.

DS41236E-page 72

PIC12F508/509/16F505

TABLE 10-1: DC CHARACTERISTICS: PIC12F508/509/16F505 (Industrial, Extended)

Standard Operating Conditions (unless otherwise specified)

Operating temperature -40°C ≤ TA ≤ +85°C (industrial)

DC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C (extended)

Operating voltage VDD range as described in DC specification

Param

No.

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

VIL

Input Low Voltage

I/O ports:

with TTL buffer

D030

D030A

D031

D032

D033

Vss

—

0.8V

V

For all 4.5 ≤ VDD ≤ 5.5V

0.15 VDD

0.3 VDD

0.3

Otherwise

with Schmitt Trigger buffer

MCLR, T0CKI

OSC1 (in EXTRC)

OSC1 (in HS)

(Note1)

OSC1 (in XT and LP)

Input High Voltage

I/O ports:

VIH

—

D040

with TTL buffer

2.0

VDD

V

4.5 ≤ VDD ≤ 5.5V

D040A

0.25 VDD

+ 0.8

Otherwise

D041

D042

D043

D070

with Schmitt Trigger buffer

0.85 VDD

0.7 VDD

1.6

—

VDD

400

V

For entire VDD range

MCLR, T0CKI

OSC1 (in EXTRC)

OSC1 (in HS)

—

V

(Note1)

—

V

OSC1 (in XT and LP)

—

V

IPUR GPIO/PORTB weak pull-up

50

250

μA

VDD = 5V, VPIN = VSS

current⁽⁴⁾

IIL

Input Leakage Current^{(2), (3)}

D060

D061

D063

I/O ports

—

± 0.7

—

± 1

± 5

μA

Vss ≤ VPIN ≤ VDD, Pin at high-impedance

Vss ≤ VPIN ≤ VDD

GP3/RB3/MCLRI⁽⁵⁾

OSC1

Vss ≤ VPIN ≤ VDD, XT, HS and LP oscillator

configuration

Output Low Voltage

D080

I/O ports/CLKOUT

—

0.6

V

IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C

IOL = 7.0 mA, VDD = 4.5V, -40°C to +125°C

IOL = 1.6 mA, VDD = 4.5V, -40°C to +85°C

IOL = 1.2 mA, VDD = 4.5V, -40°C to +125°C

D080A

D083

OSC2

D083A

Output High Voltage

D090

I/O ports/CLKOUT⁽³⁾

VDD – 0.7

—

V

IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C

IOH = -2.5 mA, VDD = 4.5V, -40°C to +125°C

IOH = -1.3 mA, VDD = 4.5V, -40°C to +85°C

IOH = -1.0 mA, VDD = 4.5V, -40°C to +125°C

D090A

D092

OSC2

D092A

Capacitive Loading Specs on

Output Pins

D100

D101

OSC2 pin

—

15

50

pF

In XT, HS and LP modes when external clock is

used to drive OSC1.

All I/O pins and OSC2

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12F508/509/

16F505 be driven with external clock in RC mode.

Note 1:

2:

The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating

conditions. Higher leakage current may be measured at different input voltages.

3:

4:

Negative current is defined as coming out of the pin.

The specification applies to all weak pull-up devices, including the weak pull-up on GP3/MCLR. The current listed will be the same

whether GP3/MCLR is configured as GP3 with a weak pull-up or enabled as MCLR.

5:

This specification applies when GP3/RB3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit

is higher than the standard I/O logic.

DS41236E-page 73

PIC12F508/509/16F505

TABLE 10-2: PULL-UP RESISTOR RANGES – PIC12F508/509/16F505

VDD (Volts)

Temperature (°C)

Min.

Typ.

Max.

GP0(RBO)/GP1(RB1)

2.0

–40

25

73K

82K

86K

15K

19K

23K

105K

113K

123K

132k

21K

186K

187K

190K

33K

85

125

–40

25

5.5

22K

34K

85

26k

35K

125

29K

35K

GP3(RB3)

2.0

–40

25

63K

77K

82K

86K

16K

24K

26K

81K

93K

96k

96K

116K

119K

22K

85

125

–40

25

100K

20k

5.5

21K

25k

23K

85

28K

125

27K

29K

*

These parameters are characterized but not tested.

DS41236E-page 74

PIC12F508/509/16F505

10.3 Timing Parameter Symbology and Load Conditions – PIC12F508/509/16F505

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

T Time

Lowercase subscripts (pp) and their meanings:

pp

2

to

mc

osc

os

MCLR

ck

cy

drt

io

CLKOUT

Cycle time

Device Reset Timer

I/O port

Oscillator

OSC1

t0

T0CKI

wdt

Watchdog Timer

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (high-impedance)

Low

Valid

L

High-impedance

FIGURE 10-3:

LOAD CONDITIONS – PIC12F508/509/16F505

Legend:

CL

CL = 50 pF for all pins except OSC2

15 pF for OSC2 in XT, HS or LP

modes when external clock

is used to drive OSC1

VSS

FIGURE 10-4:

EXTERNAL CLOCK TIMING – PIC12F508/509/16F505

Q4

Q3

Q4

Q1

Q2

OSC1

1

3

4

2

DS41236E-page 75

PIC12F508/509/16F505

TABLE 10-3: EXTERNAL CLOCK TIMING REQUIREMENTS – PIC12F508/509/16F505

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial),

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 10.1 "Power-

on Reset (POR)"

Param

Sym.

Characteristic

Min. Typ⁽¹⁾

Max. Units

Conditions

No.

1A

FOSC External CLKIN Frequency⁽²⁾DC

DC

—

4

MHz XT Oscillator mode

20

MHz EC, HS Oscillator mode

(PIC16F505 only)

DC

—

200

4

kHz LP Oscillator mode

MHz EXTRC Oscillator mode

MHz XT Oscillator mode

Oscillator Frequency⁽²⁾

—

0.1

4

20

MHz HS Oscillator mode (PIC16F505

only)

—

250

50

—

200

—

kHz LP Oscillator mode

ns XT Oscillator mode

1

TOSC

External CLKIN Period⁽²⁾

Oscillator Period⁽²⁾

—

ns EC, HS Oscillator mode

(PIC16F505 only)

5

—

μs LP Oscillator mode

250

ns EXTRC Oscillator mode

10,000 ns XT Oscillator mode

50

5

—

250

ns HS Oscillator mode (PIC16F505

only)

—

μs LP Oscillator mode

ns

2

3

TCY

Instruction Cycle Time

200 4/FOSC

TosL, Clock in (OSC1) Low or High 50*

—

ns XT Oscillator

μs LP Oscillator

TosH Time

2*

10*

ns EC, HS Oscillator

(PIC16F505 only)

4

TosR, Clock in (OSC1) Rise or Fall

TosF Time

—

25*

50*

15*

ns XT Oscillator

ns LP Oscillator

ns EC, HS Oscillator

(PIC16F505 only)

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for

design guidance only and are not tested.

2: All specified values are based on characterization data for that particular oscillator type under standard

operating conditions with the device executing code. Exceeding these specified limits may result in an

unstable oscillator operation and/or higher than expected current consumption. When an external clock

input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

DS41236E-page 76

PIC12F508/509/16F505

TABLE 10-4: CALIBRATED INTERNAL RC FREQUENCIES – PIC12F508/509/16F505

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial),

-40°C ≤ TA ≤ +125°C (extended)

AC CHARACTERISTICS

Param

Freq

Tolerance

Sym.

Characteristic

Min. Typ† Max. Units

Conditions

No.

F10

FOSC

Internal Calibrated

1%

2%

3.96 4.00

3.92 4.00

4.04 MHz VDD = 3.5V, TA = 25°C

INTOSC Frequency⁽¹⁾

4.08 MHz 2.5V ≤ VDD ≤ 5.5V

0°C ≤ TA ≤ +85°C

5%

3.80 4.00

4.20 MHz 2.0V ≤ VDD ≤ 5.5V

-40°C ≤ TA ≤ +85°C (Ind.)

-40°C ≤ TA ≤ +125°C (Ext.)

*

These parameters are characterized but not tested.

†

Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for

design guidance only and are not tested.

Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to

the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended.

FIGURE 10-5:

I/O TIMING – PIC12F508/509/16F505

Q1

Q4

Q2

Q3

OSC1

I/O Pin

(input)

17

18

19

I/O Pin

(output)

New Value

Old Value

20, 21

Note:

All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

DS41236E-page 77

PIC12F508/509/16F505

TABLE 10-5: TIMING REQUIREMENTS – PIC12F508/509/16F505

Standard Operating Conditions (unless otherwise specified)

AC

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)

-40°C ≤ TA ≤ +125°C (extended)

CHARACTERISTICS

Operating Voltage VDD range is described in Section 10.1 "Power-on Reset (POR)"

Param

Sym.

No.

Characteristic

Min.

Typ⁽¹⁾

Max.

Units

17

18

19

20

21

TOSH2IOV OSC1↑ (Q1 cycle) to Port Out Valid^{(2), (3)}

TOSH2IOI

OSC1↑ (Q2 cycle) to Port Input Invalid (I/O in hold time)⁽²⁾

TIOV2OSH Port Input Valid to OSC1↑ (I/O in setup time)

—

50

20

—

10

100*

—

ns

—

TIOR

TIOF

Port Output Rise Time⁽³⁾

Port Output Fall Time⁽³⁾

25**

*

These parameters are characterized but not tested.

** These parameters are design targets and are not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

2: Measurements are taken in EXTRC mode.

3: See Figure 10-3 for loading conditions.

FIGURE 10-6:

RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING –

PIC12F508/509/16F505

VDD

MCLR

30

Internal

POR

32

DRT

(2)

Timeout

Internal

Reset

Watchdog

Timer

Reset

31

34

(1)

I/O pin

Note 1: I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software.

2: Runs in MCLR or WDT Reset only in XT, LP and HS (PIC16F505) modes.

DS41236E-page 78

PIC12F508/509/16F505

TABLE 10-6: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC12F508/509/16F505

Standard Operating Conditions (unless otherwise specified)

AC CHARACTERISTICS

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)

-40°C ≤ TA ≤ +125°C (extended)

Param

Sym.

No.

Characteristic

Min. Typ⁽¹⁾Max. Units

Conditions

30

31

TMCL MCLR Pulse Width (low)

2000*

—

ns

VDD = 5.0V

TWDT Watchdog Timer Time-out Period

(no prescaler)

9*

18*

30*

40*

ms

VDD = 5.0V (Industrial)

VDD = 5.0V (Extended)

32

34

TDRT

Device Reset Timer Period⁽²⁾

9*

18*

30*

40*

ms

VDD = 5.0V (Industrial)

VDD = 5.0V (Extended)

TIOZ

I/O High-impedance from MCLR

low

—

2000*

ns

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for

design guidance only and are not tested.

DS41236E-page 79

PIC12F508/509/16F505

FIGURE 10-7:

TIMER0 CLOCK TIMINGS – PIC12F508/509/16F505

T0CKI

40

41

42

TABLE 10-7: TIMER0 CLOCK REQUIREMENTS – PIC12F508/509/16F505

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in

Section 10.1 "Power-on Reset (POR)"

Param

Sym.

No.

Characteristic

Min.

Typ⁽¹⁾Max. Units

Conditions

40

41

42

Tt0H T0CKI High Pulse

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5 TCY + 20*

10*

—

ns

Width

Tt0L T0CKI Low Pulse

Width

0.5 TCY + 20*

10*

Tt0P T0CKI Period

20 or TCY + 40* N

ns Whichever is greater.

N = Prescale Value

(1, 2, 4,..., 256)

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

DS41236E-page 80

PIC12F508/509/16F505

11.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are

not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean -

3σ) respectively, where s is a standard deviation, over each temperature range.

FIGURE 11-1:

IDD vs. VDD at FOSC = 4 MHz

1,400

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3σ

(-40°C to 125°C)

1,200

1,000

800

600

400

200

0

Maximum

4 MHz

Typical

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41236E-page 81

PIC12F508/509/16F505

FIGURE 11-2:

IDD VS. FOSC Over VDD (HS MODE, PIC16F505 only)

3.00

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3σ

(-40°C to 125°C)

2.50

Max. 5V

Typical 5V

2.00

1.50

1.00

Max. 3V

0.50

0.00

Typical 3V

10

25

5

15

20

Fosc (MHz)

FIGURE 11-3:

TYPICAL IPD vs. VDD (SLE_TE_yP_picM_aO_lDE, ALL PERIPHERALS DISABLED)

(Sleep Mode all Peripherals Disabled)

0.45

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3σ

(-40°C to 125°C)

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41236E-page 82

PIC12F508/509/16F505

FIGURE 11-4:

MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)

Maximum

(Sleep Mode all Peripherals Disabled)

18.0

Typical: Statistical Mean @25°C

16.0

14.0

12.0

10.0

8.0

Maximum: Mean (Worst-Case Temp) + 3σ

(-40°C to 125°C)

Max. 125°C

6.0

4.0

Max. 85°C

2.0

0.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 11-5:

TYPICAL WDT IPD vs. VDD

9

8

7

6

5

4

3

2

1

0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3σ

(-40°C to 125°C)

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41236E-page 83

PIC12F508/509/16F505

FIGURE 11-6:

MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE

Maximum

25.0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3σ

(-40°C to 125°C)

20.0

15.0

10.0

5.0

Max. 125°C

Max. 85°C

0.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 11-7:

WDT TIME-OUT or DEVICE RESET TIMER vs. VDD OVER TEMPERATURE (NO

WDT PRESCALER)⁽¹⁾

50

45

40

35

30

25

20

15

10

5

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3σ

(-40°C to 125°C)

Max. 125°C

Max. 85°C

Typical. 25°C

Min. -40°C

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

Note 1: Device Reset Timer (DRT) values are for case of Reset of power-up. Table 7-6 shows DRT values for

the case of other types of Reset events.

DS41236E-page 84

PIC12F508/509/16F505

FIGURE 11-8:

VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)

(VDD = 3V, -40×C TO 125×C)

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3σ

(-40°C to 125°C)

Max. 125°C

Max. 85°C

Typical 25°C

Min. -40°C

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

IOL (mA)

FIGURE 11-9:

VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)

0.45

Typical: Statistical Mean @25°C

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

Typical: Statistical Mean @25×C

Maximum: Mean (Worst-Case Temp) + 3σ

Maximum: Meas(-+403×C to 125×C)

(-40°C to 125°C)

Max. 125°C

Max. 85°C

Typ. 25°C

Min. -40°C

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

IOL (mA)

DS41236E-page 85

PIC12F508/509/16F505

FIGURE 11-10:

VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)

3.5

3.0

2.5

2.0

1.5

Max. -40°C

Typ. 25°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3σ

(-40°C to 125°C)

1.0

0.5

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

-3.5

-4.0

IOH (mA)

FIGURE 11-11:

VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V)

5.5

5.0

4.5

4.0

Max. -40°C

Typ. 25°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3σ

(-40°C to 125°C)

3.5

3.0

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

-3.5

-4.0

-4.5

-5.0

IOH (mA)

DS41236E-page 86

PIC12F508/509/16F505

FIGURE 11-12:

TTL INPUT THRESHOLD VIN vs. VDD

(TTL Input, -40×C TO 125×C)

1.7

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3σ

(-40°C to 125°C)

1.5

1.3

1.1

0.9

0.7

0.5

Max. -40°C

Typ. 25°C

Min. 125°C

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 11-13:

SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD

(ST Input, -40×C TO 125×C)

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

VIH Max. 125°C

VIH Min. -40°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3σ

(-40°C to 125°C)

VIL Max. -40°C

VIL Min. 125°C

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41236E-page 87

PIC12F508/509/16F505

FIGURE 11-14:

TYPICAL INTOSC FREQUENCY CHANGE vs VDD (25°C)

5

4

3

22

1₁

0₀

-1

-2

-3

-4-4

-5

5.5

2

2.5

3

3.5

44

44..55

5

VDD (V)

FIGURE 11-15:

TYPICAL INTOSC FREQUENCY CHANGE vs VDD (-40°C)

5

4

3

2

1

0

-1

-2

-3

-4

-5

2

2.5

3

3.5

4

4.5

5

5.5

5

5.5

4

4.5

3

3.5

2.5

2

VDD (V)

DS41236E-page 88

PIC12F508/509/16F505

FIGURE 11-16:

TYPICAL INTOSC FREQUENCY CHANGE vs VDD (85°C)

5

4

33

2

1

0

-1

-2-2

-3

-4

-5

2

2.5

3

3.5

4

4.5

5

5.5

2.5

2

VDD (V)

FIGURE 11-17:

TYPICAL INTOSC FREQUENCY CHANGE vs VDD (125°C

5

4

3

2

11

0

-1-1

-2

-3

-4

-5

2

2.5

3

3.5

4

4.5

5

5.5

2

VDD (V)

DS41236E-page 89

PIC12F508/509/16F505

NOTES:

DS41236E-page 90

PIC12F508/509/16F505

12.0 PACKAGING INFORMATION

12.1 Package Marking Information

8-Lead PDIP

Example

12F508-I

XXXXXXXX

XXXXXNNN

YYWW

e

3

/P

017

0610

8-Lead SOIC (3.90 mm)

Example

XXXXXXXX

XXXXYYWW

12F509-I

/SN 0610

e

3

NNN

017

8-Lead MSOP

Example

12F509

0610017

XXXXXX

YWWNNN

8-Lead 2x3 DFN*

Example

X X X

Y W W

N N

B E Q

6 1 0

1 7

Legend: XX...X Customer-specific information

Y

YY

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

*

)

3

e

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line thus limiting the number of available characters

for customer specific information.

*

Standard PIC^®device marking consists of Microchip part number, year code, week code, and traceability

code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip

Sales Office. For QTP devices, any special marking adders are included in QTP price.

DS41236E-page 91

PIC12F508/509/16F505

12.1 Package Marking Information (Continued)

14-Lead PDIP (300 mil)

Example

XXXXXXXXXXXXXX

PIC16F505

-I/P

0215

e

3

YYWWNNN

0610017

Example

14-Lead SOIC (3.90 mm)

PIC16F505-E

/SL0125

XXXXXXXXXXX

YYWWNNN

0610017

Example

16F505-I

14-Lead TSSOP (4.4 mm)

XXXXXXXX

YYWW

0610

017

NNN

16-Lead QFN

Example

XXXXXXX

YYWWNNN

16F505

-I/MG

0610017

TABLE 12-1: 8-LEAD 2X3 DFN (MC) TOP MARKING

Part Number

Marking

PIC12F508 (T) - I/MC

PIC12F508-E/MC

BN0

BP0

BQ0

BR0

PIC12F509 (T) - I/MC

PIC12F509-E/MC

DS41236E-page 92

PIC12F508/509/16F505

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1ꢐ,2ꢅ1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ

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DS41236E-page 93

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ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆꢑ ꢛꢒꢆMꢆꢛꢄ""ꢗ#$ꢆꢓ%&ꢔꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ !ꢏ'ꢚ

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ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ

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DS41236E-page 94

PIC12F508/509/16F505

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆꢑ ꢛꢒꢆMꢆꢛꢄ""ꢗ#$ꢆꢓ%&ꢔꢆꢕꢕꢆꢖꢗꢅꢘꢆꢙ !ꢏ'ꢚ

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ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ

DS41236E-page 95

PIC12F508/509/16F505

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ(ꢋꢌ"ꢗꢆ ꢕꢄꢈꢈꢆ!ꢎꢊꢈꢋꢐꢃꢆꢇꢄꢌ)ꢄ*ꢃꢆꢑ( ꢒꢆꢙ( !ꢇꢚ

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DS41236E-page 96

PIC12F508/509/16F505

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DS41236E-page 100

PIC12F508/509/16F505

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS41236E-page 101

PIC12F508/509/16F505

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS41236E-page 102

PIC12F508/509/16F505

APPENDIX A: REVISION HISTORY

Revision A (April 2004)

Original data sheet for PIC12F508/509/16F505

devices

Revision B (June 2005)

Update packages

Revision C (03/2007)

Revised Table 3-2 Legend; Revised Table 3-3 RB3 and

Legend; Revised Table 10-4 F10; Replaced Package

Drawings (Rev. AN); Added DFN package; Replaced

Development Support Section; Revised Product ID

System.

Revision D (12/2007)

Revised Title; Operating Current; Table 1-1 added DFN

and revised note; Revised Section 3.0, last paragraph;

Revised Figure 4-4; Revised Table 4-2 (FSR); Revised

Register 7-1 and Register 7-2; Revised Section 7.2.2;

Revised Table 7-3, Note 2; Revised Table 7-4 (FSR)

and Note 2; Deleted Section 7.3.1: External Clock In

and Figure 7-6; Revised new Section 7.3.1; Replaced

TBD with new data in Tables 10-4 and 10-5; Revised

Tables 10-1 (Industrial), 10-2 (Extended), and Tables

10-1 (Industrial, Extended) and 10-2 (Pull-up Resistor

Ranges), 10-3, 10-4 and 10-6; Revised Figure 10-1,

Figure 10-2; Section 11.0, Added Char data; Revised

Package Marking Information; Revised Product ID

System.

Revision E (08/2009)

Added PIC16F505 16-Pin diagram (QFN); Added Note

after subsection 5.2 PORTC; Updated Note 4 and

deleted Note 5, Table 10-1; Deleted Param. No. D061

(Table 10-1) and Param. No. D061A becomes D061;

Added QFN Package Information; Revised Product

Identification System; Added Figures 11-14, 11-15, 11-

16, 11-7 to Char Data section; Other minor corrections;

Removed Preliminary status.

DS41236E-page 103

PIC12F508/509/16F505

NOTES:

DS41236E-page 104

PIC12F508/509/16F505

INDEX

MPLAB Integrated Development Environment Software.... 65

MPLAB PM3 Device Programmer ...................................... 67

MPLAB REAL ICE In-Circuit Emulator System .................. 67

MPLINK Object Linker/MPLIB Object Librarian.................. 66

A

ALU ..................................................................................... 11

Assembler

MPASM Assembler..................................................... 66

O

B

Option Register................................................................... 24

OSC selection..................................................................... 41

OSCCAL Register............................................................... 26

Oscillator Configurations..................................................... 44

Oscillator Types

Block Diagram

On-Chip Reset Circuit................................................. 50

Timer0......................................................................... 35

TMR0/WDT Prescaler................................................. 39

Watchdog Timer.......................................................... 53

Brown-Out Protection Circuit .............................................. 54

HS............................................................................... 44

LP ............................................................................... 44

RC .............................................................................. 44

XT............................................................................... 44

C

C Compilers

MPLAB C18 ................................................................ 66

MPLAB C30 ................................................................ 66

Carry ................................................................................... 11

Clocking Scheme ................................................................ 16

Code Protection ............................................................ 41, 55

Configuration Bits................................................................ 41

Configuration Word ............................................................. 43

Customer Change Notification Service ............................. 107

Customer Notification Service........................................... 107

Customer Support............................................................. 107

P

PIC12F508/509/16F505 Device Varieties ............................ 9

PICSTART Plus Development Programmer....................... 68

POR

Device Reset Timer (DRT) ................................... 41, 52

PD......................................................................... 54, 41

TO............................................................................... 54

PORTB ............................................................................... 31

Power-down Mode.............................................................. 55

Prescaler ............................................................................ 38

Program Counter................................................................ 27

D

DC and AC Characteristics................................................. 81

Development Support ......................................................... 65

Digit Carry........................................................................... 11

Q

Q cycles.............................................................................. 16

R

E

RC Oscillator....................................................................... 45

Reader Response............................................................. 108

Read-Modify-Write.............................................................. 33

Register File Map

Errata .................................................................................... 6

F

Family of Devices

PIC12F508 ................................................................. 19

PIC12F509 ................................................................. 19

PIC16F505 ................................................................. 19

Registers

PIC12F508/509/PIC16F505.......................................... 7

FSR..................................................................................... 28

I

Special Function......................................................... 20

Reset .................................................................................. 41

Reset on Brown-Out ........................................................... 54

I/O Interfacing ..................................................................... 31

I/O Ports.............................................................................. 31

I/O Programming Considerations........................................ 33

ID Locations.................................................................. 41, 55

INDF.................................................................................... 28

Indirect Data Addressing..................................................... 28

Instruction Cycle ................................................................. 16

Instruction Flow/Pipelining .................................................. 16

Instruction Set Summary..................................................... 58

Internet Address................................................................ 107

S

Sleep ............................................................................ 41, 55

Software Simulator (MPLAB SIM) ...................................... 66

Special Features of the CPU .............................................. 41

Special Function Registers................................................. 20

Stack................................................................................... 27

Status Register ............................................................. 11, 22

L

T

Loading of PC ..................................................................... 27

Timer0

M

Timer0 ........................................................................ 35

Timer0 (TMR0) Module .............................................. 35

TMR0 with External Clock .......................................... 37

Timing Diagrams and Specifications .................................. 75

Timing Parameter Symbology and Load Conditions .......... 75

TRIS Registers ................................................................... 31

Memory Organization.......................................................... 17

Data Memory .............................................................. 18

Program Memory (PIC12F508/509)............................ 17

Program Memory (PIC16F505)................................... 18

Microchip Internet Web Site.............................................. 107

MPLAB ASM30 Assembler, Linker, Librarian ..................... 66

MPLAB ICD 2 In-Circuit Debugger ..................................... 67

MPLAB ICE 2000 High-Performance Universal

In-Circuit Emulator ...................................................... 67

DS41236E-page 105

PIC12F508/509/16F505

W

Wake-up from Sleep ...........................................................55

Watchdog Timer (WDT) ................................................ 41, 52

Period..........................................................................52

Programming Considerations .....................................52

WWW Address..................................................................107

WWW, On-Line Support........................................................6

Z

Zero bit................................................................................11

DS41236E-page 106

PIC12F508/509/16F505

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

DS41236E-page 107

PIC12F508/509/16F505

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

Technical Publications Manager

Reader Response

Total Pages Sent ________

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

PIC12F508/509/16F505

DS41236E

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS41236E-page 108

PIC12F508/509/16F505

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

XXX

Examples:

Temperature

Range

Package

Pattern

a)

b)

c)

PIC12F508-E/P 301 = Extended Temp., PDIP

package, QTP pattern #301

PIC12F508-I/SN

package

=

Industrial Temp., SOIC

PIC12F508T-E/P

=

Extended Temp., PDIP

Device:

PIC16F505

PIC12F508

package, Tape and Reel

PIC12F509

PIC16F505T⁽¹⁾

PIC12F508T⁽²⁾

PIC12F509T⁽²⁾

Temperature

Range:

I

E

=

-40°C to +85°C (Industrial)

-40°C to +125°C (Extended)

Package:

MC

MS

P

SL

SN

ST

MG

=

8L DFN 2x3 (DUAL Flatpack No-Leads)^{(3, 4)}

Micro-Small Outline Package (MSOP)^{(3, 4)}

Plastic (PDIP)⁽⁴⁾

=

Note 1:

2:

T

=

in tape and reel SOIC, TSSOP and

QFN packages only

in tape and reel SOIC and MSOP

packages only.

14L Small Outline, 3.90 mm (SOIC)⁽⁴⁾

8L Small Outline, 3.90 mm Narrow (SOIC)⁽⁴⁾

Thin Shrink Small Outline (TSSOP)⁽⁴⁾

16L QFN (3x3x0.9)⁽⁵⁾

3:

4:

5:

PIC12F508/PIC12F509 only.

Pb-free.

PIC16F505 only.

Pattern:

Note:

Special Requirements

Tape and Reel available for only the following packages: SOIC, MSOP

and TSSOP.

DS41236E-page 109

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4080

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Cleveland

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Hsin Chu

Tel: 886-3-6578-300

Fax: 886-3-6578-370

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

03/26/09

DS41236E-page 110


型号：	PIC16F508-I/MC
厂家：	MICROCHIP
描述：	8/14-Pin, 8-Bit Flash Microcontrollers 8月14日引脚， 8位闪存微控制器闪存微控制器
文件：	总110页 (文件大小：1484K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC16F508-I/MC [MICROCHIP]

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