PIC16F631-I/SO_技术文档

PIC16F631/677/685/687/689/690

Data Sheet

20-Pin Flash-Based, 8-Bit

CMOS Microcontrollers with

nanoWatt Technology

DS41262D

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and

SmartShunt are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable

Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor

and The Embedded Control Solutions Company are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,

MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its PIC^®

MCUs and dsPIC^®DSCs, KEELOQ^®code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

DS41262D-page ii

PIC16F631/677/685/687/689/690

20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with

nanoWatt Technology

High-Performance RISC CPU:

Low-Power Features:

• Only 35 instructions to learn:

- All single-cycle instructions except branches

• Operating speed:

• Standby Current:

- 50 nA @ 2.0V, typical

• Operating Current:

- DC – 20 MHz oscillator/clock input

- DC – 200 ns instruction cycle

• Interrupt capability

• 8-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

- 11 μA @ 32 kHz, 2.0V, typical

- 220 μA @ 4 MHz, 2.0V, typical

• Watchdog Timer Current:

- <1 μA @ 2.0V, typical

Peripheral Features:

Special Microcontroller Features:

• 17 I/O pins and 1 input only pin:

- High current source/sink for direct LED drive

- Interrupt-on-Change pin

• Precision Internal Oscillator:

- Factory calibrated to ± 1%

- Software selectable frequency range of

8 MHz to 32 kHz

- Software tunable

- Individually programmable weak pull-ups

- Ultra Low-Power Wake-up (ULPWU)

• Analog Comparator module with:

- Two analog comparators

- Two-Speed Start-up mode

- Crystal fail detect for critical applications

- Clock mode switching during operation for

power savings

- Programmable on-chip voltage reference

(CVREF) module (% of VDD)

- Comparator inputs and outputs externally

accessible

• Power-Saving Sleep mode

• Wide operating voltage range (2.0V-5.5V)

• Industrial and Extended Temperature range

• Power-on Reset (POR)

- SR Latch mode

- Timer 1 Gate Sync Latch

- Fixed 0.6V VREF

• Power-up Timer (PWRTE) and Oscillator Start-up

Timer (OST)

• Brown-out Reset (BOR) with software control

option

• A/D Converter:

- 10-bit resolution and 12 channels

• Timer0: 8-bit timer/counter with 8-bit

programmable prescaler

• Enhanced low-current Watchdog Timer (WDT)

with on-chip oscillator (software selectable

nominal 268 seconds with full prescaler) with

software enable

• Multiplexed Master Clear/Input pin

• Programmable code protection

• High Endurance Flash/EEPROM cell:

- 100,000 write Flash endurance

- 1,000,000 write EEPROM endurance

- Flash/Data EEPROM retention: > 40 years

• Enhanced USART module:

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Timer1 Gate (count enable)

- Option to use OSC1 and OSC2 in LP mode

as Timer1 oscillator if INTOSC mode

selected

• Timer2: 8-bit timer/counter with 8-bit period

register, prescaler and postscaler

• Enhanced Capture, Compare, PWM+ module:

- 16-bit Capture, max resolution 12.5 ns

- Compare, max resolution 200 ns

- 10-bit PWM with 1, 2 or 4 output channels,

programmable “dead time”, max frequency

20 kHz

- Supports RS-485, RS-232 and LIN 2.0

- Auto-Baud Detect

- Auto-wake-up on Start bit

- PWM output steering control

• Synchronous Serial Port (SSP):

- SPI mode (Master and Slave)

• I²C™ (Master/Slave modes):

- I²C™ address mask

• In-Circuit Serial Programming^TM(ICSP^TM) via two

pins

DS41262D-page 1

PIC16F631/677/685/687/689/690

Program

Data Memory

Memory

10-bitA/D

(ch)

Timers

8/16-bit

Device

I/O

Comparators

SSP ECCP+ EUSART

Flash

SRAM EEPROM

(words) (bytes) (bytes)

PIC16F631 1024

PIC16F677 2048

PIC16F685 4096

PIC16F687 2048

PIC16F689 4096

PIC16F690 4096

64

128

256

18

—

12

2

1/1

2/1

1/1

2/1

No

Yes

No

128

256

128

256

Yes

No

Yes

No

Yes

PIC16F631 Pin Diagram

20-pin PDIP, SOIC, SSOP

VDD

1

20

VSS

RA5/T1CKI/OSC1/CLKIN

RA4/T1G/OSC2/CLKOUT

2

19

18

RA0/C1IN+/ICSPDAT/ULPWU

RA1/C12IN0-/ICSPCLK

RA2/T0CKI/INT/C1OUT

RC0/C2IN+

3

4

RA3/MCLR/VPP

RC5

17

16

5

RC4/C2OUT

RC3/C12IN3-

RC6

6

15

14

13

12

11

RC1/C12IN1-

RC2/C12IN2-

RB4

RB5

RB6

7

8

RC7

RB7

9

10

TABLE 1:

PIC16F631 PIN SUMMARY

I/O

Analog

Comparators

Timers

Interrupt

Pull-up

Basic

RA0

RA1

RA2

RA3

RA4

RA5

RB4

RB5

RB6

RB7

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

—

19

18

17

4

AN0/ULPWU

C1IN+

C12IN0-

C1OUT

—

IOC

IOC/INT

IOC

—

Y

ICSPDAT

AN1

—

ICSPCLK

T0CKI

—

Y

Y⁽¹⁾

—

MCLR/VPP

3

—

T1G

T1CKI

—

Y

OSC2/CLKOUT

2

—

Y

OSC1/CLKIN

13

12

11

10

16

15

14

7

—

Y

—

Y

—

Y

—

Y

—

AN4

AN5

AN6

AN7

—

C2IN+

C12IN1-

C12IN2-

C12IN3-

C2OUT

—

6

—

5

—

8

—

9

—

1

—

VDD

VSS

—

20

—

Note 1: Pull-up enabled only with external MCLR configuration.

DS41262D-page 2

PIC16F631/677/685/687/689/690

PIC16F677 Pin Diagram

20-pin PDIP, SOIC, SSOP

VDD

1

20

19

18

VSS

RA5/T1CKI/OSC1/CLKIN

RA4/AN3/T1G/OSC2/CLKOUT

RA3/MCLR/VPP

RC5

2

3

RA0/AN0/C1IN+/ICSPDAT/ULPWU

RA1/AN1/C12IN0-/VREF/ICSPCLK

RA2/AN2/T0CKI/INT/C1OUT

RC0/AN4/C2IN+

4

5

17

16

RC4/C2OUT

RC3/AN7C12IN3-

RC6/AN8/SS

6

7

8

9

15

14

13

12

11

RC1/AN5/C12IN1-

RC2/AN6/C12IN2-

RB4/AN10/SDI/SDA

RB5/AN11

RC7/AN9/SDO

RB7

10

RB6/SCK/SCL

TABLE 2:

PIC16F677 PIN SUMMARY

I/O

Analog

Comparators Timers

SSP

Interrupt

Pull-up

Basic

RA0

RA1

RA2

RA3

RA4

RA5

RB4

RB5

RB6

RB7

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

—

19

18

17

4

AN0/ULPWU

AN1/VREF

AN2

—

C1IN+

C12IN0-

C1OUT

—

IOC

IOC/INT

IOC

—

Y

ICSPDAT

ICSPCLK

T0CKI

—

Y

Y⁽¹⁾

—

MCLR/VPP

3

AN3

—

Y

OSC2/CLKOUT

T1G

T1CKI

—

2

—

Y

OSC1/CLKIN

13

12

11

10

16

15

14

7

AN10

AN11

—

SDI/SDA

Y

—

SCL/SCK

—

Y

—

Y

—

Y

—

AN4

AN5

AN6

AN7

—

C2IN+

C12IN1-

C12IN2-

C12IN3-

C2OUT

—

6

—

5

—

8

AN8

AN9

—

SS

—

9

—

SDO

—

1

—

VDD

VSS

—

20

—

Note 1: Pull-up activated only with external MCLR configuration.

DS41262D-page 3

PIC16F631/677/685/687/689/690

PIC16F685 Pin Diagram

20-pin PDIP, SOIC, SSOP

VDD

RA5/T1CKI/OSC1/CLKIN

RA4/AN3/T1G/OSC2/CLKOUT

RA3/MCLR/VPP

1

20

19

18

VSS

2

3

RA0/AN0/C1IN+/ICSPDAT/ULPWU

RA1/AN1/C12IN0-/VREF/ICSPCLK

RA2/AN2/T0CKI/INT/C1OUT

RC0/AN4/C2IN+

4

5

17

16

RC5/CCP1/P1A

RC4/C2OUT/P1B

RC3/AN7/C12IN3-/P1C

RC6/AN8

6

15

14

13

12

11

RC1/AN5/C12IN1-

RC2/AN6/C12IN2-/P1D

RB4/AN10

RB5/AN11

RB6

7

8

9

10

RC7/AN9

RB7

TABLE 3:

PIC16F685 PIN SUMMARY

I/O

Analog

Comparators Timers

ECCP

Interrupt

Pull-up

Basic

RA0

RA1

RA2

RA3

RA4

RA5

RB4

RB5

RB6

RB7

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

—

19

18

17

4

AN0/ULPWU

AN1/VREF

AN2

—

C1IN+

C12IN0-

C1OUT

—

IOC

IOC/INT

IOC

—

Y

ICSPDAT

ICSPCLK

T0CKI

—

Y

Y⁽¹⁾

—

MCLR/VPP

3

AN3

—

Y

OSC2/CLKOUT

T1G

T1CKI

—

2

—

Y

OSC1/CLKIN

13

12

11

10

16

15

14

7

AN10

AN11

—

Y

—

Y

—

Y

—

Y

—

AN4

AN5

AN6

AN7

—

C2IN+

C12IN1-

C12IN2-

C12IN3-

C2OUT

—

P1D

P1C

P1B

—

6

—

5

—

CCP1/P1A

—

8

AN8

AN9

—

9

—

1

—

VDD

VSS

—

20

—

Note 1: Pull-up activated only with external MCLR configuration.

DS41262D-page 4

PIC16F631/677/685/687/689/690

PIC16F687/689 Pin Diagram

20-pin PDIP, SOIC, SSOP

VDD

1

2

20

19

18

VSS

RA5/T1CKI/OSC1/CLKIN

RA4/AN3/T1G/OSC2/CLKOUT

RA3/MCLR/VPP

RC5

RA0/AN0/C1IN+/ICSPDAT/ULPWU

RA1/AN1/C12IN0-/VREF/ICSPCLK

RA2/AN2/T0CKI/INT/C1OUT

RC0/AN4/C2IN+

3

4

17

16

5

RC4/C2OUT

RC3/AN7/C12IN3-

RC6/AN8/SS

6

15

14

13

12

11

RC1/AN5/C12IN1-

RC2/AN6/C12IN2-

RB4/AN10/SDI/SDA

RB5/AN11/RX/DT

RB6/SCK/SCL

7

8

RC7/AN9/SDO

9

10

RB7/TX/CK

TABLE 4:

PIC16F687/689 PIN SUMMARY

I/O

Analog

Comparators Timers EUSART

SSP

Interrupt Pull-up

Basic

RA0

RA1

RA2

RA3

RA4

RA5

RB4

RB5

RB6

RB7

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

—

19

18

17

4

AN0/ULPWU

AN1/VREF

AN2

—

C1IN+

C12IN0-

C1OUT

—

IOC

IOC/INT

IOC

—

Y

ICSPDAT

ICSPCLK

—

T0CKI

—

Y

Y⁽¹⁾

—

MCLR/VPP

3

AN3

—

Y

OSC2/CLKOUT

T1G

T1CKI

—

2

—

Y

OSC1/CLKIN

13

12

11

10

16

15

14

7

AN10

AN11

—

SDI/SDA

Y

—

RX/DT

—

SCL/SCK

—

Y

—

Y

—

TX/CK

—

Y

—

AN4

AN5

AN6

AN7

—

C2IN+

C12IN1-

C12IN2-

C12IN3-

C2OUT

—

6

—

5

—

8

AN8

AN9

—

SS

9

—

SDO

—

1

—

VDD

VSS

—

20

—

Note 1: Pull-up activated only with external MCLR configuration.

DS41262D-page 5

PIC16F631/677/685/687/689/690

PIC16F690 Pin Diagram (PDIP, SOIC, SSOP)

20-pin PDIP, SOIC, SSOP

VDD

RA5/T1CKI/OSC1/CLKIN

RA4/AN3/T1G/OSC2/CLKOUT

RA3/MCLR/VPP

1

20

19

18

VSS

2

3

RA0/AN0/C1IN+/ICSPDAT/ULPWU

RA1/AN1/C12IN0-/VREF/ICSPCLK

RA2/AN2/T0CKI/INT/C1OUT

RC0/AN4/C2IN+

4

5

17

16

RC5/CCP1/P1A

RC4/C2OUT/P1B

RC3/AN7/C12IN3-/P1C

RC6/AN8/SS

6

7

8

9

15

14

13

12

11

RC1/AN5/C12IN1-

RC2/AN6/C12IN2-/P1D

RB4/AN10/SDI/SDA

RB5/AN11/RX/DT

RC7/AN9/SDO

RB7/TX/CK

10

RB6/SCK/SCL

TABLE 5:

PIC16F690 PIN SUMMARY

I/O

Analog

Comparators Timers

ECCP

EUSART

SSP

Interrupt Pull-up

Basic

RA0

RA1

RA2

RA3

RA4

RA5

RB4

RB5

RB6

RB7

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

—

19

18

17

4

AN0/ULPWU

AN1/VREF

AN2

—

C1IN+

C12IN0-

C1OUT

—

IOC

IOC/INT

IOC

—

Y

ICSPDAT

ICSPCLK

—

T0CKI

—

(1)

—

Y

MCLR/VPP

3

AN3

—

Y

OSC2/CLKOUT

T1G

T1CKI

—

2

—

OSC1/CLKIN

13

12

11

10

16

15

14

7

AN10

AN11

—

SDI/SDA

Y

—

RX/DT

—

SCL/SCK

—

Y

—

Y

—

TX/CK

—

Y

—

AN4

AN5

AN6

AN7

—

C2IN+

C12IN1-

C12IN2-

C12IN3-

C2OUT

—

P1D

P1C

P1B

CCP1/P1A

—

6

—

5

—

8

AN8

AN9

—

SS

9

—

SDO

—

1

—

VDD

VSS

—

20

—

Note 1: Pull-up activated only with external MCLR configuration.

DS41262D-page 6

PIC16F631/677/685/687/689/690

PIC16F690 Pin Diagram (QFN)

20-pin QFN

1

2

15

14

13

12

11

RA3/MCLR/VPP

RA1/AN1/C12IN0-/VREF/ICSPCLK

RA2/AN2/T0CKI/INT/C1OUT

RC0/AN4/C2IN+

(1)

RC5/CCP1/P1A

PIC16F631/677/

685/687/689/690

(1)

RC4/C2OUT/P1B

3

4

(1)

RC3/AN7/C12IN3-/P1C

RC6/AN8/SS

RC1/AN5/C12IN1-

(2)

(1)

5

RC2/AN6/C12IN2-/P1D

Note 1: CCP1/P1A, P1B, P1C and P1D are available on PIC16F685/PIC16F690 only.

2: SS, SDO, SDI/SDA and SCL/SCK are available on PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.

3: RX/DT and TX/CK are available on PIC16F687/PIC16F689/PIC16F690 only.

DS41262D-page 7

PIC16F631/677/685/687/689/690

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Memory Organization................................................................................................................................................................. 25

3.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 47

4.0 I/O Ports ..................................................................................................................................................................................... 59

5.0 Timer0 Module ........................................................................................................................................................................... 81

6.0 Timer1 Module with Gate Control............................................................................................................................................... 84

7.0 Timer2 Module ........................................................................................................................................................................... 91

8.0 Comparator Module.................................................................................................................................................................... 93

9.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 107

10.0 Data EEPROM and Flash Program Memory Control............................................................................................................... 119

11.0 Enhanced Capture/Compare/PWM Module ............................................................................................................................. 127

12.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 149

13.0 SSP Module Overview ............................................................................................................................................................. 175

14.0 Special Features of the CPU.................................................................................................................................................... 193

15.0 Instruction Set Summary.......................................................................................................................................................... 213

16.0 Development Support............................................................................................................................................................... 223

17.0 Electrical Specifications............................................................................................................................................................ 227

18.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 255

19.0 Packaging Information.............................................................................................................................................................. 275

Appendix A: Data Sheet Revision History.......................................................................................................................................... 281

Appendix B: Migrating from other PIC® Devices............................................................................................................................... 281

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DS41262D-page 8

PIC16F631/677/685/687/689/690

Block Diagrams and pinout descriptions of the devices

are as follows:

1.0

DEVICE OVERVIEW

The PIC16F631/677/685/687/689/690 devices are

covered by this data sheet. They are available in 20-pin

PDIP, SOIC, TSSOP and QFN packages.

• PIC16F631 (Figure 1-1, Table 1-1)

• PIC16F677 (Figure 1-2, Table 1-2)

• PIC16F685 (Figure 1-3, Table 1-3)

• PIC16F687/PIC16F689 (Figure 1-4, Table 1-4)

• PIC16F690 (Figure 1-5, Table 1-5)

FIGURE 1-1:

PIC16F631 BLOCK DIAGRAM

INT

Configuration

13

8

PORTA

Data Bus

Program Counter

RA0

RA1

RA2

RA3

RA4

RA5

Flash

1K x 14

Program

Memory

RAM

64 bytes

File

8-Level Stack (13-bit)

Registers

Program

Bus

14

RAM Addr

PORTB

9

Addr MUX

Instruction Reg

RB4

Indirect

Addr

7

Direct Addr

8

RB5

RB6

RB7

FSR Reg

STATUS Reg

MUX

8

PORTC

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

3

Power-up

Timer

Instruction

Decode and

Control

Oscillator

Start-up Timer

ALU

OSC1/CLKI

OSC2/CLKO

Power-on

Reset

8

Timing

Generation

Watchdog

Timer

W Reg

Brown-out

Reset

Internal

Oscillator

Block

VDD

VSS

MCLR

C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT

T0CKI

T1G T1CKI

ULPWU

EEDAT

128 Bytes

Data

EEPROM

2

Ultra Low-Power

Wake-up

Analog Comparators

and Reference

Timer0

Timer1

EEADR

8

DS41262D-page 9

PIC16F631/677/685/687/689/690

FIGURE 1-2:

PIC16F677 BLOCK DIAGRAM

INT

Configuration

13

8

PORTA

Data Bus

Program Counter

Flash

RA0

RA1

2K x 14

RA2

RA3

RA4

RA5

Program

RAM

128 bytes

File

8-Level Stack (13-bit)

Memory

Registers

Program

Bus

14

RAM Addr

9

PORTB

Addr MUX

Instruction Reg

Indirect

Addr

7

RB4

RB5

RB6

RB7

Direct Addr

8

FSR Reg

STATUS Reg

MUX

8

PORTC

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

3

Power-up

Timer

Instruction

Decode and

Control

Oscillator

Start-up Timer

ALU

OSC1/CLKI

OSC2/CLKO

Power-on

Reset

8

Timing

Generation

Watchdog

Timer

W Reg

Brown-out

Reset

Internal

Oscillator

Block

VDD VSS

MCLR

T0CKI

SDI/ SCK/

SDO SDA SCL

SS

T1G T1CKI

ULPWU

Ultra Low-Power

Wake-up

Synchronous

Serial Port

Timer0

Timer1

AN8 AN9 AN10 AN11

EEDAT

256 Bytes

Data

EEPROM

8

2

Analog Comparators

and Reference

Analog-To-Digital Converter

EEADR

VREF

AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT

DS41262D-page 10

PIC16F631/677/685/687/689/690

FIGURE 1-3:

PIC16F685 BLOCK DIAGRAM

INT

Configuration

13

8

PORTA

Data Bus

Program Counter

Flash

RA0

RA1

RA2

RA3

RA4

RA5

4K x 14

Program

Memory

RAM

256 bytes

File

8-Level Stack (13-bit)

Registers

Program

Bus

14

RAM Addr

9

PORTB

Addr MUX

Instruction Reg

Indirect

Addr

RB4

RB5

7

Direct Addr

8

RB6

RB7

FSR Reg

STATUS Reg

MUX

8

PORTC

RC0

RC1

3

Power-up

Timer

RC2

RC3

RC4

RC5

RC6

RC7

Instruction

Decode and

Control

Oscillator

Start-up Timer

ALU

OSC1/CLKI

OSC2/CLKO

Power-on

Reset

8

Timing

Generation

Watchdog

Timer

W Reg

Brown-out

Reset

Internal

Oscillator

Block

VDD VSS

MCLR

CCP1/

P1A P1B P1C P1D

T0CKI

T1G T1CKI

ULPWU

Ultra Low-Power

Wake-up

Timer2

Timer0

Timer1

ECCP+

AN8 AN9 AN10 AN11

EEDAT

256 Bytes

Data

EEPROM

8

2

Analog Comparators

and Reference

Analog-To-Digital Converter

EEADR

VREF AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7

C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT

DS41262D-page 11

PIC16F631/677/685/687/689/690

FIGURE 1-4:

PIC16F687/PIC16F689 BLOCK DIAGRAM

INT

Configuration

13

8

PORTA

Data Bus

Program Counter

Flash

2K⁽¹⁾/4K x 14

Program

RA0

RA1

RA2

RA3

RA4

RA5

RAM

128⁽¹⁾/256 bytes

File

8-Level Stack (13-bit)

Memory

Registers

Program

Bus

14

RAM Addr

9

PORTB

Addr MUX

Instruction Reg

Indirect

Addr

7

RB4

Direct Addr

8

RB5

RB6

RB7

FSR Reg

STATUS Reg

8

PORTC

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

3

MUX

Power-up

Timer

Instruction

Decode and

Control

Oscillator

Start-up Timer

ALU

OSC1/CLKI

OSC2/CLKO

Power-on

Reset

8

Timing

Generation

Watchdog

Timer

W Reg

Brown-out

Reset

Internal

Oscillator

Block

VDD

VSS

MCLR

SDI/ SCK/

SDA SCL

SS

SDO

TX/CK

RX/DT

T0CKI

T1G T1CKI

ULPWU

Ultra Low-Power

Wake-up

Synchronous

Serial Port

EUSART

Timer0

Timer1

AN8 AN9 AN10 AN11

EEDAT

256 Bytes

Data

EEPROM

8

2

Analog Comparators

and Reference

Analog-To-Digital Converter

EEADR

VREF

AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT

Note 1: PIC16F687 only.

DS41262D-page 12

PIC16F631/677/685/687/689/690

FIGURE 1-5:

PIC16F690 BLOCK DIAGRAM

INT

Configuration

13

8

PORTA

Data Bus

Program Counter

Flash

RA0

RA1

RA2

RA3

RA4

RA5

4k x 14

Program

Memory

RAM

256 bytes

File

8-Level Stack (13-bit)

Registers

Program

Bus

14

RAM Addr

9

PORTB

Addr MUX

Instruction Reg

Indirect

Addr

7

RB4

RB5

RB6

RB7

Direct Addr

8

FSR Reg

STATUS Reg

MUX

8

PORTC

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

3

Power-up

Timer

Instruction

Decode and

Control

Oscillator

Start-up Timer

ALU

OSC1/CLKI

OSC2/CLKO

Power-on

Reset

8

Timing

Generation

Watchdog

Timer

W Reg

Brown-out

Reset

Internal

Oscillator

Block

VDD VSS

MCLR

CCP1/

P1A

SDI/ SCK/

SDA SCL

TX/CK RX/DT

SS

SDO

P1B P1C P1D

ECCP+

T1G T1CKI

ULPWU

T0CKI

Timer0

Ultra Low-Power

Wake-up

Synchronous

Serial Port

Timer1

Timer2

EUSART

AN8 AN9 AN10 AN11

EEDAT

256 Bytes

Data

EEPROM

8

2

Analog Comparators

and Reference

Analog-To-Digital Converter

EEADR

VREF

AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT

DS41262D-page 13

PIC16F631/677/685/687/689/690

TABLE 1-1:

PINOUT DESCRIPTION – PIC16F631

Input Output

Function

Name

Description

Type

RA0/C1IN+/ICSPDAT/ULPWU

RA0

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

C1IN+

ICSPDAT

ULPWU

RA1

AN

ST

—

Comparator C1 non-inverting input.

CMOS ICSP™ Data I/O.

AN

TTL

—

Ultra Low-Power Wake-up input.

RA1/C12IN0-/ICSPCLK

RA2/T0CKI/INT/C1OUT

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

C12IN0-

ICSPCLK

RA2

AN

ST

—

Comparator C1 or C2 inverting input.

ICSP™ clock.

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

T0CKI

INT

ST

—

Timer0 clock input.

External interrupt pin.

C1OUT

RA3

CMOS Comparator C1 output.

RA3/MCLR/VPP

TTL

—

General purpose input. Individually controlled interrupt-on-

change.

MCLR

VPP

ST

HV

—

Master Clear with internal pull-up.

Programming voltage.

RA4/T1G/OSC2/CLKOUT

RA4

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

T1G

OSC2

CLKOUT

RA5

ST

—

Timer1 gate input.

XTAL Crystal/Resonator.

CMOS FOSC/4 output.

—

RA5/T1CKI/OSC1/CLKIN

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

T1CKI

OSC1

CLKIN

RB4

ST

XTAL

ST

—

Timer1 clock input.

Crystal/Resonator.

External clock input/RC oscillator connection.

RB4

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

RB5

RB6

RB7

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

RB6

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

RB7

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

RC0/C2IN+

RC0

C2IN+

RC1

ST

AN

ST

AN

ST

AN

ST

AN

ST

—

CMOS General purpose I/O.

—

Comparator C2 non-inverting input.

RC1/C12IN1-

RC2/C12IN2-

RC3/C12IN3-

RC4/C2OUT

RC5

CMOS General purpose I/O.

C12IN1-

RC2

—

Comparator C1 or C2 inverting input.

CMOS General purpose I/O.

C12IN2-

RC3

—

Comparator C1 or C2 inverting input.

CMOS General purpose I/O.

C12IN3-

RC4

—

Comparator C1 or C2 inverting input.

CMOS General purpose I/O.

CMOS Comparator C2 output.

CMOS General purpose I/O.

C2OUT

RC5

ST

Legend:

AN

TTL

HV

=

Analog input or output

TTL compatible input

High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

XTAL = Crystal

DS41262D-page 14

PIC16F631/677/685/687/689/690

TABLE 1-1:

PINOUT DESCRIPTION – PIC16F631 (CONTINUED)

Input Output

Name

Function

Description

Type

RC6

RC7

VSS

VDD

ST

CMOS General purpose I/O.

RC7

VSS

Power

—

Ground reference.

Positive supply.

VDD

Legend:

AN

TTL

HV

=

Analog input or output

TTL compatible input

High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

XTAL = Crystal

DS41262D-page 15

PIC16F631/677/685/687/689/690

TABLE 1-2:

PINOUT DESCRIPTION – PIC16F677

Input Output

Function

Name

Description

Type

RA0/AN0/C1IN+/ICSPDAT/

ULPWU

RA0

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN0

C1IN+

AN

ST

—

A/D Channel 0 input.

Comparator C1 non-inverting input.

ICSPDAT

ULPWU

RA1

CMOS ICSP™ Data I/O.

AN

TTL

—

Ultra Low-Power Wake-up input.

RA1/AN1/C12IN0-/VREF/

ICSPCLK

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN1

C12IN0-

VREF

AN

ST

—

A/D Channel 1 input.

Comparator C1 or C2 inverting input.

External Voltage Reference for A/D.

ICSP™ clock.

ICSPCLK

RA2

RA2/AN2/T0CKI/INT/C1OUT

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN2

T0CKI

INT

AN

ST

—

A/D Channel 2 input.

Timer0 clock input.

External interrupt pin.

C1OUT

RA3

CMOS Comparator C1 output.

RA3/MCLR/VPP

TTL

—

General purpose input. Individually controlled interrupt-on-

change.

MCLR

VPP

ST

HV

—

Master Clear with internal pull-up.

Programming voltage.

RA4/AN3/T1G/OSC2/CLKOUT

RA4

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN3

T1G

AN

ST

—

A/D Channel 3 input.

Timer1 gate input.

OSC2

CLKOUT

RA5

XTAL Crystal/Resonator.

CMOS FOSC/4 output.

—

RA5/T1CKI/OSC1/CLKIN

RB4/AN10/SDI/SDA

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

T1CKI

OSC1

CLKIN

RB4

ST

XTAL

ST

—

Timer1 clock input.

Crystal/Resonator.

External clock input/RC oscillator connection.

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN10

SDI

AN

ST

—

A/D Channel 10 input.

SPI data input.

2

SDA

RB5

ST

OD

I C™ data input/output.

RB5/AN11

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN11

RB6

AN

—

A/D Channel 11 input.

RB6/SCK/SCL

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

SCK

SCL

ST

CMOS SPI clock.

2

OD

I C™ clock.

Legend:

AN

TTL

HV

=

Analog input or output

TTL compatible input

High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

XTAL = Crystal

DS41262D-page 16

PIC16F631/677/685/687/689/690

TABLE 1-2:

PINOUT DESCRIPTION – PIC16F677 (CONTINUED)

Input Output

Name

Function

Description

Type

RB7

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

RC0/AN4/C2IN+

RC0

AN4

ST

AN

ST

CMOS General purpose I/O.

—

A/D Channel 4 input.

C2IN+

RC1

Comparator C2 non-inverting input.

RC1/AN5/C12IN1-

RC2/AN6/C12IN2-

RC3/AN7/C12IN3-

RC4/C2OUT

CMOS General purpose I/O.

AN5

AN

ST

—

A/D Channel 5 input.

C12IN1-

RC2

Comparator C1 or C2 inverting input.

CMOS General purpose I/O.

AN6

AN

ST

—

A/D Channel 6 input.

C12IN2-

RC3

Comparator C1 or C2 inverting input.

CMOS General purpose I/O.

AN7

AN

ST

—

A/D Channel 7 input.

C12IN3-

RC4

Comparator C1 or C2 inverting input.

CMOS General purpose I/O.

CMOS Comparator C2 output.

CMOS General purpose I/O.

C2OUT

RC5

—

RC5

ST

RC6/AN8/SS

RC6

ST

AN8

AN

ST

—

A/D Channel 8 input.

Slave Select input.

SS

RC7/AN9/SDO

RC7

ST

CMOS General purpose I/O.

A/D Channel 9 input.

CMOS SPI data output.

AN9

AN

—

SDO

VSS

VDD

Power

—

Ground reference.

Positive supply.

VDD

Legend:

AN

TTL

HV

=

Analog input or output

TTL compatible input

High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

XTAL = Crystal

DS41262D-page 17

PIC16F631/677/685/687/689/690

TABLE 1-3:

PINOUT DESCRIPTION – PIC16F685

Input Output

Name

Function

Description

Type

RA0/AN0/C1IN+/ICSPDAT/

ULPWU

RA0

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

AN0

C1IN+

AN

—

A/D Channel 0 input.

Comparator C1 positive input.

ICSPDAT

ULPWU

RA1

TTL

AN

CMOS ICSP™ Data I/O.

—

Ultra Low-Power Wake-up input.

RA1/AN1/C12IN0-/VREF/ICSPCLK

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

AN1

C12IN0-

VREF

AN

ST

—

A/D Channel 1 input.

Comparator C1 or C2 negative input.

External Voltage Reference for A/D.

ICSP™ clock.

ICSPCLK

RA2

RA2/AN2/T0CKI/INT/C1OUT

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

AN2

T0CKI

INT

AN

ST

—

A/D Channel 2 input.

Timer0 clock input.

External interrupt pin.

C1OUT

RA3

CMOS Comparator C1 output.

RA3/MCLR/VPP

TTL

—

General purpose input. Individually controlled interrupt-on-

change.

MCLR

VPP

ST

HV

—

Master Clear with internal pull-up.

Programming voltage.

RA4/AN3/T1G/OSC2/CLKOUT

RA4

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

AN3

T1G

AN

ST

—

A/D Channel 3 input.

Timer1 gate input.

OSC2

CLKOUT

RA5

XTAL Crystal/Resonator.

CMOS FOSC/4 output.

—

RA5/T1CKI/OSC1/CLKIN

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

T1CKI

OSC1

CLKIN

RB4

ST

XTAL

ST

—

Timer1 clock input.

Crystal/Resonator.

External clock input/RC oscillator connection.

RB4/AN10

RB5/AN11

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

AN10

RB5

AN

—

A/D Channel 10 input.

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

AN11

RB6

AN

—

A/D Channel 11 input.

RB6

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

RB7

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

RC0/AN4/C2IN+

RC0

AN4

ST

AN

CMOS General purpose I/O.

—

A/D Channel 4 input.

C2IN+

Comparator C2 positive input.

Legend:

AN

TTL

HV

=

Analog input or output

TTL compatible input

High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

XTAL = Crystal

DS41262D-page 18

PIC16F631/677/685/687/689/690

TABLE 1-3:

PINOUT DESCRIPTION – PIC16F685 (CONTINUED)

Input Output

Name

Function

Description

Type

RC1/AN5/C12IN1-

RC1

AN5

ST

AN

ST

CMOS General purpose I/O.

—

A/D Channel 5 input.

Comparator C1 or C2 negative input.

C12IN1-

RC2

RC2/AN6/C12IN2-/P1D

CMOS General purpose I/O.

AN6

AN

—

A/D Channel 6 input.

C12IN2-

P1D

Comparator C1 or C2 negative input.

CMOS PWM output.

RC3/AN7/C12IN3-/P1C

RC3

ST

CMOS General purpose I/O.

AN7

AN

—

A/D Channel 7 input.

C12IN3-

P1C

Comparator C1 or C2 negative input.

CMOS PWM output.

RC4/C2OUT/P1B

RC5/CCP1/P1A

RC4

ST

CMOS General purpose I/O.

CMOS Comparator C2 output.

CMOS PWM output.

C2OUT

P1B

—

RC5

ST

CMOS General purpose I/O.

CMOS Capture/Compare input.

CMOS PWM output.

CCP1

P1A

ST

RC6/AN8

RC7/AN9

RC6

ST

CMOS General purpose I/O.

AN8

AN

ST

—

A/D Channel 8 input.

RC7

CMOS General purpose I/O.

AN9

AN

Power

—

A/D Channel 9 input.

Ground reference.

Positive supply.

VSS

VDD

VSS

VDD

Legend:

AN

TTL

HV

=

Analog input or output

TTL compatible input

High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

XTAL = Crystal

DS41262D-page 19

PIC16F631/677/685/687/689/690

TABLE 1-4:

PINOUT DESCRIPTION – PIC16F687/PIC16F689

Input Output

Name

Function

Description

Type

RA0/AN0/C1IN+/ICSPDAT/

ULPWU

RA0

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

AN0

C1IN+

AN

—

A/D Channel 0 input.

Comparator C1 positive input.

ICSPDAT

ULPWU

RA1

TTL

AN

CMOS ICSP™ Data I/O.

—

Ultra Low-Power Wake-up input.

RA1/AN1/C12IN0-/VREF/ICSPCLK

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

AN1

C12IN0-

VREF

AN

ST

—

A/D Channel 1 input.

Comparator C1 or C2 negative input.

External Voltage Reference for A/D.

ICSP™ clock.

ICSPCLK

RA2

RA2/AN2/T0CKI/INT/C1OUT

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

AN2

T0CKI

INT

AN

ST

—

A/D Channel 2 input.

Timer0 clock input.

External Interrupt.

C1OUT

RA3

CMOS Comparator C1 output.

RA3/MCLR/VPP

TTL

—

General purpose input. Individually controlled

interrupt-on-change.

MCLR

VPP

ST

HV

—

Master Clear with internal pull-up.

Programming voltage.

RA4/AN3/T1G/OSC2/CLKOUT

RA4

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

AN3

T1G

AN

ST

—

A/D Channel 3 input.

Timer1 gate input.

OSC2

CLKOUT

RA5

XTAL Crystal/Resonator.

CMOS FOSC/4 output.

—

RA5/T1CKI/OSC1/CLKIN

RB4/AN10/SDI/SDA

RB5/AN11/RX/DT

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

T1CKI

OSC1

CLKIN

RB4

ST

XTAL

ST

—

Timer1 clock input.

Crystal/Resonator.

External clock input/RC oscillator connection.

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

AN10

SDI

AN

ST

—

A/D Channel 10 input.

SPI data input.

2

SDA

RB5

ST

OD

I C™ data input/output.

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

AN11

RX

AN

ST

—

A/D Channel 11 input.

EUSART asynchronous input.

DT

CMOS EUSART synchronous data.

Legend:

AN

TTL

HV

=

Analog input or output

TTL compatible input

High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

XTAL = Crystal

OD = Open Drain

DS41262D-page 20

PIC16F631/677/685/687/689/690

TABLE 1-4:

PINOUT DESCRIPTION – PIC16F687/PIC16F689 (CONTINUED)

Input Output

Name

Function

Description

Type

RB6/SCK/SCL

RB6

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

SCK

SCL

RB7

ST

CMOS SPI clock.

2

OD

I C™ clock.

RB7/TX/CK

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

TX

CK

—

ST

CMOS EUSART asynchronous output.

CMOS EUSART synchronous clock.

CMOS General purpose I/O.

RC0/AN4/C2IN+

RC1/AN5/C12IN1-

RC2/AN6/C12IN2-

RC3/AN7/C12IN3-

RC4/C2OUT

RC0

ST

AN4

AN

ST

—

A/D Channel 4 input.

C2IN+

RC1

Comparator C2 positive input.

CMOS General purpose I/O.

AN5

AN

ST

—

A/D Channel 5 input.

C12IN1-

RC2

Comparator C1 or C2 negative input.

CMOS General purpose I/O.

AN6

AN

ST

—

A/D Channel 6 input.

C12IN2-

RC3

Comparator C1 or C2 negative input.

CMOS General purpose I/O.

AN7

AN

ST

—

A/D Channel 7 input.

C12IN3-

RC4

Comparator C1 or C2 negative input.

CMOS General purpose I/O.

CMOS Comparator C2 output.

CMOS General purpose I/O.

C2OUT

RC5

—

RC5

ST

RC6/AN8/SS

RC6

ST

AN8

AN

ST

—

A/D Channel 8 input.

Slave Select input.

SS

RC7/AN9/SDO

RC7

ST

CMOS General purpose I/O.

A/D Channel 9 input.

CMOS SPI data output.

AN9

AN

—

SDO

VSS

VDD

Power

—

Ground reference.

Positive supply.

VDD

Legend:

AN

TTL

HV

=

Analog input or output

TTL compatible input

High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

XTAL = Crystal

OD = Open Drain

DS41262D-page 21

PIC16F631/677/685/687/689/690

TABLE 1-5:

PINOUT DESCRIPTION – PIC16F690

Input Output

Name

Function

Description

Type

RA0/AN0/C1IN+/ICSPDAT/

ULPWU

RA0

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

AN0

C1IN+

AN

—

A/D Channel 0 input.

Comparator C1 positive input.

ICSPDAT

ULPWU

RA1

TTL

AN

CMOS ICSP™ Data I/O.

—

Ultra Low-Power Wake-up input.

RA1/AN1/C12IN0-/VREF/ICSPCLK

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

AN1

C12IN0-

VREF

AN

ST

—

A/D Channel 1 input.

Comparator C1 or C2 negative input.

External Voltage Reference for A/D.

ICSP™ clock.

ICSPCLK

RA2

RA2/AN2/T0CKI/INT/C1OUT

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

AN2

T0CKI

INT

AN

ST

—

A/D Channel 2 input.

Timer0 clock input.

External interrupt.

C1OUT

RA3

CMOS Comparator C1 output.

RA3/MCLR/VPP

TTL

—

General purpose input. Individually controlled interrupt-on-

change.

MCLR

VPP

ST

HV

—

Master Clear with internal pull-up.

Programming voltage.

RA4/AN3/T1G/OSC2/CLKOUT

RA4

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

AN3

T1G

AN

ST

—

A/D Channel 3 input.

Timer1 gate input.

OSC2

CLKOUT

RA5

XTAL Crystal/Resonator.

CMOS FOSC/4 output.

—

RA5/T1CKI/OSC1/CLKIN

RB4/AN10/SDI/SDA

RB5/AN11/RX/DT

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

T1CKI

OSC1

CLKIN

RB4

ST

XTAL

ST

—

Timer1 clock input.

Crystal/Resonator.

External clock input/RC oscillator connection.

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

AN10

SDI

AN

ST

—

A/D Channel 10 input.

SPI data input.

2

SDA

RB5

ST

OD

I C™ data input/output.

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

AN11

RX

AN

ST

—

A/D Channel 11 input.

EUSART asynchronous input.

DT

CMOS EUSART synchronous data.

Legend:

AN

TTL

HV

=

Analog input or output

TTL compatible input

High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

XTAL = Crystal

OD = Open Drain

DS41262D-page 22

PIC16F631/677/685/687/689/690

TABLE 1-5:

PINOUT DESCRIPTION – PIC16F690 (CONTINUED)

Input Output

Name

Function

Description

Type

RB6/SCK/SCL

RB6

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

SCK

SCL

RB7

ST

CMOS SPI clock.

2

OD

I C™ clock.

RB7/TX/CK

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

TX

CK

—

ST

AN

ST

AN

ST

AN

—

CMOS EUSART asynchronous output.

CMOS EUSART synchronous clock.

CMOS General purpose I/O.

RC0/AN4/C2IN+

RC0

AN4

—

A/D Channel 4 input.

C2IN+

RC1

Comparator C2 positive input.

RC1/AN5/C12IN1-

RC2/AN6/C12IN2-/P1D

CMOS General purpose I/O.

AN5

—

A/D Channel 5 input.

C12IN1-

RC2

Comparator C1 or C2 negative input.

CMOS General purpose I/O.

AN6

—

A/D Channel 6 input.

C12IN2-

P1D

Comparator C1 or C2 negative input.

CMOS PWM output.

RC3/AN7/C12IN3-/P1C

RC3

ST

AN

—

CMOS General purpose I/O.

AN7

—

A/D Channel 7 input.

C12IN3-

P1C

Comparator C1 or C2 negative input.

CMOS PWM output.

RC4/C2OUT/P1B

RC5/CCP1/P1A

RC6/AN8/SS

RC4

ST

—

CMOS General purpose I/O.

CMOS Comparator C2 output.

CMOS PWM output.

C2OUT

P1B

—

RC5

ST

AN

ST

AN

—

CMOS General purpose I/O.

CMOS Capture/Compare input.

CMOS PWM output.

CCP1

P1A

RC6

CMOS General purpose I/O.

AN8

—

A/D Channel 8 input.

Slave Select input.

SS

RC7/AN9/SDO

RC7

CMOS General purpose I/O.

A/D Channel 9 input.

CMOS SPI data output.

AN9

—

SDO

VSS

VDD

Power

—

Ground reference.

Positive supply.

VDD

Legend:

AN

TTL

HV

=

Analog input or output

TTL compatible input

High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

XTAL = Crystal

OD = Open Drain

DS41262D-page 23

PIC16F631/677/685/687/689/690

NOTES:

DS41262D-page 24

PIC16F631/677/685/687/689/690

FIGURE 2-2:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F685/689/690

2.0

2.1

MEMORY ORGANIZATION

Program Memory Organization

The PIC16F631/677/685/687/689/690 has a 13-bit

program counter capable of addressing an 8K x 14

program memory space. Only the first 1K x 14

(0000h-03FFh) is physically implemented for the

PIC16F631, the first 2K x 14 (0000h-07FFh) for the

PIC16F677/PIC16F687, and the first 4K x 14

(0000h-0FFFh) for the PIC16F685/PIC16F689/

PC<12:0>

13

CALL, RETURN

RETFIE, RETLW

Stack Level 1

Stack Level 2

PIC16F690. Accessing

a location above these

boundaries will cause a wraparound. The Reset vector

is at 0000h and the interrupt vector is at 0004h (see

Figures 2-1 through 2-3).

Stack Level 8

Reset Vector

0000h

FIGURE 2-1:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F631

0004h

0005h

Interrupt Vector

On-chip Program

Memory

PC<12:0>

13

CALL, RETURN

RETFIE, RETLW

0FFFh

1000h

Stack Level 1

Stack Level 2

Access 0-FFFh

1FFFh

Stack Level 8

Reset Vector

0000h

0004h

0005h

Interrupt Vector

On-chip Program

Memory

03FFh

0400h

Access 0-3FFh

1FFFh

DS41262D-page 25

PIC16F631/677/685/687/689/690

FIGURE 2-3:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F677/PIC16F687

2.2

Data Memory Organization

The data memory (see Figures 2-6 through 2-8) is

partitioned into four banks which contain the General

Purpose Registers (GPR) and the Special Function

Registers (SFR). The Special Function Registers are

located in the first 32 locations of each bank. The

General Purpose Registers, implemented as static

RAM, are located in the last 96 locations of each Bank.

Register locations F0h-FFh in Bank 1, 170h-17Fh in

Bank 2 and 1F0h-1FFh in Bank 3 point to addresses

70h-7Fh in Bank 0. The actual number of General

Purpose Resisters (GPR) in each Bank depends on the

device. Details are shown in Figures 2-4 through 2-8.

All other RAM is unimplemented and returns ‘0’ when

read. RP<1:0> of the STATUS register are the bank

select bits:

PC<12:0>

13

CALL, RETURN

RETFIE, RETLW

Stack Level 1

Stack Level 2

Stack Level 8

Reset Vector

0000h

RP1

0

RP0

0

0004h

0005h

Interrupt Vector

→

Bank 0 is selected

Bank 1 is selected

Bank 2 is selected

Bank 3 is selected

0

1

On-chip Program

Memory

1

0

1

07FFh

0800h

2.2.1

GENERAL PURPOSE REGISTER

FILE

Access 0-7FFh

The register file is organized as 128 x 8 in the

PIC16F687 and 256 in the

1FFFh

x

8

PIC16F685/PIC16F689/PIC16F690. Each register is

accessed, either directly or indirectly, through the File

Select Register (FSR) (see Section 2.4 “Indirect

Addressing, INDF and FSR Registers”).

2.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (see Tables 2-1

through 2-4). These registers are static RAM.

The special registers can be classified into two sets:

core and peripheral. The Special Function Registers

associated with the “core” are described in this section.

Registers related to the operation of peripheral features

are described in the section of that peripheral feature.

DS41262D-page 26

PIC16F631/677/685/687/689/690

FIGURE 2-4:

PIC16F631 SPECIAL FUNCTION REGISTERS

File

Address

Indirect addr. ⁽¹⁾00h

Indirect addr. ⁽¹⁾80h

Indirect addr. ⁽¹⁾100h

Indirect addr. ⁽¹⁾180h

TMR0

PCL

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

OPTION_REG 81h

TMR0

PCL

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

11Fh

120h

OPTION_REG 181h

PCL

STATUS

FSR

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

PCL

STATUS

FSR

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

19Fh

1A0h

STATUS

FSR

STATUS

FSR

PORTA

PORTB

PORTC

TRISA

TRISB

TRISC

PORTA

PORTB

PORTC

TRISA

TRISB

TRISC

PCLATH

INTCON

PIR1

PCLATH

INTCON

PIE1

PCLATH

INTCON

EEDAT

PCLATH

INTCON

EECON1

EECON2⁽¹⁾

PIR2

PIE2

EEADR

TMR1L

TMR1H

T1CON

PCON

OSCCON

OSCTUNE

WPUA

IOCA

WPUB

IOCB

WDTCON

VRCON

CM1CON0

CM2CON0

CM2CON1

ANSEL

SRCON

3Fh

40h

General

Purpose

Registers

6Fh

70h

7Fh

EFh

F0h

FFh

16Fh

170h

17Fh

1EFh

1F0h

1FFh

64 Bytes

Bank 0

accesses

70h-7Fh

accesses

70h-7Fh

accesses

70h-7Fh

Bank 1

Bank 2

Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

DS41262D-page 27

PIC16F631/677/685/687/689/690

FIGURE 2-5:

PIC16F677 SPECIAL FUNCTION REGISTERS

File

Address

Indirect addr. ⁽¹⁾00h

File

Address

Indirect addr. ⁽¹⁾80h

Address

Indirect addr. ⁽¹⁾100h

Address

Indirect addr. ⁽¹⁾180h

TMR0

PCL

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

OPTION_REG 81h

TMR0

PCL

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

11Fh

120h

OPTION_REG 181h

PCL

STATUS

FSR

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

PCL

STATUS

FSR

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

19Fh

1A0h

STATUS

FSR

STATUS

FSR

PORTA

PORTB

PORTC

TRISA

TRISB

TRISC

PORTA

PORTB

PORTC

TRISA

TRISB

TRISC

PCLATH

INTCON

PIR1

PCLATH

INTCON

PIE1

PCLATH

INTCON

EEDAT

PCLATH

INTCON

EECON1

EECON2⁽¹⁾

PIR2

PIE2

EEADR

TMR1L

TMR1H

T1CON

PCON

OSCCON

OSCTUNE

SSPBUF

SSPCON

SSPADD⁽²⁾

SSPSTAT

WPUA

WPUB

IOCB

IOCA

WDTCON

VRCON

CM1CON0

CM2CON0

CM2CON1

ADRESH

ADCON0

ADRESL

ADCON1

ANSEL

SRCON

ANSELH

General

Purpose

Register

General

Purpose

Register

32 Bytes

BFh

C0h

96 Bytes

EFh

F0h

FFh

16Fh

170h

17Fh

1EFh

1F0h

1FFh

accesses

70h-7Fh

accesses

70h-7Fh

accesses

70h-7Fh

7Fh

Bank 0

Bank 1

Bank 2

Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

2: Address 93h also accesses the SSP Mask (SSPMSK) register under certain conditions.

See Registers 13-2 and 13-3 for more details.

DS41262D-page 28

PIC16F631/677/685/687/689/690

FIGURE 2-6:

PIC16F685 SPECIAL FUNCTION REGISTERS

File

Address

Indirect addr. ⁽¹⁾00h

Indirect addr. ⁽¹⁾80h

Indirect addr. ⁽¹⁾100h

Indirect addr. ⁽¹⁾180h

TMR0

PCL

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

OPTION_REG 81h

TMR0

PCL

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

11Fh

120h

OPTION_REG 181h

PCL

STATUS

FSR

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

PCL

STATUS

FSR

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

19Fh

1A0h

STATUS

FSR

STATUS

FSR

PORTA

PORTB

PORTC

TRISA

TRISB

TRISC

PORTA

PORTB

PORTC

TRISA

TRISB

TRISC

PCLATH

INTCON

PIR1

PCLATH

INTCON

PIE1

PCLATH

INTCON

EEDAT

PCLATH

INTCON

EECON1

EECON2⁽¹⁾

PIR2

PIE2

EEADR

EEDATH

EEADRH

TMR1L

TMR1H

T1CON

TMR2

PCON

OSCCON

OSCTUNE

T2CON

PR2

CCPR1L

CCPR1H

CCP1CON

WPUA

IOCA

WPUB

IOCB

WDTCON

VRCON

CM1CON0

CM2CON0

CM2CON1

PWM1CON

ECCPAS

ADRESH

ADCON0

PSTRCON

SRCON

ADRESL

ADCON1

ANSEL

ANSELH

General

Purpose

Register

General

Purpose

Register

General

Purpose

Register

80 Bytes

96 Bytes

EFh

F0h

FFh

16Fh

170h

17Fh

accesses

70h-7Fh

accesses

70h-7Fh

accesses

70h-7Fh

1F0h

1FFh

7Fh

Bank 0

Bank 1

Bank 2

Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

DS41262D-page 29

PIC16F631/677/685/687/689/690

FIGURE 2-7:

PIC16F687/PIC16F689 SPECIAL FUNCTION REGISTERS

File

Address

Indirect addr. ⁽¹⁾00h

Indirect addr. ⁽¹⁾80h

Indirect addr. ⁽¹⁾100h

Indirect addr. ⁽¹⁾180h

TMR0

PCL

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

OPTION_REG 81h

TMR0

PCL

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

11Fh

120h

OPTION_REG 181h

PCL

STATUS

FSR

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

PCL

STATUS

FSR

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

19Fh

1A0h

STATUS

FSR

STATUS

FSR

PORTA

PORTB

PORTC

TRISA

TRISB

TRISC

PORTA

PORTB

PORTC

TRISA

TRISB

TRISC

PCLATH

INTCON

PIR1

PCLATH

INTCON

PIE1

PCLATH

INTCON

EEDAT

PCLATH

INTCON

EECON1

EECON2⁽¹⁾

PIR2

PIE2

EEADR

TMR1L

TMR1H

T1CON

PCON

EEDATH⁽³⁾

EEADRH⁽³⁾

OSCCON

OSCTUNE

SSPBUF

SSPCON

SSPADD⁽²⁾

SSPSTAT

WPUA

WPUB

IOCB

IOCA

WDTCON

TXSTA

RCSTA

TXREG

RCREG

VRCON

SPBRG

CM1CON0

CM2CON0

CM2CON1

SPBRGH

BAUDCTL

ADRESH

ADCON0

ADRESL

ADCON1

ANSEL

SRCON

ANSELH

General

Purpose

Register

32 Bytes

General

Purpose

Register

80 Bytes

(PIC16F689

only)

General

Purpose

Register

BFh

C0h

48 Bytes

(PIC16F689

only)

96 Bytes

EFh

F0h

FFh

accesses

70h-7Fh

accesses

70h-7Fh

170h

17Fh

accesses

70h-7Fh

1F0h

1FFh

7Fh

Bank 0

Bank 1

Bank 2

Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

2: Address 93h also accesses the SSP Mask (SSPMSK) register under certain conditions.

See Registers 13-2 and 13-3 for more details.

3: PIC16F689 only.

DS41262D-page 30

PIC16F631/677/685/687/689/690

FIGURE 2-8:

PIC16F690 SPECIAL FUNCTION REGISTERS

File

Address

Indirect addr. ⁽¹⁾00h

Indirect addr. ⁽¹⁾80h

Indirect addr. ⁽¹⁾100h

Indirect addr. ⁽¹⁾180h

TMR0

PCL

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

OPTION_REG 81h

TMR0

PCL

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

11Fh

120h

OPTION_REG 181h

PCL

STATUS

FSR

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

PCL

STATUS

FSR

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

19Fh

1A0h

STATUS

FSR

STATUS

FSR

PORTA

PORTB

PORTC

TRISA

TRISB

TRISC

PORTA

PORTB

PORTC

TRISA

TRISB

TRISC

PCLATH

INTCON

PIR1

PCLATH

INTCON

PIE1

PCLATH

INTCON

EEDAT

PCLATH

INTCON

EECON1

EECON2⁽¹⁾

PIR2

PIE2

EEADR

EEDATH

EEADRH

TMR1L

TMR1H

T1CON

TMR2

PCON

OSCCON

OSCTUNE

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA

TXREG

RCREG

PR2

SSPADD⁽²⁾

SSPSTAT

WPUA

WPUB

IOCB

IOCA

WDTCON

TXSTA

VRCON

SPBRG

SPBRGH

BAUDCTL

CM1CON0

CM2CON0

CM2CON1

PWM1CON

ECCPAS

ADRESH

ADCON0

PSTRCON

SRCON

ADRESL

ADCON1

ANSEL

ANSELH

General

Purpose

Register

General

Purpose

Register

General

Purpose

Register

80 Bytes

96 Bytes

EFh

F0h

FFh

16Fh

170h

17Fh

accesses

70h-7Fh

accesses

70h-7Fh

accesses

70h-7Fh

1F0h

1FFh

7Fh

Bank 0

Bank 1

Bank 2

Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

2: Address 93h also accesses the SSP Mask (SSPMSK) register under certain conditions.

See Registers 13-2 and 13-3 for more details.

DS41262D-page 31

PIC16F631/677/685/687/689/690

TABLE 2-1:

PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Value on

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

Bank 0

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 Module Register

xxxx xxxx

0000 0000

0001 1xxx

xxxx xxxx

--xx xxxx

xxxx ----

xxxx xxxx

—

44,201

81,201

44,201

36,201

44,201

59,201

69,201

76,201

—

TMR0

PCL

Program Counter’s (PC) Least Significant Byte

STATUS

FSR

PORTA⁽⁷⁾

PORTB⁽⁷⁾

PORTC⁽⁷⁾

—

IRP

RP1

RP0

TO

PD

Z

DC

C

Indirect Data Memory Address Pointer

—

RA5

RB5

RC5

RA4

RB4

RC4

RA3

—

RA2

—

RA1

—

RA0

—

RB7

RB6

RC6

RC7

RC3

RC2

RC1

RC0

Unimplemented

—

0Ah PCLATH

0Bh INTCON

0Ch PIR1

—

Write Buffer for upper 5 bits of Program Counter

---0 0000

44,201

38,201

41,201

42,201

86,201

GIE

—

PEIE

ADIF⁽⁴⁾

C2IF

T0IE

INTE

TXIF⁽²⁾

EEIF

RABIE

T0IF

INTF

RABIF⁽¹⁾0000 000x

RCIF⁽²⁾

C1IF

SSPIF⁽⁵⁾CCP1IF⁽³⁾TMR2IF⁽³⁾TMR1IF -000 0000

0Dh PIR2

OSFIF

—

0000 ----

xxxx xxxx

0Eh TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

0Fh

TMR1H

10h

11h

12h

13h

14h

T1CON

TMR2⁽³⁾

T2CON⁽³⁾

SSPBUF⁽⁵⁾

SSPCON^{(5, 6)}

T1GINV

Timer2 Module Register

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000

TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000

88,201

91,201

92,201

178,201

177,201

0000 0000

—

Synchronous Serial Port Receive Buffer/Transmit Register

WCOL SSPOV SSPEN CKP SSPM3

xxxx xxxx

SSPM0 0000 0000

xxxx xxxx

SSPM2

SSPM1

15h

16h

17h

18h

19h

CCPR1L⁽³⁾

CCPR1H⁽³⁾

CCP1CON⁽³⁾

RCSTA⁽²⁾

Capture/Compare/PWM Register 1 (LSB)

Capture/Compare/PWM Register 1 (MSB)

128,201

127,201

xxxx xxxx

P1M1

SPEN

P1M0

RX9

DC1B1

SREN

DC1B0

CREN

CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000

ADDEN

FERR

OERR

RX9D

0000 000x

0000 0000

—

159,201

151

TXREG⁽²⁾

EUSART Transmit Data Register

EUSART Receive Data Register

Unimplemented

1Ah RCREG⁽²⁾

154

1Bh

1Ch

1Dh

—

PWM1CON⁽³⁾

PRSEN

PDC6

PDC5

PDC4

PDC3

PDC2

PDC1

PDC0

0000 0000

144,201

ECCPAS⁽³⁾

ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1

A/D Result Register High Byte

PSSAC0

PSSBD1

PSSBD0 0000 0000

141,201

115,201

113,201

1Eh ADRESH⁽⁴⁾

xxxx xxxx

1Fh

ADCON0⁽⁴⁾

ADFM

VCFG

CHS3

CHS2

CHS1

CHS0

GO/DONE

ADON

0000 0000

Legend:

– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented

Note 1:

MCLR and WDT Reset do not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the

mismatch exists.

2:

3:

4:

5:

6:

PIC16F687/PIC16F689/PIC16F690 only.

PIC16F685/PIC16F690 only.

PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.

PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.

When SSPCON register bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed through the SSPMSK

register. See Registers 13-2 and 13-3 for more detail.

7:

Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the

data latches are either undefined (POR) or unchanged (other Resets).

DS41262D-page 32

PIC16F631/677/685/687/689/690

TABLE 2-2:

PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Value on

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

Bank 1

80h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx

44,201

37,201

44,201

81h

OPTION_REG RABPU

INTEDG

Program Counter’s (PC) Least Significant Byte

IRP RP1 RP0 TO

Indirect Data Memory Address Pointer

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

0000 0000

82h

PCL

83h

84h

85h

86h

87h

88h

89h

STATUS

FSR

PD

Z

DC

C

0001 1xxx

xxxx xxxx

--11 1111

1111 ----

1111 1111

—

36,201

44,201

59,201

70,202

76,201

—

TRISA

TRISB

TRISC

—

TRISA5

TRISB5

TRISC5

TRISA4

TRISB4

TRISC4

TRISA3

—

TRISA2

—

TRISA1

—

TRISA0

—

TRISB7

TRISC7

TRISB6

TRISC6

TRISC3

TRISC2

TRISC1

TRISC0

Unimplemented

—

8Ah PCLATH

8Bh INTCON

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

0000 000x

44,201

38,201

GIE

PEIE

T0IE

INTE

RABIE

T0IF

INTF

RABIF⁽¹⁾

8Ch PIE1

8Dh PIE2

8Eh PCON

—

OSFIE

—

ADIE⁽⁴⁾

C2IE

—

RCIE⁽²⁾

C1IE

TXIE⁽²⁾

EEIE

SSPIE⁽⁵⁾CCP1IE⁽³⁾TMR2IE⁽³⁾TMR1IE

-000 0000

0000 ----

--01 --qq

-110 q000

---0 0000

—

39,202

40,202

43,202

48,202

52,202

—

ULPWUE SBOREN

—

POR

LTS

BOR

SCS

TUN0

8Fh

90h

91h

92h

93h

OSCCON

OSCTUNE

—

IRCF2

—

IRCF1

—

IRCF0

TUN4

OSTS

TUN3

HTS

TUN2

—

TUN1

Unimplemented

PR2⁽³⁾

Timer2 Period Register

1111 1111

0000 0000

91,202

184,202

SSPADD^{(5, 7)}

Synchronous Serial Port (I²C mode) Address Register

93h

94h

95h

96h

97h

SSPMSK^{(5, 7)}

SSPSTAT⁽⁵⁾

WPUA⁽⁶⁾

MSK7

SMP

—

MSK6

CKE

—

MSK5

D/A

MSK4

P

MSK3

S

MSK2

R/W

MSK1

UA

MSK0

BF

1111 1111

0000 0000

--11 -111

--00 0000

187,202

176,202

62,202

WPUA5

IOCA5

—

WPUA4

IOCA4

—

WPUA2

IOCA2

WPUA1

IOCA1

WPUA0

IOCA0

IOCA

—

IOCA3

62,202

WDTCON

—

WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000

209,202

98h

99h

TXSTA⁽²⁾

SPBRG⁽²⁾

CSRC

BRG7

TX9

TXEN

BRG5

BRG13

—

SYNC

BRG4

BRG12

SCKP

SENDB

BRG3

BRGH

BRG2

BRG10

—

TRMT

BRG1

BRG9

WUE

TX9D

BRG0

BRG8

ABDEN

0000 0010

0000 0000

01-0 0-00

158,202

161,202

160,202

BRG6

BRG14

RCIDL

9Ah SPBRGH⁽²⁾

9Bh BAUDCTL⁽²⁾

BRG15

ABDOVF

BRG11

BRG16

9Ch

9Dh

—

Unimplemented

—

9Eh ADRESL⁽⁴⁾

A/D Result Register Low Byte

ADCS2 ADCS1

xxxx xxxx

-000 ----

115,202

114,202

9Fh

ADCON1⁽⁴⁾

—

ADCS0

—

Legend:

Note 1:

– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented

MCLR and WDT Reset do not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the

mismatch exists.

2:

3:

4:

5:

6:

7:

PIC16F687/PIC16F689/PIC16F690 only.

PIC16F685/PIC16F690 only.

PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.

PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.

RA3 pull-up is enabled when pin is configured as MCLR in Configuration Word.

Accessible only when SSPCON register bits SSPM<3:0> = 1001.

DS41262D-page 33

PIC16F631/677/685/687/689/690

TABLE 2-3:

PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2

Value on

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

Bank 2

100h INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 Module Register

xxxx xxxx

0000 0000

0001 1xxx

xxxx xxxx

--xx xxxx

xxxx ----

xxxx xxxx

—

44,201

81,201

44,201

36,201

44,201

59,201

69,201

76,201

—

101h TMR0

102h PCL

Program Counter’s (PC) Least Significant Byte

103h STATUS

104h FSR

105h PORTA⁽⁴⁾

106h PORTB⁽⁴⁾

107h PORTC⁽⁴⁾

IRP

RP1

RP0

TO

PD

Z

DC

C

Indirect Data Memory Address Pointer

—

RA5

RB5

RC5

RA4

RB4

RC4

RA3

—

RA2

—

RA1

—

RA0

—

RB7

RB6

RC6

RC7

RC3

RC2

RC1

RC0

108h

109h

—

Unimplemented

—

10Ah PCLATH

10Bh INTCON

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

44,201

38,201

GIE

PEIE

T0IE

INTE

RABIE

EEDAT3

EEADR3

T0IF

INTF

RABIF⁽¹⁾0000 000x

EEDAT

EEADR

EEDAT7

EEDAT6

EEDAT5

EEDAT4

EEDAT2

EEADR2

EEDAT1

EEADR1

EEDAT0 0000 0000 120,202

EEADR0 0000 0000 120,202

10Ch

EEADR7⁽³⁾EEADR6 EEADR5 EEADR4

10Dh

10Eh EEDATH⁽²⁾

10Fh EEADRH⁽²⁾

—

--00 0000 120,202

---- 0000 120,202

EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0

EEADRH3 EEADRH2 EEADRH1 EEADRH0

—

110h

111h

112h

113h

114h

—

Unimplemented

—

115h WPUB

116h IOCB

WPUB7

IOCB7

WPUB6

IOCB6

WPUB5

IOCB5

WPUB4

IOCB4

—

1111 ----

0000 ----

—

70,202

—

117h

—

Unimplemented

118h VRCON

119h CM1CON0

11Ah CM2CON0

11Bh CM2CON1

C1VREN

C1ON

C2VREN

VRR

C1OE

C2OE

—

VP6EN

C1POL

C2POL

—

VR3

—

VR2

C1R

C2R

—

VR1

VR0

0000 0000 106,202

C1OUT

C2OUT

C1CH1

C2CH1

T1GSS

C1CH0

C2CH0

0000 -000

98,202

99,202

C2ON

—

MC1OUT MC2OUT

Unimplemented

—

C2SYNC 00-- --10 101,202

11Ch

11Dh

—

Unimplemented

—

11Eh ANSEL

11Fh ANSELH⁽³⁾

ANS7

—

ANS6

—

ANS5

—

ANS4

—

ANS3⁽³⁾

ANS11

ANS2⁽³⁾

ANS10

ANS1

ANS9

ANS0

ANS8

1111 1111

---- 1111

61,202

115,202

Legend:

– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented

Note 1:

MCLR and WDT Reset does not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the

mismatch exists.

2:

3:

4:

PIC16F685/PIC16F689/PIC16F690 only.

PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.

Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the

data latches are either undefined (POR) or unchanged (other Resets).

DS41262D-page 34

PIC16F631/677/685/687/689/690

TABLE 2-4:

PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3

Value on

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

Bank 3

180h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx

44,201

37,201

44,201

181h

OPTION_REG RABPU

INTEDG

Program Counter’s (PC) Least Significant Byte

IRP RP1 RP0 TO

Indirect Data Memory Address Pointer

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

0000 0000

182h

PCL

183h

184h

185h

186h

187h

188h

189h

STATUS

FSR

PD

Z

DC

C

0001 1xxx

xxxx xxxx

--11 1111

1111 ----

1111 1111

—

36,201

44,201

59,201

70,202

76,202

—

TRISA

TRISB

TRISC

—

TRISA5

TRISB5

TRISC5

TRISA4

TRISB4

TRISC4

TRISA3

—

TRISA2

—

TRISA1

—

TRISA0

—

TRISB7

TRISC7

TRISB6

TRISC6

TRISC3

TRISC2

TRISC1

TRISC0

Unimplemented

—

18Ah PCLATH

18Bh INTCON

18Ch EECON1

18Dh EECON2

—

T0IE

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

44,201

38,201

121,202

119,202

—

GIE

PEIE

—

INTE

—

RABIE

T0IF

INTF

WR

RABIF⁽¹⁾0000 000x

EEPGD⁽²⁾

WRERR

WREN

RD

x--- x000

EEPROM Control Register 2 (not a physical register)

Unimplemented

---- ----

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

Unimplemented

—

19Dh PSTRCON⁽²⁾

—

STRSYNC

C2REN

STRD

STRC

STRB

—

STRA

—

---0 0001

0000 00--

—

145,202

103,202

—

19Eh SRCON

SR1

SR0

C1SEN

PULSS

PULSR

19Fh

—

Unimplemented

Legend:

– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented

Note 1:

MCLR and WDT Reset does not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the

mismatch exists.

2:

PIC16F685/PIC16F690 only.

DS41262D-page 35

PIC16F631/677/685/687/689/690

For example, CLRF STATUS,will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’(where u= unchanged).

2.2.2.1

STATUS Register

The STATUS register, shown in Register 2-1, contains:

• the arithmetic status of the ALU

• the Reset status

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not affect-

ing any Status bits, see Section 15.0 “Instruction Set

Summary”

• the bank select bits for data memory (GPR and

SFR)

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

Note 1: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction. See the SUBLW and SUBWF

instructions for examples.

REGISTER 2-1:

STATUS: STATUS REGISTER

R/W-0

IRP

R/W-0

RP1

R/W-0

RP0

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC⁽¹⁾

R/W-x

C⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

IRP: Register Bank Select bit (used for indirect addressing)

1= Bank 2, 3 (100h-1FFh)

0= Bank 0, 1 (00h-FFh)

bit 6-5

RP<1:0>: Register Bank Select bits (used for direct addressing)

00= Bank 0 (00h-7Fh)

01= Bank 1 (80h-FFh)

10= Bank 2 (100h-17Fh)

11= Bank 3 (180h-1FFh)

bit 4

bit 3

bit 2

bit 1

bit 0

TO: Time-out bit

1= After power-up, CLRWDTinstruction or SLEEPinstruction

0= A WDT time-out occurred

PD: Power-down bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)⁽¹⁾

1= A carry-out from the 4th low-order bit of the result occurred

0= No carry-out from the 4th low-order bit of the result

C: Carry/Borrow bit⁽¹⁾(ADDWF, ADDLW, SUBLW, SUBWF instructions)⁽¹⁾

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order

bit of the source register.

DS41262D-page 36

PIC16F631/677/685/687/689/690

2.2.2.2

OPTION Register

Note:

To achieve a 1:1 prescaler assignment for

Timer0, assign the prescaler to the WDT by

setting PSA bit of the OPTION register to

‘1’. See Section 6.3 “Timer1 Prescaler”.

The OPTION register, shown in Register 2-2, is a

readable and writable register, which contains various

control bits to configure:

• Timer0/WDT prescaler

• External RA2/INT interrupt

• Timer0

• Weak pull-ups on PORTA/PORTB

REGISTER 2-2:

OPTION_REG: OPTION REGISTER

R/W-1

RABPU

bit 7

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

PS2

R/W-1

PS1

R/W-1

PS0

INTEDG

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

RABPU: PORTA/PORTB Pull-up Enable bit

1= PORTA/PORTB pull-ups are disabled

0= PORTA/PORTB pull-ups are enabled by individual PORT latch values

INTEDG: Interrupt Edge Select bit

1= Interrupt on rising edge of RA2/INT pin

0= Interrupt on falling edge of RA2/INT pin

T0CS: Timer0 Clock Source Select bit

1= Transition on RA2/T0CKI pin

0= Internal instruction cycle clock (FOSC/4)

T0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on RA2/T0CKI pin

0= Increment on low-to-high transition on RA2/T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler is assigned to the WDT

0= Prescaler is assigned to the Timer0 module

PS<2:0>: Prescaler Rate Select bits

Bit Value

Timer0 Rate WDT Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

DS41262D-page 37

PIC16F631/677/685/687/689/690

2.2.2.3

INTCON Register

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

The INTCON register, shown in Register 2-3, is a

readable and writable register, which contains the various

enable and flag bits for TMR0 register overflow, PORTA

change and external RA2/AN2/T0CKI/INT/C1OUT pin

interrupts.

REGISTER 2-3:

INTCON: INTERRUPT CONTROL REGISTER

R/W-0

GIE

R/W-0

PEIE

R/W-0

T0IE

R/W-0

INTE

R/W-0

RABIE^(1,3)

R/W-0

T0IF⁽²⁾

R/W-0

INTF

R/W-x

RABIF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

GIE: Global Interrupt Enable bit

1= Enables all unmasked interrupts

0= Disables all interrupts

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

PEIE: Peripheral Interrupt Enable bit

1= Enables all unmasked peripheral interrupts

0= Disables all peripheral interrupts

T0IE: Timer0 Overflow Interrupt Enable bit

1= Enables the Timer0 interrupt

0= Disables the Timer0 interrupt

INTE: RA2/INT External Interrupt Enable bit

1= Enables the RA2/INT external interrupt

0= Disables the RA2/INT external interrupt

RABIE: PORTA/PORTB Change Interrupt Enable bit^(1,3)

1= Enables the PORTA/PORTB change interrupt

0= Disables the PORTA/PORTB change interrupt

T0IF: Timer0 Overflow Interrupt Flag bit⁽²⁾

1= TMR0 register has overflowed (must be cleared in software)

0= TMR0 register did not overflow

INTF: RA2/INT External Interrupt Flag bit

1= The RA2/INT external interrupt occurred (must be cleared in software)

0= The RA2/INT external interrupt did not occur

RABIF: PORTA/PORTB Change Interrupt Flag bit

1= When at least one of the PORTA or PORTB general purpose I/O pins changed state (must be

cleared in software)

0= None of the PORTA or PORTB general purpose I/O pins have changed state

Note 1: IOCA or IOCB register must also be enabled.

2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before

clearing T0IF bit.

3: Includes ULPWU interrupt.

DS41262D-page 38

PIC16F631/677/685/687/689/690

2.2.2.4

PIE1 Register

The PIE1 register contains the interrupt enable bits, as

shown in Register 2-4.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

REGISTER 2-4:

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

U-0

—

R/W-0

ADIE⁽⁵⁾

R/W-0

RCIE⁽³⁾

R/W-0

TXIE⁽³⁾

R/W-0

SSPIE⁽⁴⁾

R/W-0

CCP1IE⁽²⁾

R/W-0

TMR2IE⁽¹⁾

R/W-0

TMR1IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

ADIE: A/D Converter (ADC) Interrupt Enable bit⁽⁵⁾

1= Enables the ADC interrupt

0= Disables the ADC interrupt

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

RCIE: EUSART Receive Interrupt Enable bit⁽³⁾

1= Enables the EUSART receive interrupt

0= Disables the EUSART receive interrupt

TXIE: EUSART Transmit Interrupt Enable bit⁽⁵⁾

1= Enables the EUSART transmit interrupt

0= Disables the EUSART transmit interrupt

SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit⁽⁴⁾

1= Enables the SSP interrupt

0= Disables the SSP interrupt

CCP1IE: CCP1 Interrupt Enable bit⁽²⁾

1= Enables the CCP1 interrupt

0= Disables the CCP1 interrupt

TMR2IE: Timer2 to PR2 Match Interrupt Enable bit⁽¹⁾

1= Enables the Timer2 to PR2 match interrupt

0= Disables the Timer2 to PR2 match interrupt

TMR1IE: Timer1 Overflow Interrupt Enable bit

1= Enables the Timer1 overflow interrupt

0= Disables the Timer1 overflow interrupt

Note 1: PIC16F685/PIC16F690 only.

2: PIC16F685/PIC16F689/PIC16F690 only.

3: PIC16F687/PIC16F689/PIC16F690 only.

4: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.

5: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.

DS41262D-page 39

PIC16F631/677/685/687/689/690

2.2.2.5

PIE2 Register

The PIE2 register contains the interrupt enable bits, as

shown in Register 2-5.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

REGISTER 2-5:

PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0

OSFIE

bit 7

R/W-0

C2IE

R/W-0

C1IE

R/W-0

EEIE

U-0

—

U-0

—

U-0

—

U-0

—

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3-0

OSFIE: Oscillator Fail Interrupt Enable bit

1= Enables oscillator fail interrupt

0= Disables oscillator fail interrupt

C2IE: Comparator C2 Interrupt Enable bit

1= Enables Comparator C2 interrupt

0= Disables Comparator C2 interrupt

C1IE: Comparator C1 Interrupt Enable bit

1= Enables Comparator C1 interrupt

0= Disables Comparator C1 interrupt

EEIE: EE Write Operation Interrupt Enable bit

1= Enables write operation interrupt

0= Disables write operation interrupt

Unimplemented: Read as ‘0’

DS41262D-page 40

PIC16F631/677/685/687/689/690

2.2.2.6

PIR1 Register

The PIR1 register contains the interrupt flag bits, as

shown in Register 2-6.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

REGISTER 2-6:

PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

U-0

—

R/W-0

ADIF⁽⁵⁾

R-0

RCIF⁽³⁾

R-0

TXIF⁽³⁾

R/W-0

SSPIF⁽⁴⁾

R/W-0

CCP1IF⁽²⁾

R/W-0

TMR2IF⁽¹⁾

R/W-0

TMR1IF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

ADIF: A/D Converter Interrupt Flag bit⁽⁵⁾

1= A/D conversion complete (must be cleared in software)

0= A/D conversion has not completed or has not been started

bit 5

bit 4

bit 3

bit 2

RCIF: EUSART Receive Interrupt Flag bit⁽³⁾

1= The EUSART receive buffer is full (cleared by reading RCREG)

0= The EUSART receive buffer is not full

TXIF: EUSART Transmit Interrupt Flag bit⁽³⁾

1= The EUSART transmit buffer is empty (cleared by writing to TXREG)

0= The EUSART transmit buffer is full

SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit⁽⁴⁾

1= The Transmission/Reception is complete (must be cleared in software)

0= Waiting to Transmit/Receive

CCP1IF: CCP1 Interrupt Flag bit⁽²⁾

Capture mode:

1= A TMR1 register capture occurred (must be cleared in software)

0= No TMR1 register capture occurred

Compare mode:

1= A TMR1 register compare match occurred (must be cleared in software)

0= No TMR1 register compare match occurred

PWM mode:

Unused in this mode

bit 1

bit 0

TMR2IF: Timer2 to PR2 Interrupt Flag bit⁽¹⁾

1= A Timer2 to PR2 match occurred (must be cleared in software)

0= No Timer2 to PR2 match occurred

TMR1IF: Timer1 Overflow Interrupt Flag bit

1= The TMR1 register overflowed (must be cleared in software)

0= The TMR1 register did not overflow

Note 1: PIC16F685/PIC16F690 only.

2: PIC16F685/PIC16F689/PIC16F690 only.

3: PIC16F687/PIC16F689/PIC16F690 only.

4: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.

5: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.

DS41262D-page 41

PIC16F631/677/685/687/689/690

2.2.2.7

PIR2 Register

The PIR2 register contains the interrupt flag bits, as

shown in Register 2-7.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

REGISTER 2-7:

PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0

OSFIF

bit 7

R/W-0

C2IF

R/W-0

C1IF

R/W-0

EEIF

U-0

—

U-0

—

U-0

—

U-0

—

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3-0

OSFIF: Oscillator Fail Interrupt Flag bit

1= System oscillator failed, clock input has changed to INTOSC (must be cleared in software)

0= System clock operating

C2IF: Comparator C2 Interrupt Flag bit

1= Comparator output (C2OUT bit) has changed (must be cleared in software)

0= Comparator output (C2OUT bit) has not changed

C1IF: Comparator C1 Interrupt Flag bit

1= Comparator output (C1OUT bit) has changed (must be cleared in software)

0= Comparator output (C1OUT bit) has not changed

EEIF: EE Write Operation Interrupt Flag bit

1= Write operation completed (must be cleared in software)

0= Write operation has not completed or has not started

Unimplemented: Read as ‘0’

DS41262D-page 42

PIC16F631/677/685/687/689/690

2.2.2.8

PCON Register

The Power Control (PCON) register (see Register 2-8)

contains flag bits to differentiate between a:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Watchdog Timer Reset (WDT)

• External MCLR Reset

The PCON register also controls the Ultra Low-Power

Wake-up and software enable of the BOR.

REGISTER 2-8:

PCON: POWER CONTROL REGISTER

U-0

—

U-0

—

R/W-0

R/W-1

SBOREN⁽¹⁾

U-0

—

U-0

—

R/W-0

POR

R/W-x

BOR

ULPWUE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5

Unimplemented: Read as ‘0’

ULPWUE: Ultra Low-Power Wake-up Enable bit

1= Ultra Low-Power Wake-up enabled

0= Ultra Low-Power Wake-up disabled

bit 4

SBOREN: Software BOR Enable bit⁽¹⁾

1= BOR enabled

0= BOR disabled

bit 3-2

bit 1

Unimplemented: Read as ‘0’

POR: Power-on Reset Status bit

1= No Power-on Reset occurred

0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0

BOR: Brown-out Reset Status bit

1= No Brown-out Reset occurred

0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Note 1: BOREN<1:0> = 01in the Configuration Word register for this bit to control the BOR.

DS41262D-page 43

PIC16F631/677/685/687/689/690

2.3.2

STACK

2.3

PCL and PCLATH

The PIC16F631/677/685/687/689/690devices have an

8-level x 13-bit wide hardware stack (see Figures 2-2

and 2-3). The stack space is not part of either program

or data space and the Stack Pointer is not readable or

writable. The PC is PUSHed onto the stack when a

CALLinstruction is executed or an interrupt causes a

branch. The stack is POPed in the event of a RETURN,

RETLWor a RETFIEinstruction execution. PCLATH is

not affected by a PUSH or POP operation.

The Program Counter (PC) is 13 bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<12:8>) is not directly

readable or writable and comes from PCLATH. On any

Reset, the PC is cleared. Figure 2-9 shows the two

situations for the loading of the PC. The upper example

in Figure 2-9 shows how the PC is loaded on a write to

PCL (PCLATH<4:0> → PCH). The lower example in

Figure 2-9 shows how the PC is loaded during a CALLor

GOTOinstruction (PCLATH<4:3> → PCH).

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the first

push. The tenth push overwrites the second push (and

so on).

FIGURE 2-9:

LOADING OF PC IN

DIFFERENT SITUATIONS

PCH

PCL

Instruction with

Note 1: There are no Status bits to indicate stack

12

8

7

0

PCL as

overflow or stack underflow conditions.

Destination

PC

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions or the vectoring to an

interrupt address.

8

PCLATH<4:0>

PCLATH

5

ALU Result

PCH

12 11 10

PC

PCL

8

7

0

GOTO, CALL

2.4

Indirect Addressing, INDF and

FSR Registers

PCLATH<4:3>

PCLATH

11

2

OPCODE<10:0>

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF

register. Any instruction using the INDF register actually

accesses data pointed to by the File Select Register

(FSR). Reading INDF itself indirectly will produce 00h.

Writing to the INDF register indirectly results in a no

operation (although Status bits may be affected). An

effective 9-bit address is obtained by concatenating the

8-bit FSR and the IRP bit of the STATUS register, as

shown in Figure 2-10.

2.3.1

MODIFYING PCL

Executing any instruction with the PCL register as the

destination simultaneously causes the Program

Counter PC<12:8> bits (PCH) to be replaced by the

contents of the PCLATH register. This allows the entire

contents of the program counter to be changed by

writing the desired upper 5 bits to the PCLATH register.

When the lower 8 bits are written to the PCL register, all

13 bits of the program counter will change to the values

contained in the PCLATH register and those being

written to the PCL register.

A simple program to clear RAM location 20h-2Fh using

indirect addressing is shown in Example 2-1.

EXAMPLE 2-1:

INDIRECT ADDRESSING

A computed GOTOis accomplished by adding an offset

to the program counter (ADDWF PCL). Care should be

exercised when jumping into a look-up table or

program branch table (computed GOTO) by modifying

the PCL register. Assuming that PCLATH is set to the

table start address, if the table length is greater than

255 instructions or if the lower 8 bits of the memory

address rolls over from 0xFF to 0x00 in the middle of

the table, then PCLATH must be incremented for each

address rollover that occurs between the table

beginning and the target location within the table.

MOVLW

MOVWF

0x20

FSR

;initialize pointer

;to RAM

INCF

BTFSS

GOTO

INDF

FSR

;clear INDF register

;inc pointer

FSR,4

;no clear next

;yes continue

CONTINUE

For more information refer to Application Note AN556,

“Implementing a Table Read” (DS00556).

DS41262D-page 44

PIC16F631/677/685/687/689/690

FIGURE 2-10:

DIRECT/INDIRECT ADDRESSING PIC16F631/677/685/687/689/690

Direct Addressing

Indirect Addressing

From Opcode

7

RP1 RP0

6

0

IRP

File Select Register

Bank Select

180h

Location Select

Bank Select

Location Select

00h

00

01

10

11

Data

Memory

7Fh

1FFh

Bank 0

Bank 1

Bank 2

Bank 3

For memory map detail, see Figures 2-6, 2-7 and 2-8.

DS41262D-page 45

PIC16F631/677/685/687/689/690

NOTES:

DS41262D-page 46

PIC16F631/677/685/687/689/690

The Oscillator module can be configured in one of eight

clock modes.

3.0

3.1

OSCILLATOR MODULE (WITH

FAIL-SAFE CLOCK MONITOR)

1. EC – External clock with I/O on OSC2/CLKOUT.

2. LP – 32 kHz Low-Power Crystal mode.

Overview

3. XT – Medium Gain Crystal or Ceramic Resonator

Oscillator mode.

The Oscillator module has a wide variety of clock

sources and selection features that allow it to be used

in a wide range of applications while maximizing perfor-

mance and minimizing power consumption. Figure 3-1

illustrates a block diagram of the Oscillator module.

4. HS – High Gain Crystal or Ceramic Resonator

mode.

5. RC – External Resistor-Capacitor (RC) with

FOSC/4 output on OSC2/CLKOUT.

Clock sources can be configured from external

oscillators, quartz crystal resonators, ceramic resonators

and Resistor-Capacitor (RC) circuits. In addition, the

system clock source can be configured from one of two

internal oscillators, with a choice of speeds selectable via

software. Additional clock features include:

6. RCIO – External Resistor-Capacitor (RC) with

I/O on OSC2/CLKOUT.

7. INTOSC – Internal oscillator with FOSC/4 output

on OSC2 and I/O on OSC1/CLKIN.

8. INTOSCIO – Internal oscillator with I/O on

OSC1/CLKIN and OSC2/CLKOUT.

• Selectable system clock source between external

or internal via software.

Clock Source modes are configured by the FOSC<2:0>

bits in the Configuration Word register (CONFIG). The

internal clock can be generated from two internal

oscillators. The HFINTOSC is a calibrated high-

frequency oscillator. The LFINTOSC is an uncalibrated

low-frequency oscillator.

• Two-Speed Start-up mode, which minimizes

latency between external oscillator start-up and

code execution.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP,

XT, HS, EC or RC modes) and switch

automatically to the internal oscillator.

FIGURE 3-1:

PIC^®MCU CLOCK SOURCE BLOCK DIAGRAM

FOSC<2:0>

(Configuration Word Register)

External Oscillator

SCS<0>

(OSCCON Register)

OSC2

OSC1

Sleep

LP, XT, HS, RC, RCIO, EC

IRCF<2:0>

(OSCCON Register)

System Clock

(CPU and Peripherals)

8 MHz

111

110

101

INTOSC

Internal Oscillator

4 MHz

2 MHz

1 MHz

HFINTOSC

8 MHz

100

011

010

001

000

500 kHz

250 kHz

125 kHz

31 kHz

LFINTOSC

31 kHz

Power-up Timer (PWRT)

Watchdog Timer (WDT)

Fail-Safe Clock Monitor (FSCM)

DS41262D-page 47

PIC16F631/677/685/687/689/690

3.2

Oscillator Control

The Oscillator Control (OSCCON) register (Figure 3-1)

controls the system clock and frequency selection

options. The OSCCON register contains the following

bits:

• Frequency selection bits (IRCF)

• Frequency Status bits (HTS, LTS)

• System clock control bits (OSTS, SCS)

REGISTER 3-1:

OSCCON: OSCILLATOR CONTROL REGISTER

U-0

—

R/W-1

IRCF2

R/W-1

IRCF1

R/W-0

IRCF0

R-1

OSTS⁽¹⁾

R-0

LTS

R/W-0

SCS

HTS

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IRCF<2:0>: Internal Oscillator Frequency Select bits

111= 8 MHz

110= 4 MHz (default)

101= 2 MHz

100= 1 MHz

011= 500 kHz

010= 250 kHz

001= 125 kHz

000= 31 kHz (LFINTOSC)

bit 3

bit 2

bit 1

bit 0

OSTS: Oscillator Start-up Time-out Status bit⁽¹⁾

1= Device is running from the external clock defined by FOSC<2:0> of the CONFIG register

0= Device is running from the internal oscillator (HFINTOSC or LFINTOSC)

HTS: HFINTOSC Status bit (High Frequency – 8 MHz to 125 kHz)

1= HFINTOSC is stable

0= HFINTOSC is not stable

LTS: LFINTOSC Stable bit (Low Frequency – 31 kHz)

1= LFINTOSC is stable

0= LFINTOSC is not stable

SCS: System Clock Select bit

1= Internal oscillator is used for system clock

0= Clock source defined by FOSC<2:0> of the CONFIG register

Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe

mode is enabled.

DS41262D-page 48

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3.3

Clock Source Modes

3.4

External Clock Modes

Clock Source modes can be classified as external or

internal.

3.4.1 OSCILLATOR START-UP TIMER (OST)

If the Oscillator module is configured for LP, XT or HS

modes, the Oscillator Start-up Timer (OST) counts

1024 oscillations from OSC1. This occurs following a

Power-on Reset (POR) and when the Power-up Timer

(PWRT) has expired (if configured), or a wake-up from

Sleep. During this time, the program counter does not

increment and program execution is suspended. The

OST ensures that the oscillator circuit, using a quartz

crystal resonator or ceramic resonator, has started and

is providing a stable system clock to the Oscillator

module. When switching between clock sources, a

delay is required to allow the new clock to stabilize.

These oscillator delays are shown in Table 3-1.

• External Clock modes rely on external circuitry for

the clock source. Examples are: Oscillator mod-

ules (EC mode), quartz crystal resonators or

ceramic resonators (LP, XT and HS modes) and

Resistor-Capacitor (RC) mode circuits.

• Internal clock sources are contained internally

within the Oscillator module. The Oscillator

module has two internal oscillators: the 8 MHz

High-Frequency Internal Oscillator (HFINTOSC)

and the 31 kHz Low-Frequency Internal Oscillator

(LFINTOSC).

The system clock can be selected between external or

internal clock sources via the System Clock Select

(SCS) bit of the OSCCON register. See Section 3.6

“Clock Switching” for additional information.

In order to minimize latency between external oscillator

start-up and code execution, the Two-Speed Clock

Start-up mode can be selected (see Section 3.7 “Two-

Speed Clock Start-up Mode”).

TABLE 3-1:

Switch From

OSCILLATOR DELAY EXAMPLES

Switch To

Frequency

Oscillator Delay

LFINTOSC

HFINTOSC

31 kHz

125 kHz to 8 MHz

DC – 20 MHz

Sleep/POR

Oscillator Warm-up Delay (TWARM)

Sleep/POR

EC, RC

2 cycles

LFINTOSC (31 kHz)

Sleep/POR

EC, RC

DC – 20 MHz

1 cycle of each

1024 Clock Cycles (OST)

1 μs (approx.)

LP, XT, HS

HFINTOSC

32 kHz to 20 MHz

125 kHz to 8 MHz

LFINTOSC (31 kHz)

3.4.2

EC MODE

FIGURE 3-2:

EXTERNAL CLOCK (EC)

MODE OPERATION

The External Clock (EC) mode allows an externally

generated logic level as the system clock source. When

operating in this mode, an external clock source is

connected to the OSC1 input and the OSC2 is available

for general purpose I/O. Figure 3-2 shows the pin

connections for EC mode.

OSC1/CLKIN

Clock from

Ext. System

PIC^®MCU

(1)

I/O

OSC2/CLKOUT

The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in

operation after a Power-on Reset (POR) or wake-up

from Sleep. Because the PIC^®MCU design is fully

static, stopping the external clock input will have the

effect of halting the device while leaving all data intact.

Upon restarting the external clock, the device will

resume operation as if no time had elapsed.

Note 1: Alternate pin functions are listed in the

Section 1.0 “Device Overview”.

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3.4.3

LP, XT, HS MODES

Note 1: Quartz crystal characteristics vary according

to type, package and manufacturer. The

user should consult the manufacturer data

sheets for specifications and recommended

application.

The LP, XT and HS modes support the use of quartz

crystal resonators or ceramic resonators connected to

OSC1 and OSC2 (Figure 3-3). The mode selects a low,

medium or high gain setting of the internal inverter-

amplifier to support various resonator types and speed.

2: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

LP Oscillator mode selects the lowest gain setting of the

internal inverter-amplifier. LP mode current consumption

is the least of the three modes. This mode is designed to

drive only 32.768 kHz tuning-fork type crystals (watch

crystals).

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC^®and PIC^®

Devices” (DS00826)

• AN849, “Basic PIC^®Oscillator Design”

(DS00849)

• AN943, “Practical PIC^®Oscillator

XT Oscillator mode selects the intermediate gain

setting of the internal inverter-amplifier. XT mode

current consumption is the medium of the three modes.

This mode is best suited to drive resonators with a

medium drive level specification.

HS Oscillator mode selects the highest gain setting of the

internal inverter-amplifier. HS mode current consumption

is the highest of the three modes. This mode is best

suited for resonators that require a high drive setting.

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”

(DS00949)

Figure 3-3 and Figure 3-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

FIGURE 3-4:

CERAMIC RESONATOR

OPERATION

(XT OR HS MODE)

FIGURE 3-3:

QUARTZ CRYSTAL

OPERATION (LP, XT OR

HS MODE)

PIC^®MCU

OSC1/CLKIN

PIC^®MCU

C1

To Internal

Logic

OSC1/CLKIN

(3)

(2)

RP

RF

C1

Sleep

To Internal

Logic

Quartz

Crystal

(2)

RF

Sleep

OSC2/CLKOUT

(1)

C2

RS

Ceramic

Resonator

OSC2/CLKOUT

(1)

C2

RS

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

Note 1: A series resistor (RS) may be required for

2: The value of RF varies with the Oscillator mode

selected (typically between 2 MΩ to 10 MΩ).

quartz crystals with low drive level.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 MΩ to 10 MΩ).

3: An additional parallel feedback resistor (RP)

may be required for proper ceramic resonator

operation.

DS41262D-page 50

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3.4.4

EXTERNAL RC MODES

3.5

Internal Clock Modes

The external Resistor-Capacitor (RC) modes support

the use of an external RC circuit. This allows the

designer maximum flexibility in frequency choice while

keeping costs to a minimum when clock accuracy is not

required. There are two modes: RC and RCIO.

The Oscillator module has two independent, internal

oscillators that can be configured or selected as the

system clock source.

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates at

8 MHz. The frequency of the HFINTOSC can be

user-adjusted via software using the OSCTUNE

register (Register 3-2).

In RC mode, the RC circuit connects to OSC1. OSC2/

CLKOUT outputs the RC oscillator frequency divided

by 4. This signal may be used to provide a clock for

external circuitry, synchronization, calibration, test or

other application requirements. Figure 3-5 shows the

external RC mode connections.

2. The LFINTOSC (Low-Frequency Internal

Oscillator) is uncalibrated and operates at

31 kHz.

The system clock speed can be selected via software

using the Internal Oscillator Frequency Select bits

IRCF<2:0> of the OSCCON register.

FIGURE 3-5:

EXTERNAL RC MODES

VDD

PIC^®MCU

The system clock can be selected between external or

internal clock sources via the System Clock Selection

(SCS) bit of the OSCCON register. See Section 3.6

“Clock Switching” for more information.

REXT

OSC1/CLKIN

Internal

Clock

CEXT

VSS

3.5.1 INTOSC AND INTOSCIO MODES

The INTOSC and INTOSCIO modes configure the

internal oscillators as the system clock source when

the device is programmed using the oscillator selection

or the FOSC<2:0> bits in the Configuration Word

register (CONFIG).

(1)

FOSC/4 or

I/O

OSC2/CLKOUT

(2)

Recommended values: 10 kΩ ≤ REXT ≤ 100 kΩ, <3V

3 kΩ ≤ REXT ≤ 100 kΩ, 3-5V

In INTOSC mode, OSC1/CLKIN is available for general

purpose I/O. OSC2/CLKOUT outputs the selected

internal oscillator frequency divided by 4. The CLKOUT

signal may be used to provide a clock for external

circuitry, synchronization, calibration, test or other

application requirements.

CEXT > 20 pF, 2-5V

Note 1: Alternate pin functions are listed in the

Section 1.0 “Device Overview”.

2: Output depends upon RC or RCIO Clock

mode.

In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT

are available for general purpose I/O.

In RCIO mode, the RC circuit is connected to OSC1.

OSC2 becomes an additional general purpose I/O pin.

3.5.2

HFINTOSC

The RC oscillator frequency is a function of the supply

voltage, the resistor (REXT) and capacitor (CEXT) values

and the operating temperature. Other factors affecting

the oscillator frequency are:

The High-Frequency Internal Oscillator (HFINTOSC) is

a factory calibrated 8 MHz internal clock source. The

frequency of the HFINTOSC can be altered via

software using the OSCTUNE register (Register 3-2).

• threshold voltage variation

• component tolerances

• packaging variations in capacitance

The output of the HFINTOSC connects to a postscaler

and multiplexer (see Figure 3-1). One of seven

frequencies can be selected via software using the

IRCF<2:0> bits of the OSCCON register. See

Section 3.5.4 “Frequency Select Bits (IRCF)” for

more information.

The user also needs to take into account variation due

to tolerance of external RC components used.

The HFINTOSC is enabled by selecting any frequency

between 8 MHz and 125 kHz by setting the IRCF<2:0>

bits of the OSCCON register ≠ 000. Then, set the

System Clock Source (SCS) bit of the OSCCON

register to ‘1’ or enable Two-Speed Start-up by setting

the IESO bit in the Configuration Word register

(CONFIG) to ‘1’.

The HF Internal Oscillator (HTS) bit of the OSCCON

register indicates whether the HFINTOSC is stable or not.

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When the OSCTUNE register is modified, the

HFINTOSC frequency will begin shifting to the new

frequency. Code execution continues during this shift.

There is no indication that the shift has occurred.

3.5.2.1

OSCTUNE Register

The HFINTOSC is factory calibrated but can be

adjusted in software by writing to the OSCTUNE

register (Register 3-2).

OSCTUNE does not affect the LFINTOSC frequency.

Operation of features that depend on the LFINTOSC

clock source frequency, such as the Power-up Timer

(PWRT), Watchdog Timer (WDT), Fail-Safe Clock

Monitor (FSCM) and peripherals, are not affected by the

change in frequency.

The default value of the OSCTUNE register is ‘0’. The

value is a 5-bit two’s complement number.

REGISTER 3-2:

OSCTUNE: OSCILLATOR TUNING REGISTER

U-0

—

U-0

—

U-0

—

R/W-0

TUN4

R/W-0

TUN3

R/W-0

TUN2

R/W-0

TUN1

R/W-0

TUN0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

TUN<4:0>: Frequency Tuning bits

01111= Maximum frequency

01110=

•

00001=

00000= Oscillator module is running at the calibrated frequency.

11111=

•

10000= Minimum frequency

DS41262D-page 52

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3.5.3

LFINTOSC

3.5.5

HFINTOSC AND LFINTOSC CLOCK

SWITCH TIMING

The Low-Frequency Internal Oscillator (LFINTOSC) is

an uncalibrated 31 kHz internal clock source.

When switching between the LFINTOSC and the

HFINTOSC, the new oscillator may already be shut

down to save power (see Figure 3-6). If this is the case,

there is a delay after the IRCF<2:0> bits of the

OSCCON register are modified before the frequency

selection takes place. The LTS and HTS bits of the

OSCCON register will reflect the current active status

of the LFINTOSC and HFINTOSC oscillators. The

timing of a frequency selection is as follows:

The output of the LFINTOSC connects to a postscaler

and multiplexer (see Figure 3-1). Select 31 kHz, via

software, using the IRCF<2:0> bits of the OSCCON

register. See Section 3.5.4 “Frequency Select Bits

(IRCF)” for more information. The LFINTOSC is also the

frequency for the Power-up Timer (PWRT), Watchdog

Timer (WDT) and Fail-Safe Clock Monitor (FSCM).

The LFINTOSC is enabled by selecting 31 kHz

(IRCF<2:0> bits of the OSCCON register = 000)as the

system clock source (SCS bit of the OSCCON

register = 1), or when any of the following are enabled:

1. IRCF<2:0> bits of the OSCCON register are

modified.

2. If the new clock is shut down, a clock start-up

delay is started.

• Two-Speed Start-up IESO bit of the Configuration

Word register = 1and IRCF<2:0> bits of the

OSCCON register = 000

3. Clock switch circuitry waits for a falling edge of

the current clock.

4. CLKOUT is held low and the clock switch

circuitry waits for a rising edge in the new clock.

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

5. CLKOUT is now connected with the new clock.

LTS and HTS bits of the OSCCON register are

updated as required.

• Fail-Safe Clock Monitor (FSCM)

The LF Internal Oscillator (LTS) bit of the OSCCON

register indicates whether the LFINTOSC is stable or

not.

6. Clock switch is complete.

See Figure 3-1 for more details.

3.5.4

FREQUENCY SELECT BITS (IRCF)

If the internal oscillator speed selected is between

8 MHz and 125 kHz, there is no start-up delay before

the new frequency is selected. This is because the old

and new frequencies are derived from the HFINTOSC

via the postscaler and multiplexer.

The output of the 8 MHz HFINTOSC and 31 kHz

LFINTOSC connects to a postscaler and multiplexer

(see Figure 3-1). The Internal Oscillator Frequency

Select bits IRCF<2:0> of the OSCCON register select

the frequency output of the internal oscillators. One of

eight frequencies can be selected via software:

Start-up delay specifications are located in the

oscillator tables of Section 17.0 “Electrical

Specifications”.

• 8 MHz

• 4 MHz (Default after Reset)

• 2 MHz

• 1 MHz

• 500 kHz

• 250 kHz

• 125 kHz

• 31 kHz (LFINTOSC)

Note:

Following any Reset, the IRCF<2:0> bits of

the OSCCON register are set to ‘110’ and

the frequency selection is set to 4 MHz.

The user can modify the IRCF bits to

select a different frequency.

DS41262D-page 53

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FIGURE 3-6:

INTERNAL OSCILLATOR SWITCH TIMING

HFINTOSC

LFINTOSC (FSCM and WDT disabled)

HFINTOSC

Start-up Time

2-cycle Sync

Running

LFINTOSC

≠ 0

= 0

IRCF <2:0>

System Clock

HFINTOSC

LFINTOSC (Either FSCM or WDT enabled)

HFINTOSC

2-cycle Sync

Running

LFINTOSC

IRCF <2:0>

≠ 0

= 0

System Clock

LFINTOSC

HFINTOSC

LFINTOSC turns off unless WDT or FSCM is enabled

Running

LFINTOSC

Start-up Time 2-cycle Sync

HFINTOSC

= 0

¼ 0

IRCF <2:0>

System Clock

DS41262D-page 54

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When the Oscillator module is configured for LP, XT or

HS modes, the Oscillator Start-up Timer (OST) is

3.6

Clock Switching

The system clock source can be switched between

external and internal clock sources via software using

the System Clock Select (SCS) bit of the OSCCON

register.

enabled (see Section 3.4.1 “Oscillator Start-up Timer

(OST)”). The OST will suspend program execution until

1024 oscillations are counted. Two-Speed Start-up

mode minimizes the delay in code execution by

operating from the internal oscillator as the OST is

counting. When the OST count reaches 1024 and the

OSTS bit of the OSCCON register is set, program

execution switches to the external oscillator.

3.6.1

SYSTEM CLOCK SELECT (SCS) BIT

The System Clock Select (SCS) bit of the OSCCON

register selects the system clock source that is used for

the CPU and peripherals.

3.7.1

TWO-SPEED START-UP MODE

CONFIGURATION

• When the SCS bit of the OSCCON register = 0,

the system clock source is determined by

configuration of the FOSC<2:0> bits in the

Configuration Word register (CONFIG).

Two-Speed Start-up mode is configured by the

following settings:

• When the SCS bit of the OSCCON register = 1,

the system clock source is chosen by the internal

oscillator frequency selected by the IRCF<2:0>

bits of the OSCCON register. After a Reset, the

SCS bit of the OSCCON register is always

cleared.

• IESO (of the Configuration Word register) = 1;

Internal/External Switchover bit (Two-Speed Start-

up mode enabled).

• SCS (of the OSCCON register) = 0.

• FOSC<2:0> bits in the Configuration Word

register (CONFIG) configured for LP, XT or HS

mode.

Note:

Any automatic clock switch, which may

occur from Two-Speed Start-up or Fail-Safe

Clock Monitor, does not update the SCS bit

of the OSCCON register. The user can

monitor the OSTS bit of the OSCCON

register to determine the current system

clock source.

Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, after

Power-up Timer (PWRT) has expired, or

• Wake-up from Sleep.

If the external clock oscillator is configured to be

anything other than LP, XT or HS mode, then Two-

speed Start-up is disabled. This is because the external

clock oscillator does not require any stabilization time

after POR or an exit from Sleep.

3.6.2

OSCILLATOR START-UP TIME-OUT

STATUS (OSTS) BIT

The Oscillator Start-up Time-out Status (OSTS) bit of

the OSCCON register indicates whether the system

clock is running from the external clock source, as

defined by the FOSC<2:0> bits in the Configuration

Word register (CONFIG), or from the internal clock

source. In particular, OSTS indicates that the Oscillator

Start-up Timer (OST) has timed out for LP, XT or HS

modes.

3.7.2

TWO-SPEED START-UP

SEQUENCE

1. Wake-up from Power-on Reset or Sleep.

2. Instructions begin execution by the internal

oscillator at the frequency set in the IRCF<2:0>

bits of the OSCCON register.

3. OST enabled to count 1024 clock cycles.

3.7

Two-Speed Clock Start-up Mode

4. OST timed out, wait for falling edge of the

internal oscillator.

Two-Speed Start-up mode provides additional power

savings by minimizing the latency between external

oscillator start-up and code execution. In applications

that make heavy use of the Sleep mode, Two-Speed

Start-up will remove the external oscillator start-up

time from the time spent awake and can reduce the

overall power consumption of the device.

5. OSTS is set.

6. System clock held low until the next falling edge

of new clock (LP, XT or HS mode).

7. System clock is switched to external clock

source.

This mode allows the application to wake-up from

Sleep, perform a few instructions using the INTOSC

as the clock source and go back to Sleep without

waiting for the primary oscillator to become stable.

Note:

Executing a SLEEP instruction will abort

the oscillator start-up time and will cause

the OSTS bit of the OSCCON register to

remain clear.

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3.7.3

CHECKING TWO-SPEED CLOCK

STATUS

Checking the state of the OSTS bit of the OSCCON

register will confirm if the microcontroller is running

from the external clock source, as defined by the

FOSC<2:0> bits in the Configuration Word register

(CONFIG), or the internal oscillator.

FIGURE 3-7:

TWO-SPEED START-UP

HFINTOSC

TOST

OSC1

0

1

1022 1023

OSC2

PC - N

PC + 1

Program Counter

PC

System Clock

DS41262D-page 56

PIC16F631/677/685/687/689/690

3.8.3

FAIL-SAFE CONDITION CLEARING

3.8

Fail-Safe Clock Monitor

The Fail-Safe condition is cleared after a Reset,

executing a SLEEPinstruction or toggling the SCS bit

of the OSCCON register. When the SCS bit is toggled,

the OST is restarted. While the OST is running, the

device continues to operate from the INTOSC selected

in OSCCON. When the OST times out, the Fail-Safe

condition is cleared and the device will be operating

from the external clock source. The Fail-Safe condition

must be cleared before the OSFIF flag can be cleared.

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue operating should the external oscillator fail.

The FSCM can detect oscillator failure any time after

the Oscillator Start-up Timer (OST) has expired. The

FSCM is enabled by setting the FCMEN bit in the

Configuration Word register (CONFIG). The FSCM is

applicable to all external Oscillator modes (LP, XT, HS,

EC, RC and RCIO).

FIGURE 3-8:

FSCM BLOCK DIAGRAM

3.8.4

RESET OR WAKE-UP FROM SLEEP

Clock Monitor

Latch

The FSCM is designed to detect an oscillator failure

after the Oscillator Start-up Timer (OST) has expired.

The OST is used after waking up from Sleep and after

any type of Reset. The OST is not used with the EC or

RC Clock modes so that the FSCM will be active as

soon as the Reset or wake-up has completed. When

the FSCM is enabled, the Two-Speed Start-up is also

enabled. Therefore, the device will always be executing

code while the OST is operating.

External

Clock

S

Q

LFINTOSC

Oscillator

÷ 64

R

Q

31 kHz

(~32 μs)

488 Hz

(~2 ms)

Note:

Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active

during oscillator start-up (i.e., after exiting

Reset or Sleep). After an appropriate

amount of time, the user should check the

OSTS bit of the OSCCON register to verify

the oscillator start-up and that the system

Sample Clock

Clock

Failure

Detected

3.8.1

FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by

comparing the external oscillator to the FSCM sample

clock. The sample clock is generated by dividing the

LFINTOSC by 64. See Figure 3-8. Inside the fail

detector block is a latch. The external clock sets the

latch on each falling edge of the external clock. The

sample clock clears the latch on each rising edge of the

sample clock. A failure is detected when an entire half-

cycle of the sample clock elapses before the primary

clock goes low.

clock

completed.

switchover

has

successfully

3.8.2

FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the

device clock to an internal clock source and sets the bit

flag OSFIF of the PIR2 register. Setting this flag will

generate an interrupt if the OSFIE bit of the PIE2

register is also set. The device firmware can then take

steps to mitigate the problems that may arise from a

failed clock. The system clock will continue to be

sourced from the internal clock source until the device

firmware successfully restarts the external oscillator

and switches back to external operation.

The internal clock source chosen by the FSCM is

determined by the IRCF<2:0> bits of the OSCCON

register. This allows the internal oscillator to be

configured before a failure occurs.

DS41262D-page 57

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FIGURE 3-9:

FSCM TIMING DIAGRAM

Sample Clock

Oscillator

Failure

System

Clock

Output

Clock Monitor Output

(Q)

Failure

Detected

OSCFIF

Test

Note:

The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

TABLE 3-2:

SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Value on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

POR, BOR

(1)

Resets

(2)

CONFIG

CPD

—

CP

IRCF2

—

MCLRE PWRTE

WDTE

OSTS

TUN3

SSPIE

SSPIF

FOSC2

HTS

FOSC1

LTS

FOSC0

SCS

—

OSCCON

OSCTUNE

PIE1

IRCF1

—

IRCF0

TUN4

TXIE

-110 x000 -110 x000

---0 0000 ---u uuuu

—

TUN2

TUN1

TUN0

—

ADIE

ADIF

RCIE

RCIF

CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

PIR1

—

TXIF

Legend:

x= unknown, u= unchanged, – =unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.

Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

2: See Configuration Word register (Register 14-1) for operation of all register bits.

DS41262D-page 58

PIC16F631/677/685/687/689/690

port pins are read, this value is modified and then

written to the PORT data latch. RA3 reads ‘0’ when

4.0

I/O PORTS

There are as many as eighteen general purpose I/O

pins available. Depending on which peripherals are

enabled, some or all of the pins may not be available as

general purpose I/O. In general, when a peripheral is

enabled, the associated pin may not be used as a

general purpose I/O pin.

MCLRE = 1.

The TRISA register controls the PORTA pin output

drivers, even when they are being used as analog

inputs. The user should ensure the bits in the TRISA

register are maintained set when using them as analog

inputs. I/O pins configured as analog input always read

‘0’.

4.1

PORTA and the TRISA Registers

Note:

The ANSEL register must be initialized to

configure an analog channel as a digital

input. Pins configured as analog inputs will

read ‘0’.

PORTA is

a 6-bit wide, bidirectional port. The

corresponding data direction register is TRISA

(Register 4-2). Setting a TRISA bit (= 1) will make the

corresponding PORTA pin an input (i.e., disable the

output driver). Clearing a TRISA bit (= 0) will make the

corresponding PORTA pin an output (i.e., enables

output driver and puts the contents of the output latch

on the selected pin). The exception is RA3, which is

input only and its TRIS bit will always read as ‘1’.

Example 4-1 shows how to initialize PORTA.

EXAMPLE 4-1:

INITIALIZING PORTA

BCF

STATUS,RP0 ;Bank 0

STATUS,RP1

;

CLRF PORTA

;Init PORTA

BSF

STATUS,RP1 ;Bank 2

CLRF ANSEL

;digital I/O

BSF

BCF

STATUS,RP0 ;Bank 1

STATUS,RP1

Reading the PORTA register (Register 4-1) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

;

MOVLW 0Ch

MOVWF TRISA

;Set RA<3:2> as inputs

;and set RA<5:4,1:0>

;as outputs

BCF

STATUS,RP0 ;Bank 0

REGISTER 4-1:

PORTA: PORTA REGISTER

U-0

—

U-0

—

R/W-x

RA5

R/W-x

RA4

R-x

R/W-x

RA2

R/W-x

RA1

R/W-x

RA3

RA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

RA<5:0>: PORTA I/O Pin bit

1= Port pin is > VIH

0= Port pin is < VIL

REGISTER 4-2:

TRISA: PORTA TRI-STATE REGISTER

U-0

—

U-0

—

R/W-1

R-1

R/W-1

TRISA5

TRISA4

TRISA3

TRISA2

TRISA1

TRISA0

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

TRISA<5:0>: PORTA Tri-State Control bit

1= PORTA pin configured as an input (tri-stated)

0= PORTA pin configured as an output

Note 1: TRISA<3> always reads ‘1’.

2: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.

DS41262D-page 59

PIC16F631/677/685/687/689/690

4.2.3

INTERRUPT-ON-CHANGE

4.2

Additional Pin Functions

Each PORTA pin is individually configurable as an

interrupt-on-change pin. Control bits IOCAx enable or

disable the interrupt function for each pin. Refer to

Register 4-6. The interrupt-on-change is disabled on a

Power-on Reset.

Every PORTA pin on this device family has an

interrupt-on-change option and a weak pull-up option.

RA0 also has an Ultra Low-Power Wake-up option. The

next three sections describe these functions.

4.2.1

ANSEL AND ANSELH REGISTERS

For enabled interrupt-on-change pins, the values are

compared with the old value latched on the last read of

PORTA. The ‘mismatch’ outputs of the last read are

OR’d together to set the PORTA Change Interrupt Flag

bit (RABIF) in the INTCON register (Register 2-6).

The ANSEL and ANSELH registers are used to disable

the input buffers of I/O pins, which allow analog voltages

to be applied to those pins without causing excessive

current. Setting the ANSx bit of a corresponding pin will

cause all digital reads of that pin to return ‘0’ and also

permit analog functions of that pin to operate correctly.

This interrupt can wake the device from Sleep. The

user, in the Interrupt Service Routine, clears the

interrupt by:

The state of the ANSx bit has no effect on the digital

output function of its corresponding pin. A pin with the

TRISx bit clear and ANSx bit set will operate as a digital

output, together with the analog input function of that

pin. Pins with the ANSx bit set always read ‘0’, which

can cause unexpected behavior when executing read

or write operations on the port due to the

read-modify-write sequence of all such operations.

a) Any read or write of PORTA. This will end the

mismatch condition, then,

b) Clear the flag bit RABIF.

A mismatch condition will continue to set flag bit RABIF.

Reading PORTA will end the mismatch condition and

allow flag bit RABIF to be cleared. The latch holding the

last read value is not affected by a MCLR nor BOR

Reset. After these Resets, the RABIF flag will continue

to be set if a mismatch is present.

4.2.2

WEAK PULL-UPS

Each of the PORTA pins, except RA3, has an

individually configurable internal weak pull-up. Control

bits WPUAx enable or disable each pull-up. Refer to

Register 4-4. Each weak pull-up is automatically turned

off when the port pin is configured as an output. The

pull-ups are disabled on a Power-on Reset by the

RABPU bit of the OPTION register. A weak pull-up is

automatically enabled for RA3 when configured as

MCLR and disabled when RA3 is an I/O. There is no

software control of the MCLR pull-up.

Note:

If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RABIF

interrupt flag may not get set.

DS41262D-page 60

PIC16F631/677/685/687/689/690

REGISTER 4-3:

ANSEL: ANALOG SELECT REGISTER

R/W-1

ANS7

R/W-1

ANS6

R/W-1

ANS5

R/W-1

ANS4

R/W-1

ANS3

R/W-1

ANS2

R/W-1

ANS1

R/W-1

ANS0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

ANS<7:0>: Analog Select bits

Analog select between analog or digital function on pins AN<7:0>, respectively.

1= Analog input. Pin is assigned as analog input⁽¹⁾

0= Digital I/O. Pin is assigned to port or special function.

.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and

interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow

external control of the voltage on the pin.

REGISTER 4-4:

ANSELH: ANALOG SELECT HIGH REGISTER⁽²⁾

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

ANS11

R/W-1

ANS9

R/W-1

ANS8

ANS10

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

ANS<11:8>: Analog Select bits

Analog select between analog or digital function on pins AN<7:0>, respectively.

1= Analog input. Pin is assigned as analog input⁽¹⁾

0= Digital I/O. Pin is assigned to port or special function.

.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and

interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow

external control of the voltage on the pin.

2: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.

DS41262D-page 61

PIC16F631/677/685/687/689/690

REGISTER 4-5:

WPUA: PORTA REGISTER

U-0

—

U-0

—

R/W-1

U-0

—

R/W-1

WPUA5

WPUA4

WPUA2

WPUA1

WPUA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

WPUA<5:4>: Weak Pull-up Register bit

1= Pull-up enabled

0= Pull-up disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

WPUA<2:0>: Weak Pull-up Register bit

1= Pull-up enabled

0= Pull-up disabled

Note 1: Global RABPU bit of the OPTION register must be enabled for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0).

3: The RA3 pull-up is enabled when configured as MCLR and disabled as an I/O in the Configuration Word.

4: WPUA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.

REGISTER 4-6:

IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER

U-0

—

U-0

—

R/W-0

IOCA5

R/W-0

IOCA4

R/W-0

IOCA3

R/W-0

IOCA2

R/W-0

IOCA1

R/W-0

IOCA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

IOCA<5:0>: Interrupt-on-change PORTA Control bit

1= Interrupt-on-change enabled

0= Interrupt-on-change disabled

Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.

2: IOCA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.

DS41262D-page 62

PIC16F631/677/685/687/689/690

A series resistor between RA0 and the external

capacitor provides overcurrent protection for the

RA0/AN0/C1IN+/ICSPDAT/ULPWU pin and can allow

for software calibration of the time-out (see Figure 4-1).

A timer can be used to measure the charge time and

discharge time of the capacitor. The charge time can

then be adjusted to provide the desired interrupt delay.

This technique will compensate for the affects of

temperature, voltage and component accuracy. The

Ultra Low-Power Wake-up peripheral can also be

configured as a simple Programmable Low-Voltage

Detect or temperature sensor.

4.2.4

ULTRA LOW-POWER WAKE-UP

The Ultra Low-Power Wake-up (ULPWU) on RA0 allows

a slow falling voltage to generate an interrupt-on-change

on RA0 without excess current consumption. The mode

is selected by setting the ULPWUE bit of the PCON

register. This enables a small current sink, which can be

used to discharge a capacitor on RA0.

Follow these steps to use this feature:

a) Charge the capacitor on RA0 by configuring the

RA0 pin to output (= 1).

b) Configure RA0 as an input.

c) Enable interrupt-on-change for RA0.

Note:

For more information, refer to Application

Note AN879, “Using the Microchip Ultra

Low-Power Wake-up Module” (DS00879).

d) Set the ULPWUE bit of the PCON register to

begin the capacitor discharge.

e) Execute a SLEEPinstruction.

EXAMPLE 4-2:

ULTRA LOW-POWER

WAKE-UP INITIALIZATION

When the voltage on RA0 drops below VIL, an interrupt

will be generated which will cause the device to

wake-up and execute the next instruction. If the GIE bit

of the INTCON register is set, the device will then call

the interrupt vector (0004h). See Section 4.4.2 “Inter-

BCF

STATUS,RP0

;Bank 0

;

;Set RA0 data latch

;Bank 2

;RA0 to digital I/O

;Bank 1

BCF

BSF

STATUS,RP1

PORTA,0

BSF

BCF

STATUS,RP1

ANSEL,0

rupt-on-change”

and

Section 14.3.3

“PORTA/PORTB Interrupt” for more information.

BSF

BCF

STATUS,RP0

STATUS,RP1

TRISA,0

This feature provides a low-power technique for

periodically waking up the device from Sleep. The

time-out is dependent on the discharge time of the RC

circuit on RA0. See Example 4-2 for initializing the

Ultra Low-Power Wake-up module.

;

;Output high to

;charge capacitor

CALL

BSF

CapDelay

PCON,ULPWUE

IOCA,0

;Enable ULP Wake-up

;Select RA0 IOC

;RA0 to input

;Enable interrupt

;and clear flag

;Bank 0

BSF

TRISA,0

MOVLW

MOVWF

BCF

B’10001000’

INTCON

STATUS,RP0

SLEEP

;Wait for IOC

DS41262D-page 63

PIC16F631/677/685/687/689/690

4.2.5

PIN DESCRIPTIONS AND

DIAGRAMS

4.2.5.1

RA0/AN0/C1IN+/ICSPDAT/ULPWU

Figure 4-2 shows the diagram for this pin. The

RA0/AN0/C1IN+/ICSPDAT/ULPWU pin is configurable

to function as one of the following:

Each PORTA pin is multiplexed with other functions. The

pins and their combined functions are briefly described

here. For specific information about individual functions

such as the comparator or the A/D Converter (ADC),

refer to the appropriate section in this data sheet.

• a general purpose I/O

• an analog input for the ADC (except PIC16F631)

• an analog input to Comparator C1

• In-Circuit Serial Programming™ data

• an analog input for the Ultra Low-Power Wake-up

FIGURE 4-1:

BLOCK DIAGRAM OF RA0

Analog⁽¹⁾

Input Mode

VDD

Data Bus

D

Q

Weak

CK

WR

WPUDA

RABPU

RD

VDD

WPUDA

D

Q

I/O Pin

WR

CK

PORTA

VSS

-

+

VT

D

Q

WR

TRISA

CK

IULP

0

1

RD

TRISA

Analog⁽¹⁾

Input Mode

VSS

ULPWUE

RD

PORTA

D

Q

D

CK

WR

IOCA

Q3

EN

RD

IOCA

Q

EN

Interrupt-on-Change

RD PORTA

To Comparator

To A/D Converter⁽²⁾

Note 1: ANSEL determines Analog Input mode.

2: Not implemented on PIC16F631.

DS41262D-page 64

PIC16F631/677/685/687/689/690

4.2.5.2

RA1/AN1/C12IN0-/VREF/ICSPCLK

4.2.5.3

RA2/AN2/T0CKI/INT/C1OUT

Figure 4-2 shows the diagram for this pin. The

RA1/AN1/C12IN0-/VREF/ICSPCLK pin is configurable to

function as one of the following:

Figure 4-3 shows the diagram for this pin. The

RA2/AN2/T0CKI/INT/C1OUT pin is configurable to

function as one of the following:

• a general purpose I/O

• an analog input for the ADC (except PIC16F631)

• an analog input to Comparator C1 or C2

• a voltage reference input for the ADC

• In-Circuit Serial Programming clock

• an analog input for the ADC (except PIC16F631)

• the clock input for TMR0

• an external edge triggered interrupt

• a digital output from Comparator C1

FIGURE 4-2:

BLOCK DIAGRAM OF RA1

FIGURE 4-3:

BLOCK DIAGRAM OF RA2

Analog⁽¹⁾

Input Mode

Analog⁽¹⁾

Input Mode

Data Bus

D

Data Bus

D

Q

VDD

Q

VDD

WR

CK

WR

CK

Weak

WPUA

RABPU

RD

WPUA

RABPU

RD

WPUA

C1OUT

Enable

VDD

D

Q

D

Q

WR

PORTA

WR

PORTA

CK

C1OUT

1

0

I/O Pin

D

Q

D

Q

WR

TRISA

WR

TRISA

CK

VSS

Analog⁽¹⁾

Input Mode

RD

TRISA

RD

TRISA

RD

PORTA

RD

PORTA

D

Q

D

Q

D

Q

D

CK

WR

CK

WR

IOCA

EN

Q3

EN

RD

IOCA

RD

IOCA

D

EN

Interrupt-on-

Change

Interrupt-on-

Change

RD PORTA

To Comparator

To A/D Converter⁽²⁾

To TMR0

To INT

To A/D Converter⁽²⁾

Note 1: ANSEL determines Analog Input mode.

2: Not implemented on PIC16F631.

Note 1: ANSEL determines Analog Input mode.

2: Not implemented on PIC16F631.

DS41262D-page 65

PIC16F631/677/685/687/689/690

4.2.5.4

RA3/MCLR/VPP

4.2.5.5

RA4/AN3/T1G/OSC2/CLKOUT

Figure 4-4 shows the diagram for this pin. The

RA3/MCLR/VPP pin is configurable to function as one

of the following:

Figure 4-5 shows the diagram for this pin. The

RA4/AN3/T1G/OSC2/CLKOUT pin is configurable to

function as one of the following:

• a general purpose input

• a general purpose I/O

• as Master Clear Reset with weak pull-up

• an analog input for the ADC (except PIC16F631)

• a TMR1 gate input

FIGURE 4-4:

BLOCK DIAGRAM OF RA3

• a crystal/resonator connection

• a clock output

VDD

MCLRE

Weak

FIGURE 4-5:

BLOCK DIAGRAM OF RA4

Data Bus

Analog⁽³⁾

Input Mode

MCLRE

Reset

Input

CLK⁽¹⁾

Modes

VDD

Data Bus

D

RD

TRISA

VSS

Q

MCLRE

VSS

WR

CK

RD

PORTA

Weak

WPUA

D

Q

RABPU

RD

WPUA

Q

D

CK

WR

IOCA

Oscillator

Circuit

Q3

OSC1

EN

VDD

CLKOUT

Enable

RD

IOCA

D

FOSC/4

1

0

D

Q

EN

Interrupt-on-

Change

I/O Pin

WR

CK

PORTA

CLKOUT

Enable

RD PORTA

VSS

D

Q

INTOSC/

RC/EC⁽²⁾

WR

TRISA

CK

CLKOUT

Enable

RD

TRISA

Analog

Input Mode

RD

PORTA

D

Q

D

CK

WR

IOCA

Q3

EN

RD

IOCA

Q

EN

Interrupt-on-

Change

RD PORTA

To T1G

To A/D Converter⁽⁴⁾

Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT

Enable.

2: With CLKOUT option.

3: ANSEL determines Analog Input mode.

4: Not implemented on PIC16F631.

DS41262D-page 66

PIC16F631/677/685/687/689/690

4.2.5.6

RA5/T1CKI/OSC1/CLKIN

Figure 4-6 shows the diagram for this pin. The

RA5/T1CKI/OSC1/CLKIN pin is configurable to

function as one of the following:

• a general purpose I/O

• a TMR1 clock input

• a crystal/resonator connection

• a clock input

FIGURE 4-6:

BLOCK DIAGRAM OF RA5

INTOSC

Mode

TMR1LPEN⁽¹⁾

VDD

Data Bus

D

Q

WR

CK

Weak

WPUA

RABPU

RD

WPUA

Oscillator

Circuit

OSC2

VDD

D

Q

WR

PORTA

CK

I/O Pin

D

Q

WR

TRISA

CK

VSS

INTOSC

Mode

RD

TRISA

(2)

RD

PORTA

D

Q

D

CK

WR

IOCA

Q3

EN

RD

IOCA

D

EN

Interrupt-on-

Change

RD PORTA

To TMR1 or CLKGEN

Note 1: Timer1 LP Oscillator enabled.

2: When using Timer1 with LP oscillator, the

Schmitt Trigger is bypassed.

DS41262D-page 67

PIC16F631/677/685/687/689/690

TABLE 4-1:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADCON0

ADFM

VCFG

CHS3

CHS2

CHS1

CHS0

ADON

0000 0000

GO/DONE

ANS1

ANSEL

ANS7

C1ON

GIE

ANS6

C1OUT

PEIE

ANS5

C1OE

T0IE

ANS4

C1POL

INTE

ANS3

—

ANS2

C1R

ANS0

C1CH0

RABIF

IOCA0

PS0

1111 1111

0000 -000

0000 000x

--00 0000

1111 1111

--xx xxxx

0000 0000

--11 1111

--11 -111

1111 1111

0000 -000

0000 000x

--00 0000

1111 1111

--uu uuuu

0000 0000

uuuu uuuu

--11 1111

--11 -111

CM1CON0

INTCON

IOCA

C1CH1

INTF

RABIE

IOCA3

PSA

T0IF

—

IOCA5

T0CS

RA5

IOCA4

T0SE

RA4

IOCA2

PS2

IOCA1

PS1

OPTION_REG RABPU

INTEDG

—

PORTA

SSPCON

T1CON

TRISA

—

WCOL

T1GINV

—

RA3

RA2

RA1

RA0

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR1CS TMR1ON

—

TRISA5

WPUA5

TRISA4

WPUA4

TRISA3

—

TRISA2

WPUA2

TRISA1

WPUA1

TRISA0

WPUA0

WPUA

—

Legend:

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

DS41262D-page 68

PIC16F631/677/685/687/689/690

4.4.1

WEAK PULL-UPS

4.3

PORTB and TRISB Registers

Each of the PORTB pins has an individually configurable

internal weak pull-up. Control bits WPUB<7:4> enable or

disable each pull-up (see Register 4-9). Each weak

pull up is automatically turned off when the port pin is

configured as an output. All pull-ups are disabled on a

Power-on Reset by the RABPU bit of the OPTION

register.

PORTB is

a 4-bit wide, bidirectional port. The

corresponding data direction register is TRISB (Register

4-6). Setting a TRISB bit (= 1) will make the

corresponding PORTB pin an input (i.e., put the

corresponding output driver in a High-Impedance mode).

Clearing a TRISB bit (= 0) will make the corresponding

PORTB pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

Example 4-3 shows how to initialize PORTB. Reading

the PORTB register (Register 4-5) reads the status of the

pins, whereas writing to it will write to the PORT latch. All

write operations are read-modify-write operations.

Therefore, a write to a port implies that the port pins are

read, this value is modified and then written to the PORT

data latch.

4.4.2

INTERRUPT-ON-CHANGE

Four of the PORTB pins are individually configurable as

an interrupt-on-change pin. Control bits IOCB<7:4>

enable or disable the interrupt function for each pin.

Refer to Register 4-10. The interrupt-on-change feature

is disabled on a Power-on Reset.

For enabled interrupt-on-change pins, the present

value is compared with the old value latched on the last

read of PORTB to determine which bits have changed

or mismatch the old value. The ‘mismatch’ outputs are

OR’d together to set the PORTB Change Interrupt flag

bit (RABIF) in the INTCON register (Register 2-3).

The TRISB register controls the PORTB pin output

drivers, even when they are being used as analog inputs.

The user should ensure the bits in the TRISB register are

maintained set when using them as analog inputs. I/O

pins configured as analog input always read ‘0’.

This interrupt can wake the device from Sleep. The user,

in the Interrupt Service Routine, clears the interrupt by:

EXAMPLE 4-3:

INITIALIZING PORTB

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear the flag bit RABIF.

BCF

CLRF

BSF

STATUS,RP0 ;Bank 0

STATUS,RP1

PORTB

;

;Init PORTB

STATUS,RP0 ;Bank 1

A mismatch condition will continue to set flag bit RABIF.

Reading or writing PORTB will end the mismatch

condition and allow flag bit RABIF to be cleared. The latch

holding the last read value is not affected by a MCLR nor

Brown-out Reset. After these Resets, the RABIF flag will

continue to be set if a mismatch is present.

MOVLW

MOVWF

BCF

FFh

TRISB

STATUS,RP0 ;Bank 0

;Set RB<7:4> as inputs

;

Note:

The ANSELH register must be initialized

to configure an analog channel as a digital

input. Pins configured as analog inputs will

read ‘0’.

Note:

If a change on the I/O pin should occur when

the read operation is being executed (start of

the Q2 cycle), then the RABIF interrupt flag

may not get set. Furthermore, since a read

or write on a port affects all bits of that port,

care must be taken when using multiple pins

in Interrupt-on-Change mode. Changes on

one pin may not be seen while servicing

changes on another pin.

4.4

Additional PORTB Pin Functions

PORTB pins RB<7:4> on the device family device have

an interrupt-on-change option and a weak pull-up

option. The following three sections describe these

PORTB pin functions.

REGISTER 4-7:

PORTB: PORTB REGISTER

R/W-x

RB7

R/W-x

RB6

R/W-x

RB5

R/W-x

RB4

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-4

bit 3-0

RB<7:4>: PORTB I/O Pin bit

1= Port pin is > VIH

0= Port pin is < VIL

Unimplemented: Read as ‘0’

DS41262D-page 69

PIC16F631/677/685/687/689/690

REGISTER 4-8:

TRISB: PORTB TRI-STATE REGISTER

R/W-1

TRISB7

bit 7

R/W-1

U-0

—

U-0

—

U-0

—

U-0

—

TRISB6

TRISB5

TRISB4

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-4

TRISB<7:4>: PORTB Tri-State Control bit

1= PORTB pin configured as an input (tri-stated)

0= PORTB pin configured as an output

bit 3-0

Unimplemented: Read as ‘0’

REGISTER 4-9:

WPUB: WEAK PULL-UP PORTB REGISTER

R/W-1

WPUB7

bit 7

R/W-1

U-0

—

U-0

—

U-0

—

U-0

—

WPUB6

WPUB5

WPUB4

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

WPUB<7:4>: Weak Pull-up Register bit

1= Pull-up enabled

0= Pull-up disabled

bit 3-0

Unimplemented: Read as ‘0’

Note 1: Global RABPU bit of the OPTION register must be enabled for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISB<7:4> = 0).

REGISTER 4-10: IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER

R/W-0

IOCB7

R/W-0

IOCB6

R/W-0

IOCB5

R/W-0

IOCB4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

bit 3-0

IOCB<7:4>: Interrupt-on-Change PORTB Control bit

1= Interrupt-on-change enabled

0= Interrupt-on-change disabled

Unimplemented: Read as ‘0’

DS41262D-page 70

PIC16F631/677/685/687/689/690

4.4.3

PIN DESCRIPTIONS AND

DIAGRAMS

4.4.3.1

RB4/AN10/SDI/SDA

Figure 4-7 shows the diagram for this pin. The

RB4/AN10/SDI/SDA⁽¹⁾pin is configurable to function

as one of the following:

Each PORTB pin is multiplexed with other functions. The

pins and their combined functions are briefly described

here. For specific information about individual functions

such as the SSP, I²C™ or interrupts, refer to the

appropriate section in this data sheet.

• a general purpose I/O

• an analog input for the ADC (except PIC16F631)

• a SPI data I/O

• an I²C data I/O

Note 1: SDI and SDA are available on

PIC16F687/PIC16F689/PIC16F690 only.

FIGURE 4-7:

BLOCK DIAGRAM OF RB4

Analog⁽¹⁾

Input Mode

Data Bus

D

Q

VDD

WR

CK

Weak

WPUB

RABPU

RD

WPUB

SSPEN

SSPSR

VDD

D

Q

10

WR

PORTB

CK

01

I/O Pin

D

Q

From

SSP

10

WR

TRISB

CK

VSS

0

Analog⁽¹⁾

Input Mode

RD

TRISB

RD

PORTB

D

Q

D

CK

WR

IOCB

EN

Q3

RD

IOCB

D

ST

EN

Interrupt-on-

Change

RD PORTB

To SSPSR

To A/D Converter⁽²⁾

Available on PIC16F677/PIC16F687/PIC16F689/PIC16F690

only.

Note 1:

2:

ANSEL determines Analog Input mode.

Not implemented on PIC16F631.

DS41262D-page 71

PIC16F631/677/685/687/689/690

4.4.3.2

RB5/AN11/RX/DT

FIGURE 4-8:

BLOCK DIAGRAM OF RB5

Figure 4-8 shows the diagram for this pin. The

RB5/AN11/RX/DT^(1,2)pin is configurable to function as

one of the following:

Analog⁽¹⁾

Input Mode

Data Bus

D

Q

VDD

WR

CK

• a general purpose I/O

Weak

WPUB

• an analog input for the ADC (except PIC16F631)

• an asynchronous serial input

RABPU

RD

WPUB

• a synchronous serial data I/O

SYNC

SPEN

Note 1: RX and DT are available on

VDD

PIC16F687/PIC16F689/PIC16F690 only.

D

Q

EUSART

DT

2: AN11 is not implemented on PIC16F631.

10

WR

PORTB

CK

01

I/O Pin

From

D

Q

EUSART 10

WR

TRISB

CK

VSS

0

Analog⁽¹⁾

Input Mode

RD

TRISB

RD

PORTB

D

Q

D

CK

WR

IOCB

EN

Q3

RD

IOCB

Q

ST

EN

Interrupt-on-

Change

RD PORTB

To EUSART RX/DT

To A/D Converter⁽²⁾

Available on PIC16F687/PIC16F689/PIC16F690 only.

Note 1:

2:

ANSEL determines Analog Input mode.

Not implemented on PIC16F631.

DS41262D-page 72

PIC16F631/677/685/687/689/690

4.4.3.3

RB6/SCK/SCL

FIGURE 4-9:

BLOCK DIAGRAM OF RB6

Figure 4-9 shows the diagram for this pin. The

RB6/SCK/SCL⁽¹⁾pin is configurable to function as one

of the following:

Data Bus

D

Q

VDD

WR

WPUB

CK

Weak

• a general purpose I/O

• a SPI clock

• an I²C™ clock

RABPU

RD

WPUB

Note 1: SCK and SCL are available on

PIC16F677/PIC16F687/PIC16F689/

PIC16F690 only.

SSPEN

VDD

D

Q

SSP

Clock

10

WR

PORTB

CK

01

I/O Pin

From

SSP

D

Q

10

WR

TRISB

CK

VSS

01

RD

TRISB

RD

PORTB

D

Q

D

CK

WR

IOCB

EN

Q3

RD

IOCB

D

ST

EN

Interrupt-on-

Change

RD PORTB

To SSPSR

Available on PIC16F677/PIC16F687/PIC16F689/PIC16F690

only.

DS41262D-page 73

PIC16F631/677/685/687/689/690

4.4.3.4

RB7/TX/CK

FIGURE 4-10:

BLOCK DIAGRAM OF RB7

Figure 4-10 shows the diagram for this pin. The

RB7/TX/CK⁽¹⁾pin is configurable to function as one of

the following:

Data Bus

D

Q

VDD

WR

WPUB

CK

Weak

Q

• a general purpose I/O

• an asynchronous serial output

• a synchronous clock I/O

RABPU

RD

WPUB

SPEN

TXEN

Note 1: TX and CK are available on

PIC16F687/PIC16F689/PIC16F690 only.

SYNC

EUSART

CK

10

EUSART

TX

D

Q

0

VDD

WR

PORTB

CK

10

01

I/O Pin

D

Q

WR

‘1’

01

CK

TRISB

VSS

01

RD

TRISB

RD

PORTB

D

Q

D

CK

WR

IOCB

EN

Q3

RD

IOCB

Q

D

EN

Interrupt-on-

Change

RD PORTB

Available on PIC16F687/PIC16F689/PIC16F690 only.

DS41262D-page 74

PIC16F631/677/685/687/689/690

TABLE 4-2:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

IOCB

IOCB7 IOCB6 IOCB5 IOCB4

—

RABIE

—

T0IF

—

INTF

—

0000 ---- 0000 ----

INTCON

PORTB

TRISB

WPUB

GIE

PEIE

RB6

T0IE

RB5

INTE

RB4

RABIF 0000 000x 0000 000x

RB7

—

xxxx ---- uuuu ----

1111 ---- 1111 ----

TRISB7 TRISB6 TRISB5 TRISB4

WPUB7 WPUB6 WPUB5 WPUB4

—

Legend: x= unknown, u= unchanged, —= unimplemented read as ‘0’. Shaded cells are not used by PORTB.

DS41262D-page 75

PIC16F631/677/685/687/689/690

The TRISC register controls the PORTC pin output

drivers, even when they are being used as analog inputs.

The user should ensure the bits in the TRISC register are

maintained set when using them as analog inputs. I/O

pins configured as analog input always read ‘0’.

4.5

PORTC and TRISC Registers

PORTC is

a 8-bit wide, bidirectional port. The

corresponding data direction register is TRISC (Register

4-10). Setting a TRISC bit (= 1) will make the

corresponding PORTC pin an input (i.e., put the

corresponding output driver in a High-Impedance mode).

Clearing a TRISC bit (= 0) will make the corresponding

PORTC pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

Example 4-4 shows how to initialize PORTC. Reading

the PORTC register (Register 4-9) reads the status of the

pins, whereas writing to it will write to the PORT latch. All

write operations are read-modify-write operations.

Therefore, a write to a port implies that the port pins are

read, this value is modified and then written to the PORT

data latch.

Note:

The ANSEL and ANSELH registers must

be initialized to configure an analog

channel as a digital input. Pins configured

as analog inputs will read ‘0’.

EXAMPLE 4-4:

INITIALIZING PORTC

BCF

STATUS,RP0

;Bank 0

BCF

CLRF

BSF

CLRF

BSF

BCF

STATUS,RP1

PORTC

STATUS,RP1

ANSEL

STATUS,RP0

STATUS,RP1

0Ch

;

;Init PORTC

;Bank 2

;digital I/O

;Bank 1

;

MOVLW

MOVWF

;Set RC<3:2> as inputs

;and set RC<5:4,1:0>

;as outputs

;Bank 0

TRISC

BCF

STATUS,RP0

REGISTER 4-11: PORTC: PORTC REGISTER

R/W-0

RC7

R/W-x

RC6

R/W-x

RC5

R/W-x

RC4

R/W-x

RC3

R/W-x

RC2

R/W-x

RC1

R/W-x

RC0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-0

RC<7:0>: PORTC General Purpose I/O Pin bit

1= Port pin is > VIH

0= Port pin is < VIL

REGISTER 4-12: TRISC: PORTC TRI-STATE REGISTER

R/W-1

TRISC5

R/W-1

R-1

R/W-1

TRISC7

TRISC6

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

TRISC<7:0>: PORTC Tri-State Control bit

1= PORTC pin configured as an input (tri-stated)

0= PORTC pin configured as an output

DS41262D-page 76

PIC16F631/677/685/687/689/690

4.5.1

RC0/AN4/C2IN+

4.5.3

RC2/AN6/C12IN2-/P1D

The RC0 is configurable to function as one of the

following:

The RC2/AN6/P1D⁽¹⁾is configurable to function as

one of the following:

• a general purpose I/O

• an analog input for the ADC (except PIC16F631)

• an analog input to Comparator C2

• an analog input for the ADC (except PIC16F631)

• a PWM output

• an analog input to Comparator C1 or C2

4.5.2

RC1/AN5/C12IN1-

Note 1: P1D is available on

The RC1 is configurable to function as one of the

following:

PIC16F685/PIC16F690 only.

• a general purpose I/O

4.5.4

RC3/AN7/C12IN3-/P1C

• an analog input for the ADC

• an analog input to Comparator C1 or C2

The RC3/AN7/P1C⁽¹⁾is configurable to function as one

of the following:

• a general purpose I/O

FIGURE 4-11:

BLOCK DIAGRAM OF RC0

AND RC1

• an analog input for the ADC (except PIC16F631)

• a PWM output

Data Bus

• a PWM output

• an analog input to Comparator C1 or C2

VDD

D

Q

Note 1: P1C is available on

WR

PORTC

CK

Q

PIC16F685/PIC16F690 only.

I/O Pin

FIGURE 4-12:

BLOCK DIAGRAM OF RC2

AND RC3

D

Q

WR

CK

TRISC

VSS

Analog Input

Data Bus

CCP1OUT

Enable

VDD

Mode⁽¹⁾

RD

TRISC

D

Q

WR

PORTC

CK

RD

PORTC

Q

10

CCP1OUT

To Comparators

01

I/O Pin

To A/D Converter⁽²⁾

D

Q

WR

TRISC

CK

VSS

Note 1:

2:

ANSEL determines Analog Input mode.

Not implemented on PIC16F631.

Analog Input

Mode⁽¹⁾

RD

TRISC

RD

PORTC

To Comparators

To A/D Converter⁽²⁾

Available on PIC16F685/PIC16F690 only.

Note 1:

2:

ANSEL determines Analog Input mode.

Not implemented on PIC16F631.

DS41262D-page 77

PIC16F631/677/685/687/689/690

4.5.5

RC4/C2OUT/P1B

4.5.6

RC5/CCP1/P1A

The RC4/C2OUT/P1B^{(1, 2)}is configurable to function

as one of the following:

The RC5/CCP1/P1A⁽¹⁾is configurable to function as

one of the following:

• a general purpose I/O

• a digital output from Comparator C2

• a PWM output

• a general purpose I/O

• a digital input/output for the Enhanced CCP

• a PWM output

Note 1: Enabling both C2OUT and P1B will cause

a conflict on RC4 and create unpredictable

results. Therefore, if C2OUT is enabled,

the ECCP+ can not be used in Half-Bridge

or Full-Bridge mode and vise-versa.

Note 1: CCP1 and P1A are available on

PIC16F685/PIC16F690 only.

FIGURE 4-14:

BLOCK DIAGRAM OF RC5

Data bus

2: P1B is available on

CCP1OUT

Enable

VDD

PIC16F685/PIC16F690 only.

D

Q

FIGURE 4-13:

BLOCK DIAGRAM OF RC4

WR

PORTC

CK

10

Q

CCP1OUT

C2OUT EN

CCP1OUT EN

01

I/O Pin

D

Q

C2OUT EN

C2OUT

WR

TRISC

CK

VDD

VSS

CCP1OUT EN

CCP1OUT

10

RD

TRISC

01

I/O Pin

Data Bus

RD

PORTC

D

Q

WR

PORTC

CK

To Enhanced CCP

VSS

Q

D

Q

Available on PIC16F685/PIC16F690 only.

WR

TRISC

CK

RD

TRISC

RD

PORTC

Available on PIC16F685/PIC16F690 only.

DS41262D-page 78

PIC16F631/677/685/687/689/690

4.5.7

RC6/AN8/SS

4.5.8

RC7/AN9/SDO

The RC6/AN8/SS^(1,2)is configurable to function as one

of the following:

The RC7/AN9/SDO^(1,2)is configurable to function as

one of the following:

• a general purpose I/O

• an analog input for the ADC (except PIC16F631)

• a slave select input

• an analog input for the ADC (except PIC16F631)

• a serial data output

Note 1: SS is available on

Note 1: SDO is available on PIC16F687/

PIC16F687/PIC16F689/PIC16F690 only.

PIC16F689/PIC16F690 only.

2: AN8 is not implemented on PIC16F631.

2: AN9 is not implemented on PIC16F631.

FIGURE 4-15:

BLOCK DIAGRAM OF RC6

FIGURE 4-16:

BLOCK DIAGRAM OF RC7

Data Bus

PORT/SDO

Select

VDD

Data Bus

D

Q

10

SDO

WR

PORTC

CK

Q

VDD

D

Q

01

WR

PORTC

CK

I/O Pin

Q

D

Q

WR

TRISC

CK

I/O Pin

VSS

Analog Input

D

Q

Mode⁽¹⁾

WR

TRISC

CK

RD

TRISC

VSS

Analog Input

Mode⁽¹⁾

RD

TRISC

RD

PORTC

To SS Input

To A/D Converter⁽²⁾

RD

PORTC

To A/D Converter⁽²⁾

Available on PIC16F685/PIC16F690 only.

Note 1:

2:

ANSEL determines Analog Input mode.

Not implemented on PIC16F631.

Available on PIC16F685/PIC16F690 only.

Note 1:

2:

ANSEL determines Analog Input mode.

Not implemented on PIC16F631.

DS41262D-page 79

PIC16F631/677/685/687/689/690

TABLE 4-3:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSEL

ANS7

—

ANS6

—

ANS5

—

ANS4

—

ANS3

ANS2

ANS1

ANS9

ANS0

ANS8

1111 1111

---- 1111

0000 0000

0000 -000

1111 1111

---- 1111

0000 0000

0000 -000

00-- --10

uuuu uuuu

---0 0001

0000 00--

0000 0000

1111 1111

0000 0000

ANSELH

ANS11

ANS10

CCP1CON⁽²⁾

CM2CON0

P1M1

C2ON

P1M0

C2OUT

DC1B1

C2OE

DC1B0

C2POL

CCP1M3 CCP1M2 CCP1M1 CCP1M0

—

C2R

C2CH1

C2CH0

CM2CON1

PORTC

MC1OUT MC2OUT

—

RC4

—

T1GSS

RC1

C2SYNC

RC0

00-- --10

xxxx xxxx

---0 0001

0000 00--

0000 0000

1111 1111

0000 0000

RC7

—

RC6

—

RC5

RC3

RC2

PSTRCON

SRCON

—

STRSYNC

C2REN

CKP

STRD

PULSS

SSPM3

TRISC3

VR3

STRC

PULSR

SSPM2

TRISC2

VR2

STRB

—

STRA

—

SR1

SR0

C1SEN

SSPEN

TRISC5

VRR

SSPCON⁽¹⁾

WCOL

TRISC7

SSPOV

TRISC6

SSPM1

TRISC1

VR1

SSPM0

TRISC0

VR0

TRISC

TRISC4

VP6EN

VRCON

C1VREN C2VREN

Legend:

Note 1:

2:

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

PIC16F687/PIC16F689/PIC16F690 only.

PIC16F685/PIC16F690 only.

DS41262D-page 80

PIC16F631/677/685/687/689/690

5.1

Timer0 Operation

5.0

TIMER0 MODULE

When used as a timer, the Timer0 module can be used

as either an 8-bit timer or an 8-bit counter.

The Timer0 module is an 8-bit timer/counter with the

following features:

• 8-bit timer/counter register (TMR0)

5.1.1

8-BIT TIMER MODE

• 8-bit prescaler (shared with Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow

When used as a timer, the Timer0 module will

increment every instruction cycle (without prescaler).

Timer mode is selected by clearing the T0CS bit of the

OPTION register to ‘0’.

Figure 5-1 is a block diagram of the Timer0 module.

When TMR0 is written, the increment is inhibited for

two instruction cycles immediately following the write.

Note:

The value written to the TMR0 register can

be adjusted, in order to account for the two

instruction cycle delay when TMR0 is

written.

5.1.2

8-BIT COUNTER MODE

When used as a counter, the Timer0 module will

increment on every rising or falling edge of the T0CKI

pin. The incrementing edge is determined by the T0SE

bit of the OPTION register. Counter mode is selected by

setting the T0CS bit of the OPTION register to ‘1’.

FIGURE 5-1:

BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

FOSC/4

Data Bus

0

1

8

1

Sync 2

TMR0

cycles

T0CKI

0

1

Set Flag bit T0IF

on Overflow

T0CS

T0SE

8-bit

Prescaler

PSA

8

PSA

WDTE

SWDTEN

1

PS<2:0>

WDT

Time-out

16-bit

Prescaler

0

16

31 kHz

INTOSC

Watchdog

Timer

PSA

WDTPS<3:0>

Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.

2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register.

3: WDTE bit is in the Configuration Word register.

DS41262D-page 81

PIC16F631/677/685/687/689/690

When changing the prescaler assignment from the

WDT to the Timer0 module, the following instruction

sequence must be executed (see Example 5-2).

5.1.3

SOFTWARE PROGRAMMABLE

PRESCALER

A single software programmable prescaler is available

for use with either Timer0 or the Watchdog Timer

(WDT), but not both simultaneously. The prescaler

assignment is controlled by the PSA bit of the OPTION

register. To assign the prescaler to Timer0, the PSA bit

must be cleared to a ‘0’.

EXAMPLE 5-2:

CHANGING PRESCALER

(WDT → TIMER0)

CLRWDT

;Clear WDT and

;prescaler

;

BANKSEL OPTION_REG

There are 8 prescaler options for the Timer0 module

ranging from 1:2 to 1:256. The prescale values are

selectable via the PS<2:0> bits of the OPTION register.

In order to have a 1:1 prescaler value for the Timer0

module, the prescaler must be assigned to the WDT

module.

MOVLW

ANDWF

IORLW

MOVWF

b’11110000’ ;Mask TMR0 select and

OPTION_REG,W ; prescaler bits

b’00000011’ ;Set prescale to 1:16

OPTION_REG

;

5.1.4

TIMER0 INTERRUPT

The prescaler is not readable or writable. When the

prescaler is assigned to the Timer0 module, all

instructions writing to the TMR0 register will clear the

prescaler.

Timer0 will generate an interrupt when the TMR0

register overflows from FFh to 00h. The T0IF interrupt

flag bit of the INTCON register is set every time the

TMR0 register overflows, regardless of whether or not

the Timer0 interrupt is enabled. The T0IF bit must be

cleared in software. The Timer0 interrupt enable is the

T0IE bit of the INTCON register.

When the prescaler is assigned to WDT, a CLRWDT

instruction will clear the prescaler along with the WDT.

5.1.3.1

Switching Prescaler Between

Timer0 and WDT Modules

Note:

The Timer0 interrupt cannot wake the

processor from Sleep since the timer is

frozen during Sleep.

As a result of having the prescaler assigned to either

Timer0 or the WDT, it is possible to generate an

unintended device Reset when switching prescaler

values. When changing the prescaler assignment from

Timer0 to the WDT module, the instruction sequence

shown in Example 5-1, must be executed.

5.1.5

USING TIMER0 WITH AN

EXTERNAL CLOCK

When Timer0 is in Counter mode, the synchronization

of the T0CKI input and the Timer0 register is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks. Therefore, the

high and low periods of the external clock source must

meet the timing requirements as shown in

Section 17.0 “Electrical Specifications”.

EXAMPLE 5-1:

CHANGING PRESCALER

(TIMER0 → WDT)

BANKSEL TMR0

CLRWDT

CLRF

;

;Clear WDT

TMR0

;Clear TMR0 and

;

prescaler

BANKSEL OPTION_REG

BSF

OPTION_REG,PSA ;Select WDT

CLRWDT

;

MOVLW

ANDWF

IORLW

MOVWF

b’11111000’

OPTION_REG,W

b’00000101’

OPTION_REG

;Mask prescaler

bits

;Set WDT prescaler

to 1:32

;

DS41262D-page 82

PIC16F631/677/685/687/689/690

REGISTER 5-1:

OPTION_REG: OPTION REGISTER

R/W-1 R/W-1 R/W-1 R/W-1

INTEDG T0CS T0SE PSA

R/W-1

RABPU

bit 7

R/W-1

PS2

R/W-1

PS1

R/W-1

PS0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

RABPU: PORTA/PORTB Pull-up Enable bit

1= PORTA/PORTB pull-ups are disabled

0= PORTA/PORTB pull-ups are enabled by individual PORT latch values

INTEDG: Interrupt Edge Select bit

1= Interrupt on rising edge of INT pin

0= Interrupt on falling edge of INT pin

T0CS: TMR0 Clock Source Select bit

1= Transition on T0CKI pin

0= Internal instruction cycle clock (FOSC/4)

T0SE: TMR0 Source Edge Select bit

1= Increment on high-to-low transition on T0CKI pin

0= Increment on low-to-high transition on T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler is assigned to the WDT

0= Prescaler is assigned to the Timer0 module

PS<2:0>: Prescaler Rate Select bits

BIT VALUE TMR0 RATE

WDT RATE

000

001

010

011

100

101

110

111

1 : 2

1 : 1

1 : 4

1 : 2

1 : 8

1 : 4

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Note 1: A dedicated 16-bit WDT postscaler is available. See Section 14.5 “Watchdog Timer (WDT)” for more

information.

TABLE 5-1:

SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE

PEIE

T0IE

INTE RABIE

T0SE PSA

T0IF

PS2

INTF RABIF 0000 0000 0000 0000

OPTION_REG RABPU INTEDG T0CS

PS1

PS0 1111 1111 1111 1111

TMR0

TRISA

Timer0 Module Register

xxxx xxxx uuuu uuuu

—

TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

Legend: – = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the

Timer0 module.

DS41262D-page 83

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6.1

Timer1 Operation

6.0

TIMER1 MODULE WITH GATE

CONTROL

The Timer1 module is a 16-bit incrementing counter

which is accessed through the TMR1H:TMR1L register

pair. Writes to TMR1H or TMR1L directly update the

counter.

The Timer1 module is a 16-bit timer/counter with the

following features:

• 16-bit timer/counter register pair (TMR1H:TMR1L)

• Programmable internal or external clock source

• 3-bit prescaler

When used with an internal clock source, the module is

a timer. When used with an external clock source, the

module can be used as either a timer or counter.

• Optional LP oscillator

• Synchronous or asynchronous operation

6.2

Clock Source Selection

• Timer1 gate (count enable) via comparator or

T1G pin

The TMR1CS bit of the T1CON register is used to select

the clock source. When TMR1CS = 0, the clock source

is FOSC/4. When TMR1CS = 1, the clock source is

supplied externally.

• Interrupt on overflow

• Wake-up on overflow (external clock,

Asynchronous mode only)

• Time base for the Capture/Compare function

(PIC16F685/PIC16F690 only)

Clock

Source

FOSC

Mode

T1OSCEN

TMR1CS

• Special Event Trigger (with ECCP)

(PIC16F685/PIC16F690 only)

FOSC/4

x

0

1

xxx

0

1

• Comparator output synchronization to Timer1

clock

T1CKI pin

T1LPOSC

LP or

INTOSCIO

Figure 6-1 is a block diagram of the Timer1 module.

FIGURE 6-1:

TIMER1 BLOCK DIAGRAM

TMR1GE

T1GINV

TMR1ON

Set flag bit

To C2 Comparator module

Timer1 Clock

TMR1IF on

Overflow

(1)

TMR1

TMR1H

Synchronized

clock input

0

EN

*

TMR1L

1

Oscillator

T1SYNC

OSC1/T1CKI

1

Synchronize

det ⁽²⁾

Prescaler

1, 2, 4, 8

FOSC/4

Internal

Clock

0

OSC2/T1G

2

T1CKPS<1:0>

TMR1CS

1

0

T1OSCEN

SYNCC2OUT

FOSC = 100

FOSC = 000

T1GSS

Sleep

*

ST Buffer is low power type when using LP osc, or high speed type when using T1CKI.

Note 1: Timer1 register increments on rising edge.

2: Synchronize does not operate while in Sleep.

DS41262D-page 84

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TRISA5 and TRISA4 bits are set when the Timer1

oscillator is enabled. RA5 and RA4 bits read as ‘0’ and

TRISA5 and TRISA4 bits read as ‘1’.

6.2.1

INTERNAL CLOCK SOURCE

When the internal clock source is selected the

TMR1H:TMR1L register pair will increment on multiples

of FOSC as determined by the Timer1 prescaler.

Note:

The oscillator requires a start-up and

stabilization time before use. Thus,

T1OSCEN should be set and a suitable

delay observed prior to enabling Timer1.

6.2.2

EXTERNAL CLOCK SOURCE

When the external clock source is selected, the Timer1

module may work as a timer or a counter.

6.5

Timer1 Operation in

Asynchronous Counter Mode

When counting, Timer1 is incremented on the rising

edge of the external clock input T1CKI. In addition, the

Counter mode clock can be synchronized to the

microcontroller system clock or run asynchronously.

If control bit T1SYNC of the T1CON register is set, the

external clock input is not synchronized. The timer

increments asynchronously to the internal phase

clocks. If external clock source is selected then the

timer will continue to run during Sleep and can

generate an interrupt on overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer (see

Section 6.5.1 “Reading and Writing Timer1 in

Asynchronous Counter Mode”).

If an external clock oscillator is needed (and the

microcontroller is using the INTOSC without CLKOUT),

Timer1 can use the LP oscillator as a clock source.

Note:

In Counter mode, a falling edge must be

registered by the counter prior to the first

incrementing rising edge after any one or

more of the following conditions:

• Timer1 enabled after POR reset

• Write to TMR1H or TMR1L

• Timer1 is disabled

Note:

When switching from synchronous to

asynchronous operation, it is possible to

skip an increment. When switching from

asynchronous to synchronous operation,

it is possible to produce an additional

increment.

• Timer1 is disabled (TMR1ON 0) when

T1CKI is high then Timer1 is enabled

(TMR1ON=1) when T1CKI is low.

Note:

See Figure 6-2

6.5.1

READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

6.3

Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

Reading TMR1H or TMR1L while the timer is running

from an external asynchronous clock will ensure a valid

read (taken care of in hardware). However, the user

should keep in mind that reading the 16-bit timer in two

8-bit values itself, poses certain problems, since the

timer may overflow between the reads.

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may produce an

unpredictable value in the TMR1H:TMR1L register pair.

6.4

Timer1 Oscillator

A low-power 32.768 kHz crystal oscillator is built-in

between pins OSC1 (input) and OSC2 (amplifier

output). The oscillator is enabled by setting the

T1OSCEN control bit of the T1CON register. The

oscillator will continue to run during Sleep.

6.6

Timer1 Gate

The Timer1 oscillator is shared with the system LP

oscillator. Thus, Timer1 can use this mode only when

the primary system clock is derived from the internal

oscillator or when the oscillator is in the LP mode. The

user must provide a software time delay to ensure

proper oscillator start-up.

Timer1 gate source is software configurable to be the

T1G pin or the output of Comparator C2. This allows the

device to directly time external events using T1G or

analog events using Comparator C2. See the

CM2CON1 register (Register 8-3) for selecting the

Timer1 gate source. This feature can simplify the

software for a Delta-Sigma A/D converter and many

other applications. For more information on Delta-Sigma

A/D converters, see the Microchip web site

(www.microchip.com).

DS41262D-page 85

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In Compare mode, an event is triggered when the value

CCPR1H:CCPR1L register pair matches the value in

the TMR1H:TMR1L register pair. This event can be a

Special Event Trigger.

Note:

TMR1GE bit of the T1CON register must

be set to use either T1G or C2OUT as the

Timer1 gate source. See the CM2CON1

register (Register 8-3) for more informa-

tion on selecting the Timer1 gate source.

For more information, see Section 11.0 “Enhanced

Capture/Compare/PWM Module”.

Timer1 gate can be inverted using the T1GINV bit of

the T1CON register, whether it originates from the T1G

pin or Comparator C2 output. This configures Timer1 to

measure either the active-high or active-low time

between events.

6.10 ECCP Special Event Trigger

When the ECCP is configured to trigger a special

event, the trigger will clear the TMR1H:TMR1L register

pair. This special event does not cause a Timer1 inter-

rupt. The ECCP module may still be configured to

generate a ECCP interrupt.

6.7

Timer1 Interrupt

In this mode of operation, the CCPR1H:CCPR1L

register pair becomes the period register for Timer1.

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the Timer1 interrupt flag bit of the PIR1 register is

set. To enable the interrupt on rollover, you must set

these bits:

Timer1 should be synchronized to the FOSC to utilize

the Special Event Trigger. Asynchronous operation of

Timer1 can cause a Special Event Trigger to be

missed.

• TMR1ON bit of the T1CON register

• TMR1IE bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

In the event that a write to TMR1H or TMR1L coincides

with a Special Event Trigger from the ECCP, the write

will take precedence.

For more information, see Section 11.2.4 “Special

Event Trigger”.

The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

Note:

The TMR1H:TTMR1L register pair and the

TMR1IF bit should be cleared before

enabling interrupts.

6.11 Comparator Synchronization

The same clock used to increment Timer1 can also be

used to synchronize the comparator output. This

feature is enabled in the Comparator module.

6.8

Timer1 Operation During Sleep

When using the comparator for Timer1 gate, the

comparator output should be synchronized to Timer1.

This ensures Timer1 does not miss an increment if the

comparator changes.

Timer1 can only operate during Sleep when setup in

Asynchronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the

counter. To set up the timer to wake the device:

For

more

information,

see

Section 8.8.2

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set

• T1SYNC bit of the T1CON register must be set

• TMR1CS bit of the T1CON register must be set

• T1OSCEN bit of the T1CON register (can be set)

“Synchronizing Comparator C2 output to Timer1”.

The device will wake-up on an overflow and execute

the next instructions. If the GIE bit of the INTCON

register is set, the device will call the Interrupt Service

Routine (0004h).

6.9

ECCP Capture/Compare Time Base

The ECCP module uses the TMR1H:TMR1L register

pair as the time base when operating in Capture or

Compare mode.

In Capture mode, the value in the TMR1H:TMR1L

register pair is copied into the CCPR1H:CCPR1L

register pair on a configured event.

DS41262D-page 86

PIC16F631/677/685/687/689/690

FIGURE 6-2:

TIMER1 INCREMENTING EDGE

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

DS41262D-page 87

PIC16F631/677/685/687/689/690

6.12 Timer1 Control Register

The Timer1 Control register (T1CON), shown in

Register 6-1, is used to control Timer1 and select the

various features of the Timer1 module.

REGISTER 6-1:

T1CON: TIMER 1 CONTROL REGISTER

R/W-0

T1GINV⁽¹⁾

R/W-0

TMR1GE⁽²⁾

R/W-0

T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC

TMR1CS

TMR1ON

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

T1GINV: Timer1 Gate Invert bit⁽¹⁾

1= Timer1 gate is active high (Timer1 counts when gate is high)

0= Timer1 gate is active low (Timer1 counts when gate is low)

TMR1GE: Timer1 Gate Enable bit⁽²⁾

If TMR1ON = 0:

This bit is ignored

If TMR1ON = 1:

1= Timer1 is on if Timer1 gate is not active

0= Timer1 is on

bit 5-4

bit 3

T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11= 1:8 Prescale Value

10= 1:4 Prescale Value

01= 1:2 Prescale Value

00= 1:1 Prescale Value

T1OSCEN: LP Oscillator Enable Control bit

If INTOSC without CLKOUT oscillator is active:

1= LP oscillator is enabled for Timer1 clock

0= LP oscillator is off

Else:

This bit is ignored

bit 2

T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1:

1= Do not synchronize external clock input

0= Synchronize external clock input

TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock

bit 1

bit 0

TMR1CS: Timer1 Clock Source Select bit

1= External clock from T1CKI pin (on the rising edge)

0= Internal clock (FOSC/4)

TMR1ON: Timer1 On bit

1= Enables Timer1

0= Stops Timer1

Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.

2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CM2CON1

register, as a Timer1 gate source.

DS41262D-page 88

PIC16F631/677/685/687/689/690

TABLE 6-1:

SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CM2CON1 MC1OUT MC2OUT

—

T1GSS

INTF

C2SYNC

RABIF

---- --10

0000 0000

---- --10

0000 0000

INTCON

PIE1

GIE

—

PEIE

ADIE

ADIF

T0IE

INTE

TXIE

TXIF

RABIE

SSPIE

SSPIF

T0IF

RCIE

RCIF

CCP1IE

CCP1IF

TMR2IE

TMR2IF

TMR1IE -000 0000 -000 0000

TMR1IF -000 0000 -000 0000

PIR1

—

TMR1H

TMR1L

T1CON

Legend:

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

xxxx xxxx

0000 0000

uuuu uuuu

T1GINV

TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR1CS

TMR1ON

x= unknown, u= unchanged, —= unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

DS41262D-page 89

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NOTES:

DS41262D-page 90

PIC16F631/677/685/687/689/690

The TMR2 and PR2 registers are both fully readable

and writable. On any Reset, the TMR2 register is set to

00h and the PR2 register is set to FFh.

7.0

TIMER2 MODULE

The Timer2 module is an eight-bit timer with the

following features:

Timer2 is turned on by setting the TMR2ON bit in the

T2CON register to a ‘1’. Timer2 is turned off by clearing

the TMR2ON bit to a ‘0’.

• 8-bit timer register (TMR2)

• 8-bit period register (PR2)

• Interrupt on TMR2 match with PR2

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

The Timer2 prescaler is controlled by the T2CKPS bits

in the T2CON register. The Timer2 postscaler is

controlled by the TOUTPS bits in the T2CON register.

The prescaler and postscaler counters are cleared

when:

See Figure 7-1 for a block diagram of Timer2.

• A write to TMR2 occurs.

• A write to T2CON occurs.

7.1

Timer2 Operation

The clock input to the Timer2 module is the system

instruction clock (FOSC/4). The clock is fed into the

Timer2 prescaler, which has prescale options of 1:1,

1:4 or 1:16. The output of the prescaler is then used to

increment the TMR2 register.

• Any device Reset occurs (Power-on Reset, MCLR

Reset, Watchdog Timer Reset or Brown-out

Reset).

Note:

TMR2 is not cleared when T2CON is

written.

The values of TMR2 and PR2 are constantly compared

to determine when they match. TMR2 will increment

from 00h until it matches the value in PR2. When a

match occurs, two things happen:

• TMR2 is reset to 00h on the next increment cycle.

• The Timer2 postscaler is incremented

The match output of the Timer2/PR2 comparator is fed

into the Timer2 postscaler. The postscaler has

postscale options of 1:1 to 1:16 inclusive. The output of

the Timer2 postscaler is used to set the TMR2IF

interrupt flag bit in the PIR1 register.

FIGURE 7-1:

TIMER2 BLOCK DIAGRAM

Sets Flag

bit TMR2IF

TMR2

Output

Prescaler

Reset

EQ

TMR2

FOSC/4

1:1, 1:4, 1:16

Postscaler

1:1 to 1:16

2

Comparator

PR2

T2CKPS<1:0>

4

TOUTPS<3:0>

DS41262D-page 91

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REGISTER 7-1:

T2CON: TIMER 2 CONTROL REGISTER⁽¹⁾

U-0

—

R/W-0

TOUTPS3

TOUTPS2

TOUTPS1

TOUTPS0

TMR2ON

T2CKPS1

T2CKPS0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

Unimplemented: Read as ‘0’

bit 6-3

TOUTPS<3:0>: Timer2 Output Postscaler Select bits

0000= 1:1 Postscaler

0001= 1:2 Postscaler

0010= 1:3 Postscaler

0011= 1:4 Postscaler

0100= 1:5 Postscaler

0101= 1:6 Postscaler

0110= 1:7 Postscaler

0111= 1:8 Postscaler

1000= 1:9 Postscaler

1001= 1:10 Postscaler

1010= 1:11 Postscaler

1011= 1:12 Postscaler

1100= 1:13 Postscaler

1101= 1:14 Postscaler

1110= 1:15 Postscaler

1111= 1:16 Postscaler

bit 2

TMR2ON: Timer2 On bit

1= Timer2 is on

0= Timer2 is off

bit 1-0

T2CKPS<1:0>: Timer2 Clock Prescale Select bits

00= Prescaler is 1

01= Prescaler is 4

1x= Prescaler is 16

Note 1: PIC16F685/PIC16F690 only.

TABLE 7-1:

SUMMARY OF ASSOCIATED TIMER2⁽¹⁾REGISTERS

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

—

PEIE

ADIE

ADIF

T0IE

RCIE

RCIF

INTE

TXIE

TXIF

RABIE

SSPIE

SSPIF

T0IF

INTF

RABIF

TMR1IE

TMR1IF

0000 000x

-000 0000

1111 1111

0000 0000

-000 0000

0000 000x

-000 0000

1111 1111

0000 0000

-000 0000

CCP1IE

CCP1IF

TMR2IE

TMR2IF

PIR1

—

PR2

Timer2 Module Period Register

Holding Register for the 8-bit TMR2 Register

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0

TMR2

T2CON

—

TMR2ON

T2CKPS1

T2CKPS0

Legend:

x= unknown, u= unchanged, —= unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.

Note 1:

PIC16F685/PIC16F690 only.

DS41262D-page 92

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FIGURE 8-1:

SINGLE COMPARATOR

8.0

COMPARATOR MODULE

Comparators are used to interface analog circuits to a

digital circuit by comparing two analog voltages and

providing a digital indication of their relative magnitudes.

The comparators are very useful mixed signal building

blocks because they provide analog functionality

independent of program execution. The Analog

Comparator module includes the following features:

VIN+

VIN-

+

Output

–

VIN-

VIN+

• Independent comparator control

• Programmable input selection

• Comparator output is available internally/externally

• Programmable output polarity

• Interrupt-on-change

Output

• Wake-up from Sleep

• PWM shutdown

• Timer1 gate (count enable)

• Output synchronization to Timer1 clock input

• SR Latch

Note:

The black areas of the output of the

comparator represents the uncertainty

due to input offsets and response time.

• Programmable and fixed voltage reference

Note:

Only Comparator C2 can be linked to

Timer1.

8.1

Comparator Overview

A single comparator is shown in Figure 8-1 along with

the relationship between the analog input levels and

the digital output. When the analog voltage at VIN+ is

less than the analog voltage at VIN-, the output of the

comparator is a digital low level. When the analog

voltage at VIN+ is greater than the analog voltage at

VIN-, the output of the comparator is a digital high level.

DS41262D-page 93

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FIGURE 8-2:

COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM

C1CH<1:0>

C1POL

2

To

Data Bus

D

Q

Q1

C12IN0-

EN

0

RD_CM1CON0

Set C1IF

C12IN1-

C12IN2-

C12IN3-

1

MUX

2

D

Q

Q3*RD_CM1CON0

EN

3

CL

NRESET

C1OUT

(1)

To other peripherals

C1OUT (to SR latch)

C1ON

C1

C1R

C1VIN-

C1VIN+

-

C1IN+

0

+

MUX

1

FixedRef

0

C1POL

MUX

CVREF

1

Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.

2: Q1 and Q3 are phases of the four-phase system clock (FOSC).

3: Q1 is held high during Sleep mode.

C1VREN

FIGURE 8-3:

COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM

C2POL

To

D

Q

Data Bus

Q1

EN

RD_CM2CON0

C2CH<1:0>

Set C2IF

2

D

Q

Q3*RD_CM2CON0

EN

(1)

C2ON

C2

C12IN0-

0

CL

NRESET

C2OUT

C12IN1-

C2IN2-

C2IN3-

1

MUX

2

C2VIN-

C2VIN+

C2SYNC

3

C2POL

0

MUX

1

C2R

SYNCC2OUT

to Timer1 Gate, SR latch

and other peripherals

D

Q

C2IN+

0

From TMR1

Clock

MUX

1

FixedRef

0

MUX

1

CVREF

Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.

2: Q1 and Q3 are phases of the four-phase system clock (FOSC).

3: Q1 is held high during Sleep mode.

C2VREN

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8.2.4

COMPARATOR OUTPUT

SELECTION

8.2

Comparator Control

Each comparator has

a

separate control and

The output of the comparator can be monitored by

reading either the CxOUT bit of the CMxCON0 register

or the MCxOUT bit of the CM2CON1 register. In order

to make the output available for an external connection,

the following conditions must be true:

Configuration register: CM1CON0 for Comparator C1

and CM2CON0 for Comparator C2. In addition,

Comparator C2 has

a

second control register,

CM2CON1, for controlling the interaction with Timer1 and

simultaneous reading of both comparator outputs.

• CxOE bit of the CMxCON0 register must be set

• Corresponding TRIS bit must be cleared

The CM1CON0 and CM2CON0 registers (see Registers

8-1 and 8-2, respectively) contain the control and Status

bits for the following:

• CxON bit of the CMxCON0 register must be set

• Enable

Note 1: The CxOE bit overrides the PORT data

latch. Setting the CxON has no impact on

the port override.

• Input selection

• Reference selection

• Output selection

• Output polarity

2: The internal output of the comparator is

latched with each instruction cycle.

Unless otherwise specified, external

outputs are not latched.

8.2.1

COMPARATOR ENABLE

Setting the CxON bit of the CMxCON0 register enables

the comparator for operation. Clearing the CxON bit

disables the comparator resulting in minimum current

consumption.

8.2.5

COMPARATOR OUTPUT POLARITY

Inverting the output of the comparator is functionally

equivalent to swapping the comparator inputs. The

polarity of the comparator output can be inverted by

setting the CxPOL bit of the CMxCON0 register.

Clearing the CxPOL bit results in a non-inverted output.

8.2.2

COMPARATOR INPUT SELECTION

The CxCH<1:0> bits of the CMxCON0 register direct

one of four analog input pins to the comparator

inverting input.

Table 8-1 shows the output state versus input

conditions, including polarity control.

TABLE 8-1:

COMPARATOR OUTPUT

STATE VS. INPUT CONDITIONS

Note:

To use CxIN+ and C12INx- pins as analog

inputs, the appropriate bits must be set in

the ANSEL register and the corresponding

TRIS bits must also be set to disable the

output drivers.

Input Condition

CxPOL

CxOUT

CxVIN- > CxVIN+

CxVIN- < CxVIN+

CxVIN- > CxVIN+

CxVIN- < CxVIN+

0

1

0

1

0

8.2.3

COMPARATOR REFERENCE

SELECTION

Setting the CxR bit of the CMxCON0 register directs an

internal voltage reference or an analog input pin to the

non-inverting input of the comparator. See Section 8.9

“Comparator SR Latch” for more information on the

Internal Voltage Reference module.

8.3

Comparator Response Time

The comparator output is indeterminate for a period of

time after the change of an input source or the selection

of a new reference voltage. This period is referred to as

the response time. The response time of the

comparator differs from the settling time of the voltage

reference. Therefore, both of these times must be

considered when determining the total response time

to a comparator input change. See the Comparator and

Voltage Reference Specifications in Section 17.0

“Electrical Specifications” for more details.

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FIGURE 8-4:

COMPARATOR

8.4

Comparator Interrupt Operation

INTERRUPT TIMING W/O

CMxCON0 READ

The comparator interrupt flag can be set whenever

there is a change in the output value of the comparator.

Changes are recognized by means of a mismatch

circuit which consists of two latches and an exclusive-

or gate (see Figure 8-2 and Figure 8-3). One latch is

updated with the comparator output level when the

CMxCON0 register is read. This latch retains the value

until the next read of the CMxCON0 register or the

occurrence of a Reset. The other latch of the mismatch

circuit is updated on every Q1 system clock. A

mismatch condition will occur when a comparator

output change is clocked through the second latch on

the Q1 clock cycle. At this point the two mismatch

latches have opposite output levels which is detected

by the exclusive-or gate and fed to the interrupt

circuitry. The mismatch condition persists until either

the CMxCON0 register is read or the comparator

output returns to the previous state.

Q1

Q3

CxIN+

TRT

Cxout

Set CxIF (edge)

CxIF

reset by software

FIGURE 8-5:

COMPARATOR

INTERRUPT TIMING WITH

CMxCON0 READ

Q1

Q3

CxIN+

TRT

Note 1: A write operation to the CMxCON0

register will also clear the mismatch

condition because all writes include a read

operation at the beginning of the write

cycle.

Cxout

Set CxIF (edge)

CxIF

cleared by CMxCON0 read

reset by software

2: Comparator interrupts will operate correctly

regardless of the state of CxOE.

The comparator interrupt is set by the mismatch edge

and not the mismatch level. This means that the inter-

rupt flag can be reset without the additional step of

reading or writing the CMxCON0 register to clear the

mismatch registers. When the mismatch registers are

cleared, an interrupt will occur upon the comparator’s

return to the previous state, otherwise no interrupt will

be generated.

Note 1: If a change in the CMxCON0 register

(CxOUT) should occur when a read

operation is being executed (start of the

Q2 cycle), then the CxIF of the PIR1

register interrupt flag may not get set.

2: When either comparator is first enabled,

bias circuitry in the Comparator module

may cause an invalid output from the

comparator until the bias circuitry is

stable. Allow about 1 μs for bias settling

then clear the mismatch condition and

Software will need to maintain information about the

status of the comparator output, as read from the

CMxCON0 register, or CM2CON1 register, to determine

the actual change that has occurred.

interrupt

flags

before

enabling

comparator interrupts.

The CxIF bit of the PIR1 register is the comparator

interrupt flag. This bit must be reset in software by

clearing it to ‘0’. Since it is also possible to write a '1' to

this register, an interrupt can be generated.

The CxIE bit of the PIE1 register and the PEIE and GIE

bits of the INTCON register must all be set to enable

comparator interrupts. If any of these bits are cleared,

the interrupt is not enabled, although the CxIF bit of the

PIR1 register will still be set if an interrupt condition

occurs.

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8.5

Operation During Sleep

The comparator, if enabled before entering Sleep mode,

remains active during Sleep. The additional current

consumed by the comparator is shown separately in the

Section 17.0 “Electrical Specifications”. If the

comparator is not used to wake the device, power

consumption can be minimized while in Sleep mode by

turning off the comparator. Each comparator is turned off

by clearing the CxON bit of the CMxCON0 register.

A change to the comparator output can wake-up the

device from Sleep. To enable the comparator to wake

the device from Sleep, the CxIE bit of the PIE1 register

and the PEIE bit of the INTCON register must be set.

The instruction following the Sleep instruction always

executes following a wake from Sleep. If the GIE bit of

the INTCON register is also set, the device will then

execute the Interrupt Service Routine.

8.6

Effects of a Reset

A device Reset forces the CMxCON0 and CM2CON1

registers to their Reset states. This forces both

comparators and the voltage references to their OFF

states.

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REGISTER 8-1:

CM1CON0: COMPARATOR C1 CONTROL REGISTER 0

R/W-0

C1ON

R-0

R/W-0

C1OE

R/W-0

U-0

—

R/W-0

C1R

R/W-0

C1OUT

C1POL

C1CH1

C1CH0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

C1ON: Comparator C1 Enable bit

1= Comparator C1 is enabled

0= Comparator C1 is disabled

C1OUT: Comparator C1 Output bit

If C1POL = 1(inverted polarity):

C1OUT = 0when C1VIN+ > C1VIN-

C1OUT = 1when C1VIN+ < C1VIN-

If C1POL = 0(non-inverted polarity):

C1OUT = 1when C1VIN+ > C1VIN-

C1OUT = 0when C1VIN+ < C1VIN-

bit 5

bit 4

C1OE: Comparator C1 Output Enable bit

1= C1OUT is present on the C1OUT pin⁽¹⁾

0= C1OUT is internal only

C1POL: Comparator C1 Output Polarity Select bit

1= C1OUT logic is inverted

0= C1OUT logic is not inverted

bit 3

bit 2

Unimplemented: Read as ‘0’

C1R: Comparator C1 Reference Select bit (non-inverting input)

1= C1VIN+ connects to C1VREF output

0= C1VIN+ connects to C1IN+ pin

bit 1-0

C1CH<1:0>: Comparator C1 Channel Select bit

00= C1VIN- of C1 connects to C12IN0- pin

01= C1VIN- of C1 connects to C12IN1- pin

10= C1VIN- of C1 connects to C12IN2- pin

11= C1VIN- of C1 connects to C12IN3- pin

Note 1: Comparator output requires the following three conditions: C1OE = 1, C1ON = 1and corresponding

PORT TRIS bit = 0.

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REGISTER 8-2:

CM2CON0: COMPARATOR C2 CONTROL REGISTER 0

R/W-0

C2ON

R-0

R/W-0

C2OE

R/W-0

U-0

—

R/W-0

C2R

R/W-0

C2OUT

C2POL

C2CH1

C2CH0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

C2ON: Comparator C2 Enable bit

1= Comparator C2 is enabled

0= Comparator C2 is disabled

C2OUT: Comparator C2 Output bit

If C2POL = 1(inverted polarity):

C2OUT = 0when C2VIN+ > C2VIN-

C2OUT = 1when C2VIN+ < C2VIN-

If C2POL = 0(non-inverted polarity):

C2OUT = 1when C2VIN+ > C2VIN-

C2OUT = 0when C2VIN+ < C2VIN-

bit 5

bit 4

C2OE: Comparator C2 Output Enable bit

1= C2OUT is present on C2OUT pin⁽¹⁾

0= C2OUT is internal only

C1POL: Comparator C1 Output Polarity Select bit

1= C1OUT logic is inverted

0= C1OUT logic is not inverted

bit 3

bit 2

Unimplemented: Read as ‘0’

C2R: Comparator C2 Reference Select bits (non-inverting input)

1= C2VIN+ connects to C2VREF

0= C2VIN+ connects to C2IN+ pin

bit 1-0

C2CH<1:0>: Comparator C2 Channel Select bits

00= C2VIN- of C2 connects to C12IN0- pin

01= C2VIN- of C2 connects to C12IN1- pin

10= C2VIN- of C2 connects to C12IN2- pin

11= C2VIN- of C2 connects to C12IN3- pin

Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1and corresponding

PORT TRIS bit = 0.

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8.7

Analog Input Connection

Considerations

Note 1: When reading a PORT register, all pins

configured as analog inputs will read as a

‘0’. Pins configured as digital inputs will

convert as an analog input, according to

the input specification.

A simplified circuit for an analog input is shown in

Figure 8-6. Since the analog input pins share their con-

nection with a digital input, they have reverse biased

ESD protection diodes to VDD and VSS. The analog

input, therefore, must be between VSS and VDD. If the

input voltage deviates from this range by more than

0.6V in either direction, one of the diodes is forward

biased and a latch-up may occur.

2: Analog levels on any pin defined as a

digital input, may cause the input buffer to

consume more current than is specified.

A maximum source impedance of 10 kΩ is recommended

for the analog sources. Also, any external component

connected to an analog input pin, such as a capacitor or

a Zener diode, should have very little leakage current to

minimize inaccuracies introduced.

FIGURE 8-6:

ANALOG INPUT MODEL

VDD

VT ≈ 0.6V

RIC

Rs < 10K

To ADC Input

AIN

ILEAKAGE

±500 nA

CPIN

5 pF

VA

VT ≈ 0.6V

Vss

Legend: CPIN

= Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions

RIC

RS

VA

= Interconnect Resistance

= Source Impedance

= Analog Voltage

VT

= Threshold Voltage

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8.8.2

SYNCHRONIZING COMPARATOR

C2 OUTPUT TO TIMER1

8.8

Additional Comparator Features

There are three additional comparator features:

The Comparator C2 output can be synchronized with

Timer1 by setting the C2SYNC bit of the CM2CON1

register. When enabled, the C2 output is latched on the

falling edge of the Timer1 clock source. If a prescaler is

used with Timer1, the comparator output is latched after

the prescaling function. To prevent a race condition, the

comparator output is latched on the falling edge of the

Timer1 clock source and Timer1 increments on the

rising edge of its clock source. See the Comparator

Block Diagram (Figure 8-3) and the Timer1 Block

Diagram (Figure 6-1) for more information.

• Timer1 count enable (gate)

• Synchronizing output with Timer1

• Simultaneous read of comparator outputs

8.8.1

COMPARATOR C2 GATING TIMER1

This feature can be used to time the duration or interval

of analog events. Clearing the T1GSS bit of the

CM2CON1 register will enable Timer1 to increment

based on the output of Comparator C2. This requires

that Timer1 is on and gating is enabled. See

Section 6.0 “Timer1 Module with Gate Control” for

details.

8.8.3

SIMULTANEOUS COMPARATOR

OUTPUT READ

It is recommended to synchronize the comparator with

Timer1 by setting the C2SYNC bit when the comparator

is used as the Timer1 gate source. This ensures Timer1

does not miss an increment if the comparator changes

during an increment.

The MC1OUT and MC2OUT bits of the CM2CON1

register are mirror copies of both comparator outputs.

The ability to read both outputs simultaneously from a

single register eliminates the timing skew of reading

separate registers.

Note 1: Obtaining the status of C1OUT or C2OUT

by reading CM2CON1 does not affect the

comparator interrupt mismatch registers.

REGISTER 8-3:

CM2CON1: COMPARATOR C2 CONTROL REGISTER 1

R-0

MC1OUT

bit 7

R-0

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

MC2OUT

T1GSS

C2SYNC

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

MC1OUT: Mirror Copy of C1OUT bit

MC2OUT: Mirror Copy of C2OUT bit

Unimplemented: Read as ‘0’

bit 6

bit 5-2

bit 1

T1GSS: Timer1 Gate Source Select bit⁽¹⁾

1= Timer1 gate source is T1G

0= Timer1 gate source is SYNCC2OUT.

bit 0

C2SYNC: Comparator C2 Output Synchronization bit⁽²⁾

1= Output is synchronous to falling edge of Timer1 clock

0= Output is asynchronous

Note 1: Refer to Section 6.6 “Timer1 Gate”.

2: Refer to Figure 8-3.

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8.9.2

LATCH OUTPUT

8.9

Comparator SR Latch

The SR<1:0> bits of the SRCON register control the

latch output multiplexers and determine four possible

output configurations. In these four configurations, the

CxOUT I/O port logic is connected to:

The SR Latch module provides additional control of the

comparator outputs. The module consists of a single

SR latch and output multiplexers. The SR latch can be

set, reset or toggled by the comparator outputs. The SR

latch may also be set or reset, independent of

comparator output, by control bits in the SRCON control

register. The SR latch output multiplexers select

whether the latch outputs or the comparator outputs are

directed to the I/O port logic for eventual output to a pin.

• C1OUT and C2OUT

• C1OUT and SR latch Q

• C2OUT and SR latch Q

• SR latch Q and Q

After any Reset, the default output configuration is the

unlatched C1OUT and C2OUT mode. This maintains

compatibility with devices that do not have the SR latch

feature.

8.9.1

LATCH OPERATION

The latch is a Set-Reset latch that does not depend on a

clock source. Each of the Set and Reset inputs are

active-high. Each latch input is connected to

a

The applicable TRIS bits of the corresponding ports

must be cleared to enable the port pin output drivers.

Additionally, the CxOE comparator output enable bits of

the CMxCON0 registers must be set in order to make the

comparator or latch outputs available on the output pins.

The latch configuration enable states are completely

independent of the enable states for the comparators.

comparator output and a software controlled pulse

generator. The latch can be set by C1OUT or the PULSS

bit of the SRCON register. The latch can be reset by

C2OUT or the PULSR bit of the SRCON register. The

latch is reset-dominant, therefore, if both Set and Reset

inputs are high, the latch will go to the Reset state. Both

the PULSS and PULSR bits are self resetting which

means that a single write to either of the bits is all that is

necessary to complete a latch set or reset operation.

FIGURE 8-7:

SR LATCH SIMPLIFIED BLOCK DIAGRAM

SR0

C1OE

PULSS

Pulse

Gen⁽²⁾

0

MUX

1

C1OUT (from comparator)

C1SEN

S

Q

(3)

C1OUT pin

SR

Latch

(1)

C2OE

SYNCC2OUT (from comparator)

C2REN

1

MUX

R

Q

(3)

0

C2OUT pin

PULSR

Pulse

SR1

Gen⁽²⁾

Note 1: If R = 1and S = 1simultaneously, Q = 0, Q = 1

2: Pulse generator causes a 1/2 Q-state (1 Tosc) pulse width.

3: Output shown for reference only. See I/O port pin block diagram for more detail.

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REGISTER 8-4:

SRCON: SR LATCH CONTROL REGISTER

R/W-0

SR1⁽²⁾

bit 7

R/W-0

SR0⁽²⁾

R/W-0

R/S-0

U-0

—

U-0

—

C1SEN

C2REN

PULSS

PULSR

bit 0

Legend:

S = Bit is set only

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1-0

SR1: SR Latch Configuration bit⁽²⁾

1= C2OUT pin is the latch Q output

0= C2OUT pin is the C2 comparator output

SR0: SR Latch Configuration bits⁽²⁾

1= C1OUT pin is the latch Q output

0= C1OUT pin is the Comparator C1 output

C1SEN: C1 Set Enable bit

1= C1 comparator output sets SR latch

0= C1 comparator output has no effect on SR latch

C2REN: C2 Reset Enable bit

1= C2 comparator output resets SR latch

0= C2 comparator output has no effect on SR latch

PULSS: Pulse the SET Input of the SR Latch bit

1= Triggers pulse generator to set SR latch. Bit is immediately reset by hardware.

0= Does not trigger pulse generator

PULSR: Pulse the Reset Input of the SR Latch bit

1= Triggers pulse generator to reset SR latch. Bit is immediately reset by hardware.

0= Does not trigger pulse generator

Unimplemented: Read as ‘0’

Note 1: The CxOUT bit in the CMxCON0 register will always reflect the actual comparator output (not the level on

the pin), regardless of the SR latch operation.

2: To enable an SR latch output to the pin, the appropriate CxOE and TRIS bits must be properly configured.

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8.10.3

OUTPUT CLAMPED TO VSS

8.10 Comparator Voltage Reference

The CVREF output voltage can be set to VSS with no

power consumption by configuring VRCON as follows:

The comparator voltage reference module provides an

internally generated voltage reference for the compara-

tors. The following features are available:

• VREN = 0

• VRR = 1

• Independent from Comparator operation

• Two 16-level voltage ranges

• Output clamped to VSS

• VR<3:0> = 0000

This allows the comparator to detect a zero-crossing

while not consuming additional CVREF module current.

• Ratiometric with VDD

• Fixed Reference (0.6)

8.10.4

OUTPUT RATIOMETRIC TO VDD

The VRCON register (Register 8-5) controls the

Voltage Reference module shown in Figure 8-8.

The comparator voltage reference is VDD derived and

therefore, the CVREF output changes with fluctuations in

VDD. The tested absolute accuracy of the Comparator

Voltage Reference can be found in Section 17.0

“Electrical Specifications”.

8.10.1

INDEPENDENT OPERATION

The comparator voltage reference is independent of

the comparator configuration. Setting the VREN bit of

the VRCON register will enable the voltage reference.

8.10.2

OUTPUT VOLTAGE SELECTION

The CVREF voltage reference has 2 ranges with 16

voltage levels in each range. Range selection is

controlled by the VRR bit of the VRCON register. The

16 levels are set with the VR<3:0> bits of the VRCON

register.

The CVREF output voltage is determined by the following

equations:

EQUATION 8-1:

CVREF OUTPUT VOLTAGE

VRR = 1 (low range):

CVREF = (VR<3:0>/24) × VDD

VRR = 0 (high range):

CVREF = (VDD/4) +

(VR<3:0> × VDD/32)

The full range of VSS to VDD cannot be realized due to

the construction of the module. See Figure 8-8.

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8.10.5

FIXED VOLTAGE REFERENCE

8.10.7

VOLTAGE REFERENCE

SELECTION

The fixed voltage reference is independent of VDD, with

a nominal output voltage of 0.6V. This reference can be

enabled by setting the VP6EN bit of the VRCON

register to ‘1’. This reference is always enabled when

the HFINTOSC oscillator is active.

Multiplexers on the output of the Voltage Reference

module enable selection of either the CVREF or fixed

voltage reference for use by the comparators.

Setting the C1VREN bit of the VRCON register enables

current to flow in the CVREF voltage divider and selects

the CVREF voltage for use by C1. Clearing the C1VREN

bit selects the fixed voltage for use by C1.

8.10.6

FIXED VOLTAGE REFERENCE

STABILIZATION PERIOD

When the Fixed Voltage Reference module is enabled,

it will require some time for the reference and its

amplifier circuits to stabilize. The user program must

include a small delay routine to allow the module to

settle. See the electrical specifications section for the

minimum delay requirement.

Setting the C2VREN bit of the VRCON register enables

current to flow in the CVREF voltage divider and selects

the CVREF voltage for use by C2. Clearing the C2VREN

bit selects the fixed voltage for use by C2.

When both the C1VREN and C2VREN bits are cleared,

current flow in the CVREF voltage divider is disabled

minimizing the power drain of the voltage reference

peripheral.

FIGURE 8-8:

COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

16 Stages

8R

R

VDD

VRR

8R

16-1 Analog

MUX

CVREF

To Comparators

and ADC module

(1)

VR<3:0>

C1VREN

C2VREN

VP6EN

Sleep

HFINTOSC enable

EN

FixedRef

0.6V

Fixed Voltage

Reference

To Comparators

and ADC module

Note 1: Care should be taken to ensure VREF remains

within the comparator common mode input

range. See Section 17.0 “Electrical Specifica-

tions” for more detail.

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REGISTER 8-5:

VRCON: VOLTAGE REFERENCE CONTROL REGISTER

R/W-0

C1VREN

bit 7

R/W-0

VRR

R/W-0

R/S-0

VR3

R/S-0

VR2

U-0

C2VREN

VP6EN

VR1

VR0

bit 0

Legend:

S = Bit is set only

W = Writable bit

‘1’ = Bit is set

R = Readable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

bit 6

bit 5

bit 4

bit 3-0

C1VREN: Comparator C1 Voltage Reference Enable bit

1= CVREF circuit powered on and routed to C1VREF input of Comparator C1

0= 0.6 Volt constant reference routed to C1VREF input of Comparator C1

C2VREN: Comparator C2 Voltage Reference Enable bit

1= CVREF circuit powered on and routed to C2VREF input of Comparator C2

0= 0.6 Volt constant reference routed to C2VREF input of Comparator C2

VRR: Comparator Voltage Reference CVREF Range Selection bit

1= Low Range

0= High Range

VP6EN: 0.6V Reference Enable bit

1= Enabled

0= Disabled

VR<3:0>: Comparator Voltage Reference CVREF Value Selection 0 ≤ VR<3:0> ≤ 15

When VRR = 1: CVREF = (VR<3:0>/24) * VDD

When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD

TABLE 8-2:

SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE

REFERENCE MODULES

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

ANSEL

ANS7

C1ON

C2ON

ANS6

C1OUT

C2OUT

ANS5

ANS4

ANS3

—

ANS2

C1R

C2R

—

ANS1

C1CH1

C2CH1

T1GSS

INTF

—

ANS0

C1CH0

C2CH0

C2SYNC

RABIF

—

1111 1111 1111 1111

0000 -000 0000 0000

0000 -000 0000 -000

00-- --10 00-- --10

0000 000x 0000 000x

0000 ---- 0000 ----

CM1CON0

CM2CON0

C1OE C1POL

C2OE C2POL

—

CM2CON1 MC1OUT MC2OUT

—

INTCON

PIE2

GIE

OSFIE

OSFIF

—

PEIE

C2IE

C2IF

—

T0IE

C1IE

C1IF

RA5

INTE

EEIE

EEIF

RA4

RABIE

—

T0IF

—

PIR2

—

0000----

PORTA

PORTC

REFCON

SRCON

TRISA

RA3

RC3

VREN

RA2

RC2

RA1

RA0

--xx xxxx --uu uuuu

xxxx xxxx uuuu uuuu

--00 000- --00 000-

0000 00-- 0000 00--

--11 1111 --11 1111

1111 1111 1111 1111

0000 0000 0000 0000

RC7

—

RC6

—

RC5

BGST

RC4

VRBB

RC1

RC0

VROE CVROE

—

SR1

—

SR0

—

C1SEN C2REN PULSS PULSR

—

TRISA5 TRISA4 TRISA3 TRISA2 TRISA1

TRISA0

TRISC0

VR0

TRISC

TRISC7

TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1

VRCON

Legend:

C1VREN C2VREN VRR VP6EN VR3 VR2 VR1

x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator.

DS41262D-page 106

PIC16F631/677/685/687/689/690

Figure 9-1 shows the block diagram of the ADC.

9.0

ANALOG-TO-DIGITAL

CONVERTER (ADC) MODULE

The Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 10-bit binary

representation of that signal. This device uses analog

inputs, which are multiplexed into a single sample and

hold circuit. The output of the sample and hold is

connected to the input of the converter. The converter

generates

a 10-bit binary result via successive

approximation and stores the conversion result into the

ADC result registers (ADRESL and ADRESH).

Note:

The ADC module applies to PIC16F677/

PIC16F685/PIC16F687/PIC16F689/

PIC16F690 devices only.

The ADC voltage reference is software selectable to

either VDD or a voltage applied to the external reference

pins.

The ADC can generate an interrupt upon completion of

a conversion. This interrupt can be used to wake-up the

device from Sleep.

FIGURE 9-1:

ADC BLOCK DIAGRAM

VDD

VCFG = 0

VCFG = 1

VREF

RA0/AN0/C1IN+/ICSPDAT/ULPWU

RA1/AN1/C12IN0-/VREF/ICSPCLK

RA2/AN2/T0CKI/INT/C1OUT

RA4/AN3/T1G/OSC2/CLKOUT

RC0/AN4/C2IN+

RC1/AN5/C12IN1-

(1)

RC2/AN6/C12IN2-/P1D

ADC

(1)

RC3/AN7/C12IN3-/P1C

10

(2)

GO/DONE

RC6/AN8/SS

(2)

RC7/AN9/SDO

0= Left Justify

1= Right Justify

ADFM

(2)

RB4/AN10/SDI/SDA

(2)

ADON

RB5/AN11/RX/DT

10

CVREF

ADRESH ADRESL

VSS

VP6 Reference

CHS

Note 1: P1C and P1D available on PIC16F685/PIC16F690 only.

2: SS, SDO, SDA, RX and DT available on PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.

3: ADC module applies to the PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 devices only.

DS41262D-page 107

PIC16F631/677/685/687/689/690

9.1.3

ADC VOLTAGE REFERENCE

9.1

ADC Configuration

The VCFG bit of the ADCON0 register provides control

of the positive voltage reference. The positive voltage

reference can be either VDD or an external voltage

source. The negative voltage reference is always

connected to the ground reference.

When configuring and using the ADC the following

functions must be considered:

• Port configuration

• Channel selection

• ADC voltage reference selection

• ADC conversion clock source

• Interrupt control

9.1.4

CONVERSION CLOCK

The source of the conversion clock is software

selectable via the ADCS bits of the ADCON1 register.

There are seven possible clock options:

• Results formatting

9.1.1

PORT CONFIGURATION

• FOSC/2

The ADC can be used to convert both analog and digital

signals. When converting analog signals, the I/O pin

should be configured for analog by setting the associated

TRIS and ANSEL bits. See the corresponding port

section for more information.

• FOSC/4

• FOSC/8

• FOSC/16

• FOSC/32

• FOSC/64

Note:

Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

• FRC (dedicated internal oscillator)

The time to complete one bit conversion is defined as

TAD. One full 10-bit conversion requires 11 TAD periods

as shown in Figure 9-2.

9.1.2

CHANNEL SELECTION

For correct conversion, the appropriate TAD specification

must be met. See A/D conversion requirements in

Section 17.0 “Electrical Specifications” for more

information. Table 9-1 gives examples of appropriate

ADC clock selections.

The CHS bits of the ADCON0 register determine which

channel is connected to the sample and hold circuit.

When changing channels, a delay is required before

starting the next conversion. Refer to Section 9.2

“ADC Operation” for more information.

Note:

Unless using the FRC, any changes in the

system clock frequency will change the

ADC clock frequency, which may

adversely affect the ADC result.

DS41262D-page 108

PIC16F631/677/685/687/689/690

TABLE 9-1:

ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)

ADC Clock Period (TAD)

Device Frequency (FOSC)

ADC Clock Source

ADCS<2:0>

20 MHz

8 MHz

4 MHz

1 MHz

FOSC/2

FOSC/4

FOSC/8

FOSC/16

FOSC/32

FOSC/64

FRC

000

100

001

101

010

110

x11

100 ns⁽²⁾

200 ns⁽²⁾

400 ns⁽²⁾

800 ns⁽²⁾

1.6 μs

250 ns⁽²⁾

500 ns⁽²⁾

1.0 μs⁽²⁾

2.0 μs

500 ns⁽²⁾

1.0 μs⁽²⁾

2.0 μs

4.0 μs

8.0 μs⁽³⁾

16.0 μs⁽³⁾

32.0 μs⁽³⁾

64.0 μs⁽³⁾

2-6 μs^(1,4)

4.0 μs

8.0 μs⁽³⁾

16.0 μs⁽³⁾

2-6 μs^(1,4)

3.2 μs

2-6 μs^(1,4)

8.0 μs⁽³⁾

2-6 μs^(1,4)

Legend: Shaded cells are outside of recommended range.

Note 1: The FRC source has a typical TAD time of 4 μs for VDD > 3.0V.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the

conversion will be performed during Sleep.

FIGURE 9-2:

ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

TCY to TAD

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11

b9

b8

b7

b6

b5

b4

b3

b2

b1

b0

Conversion Starts

Holding Capacitor is disconnected from analog input (typically 100 ns)

Set GO/DONE bit

ADRESH and ADRESL registers are loaded,

GO bit is cleared,

ADIF bit is set,

Holding capacitor is connected to analog input

9.1.5

INTERRUPTS

The ADC module allows for the ability to generate an

interrupt upon completion of an Analog-to-Digital

conversion. The ADC interrupt flag is the ADIF bit in the

PIR1 register. The ADC interrupt enable is the ADIE bit

in the PIE1 register. The ADIF bit must be cleared in

software.

Note:

The ADIF bit is set at the completion of

every conversion, regardless of whether

or not the ADC interrupt is enabled.

This interrupt can be generated while the device is

operating or while in Sleep. If the device is in Sleep, the

interrupt will wake-up the device. Upon waking from

Sleep, the next instruction following the SLEEP

instruction is always executed. If the user is attempting

to wake-up from Sleep and resume in-line code

execution, the global interrupt must be disabled. If the

global interrupt is enabled, execution will switch to the

interrupt service routine.

Please see Section 9.1.5 “Interrupts” for more

information.

DS41262D-page 109

PIC16F631/677/685/687/689/690

9.1.6

RESULT FORMATTING

The 10-bit A/D conversion result can be supplied in two

formats, left justified or right justified. The ADFM bit of

the ADCON0 register controls the output format.

Figure 9-3 shows the two output formats.

FIGURE 9-3:

10-BIT A/D CONVERSION RESULT FORMAT

ADRESH

ADRESL

(ADFM = 0)

MSB

bit 7

LSB

bit 0

bit 7

bit 0

10-bit A/D Result

Unimplemented: Read as ‘0’

(ADFM = 1)

MSB

LSB

bit 0

bit 7

Unimplemented: Read as ‘0’

10-bit A/D Result

DS41262D-page 110

PIC16F631/677/685/687/689/690

9.2.5

SPECIAL EVENT TRIGGER

9.2

ADC Operation

An ECCP Special Event Trigger allows periodic ADC

measurements without software intervention. When

this trigger occurs, the GO/DONE bit is set by hardware

and the Timer1 counter resets to zero.

9.2.1

STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a ‘1’. Setting the GO/

DONE bit of the ADCON0 register to a ‘1’ will start the

Analog-to-Digital conversion.

Using the Special Event Trigger does not assure proper

ADC timing. It is the user’s responsibility to ensure that

the ADC timing requirements are met.

Note:

The GO/DONE bit should not be set in the

same instruction that turns on the ADC.

Refer to Section 9.2.6 “A/D Conversion

Procedure”.

See Section 11.0 “Enhanced Capture/Compare/

PWM Module” for more information.

9.2.6

A/D CONVERSION PROCEDURE

9.2.2

COMPLETION OF A CONVERSION

This is an example procedure for using the ADC to

perform an Analog-to-Digital conversion:

When the conversion is complete, the ADC module will:

• Clear the GO/DONE bit

• Set the ADIF flag bit

1. Configure Port:

• Disable pin output driver (See TRIS register)

• Configure pin as analog

• Update the ADRESH:ADRESL registers with new

conversion result

2. Configure the ADC module:

• Select ADC conversion clock

• Configure voltage reference

• Select ADC input channel

• Select result format

9.2.3

TERMINATING A CONVERSION

If a conversion must be terminated before completion,

the GO/DONE bit can be cleared in software. The

ADRESH:ADRESL registers will not be updated with

the partially complete Analog-to-Digital conversion

sample. Instead, the ADRESH:ADRESL register pair

will retain the value of the previous conversion. Addi-

tionally, a 2 TAD delay is required before another acqui-

sition can be initiated. Following this delay, an input

acquisition is automatically started on the selected

channel.

• Turn on ADC module

3. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

• Enable ADC interrupt

• Enable peripheral interrupt

• Enable global interrupt⁽¹⁾

4. Wait the required acquisition time⁽²⁾

.

Note:

A device Reset forces all registers to their

Reset state. Thus, the ADC module is

turned off and any pending conversion is

terminated.

5. Start conversion by setting the GO/DONE bit.

6. Wait for ADC conversion to complete by one of

the following:

• Polling the GO/DONE bit

9.2.4

ADC OPERATION DURING SLEEP

• Waiting for the ADC interrupt (interrupts

enabled)

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the FRC

option. When the FRC clock source is selected, the

ADC waits one additional instruction before starting the

conversion. This allows the SLEEP instruction to be

executed, which can reduce system noise during the

conversion. If the ADC interrupt is enabled, the device

will wake-up from Sleep when the conversion

completes. If the ADC interrupt is disabled, the ADC

module is turned off after the conversion completes,

although the ADON bit remains set.

7. Read ADC Result

8. Clear the ADC interrupt flag (required if interrupt

is enabled).

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep

and resume in-line code execution.

2: See Section 9.3 “A/D Acquisition

Requirements”.

When the ADC clock source is something other than

FRC, a SLEEP instruction causes the present conver-

sion to be aborted and the ADC module is turned off,

although the ADON bit remains set.

DS41262D-page 111

PIC16F631/677/685/687/689/690

EXAMPLE 9-1:

A/D CONVERSION

;This code block configures the ADC

;for polling, Vdd reference, Frc clock

;and AN0 input.

;

;Conversion start & polling for completion

; are included.

;

BANKSEL

MOVLW

MOVWF

BANKSEL

BSF

BANKSEL

BSF

BANKSEL

MOVLW

MOVWF

CALL

BSF

BTFSC

GOTO

BANKSEL

MOVF

MOVWF

BANKSEL

MOVF

ADCON1

;

B’01110000’ ;ADC Frc clock

ADCON1

TRISA

TRISA,0

ANSEL

ANSEL,0

ADCON0

B’10000001’ ;Right justify,

ADCON0

SampleTime

ADCON0,GO

$-1

;

;Set RA0 to input

;

;Set RA0 to analog

;

; Vdd Vref, AN0, On

;Acquisiton delay

;Start conversion

;Is conversion done?

;No, test again

;

;Read upper 2 bits

;store in GPR space

;

ADRESH

ADRESH,W

RESULTHI

ADRESL

ADRESL,W

RESULTLO

;Read lower 8 bits

;Store in GPR space

MOVWF

9.2.7

ADC REGISTER DEFINITIONS

The following registers are used to control the

operation of the ADC.

DS41262D-page 112

PIC16F631/677/685/687/689/690

REGISTER 9-1:

ADCON0: A/D CONTROL REGISTER 0

R/W-0

ADFM

bit 7

R/W-0

VCFG

R/W-0

CHS3

R/W-0

CHS2

R/W-0

CHS1

R/W-0

CHS0

R/W-0

ADON

GO/DONE

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

ADFM: A/D Conversion Result Format Select bit

1= Right justified

0= Left justified

bit 6

VCFG: Voltage Reference bit

1= VREF pin

0= VDD

bit 5-2

CHS<3:0>: Analog Channel Select bits

0000= AN0

0001= AN1

0010= AN2

0011= AN3

0100= AN4

0101= AN5

0110= AN6

0111= AN7

1000= AN8

1001= AN9

1010= AN10

1011= AN11

1100= CVREF

1101= 0.6V Reference

1110= Reserved. Do not use.

1111= Reserved. Do not use.

bit 1

bit 0

GO/DONE: A/D Conversion Status bit

1= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0= A/D conversion completed/not in progress

ADON: ADC Enable bit

1= ADC is enabled

0= ADC is disabled and consumes no operating current

DS41262D-page 113

PIC16F631/677/685/687/689/690

REGISTER 9-2:

ADCON1: A/D CONTROL REGISTER 1

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

ADCS2

ADCS1

ADCS0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

Unimplemented: Read as ‘0’

bit 6-4

ADCS<2:0>: A/D Conversion Clock Select bits

000= FOSC/2

001= FOSC/8

010= FOSC/32

x11= FRC (clock derived from a dedicated internal oscillator = 500 kHz max)

100= FOSC/4

101= FOSC/16

110= FOSC/64

bit 3-0

Unimplemented: Read as ‘0’

DS41262D-page 114

PIC16F631/677/685/687/689/690

REGISTER 9-3:

ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0

R/W-x

ADRES9

bit 7

R/W-x

ADRES8

ADRES7

ADRES6

ADRES5

ADRES4

ADRES3

ADRES2

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

ADRES<9:2>: ADC Result Register bits

Upper 8 bits of 10-bit conversion result

REGISTER 9-4:

ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0

R/W-x

ADRES1

bit 7

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

—

ADRES0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

ADRES<1:0>: ADC Result Register bits

Lower 2 bits of 10-bit conversion result

Reserved: Do not use.

REGISTER 9-5:

ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

ADRES9

ADRES8

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-2

bit 1-0

Reserved: Do not use.

ADRES<9:8>: ADC Result Register bits

Upper 2 bits of 10-bit conversion result

REGISTER 9-6:

ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1

R/W-x

ADRES7

bit 7

R/W-x

ADRES6

ADRES5

ADRES4

ADRES3

ADRES2

ADRES1

ADRES0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

ADRES<7:0>: ADC Result Register bits

Lower 8 bits of 10-bit conversion result

DS41262D-page 115

PIC16F631/677/685/687/689/690

an A/D acquisition must be done before the conversion

can be started. To calculate the minimum acquisition

time, Equation 9-1 may be used. This equation

assumes that 1/2 LSb error is used (1024 steps for the

ADC). The 1/2 LSb error is the maximum error allowed

for the ADC to meet its specified resolution.

9.3

A/D Acquisition Requirements

For the ADC to meet its specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The Analog

Input model is shown in Figure 9-4. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge the

capacitor CHOLD. The sampling switch (RSS) impedance

varies over the device voltage (VDD), see Figure 9-4.

The maximum recommended impedance for analog

sources is 10 kΩ. As the source impedance is

decreased, the acquisition time may be decreased.

After the analog input channel is selected (or changed),

EQUATION 9-1:

ACQUISITION TIME EXAMPLE

Temperature = 50°C and external impedance of 10kΩ 5.0V VDD

Assumptions:

TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

= TAMP + TC + TCOFF

= 5µs + TC + [(Temperature - 25°C)(0.05µs/°C)]

The value for TC can be approximated with the following equations:

1

2047

⎛

⎞

= VCHOLD

-----------

;[1] VCHOLD charged to within 1/2 lsb

VAPPLIED 1 –

⎝

⎠

–TC

---------

⎛

⎞

VAPPLIED 1 – e ^RC= V^CHOLD

;[2] VCHOLD charge response to VAPPLIED

⎜

⎝

⎟

⎠

–Tc

--------

⎛

⎞

1

2047

VAPPLIED 1 – e^RC= V^APPLIED1 –

⎛

⎞

⎠

;combining [1] and [2]

-----------

⎜

⎝

⎟

⎠

⎝

Solving for TC:

TC = –CHOLD(RIC + RSS + RS) ln(1/2047)

= –10pF(1kΩ + 7kΩ + 10kΩ) ln(0.0004885)

= 1.37µs

Therefore:

TACQ = 5µS + 1.37µS + [(50°C- 25°C)(0.05µS/°C)]

= 7.67µS

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin

leakage specification.

DS41262D-page 116

PIC16F631/677/685/687/689/690

FIGURE 9-4:

ANALOG INPUT MODEL

VDD

VT = 0.6V

Sampling

Switch

ANx

SS

RIC ≤ 1k

Rss

Rs

CPIN

5 pF

VA

I LEAKAGE

± 500 nA

CHOLD = 10 pF

VSS/VREF-

VT = 0.6V

6V

5V

RSS

VDD 4V

3V

Legend: CPIN

= Input Capacitance

= Threshold Voltage

VT

2V

I LEAKAGE = Leakage current at the pin due to

various junctions

RIC

SS

CHOLD

= Interconnect Resistance

= Sampling Switch

= Sample/Hold Capacitance

5 6 7 8 9 1011

Sampling Switch

(kΩ)

FIGURE 9-5:

ADC TRANSFER FUNCTION

Full-Scale Range

3FFh

3FEh

3FDh

3FCh

3FBh

1 LSB ideal

Full-Scale

Transition

004h

003h

002h

001h

000h

Analog Input Voltage

1 LSB ideal

Zero-Scale

Transition

VDD/VREF+

VSS/VREF-

DS41262D-page 117

PIC16F631/677/685/687/689/690

TABLE 9-2:

SUMMARY OF ASSOCIATED ADC REGISTERS

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADCON0

ADCON1

ANSEL

ADFM

—

VCFG

ADCS2

ANS6

—

CHS3

ADCS1

ANS5

—

CHS2

ADCS0

ANS4

—

CHS1

—

CHS0

—

GO/DONE ADON

0000 0000 0000 0000

-000 ---- -000 ----

1111 1111 1111 1111

---- 1111 ---- 1111

xxxx xxxx uuuu uuuu

0000 000x 0000 000x

—

ANS7

—

ANS3

ANS11

ANS2

ANS10

ANS1

ANS9

ANS0

ANS8

ANSELH

ADRESH A/D Result Register High Byte

ADRESL A/D Result Register Low Byte

INTCON

PIE1

GIE

—

PEIE

ADIE

ADIF

—

T0IE

RCIE

RCIF

RA5

INTE

TXIE

TXIF

RA4

RB4

RC4

RABIE

SSPIE

SSPIF

RA3

T0IF

CCP1IE

CCP1IF

RA2

INTF

TMR2IE

TMR2IF

RA1

RABIF

TMR1IE -000 0000 -000 0000

TMR1IF -000 0000 -000 0000

PIR1

—

PORTA

PORTB

PORTC

TRISA

TRISB

TRISC

Legend:

—

RA0

—

--xx xxxx --uu uuuu

xxxx ---- uuuu ----

xxxx xxxx uuuu uuuu

RB7

RC7

—

RB6

RC6

—

RB5

—

RC5

RC3

RC2

RC1

RC0

TRISA5 TRISA4 TRISA3 TRISA2

TRISA1

—

TRISA0 --11 1111 --11 1111

1111 ---- 1111 ----

TRISC0 1111 1111 1111 1111

TRISB7 TRISB6 TRISB5 TRISB4

—

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2

TRISC1

x= unknown, u= unchanged, —= unimplemented read as ‘0’. Shaded cells are not used for ADC module.

DS41262D-page 118

PIC16F631/677/685/687/689/690

10.1 EEADR and EEADRH Registers

10.0 DATA EEPROM AND FLASH

PROGRAM MEMORY

CONTROL

The EEADR and EEADRH registers can address up to

a maximum of 256 bytes of data EEPROM or up to a

maximum of 4K words of program EEPROM.

Data EEPROM memory is readable and writable and

the Flash program memory (PIC16F685/PIC16F689/

PIC16F690 only) is readable during normal operation

(full VDD range). These memories are not directly

mapped in the register file space. Instead, they are indi-

rectly addressed through the Special Function Regis-

ters (SFRs). There are six SFRs used to access these

memories:

When selecting a program address value, the MSB of

the address is written to the EEADRH register and the

LSB is written to the EEADR register. When selecting a

data address value, only the LSB of the address is

written to the EEADR register.

10.1.1

EECON1 AND EECON2 REGISTERS

EECON1 is the control register for EE memory

accesses.

• EECON1

• EECON2

Control bit EEPGD (PIC16F685/PIC16F689/PIC16F690)

determines if the access will be a program or data mem-

ory access. When clear, as it is when reset, any subse-

quent operations will operate on the data memory. When

set, any subsequent operations will operate on the pro-

gram memory. Program memory can only be read.

• EEDAT

• EEDATH (PIC16F685/PIC16F689/PIC16F690 only)

• EEADR

• EEADRH (PIC16F685/PIC16F689/PIC16F690 only)

When interfacing the data memory block, EEDAT holds

the 8-bit data for read/write, and EEADR holds the

address of the EEDAT location being accessed. These

devices, except for the PIC16F631, have 256 bytes of

data EEPROM with an address range from 0h to 0FFh.

The PIC16F631 has 128 bytes of data EEPROM with

an address range from 0h to 07Fh.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set, in

software. They are cleared in hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

When accessing the program memory block of the

PIC16F685/PIC16F689/PIC16F690 devices, the EEDAT

and EEDATH registers form a 2-byte word that holds the

14-bit data for read/write, and the EEADR and EEADRH

registers form a 2-byte word that holds the 12-bit address

of the EEPROM location being read. These devices

(PIC16F685/PIC16F689/PIC16F690) have 4K words of

program EEPROM with an address range from 0h to

0FFFh. The program memory allows one-word reads.

The WREN bit, when set, will allow a write operation to

data EEPROM. On power-up, the WREN bit is clear.

The WRERR bit is set when a write operation is

interrupted by a MCLR or a WDT Time-out Reset

during normal operation. In these situations, following

Reset, the user can check the WRERR bit and rewrite

the location.

Interrupt flag bit EEIF of the PIR2 register is set when

write is complete. It must be cleared in the software.

The EEPROM data memory allows byte read and write.

A byte write automatically erases the location and

writes the new data (erase before write).

EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used

exclusively in the data EEPROM write sequence.

The write time is controlled by an on-chip timer. The

write/erase voltages are generated by an on-chip

charge pump rated to operate over the voltage range of

the device for byte or word operations.

When the device is code-protected, the CPU may

continue to read and write the data EEPROM memory

and read the program memory. When code-protected,

the device programmer can no longer access data or

program memory.

DS41262D-page 119

PIC16F631/677/685/687/689/690

REGISTER 10-1: EEDAT: EEPROM DATA REGISTER

R/W-0

EEDAT7

EEDAT6

EEDAT5

EEDAT4

EEDAT3

EEDAT2

EEDAT1

EEDAT0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

EEDAT<7:0>: 8 Least Significant Address bits to Write to or Read from data EEPROM or Read from program memory

REGISTER 10-2: EEADR: EEPROM ADDRESS REGISTER

R/W-0

(1)

EEADR7

EEADR6

EEADR5

EEADR4

EEADR3

EEADR2

EEADR1

EEADR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

(1)

bit 7-0

EEADR<7:0>: 8 Least Significant Address bits for EEPROM Read/Write Operation or Read from program memory

Note 1: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.

REGISTER 10-3: EEDATH: EEPROM DATA HIGH BYTE REGISTER⁽¹⁾

U-0

—

U-0

—

R/W-0

EEDATH5

EEDATH4

EEDATH3

EEDATH2

EEDATH1

EEDATH0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

EEDATH<5:0>: 6 Most Significant Data bits from program memory

Note 1: PIC16F685/PIC16F689/PIC16F690 only.

REGISTER 10-4: EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

EEADRH3

EEADRH2

EEADRH1

EEADRH0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

EEADRH<3:0>: Specifies the 4 Most Significant Address bits or high bits for program memory reads

Note 1: PIC16F685/PIC16F689/PIC16F690 only.

DS41262D-page 120

PIC16F631/677/685/687/689/690

REGISTER 10-5: EECON1: EEPROM CONTROL REGISTER

R/W-x

EEPGD⁽¹⁾

U-0

—

U-0

—

U-0

—

R/W-x

R/W-0

WREN

R/S-0

WR

R/S-0

RD

WRERR

bit 7

bit 0

Legend:

S = Bit can only be set

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

EEPGD: Program/Data EEPROM Select bit⁽¹⁾

1= Accesses program memory

0= Accesses data memory

bit 6-4

bit 3

Unimplemented: Read as ‘0’

WRERR: EEPROM Error Flag bit

1= A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during

normal operation or BOR Reset)

0= The write operation completed

bit 2

bit 1

WREN: EEPROM Write Enable bit

1= Allows write cycles

0= Inhibits write to the data EEPROM

WR: Write Control bit

EEPGD = 1:

This bit is ignored

EEPGD = 0:

1= Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only

be set, not cleared, in software.)

0= Write cycle to the data EEPROM is complete

bit 0

RD: Read Control bit

1= Initiates a memory read (the RD is cleared in hardware and can only be set, not cleared, in

software.)

0= Does not initiate a memory read

Note 1: PIC16F685/PIC16F689/PIC16F690 only.

DS41262D-page 121

PIC16F631/677/685/687/689/690

10.1.2

READING THE DATA EEPROM

MEMORY

10.1.3

WRITING TO THE DATA EEPROM

MEMORY

To read a data memory location, the user must write the

address to the EEADR register, clear the EEPGD

control bit of the EECON1 register, and then set control

bit RD. The data is available at the very next cycle, in

the EEDAT register; therefore, it can be read in the next

instruction. EEDAT will hold this value until another

read or until it is written to by the user (during a write

operation).

To write an EEPROM data location, the user must first

write the address to the EEADR register and the data

to the EEDAT register. Then the user must follow a

specific sequence to initiate the write for each byte.

The write will not initiate if the above sequence is not

followed exactly (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. Interrupts

should be disabled during this code segment.

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental

writes to data EEPROM due to errant (unexpected)

code execution (i.e., lost programs). The user should

keep the WREN bit clear at all times, except when

updating EEPROM. The WREN bit is not cleared

by hardware.

EXAMPLE 10-1:

DATA EEPROM READ

BANKSEL EEADR

;

MOVF

DATA_EE_ADDR, W;

MOVWF

EEADR

;Data Memory

;Address to read

;

BANKSEL EECON1

BCF

BSF

EECON1, EEPGD ;Point to DATA memory

EECON1, RD

;EE Read

;

;W = EEDAT

;Bank 0

After a write sequence has been initiated, clearing the

WREN bit will not affect this write cycle. The WR bit will

be inhibited from being set unless the WREN bit is set.

BANKSEL EEDAT

MOVF

BCF

EEDAT, W

STATUS, RP1

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. EEIF must be

cleared by software.

EXAMPLE 10-2:

DATA EEPROM WRITE

BANKSEL EEADR

;

MOVF

DATA_EE_ADDR, W;

MOVWF

MOVF

EEADR

DATA_EE_DATA, W;

;Data Memory Address to write

MOVWF

EEDAT

;Data Memory Value to write

BANKSEL EECON1

;

BCF

BSF

EECON1, EEPGD ;Point to DATA memory

EECON1, WREN

;Enable writes

BCF

INTCON, GIE

$-2

55h

EECON2

AAh

EECON2

EECON1, WR

INTCON, GIE

;Disable INTs.

;SEE AN576

BTFSC

GOTO

MOVLW

MOVWF

MOVLW

MOVWF

BSF

;

;Write 55h

;

;Write AAh

;Set WR bit to begin write

;Enable INTs.

BSF

SLEEP

BCF

BANKSEL 0x00

;Wait for interrupt to signal write complete (optional)

;Disable writes

;Bank 0

EECON1, WREN

DS41262D-page 122

PIC16F631/677/685/687/689/690

EEDAT and EEDATH registers will hold this value until

another read or until it is written to by the user.

10.1.4

READING THE FLASH PROGRAM

MEMORY (PIC16F685/PIC16F689/

PIC16F690)

Note 1: The two instructions following a program

memory read are required to be NOPs.

This prevents the user from executing a

two-cycle instruction on the next

instruction after the RD bit is set.

To read a program memory location, the user must

write the Least and Most Significant address bits to the

EEADR and EEADRH registers, set the EEPGD con-

trol bit of the EECON1 register, and then set control bit

RD. Once the read control bit is set, the program mem-

ory Flash controller will use the second instruction

cycle to read the data. This causes the second instruc-

tion immediately following the “BSF EECON1,RD”

instruction to be ignored. The data is available in the

very next cycle, in the EEDAT and EEDATH registers;

therefore, it can be read as two bytes in the following

instructions.

2: If the WR bit is set when EEPGD = 1, it

will be immediately reset to ‘0’ and no

operation will take place.

EXAMPLE 10-3:

FLASH PROGRAM READ

BANKSELEEADR

;

MOVF

MOVWF

MOVF

MS_PROG_EE_ADDR, W

EEADRH

LS_PROG_EE_ADDR, W

EEADR

;MS Byte of Program Address to read

;

MOVWF

;LS Byte of Program Address to read

BANKSELEECON1

;

BSF

EECON1, EEPGD

EECON1, RD

;Point to PROGRAM memory

;EE Read

;

NOP

;First instruction after BSF EECON1,RD executes normally

;Any instructions here are ignored as program

;memory is read in second cycle after BSF EECON1,RD

BANKSELEEDAT

;

MOVF

EEDAT, W

;W = LS Byte of Program Memory

MOVWF

MOVF

MOVWF

LOWPMBYTE

EEDATH, W

HIGHPMBYTE

;

;W = MS Byte of Program EEDAT

;

BANKSEL0x00

;Bank 0

DS41262D-page 123

PIC16F631/677/685/687/689/690

FIGURE 10-1:

FLASH PROGRAM MEMORY READ CYCLE EXECUTION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

PC + 1

EEADRH,EEADR

PC + 3

PC+3

PC + 4

PC + 5

Flash ADDR

Flash Data

INSTR (PC)

INSTR (PC + 1)

EEDATH,EEDAT

INSTR (PC + 3)

INSTR (PC + 4)

BSF EECON1,RD

executed here

INSTR(PC - 1)

executed here

INSTR(PC + 1)

executed here

Forced NOP

executed here

INSTR(PC + 3)

executed here

INSTR(PC + 4)

executed here

RD bit

EEDATH

EEDAT

Register

EERHLT

DS41262D-page 124

PIC16F631/677/685/687/689/690

When the data memory is code-protected, only the

CPU is able to read and write data to the data

10.2 Write Verify

Depending on the application, good programming

practice may dictate that the value written to the data

EEPROM should be verified (see Example 10-4) to the

desired value to be written.

EEPROM. It is recommended to code-protect the pro-

gram memory when code-protecting data memory.

This prevents anyone from programming zeroes over

the existing code (which will execute as NOPs) to reach

an added routine, programmed in unused program

memory, which outputs the contents of data memory.

Programming unused locations in program memory to

‘0’ will also help prevent data memory code protection

from becoming breached.

EXAMPLE 10-4:

WRITE VERIFY

BANKSEL EEDAT

;

MOVF

EEDAT, W

;EEDAT not changed

;from previous write

BANKSEL EECON1

;

BSF

EECON1, RD

;YES, Read the

;value written

;

BANKSEL EEDAT

XORWF

BTFSS

GOTO

:

EEDAT, W

STATUS, Z

WRITE_ERR

;

;Is data the same

;No, handle error

;Yes, continue

;Bank 0

BANKSEL 0x00

10.2.1

USING THE DATA EEPROM

The data EEPROM is

a high-endurance, byte

addressable array that has been optimized for the

storage of frequently changing information (e.g.,

program variables or other data that are updated often).

When variables in one section change frequently, while

variables in another section do not change, it is possible

to exceed the total number of write cycles to the

EEPROM (specification D124) without exceeding the

total number of write cycles to

a single byte

(specifications D120 and D120A). If this is the case,

then a refresh of the array must be performed. For this

reason, variables that change infrequently (such as

constants, IDs, calibration, etc.) should be stored in

Flash program memory.

10.3 Protection Against Spurious Write

There are conditions when the user may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built in. On power-up, WREN is cleared. Also, the

Power-up

Timer

(64 ms

duration)

prevents

EEPROM write.

The write initiate sequence and the WREN bit together

help prevent an accidental write during:

• Brown-out

• Power Glitch

• Software Malfunction

10.4 Data EEPROM Operation During

Code-Protect

Data memory can be code-protected by programming

the CPD bit in the Configuration Word register

(Register 14-1) to ‘0’.

DS41262D-page 125

PIC16F631/677/685/687/689/690

TABLE 10-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EECON1

EECON2

EEADR

EEPGD⁽¹⁾

—

WRERR

WREN

WR

RD

x--- x000

---- ----

0000 0000

0--- q000

---- ----

0000 0000

EEPROM Control Register 2 (not a physical register)

EEADR7⁽²⁾EEADR6 EEADR5

EEADR4

EEADR3

EEADR2

EEADR1

EEADR0

EEADRH⁽¹⁾

EEDAT

—

EEDAT7

—

EEDAT6

—

EEADRH3 EEADRH2 EEADRH1 EEADRH0

EEDAT3 EEDAT2 EEDAT1 EEDAT0

---- 0000

0000 0000

--00 0000

0000 0000

0000 ----

---- 0000

0000 0000

--00 0000

0000 0000

0000 ----

EEDAT5

EEDAT4

EEDATH⁽¹⁾

INTCON

PIE2

EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0

GIE

PEIE

C2IE

C2IF

T0IE

C1IE

C1IF

INTE

EEIE

EEIF

RABIE

—

T0IF

—

INTF

—

RABIF

—

OSFIE

OSFIF

PIR2

—

Legend:

x= unknown, u= unchanged, —= unimplemented read as ‘0’, q= value depends upon condition.

Shaded cells are not used by data EEPROM module.

Note 1:

2:

PIC16F685/PIC16F689/PIC16F690 only.

PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.

DS41262D-page 126

PIC16F631/677/685/687/689/690

Table 11-1 shows the timer resources required by the

ECCP module.

11.0 ENHANCED

CAPTURE/COMPARE/PWM

MODULE

TABLE 11-1: ECCP MODE – TIMER

RESOURCES REQUIRED

The Enhanced Capture/Compare/PWM module is a

peripheral which allows the user to time and control

different events. In Capture mode, the peripheral

allows the timing of the duration of an event. The

Compare mode allows the user to trigger an external

event when a predetermined amount of time has

expired. The PWM mode can generate a Pulse-Width

Modulated signal of varying frequency and duty cycle.

ECCP Mode

Timer Resource

Capture

Compare

PWM

Timer1

Timer2

REGISTER 11-1: CCP1CON: ENHANCED CCP1 CONTROL REGISTER

R/W-0

P1M1

R/W-0

P1M0

R/W-0

DC1B0

R/W-0

CCP1M1

R/W-0

DC1B1

CCP1M3

CCP1M2

CCP1M0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

P1M<1:0>: PWM Output Configuration bits

If CCP1M<3:2> = 00, 01, 10:

xx= P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins

If CCP1M<3:2> = 11:

00= Single output; P1A modulated; P1B, P1C, P1D assigned as port pins

01= Full-Bridge output forward; P1D modulated; P1A active; P1B, P1C inactive

10= Half-Bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins

11= Full-Bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive

bit 5-4

DC1B<1:0>: PWM Duty Cycle Least Significant bits

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.

bit 3-0

CCP1M<3:0>: ECCP Mode Select bits

0000= Capture/Compare/PWM off (resets ECCP module)

0001= Unused (reserved)

0010= Compare mode, toggle output on match (CCP1IF bit is set)

0011= Unused (reserved)

0100= Capture mode, every falling edge

0101= Capture mode, every rising edge

0110= Capture mode, every 4th rising edge

0111= Capture mode, every 16th rising edge

1000= Compare mode, set output on match (CCP1IF bit is set)

1001= Compare mode, clear output on match (CCP1IF bit is set)

1010= Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is

unaffected)

1011= Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 or TMR2, and starts

an A/D conversion, if the ADC module is enabled)

1100= PWM mode; P1A, P1C active-high; P1B, P1D active-high

1101= PWM mode; P1A, P1C active-high; P1B, P1D active-low

1110= PWM mode; P1A, P1C active-low; P1B, P1D active-high

1111= PWM mode; P1A, P1C active-low; P1B, P1D active-low

DS41262D-page 127

PIC16F631/677/685/687/689/690

11.1.2

TIMER1 MODE SELECTION

11.1 Capture Mode

Timer1 must be running in Timer mode or Synchronized

Counter mode for the CCP module to use the capture

feature. In Asynchronous Counter mode, the capture

operation may not work.

In Capture mode, CCPR1H:CCPR1L captures the

16-bit value of the TMR1 register when an event occurs

on pin CCP1. An event is defined as one of the

following and is configured by the CCP1M<3:0> bits of

the CCP1CON register:

11.1.3

SOFTWARE INTERRUPT

• Every falling edge

• Every rising edge

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCP1IE interrupt enable bit of the PIE1 register clear to

avoid false interrupts. Additionally, the user should

clear the CCP1IF interrupt flag bit of the PIR1 register

following any change in operating mode.

• Every 4th rising edge

• Every 16th rising edge

When a capture is made, the Interrupt Request Flag bit

CCP1IF of the PIR1 register is set. The interrupt flag

must be cleared in software. If another capture occurs

before the value in the CCPR1H, CCPR1L register pair

is read, the old captured value is overwritten by the new

captured value (see Figure 11-1).

11.1.4

CCP PRESCALER

There are four prescaler settings specified by the

CCP1M<3:0> bits of the CCP1CON register.

Whenever the CCP module is turned off, or the CCP

module is not in Capture mode, the prescaler counter

is cleared. Any Reset will clear the prescaler counter.

11.1.1

CCP1 PIN CONFIGURATION

In Capture mode, the CCP1 pin should be configured

as an input by setting the associated TRIS control bit.

Switching from one capture prescaler to another does not

clear the prescaler and may generate a false interrupt. To

avoid this unexpected operation, turn the module off by

clearing the CCP1CON register before changing the

prescaler (see Example 11-1).

Note:

If the CCP1 pin is configured as an output,

a write to the port can cause a capture

condition.

FIGURE 11-1:

CAPTURE MODE

OPERATION BLOCK

DIAGRAM

EXAMPLE 11-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

BANKSELCCP1CON

;Set Bank bits to point

;to CCP1CON

;Turn CCP module off

Set Flag bit CCP1IF

(PIR1 register)

Prescaler

÷ 1, 4, 16

CLRF

CCP1CON

MOVLW

NEW_CAPT_PS;Load the W reg with

; the new prescaler

CCP1

CCPR1H

CCPR1L

; move value and CCP ON

Capture

Enable

MOVWF

CCP1CON

;Load CCP1CON with this

; value

and

Edge Detect

TMR1H

TMR1L

CCP1CON<3:0>

System Clock (FOSC)

DS41262D-page 128

PIC16F631/677/685/687/689/690

11.2.2

TIMER1 MODE SELECTION

11.2 Compare Mode

In Compare mode, Timer1 must be running in either

Timer mode or Synchronized Counter mode. The

compare operation may not work in Asynchronous

Counter mode.

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the CCP module may:

• Toggle the CCP1 output

• Set the CCP1 output

11.2.3

SOFTWARE INTERRUPT MODE

• Clear the CCP1 output

When Generate Software Interrupt mode is chosen

(CCP1M<3:0> = 1010), the CCP module does not

assert control of the CCP1 pin (see the CCP1CON

register).

• Generate a Special Event Trigger

• Generate a Software Interrupt

The action on the pin is based on the value of the

CCP1M<3:0> control bits of the CCP1CON register.

11.2.4

SPECIAL EVENT TRIGGER

All Compare modes can generate an interrupt.

When Special Event Trigger mode is chosen

(CCP1M<3:0> = 1011), the CCP module does the

following:

FIGURE 11-2:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

• Resets Timer1

• Starts an ADC conversion if ADC is enabled

CCP1CON<3:0>

Mode Select

The CCP module does not assert control of the CCP1

pin in this mode (see the CCP1CON register).

Set CCP1IF Interrupt Flag

The Special Event Trigger output of the CCP occurs

immediately upon a match between the TMR1H,

TMR1L register pair and the CCPR1H, CCPR1L

register pair. The TMR1H, TMR1L register pair is not

reset until the next rising edge of the Timer1 clock. This

allows the CCPR1H, CCPR1L register pair to

effectively provide a 16-bit programmable period

register for Timer1.

(PIR1)

4

CCP1

CCPR1H CCPR1L

Comparator

Q

S

R

Output

Logic

Match

TMR1H TMR1L

TRIS

Output Enable

Special Event Trigger

Note 1: The Special Event Trigger from the CCP

module does not set interrupt flag bit

TMR1IF of the PIR1 register.

Special Event Trigger will:

•

Clear TMR1H and TMR1L registers.

NOT set interrupt flag bit TMR1IF of the PIR1 register.

Set the GO/DONE bit to start the ADC conversion.

2: Removing the match condition by

changing the contents of the CCPR1H

and CCPR1L register pair, between the

clock edge that generates the Special

Event Trigger and the clock edge that

generates the Timer1 Reset, will preclude

the Reset from occurring.

11.2.1

CCP1 PIN CONFIGURATION

The user must configure the CCP1 pin as an output by

clearing the associated TRIS bit.

Note:

Clearing the CCP1CON register will force

the CCP1 compare output latch to the

default low level. This is not the port I/O

data latch.

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The PWM output (Figure 11-4) has a time base

(period) and a time that the output stays high (duty

cycle).

11.3 PWM Mode

The PWM mode generates a Pulse-Width Modulated

signal on the CCP1 pin. The duty cycle, period and

resolution are determined by the following registers:

FIGURE 11-4:

CCP PWM OUTPUT

• PR2

Period

• T2CON

• CCPR1L

• CCP1CON

Pulse Width

TMR2 = PR2

TMR2 = CCPR1L:CCP1CON<5:4>

In Pulse-Width Modulation (PWM) mode, the CCP

module produces up to a 10-bit resolution PWM output

on the CCP1 pin. Since the CCP1 pin is multiplexed

with the PORT data latch, the TRIS for that pin must be

cleared to enable the CCP1 pin output driver.

TMR2 = 0

Note:

Clearing the CCP1CON register will

relinquish CCP1 control of the CCP1 pin.

Figure 11-3 shows a simplified block diagram of PWM

operation.

Figure 11-4 shows a typical waveform of the PWM

signal.

For a step-by-step procedure on how to set up the CCP

module for PWM operation, see Section 11.3.7

“Setup for PWM Operation”.

FIGURE 11-3:

SIMPLIFIED PWM BLOCK

DIAGRAM

CCP1CON<5:4>

Duty Cycle Registers

CCPR1L

CCPR1H⁽²⁾(Slave)

Comparator

CCP1

R

S

Q

(1)

TMR2

TRIS

Comparator

PR2

Clear Timer2,

toggle CCP1 pin and

latch duty cycle

Note 1: The 8-bit timer TMR2 register is concatenated

with the 2-bit internal system clock (FOSC), or

2 bits of the prescaler, to create the 10-bit time

base.

2: In PWM mode, CCPR1H is a read-only register.

DS41262D-page 130

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11.3.1

PWM PERIOD

EQUATION 11-2: PULSE WIDTH

The PWM period is specified by the PR2 register of

Timer2. The PWM period can be calculated using the

formula of Equation 11-1.

Pulse Width = (CCPR1L:CCP1CON<5:4>) •

TOSC • (TMR2 Prescale Value)

EQUATION 11-1: PWM PERIOD

EQUATION 11-3: DUTY CYCLE RATIO

PWM Period = [(PR2) + 1] • 4 • TOSC •

(TMR2 Prescale Value)

(CCPR1L:CCP1CON<5:4>)

Duty Cycle Ratio = -----------------------------------------------------------------------

4(PR2 + 1)

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

The CCPR1H register and a 2-bit internal latch are

used to double buffer the PWM duty cycle. This double

buffering is essential for glitchless PWM operation.

• TMR2 is cleared

• The CCP1 pin is set. (Exception: If the PWM duty

cycle = 0%, the pin will not be set.)

The 8-bit timer TMR2 register is concatenated with

either the 2-bit internal system clock (FOSC), or 2 bits of

the prescaler, to create the 10-bit time base. The system

clock is used if the Timer2 prescaler is set to 1:1.

• The PWM duty cycle is latched from CCPR1L into

CCPR1H.

Note:

The Timer2 postscaler (see Section 7.1

“Timer2 Operation”) is not used in the

determination of the PWM frequency.

When the 10-bit time base matches the CCPR1H and

2-bit latch, then the CCP1 pin is cleared (see

Figure 11-3).

11.3.2

PWM DUTY CYCLE

11.3.3

PWM RESOLUTION

The PWM duty cycle is specified by writing a 10-bit

value to multiple registers: CCPR1L register and

DC1B<1:0> bits of the CCP1CON register. The

CCPR1L contains the eight MSbs and the DC1B<1:0>

bits of the CCP1CON register contain the two LSbs.

CCPR1L and DC1B<1:0> bits of the CCP1CON

register can be written to at any time. The duty cycle

value is not latched into CCPR1H until after the period

completes (i.e., a match between PR2 and TMR2

registers occurs). While using the PWM, the CCPR1H

register is read-only.

The resolution determines the number of available duty

cycles for a given period. For example, a 10-bit resolution

will result in 1024 discrete duty cycles, whereas an 8-bit

resolution will result in 256 discrete duty cycles.

The maximum PWM resolution is 10 bits when PR2 is

255. The resolution is a function of the PR2 register

value as shown by Equation 11-4.

EQUATION 11-4: PWM RESOLUTION

log[4(PR2 + 1)]

Equation 11-2 is used to calculate the PWM pulse

width.

Resolution = ----------------------------------------- bits

log(2)

Equation 11-3 is used to calculate the PWM duty cycle

ratio.

Note:

If the pulse width value is greater than the

period the assigned PWM pin(s) will

remain unchanged.

TABLE 11-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

PWM Frequency

1.22 kHz

4.88 kHz

19.53 kHz

78.12 kHz

156.3 kHz

208.3 kHz

Timer Prescale (1, 4, 16)

PR2 Value

16

0xFF

10

4

1

0x3F

8

1

0x1F

7

1

0xFF

10

0xFF

10

0x17

6.6

Maximum Resolution (bits)

TABLE 11-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

PWM Frequency

1.22 kHz

4.90 kHz

19.61 kHz

76.92 kHz

153.85 kHz 200.0 kHz

Timer Prescale (1, 4, 16)

PR2 Value

16

0x65

8

4

0x65

8

1

0x65

8

1

0x19

6

1

0x0C

5

1

0x09

5

Maximum Resolution (bits)

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11.3.4

OPERATION IN SLEEP MODE

In Sleep mode, the TMR2 register will not increment

and the state of the module will not change. If the CCP1

pin is driving a value, it will continue to drive that value.

When the device wakes up, TMR2 will continue from its

previous state.

11.3.5

CHANGES IN SYSTEM CLOCK

FREQUENCY

The PWM frequency is derived from the system clock

frequency. Any changes in the system clock frequency

will result in changes to the PWM frequency. See

Section 3.0 “Oscillator Module (With Fail-Safe

Clock Monitor)” for additional details.

11.3.6

EFFECTS OF RESET

Any Reset will force all ports to Input mode and the

CCP registers to their Reset states.

11.3.7

SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

1. Disable the PWM pin (CCP1) output driver by

setting the associated TRIS bit.

2. Set the PWM period by loading the PR2 register.

3. Configure the CCP module for the PWM mode

by loading the CCP1CON register with the

appropriate values.

4. Set the PWM duty cycle by loading the CCPR1L

register and DC1B<1:0> bits of the CCP1CON

register.

5. Configure and start Timer2:

• Clear the TMR2IF interrupt flag bit of the

PIR1 register.

• Set the Timer2 prescale value by loading the

T2CKPS bits of the T2CON register.

• Enable Timer2 by setting the TMR2ON bit of

the T2CON register.

6. Enable PWM output after a new PWM cycle has

started:

• Wait until Timer2 overflows (TMR2IF bit of

the PIR1 register is set).

• Enable the CCP1 pin output driver by clearing

the associated TRIS bit.

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The PWM outputs are multiplexed with I/O pins and are

11.4 PWM (Enhanced Mode)

designated P1A, P1B, P1C and P1D. The polarity of the

PWM pins is configurable and is selected by setting the

CCP1M bits in the CCP1CON register appropriately.

The Enhanced PWM Mode can generate a PWM signal

on up to four different output pins with up to 10-bits of

resolution. It can do this through four different PWM

Output modes:

Table 11-4 shows the pin assignments for each

Enhanced PWM mode.

• Single PWM

Figure 11-5 shows an example of a simplified block

diagram of the Enhanced PWM module.

• Half-Bridge PWM

• Full-Bridge PWM, Forward mode

• Full-Bridge PWM, Reverse mode

Note:

To prevent the generation of an

incomplete waveform when the PWM is

first enabled, the ECCP module waits until

the start of a new PWM period before

generating a PWM signal.

To select an Enhanced PWM mode, the P1M bits of the

CCP1CON register must be set appropriately.

FIGURE 11-5:

EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE

DC1B<1:0>

P1M<1:0>

CCP1M<3:0>

4

Duty Cycle Registers

2

CCPR1L

CCP1/P1A

P1B

TRIS

CCPR1H (Slave)

Comparator

P1B

Output

Controller

R

S

Q

P1C

(1)

TMR2

P1D

Comparator

PR2

Clear Timer2,

toggle PWM pin and

latch duty cycle

PWM1CON

Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit

time base.

Note 1: The TRIS register value for each PWM output must be configured appropriately.

2: Clearing the CCP1CON register will relinquish ECCP control of all PWM output pins.

3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions

TABLE 11-4: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES

ECCP Mode

P1M<1:0>

CCP1/P1A

P1B

P1C

P1D

Single

00

10

01

11

Yes⁽¹⁾

Yes

Yes⁽¹⁾

Yes

Yes⁽¹⁾

No

Yes⁽¹⁾

No

Half-Bridge

Full-Bridge, Forward

Full-Bridge, Reverse

Yes

Note 1: Pulse Steering enables outputs in Single mode.

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FIGURE 11-6:

EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH

STATE)

PR2+1

Pulse

Width

0

Signal

P1M<1:0>

Period

P1A Modulated

(Single Output)

00

10

Delay⁽¹⁾

P1A Modulated

P1B Modulated

P1A Active

(Half-Bridge)

P1B Inactive

(Full-Bridge,

Forward)

01

P1C Inactive

P1D Modulated

P1A Inactive

P1B Modulated

P1C Active

(Full-Bridge,

Reverse)

11

P1D Inactive

Relationships:

•

Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)

Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)

Delay = 4 * TOSC * (PWM1CON<6:0>)

Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 “Programmable Dead-Band Delay

mode”).

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FIGURE 11-7:

EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)

PR2+1

Pulse

Width

0

Signal

P1M<1:0>

Period

P1A Modulated

P1B Modulated

P1A Active

(Single Output)

00

10

Delay⁽¹⁾

(Half-Bridge)

(Full-Bridge,

Forward)

P1B Inactive

P1C Inactive

P1D Modulated

P1A Inactive

P1B Modulated

P1C Active

01

(Full-Bridge,

Reverse)

11

P1D Inactive

Relationships:

•

Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)

Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)

Delay = 4 * TOSC * (PWM1CON<6:0>)

Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 “Programmable Dead-Band Delay

mode”).

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Since the P1A and P1B outputs are multiplexed with

the PORT data latches, the associated TRIS bits must

be cleared to configure P1A and P1B as outputs.

11.4.1

HALF-BRIDGE MODE

In Half-Bridge mode, two pins are used as outputs to

drive push-pull loads. The PWM output signal is output

on the CCP1/P1A pin, while the complementary PWM

output signal is output on the P1B pin (see

Figure 11-6). This mode can be used for Half-Bridge

applications, as shown in Figure 11-9, or for Full-Bridge

applications, where four power switches are being

modulated with two PWM signals.

FIGURE 11-8:

EXAMPLE OF

HALF-BRIDGE PWM

OUTPUT

Period

Pulse Width

In Half-Bridge mode, the programmable dead-band delay

can be used to prevent shoot-through current in

Half-Bridge power devices. The value of the PDC<6:0>

bits of the PWM1CON register sets the number of

instruction cycles before the output is driven active. If the

value is greater than the duty cycle, the corresponding

output remains inactive during the entire cycle. See

Section 11.4.6 “Programmable Dead-Band Delay

mode” for more details of the dead-band delay

operations.

(2)

P1A

td

P1B

(1)

td = Dead-Band Delay

Note 1: At this time, the TMR2 register is equal to the

PR2 register.

2: Output signals are shown as active-high.

FIGURE 11-9:

EXAMPLE OF HALF-BRIDGE APPLICATIONS

Standard Half-Bridge Circuit (“Push-Pull”)

FET

Driver

+

-

P1A

Load

FET

Driver

+

-

P1B

Half-Bridge Output Driving a Full-Bridge Circuit

V+

FET

Driver

FET

Driver

P1A

Load

FET

Driver

P1B

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11.4.2

FULL-BRIDGE MODE

In Full-Bridge mode, all four pins are used as outputs.

An example of Full-Bridge application is shown in

Figure 11-10.

In the Forward mode, pin CCP1/P1A is driven to its active

state, pin P1D is modulated, while P1B and P1C will be

driven to their inactive state as shown in Figure 11-11.

In the Reverse mode, P1C is driven to its active state,

pin P1B is modulated, while P1A and P1D will be driven

to their inactive state as shown Figure 11-11.

P1A, P1B, P1C and P1D outputs are multiplexed with

the PORT data latches. The associated TRIS bits must

be cleared to configure the P1A, P1B, P1C and P1D

pins as outputs.

FIGURE 11-10:

EXAMPLE OF FULL-BRIDGE APPLICATION

V+

QC

QA

FET

Driver

FET

Driver

P1A

P1B

Load

FET

Driver

FET

Driver

P1C

P1D

QD

QB

V-

DS41262D-page 137

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FIGURE 11-11:

EXAMPLE OF FULL-BRIDGE PWM OUTPUT

Forward Mode

Period

(2)

P1A

Pulse Width

(2)

P1B

(2)

P1C

(2)

P1D

(1)

Reverse Mode

Period

Pulse Width

(2)

P1A

(2)

P1B

(2)

P1C

(2)

P1D

(1)

Note 1: At this time, the TMR2 register is equal to the PR2 register.

2: Output signal is shown as active-high.

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The Full-Bridge mode does not provide dead-band

delay. As one output is modulated at a time, dead-band

delay is generally not required. There is a situation

where dead-band delay is required. This situation

occurs when both of the following conditions are true:

11.4.2.1

Direction Change in Full-Bridge

Mode

In the Full-Bridge mode, the P1M1 bit in the CCP1CON

register allows users to control the forward/reverse

direction. When the application firmware changes this

direction control bit, the module will change to the new

direction on the next PWM cycle.

1. The direction of the PWM output changes when

the duty cycle of the output is at or near 100%.

2. The turn off time of the power switch, including

the power device and driver circuit, is greater

than the turn on time.

A direction change is initiated in software by changing

the P1M1 bit of the CCP1CON register. The following

sequence occurs four Timer2 cycles prior to the end of

the current PWM period:

Figure 11-13 shows an example of the PWM direction

changing from forward to reverse, at a near 100% duty

cycle. In this example, at time t1, the output P1A and

P1D become inactive, while output P1C becomes

active. Since the turn off time of the power devices is

longer than the turn on time, a shoot-through current

will flow through power devices QC and QD (see

Figure 11-10) for the duration of ‘t’. The same

phenomenon will occur to power devices QA and QB

for PWM direction change from reverse to forward.

• The modulated outputs (P1B and P1D) are placed

in their inactive state.

• The associated unmodulated outputs (P1A and

P1C) are switched to drive in the opposite

direction.

• PWM modulation resumes at the beginning of the

next period.

See Figure 11-12 for an illustration of this sequence.

If changing PWM direction at high duty cycle is required

for an application, two possible solutions for eliminating

the shoot-through current are:

1. Reduce PWM duty cycle for one PWM period

before changing directions.

2. Use switch drivers that can drive the switches off

faster than they can drive them on.

Other options to prevent shoot-through current may

exist.

FIGURE 11-12:

EXAMPLE OF PWM DIRECTION CHANGE

(1)

Period

Signal

P1A (Active-High)

P1B (Active-High)

Pulse Width

P1C (Active-High)

P1D (Active-High)

(2)

Pulse Width

Note 1: The direction bit P1M1 of the CCP1CON register is written any time during the PWM cycle.

2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The

modulated P1B and P1D signals are inactive at this time. The length of this time is four Timer2 counts.

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FIGURE 11-13:

EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE

Forward Period

Reverse Period

t1

P1A

P1B

PW

P1C

P1D

PW

TON

External Switch C

External Switch D

TOFF

Potential

T = TOFF – TON

Shoot-Through Current

Note 1: All signals are shown as active-high.

2: TON is the turn on delay of power switch QC and its driver.

3: TOFF is the turn off delay of power switch QD and its driver.

11.4.3

START-UP CONSIDERATIONS

When any PWM mode is used, the application

hardware must use the proper external pull-up and/or

pull-down resistors on the PWM output pins.

Note:

When the microcontroller is released from

Reset, all of the I/O pins are in the

high-impedance state. The external cir-

cuits must keep the power switch devices

in the OFF state until the microcontroller

drives the I/O pins with the proper signal

levels or activates the PWM output(s).

The CCP1M<1:0> bits of the CCP1CON register allow

the user to choose whether the PWM output signals are

active-high or active-low for each pair of PWM output pins

(P1A/P1C and P1B/P1D). The PWM output polarities

must be selected before the PWM pin output drivers are

enabled. Changing the polarity configuration while the

PWM pin output drivers are enabled is not recommended

since it may result in damage to the application circuits.

The P1A, P1B, P1C and P1D output latches may not be

in the proper states when the PWM module is

initialized. Enabling the PWM pin output drivers at the

same time as the Enhanced PWM modes may cause

damage to the application circuit. The Enhanced PWM

modes must be enabled in the proper Output mode and

complete a full PWM cycle before enabling the PWM

pin output drivers. The completion of a full PWM cycle

is indicated by the TMR2IF bit of the PIR1 register

being set as the second PWM period begins.

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A shutdown condition is indicated by the ECCPASE

11.4.4

ENHANCED PWM

(Auto-Shutdown Event Status) bit of the ECCPAS

register. If the bit is a ‘0’, the PWM pins are operating

normally. If the bit is a ‘1’, the PWM outputs are in the

shutdown state.

AUTO-SHUTDOWN MODE

The PWM mode supports an Auto-Shutdown mode that

will disable the PWM outputs when an external

shutdown event occurs. Auto-Shutdown mode places

the PWM output pins into a predetermined state. This

mode is used to help prevent the PWM from damaging

the application.

When a shutdown event occurs, two things happen:

The ECCPASE bit is set to ‘1’. The ECCPASE will

remain set until cleared in firmware or an auto-restart

occurs (see Section 11.4.5 “Auto-Restart Mode”).

The auto-shutdown sources are selected using the

ECCPASx bits of the ECCPAS register. A shutdown

event may be generated by:

The enabled PWM pins are asynchronously placed in

their shutdown states. The PWM output pins are

grouped into pairs [P1A/P1C] and [P1B/P1D]. The state

of each pin pair is determined by the PSSAC and

PSSBD bits of the ECCPAS register. Each pin pair may

be placed into one of three states:

• A logic ‘0’ on the INT pin

• Comparator C1

• Comparator C2

• Setting the ECCPASE bit in firmware

• Drive logic ‘1’

• Drive logic ‘0’

• Tri-state (high-impedance)

REGISTER 11-2: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN

CONTROL REGISTER

U-0

R/W-0

ECCPASE

ECCPAS2

ECCPAS1

ECCPAS0

PSSAC1

PSSAC0

PSSBD1

PSSBD0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

ECCPASE: ECCP Auto-Shutdown Event Status bit

1= A shutdown event has occurred; ECCP outputs are in shutdown state

0= ECCP outputs are operating

bit 6-4

ECCPAS<2:0>: ECCP Auto-shutdown Source Select bits

000= Auto-Shutdown is disabled

001= Comparator C1 output change

010= Comparator C2 output change⁽¹⁾

011= Either Comparator C1 or C2 change

100= VIL on INT pin

101= VIL on INT pin or Comparator C1 change

110= VIL on INT pin or Comparator C2 change

111= VIL on INT pin or Comparator C1 or C2 change

bit 3-2

bit 1-0

PSSACn: Pins P1A and P1C Shutdown State Control bits

00= Drive pins P1A and P1C to ‘0’

01= Drive pins P1A and P1C to ‘1’

1x= Pins P1A and P1C tri-state

PSSBDn: Pins P1B and P1D Shutdown State Control bits

00= Drive pins P1B and P1D to ‘0’

01= Drive pins P1B and P1D to ‘1’

1x= Pins P1B and P1D tri-state

Note 1: If C2SYNC is enabled, the shutdown will be delayed by Timer1.

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Note 1: The auto-shutdown condition is

a

level-based signal, not an edge-based

signal. As long as the level is present, the

auto-shutdown will persist.

2: Writing to the ECCPASE bit is disabled

while an auto-shutdown condition

persists.

3: Once the auto-shutdown condition has

been removed and the PWM restarted

(either through firmware or auto-restart)

the PWM signal will always restart at the

beginning of the next PWM period.

FIGURE 11-14:

PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0)

PWM Period

Shutdown Event

ECCPASE bit

PWM Activity

Normal PWM

ECCPASE

Cleared by

Firmware

Start of

Shutdown

PWM

PWM Period

Event Occurs Event Clears

Resumes

11.4.5

AUTO-RESTART MODE

The Enhanced PWM can be configured to automati-

cally restart the PWM signal once the auto-shutdown

condition has been removed. Auto-restart is enabled by

setting the PRSEN bit in the PWM1CON register.

If auto-restart is enabled, the ECCPASE bit will remain

set as long as the auto-shutdown condition is active.

When the auto-shutdown condition is removed, the

ECCPASE bit will be cleared via hardware and normal

operation will resume.

FIGURE 11-15:

PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1)

PWM Period

Shutdown Event

ECCPASE bit

PWM Activity

Normal PWM

Start of

PWM Period

Shutdown

Event Occurs Event Clears

Shutdown

PWM

Resumes

DS41262D-page 142

PIC16F631/677/685/687/689/690

11.4.6

PROGRAMMABLE DEAD-BAND

DELAY MODE

FIGURE 11-16:

EXAMPLE OF

HALF-BRIDGE PWM

OUTPUT

In Half-Bridge applications where all power switches

are modulated at the PWM frequency, the power

switches normally require more time to turn off than to

turn on. If both the upper and lower power switches are

switched at the same time (one turned on, and the

other turned off), both switches may be on for a short

period of time until one switch completely turns off.

Period

Pulse Width

(2)

P1A

td

During this brief interval,

a very high current

P1B

(shoot-through current) will flow through both power

switches, shorting the bridge supply. To avoid this

potentially destructive shoot-through current from

flowing during switching, turning on either of the power

switches is normally delayed to allow the other switch

to completely turn off.

(1)

td = Dead-Band Delay

Note 1: At this time, the TMR2 register is equal to the

PR2 register.

In Half-Bridge mode,

a

digitally programmable

2: Output signals are shown as active-high.

dead-band delay is available to avoid shoot-through

current from destroying the bridge power switches. The

delay occurs at the signal transition from the non-active

state to the active state. See Figure 11-8 for illustration.

The lower seven bits of the associated PWM1CON

register (Register 11-3) sets the delay period in terms

of microcontroller instruction cycles (TCY or 4 TOSC).

FIGURE 11-17:

EXAMPLE OF HALF-BRIDGE APPLICATIONS

V+

Standard Half-Bridge Circuit (“Push-Pull”)

FET

Driver

+

V

-

P1A

Load

FET

Driver

+

V

-

P1B

V-

DS41262D-page 143

PIC16F631/677/685/687/689/690

REGISTER 11-3: PWM1CON: ENHANCED PWM CONTROL REGISTER

R/W-0

PDC6

R/W-0

PDC5

R/W-0

PDC4

R/W-0

PDC3

R/W-0

PDC2

R/W-0

PDC1

R/W-0

PDC0

PRSEN

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

PRSEN: PWM Restart Enable bit

1= Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes

away; the PWM restarts automatically

0= Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM

bit 6-0

PDC<6:0>: PWM Delay Count bits

PDCn = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal

should transition active and the actual time it transitions active

Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe

mode is enabled.

DS41262D-page 144

PIC16F631/677/685/687/689/690

11.4.7

PULSE STEERING MODE

In Single Output mode, pulse steering allows any of the

PWM pins to be the modulated signal. Additionally, the

same PWM signal can be simultaneously available on

multiple pins.

Note:

The associated TRIS bits must be set to

output (‘0’) to enable the pin output driver

in order to see the PWM signal on the pin.

While the PWM Steering mode is active, CCP1M<1:0>

bits of the CCP1CON register select the PWM output

polarity for the P1<D:A> pins.

Once the Single Output mode is selected

(CCP1M<3:2> = 11 and P1M<1:0> = 00 of the

CCP1CON register), the user firmware can bring out

the same PWM signal to one, two, three or four output

pins by setting the appropriate STR<D:A> bits of the

PSTRCON register, as shown in Figure 11-18.

The PWM auto-shutdown operation also applies to

PWM Steering mode as described in Section 11.4.4

“Enhanced PWM Auto-shutdown mode”. An

auto-shutdown event will only affect pins that have

PWM outputs enabled.

REGISTER 11-4: PSTRCON: PULSE STEERING CONTROL REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

R/W-0

STRD

R/W-0

STRC

R/W-0

STRB

R/W-1

STRA

STRSYNC

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-5

bit 4

Unimplemented: Read as ‘0’

STRSYNC: Steering Sync bit

1= Output steering update occurs on next PWM period

0= Output steering update occurs at the beginning of the instruction cycle boundary

bit 3

bit 2

bit 1

bit 0

STRD: Steering Enable bit D

1= P1D pin has the PWM waveform with polarity control from CCP1M<1:0>

0= P1D pin is assigned to port pin

STRC: Steering Enable bit C

1= P1C pin has the PWM waveform with polarity control from CCP1M<1:0>

0= P1C pin is assigned to port pin

STRB: Steering Enable bit B

1= P1B pin has the PWM waveform with polarity control from CCP1M<1:0>

0 = P1B pin is assigned to port pin

STRA: Steering Enable bit A

1= P1A pin has the PWM waveform with polarity control from CCP1M<1:0>

0= P1A pin is assigned to port pin

Note 1: The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2> = 11and

P1M<1:0> = 00.

DS41262D-page 145

PIC16F631/677/685/687/689/690

FIGURE 11-18:

SIMPLIFIED STEERING

BLOCK DIAGRAM

STRA

P1A Signal

CCP1M1

P1A pin

1

PORT Data

STRB

0

TRIS

P1B pin

CCP1M0

1

PORT Data

STRC

0

TRIS

P1C pin

1

CCP1M1

PORT Data

0

TRIS

STRD

P1D pin

1

CCP1M0

PORT Data

0

TRIS

Note 1: Port outputs are configured as shown when

the CCP1CON register bits P1M<1:0> = 00

and CCP1M<3:2> = 11.

2: Single PWM output requires setting at least

one of the STRx bits.

DS41262D-page 146

PIC16F631/677/685/687/689/690

Figures 11-19 and 11-20 illustrate the timing diagrams

of the PWM steering depending on the STRSYNC

setting.

11.4.7.1

Steering Synchronization

The STRSYNC bit of the PSTRCON register gives the

user two selections of when the steering event will

happen. When the STRSYNC bit is ‘0’, the steering

event will happen at the end of the instruction that

writes to the PSTRCON register. In this case, the

output signal at the P1<D:A> pins may be an

incomplete PWM waveform. This operation is useful

when the user firmware needs to immediately remove

a PWM signal from the pin.

When the STRSYNC bit is ‘1’, the effective steering

update will happen at the beginning of the next PWM

period. In this case, steering on/off the PWM output will

always produce a complete PWM waveform.

FIGURE 11-19:

EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0)

PWM Period

PWM

STRn

P1<D:A>

PORT Data

P1n = PWM

FIGURE 11-20:

EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION

(STRSYNC = 1)

PWM

STRn

P1<D:A>

PORT Data

P1n = PWM

DS41262D-page 147

PIC16F631/677/685/687/689/690

TABLE 11-5: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND PWM

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

CCP1CON

CM1CON0

CM2CON0

P1M1

C1ON

C2ON

P1M0

C1OUT

C2OUT

DC1B1

C1OE

C2OE

—

DC1B0

C1POL

C2POL

—

CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000

—

C1R

C2R

—

C1CH1

C2CH1

C1CH0 0000 -000 0000 -000

C2CH0 0000 -000 0000 -000

CM2CON1 MC1OUT MC2OUT

T1GSS C2SYNC 00-- --10 00-- --10

xxxx xxxx uuuu uuuu

CCPR1L

CCPR1H

ECCPAS

INTCON

PIE1

Capture/Compare/PWM Register 1 Low Byte

Capture/Compare/PWM Register 1 High Byte

xxxx xxxx uuuu uuuu

ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000

GIE

—

PEIE

ADIE

ADIF

—

T0IE

RCIE

RCIF

—

INTE

TXIE

RABIE

SSPIE

SSPIF

STRD

PDC3

T0IF

INTF

RABIF

0000 0000 0000 0000

CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

PIR1

—

TXIF

PSTRCON

—

STRSYNC

PDC4

STRC

PDC2

STRB

PDC1

STRA

PDC0

---0 0001 ---0 0001

0000 0000 0000 0000

0000 0000 uuuu uuuu

PWM1CON PRSEN

PDC6

PDC5

T1CON

T2CON

TMR1L

TMR1H

TMR2

T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

Timer2 Module Register

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

TRISC

TRISC7

TRISC6

TRISC5

TRISC4

TRISC3

TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

Legend: – = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the Capture,

Compare and PWM.

DS41262D-page 148

PIC16F631/677/685/687/689/690

The EUSART module includes the following capabilities:

12.0 ENHANCED UNIVERSAL

• Full-duplex asynchronous transmit and receive

• Two-character input buffer

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (EUSART)

• One-character output buffer

• Programmable 8-bit or 9-bit character length

• Address detection in 9-bit mode

The Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) module is a serial I/O

communications peripheral. It contains all the clock

generators, shift registers and data buffers necessary

to perform an input or output serial data transfer

independent of device program execution. The

EUSART, also known as a Serial Communications

Interface (SCI), can be configured as a full-duplex

asynchronous system or half-duplex synchronous

• Input buffer overrun error detection

• Received character framing error detection

• Half-duplex synchronous master

• Half-duplex synchronous slave

• Programmable clock polarity in synchronous

modes

The EUSART module implements the following

additional features, making it ideally suited for use in

Local Interconnect Network (LIN) bus systems:

system.

Full-Duplex

mode

is

useful

for

communications with peripheral systems, such as CRT

terminals and personal computers. Half-Duplex

Synchronous mode is intended for communications

with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs or other microcontrollers.

These devices typically do not have internal clocks for

baud rate generation and require the external clock

signal provided by a master synchronous device.

• Automatic detection and calibration of the baud rate

• Wake-up on Break reception

• 13-bit Break character transmit

Block diagrams of the EUSART transmitter and

receiver are shown in Figure 12-1 and Figure 12-2.

FIGURE 12-1:

EUSART TRANSMIT BLOCK DIAGRAM

Data Bus

TXIE

Interrupt

TXIF

TXREG Register

8

TX/CK pin

MSb

(8)

LSb

0

Pin Buffer

and Control

• • •

Transmit Shift Register (TSR)

TXEN

TRMT

SPEN

Baud Rate Generator

BRG16

FOSC

÷ n

TX9

n

+ 1

Multiplier x4

x16 x64

TX9D

SYNC

BRGH

BRG16

1

X

1

0

1

0

1

0

SPBRGH

SPBRG

DS41262D-page 149

PIC16F631/677/685/687/689/690

FIGURE 12-2:

EUSART RECEIVE BLOCK DIAGRAM

SPEN

CREN

OERR

RCIDL

RX/DT pin

RSR Register

MSb

Stop (8)

LSb

Start

Pin Buffer

and Control

Data

Recovery

7

1

0

• • •

Baud Rate Generator

FOSC

RX9

÷ n

BRG16

n

+ 1

Multiplier

x4

x16 x64

SYNC

BRGH

BRG16

1

X

1

0

1

0

1

0

FIFO

SPBRGH

SPBRG

X

RX9D

FERR

RCREG Register

8

Data Bus

RCIF

RCIE

Interrupt

The operation of the EUSART module is controlled

through three registers:

• Transmit Status and Control (TXSTA)

• Receive Status and Control (RCSTA)

• Baud Rate Control (BAUDCTL)

These registers are detailed in Register 12-1,

Register 12-2 and Register 12-3, respectively.

DS41262D-page 150

PIC16F631/677/685/687/689/690

12.1 EUSART Asynchronous Mode

Note 1: When the SPEN bit is set, the RX/DT I/O

pin is automatically configured as an input,

regardless of the state of the corresponding

TRIS bit and whether or not the EUSART

receiver is enabled. The RX/DT pin data

can be read via a normal PORT read but

PORT latch data output is precluded.

The EUSART transmits and receives data using the

standard non-return-to-zero (NRZ) format. NRZ is

implemented with two levels: a VOH mark state which

represents a ‘1’ data bit, and a VOL space state which

represents a ‘0’ data bit. NRZ refers to the fact that

consecutively transmitted data bits of the same value

stay at the output level of that bit without returning to a

neutral level between each bit transmission. An NRZ

transmission port idles in the mark state. Each character

transmission consists of one Start bit followed by eight

or nine data bits and is always terminated by one or

more Stop bits. The Start bit is always a space and the

Stop bits are always marks. The most common data

format is 8 bits. Each transmitted bit persists for a period

of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud

Rate Generator is used to derive standard baud rate

frequencies from the system oscillator. See Table 12-5

for examples of baud rate configurations.

2: The TXIF transmitter interrupt flag is set

when the TXEN enable bit is set.

12.1.1.2

Transmitting Data

A transmission is initiated by writing a character to the

TXREG register. If this is the first character, or the

previous character has been completely flushed from

the TSR, the data in the TXREG is immediately

transferred to the TSR register. If the TSR still contains

all or part of a previous character, the new character

data is held in the TXREG until the Stop bit of the

previous character has been transmitted. The pending

character in the TXREG is then transferred to the TSR

in one TCY immediately following the Stop bit

transmission. The transmission of the Start bit, data bits

and Stop bit sequence commences immediately

following the transfer of the data to the TSR from the

TXREG.

The EUSART transmits and receives the LSb first. The

EUSART’s transmitter and receiver are functionally

independent, but share the same data format and baud

rate. Parity is not supported by the hardware, but can

be implemented in software and stored as the ninth

data bit.

12.1.1

EUSART ASYNCHRONOUS

TRANSMITTER

12.1.1.3

Transmit Interrupt Flag

The EUSART transmitter block diagram is shown in

Figure 12-1. The heart of the transmitter is the serial

Transmit Shift Register (TSR), which is not directly

accessible by software. The TSR obtains its data from

the transmit buffer, which is the TXREG register.

The TXIF interrupt flag bit of the PIR1 register is set

whenever the EUSART transmitter is enabled and no

character is being held for transmission in the TXREG.

In other words, the TXIF bit is only clear when the TSR

is busy with a character and a new character has been

queued for transmission in the TXREG. The TXIF flag bit

is not cleared immediately upon writing TXREG. TXIF

becomes valid in the second instruction cycle following

the write execution. Polling TXIF immediately following

the TXREG write will return invalid results. The TXIF bit

is read-only, it cannot be set or cleared by software.

12.1.1.1

Enabling the Transmitter

The EUSART transmitter is enabled for asynchronous

operations by configuring the following three control

bits:

• TXEN = 1

• SYNC = 0

• SPEN = 1

The TXIF interrupt can be enabled by setting the TXIE

interrupt enable bit of the PIE1 register. However, the

TXIF flag bit will be set whenever the TXREG is empty,

regardless of the state of TXIE enable bit.

All other EUSART control bits are assumed to be in

their default state.

To use interrupts when transmitting data, set the TXIE

bit only when there is more data to send. Clear the

TXIE interrupt enable bit upon writing the last character

of the transmission to the TXREG.

Setting the TXEN bit of the TXSTA register enables the

transmitter circuitry of the EUSART. Clearing the SYNC

bit of the TXSTA register configures the EUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTA register enables the EUSART and automatically

configures the TX/CK I/O pin as an output. If the TX/CK

pin is shared with an analog peripheral the analog I/O

function must be disabled by clearing the corresponding

ANSEL bit.

DS41262D-page 151

PIC16F631/677/685/687/689/690

12.1.1.4

TSR Status

12.1.1.6

Asynchronous Transmission Set-up:

The TRMT bit of the TXSTA register indicates the

status of the TSR register. This is a read-only bit. The

TRMT bit is set when the TSR register is empty and is

cleared when a character is transferred to the TSR

register from the TXREG. The TRMT bit remains clear

until all bits have been shifted out of the TSR register.

No interrupt logic is tied to this bit, so the user has to

poll this bit to determine the TSR status.

1. Initialize the SPBRGH, SPBRG register pair and

the BRGH and BRG16 bits to achieve the desired

baud rate (see Section 12.3 “EUSART Baud

Rate Generator (BRG)”).

2. Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

3. If 9-bit transmission is desired, set the TX9 con-

trol bit. A set ninth data bit will indicate that the 8

Least Significant data bits are an address when

the receiver is set for address detection.

Note:

The TSR register is not mapped in data

memory, so it is not available to the user.

4. Enable the transmission by setting the TXEN

control bit. This will cause the TXIF interrupt bit

to be set.

12.1.1.5

Transmitting 9-Bit Characters

The EUSART supports 9-bit character transmissions.

When the TX9 bit of the TXSTA register is set the

EUSART will shift 9 bits out for each character transmit-

ted. The TX9D bit of the TXSTA register is the ninth,

and Most Significant, data bit. When transmitting 9-bit

data, the TX9D data bit must be written before writing

the 8 Least Significant bits into the TXREG. All nine bits

of data will be transferred to the TSR shift register

immediately after the TXREG is written.

5. If interrupts are desired, set the TXIE interrupt

enable bit. An interrupt will occur immediately

provided that the GIE and PEIE bits of the

INTCON register are also set.

6. If 9-bit transmission is selected, the ninth bit

should be loaded into the TX9D data bit.

7. Load 8-bit data into the TXREG register. This

will start the transmission.

A special 9-bit Address mode is available for use with

multiple receivers. See Section 12.1.2.7 “Address

Detection” for more information on the Address mode.

FIGURE 12-3:

ASYNCHRONOUS TRANSMISSION

Write to TXREG

Word 1

BRG Output

(Shift Clock)

RC4/C2OUT/TX/CK

Start bit

bit 0

bit 1

Word 1

bit 7/8

Stop bit

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

1 TCY

Word 1

Transmit Shift Reg

TRMT bit

(Transmit Shift

Reg. Empty Flag)

FIGURE 12-4:

ASYNCHRONOUS TRANSMISSION (BACK TO BACK)

Write to TXREG

Word 2

Start bit

Word 1

BRG Output

(Shift Clock)

RC4/C2OUT/TX/CK

Start bit

Word 2

bit 0

bit 1

bit 7/8

bit 0

Stop bit

1 TCY

Word 1

TXIF bit

(Interrupt Reg. Flag)

1 TCY

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1

Transmit Shift Reg.

Word 2

Transmit Shift Reg.

Note:

This timing diagram shows two consecutive transmissions.

DS41262D-page 152

PIC16F631/677/685/687/689/690

TABLE 12-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

BAUDCTL ABDOVF RCIDL

—

SCKP

INTE

TXIE

TXIF

BRG16

RABIE

SSPIE

SSPIF

—

WUE

INTF

ABDEN 01-0 0-00 01-0 0-00

RABIF 0000 000x 0000 000x

INTCON

PIE1

GIE

—

PEIE

ADIE

ADIF

T0IE

RCIE

RCIF

T0IF

CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

0000 0000 0000 0000

PIR1

—

RCREG

RCSTA

SPBRG

SPBRGH

TRISB

EUSART Receive Data Register

SPEN

BRG7

BRG15

RX9

BRG6

BRG14

SREN

BRG5

CREN

BRG4

ADDEN

BRG3

FERR

BRG2

OERR

BRG1

BRG9

RX9D

BRG0

BRG8

0000 000x 0000 000x

0000 0000 0000 0000

1111 ---- 1111 ----

0000 0000 0000 0000

0000 0010 0000 0010

BRG13

BRG12

BRG11

BRG10

TRISB7 TRISB6 TRISB5 TRISB4

EUSART Transmit Data Register

TXREG

TXSTA

Legend:

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

x= unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Transmission.

DS41262D-page 153

PIC16F631/677/685/687/689/690

12.1.2

EUSART ASYNCHRONOUS

RECEIVER

12.1.2.2

Receiving Data

The receiver data recovery circuit initiates character

reception on the falling edge of the first bit. The first bit,

also known as the Start bit, is always a zero. The data

recovery circuit counts one-half bit time to the center of

the Start bit and verifies that the bit is still a zero. If it is

not a zero then the data recovery circuit aborts

character reception, without generating an error, and

resumes looking for the falling edge of the Start bit. If

the Start bit zero verification succeeds then the data

recovery circuit counts a full bit time to the center of the

next bit. The bit is then sampled by a majority detect

circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.

This repeats until all data bits have been sampled and

shifted into the RSR. One final bit time is measured and

the level sampled. This is the Stop bit, which is always

a ‘1’. If the data recovery circuit samples a ‘0’ in the

Stop bit position then a framing error is set for this

character, otherwise the framing error is cleared for this

character. See Section 12.1.2.4 “Receive Framing

Error” for more information on framing errors.

The Asynchronous mode would typically be used in

RS-232 systems. The receiver block diagram is shown

in Figure 12-2. The data is received on the RX/DT pin

and drives the data recovery block. The data recovery

block is actually a high-speed shifter operating at 16

times the baud rate, whereas the serial Receive Shift

Register (RSR) operates at the bit rate. When all 8 or 9

bits of the character have been shifted in, they are

immediately transferred to

a

two character

First-In-First-Out (FIFO) memory. The FIFO buffering

allows reception of two complete characters and the

start of a third character before software must start

servicing the EUSART receiver. The FIFO and RSR

registers are not directly accessible by software.

Access to the received data is via the RCREG register.

12.1.2.1

Enabling the Receiver

The EUSART receiver is enabled for asynchronous

operation by configuring the following three control bits:

Immediately after all data bits and the Stop bit have

been received, the character in the RSR is transferred

to the EUSART receive FIFO and the RCIF interrupt

flag bit of the PIR1 register is set. The top character in

the FIFO is transferred out of the FIFO by reading the

RCREG register.

• CREN = 1

• SYNC = 0

• SPEN = 1

All other EUSART control bits are assumed to be in

their default state.

Setting the CREN bit of the RCSTA register enables the

receiver circuitry of the EUSART. Clearing the SYNC bit

of the TXSTA register configures the EUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTA register enables the EUSART and automatically

configures the RX/DT I/O pin as an input. If the RX/DT

pin is shared with an analog peripheral the analog I/O

function must be disabled by clearing the corresponding

ANSEL bit.

Note:

If the receive FIFO is overrun, no additional

characters will be received until the overrun

condition is cleared. See Section 12.1.2.5

“Receive Overrun Error” for more

information on overrun errors.

12.1.2.3

Receive Interrupts

The RCIF interrupt flag bit of the PIR1 register is set

whenever the EUSART receiver is enabled and there is

an unread character in the receive FIFO. The RCIF

interrupt flag bit is read-only, it cannot be set or cleared

by software.

Note:

When the SPEN bit is set the TX/CK I/O

pin is automatically configured as an

output, regardless of the state of the

corresponding TRIS bit and whether or not

the EUSART transmitter is enabled. The

PORT latch is disconnected from the

output driver so it is not possible to use the

TX/CK pin as a general purpose output.

RCIF interrupts are enabled by setting the following

bits:

• RCIE interrupt enable bit of the PIE1 register

• PEIE peripheral interrupt enable bit of the

INTCON register

• GIE global interrupt enable bit of the INTCON

register

The RCIF interrupt flag bit will be set when there is an

unread character in the FIFO, regardless of the state of

interrupt enable bits.

DS41262D-page 154

PIC16F631/677/685/687/689/690

12.1.2.4

Receive Framing Error

12.1.2.7

Address Detection

Each character in the receive FIFO buffer has a

corresponding framing error status bit. A framing error

indicates that a Stop bit was not seen at the expected

time. The framing error status is accessed via the

FERR bit of the RCSTA register. The FERR bit

represents the status of the top unread character in the

receive FIFO. Therefore, the FERR bit must be read

before reading the RCREG.

A special Address Detection mode is available for use

when multiple receivers share the same transmission

line, such as in RS-485 systems. Address detection is

enabled by setting the ADDEN bit of the RCSTA

register.

Address detection requires 9-bit character reception.

When address detection is enabled, only characters

with the ninth data bit set will be transferred to the

receive FIFO buffer, thereby setting the RCIF interrupt

bit. All other characters will be ignored.

The FERR bit is read-only and only applies to the top

unread character in the receive FIFO. A framing error

(FERR = 1) does not preclude reception of additional

characters. It is not necessary to clear the FERR bit.

Reading the next character from the FIFO buffer will

advance the FIFO to the next character and the next

corresponding framing error.

Upon receiving an address character, user software

determines if the address matches its own. Upon

address match, user software must disable address

detection by clearing the ADDEN bit before the next

Stop bit occurs. When user software detects the end of

the message, determined by the message protocol

used, software places the receiver back into the

Address Detection mode by setting the ADDEN bit.

The FERR bit can be forced clear by clearing the SPEN

bit of the RCSTA register which resets the EUSART.

Clearing the CREN bit of the RCSTA register does not

affect the FERR bit. A framing error by itself does not

generate an interrupt.

Note:

If all receive characters in the receive

FIFO have framing errors, repeated reads

of the RCREG will not clear the FERR bit.

12.1.2.5

Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated If a third character, in its

entirety, is received before the FIFO is accessed. When

this happens the OERR bit of the RCSTA register is set.

The characters already in the FIFO buffer can be read

but no additional characters will be received until the

error is cleared. The error must be cleared by either

clearing the CREN bit of the RCSTA register or by

resetting the EUSART by clearing the SPEN bit of the

RCSTA register.

12.1.2.6

Receiving 9-bit Characters

The EUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set the EUSART

will shift 9 bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth and Most Significant data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the 8 Least Significant bits from

the RCREG.

DS41262D-page 155

PIC16F631/677/685/687/689/690

12.1.2.8

Asynchronous Reception Set-up:

12.1.2.9

9-bit Address Detection Mode Set-up

1. Initialize the SPBRGH, SPBRG register pair and

the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 12.3 “EUSART

Baud Rate Generator (BRG)”).

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

1. Initialize the SPBRGH, SPBRG register pair and

the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 12.3 “EUSART

Baud Rate Generator (BRG)”).

2. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

3. If interrupts are desired, set the RCIE interrupt

enable bit and set the GIE and PEIE bits of the

INTCON register.

2. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

4. If 9-bit reception is desired, set the RX9 bit.

5. Enable reception by setting the CREN bit.

3. If interrupts are desired, set the RCIE interrupt

enable bit and set the GIE and PEIE bits of the

INTCON register.

6. The RCIF interrupt flag bit will be set when a

character is transferred from the receive shift

register to the receive buffer. An interrupt will be

generated if the RCIE interrupt enable bit was

also set.

4. Enable 9-bit reception by setting the RX9 bit.

5. Enable address detection by setting the ADDEN

bit.

6. Enable reception by setting the CREN bit.

7. Read the RCSTA register to get the error flags

and, if 9-bit data reception is enabled, the ninth

data bit.

7. The RCIF interrupt flag bit will be set when a

character with the ninth bit set is transferred

from the receive shift register to the receive

buffer. An interrupt will be generated if the RCIE

interrupt enable bit was also set.

8. Get the received 8 Least Significant data bits

from the receive buffer by reading the RCREG

register.

8. Read the RCSTA register to get the error flags.

The ninth data bit will always be set.

9. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

9. Get the received 8 Least Significant data bits

from the receive buffer by reading the RCREG

register. Software determines if this is the

device’s address.

10. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

11. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and generate interrupts.

FIGURE 12-5:

ASYNCHRONOUS RECEPTION

Start

bit

Start

bit

Start

bit

RX/DT pin

bit 7/8

bit 0 bit 1

Stop

bit

Stop

bit

Stop

bit

bit 0

bit 7/8

Rcv Shift

Reg

Rcv Buffer Reg

Word 2

RCREG

Word 1

RCREG

RCIDL

Read Rcv

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Note:

This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,

causing the OERR (overrun) bit to be set.

DS41262D-page 156

PIC16F631/677/685/687/689/690

TABLE 12-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCTL ABDOVF RCIDL

—

SCKP

INTE

TXIE

TXIF

BRG16

RABIE

SSPIE

SSPIF

—

WUE

INTF

ABDEN 01-0 0-00 01-0 0-00

RABIF 0000 000x 0000 000x

INTCON

PIE1

GIE

—

PEIE

ADIE

ADIF

T0IE

RCIE

RCIF

T0IF

CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

0000 0000 0000 0000

PIR1

—

RCREG

RCSTA

SPBRG

SPBRGH

TRISB

EUSART Receive Data Register

SPEN

BRG7

BRG15

RX9

BRG6

BRG14

SREN

BRG5

CREN

BRG4

ADDEN

BRG3

FERR

BRG2

OERR

BRG1

BRG9

RX9D

BRG0

BRG8

0000 000x 0000 000x

0000 0000 0000 0000

1111 ---- 1111 ----

0000 0000 0000 0000

0000 0010 0000 0010

BRG13

BRG12

BRG11

BRG10

TRISB7 TRISB6 TRISB5 TRISB4

EUSART Transmit Data Register

TXREG

TXSTA

Legend:

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

x= unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Reception.

DS41262D-page 157

PIC16F631/677/685/687/689/690

The first (preferred) method uses the OSCTUNE

12.2 Clock Accuracy with

Asynchronous Operation

register to adjust the INTOSC output. Adjusting the

value in the OSCTUNE register allows for fine resolution

changes to the system clock source. See Section 3.5

“Internal Clock Modes” for more information.

The factory calibrates the internal oscillator block out-

put (INTOSC). However, the INTOSC frequency may

drift as VDD or temperature changes, and this directly

affects the asynchronous baud rate. Two methods may

be used to adjust the baud rate clock, but both require

a reference clock source of some kind.

The other method adjusts the value in the Baud Rate

Generator. This can be done automatically with the

Auto-Baud Detect feature (see Section 12.3.1

“Auto-Baud Detect”). There may not be fine enough

resolution when adjusting the Baud Rate Generator to

compensate for a gradual change in the peripheral

clock frequency.

REGISTER 12-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-0

CSRC

R/W-0

TX9

R/W-0

SYNC

R/W-0

BRGH

R-1

R/W-0

TX9D

(1)

TXEN

SENDB

TRMT

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care

Synchronous mode:

1= Master mode (clock generated internally from BRG)

0= Slave mode (clock from external source)

bit 6

bit 5

bit 4

bit 3

TX9: 9-bit Transmit Enable bit

1= Selects 9-bit transmission

0= Selects 8-bit transmission

(1)

TXEN: Transmit Enable bit

1= Transmit enabled

0= Transmit disabled

SYNC: EUSART Mode Select bit

1= Synchronous mode

0= Asynchronous mode

SENDB: Send Break Character bit

Asynchronous mode:

1= Send Sync Break on next transmission (cleared by hardware upon completion)

0= Sync Break transmission completed

Synchronous mode:

Don’t care

bit 2

BRGH: High Baud Rate Select bit

Asynchronous mode:

1= High speed

0= Low speed

Synchronous mode:

Unused in this mode

bit 1

bit 0

TRMT: Transmit Shift Register Status bit

1= TSR empty

0= TSR full

TX9D: Ninth bit of Transmit Data

Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode.

DS41262D-page 158

PIC16F631/677/685/687/689/690

REGISTER 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER⁽¹⁾

R/W-0

SPEN

R/W-0

RX9

R/W-0

SREN

R/W-0

CREN

R/W-0

R-0

R-x

ADDEN

FERR

OERR

RX9D

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

SPEN: Serial Port Enable bit

1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

0= Serial port disabled (held in Reset)

RX9: 9-bit Receive Enable bit

1= Selects 9-bit reception

0= Selects 8-bit reception

SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode – Master:

1= Enables single receive

0= Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave

Don’t care

bit 4

CREN: Continuous Receive Enable bit

Asynchronous mode:

1= Enables receiver

0= Disables receiver

Synchronous mode:

1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0= Disables continuous receive

bit 3

ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1= Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set

0= Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 8-bit (RX9 = 0):

Don’t care

bit 2

bit 1

bit 0

FERR: Framing Error bit

1= Framing error (can be updated by reading RCREG register and receive next valid byte)

0= No framing error

OERR: Overrun Error bit

1= Overrun error (can be cleared by clearing bit CREN)

0= No overrun error

RX9D: Ninth bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.

DS41262D-page 159

PIC16F631/677/685/687/689/690

REGISTER 12-3: BAUDCTL: BAUD RATE CONTROL REGISTER

R-0

R-1

U-0

—

R/W-0

SCKP

R/W-0

U-0

—

R/W-0

WUE

R/W-0

ABDOVF

RCIDL

BRG16

ABDEN

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:

1= Auto-baud timer overflowed

0= Auto-baud timer did not overflow

Synchronous mode:

Don’t care

RCIDL: Receive Idle Flag bit

Asynchronous mode:

1= Receiver is Idle

0= Start bit has been received and the receiver is receiving

Synchronous mode:

Don’t care

bit 5

bit 4

Unimplemented: Read as ‘0’

SCKP: Synchronous Clock Polarity Select bit

Asynchronous mode:

1= Transmit inverted data to the RB7/TX/CK pin

0= Transmit non-inverted data to the RB7/TX/CK pin

Synchronous mode:

1= Data is clocked on rising edge of the clock

0= Data is clocked on falling edge of the clock

bit 3

BRG16: 16-bit Baud Rate Generator bit

1= 16-bit Baud Rate Generator is used

0= 8-bit Baud Rate Generator is used

bit 2

bit 1

Unimplemented: Read as ‘0’

WUE: Wake-up Enable bit

Asynchronous mode:

1= Receiver is waiting for a falling edge. No character will be received byte RCIF will be set. WUE will

automatically clear after RCIF is set.

0= Receiver is operating normally

Synchronous mode:

Don’t care

bit 0

ABDEN: Auto-Baud Detect Enable bit

Asynchronous mode:

1= Auto-Baud Detect mode is enabled (clears when auto-baud is complete)

0= Auto-Baud Detect mode is disabled

Synchronous mode:

Don’t care

DS41262D-page 160

PIC16F631/677/685/687/689/690

If the system clock is changed during an active receive

12.3 EUSART Baud Rate Generator

operation, a receive error or data loss may result. To

avoid this problem, check the status of the RCIDL bit to

make sure that the receive operation is Idle before

changing the system clock.

(BRG)

The Baud Rate Generator (BRG) is an 8-bit or 16-bit

timer that is dedicated to the support of both the

asynchronous and synchronous EUSART operation.

By default, the BRG operates in 8-bit mode. Setting the

BRG16 bit of the BAUDCTL register selects 16-bit

mode.

EXAMPLE 12-1:

CALCULATING BAUD

RATE ERROR

For a device with FOSC of 16 MHz, desired baud rate

of 9600, Asynchronous mode, 8-bit BRG:

The SPBRGH, SPBRG register pair determines the

period of the free running baud rate timer. In

Asynchronous mode the multiplier of the baud rate

period is determined by both the BRGH bit of the TXSTA

register and the BRG16 bit of the BAUDCTL register. In

Synchronous mode, the BRGH bit is ignored.

FOSC

--------------------------------------------------------------------

=

Desired Baud Rate

64([SPBRGH:SPBRG] + 1)

Solving for SPBRGH:SPBRG:

FOSC

---------------------------------------------

Table 12-3 contains the formulas for determining the

baud rate. Example 12-1 provides a sample calculation

for determining the baud rate and baud rate error.

Desired Baud Rate

---------------------------------------------

X =

=

– 1

64

16000000

-----------------------

9600

64

Typical baud rates and error values for various

asynchronous modes have been computed for your

convenience and are shown in Table 12-3. It may be

advantageous to use the high baud rate (BRGH = 1),

or the 16-bit BRG (BRG16 = 1) to reduce the baud rate

error. The 16-bit BRG mode is used to achieve slow

baud rates for fast oscillator frequencies.

-----------------------

– 1

= [25.042] = 25

16000000

64(25 + 1)

--------------------------

=

Calculated Baud Rate

= 9615

Writing a new value to the SPBRGH, SPBRG register

pair causes the BRG timer to be reset (or cleared). This

ensures that the BRG does not wait for a timer overflow

before outputting the new baud rate.

Calc. Baud Rate – Desired Baud Rate

--------------------------------------------------------------------------------------------

Error =

Desired Baud Rate

(9615 – 9600)

----------------------------------

=

= 0.16%

9600

TABLE 12-3: BAUD RATE FORMULAS

Configuration Bits

Baud Rate Formula

BRG/EUSART Mode

SYNC

BRG16

BRGH

0

1

0

1

0

1

0

1

0

1

x

8-bit/Asynchronous

16-bit/Asynchronous

8-bit/Synchronous

16-bit/Synchronous

FOSC/[64 (n+1)]

FOSC/[16 (n+1)]

FOSC/[4 (n+1)]

Legend:

x= Don’t care, n = value of SPBRGH, SPBRG register pair

TABLE 12-4: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCTL ABDOVF RCIDL

—

SCKP

CREN

BRG4

BRG12

SYNC

BRG16

ADDEN

BRG3

—

WUE

OERR

BRG1

BRG9

TRMT

ABDEN 01-0 0-00 01-0 0-00

RCSTA

SPBRG

SPBRGH

TXSTA

SPEN

BRG7

BRG15

CSRC

RX9

BRG6

BRG14

TX9

SREN

BRG5

BRG13

TXEN

FERR

BRG2

BRG10

BRGH

RX9D

BRG0

BRG8

TX9D

0000 000x 0000 000x

0000 0000 0000 0000

0000 0010 0000 0010

BRG11

SENDB

Legend:

x= unknown, – = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator.

DS41262D-page 161

PIC16F631/677/685/687/689/690

TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 20.000 MHz

FOSC = 18.432 MHz

FOSC = 11.0592 MHz

FOSC = 8.000 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

300

1200

—

255

129

32

—

239

119

29

—

143

71

17

16

8

—

1202

2404

9615

10417

—

0.16

0.00

—

103

51

12

11

1221

2404

9470

10417

19.53k

1.73

0.16

-1.36

0.00

1.73

1200

2400

9600

10286

19.20k

0.00

-1.26

0.00

—

1200

2400

9600

10165

19.20k

0.00

-2.42

0.00

—

2400

9600

10417

19.2k

57.6k

115.2k

29

27

15

14

—

2

—

57.60k

—

7

57.60k

—

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 3.6864 MHz FOSC = 2.000 MHz

FOSC = 4.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

0.00

—

300

1200

300

1202

2404

—

0.16

—

207

51

25

—

5

300

1200

2400

9600

—

191

47

23

5

300

1202

2404

—

0.16

—

103

25

12

—

2

300

1202

—

0.16

—

51

12

—

2400

9600

—

10417

19.2k

57.6k

115.2k

10417

—

0.00

—

2

10417

—

0.00

—

19.20k

0.00

—

0

—

57.60k

—

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 18.432 MHz FOSC = 11.0592 MHz

FOSC = 20.000 MHz

FOSC = 8.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

—

300

1200

2400

9600

10417

19.2k

57.6k

—

2404

9615

10417

19231

55556

—

0.16

0.00

0.16

-3.55

—

207

51

47

25

8

—

71

65

35

11

5

9615

10417

19.23k

56.82k

0.16

0.00

0.16

-1.36

129

119

64

9600

10378

19.20k

57.60k

115.2k

0.00

-0.37

0.00

119

110

59

19

9

9600

0.00

0.53

0.00

10473

19.20k

57.60k

115.2k

21

115.2k 113.64k -1.36

10

—

DS41262D-page 162

PIC16F631/677/685/687/689/690

TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 3.6864 MHz FOSC = 2.000 MHz

FOSC = 4.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

300

1200

—

1202

2404

9615

10417

19.23k

—

207

103

25

—

191

95

23

21

11

3

—

1202

2404

9615

10417

—

0.16

0.00

—

103

51

12

11

300

1202

2404

—

0.16

—

207

51

25

—

5

0.16

0.00

0.16

—

1200

0.00

0.53

0.00

2400

9600

10417

19.2k

57.6k

115.2k

23

10473

19.2k

57.60k

115.2k

10417

—

0.00

—

12

—

1

—

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 18.432 MHz FOSC = 11.0592 MHz

FOSC = 20.000 MHz

FOSC = 8.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

300

1200

2400

9600

10417

19.2k

57.6k

300.0

1200

-0.01

-0.03

0.16

0.00

0.16

-1.36

4166

1041

520

129

119

64

300.0

1200

0.00

-0.37

0.00

3839

959

479

119

110

59

300.0

1200

0.00

0.53

0.00

2303

575

287

71

299.9

1199

2404

9615

10417

19.23k

55556

—

-0.02

-0.08

0.16

0.00

0.16

-3.55

—

1666

416

207

51

2399

2400

9615

9600

10417

19.23k

56.818

10378

19.20k

57.60k

115.2k

10473

19.20k

57.60k

115.2k

65

47

35

25

21

19

11

8

115.2k 113.636 -1.36

10

9

5

—

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 3.6864 MHz FOSC = 2.000 MHz

FOSC = 4.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

Error

(decimal)

300

1200

300.1

1202

2404

9615

10417

19.23k

—

0.04

0.16

0.00

0.16

—

832

207

103

25

300.0

1200

0.00

0.53

0.00

767

191

95

23

21

11

3

299.8

1202

2404

9615

10417

—

-0.108

0.16

0.00

—

416

103

51

12

11

300.5

1202

2404

—

0.16

—

207

51

25

—

5

2400

9600

10417

19.2k

57.6k

115.2k

23

10473

19.20k

57.60k

115.2k

10417

—

0.00

—

12

—

1

—

DS41262D-page 163

PIC16F631/677/685/687/689/690

TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 20.000 MHz

FOSC = 18.432 MHz

FOSC = 11.0592 MHz

FOSC = 8.000 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

300

1200

300.0

1200

0.00

-0.01

0.02

-0.03

0.00

0.16

-0.22

0.94

16665

4166

2082

520

479

259

86

300.0

1200

0.00

0.08

0.00

15359

3839

1919

479

441

239

79

300.0

1200

0.00

0.16

0.00

9215

2303

1151

287

264

143

47

300.0

1200

0.00

-0.02

0.04

0.16

0

6666

1666

832

207

191

103

34

2400

2401

9600

9597

9600

9615

10417

19.2k

57.6k

115.2k

10417

19.23k

57.47k

116.3k

10425

19.20k

57.60k

115.2k

10433

19.20k

57.60k

115.2k

10417

19.23k

57.14k

117.6k

0.16

-0.79

2.12

42

39

23

16

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 3.6864 MHz FOSC = 2.000 MHz

FOSC = 4.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

300

1200

300.0

1200

0.01

0.04

0.08

0.16

0.00

0.16

2.12

-3.55

3332

832

416

103

95

300.0

1200

0.00

0.53

0.00

3071

767

383

95

299.9

1199

-0.02

-0.08

0.16

0.00

0.16

-3.55

—

1666

416

207

51

300.1

1202

2404

9615

10417

19.23k

—

0.04

0.16

0.00

0.16

—

832

207

103

25

2400

2398

2400

2404

9615

10417

19.23k

55.56k

—

9600

9615

9600

10417

19.2k

57.6k

115.2k

10417

19.23k

58.82k

111.1k

10473

19.20k

57.60k

115.2k

87

47

23

51

47

25

12

16

15

8

—

8

7

—

DS41262D-page 164

PIC16F631/677/685/687/689/690

and SPBRG registers are clocked at 1/8th the BRG

base clock rate. The resulting byte measurement is the

average bit time when clocked at full speed.

12.3.1

AUTO-BAUD DETECT

The EUSART module supports automatic detection

and calibration of the baud rate.

Note 1: If the WUE bit is set with the ABDEN bit,

auto-baud detection will occur on the byte

following the Break character (see

In the Auto-Baud Detect (ABD) mode, the clock to the

BRG is reversed. Rather than the BRG clocking the

incoming RX signal, the RX signal is timing the BRG.

The Baud Rate Generator is used to time the period of

a received 55h (ASCII “U”) which is the Sync character

for the LIN bus. The unique feature of this character is

that it has five rising edges including the Stop bit edge.

Section 12.3.2

“Auto-Wake-up

on

Break”).

2: It is up to the user to determine that the

incoming character baud rate is within the

range of the selected BRG clock source.

Some combinations of oscillator frequency

and EUSART baud rates are not possible.

Setting the ABDEN bit of the BAUDCTL register starts

the auto-baud calibration sequence (Figure 12-6).

While the ABD sequence takes place, the EUSART

state machine is held in Idle. On the first rising edge of

the receive line, after the Start bit, the SPBRG begins

counting up using the BRG counter clock as shown in

Table 12-6. The fifth rising edge will occur on the RX

pin at the end of the eighth bit period. At that time, an

accumulated value totaling the proper BRG period is

left in the SPBRGH, SPBRG register pair, the ABDEN

bit is automatically cleared and the RCIF interrupt flag

is set. The value in the RCREG needs to be read to

clear the RCIF interrupt. RCREG content should be

discarded. When calibrating for modes that do not use

the SPBRGH register the user can verify that the

SPBRG register did not overflow by checking for 00h in

the SPBRGH register.

3: During the auto-baud process, the

auto-baud counter starts counting at 1.

Upon completion of the auto-baud

sequence,

accuracy,

to

achieve

maximum

from the

subtract

1

SPBRGH:SPBRG register pair.

TABLE 12-6:

BRG COUNTER CLOCK RATES

BRG Base

Clock

BRG ABD

Clock

BRG16 BRGH

0

1

FOSC/64

FOSC/16

FOSC/512

FOSC/128

1

0

1

FOSC/16

FOSC/4

FOSC/128

FOSC/32

The BRG auto-baud clock is determined by the BRG16

and BRGH bits as shown in Table 12-6. During ABD,

both the SPBRGH and SPBRG registers are used as a

16-bit counter, independent of the BRG16 bit setting.

While calibrating the baud rate period, the SPBRGH

Note:

During the ABD sequence, SPBRG and

SPBRGH registers are both used as a 16-bit

counter, independent of BRG16 setting.

FIGURE 12-6:

AUTOMATIC BAUD RATE CALIBRATION

XXXXh

0000h

001Ch

BRG Value

Edge #1

bit 1

Edge #2

bit 3

Edge #3

bit 5

Edge #4

bit 7

bit 6

Edge #5

Stop bit

RX pin

Start

bit 0

bit 2

bit 4

BRG Clock

Auto Cleared

Set by User

ABDEN bit

RCIDL

RCIF bit

(Interrupt)

Read

RCREG

XXh

1Ch

00h

SPBRG

SPBRGH

Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.

DS41262D-page 165

PIC16F631/677/685/687/689/690

12.3.2

AUTO-WAKE-UP ON BREAK

12.3.2.1

Special Considerations

During Sleep mode, all clocks to the EUSART are

suspended. Because of this, the Baud Rate Generator

is inactive and a proper character reception cannot be

performed. The Auto-Wake-up feature allows the

controller to wake-up due to activity on the RX/DT line.

This feature is available only in Asynchronous mode.

Break Character

To avoid character errors or character fragments during

a wake-up event, the wake-up character must be all

zeros.

When the wake-up is enabled the function works

independent of the low time on the data stream. If the

WUE bit is set and a valid non-zero character is

received, the low time from the Start bit to the first rising

edge will be interpreted as the wake-up event. The

remaining bits in the character will be received as a

fragmented character and subsequent characters can

result in framing or overrun errors.

The Auto-Wake-up feature is enabled by setting the

WUE bit of the BAUDCTL register. Once set, the normal

receive sequence on RX/DT is disabled, and the

EUSART remains in an Idle state, monitoring for a

wake-up event independent of the CPU mode. A

wake-up event consists of a high-to-low transition on the

RX/DT line. (This coincides with the start of a Sync Break

or a wake-up signal character for the LIN protocol.)

Therefore, the initial character in the transmission must

be all ‘0’s. This must be 10 or more bit times, 13-bit

times recommended for LIN bus, or any number of bit

times for standard RS-232 devices.

The EUSART module generates an RCIF interrupt

coincident with the wake-up event. The interrupt is

generated synchronously to the Q clocks in normal CPU

operating modes (Figure 12-7), and asynchronously if

the device is in Sleep mode (Figure 12-8). The interrupt

condition is cleared by reading the RCREG register.

Oscillator Startup Time

Oscillator start-up time must be considered, especially

in applications using oscillators with longer start-up

intervals (i.e., LP, XT or HS/PLL mode). The Sync

Break (or wake-up signal) character must be of

sufficient length, and be followed by a sufficient

interval, to allow enough time for the selected oscillator

to start and provide proper initialization of the EUSART.

The WUE bit is automatically cleared by the low-to-high

transition on the RX line at the end of the Break. This

signals to the user that the Break event is over. At this

point, the EUSART module is in Idle mode waiting to

receive the next character.

WUE Bit

The wake-up event causes a receive interrupt by

setting the RCIF bit. The WUE bit is cleared in

hardware by a rising edge on RX/DT. The interrupt

condition is then cleared in software by reading the

RCREG register and discarding its contents.

To ensure that no actual data is lost, check the RCIDL

bit to verify that a receive operation is not in process

before setting the WUE bit. If a receive operation is not

occurring, the WUE bit may then be set just prior to

entering the Sleep mode.

FIGURE 12-7:

AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3Q4

OSC1

Auto Cleared

Bit set by user

WUE bit

RX/DT Line

RCIF

Cleared due to User Read of RCREG

Note 1: The EUSART remains in Idle while the WUE bit is set.

DS41262D-page 166

PIC16F631/677/685/687/689/690

FIGURE 12-8:

AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q4

Q1Q2Q3 Q4 Q1Q2 Q3Q4 Q1Q2Q3

Q1

Q2 Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4

Auto Cleared

OSC1

Bit Set by User

WUE bit

RX/DT Line

Note 1

RCIF

Cleared due to User Read of RCREG

Sleep Command Executed

Sleep Ends

Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposcsignal is

still active. This sequence should not depend on the presence of Q clocks.

2: The EUSART remains in Idle while the WUE bit is set.

12.3.3

BREAK CHARACTER SEQUENCE

12.3.4

RECEIVING A BREAK CHARACTER

The EUSART module has the capability of sending the

special Break character sequences that are required by

the LIN bus standard. A Break character consists of a

Start bit, followed by 12 ‘0’ bits and a Stop bit.

The Enhanced EUSART module can receive a Break

character in two ways.

The first method to detect a Break character uses the

FERR bit of the RCSTA register and the Received data

as indicated by RCREG. The Baud Rate Generator is

assumed to have been initialized to the expected baud

rate.

To send a Break character, set the SENDB and TXEN

bits of the TXSTA register. The Break character trans-

mission is then initiated by a write to the TXREG. The

value of data written to TXREG will be ignored and all

‘0’s will be transmitted.

A Break character has been received when;

• RCIF bit is set

• FERR bit is set

• RCREG = 00h

The SENDB bit is automatically reset by hardware after

the corresponding Stop bit is sent. This allows the user

to preload the transmit FIFO with the next transmit byte

following the Break character (typically, the Sync

character in the LIN specification).

The second method uses the Auto-Wake-up feature

described in Section 12.3.2 “Auto-Wake-up on

Break”. By enabling this feature, the EUSART will

sample the next two transitions on RX/DT, cause an

RCIF interrupt, and receive the next data byte followed

by another interrupt.

The TRMT bit of the TXSTA register indicates when the

transmit operation is active or Idle, just as it does during

normal transmission. See Figure 12-9 for the timing of

the Break character sequence.

Note that following a Break character, the user will

typically want to enable the Auto-Baud Detect feature.

For both methods, the user can set the ABDEN bit of

the BAUDCTL register before placing the EUSART in

Sleep mode.

12.3.3.1

Break and Sync Transmit Sequence

The following sequence will start a message frame

header made up of a Break, followed by an auto-baud

Sync byte. This sequence is typical of a LIN bus

master.

1. Configure the EUSART for the desired mode.

2. Set the TXEN and SENDB bits to enable the

Break sequence.

3. Load the TXREG with a dummy character to

initiate transmission (the value is ignored).

4. Write ‘55h’ to TXREG to load the Sync character

into the transmit FIFO buffer.

5. After the Break has been sent, the SENDB bit is

reset by hardware and the Sync character is

then transmitted.

When the TXREG becomes empty, as indicated by the

TXIF, the next data byte can be written to TXREG.

DS41262D-page 167

PIC16F631/677/685/687/689/690

FIGURE 12-9:

SEND BREAK CHARACTER SEQUENCE

Write to TXREG

Dummy Write

BRG Output

(Shift Clock)

TX (pin)

Start bit

bit 0

bit 1

Break

bit 11

Stop bit

TXIF bit

(Transmit

interrupt Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

SENDB Sampled Here

Auto Cleared

SENDB

(send Break

control bit)

DS41262D-page 168

PIC16F631/677/685/687/689/690

the clock Idle state as high. When the SCKP bit is set,

12.4 EUSART Synchronous Mode

the data changes on the falling edge of each clock.

Clearing the SCKP bit sets the Idle state as low. When

the SCKP bit is cleared, the data changes on the rising

edge of each clock.

Synchronous serial communications are typically used

in systems with a single master and one or more

slaves. The master device contains the necessary cir-

cuitry for baud rate generation and supplies the clock

for all devices in the system. Slave devices can take

advantage of the master clock by eliminating the

internal clock generation circuitry.

12.4.1.3

Synchronous Master Transmission

Data is transferred out of the device on the RX/DT pin.

The RX/DT and TX/CK pin output drivers are automat-

ically enabled when the EUSART is configured for

synchronous master transmit operation.

There are two signal lines in Synchronous mode: a bidi-

rectional data line and a clock line. Slaves use the

external clock supplied by the master to shift the serial

data into and out of their respective receive and trans-

mit shift registers. Since the data line is bidirectional,

synchronous operation is half-duplex only. Half-duplex

refers to the fact that master and slave devices can

receive and transmit data but not both simultaneously.

The EUSART can operate as either a master or slave

device.

A transmission is initiated by writing a character to the

TXREG register. If the TSR still contains all or part of a

previous character the new character data is held in the

TXREG until the last bit of the previous character has

been transmitted. If this is the first character, or the pre-

vious character has been completely flushed from the

TSR, the data in the TXREG is immediately transferred

to the TSR. The transmission of the character

commences immediately following the transfer of the

data to the TSR from the TXREG.

Start and Stop bits are not used in synchronous

transmissions.

Each data bit changes on the leading edge of the

master clock and remains valid until the subsequent

leading clock edge.

12.4.1

SYNCHRONOUS MASTER MODE

The following bits are used to configure the EUSART

for Synchronous Master operation:

Note:

The TSR register is not mapped in data

memory, so it is not available to the user.

• SYNC = 1

• CSRC = 1

12.4.1.4

Synchronous Master Transmission

Set-up:

• SREN = 0(for transmit); SREN = 1(for receive)

• CREN = 0(for transmit); CREN = 1(for receive)

• SPEN = 1

1. Initialize the SPBRGH, SPBRG register pair and

the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 12.3 “EUSART

Baud Rate Generator (BRG)”).

Setting the SYNC bit of the TXSTA register configures

the device for synchronous operation. Setting the CSRC

bit of the TXSTA register configures the device as a

master. Clearing the SREN and CREN bits of the RCSTA

register ensures that the device is in the Transmit mode,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

EUSART. If the RX/DT or TX/CK pins are shared with an

analog peripheral the analog I/O functions must be

disabled by clearing the corresponding ANSEL bits.

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. Disable Receive mode by clearing bits SREN

and CREN.

4. Enable Transmit mode by setting the TXEN bit.

5. If 9-bit transmission is desired, set the TX9 bit.

6. If interrupts are desired, set the TXIE, GIE and

PEIE interrupt enable bits.

12.4.1.1

Master Clock

7. If 9-bit transmission is selected, the ninth bit

should be loaded in the TX9D bit.

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device config-

ured as a master transmits the clock on the TX/CK line.

The TX/CK pin is automatically configured as an output

when the EUSART is configured for synchronous

transmit operation. Serial data bits change on the lead-

ing edge to ensure they are valid at the trailing edge of

each clock. One clock cycle is generated for each data

bit. Only as many clock cycles are generated as there

are data bits.

8. Start transmission by loading data to the TXREG

register.

12.4.1.2

Clock Polarity

A clock polarity option is provided for Microwire

compatability. Clock polarity is selected with the SCKP

bit of the BAUDCTL register. Setting the SCKP bit sets

DS41262D-page 169

PIC16F631/677/685/687/689/690

FIGURE 12-10:

SYNCHRONOUS TRANSMISSION

RX/DT

bit 0

bit 1

bit 2

bit 7

bit 0

bit 1

Word 2

bit 7

Word 1

TX/CK pin

(SCKP = 0)

TX/CK pin

(SCKP = 1)

Write to

TXREG Reg

Write Word 1

Write Word 2

TXIF bit

(Interrupt Flag)

TRMT bit

‘1’

TXEN bit

Note:

Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.

FIGURE 12-11:

SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RX/DT pin

bit 0

bit 2

bit 1

bit 6

bit 7

TX/CK pin

Write to

TXREG reg

TXIF bit

TRMT bit

TXEN bit

TABLE 12-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCTL ABDOVF RCIDL

—

SCKP

INTE

TXIE

TXIF

BRG16

RABIE

SSPIE

SSPIF

—

WUE

INTF

ABDEN 01-0 0-00 01-0 0-00

RABIF 0000 000x 0000 000x

INTCON

PIE1

GIE

—

PEIE

ADIE

ADIF

T0IE

RCIE

RCIF

T0IF

CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

0000 0000 0000 0000

PIR1

—

RCREG

RCSTA

SPBRG

SPBRGH

TRISB

EUSART Receive Data Register

SPEN

BRG7

BRG15

RX9

BRG6

BRG14

SREN

BRG5

CREN

BRG4

ADDEN

BRG3

FERR

BRG2

OERR

BRG1

BRG9

RX9D

BRG0

BRG8

0000 000x 0000 000x

0000 0000 0000 0000

1111 ---- 1111 ----

0000 0000 0000 0000

0000 0010 0000 0010

BRG13

BRG12

BRG11

BRG10

TRISB7 TRISB6 TRISB5 TRISB4

EUSART Transmit Data Register

TXREG

TXSTA

Legend:

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

x= unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Transmission.

DS41262D-page 170

PIC16F631/677/685/687/689/690

12.4.1.5

Synchronous Master Reception

12.4.1.8

Synchronous Master Reception

Set-up:

Data is received at the RX/DT pin. The RX/DT and

TX/CK pin output drivers are automatically disabled

when the EUSART is configured for synchronous

master receive operation.

1. Initialize the SPBRGH, SPBRG register pair for

the appropriate baud rate. Set or clear the

BRGH and BRG16 bits, as required, to achieve

the desired baud rate.

In Synchronous mode, reception is enabled by setting

either the Single Receive Enable bit (SREN of the

RCSTA register) or the Continuous Receive Enable bit

(CREN of the RCSTA register).

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. Ensure bits CREN and SREN are clear.

4. If using interrupts, set the GIE and PEIE bits of

the INTCON register and set RCIE.

When SREN is set and CREN is clear, only as many

clock cycles are generated as there are data bits in a

single character. The SREN bit is automatically cleared

at the completion of one character. When CREN is set,

clocks are continuously generated until CREN is

cleared. If CREN is cleared in the middle of a character

the CK clock stops immediately and the partial charac-

ter is discarded. If SREN and CREN are both set, then

SREN is cleared at the completion of the first character

and CREN takes precedence.

5. If 9-bit reception is desired, set bit RX9.

6. Start reception by setting the SREN bit or for

continuous reception, set the CREN bit.

7. Interrupt flag bit RCIF will be set when reception

of a character is complete. An interrupt will be

generated if the enable bit RCIE was set.

8. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

To initiate reception, set either SREN or CREN. Data is

sampled at the RX/DT pin on the trailing edge of the

TX/CK clock pin and is shifted into the Receive Shift

9. Read the 8-bit received data by reading the

RCREG register.

Register (RSR). When

a complete character is

10. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

register or by clearing the SPEN bit which resets

the EUSART.

received into the RSR, the RCIF bit is set and the char-

acter is automatically transferred to the two character

receive FIFO. The Least Significant eight bits of the top

character in the receive FIFO are available in RCREG.

The RCIF bit remains set as long as there are un-read

characters in the receive FIFO.

12.4.1.6

Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its

entirety, is received before RCREG is read to access

the FIFO. When this happens the OERR bit of the

RCSTA register is set. Previous data in the FIFO will

not be overwritten. The two characters in the FIFO

buffer can be read, however, no additional characters

will be received until the error is cleared. The OERR bit

can only be cleared by clearing the overrun condition.

If the overrun error occurred when the SREN bit is set

and CREN is clear then the error is cleared by reading

RCREG. If the overrun occurred when the CREN bit is

set then the error condition is cleared by either clearing

the CREN bit of the RCSTA register or by clearing the

SPEN bit which resets the EUSART.

12.4.1.7

Receiving 9-bit Characters

The EUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set the EUSART

will shift 9-bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth, and Most Significant, data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the 8 Least Significant bits from

the RCREG.

DS41262D-page 171

PIC16F631/677/685/687/689/690

FIGURE 12-12:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

RX/DT

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

TX/CK pin

(SCKP = 0)

TX/CK pin

(SCKP = 1)

Write to

bit SREN

SREN bit

‘0’

CREN bit

RCIF bit

(Interrupt)

Read

RXREG

Note:

Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.

TABLE 12-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCTL ABDOVF RCIDL

—

SCKP

INTE

TXIE

TXIF

BRG16

RABIE

SSPIE

SSPIF

—

WUE

INTF

ABDEN 01-0 0-00 01-0 0-00

RABIF 0000 000x 0000 000x

INTCON

PIE1

GIE

—

PEIE

ADIE

ADIF

T0IE

RCIE

RCIF

T0IF

CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

0000 0000 0000 0000

PIR1

—

RCREG

RCSTA

SPBRG

SPBRGH

TRISB

EUSART Receive Data Register

SPEN

BRG7

BRG15

RX9

BRG6

BRG14

SREN

BRG5

CREN

BRG4

ADDEN

BRG3

FERR

BRG2

OERR

BRG1

BRG9

RX9D

BRG0

BRG8

0000 000x 0000 000x

0000 0000 0000 0000

1111 ---- 1111 ----

0000 0000 0000 0000

0000 0010 0000 0010

BRG13

BRG12

BRG11

BRG10

TRISB7 TRISB6 TRISB5 TRISB4

EUSART Transmit Data Register

TXREG

TXSTA

Legend:

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

x= unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.

DS41262D-page 172

PIC16F631/677/685/687/689/690

If two words are written to the TXREG and then the

SLEEPinstruction is executed, the following will occur:

12.4.2

SYNCHRONOUS SLAVE MODE

The following bits are used to configure the EUSART

for Synchronous slave operation:

1. The first character will immediately transfer to

the TSR register and transmit.

• SYNC = 1

2. The second word will remain in TXREG register.

3. The TXIF bit will not be set.

• CSRC = 0

• SREN = 0(for transmit); SREN = 1(for receive)

• CREN = 0(for transmit); CREN = 1(for receive)

• SPEN = 1

4. After the first character has been shifted out of

TSR, the TXREG register will transfer the second

character to the TSR and the TXIF bit will now be

set.

Setting the SYNC bit of the TXSTA register configures the

device for synchronous operation. Clearing the CSRC bit

of the TXSTA register configures the device as a slave.

Clearing the SREN and CREN bits of the RCSTA register

ensures that the device is in the Transmit mode,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

EUSART. If the RX/DT or TX/CK pins are shared with an

analog peripheral the analog I/O functions must be

disabled by clearing the corresponding ANSEL bits.

5. If the PEIE and TXIE bits are set, the interrupt

will wake the device from Sleep and execute the

next instruction. If the GIE bit is also set, the

program will call the interrupt service routine.

12.4.2.2

Synchronous Slave Transmission

Set-up:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. Clear the CREN and SREN bits.

12.4.2.1

EUSART Synchronous Slave

Transmit

3. If using interrupts, ensure that the GIE and PEIE

bits of the INTCON register are set and set the

TXIE bit.

The operation of the Synchronous Master and Slave

modes are identical (see Section 12.4.1.3

“Synchronous Master Transmission”), except in the

4. If 9-bit transmission is desired, set the TX9 bit.

5. Enable transmission by setting the TXEN bit.

case of the Sleep mode.

6. If 9-bit transmission is selected, insert the Most

Significant bit into the TX9D bit.

7. Start transmission by writing the Least

Significant 8 bits to the TXREG register.

TABLE 12-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCTL ABDOVF RCIDL

—

SCKP

INTE

TXIE

TXIF

BRG16

RABIE

SSPIE

SSPIF

—

WUE

INTF

ABDEN 01-0 0-00 01-0 0-00

RABIF 0000 000x 0000 000x

INTCON

PIE1

GIE

—

PEIE

ADIE

ADIF

T0IE

RCIE

RCIF

T0IF

CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

0000 0000 0000 0000

PIR1

—

RCREG

RCSTA

SPBRG

SPBRGH

TRISB

EUSART Receive Data Register

SPEN

BRG7

BRG15

RX9

BRG6

BRG14

SREN

BRG5

CREN

BRG4

ADDEN

BRG3

FERR

BRG2

BRG10

OERR

BRG1

BRG9

RX9D

BRG0

BRG8

0000 000x 0000 000x

0000 0000 0000 0000

1111 ---- 1111 ----

0000 0000 0000 0000

0000 0010 0000 0010

BRG13

BRG12

BRG11

TRISB7 TRISB6 TRISB5 TRISB4

EUSART Transmit Data Register

TXREG

TXSTA

Legend:

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

x= unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.

DS41262D-page 173

PIC16F631/677/685/687/689/690

12.4.2.3

EUSART Synchronous Slave

Reception

12.4.2.4

Synchronous Slave Reception

Set-up:

The operation of the Synchronous Master and Slave

modes is identical (Section 12.4.1.5 “Synchronous

Master Reception”), with the following exceptions:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. If using interrupts, ensure that the GIE and PEIE

bits of the INTCON register are set and set the

RCIE bit.

• Sleep

• CREN bit is always set, therefore the receiver is

never Idle

3. If 9-bit reception is desired, set the RX9 bit.

4. Set the CREN bit to enable reception.

• SREN bit, which is a “don't care” in Slave mode

5. The RCIF bit will be set when reception is

complete. An interrupt will be generated if the

RCIE bit was set.

A character may be received while in Sleep mode by

setting the CREN bit prior to entering Sleep. Once the

word is received, the RSR register will transfer the data

to the RCREG register. If the RCIE enable bit is set, the

interrupt generated will wake the device from Sleep

and execute the next instruction. If the GIE bit is also

set, the program will branch to the interrupt vector.

6. If 9-bit mode is enabled, retrieve the Most

Significant bit from the RX9D bit of the RCSTA

register.

7. Retrieve the 8 Least Significant bits from the

receive FIFO by reading the RCREG register.

8. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

register or by clearing the SPEN bit which resets

the EUSART.

TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCTL ABDOVF RCIDL

—

SCKP

INTE

TXIE

TXIF

BRG16

RABIE

SSPIE

SSPIF

—

WUE

INTF

ABDEN 01-0 0-00 01-0 0-00

RABIF 0000 000x 0000 000x

INTCON

PIE1

GIE

—

PEIE

ADIE

ADIF

T0IE

RCIE

RCIF

T0IF

CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

0000 0000 0000 0000

PIR1

—

RCREG

RCSTA

SPBRG

SPBRGH

TRISB

EUSART Receive Data Register

SPEN

BRG7

BRG15

RX9

BRG6

BRG14

SREN

BRG5

CREN

BRG4

ADDEN

BRG3

FERR

BRG2

BRG10

OERR

BRG1

BRG9

RX9D

BRG0

BRG8

0000 000x 0000 000x

0000 0000 0000 0000

1111 ---- 1111 ----

0000 0000 0000 0000

0000 0010 0000 0010

BRG13

BRG12

BRG11

TRISB7 TRISB6 TRISB5 TRISB4

EUSART Transmit Data Register

TXREG

TXSTA

Legend:

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

x= unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.

DS41262D-page 174

PIC16F631/677/685/687/689/690

FIGURE 13-1:

SSP BLOCK DIAGRAM

(SPI MODE)

13.0 SSP MODULE OVERVIEW

The Synchronous Serial Port (SSP) module is a serial

interface used to communicate with other peripheral or

microcontroller devices. These peripheral devices

may be serial EEPROMs, shift registers, display

drivers, A/D converters, etc. The SSP module can

operate in one of two modes:

Internal

Data Bus

Read

Write

SSPBUF Reg

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I²C™)

Refer to Application Note AN578, “Use of the SSP

Module in the Multi-Master Environment” (DS00578).

SSPSR Reg

SDI/SDA

SDO

Shift

Clock

bit 0

13.1 SPI Mode

Peripheral OE

This section contains register definitions and operational

characteristics of the SPI module.

Control

Enable

SS

The SPI mode allows 8 bits of data to be synchronously

transmitted and received simultaneously. To accomplish

communication, typically three pins are used:

SS

Edge

Select

• Serial Data Out (SDO)

• Serial Data In (SDI)

• Serial Clock (SCK)

2

Clock Select

Additionally, a fourth pin may be used when in a Slave

mode of operation:

SSPM<3:0>

4

TMR2 Output

2

• Slave Select (SS)

Edge

Note 1: When the SPI is in Slave mode with SS

pin control enabled (SSPM<3:0> bits of

the SSPCON register = 0100), the SPI

module will reset if the SS pin is set to

VDD.

Select

TCY

Prescaler

4, 16, 64

SCK/

SCL

TRISB<6>

2: If the SPI is used in Slave mode with

CKE = 1, then the SS pin control must be

enabled.

3: When the SPI is in Slave mode with SS

pin control enabled (SSPM<3:0> bits of

the SSPCON register = 0100), the state

of the SS pin can affect the state read

back from the TRISC<4> bit. The

peripheral OE signal from the SSP

module into PORTC controls the state that

is read back from the TRISC<4> bit (see

Section 17.0

“Electrical

Specifications” for information on

PORTC). If read-write-modify instructions,

such as BSF, are performed on the

TRISC register while the SS pin is high,

this will cause the TRISC<7> bit to be set,

thus disabling the SDO output.

DS41262D-page 175

PIC16F631/677/685/687/689/690

REGISTER 13-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER⁽¹⁾

R/W-0

SMP

R/W-0

CKE

R-0

D/A

R-0

P

R-0

S

R-0

UA

R-0

BF

R/W

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

SMP: SPI Data Input Sample Phase bit

SPI Master mode:

1= Input data sampled at end of data output time

0= Input data sampled at middle of data output time (Microwire)

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode

2

I C™ mode:

This bit must be maintained clear

bit 6

CKE: SPI Clock Edge Select bit

SPI mode, CKP = 0:

1= Data transmitted on rising edge of SCK (Microwire alternate)

0= Data transmitted on falling edge of SCK

SPI mode, CKP = 1:

1= Data transmitted on falling edge of SCK (Microwire default)

0= Data transmitted on rising edge of SCK

2

I C mode:

This bit must be maintained clear

2

bit 5

bit 4

D/A: DATA/ADDRESS bit (I C mode only)

1= Indicates that the last byte received or transmitted was data

0= Indicates that the last byte received or transmitted was address

2

P: Stop bit (I C mode only)

This bit is cleared when the SSP module is disabled, or when the Start bit is detected last.

SSPEN is cleared.

1= Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)

0= Stop bit was not detected last

2

bit 3

bit 2

S: Start bit (I C mode only)

This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last.

SSPEN is cleared.

1= Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)

0= Start bit was not detected last

2

R/W: READ/WRITE bit Information (I C mode only)

This bit holds the R/W bit information following the last address match. This bit is only valid from the address match

to the next Start bit, Stop bit or ACK bit.

1= Read

0= Write

2

bit 1

bit 0

UA: Update Address bit (10-bit I C mode only)

1= Indicates that the user needs to update the address in the SSPADD register

0= Address does not need to be updated

BF: Buffer Full Status bit

2

Receive (SPI and I C modes):

1= Receive complete, SSPBUF is full

0= Receive not complete, SSPBUF is empty

2

Transmit (I C mode only):

1= Transmit in progress, SSPBUF is full

0= Transmit complete, SSPBUF is empty

Note 1: PIC16F687/PIC16F689/PIC16F690 only.

DS41262D-page 176

PIC16F631/677/685/687/689/690

REGISTER 13-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER⁽¹⁾

R/W-0

WCOL

R/W-0

CKP

R/W-0

(2)

SSPOV

SSPEN

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

WCOL: Write Collision Detect bit

1= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)

0= No collision

SSPOV: Receive Overflow Indicator bit

In SPI mode:

1= A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the

data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only

transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new recep-

tion (and transmission) is initiated by writing to the SSPBUF register.

0= No overflow

2

In I C™ mode:

1= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in

Transmit mode. SSPOV must be cleared in software in either mode.

0= No overflow

bit 5

SSPEN: Synchronous Serial Port Enable bit

In SPI mode:

1= Enables serial port and configures SCK, SDO and SDI as serial port pins

0= Disables serial port and configures these pins as I/O port pins

2

In I C mode:

1= Enables the serial port and configures the SDA and SCL pins as serial port pins

0= Disables serial port and configures these pins as I/O port pins

In both modes, when enabled, these pins must be properly configured as input or output.

bit 4

CKP: Clock Polarity Select bit

In SPI mode:

1= Idle state for clock is a high level (Microwire default)

0= Idle state for clock is a low level (Microwire alternate)

2

In I C mode:

SCK release control

1= Enable clock

0= Holds clock low (clock stretch). (Used to ensure data setup time.)

bit 3-0

SSPM<3:0>: Synchronous Serial Port Mode Select bits

0000= SPI Master mode, clock = FOSC/4

0001= SPI Master mode, clock = FOSC/16

0010= SPI Master mode, clock = FOSC/64

0011= SPI Master mode, clock = TMR2 output/2

0100= SPI Slave mode, clock = SCK pin. SS pin control enabled.

0101= SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.

2

0110= I C Slave mode, 7-bit address

2

0111= I C Slave mode, 10-bit address

1000= Reserved

1001= Load SSPMSK register at SSPADD SFR address

(2)

1010= Reserved

2

1011= I C Firmware Controlled Master mode (slave IDLE)

1100= Reserved

1101= Reserved

2

1110= I C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

2

1111= I C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

Note 1: PIC16F687/PIC16F689/PIC16F690 only.

2: When this mode is selected, any reads or writes to the SSPADD SFR address actually accesses the SSPMSK register.

DS41262D-page 177

PIC16F631/677/685/687/689/690

When the application software is expecting to receive

13.2 Operation

valid data, the SSPBUF should be read before the next

byte of data to transfer is written to the SSPBUF. Buffer

Full bit BF of the SSPSTAT register indicates when

SSPBUF has been loaded with the received data

(transmission is complete). When the SSPBUF is read,

the BF bit is cleared. This data may be irrelevant if the

SPI is only a transmitter. Generally, the SSP interrupt is

used to determine when the transmission/reception

has completed. The SSPBUF must be read and/or

written. If the interrupt method is not going to be used,

then software polling can be done to ensure that a write

collision does not occur. Example 13-1 shows the

loading of the SSPBUF (SSPSR) for data transmission.

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPCON<5:0> and SSPSTAT<7:6>).

These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Data Input Sample Phase (middle or end of data

output time)

• Clock Edge (output data on rising/falling edge of

SCK)

• Clock Rate (Master mode only)

The SSPSR is not directly readable or writable and can

only be accessed by addressing the SSPBUF register.

Additionally, the SSP Status register (SSPSTAT)

indicates the various status conditions.

• Slave Select mode (Slave mode only)

The SSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR

until the received data is ready. Once the eight bits of

data have been received, that byte is moved to the

SSPBUF register. Then, the Buffer Full Status bit BF of

the SSPSTAT register, and the interrupt flag bit SSPIF,

are set. This double-buffering of the received data

(SSPBUF) allows the next byte to start reception before

reading the data that was just received. Any write to the

SSPBUF register during transmission/reception of data

will be ignored and the Write Collision Detect bit,

WCOL of the SSPCON register, will be set. User

software must clear the WCOL bit so that it can be

determined if the following write(s) to the SSPBUF

register completed successfully.

EXAMPLE 13-1:

LOADING THE SSPBUF (SSPSR) REGISTER

BSF

BCF

STATUS,RP0

STATUS,RP1

;Bank 1

;

LOOP

BTFSS SSPSTAT, BF

;Has data been received(transmit complete)?

;No

;Bank 0

;WREG reg = contents of SSPBUF

;Save in user RAM, if data is meaningful

;W reg = contents of TXDATA

;New data to xmit

GOTO

BCF

MOVF

MOVWF

MOVF

MOVWF

LOOP

STATUS,RP0

SSPBUF, W

RXDATA

TXDATA, W

SSPBUF

DS41262D-page 178

PIC16F631/677/685/687/689/690

13.3 Enabling SPI I/O

13.4 Typical Connection

To enable the serial port, SSP Enable bit SSPEN of the

SSPCON register must be set. To reset or reconfigure

SPI mode, clear the SSPEN bit, re-initialize the

SSPCON registers and then set the SSPEN bit. This

configures the SDI, SDO, SCK and SS pins as serial

port pins. For the pins to behave as the serial port

function, some must have their data direction bits (in

the TRISB and TRISC registers) appropriately

programmed. That is:

Figure 13-2 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their

programmed clock edge and latched on the opposite

edge of the clock. Both processors should be

programmed to the same Clock Polarity (CKP), then

both controllers would send and receive data at the

same time. Whether the data is meaningful (or dummy

data) depends on the application software. This leads

to three scenarios for data transmission:

• SDI is automatically controlled by the SPI module

• SDO must have TRISC<7> bit cleared

• Master sends data – Slave sends dummy data

• Master sends data – Slave sends data

• SCK (Master mode) must have TRISB<6> bit

cleared

• Master sends dummy data – Slave sends data

• SCK (Slave mode) must have TRISB<6> bit set

• SS must have TRISC<6> bit set

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRISB and TRISC) registers to the opposite

value.

FIGURE 13-2:

SPI MASTER/SLAVE CONNECTION

SPI Master SSPM<3:0> = 00xxb

SPI Slave SSPM<3:0> = 010xb

SDI

SDO

Serial Input Buffer

(SSPBUF)

Serial Input Buffer

(SSPBUF)

SDI

SDO

Shift Register

(SSPSR)

Shift Register

(SSPSR)

LSb

MSb

LSb

Serial Clock

SCK

Processor 1

Processor 2

DS41262D-page 179

PIC16F631/677/685/687/689/690

The clock polarity is selected by appropriately

13.5 Master Mode

programming the CKP bit of the SSPCON register. This

then, would give waveforms for SPI communication as

shown in Figure 13-3, Figure 13-5 and Figure 13-6,

where the MSB is transmitted first. In Master mode, the

SPI clock rate (bit rate) is user programmable to be one

of the following:

The master can initiate the data transfer at any time

because it controls the SCK. The master determines

when the slave (Processor 2, Figure 13-2) is to

broadcast data by the software protocol.

In Master mode, the data is transmitted/received as

soon as the SSPBUF register is written to. If the SPI is

only going to receive, the SDO output could be

disabled (programmed as an input). The SSPSR

register will continue to shift in the signal present on the

SDI pin at the programmed clock rate. As each byte is

received, it will be loaded into the SSPBUF register as

if a normal received byte (interrupts and Status bits

appropriately set). This could be useful in receiver

applications as a Line Activity Monitor mode.

• FOSC/4 (or TCY)

• FOSC/16 (or 4 • TCY)

• FOSC/64 (or 16 • TCY)

• Timer2 output/2 (PIC16F685/PIC16F690 only)

This allows a maximum data rate (at 40 MHz) of

10 Mbps.

Figure 13-3 shows the waveforms for Master mode.

When the CKE bit is set, the SDO data is valid before

there is a clock edge on SCK. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSPBUF is loaded with the received

data is shown.

FIGURE 13-3:

SPI MODE WAVEFORM (MASTER MODE)

Write to

SSPBUF

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

4 Clock

Modes

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

SDO

(CKE = 0)

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

bit 7

bit 3

SDO

(CKE = 1)

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SDI

(SMP = 1)

bit 0

bit 7

Input

Sample

(SMP = 1)

SSPIF

Next Q4 Cycle

after Q2↓

SSPSR to

SSPBUF

DS41262D-page 180

PIC16F631/677/685/687/689/690

even if in the middle of a transmitted byte, and becomes

a floating output. External pull-up/pull-down resistors

may be desirable, depending on the application.

13.6 Slave Mode

In Slave mode, the data is transmitted and received as

the external clock pulses appear on SCK. When the

last bit is latched, the SSPIF interrupt flag bit is set.

Note 1: When the SPI is in Slave mode with SS

pin control enabled (SSPCON<3:0> =

0100), the SPI module will reset if the SS

pin is set to VDD.

While in Slave mode, the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times as

specified in the electrical specifications.

2: If the SPI is used in Slave Mode with CKE

set, then the SS pin control must be

enabled.

While in Sleep mode, the slave can transmit/receive

data. When a byte is received, the device will wake-up

from Sleep.

When the SPI module resets, the bit counter is forced

to ‘0’. This can be done by either forcing the SS pin to

a high level or clearing the SSPEN bit.

13.7 Slave Select Synchronization

To emulate two-wire communication, the SDO pin can

be connected to the SDI pin. When the SPI needs to

operate as a receiver, the SDO pin can be configured

as an input. This disables transmissions from the SDO.

The SDI can always be left as an input (SDI function)

since it cannot create a bus conflict.

The SS pin allows a Synchronous Slave mode. The SPI

must be in Slave mode with SS pin control enabled

(SSPCON<3:0> = 04h). The pin must not be driven low

for the SS pin to function as an input. The data latch

must be high. When the SS pin is low, transmission and

reception are enabled and the SDO pin is driven. When

the SS pin goes high, the SDO pin is no longer driven,

FIGURE 13-4:

SLAVE SYNCHRONIZATION WAVEFORM

SS

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

bit 6

bit 7

bit 0

SDO

bit 7

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 Cycle

after Q2↓

SSPSR to

SSPBUF

DS41262D-page 181

PIC16F631/677/685/687/689/690

FIGURE 13-5:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

SS

Optional

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

bit 7

bit 3

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 Cycle

after Q2↓

SSPSR to

SSPBUF

FIGURE 13-6:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SS

Not Optional

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

Write to

SSPBUF

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

bit 7

bit 3

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 Cycle

after Q2↓

SSPSR to

SSPBUF

DS41262D-page 182

PIC16F631/677/685/687/689/690

13.8 Sleep Operation

13.10 Bus Mode Compatibility

In Master mode, all module clocks are halted and the

transmission/reception will remain in that state until the

device wakes from Sleep. After the device returns to

Normal mode, the module will continue to transmit/

receive data.

Table 13-1 shows the compatibility between the

standard SPI modes and the states of the CKP and

CKE control bits.

TABLE 13-1: SPI BUS MODES

In Slave mode, the SPI Transmit/Receive Shift register

operates asynchronously to the device. This allows the

device to be placed in Sleep mode and data to be

shifted into the SPI Transmit/Receive Shift register.

When all 8 bits have been received, the SSP interrupt

flag bit will be set and if enabled, will wake the device

from Sleep.

Control Bits State

Standard SPI Mode

Terminology

CKP

CKE

0, 0

0, 1

1, 0

1, 1

0

1

0

1

0

13.9 Effects of a Reset

There is also a SMP bit which controls when the data is

sampled.

A Reset disables the SSP module and terminates the

current transfer.

TABLE 13-2: REGISTERS ASSOCIATED WITH SPI OPERATION⁽¹⁾

Value on

POR,

BOR

Value on

all other

Resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh/8Bh/

10Bh/18Bh

INTCON

PIR1

GIE

—

PEIE

ADIF

T0IE

INTE

TXIF

RABIE

T0IF

INTF

RABIF 0000 000x 0000 000x

0Ch

RCIF

SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

xxxx xxxx uuuu uuuu

SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

13h

SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register

SSPCON WCOL SSPOV SSPEN CKP

TRISB7 TRISB6 TRISB5 TRISB4

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111

14h

—

1111 ----

1111 1111

86h/186h

87h/187h

8Ch

TRISB

TRISC

PIE1

—

ADIE

CKE

RCIE

D/A

TXIE

P

SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

94h

SSPSTAT

SMP

S

R/W

UA

BF

0000 0000 0000 0000

Legend:

x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.

Note 1: PIC16F687/PIC16F689/PIC16F690 only.

DS41262D-page 183

PIC16F631/677/685/687/689/690

The SSPCON register allows control of the I²C

2

13.11 SSP I C Operation

operation. Four mode selection bits (SSPCON<3:0>)

The SSP module in I²C mode, fully implements all slave

functions, except general call support, and provides

interrupts on Start and Stop bits in hardware to facilitate

firmware implementations of the master functions. The

SSP module implements the Standard mode

specifications, as well as 7-bit and 10-bit addressing.

allow one of the following I²C modes to be selected:

• I²C Slave mode (7-bit address)

• I²C Slave mode (10-bit address)

• I²C Slave mode (7-bit address), with Start and

Stop bit interrupts enabled to support Firmware

Master mode

• I²C Slave mode (10-bit address), with Start and

Stop bit interrupts enabled to support Firmware

Master mode

• I²C Start and Stop bit interrupts enabled to

support Firmware Master mode; Slave is idle

Two pins are used for data transfer. These are the RB6/

SCK/SCL pin, which is the clock (SCL), and the RB4/

AN10/SDI/SDA pin, which is the data (SDA).

The SSP module functions are enabled by setting SSP

enable bit SSPEN (SSPCON<5>).

Selection of any I²C mode with the SSPEN bit set

forces the SCL and SDA pins to be open drain,

provided these pins are programmed to inputs by

setting the appropriate TRISB bits. Pull-up resistors

must be provided externally to the SCL and SDA pins

for proper operation of the I²C module.

FIGURE 13-7:

SSP BLOCK DIAGRAM

(I²C™ MODE)

Internal

Data Bus

Read

Write

RB6/

SCK/

SCL

13.12 Slave Mode

SSPBUF Reg

In Slave mode, the SCL and SDA pins must be

configured as inputs (TRISB<6,4> are set). The SSP

module will override the input state with the output data

when required (slave-transmitter).

Shift

Clock

SSPSR Reg

RB4/

AN10/

SDI/SDA

MSb

LSb

When an address is matched, or the data transfer after

an address match is received, the hardware

automatically will generate the Acknowledge (ACK)

pulse, and then load the SSPBUF register with the

received value currently in the SSPSR register.

Addr Match

Match Detect

SSPMSK Reg

SSPADD Reg

There are certain conditions that will cause the SSP

module not to give this ACK pulse. They include (either

or both):

a) The Buffer Full bit BF of the SSPSTAT register

was set before the transfer was received.

Set, Reset

S, P bits

(SSPSTAT Reg)

Start and

Stop bit Detect

b) The overflow bit SSPOV of the SSPCON

register was set before the transfer was

received.

In this case, the SSPSR register value is not loaded

into the SSPBUF, but bit SSPIF of the PIR1 register is

set. Table 13-3 shows the results of when a data

transfer byte is received, given the status of bits BF and

SSPOV. The shaded cells show the condition where

user software did not properly clear the overflow

condition. Flag bit BF is cleared by reading the

SSPBUF register, while bit SSPOV is cleared through

software.

The SSP module has six registers for the I²C operation,

which are listed below.

• SSP Control register (SSPCON)

• SSP Status register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• SSP Shift register (SSPSR) – Not directly

accessible

• SSP Address register (SSPADD)

• SSP Mask register (SSPMSK)

The SCL clock input must have a minimum high and low

for proper operation. For high and low times of the I²C

specification, as well as the requirements of the SSP

module, see Section 17.0 “Electrical Specifications”.

DS41262D-page 184

PIC16F631/677/685/687/689/690

The sequence of events for 10-bit address is as

follows, with steps 7-9 for slave-transmitter:

13.12.1 ADDRESSING

Once the SSP module has been enabled, it waits for a

Start condition to occur. Following the Start condition,

the 8-bits are shifted into the SSPSR register. All

incoming bits are sampled with the rising edge of the

clock (SCL) line. The value of register SSPSR<7:1> is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match, and the BF

and SSPOV bits are clear, the following events occur:

1. Receive first (high) byte of address (bits SSPIF,

BF and bit UA (SSPSTAT<1>) are set).

2. Update the SSPADD register with second (low)

byte of address (clears bit UA and releases the

SCL line).

3. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

4. Receive second (low) byte of address (bits

SSPIF, BF and UA are set).

a) The SSPSR register value is loaded into the

SSPBUF register.

5. Update the SSPADD register with the first (high)

byte of address; if match releases SCL line, this

will clear bit UA.

b) The buffer full bit, BF is set.

c) An ACK pulse is generated.

6. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

d) SSP interrupt flag bit, SSPIF of the PIR1 register

is set (interrupt is generated if enabled) on the

falling edge of the ninth SCL pulse.

7. Receive repeated Start condition.

8. Receive first (high) byte of address (bits SSPIF

and BF are set).

In 10-bit Address mode, two address bytes need to be

received by the slave (Figure 13-8). The five Most

Significant bits (MSbs) of the first address byte specify

if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must

specify a write so the slave device will receive the

second address byte. For a 10-bit address, the first

byte would equal ‘1111 0 A9 A8 0’, where A9and

A8are the two MSbs of the address.

9. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

TABLE 13-3: DATA TRANSFER RECEIVED BYTE ACTIONS

Status Bits as Data

Set bit SSPIF

(SSP Interrupt occurs

if enabled)

Generate ACK

Transfer is Received

SSPSR → SSPBUF

Pulse

BF

SSPOV

0

1

Yes

No

Yes

No

Yes

1

0

Note:

Shaded cells show the conditions where the user software did not properly clear the overflow condition.

DS41262D-page 185

PIC16F631/677/685/687/689/690

13.12.2 RECEPTION

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

register is cleared. The received address is loaded into

the SSPBUF register.

When the address byte overflow condition exists, then

no Acknowledge (ACK) pulse is given. An overflow

condition is defined as either bit BF of the SSPSTAT

register is set, or bit SSPOV of the SSPCON register is

set. This is an error condition due to the user’s firm-

ware.

An SSP interrupt is generated for each data transfer

byte. Flag bit SSPIF of the PIR1 register must be

cleared in software. The SSPSTAT register is used to

determine the status of the byte.

FIGURE 13-8:

I²C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

R/W = 0

Receiving Address

A7 A6 A5 A4 A3 A2

Receiving Data

ACK

9

ACK

9

SDA

SCL

A1

7

D2 D1 D0

D4

D3

D7 D6 D5 D4 D3 D2 D1 D0

D7

1

D6 D5

1

2

3

4

5

6

8

9

1

2

3

4

5

6

8

2

3

4

5

6

7

8

7

P

S

SSPIF (PIR1<3>)

Cleared in software

Bus Master

terminates

transfer

BF (SSPSTAT<0>)

SSPBUF register is read

SSPOV (SSPCON<6>)

Bit SSPOV is set because the SSPBUF register is still full.

ACK is not sent.

DS41262D-page 186

PIC16F631/677/685/687/689/690

This register must be initiated prior to setting

SSPM<3:0> bits to select the I²C Slave mode (7-bit or

10-bit address).

13.12.3 SSP MASK REGISTER

An SSP Mask (SSPMSK) register is available in I²C

Slave mode as a mask for the value held in the

SSPSR register during an address comparison

operation. A zero (‘0’) bit in the SSPMSK register has

the effect of making the corresponding bit in the

SSPSR register a ‘don’t care’.

This register can only be accessed when the appropriate

mode is selected by bits (SSPM<3:0> of SSPCON).

The SSP Mask register is active during:

• 7-bit Address mode: address compare of A<7:1>.

This register is reset to all ‘1’s upon any Reset

condition and, therefore, has no effect on standard

SSP operation until written with a mask value.

• 10-bit Address mode: address compare of A<7:0>

only. The SSP mask has no effect during the

reception of the first (high) byte of the address.

REGISTER 13-3: SSPMSK: SSP MASK REGISTER⁽¹⁾

R/W-1

MSK7

R/W-1

MSK6

R/W-1

MSK5

R/W-1

MSK4

R/W-1

MSK3

R/W-1

MSK2

R/W-1

MSK1

R/W-1

MSK0⁽²⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-1

bit 0

MSK<7:1>: Mask bits

1= The received address bit n is compared to SSPADD<n> to detect I²C address match

0= The received address bit n is not used to detect I²C address match

MSK<0>: Mask bit for I²C Slave mode, 10-bit Address⁽²⁾

I²C Slave mode, 10-bit Address (SSPM<3:0> = 0111):

1= The received address bit 0 is compared to SSPADD<0> to detect I²C address match

0= The received address bit 0 is not used to detect I²C address match

Note 1: When SSPCON bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed

through the SSPMSK register. The SSPEN bit of the SSPCON register should be zero when accessing

the SSPMSK register.

2: In all other SSP modes, this bit has no effect.

DS41262D-page 187

PIC16F631/677/685/687/689/690

FIGURE 13-9:

I²C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS)

DS41262D-page 188

PIC16F631/677/685/687/689/690

An SSP interrupt is generated for each data transfer

byte. Flag bit SSPIF must be cleared in software, and

the SSPSTAT register is used to determine the status

of the byte. Flag bit SSPIF is set on the falling edge of

the ninth clock pulse.

13.12.4 TRANSMISSION

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit, and pin RB6/SCK/SCL is held

low. The transmit data must be loaded into the

SSPBUF register, which also loads the SSPSR

register. Then, pin RB6/SCK/SCL should be enabled

by setting bit CKP (SSPCON<4>). The master must

monitor the SCL pin prior to asserting another clock

pulse. The slave devices may be holding off the master

by stretching the clock. The eight data bits are shifted

out on the falling edge of the SCL input. This ensures

that the SDA signal is valid during the SCL high time

(Figure 13-10).

As a slave-transmitter, the ACK pulse from the master

receiver is latched on the rising edge of the ninth SCL

input pulse. If the SDA line was high (not ACK), then

the data transfer is complete. When the ACK is latched

by the slave, the slave logic is reset (resets SSPSTAT

register) and the slave then monitors for another

occurrence of the Start bit. If the SDA line was low

(ACK), the transmit data must be loaded into the

SSPBUF register, which also loads the SSPSR

register. Then pin RB6/SCK/SCL should be enabled by

setting bit CKP.

FIGURE 13-10:

I²C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

Receiving Address

R/W = 1

ACK

Transmitting Data

ACK

9

SDA

A7 A6 A5 A4 A3 A2 A1

D7 D6 D5 D4 D3 D2 D1 D0

SCL

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

S

P

SCL held low

while CPU

responds to SSPIF

Data in

sampled

Cleared in software

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

From SSP Interrupt

Service Routine

SSPBUF is written in software

CKP (SSPCON<4>)

Set bit after writing to SSPBUF

(the SSPBUF must be written to

before the CKP bit can be set)

DS41262D-page 189

PIC16F631/677/685/687/689/690

2

FIGURE 13-11:

I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)

DS41262D-page 190

PIC16F631/677/685/687/689/690

13.13 Master Mode

13.14 Multi-Master Mode

Master mode of operation is supported in firmware

using interrupt generation on the detection of the Start

and Stop conditions. The Stop (P) and Start (S) bits are

cleared from a Reset or when the SSP module is

disabled. The Stop (P) and Start (S) bits will toggle

based on the Start and Stop conditions. Control of the

I²C bus may be taken when the P bit is set or the bus

is idle and both the S and P bits are clear.

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions, allows the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the SSP

module is disabled. The Stop (P) and Start (S) bits will

toggle based on the Start and Stop conditions. Control

of the I²C bus may be taken when bit P (SSPSTAT<4>)

is set, or the bus is idle and both the S and P bits clear.

When the bus is busy, enabling the SSP Interrupt will

generate the interrupt when the Stop condition occurs.

In Master mode, the SCL and SDA lines are

manipulated

by

clearing

the

corresponding

TRISB<6,4> bit(s). The output level is always low,

irrespective of the value(s) in PORTB<6,4>. So when

transmitting data, a ‘1’ data bit must have the

TRISB<4> bit set (input) and a ‘0’ data bit must have

the TRISB<4> bit cleared (output). The same scenario

is true for the SCL line with the TRISB<6> bit. Pull-up

resistors must be provided externally to the SCL and

SDA pins for proper operation of the I²C module.

In Multi-Master operation, the SDA line must be

monitored to see if the signal level is the expected

output level. This check only needs to be done when a

high level is output. If a high level is expected and a low

level is present, the device needs to release the SDA

and SCL lines (set TRISB<6,4>). There are two stages

where this arbitration can be lost, these are:

• Address Transfer

• Data Transfer

The following events will cause the SSP Interrupt Flag

bit, SSPIF, to be set (SSP Interrupt will occur if

enabled):

When the slave logic is enabled, the slave continues to

receive. If arbitration was lost during the address

transfer stage, communication to the device may be in

progress. If addressed, an ACK pulse will be generated.

If arbitration was lost during the data transfer stage, the

device will need to re-transfer the data at a later time.

• Start condition

• Stop condition

• Data transfer byte transmitted/received

Master mode of operation can be done with either the

Slave mode idle (SSPM<3:0> = 1011), or with the

Slave active. When both Master and Slave modes are

enabled, the software needs to differentiate the

source(s) of the interrupt.

13.14.1 CLOCK SYNCHRONIZATION AND

THE CKP BIT

When the CKP bit is cleared, the SCL output is forced

to ‘0’; however, setting the CKP bit will not assert the

SCL output low until the SCL output is already sampled

low. Therefore, the CKP bit will not assert the SCL line

until an external I²C master device has already

asserted the SCL line. The SCL output will remain low

until the CKP bit is set and all other devices on the I²C

bus have deasserted SCL. This ensures that a write to

the CKP bit will not violate the minimum high time

requirement for SCL (see Figure 13-12).

DS41262D-page 191

PIC16F631/677/685/687/689/690

FIGURE 13-12:

CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDA

SCL

DX

DX-1

Master device

asserts clock

CKP

Master device

deasserts clock

WR

SSPCON

TABLE 13-4: REGISTERS ASSOCIATED WITH I²C™ OPERATION⁽¹⁾

Value on

all other

Resets

Value on

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh/8Bh/

10Bh/18Bh

INTCON

GIE

—

PEIE

ADIF

T0IE

INTE

TXIF

RABIE

SSPIF

T0IF

INTF

RABIF

0000 000x

0Ch

13h

14h

86h

PIR1

RCIF

CCP1IF

TMR2IF

TMR1IF -000 0000

-000 0000

uuuu uuuu

0000 0000

1111 ----

SSPBUF

SSPCON

TRISB

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx

WCOL

SSPOV

TRISB6

SSPEN

TRISB5

CKP

SSPM3

—

SSPM2

—

SSPM1

—

SSPM0

—

0000 0000

1111 ----

TRISB7

TRISB4

93h

94h

8Ch

SSPMSK⁽²⁾

SSPSTAT

PIE1

MSK7

SMP⁽³⁾

—

MSK6

CKE⁽³⁾

ADIE

MSK5

D/A

MSK4

P

MSK3

S

MSK2

R/W

MSK1

UA

MSK0

BF

1111 1111

0000 0000

1111 1111

0000 0000

-000 0000

RCIE

TXIE

SSPIE

CCP1IE

TMR2IF

TMR1IF -000 0000

Legend:

Note 1:

2:

– = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the SSP module.

PIC16F687/PIC16F689/PIC16F690 only.

SSPMSK register (Register 13-3) can be accessed by reading or writing to SSPADD register with bits SSPM<3:0> = 1001.

See Registers 13-2 and 13-3 for more details.

3:

Maintain these bits clear.

DS41262D-page 192

PIC16F631/677/685/687/689/690

14.0 SPECIAL FEATURES OF THE

CPU

The PIC16F631/677/685/687/689/690 have a host of

features intended to maximize system reliability,

minimize cost through elimination of external compo-

nents, provide power saving features and offer code

protection.

These features are:

• Reset

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)

• Oscillator selection

• Sleep

• Code protection

• ID Locations

• In-Circuit Serial Programming

The PIC16F631/677/685/687/689/690 have two timers

that offer necessary delays on power-up. One is the

Oscillator Start-up Timer (OST), intended to keep the

chip in Reset until the crystal oscillator is stable. The

other is the Power-up Timer (PWRT), which provides a

fixed delay of 64 ms (nominal) on power-up only,

designed to keep the part in Reset while the power

supply stabilizes. There is also circuitry to reset the

device if a brown-out occurs, which can use the Power-

up Timer to provide at least a 64 ms Reset. With these

three functions-on-chip, most applications need no

external Reset circuitry.

The Sleep mode is designed to offer a very low-current

Power-down mode. The user can wake-up from Sleep

through:

• External Reset

• Watchdog Timer Wake-up

• An interrupt

Several oscillator options are also made available to

allow the part to fit the application. The INTOSC option

saves system cost while the LP crystal option saves

power. A set of Configuration bits are used to select

various options (see Register 14-2).

DS41262D-page 193

PIC16F631/677/685/687/689/690

14.1 Configuration Bits

The Configuration bits can be programmed (read as

‘0’), or left unprogrammed (read as ‘1’) to select various

device configurations as shown in Register 14-2.

These bits are mapped in program memory location

2007h.

Note:

Address 2007h is beyond the user program

memory space. It belongs to the special

configuration memory space (2000h-

3FFFh), which can be accessed only during

programming. See “PIC12F6XX/16F6XX

Memory

Programming

Specification”

(DS41204) for more information.

DS41262D-page 194

PIC16F631/677/685/687/689/690

REGISTER 14-1: CONFIG: CONFIGURATION WORD REGISTER

Reserved

bit 13

Reserved

FCMEN

PWRTE

IESO

BOREN1⁽¹⁾

BOREN0⁽¹⁾

CPD⁽²

bit 7

CP⁽³⁾

MCLRE⁽⁴⁾

WDTE

FOSC2

FOSC1

FOSC0

bit 0

bit 6

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

P = Programmable’

‘0’ = Bit is cleared

U = Unimplemented

bit, read as ‘0’

-n = Value at POR

x = Bit is unknown

bit 13-12

bit 11

Reserved: Reserved bits. Do Not Use.

FCMEN: Fail-Safe Clock Monitor Enabled bit

1= Fail-Safe Clock Monitor is enabled

0= Fail-Safe Clock Monitor is disabled

bit 10

IESO: Internal External Switchover bit

1= Internal External Switchover mode is enabled

0= Internal External Switchover mode is disabled

bit 9-8

BOREN<1:0>: Brown-out Reset Selection bits⁽¹⁾

11= BOR enabled

10= BOR enabled during operation and disabled in Sleep

01= BOR controlled by SBOREN bit of the PCON register

00= BOR disabled

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

CPD: Data Code Protection bit⁽²⁾

1= Data memory code protection is disabled

0= Data memory code protection is enabled

CP: Code Protection bit⁽²⁾

1= Program memory code protection is disabled

0= Program memory code protection is enabled

MCLRE: MCLR Pin Function Select bit⁽³⁾

1= MCLR pin function is MCLR

0= MCLR pin function is digital input, MCLR internally tied to VDD

PWRTE: Power-up Timer Enable bit

1= PWRT disabled

0= PWRT enabled

WDTE: Watchdog Timer Enable bit

1= WDT enabled

0= WDT disabled

FOSC<2:0>: Oscillator Selection bits

111=

110=

101=

RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN

RCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN

INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on

RA5/OSC1/CLKIN

100=

INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on

RA5/OSC1/CLKIN

011=

010=

001=

000=

EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN

HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN

XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN

LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN

Note 1:

Enabling Brown-out Reset does not automatically enable Power-up Timer.

The entire data EEPROM will be erased when the code protection is turned off.

The entire program memory will be erased when the code protection is turned off.

When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.

2:

3:

4:

DS41262D-page 195

PIC16F631/677/685/687/689/690

They are not affected by a WDT Wake-up since this is

14.2 Reset

viewed as the resumption of normal operation. TO and

PD bits are set or cleared differently in different Reset

situations, as indicated in Table 14-2. These bits are

used in software to determine the nature of the Reset.

See Table 14-4 for a full description of Reset states of

all registers.

The PIC16F631/677/685/687/689/690 differentiates

between various kinds of Reset:

a) Power-on Reset (POR)

b) WDT Reset during normal operation

c) WDT Reset during Sleep

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 14-1.

d) MCLR Reset during normal operation

e) MCLR Reset during Sleep

f) Brown-out Reset (BOR)

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Section 17.0 “Electrical

Specifications” for pulse-width specifications.

Some registers are not affected in any Reset condition;

their status is unknown on POR and unchanged in any

other Reset. Most other registers are reset to a “Reset

state” on:

• Power-on Reset

• MCLR Reset

• MCLR Reset during Sleep

• WDT Reset

• Brown-out Reset (BOR)

FIGURE 14-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/VPP pin

Sleep

WDT

Module

Time-out

Reset

VDD Rise

Detect

Power-on Reset

VDD

Brown-out⁽¹⁾

Reset

BOREN

SBOREN

S

OST/PWRT

OST

10-bit Ripple Counter

Chip_Reset

R

Q

OSC1/

CLKI pin

PWRT

11-bit Ripple Counter

LFINTOSC

Enable PWRT

Enable OST

Note 1: Refer to the Configuration Word register (Register 14-1).

DS41262D-page 196

PIC16F631/677/685/687/689/690

14.2.1

POWER-ON RESET (POR)

FIGURE 14-2:

RECOMMENDED MCLR

CIRCUIT

The on-chip POR circuit holds the chip in Reset until VDD

has reached a high enough level for proper operation. A

maximum rise time for VDD is required. See

Section 17.0 “Electrical Specifications” for details. If

the BOR is enabled, the maximum rise time specification

does not apply. The BOR circuitry will keep the device in

Reset until VDD reaches VBOR (see Section 14.2.4

“Brown-out Reset (BOR)”).

VDD

R1

PIC16F685

1 kΩ (or greater)

MCLR

Note:

The POR circuit does not produce an

internal Reset when VDD declines. To

re-enable the POR, VDD must reach Vss

for a minimum of 100 μs.

C1

0.1 μF

(optional, not critical)

When the device starts normal operation (exits the

Reset condition), device operating parameters (i.e.,

voltage, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

14.2.3

POWER-UP TIMER (PWRT)

The Power-up Timer provides a fixed 64 ms (nominal)

time-out on power-up only, from POR or Brown-out

Reset. The Power-up Timer operates from the 31 kHz

LFINTOSC oscillator. For more information, see

Section 3.5 “Internal Clock Modes”. The chip is kept

in Reset as long as PWRT is active. The PWRT delay

allows the VDD to rise to an acceptable level. A

Configuration bit, PWRTE, can disable (if set) or enable

(if cleared or programmed) the Power-up Timer. The

Power-up Timer should be enabled when Brown-out

Reset is enabled, although it is not required.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting” (DS00607).

14.2.2

MCLR

PIC16F631/677/685/687/689/690 has a noise filter in

the MCLR Reset path. The filter will detect and ignore

small pulses.

It should be noted that a WDT Reset does not drive

MCLR pin low.

The Power-up Timer delay will vary from chip-to-chip

and vary due to:

The behavior of the ESD protection on the MCLR pin

has been altered from early devices of this family.

Voltages applied to the pin that exceed its specification

can result in both MCLR Resets and excessive current

beyond the device specification during the ESD event.

For this reason, Microchip recommends that the MCLR

pin no longer be tied directly to VDD. The use of an RC

network, as shown in Figure 14-2, is suggested.

• VDD variation

• Temperature variation

• Process variation

See DC parameters for details (Section 17.0 “Electrical

Specifications”).

An internal MCLR option is enabled by clearing the

MCLRE bit in the Configuration Word register. When

MCLRE = 0, the Reset signal to the chip is generated

internally. When the MCLRE = 1, the RA3/MCLR pin

becomes an external Reset input. In this mode, the

RA3/MCLR pin has a weak pull-up to VDD.

DS41262D-page 197

PIC16F631/677/685/687/689/690

On any Reset (Power-on, Brown-out Reset, Watchdog

Timer, etc.), the chip will remain in Reset until VDD rises

above VBOR (see Figure 14-3). The Power-up Timer

will now be invoked, if enabled and will keep the chip in

Reset an additional 64 ms.

14.2.4

BROWN-OUT RESET (BOR)

The BOREN0 and BOREN1 bits in the Configuration

Word register select one of four BOR modes. Two

modes have been added to allow software or hardware

control of the BOR enable. When BOREN<1:0> = 01,

the SBOREN bit (PCON<4>) enables/disables the

BOR allowing it to be controlled in software. By

selecting BOREN<1:0>, the BOR is automatically

disabled in Sleep to conserve power and enabled on

wake-up. In this mode, the SBOREN bit is disabled.

See Register 14-2 for the Configuration Word

definition.

Note:

The Power-up Timer is enabled by the

PWRTE bit in the Configuration Word

register.

If VDD drops below VBOR while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Power-up Timer will be re-initialized. Once VDD

rises above VBOR, the Power-up Timer will execute a

64 ms Reset.

If VDD falls below VBOR for greater than parameter

(TBOR) (see Section 17.0 “Electrical Specifications”),

the Brown-out situation will reset the device. This will

occur regardless of VDD slew rate. A Reset is not insured

to occur if VDD falls below VBOR for less than parameter

(TBOR).

FIGURE 14-3:

BROWN-OUT SITUATIONS

VDD

VBOR

Internal

Reset

(1)

64 ms

VDD

VBOR

Internal

Reset

< 64 ms

(1)

64 ms

VDD

VBOR

Internal

Reset

(1)

64 ms

Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.

DS41262D-page 198

PIC16F631/677/685/687/689/690

14.2.5

TIME-OUT SEQUENCE

14.2.6

POWER CONTROL (PCON)

REGISTER

On power-up, the time-out sequence is as follows: first,

PWRT time-out is invoked after POR has expired, then

OST is activated after the PWRT time-out has expired.

The total time-out will vary based on oscillator

configuration and PWRTE bit status. For example, in

EC mode with PWRTE bit erased (PWRT disabled),

there will be no time-out at all. Figures 14-4, 14-5

and 14-6 depict time-out sequences. The device can

execute code from the INTOSC while OST is active by

enabling Two-Speed Start-up or Fail-Safe Monitor (see

Section 3.7.2 “Two-speed Start-up Sequence” and

Section 3.8 “Fail-Safe Clock Monitor”).

The Power Control register PCON (address 8Eh) has

two Status bits to indicate what type of Reset that last

occurred.

Bit 0 is BOR (Brown-out Reset). BOR is unknown on

Power-on Reset. It must then be set by the user and

checked on subsequent Resets to see if BOR = 0,

indicating that a Brown-out has occurred. The BOR

Status bit is a “don’t care” and is not necessarily

predictable if the brown-out circuit is disabled

(BOREN<1:0> = 00 in the Configuration Word

register).

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then,

bringing MCLR high will begin execution immediately

(see Figure 14-5). This is useful for testing purposes or

to synchronize more than one PIC16F631/677/685/

687/689/690 device operating in parallel.

Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaffected otherwise. The user must write a

‘1’ to this bit following a Power-on Reset. On a

subsequent Reset, if POR is ‘0’, it will indicate that a

Power-on Reset has occurred (i.e., VDD may have

gone too low).

Table 14-5 shows the Reset conditions for some

special registers, while Table 14-4 shows the Reset

conditions for all the registers.

For more information, see Section 4.2.4 “Ultra Low-

Power Wake-up” and Section 14.2.4 “Brown-out

Reset (BOR)”.

TABLE 14-1: TIME-OUT IN VARIOUS SITUATIONS

Power-up

Brown-out Reset

Wake-up from

Oscillator Configuration

Sleep

PWRTE = 0

PWRTE = 1

PWRTE = 0

PWRTE = 1

XT, HS, LP

TPWRT +

1024 • TOSC

TPWRT +

1024 • TOSC

LP, T1OSCIN = 1

TPWRT

—

TPWRT

—

RC, EC, INTOSC

TABLE 14-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE

POR

BOR

TO

PD

Condition

0

u

x

0

u

1

0

u

1

u

0

u

0

Power-on Reset

Brown-out Reset

WDT Reset

WDT Wake-up

MCLR Reset during normal operation

MCLR Reset during Sleep

Legend: u= unchanged, x= unknown

TABLE 14-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PCON

—

ULPWUE SBOREN

RPO TO

—

Z

POR

DC

BOR

C

--01 --qq

0001 1xxx

--0u --uu

000q quuu

IRP

RP1

PD

STATUS

Legend:

u= unchanged, x= unknown, – = unimplemented bit, reads as ‘0’, q= value depends on condition. Shaded cells are not used by BOR.

Note 1:

Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

DS41262D-page 199

PIC16F631/677/685/687/689/690

FIGURE 14-4:

TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

FIGURE 14-5:

TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

FIGURE 14-6:

TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

DS41262D-page 200

PIC16F631/677/685/687/689/690

TABLE 14-4: INITIALIZATION CONDITION FOR REGISTER

Wake-up from Sleep

through Interrupt

Wake-up from Sleep

through WDT Time-out

MCLR Reset

WDT Reset

Brown-out Reset

Register

Address

Power-on Reset

(1)

W

—

xxxx xxxx

uuuu uuuu

xxxx xxxx

uuuu uuuu

INDF

00h/80h/

100h/180h

TMR0

PCL

01h/101h

xxxx xxxx

0000 0000

uuuu uuuu

0000 0000

uuuu uuuu

(3)

02h/82h/

PC + 1

102h/182h

(4)

STATUS

FSR

03h/83h/

103h/183h

0001 1xxx

xxxx xxxx

000q quuu

uuuq quuu

04h/84h/

uuuu uuuu

104h184h

PORTA

PORTB

PORTC

PCLATH

05h/105h

06h/106h

07h/107h

--xx xxxx

xxxx ----

xxxx xxxx

---0 0000

--uu uuuu

uuuu ----

uuuu uuuu

---0 0000

--uu uuuu

uuuu ----

uuuu uuuu

---u uuuu

0Ah/8Ah/

10Ah/18Ah

(2)

INTCON

0Bh/8Bh/

0000 000x

0000 000u

uuuu uuuu

10Bh/18Bh

(2)

PIR1

0Ch

0Dh

0Eh

-000 0000

0000 ----

xxxx xxxx

0000 0000

-000 0000

xxxx xxxx

0000 0000

xxxx xxxx

0000 0000

0000 000x

0000 0000

xxxx xxxx

0000 0000

1111 1111

--11 1111

-000 0000

0000 ----

uuuu uuuu

0000 0000

-000 0000

uuuu uuuu

0000 0000

uuuu uuuu

0000 0000

0000 000x

0000 0000

uuuu uuuu

0000 0000

1111 1111

--11 1111

-uuu uuuu

(2)

PIR2

uuuu ----

TMR1L

uuuu uuuu

-uuu uuuu

uuuu uuuu

--uu uuuu

TMR1H

T1CON

0Fh

10h

TMR2

11h

T2CON

12h

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA

13h

14h

15h

16h

17h

18h

TXREG

RCREG

PWM1CON

ECCPAS

ADRESH

ADCON0

OPTION_REG

TRISA

19h

1Ah

1Ch

1Dh

1Eh

1Fh

81h/181h

85h/185h

Legend: u= unchanged, x= unknown, —= unimplemented bit, reads as ‘0’, q= value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

4: See Table 14-5 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

6: Accessible only when SSPM<3:0> = 1001.

DS41262D-page 201

PIC16F631/677/685/687/689/690

TABLE 14-4: INITIALIZATION CONDITION FOR REGISTER (CONTINUED)

Wake-up from Sleep

through Interrupt

Wake-up from Sleep

through WDT Time-out

MCLR Reset

WDT Reset (Continued)

Brown-out Reset

Register

Address

Power-on Reset

(1)

TRISB

86h/186h

87h/187h

8Ch

1111 ----

1111 1111

-000 0000

0000 ----

--01 --0x

-110 q000

---0 0000

1111 1111

0000 0000

---- ----

0000 0000

--11 -111

--00 0000

---0 1000

0000 0010

0000 0000

01-0 0-00

xxxx xxxx

-000 ----

0000 0000

--00 0000

---- 0000

1111 ----

0000 ----

0000 0000

0000 -000

00-- --00

1111 1111

---- 1111

x--- x000

---- ----

---0 0001

0000 00--

1111 ----

1111 1111

-000 0000

0000 ----

uuuu ----

uuuu uuuu

-uuu uuuu

uuuu uuuu

--uu --uu

-uuu uuuu

---u uuuu

uuuu uuuu

--uu uuuu

---u uuuu

uuuu uuuu

uu-u u-uu

uuuu uuuu

-uuu ----

uuuu uuuu

--uu uuuu

---- uuuu

uuuu ----

uuuu uuuu

uuuu -uuu

uu-- --uu

uuuu uuuu

---- uuuu

---- ----

---u uuuu

uuuu uu--

TRISC

PIE1

PIE2

8Dh

1, 5)

PCON

8Eh

--0u --uq

OSCCON

OSCTUNE

PR2

8Fh

-110 q000

---u uuuu

1111 1111

--11 -111

--00 0000

---0 1000

0000 0010

0000 0000

01-0 0-00

uuuu uuuu

-000 ----

0000 0000

--00 0000

---- 0000

1111 ----

0000 ----

0000 0000

0000 -000

00-- --10

1111 1111

---- 1111

u--- q000

---- ----

---0 0001

0000 00--

90h

92h

SSPADD

93h

(6)

SSPMSK

SSPSTAT

WPUA

93h

94h

95h

IOCA

96h

WDTCON

TXSTA

97h

98h

SPBRG

99h

SPBRGH

BAUDCTL

ADRESL

ADCON1

EEDAT

9Ah

9Bh

9Eh

9Fh

10Ch

10Dh

10Eh

10Fh

115h

116h

118h

119h

11Ah

11Bh

11Eh

11Fh

18Ch

18Dh

19Dh

19EH

EEADR

EEDATH

EEADRH

WPUB

IOCB

VRCON

CM1CON0

CM2CON0

CM2CON1

ANSEL

ANSELH

EECON1

EECON2

PSTRCON

SRCON

Legend: u= unchanged, x= unknown, —= unimplemented bit, reads as ‘0’, q= value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

4: See Table 14-5 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

6: Accessible only when SSPM<3:0> = 1001.

DS41262D-page 202

PIC16F631/677/685/687/689/690

TABLE 14-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

Program Status

PCON

Register

Condition

Counter

Register

Power-on Reset

000h

0001 1xxx

000u uuuu

0001 0uuu

0000 uuuu

uuu0 0uuu

0001 1uuu

uuu1 0uuu

--01 --0x

--0u --uu

--uu --uu

--01 --u0

--uu --uu

MCLR Reset during normal operation

MCLR Reset during Sleep

WDT Reset

000h

WDT Wake-up

PC + 1

Brown-out Reset

000h

PC + 1⁽¹⁾

Interrupt Wake-up from Sleep

Legend: u= unchanged, x= unknown, —= unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with

the interrupt vector (0004h) after execution of PC + 1.

DS41262D-page 203

PIC16F631/677/685/687/689/690

When an interrupt is serviced:

14.3 Interrupts

• The GIE is cleared to disable any further interrupt.

• The return address is pushed onto the stack.

• The PC is loaded with 0004h.

The PIC16F631/677/685/687/689/690 have multiple

sources of interrupt:

• External Interrupt RA2/INT

For external interrupt events, such as the INT pin,

PORTA/PORTB change interrupts, the interrupt

latency will be three or four instruction cycles. The

exact latency depends upon when the interrupt event

occurs (see Figure 14-8). The latency is the same for

one or two-cycle instructions. Once in the Interrupt

Service Routine, the source(s) of the interrupt can be

determined by polling the interrupt flag bits. The

interrupt flag bit(s) must be cleared in software before

re-enabling interrupts to avoid multiple interrupt

requests.

• TMR0 Overflow Interrupt

• PORTA/PORTB Change Interrupts

• 2 Comparator Interrupts

• A/D Interrupt (except PIC16F631)

• Timer1 Overflow Interrupt

• Timer2 Match Interrupt (PIC16F685/PIC16F690

only)

• EEPROM Data Write Interrupt

• Fail-Safe Clock Monitor Interrupt

• Enhanced CCP Interrupt (PIC16F685/PIC16F690

only)

• EUSART Receive and Transmit interrupts

(PIC16F687/PIC16F689/PIC16F690 only)

Note 1: Individual interrupt flag bits are set,

regardless of the status of their

corresponding mask bit or the GIE bit.

The Interrupt Control register (INTCON) and Peripheral

Interrupt Request Register 1 (PIR1) record individual

interrupt requests in flag bits. The INTCON register

also has individual and global interrupt enable bits.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The interrupts, which were

ignored, are still pending to be serviced

when the GIE bit is set again.

A Global Interrupt Enable bit, GIE (INTCON<7>),

enables (if set) all unmasked interrupts, or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in the

INTCON, PIE1 and PIE2 registers, respectively. GIE is

cleared on Reset.

For additional information on Timer1, Timer2,

comparators, A/D, data EEPROM, EUSART, SSP or

Enhanced CCP modules, refer to the respective

peripheral section.

The Return from Interrupt instruction, RETFIE, exits

the interrupt routine, as well as sets the GIE bit, which

re-enables unmasked interrupts.

14.3.1

RA2/INT INTERRUPT

External interrupt on RA2/INT pin is edge-triggered;

either rising if the INTEDG bit (OPTION_REG<6>) is

set, or falling, if the INTEDG bit is clear. When a valid

edge appears on the RA2/INT pin, the INTF bit

(INTCON<1>) is set. This interrupt can be disabled by

clearing the INTE control bit (INTCON<4>). The INTF

bit must be cleared in software in the Interrupt Service

Routine before re-enabling this interrupt. The RA2/INT

interrupt can wake-up the processor from Sleep, if the

INTE bit was set prior to going into Sleep. The status of

the GIE bit decides whether or not the processor

branches to the interrupt vector following wake-up

(0004h). See Section 14.6 “Power-Down Mode

(Sleep)” for details on Sleep and Figure 14-10 for

timing of wake-up from Sleep through RA2/INT

interrupt.

The following interrupt flags are contained in the

INTCON register:

• INT Pin Interrupt

• PORTA/PORTB Change Interrupts

• TMR0 Overflow Interrupt

The peripheral interrupt flags are contained in the PIR1

and PIR2 registers. The corresponding interrupt enable

bits are contained in PIE1 and PIE2 registers.

The following interrupt flags are contained in the PIR1

register:

• A/D Interrupt

• EUSART Receive and Transmit Interrupts

• Timer1 Overflow Interrupt

• Synchronous Serial Port (SSP) Interrupt

• Enhanced CCP1 Interrupt

• Timer1 Overflow Interrupt

• Timer2 Match Interrupt

Note:

The ANSEL and CM2CON0 registers

must be initialized to configure an analog

channel as a digital input. Pins configured

as analog inputs will read ‘0’.

The following interrupt flags are contained in the PIR2

register:

• Fail-Safe Clock Monitor Interrupt

• 2 Comparator Interrupts

• EEPROM Data Write Interrupt

DS41262D-page 204

PIC16F631/677/685/687/689/690

14.3.2

TMR0 INTERRUPT

14.3.3

PORTA/PORTB INTERRUPT

An overflow (FFh → 00h) in the TMR0 register will set

the T0IF (INTCON<2>) bit. The interrupt can be

enabled/disabled by setting/clearing T0IE (INTCON<5>)

bit. See Section 5.0 “Timer0 Module” for operation of

the Timer0 module.

An input change on PORTA or PORTB change sets the

RABIF (INTCON<0>) bit. The interrupt can be enabled/

disabled by setting/clearing the RABIE (INTCON<3>)

bit. Plus, individual pins can be configured through the

IOCA or IOCB registers.

Note:

If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RABIF

interrupt flag may not get set. See

Section 4.2.3 “Interrupt-on-change” for

more information.

FIGURE 14-7:

INTERRUPT LOGIC

IOC-RA0

IOCA0

IOC-RA1

IOCA1

IOC-RA2

IOCA2

IOC-RA3

IOCA3

SSPIF

SSPIE

IOC-RA4

IOCA4

TXIF

TXIE

IOC-RA5

IOCA5

RCIF

RCIE

(1)

Wake-up (If in Sleep mode)

IOC-RB4

IOCB4

T0IF

T0IE

TMR2IF

TMR2IE

Interrupt to CPU

INTF

INTE

RABIF

IOC-RB5

IOCB5

TMR1IF

TMR1IE

IOC-RB6

IOCB6

RABIE

C1IF

C1IE

PEIE

GIE

IOC-RB7

IOCB7

C2IF

C2IE

ADIF

ADIE

EEIF

EEIE

Note 1: Some peripherals depend upon the system

clock for operation. Since the system clock is

suspended during Sleep, these peripherals

will not wake the part from Sleep. See

OSFIF

OSFIE

CCP1IF

CCP1IE

Section 14.6.1 “Wake-up from Sleep”.

DS41262D-page 205

PIC16F631/677/685/687/689/690

FIGURE 14-8:

INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

(3)

CLKOUT

(4)

INT pin

(1)

(2)

(5)

Interrupt Latency

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

PC

PC + 1

—

0004h

0005h

PC

Inst (PC)

PC + 1

Instruction

Fetched

Inst (PC + 1)

Inst (0004h)

Inst (0005h)

Inst (0004h)

Instruction

Executed

Dummy Cycle

Inst (PC)

Inst (PC – 1)

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency

is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in INTOSC and RC Oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 17.0 “Electrical Specifications”.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

TABLE 14-6: SUMMARY OF INTERRUPT REGISTERS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

INTCON

PIE1

GIE

—

PEIE

ADIE

C2IE

ADIF

C2IF

T0IE

RCIE

C1IE

RCIF

C1IF

INTE

TXIE

EEIE

TXIF

EEIF

RABIE

SSPIE

—

T0IF

INTF

RABIF

0000 000x 0000 000x

CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

0000 ---- 0000 ----

CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

0000 ---- 0000 ----

PIE2

OSFIE

—

PIR1

SSPIF

—

PIR2

OSFIF

—

Legend:

x= unknown, u= unchanged, —= unimplemented read as ‘0’, q= value depends upon condition.

Shaded cells are not used by the Interrupt module.

DS41262D-page 206

PIC16F631/677/685/687/689/690

14.4 Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key

registers during an interrupt (e.g., W and STATUS

registers). This must be implemented in software.

Since the upper 16 bytes of all GPR banks are common

in

the

PIC16F631/677/685/687/689/690

(see

Figures 2-2 and 2-3), temporary holding registers,

W_TEMP and STATUS_TEMP, should be placed in

here. These 16 locations do not require banking and

therefore, make it easier to context save and restore.

The same code shown in Example 14-1 can be used

to:

• Store the W register

• Store the STATUS register

• Execute the ISR code

• Restore the Status (and Bank Select Bit register)

• Restore the W register

Note:

The

PIC16F631/677/685/687/689/690

normally does not require saving the

PCLATH. However, if computed GOTO’s

are used in the ISR and the main code, the

PCLATH must be saved and restored in

the ISR.

EXAMPLE 14-1:

SAVING STATUS AND W REGISTERS IN RAM

MOVWF W_TEMP

;Copy W to TEMP register

SWAPF STATUS,W

CLRF STATUS

MOVWF STATUS_TEMP

;Swap status to be saved into W

;bank 0, regardless of current bank, Clears IRP,RP1,RP0

;Save status to bank zero STATUS_TEMP register

:

:(ISR)

;Insert user code here

:

SWAPF STATUS_TEMP,W

;Swap STATUS_TEMP register into W

;(sets bank to original state)

;Move W into STATUS register

;Swap W_TEMP

MOVWF STATUS

SWAPF W_TEMP,F

SWAPF W_TEMP,W

;Swap W_TEMP into W

DS41262D-page 207

PIC16F631/677/685/687/689/690

14.5.2

WDT CONTROL

14.5 Watchdog Timer (WDT)

The WDTE bit is located in the Configuration Word

register. When set, the WDT runs continuously.

The WDT has the following features:

• Operates from the LFINTOSC (31 kHz)

• Contains a 16-bit prescaler

When the WDTE bit in the Configuration Word register

is set, the SWDTEN bit of the WDTCON register has no

effect. If WDTE is clear, then the SWDTEN bit can be

used to enable and disable the WDT. Setting the bit will

enable it and clearing the bit will disable it.

• Shares an 8-bit prescaler with Timer0

• Time-out period is from 1 ms to 268 seconds

• Configuration bit and software controlled

WDT is cleared under certain conditions described in

Table 14-7.

The PSA and PS<2:0> bits of the OPTION register

have the same function as in previous versions of the

PIC16F631/677/685/687/689/690 Family of microcon-

trollers. See Section 5.0 “Timer0 Module” for more

information.

14.5.1

WDT OSCILLATOR

The WDT derives its time base from the 31 kHz

LFINTOSC. The LTS bit of the OSCCON register does

not reflect that the LFINTOSC is enabled.

The value of WDTCON is ‘---0 1000’ on all Resets.

This gives a nominal time base of 17 ms.

Note:

When the Oscillator Start-up Timer (OST)

is invoked, the WDT is held in Reset,

because the WDT Ripple Counter is used

by the OST to perform the oscillator delay

count. When the OST count has expired,

the WDT will begin counting (if enabled).

FIGURE 14-9:

WATCHDOG TIMER BLOCK DIAGRAM

0

1

From TMR0 Clock Source

Prescaler⁽¹⁾

16-bit WDT Prescaler

8

PSA

PS<2:0>

To TMR0

31 kHz

LFINTOSC Clock

WDTPS<3:0>

1

0

PSA

WDTE from the Configuration Word Register

SWDTEN from WDTCON

WDT Time-out

Note 1: This is the shared Timer0/WDT prescaler. See Section 5.4 “Prescaler” for more information.

TABLE 14-7: WDT STATUS

Conditions

WDT

WDTE = 0

Cleared

CLRWDTCommand

Oscillator Fail Detected

Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP

Cleared until the end of OST

DS41262D-page 208

PIC16F631/677/685/687/689/690

REGISTER 14-2: WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0

—

U-0

—

U-0

—

R/W-0

R/W-1

R/W-0

SWDTEN⁽¹⁾

bit 0

WDTPS3

WDTPS2

WDTPS1

WDTPS0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-5

bit 4-1

Unimplemented: Read as ‘0’

WDTPS<3:0>: Watchdog Timer Period Select bits

Bit Value = Prescale Rate

0000 = 1:32

0001 = 1:64

0010 = 1:128

0011 = 1:256

0100 = 1:512 (Reset value)

0101 = 1:1024

0110 = 1:2048

0111 = 1:4096

1000 = 1:8192

1001 = 1:16384

1010 = 1:32768

1011 = 1:65536

1100 = reserved

1101 = reserved

1110 = reserved

1111 = reserved

bit 0

SWDTEN: Software Enable or Disable the Watchdog Timer bit⁽¹⁾

1= WDT is turned on

0= WDT is turned off (Reset value)

Note 1: If WDTE Configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE

Configuration bit = 0, then it is possible to turn WDT on/off with this control bit.

TABLE 14-8: SUMMARY OF WATCHDOG TIMER REGISTER

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

(1)

CONFIG

CPD

CP

MCLRE PWRTE

T0SE

WDTE

PSA

FOSC2

PS2

FOSC1

PS1

FOSC0

PS0

—

1111 1111 1111 1111

OPTION_REG RABPU INTEDG T0CS

WDTCON

—

WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000

Legend:

Shaded cells are not used by the Watchdog Timer.

Note 1: See Register 14-1 for operation of all Configuration Word register bits.

DS41262D-page 209

PIC16F631/677/685/687/689/690

When the SLEEPinstruction is being executed, the next

14.6 Power-Down Mode (Sleep)

instruction (PC + 1) is prefetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up

occurs regardless of the state of the GIE bit. If the GIE

bit is clear (disabled), the device continues execution at

the instruction after the SLEEPinstruction. If the GIE bit

is set (enabled), the device executes the instruction

after the SLEEPinstruction, then branches to the inter-

rupt address (0004h). In cases where the execution of

the instruction following SLEEP is not desirable, the

user should have a NOPafter the SLEEPinstruction.

The Power-down mode is entered by executing a

SLEEPinstruction.

If the Watchdog Timer is enabled:

• WDT will be cleared but keeps running.

• PD bit in the STATUS register is cleared.

• TO bit is set.

• Oscillator driver is turned off.

• I/O ports maintain the status they had before

SLEEPwas executed (driving high, low or high-

impedance).

Note:

If the global interrupts are disabled (GIE is

cleared), but any interrupt source has both

its interrupt enable bit and the corresponding

interrupt flag bits set, the device will

immediately wake-up from Sleep. The

SLEEPinstruction is completely executed.

For lowest current consumption in this mode, all I/O pins

should be either at VDD or VSS, with no external circuitry

drawing current from the I/O pin and the comparators

and CVREF should be disabled. I/O pins that are high-

impedance inputs should be pulled high or low externally

to avoid switching currents caused by floating inputs.

The T0CKI input should also be at VDD or VSS for lowest

current consumption. The contribution from on-chip pull-

ups on PORTA should be considered.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

14.6.2

WAKE-UP USING INTERRUPTS

The MCLR pin must be at a logic high level.

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

Note:

It should be noted that a Reset generated

by a WDT time-out does not drive MCLR

pin low.

• If the interrupt occurs before the execution of a

SLEEPinstruction, the SLEEPinstruction will

complete as a NOP. Therefore, the WDT and WDT

prescaler and postscaler (if enabled) will not be

cleared, the TO bit will not be set and the PD bit

will not be cleared.

14.6.1

WAKE-UP FROM SLEEP

The device can wake-up from Sleep through one of the

following events:

1. External Reset input on MCLR pin.

• If the interrupt occurs during or after the execu-

tion of a SLEEPinstruction, the device will imme-

diately wake-up from Sleep. The SLEEP

instruction will be completely executed before the

wake-up. Therefore, the WDT and WDT prescaler

and postscaler (if enabled) will be cleared, the TO

bit will be set and the PD bit will be cleared.

2. Watchdog Timer Wake-up (if WDT was enabled).

3. Interrupt from RA2/INT pin, PORTA change or a

peripheral interrupt.

The first event will cause a device Reset. The two latter

events are considered a continuation of program exe-

cution. The TO and PD bits in the STATUS register can

be used to determine the cause of device Reset. The

PD bit, which is set on power-up, is cleared when Sleep

is invoked. TO bit is cleared if WDT Wake-up occurred.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEPinstruction completes. To

determine whether a SLEEPinstruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

The following peripheral interrupts can wake the device

from Sleep:

1. TMR1 interrupt. Timer1 must be operating as an

asynchronous counter.

To ensure that the WDT is cleared, a CLRWDTinstruction

should be executed before a SLEEPinstruction.

2. ECCP Capture mode interrupt.

3. A/D conversion (when A/D clock source is FRC).

4. EEPROM write operation completion.

5. Comparator output changes state.

6. Interrupt-on-change.

7. External Interrupt from INT pin.

8. EUSART Break detect, I²C slave.

Other peripherals cannot generate interrupts since

during Sleep, no on-chip clocks are present.

DS41262D-page 210

PIC16F631/677/685/687/689/690

FIGURE 14-10:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT⁽⁴⁾

INT pin

(2)

TOST

INTF flag

(INTCON<1>)

Interrupt Latency⁽³⁾

GIE bit

(INTCON<7>)

Processor in

Sleep

Instruction Flow

PC

PC + 1

PC + 2

0004h

0005h

Instruction

Inst(0004h)

Inst(PC + 1)

Inst(PC + 2)

Inst(0005h)

Inst(PC) = Sleep

Inst(PC – 1)

Fetched

Instruction

Executed

Dummy Cycle

Sleep

Inst(PC + 1)

Inst(0004h)

Note 1: XT, HS or LP Oscillator mode assumed.

2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes.

3: GIE = 1assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.

4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.

This allows customers to manufacture boards with

14.7 Code Protection

unprogrammed devices and then program the micro-

controller just before shipping the product. This also

allows the most recent firmware or a custom firmware

to be programmed.

If the code protection bit(s) have not been

programmed, the on-chip program memory can be

read out using ICSP^™for verification purposes.

Note:

The entire data EEPROM and Flash

program memory will be erased when the

code protection is switched from on to off.

See the “PIC12F6XX/16F6XX Memory

Programming Specification” (DS41204)

for more information.

The device is placed into a Program/Verify mode by

holding the RA0/AN0/C1IN+/ICSPDAT/ULPWU and

RA1/AN1/C12IN-/VREF/ICSPCLK pins low, while rais-

ing the MCLR (VPP) pin from VIL to VIHH. See the

“PIC12F6XX/16F6XX Memory Programming Specifi-

cation” (DS41204) for more information. RA0 becomes

the programming data and RA1 becomes the

programming clock. Both RA0 and RA1 are Schmitt

Trigger inputs in this mode.

14.8 ID Locations

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

not accessible during normal execution but are

readable and writable during Program/Verify mode.

Only the Least Significant 7 bits of the ID locations are

used.

After Reset, to place the device into Program/Verify

mode, the Program Counter (PC) is at location 00h. A

6-bit command is then supplied to the device.

Depending on the command, 14 bits of program data

are then supplied to or from the device, depending on

whether the command was a load or a read. For

complete details of serial programming, please refer to

the “PIC12F6XX/16F6XX Memory Programming

Specification” (DS41204).

14.9 In-Circuit Serial Programming

The PIC16F631/677/685/687/689/690 microcontrollers

can be serially programmed while in the end applica-

tion circuit. This is simply done with two lines for clock

and data and three other lines for:

A typical In-Circuit Serial Programming connection is

shown in Figure 14-11.

• power

• ground

• programming voltage

DS41262D-page 211

PIC16F631/677/685/687/689/690

FIGURE 14-11:

TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING

CONNECTION

To Normal

Connections

External

Connector

Signals

PIC16F631/677/

685/687/689/690

*

+5V

0V

VDD

VSS

VPP

RA3/MCLR/VPP

RA1

RA0

CLK

Data I/O

*

To Normal

Connections

*

Isolation devices (as required)

DS41262D-page 212

PIC16F631/677/685/687/689/690

TABLE 15-1: OPCODE FIELD

15.0 INSTRUCTION SET SUMMARY

DESCRIPTIONS

The PIC16F690 instruction set is highly orthogonal and

is comprised of three basic categories:

Field

Description

f

W

b

Register file address (0x00 to 0x7F)

Working register (accumulator)

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations

Bit address within an 8-bit file register

Literal field, constant data or label

k

Each PIC16 instruction is a 14-bit word divided into an

opcode, which specifies the instruction type and one or

more operands, which further specify the operation of

the instruction. The formats for each of the categories

is presented in Figure 15-1, while the various opcode

fields are summarized in Table 15-1.

x

Don’t care location (= 0or 1).

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip software tools.

d

Destination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1.

Table 15-2 lists the instructions recognized by the

MPASM^TMassembler.

For byte-oriented instructions, ‘f’ represents a file

register designator and ‘d’ represents a destination

designator. The file register designator specifies which

file register is to be used by the instruction.

PC

TO

C

Program Counter

Time-out bit

Carry bit

DC

Z

Digit carry bit

Zero bit

The destination designator specifies where the result of

the operation is to be placed. If ‘d’ is zero, the result is

placed in the W register. If ‘d’ is one, the result is placed

in the file register specified in the instruction.

PD

Power-down bit

FIGURE 15-1:

GENERAL FORMAT FOR

INSTRUCTIONS

For bit-oriented instructions, ‘b’ represents a bit field

designator, which selects the bit affected by the

operation, while ‘f’ represents the address of the file in

which the bit is located.

Byte-oriented file register operations

13

8

7

6

0

For literal and control operations, ‘k’ represents an

8-bit or 11-bit constant, or literal value.

OPCODE

d

f (FILE #)

d = 0for destination W

d = 1for destination f

f = 7-bit file register address

One instruction cycle consists of four oscillator periods;

for an oscillator frequency of 4 MHz, this gives a normal

instruction execution time of 1 μs. All instructions are

executed within a single instruction cycle, unless a

conditional test is true, or the program counter is

changed as a result of an instruction. When this occurs,

the execution takes two instruction cycles, with the

second cycle executed as a NOP.

Bit-oriented file register operations

13 10 9

b (BIT #)

7

6

0

OPCODE

f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies a

hexadecimal digit.

Literal and control operations

General

13

8

7

0

15.1 Read-Modify-Write Operations

OPCODE

k (literal)

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (RMW)

operation. The register is read, the data is modified,

and the result is stored according to either the instruc-

tion, or the destination designator ‘d’. A read operation

is performed on a register even if the instruction writes

to that register.

k = 8-bit immediate value

CALLand GOTOinstructions only

13 11 10

OPCODE

k = 11-bit immediate value

k (literal)

For example, a CLRF PORTA instruction will read

PORTA, clear all the data bits, then write the result back

to PORTA. This example would have the unintended

consequence of clearing the condition that set the RAIF

flag.

DS41262D-page 213

PIC16F631/677/685/687/689/690

TABLE 15-2: PIC16F684 INSTRUCTION SET

14-Bit Opcode

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

MSb

LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

f, d

f

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

1

1(2)

1

1(2)

1

00 0111 dfff ffff C, DC, Z

1, 2

2

00 0101 dfff ffff

00 0001 lfff ffff

00 0001 0xxx xxxx

00 1001 dfff ffff

00 0011 dfff ffff

00 1011 dfff ffff

00 1010 dfff ffff

00 1111 dfff ffff

00 0100 dfff ffff

00 1000 dfff ffff

00 0000 lfff ffff

00 0000 0xx0 0000

00 1101 dfff ffff

00 1100 dfff ffff

Z

–

f, d

f

1, 2

1, 2, 3

1, 2

1, 2, 3

1, 2

Z

Move W to f

No Operation

–

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

C

1, 2

00 0010 dfff ffff C, DC, Z

00 1110 dfff ffff

00 0110 dfff ffff

Z

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1

1 (2)

01 00bb bfff ffff

1, 2

3

01 01bb bfff ffff

01 10bb bfff ffff

01 11bb bfff ffff

3

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

k

–

k

–

k

–

k

Add literal and W

AND literal with W

Call Subroutine

Clear Watchdog Timer

Go to address

1

2

1

2

1

2

1

11 111x kkkk kkkk C, DC, Z

11 1001 kkkk kkkk

10 0kkk kkkk kkkk

Z

00 0000 0110 0100 TO, PD

10 1kkk kkkk kkkk

Inclusive OR literal with W

Move literal to W

11 1000 kkkk kkkk

11 00xx kkkk kkkk

00 0000 0000 1001

11 01xx kkkk kkkk

00 0000 0000 1000

Z

Return from interrupt

Return with literal in W

Return from Subroutine

Go into Standby mode

Subtract Wfrom literal

Exclusive OR literal with W

00 0000 0110 0011 TO, PD

11 110x kkkk kkkk C, DC, Z

11 1010 kkkk kkkk

Z

Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external

device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if

assigned to the Timer0 module.

3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second

cycle is executed as a NOP.

DS41262D-page 214

PIC16F631/677/685/687/689/690

15.2 Instruction Descriptions

BCF

Bit Clear f

ADDLW

Add literal and W

Syntax:

[ label ] BCF f,b

Syntax:

[ label ] ADDLW

0 ≤ k ≤ 255

k

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

Operation:

Status Affected:

Description:

(W) + k → (W)

C, DC, Z

Operation:

0→ (f<b>)

Status Affected:

Description:

None

The contents of the W register

are added to the eight-bit literal ‘k’

and the result is placed in the

W register.

Bit ‘b’ in register ‘f’ is cleared.

BSF

Bit Set f

ADDWF

Add W and f

Syntax:

[ label ] BSF f,b

Syntax:

[ label ] ADDWF f,d

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

1→ (f<b>)

Operation:

(W) + (f) → (destination)

Status Affected:

Description:

None

Status Affected: C, DC, Z

Bit ‘b’ in register ‘f’ is set.

Description:

Add the contents of the W register

with register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W register. If

‘d’ is ‘1’, the result is stored back

in register ‘f’.

BTFSC

Bit Test f, Skip if Clear

ANDLW

AND literal with W

Syntax:

[ label ] BTFSC f,b

Syntax:

[ label ] ANDLW

0 ≤ k ≤ 255

k

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

Operation:

Status Affected:

Description:

(W) .AND. (k) → (W)

Operation:

skip if (f<b>) = 0

Z

Status Affected: None

The contents of W register are

AND’ed with the eight-bit literal

‘k’. The result is placed in the W

register.

Description: If bit ‘b’ in register ‘f’ is ‘1’, the next

instruction is executed.

If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is discarded, and a NOP

is executed instead, making this a

two-cycle instruction.

ANDWF

AND W with f

Syntax:

[ label ] ANDWF f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(W) .AND. (f) → (destination)

Status Affected:

Description:

Z

AND the W register with register

‘f’. If ‘d’ is ‘0’, the result is stored in

the W register. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

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CLRWDT

Clear Watchdog Timer

BTFSS

Bit Test f, Skip if Set

Syntax:

[ label ] CLRWDT

Syntax:

[ label ] BTFSS f,b

Operands:

Operation:

None

Operands:

0 ≤ f ≤ 127

0 ≤ b < 7

00h → WDT

0→ WDT prescaler,

1→ TO

Operation:

skip if (f<b>) = 1

Status Affected: None

1→ PD

Description:

If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is executed.

Status Affected: TO, PD

Description:

CLRWDTinstruction resets the

Watchdog Timer. It also resets the

prescaler of the WDT.

If bit ‘b’ is ‘1’, then the next

instruction is discarded and a NOP

is executed instead, making this a

two-cycle instruction.

Status bits TO and PD are set.

CALL

Call Subroutine

COMF

Complement f

Syntax:

[ label ] CALL k

0 ≤ k ≤ 2047

Syntax:

[ label ] COMF f,d

Operands:

Operation:

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

(PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Operation:

(f) → (destination)

Status Affected:

Description:

Z

Status Affected: None

The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’,

the result is stored back in

register ‘f’.

Description:

Call Subroutine. First, return

address (PC + 1) is pushed onto

the stack. The eleven-bit

immediate address is loaded into

PC bits <10:0>. The upper bits of

the PC are loaded from PCLATH.

CALLis a two-cycle instruction.

CLRF

Clear f

DECF

Decrement f

Syntax:

[ label ] CLRF

0 ≤ f ≤ 127

f

Syntax:

[ label ] DECF f,d

Operands:

Operation:

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

00h → (f)

1→ Z

Operation:

(f) - 1 → (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

The contents of register ‘f’ are

cleared and the Z bit is set.

Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

CLRW

Clear W

Syntax:

[ label ] CLRW

Operands:

Operation:

None

00h → (W)

1→ Z

Status Affected:

Description:

Z

W register is cleared. Zero bit (Z)

is set.

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DECFSZ

Decrement f, Skip if 0

INCFSZ

Increment f, Skip if 0

Syntax:

[ label ] DECFSZ f,d

Syntax:

[ label ] INCFSZ f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(f) - 1 → (destination);

skip if result = 0

Operation:

(f) + 1 → (destination),

skip if result = 0

Status Affected: None

Description:

The contents of register ‘f’ are

Description:

The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

If the result is ‘1’, the next

instruction is executed. If the

result is ‘0’, then a NOPis

executed instead, making it a

two-cycle instruction.

If the result is ‘1’, the next

instruction is executed. If the

result is ‘0’, a NOPis executed

instead, making it a two-cycle

instruction.

GOTO

Unconditional Branch

IORLW

Inclusive OR literal with W

Syntax:

[ label ] GOTO k

0 ≤ k ≤ 2047

Syntax:

[ label ] IORLW k

0 ≤ k ≤ 255

Operands:

Operation:

Operands:

Operation:

Status Affected:

Description:

k → PC<10:0>

PCLATH<4:3> → PC<12:11>

(W) .OR. k → (W)

Z

Status Affected: None

The contents of the W register are

OR’ed with the eight-bit literal ‘k’.

The result is placed in the

W register.

Description:

GOTOis an unconditional branch.

The eleven-bit immediate value is

loaded into PC bits <10:0>. The

upper bits of PC are loaded from

PCLATH<4:3>. GOTOis a

two-cycle instruction.

IORWF

Inclusive OR W with f

INCF

Increment f

Syntax:

[ label ] IORWF f,d

Syntax:

[ label ] INCF f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(W) .OR. (f) → (destination)

Operation:

(f) + 1 → (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

Inclusive OR the W register with

register ‘f’. If ‘d’ is ‘0’, the result is

placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

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MOVWF

Move W to f

[ label ] MOVWF

0 ≤ f ≤ 127

(W) → (f)

MOVF

Move f

Syntax:

f

Syntax:

Operands:

[ label ] MOVF f,d

Operands:

Operation:

Status Affected:

Description:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(f) → (dest)

None

Status Affected:

Description:

Z

Move data from W register to

register ‘f’.

The contents of register ‘f’ is

moved to a destination dependent

upon the status of ‘d’. If d = 0,

destination is W register. If d = 1,

the destination is file register ‘f’

itself. d = 1is useful to test a file

register since status flag Z is

affected.

Words:

1

Cycles:

Example:

MOVW

F

OPTION

Before Instruction

OPTION = 0xFF

Words:

1

W

=

0x4F

After Instruction

Cycles:

Example:

OPTION = 0x4F

W

MOVF

FSR, 0

=

0x4F

After Instruction

W

=

value in FSR

register

Z

=

1

MOVLW

Syntax:

Move literal to W

NOP

No Operation

[ label ] MOVLW k

0 ≤ k ≤ 255

Syntax:

[ label ] NOP

Operands:

Operation:

Operands:

Operation:

Status Affected:

Description:

Words:

None

k → (W)

No operation

Status Affected: None

None

Description:

The eight-bit literal ‘k’ is loaded into

W register. The “don’t cares” will

assemble as ‘0’s.

No operation.

1

Cycles:

1

Words:

1

NOP

Example:

Cycles:

Example:

MOVLW

0x5A

After Instruction

W

=

0x5A

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RETFIE

Return from Interrupt

[ label ] RETFIE

None

RETLW

Return with literal in W

[ label ] RETLW k

0 ≤ k ≤ 255

Syntax:

Operands:

Operation:

Operands:

Operation:

TOS → PC,

1→ GIE

k → (W);

TOS → PC

Status Affected:

Description:

None

Status Affected:

Description:

None

Return from Interrupt. Stack is

POPed and Top-of-Stack (TOS) is

loaded in the PC. Interrupts are

enabled by setting Global

Interrupt Enable bit, GIE

The W register is loaded with the

eight-bit literal ‘k’. The program

counter is loaded from the top of

the stack (the return address).

This is a two-cycle instruction.

(INTCON<7>). This is a two-cycle

instruction.

Words:

1

2

Cycles:

Example:

Words:

1

CALL TABLE;W contains

table

Cycles:

Example:

2

RETFIE

;offset value

TABLE

•

;W now has

;table value

After Interrupt

PC = TOS

GIE =

1

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

•

RETLW kn ;End of table

Before Instruction

W

=

0x07

After Instruction

W

=

value of k8

RETURN

Return from Subroutine

Syntax:

[ label ] RETURN

None

Operands:

Operation:

TOS → PC

Status Affected: None

Description: Return from subroutine. The stack

is POPed and the top of the stack

(TOS) is loaded into the program

counter. This is a two-cycle

instruction.

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RLF

Rotate Left f through Carry

SLEEP

Enter Sleep mode

[ label ] SLEEP

None

Syntax:

Operands:

[ label ]

RLF f,d

Syntax:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

00h → WDT,

0→ WDT prescaler,

1→ TO,

Operation:

See description below

C

Status Affected:

Description:

0→ PD

The contents of register ‘f’ are

rotated one bit to the left through

the Carry flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

Status Affected:

Description:

TO, PD

The power-down Status bit, PD is

cleared. Time-out Status bit, TO

is set. Watchdog Timer and its

prescaler are cleared.

The processor is put into Sleep

mode with the oscillator stopped.

C

Register f

Words:

1

Cycles:

Example:

RLF

REG1,0

Before Instruction

REG1

C

=

1110 0110

0

After Instruction

REG1

W

C

=

1110 0110

1100 1100

1

SUBLW

Subtract W from literal

RRF

Rotate Right f through Carry

Syntax:

[ label ] SUBLW k

0 ≤ k ≤ 255

Syntax:

[ label ] RRF f,d

Operands:

Operation:

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

k - (W) → (W)

Operation:

See description below

C

Status Affected: C, DC, Z

Status Affected:

Description:

Description: The W register is subtracted (2’s

complement method) from the

eight-bit literal ‘k’. The result is

placed in the W register.

The contents of register ‘f’ are

rotated one bit to the right through

the Carry flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is placed

back in register ‘f’.

C = 0

W > k

C = 1

W ≤ k

DC = 0

DC = 1

W<3:0> > k<3:0>

W<3:0> ≤ k<3:0>

C

Register f

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SUBWF

Subtract W from f

XORLW

Exclusive OR literal with W

Syntax:

[ label ] SUBWF f,d

Syntax:

[ label ] XORLW k

0 ≤ k ≤ 255

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

Status Affected:

Description:

(W) .XOR. k → (W)

Z

Operation:

(f) - (W) → (destination)

Status Affected: C, DC, Z

The contents of the W register

are XOR’ed with the eight-bit

literal ‘k’. The result is placed in

the W register.

Description:

Subtract (2’s complement method)

W register from register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

C = 0

W > f

C = 1

W ≤ f

DC = 0

DC = 1

W<3:0> > f<3:0>

W<3:0> ≤ f<3:0>

XORWF

Exclusive OR W with f

SWAPF

Swap Nibbles in f

Syntax:

[ label ] XORWF f,d

Syntax:

[ label ] SWAPF f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(W) .XOR. (f) → (destination)

Operation:

(f<3:0>) → (destination<7:4>),

(f<7:4>) → (destination<3:0>)

Status Affected:

Description:

Z

Status Affected: None

Exclusive OR the contents of the

W register with register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

Description: The upper and lower nibbles of

register ‘f’ are exchanged. If ‘d’ is

‘0’, the result is placed in the W

register. If ‘d’ is ‘1’, the result is

placed in register ‘f’.

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NOTES:

DS41262D-page 222

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16.1 MPLAB Integrated Development

Environment Software

16.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers are supported with a full

range of hardware and software development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• Assemblers/Compilers/Linkers

- MPASM^TMAssembler

• A single graphical interface to all debugging tools

- Simulator

- MPLAB C18 and MPLAB C30 C Compilers

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- Programmer (sold separately)

- Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

• Emulators

• Customizable data windows with direct edit of

contents

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debugger

• High-level source code debugging

• Visual device initializer for easy register

initialization

- MPLAB ICD 2

• Mouse over variable inspection

• Device Programmers

• Drag and drop variables from source to watch

windows

- PICSTART^®Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Extensive on-line help

• Integration of select third party tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

The MPLAB IDE allows you to:

• Edit your source files (either assembly or C)

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools

(automatically updates all project information)

• Debug using:

- Source files (assembly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

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16.2 MPASM Assembler

16.5 MPLAB ASM30 Assembler, Linker

and Librarian

The MPASM Assembler is a full-featured, universal

macro assembler for all PIC MCUs.

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• User-defined macros to streamline

assembly code

• Rich directive set

• Conditional assembly for multi-purpose

source files

• Flexible macro language

• MPLAB IDE compatibility

• Directives that allow complete control over the

assembly process

16.6 MPLAB SIM Software Simulator

16.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC^®DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI

C

compilers for

Microchip’s PIC18 and PIC24 families of microcontrol-

lers and the dsPIC30 and dsPIC33 family of digital sig-

nal controllers. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

16.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

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16.7 MPLAB ICE 2000

High-Performance

16.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

In-Circuit Emulator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PIC

microcontrollers. Software control of the MPLAB ICE

2000 In-Circuit Emulator is advanced by the MPLAB

Integrated Development Environment, which allows

editing, building, downloading and source debugging

from a single environment.

USB interface. This tool is based on the Flash PIC

MCUs and can be used to develop for these and other

PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes

the in-circuit debugging capability built into the Flash

devices. This feature, along with Microchip’s In-Circuit

Serial Programming^TM(ICSP^TM) protocol, offers cost-

effective, in-circuit Flash debugging from the graphical

user interface of the MPLAB Integrated Development

Environment. This enables a designer to develop and

debug source code by setting breakpoints, single step-

ping and watching variables, and CPU status and

peripheral registers. Running at full speed enables

testing hardware and applications in real time. MPLAB

ICD 2 also serves as a development programmer for

selected PIC devices.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing features. Interchangeable processor modules allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PIC microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft^®Windows^®32-bit operating system were

chosen to best make these features available in a

simple, unified application.

16.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an SD/MMC card for

file storage and secure data applications.

16.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC^®and MCU devices. It debugs and

programs PIC^®and dsPIC^®Flash microcontrollers with

the easy-to-use, powerful graphical user interface of the

MPLAB Integrated Development Environment (IDE),

included with each kit.

The MPLAB REAL ICE probe is connected to the design

engineer’s PC using a high-speed USB 2.0 interface and

is connected to the target with either a connector

compatible with the popular MPLAB ICD 2 system

(RJ11) or with the new high speed, noise tolerant, low-

voltage differential signal (LVDS) interconnection

(CAT5).

MPLAB REAL ICE is field upgradeable through future

firmware downloads in MPLAB IDE. In upcoming

releases of MPLAB IDE, new devices will be supported,

and new features will be added, such as software break-

points and assembly code trace. MPLAB REAL ICE

offers significant advantages over competitive emulators

including low-cost, full-speed emulation, real-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables.

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16.11 PICSTART Plus Development

Programmer

16.13 Demonstration, Development and

Evaluation Boards

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PIC devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76X, may be supported with an adapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

16.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer and selected Flash device debugger with

an easy-to-use interface for programming many of

Microchip’s baseline, mid-range and PIC18F families of

Flash memory microcontrollers. The PICkit 2 Starter Kit

includes a prototyping development board, twelve

sequential lessons, software and HI-TECH’s PICC™

Lite C compiler, and is designed to help get up to speed

quickly using PIC^®microcontrollers. The kit provides

everything needed to program, evaluate and develop

applications using Microchip’s powerful, mid-range

Flash memory family of microcontrollers.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

®

for analog filter design, KEELOQ security ICs, CAN,

IrDA^®, PowerSmart^®battery management, SEEVAL^®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

and the latest “Product Selector Guide” (DS00148) for

the complete list of demonstration, development and

evaluation kits.

DS41262D-page 226

PIC16F631/677/685/687/689/690

17.0 ELECTRICAL SPECIFICATIONS

(†)

Absolute Maximum Ratings

Ambient temperature under bias..........................................................................................................-40° to +125°C

Storage temperature ........................................................................................................................ -65°C to +150°C

Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V

Voltage on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V

Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)

Total power dissipation⁽¹⁾............................................................................................................................... 800 mW

Maximum current out of VSS pin ..................................................................................................................... 300 mA

Maximum current into VDD pin ........................................................................................................................ 250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)............................................................................................................... 20 mA

Output clamp current, IOK (Vo < 0 or Vo >VDD)......................................................................................................... 20 mA

Maximum output current sunk by any I/O pin....................................................................................................25 mA

Maximum output current sourced by any I/O pin .............................................................................................. 25 mA

Maximum current sunk by PORTA, PORTB and PORTC (combined)............................................................ 200 mA

Maximum current sourced PORTA, PORTB and PORTC (combined)............................................................ 200 mA

Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOL x IOL).

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Note:

Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.

Thus, a series resistor of 50-100 Ω should be used when applying a “low” level to the MCLR pin, rather than

pulling this pin directly to VSS.

DS41262D-page 227

PIC16F631/677/685/687/689/690

FIGURE 17-1:

PIC16F631/677/685/687/689/690 VOLTAGE-FREQUENCY GRAPH,

-40°C ≤ TA ≤ +125°C

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

0

8

10

20

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

FIGURE 17-2:

HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE

125

85

60

25

0

± 5%

± 2%

± 1%

2.0

2.5

3.0

3.5

4.0

VDD (V)

4.5

5.0

5.5

DS41262D-page 228

PIC16F631/677/685/687/689/690

17.1 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial)

PIC16F631/677/685/687/689/690-E (Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

DC CHARACTERISTICS

Param

Sym

Characteristic

Min Typ† Max Units

Conditions

No.

VDD

Supply Voltage

2.0

3.0

4.5

—

5.5

V

FOSC < = 8 MHz: HFINTOSC, EC

FOSC < = 4 MHz

FOSC < = 10 MHz

D001

D001C

D001D

FOSC < = 20 MHz

D002* VDR

RAM Data Retention

Voltage⁽¹⁾

1.5

—

V

Device in Sleep mode

D003 VPOR

VDD Start Voltage to

ensure internal Power-on

Reset signal

—

VSS

—

V

See Section 14.2.1 “Power-on Reset

(POR)” for details.

D004* SVDD

VDD Rise Rate to ensure

internal Power-on Reset

signal

0.05

—

V/ms See Section 14.2.1 “Power-on Reset

(POR)” for details.

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

DS41262D-page 229

PIC16F631/677/685/687/689/690

17.2 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

Conditions

Note

Param

No.

Device Characteristics

Min

Typ†

Max

Units

VDD

(1, 2)

D010

D011*

D012

D013*

D014

D015

D016*

D017

D018

Supply Current (IDD)

—

9

TBD

240

380

550

360

650

1.1

μA

mA

μA

mA

μA

mA

μA

mA

μA

mA

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

4.5

5.0

FOSC = 32 kHz

LP Oscillator mode

18

35

140

220

380

260

420

0.8

130

215

360

220

375

0.65

8

FOSC = 1 MHz

XT Oscillator mode

FOSC = 4 MHz

XT Oscillator mode

220

360

520

340

550

1.0

FOSC = 1 MHz

EC Oscillator mode

FOSC = 4 MHz

EC Oscillator mode

20

FOSC = 31 kHz

LFINTOSC mode

16

40

31

65

340

500

0.8

410

700

1.30

230

400

0.63

2.6

2.8

450

700

1.2

FOSC = 4 MHz

HFINTOSC mode

650

950

1.65

400

680

1.1

FOSC = 8 MHz

HFINTOSC mode

FOSC = 4 MHz

(3)

EXTRC mode

D019

3.25

3.35

FOSC = 20 MHz

HS Oscillator mode

Legend:

TBD = To Be Determined

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended

by the formula IR = VDD/2REXT (mA) with REXT in kΩ.

4: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

5: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

DS41262D-page 230

PIC16F631/677/685/687/689/690

17.2 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial) (Continued)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

Conditions

Param

No.

Device Characteristics

Power-down Base

Min

Typ†

Max

Units

VDD

Note

D020

—

0.15

0.20

0.35

90

1.2

1.5

1.8

500

2.2

4.0

7.0

60

μA

nA

μA

2.0

3.0

5.0

3.0

2.0

3.0

5.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

3.0

5.0

3.0

5.0

WDT, BOR, Comparators, VREF and

T1OSC disabled

(2)

Current(IPD)

-40°C ≤ TA ≤ +25°C

(1)

D021

1.0

2.0

3.0

42

WDT Current

(1)

D022

D023

BOR Current

85

122

45

(1)

32

Comparator Current , both

comparators enabled

60

78

120

30

160

36

(1)

D024

CVREF Current (high range)

45

55

75

95

(1)

D024a*

D025

39

47

CVREF Current (low range)

59

72

98

124

TBD

1.6

1.9

TBD

4.0

4.6

6.0

0.30

0.36

TBD

T1OSC Current

(1)

D026

A/D Current , no conversion in

progress

D027

VP6 Current

Legend:

TBD = To Be Determined

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended

by the formula IR = VDD/2REXT (mA) with REXT in kΩ.

4: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

5: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

DS41262D-page 231

PIC16F631/677/685/687/689/690

17.3 DC Characteristics: PIC16F631/677/685/687/689/690-E (Extended)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +125°C for extended

Conditions

Note

Param

No.

Device Characteristics

Min

Typ†

Max

Units

VDD

(1, 2)

D010E

D011E*

D012E

D013E*

D014E

D015E

D016E*

D017E

D018E

Supply Current (IDD)

—

9

TBD

240

380

550

360

650

1.1

μA

mA

μA

mA

μA

mA

μA

mA

μA

mA

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

4.5

5.0

FOSC = 32 kHz

LP Oscillator mode

18

35

140

220

380

260

420

0.8

FOSC = 1 MHz

XT Oscillator mode

FOSC = 4 MHz

XT Oscillator mode

130

215

360

220

375

0.65

8

220

360

520

340

550

1.0

FOSC = 1 MHz

EC Oscillator mode

FOSC = 4 MHz

EC Oscillator mode

20

FOSC = 31 kHz

LFINTOSC mode

16

40

31

65

340

500

0.8

450

700

1.2

FOSC = 4 MHz

HFINTOSC mode

410

700

1.30

230

400

0.63

2.6

650

950

1.65

400

680

1.1

FOSC = 8 MHz

HFINTOSC mode

FOSC = 4 MHz

(3)

EXTRC mode

D019E

3.25

3.35

FOSC = 20 MHz

HS Oscillator mode

2.8

Legend:

TBD = To Be Determined

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended

by the formula IR = VDD/2REXT (mA) with REXT in kΩ.

4: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

5: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

DS41262D-page 232

PIC16F631/677/685/687/689/690

17.3 DC Characteristics: PIC16F631/677/685/687/689/690-E (Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C for extended

DC CHARACTERISTICS

Conditions

Param

No.

Device Characteristics

Min

Typ†

Max

Units

VDD

Note

D020E

Power-down Base

Current(IPD)

—

0.15

0.20

0.35

90

1.2

1.5

1.8

500

2.2

4.0

7.0

60

μA

nA

μA

2.0

3.0

5.0

3.0

2.0

3.0

5.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

3.0

5.0

3.0

5.0

WDT, BOR, Comparators, VREF and

T1OSC disabled

(2)

-40°C ≤ TA ≤ +25°C

(1)

D021E

1.0

2.0

3.0

42

WDT Current

(1)

D022E

D023E

BOR Current

85

122

45

(1)

32

Comparator Current , both

comparators enabled

60

78

120

30

160

36

(1)

D024E

CVREF Current (high range)

45

55

75

95

(1)

D024AE*

D025E

39

47

CVREF Current (low range)

59

72

98

124

TBD

1.6

1.9

TBD

4.0

4.6

6.0

0.30

0.36

TBD

T1OSC Current

(1)

D026E

D027E

Legend:

A/D Current , no conversion in

progress

VP6 Current

TBD = To Be Determined

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended

by the formula IR = VDD/2REXT (mA) with REXT in kΩ.

4: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

5: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

DS41262D-page 233

PIC16F631/677/685/687/689/690

17.4 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial)

PIC16F631/677/685/687/689/690-E (Extended)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

Sym

No.

Characteristic

Min

Typ†

Max

Units

Conditions

VIL

Input Low Voltage

I/O Port:

with TTL buffer

D030

D030A

D031

D032

D033

D033A

Vss

VSS

—

0.8

V

4.5V ≤ VDD ≤ 5.5V

0.15 VDD

0.2 VDD

0.3

2.0V ≤ VDD ≤ 4.5V

2.0V ≤ VDD ≤ 5.5V

with Schmitt Trigger buffer

(1)

MCLR, OSC1 (RC mode)

OSC1 (XT and LP modes)

OSC1 (HS mode)

Input High Voltage

I/O Ports:

0.3 VDD

VIH

—

D040

with TTL buffer

2.0

0.25 VDD + 0.8

0.8 VDD

1.6

VDD

V

4.5V ≤ VDD ≤ 5.5V

2.0V ≤ VDD ≤ 4.5V

2.0V ≤ VDD ≤ 5.5V

D040A

D041

with Schmitt Trigger buffer

MCLR

D042

D043

OSC1 (XT and LP modes)

OSC1 (HS mode)

D043A

D043B

0.7 VDD

0.9 VDD

OSC1 (RC mode)

(Note 1)

(2)

IIL

Input Leakage Current

D060

I/O ports

—

0.1

1

μA VSS ≤ VPIN ≤ VDD,

Pin at high-impedance

(3)

D061

D063

MCLR

—

0.1

5

μA VSS ≤ VPIN ≤ VDD

OSC1

μA VSS ≤ VPIN ≤ VDD, XT, HS and

LP oscillator configuration

D070* IPUR

VOL

PORTA Weak Pull-up Current

50

—

250

—

400

0.6

—

μA VDD = 5.0V, VPIN = VSS

(5)

Output Low Voltage

D080

I/O ports

V

IOL = 8.5 mA, VDD = 4.5V (Ind.)

IOH = -3.0 mA, VDD = 4.5V (Ind.)

(5)

VOH

Output High Voltage

D090

I/O ports

VDD – 0.7

—

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external

clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

4: See Section 10.2.1 “Using the Data EEPROM” for additional information.

5: Including OSC2 in CLKOUT mode.

DS41262D-page 234

PIC16F631/677/685/687/689/690

17.4 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial)

PIC16F631/677/685/687/689/690-E (Extended) (Continued)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

Sym

No.

Characteristic

Min

Typ†

Max

Units

Conditions

D100

IULP

Ultra Low-Power Wake-up

Current

—

200

—

nA See Application Note AN879,

“Using the Microchip Ultra

Low-Power Wake-up Module”

(DS00879)

Capacitive Loading Specs on

Output Pins

D101* COSC2 OSC2 pin

—

15

50

pF In XT, HS and LP modes when

external clock is used to drive

OSC1

D101A* CIO

All I/O pins

pF

Data EEPROM Memory

Byte Endurance

VDD for Read/Write

D120

ED

100K

10K

1M

100K

—

E/W -40°C ≤ TA ≤ +85°C

E/W +85°C ≤ TA ≤ +125°C

D120A ED

D121

VDRW

VMIN

5.5

V

Using EECON1 to read/write

VMIN = Minimum operating

voltage

D122

D123

TDEW

Erase/Write Cycle Time

Characteristic Retention

—

5

6

ms

TRETD

40

—

Year Provided no other specifications

are violated

D124

TREF

Number of Total Erase/Write

Cycles before Refresh

1M

10M

—

E/W -40°C ≤ TA ≤ +85°C

(4)

Program Flash Memory

Cell Endurance

D130

EP

10K

1K

100K

10K

—

E/W -40°C ≤ TA ≤ +85°C

E/W +85°C ≤ TA ≤ +125°C

D130A ED

Cell Endurance

D131

VPR

VDD for Read

VMIN

5.5

V

VMIN = Minimum operating

voltage

D132

D133

D134

VPEW

TPEW

TRETD

VDD for Erase/Write

4.5

—

2

5.5

2.5

—

V

Erase/Write cycle time

Characteristic Retention

ms

40

—

Year Provided no other specifications

are violated

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external

clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

4: See Section 10.2.1 “Using the Data EEPROM” for additional information.

5: Including OSC2 in CLKOUT mode.

DS41262D-page 235

PIC16F631/677/685/687/689/690

17.5 Thermal Considerations

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C ≤ TA ≤ +125°C

Param

Sym

No.

Characteristic

Typ

Units

Conditions

20-pin PDIP package

TH01

θ^JA

Thermal Resistance

Junction to Ambient

62.4

85.2

108.1

40

C/W

C

20-pin SOIC package

20-pin SSOP package

20-pin QFN 4x4mm package

20-pin PDIP package

TH02

θ^JC

Thermal Resistance

Junction to Case

28.1

24.2

32.2

2.5

20-pin SOIC package

20-pin SSOP package

20-pin QFN 4x4mm package

For derated power calculations

PD = PINTERNAL + PI/O

TH03

TH04

TH05

TDIE

PD

Die Temperature

Power Dissipation

150

—

W

PINTERNAL Internal Power Dissipation

—

W

PINTERNAL = IDD x VDD

(NOTE 1)

TH06

TH07

PI/O

I/O Power Dissipation

Derated Power

—

W

PI/O = Σ (IOL * VOL) + Σ (IOH * (VDD - VOH))

PDER = PDMAX (TDIE - TA)/θJA

(NOTE 2, 3)

PDER

Note 1: IDD is current to run the chip alone without driving any load on the output pins.

2: TA = Ambient Temperature.

3: Maximum allowable power dissipation is the lower value of either the absolute maximum total power

dissipation or derated power.

DS41262D-page 236

PIC16F631/677/685/687/689/690

17.6

Timing Parameter Symbology

The timing parameter symbols have been created with

one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase letters (pp) and their meanings:

pp

cc

T

Time

CCP1

CLKOUT

CS

osc

rd

OSC1

RD

ck

cs

di

rw

sc

ss

t0

RD or WR

SCK

SDI

do

dt

SDO

SS

Data in

I/O Port

MCLR

T0CKI

T1CKI

WR

io

t1

mc

wr

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (High-impedance)

Low

Valid

L

High-impedance

FIGURE 17-3:

LOAD CONDITIONS

Load Condition

CL

VSS

Legend: CL

=

50 pF for all pins

15 pF for OSC2 output

DS41262D-page 237

PIC16F631/677/685/687/689/690

17.7 AC Characteristics: PIC16F631/677/685/687/689/690 (Industrial, Extended)

FIGURE 17-4:

CLOCK TIMING

Q4

Q1

Q2

Q3

Q4

Q1

OSC1/CLKIN

OS02

OS04

OS03

OSC2/CLKOUT

(LP,XT,HS Modes)

OSC2/CLKOUT

(CLKOUT Mode)

TABLE 17-1: CLOCK OSCILLATOR TIMING REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C ≤ TA ≤ +125°C

Param

Sym

No.

Characteristic

Min

Typ†

Max

Units

kHz

Conditions

(1)

OS01

FOSC

TOSC

TCY

External CLKIN Frequency

DC

—

37

4

LP Oscillator mode

MHz XT Oscillator mode

MHz HS Oscillator mode

MHz EC Oscillator mode

—

20

—

4

—

(1)

Oscillator Frequency

32.768

—

kHz

LP Oscillator mode

0.1

1

MHz XT Oscillator mode

MHz HS Oscillator mode

MHz RC Oscillator mode

—

20

4

DC

27

250

50

—

(1)

OS02

External CLKIN Period

—

∞

μs

ns

μs

ns

μs

ns

LP Oscillator mode

XT Oscillator mode

HS Oscillator mode

EC Oscillator mode

LP Oscillator mode

XT Oscillator mode

HS Oscillator mode

RC Oscillator mode

TCY = 4/FOSC

—

(1)

Oscillator Period

30.5

—

10,000

1,000

—

DC

—

∞

250

50

250

200

2

—

(1)

OS03

Instruction Cycle Time

TCY

—

OS04*

TOSH,

TOSL

External CLKIN High,

External CLKIN Low

LP oscillator

100

20

0

—

XT oscillator

—

HS oscillator

OS05*

TOSR,

TOSF

External CLKIN Rise,

External CLKIN Fall

—

LP oscillator

0

—

∞

XT oscillator

0

—

HS oscillator

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing

code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current

consumption. All devices are tested to operate at ‘min’ values with an external clock applied to OSC1 pin. When an

external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices.

DS41262D-page 238

PIC16F631/677/685/687/689/690

TABLE 17-2: OSCILLATOR PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C ≤ TA ≤ +125°C

Param

Sym

No.

Freq

Tolerance

Characteristic

Min

Typ†

Max

Units

TOSC Slowest clock

ms LFINTOSC/64

Conditions

OS06

OS07

OS08

TWARM

Internal Oscillator Switch

—

2

(3)

when running

TSC

Fail-Safe Sample Clock

—

21

—

(1)

Period

HFOSC

Internal Calibrated

HFINTOSC Frequency

1%

2%

7.92

7.84

8.0

8.08

8.16

MHz VDD = 3.5V, 25°C

(2)

MHz 2.5V ≤ VDD ≤ 5.5V,

0°C ≤ TA ≤ +85°C

5%

—

7.60

15

8.0

31

8.40

45

MHz 2.0V ≤ VDD ≤ 5.5V,

-40°C ≤ TA ≤ +85°C (Ind.),

-40°C ≤ TA ≤ +125°C (Ext.)

OS09*

OS10*

LFOSC

Internal Uncalibrated

LFINTOSC Frequency

kHz

TIOSC ST HFINTOSC Oscillator

Wake-up from Sleep

Start-up Time

—

5.5

3.5

3

12

7

24

14

11

μs

VDD = 2.0V, -40°C to +85°C

VDD = 3.0V, -40°C to +85°C

VDD = 5.0V, -40°C to +85°C

6

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing

code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected

current consumption. All devices are tested to operate at ‘min’ values with an external clock applied to the OSC1 pin.

When an external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices.

2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 μF and 0.01 μF values in parallel are recommended.

3: By design.

DS41262D-page 239

PIC16F631/677/685/687/689/690

FIGURE 17-5:

CLKOUT AND I/O TIMING

Cycle

Write

Q4

Fetch

Q1

Read

Q2

Execute

Q3

FOSC

OS12

OS11

OS20

OS21

CLKOUT

OS19

OS13

OS18

OS16

OS17

I/O pin

(Input)

OS14

OS15

I/O pin

(Output)

New Value

Old Value

OS18, OS19

TABLE 17-3: CLKOUT AND I/O TIMING PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C ≤ TA ≤ +125°C

Param

No.

Sym

Characteristic

Min

Typ† Max Units

Conditions

OS11

OS12

OS13

OS14

OS15

OS16

TOSH2CKL FOSC↑ to CLKOUT↓ ⁽¹⁾

TOSH2CKH FOSC↑ to CLKOUT↑ ⁽¹⁾

—

70

72

20

—

ns VDD = 5.0V

ns

—

50

—

TCKL2IOV

CLKOUT↓ to port out valid⁽¹⁾

TIOV2CKH Port input valid before CLKOUT↑⁽¹⁾

TOSC + 200 ns

ns

TOSH2IOV FOSC↑ (Q1 cycle) to port out valid

—

70*

—

ns VDD = 5.0V

TOSH2IOI

FOSC↑ (Q2 cycle) to port input invalid

(I/O in hold time)

50

OS17

OS18

OS19

TIOV2OSH Port input valid to FOSC↑ (Q2 cycle)

20

—

ns

(I/O in setup time)

TIOR

TIOF

Port output rise time⁽²⁾

—

15

40

72

32

ns VDD = 2.0V

VDD = 5.0V

Port output fall time⁽²⁾

—

28

15

55

30

ns VDD = 2.0V

VDD = 5.0V

OS20* TINP

OS21* TRAP

INT pin input high or low time

25

—

ns

PORTA interrupt-on-change new input

level time

TCY

*

These parameters are characterized but not tested.

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated.

†

Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.

2: Includes OSC2 in CLKOUT mode.

DS41262D-page 240

PIC16F631/677/685/687/689/690

FIGURE 17-6:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND

POWER-UP TIMER TIMING

VDD

MCLR

30

Internal

POR

33

PWRT

Time-out

32

OSC

Start-up Time

(1)

Internal Reset

Watchdog Timer

(1)

Reset

31

34

I/O pins

Note 1:

Asserted low.

FIGURE 17-7:

BROWN-OUT RESET TIMING AND CHARACTERISTICS

VDD

VBOR + VHYST

VBOR

(Device in Brown-out Reset)

(Device not in Brown-out Reset)

37

Reset

(due to BOR)

33*

*

64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.

DS41262D-page 241

PIC16F631/677/685/687/689/690

TABLE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C ≤ TA ≤ +125°C

Param

No.

Sym

TMCL

Characteristic

Min

Typ†

Max Units

Conditions

30

MCLR Pulse Width (low)

2

5

—

μs VDD = 5V, -40°C to +85°C

μs VDD = 5V

31

32

TWDT

TOST

Watchdog Timer Time-out

Period (No Prescaler)

10

17

25

30

ms VDD = 5V, -40°C to +85°C

ms VDD = 5V

Oscillation Start-up Timer

Period^{(1, 2)}

—

1024

—

TOSC (NOTE 3)

33*

34*

TPWRT Power-up Timer Period

40

—

65

—

140

2.0

ms

TIOZ

I/O High-impedance from

MCLR Low or Watchdog Timer

Reset

μs

35

VBOR

VHYST

TBOR

Brown-out Reset Voltage

2.0

—

50

—

2.2

—

V

(NOTE 4)

36*

37*

Brown-out Reset Hysteresis

mV

Brown-out Reset Minimum

Detection Period

100

—

μs VDD ≤ VBOR

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper-

ation and/or higher than expected current consumption. All devices are tested to operate at ‘min’ values

with an external clock applied to the OSC1 pin. When an external clock input is used, the ‘max’ cycle time

limit is ‘DC’ (no clock) for all devices.

2: By design.

3: Period of the slower clock.

4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 μF and 0.01 μF values in parallel are recommended.

DS41262D-page 242

PIC16F631/677/685/687/689/690

FIGURE 17-8:

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

40

41

42

T1CKI

45

46

49

47

TMR0 or

TMR1

TABLE 17-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C ≤ TA ≤ +125°C

Param

Sym

No.

Characteristic

Min

Typ†

Max

Units

Conditions

40*

41*

42*

TT0H

TT0L

TT0P

T0CKI High Pulse Width

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5 TCY + 20

—

ns

10

0.5 TCY + 20

10

T0CKI Low Pulse Width

T0CKI Period

Greater of:

20 or TCY + 40

N

ns N = prescale value

(2, 4, ..., 256)

45*

46*

47*

TT1H

TT1L

T1CKI High Synchronous, No Prescaler

0.5 TCY + 20

15

—

ns

Time

Synchronous,

with Prescaler

Asynchronous

30

0.5 TCY + 20

15

—

ns

T1CKI Low Synchronous, No Prescaler

Time

Synchronous,

with Prescaler

Asynchronous

30

—

ns

TT1P

FT1

T1CKI Input Synchronous

Period

Greater of:

30 or TCY + 40

N

ns N = prescale value

(1, 2, 4, 8)

Asynchronous

60

—

ns

48

Timer1 Oscillator Input Frequency Range

(oscillator enabled by setting bit T1OSCEN)

32.768

kHz

49*

TCKEZTMR1 Delay from External Clock Edge to Timer

Increment

2 TOSC

—

7 TOSC

—

Timers in Sync

mode

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

DS41262D-page 243

PIC16F631/677/685/687/689/690

FIGURE 17-9:

CAPTURE/COMPARE/PWM TIMINGS (ECCP)

CCP1

(Capture mode)

CC01

CC02

CC03

Note:

Refer to Figure 17-3 for load conditions.

TABLE 17-6: CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP)

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C ≤ TA ≤ +125°C

Param

No.

Sym

Characteristic

Min

Typ† Max Units

Conditions

CC01* TccL

CC02* TccH

CC03* TccP

CCP1 Input Low Time

CCP1 Input High Time

CCP1 Input Period

No Prescaler

0.5TCY + 20

20

—

ns

With Prescaler

No Prescaler

With Prescaler

0.5TCY + 20

20

3TCY + 40

N

ns N = prescale

value (1, 4 or

16)

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

DS41262D-page 244

PIC16F631/677/685/687/689/690

TABLE 17-7: COMPARATOR SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C

Comparator Specifications

Param.

Sym

Characteristics

Min

Typ

Max

Units

Comments

No.

CM01

CM02

CM03

VOS

Input Offset Voltage

—

0

5.0

—

10

VDD - 1.5

—

mV

V

VCM

CMRR

Input Common Mode Voltage

Common Mode Rejection

Ratio

+55*

—

db

CM04

CM05

TRT

Response Time⁽¹⁾

—

150

—

400*

10*

ns

TMC2COV Comparator Mode Change to

Output Valid

μs

*

These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from

VSS to VDD - 1.5V.

TABLE 17-8: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C ≤ TA ≤ +125°C

Param

Sym

No.

Characteristics

Min

Typ†

Max

Units

Comments

CV01* CLSB

Step Size⁽²⁾

Absolute Accuracy

—

VDD/24

VDD/32

—

V

Low Range (VRR = 1)

High Range (VRR = 0)

CV02* CACC

—

1/4

1/2

LSb Low Range (VRR = 1)

LSb High Range (VRR = 0)

CV03* CR

CV04* CST

Unit Resistor Value (R)

Settling Time⁽¹⁾

—

2k

—

Ω

10

μs

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

Note 1: Settling time measured while VRR = 1and VR<3:0> transitions from ‘0000’ to ‘1111’.

2: See Section 8.10 “Comparator Voltage Reference” for more information.

TABLE 17-9: VOLTAGE (VR) REFERENCE SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

VR Voltage Reference Specifications

Operating temperature

-40°C ≤ TA ≤ +125°C

Param

No.

Symbol

Characteristics

VR voltage output

Min

Typ

Max

Units

Comments

VR01

VR02

VROUT

TBD

—

0.6

TBD

V

TCVOUT Voltage drift temperature

coefficient

150

ppm/°C

VR03

VR04

ΔVROUT/ Voltage drift with respect to

—

200

10

—

μV/V

μs

ΔVDD

VDD regulation

TSTABLE Settling Time

100*

Legend: TBD = To Be Determined

These parameters are characterized but not tested.

*

DS41262D-page 245

PIC16F631/677/685/687/689/690

FIGURE 17-10:

EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

RB7/TX/CK

121

RB5/AN11/RX/DT

120

Refer to Figure 17-3 for load conditions.

122

Note:

TABLE 17-10: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C ≤ TA ≤ +125°C

Param.

Symbol

No.

Characteristic

Min

Max

Units Conditions

120 TCKH2DTV SYNC XMIT (Master & Slave)

Clock high to data-out valid

—

40

ns

121 TCKRF

122 TDTRF

Clock out rise time and fall time (Master mode)

Data-out rise time and fall time

—

20

ns

FIGURE 17-11:

EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

RC4/C2OUT/TX/CK

125

RC5/RX/DT

126

Note: Refer to Figure 17-3 for load conditions.

TABLE 17-11: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C ≤ TA ≤ +125°C

Param.

No.

Symbol

Characteristic

Min

Max

Units

Conditions

125

TDTV2CKL SYNC RCV (Master & Slave)

Data-hold before CK ↓ (DT hold time)

10

15

—

ns

126

TCKL2DTL Data-hold after CK ↓ (DT hold time)

DS41262D-page 246

PIC16F631/677/685/687/689/690

FIGURE 17-12:

SPI MASTER MODE TIMING (CKE = 0, SMP = 0)

SS

70

SCK

(CKP = 0)

71

72

78

79

SCK

(CKP = 1)

78

80

MSb

bit 6 - - - - - -1

LSb

SDO

SDI

75, 76

MSb In

74

bit 6 - - - -1

LSb In

73

Note: Refer to Figure 17-3 for load conditions.

FIGURE 17-13:

SPI MASTER MODE TIMING (CKE = 1, SMP = 1)

SS

81

SCK

(CKP = 0)

71

72

79

78

73

SCK

(CKP = 1)

80

LSb

MSb

bit 6 - - - - - -1

SDO

SDI

75, 76

MSb In

74

bit 6 - - - -1

LSb In

Note: Refer to Figure 17-3 for load conditions.

DS41262D-page 247

PIC16F631/677/685/687/689/690

FIGURE 17-14:

SPI SLAVE MODE TIMING (CKE = 0)

SS

70

SCK

(CKP = 0)

83

71

72

78

79

SCK

(CKP = 1)

78

80

MSb

LSb

SDO

SDI

bit 6 - - - - - -1

77

75, 76

MSb In

74

bit 6 - - - -1

LSb In

73

Note: Refer to Figure 17-3 for load conditions.

FIGURE 17-15:

SPI SLAVE MODE TIMING (CKE = 1)

82

SS

70

SCK

83

(CKP = 0)

71

72

SCK

(CKP = 1)

80

MSb

bit 6 - - - - - -1

LSb

SDO

SDI

75, 76

77

MSb In

74

bit 6 - - - -1

LSb In

Note: Refer to Figure 17-3 for load conditions.

DS41262D-page 248

PIC16F631/677/685/687/689/690

TABLE 17-12: SPI MODE REQUIREMENTS

Param

No.

Symbol

Characteristic

Min

Typ† Max Units Conditions

70* TSSL2SCH, SS↓ to SCK↓ or SCK↑ input

TCY

—

ns

TSSL2SCL

71* TSCH

72* TSCL

SCK input high time (Slave mode)

SCK input low time (Slave mode)

TCY + 20

100

—

ns

73* TDIV2SCH, Setup time of SDI data input to SCK edge

TDIV2SCL

74* TSCH2DIL, Hold time of SDI data input to SCK edge

TSCL2DIL

100

—

ns

75* TDOR

SDO data output rise time

3.0-5.5V

2.0-5.5V

—

10

—

Tcy

10

25

10

—

10

25

10

—

25

50

25

50

25

50

25

50

145

—

ns

76* TDOF

SDO data output fall time

77* TSSH2DOZ SS↑ to SDO output high-impedance

78* TSCR

SCK output rise time

(Master mode)

3.0-5.5V

2.0-5.5V

79* TSCF

SCK output fall time (Master mode)

80* TSCH2DOV, SDO data output valid after

TSCL2DOV SCK edge

3.0-5.5V

2.0-5.5V

81* TDOV2SCH, SDO data output setup to SCK edge

TDOV2SCL

82* TSSL2DOV SDO data output valid after SS↓ edge

—

50

—

ns

83* TSCH2SSH, SS ↑ after SCK edge

1.5TCY + 40

TSCL2SSH

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

FIGURE 17-16:

I²C™ BUS START/STOP BITS TIMING

SCL

SDA

91

93

90

92

Stop

Condition

Start

Condition

Note: Refer to Figure 17-3 for load conditions.

DS41262D-page 249

PIC16F631/677/685/687/689/690

TABLE 17-13: I²C™ BUS START/STOP BITS REQUIREMENTS

Param

No.

Symbol

Characteristic

Min Typ Max Units

Conditions

90*

TSU:STA Start condition

Setup time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

4700

600

—

ns Only relevant for Repeated

Start condition

91*

92*

93

THD:STA Start condition

Hold time

4000

600

ns After this period, the first

clock pulse is generated

TSU:STO Stop condition

Setup time

4700

600

ns

THD:STO Stop condition

Hold time

4000

600

ns

*

These parameters are characterized but not tested.

FIGURE 17-17:

I²C™ BUS DATA TIMING

103

102

100

101

SCL

90

106

107

91

92

SDA

In

110

109

SDA

Out

Note: Refer to Figure 17-3 for load conditions.

DS41262D-page 250

PIC16F631/677/685/687/689/690

TABLE 17-14: I²C™ BUS DATA REQUIREMENTS

Param.

No.

Symbol

Characteristic

100 kHz mode

Min

Max Units

Conditions

100*

THIGH

Clock high time

4.0

—

μs

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

0.6

Device must operate at a

minimum of 10 MHz

SSP Module

1.5TCY

4.7

—

101*

TLOW

Clock low time

100 kHz mode

μs

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

SSP Module

1.3

—

Device must operate at a

minimum of 10 MHz

1.5TCY

—

102*

103*

TR

TF

SDA and SCL rise 100 kHz mode

time

1000

ns

400 kHz mode

20 + 0.1CB 300

CB is specified to be from

10-400 pF

SDA and SCL fall

time

100 kHz mode

400 kHz mode

—

300

ns

20 + 0.1CB 300

CB is specified to be from

10-400 pF

90*

91*

TSU:STA Start condition

setup time

100 kHz mode

400 kHz mode

4.7

0.6

4.0

0.6

0

—

μs

ns

μs

ns

μs

ns

μs

Only relevant for

Repeated Start condition

THD:STA Start condition hold 100 kHz mode

—

After this period the first

clock pulse is generated

time

400 kHz mode

—

106*

107*

92*

THD:DAT Data input hold time 100 kHz mode

400 kHz mode

—

0

0.9

—

TSU:DAT Data input setup

time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

250

100

4.7

0.6

—

(Note 2)

—

TSU:STO Stop condition

setup time

—

109*

110*

TAA

Output valid from

clock

3500

—

(Note 1)

—

TBUF

Bus free time

4.7

1.3

—

Time the bus must be free

before a new transmission

can start

—

CB

Bus capacitive loading

—

400

pF

*

These parameters are characterized but not tested.

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A Fast mode (400 kHz) I²C bus device can be used in a Standard mode (100 kHz) I²C bus system, but the

requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not

stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it

must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the

Standard mode I²C bus specification), before the SCL line is released.

DS41262D-page 251

PIC16F631/677/685/687/689/690

TABLE 17-15: A/D CONVERTER (ADC) CHARACTERISTICS:

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C ≤ TA ≤ +125°C

Param

No.

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

AD01 NR

AD02 EIL

AD03 EDL

Resolution

—

10 bits

bit

Integral Error

—

1

LSb VREF = 5.12V

Differential Error

LSb No missing codes to 10 bits

VREF = 5.12V

AD04 EOFF Offset Error

AD04A

—

1.5

—

1

—

1

LSb VREF = 5.12V

LSb (PIC16F677 only)

LSb VREF = 5.12V

AD07 EGN Gain Error

AD06 VREF Reference Voltage⁽³⁾

AD06A

2.2

2.5

—

VDD

V

Absolute minimum to ensure 1 LSb

accuracy

AD07 VAIN Full-Scale Range

VSS

—

VREF

10

V

AD08 ZAIN Recommended

Impedance of Analog

Voltage Source

kΩ

AD09* IREF

VREF Input Current⁽³⁾

10

—

1000

50

μA During VAIN acquisition.

Based on differential of VHOLD to VAIN.

μA During A/D conversion cycle

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Total Absolute Error includes integral, differential, offset and gain errors.

2: The A/D conversion result never decreases with an increase in the input voltage and has no missing

codes.

3: ADC VREF is from external VREF or VDD pin, whichever is selected as reference input.

4: When ADC is off, it will not consume any current other than leakage current. The power-down current

specification includes any such leakage from the ADC module.

DS41262D-page 252

PIC16F631/677/685/687/689/690

FIGURE 17-18:

A/D CONVERSION TIMING (NORMAL MODE)

BSF ADCON0, GO

134

Q4

1 TCY

(1)

(TOSC/2)

131

130

A/D CLK

9

8

7

6

3

2

1

0

A/D Data

ADRES

NEW_DATA

1 TCY

OLD_DATA

ADIF

GO

DONE

Sampling Stopped

132

Sample

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEPinstruction to be executed.

TABLE 17-16: A/D CONVERSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C ≤ TA ≤ +125°C

Param

No.

Sym

Characteristic

A/D Clock Period

Min

Typ†

Max

Units

Conditions

130

TAD

1.5

—

μs TOSC-based, VREF ≥ 2.5V

μs TOSC-based, VREF full range

3.0*

130

TAD

A/D Internal RC

Oscillator Period

ADCS<1:0> = 11(RC mode)

μs At VDD = 2.5V

3.0*

2.0*

—

6.0

4.0

11

9.0*

6.0*

—

μs At VDD = 5.0V

131

132

TCNV Conversion Time

(not including

TAD Set GO bit to new data in A/D Result

register

Acquisition Time)⁽¹⁾

(2)

TACQ Acquisition Time

11.5

—

μs

5*

μs The minimum time is the amplifier

settling time. This may be used if the

“new” input voltage has not changed

by more than 1 LSb (i.e., 4.1 mV @

4.096V) from the last sampled

voltage (as stored on CHOLD).

134

TGO

Q4 to A/D Clock

Start

—

TOSC/2

—

If the A/D clock source is selected as

RC, a time of TCY is added before

the A/D clock starts. This allows the

SLEEPinstruction to be executed.

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle.

2: See Table 9-1 for minimum conditions.

DS41262D-page 253

PIC16F631/677/685/687/689/690

FIGURE 17-19:

A/D CONVERSION TIMING (SLEEP MODE)

BSF ADCON0, GO

134

(1)

1 TCY

(TOSC/2 + TCY)

131

Q4

130

A/D CLK

A/D Data

9

8

7

3

2

1

0

6

NEW_DATA

1 TCY

OLD_DATA

ADRES

ADIF

GO

DONE

Sampling Stopped

132

Sample

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEPinstruction to be executed.

TABLE 17-17: A/D CONVERSION REQUIREMENTS (SLEEP MODE)

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C ≤ TA ≤ +125°C

Param

No.

Sym

Characteristic

A/D Internal RC

Min

Typ†

Max Units

Conditions

130

TAD

ADCS<1:0> = 11(RC mode)

Oscillator Period

3.0*

2.0*

—

6.0

4.0

11

9.0*

6.0*

—

μs At VDD = 2.5V

μs At VDD = 5.0V

131

132

TCNV

TACQ

Conversion Time

(not including

TAD

Acquisition Time)⁽¹⁾

(2)

Acquisition Time

11.5

—

μs

5*

μs The minimum time is the amplifier

settling time. This may be used if

the “new” input voltage has not

changed by more than 1 LSb (i.e.,

4.1 mV @ 4.096V) from the last

sampled voltage (as stored on

CHOLD).

134

TGO

Q4 to A/D Clock

Start

—

TOSC/2 + TCY

—

If the A/D clock source is selected

as RC, a time of TCY is added

before the A/D clock starts. This

allows the SLEEPinstruction to be

executed.

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: ADRES register may be read on the following TCY cycle.

2: See Table 9-1 for minimum conditions.

DS41262D-page 254

PIC16F631/677/685/687/689/690

18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

The graphs and tables provided in this section are for design guidance and are not tested.

In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD

range). This is for information only and devices are ensured to operate properly only within the specified range.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are

not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents

(mean + 3σ) or (mean - 3σ) respectively, where σ is a standard deviation, over each temperature range.

FIGURE 18-1:

TYPICAL IDD vs. FOSC OVER VDD (EC MODE)

3.5

Typical: Statistical Mean @25°C

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

5.5V

5.0V

4.0V

3.0V

2.0V

1 MHz

2 MHz

4 MHz

6 MHz

8 MHz

10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz

FOSC

DS41262D-page 255

PIC16F631/677/685/687/689/690

FIGURE 18-2:

MAXIMUM IDD vs. FOSC OVER VDD (EC MODE)

4.0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

5.5V

5.0V

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

4.0V

3.0V

2.0V

1 MHz

2 MHz

4 MHz

6 MHz

8 MHz

10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz

FOSC

FIGURE 18-3:

TYPICAL IDD vs. FOSC OVER VDD (HS MODE)

Typical IDD vs FOSC Over Vdd

HS Mode

4.0

Typical: Statistical Mean @25°C

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

4 MHz

10 MHz

16 MHz

20 MHz

FOSC

DS41262D-page 256

PIC16F631/677/685/687/689/690

FIGURE 18-4:

MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)

Maximum IDD vs FOSC Over Vdd

HS Mode

5.0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

4 MHz

10 MHz

16 MHz

20 MHz

FOSC

FIGURE 18-5:

TYPICAL IDD vs. VDD OVER FOSC (XT MODE)

XT Mode

900

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

800

700

600

500

400

300

200

100

0

4 MHz

1 MHz

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41262D-page 257

PIC16F631/677/685/687/689/690

FIGURE 18-6:

MAXIMUM IDD vs. VDD OVER FOSC (XT MODE)

XT Mode

1,400

1,200

1,000

800

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

4 MHz

1 MHz

600

400

200

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 18-7:

TYPICAL IDD vs. VDD OVER FOSC (EXTRC MODE)

800

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

700

600

500

400

300

200

100

0

4 MHz

1 MHz

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41262D-page 258

PIC16F631/677/685/687/689/690

FIGURE 18-8:

MAXIMUM IDD vs. VDD O_EV_XE_TR_RCF_MO_oS_dC_e(EXTRC MODE)

1,400

1,200

1,000

800

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

4 MHz

1 MHz

600

400

200

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 18-9:

IDD vs. VDD OVER FOSC (LFINTOSC MODE, 31 kHz)

LFINTOSC Mode, 31KHZ

80

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

70

60

50

40

30

20

10

0

Maximum

Typical

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41262D-page 259

PIC16F631/677/685/687/689/690

FIGURE 18-10:

TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE)

1,600

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

5.5V

5.0V

1,400

1,200

1,000

800

4.0V

3.0V

2.0V

600

400

200

0

125 kHz

250 kHz

500 kHz

1 MHz

2 MHz

4 MHz

8 MHz

FOSC

FIGURE 18-11:

MAXIMUM IDD vs. FOSC OVER VDD (HFINTOSC MODE)

HFINTOSC

2,000

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

5.5V

5.0V

1,800

1,600

1,400

1,200

1,000

800

4.0V

3.0V

600

2.0V

400

200

0

125 kHz

250 kHz

500 kHz

1 MHz

2 MHz

4 MHz

8 MHz

FOSC

DS41262D-page 260

PIC16F631/677/685/687/689/690

FIGURE 18-12:

TYPICAL IPD vs. VDD (SLE_TE_yP_piM_caO_lDE, ALL PERIPHERALS DISABLED)

(Sleep Mode all Peripherals Disabled)

0.45

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 18-13:

MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)

Maximum

(Sleep Mode all Peripherals Disabled)

18.0

Typical: Statistical Mean @25°C

Maximum: Mean + 3σ

16.0

14.0

12.0

10.0

8.0

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

Max. 125°C

6.0

4.0

Max. 85°C

3.5

2.0

0.0

2.0

2.5

3.0

4.0

4.5

5.0

5.5

VDD (V)

DS41262D-page 261

PIC16F631/677/685/687/689/690

FIGURE 18-14:

COMPARATOR IPD vs. VDD (BOTH COMPARATORS ENABLED)

180

160

140

120

100

80

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

Maximum

Typical

60

40

20

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 18-15:

BOR IPD vs. VDD OVER TEMPERATURE

160

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

140

120

100

80

Maximum

Typical

60

40

20

0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41262D-page 262

PIC16F631/677/685/687/689/690

FIGURE 18-16:

TYPICAL WDT IPD vs. VDD OVER TEMPERATURE

Typical

3.0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

2.5

2.0

1.5

1.0

0.5

0.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 18-17:

MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE

Maximum

25.0

20.0

15.0

10.0

5.0

Max. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

Max. 85°C

0.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41262D-page 263

PIC16F631/677/685/687/689/690

FIGURE 18-18:

WDT PERIOD vs. VDD OVER TEMPERATURE

30

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

28

26

24

22

20

18

16

14

12

10

Max. (125°C)

Max. (85°C)

Typical

Minimum

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 18-19:

WDT PERIOD vs. TEMPER_VA_dT_dU₌R₅E_VOVER VDD (5.0V)

30

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

28

26

24

22

20

18

16

14

12

10

Maximum

Typical

Minimum

-40°C

25°C

85°C

125°C

Temperature (°C)

DS41262D-page 264

PIC16F631/677/685/687/689/690

FIGURE 18-20:

CVREF IPD vs. VDD OVER_HT_igE_hM_RP_aE_ngR_eATURE (HIGH RANGE)

140

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

120

100

80

60

40

20

0

Max. 125°C

Max. 85°C

Typical

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 18-21:

CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE)

180

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

160

140

120

100

80

Max. 125°C

Max. 85°C

Typical

60

40

20

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41262D-page 265

PIC16F631/677/685/687/689/690

FIGURE 18-22:

VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)

(VDD = 3V, -40×C TO 125×C)

0.8

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

Max. 125°C

Max. 85°C

Typical 25°C

Min. -40°C

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

IOL (mA)

FIGURE 18-23:

VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)

0.45

Typical: Statistical Mean @25°C

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

Typical: Statistical Mean @25×C

Maximum: Mean (Worst Case Temp) + 3σ

Maximum: Meas(-+403×C to 125×C)

(-40°C to 125°C)

Max. 125°C

Max. 85°C

Typ. 25°C

Min. -40°C

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

IOL (mA)

DS41262D-page 266

PIC16F631/677/685/687/689/690

FIGURE 18-24:

VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)

3.5

3.0

2.5

2.0

1.5

Max. -40°C

Typ. 25°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

1.0

0.5

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

-3.5

-4.0

IOH (mA)

FIGURE 18-25:

VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V)

5.5

5.0

4.5

4.0

Max. -40°C

Typ. 25°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

3.5

3.0

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

-3.5

-4.0

-4.5

-5.0

IOH (mA)

DS41262D-page 267

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FIGURE 18-26:

TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE

(TTL Input, -40×C TO 125×C)

1.7

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

1.5

1.3

1.1

0.9

0.7

0.5

Max. -40°C

Typ. 25°C

Min. 125°C

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 18-27:

SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE

(ST Input, -40×C TO 125×C)

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

VIH Max. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

VIH Min. -40°C

VIL Max. -40°C

VIL Min. 125°C

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41262D-page 268

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FIGURE 18-28:

COMPARATOR RESPONSE TIME (RISING EDGE)

531

806

1000

900

800

700

Max. 125°C

Max. 85°C

VCM = VDD - 1.5V)/2

V+ input = VCM

V- input = Transition from VCM + 100MV to VCM - 20MV

Note:

600

500

400

300

200

100

Typ. 25°C

Min. -40°C

0

2.0

2.5

4.0

5.5

VDD (V)

FIGURE 18-29:

COMPARATOR RESPONSE TIME (FALLING EDGE)

1000

900

800

700

Max. 125°C

Max. 85°C

VCM = VDD - 1.5V)/2

600

500

400

300

200

100

0

Note:

V+ input = VCM

V- input = Transition from VCM - 100MV to VCM + 20MV

Typ. 25°C

Min. -40°C

2.0

2.5

4.0

5.5

VDD (V)

DS41262D-page 269

PIC16F631/677/685/687/689/690

FIGURE 18-30:

LFINTOSC FREQUENCY vs. VDD OVER TEMPERATURE (31 kHz)

LFINTOSC 31Khz

45,000

40,000

35,000

30,000

25,000

20,000

15,000

10,000

5,000

Max. -40°C

Typ. 25°C

Min. 85°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 18-31:

ADC CLOCK PERIOD vs. VDD OVER TEMPERATURE

8

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

125°C

85°C

6

4

2

0

25°C

-40°C

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41262D-page 270

PIC16F631/677/685/687/689/690

FIGURE 18-32:

TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE

16

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

14

85°C

12

25°C

10

-40°C

8

6

4

2

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 18-33:

MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE

-40C to +85C

25

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

20

15

10

5

85°C

25°C

-40°C

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41262D-page 271

PIC16F631/677/685/687/689/690

FIGURE 18-34:

MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE

10

9

Typical: Statistical Mean @25°C

Maximum: Mean (Worst Case Temp) + 3σ

(-40°C to 125°C)

8

7

85°C

6

25°C

5

-40°C

4

3

2

1

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 18-35:

TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C)

5

4

3

2

1

0

-1

-2

-3

-4

-5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41262D-page 272

PIC16F631/677/685/687/689/690

FIGURE 18-36:

TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE VDD (85°C)

5

4

3

2

1

0

-1

-2

-3

-4

-5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 18-37:

TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C)

5

4

3

2

1

0

-1

-2

-3

-4

-5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41262D-page 273

PIC16F631/677/685/687/689/690

FIGURE 18-38:

TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C)

5

4

3

2

1

0

-1

-2

-3

-4

-5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41262D-page 274

PIC16F631/677/685/687/689/690

19.0 PACKAGING INFORMATION

19.1 Package Marking Information

20-Lead PDIP

Example

XXXXXXXXXXXXXXXXX

YYWWNNN

PIC16F685-I/P

0510017

e

3

20-Lead SOIC (7.50 mm)

Example

XXXXXXXXXXXXXX

PIC16F685-I

/SO

e

3

0510017

YYWWNNN

20-Lead SSOP

Example

XXXXXXXXXXX

PIC16F687

-I/SS

e

3

YYWWNNN

0510017

20-Lead QFN

Example

XXXXXX

YWWNNN

16F690

-I/ML

510017

e

3

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

*

)

3

e

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS41262D-page 275

PIC16F631/677/685/687/689/690

19.2 Package Details

The following sections give the technical details of the packages.

20-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

E1

NOTE 1

1

2

3

D

E

A2

A

L

c

A1

b1

eB

e

b

Units

INCHES

NOM

20

Dimension Limits

MIN

MAX

Number of Pins

Pitch

N

e

.100 BSC

–

Top to Seating Plane

A

–

.210

.195

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.300

.240

.980

.115

.008

.045

.014

–

.130

–

.310

.250

1.030

.130

.010

.060

.018

–

.325

.280

1.060

.150

.015

.070

.022

.430

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

b1

b

Lower Lead Width

Overall Row Spacing §

eB

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-019B

DS41262D-page 276

PIC16F631/677/685/687/689/690

20-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

1

2

3

e

b

α

h

c

φ

A2

A

L

β

A1

L1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

20

1.27 BSC

Overall Height

A

–

2.65

–

Molded Package Thickness

Standoff §

A2

A1

E

2.05

0.10

–

0.30

Overall Width

10.30 BSC

Molded Package Width

Overall Length

E1

D

h

7.50 BSC

12.80 BSC

Chamfer (optional)

Foot Length

0.25

0.40

–

0.75

1.27

L

–

Footprint

L1

φ

1.40 REF

Foot Angle

0°

0.20

0.31

5°

–

8°

Lead Thickness

Lead Width

c

0.33

0.51

15°

b

Mold Draft Angle Top

Mold Draft Angle Bottom

α

β

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-094B

DS41262D-page 277

PIC16F631/677/685/687/689/690

20-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

1

2

e

b

c

A2

A

φ

A1

L1

L

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

20

0.65 BSC

Overall Height

Molded Package Thickness

Standoff

A

–

1.75

–

2.00

1.85

–

A2

A1

E

1.65

0.05

7.40

5.00

6.90

0.55

Overall Width

Molded Package Width

Overall Length

Foot Length

7.80

5.30

7.20

0.75

1.25 REF

–

8.20

5.60

7.50

0.95

E1

D

L

Footprint

L1

c

Lead Thickness

Foot Angle

0.09

0°

0.25

8°

φ

4°

Lead Width

b

0.22

–

0.38

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-072B

DS41262D-page 278

PIC16F631/677/685/687/689/690

20-Lead Plastic Quad Flat, No Lead Package (ML) – 4x4x0.9 mm Body [QFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

D2

EXPOSED

PAD

e

E2

E

2

1

b

2

1

K

N

NOTE 1

L

BOTTOM VIEW

TOP VIEW

A

A1

A3

Units

MILLIMETERS

NOM

Dimension Limits

MIN

MAX

Number of Pins

N

e

20

Pitch

0.50 BSC

0.90

Overall Height

Standoff

A

0.80

0.00

1.00

0.05

A1

A3

E

0.02

Contact Thickness

Overall Width

0.20 REF

4.00 BSC

2.70

Exposed Pad Width

Overall Length

Exposed Pad Length

Contact Width

Contact Length

Contact-to-Exposed Pad

E2

D

2.60

2.80

4.00 BSC

2.70

D2

b

2.60

0.18

0.30

0.20

2.80

0.30

0.50

–

0.25

L

0.40

K

–

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-126B

DS41262D-page 279

PIC16F631/677/685/687/689/690

NOTES:

DS41262D-page 280

PIC16F631/677/685/687/689/690

APPENDIX A: DATA SHEET

REVISION HISTORY

APPENDIX B: MIGRATING FROM

OTHER PIC^®

DEVICES

Revision A (March 2005)

This discusses some of the issues in migrating from

other PIC devices to the PIC16F6XX Family of devices.

This is a new data sheet.

Revision B (May 2006)

B.1

PIC16F676 to PIC16F685

Added 631/677 part numbers; Added pin summary

tables after pin diagrams; Incorporated Golden

Chapters.

TABLE B-1:

Feature

FEATURE COMPARISON

PIC16F676

PIC16F685

Max Operating

Speed

20 MHz

Revision C (July 2006)

Max Program

Memory (Words)

1024

4096

Revised Section 4.2.1, ANSEL and ANSELH

Registers; Register 4-3, ANSEL Analog Select; Added

Register 4-4, ANSELH Analog Select High; Section

11.3.2, Revised CCP1<1:0> to DC1B<1:0>; Section

11.3.7, Number 4 - Revised CCP1 to DC1B; Figure 11-

5, Revised CCP1 to DC1B; Table 11-4, Revised P1M to

P1M<1:0>; Section 12.3.1, Revised Paragraph 3;

Revised Note 2; Revised Figure 12-6 Title.

SRAM (bytes)

A/D Resolution

64

128

10-bit

256

10-bit

128

Data EEPROM

(Bytes)

Timers (8/16-bit)

Oscillator Modes

Brown-out Reset

Internal Pull-ups

1/1

8

2/1

8

Revision D (February 2007)

Y

RA0/1/2/4/5 RA0/1/2/4/5,

MCLR

Removed Preliminary status; Changed PICmicro to

PIC; Replaced Dev. Tool Section; Replaced Package

Drawings.

Interrupt-on-change RA0/1/2/3/4/5 RA0/1/2/3/4/5

Comparator

ECCP+

1

N

2

Y

Ultra Low-Power

Wake-up

Extended WDT

N

Y

Software Control

Option of WDT/BOR

INTOSC

Frequencies

4 MHz

N

31 kHz-8 MHz

Y

Clock Switching

Note: This device has been designed to perform

to the parameters of its data sheet. It has

been tested to an electrical specification

designed to determine its conformance

with these parameters. Due to process

differences in the manufacture of this

device, this device may have different

performance characteristics than its earlier

version. These differences may cause this

device to perform differently in your

application than the earlier version of this

device.

DS41262D-page 281

PIC16F631/677/685/687/689/690

NOTES:

DS41262D-page 282

PIC16F631/677/685/687/689/690

INDEX

PIC16F685 ................................................................. 11

PIC16F687/689 .......................................................... 12

PIC16F690 ................................................................. 13

A

A/D

Specifications............................................ 252, 253, 254

PWM (Enhanced) ..................................................... 133

RA0 Pins..................................................................... 64

RA1 Pins..................................................................... 65

RA2 Pin ...................................................................... 65

RA3 Pin ...................................................................... 66

RA4 Pin ...................................................................... 66

RA5 Pin ...................................................................... 67

RB4 Pin ...................................................................... 71

RB5 Pin ...................................................................... 72

RB6 Pin ...................................................................... 73

RB7 Pin ...................................................................... 74

RC0 and RC1 Pins ..................................................... 77

RC2 and RC3 Pins ..................................................... 77

RC4 Pin ...................................................................... 78

RC5 Pin ...................................................................... 78

RC6 Pin ...................................................................... 79

RC7 Pin ...................................................................... 79

Resonator Operation .................................................. 50

Absolute Maximum Ratings .............................................. 227

AC Characteristics

Industrial and Extended ............................................ 238

Load Conditions........................................................ 237

ACK pulse......................................................................... 184

ADC .................................................................................. 107

Acquisition Requirements ......................................... 116

Associated registers.................................................. 118

Block Diagram........................................................... 107

Calculating Acquisition Time..................................... 116

Channel Selection..................................................... 108

Configuration............................................................. 108

Configuring Interrupt ................................................. 111

Conversion Clock...................................................... 108

Conversion Procedure .............................................. 111

Internal Sampling Switch (RSS) Impedance.............. 116

Interrupts................................................................... 109

Operation .................................................................. 111

Operation During Sleep ............................................ 111

Port Configuration..................................................... 108

Reference Voltage (VREF)......................................... 108

Result Formatting...................................................... 110

Source Impedance.................................................... 116

Special Event Trigger................................................ 111

Starting an A/D Conversion ...................................... 110

ADCON0 Register............................................................. 113

ADCON1 Register............................................................. 114

ADRESH Register (ADFM = 0)......................................... 115

ADRESH Register (ADFM = 1)......................................... 115

ADRESL Register (ADFM = 0).......................................... 115

ADRESL Register (ADFM = 1).......................................... 115

Analog Input Connection Considerations.......................... 100

Analog-to-Digital Converter. See ADC

2

SSP (I C Mode)........................................................ 184

SSP (SPI Mode) ....................................................... 175

Timer1 ........................................................................ 84

Timer2 ........................................................................ 91

TMR0/WDT Prescaler ................................................ 81

Watchdog Timer (WDT)............................................ 208

Break Character (12-bit) Transmit and Receive ............... 167

Brown-out Reset (BOR).................................................... 198

Associated................................................................ 199

Specifications ........................................................... 242

Timing and Characteristics....................................... 241

C

C Compilers

MPLAB C18.............................................................. 224

MPLAB C30.............................................................. 224

Capture Module. See Enhanced Capture/Compare/

PWM(ECCP)

ANSEL Register.................................................................. 61

ANSELH Register ............................................................... 61

Assembler

Capture/Compare/PWM (CCP)

MPASM Assembler................................................... 224

Associated registers w/ Capture/Compare/PWM ..... 148

Capture Mode........................................................... 128

CCPx Pin Configuration............................................ 128

Compare Mode......................................................... 129

CCPx Pin Configuration.................................... 129

Software Interrupt Mode........................... 128, 129

Special Event Trigger....................................... 129

Timer1 Mode Selection............................. 128, 129

Prescaler .................................................................. 128

PWM Mode............................................................... 130

Duty Cycle ........................................................ 131

Effects of Reset................................................ 132

Example PWM Frequencies and

B

BAUDCTL Register........................................................... 160

BF bit................................................................................. 176

Block Diagrams

(CCP) Capture Mode Operation ............................... 128

ADC .......................................................................... 107

ADC Transfer Function ............................................. 117

Analog Input Model........................................... 100, 117

CCP PWM................................................................. 130

Clock Source............................................................... 47

Comparator C1 ........................................................... 94

Comparator C2 ........................................................... 94

Compare ................................................................... 129

Crystal Operation........................................................ 50

EUSART Receive ..................................................... 150

EUSART Transmit .................................................... 149

External RC Mode....................................................... 51

Fail-Safe Clock Monitor (FSCM)................................. 57

In-Circuit Serial Programming Connections.............. 212

Interrupt Logic........................................................... 205

On-Chip Reset Circuit............................................... 196

PIC16F631.................................................................... 9

PIC16F677.................................................................. 10

Resolutions, 20 MHZ................................ 131

Example PWM Frequencies and

Resolutions, 8 MHz .................................. 131

Operation in Sleep Mode.................................. 132

Setup for Operation .......................................... 132

System Clock Frequency Changes .................. 132

PWM Period ............................................................. 131

Setup for PWM Operation ........................................ 132

CCPxCON (Enhanced) Register ...................................... 127

CKE bit ............................................................................. 176

CKP bit ............................................................................. 177

DS41262D-page 283

PIC16F631/677/685/687/689/690

Clock Accuracy with Asynchronous Operation .................158

Clock Sources

Reading .................................................................... 122

Writing ...................................................................... 122

Data Memory ...................................................................... 26

Data/Address bit (D/A)...................................................... 176

DC Characteristics

Extended .................................................................. 232

Extended and Industrial............................................ 234

Industrial ................................................................... 230

Industrial and Extended............................................ 229

Development Support....................................................... 223

Device Overview................................................................... 9

External Modes...........................................................49

EC.......................................................................49

HS.......................................................................50

LP........................................................................50

OST.....................................................................49

RC.......................................................................51

XT .......................................................................50

Internal Modes ............................................................51

Frequency Selection ...........................................53

HFINTOSC..........................................................51

HFINTOSC/LFINTOSC Switch Timing ...............53

INTOSC ..............................................................51

INTOSCIO...........................................................51

LFINTOSC ..........................................................53

Clock Switching...................................................................55

CM1CON0 Register ............................................................98

CM2CON0 Register ............................................................99

CM2CON1 Register ..........................................................101

Code Examples

A/D Conversion.........................................................112

Assigning Prescaler to Timer0 ....................................82

Assigning Prescaler to WDT .......................................82

Changing Between Capture Prescalers....................128

Indirect Addressing .....................................................44

Initializing PORTA.......................................................59

Initializing PORTB.......................................................69

Initializing PORTC.......................................................76

Loading the SSPBUF (SSPSR) Register..................178

Saving STATUS and W Registers in RAM ...............207

Ultra Low-Power Wake-up Initialization ......................63

Write Verify ...............................................................125

Code Protection ................................................................211

Comparator

C2OUT as T1 Gate ...................................................101

Operation ....................................................................93

Operation During Sleep ..............................................97

Response Time...........................................................95

Synchronizing COUT w/Timer1 ................................101

Comparator Module ............................................................93

Associated registers..................................................106

C1 Output State Versus Input Conditions...................95

Comparator Voltage Reference (CVREF)

Response Time...........................................................95

Comparator Voltage Reference (CVREF) ..........................104

Effects of a Reset........................................................97

Specifications............................................................245

Comparators

E

ECCP. See Enhanced Capture/Compare/PWM

ECCPAS Register............................................................. 141

EEADR Register............................................................... 120

EEADR Registers ............................................................. 119

EEADRH Registers........................................................... 119

EECON1 Register..................................................... 119, 121

EECON2 Register............................................................. 119

EEDAT Register ............................................................... 120

EEDATH Register............................................................. 120

EEPROM Data Memory

Avoiding Spurious Write ........................................... 125

Write Verify............................................................... 125

Effects of Reset

PWM mode............................................................... 132

Electrical Specifications.................................................... 227

Enhanced Capture/Compare/PWM .................................. 127

Enhanced Capture/Compare/PWM (ECCP)

Enhanced PWM Mode.............................................. 133

Auto-Restart ..................................................... 142

Auto-shutdown.................................................. 141

Direction Change in Full-Bridge Output Mode.. 139

Full-Bridge Application...................................... 137

Full-Bridge Mode .............................................. 137

Half-Bridge Application..................................... 136

Half-Bridge Application Examples .................... 143

Half-Bridge Mode.............................................. 136

Output Relationships (Active-High and

Active-Low)............................................... 134

Output Relationships Diagram.......................... 135

Programmable Dead Band Delay..................... 143

Shoot-through Current...................................... 143

Start-up Considerations.................................... 140

Specifications ........................................................... 244

Timer Resources ...................................................... 127

Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) .............................. 149

Errata.................................................................................... 8

EUSART ........................................................................... 149

Associated Registers

C2OUT as T1 Gate .....................................................85

Effects of a Reset........................................................97

Specifications............................................................245

Compare Module. See Enhanced Capture/

Baud Rate Generator ....................................... 161

Asynchronous Mode................................................. 151

12-bit Break Transmit and Receive .................. 167

Associated Registers

Compare/PWM (ECCP)

CONFIG Register..............................................................195

Configuration Bits..............................................................194

CPU Features ...................................................................193

Customer Change Notification Service .............................289

Customer Notification Service...........................................289

Customer Support.............................................................289

Receive .................................................... 157

Transmit.................................................... 153

Auto-Wake-up on Break ................................... 166

Baud Rate Generator (BRG) ............................ 161

Clock Accuracy................................................. 158

Receiver ........................................................... 154

Setting up 9-bit Mode with Address Detect ...... 156

Transmitter ....................................................... 151

Baud Rate Generator (BRG)

D

D/A bit ...............................................................................176

Data EEPROM Memory....................................................119

Associated Registers ................................................126

Code Protection ........................................................125

Auto Baud Rate Detect..................................... 165

DS41262D-page 284

PIC16F631/677/685/687/689/690

Baud Rate Error, Calculating ............................ 161

GOTO....................................................................... 217

INCF ......................................................................... 217

INCFSZ..................................................................... 217

IORLW...................................................................... 217

IORWF...................................................................... 217

MOVF ....................................................................... 218

MOVLW.................................................................... 218

MOVWF.................................................................... 218

NOP.......................................................................... 218

RETFIE..................................................................... 219

RETLW..................................................................... 219

RETURN................................................................... 219

RLF........................................................................... 220

RRF .......................................................................... 220

SLEEP...................................................................... 220

SUBLW..................................................................... 220

SUBWF..................................................................... 221

SWAPF..................................................................... 221

XORLW .................................................................... 221

XORWF .................................................................... 221

Summary Table ........................................................ 214

INTCON Register................................................................ 38

Baud Rates, Asynchronous Modes .................. 162

Formulas........................................................... 161

High Baud Rate Select (BRGH Bit) .................. 161

Synchronous Master Mode....................................... 169

Associated Registers

Receive..................................................... 172

Transmit.................................................... 170

Reception.......................................................... 171

Requirements, Synchronous Receive .............. 246

Requirements, Synchronous Transmission ...... 246

Timing Diagram, Synchronous Receive ........... 246

Timing Diagram, Synchronous Transmission ... 246

Transmission .................................................... 169

Synchronous Slave Mode......................................... 173

Associated Registers

Receive..................................................... 174

Transmit.................................................... 173

Reception.......................................................... 174

Transmission .................................................... 173

F

2

Fail-Safe Clock Monitor....................................................... 57

Fail-Safe Condition Clearing....................................... 57

Fail-Safe Detection ..................................................... 57

Fail-Safe Operation..................................................... 57

Reset or Wake-up from Sleep..................................... 57

Firmware Instructions........................................................ 213

Flash Program Memory .................................................... 119

Fuses. See Configuration Bits

Inter-Integrated Circuit (I C). See I C Mode

Internal Oscillator Block

INTOSC

Specifications ................................................... 239

Internal Sampling Switch (RSS) Impedance ..................... 116

Internet Address ............................................................... 289

Interrupts .......................................................................... 204

ADC.......................................................................... 111

Associated Registers................................................ 206

Context Saving ......................................................... 207

Interrupt-on-Change ................................................... 60

Interrupt-on-change.................................................... 69

PORTA/PORTB Interrupt-on-Change ...................... 205

RA2/INT.................................................................... 204

TMR0........................................................................ 205

TMR1.......................................................................... 86

INTOSC Specifications..................................................... 239

IOCA Register..................................................................... 62

IOCB Register..................................................................... 70

G

General Purpose Register File............................................ 26

I

2

I C Mode

Addressing................................................................ 185

Associated Registers ................................................ 192

Master Mode............................................................. 191

Mode Selection ......................................................... 184

Multi-Master Mode .................................................... 191

Operation .................................................................. 184

Reception.................................................................. 186

Slave Mode

L

Load Conditions................................................................ 237

SCL and SDA pins............................................ 184

Transmission............................................................. 189

ID Locations...................................................................... 211

In-Circuit Serial Programming (ICSP)............................... 211

Indirect Addressing, INDF and FSR registers..................... 44

Instruction Format............................................................. 213

Instruction Set................................................................... 213

ADDLW..................................................................... 215

ADDWF..................................................................... 215

ANDLW..................................................................... 215

ANDWF..................................................................... 215

BCF........................................................................... 215

BSF........................................................................... 215

BTFSC ...................................................................... 215

BTFSS ...................................................................... 216

CALL......................................................................... 216

CLRF......................................................................... 216

CLRW ....................................................................... 216

CLRWDT................................................................... 216

COMF ....................................................................... 216

DECF ........................................................................ 216

DECFSZ.................................................................... 217

M

MCLR ............................................................................... 197

Internal...................................................................... 197

Memory Organization ......................................................... 25

Data............................................................................ 26

Program...................................................................... 25

Microchip Internet Web Site.............................................. 289

Migrating from other PIC Devices..................................... 281

MPLAB ASM30 Assembler, Linker, Librarian................... 224

MPLAB ICD 2 In-Circuit Debugger ................................... 225

MPLAB ICE 2000 High-Performance Universal

In-Circuit Emulator.................................................... 225

MPLAB ICE 4000 High-Performance Universal

In-Circuit Emulator.................................................... 225

MPLAB Integrated Development Environment Software.. 223

MPLAB PM3 Device Programmer .................................... 225

MPLINK Object Linker/MPLIB Object Librarian................ 224

DS41262D-page 285

PIC16F631/677/685/687/689/690

Interrupt-on-change .................................................... 69

O

Pin Descriptions and Diagrams .................................. 71

RB4............................................................................. 71

RB5............................................................................. 72

RB6............................................................................. 73

RB7............................................................................. 74

Registers .................................................................... 69

PORTB Register................................................................. 69

PORTC ............................................................................... 76

Associated registers ................................................... 80

P1A/P1B/P1C/P1D.See Enhanced Capture/

Compare/PWM+ (ECCP+) ................................. 76

RC0 ............................................................................ 77

RC1 ............................................................................ 77

RC2 ............................................................................ 77

RC3 ............................................................................ 77

RC4 ............................................................................ 78

RC5 ............................................................................ 78

RC6 ............................................................................ 79

RC7 ............................................................................ 79

Registers .................................................................... 76

Specifications ........................................................... 240

PORTC Register................................................................. 76

Power-Down Mode (Sleep)............................................... 210

Power-on Reset (POR)..................................................... 197

Power-up Timer (PWRT) .................................................. 197

Specifications ........................................................... 242

Prescaler

Shared WDT/Timer0................................................... 82

Switching Prescaler Assignment ................................ 82

Program Memory................................................................ 25

Map and Stack...................................................... 25, 26

Programming, Device Instructions.................................... 213

PSTRCON Register.......................................................... 145

Pulse Steering .................................................................. 145

PWM (ECCP Module)

Pulse Steering .......................................................... 145

Steering Synchronization.......................................... 147

PWM Mode. See Enhanced Capture/Compare/PWM...... 133

PWMxCON Register......................................................... 144

OPCODE Field Descriptions.............................................213

OPTION Register.......................................................... 37, 83

OSCCON Register..............................................................48

Oscillator

Associated registers.............................................. 58, 89

Oscillator Module ................................................................47

EC ...............................................................................47

HFINTOSC..................................................................47

HS...............................................................................47

INTOSC ......................................................................47

INTOSCIO...................................................................47

LFINTOSC ..................................................................47

LP................................................................................47

RC...............................................................................47

RCIO...........................................................................47

XT ...............................................................................47

Oscillator Parameters........................................................239

Oscillator Specifications....................................................238

Oscillator Start-up Timer (OST)

Specifications............................................................242

Oscillator Switching

Fail-Safe Clock Monitor...............................................57

Two-Speed Clock Start-up..........................................55

OSCTUNE Register ............................................................52

P

P (Stop) bit ........................................................................176

P1A/P1B/P1C/P1D.See Enhanced Capture/

Compare/PWM (ECCP)............................................133

Packaging .........................................................................275

Marking .....................................................................275

PDIP Details..............................................................276

PCL and PCLATH...............................................................44

Stack...........................................................................44

PCON Register ........................................................... 43, 199

PICkit 2 Development Programmer ..................................226

PICSTART Plus Development Programmer .....................226

PIE1 Register......................................................................39

PIE2 Register......................................................................40

Pin Diagram ......................................................2, 3, 4, 5, 6, 7

PIR1 Register......................................................................41

PIR2 Register......................................................................42

PORTA

Additional Pin Functions .............................................60

ANSEL Register..................................................60

ANSELH Register ...............................................60

Interrupt-on-Change............................................60

Ultra Low-Power Wake-up............................ 60, 63

Weak Pull-Up......................................................60

Associated Registers ..................................................68

Pin Descriptions and Diagrams...................................64

RA0 .............................................................................64

RA1 .............................................................................65

RA2 .............................................................................65

RA3 .............................................................................66

RA4 .............................................................................66

RA5 .............................................................................67

Registers.....................................................................59

Specifications............................................................240

PORTA Register .................................................................59

PORTB

R

R/W bit.............................................................................. 176

RCREG............................................................................. 156

RCSTA Register ............................................................... 159

Reader Response............................................................. 290

Read-Modify-Write Operations ......................................... 213

Receive Overflow Indicator bit (SSPOV) .......................... 177

Register

RCREG Register ...................................................... 165

Registers

ADCON0 (ADC Control 0)........................................ 113

ADCON1 (ADC Control 1)........................................ 114

ADRESH (ADC Result High) with ADFM = 0) .......... 115

ADRESH (ADC Result High) with ADFM = 1) .......... 115

ADRESL (ADC Result Low) with ADFM = 0)............ 115

ADRESL (ADC Result Low) with ADFM = 1)............ 115

ANSEL (Analog Select) .............................................. 61

ANSELH (Analog Select High) ................................... 61

BAUDCTL (Baud Rate Control)................................ 160

CCPxCON (Enhanced CCPx Control)...................... 127

CM1CON0 (C1 Control).............................................. 98

CM2CON0 (C2 Control).............................................. 99

CM2CON1 (C2 Control)............................................ 101

CONFIG (Configuration Word) ................................. 195

ECCPAS (Enhanced CCP Auto-shutdown Control) . 141

Additional Pin Functions .............................................69

Weak Pull-Up......................................................69

Associated Registers ..................................................75

DS41262D-page 286

PIC16F631/677/685/687/689/690

EEADR (EEPROM Address) .................................... 120

SPI Mode.................................................................. 175, 181

Associated Registers................................................ 183

Bus Mode Compatibility............................................ 183

Effects of a Reset ..................................................... 183

Enabling SPI I/O....................................................... 179

Master Mode............................................................. 180

Master/Slave Connection ......................................... 179

Serial Clock (SCK pin).............................................. 175

Serial Data In (SDI pin)............................................. 175

Serial Data Out (SDO pin)........................................ 175

Slave Select.............................................................. 175

Slave Select Synchronization................................... 181

Sleep Operation........................................................ 183

SPI Clock.................................................................. 180

Typical Connection................................................... 179

SRCON Register .............................................................. 103

SSP

EECON1 (EEPROM Control 1)................................. 121

EEDAT (EEPROM Data) .......................................... 120

EEDATH (EEPROM Data)........................................ 120

INTCON (Interrupt Control)......................................... 38

IOCA (Interrupt-on-Change PORTA).......................... 62

IOCB (Interrupt-on-Change PORTB).......................... 70

OPTION_REG (OPTION) ..................................... 37, 83

OSCCON (Oscillator Control) ..................................... 48

OSCTUNE (Oscillator Tuning).................................... 52

PCON (Power Control Register)................................. 43

PCON (Power Control) ............................................. 199

PIE1 (Peripheral Interrupt Enable 1)........................... 39

PIE2 (Peripheral Interrupt Enable 2)........................... 40

PIR1 (Peripheral Interrupt Register 1) ........................ 41

PIR2 (Peripheral Interrupt Request 2) ........................ 42

PORTA........................................................................ 59

PORTB........................................................................ 69

PORTC ....................................................................... 76

PSTRCON (Pulse Steering Control)......................... 145

PWMxCON (Enhanced PWM Control) ..................... 144

RCSTA (Receive Status and Control)....................... 159

Reset Values............................................................. 201

Reset Values (special registers) ............................... 203

Special Function Register Map

Overview

SPI Master/Slave Connection................................... 179

2

SSP I C Operation ........................................................... 184

Slave Mode............................................................... 184

SSP Module

Clock Synchronization and the CKP Bit ................... 191

SPI Master Mode...................................................... 180

SPI Slave Mode........................................................ 181

SSPBUF ................................................................... 180

SSPSR ..................................................................... 180

SSPCON Register ............................................................ 177

SSPEN bit......................................................................... 177

SSPM bits......................................................................... 177

SSPMSK Register ............................................................ 187

SSPOV bit ........................................................................ 177

SSPSTAT Register........................................................... 176

STATUS Register ............................................................... 36

Synchronous Serial Port Enable bit (SSPEN) .................. 177

Synchronous Serial Port Mode Select bits (SSPM).......... 177

Synchronous Serial Port. See SSP

PIC16F677.......................................................... 28

PIC16F685.................................................... 27, 29

PIC16F687/689................................................... 30

PIC16F690.......................................................... 31

Special Function Registers ......................................... 26

Special Register Summary

Bank 0................................................................. 32

Bank 1................................................................. 33

Bank 2................................................................. 34

Bank 3................................................................. 35

SRCON (SR Latch Control) ...................................... 103

SSPCON (Sync Serial Port Control) Register........... 177

SSPMSK (SSP Mask)............................................... 187

SSPSTAT (Sync Serial Port Status) Register........... 176

STATUS...................................................................... 36

T1CON........................................................................ 88

T2CON........................................................................ 92

TRISA (Tri-State PORTA)........................................... 59

TRISB (Tri-State PORTB)........................................... 70

TRISC (Tri-State PORTC) .......................................... 76

TXSTA (Transmit Status and Control) ...................... 158

VRCON (Voltage Reference Control) ....................... 106

WDTCON (Watchdog Timer Control) ....................... 209

WPUA (Weak Pull-Up PORTA) .................................. 62

WPUB (Weak Pull-up PORTB)................................... 70

Reset................................................................................. 196

Revision History................................................................ 281

T

T1CON Register ................................................................. 88

T2CON Register ................................................................. 92

Thermal Considerations.................................................... 236

Time-out Sequence .......................................................... 199

Timer0 ................................................................................ 81

Associated Registers.................................................. 83

External Clock ............................................................ 82

Interrupt ...................................................................... 83

Operation.............................................................. 81, 84

Specifications ........................................................... 243

T0CKI ......................................................................... 82

Timer1 ................................................................................ 84

Associated registers ................................................... 89

Asynchronous Counter Mode..................................... 85

Reading and Writing........................................... 85

Interrupt ...................................................................... 86

Modes of Operation.................................................... 84

Operation During Sleep.............................................. 86

Oscillator..................................................................... 85

Prescaler .................................................................... 85

Specifications ........................................................... 243

Timer1 Gate

S

S (Start) bit........................................................................ 176

Shoot-through Current ...................................................... 143

Slave Select Synchronization ........................................... 181

Sleep................................................................................. 210

Wake-up.................................................................... 210

Wake-up Using Interrupts ......................................... 210

SMP bit ............................................................................. 176

Software Simulator (MPLAB SIM)..................................... 224

SPBRG ............................................................................. 161

SPBRGH........................................................................... 161

Special Event Trigger........................................................ 111

Special Function Registers ................................................. 26

Inverting Gate..................................................... 86

Selecting Source ........................................ 85, 101

Synchronizing COUT w/Timer1........................ 101

TMR1H Register......................................................... 84

TMR1L Register ......................................................... 84

DS41262D-page 287

PIC16F631/677/685/687/689/690

Timer2

Associated registers....................................................92

Timers

Timer1

T1CON................................................................88

Timer2

T2CON................................................................92

Timing Diagrams

A/D Conversion.........................................................253

Timing Parameter Symbology .......................................... 237

Timing Requirements

2

I C Bus Data............................................................. 251

I2C Bus Start/Stop Bits............................................. 250

SPI Mode.................................................................. 249

TRISA

Registers .................................................................... 59

TRISA Register................................................................... 59

TRISB

A/D Conversion (Sleep Mode) ..................................254

Asynchronous Reception ..........................................156

Asynchronous Transmission.....................................152

Asynchronous Transmission (Back to Back) ............152

Auto Wake-up Bit (WUE) During Normal Operation .166

Auto Wake-up Bit (WUE) During Sleep ....................167

Automatic Baud Rate Calculator...............................165

Brown-out Reset (BOR)............................................241

Brown-out Reset Situations ......................................198

CLKOUT and I/O.......................................................240

Clock Synchronization ..............................................192

Clock Timing .............................................................238

Comparator Output .....................................................93

Enhanced Capture/Compare/PWM (ECCP).............244

EUSART Synchronous Receive (Master/Slave) .......246

EUSART Synchronous Transmission

Registers .................................................................... 69

TRISB Register................................................................... 70

TRISC

Registers .................................................................... 76

TRISC Register................................................................... 76

Two-Speed Clock Start-up Mode........................................ 55

TXREG ............................................................................. 151

TXSTA Register................................................................ 158

BRGH Bit .................................................................. 161

U

UA..................................................................................... 176

Ultra Low-Power Wake-up.............. 14, 16, 18, 20, 22, 60, 63

Update Address bit, UA .................................................... 176

V

Voltage Reference (VR)

Specifications ........................................................... 245

Voltage Reference. See Comparator

Voltage Reference (CVREF)

Voltage References

Associated registers ................................................. 106

VP6 Stabilization ...................................................... 105

VRCON Register .............................................................. 106

VREF. SEE ADC Reference Voltage

(Master/Slave)...................................................246

Fail-Safe Clock Monitor (FSCM).................................58

Full-Bridge PWM Output ...........................................138

Half-Bridge PWM Output .................................. 136, 143

2

I C Bus Data.............................................................250

2

I C Bus Start/Stop Bits..............................................249

2

I C Reception (7-bit Address)...................................186

2

I C Slave Mode (Transmission, 10-bit Address).......190

2

I C Slave Mode with SEN = 0 (Reception,

10-bit Address)..................................................188

I C Transmission (7-bit Address)..............................189

W

2

Wake-up on Break............................................................ 166

Wake-up Using Interrupts................................................. 210

Watchdog Timer (WDT).................................................... 208

Associated registers ................................................. 209

Clock Source ............................................................ 208

Modes....................................................................... 208

Period ....................................................................... 208

Specifications ........................................................... 242

WCOL bit .......................................................................... 177

WDTCON Register ........................................................... 209

WPUA Register................................................................... 62

WPUB Register................................................................... 70

Write Collision Detect bit (WCOL) .................................... 177

WWW Address ................................................................. 289

WWW, On-Line Support ....................................................... 8

INT Pin Interrupt........................................................206

Internal Oscillator Switch Timing.................................54

PWM Auto-shutdown

Auto-restart Enabled.........................................142

Firmware Restart ..............................................142

PWM Direction Change ............................................139

PWM Direction Change at Near 100% Duty Cycle ...140

PWM Output (Active-High)........................................134

PWM Output (Active-Low) ........................................135

Reset, WDT, OST and Power-up Timer ...................241

Send Break Character Sequence .............................168

Slave Synchronization ..............................................181

SPI Master Mode (CKE = 1, SMP = 1) .....................247

SPI Mode (Master Mode)..........................................180

SPI Mode (Slave Mode with CKE = 0)......................182

SPI Mode (Slave Mode with CKE = 1)......................182

SPI Slave Mode (CKE = 0) .......................................248

SPI Slave Mode (CKE = 1) .......................................248

Synchronous Reception (Master Mode, SREN) .......172

Synchronous Transmission.......................................170

Synchronous Transmission (Through TXEN) ...........170

Time-out Sequence

Case 1...............................................................200

Case 2...............................................................200

Case 3...............................................................200

Timer0 and Timer1 External Clock ...........................243

Timer1 Incrementing Edge..........................................87

Two Speed Start-up ....................................................56

Wake-up from Interrupt .............................................211

DS41262D-page 288

PIC16F631/677/685/687/689/690

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

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customers. Accessible by using your favorite Internet

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Technical support is available through the web site

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To register, access the Microchip web site at

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DS41262D-page 289

PIC16F631/677/685/687/689/690

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

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PIC16F631/677/685/687/689/690

DS41262D

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS41262D-page 290

PIC16F631/677/685/687/689/690

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

XXX

Examples:

Temperature

Range

Package

Pattern

a)

b)

PIC16F685 - I/ML 301 = Industrial temp., QFN

package, QTP pattern #301.

PIC16F689 - I/SO = Industrial temp., SOIC

package.

c)

PIC16F690T - T/E/SS = Extended temp.,

SSOP package.

Device:

PIC16F631⁽¹⁾, PIC16F677⁽¹⁾, PIC16F685⁽¹⁾

,

PIC16F687⁽¹⁾, PIC16F689⁽¹⁾, PIC16F690⁽¹⁾

VDD range 2.0V to 5.5V

;

Temperature Range:

Package:

I

E

=

-40°C to +85°C (Industrial)

-40°C to +125°C (Extended)

ML

P

SO

SS

=

QFN (Quad Flat, no lead)

PDIP

SOIC

SSOP

Note 1:

T = in tape and reel SSOP, SOIC and

QFN packages only.

Pattern:

QTP, SQTP, Code or Special Requirements

(blank otherwise)

DS41262D-page 291

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Kokomo, IN

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Fax: 886-3-572-6459

China - Shenzhen

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Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Shunde

Tel: 86-757-2839-5507

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Taiwan - Taipei

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Santa Clara

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China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

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Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

12/08/06

DS41262D-page 292


型号：	PIC16F631-I/SO
厂家：	MICROCHIP
描述：	20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology 20引脚基于闪存的8位CMOS微控制器采用纳瓦技术闪存微控制器和处理器外围集成电路光电二极管 PC 时钟
文件：	总294页 (文件大小：5272K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC16F631-I/SO [MICROCHIP]

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