PIC16F716-E/SSVAO_技术文档

PIC16F716

Data Sheet

8-bit Flash-based Microcontroller

with A/D Converter and

Enhanced Capture/Compare/PWM

DS41206B

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•

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•

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•

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EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

DS41206B-page ii

PIC16F716

8-bit Flash-based Microcontroller with A/D Controller and

Enhanced Capture/Compare PWM

Microcontroller Core Features:

Low-Power Features:

• High-performance RISC CPU

• Standby Current:

• Only 35 single-word instructions to learn

- 100 nA @ 2.0V, typical

• Operating Current:

- All single-cycle instructions except for

program branches which are two-cycle

- 14 μA @ 32 kHz, 2.0V, typical

- 120 μA @ 1 MHz, 2.0V, typical

• Watchdog Timer Circuit:

- 1 μA @ 2.0V, typical

• Operating speed: DC – 20 MHz clock input

DC – 200 ns instruction cycle

• Interrupt capability

(up to 7 internal/external interrupt sources)

• Timer1 Oscillator Current:

• 8-level deep hardware stack

- 3.0 μA @ 32 kHz, 2.0V, typical

• Direct, Indirect and Relative Addressing modes

Peripheral Features:

Special Microcontroller Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Power-on Reset (POR)

• Timer1: 16-bit timer/counter with prescaler

can be incremented during Sleep via external

crystal/clock

• Power-up Timer (PWRT) and

Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

• Timer2: 8-bit timer/counter with 8-bit period

register, prescaler and postscaler

• Dual level Brown-out Reset circuitry

- 2.5 VBOR (Typical)

• Enhanced Capture, Compare, PWM module:

- Capture is 16-bit, max. resolution is 12.5 ns

- Compare is 16-bit, max. resolution is 200 ns

- PWM maximum resolution is 10-bit

- Enhanced PWM:

- 4.0 VBOR (Typical)

• Programmable code protection

• Power-Saving Sleep mode

• Selectable oscillator options

• Fully static design

- Single, Half-Bridge and Full-Bridge modes

- Digitally programmable dead-band delay

- Auto-shutdown/restart

• In-Circuit Serial Programming™ (ICSP™)

• 8-bit multi-channel Analog-to-Digital Converter

• 13 I/O pins with individual direction control

• Programmable weak pull-ups on PORTB

CMOS Technology:

• Wide operating voltage range:

- Industrial: 2.0V to 5.5V

- Extended: 3.0V to 5.5V

• High Sink/Source Current 25/25 mA

• Wide temperature range:

^{- Industrial: -40}°C to 85°C

- Extended: -40°C to 125°C

Memory

Device

8-bit A/D

(ch)

PWM

(outputs)

I/O

Timers 8/16

VDD Range

Flash

Data

PIC16F716

2048 x 14

128 x 8

13

4

2/1

1/2/4

2.0V-5.5V

DS41206B-page 1

PIC16F716

18-Pin Diagram

18-pin PDIP, SOIC

RA1/AN1

RA0/AN0

OSC1/CLKIN

OSC2/CLKOUT

VDD

RA2/AN2

RA3/AN3/VREF

1

2

3

4

5

18

17

16

15

14

RA4/T0CKI

MCLR/VPP

VSS

RB7/P1D

RB6/P1C

RB5/P1B

RB0/INT/ECCPAS2

RB1/T1OSO/T1CKI

6

7

8

9

13

12

11

RB2/T1OSI

RB3/CCP1/P1A

RB4/ECCPAS0

10

TABLE 1:

18-PIN PDIP, SOIC SUMMARY

I/O

Analog

ECCP

Timer

Interrupts

Pull-ups

Basic

RA0

RA1

RA2

RA3

17

18

1

AN0

AN1

AN2

—

2

3

AN3/VREF

—

T0CKI

—

Y

—

RA4

RB0

RB1

RB2

RB3

RB4

RB5

RB6

RB7

—

6

ECCPAS2

INT

—

7

—

T1CKI

T1OSI

—

Y

—

8

—

CCP1/P1A

ECCPAS0

P1B

—

Y

—

9

—

Y

10

11

12

13

14

5

—

IOC

—

Y

—

Y

—

P1C

P1D

—

Y

ICSPCLK

ICSPDAT

VDD

—

Y

—

VSS

—

4

—

MCLR/VPP

OSC1/CLKIN

OSC2/CLKOUT

—

16

15

—

DS41206B-page 2

PIC16F716

20-Pin Diagram

20-pin SSOP

RA1/AN1

RA0/AN0

OSC1/CLKIN

OSC2/CLKOUT

VDD

RA2/AN2

RA3/AN3/VREF

1

2

3

4

5

20

19

18

17

16

RA4/T0CKI

MCLR/VPP

VSS

VDD

6

15

RB7/P1D

RB6/P1C

RB0/INT/ECCPAS2

RB1/T1OSO/T1CKI

7

8

14

13

12

11

RB5/P1B

RB4/ECCPAS0

9

10

RB2/T1OSI

RB3/CCP1/P1A

TABLE 2:

20-PIN SSOP SUMMARY

I/O

Analog

ECCP

Timer

Interrupts

Pull-ups

Basic

RA0

RA1

RA2

RA3

19

20

1

AN0

AN1

AN2

—

2

3

AN3/VREF

—

T0CKI

—

Y

—

RA4

RB0

RB1

RB2

RB3

RB4

RB5

RB6

RB7

—

7

ECCPAS2

INT

—

8

—

T1CKI

T1OSI

—

Y

—

9

—

Y

—

10

11

12

13

14

15

16

5

CCP1/P1A

—

Y

ECCPAS0

—

IOC

—

Y

—

P1B

P1C

P1D

—

Y

—

Y

ICSPCLK

ICSPDAT

VDD

—

Y

—

VDD

—

VSS

—

6

—

VSS

—

4

—

MCLR/VPP

OSC1/CLKIN

OSC2/CLKOUT

—

18

17

—

DS41206B-page 3

PIC16F716

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 5

2.0 Memory Organization................................................................................................................................................................... 7

3.0 I/O Ports ..................................................................................................................................................................................... 19

4.0 Timer0 Module ........................................................................................................................................................................... 27

5.0 Timer1 Module with Gate Control............................................................................................................................................... 29

6.0 Timer2 Module ........................................................................................................................................................................... 35

7.0 Analog-to-Digital Converter (ADC) Module ................................................................................................................................ 37

8.0 Enhanced Capture/Compare/PWM Module ............................................................................................................................... 47

9.0 Special Features of the CPU...................................................................................................................................................... 61

10.0 Instruction Set Summary............................................................................................................................................................ 77

11.0 Development Support................................................................................................................................................................. 87

12.0 Electrical Characteristics ............................................................................................................................................................ 91

13.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 107

14.0 Packaging Information.............................................................................................................................................................. 121

Appendix A: Revision History............................................................................................................................................................. 125

Appendix B: Conversion Considerations............................................................................................................................................ 125

Appendix C: Migration from Base-line to Mid-Range Devices ........................................................................................................... 126

The Microchip Web Site..................................................................................................................................................................... 127

Customer Change Notification Service .............................................................................................................................................. 127

Customer Support.............................................................................................................................................................................. 127

Reader Response .............................................................................................................................................................................. 128

Index .................................................................................................................................................................................................. 129

Product Identification System............................................................................................................................................................. 133

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DS41206B-page 4

PIC16F716

1.0

DEVICE OVERVIEW

This document contains device specific information for

the PIC16F716. Figure 1-1 is the block diagram for the

PIC16F716 device. The pinouts are listed in Table 1-1.

FIGURE 1-1:

PIC16F716 BLOCK DIAGRAM

13

8

PORTA

Data Bus

RAM

Program Counter

Flash

RA0

RA11

RA2

RA3

RA4

2K x 14

Program

Memory

8 Level Stack

(13-bit)

128 x 8

File

Registers

Program

Bus

14

RAM Addr⁽¹⁾

PORTB

9

Addr MUX

RB0

RB1

RB2

RB3

RB4

RB5

RB6

RB7

Instruction Reg

Indirect

Addr

7

Direct Addr

8

FSR Reg

STATUS Reg

8

3

MUX

Power-up

Timer

Oscillator

Instruction

Decode and

Control

Start-up Timer

ALU

Power-on

Reset

8

OSC1/CLKIN

Timing

Generation

Watchdog

Timer

W Reg

OSC2/CLKOUT

Brown-out

Reset

MCLR VDD, VSS

Timer1

Timer2

A/D

Timer0

Enhanced CCP

(ECCP)

Note 1:

Higher order bits are from the STATUS register.

DS41206B-page 5

PIC16F716

TABLE 1-1:

Name

PIC16F716 PINOUT DESCRIPTION

Function

Input Type Output Type

Description

Master clear (Reset) input. This pin is an active-low Reset to

the device.

MCLR/VPP

MCLR

ST

—

VPP

P

—

Programming voltage input

Oscillator crystal input

External clock source input

RC Oscillator mode

OSC1/CLKIN

OSC1

CLKIN

OSC2

XTAL

CMOS

ST

OSC2/CLKOUT

XTAL

Oscillator crystal output. Connects to crystal or resonator in

Crystal Oscillator mode.

CLKOUT

—

CMOS

In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the

frequency of OSC1, and denotes the instruction cycle rate.

RA0/AN0

RA0

AN0

TTL

AN

TTL

AN

TTL

AN

TTL

AN

ST

CMOS

—

Bidirectional I/O

Analog Channel 0 input

RA1/AN1

RA1

CMOS

—

Bidirectional I/O

AN1

Analog Channel 1 input

RA2/AN2

RA2

CMOS

—

Bidirectional I/O

AN2

Analog Channel 2 input

RA3/AN3/VREF

RA3

CMOS

—

Bidirectional I/O

AN3

Analog Channel 3 input

VREF

RA4

—

A/D reference voltage input

Bidirectional I/O. Open drain when configured as output.

Timer0 external clock input

Bidirectional I/O. Programmable weak pull-up.

External Interrupt

RA4/T0CKI

OD

T0CKI

RB0

ST

—

RB0/INT/ECCPAS2

TTL

ST

CMOS

—

INT

ECCPAS2

RB1

ST

—

ECCP Auto-Shutdown pin

Bidirectional I/O. Programmable weak pull-up.

RB1/T1OSO/T1CKI

TTL

—

CMOS

XTAL

T1OSO

Timer1 oscillator output. Connects to crystal in Oscillator

mode.

T1CKI

RB2

ST

TTL

XTAL

TTL

ST

—

Timer1 external clock input

RB2/T1OSI

CMOS

—

Bidirectional I/O. Programmable weak pull-up.

Timer1 oscillator input. Connects to crystal in Oscillator mode.

Bidirectional I/O. Programmable weak pull-up.

Capture1 input, Compare1 output, PWM1 output.

PWM P1A output

T1OSI

RB3

RB3/CCP1/P1A

CMOS

CCP1

P1A

—

RB4/ECCPAS0

RB5/P1B

RB4

TTL

Bidirectional I/O. Programmable weak pull-up. Interrupt-on-

change.

ECCPAS0

RB5

ST

—

ECCP Auto-Shutdown pin

TTL

CMOS

Bidirectional I/O. Programmable weak pull-up. Interrupt-on-

change.

P1B

RB6

—

CMOS

PWM P1B output

RB6/P1C

TTL

Bidirectional I/O. Programmable weak pull-up. Interrupt-on-

change. ST input when used as ICSP programming clock.

P1C

RB7

—

CMOS

PWM P1C output

RB7/P1D

TTL

Bidirectional I/O. Programmable weak pull-up. Interrupt-on-

change. ST input when used as ICSP programming data.

P1D

VSS

VDD

AN

—

P

CMOS

—

PWM P1D output

VSS

VDD

Ground reference for logic and I/O pins.

Positive supply for logic and I/O pins.

P

—

Legend:

I

= Input

O = Output

= Power

= Analog input or output

OD

ST

= Open drain

= Schmitt Trigger input with CMOS levels

TTL = TTL compatible input

XTAL = Crystal

P

CMOS = CMOS compatible input or output

DS41206B-page 6

PIC16F716

2.2

Data Memory Organization

2.0

MEMORY ORGANIZATION

The data memory is partitioned into multiple banks

which contain the General Purpose Registers (GPR)

and the Special Function Registers (SFR). Bits RP1

and RP0 of the STATUS register are the bank select

bits.

There are two memory blocks in the PIC16F716

device. Each block (program memory and data

memory) has its own bus so that concurrent access

can occur.

2.1

Program Memory Organization

RP<1:0>⁽¹⁾

Bank

(Status<6:5>)

The PIC16F716 has a 13-bit program counter capable

of addressing an 8K x 14 program memory space. The

PIC16F716 has 2K x 14 words of program memory.

Accessing a location above the physically implemented

address will cause a wrap-around.

00

01

10

11

0

1

2⁽²⁾

3⁽²⁾

The Reset vector is at 0000h and the interrupt vector is

at 0004h.

Note 1: Maintain Status bit 6 clear to ensure

upward compatibility with future products.

FIGURE 2-1:

PROGRAM MEMORY MAP

AND STACK OF

PIC16F716

2: Not implemented

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Function Registers. Above the Special Function

PC<12:0>

13

Registers

are

General

Purpose

Registers,

implemented as static RAM. All implemented banks

contain Special Function Registers. The upper 16

bytes of GPR space and some “high use” Special

Function Registers in Bank 0 are mirrored in Bank 1 for

code reduction and quicker access.

CALL, RETURN

RETFIE, RETLW

Stack Level 1

Stack Level 8

Reset Vector

0000h

Interrupt Vector

0004h

0005h

On-chip Program

Memory

07FFh

0800h

1FFFh

DS41206B-page 7

PIC16F716

2.2.1

GENERAL PURPOSE REGISTER

FILE

FIGURE 2-2:

REGISTER FILE MAP

The register file can be accessed either directly or

indirectly through the File Select Register FSR

(Section 2.5 “Indirect Addressing, INDF and FSR

Registers”).

File

Address

File

Address

80h

OPTION_REG 81h

(1)

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

INDF

TMR0

PCL

STATUS

FSR

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

STATUS

FSR

PORTA

PORTB

TRISA

TRISB

PCLATH

INTCON

PIR1

PCLATH

INTCON

PIE1

TMR1L

TMR1H

T1CON

TMR2

PCON

T2CON

PR2

CCPR1L

CCPR1H

17h CCP1CON

18h PWM1CON

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

ECCPAS

ADRES

ADCON0

ADCON1

General

Purpose

Registers

General

Purpose

Registers

32 Bytes

BFh

80 Bytes

C0h

EFh

6Fh

70h

7Fh

16 Bytes

Bank 0

Accesses

70-7Fh

F0h

FFh

Bank 1

Unimplemented data memory locations,

read as ‘0’.

Note 1: Not a physical register.

DS41206B-page 8

PIC16F716

2.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral modules for controlling the

desired operation of the device. These registers are

implemented as static RAM. A list of these registers is

give in Table 2-1.

The Special Function Registers can be classified into

two sets; core (CPU) and peripheral. Those registers

associated with the core functions are described in

detail in this section. Those related to the operation of

the peripheral features are described in detail in that

peripheral feature section.

TABLE 2-1:

SPECIAL FUNCTION REGISTER SUMMARY BANK 0

Value on

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

00h

01h

02h

INDF⁽¹⁾

TMR0

PCL⁽¹⁾

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 module’s register

0000 0000

xxxx xxxx

0000 0000

18

27

17

Program Counter’s (PC) Least Significant Byte

03h

STATUS⁽¹⁾

FSR⁽¹⁾

PORTA^(5,6)

PORTB^(5,6)

—

PCLATH^(1,2)

INTCON⁽¹⁾

PIR1

IRP⁽⁴⁾

RP1⁽⁴⁾

RP0

TO

PD

Z

DC

C

0001 1xxx

xxxx xxxx

---x 0000

xxxx xxxx

—

11

18

19

21

04h

Indirect Data Memory Address Pointer

(7)

05h

—

RA4

RB4

RA3

RB3

RA2

RB2

RA1

RB1

RA0

RB0

06h

RB7

RB6

RB5

07h-09h

0Ah

Unimplemented

—

T0IE

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

0000 000x

-0-- -000

—

17

13

15

0Bh

GIE

PEIE

ADIF

INTE

—

RBIE

—

T0IF

INTF

RBIF

0Ch

0Dh

0Eh

—

CCP1IF

TMR2IF

TMR1IF

—

Unimplemented

TMR1L

TMR1H

T1CON

TMR2

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx

29

32

35

36

0Fh

10h

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

Timer2 Module’s Register

TMR1CS TMR1ON --00 0000

11h

0000 0000

12h

T2CON

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000

13h-14h

15h

Unimplemented

—

CCPR1L

CCPR1H

CCP1CON

PWM1CON

ECCPAS

—

Capture/Compare/PWM Register 1 (LSB)

Capture/Compare/PWM Register 1 (MSB)

xxxx xxxx

0000 0000

00-0 0000

—

48

60

57

16h

17h

P1M1

P1M0

PDC6

DC1B1

PDC5

DC1B0

PDC4

CCP1M3

PDC3

CCP1M2

PDC2

CCP1M1

PDC1

CCP1M0

PDC0

18h

PRSEN

(8)

19h

ECCPASE ECCPAS2

Unimplemented

—

ECCPAS0 PSSAC1

PSSAC0

PSSBD1

PSSBD0

1Ah-1Dh

1Eh

ADRES

A/D Result Register

xxxx xxxx

37

41

(7)

1Fh

ADCON0

ADCS1

ADCS0

CHS2

CHS1

CHS0

GO/DONE

—

ADON

0000 0000

Legend:

x= unknown, u= unchanged, q= value depends on condition, – = unimplemented, read as ‘0’, Shaded locations are unimplemented,

read as ‘0’.

Note 1:

2:

These registers can be addressed from either bank.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are

transferred to the upper byte of the program counter.

3:

4:

5:

6:

7:

8:

Other (non Power-up) Resets include: external Reset through MCLR and the Watchdog Timer Reset.

The IRP and RP1 bits are reserved. Always maintain these bits clear.

On any device Reset, these pins are configured as inputs.

This is the value that will be in the PORT output latch.

Reserved bits, do not use.

ECCPAS1 bit is not used on PIC16F716.

DS41206B-page 9

PIC16F716

TABLE 2-2:

SPECIAL FUNCTION REGISTER SUMMARY BANK 1

Value on

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

80h

INDF⁽¹⁾

Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000

18

81h

82h

OPTION_REG

PCL⁽¹⁾

RBPU

Program Counter’s (PC) Least Significant Byte

IRP⁽⁴⁾RP1⁽⁴⁾

RP0 TO

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

0000 0000

12

17

83h

STATUS⁽¹⁾

FSR⁽¹⁾

TRISA

TRISB

—

PCLATH^(1,2)

INTCON⁽¹⁾

PIE1

PD

Z

DC

C

0001 1xxx

xxxx xxxx

---1 1111

1111 1111

—

11

18

19

21

84h

Indirect Data Memory Address Pointer

(7)

85h

—

TRISA4

TRISA3

TRISB3

TRISA2

TRISB2

TRISA1

TRISB1

TRISA0

TRISB0

86h

TRISB7

TRISB6

TRISB5 TRISB4

87h-89h

8Ah

8Bh

8Ch

8Dh

Unimplemented

—

GIE

—

T0IE

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

0000 000x

-0-- -000

—

17

13

14

PEIE

ADIE

INTE

—

RBIE

—

T0IF

INTF

RBIF

CCP1IE

TMR2IE

TMR1IE

—

Unimplemented

8Eh

PCON

—

POR

BOR

---- --qq

—

16

35, 52

42

8Fh-91h

92h

Unimplemented

Timer2 Period Register

Unimplemented

PR2

1111 1111

—

93h-9Eh

9Fh

—

ADCON1

—

PCFG2

PCFG1

PCFG0

---- -000

Legend:

x= unknown, u= unchanged, q= value depends on condition, -= unimplemented, read as ‘0’, Shaded locations are unimplemented,

read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are

transferred to the upper byte of the program counter.

3: Other (non Power-up) Resets include: external Reset through MCLR and the Watchdog Timer Reset.

4: The IRP and RP1 bits are reserved. Always maintain these bits clear.

5: On any device Reset, these pins are configured as inputs.

6: This is the value that will be in the PORT output latch.

7: Reserved bits, do not use.

DS41206B-page 10

PIC16F716

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register because these instructions do not

affect the Z, C or DC bits from the STATUS register. For

other instructions, not affecting any Status bits, see the

“Instruction Set Summary.”

2.2.2.1

STATUS Register

The STATUS register, shown in Register 2-1, contains

the arithmetic status of the ALU, the Reset status and

the bank select bits for data memory.

The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

Note 1: The PIC16F716 does not use bits IRP

and RP1 of the STATUS register. Main-

tain these bits clear to ensure upward

compatibility with future products.

2: The C and DC bits operate as a borrow

and digit borrow bit, respectively, in

subtraction.

For example, CLRF STATUSwill clear the upper-three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu(where u= unchanged).

REGISTER 2-1:

STATUS: STATUS REGISTER

Reserved

IRP

Reserved

RP1

R/W-0

RP0

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC

R/W-x

C

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

bit 6

bit 5

IRP: This bit is reserved and should be maintained as ‘0’

RP1: This bit is reserved and should be maintained as ‘0’

RP0: Register Bank Select bit (used for direct addressing)

1= Bank 1 (80h-FFh)

0= Bank 0 (00h-7Fh)

bit 4

bit 3

bit 2

bit 1

TO: Time-out bit

1= After power-up, CLRWDTinstruction or SLEEPinstruction

0= A WDT time-out occurred

PD: Power-down bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions), For Borrow, the polarity is

reversed.

1= A carry-out from the 4th low-order bit of the result occurred

0= No carry-out from the 4th low-order bit of the result

bit 0

C: Carry/Borrow bit⁽¹⁾(ADDWF, ADDLW, SUBLW, SUBWF instructions)

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the sec-

ond operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit

of the source register.

DS41206B-page 11

PIC16F716

2.2.2.2

OPTION Register

Note:

To achieve a 1:1 prescaler assignment for

the Timer0 register, assign the prescaler

to the Watchdog Timer.

The OPTION register is a readable and writable regis-

ter, which contains various control bits to configure the

TMR0 prescaler/WDT postscaler (single assignable

register known also as the prescaler), the External INT

Interrupt, TMR0 and the weak pull-ups on PORTB.

REGISTER 2-2:

OPTION_REG: OPTION REGISTER

R/W-1

RBPU

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

PS2

R/W-1

PS1

R/W-1

PS0

INTEDG

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

RBPU: PORTB Pull-up Enable bit

1= PORTB pull-ups are disabled

0= PORTB pull-ups are enabled by individual PORT latch values

INTEDG: Interrupt Edge Select bit

1= Interrupt on rising edge of RB0/INT pin

0= Interrupt on falling edge of RB0/INT pin

T0CS: Timer0 Clock Source Select bit

1= Transition on RA4/T0CKI pin

0= Internal instruction cycle clock (FOSC/4)

T0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on RA4/T0CKI pin

0= Increment on low-to-high transition on RA4/T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler is assigned to the WDT

0= Prescaler is assigned to the Timer0 module

PS<2:0>: Prescaler Rate Select bits

Bit Value

Timer0 Rate WDT Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

DS41206B-page 12

PIC16F716

2.2.2.3

INTCON Register

Note:

Interrupt flag bits get set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

The INTCON Register is a readable and writable

register which contains various enable and flag bits for

the TMR0 register overflow, RB Port change and

external RB0/INT pin interrupts.

REGISTER 2-3:

INTCON: INTERRUPT CONTROL REGISTER

R/W-0

GIE

R/W-0

PEIE

R/W-0

T0IE

R/W-0

INTE

R/W-0

RBIE⁽¹⁾

R/W-0

T0IF⁽²⁾

R/W-0

INTF

R/W-x

RBIF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

GIE: Global Interrupt Enable bit

1= Enables all unmasked interrupts

0= Disables all interrupts

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

PEIE: Peripheral Interrupt Enable bit

1= Enables all unmasked peripheral interrupts

0= Disables all peripheral interrupts

T0IE: Timer0 Overflow Interrupt Enable bit

1= Enables the Timer0 interrupt

0= Disables the Timer0 interrupt

INTE: RB0/INT External Interrupt Enable bit

1= Enables the RB0/INT external interrupt

0= Disables the RB0/INT external interrupt

RBIE: PORTB Change Interrupt Enable bit⁽¹⁾

1= Enables the PORTB change interrupt

0= Disables the PORTB change interrupt

T0IF: Timer0 Overflow Interrupt Flag bit⁽²⁾

1= TMR0 register has overflowed (must be cleared in software)

0= TMR0 register did not overflow

INTF: RB0/INT External Interrupt Flag bit

1= The RB0/INT external interrupt occurred (must be cleared in software)

0= The RB0/INT external interrupt did not occur

RBIF: PORTB Change Interrupt Flag bit

1 = When at least one of the PORTB general purpose I/O pins changed state (must be cleared in

software)

0= None of the PORTB general purpose I/O pins have changed state

Note 1: IOCB register must also be enabled.

2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before

clearing T0IF bit.

DS41206B-page 13

PIC16F716

2.2.2.4

PIE1 Register

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

This register contains the individual enable bits for the

peripheral interrupts.

REGISTER 2-4:

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

U-0

—

R/W-0

ADIE

U-0

—

U-0

—

U-0

—

R/W-0

CCP1IE

TMR2IE

TMR1IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

ADIE: A/D Converter (ADC) Interrupt Enable bit

1= Enables the ADC interrupt

0= Disables the ADC interrupt

bit 5-3

bit 2

Unimplemented: Read as ‘0’

CCP1IE: CCP1 Interrupt Enable bit

1= Enables the CCP1 interrupt

0= Disables the CCP1 interrupt

bit 1

bit 0

TMR2IE: Timer2 to PR2 Match Interrupt Enable bit

1= Enables the Timer2 to PR2 match interrupt

0= Disables the Timer2 to PR2 match interrupt

TMR1IE: Timer1 Overflow Interrupt Enable bit

1= Enables the Timer1 overflow interrupt

0= Disables the Timer1 overflow interrupt

DS41206B-page 14

PIC16F716

2.2.2.5

PIR1 Register

Note:

Interrupt flag bits get set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

This register contains the individual flag bits for the

peripheral interrupts.

REGISTER 2-5:

PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

U-0

—

R/W-0

ADIF

R/W-0

—

R/W-0

—

R/W-0

—

U-0

R/W-0

CCP1IF

TMR2IF

TMR1IF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

ADIF: A/D Interrupt Flag bit

1= A/D conversion complete

0= A/D conversion has not completed or has not been started

bit 5-3

bit 2

Unimplemented: Read as ‘0’

CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1= A TMR1 register capture occurred (must be cleared in software)

0= No TMR1 register capture occurred

Compare Mode

1= A TMR1 register compare match occurred (must be cleared in software)

0= No TMR1 register compare match occurred

PWM Mode

Unused in this mode

bit 1

bit 0

TMR2IF: Timer2 to PR2 Match Interrupt Flag bit

1= Timer2 to PR2 match occurred (must be cleared in software)

0= Timer2 to PR2 match has not occurred

TMR1IF: Timer1 Overflow Interrupt Flag bit

1= Timer1 register overflowed (must be cleared in software)

0= Timer1 has not overflowed

DS41206B-page 15

PIC16F716

2.2.2.6

PCON Register

Note:

If the BOREN Configuration bit is set, BOR

is ‘1’ on Power-on Reset and reset to ‘0’

when a Brown-out condition occurs. BOR

must then be set by the user and checked

on subsequent Resets to see if it is clear,

indicating that another Brown-out has

occurred.

The Power Control (PCON) register contains a flag bit

to allow differentiation between a Power-on Reset

(POR) to an external MCLR Reset or WDT Reset.

These devices contain an additional bit to differentiate

a Brown-out Reset condition from a Power-on Reset

condition.

If the BOREN Configuration bit is clear,

BOR is unknown on Power-on Reset.

REGISTER 2-6:

PCON: POWER CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

POR

R/W-x

BOR

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-2

bit 1

Unimplemented: Read as ‘0’

POR: Power-on Reset Status bit

1= No Power-on Reset occurred

0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0

BOR: Brown-out Reset Status bit

1= No Brown-out Reset occurred

0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

DS41206B-page 16

PIC16F716

FIGURE 2-3:

LOADING OF PC IN

DIFFERENT SITUATIONS

2.3

PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<12:8>) is not directly

readable or writable and comes from PCLATH. On any

Reset, the PC is cleared. Figure 2-3 shows the two

situations for the loading of the PC. The upper example

in Figure 2-3 shows how the PC is loaded on a write to

PCL (PCLATH<4:0> → PCH). The lower example in

Figure 2-3 shows how the PC is loaded during a CALLor

GOTOinstruction (PCLATH<4:3> → PCH).

PCH

12

PCL

8 7

0

Instruction with

PCL as

Destination

8

PCLATH<4:0>

ALU

5

PCLATH

PCL

PCH

12 1110

0

8 7

GOTO, CALL

11

PCLATH<4:3>

PCLATH

Opcode <10:0>

2.3.1

MODIFYING PCL

2

Executing any instruction with the PCL register as the

destination simultaneously causes the Program

Counter PC<12:8> bits (PCH) to be replaced by the

contents of the PCLATH register. This allows the entire

contents of the program counter to be changed by

writing the desired upper 5 bits to the PCLATH register.

When the lower 8 bits are written to the PCL register, all

13 bits of the program counter will change to the values

contained in the PCLATH register and those being

written to the PCL register.

2.4

Stack

The stack allows a combination of up to 8 program calls

and interrupts to occur. The stack contains the return

address from this branch in program execution.

Mid-range devices have an 8-level deep x 13-bit wide

hardware stack. The stack space is not part of either

program or data space, and the Stack Pointer is not

readable or writable. The PC is PUSHed onto the stack

when a CALL instruction is executed or an interrupt

causes a branch. The stack is POPed in the event of a

RETURN, RETLWor a RETFIE instruction execution.

PCLATH is not modified when the stack is PUSHed or

POPed.

A computed GOTOis accomplished by adding an offset

to the program counter (ADDWF PCL). Care should be

exercised when jumping into a look-up table or

program branch table (computed GOTO) by modifying

the PCL register. Assuming that PCLATH is set to the

table start address, if the table length is greater than

255 instructions or if the lower 8 bits of the memory

address rolls over from 0xFF to 0x00 in the middle of

the table, then PCLATH must be incremented for each

address rollover that occurs between the table

beginning and the target location within the table.

After the stack has been PUSHed 8 times, the ninth

push overwrites the value that was stored from the first

push. The tenth push overwrites the second push (and

so on).

For more information refer to Application Note AN556,

“Implementing a Table Read” (DS00556).

2.3.2

PROGRAM MEMORY PAGING

The CALL and GOTO instructions provide 11 bits of

address to allow branching within any 2K program

memory page. When doing a CALLor GOTOinstruction,

the upper bit of the address is provided by

PCLATH<3>. When doing a CALLor GOTOinstruction,

the user must ensure that the page select bit is

programmed so that the desired program memory

page is addressed. If a RETURNfrom a CALLinstruction

(or interrupt) is executed, the entire 13-bit PC is pushed

onto the stack. Therefore, manipulation of the

PCLATH<3> bit is not required for the RETURN

instructions (which POPs the address from the stack).

DS41206B-page 17

PIC16F716

EXAMPLE 2-2:

HOW TO CLEAR RAM

USING INDIRECT

ADDRESSING

2.5

Indirect Addressing, INDF and

FSR Registers

The INDF register is not a physical register. Addressing

INDF actually addresses the register whose address is

contained in the FSR register (FSR is a pointer). This is

indirect addressing.

MOVLW 0x20

MOVWF FSR

CLRF INDF

INCF FSR

;initialize pointer

;to RAM

;clear RAM & FSR

;inc pointer

EXAMPLE 2-1:

INDIRECT ADDRESSING

GOTO

;yes, continue

CONTINUE

• Register file 05 contains the value 10h

• Register file 06 contains the value 0Ah

• Load the value 05 into the FSR register

:

An effective 9-bit address is obtained by concatenating

the 8-bit FSR register and the IRP bit of the STATUS

register, as shown in Figure 2-4. However, IRP is not

used in the PIC16F716.

• A read of the INDF register will return the value of

10h

• Increment the value of the FSR register by one

(FSR = 06)

• A read of the INDR register now will return the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce

00h. Writing to the INDF register indirectly results in a

no-operation (although Status bits may be affected).

A simple program to clear RAM locations 20h-2Fh

using indirect addressing is shown in Example 2-2.

FIGURE 2-4:

DIRECT/INDIRECT ADDRESSING

Direct Addressing

from opcode

Indirect Addressing

RP1:

7

RP0

6

0

IRP

FSR register

(2)

bank select

location select

bank select

location select

00

01

80h

10

100h

11

00h

180h

(3)

Data

Memory

(1)

7Fh

Bank 0

Note 1: For register file map detail see Figure 2-2.

FFh

17Fh

Bank 2

1FFh

Bank 3

Bank 1

2: Maintain clear for upward compatibility with future products.

3: Not implemented.

DS41206B-page 18

PIC16F716

EXAMPLE 3-1:

INITIALIZING PORTA

3.0

I/O PORTS

Some pins for these I/O ports are multiplexed with an

alternate function for the peripheral features on the

device. In general, when a peripheral is enabled, that

pin may not be used as a general purpose I/O pin.

BCF

CLRF

STATUS, RP0

PORTA

;

;Initialize PORTA by

;clearing output

;data latches

BSF

STATUS, RP0 ;Select Bank 1

MOVLW 0xEF

;Value used to

;initialize data

;direction

;Set RA<3:0> as inputs

;RA<4> as outputs

3.1

PORTA and the TRISA Register

PORTA is

a 5-bit wide bidirectional port. The

MOVWF TRISA

corresponding data direction register is TRISA. Setting

a TRISA bit (= 1) will make the corresponding PORTA

pin an input (i.e., put the corresponding output driver in

a High-impedance mode). Clearing a TRISA bit (= 0)

will make the corresponding PORTA pin an output (i.e.,

put the contents of the output latch on the selected pin).

BCF

STATUS, RP0 ;Return to Bank 0

FIGURE 3-1:

BLOCK DIAGRAM OF

RA<3:0>

Reading the PORTA register reads the status of the

pins, whereas writing to it will write to the PORT latch.

All write operations are read-modify-write operations.

Therefore, a write to a port implies that the port pins are

read, the value is modified and then written to the

PORT data latch.

DATA

BUS

D

Q

VDD

WR

PORT

CK

P

Pin RA4 is multiplexed with the Timer0 module clock

input to become the RA4/T0CKI pin. The RA4/T0CKI

pin is a Schmitt Trigger input and an open drain output.

All other RA port pins have TTL input levels and full

CMOS output drivers.

Data Latch

I/O pin

N

D

Q

WR

VSS

TRIS

CK

Q

PORTA pins, RA<3:0>, are multiplexed with analog

inputs and analog VREF input. The operation of each

pin is selected by clearing/setting the control bits in the

ADCON1 register (A/D Control Register 1).

Analog

Input

mode

TRIS Latch

Note:

On a Power-on Reset, these pins are

configured as analog inputs and read as

‘0’.

RD TRIS

Q

TTL

Input

Buffer

D

The TRISA register controls the direction of the RA

pins, even when they are being used as analog inputs.

The user must ensure the bits in the TRISA register are

maintained set when using them as analog inputs.

EN

RD PORT

Note:

Setting RA3:0 to output while in Analog

mode will force pins to output contents of

data latch.

To A/D Converter

DS41206B-page 19

PIC16F716

FIGURE 3-2:

BLOCK DIAGRAM OF

RA4/T0CKI PIN

Data Latch

DATA

BUS

Q

D

RA4/T0CKI

WR

PORT

CK

Q

N

TRIS Latch

VSS

Q

D

VSS

WR

TRIS

Schmitt

Trigger

Input

CK

Q

Buffer

RD TRIS

Q

D

EN

RD PORT

Timer0 Clock Input

TABLE 3-1:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on

all other

Resets

Value on

POR, BOR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTA

TRISA

—

RA4

RA3

RA2

RA1

RA0

---x 0000 ---u uuuu

TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111

PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

ADCON1

—

Legend: x= unknown, u= unchanged, –= unimplemented locations read as ‘0’. Shaded cells are not used by

PORTA.

DS41206B-page 20

PIC16F716

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTB pin. Some

peripherals override the TRIS bit to make a pin an

output, while other peripherals override the TRIS bit to

make a pin an input. Since the TRIS bit override is in

effect while the peripheral is enabled, read-modify-

write instructions (such as BSF, BCF, XORWF) with

TRISB as the destination should be avoided. The user

should refer to the corresponding peripheral section for

the correct TRIS bit settings.

3.2

PORTB and the TRISB Register

PORTB is an 8-bit wide bidirectional port. The

corresponding data direction register is TRISB. Setting

a TRISB bit (= 1) will make the corresponding PORTB

pin an input (i.e., put the corresponding output driver in

a High-Impedance mode). Clearing a TRISB bit (= 0)

will make the corresponding PORTB pin an output (i.e.,

put the contents of the output latch on the selected pin).

EXAMPLE 3-2:

INITIALIZING PORTB

Four of PORTB’s pins, RB<7:4>, have an interrupt-on-

change feature. Only pins configured as inputs can

cause this interrupt to occur (i.e., any RB<7:4> pin

configured as an output is excluded from the interrupt-

on-change comparison). The input pins, RB<7:4>, are

compared with the old value latched on the last read of

PORTB. The “mismatch” outputs of RB<7:4> are

OR’ed together to generate the RB Port Change

Interrupt with flag bit RBIF of the INTCON register.

BCF

CLRF

STATUS, RP0

;select Bank 0

PORTB

;Initialize PORTB by

;clearing output

;data latches

BSF

MOVLW

STATUS, RP0

0xCF

;Select Bank 1

;Value used to

;initialize data

;direction

MOVWF

TRISB

;Set RB<3:0> as inputs

;RB<5:4> as outputs

;RB<7:6> as inputs

This interrupt can wake the device from Sleep. The

user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

1. Perform a read of PORTB to end the mismatch

condition.

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is

performed by clearing bit RBPU of the OPTION regis-

ter. The weak pull-up is automatically turned off when

the port pin is configured as an output. The pull-ups are

disabled on a Power-on Reset.

2. Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.

Reading PORTB will end the mismatch condition and

allow flag bit RBIF to be cleared.

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

FIGURE 3-3:

BLOCK DIAGRAM OF

RB0/INT/ECCPAS2 PIN

VDD

RBPU⁽¹⁾

weak

pull-up

P

Data Latch

DATA

BUS

D

Q

RB0/

INT/

ECCPAS2

WR

PORT

CK

TRIS Latch

D

Q

VSS

WR

CK

TRIS

TTL

Input

Buffer

RD TRIS

Q

D

EN

RD PORT

Schmitt Trigger

Buffer

RB0/INT

RD PORT

ECCPAS2: ECCP Auto-shutdown input

Note 1:

To enable weak pull-ups, set the appropriate TRIS

bit(s) and clear the RBPU bit (OPTION register).

DS41206B-page 21

PIC16F716

FIGURE 3-4:

BLOCK DIAGRAM OF RB1/T1OSO/T1CKI PIN

VDD

weak

RBPU⁽¹⁾

T1OSCEN

P

pull-up

VDD

Data Latch

DATA BUS

RB1/T1OSO/T1CKI

D

Q

WR PORTB

CK

TRIS Latch

VSS

D

Q

WR TRISB

CK

RD TRISB

T1OSCEN

TTL Buffer

Q

D

EN

RD PORTB

T1OSI (From RB2)

TMR1 oscillator

To Timer1 clock input

ST Buffer

Note 1:

To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION register).

FIGURE 3-5:

BLOCK DIAGRAM OF RB2/T1OSI PIN

VDD

RBPU⁽¹⁾

T1OSCEN

weak

P

VDD

pull-up

Data Latch

DATA BUS

D

Q

RB2/T1OSI

WR PORTB

CK

TRIS Latch

D

Q

VSS

WR TRISB

Q

CK

RD TRIS

T1OSCEN

TTL Buffer

Q

D

EN

RD PORTB

TMR1

Oscillator

T1OSO (To RB1)

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION register).

DS41206B-page 22

PIC16F716

FIGURE 3-6:

BLOCK DIAGRAM OF RB3/CCP1/P1A PIN

VDD

weak

RBPU⁽¹⁾

[PWMA(P1A) / CCP1 Compare] Output Enable

VDD

P

pull-up

[PWMA(P1A) / CCP1 Compare] Output

PWMA(P1A) Auto-shutdown tri-state

1

0

RB3/CCP1/P1A

VSS

Data Latch

DATA BUS

D

Q

WR PORTB

Q

CK

TRIS Latch

D

Q

WR TRISB

RD TRIS

CK

Q

TTL Buffer

Q

D

EN

RD PORTB

Schmitt Trigger Buffer

CCP – Capture input

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION register).

FIGURE 3-7:

BLOCK DIAGRAM OF RB4/ECCPAS0 PIN

VDD

RBPU⁽¹⁾

VDD

weak

P

pull-up

Data Latch

DATA BUS

RB4/ECCPAS0

D

Q

WR PORTB

CK

TRIS Latch

D

Q

VSS

WR TRISB

TTL

Buffer

CK

ST

Buffer

RD TRIS

Latch

Q

D

EN

Q1

RD PORT

Set RBIF

D

From other

RB<7:4> pins

Note 1: To enable weak pull-ups, set

the appropriate TRIS bit(s)

and clear the RBPU bit of the

OPTION register.

RD PORT

Q3

EN

ECCPAS0: ECCP Auto-Shutdown input

DS41206B-page 23

PIC16F716

FIGURE 3-8:

BLOCK DIAGRAM OF RB5/P1B PIN

VDD

weak

RBPU⁽¹⁾

PWMB(P1B) Enable

VDD

P

pull-up

PWMB(P1B) Data out

PWMB(P1B) Auto-shutdown tri-state

1

0

RB5/P1B

Data Latch

DATA BUS

D

Q

WR PORTB

WR TRISB

CK

TRIS Latch

VSS

D

Q

TTL

Buffer

Q

CK

RD TRISB

Latch

Q

D

EN

Q1

RD PORTB

Set RBIF

Q

D

From other

RB<7:4> pins

RD PORTB

Q3

EN

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION register).

FIGURE 3-9:

BLOCK DIAGRAM OF RB6/P1C PIN

VDD

RBPU⁽¹⁾

weak

PWMC(P1C) Enable

VDD

P

pull-up

PWMC(P1C) Data out

PWMC(P1C) Auto-shutdown tri-state

1

0

RB6/P1C

Data Latch

DATA BUS

D

Q

WR PORTB

WR TRISB

CK

TRIS Latch

VSS

D

Q

TTL

Buffer

Q

CK

ST

Buffer

RD TRISB

Latch

Q

D

EN

RD PORTB

Q1

Set RBIF

Q

D

From other

RB<7:4> pins

RD PORTB

Q3

EN

ICSPC – In-Circuit Serial Programming™ Clock Input

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION register).

DS41206B-page 24

PIC16F716

FIGURE 3-10:

BLOCK DIAGRAM OF RB7/P1D PIN

VDD

weak

RBPU⁽¹⁾

PWMD(P1D) Enable

VDD

P

pull-up

PWMD(P1D) Data out

PWMD(P1D) Auto-shutdown tri-state

1

0

RB7/P1D

Data Latch

DATA BUS

D

Q

WR PORTB

WR TRISB

CK

TRIS Latch

VSS

D

Q

TTL

Buffer

Q

ST

Buffer

CK

RD TRISB

Latch

Q

D

EN

Q1

RD PORTB

Set RBIF

Q

D

From other

Note 1: To enable weak pull-ups,

set the appropriate TRIS

RB<7:4> pins

RD PORTB

Q3

EN

bit(s) and clear the RBPU

bit of the OPTION register.

ICSPD – In-Circuit Serial Programming™ Data Input

TABLE 3-2:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

PORTB

TRISB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx xxxx uuuu uuuu

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

OPTION_REG RBPU INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111 1111 1111

Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.

DS41206B-page 25

PIC16F716

NOTES:

DS41206B-page 26

PIC16F716

4.1

Timer0 Operation

4.0

TIMER0 MODULE

When used as a timer, the Timer0 module can be used

as either an 8-bit timer or an 8-bit counter.

The Timer0 module is an 8-bit timer/counter with the

following features:

• 8-bit timer/counter register (TMR0)

4.1.1

8-BIT TIMER MODE

• 8-bit prescaler (shared with Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow

When used as a timer, the Timer0 module will

increment every instruction cycle (without prescaler).

Timer mode is selected by clearing the T0CS bit of the

OPTION register to ‘0’.

Figure 4-1 is a block diagram of the Timer0 module.

When TMR0 is written, the increment is inhibited for

two instruction cycles immediately following the write.

Note:

The value written to the TMR0 register can

be adjusted, in order to account for the two

instruction cycle delay when TMR0 is

written.

4.1.2

8-BIT COUNTER MODE

When used as a counter, the Timer0 module will

increment on every rising or falling edge of the T0CKI

pin. The incrementing edge is determined by the T0SE

bit of the OPTION register. Counter mode is selected by

setting the T0CS bit of the OPTION register to ‘1’.

FIGURE 4-1:

BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

FOSC/4

Data Bus

0

1

8

1

Sync

TMR0

2 TCY

T0CKI

0

1

Set Flag bit T0IF

on Overflow

T0CS

T0SE

8-bit

Prescaler

PSA

8

PSA

WDTE

1

PS<2:0>

WDT

Time-out

0

31 kHz

INTOSC

Watchdog

Timer

PSA

Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.

2: WDTE bit is in the Configuration Word register.

DS41206B-page 27

PIC16F716

When changing the prescaler assignment from the

WDT to the Timer0 module, the following instruction

sequence must be executed (see Example 4-2).

4.1.3

SOFTWARE PROGRAMMABLE

PRESCALER

A single software programmable prescaler is available

for use with either Timer0 or the Watchdog Timer

(WDT), but not both simultaneously. The prescaler

assignment is controlled by the PSA bit of the OPTION

register. To assign the prescaler to Timer0, the PSA bit

must be cleared to a ‘0’.

EXAMPLE 4-2:

CHANGING PRESCALER

(WDT → TIMER0)

CLRWDT

;Clear WDT and

;prescaler

;

BANKSEL OPTION_REG

There are 8 prescaler options for the Timer0 module

ranging from 1:2 to 1:256. The prescale values are

selectable via the PS<2:0> bits of the OPTION register.

In order to have a 1:1 prescaler value for the Timer0

module, the prescaler must be assigned to the WDT

module.

MOVLW

ANDWF

IORLW

MOVWF

b’11110000’ ;Mask TMR0 select and

OPTION_REG,W ;prescaler bits

b’00000011’ ;Set prescale to 1:16

OPTION_REG

;

4.1.4

TIMER0 INTERRUPT

The prescaler is not readable or writable. When

assigned to the Timer0 module, all instructions writing to

the TMR0 register will clear the prescaler.

Timer0 will generate an interrupt when the TMR0

register overflows from FFh to 00h. The T0IF interrupt

flag bit of the INTCON register is set every time the

TMR0 register overflows, regardless of whether or not

the Timer0 interrupt is enabled. The T0IF bit must be

cleared in software. The Timer0 interrupt enable is the

T0IE bit of the INTCON register.

When the prescaler is assigned to WDT, a CLRWDT

instruction will clear the prescaler along with the WDT.

4.1.3.1

Switching Prescaler Between

Timer0 and WDT Modules

Note:

The Timer0 interrupt cannot wake the

processor from Sleep since the timer is

frozen during Sleep.

As a result of having the prescaler assigned to either

Timer0 or the WDT, it is possible to generate an

unintended device Reset when switching prescaler

values. When changing the prescaler assignment from

Timer0 to the WDT module, the instruction sequence

shown in Example 4-1, must be executed.

4.1.5

USING TIMER0 WITH AN

EXTERNAL CLOCK

When Timer0 is in Counter mode, the synchronization

of the T0CKI input and the Timer0 register is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks. Therefore, the

high and low periods of the external clock source must

meet the timing requirements as shown in the

Section 12.0 “Electrical Characteristics”.

EXAMPLE 4-1:

CHANGING PRESCALER

(TIMER0 → WDT)

BANKSEL TMR0

CLRWDT

;

;Clear WDT

;Clear TMR0 and

;prescaler

CLRF

TMR0

BANKSEL OPTION_REG

;

BSF

OPTION_REG,PSA ;Select WDT

CLRWDT

;

MOVLW

ANDWF

IORLW

MOVWF

b’11111000’

OPTION_REG,W

b’00000101’

OPTION_REG

;Mask prescaler

;bits

;Set WDT prescaler

;to 1:32

TABLE 4-1:

SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TMR0

Timer0 Module Register

GIE PEIE

RBPU INTEDG

xxxx xxxx uuuu uuuu

0000 000x 0000 000u

1111 1111 1111 1111

INTCON

OPTION_REG

TRISA

T0IE

T0CS

—

INTE

T0SE

RBIE

PSA

T0IF

PS2

INTF

PS1

RBIF

PS0

—

TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111

Legend:

– = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the Timer0

module.

DS41206B-page 28

PIC16F716

5.1

Timer1 Operation

5.0

TIMER1 MODULE WITH GATE

CONTROL

The Timer1 module is a 16-bit incrementing counter

which is accessed through the TMR1H:TMR1L register

pair. Writes to TMR1H or TMR1L directly update the

counter.

The Timer1 module is a 16-bit timer/counter with the

following features:

• 16-bit timer/counter register pair (TMR1H:TMR1L)

• Programmable internal or external clock source

• 3-bit prescaler

When used with an internal clock source, the module is

a timer. When used with an external clock source, the

module can be used as either a timer or counter.

• Optional LP oscillator

• Synchronous or asynchronous operation

• Interrupt on overflow

5.2

Clock Source Selection

The TMR1CS bit of the T1CON register is used to select

the clock source. When TMR1CS = 0, the clock source

is FOSC/4. When TMR1CS = 1, the clock source is

supplied externally.

• Wake-up on overflow (external clock,

Asynchronous mode only)

• Time base for the Capture/Compare function

• Special Event Trigger (with ECCP)

Figure 5-1 is a block diagram of the Timer1 module.

FIGURE 5-1:

TIMER1 BLOCK DIAGRAM

Set flag bit

TMR1IF on

Overflow

Synchronized

(2)

0

TMR1

clock input

TMR1L

TMR1H

1

TMR1ON

on/off

T1SYNC

T1OSC

RB1/T1OSO/T1CKI

1

(3)

Synchronize

det

Prescaler

1, 2, 4, 8

T1OSCEN

Enable

Oscillator

FOSC/4

Internal

Clock

0

(1)

RB2/T1OSI

2

Sleep input

T1CKPS<1:0>

Note 1: ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI.

2: Timer1 register increments on rising edge.

3: Synchronize does not operate while in Sleep.

5.2.1

INTERNAL CLOCK SOURCE

5.2.2

EXTERNAL CLOCK SOURCE

When the internal clock source is selected, the

TMR1H:TMR1L register pair will increment on multiples

of TCY as determined by the Timer1 prescaler.

When the external clock source is selected, the Timer1

module may work as a timer or a counter.

When counting, Timer1 is incremented on the rising

edge of the external clock input T1CKI. In addition, the

Counter mode clock can be synchronized to the

microcontroller system clock or run asynchronously.

In Counter mode, a falling edge must be registered by

the counter prior to the first incrementing rising edge

after one or more of the following conditions:

• Timer1 is enabled after POR or BOR Reset

• A write to TMR1H or TMR1L

• T1CKI is high when Timer1 is disabled and when

Timer1 is reenabled T1CKI is low. See Figure 5-2.

DS41206B-page 29

PIC16F716

5.5.1

READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

5.3

Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

Reading TMR1H or TMR1L while the timer is running

from an external asynchronous clock will ensure a valid

read (taken care of in hardware). However, the user

should keep in mind that reading the 16-bit timer in two

8-bit values itself poses certain problems, since the

timer may overflow between the reads.

5.4

Timer1 Oscillator

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write contention

may occur by writing to the timer registers, while the

register is incrementing. This may produce an

unpredictable value in the TMR1H:TMR1L register pair.

A low-power 32.768 kHz crystal oscillator is built-in

between pins T1OSI (input) and T1OSO (output). The

oscillator is enabled by setting the T1OSCEN control

bit of the T1CON register. The oscillator will continue to

run during Sleep.

The Timer1 oscillator is shared with the system LP

oscillator. Thus, Timer1 can use this mode only when

the primary system clock is derived from the internal

oscillator or when in LP oscillator mode. The user must

provide a software time delay to ensure proper oscilla-

tor start-up.

5.6

Timer1 Interrupt

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the Timer1 interrupt flag bit of the PIR1 register is

set. To enable the interrupt on rollover, you must set

these bits:

TRISB1 and TRISB2 bits are set when the Timer1

oscillator is enabled. RB1 and RB2 bits read as ‘0’ and

TRISB1 and TRISB2 bits read as ‘1’.

• Timer1 interrupt enable bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

Note:

The oscillator requires a start-up and

stabilization time before use. Thus,

T1OSCEN should be set and a suitable

delay observed prior to enabling Timer1.

The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

Note:

The TMR1H:TMR1L register pair and the

TMR1IF bit should be cleared before

enabling interrupts.

5.5

Timer1 Operation in

Asynchronous Counter Mode

5.7

Timer1 Operation During Sleep

If control bit T1SYNC of the T1CON register is set, the

external clock input is not synchronized. The timer

continues to increment asynchronous to the internal

phase clocks. The timer will continue to run during

Sleep and can generate an interrupt on overflow,

which will wake-up the processor. However, special

precautions in software are needed to read/write the

timer (see Section 5.5.1 “Reading and Writing

Timer1 in Asynchronous Counter Mode”).

Timer1 can only operate during Sleep when setup in

Asynchronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the

counter. To set up the timer to wake the device:

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set

Note 1: When switching from synchronous to

asynchronous operation, it is possible to

skip an increment. When switching from

asynchronous to synchronous operation,

it is possible to produce an additional

increment.

The device will wake-up on an overflow and execute

the next instruction. If the GIE bit of the INTCON

register is set, the device will call the Interrupt Service

Routine (0004h).

2: In Asynchronous Counter mode, Timer1

can not be used as a time base for the

Capture or Compare modes of the ECCP

module.

DS41206B-page 30

PIC16F716

5.8

ECCP Capture/Compare Time

Base

5.9

ECCP Special Event Trigger

If a ECCP is configured to trigger a special event, the

trigger will clear the TMR1H:TMR1L register pair. This

special event does not cause a Timer1 interrupt. The

ECCP module may still be configured to generate a

ECCP interrupt.

The ECCP module uses the TMR1H:TMR1L register

pair as the time base when operating in Capture or

Compare mode.

In Capture mode, the value in the TMR1H:TMR1L

register pair is copied into the CCPR1H:CCPR1L

register pair on a configured event.

In this mode of operation, the CCPR1H:CCPR1L regis-

ter pair effectively becomes the period register for

Timer1.

In Compare mode, an event is triggered when the value

CCPR1H:CCPR1L register pair matches the value in

the TMR1H:TMR1L register pair. This event can be a

Special Event Trigger.

Timer1 should be synchronized to the FOSC to utilize

the Special Event Trigger. Asynchronous operation of

Timer1 can cause a Special Event Trigger to be

missed.

For more information, see Section 8.0 “Enhanced

Capture/Compare/PWM Module”.

In the event that a write to TMR1H or TMR1L coincides

with a Special Event Trigger from the ECCP, the write

will take precedence.

For more information, see Section 8.0 “Enhanced

Capture/Compare/PWM Module”.

FIGURE 5-2:

TIMER1 INCREMENTING EDGE

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of

the clock.

DS41206B-page 31

PIC16F716

5.10 Timer1 Control Register

The Timer1 Control register (T1CON), shown in

Register 5-1, is used to control Timer1 and select the

various features of the Timer1 module.

REGISTER 5-1:

T1CON: TIMER 1 CONTROL REGISTER

U-0

—

U-0

—

R/W-0

T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC

TMR1CS

TMR1ON

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11= 1:8 Prescale Value

10= 1:4 Prescale Value

01= 1:2 Prescale Value

00= 1:1 Prescale Value

bit 3

bit 2

T1OSCEN: Timer1 Oscillator Enable Control bit

1= Timer1 oscillator is enabled

0= Timer1 oscillator is disabled

T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1:

1= Do not synchronize external clock input

0= Synchronize external clock input

TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock

bit 1

bit 0

TMR1CS: Timer1 Clock Source Select bit

1= External clock from T1CKI pin (on the rising edge)

0= Internal clock (FOSC/4)

TMR1ON: Timer1 On bit

1= Enables Timer1

0= Stops Timer1

DS41206B-page 32

PIC16F716

TABLE 5-1:

SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Value on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

POR, BOR

Resets

INTCON

PIE1

GIE

—

PEIE

ADIE

ADIF

T0IE

—

INTE

—

RBIE

—

T0IF

INTF

RBIF

0000 000x

-0-- -000

xxxx xxxx

0000 000x

-0-- -000

uuuu uuuu

CCP1IE

CCP1IF

TMR2IE

TMR2IF

TMR1IE

TMR1IF

PIR1

—

TMR1H

TMR1L

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

—

T1CON

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR1CS

TMR1ON

--00 0000

--uu uuuu

Legend:

x= unknown, u= unchanged, –= unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

DS41206B-page 33

PIC16F716

NOTES:

DS41206B-page 34

PIC16F716

The TMR2 and PR2 registers are both fully readable

and writable. On any Reset, the TMR2 register is set to

00h and the PR2 register is set to FFh.

6.0

TIMER2 MODULE

The Timer2 module is an 8-bit timer with the following

features:

Timer2 is turned on by setting the TMR2ON bit in the

T2CON register to a ‘1’. Timer2 is turned off by clearing

the TMR2ON bit to a ‘0’.

• 8-bit timer register (TMR2)

• 8-bit period register (PR2)

• Interrupt on TMR2 match with PR2

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

The Timer2 prescaler is controlled by the T2CKPS bits

in the T2CON register. The Timer2 postscaler is

controlled by the TOUTPS bits in the T2CON register.

The prescaler and postscaler counters are cleared

when:

See Figure 6-1 for a block diagram of Timer2.

• A write to TMR2 occurs.

• A write to T2CON occurs.

6.1

Timer2 Operation

The clock input to the Timer2 module is the system

instruction clock (FOSC/4). The clock is fed into the

Timer2 prescaler, which has prescale options of 1:1,

1:4 or 1:16. The output of the prescaler is then used to

increment the TMR2 register.

• Any device Reset occurs (Power-on Reset, MCLR

Reset, Watchdog Timer Reset, or Brown-out

Reset).

Note:

TMR2 is not cleared when T2CON is

written.

The values of TMR2 and PR2 are constantly compared

to determine when they match. TMR2 will increment

from 00h until it matches the value in PR2. When a

match occurs, two things happen:

• TMR2 is reset to 00h on the next increment cycle

• The Timer2 postscaler is incremented

The match output of the Timer2/PR2 comparator is

then fed into the Timer2 postscaler. The postscaler has

postscale options of 1:1 to 1:16 inclusive. The output of

the Timer2 postscaler is used to set the TMR2IF

interrupt flag bit in the PIR2 register.

FIGURE 6-1:

TIMER2 BLOCK DIAGRAM

Sets Flag

bit TMR2IF

TMR2

Output

Prescaler

Reset

EQ

TMR2

FOSC/4

1:1, 1:4, 1:16

Postscaler

1:1 to 1:16

2

Comparator

PR2

T2CKPS<1:0>

4

TOUTPS<3:0>

DS41206B-page 35

PIC16F716

REGISTER 6-1:

T2CON: TIMER 2 CONTROL REGISTER

U-0

—

R/W-0

TOUTPS3

TOUTPS2

TOUTPS1

TOUTPS0

TMR2ON

T2CKPS1

T2CKPS0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

Unimplemented: Read as ‘0’

bit 6-3

TOUTPS<3:0>: Timer2 Output Postscaler Select bits

0000= 1:1 Postscaler

0001= 1:2 Postscaler

0010= 1:3 Postscaler

0011= 1:4 Postscaler

0100= 1:5 Postscaler

0101= 1:6 Postscaler

0110= 1:7 Postscaler

0111= 1:8 Postscaler

1000= 1:9 Postscaler

1001= 1:10 Postscaler

1010= 1:11 Postscaler

1011= 1:12 Postscaler

1100= 1:13 Postscaler

1101= 1:14 Postscaler

1110= 1:15 Postscaler

1111= 1:16 Postscaler

bit 2

TMR2ON: Timer2 On bit

1= Timer2 is on

0= Timer2 is off

bit 1-0

T2CKPS<1:0>: Timer2 Clock Prescale Select bits

00= Prescaler is 1

01= Prescaler is 4

1x= Prescaler is 16

TABLE 6-1:

SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

—

PEIE

ADIE

ADIF

T0IE

—

INTE

—

RBIE

—

T0IF

INTF

RBIF

0000 000x

-0-- -000

1111 1111

0000 0000

-000 0000

0000 000x

-0-- -000

1111 1111

0000 0000

-000 0000

CCP1IE

CCP1IF

TMR2IE

TMR2IF

TMR1IE

TMR1IF

PIR1

—

PR2

Timer2 Module Period Register

Holding Register for the 8-bit TMR2 Register

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0

TMR2

T2CON

Legend:

—

TMR2ON

T2CKPS1

T2CKPS0

x= unknown, u= unchanged, -= unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.

DS41206B-page 36

PIC16F716

The ADC voltage reference is software selectable to

either VDD or a voltage applied to the external reference

pins.

7.0

ANALOG-TO-DIGITAL

CONVERTER (ADC) MODULE

The Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 8-bit binary

representation of that signal. This device uses analog

inputs, which are multiplexed into a single sample and

hold circuit. The output of the sample and hold is

connected to the input of the converter. The converter

The ADC can generate an interrupt upon completion of

a conversion. This interrupt can be used to wake-up the

device from Sleep.

Figure 7-1 shows the block diagram of the ADC.

generates

a 8-bit binary result via successive

approximation and stores the conversion result into the

ADC result register (ADRES).

FIGURE 7-1:

ADC BLOCK DIAGRAM

VDD

PFCG<2:0>

(ADCON1 register)

VREF

000

001

010

011

RA0/AN0

RA1/AN1

ADC

RA2/AN2

8

GO/DONE

RA3/VREF/AN3

CHS

ADRES

ADON

VSS

DS41206B-page 37

PIC16F716

7.1.3

ADC VOLTAGE REFERENCE

7.1

ADC Configuration

The PCFG bits of the ADCON0 register provide

independent control of the positive voltage reference.

The positive voltage reference can be either VDD or an

external voltage source.

When configuring and using the ADC the following

functions must be considered:

• Port configuration

• Channel selection

7.1.4

CONVERSION CLOCK

• ADC voltage reference selection

• ADC conversion clock source

• Interrupt control

The source of the conversion clock is software select-

able via the ADCS bits of the ADCON0 register. There

are four possible clock options:

7.1.1

PORT CONFIGURATION

• FOSC/2

The ADC can be used to convert both analog and digital

signals. When converting analog signals, the I/O pin

should be configured for analog by setting the associated

TRIS and ADCON1 bits. See the corresponding Port

section for more information.

• FOSC/8

• FOSC/32

• FRC (dedicated internal oscillator)

The time to complete one bit conversion is defined as

TAD. One full 8-bit conversion requires 9.5 TAD periods.

Note:

Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

For correct conversion, the appropriate TAD specification

must be met. See A/D conversion requirements in

Section 12.0 “Electrical Characteristics” for more

information. Table 7-1 gives examples of appropriate

ADC clock selections.

7.1.2

CHANNEL SELECTION

The CHS bits of the ADCON0 register determine which

channel is connected to the sample and hold circuit.

Note:

Unless using the FRC, any changes in the

system clock frequency will change the

ADC clock frequency, which may

adversely affect the ADC result.

When changing channels, a delay is required before

starting the next conversion. Refer to Section 7.2

“ADC Operation” for more information.

TABLE 7-1:

TAD vs. DEVICE OPERATING FREQUENCIES

Device Frequency

AD Clock Source (TAD)

Operation

2 TOSC

8 TOSC

32 TOSC

RC

ADCS<1:0>

20 MHz

100 ns⁽²⁾

400 ns⁽²⁾

1.6 μs

5 MHz

400 ns⁽²⁾

1.25 MHz

1.6 μs

6.4 μs

25.6 μs⁽³⁾

2-6 μs^{(1), (4)}

333.33 kHz

6 μs

24 μs⁽³⁾

96 μs⁽³⁾

2-6 μs⁽¹⁾

00

01

10

11

1.6 μs

6.4 μs

2-6 μs^{(1), (4)}

Legend: Shaded cells are outside of recommended range.

Note 1: The RC source has a typical TAD time of 4 μs.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for

Sleep operation only.

DS41206B-page 38

PIC16F716

7.1.5

INTERRUPTS

The ADC module allows for the ability to generate an

interrupt upon completion of an Analog-to-Digital

conversion. The ADC interrupt flag is the ADIF bit in the

PIR1 register. The ADC interrupt enable is the ADIE bit

in the PIE1 register. The ADIF bit must be cleared in

software.

Note:

The ADIF bit is set at the completion of

every conversion, regardless of whether

or not the ADC interrupt is enabled.

This interrupt can be generated while the device is

operating or while in Sleep. If the device is in Sleep, the

interrupt will wake-up the device. Upon waking from

Sleep, the next instruction following the SLEEP

instruction is always executed. If the user is attempting

to wake-up from Sleep and resume in-line code

execution, the global interrupt must be disabled. If the

global interrupt is enabled, execution will switch to the

Interrupt Service Routine.

Please see Section 7.1.5 “Interrupts” for more

information.

DS41206B-page 39

PIC16F716

7.2.5

SPECIAL EVENT TRIGGER

7.2

ADC Operation

The ECCP Special Event Trigger allows periodic ADC

measurements without software intervention. When

this trigger occurs, the GO/DONE bit is set by hardware

and the Timer1 counter resets to zero.

7.2.1

STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a ‘1’. Setting the GO/

DONE bit of the ADCON0 register to a ‘1’ will start the

Analog-to-Digital conversion.

Using the Special Event Trigger does not assure proper

ADC timing. It is the user’s responsibility to ensure that

the ADC timing requirements are met.

Note:

The GO/DONE bit should not be set in the

same instruction that turns on the ADC.

Refer to Section 7.2.6 “A/D Conversion

Procedure”.

See Section 8.0 “Enhanced Capture/Compare/

PWM Module” for more information.

7.2.6

A/D CONVERSION PROCEDURE

7.2.2

COMPLETION OF A CONVERSION

This is an example procedure for using the ADC to

perform an Analog-to-Digital conversion:

When the conversion is complete, the ADC module will:

• Clear the GO/DONE bit

• Set the ADIF flag bit

1. Configure Port:

• Disable pin output driver (See TRIS register)

• Configure pin as analog

• Update the ADRES register with new conversion

result

2. Configure the ADC module:

• Select ADC conversion clock

• Configure voltage reference

• Select ADC input channel

• Select result format

7.2.3

TERMINATING A CONVERSION

If a conversion must be terminated before completion,

the GO/DONE bit can be cleared in software. The

ADRES register will not be updated with the partially

complete Analog-to-Digital conversion sample.

Instead, the ADRES register will retain the value of the

previous conversion. Additionally, a 2 TAD delay is

required before another acquisition can be initiated.

Following this delay, an input acquisition is automati-

cally started on the selected channel.

• Turn on ADC module

3. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

• Enable ADC interrupt

• Enable peripheral interrupt

• Enable global interrupt⁽¹⁾

4. Wait the required acquisition time⁽²⁾

Note:

A device Reset forces all registers to their

Reset state. Thus, the ADC module is

turned off and any pending conversion is

terminated.

.

5. Start conversion by setting the GO/DONE bit.

6. Wait for ADC conversion to complete by one of

the following:

7.2.4

ADC OPERATION DURING SLEEP

• Polling the GO/DONE bit

• Waiting for the ADC interrupt (interrupts

enabled)

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the FRC

option. When the FRC clock source is selected, the

ADC waits one additional instruction before starting the

conversion. This allows the SLEEP instruction to be

executed, which can reduce system noise during the

conversion. If the ADC interrupt is enabled, the device

will wake-up from Sleep when the conversion

completes. If the ADC interrupt is disabled, the ADC

module is turned off after the conversion completes,

although the ADON bit remains set.

7. Read ADC Result

8. Clear the ADC interrupt flag (required if interrupt

is enabled).

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep

and resume in-line code execution.

2: See Section 7.3 “A/D Acquisition

Requirements”.

When the ADC clock source is something other than

FRC, a SLEEP instruction causes the present conver-

sion to be aborted and the ADC module is turned off,

although the ADON bit remains set.

DS41206B-page 40

PIC16F716

7.2.7

ADC REGISTER DEFINITIONS

The following registers are used to control the

operation of the ADC.

REGISTER 7-1:

ADCON0: A/D CONTROL REGISTER 0

R/W-0

CHS2

R/W-0

CHS1

R/W-0

CHS0

R/W-0

U-0

—

R/W-0

ADON

ADCS1

bit 7

ADCS0

GO/DONE

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-3

ADCS<1:0>: A/D Conversion Clock Select bits

00= FOSC/2

01= FOSC/8

10= FOSC/32

11= FRC (Clock derived from the internal ADC RC oscillator)

CHS<2:0>: Analog Channel Select bits

000= AN0

001= AN1

010= AN2

011= AN3

100= Reserved, do not use

101= Reserved, do not use

110= Reserved, do not use

111= Reserved, do not use

bit 2

GO/DONE: A/D Conversion Status bit

1= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0= A/D conversion completed/not in progress

bit 1

bit 0

Unimplemented: Read as ‘0’

ADON: ADC Enable bit

1= ADC is enabled

0= ADC is disabled and consumes no operating current

DS41206B-page 41

PIC16F716

REGISTER 7-2:

ADCON1: A/D CONTROL REGISTER 1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

PCFG2

PCFG1

PCFG0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

PCFG<2:0>: A/D Port Configuration Control bits.

The following table illustrates the effects of the various configurations:

AN3/

RA3

AN2/

RA2

AN2/

RA1

AN0/

RA0

PCFG<2:0>

0x0

VREF

A

VREF

A

D

A

D

A

D

VDD

RA3

VDD

RA3

VDD

0x1

100

101

VREF

D

11x

Legend:

A = Analog input, D = Digital I/O

DS41206B-page 42

PIC16F716

an A/D acquisition must be done before the conversion

can be started. To calculate the minimum acquisition

time, Equation 7-1 may be used. This equation

assumes that 1/2 LSb error is used. The 1/2 LSb error is

the maximum error allowed for the ADC to meet its

specified resolution.

7.3

A/D Acquisition Requirements

For the ADC to meet its specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The Analog

Input model is shown in Figure 7-2. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge the

capacitor CHOLD. The sampling switch (RSS) impedance

varies over the device voltage (VDD), see Figure 7-2.

The maximum recommended impedance for analog

sources is 10 kΩ. As the source impedance is

decreased, the acquisition time may be decreased.

After the analog input channel is selected (or changed),

EQUATION 7-1:

ACQUISITION TIME EXAMPLE

Temperature = 50°C and external impedance of 10kΩ 5.0V VDD

Assumptions:

TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

= TAMP + TC + TCOFF

= 2μs + TC + [(Temperature - 25°C)(0.05μs/°C)]

The value for TC can be approximated with the following equations:

1

2047

⎛

⎞

;[1] VCHOLD charged to within 1/2 lsb

V^APPLIED1 – ----------- = VCHOLD

⎝

⎠

–TC

---------

⎛

⎞

V^APPLIED1 – e ^RC= V^CHOLD

;[2] VCHOLD charge response to VAPPLIED

⎜

⎝

⎟

⎠

–Tc

--------

⎛

⎞

1

2047

VAPPLIED 1 – e^RC= V^APPLIED1 – -----------

⎛

⎞

⎠

;combining [1] and [2]

⎜

⎝

⎟

⎠

⎝

Solving for TC:

TC = –CHOLD(RIC + RSS + RS) ln(1/2047)

= –10pF(1kΩ + 7kΩ + 10kΩ) ln(0.0004885)

= 1.37μs

Therefore:

TACQ = 2μS + 1.37μS + [(50°C- 25°C)(0.05μS/°C)]

= 4.67μS

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin

leakage specification.

DS41206B-page 43

PIC16F716

FIGURE 7-2:

ANALOG INPUT MODEL

VDD

VT = 0.6V

Sampling

Switch

ANx

SS

RIC ≤ 1k

Rss

Rs

(1)

ILEAKAGE

CPIN

5 pF

VA

CHOLD = 10 pF

VSS

VT = 0.6V

6V

5V

RSS

VDD 4V

3V

Legend: CPIN

= Input Capacitance

= Threshold Voltage

VT

2V

I LEAKAGE = Leakage current at the pin due to

various junctions

RIC

SS

CHOLD

= Interconnect Resistance

= Sampling Switch

= Sample/Hold Capacitance

5 6 7 8 9 1011

Sampling Switch

(kΩ)

Note 1: See Section 12.0 “Electrical Characteristics”.

FIGURE 7-3:

ADC TRANSFER FUNCTION

Full-Scale Range

FFh

FEh

FDh

FCh

FBh

1 LSB ideal

Full-Scale

Transition

04h

03h

02h

01h

00h

Analog Input Voltage

1 LSB ideal

Zero-Scale

Transition

VDD/VREF+

VSS

DS41206B-page 44

PIC16F716

TABLE 7-2:

SUMMARY OF ASSOCIATED ADC REGISTERS

Value on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

POR, BOR

Resets

ADCON0

ADCON1

0000 0000

ADCS1

—

ADCS0

—

CHS2

—

CHS1

—

CHS0

—

GO/DONE

PCFG2

—

ADON

PCFG1

PCFG0

---- -000

xxxx xxxx

0000 000x

-0-- -000

--xx xxxx

--11 1111

---- -000

uuuu uuuu

0000 000x

-0-- -000

--uu uuuu

--11 1111

ADRES

INTCON

PIE1

A/D Result Register

GIE

—

PEIE

ADIE

ADIF

—

T0IE

—

INTE

—

RBIE

—

T0IF

CCP1IE

CCP1IF

RA2

INTF

TMR2IE

TMR2IF

RA1

RBIF

TMR1IE

TMR1IF

RA0

PIR1

—

PORTA

TRISA

Legend:

—

RA4

TRISA4

RA3

TRISA3

—

TRISA2

TRISA1

TRISA0

x= unknown, u= unchanged, —= unimplemented read as ‘0’. Shaded cells are not used for ADC module.

DS41206B-page 45

PIC16F716

NOTES:

DS41206B-page 46

PIC16F716

8.0

ENHANCED CAPTURE/

COMPARE/PWM MODULE

Note:

CCPR1 and CCP1 throughout this

document refer to CCPR1 or CCPR2 and

CCP1 or CCP2, respectively.

The Enhanced Capture/Compare/PWM module is a

peripheral which allows the user to time and control

different events. In Capture mode, the peripheral

allows the timing of the duration of an event. The

Compare mode allows the user to trigger an external

event when a predetermined amount of time has

expired. The PWM mode can generate a Pulse-Width

Modulated signal of varying frequency and duty cycle.

TABLE 8-1:

ECCP MODE – TIMER

RESOURCES REQUIRED

ECCP Mode

Capture

Timer Resource

Timer1

Timer2

Compare

PWM

Table 8-1 shows the timer resources required by the

ECCP module.

REGISTER 8-1:

CCP1CON: ENHANCED CCP1 CONTROL REGISTER

R/W-0

P1M1

R/W-0

P1M0

R/W-0

DC1B0

R/W-0

CCP1M1

R/W-0

DC1B1

CCP1M3

CCP1M2

CCP1M0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

P1M<1:0>: PWM Output Configuration bits

If CCP1M<3:2> = 00, 01, 10:

xx= P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins

If CCP1M<3:2> = 11:

00= Single output; P1A modulated; P1B, P1C, P1D assigned as port pins

01= Full-Bridge output forward; P1D modulated; P1A active; P1B, P1C inactive

10= Half-Bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins

11= Full-Bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive

bit 5-4

DC1B<1:0>: PWM Duty Cycle Least Significant bits

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.

bit 3-0

CCP1M<3:0>: ECCP Mode Select bits

0000= Capture/Compare/PWM off (resets ECCP module)

0001= Unused (reserved)

0010= Compare mode, toggle output on match (CCP1IF bit is set)

0011= Unused (reserved)

0100= Capture mode, every falling edge

0101= Capture mode, every rising edge

0110= Capture mode, every 4th rising edge

0111= Capture mode, every 16th rising edge

1000= Compare mode, set output on match (CCP1IF bit is set)

1001= Compare mode, clear output on match (CCP1IF bit is set)

1010= Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is

unaffected)

1011= Compare mode, Special Event Trigger (CCP1IF bit is set; CCP1 resets TMR1 or TMR2)

1100= PWM mode; P1A, P1C active-high; P1B, P1D active-high

1101= PWM mode; P1A, P1C active-high; P1B, P1D active-low

1110= PWM mode; P1A, P1C active-low; P1B, P1D active-high

1111= PWM mode; P1A, P1C active-low; P1B, P1D active-low

DS41206B-page 47

PIC16F716

8.1.2

TIMER1 MODE SELECTION

8.1

Capture Mode

Timer1 must be running in Timer mode or Synchronized

Counter mode for the CCP module to use the capture

feature. In Asynchronous Counter mode, the capture

operation may not work.

In Capture mode, CCPR1H:CCPR1L captures the

16-bit value of the TMR1 register when an event occurs

on pin CCP1. An event is defined as one of the

following and is configured by the CCP1M<3:0> bits of

the CCP1CON register:

8.1.3

SOFTWARE INTERRUPT

• Every falling edge

• Every rising edge

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCP1IE interrupt enable bit of the PIE1 register clear to

avoid false interrupts. Additionally, the user should

clear the CCP1IF interrupt flag bit of the PIR1 register

following any change in operating mode.

• Every 4th rising edge

• Every 16th rising edge

When a capture is made, the Interrupt Request Flag bit

CCP1IF of the PIR1 register is set. The interrupt flag

must be cleared in software. If another capture occurs

before the value in the CCPR1H, CCPR1L register pair

is read, the old captured value is overwritten by the new

captured value (see Figure 8-1).

8.1.4

CCP PRESCALER

There are four prescaler settings specified by the

CCP1M<3:0> bits of the CCP1CON register.

Whenever the CCP module is turned off, or the CCP

module is not in Capture mode, the prescaler counter

is cleared. Any Reset will clear the prescaler counter.

8.1.1

CCP1 PIN CONFIGURATION

In Capture mode, the CCP1 pin should be configured

as an input by setting the associated TRIS control bit.

Switching from one capture prescaler to another does not

clear the prescaler and may generate a false interrupt. To

avoid this unexpected operation, turn the module off by

clearing the CCP1CON register before changing the

prescaler (see Example 8-1).

Note:

If the CCP1 pin is configured as an output,

a write to the port can cause a capture

condition.

FIGURE 8-1:

CAPTURE MODE

OPERATION BLOCK

DIAGRAM

EXAMPLE 8-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

BANKSELCCP1CON

;Set Bank bits to point

;to CCP1CON

;Turn CCP module off

Set Flag bit CCP1IF

(PIR1 register)

Prescaler

÷ 1, 4, 16

CLRF

CCP1CON

MOVLW

NEW_CAPT_PS;Load the W reg with

; the new prescaler

CCP1

CCPR1H

CCPR1L

; move value and CCP ON

Capture

Enable

MOVWF

CCP1CON

;Load CCP1CON with this

; value

and

Edge Detect

TMR1H

TMR1L

CCP1CON<3:0>

System Clock (FOSC)

DS41206B-page 48

PIC16F716

TABLE 8-2:

REGISTERS ASSOCIATED WITH CAPTURE

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

CCPR1L

CCPR1H

CCP1CON

INTCON

PIE1

Capture/Compare/PWM Register 1 (LSB)

Capture/Compare/PWM Register 1 (MSB)

xxxx xxxx

0000 0000

0000 000x

-0-- -000

1111 1111

xxxx xxxx

0000 0000

1111 1111

xxxx xxxx

0000 0000

0000 000x

-0-- -000

1111 1111

xxxx xxxx

0000 0000

1111 1111

P1M1

GIE

—

P1M0

PEIE

ADIE

ADIF

DC1B1

T0IE

—

DC1B0

INTE

—

CCP1M3

RBIE

—

CCP1M2

T0IF

CCP1M1

INTF

CCP1M0

RBIF

CCP1IE

CCP1IF

TMR2IE

TMR2IF

TMR1IE

TMR1IF

PIR1

—

PR2

Timer2 Period Register

TMR1L

TMR1H

TMR2

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

Timer2 module’s register

TRISB

TRISB7

TRISB6

TRISB5

TRISB4

TRISB3

TRISB2

TRISB1

TRISB0

Legend: – = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the Capture.

DS41206B-page 49

PIC16F716

8.2.2

TIMER1 MODE SELECTION

8.2

Compare Mode

In Compare mode, Timer1 must be running in either

Timer mode or Synchronized Counter mode. The

compare operation may not work in Asynchronous

Counter mode.

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the CCP1 module may:

• Toggle the CCP1 output.

• Set the CCP1 output.

8.2.3

SOFTWARE INTERRUPT MODE

• Clear the CCP1 output.

When Generate Software Interrupt mode is chosen

(CCP1M<3:0> = 1010), the CCP1 module does not

assert control of the CCP1 pin (see the CCP1CON

register).

• Generate a Special Event Trigger.

• Generate a Software Interrupt.

The action on the pin is based on the value of the

CCP1M<3:0> control bits of the CCP1CON register.

8.2.4

SPECIAL EVENT TRIGGER

All Compare modes can generate an interrupt.

When Special Event Trigger mode is chosen

(CCP1M<3:0> = 1011), the CCP1 module does the

following:

FIGURE 8-2:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

• Resets Timer1

• Starts an ADC conversion if ADC is enabled

CCP1CON<3:0>

Mode Select

The CCP1 module does not assert control of the CCP1

pin in this mode (see the CCP1CON register).

Set CCP1IF Interrupt Flag

The Special Event Trigger output of the CCP occurs

immediately upon a match between the TMR1H,

TMR1L register pair and the CCPR1H, CCPR1L

register pair. The TMR1H, TMR1L register pair is not

reset until the next rising edge of the Timer1 clock. This

allows the CCPR1H, CCPR1L register pair to

effectively provide a 16-bit programmable period

register for Timer1.

(PIR1)

4

CCP1

CCPR1H CCPR1L

Comparator

Q

S

R

Output

Logic

Match

TMR1H TMR1L

TRIS

Output Enable

Special Event Trigger

Note 1: The Special Event Trigger from the CCP

module does not set interrupt flag bit

TMRxIF of the PIR1 register.

Special Event Trigger will:

•

Clear TMR1H and TMR1L registers.

NOT set interrupt flag bit TMR1IF of the PIR1 register.

Set the GO/DONE bit to start the ADC conversion.

2: Removing the match condition by

changing the contents of the CCPR1H

and CCPR1L register pair, between the

clock edge that generates the Special

Event Trigger and the clock edge that

generates the Timer1 Reset, will preclude

the Reset from occurring.

8.2.1

CCP1 PIN CONFIGURATION

The user must configure the CCP1 pin as an output by

clearing the associated TRIS bit.

Note:

Clearing the CCP1CON register will force

the CCP1 compare output latch to the

default low level. This is not the PORT I/O

data latch.

DS41206B-page 50

PIC16F716

TABLE 8-3:

REGISTERS ASSOCIATED WITH COMPARE

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

CCPR1L

CCPR1H

CCP1CON

INTCON

PIE1

Capture/Compare/PWM Register 1 (LSB)

Capture/Compare/PWM Register 1 (MSB)

xxxx xxxx

0000 0000

0000 000x

-0-- -000

1111 1111

xxxx xxxx

0000 0000

1111 1111

xxxx xxxx

0000 0000

0000 000x

-0-- -000

1111 1111

xxxx xxxx

0000 0000

1111 1111

P1M1

GIE

—

P1M0

PEIE

ADIE

ADIF

DC1B1

T0IE

—

DC1B0

INTE

—

CCP1M3

RBIE

—

CCP1M2

T0IF

CCP1M1

INTF

CCP1M0

RBIF

CCP1IE

CCP1IF

TMR2IE

TMR2IF

TMR1IE

TMR1IF

PIR1

—

PR2

Timer2 Period Register

TMR1L

TMR1H

TMR2

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

Timer2 module’s register

TRISB

TRISB7

TRISB6

TRISB5

TRISB4

TRISB3

TRISB2

TRISB1

TRISB0

Legend: – = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the Compare.

DS41206B-page 51

PIC16F716

The PWM output (Figure 8-4) has a time base

(period) and a time that the output stays high (duty

cycle).

8.3

PWM Mode

The PWM mode generates a Pulse-Width Modulated

signal on the CCP1 pin. The duty cycle, period and

resolution are determined by the following registers:

FIGURE 8-4:

CCP PWM OUTPUT

• PR2

Period

• T2CON

• CCPR1L

• CCP1CON

Pulse Width

TMR2 = PR2

TMR2 = CCPR1L:CCP1CON<5:4>

In Pulse-Width Modulation (PWM) mode, the CCP

module produces up to a 10-bit resolution PWM output

on the CCP1 pin. Since the CCP1 pin is multiplexed

with the PORT data latch, the TRIS for that pin must be

cleared to enable the CCP1 pin output driver.

TMR2 = 0

Note:

Clearing the CCP1CON register will

relinquish CCP1 control of the CCP1 pin.

Figure 8-3 shows a simplified block diagram of PWM

operation.

Figure 8-4 shows a typical waveform of the PWM

signal.

For a step-by-step procedure on how to set up the CCP

module for PWM operation, see Section 8.3.7 “Setup

for PWM Operation”.

FIGURE 8-3:

SIMPLIFIED PWM BLOCK

DIAGRAM

CCP1CON<5:4>

Duty Cycle Registers

CCPR1L

CCPR1H⁽²⁾(Slave)

Comparator

CCP1

R

S

Q

(1)

TMR2

TRIS

Comparator

PR2

Clear Timer2,

toggle CCP1 pin and

latch duty cycle

Note 1: The 8-bit timer TMR2 register is concatenated

with the 2-bit internal system clock (FOSC), or

2 bits of the prescaler, to create the 10-bit time

base.

2: In PWM mode, CCPR1H is a read-only register.

DS41206B-page 52

PIC16F716

8.3.1

PWM PERIOD

8.3.2

PWM DUTY CYCLE

The PWM period is specified by the PR2 register of

Timer2. The PWM period can be calculated using the

formula of Equation 8-1.

The PWM duty cycle is specified by writing a 10-bit

value to multiple registers: CCPR1L register and

DC1B<1:0> bits of the CCP1CON register. The

CCPR1L contains the eight MSbs and the DC1B<1:0>

bits of the CCP1CON register contain the two LSbs.

CCPR1L and DC1B<1:0> bits of the CCP1CON

register can be written to at any time. The duty cycle

value is not latched into CCPR1H until after the period

completes (i.e., a match between PR2 and TMR2

registers occurs). While using the PWM, the CCPR1H

register is read-only.

EQUATION 8-1:

PWM PERIOD

PWM Period = [(PR2) + 1] • 4 • TOSC •

(TMR2 Prescale Value)

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

Equation 8-2 is used to calculate the PWM pulse width.

• TMR2 is cleared

Equation 8-3 is used to calculate the PWM duty cycle

ratio.

• The CCP1 pin is set. (Exception: If the PWM duty

cycle = 0%, the pin will not be set.)

• The PWM duty cycle is latched from CCPR1L into

CCPR1H.

EQUATION 8-2:

PULSE WIDTH

Pulse Width = (CCPR1L:CCP1CON<5:4>) •

TOSC • (TMR2 Prescale Value)

Note:

The Timer2 postscaler (see Section 6.0

“Timer2 Module”) is not used in the

determination of the PWM frequency.

EQUATION 8-3:

DUTY CYCLE RATIO

(CCPR1L:CCP1CON<5:4>)

Duty Cycle Ratio = -----------------------------------------------------------------------

4(PR2 + 1)

The CCPR1H register and a 2-bit internal latch are

used to double buffer the PWM duty cycle. This double

buffering is essential for glitchless PWM operation.

The 8-bit timer TMR2 register is concatenated with

either the 2-bit internal system clock (FOSC), or 2 bits of

the prescaler, to create the 10-bit time base. The system

clock is used if the Timer2 prescaler is set to 1:1.

When the 10-bit time base matches the CCPR1H and 2-

bit latch, then the CCP1 pin is cleared (see Figure 8-3).

DS41206B-page 53

PIC16F716

8.3.3

PWM RESOLUTION

EQUATION 8-4:

PWM RESOLUTION

The resolution determines the number of available duty

cycles for a given period. For example, a 10-bit resolution

will result in 1024 discrete duty cycles, whereas an 8-bit

resolution will result in 256 discrete duty cycles.

log[4(PR2 + 1)]

Resolution = ----------------------------------------- bits

log(2)

The maximum PWM resolution is 10 bits when PR2 is

255. The resolution is a function of the PR2 register

value as shown by Equation 8-4.

Note:

If the pulse width value is greater than the

period the assigned PWM pin(s) will

remain unchanged.

TABLE 8-4:

EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

PWM Frequency

1.22 kHz

4.88 kHz

19.53 kHz

78.12 kHz

156.3 kHz

208.3 kHz

Timer Prescale (1, 4, 16)

PR2 Value

16

0xFF

10

4

1

0x3F

8

1

0x1F

7

1

0xFF

10

0xFF

10

0x17

6.6

Maximum Resolution (bits)

TABLE 8-5:

EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

PWM Frequency

1.22 kHz

4.90 kHz

19.61 kHz

76.92 kHz

153.85 kHz 200.0 kHz

Timer Prescale (1, 4, 16)

PR2 Value

16

0x65

8

4

0x65

8

1

0x65

8

1

0x19

6

1

0x0C

5

1

0x09

5

Maximum Resolution (bits)

DS41206B-page 54

PIC16F716

8.3.4

OPERATION IN SLEEP MODE

8.3.7

SETUP FOR PWM OPERATION

In Sleep mode, the TMR2 register will not increment

and the state of the module will not change. If the CCP1

pin is driving a value, it will continue to drive that value.

When the device wakes up, TMR2 will continue from its

previous state.

The following steps should be taken when configuring

the CCP module for PWM operation:

1. Disable the PWM pin (CCP1) output drivers by

setting the associated TRIS bit.

2. Set the PWM period by loading the PR2 register.

3. Configure the CCP module for the PWM mode

by loading the CCP1CON register with the

appropriate values.

8.3.5

CHANGES IN SYSTEM CLOCK

FREQUENCY

The PWM frequency is derived from the system clock

frequency. Any changes in the system clock frequency

will result in changes to the PWM frequency.

4. Set the PWM duty cycle by loading the CCPR1L

register and DC1B bits of the CCP1CON register.

5. Configure and start Timer2:

8.3.6

EFFECTS OF RESET

• Clear the TMR2IF interrupt flag bit of the

PIR1 register.

Any Reset will force all ports to Input mode and the

CCP registers to their Reset states.

• Set the Timer2 prescale value by loading the

T2CKPS bits of the T2CON register.

• Enable Timer2 by setting the TMR2ON bit of

the T2CON register.

6. Enable PWM output after a new PWM cycle has

started:

• Wait until Timer2 overflows (TMR2IF bit of

the PIR1 register is set).

• Enable the CCP1 pin output driver by

clearing the associated TRIS bit.

DS41206B-page 55

PIC16F716

When a shutdown event occurs, two things happen:

8.3.8

ENHANCED PWM AUTO-

SHUTDOWN MODE

The ECCPASE bit is set to ‘1’. The ECCPASE will

remain set until cleared in firmware or an auto-restart

occurs (see Section 8.3.9 “Auto-Restart Mode”).

The PWM mode supports an Auto-Shutdown mode that

will disable the PWM outputs when an external

shutdown event occurs. Auto-Shutdown mode places

the PWM output pins into a predetermined state. This

mode is used to help prevent the PWM from damaging

the application.

The enabled PWM pins are asynchronously placed in

their shutdown states. The PWM output pins are

grouped into pairs [P1A/P1C] and [P1B/P1D]. The state

of each pin pair is determined by the PSSAC and

PSSBD bits of the ECCPAS register. Each pin pair may

be placed into one of three states:

The auto-shutdown sources are selected using the

ECCPASx bits of the ECCPAS register. A shutdown

event may be generated by:

• Drive logic ‘1’

• A logic ‘0’ on the INT pin

• Drive logic ‘0’

• Setting the ECCPASE bit in firmware

• Tri-state (high-impedance)

A shutdown condition is indicated by the ECCPASE

(Auto-Shutdown Event Status) bit of the ECCPAS

register. If the bit is a ‘0’, the PWM pins are operating

normally. If the bit is a ‘1’, the PWM outputs are in the

shutdown state. Refer to Figure 8-5.

FIGURE 8-5:

AUTO-SHUTDOWN BLOCK DIAGRAM

ECCPAS<2:0>

PSSAC<0>

1

P1A_DRV

0

111

110

101

100

011

010

001

000

PSSAC<1>

P1A

TRISx

INT

From Comparator C2

From Comparator C1

PSSBD<0>

1

P1B_DRV

0

PRSEN

PSSBD<1>

R

D

S

P1B

TRISx

From Data Bus

ECCPASE

Q

Write to ECCPASE

PSSAC<0>

P1C_DRV

1

0

PSSAC<1>

P1C

TRISx

PSSBD<0>

P1D_DRV

1

0

PSSBD<1>

TRISx

P1D

DS41206B-page 56

PIC16F716

REGISTER 8-2:

ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN

CONTROL REGISTER

R/W-0

ECCPASE

bit 7

R/W-0

ECCPAS2

U-0

—

R/W-0

ECCPAS0

PSSAC1

PSSAC0

PSSBD1

PSSBD0

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

bit 6

ECCPASE: ECCP Auto-Shutdown Event Status bit

1= A shutdown event has occurred; ECCP outputs are in shutdown state

0= ECCP outputs are operating

ECCPAS2: ECCP Auto-Shutdown bit 2

1= RB0 (INT) pin low level (‘0’) causes shutdown

0= RB0 (INT) pin has no effect on ECCP

bit 5

bit 4

Unimplemented: Read as ‘0’

ECCPAS0: ECCP Auto-Shutdown bit ‘0’

1= RB4 pin low level (‘0’) causes shutdown

0= RB4 pin has no effect on ECCP

bit 3-2

bit 1-0

PSSACn: Pins P1A and P1C Shutdown State Control bits

00= Drive pins P1A and P1C to ‘0’

01= Drive pins P1A and P1C to ‘1’

1x= Pins P1A and P1C tri-state

PSSBDn: Pins P1B and P1D Shutdown State Control bits

00= Drive pins P1B and P1D to ‘0’

01= Drive pins P1B and P1D to ‘1’

1x= Pins P1B and P1D tri-state

Note 1: The auto-shutdown condition is a level-

based signal, not an edge-based signal.

As long as the level is present, the auto-

shutdown will persist.

2: Writing to the ECCPASE bit is disabled

while an auto-shutdown condition

persists.

3: Once the auto-shutdown condition has

been removed and the PWM restarted

(either through firmware or auto-restart),

the PWM signal will always restart at the

beginning of the next PWM period.

DS41206B-page 57

PIC16F716

FIGURE 8-6:

PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0)

Shutdown Event

ECCPASE bit

PWM Activity

PWM Period

ECCPASE

Cleared by

Firmware

Start of

PWM Period

Shutdown

PWM

Resumes

Event Occurs Event Clears

8.3.9

AUTO-RESTART MODE

The Enhanced PWM can be configured to automati-

cally restart the PWM signal once the auto-shutdown

condition has been removed. Auto-restart is enabled by

setting the PRSEN bit in the PWM1CON register.

If auto-restart is enabled, the ECCPASE bit will remain

set as long as the auto-shutdown condition is active.

When the auto-shutdown condition is removed, the

ECCPASE bit will be cleared via hardware and normal

operation will resume.

FIGURE 8-7:

PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1)

Shutdown Event

ECCPASE bit

PWM Activity

PWM Period

Shutdown

Event Occurs Event Clears

Shutdown

PWM

Resumes

Start of

PWM Period

DS41206B-page 58

PIC16F716

8.3.10

PROGRAMMABLE DEAD-BAND

DELAY MODE

FIGURE 8-8:

EXAMPLE OF HALF-

BRIDGE PWM OUTPUT

In Half-Bridge applications where all power switches

are modulated at the PWM frequency, the power

switches normally require more time to turn off than to

turn on. If both the upper and lower power switches are

switched at the same time (one turned on, and the

other turned off), both switches may be on for a short

period of time until one switch completely turns off.

During this brief interval, a very high current (shoot-

through current) will flow through both power switches,

shorting the bridge supply. To avoid this potentially

destructive shoot-through current from flowing during

switching, turning on either of the power switches is

normally delayed to allow the other switch to

completely turn off.

Period

Pulse Width

(2)

P1A

td

P1B

(1)

td = Dead-Band Delay

Note 1: At this time, the TMR2 register is equal to the

PR2 register.

2: Output signals are shown as active-high.

In Half-Bridge mode, a digitally programmable dead-

band delay is available to avoid shoot-through current

from destroying the bridge power switches. The delay

occurs at the signal transition from the non-active state

to the active state. See Figure 8-8 for illustration. The

lower seven bits of the associated PWM1CON register

(Register 8-3) sets the delay period in terms of

microcontroller instruction cycles (TCY or 4 TOSC).

FIGURE 8-9:

EXAMPLE OF HALF-BRIDGE APPLICATIONS

V+

Standard Half-Bridge Circuit (“Push-Pull”)

FET

Driver

+

V

-

P1A

Load

FET

Driver

+

V

-

P1B

V-

DS41206B-page 59

PIC16F716

REGISTER 8-3:

PWM1CON: ENHANCED PWM CONTROL REGISTER

R/W-0

PRSEN

bit 7

R/W-0

PDC6

R/W-0

PDC5

R/W-0

PDC4

R/W-0

PDC3

R/W-0

PDC2

R/W-0

PDC1

R/W-0

PDC0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

PRSEN: PWM Restart Enable bit

1= Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes

away; the PWM restarts automatically

0= Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM

bit 6-0

PDC<6:0>: PWM Delay Count bits

PDCn = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal

should transition active and the actual time it transitions active

TABLE 8-6:

REGISTERS ASSOCIATED WITH PWM

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

CCPR1L

CCPR1H

CCP1CON

ECCPAS

INTCON

PIE1

Capture/Compare/PWM Register 1 (LSB)

Capture/Compare/PWM Register 1 (MSB)

xxxx xxxx

0000 0000

00-0 0000

0000 000x

-0-- -000

-0-- 0000

1111 1111

0000 0000

xxxx xxxx

0000 0000

1111 1111

xxxx xxxx

0000 0000

00-0 0000

0000 000x

-0-- -000

1111 1111

0000 0000

xxxx xxxx

0000 0000

1111 1111

P1M1

P1M0

DC1B1

—

DC1B0

ECCPAS0

INTE

CCP1M3

PSSAC1

RBIE

—

CCP1M2

PSSAC0

T0IF

CCP1M1

PSSBD1

INTF

CCP1M0

PSSBD0

RBIF

ECCPASE ECCPAS2

GIE

—

PEIE

ADIE

ADIF

T0IE

—

CCP1IE

CCP1IF

TMR2IE

TMR2IF

TMR1IE

TMR1IF

PIR1

—

PR2

Timer2 Period Register

PRSEN PDC6

PWM1CON

TMR1L

TMR1H

TMR2

PDC5

PDC4

PDC3

PDC2

PDC1

PDC0

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

Timer2 Module’s Register

TRISB

TRISB7

TRISB6

TRISB5

TRISB4

TRISB3

TRISB2

TRISB1

TRISB0

Legend: – = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the PWM.

DS41206B-page 60

PIC16F716

9.1

Configuration Bits

9.0

SPECIAL FEATURES OF THE

CPU

The Configuration bits can be programmed (read as

‘0’) or left unprogrammed (read as ‘1’) to select various

device configurations. These bits are mapped in

program memory location 2007h.

The PIC16F716 device has a host of features intended

to maximize system reliability, minimize cost through

elimination of external components, provide

power-saving operating modes and offer code

protection. These are:

The user will note that address 2007h is beyond the

user program memory space. In fact, it belongs to the

special configuration memory space (2000h-3FFFh),

which can be accessed only during programming.

• OSC Selection

• Reset

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)

• Sleep

• Code protection

• ID locations

• In-Circuit Serial Programming™ (ICSP™)

The PIC16F716 device has a Watchdog Timer, which

can be shut off only through Configuration bits. It runs

off its own RC oscillator for added reliability. There are

two timers that offer necessary delays on power-up.

One is the Oscillator Start-up Timer (OST), intended to

keep the chip in Reset until the crystal oscillator is

stable. The other is the Power-up Timer (PWRT), which

provides a fixed delay on power-up only and is

designed to keep the part in Reset while the power

supply stabilizes. With these two timers on-chip, most

applications need no external Reset circuitry.

Sleep mode is designed to offer a very low-current

Power-Down mode. The user can wake-up from Sleep

through external Reset, Watchdog Timer Wake-up, or

through an interrupt. Several oscillator options are also

made available to allow the part to fit the application.

The RC oscillator option saves system cost, while the

LP crystal option saves power. A set of Configuration

bits are used to select various options.

DS41206B-page 61

PIC16F716

REGISTER 9-1:

CONFIG: CONFIGURATION WORD REGISTER

CP⁽²⁾

—

bit 15

bit 8

BORV

bit 7

BOREN⁽¹⁾

—

PWRTE

WDTE

FOSC1

FOSC0

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

P = Programmable’

‘0’ = Bit is cleared

U = Unimplemented bit,

read as ‘0’

-n = Value at POR

x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘1’

CP: Code Protection bit⁽²⁾

1= Program memory code protection is disabled

0= Program memory code protection is enabled

bit 12-8

bit 7

Unimplemented: Read as ‘1’

BORV: Brown-out Reset Voltage bit

1= VBOR set to 4.0V

0= VBOR set to 2.5V

bit 6

BOREN: Brown-out Reset Selection bits⁽¹⁾

1= BOR enabled

0= BOR disabled

bit 5-4

bit 3

Unimplemented: Read as ‘1’

PWRTE: Power-up Timer Enable bit⁽¹⁾

1= PWRT disabled

0= PWRT enabled

bit 2

WDTE: Watchdog Timer Enable bit

1= WDT enabled

0= WDT disabled

bit 1-0

FOSC<2:0>: Oscillator Selection bits

11= RC oscillator

10= HS oscillator

01= XT oscillator

00= LP oscillator

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: The entire program memory will be erased when the code protection is turned off.

DS41206B-page 62

PIC16F716

TABLE 9-1:

CERAMIC RESONATORS

Ranges Tested:

9.2

Oscillator Configurations

9.2.1

OSCILLATOR TYPES

Mode

Freq

OSC1 (C1)

OSC2 (C2)

The PIC16F716 can be operated in four different

oscillator modes. The user can program two Configura-

tion bits (FOSC1 and FOSC0) to select one of these

four modes:

XT

455 kHz

2.0 MHz

68-100 pF

15-68 pF

68-100 pF

15-68 pF

HS

4.0 MHz

8.0 MHz

16.0 MHz

10-68 pF

15-68 pF

10-22 pF

10-68 pF

15-68 pF

10-22 pF

• LP – Low-power Crystal

• XT – Crystal/Resonator

Note 1: These values are for design guidance

• HS – High-speed Crystal/Resonator

• RC – Resistor/Capacitor

only. See notes at bottom of page.

TABLE 9-2:

CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

9.2.2

CRYSTAL OSCILLATOR/CERAMIC

RESONATORS

Crystal

Freq

Cap. Range

C1

Cap. Range

C2

In XT, LP or HS modes, a crystal or ceramic resonator

is connected to the OSC1/CLKIN and OSC2/CLKOUT

pins to establish oscillation (Figure 9-1). The

PIC16F716 oscillator design requires the use of a

parallel cut crystal. Use of a series cut crystal may give

Osc Type

LP

32 kHz

200 kHz

1 MHz

15-33 pF

5-10 pF

15-33 pF

5-10 pF

XT

HS

47-68 pF

15-33 pF

47-68 pF

15-33 pF

a

frequency out of the crystal manufacturers

specifications. When in XT, LP or HS modes, the

device can have an external clock source to drive the

OSC1/CLKIN pin (Figure 9-2).

4 MHz

8 MHz

FIGURE 9-1:

CRYSTAL/CERAMIC

RESONATOROPERATION

(HS, XT OR LP

20 MHz

Note 1: These values are for design guidance only.

See notes at bottom of page.

OSC CONFIGURATION)

C1⁽¹⁾

OSC1

Note 1: Higher capacitance increases the stability

of the oscillator, but also increases the

start-up time.

To

internal

logic

XTAL

RF⁽³⁾

2: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

Sleep

PIC16F716

Note 1: See Table 9-1 and Table 9-2 for

OSC2

RS⁽²⁾

C2⁽¹⁾

appropriate

values

of

external

components.

3: RS may be required to avoid overdriving

recommended values of C1 and C2.

2: A series resistor (RS) may be required.

3: RF varies with the crystal chosen.

crystals with low drive level specification.

4: When using an external clock for the

OSC1 input, loading of the OSC2 pin

must be kept to a minimum by leaving the

OSC2 pin unconnected.

FIGURE 9-2:

EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR

LP OSC

CONFIGURATION)

OSC1

Clock from

ext. system

PIC16F716

OSC2

Open

DS41206B-page 63

PIC16F716

A simplified block diagram of the On-chip Reset circuit

is shown in Figure 9-5.

The PIC^®microcontrollers have an MCLR noise filter in

the MCLR Reset path. The filter will detect and ignore

small pulses.

9.2.3

RC OSCILLATOR

For timing insensitive applications, the “RC” device

option offers additional cost savings. The RC oscillator

frequency is a function of the supply voltage, the

resistor (REXT) and capacitor (CEXT) values and the

operating temperature. In addition to this, the oscillator

frequency will vary from unit-to-unit due to normal

process parameter variation. Furthermore, the

difference in lead frame capacitance between package

types will also affect the oscillation frequency,

especially for low CEXT values. The user also needs to

take into account variation due to tolerance of external

R and C components used. Figure 9-3 shows how the

R/C combination is connected to the PIC16F716.

It should be noted that a WDT Reset does not drive the

MCLR pin low.

9.4

Power-On Reset (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected. To take advantage of the POR,

just tie the MCLR pin directly (or through a resistor) to

VDD. This will eliminate external RC components

usually needed to create a Power-on Reset. A

maximum rise time for VDD is specified (parameter

D004). For a slow rise time, see Figure 9-4.

FIGURE 9-3:

RC OSCILLATOR MODE

VDD

When the device starts normal operation (exits the

Reset condition), device operating parameters

(voltage, frequency, temperature,...) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met. Brown-out Reset may be used to

meet the start-up conditions.

REXT

Internal

OSC1

clock

CEXT

VSS

PIC16F716

OSC2/CLKOUT

FOSC/4

Recommended values:

FIGURE 9-4:

EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

3 kΩ ≤ REXT ≤ 100 kΩ (VDD ≥ 3.0V)

10 kΩ ≤ REXT ≤ 100 kΩ (VDD ≥ 3.0V)

CEXT > 20 pF

VDD VDD

R

9.3

Reset

R1

MCLR

The PIC16F716 differentiates between various kinds of

Reset:

PIC16F716

C

• Power-on Reset (POR)

• MCLR Reset during normal operation

• MCLR Reset during Sleep

Note 1: External Power-on Reset circuit is required

only if VDD power-up slope is too slow. The

diode D helps discharge the capacitor quickly

when VDD powers down.

• WDT Reset (during normal operation)

• WDT Wake-up (during Sleep)

• Brown-out Reset (BOR)

2: R < 40 kΩ is recommended to make sure that

voltage drop across R does not violate the

device’s electrical specification.

Some registers are not affected in any Reset condition;

their status is unknown on POR and unchanged in any

other Reset. Most other registers are reset to a “Reset

state” on Power-on Reset (POR), on the MCLR and

WDT Reset, on MCLR Reset during Sleep and

Brown-out Reset (BOR). They are not affected by a

WDT Wake-up, which is viewed as the resumption of

normal operation. The TO and PD bits are set or

cleared differently in different Reset situations as indi-

cated in Table 9-4. These bits are used in software to

determine the nature of the Reset. See Table 9-6 for a

full description of Reset states of all registers.

3: R1 = 100Ω to 1 kΩ will limit any current

flowing into MCLR from external capacitor C

in the event of MCLR/VPP pin breakdown due

to Electrostatic Discharge (ESD) or Electrical

Overstress (EOS).

DS41206B-page 64

PIC16F716

9.5

Power-up Timer (PWRT)

9.7

Programmable Brown-Out Reset

(PBOR)

The Power-up Timer provides a fixed nominal time-out,

on power-up only, from the POR. The Power-up Timer

operates on an internal RC oscillator. The chip is kept

in Reset as long as the PWRT is active. The PWRT’s

time delay allows VDD to rise to an acceptable level.

The power-up timer enable Configuration bit, PWRTE,

is provided to enable/disable the PWRT.

The PIC16F716 has on-chip Brown-out Reset circuitry.

A Configuration bit, BOREN, can disable (if clear/pro-

grammed) or enable (if set) the Brown-out Reset

circuitry.

The BORV Configuration bit selects the programmable

Brown-out Reset threshold voltage (VBOR). When

BORV is 1, VBOR IS 4.0V. When BORV is 0, VBOR is

2.5V

The power-up time delay will vary from chip-to-chip due

to VDD, temperature and process variation. See AC

parameters for details.

A Brown-out Reset occurs when VDD falls below VBOR

for a time greater than parameter TBOR (see Table 12-4).

A Brown-out Reset is not guaranteed to occur if VDD falls

below VBOR for less than parameter TBOR.

9.6

Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over. This ensures that the crystal

oscillator or resonator has started and stabilized. See

AC parameters for details.

On any Reset (Power-on, Brown-out, Watchdog, etc.)

the chip will remain in Reset until VDD rises above

VBOR. The Power-up Timer will be invoked and will

keep the chip in Reset an additional 72 ms only if the

Power-up Timer enable bit in the Configuration register

is set to 0 (PWRTE = 0).

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

Sleep.

If the Power-up Timer is enabled and VDD drops below

VBOR while the Power-up Timer is running, the chip will

go back into a Brown-out Reset and the Power-up

Timer will be re-initialized. Once VDD rises above VBOR,

the Power-up Timer will execute a 72 ms Reset. See

Figure 9-6.

For operations where the desired brown-out voltage is

other than 4.0V or 2.5V, an external brown-out circuit

must be used. Figure 9-8, Figure 9-9 and Figure 9-10

show examples of external Brown-out Protection

circuits.

DS41206B-page 65

PIC16F716

FIGURE 9-5:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR

Sleep

WDT

Module

Time-out

Reset

VDD rise

detect

Power-on Reset

VDD

Brown-out

Reset

S

R

BOREN

OST/PWRT

OST

10-bit Ripple counter

Chip_Reset

Q

OSC1

(1)

On-chip

RC OSC

PWRT

10-bit Ripple counter

PWRTE

See Table 9-3 for time-out

situations.

Enable OST

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.

FIGURE 9-6:

BROWN-OUT SITUATIONS (PWRTE = 0)

VDD

VBOR

Internal

Reset

72 ms

VDD

VBOR

Internal

Reset

<72 ms

72 ms

VDD

VBOR

Internal

Reset

72 ms

DS41206B-page 66

PIC16F716

FIGURE 9-7:

EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 1

FIGURE 9-9:

EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 3

VDD

33k

VDD

MCP809

Vss

VDD

Q1

bypass

capacitor

10k

MCLR

VDD

40k

RST

PIC16F716

MCLR

PIC16F716

Note 1: This circuit will activate Reset when VDD goes

below (Vz + 0.7V) where Vz = Zener voltage.

2: Internal Brown-out Reset circuitry should be

disabled when using this circuit.

Note 1: This brown-out protection circuit employs

Microchip Technology’s MCP809

microcontroller supervisor. The MCP8XX and

MCP1XX families of supervisors provide

push-pull and open collector outputs with

both high and low active Reset pins. There

are 7 different trip point selections to

accommodate 5V and 3V systems.

FIGURE 9-8:

EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 2

VDD

R1

VDD

Q1

MCLR

R2

40k

PIC16F716

Note 1: This brown-out circuit is less expensive, albeit

less accurate. Transistor Q1 turns off when VDD

is below a certain level such that:

R1

= 0.7 V

VDD x

R1 + R2

2: Internal Brown-out Reset should be disabled

when using this circuit.

3: Resistors should be adjusted for the

characteristics of the transistor.

DS41206B-page 67

PIC16F716

9.8

Time-out Sequence

9.9

Power Control/STATUS Register

(PCON)

On power-up, the time-out sequence is as follows: First

PWRT time-out is invoked after the POR time delay has

expired. Then OST is activated. The total time-out will

vary based on oscillator configuration and the status of

the PWRT. For example, in RC mode with the PWRT

disabled, there will be no time-out at all. Figure 9-10,

Figure 9-11, and Figure 9-12 depict time-out

sequences on power-up.

The Power Control/STATUS Register, PCON has two

bits.

Bit 0 is the Brown-out Reset Status bit, BOR. If the

BOREN Configuration bit is set, BOR is ‘1’ on

Power-on Reset and reset to ‘0’ when a Brown-out con-

dition occurs. BOR must then be set by the user and

checked on subsequent resets to see if it is clear, indi-

cating that another Brown-out has occurred.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then

bringing MCLR high will begin execution immediately

(Figure 9-12). This is useful for testing purposes or to

synchronize more than one PIC16F716 device

operating in parallel.

If the BOREN Configuration bit is clear, BOR is

unknown on Power-on Reset.

Bit 1 is POR (Power-on Reset Status bit). It is cleared

on a Power-on Reset and unaffected otherwise. The

user must set this bit following a Power-on Reset.

Table 9-5 shows the Reset conditions for some Special

Function Registers, while Table 9-6 shows the Reset

conditions for all the registers.

TABLE 9-3:

TIME-OUT IN VARIOUS SITUATIONS

Power-up or Brown-out

Oscillator Configuration

Wake-up from Sleep

PWRTE = 0

PWRTE = 1

XT, HS, LP

RC

72 ms + 1024 TOSC

72 ms

1024 TOSC

—

1024 TOSC

—

TABLE 9-4:

STATUS BITS AND THEIR SIGNIFICANCE

POR

BOR

TO

PD

0

x

1

Power-on Reset (BOREN = 0)

Power-on Reset (BOREN = 1)

0

x

0

x

Illegal, TO is set on POR

0

1

x

0

1

x

1

0

1

0

Illegal, PD is set on POR

Brown-out Reset

WDT Reset

WDT Wake-up

1

u

1

u

0

MCLR Reset during normal operation

MCLR Reset during Sleep or interrupt wake-up from Sleep

DS41206B-page 68

PIC16F716

TABLE 9-5:

RESET CONDITION FOR SPECIAL REGISTERS

Program

STATUS

Register

PCON

Register

Condition

Counter

Power-on Reset (BOREN = 0)

Power-on Reset (BOREN = 1)

000h

0001 1xxx

---- --0x

---- --01

MCLR Reset during normal operation

000h

000u uuuu

---- --uu

MCLR Reset during Sleep

WDT Reset

000h

0001 0uuu

0000 1uuu

uuu0 0uuu

0001 1uuu

uuu1 0uuu

---- --uu

---- --u0

---- --uu

WDT Wake-up

PC + 1

Brown-out Reset

000h

(1)

Interrupt wake-up from Sleep

PC + 1

Legend: u= unchanged, x= unknown, -= unimplemented bit read as ‘0’.

Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

DS41206B-page 69

PIC16F716

TABLE 9-6:

Register

INITIALIZATION CONDITIONS FOR ALL REGISTERS OF THE PIC16F716

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

Wake-up via WDT or

Interrupt

W

xxxx xxxx

N/A

uuuu uuuu

N/A

uuuu uuuu

N/A

INDF

TMR0

xxxx xxxx

0000h

uuuu uuuu

0000h

uuuu uuuu

PC + 1⁽²⁾

PCL

STATUS

0001 1xxx

xxxx xxxx

--xx 0000

xxxx xxxx

---0 0000

0000 -00x

-0-- -000

xxxx xxxx

--00 0000

0000 0000

-000 0000

xxxx xxxx

0000 0000

00-0 0000

xxxx xxxx

0000 0000

1111 1111

--11 1111

1111 1111

-0-- -000

---- --qq

1111 1111

---- -000

000q quuu⁽³⁾

uuuu uuuu

--xx 0000

uuuu uuuu

---0 0000

0000 -00u

-0-- -000

uuuu uuuu

--uu uuuu

0000 0000

-000 0000

uuuu uuuu

0000 0000

00-0 0000

uuuu uuuu

0000 0000

1111 1111

--11 1111

1111 1111

-0-- -000

---- --uu

1111 1111

---- -000

uuuq quuu⁽³⁾

uuuu uuuu

--uu uuuu

uuuu uuuu

---u uuuu

uuuu -uuu⁽¹⁾

-u-- -uuu⁽¹⁾

uuuu uuuu

--uu uuuu

uuuu uuuu

-uuu uuuu

uuuu uuuu

u-uu uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

-u-- -uuu

---- --uu

uuuu uuuu

---- -uuu

FSR

PORTA^{(4), (5), (6)}

PORTB^{(4), (5)}

PCLATH

INTCON

PIR1

TMR1L

TMR1H

T1CON

TMR2

T2CON

CCPR1L

CCPR1H

CCP1CON

PWM1CON

ECCPAS

ADRES

ADCON0

OPTION_REG

TRISA

TRISB

PIE1

PCON

PR2

ADCON1

Legend: u = unchanged, x = unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition

Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

3: See Table 9-5 for Reset value for specific condition.

4: On any device Reset, these pins are configured as inputs.

5: This is the value that will be in the port output latch.

6: Output latches are unknown or unchanged. Analog inputs default to analog and read ‘0’.

DS41206B-page 70

PIC16F716

FIGURE 9-10:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

FIGURE 9-11:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

FIGURE 9-12:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

DS41206B-page 71

PIC16F716

The peripheral interrupt flags are contained in the Spe-

cial Function Registers, PIR1 and PIR2. The

corresponding interrupt enable bits are contained in

Special Function Registers, PIE1 and PIE2, and the

peripheral interrupt enable bit is contained in Special

Function Register, INTCON.

9.10 Interrupts

The PIC16F716 devices have up to 7 sources of

interrupt. The Interrupt Control Register (INTCON)

records individual interrupt requests in flag bits. It also

has individual and global interrupt enable bits.

Note:

Individual interrupt flag bits are set regard-

less of the status of their corresponding

mask bit or the GIE bit.

When an interrupt is responded to, the GIE bit is

cleared to disable any further interrupt, the return

address is pushed onto the stack and the PC is loaded

with 0004h. Once in the Interrupt Service Routine, the

source(s) of the interrupt can be determined by polling

the interrupt flag bits. The interrupt flag bit(s) must be

cleared in software before re-enabling interrupts to

avoid recursive interrupts.

A Global Interrupt Enable bit, GIE of the INTCON

register enables all un-masked interrupts when set, or

disables all interrupts when cleared. When bit GIE is

enabled, and an interrupt’s flag bit and mask bit are set,

the interrupt will vector immediately. Individual

interrupts can be disabled through their corresponding

enable bits in various registers. Individual interrupt bits

are set, regardless of the status of the GIE bit. The GIE

bit is cleared on Reset and when an interrupt vector

occurs.

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs. The latency

is the same for one or two-cycle instructions. Individual

interrupt flag bits are set, regardless of the status of

their corresponding mask bit or the GIE bit.

The “return-from-interrupt” instruction, RETFIE, exits

the interrupt routine, as well as sets the GIE bit, which

re-enables interrupts.

The RB0/INT pin interrupt, the RB port change interrupt

and the TMR0 overflow interrupt flags are contained in

the INTCON register.

FIGURE 9-13:

INTERRUPT LOGIC

Wake-up (If in Sleep mode)

Interrupt to CPU

T0IF

T0IE

INTF

INTE

ADIF

ADIE

RBIF

RBIE

PEIE

GIE

CCP1IF

CCP1IE

TMR2IF

TMR2IE

TMR1IF

TMR1IE

DS41206B-page 72

PIC16F716

9.10.1

INT INTERRUPT

9.11 Context Saving During Interrupts

External interrupt on RB0/INT pin is edge triggered,

either rising if bit INTEDG of the OPTION register is set,

or falling if the INTEDG bit is clear. When a valid edge

appears on the RB0/INT pin, flag bit INTF of the

INTCON register is set. This interrupt can be disabled

by clearing enable bit INTE of the INTCON register.

Flag bit INTF must be cleared in software in the Inter-

rupt Service Routine before re-enabling this interrupt.

The INT interrupt can wake-up the processor from

Sleep, if bit INTE was set prior to going into Sleep. The

status of global interrupt enable bit GIE decides

whether or not the processor branches to the interrupt

vector following wake-up. See Section 9.13

“Power-down Mode (Sleep)” for details on Sleep

mode.

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key

registers during an interrupt, (i.e., W register and

STATUS register). This will have to be implemented in

firmware.

Example 9-1 stores and restores the W, STATUS,

PCLATH and FSR registers. Context storage registers,

W_TEMP, STATUS_TEMP, PCLATH_TEMP and

FSR_TEMP, must be defined in Common RAM which

are those addresses between 70h-7Fh in Bank 0 and

between F0h-FFh in Bank 1.

The example:

a) Stores the W register.

b) Stores the STATUS register in Bank 0.

c) Stores the PCLATH register.

d) Stores the FSR register.

9.10.2

TMR0 INTERRUPT

An overflow (FFh → 00h) in the TMR0 register will set

flag bit T0IF of the INTCON register. The interrupt can

be enabled/disabled by setting/clearing enable bit

T0IE of the INTCON register. (Section 4.0 “Timer0

Module”).

e) Executes the Interrupt Service Routine code

(User-generated).

f) Restores all saved registers in reverse order

from which they were stored.

9.10.3

PORTB INTCON CHANGE

An input change on PORTB<7:4> sets flag bit RBIF of

the INTCON register. The interrupt can be

enabled/disabled by setting/clearing enable bit RBIE of

the INTCON register. (Section 3.2 “PORTB and the

TRISB Register”).

EXAMPLE 9-1:

SAVING STATUS, W, AND PCLATH REGISTERS IN RAM

MOVWF

SWAPF

MOVWF

MOVF

MOVWF

CLRF

BCF

MOVF

MOVWF

:

W_TEMP

;Copy W to TEMP register, could be bank one or zero

STATUS,W

STATUS_TEMP

PCLATH, W

PCLATH_TEMP

PCLATH

STATUS, IRP

FSR, W

FSR_TEMP

;Swap status to be saved into W

;Save status to bank zero STATUS_TEMP register

;Only required if using pages 1, 2 and/or 3

;Save PCLATH into W

;Page zero, regardless of current page

;Return to Bank 0

;Copy FSR to W

;Copy FSR from W to FSR_TEMP

:(ISR)

:

MOVF

MOVWF

MOVF

MOVWF

SWAPF

MOVWF

SWAPF

RETFIE

FSR_TEMP,W

FSR

PCLATH_TEMP, W

PCLATH

STATUS_TEMP,W

STATUS

W_TEMP,F

W_TEMP,W

;Restore FSR

;Move W into FSR

;Restore PCLATH

;Move W into PCLATH

;Swap STATUS_TEMP register into W

;Move W into STATUS register

;Swap W_TEMP

;Swap W_TEMP into W

;Return from interrupt and enable GIE

DS41206B-page 73

PIC16F716

WDT time-out period values may be found in the

Electrical Specifications section under TWDT (parameter

#31). Values for the WDT prescaler (actually a

postscaler, but shared with the Timer0 prescaler) may be

assigned using the OPTION register.

9.12 Watchdog Timer (WDT)

The Watchdog Timer is a free running, on-chip, RC

oscillator which does not require any external

components. This RC oscillator is separate from the RC

oscillator of the OSC1/CLKIN pin. That means that the

WDT will run, even if the clock on the OSC1/CLKIN and

OSC2/CLKOUT pins of the device have been stopped,

for example, by execution of a SLEEPinstruction.

Note:

The CLRWDTand SLEEPinstructions clear

the WDT and the postscaler, if assigned to

the WDT, and prevent it from timing out

and generating a device Reset condition.

During normal operation, a WDT time-out generates a

device Reset (Watchdog Timer Reset). If the device is in

Sleep mode, a WDT time-out causes the device to

wake-up and continue with normal operation (Watchdog

Timer Wake-up). The TO bit in the STATUS register will

be cleared upon a Watchdog Timer time-out.

.

Note:

When a CLRWDT instruction is executed

and the prescaler is assigned to the WDT,

the prescaler count will be cleared, but the

prescaler assignment is not changed.

The WDT can be permanently disabled by clearing

Configuration bit WDTE (Section 9.1 “Configuration

Bits”).

FIGURE 9-14:

WATCHDOG TIMER BLOCK DIAGRAM

From TMR0 Clock Source (Figure 4-1)

0

Postscaler

M

1

U

WDT Timer

X

8

8-to-1 MUX

PS2:PS0

PSA

WDT

Enable Bit

To TMR0 (Figure 4-1)

0

1

MUX

PSA

WDT

Time-out

Note:

PSA and PS2:PS0 are bits in the OPTION register.

TABLE 9-7:

SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CONFIG1⁽¹⁾

BORV

RBPU

BOREN

INTEDG

—

PWRTE

PSA

WDTE

PS2

FOSC1

PS1

FOSC0

PS0

—

OPTION_REG

T0CS

T0SE

1111 1111

Legend:

x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used the Watchdog Timer.

Note 1:

See Configuration Word Register (Register 9-1) for operation of all register bits.

DS41206B-page 74

PIC16F716

The following peripheral interrupts can wake the device

from Sleep:

9.13 Power-down Mode (Sleep)

Power-Down mode is entered by executing a SLEEP

instruction.

1. TMR1 interrupt. Timer1 must be operating as an

asynchronous counter.

If enabled, the Watchdog Timer will be cleared but

keeps running, the PD bit of the STATUS register is

cleared, the TO of the STATUS register bit is set, and

the oscillator driver is turned off. The I/O ports maintain

the status they had, before the SLEEPinstruction was

executed (driving high, low or high-impedance).

2. ECCP capture mode interrupt.

3. ADC running in ADRC mode.

Other peripherals cannot generate interrupts, since

during Sleep, no on-chip clocks are present.

When the SLEEPinstruction is being executed, the next

instruction (PC + 1) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEPinstruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the

interrupt address (0004h). In cases where the

execution of the instruction following SLEEP is not

desirable, the user should have a NOPafter the SLEEP

instruction.

For lowest current consumption in this mode, place all

I/O pins at either VDD or VSS, ensure no external

circuitry is drawing current from the I/O pin,

power-down the A/D and the disable external clocks.

Pull all I/O pins that are high-impedance inputs, high or

low externally, to avoid switching currents caused by

floating inputs. The T0CKI input should also be at VDD

or VSS for lowest current consumption. The

contribution from on-chip pull-ups on PORTB should be

considered.

The MCLR pin must be at a logic high level (parameter

D042).

9.13.2

WAKE-UP USING INTERRUPTS

9.13.1

WAKE-UP FROM SLEEP

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

The device can wake-up from Sleep through one of the

following events:

1. External Reset input on MCLR pin.

• If the interrupt occurs before the execution of a

SLEEPinstruction, the SLEEPinstruction will com-

plete as a NOP. Therefore, the WDT and WDT

postscaler will not be cleared, the TO bit will not

be set and PD bits will not be cleared.

2. Watchdog Timer Wake-up (if WDT was

enabled).

3. Interrupt from INT pin, RB port change or some

peripheral interrupts.

External MCLR Reset will cause a device Reset. All

other events are considered a continuation of program

execution and cause a “wake-up”. The TO and PD bits

in the STATUS register can be used to determine the

cause of device Reset. The PD bit, which is set on

power-up, is cleared when Sleep is invoked. The TO bit

is cleared if a WDT time-out occurred (and caused

wake-up).

• If the interrupt occurs during or after the execu-

tion of a SLEEPinstruction, the device will imme-

diately wake-up from Sleep. The SLEEP

instruction will be completely executed before the

wake-up. Therefore, the WDT and WDT

postscaler will be cleared, the TO bit will be set

and the PD bit will be cleared.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEPinstruction completes. To

determine whether a SLEEPinstruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

To ensure that the WDT is cleared, a CLRWDT

instruction should be executed before a SLEEP

instruction.

DS41206B-page 75

PIC16F716

FIGURE 9-15:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

TOST(2)

INTF flag

Interrupt Latency

(INTCON Reg.)

(Note 3)

GIE bit

Processor in

Sleep

(INTCON Reg.)

INSTRUCTION FLOW

PC

PC+1

PC+2

PC + 2

0004h

0005h

Instruction

Inst(0004h)

Inst(PC + 1)

Inst(PC + 2)

Inst(0005h)

Inst(PC) = Sleep

fetched

Instruction

executed

Dummy cycle

Sleep

Inst(PC + 1)

Inst(PC - 1)

Inst(0004h)

Note 1:

XT, HS or LP Oscillator mode assumed.

TOST = 1024TOSC (drawing not to scale). This delay will not be there for RC Osc mode.

GIE = 1assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.

2:

3:

4:

CLKOUT is not available in these osc modes, but shown here for timing reference.

9.14 Program Verification/Code

Protection

9.16

In-Circuit Serial Programming™

PIC16F716

microcontrollers

can

be

serially

programmed while in the end application circuit. This is

simply done with two lines for clock and data, and three

other lines for power, ground and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware or a custom

firmware to be programmed.

If the code protection bit has not been programmed, the

on-chip program memory can be read out for

verification purposes.

9.15 ID Locations

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code-identification numbers. These locations are

not accessible during normal execution, but are

readable and writable during program/verify. It is

recommended that only the 4 Least Significant bits of

the ID location are used.

For complete details on serial programming, please

refer to the In-Circuit Serial Programming™ (ICSP™)

Specification, (DS40245).

DS41206B-page 76

PIC16F716

TABLE 10-1: OPCODE FIELD

10.0 INSTRUCTION SET SUMMARY

DESCRIPTIONS

The PIC16F716 instruction set is highly orthogonal and

is comprised of three basic categories:

Field

Description

f

W

b

Register file address (0x00 to 0x7F)

Working register (accumulator)

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations

Bit address within an 8-bit file register

Literal field, constant data or label

k

Each PIC16 instruction is a 14-bit word divided into an

opcode, which specifies the instruction type and one or

more operands, which further specify the operation of

the instruction. The formats for each of the categories

is presented in Figure 10-1, while the various opcode

fields are summarized in Table 10-1.

x

Don’t care location (= 0or 1).

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip software tools.

d

Destination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1.

Table 10-2 lists the instructions recognized by the

MPASM^TMassembler.

For byte-oriented instructions, ‘f’ represents a file

register designator and ‘d’ represents a destination

designator. The file register designator specifies which

file register is to be used by the instruction.

PC

TO

C

Program Counter

Time-out bit

Carry bit

DC

Z

Digit carry bit

Zero bit

The destination designator specifies where the result of

the operation is to be placed. If ‘d’ is zero, the result is

placed in the W register. If ‘d’ is one, the result is placed

in the file register specified in the instruction.

PD

Power-down bit

FIGURE 10-1:

GENERAL FORMAT FOR

INSTRUCTIONS

For bit-oriented instructions, ‘b’ represents a bit field

designator, which selects the bit affected by the

operation, while ‘f’ represents the address of the file in

which the bit is located.

Byte-oriented file register operations

13

8

7

6

0

For literal and control operations, ‘k’ represents an

8-bit or 11-bit constant, or literal value.

OPCODE

d

f (FILE #)

d = 0for destination W

d = 1for destination f

f = 7-bit file register address

One instruction cycle consists of four oscillator periods;

for an oscillator frequency of 4 MHz, this gives a

nominal instruction execution time of 1 μs. All

instructions are executed within a single instruction

cycle, unless a conditional test is true, or the program

counter is changed as a result of an instruction. When

this occurs, the execution takes two instruction cycles,

with the second cycle executed as a NOP.

Bit-oriented file register operations

13 10 9

b (BIT #)

7

6

0

OPCODE

f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies a

hexadecimal digit.

Literal and control operations

General

13

8

7

0

10.1 Read-Modify-Write Operations

OPCODE

k (literal)

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (R-M-W)

operation. The register is read, the data is modified,

and the result is stored according to either the instruc-

tion, or the destination designator ‘d’. A read operation

is performed on a register even if the instruction writes

to that register.

k = 8-bit immediate value

CALLand GOTOinstructions only

13 11 10

OPCODE

k = 11-bit immediate value

k (literal)

For example, a CLRF PORTA instruction will read

PORTA, clear all the data bits, then write the result back

to PORTA. This example would have the unintended

consequence of clearing the condition that set the RAIF

flag.

DS41206B-page 77

PIC16F716

TABLE 10-2: PIC16F716 INSTRUCTION SET

14-Bit Opcode

Mnemonic,

Description

Operands

Status

Affected

Cycles

Notes

MSb

LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

f, d

f

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

1

1(2)

1

1(2)

1

00 0111 dfff ffff C, DC, Z

1, 2

2

00 0101 dfff ffff

00 0001 lfff ffff

00 0001 0xxx xxxx

00 1001 dfff ffff

00 0011 dfff ffff

00 1011 dfff ffff

00 1010 dfff ffff

00 1111 dfff ffff

00 0100 dfff ffff

00 1000 dfff ffff

00 0000 lfff ffff

00 0000 0xx0 0000

00 1101 dfff ffff

00 1100 dfff ffff

Z

–

f, d

f

1, 2

1, 2, 3

1, 2

1, 2, 3

1, 2

DECFSZ

INCF

Z

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

Z

Move W to f

No Operation

–

f, d

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

C

1, 2

00 0010 dfff ffff C, DC, Z

00 1110 dfff ffff

00 0110 dfff ffff

Z

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1

1 (2)

01 00bb bfff ffff

1, 2

3

01 01bb bfff ffff

01 10bb bfff ffff

01 11bb bfff ffff

3

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

k

–

k

–

k

–

k

Add literal and W

AND literal with W

Call Subroutine

Clear Watchdog Timer

Go to address

1

2

1

2

1

2

1

11 111x kkkk kkkk C, DC, Z

11 1001 kkkk kkkk

10 0kkk kkkk kkkk

Z

00 0000 0110 0100 TO, PD

10 1kkk kkkk kkkk

Inclusive OR literal with W

Move literal to W

11 1000 kkkk kkkk

11 00xx kkkk kkkk

00 0000 0000 1001

11 01xx kkkk kkkk

00 0000 0000 1000

Z

Return from interrupt

Return with literal in W

Return from Subroutine

Go into Standby mode

Subtract W from literal

Exclusive OR literal with W

00 0000 0110 0011 TO, PD

11 110x kkkk kkkk C, DC, Z

11 1010 kkkk kkkk

Z

Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external

device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if

assigned to the Timer0 module.

3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second

cycle is executed as a NOP.

DS41206B-page 78

PIC16F716

10.2 Instruction Descriptions

BCF

Bit Clear f

ADDLW

Add literal and W

Syntax:

[ label ] BCF f,b

Syntax:

[ label ] ADDLW

0 ≤ k ≤ 255

k

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

Operation:

Status Affected:

Description:

(W) + k → (W)

C, DC, Z

Operation:

0→ (f<b>)

Status Affected:

Description:

None

The contents of the W register

are added to the eight-bit literal ‘k’

and the result is placed in the

W register.

Bit ‘b’ in register ‘f’ is cleared.

BSF

Bit Set f

ADDWF

Add W and f

Syntax:

[ label ] BSF f,b

Syntax:

[ label ] ADDWF f,d

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

1→ (f<b>)

Operation:

(W) + (f) → (destination)

Status Affected:

Description:

None

Status Affected: C, DC, Z

Bit ‘b’ in register ‘f’ is set.

Description:

Add the contents of the W register

with register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W register. If

‘d’ is ‘1’, the result is stored back

in register ‘f’.

BTFSC

Bit Test f, Skip if Clear

ANDLW

AND literal with W

Syntax:

[ label ] BTFSC f,b

Syntax:

[ label ] ANDLW

0 ≤ k ≤ 255

k

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

Operation:

Status Affected:

Description:

(W) .AND. (k) → (W)

Operation:

skip if (f<b>) = 0

Z

Status Affected: None

The contents of W register are

AND’ed with the eight-bit literal

‘k’. The result is placed in the W

register.

Description: If bit ‘b’ in register ‘f’ is ‘1’, the next

instruction is executed.

If bit ‘b’, in register ‘f’, is ‘0’, the

next instruction is discarded, and

a NOPis executed instead, making

this a two-cycle instruction.

ANDWF

AND W with f

Syntax:

[ label ] ANDWF f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(W) .AND. (f) → (destination)

Status Affected:

Description:

Z

AND the W register with register

‘f’. If ‘d’ is ‘0’, the result is stored in

the W register. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

DS41206B-page 79

PIC16F716

CLRWDT

Clear Watchdog Timer

BTFSS

Bit Test f, Skip if Set

Syntax:

[ label ] CLRWDT

Syntax:

[ label ] BTFSS f,b

Operands:

Operation:

None

Operands:

0 ≤ f ≤ 127

0 ≤ b < 7

00h → WDT

0→ WDT prescaler,

1→ TO

Operation:

skip if (f<b>) = 1

Status Affected: None

1→ PD

Description:

If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is executed.

Status Affected: TO, PD

Description:

CLRWDTinstruction resets the

Watchdog Timer. It also resets the

prescaler of the WDT.

If bit ‘b’ is ‘1’, then the next

instruction is discarded and a NOP

is executed instead, making this a

two-cycle instruction.

Status bits TO and PD are set.

CALL

Call Subroutine

COMF

Complement f

Syntax:

[ label ] CALL k

0 ≤ k ≤ 2047

Syntax:

[ label ] COMF f,d

Operands:

Operation:

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

(PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Operation:

(f) → (destination)

Status Affected:

Description:

Z

Status Affected: None

The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’,

the result is stored back in

register ‘f’.

Description:

Call Subroutine. First, return

address (PC + 1) is pushed onto

the stack. The eleven-bit

immediate address is loaded into

PC bits <10:0>. The upper bits of

the PC are loaded from PCLATH.

CALLis a two-cycle instruction.

CLRF

Clear f

DECF

Decrement f

Syntax:

[ label ] CLRF

0 ≤ f ≤ 127

f

Syntax:

[ label ] DECF f,d

Operands:

Operation:

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

00h → (f)

1→ Z

Operation:

(f) - 1 → (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

The contents of register ‘f’ are

cleared and the Z bit is set.

Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

CLRW

Clear W

Syntax:

[ label ] CLRW

Operands:

Operation:

None

00h → (W)

1→ Z

Status Affected:

Description:

Z

W register is cleared. Zero bit (Z)

is set.

DS41206B-page 80

PIC16F716

DECFSZ

Decrement f, Skip if 0

INCFSZ

Increment f, Skip if 0

Syntax:

[ label ] DECFSZ f,d

Syntax:

[ label ] INCFSZ f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(f) - 1 → (destination);

skip if result = 0

Operation:

(f) + 1 → (destination),

skip if result = 0

Status Affected: None

Description:

The contents of register ‘f’ are

Description:

The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

If the result is ‘1’, the next

instruction is executed. If the

result is ‘0’, then a NOPis

executed instead, making it a

two-cycle instruction.

If the result is ‘1’, the next

instruction is executed. If the

result is ‘0’, a NOPis executed

instead, making it a two-cycle

instruction.

GOTO

Unconditional Branch

IORLW

Inclusive OR literal with W

Syntax:

[ label ] GOTO

0 ≤ k ≤ 2047

k

Syntax:

[ label ] IORLW k

0 ≤ k ≤ 255

Operands:

Operation:

Operands:

Operation:

Status Affected:

Description:

k → PC<10:0>

PCLATH<4:3> → PC<12:11>

(W) .OR. k → (W)

Z

Status Affected: None

The contents of the W register are

OR’ed with the eight-bit literal ‘k’.

The result is placed in the

W register.

Description:

GOTOis an unconditional branch.

The eleven-bit immediate value is

loaded into PC bits <10:0>. The

upper bits of PC are loaded from

PCLATH<4:3>. GOTOis a

two-cycle instruction.

IORWF

Inclusive OR W with f

INCF

Increment f

Syntax:

[ label ] IORWF f,d

Syntax:

[ label ] INCF f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(W) .OR. (f) → (destination)

Operation:

(f) + 1 → (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

Inclusive OR the W register with

register ‘f’. If ‘d’ is ‘0’, the result is

placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

DS41206B-page 81

PIC16F716

MOVWF

Move W to f

[ label ] MOVWF

0 ≤ f ≤ 127

(W) → (f)

MOVF

Move f

Syntax:

f

Syntax:

Operands:

[ label ] MOVF f,d

Operands:

Operation:

Status Affected:

Description:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(f) → (dest)

None

Status Affected:

Description:

Z

Move data from W register to

register ‘f’.

The contents of register f is

moved to a destination dependent

upon the status of d. If d = 0,

destination is W register. If d = 1,

the destination is file register f

itself. d = 1is useful to test a file

register since status flag Z is

affected.

Words:

1

Cycles:

Example:

MOVW

F

OPTION

Before Instruction

OPTION = 0xFF

Words:

1

W

=

0x4F

After Instruction

Cycles:

Example:

OPTION = 0x4F

W

MOVF

FSR, 0

=

0x4F

After Instruction

W

=

value in FSR

register

Z

=

1

MOVLW

Syntax:

Move literal to W

NOP

No Operation

[ label ] MOVLW k

0 ≤ k ≤ 255

Syntax:

[ label ] NOP

Operands:

Operation:

Operands:

Operation:

Status Affected:

Description:

Words:

None

k → (W)

No operation

Status Affected: None

None

Description:

The eight-bit literal ‘k’ is loaded into

W register. The “don’t cares” will

assemble as ‘0’s.

No operation.

1

Cycles:

1

Words:

1

NOP

Example:

Cycles:

Example:

MOVLW

0x5A

After Instruction

W

=

0x5A

DS41206B-page 82

PIC16F716

RETFIE

Return from Interrupt

[ label ] RETFIE

None

RETLW

Return with literal in W

Syntax:

[ label ] RETLW k

0 ≤ k ≤ 255

Operands:

Operation:

Operands:

Operation:

TOS → PC,

1→ GIE

k → (W);

TOS → PC

Status Affected:

Description:

None

Status Affected:

Description:

None

Return from Interrupt. Stack is

POPed and Top-of-Stack (TOS) is

loaded in the PC. Interrupts are

enabled by setting Global

Interrupt Enable bit, GIE

The W register is loaded with the

eight bit literal ‘k’. The program

counter is loaded from the top of

the stack (the return address).

This is a two-cycle instruction.

(INTCON<7>). This is a two-cycle

instruction.

Words:

1

2

Cycles:

Example:

Words:

1

CALL TABLE;W contains

table

Cycles:

Example:

2

RETFIE

;offset value

•

;W now has table value

TABLE

After Interrupt

PC = TOS

GIE =

1

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2

;

•

RETLW kn ; End of table

Before Instruction

W

=

0x07

After Instruction

W

=

value of k8

RETURN

Return from Subroutine

Syntax:

[ label ] RETURN

None

Operands:

Operation:

TOS → PC

Status Affected: None

Description: Return from subroutine. The stack

is POPed and the top of the stack

(TOS) is loaded into the program

counter. This is a two-cycle

instruction.

DS41206B-page 83

PIC16F716

RLF

Rotate Left f through Carry

SLEEP

Enter Sleep mode

[ label ] SLEEP

None

Syntax:

Operands:

[ label ]

RLF f,d

Syntax:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

00h → WDT,

0→ WDT prescaler,

1→ TO,

Operation:

See description below

C

Status Affected:

Description:

0→ PD

The contents of register ‘f’ are

rotated one bit to the left through

the Carry flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

Status Affected:

Description:

TO, PD

The power-down Status bit, PD is

cleared. Time-out Status bit, TO

is set. Watchdog Timer and its

prescaler are cleared.

The processor is put into Sleep

mode with the oscillator stopped.

C

Register f

Words:

1

Cycles:

Example:

RLF

REG1,0

Before Instruction

REG1

C

=

1110 0110

0

After Instruction

REG1

W

C

=

1110 0110

1100 1100

1

SUBLW

Subtract W from literal

RRF

Rotate Right f through Carry

Syntax:

[ label ] SUBLW k

0 ≤ k ≤ 255

Syntax:

[ label ] RRF f,d

Operands:

Operation:

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

k - (W) → (W)

Operation:

See description below

C

Status Affected: C, DC, Z

Status Affected:

Description:

Description: The W register is subtracted (2’s

complement method) from the

eight-bit literal ‘k’. The result is

placed in the W register.

The contents of register ‘f’ are

rotated one bit to the right through

the Carry flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is placed

back in register ‘f’.

C = 0

W > k

C = 1

W ≤ k

DC = 0

DC = 1

W<3:0> > k<3:0>

W<3:0> ≤ k<3:0>

C

Register f

DS41206B-page 84

PIC16F716

SUBWF

Subtract W from f

XORLW

Exclusive OR literal with W

Syntax:

[ label ] SUBWF f,d

Syntax:

[ label ] XORLW k

0 ≤ k ≤ 255

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

Status Affected:

Description:

(W) .XOR. k → (W)

Z

Operation:

(f) - (W) → (destination)

Status Affected: C, DC, Z

The contents of the W register

are XOR’ed with the eight-bit

literal ‘k’. The result is placed in

the W register.

Description:

Subtract (2’s complement method)

W register from register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f.

C = 0

W > f

C = 1

W ≤ f

DC = 0

DC = 1

W<3:0> > f<3:0>

W<3:0> ≤ f<3:0>

SWAPF

Swap Nibbles in f

XORWF

Exclusive OR W with f

Syntax:

[ label ] SWAPF f,d

Syntax:

[ label ] XORWF f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(f<3:0>) → (destination<7:4>),

(f<7:4>) → (destination<3:0>)

Operation:

(W) .XOR. (f) → (destination)

Status Affected:

Description:

Z

Status Affected: None

Exclusive OR the contents of the

W register with register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

Description: The upper and lower nibbles of

register ‘f’ are exchanged. If ‘d’ is

‘0’, the result is placed in the W

register. If ‘d’ is ‘1’, the result is

placed in register ‘f’.

DS41206B-page 85

PIC16F716

NOTES:

DS41206B-page 86

PIC16F716

11.1 MPLAB Integrated Development

Environment Software

11.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers are supported with a full

range of hardware and software development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• Assemblers/Compilers/Linkers

- MPASM^TMAssembler

• A single graphical interface to all debugging tools

- Simulator

- MPLAB C18 and MPLAB C30 C Compilers

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- Programmer (sold separately)

- Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

• Emulators

• Customizable data windows with direct edit of

contents

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debugger

• High-level source code debugging

• Visual device initializer for easy register

initialization

- MPLAB ICD 2

• Mouse over variable inspection

• Device Programmers

• Drag and drop variables from source to watch

windows

- PICSTART^®Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Extensive on-line help

• Integration of select third party tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

The MPLAB IDE allows you to:

• Edit your source files (either assembly or C)

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools

(automatically updates all project information)

• Debug using:

- Source files (assembly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

DS41206B-page 87

PIC16F716

11.2 MPASM Assembler

11.5 MPLAB ASM30 Assembler, Linker

and Librarian

The MPASM Assembler is a full-featured, universal

macro assembler for all PIC MCUs.

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• User-defined macros to streamline

assembly code

• Rich directive set

• Conditional assembly for multi-purpose

source files

• Flexible macro language

• MPLAB IDE compatibility

• Directives that allow complete control over the

assembly process

11.6 MPLAB SIM Software Simulator

11.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC^®DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI

C

compilers for

Microchip’s PIC18 and PIC24 families of microcontrol-

lers and the dsPIC30 and dsPIC33 family of digital sig-

nal controllers. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

11.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

DS41206B-page 88

PIC16F716

11.7 MPLAB ICE 2000

High-Performance

11.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash PIC

MCUs and can be used to develop for these and other

PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes

the in-circuit debugging capability built into the Flash

devices. This feature, along with Microchip’s In-Circuit

Serial Programming^TM(ICSP^TM) protocol, offers cost-

effective, in-circuit Flash debugging from the graphical

user interface of the MPLAB Integrated Development

Environment. This enables a designer to develop and

debug source code by setting breakpoints, single step-

ping and watching variables, and CPU status and

peripheral registers. Running at full speed enables

testing hardware and applications in real time. MPLAB

ICD 2 also serves as a development programmer for

selected PIC devices.

In-Circuit Emulator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PIC

microcontrollers. Software control of the MPLAB ICE

2000 In-Circuit Emulator is advanced by the MPLAB

Integrated Development Environment, which allows

editing, building, downloading and source debugging

from a single environment.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing features. Interchangeable processor modules allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PIC microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft^®Windows^®32-bit operating system were

chosen to best make these features available in a

simple, unified application.

11.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an SD/MMC card for

file storage and secure data applications.

11.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC^®and MCU devices. It debugs and

programs PIC^®and dsPIC^®Flash microcontrollers with

the easy-to-use, powerful graphical user interface of the

MPLAB Integrated Development Environment (IDE),

included with each kit.

The MPLAB REAL ICE probe is connected to the design

engineer’s PC using a high-speed USB 2.0 interface and

is connected to the target with either a connector

compatible with the popular MPLAB ICD 2 system

(RJ11) or with the new high speed, noise tolerant, low-

voltage differential signal (LVDS) interconnection

(CAT5).

MPLAB REAL ICE is field upgradeable through future

firmware downloads in MPLAB IDE. In upcoming

releases of MPLAB IDE, new devices will be supported,

and new features will be added, such as software break-

points and assembly code trace. MPLAB REAL ICE

offers significant advantages over competitive emulators

including low-cost, full-speed emulation, real-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables.

DS41206B-page 89

PIC16F716

11.11 PICSTART Plus Development

Programmer

11.13 Demonstration, Development and

Evaluation Boards

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PIC devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76X, may be supported with an adapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

11.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer and selected Flash device debugger with

an easy-to-use interface for programming many of

Microchip’s baseline, mid-range and PIC18F families of

Flash memory microcontrollers. The PICkit 2 Starter Kit

includes a prototyping development board, twelve

sequential lessons, software and HI-TECH’s PICC™

Lite C compiler, and is designed to help get up to speed

quickly using PIC^®microcontrollers. The kit provides

everything needed to program, evaluate and develop

applications using Microchip’s powerful, mid-range

Flash memory family of microcontrollers.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

®

for analog filter design, KEELOQ security ICs, CAN,

IrDA^®, PowerSmart^®battery management, SEEVAL^®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

and the latest “Product Selector Guide” (DS00148) for

the complete list of demonstration, development and

evaluation kits.

DS41206B-page 90

PIC16F716

12.0 ELECTRICAL CHARACTERISTICS

†

Absolute Maximum Ratings^{( )}

Ambient temperature under bias..........................................................................................................-55°C to +125°C

Storage temperature ........................................................................................................................... -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ....................................... -0.3V to (VDD +0.3V)

Voltage on VDD with respect to VSS ...................................................................................................... -0.3V to +7.5V

Voltage on MCLR with respect to VSS (Note 2) ...................................................................................... 0V to +13.25V

Voltage on RA4 with respect to Vss............................................................................................................ 0V to +8.5V

Total power dissipation (Note 1) (PDIP and SOIC)................................................................................................1.0W

Total power dissipation (Note 1) (SSOP).............................................................................................................0.65W

Maximum current out of VSS pin ........................................................................................................................300 mA

Maximum current into VDD pin ...........................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)................................................................................................................... 20 mA

Output clamp current, IOK (VO < 0 or VO > VDD) ........................................................................................................... 20 mA

Maximum output current sunk by any I/O pin.......................................................................................................25 mA

Maximum output current sourced by any I/O pin .................................................................................................25 mA

Maximum current sunk by PORTA and PORTB (combined)..............................................................................200 mA

Maximum current sourced by PORTA and PORTB (combined) ........................................................................200 mA

Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)

2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.

Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin rather

than pulling this pin directly to VSS.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

DS41206B-page 91

PIC16F716

FIGURE 12-1:

PIC16F716 VOLTAGE-FREQUENCY GRAPH, -40°C < TA < +85°C⁽¹⁾

6.0

5.5

5.0

4.5

4.0

3.5

VDD

(Volts)

3.0

2.5

2.0

0

4

10

20

25

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

FIGURE 12-2:

PIC16F716 VOLTAGE-FREQUENCY GRAPH, 85°C < TA < +125°C⁽¹⁾

6.0

5.5

5.0

4.5

VDD

(Volts)

4.0

3.5

3.0

2.5

2.0

0

4

10

20

25

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

DS41206B-page 92

PIC16F716

12.1 DC Characteristics: PIC16F716 (Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

DC CHARACTERISTICS

Param

Sym

No.

Characteristic

Min Typ† Max Units

Conditions

VDD Supply Voltage

D001

D001A

2.0

3.0

—

5.5

V

Industrial

Extended

D002* VDR RAM Data Retention

—

1.5*

Vss

—

V

Voltage⁽¹⁾

D003

D004*

D005

VPOR VDD Start Voltage to ensure

—

V

See section on Power-on Reset for

details

internal Power-on Reset signal

SVDD VDD Rise Rate to ensure

0.05

V/ms PWRT enabled (PWRTE bit clear)

internal Power-on Reset signal

VBOR Brown-out Reset voltage trip

point

3.65

2.2

4.0 4.35

2.5 2.7

V

BOREN bit set, BOR bit = ‘1’

BOREN bit set, BOR bit = ‘0’

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: This is the limit to which VDD can be lowered without losing RAM data.

DS41206B-page 93

PIC16F716

12.2 DC Characteristics: PIC16F716 (Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

DC CHARACTERISTICS

Param

No.

Sym

Characteristic

Min Typ† Max Units VDD

Conditions

VDD

Supply Voltage

Supply Current

D001

2.0

—

5.5

V

—

IDD

—

14

23

45

17

28

μA

mA

2.0 FOSC = 32 kHz

D010

LP Oscillator mode

3.0

63.7

5.0

120 160

180 250

290 370

220 300

350 470

600 780

2.0 FOSC = 1 MHz

D011

D012

XT Oscillator mode

3.0

5.0

2.0 FOSC = 4 MHz

XT Oscillator mode

3.0

5.0

2.1

2.5

2.9

3.3

4.5 FOSC = 20 MHz

D013

D020

HS Oscillator mode

5.0

IPD

Power-down Base Current

Peripheral Module Current⁽¹⁾

—

0.1

0.8

μA

2.0 WDT, BOR and T1OSC:

disabled

0.1 0.85

3.0

0.2

2.7

5.0

—

1

2

2.0

3.5

13.5

50

55

60

6

μA

2.0 WDT Current

D021

3.0

9

5.0

37

40

45

1.8

2.6

3.0

3.0 BOR Current

D022

D025

4.5

5.0

2.0 T1OSC Current

7.5

9

3.0

5.0

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this

peripheral is enabled. The peripheral “Δ” current can be determined by subtracting the base IDD or IPD

current from this limit.

DS41206B-page 94

PIC16F716

12.3 DC Characteristics: PIC16F716 (Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C

DC CHARACTERISTICS

Param

No.

Sym

Characteristic

Min Typ† Max Units VDD

Conditions

VDD

Supply Voltage

Supply Current

D001

3.0

—

5.5

28

V

—

IDD

—

21

μA

3.0 FOSC = 32 kHz

D010E

LP Oscillator mode

38 63.7 μA

5.0

182 250

293 370

371 470

668 780

μA

mA

3.0 FOSC = 1 MHz

D011E

D012E

D013E

XT Oscillator mode

5.0

3.0 FOSC = 4 MHz

XT Oscillator mode

5.0

2.6

3

2.9

3.3

4.5 FOSC = 20 MHz

HS Oscillator mode

5.0

IPD

Power-down Base Current

Peripheral Module Current⁽¹⁾

—

0.1

0.2

11

15

μA

3.0 WDT, BOR and T1OSC: disabled

5.0

D020E

—

2

19

22

60

71

76

20

25

μA

3.0 WDT Current

D021E

D022E

9

5.0

37

40

45

2.6

3.0

4.5 BOR Current

5.0

3.0 T1OSC Current

5.0

D025E

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this

peripheral is enabled. The peripheral “Δ” current can be determined by subtracting the base IDD or IPD

current from this limit.

DS41206B-page 95

PIC16F716

12.4 DC Characteristics: PIC16F716 (Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

DC CHARACTERISTICS

Operating voltage VDD range as described in DC spec Section 12.1 “DC Charac-

teristics: PIC16F716 (Industrial, Extended)” and Section 12.4 “DC Character-

istics: PIC16F716 (Industrial, Extended)”.

Param

Sym

No.

Characteristic

Min

Typ†

Max

Units

Conditions

Input Low Voltage

I/O ports

VIL

D030

D030A

D031

D032

D033

with TTL buffer

VSS

—

0.8

V

4.5V ≤ VDD ≤ 5.5V

otherwise

0.15 VDD

0.2 VDD

0.3 VDD

0.6

with Schmitt Trigger buffer

MCLR, OSC1 (in RC mode)

OSC1 (in HS mode)

OSC1 (in XT and LP modes)

Input High Voltage

I/O ports

VSS

(Note1)

VIH

—

D040

with TTL buffer

2.0

0.25 VDD +

0.8V

VDD

V

4.5V ≤ VDD ≤ 5.5V

otherwise

D040A

D041

D042

D042A

D043

with Schmitt Trigger buffer

MCLR

0.8 VDD

0.7 VDD

0.9 VDD

—

VDD

V

For entire VDD range

OSC1 (XT, HS and LP modes)

OSC1 (in RC mode)

(Note1)

(2), (3)

Input Leakage Current

D060

IIL

I/O ports

—

1

μA Vss ≤ VPIN ≤ VDD, Pin at

high-impedance

nA Vss ≤ VPIN ≤ VDD, Pin configured as

analog input

500

D061

D063

MCLR, RA4/T0CKI

OSC1/CLKIN

—

5

μA Vss ≤ VPIN ≤ VDD

μA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc

modes

D070

D080

IPURB

VOL

PORTB weak pull-up current

Output Low Voltage

I/O ports

50

—

250

—

400

0.6

μA VDD = 5V, VPIN = VSS

V

IOL = 8.5 mA, VDD = 4.5V, -40°C to

+85°C

IOL = 7.0 mA, VDD = 4.5V, -40°C to

+125°C

IOL = 1.6 mA, VDD = 4.5V, -40°C to

+85°C

IOL = 1.2 mA, VDD = 4.5V, -40°C to

+125°C

—

D083

OSC2/CLKOUT (RC Osc mode)

—

Output High Voltage

(3)

D090

D092

D150*

VOH

I/O ports

VDD-0.7

—

V

IOH = -3.0 mA, VDD = 4.5V, -40°C to

+85°C

IOH = -2.5 mA, VDD = 4.5V, -40°C to

+125°C

IOH = -1.3 mA, VDD = 4.5V, -40°C to

+85°C

IOH = -1.0 mA, VDD = 4.5V, -40°C to

+125°C

OSC2/CLKOUT (RC Osc mode)

—

VOD

Open-Drain High Voltage

8.5

RA4 pin

Capacitive Loading Specs on Output Pins

D100

D101

COSC2 OSC2/CLKOUT pin

—

15

50

pF In XT, HS and LP modes when external

clock is used to drive OSC1.

pF

CIO All I/O pins and OSC2 (in RC mode)

—

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

In RC Oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC^®be driven with

external clock in RC mode.

Note 1:

2:

3:

The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

Negative current is defined as current sourced by the pin.

DS41206B-page 96

PIC16F716

12.5 AC (Timing) Characteristics

12.5.1 TIMING PARAMETER SYMBOLOGY

The timing parameter symbols have been created

using one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

T

Time

Lowercase letters (pp) and their meanings:

pp

cc

ck

cs

di

CCP1

CLKOUT

CS

osc

rd

OSC1

RD

rw

sc

ss

t0

RD or WR

SCK

SDI

do

dt

SDO

SS

Data in

I/O port

MCLR

T0CKI

T1CKI

WR

io

t1

mc

wr

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

Rise

High

Invalid (High-impedance)

Low

Valid

L

High-impedance

DS41206B-page 97

PIC16F716

12.5.2

TIMING CONDITIONS

The temperature and voltages specified in Table 12-1

apply to all timing specifications, unless otherwise

noted. Figure 12-3 specifies the load conditions for the

timing specifications.

TABLE 12-1: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

AC CHARACTERISTICS

Operating voltage VDD range as described in DC spec Section 12.1 “DC Character-

istics: PIC16F716 (Industrial, Extended)” and Section 12.4 “DC Characteristics:

PIC16F716 (Industrial, Extended)”. LC parts operate for commercial/industrial

temp’s only.

FIGURE 12-3:

LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load condition 1 Load condition 2

VDD/2

Cl

Rl

VSS

Cl

Legend:

RL = 464Ω

VSS

CL = 50 pF for all pins except OSC2/CLKOUT

15 pF for OSC2 output

12.5.3

TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 12-4:

EXTERNAL CLOCK TIMING

Q1

Q2

Q3

Q4

4

Q4

Q1

OSC1

3

1

4

2

CLKOUT

DS41206B-page 98

PIC16F716

TABLE 12-2: EXTERNAL CLOCK TIMING REQUIREMENTS

Param

Sym

Characteristic

Min Typ†

Max

Units

Conditions

No.

1A

FOSC Ext. Clock Input Frequency⁽¹⁾

DC

0.1

4

—

4

20

MHz RC and XT Osc modes

MHz HS Osc mode

kHz LP Osc mode

MHz RC Osc mode

MHz XT Osc mode

MHz HS Osc mode

kHz LP Osc mode

ns RC and XT Osc modes

ns HS Osc mode

μs LP Osc mode

200

4

Oscillator Frequency⁽¹⁾

4

20

5

200

—

1

TOSC

External CLKIN Period⁽¹⁾

Oscillator Period⁽¹⁾

250

50

—

5

—

250

50

—

ns RC Osc mode

10,000

250

—

ns XT Osc mode

ns HS Osc mode

μs LP Osc mode

5

2

Tcy

Instruction Cycle Time⁽¹⁾

200

DC

—

ns

TCY = 4/FOSC

3*

TosL, External Clock in (OSC1) High or 100

TosH Low Time

ns XT oscillator

μs LP oscillator

ns HS oscillator

ns XT oscillator

ns LP oscillator

ns HS oscillator

2.5

—

15

—

4*

TosR, External Clock in (OSC1) Rise or

TosF Fall Time

—

25

50

15

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code. Exceeding these specified limits may result in an unstable oscillator

operation and/or higher than expected current consumption. All devices are tested to operate at “min”

values with an external clock applied to the OSC1/CLKIN pin.

When an external clock input is used, the “Max” cycle time limit is “DC” (no clock) for all devices.

DS41206B-page 99

PIC16F716

FIGURE 12-5:

CLKOUT AND I/O TIMING

Q1

Q2

Q3

Q4

OSC1

11

10

CLKOUT

13

12

19

18

14

16

I/O Pin

(input)

15

17

I/O Pin

(output)

new value

old value

20, 21

Note 1: Refer to Figure 12-3 for load conditions.

TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS

Param

Sym

Characteristic

Min

Typ†

Max

Units Conditions

No.

10*

TOSH2CKL OSC1↑ to CLKOUT↓

TOSH2CKH OSC1↑ to CLKOUT↑

—

75

35

—

200

100

20

ns

(Note 1)

11*

12*

13*

14*

15*

TCKR

TCKF

CLKOUT rise time

CLKOUT fall time

TCKL2IOV CLKOUT ↓ to Port out valid

TIOV2CKH Port input valid before CLKOUT ↑

TOSC +

200

—

16*

TCKH2IOI

Port input hold after CLKOUT ↑

0

—

50

—

150

—

ns

(Note 1)

17*

TOSH2IOV OSC1↑ (Q1 cycle) to Port out valid

—

18*

TOSH2IOI

OSC1↑ (Q2 cycle) to Port Standard

100

200

input invalid (I/O in hold

time)

18A*

Extended (LC)

—

19*

TIOV2OSH Port input valid to OSC1↑ (I/O in setup time)

0

—

10

—

10

—

40

80

40

80

—

ns

20*

TIOR

TIOF

Port output rise time

Port output fall time

INT pin high or low time

Standard

—

20A*

21*

Extended (LC)

Standard

—

21A*

22††*

23††*

Extended (LC)

—

TINP

Tcy

TRBP

RB<7:4> change INT high or low time

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

†† These parameters are asynchronous events not related to any internal clock edge.

Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.

DS41206B-page 100

PIC16F716

FIGURE 12-6:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING⁽¹⁾

VDD

MCLR

30

Internal

POR

33

PWRT

Time-out

32

OSC

Time-out

Internal

Reset

Watchdog

Timer

Reset

31

34

I/O Pins

Note 1: Refer to Figure 12-3 for load conditions.

FIGURE 12-7:

BROWN-OUT RESET TIMING

BVDD

VDD

35

TABLE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

AND BROWN-OUT RESET REQUIREMENTS

Param

No.

Sym

Characteristic

Min

Typ†

Max Units

Conditions

30

TMCL

TWDT

MCLR Pulse Width (low)

Watchdog Timer Time-out Period

(No Prescaler)

2

7

—

18

—

33

μs VDD = 5V, -40°C to +125°C

ms VDD = 5V, -40°C to +85°C

ms VDD = 5V, +85°C to +125°C

31*

TBD

—

TBD

—

32

TOST

Oscillation Start-up Timer Period

1024 TOSC

72

—

TOSC = OSC1 period

33*

TPWRT Power-up Timer Period

28

132

TBD

ms VDD = 5V, -40°C to +85°C

ms VDD = 5V, +85°C to +125°C

TBD

34

35

T^IOZ

I/O high-impedance from MCLR

Low or WDT Reset

—

2.1

μs

T^BOR

Brown-out Reset Pulse Width

100

—

μs VDD ≤ BVDD (D005)

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

DS41206B-page 101

PIC16F716

FIGURE 12-8:

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS⁽¹⁾

T0CKI

41

40

42

T1OSO/T1CKI

46

45

47

48

TMR0 or

TMR1

Note 1: Refer to Figure 12-3 for load conditions.

TABLE 12-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

No.

Sym

Tt0H

Characteristic

T0CKI High Pulse Width

Min

Typ† Max Units

Conditions

40*

No Prescaler

With Prescaler

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5TCY + 20

10

—

ns Must also meet

parameter 42

ns Must also meet

ns

41*

42*

Tt0L

Tt0P

T0CKI Low Pulse Width

T0CKI Period

0.5TCY + 20

10

parameter 42

ns

TCY + 40

Greater of:

20 or TCY + 40

N

ns N = prescale

value

(2, 4,..., 256)

ns Must also meet

45*

46*

47*

Tt1H

Tt1L

T1CKI High Time Synchronous, Prescaler = 1

Synchronous, Standard

Prescaler =

0.5TCY + 20

15

—

parameter 47

ns

2,4,8

Asynchronous Standard

T1CKI Low Time Synchronous, Prescaler = 1

Synchronous, Standard

Prescaler =

30

0.5TCY + 20

15

—

ns

ns Must also meet

parameter 47

ns

2,4,8

Asynchronous Standard

30

Greater of:

30 OR TCY + 40

N

—

ns

Tt1P

Ft1

T1CKI input

period

Synchronous Standard

ns N = prescale

value (1, 2, 4, 8)

Asynchronous Standard

60

—

ns

Timer1 oscillator input frequency range

32.768

32.768 kHz

(oscillator enabled by setting bit T1OSCEN)

48*

TCKEZtmr1 Delay from external clock edge to timer increment

2Tosc

—

7Tosc

—

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

DS41206B-page 102

PIC16F716

FIGURE 12-9:

CAPTURE/COMPARE/PWM TIMINGS⁽¹⁾

CCP1

(Capture Mode)

50

51

52

54

CCP1

(Compare or PWM Mode)

53

Note 1: Refer to Figure 12-3 for load conditions.

TABLE 12-6: CAPTURE/COMPARE/PWM REQUIREMENTS

Param

Sym

Characteristic

Min

Typ† Max Units Conditions

No.

50*

TccL CCP1 input low No Prescaler

time

0.5TCY + 20

10

—

ns

With Prescaler Standard

51*

52*

TccH CCP1 input high No Prescaler

time

0.5TCY + 20

10

With Prescaler Standard

TccP CCP1 input period

3TCY + 40

N

ns N = prescale

value (1,4, or

16)

53*

TccR CCP1 output rise time

TccF CCP1 output fall time

Standard

Extended

Standard

Extended

—

10

—

10

—

40

80

40

80

ns

53A*

54*

54A*

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

DS41206B-page 103

PIC16F716

TABLE 12-7: A/D CONVERTER CHARACTERISTICS: PIC16F716 (INDUSTRIAL, EXTENDED)

Param

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

No.

A00

VDD VDD Operation

NR Resolution

2.5

—

5.5

V

A01

A02

A03

A04

A05

A06

8-bits

bit VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

EABS Total Absolute error

EIL Integral linearity error

EDL Differential linearity error

EFS Full scale error

—

< ± 1

LSb VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

LSb VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

LSb VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

LSb VREF = VDD= 5.12V,

VSS ≤ VAIN ≤ VREF

EOFF Offset error

LSb VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

A10

A20

A25

—

Monotonicity

—

guaranteed⁽³⁾

—

V

VSS ≤ VAIN ≤ VREF

VREF Reference voltage

VAIN Analog input voltage

2.5V

—

VDD + 0.3

VSS -

0.3

VREF +

0.3

V

A30

A40

ZAIN Recommended impedance of

analog voltage source

—

10.0

kΩ

IAD A/D conversion

current (VDD)

Standard

—

180

—

μA Average current

consumption when

A/D is on.⁽¹⁾

A50

IREF VREF input current⁽²⁾

10

—

1000

10

μA During VAIN

acquisition.

Based on differential

of VHOLD to VAIN to

charge CHOLD, see

μA Section 12.1 “DC

Characteristics:

PIC16F716 (Indus-

trial, Extended)”.

During A/D

Conversion cycle

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: When A/D is off, it will not consume any current other than minor leakage current.

The power-down current spec includes any such leakage from the A/D module.

2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.

3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing

codes.

DS41206B-page 104

PIC16F716

FIGURE 12-10:

A/D CONVERSION TIMING

BSF ADCON0, GO

134

1 Tcy

(TOSC/2)⁽¹⁾

131

130

Q4

132

A/D CLK

7

6

5

4

3

2

1

0

A/D DATA

NEW_DATA

DONE

OLD_DATA

ADRES

ADIF

GO

SAMPLING STOPPED

SAMPLE

Note 1:

If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEPinstruction

to be executed.

TABLE 12-8: A/D CONVERSION REQUIREMENTS

Param

No.

Sym

Characteristic

Min

Typ†

Max Units

Conditions

130

TAD A/D clock period

Industrial

Extended

1.6

—

4.0

—

6.0

—

μs

TOSC based, VREF ≥ 3.0V

μs A/D RC mode

1.6

μs

TOSC based, VREF ≥ 3.0V

1.6

6.0

—

9.0

9.5

—

μs A/D RC mode

(1)

131

132

TCNV Conversion time (not including S/H time)

TACQ Acquisition time

9.5

TAD

(Note 2)

20

μs

5*

—

μs The minimum time is the amplifier

settling time. This may be used if

the “new” input voltage has not

changed by more than 1 LSb (i.e.,

20.0 mV @ 5.12V) from the last

sampled voltage (as stated on

CHOLD).

134

135

TGO Q4 to A/D clock start

—

TOSC/2 **

—

If the A/D clock source is selected

as RC, a time of TCY is added

before the A/D clock starts. This

allows the SLEEPinstruction to be

executed.

TSWC Switching from convert → sample time

1.5 **

—

TAD

*

These parameters are characterized but not tested.

** This specification ensured by design.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: ADRES register may be read on the following TCY cycle.

2: See Section 12.1 “DC Characteristics: PIC16F716 (Industrial, Extended)” for min. conditions.

DS41206B-page 105

PIC16F716

NOTES:

DS41206B-page 106

PIC16F716

13.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

The graphs and tables provided in this section are for design guidance and are not tested.

In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD

range). This is for information only and devices are ensured to operate properly only within the specified range.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are

not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents

(mean + 3σ) or (mean - 3σ) respectively, where σ is a standard deviation, over each temperature range.

FIGURE 13-1:

TYPICAL IDD vs. FOSC OVER VDD (EC MODE)

3.5

Typical: Statistical Mean @25°C

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

5.5V

5.0V

4.0V

3.0V

2.0V

1 MHz

2 MHz

4 MHz

6 MHz

8 MHz

10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz

FOSC

DS41206B-page 107

PIC16F716

FIGURE 13-2:

MAXIMUM IDD vs. FOSC OVER VDD (EC MODE)

4.0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

5.5V

5.0V

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

4.0V

3.0V

2.0V

1 MHz

2 MHz

4 MHz

6 MHz

8 MHz

10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz

FOSC

FIGURE 13-3:

TYPICAL IDD vs. FOSC OVER VDD (HS MODE)

Typical IDD vs. FOSC Over Vdd

HS Mode

4.0

Typical: Statistical Mean @25°C

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

4 MHz

10 MHz

16 MHz

20 MHz

FOSC

DS41206B-page 108

PIC16F716

FIGURE 13-4:

MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)

Maximum IDD vs. FOSC Over Vdd

HS Mode

5.0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

4 MHz

10 MHz

16 MHz

20 MHz

FOSC

FIGURE 13-5:

TYPICAL IDD vs. VDD OVER FOSC (XT MODE)

XT Mode

900

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

800

700

600

500

400

300

200

100

0

4 MHz

1 MHz

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41206B-page 109

PIC16F716

FIGURE 13-6:

MAXIMUM IDD vs. VDD OVER FOSC (XT MODE)

XT Mode

1,400

1,200

1,000

800

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

4 MHz

1 MHz

600

400

200

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 13-7:

TYPICAL IDD vs. VDD OVER FOSC (EXTRC MODE)

800

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

700

600

500

400

300

200

100

0

4 MHz

1 MHz

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41206B-page 110

PIC16F716

FIGURE 13-8:

MAXIMUM IDD vs. VDD (EXTRC MODE)

EXTRC Mode

1,400

1,200

1,000

800

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

4 MHz

1 MHz

600

400

200

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 13-9:

IDD vs. VDD (LP MODE)

70

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

60

50

40

30

20

10

0

32 kHz Maximum

32 kHz Typical

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41206B-page 111

PIC16F716

FIGURE 13-10:

TYPICAL IPD vs. VDD (SLE_TE_yP_picM_aO_lDE, ALL PERIPHERALS DISABLED)

(Sleep Mode all Peripherals Disabled)

0.45

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 13-11:

MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)

Maximum

(Sleep Mode all Peripherals Disabled)

18.0

Typical: Statistical Mean @25°C

Maximum: Mean + 3σ

16.0

14.0

12.0

10.0

8.0

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

Max. 125°C

6.0

4.0

Max. 85°C

3.5

2.0

0.0

2.0

2.5

3.0

4.0

4.5

5.0

5.5

VDD (V)

DS41206B-page 112

PIC16F716

FIGURE 13-12:

BOR IPD vs. VDD OVER TEMPERATURE

160

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

140

120

100

80

Maximum

Typical

60

40

20

0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 13-13:

TYPICAL WDT IPD vs. VDD OVER TEMPERATURE

Typical

3.0

TTyyppicicaal:l:SSttaattisistticicaallMMeeaann@@2255°°CC

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

2.5

2.0

1.5

1.0

0.5

0.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41206B-page 113

PIC16F716

FIGURE 13-14:

MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE

Maximum

25.0

20.0

15.0

10.0

5.0

Max. 125°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

Max. 85°C

0.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 13-15:

WDT PERIOD vs. VDD OVER TEMPERATURE

30

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

28

26

24

22

20

18

16

14

12

10

Max. (125°C)

Max. (85°C)

Typical

Minimum

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41206B-page 114

PIC16F716

FIGURE 13-16:

WDT PERIOD vs. TEMPER_VA_dT_dU₌R₅E_VOVER VDD (5.0V)

30

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

28

26

24

22

20

18

16

14

12

10

Maximum

Typical

Minimum

-40°C

25°C

85°C

125°C

Temperature (°C)

DS41206B-page 115

PIC16F716

FIGURE 13-17:

VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)

(VDD = 3V, -40×C TO 125×C)

0.8

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

Max. 125°C

Max. 85°C

Typical 25°C

Min. -40°C

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

IOL (mA)

FIGURE 13-18:

VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)

0.45

Typical: Statistical Mean @25°C

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

Typical: Statistical Mean @25×C

Maximum: Mean (Worst-case Temp) + 3σ

Maximum: Mean(s-4+0×3C to 125×C)

(-40°C to 125°C)

Max. 125°C

Max. 85°C

Typ. 25°C

Min. -40°C

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

IOL (mA)

DS41206B-page 116

PIC16F716

FIGURE 13-19:

VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)

3.5

3.0

2.5

2.0

1.5

Max. -40°C

Typ. 25°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

1.0

0.5

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

-3.5

-4.0

IOH (mA)

FIGURE 13-20:

VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V)

5.5

5.0

4.5

4.0

Max. -40°C

Typ. 25°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

3.5

3.0

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

-3.5

-4.0

-4.5

-5.0

IOH (mA)

DS41206B-page 117

PIC16F716

FIGURE 13-21:

TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE

(TTL Input, -40×C TO 125×C)

1.7

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

1.5

1.3

1.1

0.9

0.7

0.5

Max. -40°C

Typ. 25°C

Min. 125°C

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 13-22:

SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE

(ST Input, -40×C TO 125×C)

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

VIH Max. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

VIH Min. -40°C

VIL Max. -40°C

VIL Min. 125°C

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41206B-page 118

PIC16F716

FIGURE 13-23:

T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz)

45.0

Typical: Statistical Mean @25°C

40.0

35.0

30.0

25.0

20.0

15.0

10.0

5.0

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

Maximum: Mean(-4+03×C to 125×C)

Max. 125°C

Max. 85°C

Typ. 25°C

3.5

0.0

2.0

2.5

3.0

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 13-24:

ADC CLOCK PERIOD vs. VDD OVER TEMPERATURE

8

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

125°C

85°C

6

4

2

0

25°C

-40°C

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41206B-page 119

PIC16F716

NOTES:

DS41206B-page 120

PIC16F716

14.0 PACKAGING INFORMATION

14.1 Package Marking Information

18-Lead PDIP

Example

XXXXXXXXXXXXXXXXX

YYWWNNN

PIC16F716-04/P

0610017

e

3

18-Lead SOIC (7.50 mm)

XXXXXXXXXXXX

PIC16F716-20

/SO

e

3

0610017

YYWWNNN

20-Lead SSOP

Example

PIC16F716

XXXXXXXXXXX

-20I/SS025

YYWWNNN

0610017

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

*

)

3

e

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

*

Standard PIC^®device marking consists of Microchip part number, year code, week code, and traceability

code. For PIC^®device marking beyond this, certain price adders apply. Please check with your Microchip

Sales Office. For QTP devices, any special marking adders are included in QTP price.

DS41206B-page 121

PIC16F716

14.2 Package Details

The following sections give the technical details of the packages.

18-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

NOTE 1

E1

2

3

1

D

E

A2

A

L

c

A1

b1

e

b

eB

Units

INCHES

NOM

18

Dimension Limits

MIN

MAX

Number of Pins

Pitch

N

e

.100 BSC

–

Top to Seating Plane

A

–

.210

.195

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.300

.240

.880

.115

.008

.045

.014

–

.130

–

.310

.250

.900

.130

.010

.060

.018

–

.325

.280

.920

.150

.014

.070

.022

.430

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

b1

b

Lower Lead Width

Overall Row Spacing §

eB

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-007B

DS41206B-page 122

PIC16F716

18-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

1

2

3

e

b

α

h

c

φ

A2

A

β

A1

L

L1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

18

1.27 BSC

Overall Height

A

–

2.65

–

Molded Package Thickness

Standoff §

A2

A1

E

2.05

0.10

–

0.30

Overall Width

10.30 BSC

Molded Package Width

Overall Length

E1

D

h

7.50 BSC

11.55 BSC

Chamfer (optional)

Foot Length

0.25

0.40

–

0.75

1.27

L

–

Footprint

L1

φ

1.40 REF

Foot Angle

0°

0.20

0.31

5°

–

8°

Lead Thickness

Lead Width

c

0.33

0.51

15°

b

Mold Draft Angle Top

Mold Draft Angle Bottom

α

β

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-051B

DS41206B-page 123

PIC16F716

20-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

1

2

e

b

c

A2

A

φ

A1

L1

L

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

20

0.65 BSC

Overall Height

Molded Package Thickness

Standoff

A

–

1.75

–

2.00

1.85

–

A2

A1

E

1.65

0.05

7.40

5.00

6.90

0.55

Overall Width

Molded Package Width

Overall Length

Foot Length

7.80

5.30

7.20

0.75

1.25 REF

–

8.20

5.60

7.50

0.95

E1

D

L

Footprint

L1

c

Lead Thickness

Foot Angle

0.09

0°

0.25

8°

φ

4°

Lead Width

b

0.22

–

0.38

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-072B

DS41206B-page 124

PIC16F716

APPENDIX A: REVISION HISTORY

APPENDIX B: CONVERSION

CONSIDERATIONS

Revision A (June 2003)

This is a Flash program memory version of the

PIC16C716 device. Refer to the migration document,

DS40059, for more information about differences

between the PIC16F716 and PIC16C716.

Original data sheet. However, the device described in

this data sheet are upgrades to PIC16C716.

Revision B (February 2007)

Updated with current formats and added Characterization

Data. Replaced Package Drawings.

DS41206B-page 125

PIC16F716

To convert code written for PIC16C5X to PIC16F716,

the user should take the following steps:

APPENDIX C: MIGRATION FROM

BASE-LINE TO

1. Remove any program memory page select

MID-RANGE DEVICES

operations (PA2, PA1, PA0 bits) for CALL, GOTO.

This section discusses how to migrate from a baseline

device (i.e., PIC16C5X) to a mid-range device (i.e.,

PIC16F716).

2. Revisit any computed jump operations (write to

PC or add to PC, etc.) to make sure page bits

are set properly under the new scheme.

The following are the list of modifications over the

PIC16C5X microcontroller family:

3. Eliminate any data memory page switching.

Redefine data variables to reallocate them.

4. Verify all writes to STATUS, OPTION, and FSR

registers since these have changed.

1. Instruction word length is increased to 14-bits.

This allows larger page sizes both in program

memory (2K now as opposed to 512 before) and

register file (128 bytes now versus 32 bytes

before).

5. Change Reset vector to 0000h

.

Note 1: This device has been designed to

perform to the parameters of its data

sheet. It has been tested to an electrical

specification designed to determine its

conformance with these parameters. Due

to process differences in the manufacture

of this device, this device may have differ-

ent performance characteristics than its

earlier version. These differences may

cause this device to perform differently in

your application than the earlier version of

this device.

2. A PC high latch register (PCLATH) is added to

handle program memory paging. Bits PA2, PA1,

PA0 are removed from STATUS register.

3. Data memory paging is redefined slightly.

STATUS register is modified.

4. Four new instructions have been added:

RETURN, RETFIE, ADDLW, and SUBLW.

Two instructions TRIS and OPTION are being

phased out although they are kept for

compatibility with PIC16C5X.

5. OPTION_REG and TRIS registers are made

addressable.

2: The user should verify that the device

oscillator starts and performs as

expected. Adjusting the loading capacitor

values and/or the Oscillator mode may be

required.

6. Interrupt capability is added. Interrupt vector is

at 0004h.

7. Stack size is increased to 8 deep.

8. Reset vector is changed to 0000h.

9. Reset of all registers is revisited. Five different

Reset (and wake-up) types are recognized.

Registers are reset differently.

10. Wake-up from Sleep through interrupt is added.

11. Two separate timers, Oscillator Start-up Timer

(OST) and Power-up Timer (PWRT) are

included for more reliable power-up. These

timers are invoked selectively to avoid

unnecessary delays on power-up and wake-up.

12. PORTB has weak pull-ups and interrupt-on-

change feature.

13. T0CKI pin is also a port pin (RA4) now.

14. FSR is made a full eight-bit register.

15. “In-circuit serial programming” is made possible.

The user can program PIC16F716 devices

using only five pins: VDD, VSS, MCLR/VPP, RB6

(clock) and RB7 (data in/out).

16. PCON STATUS register is added with a Power-

on Reset Status bit (POR).

17. Brown-out protection circuitry has been added.

Controlled by Configuration Word bits BOREN

and BORV. Brown-out Reset ensures the device

is placed in a Reset condition if VDD dips below

a fixed setpoint.

DS41206B-page 126

PIC16F716

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

DS41206B-page 127

PIC16F716

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

Technical Publications Manager

Reader Response

Total Pages Sent ________

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

PIC16F716

DS41206B

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS41206B-page 128

PIC16F716

INDEX

A

C

A/D

C Compilers

ADCON0 Register......................................................... 9

MPLAB C18................................................................ 88

MPLAB C30................................................................ 88

Capture Module. See Enhanced Capture/Compare/

PWM(ECCP)

ADCON1 Register....................................................... 10

ADRES Register ........................................................... 9

Converter Characteristics ......................................... 104

Timing Diagram......................................................... 105

Absolute Maximum Ratings ................................................ 91

ADC .................................................................................... 37

Acquisition Requirements ........................................... 43

Associated registers.................................................... 45

Block Diagram............................................................. 37

Calculating Acquisition Time....................................... 43

Channel Selection....................................................... 38

Configuration............................................................... 38

Configuring Interrupt ................................................... 40

Conversion Clock........................................................ 38

Conversion Procedure ................................................ 40

Internal Sampling Switch (RSS) IMPEDANCE ................ 43

Interrupts..................................................................... 39

Operation .................................................................... 40

Operation During Sleep .............................................. 40

Port Configuration....................................................... 38

Reference Voltage (VREF)........................................... 38

Source Impedance...................................................... 43

Special Event Trigger.................................................. 40

ADCON0 Register........................................................... 9, 41

ADCON1 Register......................................................... 10, 42

ADRES Register ................................................................... 9

Analog-to-Digital Converter. See ADC

Capture/Compare/PWM (CCP)

Associated registers w/ Capture................................. 49

Associated registers w/ Compare............................... 51

Associated registers w/ PWM..................................... 60

Capture Mode............................................................. 48

CCP1 Pin Configuration ............................................. 48

CCP1CON Register...................................................... 9

CCPR1H Register ........................................................ 9

CCPR1L Register......................................................... 9

Compare Mode........................................................... 50

CCP1 Pin Configuration ..................................... 50

Software Interrupt Mode............................... 48, 50

Special Event Trigger......................................... 50

Timer1 Mode Selection................................. 48, 50

Flag (CCP1IF Bit) ....................................................... 15

Prescaler .................................................................... 48

PWM Mode................................................................. 52

Duty Cycle .......................................................... 53

Effects of Reset.................................................. 55

Example PWM Frequencies and Resolutions,

20 MHZ...................................................... 54

Example PWM Frequencies and Resolutions,

8 MHz........................................................ 54

Operation in Sleep Mode.................................... 55

Setup for Operation ............................................ 55

System Clock Frequency Changes .................... 55

PWM Period ............................................................... 53

Setup for PWM Operation .......................................... 55

Timing Diagram ........................................................ 103

CCP1CON (Enhanced) Register ........................................ 47

Code Examples

Assembler

MPASM Assembler..................................................... 88

B

Banking, Data Memory ......................................................... 7

Block Diagrams

(CCP) Capture Mode Operation ................................. 48

ADC ............................................................................ 37

ADC Transfer Function ............................................... 44

Analog Input Model..................................................... 44

Auto-Shutdown ........................................................... 56

CCP PWM................................................................... 52

Compare ..................................................................... 50

Interrupt Sources ........................................................ 72

On-Chip Reset Circuit................................................. 66

PIC16F716.................................................................... 5

PORTA.................................................................. 19, 20

PORTB........................................................................ 21

RB1/T1OSO/T1CKI..................................................... 22

RB2/T1OSI.................................................................. 22

RB3/CCP1/P1A........................................................... 23

RB4............................................................................. 23

RB5............................................................................. 24

RB6/P1C..................................................................... 24

RB7/P1D..................................................................... 25

Timer1......................................................................... 29

Timer2......................................................................... 35

TMR0/WDT Prescaler................................................. 27

Watchdog Timer (WDT).............................................. 74

BOR. See Brown-out Reset

Assigning Prescaler to Timer0.................................... 28

Assigning Prescaler to WDT....................................... 28

Changing Between Capture Prescalers ..................... 48

How to Clear RAM Using Indirect Addressing............ 18

Initializing PORTA ...................................................... 19

Initializing PORTB ...................................................... 21

Code Protection............................................................ 61, 76

Compare Module. See Enhanced Capture/

Compare/PWM (ECCP)

CONFIG Register ............................................................... 62

Configuration Bits ............................................................... 61

Conversion Considerations............................................... 125

Customer Change Notification Service............................. 127

Customer Notification Service .......................................... 127

Customer Support............................................................. 127

D

Data Memory ........................................................................ 7

Bank Select (RP Bits)................................................... 7

General Purpose Registers .......................................... 8

Register File Map ......................................................... 8

Special Function Registers........................................... 9

DC Characteristics............................................ 93, 94, 95, 96

Development Support......................................................... 87

Direct Addressing ............................................................... 18

Brown-out Reset (BOR) .............................. 61, 64, 65, 69, 70

Timing Diagram......................................................... 101

DS41206B-page 129

PIC16F716

XORWF ...................................................................... 85

Summary Table .......................................................... 78

INT Interrupt (RB0/INT). See Interrupt Sources

E

ECCP. See Enhanced Capture/Compare/PWM

ECCPAS Register...............................................................57

Effects of Reset

PWM mode .................................................................55

Electrical Characteristics.....................................................91

Enhanced Capture/Compare/PWM.....................................47

Enhanced Capture/Compare/PWM (ECCP)

INTCON Register............................................................ 9, 13

Internal Sampling Switch (RSS) IMPEDANCE ........................ 43

Internet Address ............................................................... 127

Interrupt Sources .......................................................... 61, 72

Interrupt-on-Change (RB)........................................... 21

RB0/INT Pin, External................................................. 73

TMR0 Overflow........................................................... 73

Interrupts

ADC ............................................................................ 40

TMR1.......................................................................... 30

Interrupts, Context Saving During....................................... 73

Interrupts, Enable Bits

Enhanced PWM Mode

Auto-Restart........................................................58

Auto-shutdown....................................................56

Half-Bridge Application Examples.......................59

Programmable Dead Band Delay .......................59

Shoot-through Current ........................................59

Timer Resources.........................................................47

Errata ....................................................................................4

External Power-on Reset Circuit.........................................64

Global Interrupt Enable (GIE Bit)................................ 72

Interrupt-on-Change (RB) Enable (RBIE Bit).............. 73

Interrupts, Flag Bits

CCP1 Flag (CCP1IF Bit)............................................. 15

Interrupt-on-Change (RB) Flag (RBIF Bit) .................. 73

TMR0 Overflow Flag (T0IF Bit)................................... 73

F

Firmware Instructions..........................................................77

Fuses. See Configuration Bits

M

I

Master Clear (MCLR)

I/O Ports..............................................................................19

ID Locations ..................................................................61, 76

In-Circuit Serial Programming (ICSP) ........................... 61, 76

Indirect Addressing .............................................................18

FSR Register ...................................................... 8, 9, 18

INDF Register ...............................................................9

Instruction Format ...............................................................77

Instruction Set .....................................................................77

ADDLW .......................................................................79

ADDWF.......................................................................79

ANDLW .......................................................................79

ANDWF.......................................................................79

BCF.............................................................................79

BSF.............................................................................79

BTFSC ........................................................................79

BTFSS ........................................................................80

CALL ...........................................................................80

CLRF...........................................................................80

CLRW .........................................................................80

CLRWDT.....................................................................80

COMF .........................................................................80

DECF ..........................................................................80

DECFSZ......................................................................81

GOTO .........................................................................81

INCF............................................................................81

INCFSZ.......................................................................81

IORLW ........................................................................81

IORWF ........................................................................81

MOVF..........................................................................82

MOVLW ......................................................................82

MOVWF ......................................................................82

NOP ............................................................................82

RETFIE .......................................................................83

RETLW .......................................................................83

RETURN .....................................................................83

RLF .............................................................................84

RRF.............................................................................84

SLEEP ........................................................................84

SUBLW .......................................................................84

SUBWF.......................................................................85

SWAPF .......................................................................85

XORLW.......................................................................85

MCLR Reset, Normal Operation..................... 64, 69, 70

MCLR Reset, Sleep........................................ 64, 69, 70

Memory Organization

Data Memory ................................................................ 7

Program Memory.......................................................... 7

Microchip Internet Web Site.............................................. 127

Migration from Base-Line to Mid-Range Devices ............. 126

MPLAB ASM30 Assembler, Linker, Librarian..................... 88

MPLAB ICD 2 In-Circuit Debugger ..................................... 89

MPLAB ICE 2000 High-Performance Universal

In-Circuit Emulator...................................................... 89

MPLAB Integrated Development Environment Software.... 87

MPLAB PM3 Device Programmer ...................................... 89

MPLAB REAL ICE In-Circuit Emulator System .................. 89

MPLINK Object Linker/MPLIB Object Librarian.................. 88

O

OPCODE Field Descriptions............................................... 77

OPTION Register................................................................ 12

OPTION_REG Register................................................ 10, 12

Oscillator

Associated registers ................................................... 33

Oscillator Configuration ................................................ 61, 63

HS......................................................................... 63, 68

LP ......................................................................... 63, 68

RC .................................................................. 63, 64, 68

XT ......................................................................... 63, 68

Oscillator, WDT................................................................... 74

P

Packaging......................................................................... 121

PDIP Details ............................................................. 122

Paging, Program Memory............................................... 7, 17

PCON Register............................................................. 16, 68

PICSTART Plus Development Programmer....................... 90

PIE1 Register................................................................ 10, 14

PIR1 Register ................................................................. 9, 15

CCP1IF Bit.................................................................. 15

Pointer, FSR ....................................................................... 18

POR. See Power-on Reset

PORTA

Associated Registers.................................................. 20

DS41206B-page 130

PIC16F716

PORTA Register ..................................................... 9, 19

TRISA Register..................................................... 10, 19

PORTB

MCLR Reset. See MCLR

Power-on Reset (POR). See Power-on Reset (POR)

Reset Conditions for PCON Register ......................... 69

Reset Conditions for Program Counter ...................... 69

Reset Conditions for STATUS Register ..................... 69

Timing Diagram ........................................................ 101

WDT Reset. See Watchdog Timer (WDT)

Associated Registers .................................................. 25

PORTB Register ..................................................... 9, 21

RB Interrupt-on-Change.............................................. 73

RB Interrupt-on-Change Enable (RBIE Bit) ................ 73

RB0/INT Pin, External................................................. 73

RB7:RB4 Interrupt-on-Change Flag (RBIF Bit)........... 73

TRISB Register..................................................... 10, 21

Power-down Mode. See Sleep

Power-on Reset (POR)..................................... 61, 64, 69, 70

Oscillator Start-up Timer (OST) ............................ 61, 65

Power Control (PCON) Register................................. 68

Power-down (PD Bit) .................................................. 64

Power-on Reset Circuit, External................................ 64

Power-up Timer (PWRT) ...................................... 61, 65

Time-out (TO Bit) ........................................................ 64

Time-out Sequence..................................................... 68

Time-out Sequence on Power-up ............................... 71

Timing Diagram......................................................... 101

Prescaler

Revision History................................................................ 125

S

Shoot-through Current........................................................ 59

Sleep ...................................................................... 61, 64, 75

Software Simulator (MPLAB SIM) ...................................... 88

Special Event Trigger ......................................................... 40

Special Features of the CPU .............................................. 61

Special Function Registers................................................... 9

Speed, Operating ................................................................. 1

Stack................................................................................... 17

STATUS Register ............................................................... 11

STATUS Register ........................................................... 9, 73

PD Bit ......................................................................... 64

TO Bit ......................................................................... 64

Shared WDT/Timer0................................................... 28

Switching Prescaler Assignment................................. 28

Program Counter

T

T1CON Register ............................................................. 9, 32

T2CON Register ............................................................. 9, 36

Timer0 ................................................................................ 27

Associated Registers.................................................. 28

External Clock ............................................................ 28

Operation.............................................................. 27, 29

Overflow Flag (T0IF Bit) ............................................. 73

Overflow Interrupt....................................................... 73

T0CKI ......................................................................... 28

Timing Diagram ........................................................ 102

TMR0 Register ............................................................. 9

Timer1 ................................................................................ 29

Associated registers ................................................... 33

Asynchronous Counter Mode..................................... 30

Reading and Writing........................................... 30

Interrupt ...................................................................... 30

Modes of Operation.................................................... 29

Operation During Sleep.............................................. 30

Oscillator..................................................................... 30

Prescaler .................................................................... 30

T1CON Register........................................................... 9

Timing Diagram ........................................................ 102

TMR1H Register..................................................... 9, 29

TMR1L Register ..................................................... 9, 29

Timer2

PCL Register........................................................... 9, 17

PCLATH Register ............................................. 9, 17, 73

Reset Conditions......................................................... 69

Program Memory .................................................................. 7

Interrupt Vector ............................................................. 7

Paging..................................................................... 7, 17

Program Memory Map .................................................. 7

Reset Vector ................................................................. 7

Program Verification ........................................................... 76

Programming, Device Instructions ...................................... 77

PWM1CON Register........................................................... 60

R

RA<3

0>................................................................................ 19

RA4/T0CKI Pin.................................................................... 20

RAM. See Data Memory.

RB0 Pin............................................................................... 21

Reader Response............................................................. 128

Read-Modify-Write Operations ........................................... 77

Register File.......................................................................... 8

Register File Map.................................................................. 8

Registers

ADCON0 (ADC Control 0) .......................................... 41

ADCON1 (ADC Control 1) .......................................... 42

CCP1CON (Enhanced CCP1 Control)........................ 47

CONFIG (Configuration Word).................................... 62

ECCPAS (Enhanced CCP Auto-shutdown Control) ... 57

INTCON (Interrupt Control)......................................... 13

INTCON Register

Associated registers ................................................... 36

PR2 Register .............................................................. 10

T2CON Register........................................................... 9

TMR2 Register ............................................................. 9

Timers

Timer1

T1CON ............................................................... 32

Timer2

T2CON ............................................................... 36

Timing Diagrams

RBIF.................................................................... 21

OPTION_REG (OPTION) ........................................... 12

PCON (Power Control Register)................................. 16

PIE1 (Peripheral Interrupt Enable 1)........................... 14

PIR1 (Peripheral Interrupt Register 1) ........................ 15

PWM1CON (Enhanced PWM Control) ....................... 60

STATUS...................................................................... 11

T1CON........................................................................ 32

T2CON........................................................................ 36

Reset............................................................................. 61, 64

Brown-out Reset (BOR). See Brown-out Reset (BOR)

Half-Bridge PWM Output............................................ 59

PWM Auto-shutdown

Auto-restart Enabled........................................... 58

Firmware Restart................................................ 58

Time-out Sequence on Power-up............................... 71

Timer1 Incrementing Edge ......................................... 31

Wake-up from Sleep via Interrupt............................... 76

DS41206B-page 131

PIC16F716

Timing Diagrams and Specifications...................................98

A/D Conversion.........................................................105

Brown-out Reset (BOR)............................................101

Capture/Compare/PWM (CCP).................................103

CLKOUT and I/O.......................................................100

External Clock.............................................................98

Oscillator Start-up Timer (OST) ................................101

Power-up Timer (PWRT) ..........................................101

Reset.........................................................................101

Timer0 and Timer1....................................................102

Watchdog Timer (WDT)............................................101

V

VREF. SEE ADC Reference Voltage

W

W Register ..........................................................................73

Wake-up from Sleep ..................................................... 61, 75

Interrupts............................................................... 69, 70

MCLR Reset ...............................................................70

Timing Diagram...........................................................76

WDT Reset .................................................................70

Watchdog Timer (WDT) ................................................ 61, 74

Enable (WDTE Bit)......................................................74

Postscaler. See Postscaler, WDT

Programming Considerations .....................................74

RC Oscillator...............................................................74

Time-out Period ..........................................................74

Timing Diagram.........................................................101

WDT Reset, Normal Operation ....................... 64, 69, 70

WDT Reset, Sleep .......................................... 64, 69, 70

WWW Address..................................................................127

WWW, On-Line Support........................................................4

DS41206B-page 132

PIC16F716

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

XXX

Examples:

Temperature

Range

Package

Pattern

a)

b)

PIC16F716 - I/L 301 = Industrial temp., PDIP

package, QTP pattern #301.

PIC16F716 - E/SO = Extended temp., SOIC

package.

Device:

PIC16F716⁽¹⁾, PIC16F716T⁽²⁾

VDD range 2.0V to 5.5V

;

Temperature Range:

Package:

I

E

=

-40°C to +85°C (Industrial)

-40°C to +125°C (Extended)

SO

P

SS

=

SOIC

PDIP

SSOP

Pattern:

QTP, SQTP, Code or Special Requirements

(blank otherwise)

Note 1:

2:

F

LF

T

=

Standard Voltage Range

Wide Voltage Range

in tape and reel SOIC and SSOP

packages only.

DS41206B-page 133

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Habour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

12/08/06

DS41206B-page 134


型号：	PIC16F716-E/SSVAO
厂家：	MICROCHIP
描述：	RISC Microcontroller, 8-Bit, FLASH, 20MHz, CMOS, PDSO20 时钟微控制器光电二极管外围集成电路
文件：	总136页 (文件大小：2469K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC16F716-E/SSVAO [MICROCHIP]

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