PIC16F716 [MICROCHIP]
8-bit Flash-based Microcontroller with A/D Converter and Enhanced Capture/Compare/PWM; 8位闪存单片机与A / D转换器和增强型捕捉/比较/ PWM
| 型号： | PIC16F716 |
| 厂家： | 
MICROCHIP |
| 描述： | 8-bit Flash-based Microcontroller with A/D Converter and Enhanced Capture/Compare/PWM |
| 文件： | 总126页 (文件大小：1052K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC16F716
Data Sheet
8-bit Flash-based Microcontroller
with A/D Converter and
Enhanced Capture/Compare/PWM
2003 Microchip Technology Inc.
Preliminary
DS41206A
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and
PowerSmart are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Accuron, Application Maestro, dsPICDEM, dsPICDEM.net,
ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
DS41206A-page ii
Preliminary
2003 Microchip Technology Inc.
PIC16F716
8-bit Flash-based Microcontroller with A/D Controller and
Enhanced Capture/Compare PWM
Microcontroller Core Features:
Low-Power Features:
• High-performance RISC CPU
• Standby Current:
• Only 35 single-word instructions to learn
- 100 nA @ 2.0V, typical
• Operating Current:
- All single-cycle instructions except for
program branches which are two-cycle
- 14 µA @ 32 kHz, 2.0V, typical
- 120 µA @ 1 MHz, 2.0V, typical
• Watchdog Timer Circuit:
- 1 µA @ 2.0V, typical
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• Interrupt capability
(up to 7 internal/external interrupt sources)
• Timer1 Oscillator Current:
- 3.0 µA @ 32 kHz, 2.0V, typical
• 8-level deep hardware stack
• Direct, Indirect and Relative Addressing modes
Peripheral Features:
Special Microcontroller Features
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Power-on Reset (POR)
• Timer1: 16-bit timer/counter with prescaler
can be incremented during Sleep via external
crystal/clock
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Dual level Brown-out Reset circuitry
- 2.5 VBOR (Typical)
• Enhanced Capture, Compare, PWM module:
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM maximum resolution is 10-bit
- Enhanced PWM:
- 4.0 VBOR (Typical)
• Programmable code protection
• Power saving Sleep mode
• Selectable oscillator options
• Fully static design
- Single, Half-Bridge and Full-Bridge modes
- Digitally programmable dead-band delay
- Auto-shutdown/restart
• In-Circuit Serial Programming (ICSP™)
• 8-bit multi-channel Analog-to-Digital converter
• 13 I/O pins with individual direction control
• Programmable weak pull-ups on PORTB
CMOS Technology
• Wide operating voltage range:
- Industrial: 2.0V to 5.5V
- Extended: 3.0V to 5.5V
• High Sink/Source Current 25/25 mA
• Wide temperature range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
Memory
Device
8-bit A/D
(ch)
PWM
(outputs)
I/O
Timers 8/16
VDD Range
Flash
Data
PIC16F716
2048 x 14
128 x 8
13
4
2/1
1/2/4
2.0V - 5.5V
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 1
PIC16F716
Pin Diagrams
18-pin PDIP, SOIC
RA1/AN1
RA0/AN0
OSC1/CLKIN
OSC2/CLKOUT
VDD
RB7/P1D
RB6/P1C
RB5/P1B
RB4/ECCPAS0
RA2/AN2
RA3/AN3/VREF
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
RA4/T0CKI
MCLR/VPP
VSS
RB0/INT/ECCPAS2
RB1/T1OSO/T1CKI
RB2/T1OSI
RB3/CCP1/P1A
10
20-pin SSOP
RA1/AN1
RA0/AN0
OSC1/CLKIN
OSC2/CLKOUT
VDD
RA2/AN2
RA3/AN3/VREF
1
2
3
4
5
6
20
19
18
17
16
15
RA4/T0CKI
MCLR/VPP
VSS
VSS
VDD
RB7/P1D
RB6/P1C
RB0/INT/ECCPAS2
RB1/T1OSO/T1CKI
7
8
14
13
12
11
RB5/P1B
RB4/ECCPAS0
9
10
RB2/T1OSI
RB3/CCP1/P1A
DS41206A-page 2
Preliminary
2003 Microchip Technology Inc.
PIC16F716
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Memory Organization................................................................................................................................................................... 7
3.0 I/O Ports ..................................................................................................................................................................................... 19
4.0 Timer0 Module ........................................................................................................................................................................... 27
5.0 Timer1 Module ........................................................................................................................................................................... 29
6.0 Timer2 Module ........................................................................................................................................................................... 31
7.0 Enhanced Capture/Compare/PWM (ECCP) Module.................................................................................................................. 33
8.0 Analog-to-Digital Converter (A/D) Module.................................................................................................................................. 49
9.0 Special Features of the CPU...................................................................................................................................................... 55
10.0 Instruction Set Summary............................................................................................................................................................ 71
11.0 Development Support................................................................................................................................................................. 85
12.0 Electrical Characteristics............................................................................................................................................................ 91
13.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 107
14.0 Packaging Information.............................................................................................................................................................. 109
Appendix A: Revision History............................................................................................................................................................. 113
Appendix B: Conversion Considerations ........................................................................................................................................... 113
Appendix C: Migration from Base-line to MID-RANGE Devices ........................................................................................................ 114
On-Line Support................................................................................................................................................................................. 115
Systems Information and Upgrade Hot Line ...................................................................................................................................... 115
Reader Response.............................................................................................................................................................................. 116
Index .................................................................................................................................................................................................. 117
Product Identification System ............................................................................................................................................................ 123
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2003 Microchip Technology Inc.
Preliminary
DS41206A-page 3
PIC16F716
NOTES:
DS41206A-page 4
Preliminary
2003 Microchip Technology Inc.
PIC16F716
1.0
DEVICE OVERVIEW
This document contains device specific information for
the PIC16F716. Additional information may be found in
the PICmicro® Mid-Range Reference Manual,
(DS33023), which may be obtained from your local
Microchip Sales Representative or downloaded from
the Microchip web site (www.microchip.com). The
Reference Manual should be considered
complementary document to this data sheet, and is
highly recommended reading for better
a
a
understanding of the device architecture and operation
of the peripheral modules.
Figure 1-1 is the block diagram for the PIC16F716
device. The pinouts are listed in Table 1-1.
FIGURE 1-1:
PIC16F716 BLOCK DIAGRAM
13
8
PORTA
Data Bus
Program Counter
Flash
RA0/AN0
2K x 14
RA1/AN1
Program
Memory
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RAM
8 Level Stack
(13-bit)
128 x 8
File
Registers
Program
Bus
14
RAM Addr(1)
PORTB
9
Addr MUX
RB0/INT/ECCPAS2
RB1/T1OSO/T1CKI
RB2/T1OSI
Instruction reg
Indirect
Addr
7
Direct Addr
8
RB3/CCP1/P1A
FSR reg
RB4/ECCPAS0
RB5/P1B
RB6/P1C
RB7/P1D
Status reg
8
3
MUX
Power-up
Timer
Oscillator
Instruction
Decode and
Control
Start-up Timer
ALU
Power-on
Reset
8
OSC1/CLKIN
Timing
Generation
Watchdog
Timer
W reg
OSC2/CLKOUT
Brown-out
Reset
MCLR VDD, VSS
Timer1
Timer2
A/D
Timer0
Enhanced CCP
(ECCP)
Note 1:
Higher order bits are from the Status register.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 5
PIC16F716
TABLE 1-1:
Name
PIC16F716 PINOUT DESCRIPTION
Function
Input Type Output Type
Description
Master clear (Reset) input. This pin is an active low Reset to
the device.
MCLR/VPP
MCLR
ST
—
VPP
P
—
—
—
—
—
Programming voltage input
Oscillator crystal input
External clock source input
RC Oscillator mode
OSC1/CLKIN
OSC1
CLKIN
CLKIN
OSC2
XTAL
CMOS
ST
OSC2/CLKOUT
XTAL
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode.
CLKOUT
—
CMOS
In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the
frequency of OSC1, and denotes the instruction cycle rate.
RA0/AN0
RA0
AN0
TTL
AN
TTL
AN
TTL
AN
TTL
AN
AN
ST
CMOS
—
Bidirectional I/O
Analog Channel 0 input
RA1/AN1
RA1
CMOS
—
Bidirectional I/O
AN1
Analog Channel 1 input
RA2/AN2
RA2
CMOS
—
Bidirectional I/O
AN2
Analog Channel 2 input
RA3/AN3/VREF
RA3
CMOS
—
Bidirectional I/O
AN3
Analog Channel 3 input
VREF
RA4
—
A/D reference voltage input
Bidirectional I/O. Open drain when configured as output.
Timer0 external clock input
Bidirectional I/O. Programmable weak pull-up.
External Interrupt
RA4/T0CKI
OD
T0CKI
RB0
ST
—
RB0/INT/ECCPAS2
TTL
ST
CMOS
—
INT
ECCPAS2
RB1
ST
—
ECCP Auto-Shutdown pin
Bidirectional I/O. Programmable weak pull-up.
RB1/T1OSO/T1CKI
TTL
—
CMOS
XTAL
T1OSO
Timer1 oscillator output. Connects to crystal in Oscillator
mode.
T1CKI
RB2
ST
TTL
XTAL
TTL
ST
—
Timer1 external clock input
RB2/T1OSI
CMOS
—
Bidirectional I/O. Programmable weak pull-up.
Timer1 oscillator input. Connects to crystal in Oscillator mode.
Bidirectional I/O. Programmable weak pull-up.
Capture1 input, Compare1 output, PWM1 output.
PWM P1A output
T1OSI
RB3
RB3/CCP1/P1A
CMOS
CMOS
CMOS
CMOS
CCP1
P1A
—
RB4/ECCPAS0
RB5/P1B
RB4
TTL
Bidirectional I/O. Programmable weak pull-up. Interrupt-on-
change.
ECCPAS0
RB5
ST
—
ECCP Auto-Shutdown pin
TTL
CMOS
Bidirectional I/O. Programmable weak pull-up. Interrupt-on-
change.
P1B
RB6
—
CMOS
CMOS
PWM P1B output
RB6/P1C
TTL
Bidirectional I/O. Programmable weak pull-up. Interrupt-on-
change. ST input when used as ICSP programming clock.
P1C
RB7
—
CMOS
CMOS
PWM P1C output
RB7/P1D
TTL
Bidirectional I/O. Programmable weak pull-up. Interrupt-on-
change. ST input when used as ICSP programming data.
P1D
VSS
VDD
AN
—
P
CMOS
—
PWM P1D output
VSS
VDD
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
P
—
Legend:
I
= Input
O = Output
= Power
= Analog input or output
OD
ST
= Open drain
= Schmitt Trigger input with CMOS levels
TTL = TTL compatible input
XTAL = Crystal
P
CMOS = CMOS compatible input or output
DS41206A-page 6
Preliminary
2003 Microchip Technology Inc.
PIC16F716
2.2
Data Memory Organization
2.0
MEMORY ORGANIZATION
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP1
and RP0 of the Status register are the bank select bits.
There are two memory blocks in the PIC16F716
PICmicro® microcontroller device. Each block
(program memory and data memory) has its own bus
so that concurrent access can occur.
RP1:RP0(1)
Bank
Additional information on device memory may be found
in the PICmicro® Mid-Range Reference Manual,
(DS33023).
(status<6:5>)
00
01
10
11
0
1
2.1
Program Memory Organization
2(2)
3(2)
The PIC16F716 has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. The
PIC16F716 has 2K x 14 words of program memory.
Accessing a location above the physically implemented
address will cause a wrap-around.
Note 1: Maintain Status bit 6 clear to ensure
upward compatibility with future products.
2: Not implemented
The Reset vector is at 0000h and the interrupt vector is
at 0004h.
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK OF
PIC16F716
Registers
are
General
Purpose
Registers,
implemented as static RAM. All implemented banks
contain Special Function Registers. The upper 16
bytes of GPR space and some “high use” Special
Function Registers in Bank 0 are mirrored in Bank 1 for
code reduction and quicker access.
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 8
Reset Vector
0000h
Interrupt Vector
0004h
0005h
On-chip Program
Memory
07FFh
0800h
1FFFh
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 7
PIC16F716
2.2.1
GENERAL PURPOSE REGISTER
FILE
FIGURE 2-2:
REGISTER FILE MAP
The register file can be accessed either directly or
indirectly through the File Select Register FSR
(Section 2.5 “Indirect Addressing, INDF and FSR
Registers”).
File
Address
File
Address
80h
OPTION_REG 81h
(1)
(1)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
INDF
INDF
TMR0
PCL
PCL
STATUS
FSR
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
STATUS
FSR
PORTA
PORTB
TRISA
TRISB
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
TMR1L
TMR1H
T1CON
TMR2
PCON
T2CON
PR2
CCPR1L
CCPR1H
17h CCP1CON
18h PWM1CON
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
ECCPAS
ADRES
ADCON0
ADCON1
General
Purpose
Registers
General
Purpose
Registers
32 Bytes
BFh
80 Bytes
C0h
EFh
6Fh
70h
7Fh
16 Bytes
Bank 0
Accesses
70-7Fh
F0h
FFh
Bank 1
Unimplemented data memory locations,
read as '0'.
Note 1: Not a physical register.
DS41206A-page 8
Preliminary
2003 Microchip Technology Inc.
PIC16F716
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
give in Table 2-1.
The Special Function Registers can be classified into
two sets; core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in that
peripheral feature section.
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY BANK 0
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
00h
01h
02h
INDF(1)
TMR0
PCL(1)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000
xxxx xxxx
0000 0000
18
27
17
Program Counter's (PC) Least Significant Byte
03h
STATUS(1)
FSR(1)
PORTA(5,6)
PORTB(5,6)
—
PCLATH(1,2)
INTCON(1)
PIR1
IRP(4)
RP1(4)
RP0
TO
PD
Z
DC
C
0001 1xxx
xxxx xxxx
--xx 0000
xxxx xxxx
—
11
18
19
21
04h
Indirect data memory address pointer
(7)
05h
—
—
—
PORTA Data Latch when written: PORTA pins when read
06h
PORTB Data Latch when written: PORTB pins when read
Unimplemented
07h-09h
0Ah
—
—
—
T0IE
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
0000 000x
-0-- 0000
—
17
13
15
0Bh
GIE
PEIE
ADIF
INTE
—
RBIE
—
T0IF
INTF
RBIF
0Ch
0Dh
0Eh
—
CCP1IF
TMR2IF
TMR1IF
—
Unimplemented
TMR1L
TMR1H
T1CON
TMR2
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx
xxxx xxxx
29
29
29
31
31
0Fh
10h
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
Timer2 module’s register
TMR1CS TMR1ON --00 0000
11h
0000 0000
12h
T2CON
—
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000
13h-14h
15h
Unimplemented
—
CCPR1L
CCPR1H
CCP1CON
PWM1CON
ECCPAS
—
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
00-0 0000
—
34
34
33
46
46
16h
17h
P1M1
P1M0
PDC6
DC1B1
DC1B0
PDC4
CCP1M3
PDC3
CCP1M2
PDC2
CCP1M1
PDC1
CCP1M0
PDC0
18h
PRSEN
PDC5
(8)
—
19h
ECCPASE ECCPAS2
Unimplemented
ECCPAS0 PSSAC1
PSSAC0
PSSBD1
PSSBD0
1Ah-1Dh
1Eh
ADRES
A/D Result Register
xxxx xxxx
49
49
(7)
1Fh
ADCON0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
0000 0000
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, Shaded locations are unimplemented,
read as ‘0’.
Note 1:
2:
These registers can be addressed from either bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are
transferred to the upper byte of the program counter.
3:
4:
5:
6:
7:
8:
Other (non Power-up) Resets include: external Reset through MCLR and the Watchdog Timer Reset.
The IRP and RP1 bits are reserved. Always maintain these bits clear.
On any device Reset, these pins are configured as inputs.
This is the value that will be in the port output latch.
Reserved bits, do not use.
ECCPAS1 bit is not used on PIC16F716.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 9
PIC16F716
TABLE 2-2:
SPECIAL FUNCTION REGISTER SUMMARY BANK 1
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
80h
INDF(1)
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
18
81h
82h
OPTION_REG
PCL(1)
RBPU
Program Counter's (PC) Least Significant Byte
IRP(4) RP1(4)
RP0 TO
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
0000 0000
12
17
83h
STATUS(1)
FSR(1)
TRISA
TRISB
—
PCLATH(1,2)
INTCON(1)
PIE1
PD
Z
DC
C
0001 1xxx
xxxx xxxx
--11 1111
1111 1111
—
11
18
19
21
84h
Indirect data memory address pointer
(7)
85h
—
—
—
PORTA Data Direction Register
86h
PORTB Data Direction Register
Unimplemented
87h-89h
8Ah
8Bh
8Ch
8Dh
—
GIE
—
—
—
T0IE
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
0000 000x
-0-- -000
—
17
13
14
PEIE
ADIE
INTE
—
RBIE
—
T0IF
INTF
RBIF
CCP1IE
TMR2IE
TMR1IE
—
Unimplemented
8Eh
PCON
—
—
—
—
—
—
—
POR
BOR
---- --qq
—
16
32, 36
50
8Fh-91h
92h
Unimplemented
Timer2 Period Register
Unimplemented
PR2
1111 1111
—
93h-9Eh
9Fh
—
ADCON1
—
—
—
—
—
PCFG2
PCFG1
PCFG0
---- -000
Legend:
x= unknown, u= unchanged, q= value depends on condition, -= unimplemented, read as '0', Shaded locations are unimplemented,
read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are
transferred to the upper byte of the program counter.
3: Other (non Power-up) Resets include: external Reset through MCLR and the Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved. Always maintain these bits clear.
5: On any device Reset, these pins are configured as inputs.
6: This is the value that will be in the port output latch.
7: Reserved bits, do not use.
DS41206A-page 10
Preliminary
2003 Microchip Technology Inc.
PIC16F716
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
Status register because these instructions do not affect
the Z, C or DC bits from the Status register. For other
instructions, not affecting any Status bits, see the
“Instruction Set Summary.”
2.2.2.1
Status Register
The Status register, shown in Register 2-1, contains the
arithmetic status of the ALU, the Reset status and the
bank select bits for data memory.
The Status register can be the destination for any
instruction, as with any other register. If the Status
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
Status register as destination may be different than
intended.
Note 1: The PIC16F716 does not use bits IRP
and RP1 (STATUS<7:6>). Maintain these
bits clear to ensure upward compatibility
with future products.
2: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUSwill clear the upper-three
bits and set the Z bit. This leaves the Status register as
000u u1uu(where u= unchanged).
REGISTER 2-1:
STATUS REGISTER (ADDRESS: 03h, 83h)
R/W-0
IRP(1)
R/W-0
RP1(1)
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 7
bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing)(1)
1= Bank 2, 3 (100h – 1FFh)
0= Bank 0, 1 (00h – FFh)
bit 6-5
RP1(1):RP0: Register Bank Select bits (used for direct addressing)
01= Bank 1 (80h – FFh)
00= Bank 0 (00h – 7Fh)
Each bank is 128 bytes
bit 4
bit 3
bit 2
bit 1
TO: Time-out bit
1= After power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions) (for borrow the polarity
is reversed)
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(2)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: Reserved, maintain clear
2: For borrow the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 11
PIC16F716
2.2.2.2
OPTION_REG Register
Note:
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
The OPTION_REG register is a readable and writable
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single
assignable register known also as the prescaler), the
External INT Interrupt, TMR0 and the weak pull-ups on
PORTB.
REGISTER 2-2:
OPTION_REG REGISTER (ADDRESS: 81h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
RBPU
INTEDG
T0CS
T0SE
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
RBPU: PORTB Weak Pull-up Enable bit
1= PORTB weak pull-ups are disabled
0= PORTB weak pull-ups are determined by alternate function or TRISBn bit value
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
PS2:PS0: Prescaler Rate Select bits
Bit Value
000
TMR0 Rate
1 : 2
WDT Rate
1 : 1
001
1 : 4
1 : 2
010
1 : 8
1 : 4
011
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 8
100
1 : 16
1 : 32
1 : 64
1 : 128
101
110
111
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
DS41206A-page 12
Preliminary
2003 Microchip Technology Inc.
PIC16F716
2.2.2.3
INTCON Register
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
The INTCON Register is a readable and writable
register which contains various enable and flag bits for
the TMR0 register overflow, RB Port change and
external RB0/INT pin interrupts.
REGISTER 2-3:
INTCON REGISTER (ADDRESS: 0Bh, 8Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
GIE: Global Interrupt Enable bit
1= Enables all un-masked interrupts
0= Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1= Enables all un-masked peripheral interrupts
0= Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1= Enables the RB0/INT external interrupt
0= Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1= The RB0/INT external interrupt occurred (must be cleared in software)
0= The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 13
PIC16F716
2.2.2.4
PIE1 Register
Note:
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 2-4:
PIE1 REGISTER (ADDRESS: 8Ch)
U-0
—
R/W-0
ADIE
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CCP1IE TMR2IE TMR1IE
bit 0
bit 7
bit 7
bit 6
Unimplemented: Read as ‘0’
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
bit 5-3
bit 2
Unimplemented: Read as ‘0’
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
bit 1
bit 0
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41206A-page 14
Preliminary
2003 Microchip Technology Inc.
PIC16F716
2.2.2.5
PIR1 Register
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
This register contains the individual flag bits for the
peripheral interrupts.
REGISTER 2-5:
PIR1 REGISTER (ADDRESS: 0Ch)
U-0
—
R/W-0
ADIF
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CCP1IF TMR2IF TMR1IF
bit 0
bit 7
bit 7
bit 6
Unimplemented: Read as ‘0’
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared in software)
0= The A/D conversion is not complete
bit 5-3
bit 2
Unimplemented: Read as ‘0’
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare Mode
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 15
PIC16F716
2.2.2.6
PCON Register
Note:
If the BOREN configuration bit is set, BOR
is ‘1’ on Power-on Reset and reset to ‘0’
when a Brown-out condition occurs. BOR
must then be set by the user and checked
on subsequent resets to see if it is clear,
indicating that another Brown-out has
occurred.
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR) to an external MCLR Reset or WDT Reset.
These devices contain an additional bit to differentiate
a Brown-out Reset condition from a Power-on Reset
condition.
If the BOREN configuration bit is clear,
BOR is unknown on Power-on Reset.
REGISTER 2-6:
PCON REGISTER (ADDRESS: 8Eh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
POR
R/W-q
BOR
bit 7
bit 0
bit 7-2
bit 1
Unimplemented: Read as ‘0’
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
q = Depends on condition
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41206A-page 16
Preliminary
2003 Microchip Technology Inc.
PIC16F716
FIGURE 2-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
2.3
PCL and PCLATH
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register. This
register is readable and writable. The high byte is
called the PCH register. This register contains the
PC<12:8> bits and is not directly readable or writable.
All updates to the PCH register go through the PCLATH
register.
PCH
12
PCL
8 7
0
Instruction with
PCL as
Destination
8
PCLATH<4:0>
ALU
5
PCLATH
PCL
PCH
12 1110
0
8 7
2.3.1
MODIFYING PCL
GOTO, CALL
11
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<12:8> bits (PCH) to be replaced by the
contents of PCLATH register. This allows the entire
contents of the program counter to be changed by first
writing the desired upper 5 bits to the PCLATH register.
When the lower 8 bits are then written to the PCL
register, all 13 bits of the program counter will change
to the values contained in the PCLATH register and
those being written to the PCL register.
PCLATH<4:3>
PCLATH
Opcode <10:0>
2
2.4
Stack
The stack allows a combination of up to 8 program calls
and interrupts to occur. The stack contains the return
address from this branch in program execution.
Care should be exercised when modifying the PCL
register to jump into a look-up table or program branch
table (computed GOTO). With PCLATH set to the table
start address, if the table is greater than 255
instructions or if the lower 8 bits of the memory address
rolls over from 0xFF to 0x00 in the middle of the table,
then PCLATH must be incremented for each address
rollover that occurs between the table beginning and
the target address.
Mid-range devices have an 8-level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space, and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLWor a RETFIE instruction execution.
PCLATH is not modified when the stack is PUSHed or
POPed.
2.3.2
PROGRAM MEMORY PAGING
After the stack has been PUSHed 8 times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
The CALL and GOTO instructions provide 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALLor GOTOinstruction,
the upper bit of the address is provided by
PCLATH<3>. When doing a CALLor GOTOinstruction,
the user must ensure that the page select bit is
programmed so that the desired program memory
page is addressed. If a RETURNfrom a CALLinstruction
(or interrupt) is executed, the entire 13-bit PC is pushed
onto the stack. Therefore, manipulation of the
PCLATH<3> bit is not required for the RETURN
instructions (which POPs the address from the stack).
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 17
PIC16F716
EXAMPLE 2-2:
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
2.5
Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
INDF actually addresses the register whose address is
contained in the FSR register (FSR is a pointer). This is
indirect addressing.
MOVLW 0x20
MOVWF FSR
CLRF INDF
INCF FSR
;initialize pointer
;to RAM
;clear RAM & FSR
;inc pointer
NEXT
BTFSS FSR,4 ;all done?
GOTO
:
NEXT
;no, clear next
;yes, continue
EXAMPLE 2-1:
INDIRECT ADDRESSING
CONTINUE
• Register file 05 contains the value 10h
• Register file 06 contains the value 0Ah
• Load the value 05 into the FSR register
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-4. However, IRP is not used in the
PIC16F716.
• A read of the INDF register will return the value of
10h
• Increment the value of the FSR register by one
(FSR = 06)
• A read of the INDR register now will return the
value of 0Ah.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although Status bits may be affected).
A simple program to clear RAM locations 20h – 2Fh
using indirect addressing is shown in Example 2-2.
FIGURE 2-4:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
from opcode
Indirect Addressing
RP1:
7
RP0
6
0
0
IRP
FSR register
(2)
(2)
bank select
location select
bank select
location select
00
01
80h
10
100h
11
00h
180h
(3)
(3)
Data
Memory
(1)
7Fh
Bank 0
Note 1: For register file map detail see Figure 2-2.
FFh
17Fh
Bank 2
1FFh
Bank 3
Bank 1
2: Maintain clear for upward compatibility with future products.
3: Not implemented.
DS41206A-page 18
Preliminary
2003 Microchip Technology Inc.
PIC16F716
EXAMPLE 3-1:
INITIALIZING PORTA
3.0
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
BCF
CLRF
STATUS, RP0
PORTA
;
;Initialize PORTA by
;clearing output
;data latches
BSF
MOVLW 0xEF
STATUS, RP0 ;Select Bank 1
Additional information on I/O ports may be found in the
PICmicro® Mid-Range Reference Manual, (DS33023).
;Value used to
;initialize data
;direction
MOVWF TRISA
;Set RA<3:0> as inputs
;RA<4> as outputs
3.1
PORTA and the TRISA Register
PORTA is
a 5-bit wide bidirectional port. The
BCF
STATUS, RP0 ;Return to Bank 0
corresponding data direction register is TRISA. Setting
a TRISA bit (= 1) will make the corresponding PORTA
pin an input (i.e., put the corresponding output driver in
a High-impedance mode). Clearing a TRISA bit (= 0)
will make the corresponding PORTA pin an output (i.e.,
put the contents of the output latch on the selected pin).
FIGURE 3-1:
BLOCK DIAGRAM OF
RA3:RA0
DATA
BUS
D
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
Q
VDD
VDD
WR
PORT
CK
Q
P
Data Latch
I/O pin
N
D
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other RA port pins have TTL input levels and full
CMOS output drivers.
Q
WR
TRIS
VSS
VSS
CK
Q
Analog
Input
TRIS Latch
mode
PORTA pins, RA3:0, are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register 1).
RD TRIS
Q
TTL
Input
Buffer
Note:
On a Power-on Reset, these pins are
configured as analog inputs and read as
‘0’.
D
EN
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
RD PORT
To A/D Converter
Note:
Setting RA3:0 to output while in Analog
mode will force pins to output contents of
data latch.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 19
PIC16F716
FIGURE 3-2:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
Data Latch
DATA
BUS
Q
D
RA4/T0CKI
WR
PORT
CK
Q
N
TRIS Latch
VSS
Q
D
VSS
WR
TRIS
Schmitt
Trigger
Input
CK
Q
Buffer
RD TRIS
Q
D
EN
RD PORT
TMR0 Clock Input
TABLE 3-1:
Name
PORTA FUNCTIONS
Bit#
Buffer
Function
RA0/AN0
bit 0
bit 1
bit 2
bit 3
bit 4
TTL
TTL
TTL
TTL
ST
Input/output or analog input
Input/output or analog input
Input/output or analog input
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
Input/output or analog input or VREF
Input/output or external clock input for Timer0
Output is open drain type
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 3-2:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
POR,
Value on all
other
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
BOR
Resets
(1)
05h
85h
9Fh
PORTA
TRISA
—
—
—
—
—
—
—
—
RA4 RA3
RA2
RA1
RA0
--xx 0000
--11 1111
--uu uuuu
--11 1111
---- -000
(1)
PORTA Data Direction Register
ADCON1
—
—
—
PCFG2 PCFG1 PCFG0 ---- -000
Legend: x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by
PORTA.
Note 1: Reserved bits, do not use.
DS41206A-page 20
Preliminary
2003 Microchip Technology Inc.
PIC16F716
PORTB pins RB7:RB0 are multiplexed with several
peripheral functions (Table 3-3).
3.2
PORTB and the TRISB Register
PORTB is an 8-bit wide bidirectional port. The
corresponding data direction register is TRISB. Setting
a TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a High-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTB pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (such as BSF, BCF, XORWF) with
TRISB as the destination should be avoided. The user
should refer to the corresponding peripheral section for
the correct TRIS bit settings.
EXAMPLE 3-2:
INITIALIZING PORTB
BCF
STATUS, RP0
;select Bank 0
CLRF
PORTB
;Initialize PORTB by
;clearing output
;data latches
;Select Bank 1
;Value used to
;initialize data
;direction
;Set RB<3:0> as inputs
;RB<5:4> as outputs
;RB<7:6> as inputs
Four of PORTB’s pins, RB7:RB4, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins, RB7:RB4, are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
BSF
MOVLW
STATUS, RP0
0xCF
MOVWF
TRISB
This interrupt can wake the device from Sleep. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (OPTION_REG<7>).
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
1. Perform a read of PORTB to end the mismatch
condition.
2. Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
FIGURE 3-3:
BLOCK DIAGRAM OF
RB0/INT/ECCPAS2 PIN
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
VDD
VDD
RBPU(1)
weak
pull-up
P
Data Latch
DATA
BUS
D
Q
RB0/
INT/
ECCPAS2
WR
PORT
CK
TRIS Latch
D
Q
VSS
WR
CK
TRIS
TTL
Input
Buffer
RD TRIS
Q
D
EN
RD PORT
Schmitt Trigger
Buffer
RB0/INT
RD PORT
ECCPAS2: ECCP Auto-shutdown input
Note 1:
To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 21
PIC16F716
FIGURE 3-4:
BLOCK DIAGRAM OF RB1/T1OSO/T1CKI PIN
VDD
weak
RBPU(1)
T1OSCEN
P
pull-up
VDD
Data Latch
DATA BUS
RB1/T1OSO/T1CKI
D
Q
Q
WR PORTB
CK
TRIS Latch
VSS
D
Q
Q
WR TRISB
CK
RD TRISB
T1OSCEN
TTL Buffer
Q
D
EN
RD PORTB
T1OSI (From RB2)
TMR1 oscillator
To Timer1 clock input
ST Buffer
Note 1:
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
FIGURE 3-5:
BLOCK DIAGRAM OF RB2/T1OSI PIN
VDD
RBPU(1)
T1OSCEN
weak
P
VDD
pull-up
Data Latch
DATA BUS
D
Q
Q
RB2/T1OSI
WR PORTB
CK
TRIS Latch
D
Q
VSS
WR TRISB
Q
CK
RD TRIS
T1OSCEN
TTL Buffer
Q
D
EN
RD PORTB
TMR1
Oscillator
T1OSO (To RB1)
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
DS41206A-page 22
Preliminary
2003 Microchip Technology Inc.
PIC16F716
FIGURE 3-6:
BLOCK DIAGRAM OF RB3/CCP1/P1A PIN
VDD
weak
RBPU(1)
[PWMA(P1A) / CCP1 Compare] Output Enable
VDD
P
pull-up
[PWMA(P1A) / CCP1 Compare] Output
PWMA(P1A) Auto-shutdown tri-state
1
0
RB3/CCP1/P1A
VSS
Data Latch
DATA BUS
D
Q
WR PORTB
Q
CK
TRIS Latch
D
Q
WR TRISB
RD TRIS
CK
Q
TTL Buffer
Q
D
EN
RD PORTB
Schmitt Trigger Buffer
CCP - Capture input
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
FIGURE 3-7:
BLOCK DIAGRAM OF RB4/ECCPAS0 PIN
VDD
RBPU(1)
VDD
weak
P
pull-up
Data Latch
DATA BUS
RB4/ECCPAS0
D
Q
WR PORTB
CK
TRIS Latch
D
Q
VSS
WR TRISB
TTL
Buffer
CK
ST
Buffer
RD TRIS
Latch
Q
Q
D
EN
Q1
RD PORT
Set RBIF
D
From other
RB7:RB4 pins
Note 1: To enable weak pull-ups, set
the appropriate TRIS bit(s)
and clear the RBPU bit
RD PORT
Q3
EN
(OPTION_REG<7>).
ECCPAS0: ECCP Auto-Shutdown input
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 23
PIC16F716
FIGURE 3-8:
BLOCK DIAGRAM OF RB5/P1B PIN
VDD
weak
RBPU(1)
PWMB(P1B) Enable
VDD
P
pull-up
PWMB(P1B) Data out
PWMB(P1B) Auto-shutdown tri-state
1
0
RB5/P1B
Data Latch
DATA BUS
D
Q
WR PORTB
WR TRISB
CK
TRIS Latch
VSS
D
Q
TTL
Buffer
Q
CK
RD TRISB
Latch
Q
D
EN
Q1
RD PORTB
Set RBIF
Q
D
From other
RB7:RB4 pins
RD PORTB
Q3
EN
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
FIGURE 3-9:
BLOCK DIAGRAM OF RB6/P1C PIN
VDD
RBPU(1)
weak
PWMC(P1C) Enable
VDD
P
pull-up
PWMC(P1C) Data out
PWMC(P1C) Auto-shutdown tri-state
1
0
RB6/P1C
Data Latch
DATA BUS
D
Q
WR PORTB
WR TRISB
CK
TRIS Latch
VSS
D
Q
TTL
Buffer
Q
CK
ST
Buffer
RD TRISB
Latch
Q
D
EN
RD PORTB
Q1
Set RBIF
Q
D
From other
RB7:RB4 pins
RD PORTB
Q3
EN
ICSPC - In circuit serial programming clock input
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
DS41206A-page 24
Preliminary
2003 Microchip Technology Inc.
PIC16F716
FIGURE 3-10:
BLOCK DIAGRAM OF RB7/P1D PIN
VDD
RBPU(1)
weak
PWMD(P1D) Enable
VDD
P
pull-up
PWMD(P1D) Data out
PWMD(P1D) Auto-shutdown tri-state
1
0
RB7/P1D
Data Latch
DATA BUS
D
Q
WR PORTB
WR TRISB
CK
TRIS Latch
VSS
D
Q
TTL
Buffer
Q
ST
Buffer
CK
RD TRISB
Latch
Q
D
EN
Q1
RD PORTB
Set RBIF
Q
D
From other
Note 1: To enable weak pull-ups,
set the appropriate TRIS
RB7:RB4 pins
RD PORTB
Q3
EN
bit(s) and clear the RBPU
bit (OPTION_REG<7>).
ICSPD - In circuit serial programming data input
TABLE 3-3:
Name
PORTB FUNCTIONS
Bit#
Buffer
Function
RB0/INT/
ECCPAS2
bit 0
TTL/ST(1)
Input/output pin or external interrupt input. Internal software
programmable weak pull-up. ECCP auto-shutdown input.
RB1/T1OS0/
T1CKI
bit 1
TTL/ST(1)
Input/output pin or Timer1 oscillator output, or Timer1 clock input. Internal
software programmable weak pull-up. See Section 5.0 “Timer1 Module”
for detailed operation.
RB2/T1OSI
bit 2
bit 3
TTL/XTAL
TTL/ST(1)
Input/output pin or Timer1 oscillator input. Internal software programmable
weak pull-up. See Section 5.0 “Timer1 Module” for detailed operation.
RB3/CCP1/
P1A
Input/output pin or Capture1 input, or Compare1 output, or PWM A output.
Internal software programmable weak pull-up. See CCP1 section for
detailed operation.
RB4/
ECCPAS0
bit 4
bit 5
bit 6
bit 7
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. ECCP auto-shutdown input.
RB5/P1B
RB6/P1C
RB7/P1D
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. PWM B output.
TTL/ST(2)
TTL/ST(2)
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. PWM C output. Serial programming clock.
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. PWM D output. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input, XTAL = Crystal Oscillator input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt or peripheral input.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 25
PIC16F716
TABLE 3-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on:
POR,
BOR
Value on all
other Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
06h
86h
81h
PORTB
TRISB
OPTION_REG RBPU
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
PS0
xxxx xxxx
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PORTB Data Direction Register
INTEDG T0CS T0SE PSA
PS2
PS1
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.
DS41206A-page 26
Preliminary
2003 Microchip Technology Inc.
PIC16F716
4.2
Prescaler
4.0
TIMER0 MODULE
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer, respectively (Figure 4-2). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet.
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• Internal or external clock select
• Edge select for external clock
• 8-bit software programmable prescaler
• Interrupt on overflow from FFh to 00h
Note:
There is only one prescaler available,
which is mutually exclusively shared
between the Timer0 module and Watch-
dog Timer. Thus, a prescaler assignment
for the Timer0 module means that there is
no prescaler for the Watchdog Timer and
vice-versa.
Figure 4-1 is a simplified block diagram of the Timer0
module.
Additional information on timer modules is available in
the PICmicro® Mid-Range Reference Manual,
(DS33023).
The prescaler is not readable or writable.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
4.1
Timer0 Operation
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0
module will increment every instruction cycle (without
prescaler). If the TMR0 register is written, the
increment is inhibited for the following two instruction
cycles. The user can work around this by writing an
adjusted value to the TMR0 register.
Setting bit PSA will assign the prescaler to the
Watchdog Timer (WDT). When the prescaler is
assigned to the WDT, prescale values of 1:1, 1:2, ...,
1:128 are selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment on every rising or falling edge of pin RA4/
T0CKI. The incrementing edge is determined by the
BSF
1,x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the WDT.
Timer0
Source
Edge
Select
bit
T0SE
Note:
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
(OPTION_REG<4>). Clearing bit T0SE selects the
rising edge. Restrictions on the external clock input are
discussed below.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
Additional information on external clock requirements
is available in the PICmicro® Mid-Range Reference
Manual, (DS33023).
FIGURE 4-1:
TIMER0 BLOCK DIAGRAM
Data Bus
8
FOSC/4
0
1
PSOUT
1
0
Sync with
Internal
clock
TMR0
Programmable
Prescaler(2)
RA4/T0CKI
pin
PSOUT
T0SE(1)
(2 cycle delay)
Set interrupt
flag bit T0IF
on overflow
3
T0CS(1)
PSA(1)
PS2, PS1, PS0(1)
Note 1:
2:
T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 27
PIC16F716
4.2.1
SWITCHING PRESCALER
ASSIGNMENT
4.3
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h. This overflow sets
bit T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt
service routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
Sleep since the timer is shut off during Sleep.
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution).
Note:
To avoid an unintended device Reset, a
specific instruction sequence (shown in
the PICmicro® Mid-Range Reference
Manual, DS33023) must be executed
when changing the prescaler assignment
from Timer0 to the WDT. This sequence
must be followed even if the WDT is
disabled.
FIGURE 4-2:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
8
CLKOUT (=FOSC/4)
M
U
X
1
0
0
1
M
U
X
RA4/T0CKI
pin
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
Set flag bit T0IF
on Overflow
PSA
0
1
8-bit Prescaler
M
U
X
Watchdog
Timer
8
8 - to - 1MUX
PS2:PS0
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
Time-out
Note:
T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
TABLE 4-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on:
POR,
BOR
Value on all
other Resets
Address
Name
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h
TMR0
INTCON
Timer0 module’s register
GIE PEIE T0IE INTE
xxxx xxxx uuuu uuuu
RBIF 0000 000x 0000 000u
0Bh,8Bh
RBIE
PSA
T0IF
PS2
INTF
PS1
81h
85h
OPTION_REG RBPU INTEDG T0CS T0SE
PS0
1111 1111 1111 1111
--11 1111 --11 1111
(1)
TRISA
—
—
—
Bit 4 PORTA Data Direction Register
Legend: x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
Note 1: Reserved bits, do not use.
DS41206A-page 28
Preliminary
2003 Microchip Technology Inc.
PIC16F716
5.1
Timer1 Operation
5.0
TIMER1 MODULE
Timer1 can operate in one of these modes:
The Timer1 module timer/counter has the following
features:
• As a timer
• 16-bit timer/counter
(Two 8-bit registers; TMR1H and TMR1L)
• As a synchronous counter
• As an asynchronous counter
• Readable and writable (Both registers)
• Internal or external clock select
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
• Interrupt on overflow from FFFFh to 0000h
• Reset from ECCP module trigger
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
Timer1 has a control register, shown in Register 5-1.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RB2/T1OSI and RB1/T1OSO/T1CKI pins
become inputs. That is, the TRISB<2:1> value is
ignored.
Figure 5-1 is a simplified block diagram of the Timer1
module.
Timer1 also has an internal “Reset input”. This Reset
can be generated by the ECCP module
(Section 7.0 “Enhanced Capture/Compare/PWM
(ECCP) Module”).
Additional information on timer modules is available in
the PICmicro® Mid-Range Reference Manual,
(DS33023).
REGISTER 5-1:
T1CON: TIMER1 CONTROL REGISTER (ADDRESS: 10h)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 0
bit 7
bit 7-6
bit 5-4
Unimplemented: Read as '0'
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable Control bit
1= Oscillator is enabled
0= Oscillator is shut off(1)
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1= Do not synchronize external clock input
0= Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RB1/T1OSO/T1CKI (on the rising edge after the first falling edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Note 1: The oscillator inverter and feedback resistor are turned off to eliminate power drain.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 29
PIC16F716
FIGURE 5-1:
TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow
Synchronized
clock input
0
TMR1
TMR1L
TMR1H
1
TMR1ON
on/off
T1SYNC
T1OSC
RB1/T1OSO/T1CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
FOSC/4
Internal
Clock
0
(1)
RB2/T1OSI
2
Sleep input
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
which is latched in interrupt flag bit TMR1IF (PIR1<0>).
This interrupt can be enabled/disabled by setting/clear-
ing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
5.2
Timer1 Oscillator
A crystal oscillator circuit is built in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The
oscillator is a low-power oscillator designed to operate
with a 32.768 kHz tuning fork crystal. It will continue to
run during Sleep.
5.4
Resetting Timer1 using an ECCP
Trigger Output
If the ECCP module is configured in Compare mode to
generate a “special event trigger” (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
The user must provide a software time delay to ensure
proper oscillator start-up.
Note 1: Circuit guidelines for the LP oscillator
(32 kHz), as shown in Section 9.2
“Oscillator Configurations”, also apply
to the Timer1 Oscillator.
Note:
The special event triggers from the ECCP
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Timer1 must be configured for either Timer or
Synchronized Counter mode to take advantage of this
feature. If Timer1 is running in Asynchronous Counter
mode, this Reset operation may not work.
2: The Timer1 register pair, TMR1H and
TMR1L, in combination with the Timer1
overflow flag (TMR1IF) can be used as
the oscillator start-up stabilization timer.
In the event that a write to Timer1 coincides with a
special event trigger from the ECCP, the write will take
precedence.
5.3
Timer1 Interrupt
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 interrupt, if enabled, is generated on overflow
In this mode of operation, the CCPR1H:CCPR1L
register pair effectively becomes the period register for
Timer1.
TABLE 5-1:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
POR,
BOR
Value on
all other
Resets
Address Name Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh INTCON GIE PEIE
T0IE
—
INTE
—
RBIE
—
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
PIE1
—
—
ADIF
ADIE
CCP1IF TMR2IF TMR1IF -0-- -000 -0-- -000
CCP1IE TMR2IE TMR1IE -0-- -000 -0-- -000
8Ch
—
—
—
0Eh
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0Fh
10h
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend:
x= unknown, u= unchanged, -= unimplemented read as ‘0’. Shaded cells are not used by the Timer1 module.
DS41206A-page 30
Preliminary
2003 Microchip Technology Inc.
PIC16F716
Figure 6-1 is a simplified block diagram of the Timer2
module.
6.0
TIMER2 MODULE
The Timer2 module timer has the following features:
Additional information on timer modules is available in
the PICmicro® Mid-Range Reference Manual,
(DS33023).
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match of PR2
Timer2 has a control register, shown in Register 6-1.
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
REGISTER 6-1:
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1
TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
0010= 1:3 Postscale
0011= 1:4 Postscale
0100= 1:5 Postscale
0101= 1:6 Postscale
0110= 1:7 Postscale
0111= 1:8 Postscale
1000= 1:9 Postscale
1001= 1:10 Postscale
1010= 1:11 Postscale
1011= 1:12 Postscale
1100= 1:13 Postscale
1101= 1:14 Postscale
1110= 1:15 Postscale
1111= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 31
PIC16F716
6.1
Timer2 Operation
6.2
Timer2 Interrupt
Timer2 can be used as the PWM time base for PWM
mode of the ECCP module.
The Timer2 module has an 8-bit Period register (PR2).
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
The TMR2 register is readable and writable, and is
cleared on any device Reset
The input clock (FOSC/4) has a prescale option of 1:1,
1:4
or
1:16,
selected
by
control
bits
FIGURE 6-1:
TIMER2 BLOCK DIAGRAM
T2CKPS1:T2CKPS0 (T2CON<1:0>).
Sets flag
bit TMR2IF
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>).
TMR2
output
Reset
Prescaler
1:1, 1:4, 1:16
TMR2 reg
FOSC/4
The prescaler and postscaler counters are cleared
when any of the following occurs:
Postscaler
2
Comparator
1:1 to 1:16
EQ
• A write to the TMR2 register
• A write to the T2CON register
4
PR2 reg
• Any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset, or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
TABLE 6-1:
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on
POR,
BOR
Value on
all other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh INTCON
GIE
—
PEIE
ADIF
ADIE
T0IE
—
INTE
—
RBIE
—
T0IF
INTF
RBIF
0000 000x
-0-- -000
0000 000u
-0-- -000
0Ch
8Ch
PIR1
PIE1
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
—
—
—
—
-0-- -000
-0-- -000
11h
TMR2
T2CON
PR2
Timer2 module’s register
0000 0000
-000 0000
1111 1111
0000 0000
-000 0000
1111 1111
12h
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
92h
Legend:
x= unknown, u= unchanged, -= unimplemented read as ‘0’. Shaded cells are not used by the Timer2 module.
DS41206A-page 32
Preliminary
2003 Microchip Technology Inc.
PIC16F716
The CCP1CON register controls ECCP operation. All
the CCP1CON bits are readable and writable.
7.0
ENHANCED CAPTURE/
COMPARE/PWM (ECCP)
MODULE
Additional information on the ECCP module is available
in the PICmicro® Mid-Range Reference Manual,
(DS33023).
The ECCP (Enhanced Capture/Compare/PWM)
module contains a 16-bit register, which can operate
as:
TABLE 7-1:
ECCP MODE - TIMER
RESOURCE
• 16-bit Capture register
• 16-bit Compare register
ECCP Mode
Timer Resource
• PWM Master/Slave Duty Cycle register
Capture
Compare
PWM
Timer1
Timer1
Timer2
Table 7-1 shows the timer resources of the ECCP
module modes.
Capture/Compare/PWM Register
1
(CCPR1) is
comprised of two 8-bit registers: CCPR1L (low byte)
and CCPR1H (high byte).
REGISTER 7-1:
CCP1CON REGISTER (ADDRESS: 17h)
R/W-0
P1M1
R/W-0
P1M0
R/W-0
R/W-0
DC1B0
R/W-0
R/W-0
R/W-0
R/W-0
CCP1M0
bit 0
DC1B1
CCP1M3
CCP1M2 CCP1M1
bit 7
bit 7-6
P1M1:P1M0: PWM Output Configuration bits
CCP1M<3:2> = 00, 01, 10
xx= P1A assigned as Capture/Compare I/O. P1B, P1C, P1D assigned as Port pins.
CCP1M<3:2> = 11
00= Single output, P1A modulated. P1B, P1C, P1D assigned as Port pins.
01= Quad output forward. P1D modulated, P1A active. P1B and P1C inactive.
10= Dual output. P1A, P1B modulated with dead-time control. P1C, P1D assigned as port pins.
11= Quad output reverse. P1B modulated, P1C active. P1A and P1D inactive.
bit 5-4
bit 3-0
DC1B1:DC1B0: PWM Least Significant bits
Capture mode: Unused
Compare mode: Unused
PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found
in CCPR1L.
CCP1M3:CCP1M0: ECCP Mode Select bits
0000= Capture/Compare/PWM off (resets ECCP module)
0001= Unused (Reserved)
0010= Compare mode, toggle output on match (CCP1IF bit is set)
0011= Unused (Reserved)
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, set CCP1 output on match (CCP1IF bit is set)
1001= Compare mode, clear CCP1 output on match (CCP1IF bit is set)
1010= Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected)
1011= Compare mode, trigger special event (CCP1IF bit is set, TMR1 is reset, and an A/D conversion is
started if the A/D module is enabled. CCP1 pin is unaffected).
1100= PWM mode. P1A, P1C active-high; P1B, P1D active-high.
1101= PWM mode. P1A, P1C active-high; P1B, P1D active-low.
1110= PWM mode. P1A, P1C active-low; P1B, P1D active-high.
1111= PWM mode. P1A, P1C active-low; P1B, P1D active-low.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 33
PIC16F716
7.1.4
ECCP PRESCALER
7.1
Capture Mode
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the ECCP module is
turned off, or the ECCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RB3/CCP1/P1A. An event is defined as:
• Every falling edge
• Every rising edge
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
• Every 4th rising edge
• Every 16th rising edge
a
non-zero prescaler. Example 7-1 shows the
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the
interrupt request flag bit CCP1IF (PIR1<2>) is set. It
must be cleared in software. If another capture occurs
before the value in register CCPR1 is read, the old
captured value will be lost.
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 7-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
Note:
Always reset the ECCP module
(CCP1M3:CCP1M0 = ‘0000’) between
changing from one capture mode to
another. This is necessary to reset the
internal capture counter.
CLRF
MOVLW
CCP1CON
NEW_CAPT_PS
;Turn ECCP module off
;Load the W reg with
;the new prescaler
;mode value and ECCP ON
;Load CCP1CON with this
;value
MOVWF CCP1CON
FIGURE 7-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
7.2
Compare Mode
Set flag bit CCP1IF
(PIR1<2>)
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RB3/CCP1/P1A pin is
either:
Prescaler
1, 4, 16
RB3/CCP1/P1A
Pin
CCPR1H
CCPR1L
• Driven High
• Driven Low
Capture
Enable
and
edge detect
• Toggle output (high-to-low or low-to-high)
• Remains Unchanged
TMR1H
TMR1L
CCP1CON<3:0>
Q’s
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
7.1.1
CCP1 PIN CONFIGURATION
In Capture mode, the RB3/CCP1/P1A pin should be
configured as an input by setting the TRISB<3> bit.
Changing the ECCP mode to clear output on match
(CCP1M<3:0> = 1000) presets the CCP1 output latch
to the logic 1 level. Changing the ECCP mode to set
output on match (CCP1M<3:0> = 1001) presets the
CCP1 output latch to the logic 0 level.
Note:
If the RB3/CCP1/P1A is configured as an
output, a write to PORTB can cause a
capture condition.
7.1.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or
Synchronized Counter mode for the ECCP module to
use the capture feature. In Asynchronous Counter
mode, the capture operation may not work.
7.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
DS41206A-page 34
Preliminary
2003 Microchip Technology Inc.
PIC16F716
7.2.1
CCP1 PIN CONFIGURATION
The user must configure the RB3/CCP1/P1A pin as the
CCP1 output by clearing the TRISB<3> bit.
Note:
The special event trigger from the ECCP
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Note:
Clearing the CCP1CON register will force
the RB3/CCP1/P1A compare output latch
to the default low level. This is not the
PORTB I/O data latch.
FIGURE 7-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
7.2.2
TIMER1 MODE SELECTION
Special Event Trigger
Set flag bit CCP1IF
(PIR1<2>)
Timer1 must be running in Timer mode or
Synchronized Counter mode if the ECCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
RB3/CCP1/P1A
Pin
CCPR1H CCPR1L
Q
S
R
Output
Logic
Comparator
match
7.2.3
SOFTWARE INTERRUPT MODE
TRISB<3>
TMR1H TMR1L
Output Enable
CCP1CON<3:0>
Mode Select
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. Only a CCP interrupt is
generated (if enabled).
Note 1:
Special event trigger will reset Timer1, but not set
interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/
DONE (ADCON0<2>) which starts an A/D
conversion.
7.2.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of the ECCP resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special event trigger output of the ECCP also starts
an A/D conversion (if the A/D module is enabled).
TABLE 7-2:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Value on
POR,
BOR
Value on
all other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh
0Ch
INTCON
PIR1
GIE
—
PEIE
ADIF
T0IE
—
INTE
—
RBIE
—
T0IF
INTF
RBIF
0000 000x 0000 000u
-0-- -000 -0-- -000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1IF
TMR2IF
TMR1IF
0Eh
TMR1L
TMR1H
T1CON
CCPR1L
CCPR1H
CCP1CON
TRISB
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1register
0Fh
10h
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h
Capture/Compare/PWM register1 (LSB)
Capture/Compare/PWM register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
16h
17h
P1M1
PORTB Data direction register
ADIE
P1M0
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
1111 1111 1111 1111
86h
8Ch
PIE1
—
—
—
—
CCP1IE
TMR2IE
TMR1IE -0-- -000 -0-- -000
Legend:
x= unknown, u= unchanged, -= unimplemented read as ‘0’. Shaded cells are not used by Capture and Timer1.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 35
PIC16F716
A PWM output (Figure 7-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
7.3
PWM Mode
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTB data latch,
the TRISB<3> bit must be cleared to make the CCP1
pin an output.
FIGURE 7-4:
PWM OUTPUT
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTB I/O data
latch.
Period = PR2+1
Duty Cycle
Figure 7-3 shows a simplified block diagram of the
CCP module in PWM mode.
TMR2 = PR2
TMR2 = Duty Cycle (CCPR1H)
For a step-by-step procedure on how to setup the
ECCP module for PWM operation, see Section 7.3.3
“Set-Up for PWM Operation”.
TMR2 = PR2
FIGURE 7-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
7.3.1
PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
CCP1CON<5:4>
Duty cycle registers
CCPR1L
EQUATION 7-1:
PWM Period = [(PR2) + 1] • 4 • Tosc •
(TMR2 prescale value)
CCPR1H (Slave)
Comparator
RB3/CCP1/P1A
Q
R
S
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
(Note 1)
TMR2
• TMR2 is cleared
TRISB<3>
Comparator
PR2
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
Clear Timer,
CCP1 pin and
latch D.C.
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time base.
Note:
The Timer2 postscaler (see Section 6.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
DS41206A-page 36
Preliminary
2003 Microchip Technology Inc.
PIC16F716
7.3.2
PWM DUTY CYCLE
EQUATION 7-3:
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
F
OSC
PWM
log
(
)
F
Max resolution
bits
=
log(2)
Note:
If the PWM duty cycle value is longer than
the PWM period the CCP1 pin will not be
cleared.
EQUATION 7-2:
For an example PWM period and duty cycle
calculation, see the PICmicro® Mid-Range Reference
Manual, (DS33023).
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4> •
TOSC • (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read-only register.
7.3.3
SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the ECCP module for PWM operation:
1. Set the PWM period by writing to the PR2
register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISB<3> bit.
When the CCPR1H and 2-bit latch match TMR2
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Maximum PWM resolution (bits) for a given PWM
frequency is given by the following equation:
5. Configure the CCP1 module for PWM operation.
TABLE 7-3:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
0xFF
10
0xFF
10
0x17
6.6
Maximum Resolution (bits)
TABLE 7-4:
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
POR,
BOR
Value on
all other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh INTCON
GIE
—
PEIE
ADIF
T0IE
—
INTE
—
RBIE
—
T0IF
INTF
RBIF
0000 000x 0000 000u
-0-- -000 -0-- -000
0000 0000 0000 0000
0Ch
11h
PIR1
CCP1IF
TMR2IF
TMR1IF
TMR2
Timer2 module’s register
12h
T2CON
CCPR1L
CCPR1H
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h
Capture/Compare/PWM register1 (LSB)
Capture/Compare/PWM register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
16h
17h
CCP1CON P1M1
P1M0
PORB Data direction register
ADIE
Timer2 module’s period register
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
1111 1111 1111 1111
86h
TRISB
PIE1
PR2
8Ch
92h
—
—
—
—
CCP1IE
TMR2IE
TMR1IE -0-- -000 -0-- -000
1111 1111 1111 1111
Legend:
x= unknown, u= unchanged, -= unimplemented read as ‘0’. Shaded cells are not used by PWM and Timer2.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 37
PIC16F716
7.4.1
PWM OUTPUT CONFIGURATIONS
7.4
ENHANCED PWM MODE
The P1M1:P1M0 bits in the CCP1CON register allows
one of four configurations:
The Enhanced PWM mode provides additional PWM
output options for
a broader range of control
applications. The module is an upwardly compatible
version of the standard CCP module and offers up to
four outputs, designated P1A through P1D. Users are
also able to select the polarity of the signal (either
active-high or active-low). The module’s Output mode
and polarity are configured by setting the P1M1:P1M0
and CCP1M3:CCP1M0 bits of the CCP1CON register
(CCP1CON<7:6> and CCP1CON<3:0>, respectively).
• Single Output
• Half-Bridge Output
• Full-Bridge Output Forward mode
• Full-Bridge Output Reverse mode
The Single Output mode is the Standard PWM mode
discussed in Section 7.3 “PWM Mode”. The Half-
Bridge and Full-Bridge Output modes are covered in
detail in the sections that follow.
Figure 7-5 shows a simplified block diagram of PWM
operation. All control registers are double buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to
prevent glitches on any of the outputs. The exception is
the PWM Dead-band Delay, which is loaded at either
the duty cycle boundary or the boundary period
(whichever comes first). Because of the buffering, the
module waits until the assigned timer resets, instead of
starting immediately. This means that enhanced PWM
waveforms do not exactly match the standard PWM
waveforms, but are instead offset by one full instruction
cycle (4 TOSC).
The general relationship of the outputs in all
configurations is summarized in Figure 7-6.
As before, the user must manually configure the
appropriate TRISB bits for output.
FIGURE 7-5:
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
CCP1CON<5:4>
CCP1M<3:0>
4
P1M<1:0>
Duty Cycle Registers
2
CCPR1L
CCP1/P1A
RB3/CCP1/P1A
TRISB<3>
TRISB<5>
TRISB<6>
TRISB<7>
CCPR1H (Slave)
Comparator
P1B
RB5/P1B
RB6/P1C
Output
R
Q
Controller
P1C
(Note 1)
TMR2
S
P1D
RB7/P1D
Comparator
PR2
Clear Timer,
set CCP1 pin and
latch D.C.
PWM1CON
Note 1:
The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit
time base.
DS41206A-page 38
Preliminary
2003 Microchip Technology Inc.
PIC16F716
FIGURE 7-6:
PWM OUTPUT RELATIONSHIPS (P1A, P1B, P1C, P1D ACTIVE-HIGH STATE)
0
PR2+1
Duty
Cycle
SIGNAL
CCP1CON
<7:6>
Period
P1A Modulated
(Single Output)
00
10
(1)
(1)
Delay
Delay
P1A Modulated
P1B Modulated
(Half-Bridge)
P1A Active
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
(Full-Bridge,
Forward)
01
(Full-Bridge,
Reverse)
11
P1D Inactive
FIGURE 7-7:
PWM OUTPUT RELATIONSHIPS (P1A, P1B, P1C, P1D ACTIVE-LOW STATE)
0
PR2+1
Duty
Cycle
SIGNAL
CCP1CON
<7:6>
Period
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
(Single Output)
00
10
(1)
(1)
Delay
Delay
(Half-Bridge)
P1B Inactive
(Full-Bridge,
Forward)
01
11
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
(Full-Bridge,
Reverse)
P1D Inactive
Relationships:
•
•
•
Period = 4 * TOSC * (PR2 + 1) * (TMR2 prescale value)
Duty Cycle = TOSC * (CCPR1L<7:0> : CCP1CON<5:4>) * (TMR2 prescale value)
Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 7.4.4 “Programmable Dead-Band
Delay”).
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 39
PIC16F716
FIGURE 7-8:
PWM OUTPUT RELATIONSHIPS (P1A, P1C ACTIVE-HIGH. P1B, P1D
ACTIVE-LOW)
0
PR2+1
Duty
Cycle
SIGNAL
CCP1CON
<7:6>
Period
P1A Modulated
(Single Output)
00
10
(1)
(1)
Delay
Delay
P1A Modulated
P1B Modulated
(Half-Bridge)
P1A Active
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
(Full-Bridge,
Forward)
01
11
(Full-Bridge,
Reverse)
P1D Inactive
DS41206A-page 40
Preliminary
2003 Microchip Technology Inc.
PIC16F716
FIGURE 7-9:
PWM OUTPUT RELATIONSHIPS (P1A, P1C ACTIVE-LOW. P1B, P1D
ACTIVE-HIGH)
0
PR2+1
Duty
Cycle
SIGNAL
CCP1CON
<7:6>
Period
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
(Single Output)
00
10
(1)
(1)
Delay
Delay
(Half-Bridge)
P1B Inactive
(Full-Bridge,
Forward)
01
11
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
(Full-Bridge,
Reverse)
P1D Inactive
Relationships:
•
•
•
Period = 4 * TOSC * (PR2 + 1) * (TMR2 prescale value)
Duty Cycle = TOSC * (CCPR1L<7:0> : CCP1CON<5:4>) * (TMR2 prescale value)
Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 7.4.4 “Programmable Dead-Band
Delay”).
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 41
PIC16F716
Since the P1A and P1B outputs are multiplexed with
the PORTB<3> and PORTB<5> data latches, the
TRISB<3> and TRISB<5> bits must be cleared to
configure P1A and P1B as outputs.
7.4.2
HALF-BRIDGE MODE
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output
signal is output on the RB3/CCP1/P1A pin, while the
complementary PWM output signal is output on the
RB5/P1B pin (Figure 7-12). This mode can be used for
half-bridge applications, as shown in Figure 7-11 or for
full-bridge applications, where four power switches are
being modulated with two PWM signals.
FIGURE 7-10:
HALF-BRIDGE PWM
OUTPUT
Period
Period
Duty Cycle
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of
PWM1CON bits PDC6:PDC0 sets the number of
instruction cycles before the output is driven active. If
the value is greater than the duty cycle, the
corresponding output remains inactive during the entire
cycle. See Section 7.4.4 “Programmable Dead-
Band Delay” for more details of the dead-band delay
operations.
(2)
(2)
P1A
td
td
P1B
(1)
(1)
(1)
td = Dead-band Delay
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
FIGURE 7-11:
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
V+
Standard Half-Bridge Circuit (“Push-Pull”)
PIC16F716
P1A
FET
Driver
+
V
-
Load
FET
Driver
+
V
-
P1B
V-
Half-Bridge Output Driving a Full-Bridge Circuit
V+
PIC16F716
FET
FET
Driver
Driver
P1A
Load
FET
FET
Driver
Driver
P1B
V-
DS41206A-page 42
Preliminary
2003 Microchip Technology Inc.
PIC16F716
P1A, P1B, P1C and P1D outputs are multiplexed with
the PORTB<3> and PORTB<5:7> data latches. The
TRISB<3> and TRISB<5:7> bits must be cleared to
make the P1A, P1B, P1C, and P1D pins output.
7.4.3
FULL-BRIDGE MODE
In Full-Bridge Output mode, four pins are used as
outputs; however, only two outputs are active at a time.
In the Forward mode, pin RB3/CCP1/P1A is
continuously active, and pin RB7/P1D is modulated. In
the Reverse mode, RB6/P1C pin is continuously active,
and RB5/P1B pin is modulated. These are illustrated in
Figure 7-6 through Figure 7-9.
FIGURE 7-12:
EXAMPLE OF FULL-BRIDGE APPLICATION
V+
PIC16F716
QC
QA
FET
Driver
FET
Driver
P1A
Load
P1B
FET
Driver
FET
Driver
P1C
P1D
QD
QB
V-
7.4.3.1
Direction Change in Full-Bridge
Mode
Note:
In the Full-Bridge Output mode, the ECCP
module does not provide any dead-band
delay. In general, since only one output is
modulated at all times, dead-band delay is
not required. However, there is a situation
In the Full-Bridge Output mode, the P1M1 bit in the
CCP1CON register allows the user to control the
Forward/Reverse direction. When the application
firmware changes this direction control bit, the module
will assume the new direction on the next PWM cycle.
where
a dead-band delay might be
required. This situation occurs when both
of the following conditions are true:
Just before the end of the current PWM period, the
modulated outputs (P1B and P1D) are placed in their
inactive state, while the unmodulated outputs (P1A and
P1C) are switched to drive in the opposite direction. This
occurs in a time interval of (4•TOSC•(Timer2 Prescale
value)) before the next PWM period begins. The Timer2
prescaler will be either 1, 4 or 16, depending on the
value of the T2CKPSx bits (T2CON<1:0>). During the
interval from the switch of the unmodulated outputs to
the beginning of the next period, the modulated outputs
(P1B and P1D) remain inactive. This relationship is
shown in Figure 7-13.
1. The direction of the PWM output
changes when the duty cycle of the
output is at or near 100%.
2. The turn off time of the power switch,
including the power device and driver
circuit, is greater than the turn on
time.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 43
PIC16F716
Figure 7-14 shows an example where the PWM
direction changes from forward to reverse, at a near
100% duty cycle. At time t1, the output P1A and P1D
become inactive, while output P1C becomes active. In
this example, since the turn-off time of the power
devices is longer than the turn-on time, a shoot-through
current may flow through power devices QC and QD
(see Figure 7-12) for the duration of ‘t’. The same
phenomenon will occur to power devices QA and QB
for PWM direction change from reverse to forward.
If changing PWM direction at high duty cycle is required
for an application, one of the following requirements
must be met:
1. Reduce PWM for a PWM period before changing
directions.
2. Use switch drivers that can drive the switches off
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
FIGURE 7-13:
PWM DIRECTION CHANGE
(1)
Period
Period
SIGNAL
P1A (Active-High)
P1B (Active-High)
DC
P1C (Active-High)
P1D (Active-High)
(Note 2)
DC
Note 1: The direction bit in the CCP1 Control Register (CCP1CON<7>) is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of
4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are
inactive at this time.
FIGURE 7-14:
PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
Forward Period
Reverse Period
t1
P1A
P1B
DC
P1C
P1D
DC
t
on
External Switch C
External Switch D
t
off
Potential
t = t - t
off on
Shoot-Through
Current
Note 1: All signals are shown as active-high.
2:
3:
t
t
is the turn-on delay of power switch QC and its driver.
is the turn-off delay of power switch QD and its driver.
on
off
DS41206A-page 44
Preliminary
2003 Microchip Technology Inc.
PIC16F716
7.4.4
PROGRAMMABLE DEAD-BAND
DELAY
7.4.5
ENHANCED PWM
AUTO-SHUTDOWN
In half-bridge applications where all power switches are
modulated at the PWM frequency at all times, the
power switches normally require more time to turn off
than to turn on. If both the upper and lower power
switches are switched at the same time (one turned on,
and the other turned off), both switches may be on for
a short period of time until one switch completely turns
off. During this brief interval, a very high current (shoot-
through current) may flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from
flowing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
When the ECCP is programmed for any of the
enhanced PWM modes, the active output pins may be
configured
for
auto-shutdown.
Auto-shutdown
immediately places the enhanced PWM output pins
into a defined shutdown state when a shutdown event
occurs.
A shutdown event can be caused by a logic low level on
either or both of the RB0/INT/ECCPAS2 or RB4/
ECCPAS0 pins. The auto-shutdown feature can be
disabled by not selecting any auto-shutdown sources.
The auto-shutdown sources to be used are selected
using the ECCPAS2 and ECCPAS0 bits (ECCPAS<6>
and ECCPAS<4>).
When a shutdown occurs, the output pins are
asynchronously placed in their shutdown states,
In the Half-Bridge Output mode, a digitally program-
mable dead-band delay is available to avoid shoot-
through current from destroying the bridge power
switches. The delay occurs at the signal transition from
the non-active state to the active state. See Figure 7-10
for illustration. The lower seven bits of the PWM1CON
register (Register 7-2) sets the delay period in terms of
microcontroller instruction cycles (TCY or 4 TOSC).
specified
by
the
PSSAC1:PSSAC0
and
PSSBD1:PSSBD0 bits (ECCPAS<3:0>). Each pin pair
(P1A/P1C and P1B/P1D) may be set to drive high,
drive low, or be tri-stated (not driving). The ECCPASE
bit (ECCPAS<7>) is also set to hold the enhanced
PWM outputs in their shutdown states.
The ECCPASE bit is set by hardware when a shutdown
event occurs. If automatic restarts are not enabled, the
ECCPASE bit must be cleared by firmware when the
cause of the shutdown clears. If automatic restarts are
enabled, the ECCPASE bit is automatically cleared
when the cause of the auto-shutdown has cleared.
If the ECCPASE bit is set when a PWM period begins,
the PWM outputs remain in their shutdown state for that
entire PWM period. When the ECCPASE bit is cleared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
Note: Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 45
PIC16F716
REGISTER 7-2:
PWM1CON: PWM CONFIGURATION REGISTER (ADDRESS: 18h)
R/W-0
R/W-0
PDC6
R/W-0
PDC5
R/W-0
PDC4
R/W-0
PDC3
R/W-0
PDC2
R/W-0
PDC1
R/W-0
PDC0
PRSEN
bit 7
bit 0
bit 7
PRSEN: PWM Restart Enable bit
1= Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes
away; the PWM restarts automatically.
0= Upon auto-shutdown, ECCPASE must be cleared in firmware to restart the PWM.
bit 6-0
PDC<6:0>: PWM Delay Count bits
Number of FOSC/4 (4*TOSC) cycles between the scheduled time when a PWM signal should
transition active, and the actual time it transitions active.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
REGISTER 7-3:
ECCPAS – ENHANCED CCP AUTO SHUT DOWN REGISTER (ADDRESS: 19h)
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ECCPASE ECCPAS2
bit 7
ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0
bit 0
bit 7
bit 6
ECCPASE: ECCP Auto-Shutdown Event Status bit
1= A shutdown event has occurred. Must be reset in firmware to re-enable ECCP if
PRSEN = 0
0= ECCP outputs enabled, no shutdown event
ECCPAS2: ECCP Auto-Shutdown bit 2
1= RB0 (INT) pin low level (‘0’) causes shutdown
0= RB0 (INT) pin has no effect on ECCP
bit 5
bit 4
Unimplemented: Read as ‘0’
ECCPAS0: ECCP Auto-Shutdown bit ‘0’
1= RB4 pin low level (‘0’) causes shutdown
0= RB4 pin has no effect on ECCP
bit 3-2
bit 1-0
PSSAC<1:0>: Pin P1A and P1C Shutdown State Control
00= Drive Pins P1A and P1C to ‘0’
01= Drive Pins P1A and P1C to ‘1’
1x= Pins P1A and P1C tri-state
PSSBD<1:0>: Pin P1B and P1D Shutdown State Control
00= Drive Pins P1B and P1D to ‘0’
01= Drive Pins P1B and P1D to ‘1’
1x= Pins P1B and P1D tri-state
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS41206A-page 46
Preliminary
2003 Microchip Technology Inc.
PIC16F716
7.4.5.1
Auto-Shutdown and Automatic
Restart
7.4.6
START-UP CONSIDERATIONS
When the ECCP module is used in the PWM mode, the
application hardware must use the proper external pull-
up and/or pull-down resistors on the PWM output pins.
When the microcontroller is released from Reset, all of
the I/O pins are in the high-impedance state. The
external circuits must keep the power switch devices in
the off state, until the microcontroller drives the I/O pins
with the proper signal levels, or activates the PWM
output(s).
The auto-shutdown feature can be configured to allow
automatic restarts of the module following a shutdown
event. This is enabled by setting the PRSEN bit of the
PWM1CON register (PWM1CON<7>).
In Shutdown mode with PRSEN = 1(PWM1CON <7>)
(Figure 7-15), the ECCPASE bit will remain set for as
long as the cause of the shutdown continues. When the
shutdown condition clears, the ECCPASE bit is
cleared. If PRSEN = 0(Figure 7-16), once a shutdown
condition occurs, the ECCPASE bit will remain set until
it is cleared by firmware. Once ECCPASE is cleared,
the enhanced PWM will resume at the beginning of the
next PWM period.
The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow
the user to choose whether the PWM output signals are
active-high or active-low for each pair of PWM output
pins (P1A/P1C and P1B/P1D). The PWM output
polarities must be selected before the PWM pins are
configured as outputs. Changing the polarity
configuration while the PWM pins are configured as
outputs is not recommended since it may result in
damage to the application circuits.
Note: Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
The ECCPASE bit cannot be cleared as long as the
cause of the shutdown persists.
The P1A, P1B, P1C and P1D output latches may not
be in the proper states when the PWM module is
initialized. Enabling the PWM pins for output at the
same time as the ECCP module may cause damage to
the application circuit. The ECCP module must be
enabled in the proper Output mode and complete a full
PWM cycle before configuring the PWM pins as
outputs. The completion of a full PWM cycle is
indicated by the TMR2IF bit being set as the second
PWM period begins.
The Auto-shutdown mode can be forced by writing a '1'
to the ECCPASE bit.
FIGURE 7-15:
PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)
PWM Period
Shutdown Event
ECCPASE bit
PWM Activity
Normal PWM
Start of
PWM Period
Shutdown
Event Occurs Event Clears
Shutdown
PWM
Resumes
FIGURE 7-16:
PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)
PWM Period
Shutdown Event
ECCPASE bit
PWM Activity
Normal PWM
ECCPASE
Cleared by
Firmware
Start of
PWM Period
Shutdown
Event Occurs Event Clears
Shutdown
PWM
Resumes
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 47
PIC16F716
8. Configure and start TMR2:
7.4.7
SETUP FOR PWM OPERATION
• Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit (PIR1<1>).
The following steps should be taken when configuring
the ECCP module for PWM operation:
• Set the TMR2 prescale value by loading the
T2CKPSx bits (T2CON<1:0>).
1. Configure the PWM pins P1A and P1B (and
P1C and P1D, if used) as inputs by setting the
corresponding TRISB bits.
• Enable Timer2 by setting the TMR2ON bit
(T2CON<2>).
2. Set the PWM period by loading the PR2 register.
3. Configure the ECCP module for the desired
PWM mode and configuration by loading the
CCP1CON register with the appropriate values:
9. Enable PWM outputs after a new PWM cycle
has started:
• Wait until TMR2 overflows (TMR2IF bit is set).
• Select one of the available output
configurations and direction with the
P1M1:P1M0 bits.
• Enable the CCP1/P1A, P1B, P1C and/or P1D
pin outputs by clearing the respective TRISB
bits.
• Select the polarities of the PWM output
signals with the CCP1M3:CCP1M0 bits.
• Clear the ECCPASE bit (ECCPAS<7>).
See the previous section for additional details.
4. Set the PWM duty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
7.4.8
EFFECTS OF A RESET
5. For Half-Bridge Output mode, set the dead-
band delay by loading PWM1CON<6:0> with
the appropriate value.
Both Power-on and subsequent Resets will force all
ports to Input mode and the ECCP registers to their
Reset states.
6. If auto-shutdown operation is required, load the
ECCPAS register.
This forces the Enhanced CCP module to reset to a
state compatible with the standard ECCP module.
• Select the auto-shutdown sources using the
ECCPAS<2> AND ECCPAS<0> bits.
• Select the shutdown states of the PWM output
pins
using
PSSAC1:PSSAC0
and
PSSBD1:PSSBD0 bits.
• Set the ECCPASE bit (ECCPAS<7>).
7. If auto-restart operation is required, set the
PRSEN bit (PWM1CON<7>).
TABLE 7-5:
REGISTERS ASSOCIATED WITH ENHANCED PWM AND TIMER2
Value on
Value on
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
0Bh
0Ch
8Ch
11h
INTCON
PIR1
GIE
—
PEIE
ADIF
ADIE
TMR0IE
INT0IE
—
RBIE
—
TMR0IF
CCP1IF
INT0IF
RBIF
0000 000x 0000 000u
—
—
TMR2IF
TMR1IF -0-- -000 -0-- -000
TMR1IE -0-- --00 -0-- --00
0000 0000 0000 0000
PIE1
—
—
—
CCP1IE TMR2IE
TMR2
Timer2 Module Register
92h
PR2
Timer2 Module Period Register
1111 1111 1111 1111
12h
T2CON
TRISB
—
TOUTPS3
TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
86h
PORTB Data Direction Register
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
16h
CCPR1H
CCPR1L
CCP1CON
ECCPAS
PWM1CON
Enhanced Capture/Compare/PWM Register1 High Byte
Enhanced Capture/Compare/PWM Register1 Low Byte
15h
xxxx xxxx uuuu uuuu
17h
P1M1
ECCPASE
PRSEN
P1M0
ECCPAS2
PDC6
DC1B1
—
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
19h
ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 00-0 0000 00-0 0000
PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 0000 0000
18h
PDC5
Legend:
x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by the ECCP module in enhanced PWM mode.
DS41206A-page 48
Preliminary
2003 Microchip Technology Inc.
PIC16F716
Additional information on the A/D module is available in
the PICmicro® Mid-Range Reference Manual,
(DS33023).
8.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module has four
inputs.
The A/D module has three registers. These registers
are:
The A/D allows conversion of an analog input signal to
• A/D Result Register (ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
a
corresponding 8-bit digital number (refer to
Application Note AN546 for use of A/D Converter). The
output of the sample and hold is the input into the
converter, which generates the result via successive
approximation. The analog reference voltage is
software selectable to either the device’s positive
supply voltage (VDD) or the voltage level on the RA3/
AN3/VREF pin.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion is aborted.
The ADCON0 register, shown in Register 8-1, controls
the operation of the A/D module. The ADCON1
register, shown in Register 8-2, configures the
functions of the port pins. The port pins can be
configured as analog inputs (RA3 can also be a voltage
reference) or as digital I/O.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
REGISTER 8-1:
ADCON0 REGISTER (ADDRESS: 1Fh)
R/W-0
R/W-0
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
—
R/W-0
ADON
ADCS1
ADCS0
GO/DONE
bit 7
bit 0
bit 7-6
bit 5-3
ADCS1:ADCS0: A/D Conversion Clock Select bits
00= FOSC/2
01= FOSC/8
10= FOSC/32
11= FRC (Clock derived from the internal ADC RC oscillator)
CHS2:CHS0: Analog Channel Select bits
000= channel 0, (RA0/AN0)
001= channel 1, (RA1/AN1)
010= channel 2, (RA2/AN2)
011= channel 3, (RA3/AN3)
1xx= reserved, do not use
bit 2
GO/DONE: A/D Conversion Status bit
If ADON = 1
1= A/D conversion in progress (Setting this bit starts the A/D conversion)
0= A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D
conversion is complete)
bit 1
bit 0
Reserved: Maintain this bit as '0'
ADON: A/D On bit
1= A/D converter module is operating
0= A/D converter module is shutoff and consumes no operating current
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 49
PIC16F716
REGISTER 8-2:
ADCON1 REGISTER (ADDRESS: 9Fh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
PCFG2 PCFG1
PCFG0
bit 7
bit 0
bit 7-3
bit 2-0
Unimplemented: Read as '0'
PCFG2:PCFG0: A/D Port Configuration Control bits
AN3
RA3
AN2
RA2
AN2
RA1
AN0
RA0
PCFG2:PCFG0
VREF
0x0
0x1
100
101
11x
A
VREF
A
A
A
D
D
D
A
A
A
A
D
A
A
A
A
D
VDD
RA3
VDD
RA3
VDD
VREF
D
Legend:
A = Analog input, D = Digital I/O
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘0’ = Bit is cleared
x = Bit is unknown
The ADRES register contains the result of the A/D
conversion. When the A/D conversion is complete, the
result is loaded into the ADRES register, the GO/DONE
bit (ADCON0<2>) is cleared and the A/D interrupt flag
bit ADIF is set. The block diagram of the A/D module is
shown in Figure 8-1.
1. Configure the A/D module:
- Configure analog pins/voltage reference/
and digital I/O (ADCON1)
- Select A/D input channel (ADCON0)
- Select A/D conversion clock (ADCON0)
- Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
- Clear ADIF bit
The value that is in the ADRES register is not modified
for any Reset. The ADRES register will contain
unknown data after a Power-on Reset.
- Set ADIE bit
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 8.1
“A/D Acquisition Requirements”. After this
acquisition time has elapsed, the A/D conversion can
be started. The following steps should be followed for
doing an A/D conversion:
- Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
- Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
- Polling for the GO/DONE bit to be cleared
OR
- Waiting for the A/D interrupt
6. Read A/D Result register (ADRES), clear bit
ADIF if required.
7. For the next conversion, go to step 1 or step 2
as required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
DS41206A-page 50
Preliminary
2003 Microchip Technology Inc.
PIC16F716
FIGURE 8-1:
A/D BLOCK DIAGRAM
CHS2:CHS0
VIN
011
(Input voltage)
RA3/AN3/VREF
RA2/AN2
010
001
000
A/D
Converter
RA1/AN1
VDD
RA0/AN0
000or
010or
VREF
100or
110or 111
(Reference
voltage)
001or
011or
101
PCFG2:PCFG0
To calculate the minimum acquisition time, TACQ, see
the PICmicro® Mid-Range Reference Manual,
(DS33023). This equation calculates the acquisition
time to within 1/2 LSb error. The 1/2 LSb error is the
maximum error allowed for the A/D to meet its specified
accuracy.
8.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 8-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
source impedance affects the offset voltage at the
analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 10 kΩ. After the analog input channel is
selected (changed) this acquisition must be done
before the conversion can be started.
Note:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
FIGURE 8-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
Rs
SS
RIC ≤ 1k
RSS
CHOLD
= DAC capacitance
= 51.2 pF
CPIN
5 pF
VA
I leakage
± 500 nA
VT = 0.6V
VSS
Legend:
CPIN
VT
= input capacitance
= threshold voltage
6V
5V
I leakage = leakage current at the pin due to
various junctions
VDD 4V
3V
2V
RIC
SS
= interconnect resistance
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
5 6 7 8 9 10 11
Sampling Switch
(kΩ)
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 51
PIC16F716
8.2
Selecting the A/D Conversion
Clock
8.3
Configuring Analog Port Pins
The ADCON1 and TRISA registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bits set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.5 TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selectable. The four possible options for TAD are:
• 2 TOSC
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
• 8 TOSC
• 32 TOSC
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins
configured as digital inputs, will convert
an analog input. Analog levels on a
digitally configured input will not affect the
conversion accuracy.
• Internal RC oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
Table 8-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
2: Analog levels on any pin that is defined as
a digital input (including the AN3:AN0
pins), may cause the input buffer to
consume current that is out of the devices
specification.
TABLE 8-1:
TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
Device Frequency
Operation
2 TOSC
8 TOSC
32 TOSC
RC
ADCS1:ADCS0
20 MHz
100 ns(2)
400 ns(2)
1.6 µs
5 MHz
400 ns(2)
1.6 µs
1.25 MHz
1.6 µs
333.33 kHz
6 µs
24 µs(3)
96 µs(3)
2-6 µs(1)
00
01
10
11
6.4 µs
6.4 µs
2-6 µs(1), (4)
25.6 µs(3)
2-6 µs(1), (4)
2-6 µs(1), (4)
Legend: Shaded cells are outside of recommended range.
Note 1: The RC source has a typical TAD time of 4 µs.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for
Sleep operation only.
DS41206A-page 52
Preliminary
2003 Microchip Technology Inc.
PIC16F716
8.4
A/D Conversions
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
8.5
Use of the ECCP Trigger
An A/D conversion can be started by the “special event
trigger” of the ECCP module. This requires that the
CCP1M3:CCP1M0
bits
(CCP1CON<3:0>)
be
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion,
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with minimal software overhead (moving the ADRES to
the desired location). The appropriate analog input
channel must be selected and the minimum acquisition
done before the “special event trigger” sets the GO/
DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
TABLE 8-2:
SUMMARY OF A/D REGISTERS
Value on
Value on all
POR,
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
other Resets
BOR
(1)
05h
PORTA
—
GIE
—
—
—
RA4
INTE
—
RA3
RBIE
—
RA2
T0IF
RA1
INTF
RA0
RBIF
--xx 0000
0000 000x
-0-- -000
xxxx xxxx
0000 0000
--11 1111
-0-- -000
---- -000
--uu uuuu
0000 000u
-0-- -000
uuuu uuuu
0000 0000
--11 1111
-0-- 0000
---- -000
0Bh,8Bh INTCON
PEIE
ADIF
T0IE
—
0Ch
1Eh
1Fh
85h
8Ch
9Fh
PIR1
CCP1IF
TMR2IF
TMR1IF
ADRES
ADCON0
TRISA
PIE1
A/D Result Register
(1)
ADCS1
—
ADCS0
—
CHS2
(1)
CHS1
CHS0
GO/DONE
—
ADON
—
PORTA Data Direction Register
—
ADIE
—
—
—
—
—
—
—
CCP1IE
PCFG2
TMR2IE
PCFG1
TMR1IE
PCFG0
ADCON1
—
Legend:
x= unknown, u= unchanged, -= unimplemented read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1:
Reserved bit, do not use.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 53
PIC16F716
NOTES:
DS41206A-page 54
Preliminary
2003 Microchip Technology Inc.
PIC16F716
9.1
Configuration Bits
9.0
SPECIAL FEATURES OF THE
CPU
The configuration bits can be programmed (read as ‘0’)
or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped in
program memory location 2007h.
The PIC16F716 device has a host of features intended
to maximize system reliability, minimize cost through
elimination of external components, provide power
saving operating modes and offer code protection.
These are:
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special configuration memory space (2000h – 3FFFh),
which can be accessed only during programming.
• OSC Selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Sleep
• Code protection
• ID locations
• In-Circuit Serial Programming™ (ICSP™)
The PIC16F716 device has a Watchdog Timer, which
can be shut off only through configuration bits. It runs
off its own RC oscillator for added reliability. There are
two timers that offer necessary delays on power-up.
One is the Oscillator Start-up Timer (OST), intended to
keep the chip in Reset until the crystal oscillator is
stable. The other is the Power-up Timer (PWRT), which
provides a fixed delay on power-up only and is
designed to keep the part in Reset while the power
supply stabilizes. With these two timers on-chip, most
applications need no external Reset circuitry.
Sleep mode is designed to offer a very low current
Power-down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost, while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
Additional information on special features is available
in the PICmicro® Mid-Range Reference Manual,
(DS33023).
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 55
PIC16F716
REGISTER 9-1:
CONFIGURATION WORD
CP
bit 13
—
—
—
—
—
BORV BOREN
—
—
PWRTE WDTE FOSC1 FOSC0
bit 0
bit 13
CP: Flash Program Memory Code Protection bit
1= Code protection off
0= All program memory code protected
bit 12-8
bit 7
Unimplemented: Read as ‘1’
BORV: Brown-out Reset Voltage bit
1= VBOR set to 4.0V
0= VBOR set to 2.5V
(1)
bit 6
BOREN: Brown-out Reset Enable bit
1= BOR enabled
0= BOR disabled
bit 5-4
bit 3
Unimplemented: Read as ‘1’
(1)
PWRTE: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
bit 2
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
bit 1-0
FOSC1:FOSC0: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer (PWRTE).
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = bit is cleared
x = bit is unknown
DS41206A-page 56
Preliminary
2003 Microchip Technology Inc.
PIC16F716
TABLE 9-1:
CERAMIC RESONATORS
Ranges Tested:
9.2
Oscillator Configurations
9.2.1
OSCILLATOR TYPES
Mode
Freq
OSC1 (C1)
OSC2 (C2)
The PIC16F716 can be operated in four different
oscillator modes. The user can program two
configuration bits (FOSC1 and FOSC0) to select one of
these four modes:
XT
455 kHz
2.0 MHz
68-100 pF
15-68 pF
68-100 pF
15-68 pF
HS
4.0 MHz
8.0 MHz
16.0 MHz
10-68 pF
15-68 pF
10-22 pF
10-68 pF
15-68 pF
10-22 pF
• LP - Low-power Crystal
• XT - Crystal/Resonator
Note 1: These values are for design guidance
• HS - High-speed Crystal/Resonator
• RC - Resistor/Capacitor
only. See notes at bottom of page.
TABLE 9-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
9.2.2
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
Crystal
Freq
Cap. Range
C1
Cap. Range
C2
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 9-1). The
PIC16F716 oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may give
Osc Type
LP
32 kHz
200 kHz
200 kHz
1 MHz
15-33 pF
5-10 pF
15-33 pF
5-10 pF
XT
HS
47-68 pF
15-33 pF
15-33 pF
15-33 pF
15-33 pF
15-33 pF
47-68 pF
15-33 pF
15-33 pF
15-33 pF
15-33 pF
15-33 pF
a
frequency out of the crystal manufacturers
specifications. When in XT, LP or HS modes, the
device can have an external clock source to drive the
OSC1/CLKIN pin (Figure 9-2).
4 MHz
4 MHz
8 MHz
FIGURE 9-1:
CRYSTAL/CERAMIC
RESONATOROPERATION
(HS, XT OR LP
20 MHz
Note 1: These values are for design guidance only.
See notes at bottom of page.
OSC CONFIGURATION)
C1(1)
OSC1
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
To
internal
logic
XTAL
RF(3)
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
Sleep
PIC16F716
Note 1: See Table 9-1 and Table 9-2 for
OSC2
RS(2)
C2(1)
appropriate
values
of
external
components.
3: RS may be required to avoid overdriving
recommended values of C1 and C2.
2: A series resistor (RS) may be required.
3: RF varies with the crystal chosen.
crystals with low drive level specification.
4: When using an external clock for the
OSC1 input, loading of the OSC2 pin
must be kept to a minimum by leaving the
OSC2 pin unconnected.
FIGURE 9-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
CONFIGURATION)
OSC1
Clock from
ext. system
PIC16F716
OSC2
Open
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 57
PIC16F716
A simplified block diagram of the On-chip Reset circuit
is shown in Figure 9-5.
The PICmicro® microcontrollers have an MCLR noise
filter in the MCLR Reset path. The filter will detect and
ignore small pulses.
9.2.3
RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (REXT) and capacitor (CEXT) values and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low CEXT values. The user also needs to
take into account variation due to tolerance of external
R and C components used. Figure 9-3 shows how the
R/C combination is connected to the PIC16F716.
It should be noted that a WDT Reset does not drive the
MCLR pin low.
9.4
Power-On Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected. To take advantage of the POR,
just tie the MCLR pin directly (or through a resistor) to
VDD. This will eliminate external RC components
usually needed to create a Power-on Reset. A
maximum rise time for VDD is specified (parameter
D004). For a slow rise time, see Figure 9-4.
FIGURE 9-3:
RC OSCILLATOR MODE
VDD
When the device starts normal operation (exits the
Reset condition), device operating parameters
(voltage, frequency, temperature,...) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met. Brown-out Reset may be used to
meet the start-up conditions.
REXT
Internal
OSC1
clock
CEXT
VSS
PIC16F716
OSC2/CLKOUT
FOSC/4
Recommended values:
FIGURE 9-4:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
3 kΩ ≤ REXT ≤ 100 kΩ (VDD ≥ 3.0V)
10 kΩ ≤ REXT ≤ 100 kΩ (VDD ≥ 3.0V)
CEXT > 20 pF
VDD VDD
R
9.3
Reset
R1
MCLR
The PIC16F716 differentiates between various kinds of
Reset:
PIC16F716
C
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during Sleep
Note 1: External Power-on Reset circuit is required
only if VDD power-up slope is too slow. The
diode D helps discharge the capacitor quickly
when VDD powers down.
• WDT Reset (during normal operation)
• WDT Wake-up (during Sleep)
• Brown-out Reset (BOR)
2: R < 40 kΩ is recommended to make sure that
voltage drop across R does not violate the
device’s electrical specification.
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR Reset during Sleep and Brown-
out Reset (BOR). They are not affected by a WDT
Wake-up, which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared differ-
ently in different Reset situations as indicated in
Table 9-4. These bits are used in software to determine
the nature of the Reset. See Table 9-6 for a full
description of Reset states of all registers.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor C
in the event of MCLR/VPP pin breakdown due
to Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
DS41206A-page 58
Preliminary
2003 Microchip Technology Inc.
PIC16F716
9.5
Power-up Timer (PWRT)
9.7
Programmable Brown-Out Reset
(PBOR)
The Power-up Timer provides a fixed nominal time-out,
on power-up only, from the POR. The Power-up Timer
operates on an internal RC oscillator. The chip is kept
in Reset as long as the PWRT is active. The PWRT’s
time delay allows VDD to rise to an acceptable level.
The power-up timer enable configuration bit, PWRTE,
is provided to enable/disable the PWRT.
The PIC16F716 has on-chip Brown-out Reset circuitry.
A configuration bit, BOREN, can disable (if clear/pro-
grammed) or enable (if set) the Brown-out Reset
circuitry.
The BORV configuration bit selects the programmable
Brown-out Reset threshold voltage (VBOR). When
BORV is 1, VBOR IS 4.0V. When BORV is 0, VBOR is
2.5V
The power-up time delay will vary from chip-to-chip due
to VDD, temperature and process variation. See AC
parameters for details.
A Brown-out Reset occurs when VDD falls below VBOR
for a time greater than parameter TBOR (see Table 12-4).
A Brown-out Reset is not guaranteed to occur if VDD falls
below VBOR for less than parameter TBOR.
9.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized. See
AC parameters for details.
On any Reset (Power-on, Brown-out, Watchdog, etc.)
the chip will remain in Reset until VDD rises above
VBOR. The Power-up Timer will be invoked and will
keep the chip in Reset an additional 72 ms only if the
Power-up Timer enable bit in the configuration register
is set to 0 (PWRTE = 0).
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
Sleep.
If the Power-up Timer is enabled and VDD drops below
VBOR while the Power-up Timer is running, the chip will
go back into a Brown-out Reset and the Power-up
Timer will be re-initialized. Once VDD rises above VBOR,
the Power-up Timer will execute a 72 ms Reset. See
Figure 9-6.
For operations where the desired brown-out voltage is
other than 4.0V or 2.5V, an external brown-out circuit
must be used. Figure 9-8, Figure 9-9 and Figure 9-10
show examples of external Brown-out Protection
circuits.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 59
PIC16F716
FIGURE 9-5:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
Sleep
WDT
WDT
Module
Time-out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset
S
R
BOREN
OST/PWRT
OST
10-bit Ripple counter
Chip_Reset
Q
OSC1
(1)
On-chip
RC OSC
PWRT
10-bit Ripple counter
PWRTE
See Table 9-3 for time-out
situations.
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
FIGURE 9-6:
BROWN-OUT SITUATIONS (PWRTE = 0
VDD
VBOR
Internal
Reset
72 ms
VDD
VBOR
Internal
Reset
<72 ms
72 ms
VDD
VBOR
Internal
Reset
72 ms
DS41206A-page 60
Preliminary
2003 Microchip Technology Inc.
PIC16F716
FIGURE 9-7:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
FIGURE 9-9:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 3
VDD
33k
VDD
VDD
MCP809
Vss
VDD
Q1
bypass
capacitor
10k
MCLR
VDD
40k
RST
PIC16F716
MCLR
PIC16F716
Note 1: This circuit will activate Reset when VDD goes
below (Vz + 0.7V) where Vz = Zener voltage.
2: Internal Brown-out Reset circuitry should be
disabled when using this circuit.
Note 1: This brown-out protection circuit employs
Microchip Technology’s MCP809
microcontroller supervisor. The MCP8XX and
MCP1XX families of supervisors provide
push-pull and open collector outputs with
both high and low active Reset pins. There
are 7 different trip point selections to
accommodate 5V and 3V systems.
FIGURE 9-8:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
VDD
R1
VDD
Q1
MCLR
R2
40k
PIC16F716
Note 1: This brown-out circuit is less expensive, albeit
less accurate. Transistor Q1 turns off when VDD
is below a certain level such that:
R1
= 0.7 V
VDD x
R1 + R2
2: Internal Brown-out Reset should be disabled
when using this circuit.
3: Resistors should be adjusted for the
characteristics of the transistor.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 61
PIC16F716
9.8
Time-out Sequence
9.9
Power Control/Status Register
(PCON)
On power-up, the time-out sequence is as follows: First
PWRT time-out is invoked after the POR time delay has
expired. Then OST is activated. The total time-out will
vary based on oscillator configuration and the status of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 9-10,
Figure 9-11, and Figure 9-12 depict time-out
sequences on power-up.
The Power Control/Status Register, PCON has two
bits.
Bit 0 is the Brown-out Reset Status bit, BOR. If the
BOREN configuration bit is set, BOR is ‘1’ on Power-on
Reset and reset to ‘0’ when a Brown-out condition
occurs. BOR must then be set by the user and checked
on subsequent resets to see if it is clear, indicating that
another Brown-out has occurred.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 9-12). This is useful for testing purposes or to
synchronize more than one PIC16F716 device
operating in parallel.
If the BOREN configuration bit is clear, BOR is
unknown on Power-on Reset.
Bit 1 is POR (Power-on Reset Status bit). It is cleared
on a Power-on Reset and unaffected otherwise. The
user must set this bit following a Power-on Reset.
Table 9-5 shows the Reset conditions for some special
function registers, while Table 9-6 shows the Reset
conditions for all the registers.
TABLE 9-3:
TIME-OUT IN VARIOUS SITUATIONS
Power-up or Brown-out
Oscillator Configuration
Wake-up from Sleep
PWRTE = 0
PWRTE = 1
XT, HS, LP
RC
72 ms + 1024 TOSC
72 ms
1024 TOSC
—
1024 TOSC
—
TABLE 9-4:
STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
0
x
1
1
1
1
1
Power-on Reset (BOREN = 0)
Power-on Reset (BOREN = 1)
0
x
0
x
Illegal, TO is set on POR
0
1
1
1
x
0
1
1
x
1
0
0
0
1
1
0
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
1
1
1
1
u
1
u
0
MCLR Reset during normal operation
MCLR Reset during Sleep or interrupt wake-up from Sleep
DS41206A-page 62
Preliminary
2003 Microchip Technology Inc.
PIC16F716
TABLE 9-5:
RESET CONDITION FOR SPECIAL REGISTERS
Program
Status
Register
PCON
Register
Condition
Counter
Power-on Reset (BOREN = 0)
Power-on Reset (BOREN = 1)
000h
000h
0001 1xxx
0001 1xxx
---- --0x
---- --01
MCLR Reset during normal operation
000h
000u uuuu
---- --uu
MCLR Reset during Sleep
WDT Reset
000h
000h
0001 0uuu
0000 1uuu
uuu0 0uuu
0001 1uuu
uuu1 0uuu
---- --uu
---- --uu
---- --uu
---- --u0
---- --uu
WDT Wake-up
PC + 1
Brown-out Reset
000h
(1)
Interrupt wake-up from Sleep
PC + 1
Legend: u= unchanged, x= unknown, -= unimplemented bit read as ‘0’.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 63
PIC16F716
TABLE 9-6:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS OF THE PIC16F716
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
W
xxxx xxxx
N/A
uuuu uuuu
N/A
uuuu uuuu
N/A
INDF
TMR0
xxxx xxxx
0000h
uuuu uuuu
0000h
uuuu uuuu
PC + 1(2)
PCL
STATUS
0001 1xxx
xxxx xxxx
--xx 0000
xxxx xxxx
---0 0000
0000 -00x
-0-- -000
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
-000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
00-0 0000
xxxx xxxx
0000 0000
1111 1111
--11 1111
1111 1111
-0-- -000
---- --qq
1111 1111
---- -000
000q quuu(3)
uuuu uuuu
--xx 0000
uuuu uuuu
---0 0000
0000 -00u
-0-- -000
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0000
-000 0000
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
00-0 0000
uuuu uuuu
0000 0000
1111 1111
--11 1111
1111 1111
-0-- -000
---- --uu
1111 1111
---- -000
uuuq quuu(3)
uuuu uuuu
--uu uuuu
uuuu uuuu
---u uuuu
uuuu -uuu(1)
-u-- -uuu(1)
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
-u-- -uuu
---- --uu
uuuu uuuu
---- -uuu
FSR
PORTA(4), (5), (6)
PORTB(4), (5)
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
PWM1CON
ECCPAS
ADRES
ADCON0
OPTION_REG
TRISA
TRISB
PIE1
PCON
PR2
ADCON1
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition
Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 9-5 for Reset value for specific condition.
4: On any device Reset, these pins are configured as inputs.
5: This is the value that will be in the port output latch.
6: Output latches are unknown or unchanged. Analog inputs default to analog and read ‘0’.
DS41206A-page 64
Preliminary
2003 Microchip Technology Inc.
PIC16F716
FIGURE 9-10:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 9-11:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 9-12:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 65
PIC16F716
The peripheral interrupt flags are contained in the
special function registers, PIR1 and PIR2. The
corresponding interrupt enable bits are contained in
special function registers, PIE1 and PIE2, and the
peripheral interrupt enable bit is contained in special
function register, INTCON.
9.10 Interrupts
The PIC16F716 devices have up to 7 sources of
interrupt. The Interrupt Control Register (INTCON)
records individual interrupt requests in flag bits. It also
has individual and global interrupt enable bits.
Note:
Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
A Global Interrupt Enable bit, GIE (INTCON<7>)
enables all un-masked interrupts when set, or disables
all interrupts when cleared. When bit GIE is enabled,
and an interrupt’s flag bit and mask bit are set, the
interrupt will vector immediately. Individual interrupts
can be disabled through their corresponding enable
bits in various registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on Reset and when an interrupt vector occurs.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two-cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit or the GIE bit.
The “return-from-interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
FIGURE 9-13:
INTERRUPT LOGIC
Wake-up (If in Sleep mode)
Interrupt to CPU
T0IF
T0IE
INTF
INTE
ADIF
ADIE
RBIF
RBIE
PEIE
GIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
DS41206A-page 66
Preliminary
2003 Microchip Technology Inc.
PIC16F716
9.10.1
INT INTERRUPT
9.11 Context Saving During Interrupts
External interrupt on RB0/INT pin is edge triggered,
either rising if bit INTEDG (OPTION_REG<6>) is set,
or falling if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service
routine before re-enabling this interrupt. The INT
interrupt can wake-up the processor from Sleep, if bit
INTE was set prior to going into Sleep. The status of
global interrupt enable bit GIE decides whether or not
the processor branches to the interrupt vector following
wake-up. See Section 9.13 “Power-down Mode
(Sleep)” for details on Sleep mode.
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt, (i.e., W register and Status
register). This will have to be implemented in firmware.
Example 9-1 stores and restores the W, Status,
PCLATH and FSR registers. Context storage registers,
W_TEMP, STATUS_TEMP, PCLATH_TEMP and
FSR_TEMP, must be defined in Common RAM which
are those addresses between 70h-7Fh in Bank 0 and
between F0h-FFh in Bank 1.
The example:
a) Stores the W register.
b) Stores the Status register in Bank 0.
c) Stores the PCLATH register
d) Stores the FSR register.
9.10.2
TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 4.0 “Timer0 Module”).
e) Executes the interrupt service routine code
(User-generated).
f) Restores all saved registers in reverse order
from which they were stored
9.10.3
PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 3.2 “PORTB and the TRISB Register”).
EXAMPLE 9-1:
SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
MOVWF
MOVF
MOVWF
CLRF
BCF
MOVF
MOVWF
:
W_TEMP
;Copy W to TEMP register, could be bank one or zero
STATUS,W
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
STATUS, IRP
FSR, W
FSR_TEMP
;Swap status to be saved into W
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
;Return to Bank 0
;Copy FSR to W
;Copy FSR from W to FSR_TEMP
:(ISR)
:
MOVF
MOVWF
MOVF
MOVWF
SWAPF
MOVWF
SWAPF
SWAPF
RETFIE
FSR_TEMP,W
FSR
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
;Restore FSR
;Move W into FSR
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
;Return from interrupt and enable GIE
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 67
PIC16F716
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 9.1 “Configuration
Bits”).
9.12 Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip, RC
oscillator which does not require any external
components. This RC oscillator is separate from the
RC oscillator of the OSC1/CLKIN pin. That means that
the WDT will run, even if the clock on the OSC1/CLKIN
and OSC2/CLKOUT pins of the device have been
stopped, for example, by execution of a SLEEPinstruc-
tion.
WDT time-out period values may be found in the
Electrical Specifications section under TWDT (parame-
ter #31). Values for the WDT prescaler (actually a
postscaler, but shared with the Timer0 prescaler) may
be assigned using the OPTION_REG register.
Note:
The CLRWDTand SLEEPinstructions clear
the WDT and the postscaler, if assigned to
the WDT, and prevent it from timing out
and generating a device Reset condition.
During normal operation, a WDT time-out generates a
device Reset (Watchdog Timer Reset). If the device is
in Sleep mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the Status register
will be cleared upon a Watchdog Timer time-out.
.
Note:
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
FIGURE 9-14:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source (Figure 4-2)
0
Postscaler
M
1
U
WDT Timer
X
8
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 4-2)
0
1
MUX
PSA
WDT
Time-out
Note:
PSA and PS2:PS0 are bits in the OPTION_REG register.
FIGURE 9-15:
SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
Bits 13:8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
(1)
(1)
—
—
2007h
81h
Config. bits
(1)
BORV
RBPU
BOREN
PWRTE
PSA
WDTE
PS2
FOSC1
PS1
FOSC0
PS0
OPTION_REG
N/A
INTEDG
T0CS T0SE
Legend:
Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 9-1 for operation of these bits.
DS41206A-page 68
Preliminary
2003 Microchip Technology Inc.
PIC16F716
The following peripheral interrupts can wake the device
from Sleep:
9.13 Power-down Mode (Sleep)
Power-down mode is entered by executing a SLEEP
instruction.
1. TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low or high-impedance).
2. ECCP capture mode interrupt.
3. ADC running in ADRC mode.
Other peripherals cannot generate interrupts, since
during Sleep, no on-chip clocks are present.
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the
execution of the instruction following SLEEP is not
desirable, the user should have a NOPafter the SLEEP
instruction.
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external
circuitry is drawing current from the I/O pin, power-
down the A/D and the disable external clocks. Pull all
I/O pins that are hi-impedance inputs, high or low
externally, to avoid switching currents caused by
floating inputs. The T0CKI input should also be at VDD
or VSS for lowest current consumption. The
contribution from on-chip pull-ups on PORTB should be
considered.
The MCLR pin must be at a logic high level (parameter
D042).
9.13.2
WAKE-UP USING INTERRUPTS
9.13.1
WAKE-UP FROM SLEEP
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
The device can wake-up from Sleep through one of the
following events:
1. External Reset input on MCLR pin.
• If the interrupt occurs before the execution of a
SLEEPinstruction, the SLEEPinstruction will
complete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change or some
peripheral interrupts.
External MCLR Reset will cause a device Reset. All
other events are considered a continuation of program
execution and cause a “wake-up”. The TO and PD bits
in the Status register can be used to determine the
cause of device Reset. The PD bit, which is set on
power-up, is cleared when Sleep is invoked. The TO bit
is cleared if a WDT time-out occurred (and caused
wake-up).
• If the interrupt occurs during or after the
execution of a SLEEPinstruction, the device will
immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT
instruction should be executed before a SLEEP
instruction.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 69
PIC16F716
FIGURE 9-16:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
TOST(2)
INTF flag
Interrupt Latency
(INTCON<1>)
(Note 3)
GIE bit
Processor in
Sleep
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = Sleep
fetched
Instruction
executed
Dummy cycle
Dummy cycle
Sleep
Inst(PC + 1)
Inst(PC - 1)
Inst(0004h)
Note 1:
XT, HS or LP Oscillator mode assumed.
TOST = 1024TOSC (drawing not to scale). This delay will not be there for RC Osc mode.
GIE = ‘1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = ‘0’, execution will continue in-line.
2:
3:
4:
CLKOUT is not available in these osc modes, but shown here for timing reference.
9.14 Program Verification/Code
Protection
9.16
In-Circuit Serial Programming™
PIC16F716
microcontrollers
can
be
serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
If the code protection bit has not been programmed, the
on-chip program memory can be read out for
verification purposes.
9.15 ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution, but are
readable and writable during program/verify. It is
recommended that only the 4 Least Significant bits of
the ID location are used.
For complete details on serial programming, please
refer to the In-Circuit Serial Programming™ (ICSP™)
Specification, (DS40245).
DS41206A-page 70
Preliminary
2003 Microchip Technology Inc.
PIC16F716
The instruction set is highly orthogonal and is grouped
into three basic categories:
10.0 INSTRUCTION SET SUMMARY
Each PIC16F716 instruction is a 14-bit word divided
into an opcode which specifies the instruction type and
one or more operands which further specify the
operation of the instruction. The PIC16F716 instruction
set summary in Table 10-2 lists byte-oriented, bit-
oriented, and literal and control operations.
Table 10-1 shows the opcode field descriptions.
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of an
instruction. In this case, the execution takes two
instruction cycles with the second cycle executed as a
NOP. One instruction cycle consists of four oscillator
periods. Thus, for an oscillator frequency of 4 MHz, the
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
normal instruction execution time is 1 µs. If
a
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
conditional test is true or the program counter is
changed as a result of an instruction, the instruction
execution time is 2 µs.
Table 10-2 lists the instructions recognized by the
MPASM™ assembler.
For bit-oriented instructions, ‘b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ‘f’ represents the number of the
file in which the bit is located.
Figure 10-1 shows the three general formats that the
instructions can have.
For literal and control operations, ‘k’ represents an
eight or eleven bit constant or literal value.
Note 1: Any unused opcode is reserved. Use of
any reserved opcode may cause
unexpected operation.
TABLE 10-1: OPCODE FIELD
DESCRIPTIONS
2: To maintain upward compatibility with
future PICmicro products, do not use the
OPTIONand TRISinstructions.
Field
Description
All examples use the following format to represent a
hexadecimal number:
f
Register file address (0x00 to 0x7F)
Working register (accumulator)
W
b
Bit address within an 8-bit file register
Literal field, constant data or label
0xhh
k
where h signifies a hexadecimal digit.
x
Don't care location (= 0or 1)
The assembler will generate code with x = 0. It is the rec-
ommended form of use for compatibility with all Microchip
software tools.
FIGURE 10-1:
GENERAL FORMAT FOR
INSTRUCTIONS
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
Byte-oriented file register operations
13
8
7
6
0
label
TOS
PC
Label name
OPCODE
d
f (FILE #)
Top of Stack
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Program Counter
PCLATH Program Counter High Latch
GIE
WDT
TO
Global Interrupt Enable bit
Watchdog Timer/Counter
Time-out bit
Bit-oriented file register operations
13 10 9
b (BIT #)
7 6
0
PD
Power-down bit
OPCODE
f (FILE #)
dest
Destination either the W register or the specified register
file location
b = 3-bit address
f = 7-bit file register address
[ ]
( )
→
Options
Contents
Literal and control operations
Assigned to
General
13
< >
Register bit field
In the set of
8 7
0
0
OPCODE
k (literal)
italics
User defined term (font is courier)
k = 8-bit immediate value
CALLand GOTOinstructions only
13
11 10
OPCODE
k (literal)
k = 11-bit immediate value
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 71
PIC16F716
TABLE 10-2: PIC16F716 INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Description
Operands
Status
Affected
Cycles
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111 dfff ffff C,DC,Z
1,2
1,2
2
0101 dfff ffff
0001 lfff ffff
0001 0xxx xxxx
1001 dfff ffff
0011 dfff ffff
1011 dfff ffff
1010 dfff ffff
1111 dfff ffff
0100 dfff ffff
1000 dfff ffff
0000 lfff ffff
0000 0xx0 0000
1101 dfff ffff
1100 dfff ffff
Z
Z
Z
Z
Z
—
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
(2)
DECFSZ
INCF
1
1
Z
(2)
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
1
1
1
1
1
1
1
1
1
1
Z
Z
Move W to f
No Operation
—
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
0010 dfff ffff C,DC,Z
1110 dfff ffff
0110 dfff ffff
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
01
01
01
01
00bb bfff ffff
01bb bfff ffff
10bb bfff ffff
11bb bfff ffff
1,2
1,2
3
(2)
1
(2)
1
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
—
k
k
k
—
k
—
—
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x kkkk kkkk C,DC,Z
1001 kkkk kkkk
0kkk kkkk kkkk
Z
0000 0110 0100 TO,PD
1kkk kkkk kkkk
Inclusive OR literal with W
Move literal to W
1000 kkkk kkkk
00xx kkkk kkkk
0000 0000 1001
01xx kkkk kkkk
0000 0000 1000
Z
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
0000 0110 0011 TO,PD
110x kkkk kkkk C,DC,Z
1010 kkkk kkkk Z
k
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the
pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data
will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the
Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed
as a NOP.
DS41206A-page 72
Preliminary
2003 Microchip Technology Inc.
PIC16F716
10.1 Instruction Descriptions
ADDLW
Add Literal and W
ANDLW
AND Literal with W
Syntax:
[ label ] ADDLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
k
Operands:
Operation:
Status Affected:
Encoding:
Operands:
Operation:
Status Affected:
Encoding:
(W) + k → (W)
C, DC, Z
(W) .AND. (k) → (W)
Z
11
111x
kkkk
kkkk
11
1001
kkkk
kkkk
Description:
The contents of the W register
are added to the eight bit literal
‘k’ and the result is placed in the
W register.
Description:
The contents of W register are
AND’ed with the eight bit literal
‘k’. The result is placed in the W
register.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
ADDLW
0x15
ANDLW
0x5F
Before Instruction
W = 0x10
Before Instruction
W = 0xA3
After Instruction
W = 0x25
After Instruction
W = 0x03
ANDWF
AND W with f
ADDWF
Add W and f
Syntax:
[ label ] ANDWF f,d
0 ≤ f ≤ 127
Syntax:
[ label ] ADDWF f,d
0 ≤ f ≤ 127
Operands:
d
[0,1]
Operands:
d
[0,1]
Operation:
(W) .AND. (f) → (dest)
Operation:
(W) + (f) → (dest)
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
C, DC, Z
00
0101
dfff
ffff
00
0111
dfff
ffff
Description:
AND the W register with register
‘f’. If ‘d’ is 0 the result is stored in
the W register. If ‘d’ is 1 the
result is stored back in register
‘f’.
Description:
Add the contents of the W
register with register ‘f’. If ‘d’ is 0
the result is stored in the W
register. If ‘d’ is 1 the result is
stored back in register ‘f’.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
ANDWF
REG1, 1
ADDWF
REG1, 0
Before Instruction
W
= 0x17
Before Instruction
REG1 = 0xC2
W
= 0x17
After Instruction
= 0x17
REG1 = 0x02
REG1 = 0xC2
W
After Instruction
= 0xD9
REG1 = 0xC2
W
Z
C
DC
= 0
= 0
= 0
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 73
PIC16F716
BCF
Bit Clear f
BTFSC
Bit Test f, Skip if Clear
Syntax:
[ label ] BCF f,b
Syntax:
[ label ] BTFSC f,b
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
Status Affected:
Encoding:
Description:
Words:
0 → (f<b>)
Operation:
skip if (f<b>) = 0
None
None
Status Affected:
Encoding:
01
00bb
bfff
ffff
01
10bb
bfff
ffff
Bit ‘b’ in register ‘f’ is cleared.
Description:
If bit ‘b’ in register ‘f’ is ‘0’ then the
next instruction is skipped.
If bit ‘b’ is ‘0’ then the next
instruction fetched during the
current instruction execution is
discarded, and a NOPis executed
instead, making this a two-cycle
instruction.
1
1
Cycles:
BCF
REG1, 7
Example
Before Instruction
REG1 = 0xC7
After Instruction
REG1 = 0x47
Words:
Cycles:
Example
1
1(2)
HERE
FALSE
TRUE
BTFSC
GOTO
•
•
•
REG1
PROCESS_CODE
BSF
Bit Set f
Syntax:
[ label ] BSF f,b
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Before Instruction
PC = address HERE
After Instruction
if REG<1> = 0,
Operation:
Status Affected:
Encoding:
Description:
Words:
1 → (f<b>)
None
01
01bb
bfff
ffff
PC = address TRUE
if REG<1>=1,
PC = address FALSE
Bit ‘b’ in register ‘f’ is set.
1
1
Cycles:
BSF
REG1, 7
Example
Before Instruction
REG1 = 0x0A
After Instruction
REG1 = 0x8A
DS41206A-page 74
Preliminary
2003 Microchip Technology Inc.
PIC16F716
BTFSS
Bit Test f, Skip if Set
CALL
Call Subroutine
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CALL k
0 ≤ k ≤ 2047
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
(PC)+ 1→ TOS,
Operation:
skip if (f<b>) = 1
None
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Status Affected:
Encoding:
Status Affected:
Encoding:
None
01
11bb
bfff
ffff
10
0kkk
kkkk
kkkk
Description:
If bit ‘b’ in register ‘f’ is ‘1’ then the
next instruction is skipped.
If bit ‘b’ is ‘1’, then the next
instruction fetched during the
current instruction execution, is
discarded and a NOPis executed
instead, making this a two-cycle
instruction.
Description:
Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven bit
immediate address is loaded
into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALL is a two-cycle
instruction.
Words:
Cycles:
Example
1
Words:
Cycles:
Example
1
2
1(2)
HERE
FALSE
TRUE
BTFSS
GOTO
•
•
•
REG1
PROCESS_CODE
HERE
CALL
THERE
Before Instruction
PC Address HERE
After Instruction
PC Address THERE
TOS = Address HERE+1
=
Before Instruction
PC = address HERE
After Instruction
=
if FLAG<1> = 0,
PC = address FALSE
if FLAG<1> = 1,
PC = address TRUE
CLRF
Clear f
Syntax:
[ label ] CLRF
0 ≤ f ≤ 127
f
Operands:
Operation:
00h → (f)
1 → Z
Status Affected:
Encoding:
Z
00
0001
1fff
ffff
Description:
The contents of register ‘f’ are
cleared and the Z bit is set.
Words:
Cycles:
Example
1
1
CLRF
REG1
Before Instruction
REG1
After Instruction
=
0x5A
REG1
Z
=
=
0x00
1
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 75
PIC16F716
CLRW
Clear W
COMF
Complement f
Syntax:
[ label ] CLRW
Syntax:
[ label ] COMF f,d
0 ≤ f ≤ 127
Operands:
Operation:
None
Operands:
d
[0,1]
00h → (W)
1 → Z
Operation:
(f) → (dest)
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
Z
00
0001
0000
0011
00
1001
dfff
ffff
Description:
W register is cleared. Zero bit
(Z) is set.
Description:
The contents of register ‘f’ are
complemented. If ‘d’ is 0 the
result is stored in W. If ‘d’ is 1
the result is stored back in
register ‘f’.
Words:
Cycles:
Example
1
1
CLRW
Words:
Cycles:
Example
1
1
Before Instruction
W = 0x5A
After Instruction
W = 0x00
COMF
REG1, 0
Before Instruction
REG1 = 0x13
After Instruction
REG1 = 0x13
Z = 1
W
= 0xEC
CLRWDT
Clear Watchdog Timer
DECF
Decrement f
Syntax:
[ label ] CLRWDT
Syntax:
[ label ] DECF f,d
0 ≤ f ≤ 127
Operands:
Operation:
None
Operands:
d
[0,1]
00h → WDT
0 → WDT prescaler,
1 → TO
Operation:
(f) - 1 → (dest)
Status Affected:
Encoding:
Z
1 → PD
00
0011
dfff
ffff
Status Affected:
Encoding:
TO, PD
Description:
Decrement register ‘f’. If ‘d’ is 0
the result is stored in the W
register. If ‘d’ is 1 the result is
stored back in register ‘f’.
00
0000
0110
0100
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets
the prescaler of the WDT. Status
bits TO and PD are set.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
DECF
CNT, 1
1
Before Instruction
CNT = 0x01
= 0
After Instruction
CNT = 0x00
= 1
CLRWDT
Before Instruction
WDT counter = ?
After Instruction
Z
WDT counter = 0x00
WDT prescaler = 0
Z
TO
PD
= 1
= 1
DS41206A-page 76
Preliminary
2003 Microchip Technology Inc.
PIC16F716
DECFSZ
Syntax:
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0 ≤ f ≤ 127
GOTO
Unconditional Branch
Syntax:
[ label ] GOTO k
0 ≤ k ≤ 2047
Operands:
Operands:
Operation:
d
[0,1]
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Operation:
(f) - 1 → (dest); skip if result =
0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
10
1kkk
kkkk
kkkk
00
1011
dfff
ffff
Description:
GOTOis an unconditional
branch. The eleven-bit
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is 0 the result
is placed in the W register. If ‘d’
is 1 the result is placed back in
register ‘f’.
If the result is 0, the next
instruction, which is already
fetched, is discarded. A NOPis
executed instead making it a
two-cycle instruction.
immediate value is loaded into
PC bits <10:0>. The upper bits
of PC are loaded from
PCLATH<4:3>. GOTOis a
two-cycle instruction.
Words:
Cycles:
Example
1
2
GOTO THERE
Words:
Cycles:
Example
1
After Instruction
1(2)
PC = Address THERE
HERE
DECFSZ
GOTO
REG1, 1
LOOP
CONTINUE •
•
•
Before Instruction
PC
After Instruction
REG1 = REG1 - 1
= address HERE
if REG1 = 0,
PC = address CONTINUE
if REG1 ≠ 0,
PC
= address HERE+1
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 77
PIC16F716
INCF
Increment f
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] INCF f,d
0 ≤ f ≤ 127
Syntax:
[ label ] INCFSZ f,d
0 ≤ f ≤ 127
Operands:
Operands:
d
[0,1]
d
[0,1]
Operation:
(f) + 1 → (dest)
Operation:
(f) + 1 → (dest), skip if result = 0
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
None
00
1010
dfff
ffff
00
1111
dfff
ffff
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is 0 the result
is placed in the W register. If ‘d’
is 1 the result is placed back in
register ‘f’.
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is 0 the result
is placed in the W register. If ‘d’
is 1 the result is placed back in
register ‘f’.
If the result is 0, the next
instruction, which is already
fetched, is discarded. A NOPis
executed instead making it a
two-cycle instruction.
Words:
Cycles:
Example
1
1
INCF
REG1, 1
Before Instruction
REG1 = 0xFF
= 0
After Instruction
REG1 = 0x00
= 1
Words:
Cycles:
Example
1
Z
1(2)
HERE
INCFSZ
GOTO
REG1, 1
LOOP
Z
CONTINUE •
•
•
Before Instruction
PC
= address HERE
After Instruction
REG1 = REG1 + 1
if CNT = 0,
PC = address CONTINUE
if REG1≠ 0,
PC
= address HERE +1
DS41206A-page 78
Preliminary
2003 Microchip Technology Inc.
PIC16F716
IORLW
Inclusive OR Literal with W
MOVLW
Move Literal to W
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
[ label ] MOVLW k
0 ≤ k ≤ 255
k → (W)
Operands:
Operation:
Status Affected:
Encoding:
Operands:
Operation:
Status Affected:
Encoding:
(W) .OR. k → (W)
Z
None
11
1000
kkkk
kkkk
11
00xx
kkkk
kkkk
Description:
The contents of the W register is
OR’ed with the eight bit literal ‘k’.
The result is placed in the W
register.
Description:
The eight bit literal ‘k’ is loaded
into W register. The don’t cares
will assemble as ‘0’s.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
MOVLW
0x5A
IORLW
0x35
After Instruction
W = 0x5A
Before Instruction
W = 0x9A
After Instruction
W = 0xBF
Z = 0
IORWF
Inclusive OR W with f
MOVF
Move f
Syntax:
[ label ] IORWF f,d
0 ≤ f ≤ 127
Syntax:
[ label ] MOVF f,d
0 ≤ f ≤ 127
Operands:
Operands:
d
[0,1]
d
[0,1]
Operation:
(W) .OR. (f) → (dest)
Operation:
(f) → (dest)
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
Z
00
0100
dfff
ffff
00
1000
dfff
ffff
Description:
Inclusive OR the W register with
register ‘f’. If ‘d’ is 0 the result is
placed in the W register. If ‘d’ is
1 the result is placed back in
register ‘f’.
Description:
The contents of register ‘f’ is
moved to a destination
dependent upon the status of
‘d’. If ‘d’ = 0, destination is W
register. If ‘d’ = 1, the destination
is file register ‘f’ itself. ‘d’ = 1 is
useful to test a file register since
status flag Z is affected.
Words:
Cycles:
Example
1
1
IORWF
REG1, 0
Words:
Cycles:
Example
1
1
Before Instruction
REG1 = 0x13
MOVF
REG1, 0
W
= 0x91
After Instruction
REG1 = 0x13
After Instruction
W= value in REG1 register
W
Z
= 0x93
= 1
Z =
1
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 79
PIC16F716
MOVWF
Move W to f
OPTION
Load Option Register
Syntax:
[ label ] OPTION
None
Syntax:
[ label ] MOVWF
0 ≤ f ≤ 127
(W) → (f)
f
Operands:
Operation:
Status Affected:
Encoding:
Operands:
Operation:
Status Affected:
Encoding:
(W) → OPTION
None
None
00
0000
0110
0010
00
0000
1fff
ffff
Description:
The contents of the W register are
loaded in the OPTION register.
This instruction is supported for
code compatibility with PIC16C5X
products. Since OPTION is a
readable/writable register, the
user can directly address it. Using
only register instruction such as
MOVWF.
Description:
Move data from W register to
register ‘f’.
Words:
Cycles:
Example
1
1
MOVWF
REG1
Before Instruction
REG1 = 0xFF
W
= 0x4F
Words:
Cycles:
Example
1
1
After Instruction
REG1 = 0x4F
W
= 0x4F
To maintain upward compatibil-
ity with future PICmicro®
products, do not use this
instruction.
RETFIE
Return from Interrupt
NOP
No Operation
Syntax:
[ label ] RETFIE
Syntax:
[ label ] NOP
None
Operands:
Operation:
None
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
TOS → PC,
1 → GIE
No operation
None
Status Affected:
Encoding:
None
00
0000
0xx0
0000
00
0000
0000
1001
No operation.
Description:
Return from Interrupt. Stack is
POPed and Top of Stack (TOS)
is loaded in the PC. Interrupts
are enabled by setting Global
Interrupt Enable bit, GIE
1
Cycles:
1
NOP
Example
(INTCON<7>). This is a
two-cycle instruction.
Words:
Cycles:
Example
1
2
RETFIE
After Interrupt
PC = TOS
GIE =
1
DS41206A-page 80
Preliminary
2003 Microchip Technology Inc.
PIC16F716
RETLW
Return with Literal in W
RLF
Rotate Left f through Carry
Syntax:
[ label ] RETLW k
0 ≤ k ≤ 255
Syntax:
[ label ] RLF f,d
0 ≤ f ≤ 127
Operands:
Operation:
Operands:
d
[0,1]
k → (W);
TOS → PC
Operation:
See description below
C
Status Affected:
Encoding:
None
Status Affected:
Encoding:
11
01xx
kkkk
kkkk
00
1101
dfff
ffff
Description:
The W register is loaded with
the eight bit literal ‘k’. The
program counter is loaded from
the top of the stack (the return
address). This is a two-cycle
instruction.
Description:
The contents of register ‘f’ are
rotated one bit to the left through
the Carry Flag. If ‘d’ is 0 the result
is placed in the W register. If ‘d’ is
1 the result is stored back in
register ‘f’.
C
REGISTER F
Words:
Cycles:
Example
1
2
Words:
Cycles:
Example
1
CALL TABLE;W contains table
;offset value
•
•
•
1
;W now has table value
RLF
REG1, 0
Before Instruction
TABLE
REG1=1110 0110
ADDWF PC;W = offset
C
= 0
RETLW k1;Begin table
After Instruction
RETLW k2;
•
REG1=1110 0110
•
•
W
C
= 1100 1100
= 1
RETLW kn; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8
RETURN
Return from Subroutine
Syntax:
[ label ] RETURN
None
Operands:
Operation:
Status Affected:
Encoding:
TOS → PC
None
00
0000
0000
1000
Description:
Return from subroutine. The
stack is POPed and the top of
the stack (TOS) is loaded into
the program counter. This is a
two-cycle instruction.
Words:
Cycles:
Example
1
2
RETURN
After Interrupt
PC = TOS
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 81
PIC16F716
RRF
Rotate Right f through Carry
SUBLW
Subtract W from Literal
Syntax:
[ label ] RRF f,d
0 ≤ f ≤ 127
Syntax:
[ label ]
SUBLW k
Operands:
Operands:
Operation:
0 ≤ k ≤ 255
d
[0,1]
k - (W) → (W)
Operation:
See description below
C
Status
Affected:
C, DC, Z
Status Affected:
Encoding:
00
1100
dfff
ffff
11
110x
kkkk
kkkk
Encoding:
Description:
The contents of register ‘f’ are
rotated one bit to the right
through the Carry Flag. If ‘d’ is 0
the result is placed in the W
register. If ‘d’ is 1 the result is
placed back in register ‘f’.
Description:
The W register is subtracted (2’s
complement method) from the eight
bit literal ‘k’. The result is placed in
the W register.
Words:
1
1
Cycles:
C
REGISTER F
SUBLW
0x02
Example 1:
Before Instruction
W = 1
Words:
Cycles:
Example
1
1
C
= ?
RRF
REG1, 0
After Instruction
Before Instruction
REG1 = 1110 0110
= 0
After Instruction
REG1 = 1110 0110
W = 1
C
= 1; result is positive
C
Example 2:
Example 3:
Before Instruction
W = 2
C = ?
W
C
= 0111 0011
= 0
After Instruction
W = 0
C = 1; result is zero
Before Instruction
SLEEP
Syntax:
[ label ] SLEEP
W =
C =
3
?
Operands:
Operation:
None
00h → WDT,
0 → WDT prescaler,
1 → TO,
After Instruction
W = 0xFF
C = 0; result is negative
0 → PD
Status Affected:
Encoding:
TO, PD
00
0000
0110
0011
Description:
The power-down Status bit, PD
is cleared. Time out Status bit,
TO is set. Watchdog Timer and
its prescaler are cleared.
The processor is put into Sleep
mode with the oscillator
stopped.
Words:
1
Cycles:
Example:
1
SLEEP
DS41206A-page 82
Preliminary
2003 Microchip Technology Inc.
PIC16F716
SUBWF
Subtract W from f
SWAPF
Swap Nibbles in f
Syntax:
[ label ]
SUBWF f,d
Syntax:
[ label ]
SWAPF f,d
Operands:
0 ≤ f ≤ 127
Operands:
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(f) - (W) → (dest)
Operation:
(f<3:0>) → (dest<7:4>),
(f<7:4>) → (dest<3:0>)
Status
C, DC, Z
Affected:
Status Affected:
Encoding:
None
00
0010
dfff
ffff
00
1110
dfff
ffff
Encoding:
Description:
Subtract (2’s complement method)
W register from register ‘f’. If ‘d’ is 0
the result is stored in the W register.
If ‘d’ is 1 the result is stored back in
register ‘f’.
Description:
The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
0 the result is placed in W
register. If ‘d’ is 1 the result is
placed in register ‘f’.
Words:
1
1
Words:
Cycles:
Example
1
1
Cycles:
SUBWF
REG1, 1
SWAPF
REG1, 0
Example 1:
Before Instruction
REG1 = 3
Before Instruction
REG1 = 0xA5
After Instruction
REG1 = 0xA5
0x5A
W
C
= 2
= ?
After Instruction
W
=
REG1 = 1
W
C
= 2
= 1; result is positive
TRIS
Load TRIS Register
Z
DC
= 0
= 1
Syntax:
[ label ] TRIS
5 ≤ f ≤ 6
f
Operands:
Operation:
Status Affected:
Encoding:
Description:
Example 2:
Before Instruction
(W) → TRIS register f;
REG1 = 2
W
C
None
= 2
= ?
00
0000
0110
0fff
The instruction is supported for
code compatibility with the
PIC16C5X products. Since TRIS
registers are readable and
writable, the user can directly
address them.
After Instruction
REG1 = 0
W
C
Z
= 2
= 1; result is zero
= DC = 1
Example 3:
Before Instruction
Words:
Cycles:
Example
1
1
REG1 = 1
W
C
= 2
= ?
To maintain upward compatibil-
ity with future PICmicro®
products, do not use this
instruction.
After Instruction
REG1 = 0xFF
W
C
Z
= 2
= 0; result is negative
= DC = 0
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 83
PIC16F716
XORLW
Exclusive OR Literal with W
XORWF
Exclusive OR W with f
Syntax:
[ label ] XORLW k
0 ≤ k ≤ 255
Syntax:
[ label ]
XORWF f,d
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 ≤ f ≤ 127
d
[0,1]
(W) .XOR. k → (W)
Z
Operation:
(W) .XOR. (f) → (dest)
Status Affected:
Encoding:
Z
11
1010
kkkk
kkkk
00
0110
dfff
ffff
Description:
The contents of the W register
are XOR’ed with the eight bit
literal ‘k’. The result is placed in
the W register.
Description:
Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
0 the result is stored in the W
register. If ‘d’ is 1 the result is
stored back in register ‘f’.
Words:
1
1
Cycles:
Example:
Words:
Cycles:
Example
1
1
XORLW
0xAF
Before Instruction
W = 0xB5
XORWF
REG1, 1
Before Instruction
REG1 = 0xAF
0xB5
After Instruction
W = 0x1A
W
=
After Instruction
REG1 = 0x1A
0xB5
W
=
DS41206A-page 84
Preliminary
2003 Microchip Technology Inc.
PIC16F716
11.1 MPLAB Integrated Development
Environment Software
11.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
• An interface to debugging tools
- simulator
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor with color coded context
• A multiple project manager
- MPLAB C30 C Compiler
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
• Customizable data windows with direct edit of
contents
- MPLAB SIM Software Simulator
- MPLAB dsPIC30 Software Simulator
• Emulators
• High level source code debugging
• Mouse over variable inspection
• Extensive on-line help
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
• In-Circuit Debugger
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
- MPLAB ICD 2
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools
(automatically updates all project information)
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Development Programmer
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM.netTM Demonstration Board
- PICDEM 2 Plus Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 4 Demonstration Board
- PICDEM 17 Demonstration Board
- PICDEM 18R Demonstration Board
- PICDEM LIN Demonstration Board
- PICDEM USB Demonstration Board
• Evaluation Kits
• Debug using:
- source files (assembly or C)
- absolute listing file (mixed assembly and C)
- machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost effective
simulators, through low cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increasing flexibility
and power.
11.2 MPASM Assembler
®
- KEELOQ
The MPASM assembler is a full-featured, universal
macro assembler for all PICmicro MCUs.
- PICDEM MSC
- microID®
- CAN
The MPASM assembler generates relocatable object
files for the MPLINK object linker, Intel® standard hex
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
- PowerSmart®
- Analog
The MPASM assembler features include:
• Integration into MPLAB IDE projects
• User defined macros to streamline assembly code
• Conditional assembly for multi-purpose source
files
• Directives that allow complete control over the
assembly process
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 85
PIC16F716
11.3 MPLAB C17 and MPLAB C18
C Compilers
11.6 MPLAB ASM30 Assembler, Linker,
and Librarian
The MPLAB C17 and MPLAB C18 Code Development
MPLAB ASM30 assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 compiler uses the
assembler to produce it’s object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
Systems are complete ANSI
C
compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
11.4 MPLINK Object Linker/
MPLIB Object Librarian
• Rich directive set
• Flexible macro language
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can link
relocatable objects from pre-compiled libraries, using
directives from a linker script.
• MPLAB IDE compatibility
11.7 MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any pin. The
execution can be performed in Single-Step, Execute
Until Break, or Trace mode.
The MPLIB object librarian manages the creation and
modification of library files of pre-compiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool.
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
11.5 MPLAB C30 C Compiler
11.8 MPLAB SIM30 Software Simulator
The MPLAB C30 C compiler is a full-featured, ANSI
compliant, optimizing compiler that translates standard
ANSI C programs into dsPIC30F assembly language
source. The compiler also supports many command-
line options and language extensions to take full
advantage of the dsPIC30F device hardware capabili-
ties, and afford fine control of the compiler code
generator.
The MPLAB SIM30 software simulator allows code
development in a PC hosted environment by simulating
the dsPIC30F series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any of the pins.
The MPLAB SIM30 simulator fully supports symbolic
debugging using the MPLAB C30 C Compiler and
MPLAB ASM30 assembler. The simulator runs in either
a Command Line mode for automated tasks, or from
MPLAB IDE. This high speed simulator is designed to
debug, analyze and optimize time intensive DSP
routines.
MPLAB C30 is distributed with a complete ANSI C
standard library. All library functions have been vali-
dated and conform to the ANSI C library standard. The
library includes functions for string manipulation,
dynamic memory allocation, data conversion, time-
keeping, and math functions (trigonometric, exponen-
tial and hyperbolic). The compiler provides symbolic
information for high level source debugging with the
MPLAB IDE.
DS41206A-page 86
Preliminary
2003 Microchip Technology Inc.
PIC16F716
11.9 MPLAB ICE 2000
High Performance Universal
11.11 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low cost, run-time development tool,
connecting to the host PC via an RS-232 or high speed
USB interface. This tool is based on the Flash
PICmicro MCUs and can be used to develop for these
and other PICmicro microcontrollers. The MPLAB
ICD 2 utilizes the in-circuit debugging capability built
into the Flash devices. This feature, along with
In-Circuit Emulator
The MPLAB ICE 2000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers. Software control of the
MPLAB ICE 2000 in-circuit emulator is advanced by
the MPLAB Integrated Development Environment,
which allows editing, building, downloading and source
debugging from a single environment.
Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM
)
protocol, offers cost effective in-circuit Flash debugging
from the graphical user interface of the MPLAB Inte-
grated Development Environment. This enables a
designer to develop and debug source code by setting
breakpoints, single-stepping and watching variables,
CPU status and peripheral registers. Running at full
speed enables testing hardware and applications in
real-time. MPLAB ICD 2 also serves as a development
programmer for selected PICmicro devices.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitor-
ing features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLAB ICE 2000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
11.12 PRO MATE II Universal Device
Programmer
The PRO MATE II is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maximum reliability. It features
an LCD display for instructions and error messages
and a modular detachable socket assembly to support
various package types. In Stand-alone mode, the
PRO MATE II device programmer can read, verify, and
program PICmicro devices without a PC connection. It
can also set code protection in this mode.
11.10 MPLAB ICE 4000
High Performance Universal
In-Circuit Emulator
The MPLAB ICE 4000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for high-
end PICmicro microcontrollers. Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debugging from a single environment.
11.13 PICSTART Plus Development
Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus development programmer supports
most PICmicro devices up to 40 pins. Larger pin count
devices, such as the PIC16C92X and PIC17C76X,
may be supported with an adapter socket. The
PICSTART Plus development programmer is CE
compliant.
The MPLAB ICD 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high speed perfor-
mance for dsPIC30F and PIC18XXXX devices. Its
advanced emulator features include complex triggering
and timing, up to 2 Mb of emulation memory, and the
ability to view variables in real-time.
The MPLAB ICE 4000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 87
PIC16F716
11.14 PICDEM 1 PICmicro
Demonstration Board
11.17 PICDEM 3 PIC16C92X
Demonstration Board
The PICDEM 1 demonstration board demonstrates the
capabilities of the PIC16C5X (PIC16C54 to
PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,
PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All
necessary hardware and software is included to run
basic demo programs. The sample microcontrollers
provided with the PICDEM 1 demonstration board can
be programmed with a PRO MATE II device program-
mer, or a PICSTART Plus development programmer.
The PICDEM 1 demonstration board can be connected
to the MPLAB ICE in-circuit emulator for testing. A
prototype area extends the circuitry for additional appli-
cation components. Features include an RS-232
interface, a potentiometer for simulated analog input,
push button switches and eight LEDs.
The PICDEM 3 demonstration board supports the
PIC16C923 and PIC16C924 in the PLCC package. All
the necessary hardware and software is included to run
the demonstration programs.
11.18 PICDEM 4 8/14/18-Pin
Demonstration Board
The PICDEM 4 can be used to demonstrate the capa-
bilities of the 8-, 14-, and 18-pin PIC16XXXX and
PIC18XXXX MCUs, including the PIC16F818/819,
PIC16F87/88, PIC16F62XA and the PIC18F1320 fam-
ily of microcontrollers. PICDEM 4 is intended to show-
case the many features of these low pin count parts,
including LIN and Motor Control using ECCP. Special
provisions are made for low power operation with the
super capacitor circuit, and jumpers allow on-board
hardware to be disabled to eliminate current draw in
this mode. Included on the demo board are provisions
for Crystal, RC or Canned Oscillator modes, a five volt
regulator for use with a nine volt wall adapter or battery,
DB-9 RS-232 interface, ICD connector for program-
ming via ICSP and development with MPLAB ICD 2,
2x16 liquid crystal display, PCB footprints for H-Bridge
motor driver, LIN transceiver and EEPROM. Also
included are: header for expansion, eight LEDs, four
potentiometers, three push buttons and a prototyping
area. Included with the kit is a PIC16F627A and a
PIC18F1320. Tutorial firmware is included along with
the User’s Guide.
11.15 PICDEM.net Internet/Ethernet
Demonstration Board
The PICDEM.net demonstration board is an Internet/
Ethernet demonstration board using the PIC18F452
microcontroller and TCP/IP firmware. The board
supports any 40-pin DIP device that conforms to the
standard pinout used by the PIC16F877 or
PIC18C452. This kit features a user friendly TCP/IP
stack, web server with HTML, a 24L256 Serial
EEPROM for Xmodem download to web pages into
Serial EEPROM, ICSP/MPLAB ICD 2 interface con-
nector, an Ethernet interface, RS-232 interface, and a
16 x 2 LCD display. Also included is the book and
CD-ROM “TCP/IP Lean, Web Servers for Embedded
Systems,” by Jeremy Bentham
11.19 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. A pro-
grammed sample is included. The PRO MATE II device
programmer, or the PICSTART Plus development pro-
grammer, can be used to reprogram the device for user
tailored application development. The PICDEM 17
demonstration board supports program download and
execution from external on-board Flash memory. A
generous prototype area is available for user hardware
expansion.
11.16 PICDEM 2 Plus
Demonstration Board
The PICDEM 2 Plus demonstration board supports
many 18-, 28-, and 40-pin microcontrollers, including
PIC16F87X and PIC18FXX2 devices. All the neces-
sary hardware and software is included to run the dem-
onstration programs. The sample microcontrollers
provided with the PICDEM 2 demonstration board can
be programmed with a PRO MATE II device program-
mer, PICSTART Plus development programmer, or
MPLAB ICD 2 with a Universal Programmer Adapter.
The MPLAB ICD 2 and MPLAB ICE in-circuit emulators
may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area extends the
circuitry for additional application components. Some
of the features include an RS-232 interface, a 2 x 16
LCD display, a piezo speaker, an on-board temperature
sensor, four LEDs, and sample PIC18F452 and
PIC16F877 Flash microcontrollers.
DS41206A-page 88
Preliminary
2003 Microchip Technology Inc.
PIC16F716
11.20 PICDEM 18R PIC18C601/801
Demonstration Board
11.23 PICDEM USB PIC16C7X5
Demonstration Board
The PICDEM 18R demonstration board serves to assist
development of the PIC18C601/801 family of Microchip
microcontrollers. It provides hardware implementation
of both 8-bit Multiplexed/De-multiplexed and 16-bit
memory modes. The board includes 2 Mb external
Flash memory and 128 Kb SRAM memory, as well as
serial EEPROM, allowing access to the wide range of
memory types supported by the PIC18C601/801.
The PICDEM USB Demonstration Board shows off the
capabilities of the PIC16C745 and PIC16C765 USB
microcontrollers. This board provides the basis for
future USB products.
11.24 Evaluation and
Programming Tools
In addition to the PICDEM series of circuits, Microchip
has a line of evaluation kits and demonstration software
for these products.
11.21 PICDEM LIN PIC16C43X
Demonstration Board
• KEELOQ evaluation and programming tools for
Microchip’s HCS Secure Data Products
The powerful LIN hardware and software kit includes a
series of boards and three PICmicro microcontrollers.
The small footprint PIC16C432 and PIC16C433 are
used as slaves in the LIN communication and feature
on-board LIN transceivers. A PIC16F874 Flash micro-
controller serves as the master. All three microcontrol-
lers are programmed with firmware to provide LIN bus
communication.
• CAN developers kit for automotive network
applications
• Analog design boards and filter design software
• PowerSmart battery charging evaluation/
calibration kits
• IrDA® development kit
• microID development and rfLabTM development
software
• SEEVAL® designer kit for memory evaluation and
endurance calculations
11.22 PICkitTM 1 Flash Starter Kit
A complete "development system in a box", the PICkit
Flash Starter Kit includes a convenient multi-section
board for programming, evaluation, and development
of 8/14-pin Flash PIC® microcontrollers. Powered via
USB, the board operates under a simple Windows GUI.
The PICkit 1 Starter Kit includes the user's guide (on
CD ROM), PICkit 1 tutorial software and code for vari-
ous applications. Also included are MPLAB® IDE (Inte-
grated Development Environment) software, software
and hardware "Tips 'n Tricks for 8-pin Flash PIC®
Microcontrollers" Handbook and a USB Interface
Cable. Supports all current 8/14-pin Flash PIC
microcontrollers, as well as many future planned
devices.
• PICDEM MSC demo boards for Switching mode
power supply, high power IR driver, delta sigma
ADC, and flow rate sensor
Check the Microchip web page and the latest Product
Line Card for the complete list of demonstration and
evaluation kits.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 89
PIC16F716
NOTES:
DS41206A-page 90
Preliminary
2003 Microchip Technology Inc.
PIC16F716
12.0 ELECTRICAL CHARACTERISTICS
†
Absolute Maximum Ratings( )
Ambient temperature under bias..........................................................................................................-55°C to +125°C
Storage temperature ........................................................................................................................... -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ....................................... -0.3V to (VDD +0.3V)
Voltage on VDD with respect to VSS ...................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ...................................................................................... 0V to +13.25V
Voltage on RA4 with respect to Vss............................................................................................................ 0V to +8.5V
Total power dissipation (Note 1) (PDIP and SOIC)................................................................................................1.0W
Total power dissipation (Note 1) (SSOP).............................................................................................................0.65W
Maximum current out of VSS pin ........................................................................................................................300 mA
Maximum current into VDD pin ...........................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ...........................................................................................................±20 mA
Maximum output current sunk by any I/O pin.......................................................................................................25 mA
Maximum output current sourced by any I/O pin .................................................................................................25 mA
Maximum current sunk by PORTA and PORTB (combined)..............................................................................200 mA
Maximum current sourced by PORTA and PORTB (combined) ........................................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin rather
than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 91
PIC16F716
FIGURE 12-1:
PIC16F716 VOLTAGE-FREQUENCY GRAPH, -40°C < TA < +85°C(1)
6.0
5.5
5.0
4.5
4.0
3.5
VDD
(Volts)
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 12-2:
PIC16F716 VOLTAGE-FREQUENCY GRAPH, 85°C < TA < +125°C(1)
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
DS41206A-page 92
Preliminary
2003 Microchip Technology Inc.
PIC16F716
12.1 DC Characteristics: PIC16F716 (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Param
Sym
No.
Characteristic
Min Typ† Max Units
Conditions
VDD Supply Voltage
D001
D001A
2.0
3.0
—
—
5.5
5.5
V
V
Industrial
Extended
D002* VDR RAM Data Retention
—
1.5*
—
V
Voltage(1)
D003
VPOR VDD Start Voltage to ensure
—
Vss
—
V
See section on Power-on Reset for
details
internal Power-on Reset signal
D004*
D004A*
SVDD VDD Rise Rate to ensure
0.05
—
—
—
—
V/ms PWRT enabled (PWRTE bit clear)
PWRT disabled (PWRTE bit set)
See section on Power-on Reset for
details
internal Power-on Reset signal TBD
VBOR Brown-out Reset voltage trip
point
D005
3.65
TBD
4.0 4.35
2.5 TBD
V
V
BOREN bit set, BOR bit = ‘1’
BOREN bit set, BOR bit = ‘0’
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 93
PIC16F716
12.2 DC Characteristics: PIC16F716 (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C
DC CHARACTERISTICS
Para
m No.
Sym
Characteristic
Min Typ† Max Units VDD
Conditions
VDD
Supply Voltage
D001
2.0
—
5.5
0.8
V
—
IPD
Power-down Base Current
—
—
—
0.1
µA
µA
µA
2.0 WDT, BOR and T1OSC:
D020
D021
disabled
0.1 0.85
3.0
0.2
2.7
5.0
∆IMOD Peripheral Module Current(1)
—
—
—
—
—
—
—
—
—
1
2
9
2.0
3.5
µA
µA
µA
µA
µA
µA
µA
µA
µA
2.0 WDT Current
3.0
13.5
5.0
TBD TBD
3.0 BOR Current
D022
D025
40
45
TBD
TBD
4.5
5.0
1.8 TBD
2.6 TBD
3.0 TBD
2.0 T1OSC Current
3.0
5.0
IDD
Supply Current
—
—
—
—
—
—
—
—
—
—
—
14
23
45
17
28
60
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
2.0 FOSC = 32 kHz
D010
LP Oscillator mode
3.0
5.0
120 160
180 250
290 370
220 300
350 470
600 780
2.0 FOSC = 1 MHz
D011
D012
D013
XT Oscillator mode
3.0
5.0
2.0 FOSC = 4 MHz
XT Oscillator mode
3.0
5.0
2.1
2.5
2.9
3.3
4.5 FOSC = 20 MHz
HS Oscillator mode
5.0
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The “∆” current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement. Max values should be used when calculating total current
consumption.
2: ADC on, not converting.
DS41206A-page 94
Preliminary
2003 Microchip Technology Inc.
PIC16F716
12.3 DC Characteristics: PIC16F716 (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +125°C
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Min Typ† Max Units VDD
Conditions
VDD
Supply Voltage
D001
3.0
—
5.5
V
—
IPD
Power-down Base Current
—
—
0.1 TBD µA
0.2 TBD µA
3.0 WDT, BOR and T1OSC: disabled
5.0
D020E
∆IMOD Peripheral Module Current(1)
—
—
—
—
—
—
—
2
9
TBD µA
TBD µA
3.0 WDT Current
D021E
D022E
5.0
TBD TBD µA
40 TBD µA
45 TBD µA
2.6 TBD µA
3.0 TBD µA
3.0
4.5 BOR Current
5.0
3.0 T1OSC Current
5.0
D025E
D010E
IDD
Supply Current
—
—
—
—
—
—
—
—
21 TBD µA
38 TBD µA
182 TBD µA
293 TBD µA
371 TBD µA
668 TBD µA
2.6 TBD mA
3.0 FOSC = 32 kHz
LP Oscillator mode
5.0
3.0 FOSC = 1 MHz
D011E
D012E
D013E
XT Oscillator mode
5.0
3.0 FOSC = 4 MHz
XT Oscillator mode
5.0
4.5 FOSC = 20 MHz
HS Oscillator mode
3
TBD mA
5.0
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The “∆” current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement. Max values should be used when calculating total current
consumption.
2: ADC on, not converting.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 95
PIC16F716
12.4 DC Characteristics: PIC16F716 (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 12.1 “DC Charac-
teristics: PIC16F716 (Industrial, Extended)” and Section 12.4 “DC Character-
istics: PIC16F716 (Industrial, Extended)”.
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
Input Low Voltage
I/O ports
VIL
D030
D030A
D031
D032
D033
with TTL buffer
VSS
VSS
—
—
—
—
—
—
0.8
V
V
V
V
V
V
4.5V ≤ VDD ≤ 5.5V
otherwise
0.15 VDD
0.2 VDD
0.2 VDD
0.3 VDD
0.6
with Schmitt Trigger buffer
MCLR, OSC1 (in RC mode)
OSC1 (in HS mode)
OSC1 (in XT and LP modes)
Input High Voltage
I/O ports
VSS
VSS
VSS
VSS
(Note1)
VIH
—
—
—
D040
with TTL buffer
2.0
0.25 VDD +
0.8V
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
D040A
otherwise
D041
D042
D042A
D043
with Schmitt Trigger buffer
MCLR
0.8 VDD
0.8 VDD
0.7 VDD
0.9 VDD
—
—
—
—
VDD
VDD
VDD
VDD
V
V
V
V
For entire VDD range
OSC1 (XT, HS and LP modes)
OSC1 (in RC mode)
(Note1)
(2), (3)
Input Leakage Current
D060
IIL
I/O ports
—
—
—
—
±1
µA Vss ≤ VPIN ≤ VDD, Pin at
high-impedance
nA Vss ≤ VPIN ≤ VDD, Pin configured as
analog input
±500
D061
D063
MCLR, RA4/T0CKI
OSC1/CLKIN
—
—
—
—
±5
±5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc
modes
D070
D080
IPURB
VOL
PORTB weak pull-up current
Output Low Voltage
I/O ports
50
—
—
—
—
250
—
400
0.6
0.6
0.6
0.6
µA VDD = 5V, VPIN = VSS
V
V
V
V
IOL = 8.5 mA, VDD = 4.5V, -40°C to
+85°C
—
IOL = 7.0 mA, VDD = 4.5V, -40°C to
+125°C
D083
OSC2/CLKOUT (RC Osc mode)
—
IOL = 1.6 mA, VDD = 4.5V, -40°C to
+85°C
—
IOL = 1.2 mA, VDD = 4.5V, -40°C to
+125°C
Output High Voltage
(3)
D090
D092
D150*
VOH
I/O ports
VDD-0.7
VDD-0.7
VDD-0.7
VDD-0.7
—
—
—
—
—
—
—
—
V
V
V
V
V
IOH = -3.0 mA, VDD = 4.5V, -40°C to
+85°C
IOH = -2.5 mA, VDD = 4.5V, -40°C to
+125°C
OSC2/CLKOUT (RC Osc mode)
—
IOH = -1.3 mA, VDD = 4.5V, -40°C to
+85°C
—
IOH = -1.0 mA, VDD = 4.5V, -40°C to
+125°C
VOD
Open-Drain High Voltage
8.5
RA4 pin
*
These parameters are characterized but not tested.
†
Data in “Type” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
In RC Oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmicro be driven with
external clock in RC mode.
Note 1:
2:
3:
The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as current sourced by the pin.
DS41206A-page 96
Preliminary
2003 Microchip Technology Inc.
PIC16F716
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC spec Section 12.1 “DC Charac-
teristics: PIC16F716 (Industrial, Extended)” and Section 12.4 “DC Character-
istics: PIC16F716 (Industrial, Extended)”.
DC CHARACTERISTICS
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
Capacitive Loading Specs on Output Pins
D100
D101
COSC2 OSC2/CLKOUT pin
CIO All I/O pins and OSC2 (in RC mode)
—
—
—
—
15
50
pF In XT, HS and LP modes when external
clock is used to drive OSC1.
pF
*
These parameters are characterized but not tested.
†
Data in “Type” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
In RC Oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmicro be driven with
external clock in RC mode.
Note 1:
2:
3:
The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as current sourced by the pin.
12.5 AC (Timing) Characteristics
12.5.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
using one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
ck
cs
di
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 97
PIC16F716
12.5.2
TIMING CONDITIONS
The temperature and voltages specified in Table 12-1
apply to all timing specifications, unless otherwise
noted. Figure 12-3 specifies the load conditions for the
timing specifications.
TABLE 12-1: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
AC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 12.1 “DC Character-
istics: PIC16F716 (Industrial, Extended)” and Section 12.4 “DC Characteristics:
PIC16F716 (Industrial, Extended)”. LC parts operate for commercial/industrial
temp’s only.
FIGURE 12-3:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1 Load condition 2
VDD/2
Cl
Rl
Pin
VSS
Cl
Pin
RL = 464Ω
VSS
CL = 50 pF for all pins except OSC2/CLKOUT
15 pF for OSC2 output
12.5.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 12-4:
EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
4
Q4
Q1
OSC1
3
3
1
4
2
CLKOUT
DS41206A-page 98
Preliminary
2003 Microchip Technology Inc.
PIC16F716
TABLE 12-2: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
Sym
Characteristic
Min Typ†
Max
Units
Conditions
No.
1A
FOSC Ext. Clock Input Frequency(1)
DC
DC
DC
DC
0.1
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
20
MHz RC and XT Osc modes
MHz HS Osc mode
kHz LP Osc mode
MHz RC Osc mode
MHz XT Osc mode
MHz HS Osc mode
kHz LP Osc mode
ns RC and XT Osc modes
ns HS Osc mode
µs LP Osc mode
200
4
Oscillator Frequency(1)
4
20
5
200
—
1
TOSC
External CLKIN Period(1)
Oscillator Period(1)
250
50
—
5
—
250
250
50
—
ns RC Osc mode
ns XT Osc mode
10,000
250
—
ns HS Osc mode
µs LP Osc mode
5
2
Tcy
Instruction Cycle Time(1)
200
DC
—
ns
TCY = 4/FOSC
3*
TosL, External Clock in (OSC1) High or 100
TosH Low Time
ns XT oscillator
µs LP oscillator
ns HS oscillator
ns XT oscillator
ns LP oscillator
ns HS oscillator
2.5
15
—
—
—
—
—
4*
TosR, External Clock in (OSC1) Rise or
TosF Fall Time
25
50
15
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at "min."
values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 99
PIC16F716
FIGURE 12-5:
CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
12
19
18
14
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note 1: Refer to Figure 12-3 for load conditions.
TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS
Param
Typ
†
Sym
Characteristic
Min
Max
Units Conditions
No.
10*
TOSH2CKL OSC1↑ to CLKOUT↓
TOSH2CKH OSC1↑ to CLKOUT↑
—
—
—
—
—
75
75
35
35
—
—
200
200
100
100
20
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
11*
12*
13*
14*
15*
TCKR
TCKF
CLKOUT rise time
CLKOUT fall time
TCKL2IOV CLKOUT ↓ to Port out valid
TIOV2CKH Port input valid before CLKOUT ↑
TOSC +
200
—
16*
TCKH2IOI
Port input hold after CLKOUT ↑
0
—
50
—
—
—
150
—
ns
ns
ns
ns
(Note 1)
17*
TOSH2IOV OSC1↑ (Q1 cycle) to Port out valid
—
18*
TOSH2IOI
OSC1↑ (Q2 cycle) to Port Standard
100
200
input invalid (I/O in hold
time)
18A*
Extended (LC)
—
19*
TIOV2OSH Port input valid to OSC1↑ (I/O in setup time)
0
—
10
—
10
—
—
—
—
40
80
40
80
—
—
ns
ns
ns
ns
ns
ns
ns
20*
TIOR
TIOF
Port output rise time
Port output fall time
INT pin high or low time
Standard
—
20A*
21*
Extended (LC)
Standard
—
—
21A*
22††*
23††*
Extended (LC)
—
TINP
Tcy
Tcy
TRBP
RB7:RB4 change INT high or low time
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edge.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
DS41206A-page 100
Preliminary
2003 Microchip Technology Inc.
PIC16F716
FIGURE 12-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING(1)
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note 1: Refer to Figure 12-3 for load conditions.
FIGURE 12-7:
BROWN-OUT RESET TIMING
BVDD
VDD
35
TABLE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
30
TMCL
TWDT
MCLR Pulse Width (low)
Watchdog Timer Time-out Period
(No Prescaler)
2
7
—
18
—
33
µs VDD = 5V, -40°C to +125°C
ms VDD = 5V, -40°C to +85°C
ms VDD = 5V, +85°C to +125°C
31*
TBD
—
TBD
TBD
—
32
TOST
Oscillation Start-up Timer Period
1024 TOSC
72
—
TOSC = OSC1 period
33*
TPWRT Power-up Timer Period
28
132
TBD
ms VDD = 5V, -40°C to +85°C
ms VDD = 5V, +85°C to +125°C
TBD
TBD
34
35
TIOZ
I/O high-impedance from MCLR
Low or WDT Reset
—
—
2.1
µs
TBOR
Brown-out Reset Pulse Width
100
—
—
µs VDD ≤ BVDD (D005)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 101
PIC16F716
FIGURE 12-8:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS(1)
T0CKI
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note 1: Refer to Figure 12-3 for load conditions.
TABLE 12-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Tt0H
Characteristic
T0CKI High Pulse Width
Min
Typ† Max Units
Conditions
40*
No Prescaler
With Prescaler
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5TCY + 20
10
—
—
—
—
—
—
—
—
—
—
—
—
ns Must also meet
parameter 42
ns Must also meet
ns
41*
42*
Tt0L
Tt0P
T0CKI Low Pulse Width
T0CKI Period
0.5TCY + 20
10
parameter 42
ns
ns
TCY + 40
Greater of:
20 or TCY + 40
N
ns N = prescale
value
(2, 4,..., 256)
ns Must also meet
45*
46*
47*
Tt1H
Tt1L
T1CKI High Time Synchronous, Prescaler = 1
Synchronous, Standard
Prescaler =
0.5TCY + 20
15
—
—
—
—
parameter 47
ns
2,4,8
Asynchronous Standard
T1CKI Low Time Synchronous, Prescaler = 1
Synchronous, Standard
Prescaler =
30
0.5TCY + 20
15
—
—
—
—
—
—
ns
ns Must also meet
parameter 47
ns
2,4,8
Asynchronous Standard
30
Greater of:
30 OR TCY + 40
N
—
—
—
—
ns
Tt1P
Ft1
T1CKI input
period
Synchronous Standard
ns N = prescale
value (1, 2, 4, 8)
Asynchronous Standard
60
—
—
—
ns
Timer1 oscillator input frequency range
32.768
32.768 kHz
(oscillator enabled by setting bit T1OSCEN)
48*
TCKEZtmr1 Delay from external clock edge to timer increment
2Tosc
—
7Tosc
—
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS41206A-page 102
Preliminary
2003 Microchip Technology Inc.
PIC16F716
FIGURE 12-9:
CAPTURE/COMPARE/PWM TIMINGS(1)
CCP1
(Capture Mode)
50
51
52
54
CCP1
(Compare or PWM Mode)
53
Note 1: Refer to Figure 12-3 for load conditions.
TABLE 12-6: CAPTURE/COMPARE/PWM REQUIREMENTS
Param
Typ
†
Sym
Characteristic
Min
Max Units Conditions
No.
50*
TccL CCP1 input low No Prescaler
time
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
With Prescaler Standard
10
0.5TCY + 20
10
51*
52*
TccH CCP1 input high No Prescaler
time
With Prescaler Standard
TccP CCP1 input period
3TCY + 40
N
ns N = prescale
value (1,4, or
16)
53*
TccR CCP1 output rise time
TccF CCP1 output fall time
Standard
Extended
Standard
Extended
—
—
—
—
10
—
10
—
40
80
40
80
ns
ns
ns
ns
53A*
54*
54A*
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 103
PIC16F716
TABLE 12-7: A/D CONVERTER CHARACTERISTICS: PIC16F716 (INDUSTRIAL, EXTENDED)
Para
m
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
No.
A00
VDD VDD Operation
NR Resolution
2.5
—
—
—
5.5
V
A01
A02
A03
A04
A05
A06
8-bits
bit VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
EABS Total Absolute error
EIL Integral linearity error
EDL Differential linearity error
EFS Full scale error
—
—
—
—
—
—
—
—
—
—
< ± 1
< ± 1
< ± 1
< ± 1
< ± 1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
LSb VREF = VDD= 5.12V,
VSS ≤ VAIN ≤ VREF
EOFF Offset error
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10
A20
A25
—
Monotonicity
—
guaranteed(3)
—
—
V
VSS ≤ VAIN ≤ VREF
VREF Reference voltage
VAIN Analog input voltage
2.5V
—
—
VDD + 0.3
VSS -
0.3
VREF +
0.3
V
A30
A40
ZAIN Recommended impedance of
analog voltage source
—
—
10.0
kΩ
IAD A/D conversion
current (VDD)
Standard
—
180
—
µA Average current
consumption when
A/D is on.(1)
A50
IREF VREF input current(2)
10
—
—
—
1000
10
µA During VAIN
acquisition.
Based on differential
of VHOLD to VAIN to
charge CHOLD, see
µA Section 12.1 “DC
Characteristics:
PIC16F716 (Indus-
trial, Extended)”.
During A/D
Conversion cycle
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing
codes.
DS41206A-page 104
Preliminary
2003 Microchip Technology Inc.
PIC16F716
FIGURE 12-10:
A/D CONVERSION TIMING
BSF ADCON0, GO
134
1 Tcy
(TOSC/2)(1)
131
130
Q4
132
A/D CLK
7
6
5
4
3
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note 1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEPinstruction
to be executed.
TABLE 12-8: A/D CONVERSION REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
130
TAD A/D clock period
Industrial
Industrial
Extended
Extended
1.6
1.6
—
4.0
—
—
6.0
—
µs
TOSC based, VREF ≥ 3.0V
µs A/D RC mode
1.6
µs
TOSC based, VREF ≥ 3.0V
1.6
6.0
—
9.0
9.5
—
µs A/D RC mode
(1)
131
132
TCNV Conversion time (not including S/H time)
TACQ Acquisition time
9.5
TAD
(Note 2)
20
µs
5*
—
—
µs The minimum time is the amplifier
settling time. This may be used if
the "new" input voltage has not
changed by more than 1 LSb (i.e.,
20.0 mV @ 5.12V) from the last
sampled voltage (as stated on
CHOLD).
134
135
TGO Q4 to A/D clock start
—
TOSC/2 **
—
—
—
If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEPinstruction to be
executed.
TSWC Switching from convert → sample time
1.5 **
—
TAD
*
These parameters are characterized but not tested.
** This specification ensured by design.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 12.1 “DC Characteristics: PIC16F716 (Industrial, Extended)” for min. conditions.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 105
PIC16F716
NOTES:
DS41206A-page 106
Preliminary
2003 Microchip Technology Inc.
PIC16F716
13.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
The graphs and tables provided in this section are for
design guidance and are not tested.
In some graphs or tables, the data presented are
outside specified operating range (i.e., outside
specified VDD range). This is for information only and
devices will operate properly only within the specified
range.
The data presented in this section is a statistical
summary of data collected on units from different lots
over a period of time and matrix samples. 'Typical' rep-
resents the mean of the distribution at 25°C. 'Max' or
'min' represents (mean + 3σ) or (mean - 3σ)
respectively, where σ is standard deviation, over the
whole temperature range.
Graphs and Tables not available at this
time.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 107
PIC16F716
NOTES:
DS41206A-page 108
Preliminary
2003 Microchip Technology Inc.
PIC16F716
14.0 PACKAGING INFORMATION
14.1 Package Marking Information
18-Lead PDIP
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
PIC16F716-04/P
0023CBA
YYWWNNN
18-Lead SOIC
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16F716
-20/SO
0018CDK
YYWWNNN
20-Lead SSOP
Example
PIC16F716
XXXXXXXXXXX
XXXXXXXXXXX
-20I/SS025
YYWWNNN
0020CBK
Legend: XX...X Customer specific information*
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 109
PIC16F716
18-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
α
n
1
E
A2
L
A
c
A1
B1
β
p
B
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.890
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
22.61
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.898
.130
.012
.058
.018
.370
10
.325
.260
.905
.135
.015
.070
.022
.430
15
7.94
6.35
22.80
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
22.99
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-007
DS41206A-page 110
Preliminary
2003 Microchip Technology Inc.
PIC16F716
18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
p
E1
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
18
18
.050
.099
.091
.008
.407
.295
.454
.020
.033
4
1.27
2.50
2.31
0.20
10.34
7.49
11.53
0.50
0.84
4
Overall Height
A
.093
.104
2.36
2.64
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.291
.446
.010
.016
0
.094
.012
.420
.299
.462
.029
.050
8
2.24
0.10
10.01
7.39
11.33
0.25
0.41
0
2.39
0.30
10.67
7.59
11.73
0.74
1.27
8
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.012
.020
15
0.23
0.36
0
0.27
0.42
12
0.30
0.51
15
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-051
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 111
PIC16F716
20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
E
E1
p
D
B
2
1
n
α
c
A2
A
φ
L
A1
β
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
20
MAX
n
p
Number of Pins
Pitch
20
.026
.073
.068
.006
.309
.207
.284
.030
.007
4
0.65
Overall Height
A
.068
.078
1.73
1.63
1.85
1.73
0.15
7.85
5.25
7.20
0.75
0.18
101.60
0.32
5
1.98
1.83
0.25
8.18
5.38
7.34
0.94
0.25
203.20
0.38
10
Molded Package Thickness
Standoff
A2
A1
E
.064
.002
.299
.201
.278
.022
.004
0
.072
.010
.322
.212
.289
.037
.010
8
§
0.05
7.59
5.11
7.06
0.56
0.10
0.00
0.25
0
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
c
Lead Thickness
Foot Angle
φ
Lead Width
B
α
β
.010
0
.013
5
.015
10
Mold Draft Angle Top
Mold Draft Angle Bottom
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No. C04-072
DS41206A-page 112
Preliminary
2003 Microchip Technology Inc.
PIC16F716
APPENDIX A: REVISION HISTORY
APPENDIX B: CONVERSION
CONSIDERATIONS
Revision A (June 2003)
This is a Flash program memory version of the
PIC16C716 device. Refer to the migration document,
DS40059, for more information about differences
between the PIC16F716 and PIC16C716.
Original data sheet. However, the device described in
this data sheet are upgrades to PIC16C716.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 113
PIC16F716
To convert code written for PIC16C5X to PIC16F716,
the user should take the following steps:
APPENDIX C: MIGRATION FROM
BASE-LINE TO
1. Remove any program memory page select
MID-RANGE DEVICES
operations (PA2, PA1, PA0 bits) for CALL, GOTO.
This section discusses how to migrate from a baseline
device (i.e., PIC16C5X) to a mid-range device (i.e.,
PIC16F716).
2. Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
The following are the list of modifications over the
PIC16C5X microcontroller family:
3. Eliminate any data memory page switching.
Redefine data variables to reallocate them.
4. Verify all writes to Status, Option, and FSR
registers since these have changed.
1. Instruction word length is increased to 14-bits.
This allows larger page sizes both in program
memory (2K now as opposed to 512 before) and
register file (128 bytes now versus 32 bytes
before).
5. Change Reset vector to 0000h
.
Note 1: This device has been designed to
perform to the parameters of its data
sheet. It has been tested to an electrical
specification designed to determine its
conformance with these parameters. Due
to process differences in the manufacture
of this device, this device may have differ-
ent performance characteristics than its
earlier version. These differences may
cause this device to perform differently in
your application than the earlier version of
this device.
2. A PC high latch register (PCLATH) is added to
handle program memory paging. Bits PA2, PA1,
PA0 are removed from Status register.
3. Data memory paging is redefined slightly.
Status register is modified.
4. Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW.
Two instructions TRIS and OPTION are being
phased out although they are kept for
compatibility with PIC16C5X.
5. OPTION_REG and TRIS registers are made
addressable.
2: The user should verify that the device
oscillator starts and performs as
expected. Adjusting the loading capacitor
values and/or the Oscillator mode may be
required.
6. Interrupt capability is added. Interrupt vector is
at 0004h.
7. Stack size is increased to 8 deep.
8. Reset vector is changed to 0000h.
9. Reset of all registers is revisited. Five different
Reset (and wake-up) types are recognized.
Registers are reset differently.
10. Wake-up from Sleep through interrupt is added.
11. Two separate timers, Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) are
included for more reliable power-up. These
timers are invoked selectively to avoid
unnecessary delays on power-up and wake-up.
12. PORTB has weak pull-ups and interrupt-on-
change feature.
13. T0CKI pin is also a port pin (RA4) now.
14. FSR is made a full eight bit register.
15. “In-circuit serial programming” is made possible.
The user can program PIC16F716 devices
using only five pins: VDD, VSS, MCLR/VPP, RB6
(clock) and RB7 (data in/out).
16. PCON status register is added with a Power-on
Reset Status bit (POR).
17. Brown-out protection circuitry has been added.
Controlled by configuration word bits BOREN
and BORV. Brown-out Reset ensures the device
is placed in a Reset condition if VDD dips below
a fixed setpoint.
DS41206A-page 114
Preliminary
2003 Microchip Technology Inc.
PIC16F716
ON-LINE SUPPORT
SYSTEMS INFORMATION AND
UPGRADE HOT LINE
Microchip provides on-line support on the Microchip
World Wide Web site.
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive the most current upgrade kits. The Hot Line
Numbers are:
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape® or Microsoft®
Internet Explorer. Files are also available for FTP
download from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
Connecting to the Microchip Internet
Web Site
042003
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 115
PIC16F716
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
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PIC16F716
DS41206A
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41206A-page 116
Preliminary
2003 Microchip Technology Inc.
PIC16F716
INDEX
BOR Enable (BODEN Bit) .......................................... 56
BOR Status (BOR Bit) ................................................ 16
Timing Diagram ........................................................ 101
BSF Instruction ................................................................... 74
BTFSC Instruction .............................................................. 74
BTFSS Instruction............................................................... 75
A
A/D...................................................................................... 49
A/D Converter Enable (ADIE Bit)................................ 14
A/D Converter Flag (ADIF Bit) .............................. 15, 50
A/D Converter Interrupt, Configuring .......................... 50
ADCON0 Register................................................... 9, 49
ADCON1 Register................................................. 10, 50
ADRES Register ........................................................... 9
Analog Port Pins, Configuring..................................... 52
Channel Select (CHS2:CHS0 Bits)............................. 49
Clock Select (ADCS1:ADCS0 Bits)............................. 49
Configuring the Module............................................... 50
Conversion Clock (Tad) .............................................. 52
Conversion Status (GO/DONE Bit)....................... 49, 50
Conversions................................................................ 53
Converter Characteristics ......................................... 104
Module On/Off (ADON Bit).......................................... 49
Port Configuration Control (PCFG2:PCFG0 Bits)....... 50
Sampling Requirements.............................................. 51
Special Event Trigger (CCP)................................. 35, 53
Timing Diagram......................................................... 105
Absolute Maximum Ratings ................................................ 91
ADCON0 Register................................................................. 9
ADCON1 Register............................................................... 10
ADDLW Instruction ............................................................. 73
ADDWF Instruction ............................................................. 73
ADRES Register ................................................................... 9
Analog Input Model ............................................................. 51
Analog-to-Digital Converter. See A/D
C
C Compilers
MPLAB C17................................................................ 86
MPLAB C18................................................................ 86
MPLAB C30................................................................ 86
CALL Instruction ................................................................. 75
Capture (CCP Module) ....................................................... 34
CCP Pin Configuration ............................................... 34
CCPR1H:CCPR1L Registers ..................................... 34
Software Interrupt....................................................... 34
Timer1 Mode Selection............................................... 34
Capture/Compare/PWM (CCP) .......................................... 33
Capture Mode. See Capture
CCP1CON Register...................................................... 9
CCPR1H Register .................................................. 9, 33
CCPR1L Register................................................... 9, 33
Compare Mode. See Compare
Enable (CCP1IE Bit)................................................... 14
Flag (CCP1IF Bit) ....................................................... 15
PWM Mode. See PWM
Timer Resources ........................................................ 33
Timing Diagram ........................................................ 103
CLRF Instruction................................................................. 75
CLRW Instruction................................................................ 76
CLRWDT Instruction........................................................... 76
Code Examples
ANDLW Instruction ............................................................. 73
ANDWF Instruction ............................................................. 73
Assembler
MPASM Assembler..................................................... 85
Capture (CCP Module)
Changing Between Capture Prescalers ............. 34
How to Clear RAM Using Indirect Addressing............ 18
Initializing PORTA ...................................................... 19
Initializing PORTB ...................................................... 21
Code Protection............................................................ 55, 69
CP1:CP0 Bits.............................................................. 56
COMF Instruction................................................................ 76
Compare (CCP Module) ..................................................... 34
CCP Pin Configuration ............................................... 35
Software Interrupt....................................................... 35
Special Event Trigger ..................................... 30, 35, 53
Timer1 Mode Selection............................................... 35
Configuration Bits ............................................................... 55
Conversion Considerations............................................... 113
B
Banking, Data Memory ................................................... 7, 11
BCF Instruction ................................................................... 74
Block Diagrams
A/D.............................................................................. 51
Capture (CCP Module) ............................................... 34
Compare (CCP Module) ............................................. 35
Interrupt Sources ........................................................ 65
On-Chip Reset Circuit................................................. 60
PIC16F716.................................................................... 5
PORTA.................................................................. 19, 20
PORTB........................................................................ 21
PWM (CCP Module) ................................................... 36
PWM (Enhanced)........................................................ 38
RB1/T1OSO/T1CKI..................................................... 22
RB2/T1OSI.................................................................. 22
RB3/CCP1/P1A........................................................... 23
RB4............................................................................. 23
RB5............................................................................. 24
RB6/P1C..................................................................... 24
RB7/P1D..................................................................... 25
Timer0......................................................................... 27
Timer0/WDT Prescaler ............................................... 28
Timer1......................................................................... 30
Timer2......................................................................... 32
Watchdog Timer (WDT).............................................. 67
BOR. See Brown-out Reset
D
Data Memory ........................................................................ 7
Bank Select (RP1:RP0 Bits)................................... 7, 11
General Purpose Registers .......................................... 8
Register File Map ......................................................... 8
Special Function Registers........................................... 9
DC Characteristics............................................ 93, 94, 95, 96
DECF Instruction ................................................................ 76
DECFSZ Instruction............................................................ 77
Demonstration Boards
PICDEM 1................................................................... 88
PICDEM 17................................................................. 88
PICDEM 18R PIC18C601/801 ................................... 89
PICDEM 2 Plus........................................................... 88
PICDEM 3 PIC16C92X............................................... 88
Brown-out Detect (BOD)..................................................... 59
Brown-out Reset (BOR).................................... 55, 58, 62, 63
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 117
PIC16F716
PICDEM 4 ...................................................................88
PICDEM LIN PIC16C43X ...........................................89
PICDEM USB PIC16C7X5..........................................89
PICDEM.net Internet/Ethernet ....................................88
Development Support .........................................................85
Direct Addressing................................................................18
SUBWF....................................................................... 83
SWAPF....................................................................... 83
TRIS ........................................................................... 83
XORLW ...................................................................... 84
XORWF ...................................................................... 84
Instruction Set Summary .................................................... 71
INT Interrupt (RB0/INT). See Interrupt Sources
E
INTCON Register............................................................ 9, 13
GIE Bit ........................................................................ 13
INTE Bit ...................................................................... 13
INTF Bit ...................................................................... 13
PEIE Bit ...................................................................... 13
RBIE Bit ...................................................................... 13
RBIF Bit ...................................................................... 13
T0IE Bit....................................................................... 13
T0IF Bit....................................................................... 13
Interrupt Sources .......................................................... 55, 65
A/D Conversion Complete .......................................... 50
Capture Complete (CCP)............................................ 34
Compare Complete (CCP).......................................... 35
Interrupt-on-Change (RB7:RB4 )................................ 21
RB0/INT Pin, External................................................. 66
TMR0 Overflow..................................................... 28, 66
TMR1 Overflow..................................................... 29, 30
TMR2 to PR2 Match ................................................... 32
TMR2 to PR2 Match (PWM)................................. 31, 36
Interrupts, Context Saving During....................................... 66
Interrupts, Enable Bits
ECCP
Auto-Shutdown ...........................................................45
and Automatic Restart ........................................47
Start-up Considerations ..............................................47
Electrical Characteristics.....................................................91
Enhanced Capture/Compare/PWM (ECCP)
PWM Mode. See PWM (ECCP Module)
Enhanced CCP Auto-Shutdown..........................................45
Enhanced PWM Mode. See PWM (ECCP Module)............38
Errata ....................................................................................3
Evaluation and Programming Tools....................................89
External Power-on Reset Circuit.........................................58
G
GOTO Instruction................................................................77
I
I/O Ports..............................................................................19
ID Locations ..................................................................55, 69
INCF Instruction ..................................................................78
INCFSZ Instruction..............................................................78
In-Circuit Serial Programming (ICSP) ........................... 55, 69
Indirect Addressing .............................................................18
FSR Register ...................................................... 8, 9, 18
INDF Register ...............................................................9
Instruction Set
A/D Converter Enable (ADIE Bit)................................ 14
CCP1 Enable (CCP1IE Bit) .................................. 14, 34
Global Interrupt Enable (GIE Bit).......................... 13, 65
Interrupt-on-Change (RB7:RB4) Enable (RBIE Bit)... 13,
66
Peripheral Interrupt Enable (PEIE Bit)........................ 13
RB0/INT Enable (INTE Bit)......................................... 13
TMR0 Overflow Enable (T0IE Bit) .............................. 13
TMR1 Overflow Enable (TMR1IE Bit)......................... 14
TMR2 to PR2 Match Enable (TMR2IE Bit) ................. 14
Interrupts, Flag Bits
A/D Converter Flag (ADIF Bit) .............................. 15, 50
CCP1 Flag (CCP1IF Bit)....................................... 15, 34
Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) .. 13, 66
RB0/INT Flag (INTF Bit) ............................................. 13
TMR0 Overflow Flag (T0IF Bit)............................. 13, 66
TMR1 Overflow Flag (TMR1IF Bit) ............................. 15
TMR2 to PR2 Match Flag (TMR2IF Bit)...................... 15
IORLW Instruction .............................................................. 79
IORWF Instruction .............................................................. 79
ADDLW .......................................................................73
ADDWF.......................................................................73
ANDLW .......................................................................73
ANDWF.......................................................................73
BCF.............................................................................74
BSF.............................................................................74
BTFSC ........................................................................74
BTFSS ........................................................................75
CALL ...........................................................................75
CLRF...........................................................................75
CLRW .........................................................................76
CLRWDT.....................................................................76
COMF .........................................................................76
DECF ..........................................................................76
DECFSZ......................................................................77
GOTO .........................................................................77
INCF............................................................................78
INCFSZ.......................................................................78
IORLW ........................................................................79
IORWF ........................................................................79
MOVF..........................................................................79
MOVLW ......................................................................79
MOVWF ......................................................................80
NOP ............................................................................80
OPTION ......................................................................80
RETFIE .......................................................................80
RETLW .......................................................................81
RETURN .....................................................................81
RLF .............................................................................81
RRF.............................................................................82
SLEEP ........................................................................82
SUBLW .......................................................................82
M
Master Clear (MCLR)
MCLR Reset, Normal Operation..................... 58, 62, 63
MCLR Reset, Sleep........................................ 58, 62, 63
Memory Organization
Data Memory ................................................................ 7
Program Memory.......................................................... 7
Migration from Base-Line to Mid-Range Devices ............. 114
MOVF Instruction................................................................ 79
MOVLW Instruction............................................................. 79
MOVWF Instruction ............................................................ 80
MPLAB ASM30 Assembler, Linker, Librarian..................... 86
MPLAB ICD 2 In-Circuit Debugger ..................................... 87
MPLAB ICE 2000 High Performance Universal
In-Circuit Emulator...................................................... 87
MPLAB ICE 4000 High Performance Universal
In-Circuit Emulator...................................................... 87
DS41206A-page 118
Preliminary
2003 Microchip Technology Inc.
PIC16F716
MPLAB Integrated Development Environment Software .... 85
MPLINK Object Linker/MPLIB Object Librarian .................. 86
POR Status (POR Bit) ................................................ 16
Power Control (PCON) Register................................. 62
Power-down (PD Bit)............................................ 11, 58
Power-on Reset Circuit, External ............................... 58
Power-up Timer (PWRT)...................................... 55, 59
PWRT Enable (PWRTE Bit) ....................................... 56
Time-out (TO Bit).................................................. 11, 58
Time-out Sequence .................................................... 62
Time-out Sequence on Power-up............................... 64
Timing Diagram ........................................................ 101
Prescaler, Capture.............................................................. 34
Prescaler, Timer0 ............................................................... 27
Assignment (PSA Bit)........................................... 12, 27
Rate Select (PS2:PS0 Bits).................................. 12, 27
Switching Between Timer0 and WDT......................... 28
Prescaler, Timer1 ............................................................... 30
Select (T1CKPS1:T1CKPS0 Bits) .............................. 29
Prescaler, Timer2 ............................................................... 37
Select (T2CKPS1:T2CKPS0 Bits) .............................. 31
PRO MATE II Universal Device Programmer..................... 87
Program Counter
N
NOP Instruction................................................................... 80
O
OPTION Instruction............................................................. 80
OPTION_REG Register................................................ 10, 12
INTEDG Bit ................................................................. 12
PS2:PS0 Bits ........................................................ 12, 27
PSA Bit.................................................................. 12, 27
RBPU Bit..................................................................... 12
T0CS Bit................................................................ 12, 27
T0SE Bit................................................................ 12, 27
Oscillator Configuration................................................. 55, 57
HS......................................................................... 57, 62
LP.......................................................................... 57, 62
RC................................................................... 57, 58, 62
Selection (FOSC1:FOSC0 Bits).................................. 56
XT ......................................................................... 57, 62
Oscillator, Timer1.......................................................... 29, 30
Oscillator, WDT................................................................... 67
PCL Register .......................................................... 9, 17
PCLATH Register............................................. 9, 17, 66
Reset Conditions ........................................................ 62
Program Memory.................................................................. 7
Interrupt Vector............................................................. 7
Paging .................................................................... 7, 17
Program Memory Map.................................................. 7
Reset Vector................................................................. 7
Program Verification ........................................................... 69
PWM (CCP Module) ........................................................... 36
CCPR1H:CCPR1L Registers ..................................... 36
Duty Cycle .................................................................. 37
Example Frequencies/Resolutions............................. 37
Output Diagram .......................................................... 36
Period ......................................................................... 36
Set-Up for PWM Operation......................................... 37
TMR2 to PR2 Match............................................. 31, 36
TMR2 to PR2 Match Enable (TMR2IE Bit)................. 14
TMR2 to PR2 Match Flag (TMR2IF Bit) ..................... 15
PWM (ECCP Module)......................................................... 38
Associated Registers.................................................. 48
Direction Change in Full-Bridge Output Mode............ 43
Effects of Reset .......................................................... 48
Full-Bridge Application Example................................. 43
Full-Bridge Mode ........................................................ 43
Half-Bridge Mode........................................................ 42
Half-Bridge Output Mode Applications Example ........ 42
Output Configurations................................................. 38
Output Relationships (Active High and Low).............. 40
Output Relationships (Active-High and Low).............. 39
Output Relationships Diagram.............................. 39, 41
Programmable Dead-band Delay............................... 45
Setup for Operation .................................................... 48
Shoot-through Current................................................ 45
Start-up Considerations.............................................. 47
P
Packaging ......................................................................... 109
Paging, Program Memory............................................... 7, 17
PCON Register ............................................................. 16, 62
BOR Bit....................................................................... 16
POR Bit....................................................................... 16
PICkit 1 FLASH Starter Kit.................................................. 89
PICSTART Plus Development Programmer ....................... 87
PIE1 Register................................................................ 10, 14
ADIE Bit ...................................................................... 14
CCP1IE Bit.................................................................. 14
TMR1IE Bit.................................................................. 14
TMR2IE Bit.................................................................. 14
PIR1 Register.................................................................. 9, 15
ADIF Bit....................................................................... 15
CCP1IF Bit.................................................................. 15
TMR1IF Bit.................................................................. 15
TMR2IF Bit.................................................................. 15
Pointer, FSR ....................................................................... 18
POR. See Power-on Reset
PORTA
PORTA Register ..................................................... 9, 19
TRISA Register..................................................... 10, 19
PORTB
PORTB Register ..................................................... 9, 21
Pull-up Enable (RBPU Bit).......................................... 12
RB0/INT Edge Select (INTEDG Bit)............................ 12
RB0/INT Pin, External................................................. 66
RB7:RB4 Interrupt-on-Change.................................... 66
RB7:RB4 Interrupt-on-Change Enable
(RBIE Bit)...................................................... 13, 66
RB7:RB4 Interrupt-on-Change Flag (RBIF Bit)........... 66
TRISB Register..................................................... 10, 21
Postscaler, Timer2
Q
Select (TOUTPS3:TOUTPS0 Bits) ............................. 31
Postscaler, WDT................................................................. 27
Assignment (PSA Bit) ........................................... 12, 27
Rate Select (PS2:PS0 Bits) .................................. 12, 27
Switching Between Timer0 and WDT ......................... 28
Power-down Mode. See Sleep
Q-Clock....................................................................... 37, 100
Power-on Reset (POR)..................................... 55, 58, 62, 63
Oscillator Start-up Timer (OST) ............................ 55, 59
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 119
PIC16F716
Status Register ............................................................... 9, 66
C Bit............................................................................ 11
DC Bit ......................................................................... 11
IRP Bit ........................................................................ 11
PD Bit ................................................................... 11, 58
RP1:RP0 Bits.............................................................. 11
TO Bit ................................................................... 11, 58
Z Bit ............................................................................ 11
SUBLW Instruction ............................................................. 82
SUBWF Instruction ............................................................. 83
SWAPF Instruction ............................................................. 83
R
RA3:RA0 .............................................................................19
RA4/T0CKI Pin....................................................................20
RAM. See Data Memory.
RB0 Pin...............................................................................21
Register File..........................................................................8
Register File Map..................................................................8
Registers
A/D ADCON0 ..............................................................49
A/D ADCON1 ..............................................................49
A/D ADRES........................................................... 49, 50
ADCON0 ADCS1:ADCS0 Bits....................................49
ADCON0 ADON Bit ....................................................49
ADCON0 CHS2:CHS0 Bits.........................................49
ADCON0 GO/DONE Bit........................................ 49, 50
ADCON1 PCFG2:PCFG0 Bits....................................50
CCP1CON CCP1M3:CCP1M0 Bits ............................33
CCP1CON CCP1X:CCP1Y Bits .................................33
Compare (CCP Module)
CCPR1H:CCPR1L..............................................34
INTCON Register
RBIF....................................................................21
PWM1CON (Enhanced PWM Configuration) .............46
T1CON Register
T1CKPS1:T1CKPS0 Bits....................................29
T1OSCEN Bit......................................................29
T1SYNC Bit.........................................................29
TMR1CS Bit........................................................29
TMR1ON Bit........................................................29
T2CON Register T2CKPS1:T2CKPS0 Bits ................31
T2CON Register TMR2ON Bit....................................31
T2CON Register TOUTPS3:TOUTPS0 Bits ...............31
Timer2
T
T1CON Register ................................................................... 9
T2CON Register ................................................................... 9
Timer0................................................................................. 27
Clock Source Edge Select (T0SE Bit) .................. 12, 27
Clock Source Select (T0CS Bit)............................ 12, 27
Overflow Enable (T0IE Bit) ......................................... 13
Overflow Flag (T0IF Bit)........................................ 13, 66
Overflow Interrupt ................................................. 28, 66
Prescaler. See Prescaler, Timer0
Timing Diagram ........................................................ 102
TMR0 Register.............................................................. 9
Timer1................................................................................. 29
Clock Source Select (TMR1CS Bit)............................ 29
External Clock Input Sync (T1SYNC Bit).................... 29
Module On/Off (TMR1ON Bit)..................................... 29
Oscillator............................................................... 29, 30
Oscillator Enable (T1OSCEN Bit)............................... 29
Overflow Enable (TMR1IE Bit).................................... 14
Overflow Flag (TMR1IF Bit)........................................ 15
Overflow Interrupt ................................................. 29, 30
Prescaler. See Prescaler, Timer1
PR2.....................................................................36
Timer2 PR2 Register ..................................................31
Timer2 TMR2 Register................................................31
TMR1H Timer1 Register .............................................29
TMR1L Timer1 Register..............................................29
Reset............................................................................. 55, 58
Brown-out Reset (BOR). See Brown-out Reset (BOR)
MCLR Reset. See MCLR
Special Event Trigger (CCP) ................................ 30, 35
T1CON Register ........................................................... 9
Timing Diagram ........................................................ 102
TMR1H Register........................................................... 9
TMR1L Register............................................................ 9
Timer2
Postscaler. See Postscaler, Timer2
PR2 Register .............................................................. 10
Prescaler. See Prescaler, Timer2
Power-on Reset (POR). See Power-on Reset (POR)
Reset Conditions for PCON Register..........................62
Reset Conditions for Program Counter.......................62
Reset Conditions for Status Register..........................62
Timing Diagram.........................................................101
WDT Reset. See Watchdog Timer (WDT)
T2CON Register ........................................................... 9
TMR2 Register.............................................................. 9
TMR2 to PR2 Match Enable (TMR2IE Bit) ................. 14
TMR2 to PR2 Match Flag (TMR2IF Bit)...................... 15
TMR2 to PR2 Match Interrupt......................... 31, 32, 36
Timing Diagrams
RETFIE Instruction..............................................................80
RETLW Instruction..............................................................81
RETURN Instruction............................................................81
Revision History ................................................................113
RLF Instruction....................................................................81
RRF Instruction ...................................................................82
Half-Bridge PWM Output ............................................ 42
PWM Auto-Shutdown (PRSEN = 0, Auto-Restart
Disabled) ............................................................ 47
PWM Auto-Shutdown (PRSEN = 1, Auto-Restart
Enabled) ............................................................. 47
PWM Direction Change .............................................. 44
PWM Direction Change at Near 100% Duty Cycle..... 44
Time-out Sequence on Power-up............................... 64
Wake-up from Sleep via Interrupt............................... 69
Timing Diagrams and Specifications .................................. 98
A/D Conversion......................................................... 105
Brown-out Reset (BOR)............................................ 101
Capture/Compare/PWM (CCP) ................................ 103
CLKOUT and I/O ...................................................... 100
External Clock............................................................. 98
Oscillator Start-up Timer (OST)................................ 101
Power-up Timer (PWRT).......................................... 101
S
Shoot-through Current ........................................................45
Sleep....................................................................... 55, 58, 68
Sleep Instruction .................................................................82
Software Simulator (MPLAB SIM).......................................86
Software Simulator (MPLAB SIM30)...................................86
Special Event Trigger. See Compare
Special Features of the CPU...............................................55
Special Function Registers ...................................................9
Speed, Operating..................................................................1
Stack ...................................................................................17
DS41206A-page 120
Preliminary
2003 Microchip Technology Inc.
PIC16F716
Reset......................................................................... 101
Timer0 and Timer1.................................................... 102
Watchdog Timer (WDT)............................................ 101
TRIS Instruction .................................................................. 83
W
W Register .......................................................................... 66
Wake-up from Sleep ..................................................... 55, 68
Interrupts............................................................... 62, 63
MCLR Reset ............................................................... 63
Timing Diagram........................................................... 69
WDT Reset ................................................................. 63
Watchdog Timer (WDT) ................................................ 55, 67
Enable (WDTE Bit)................................................ 56, 67
Postscaler. See Postscaler, WDT
Programming Considerations ..................................... 67
RC Oscillator............................................................... 67
Time-out Period .......................................................... 67
Timing Diagram......................................................... 101
WDT Reset, Normal Operation....................... 58, 62, 63
WDT Reset, Sleep .......................................... 58, 62, 63
WWW, On-Line Support ....................................................... 3
X
XORLW Instruction ............................................................. 84
XORWF Instruction ............................................................. 84
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 121
PIC16F716
NOTES:
DS41206A-page 122
Preliminary
2003 Microchip Technology Inc.
PIC16F716
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
b)
PIC16F716 -I/P 301= Industrial temp., PDIP
package, QTP pattern #301.
PIC16F716 - E/SO = Extended temp, SOIC
package
Device
PIC16F716, PIC16F716T, VDD range 2.0V to 5.5V
Temperature Range
Package
I
E
=
=
-40°C to +85°C
-40°C to +125°C (Extended)
(Industrial)
SO
P
SS
=
=
=
SOIC
PDIP
SSOP
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
Note 1: T = in tape and reel SOIC and SSOP
packages only.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2003 Microchip Technology Inc.
Preliminary
DS41206A-page 123
WORLDWIDE SALES AND SERVICE
Korea
AMERICAS
ASIA/PACIFIC
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
Corporate Office
Australia
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Singapore
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
China - Beijing
Unit 915
Bei Hai Wan Tai Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100
Fax: 86-10-85282104
Atlanta
3780 Mansell Road, Suite 130
Alpharetta, GA 30022
Tel: 770-640-0034
Fax: 770-640-0307
Taiwan
Kaohsiung Branch
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Tel: 886-7-536-4818
Fax: 886-7-536-4803
Boston
China - Chengdu
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Tel: 978-692-3848
Fax: 978-692-3821
Rm. 2401-2402, 24th Floor,
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Tel: 86-28-86766200
Taiwan
Taiwan Branch
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Chicago
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EUROPE
Austria
Durisolstrasse 2
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Austria
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Denmark
Regus Business Centre
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Detroit
Tri-Atria Office Building
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Fax: 86-21-6275-5060
China - Shenzhen
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No. 5022 Binhe Road, Futian District
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Tel: 86-755-82901380
Fax: 86-755-8295-1393
China - Shunde
Fax: 248-538-2260
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Tel: 45-4420-9895 Fax: 45-4420-9910
Kokomo
France
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Parc d’Activite du Moulin de Massy
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Fax: 33-1-69-30-90-79
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Phoenix
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Italy
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Milan, Italy
China - Qingdao
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Tel: 86-532-5027355 Fax: 86-532-5027205
San Jose
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
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Tel: 408-436-7950
Fax: 408-436-7955
India
Toronto
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Japan
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United Kingdom
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Tel: 44-118-921-5869
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Benex S-1 6F
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Tel: 81-45-471- 6166 Fax: 81-45-471-6122
07/28/03
DS41206A-page 124
Preliminary
2003 Microchip Technology Inc.
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