PIC16F7XISSSQTP [MICROCHIP]
28/40-pin, 8-bit CMOS FLASH Microcontrollers;
| 型号： | PIC16F7XISSSQTP |
| 厂家： | 
MICROCHIP |
| 描述： | 28/40-pin, 8-bit CMOS FLASH Microcontrollers 微控制器 |
| 文件： | 总174页 (文件大小：4284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M
PIC16F7X
Data Sheet
28/40-pin, 8-bit CMOS FLASH
Microcontrollers
2002 Microchip Technology Inc.
DS30325B
®
Note the following details of the code protection feature on PICmicro MCUs.
•
•
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
•
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, MPLAB, PIC, PICmicro, PICMASTER, PICSTART,
PRO MATE, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microID,
microPort, Migratable Memory, MPASM, MPLIB, MPLINK,
MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select
Mode and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A.
Serialized Quick Term Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
DS30325B - page ii
2002 Microchip Technology Inc.
PIC16F7X
M
28/40-Pin 8-Bit CMOS FLASH Microcontrollers
Devices Included in this Data Sheet:
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• PIC16F73
• PIC16F74
• PIC16F76
• PIC16F77
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during SLEEP via external
crystal/clock
High Performance RISC CPU:
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• High performance RISC CPU
• Only 35 single word instructions to learn
• Two Capture, Compare, PWM modules
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• All single cycle instructions except for program
branches which are two-cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 8-bit, up to 8-channel Analog-to-Digital converter
• Up to 8K x 14 words of FLASH Program Memory,
Up to 368 x 8 bytes of Data Memory (RAM)
• Synchronous Serial Port (SSP) with SPI (Master
mode) and I2C (Slave)
• Pinout compatible to the PIC16C73B/74B/76/77
• Pinout compatible to the PIC16F873/874/876/877
• Interrupt capability (up to 12 sources)
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
• Parallel Slave Port (PSP), 8-bits wide with
external RD, WR and CS controls (40/44-pin only)
• Eight level deep hardware stack
• Direct, Indirect and Relative Addressing modes
• Processor read access to program memory
• Brown-out detection circuitry for
Brown-out Reset (BOR)
Special Microcontroller Features:
CMOS Technology:
• Power-on Reset (POR)
• Low power, high speed CMOS FLASH technology
• Fully static design
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Wide operating voltage range: 2.0V to 5.5V
• High Sink/Source Current: 25 mA
• Industrial temperature range
• Low power consumption:
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
- < 2 mA typical @ 5V, 4 MHz
- 20 µA typical @ 3V, 32 kHz
- < 1 µA typical standby current
• In-Circuit Serial Programming (ICSP) via two
pins
SSP
Program Memory
(# Single Word
Instructions)
Data
SRAM
(Bytes)
8-bit
A/D (ch) (PWM)
CCP
Timers
8/16-bit
Device
I/O
Interrupts
USART
2
SPI
I C
(Master) (Slave)
PIC16F73
PIC16F74
PIC16F76
PIC16F77
4096
4096
8192
8192
192
192
368
368
22
33
22
33
11
12
11
12
5
8
5
8
2
2
2
2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
2 / 1
2 / 1
2 / 1
2 / 1
2002 Microchip Technology Inc.
DS30325B-page 1
PIC16F7X
Pin Diagrams
DIP, SOIC, SSOP
28
27
26
1
2
3
4
5
6
7
8
9
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
MCLR/VPP
RA0/AN0
RA1/AN1
25
24
23
22
21
20
19
18
17
16
15
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
VSS
10
11
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
12
13
14
RC3/SCK/SCL
MLF
24
25
27 26
23 22
21
28
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
VSS
1
2
3
4
5
6
7
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
20
19
18
17
16
15
PIC16F73
PIC16F76
OSC1/CLKI
OSC2/CLKO
RC7/RX/DT
8
9 10 11 1213 14
PDIP
MCLR/VPP
RA0/AN0
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
RB1
RB0/INT
VDD
9
10
11
12
13
14
15
16
17
18
19
20
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
DS30325B-page 2
2002 Microchip Technology Inc.
PIC16F7X
Pin Diagrams (Continued)
PLCC
RA4/T0CKI
39
38
37
36
35
34
33
32
31
30
29
RB3/PGM
RB2
7
RA5/AN4/SS
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
8
RB1
9
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
10
11
12
13
14
15
PIC16F77
PIC16F74
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CK1
NC
16
17
QFP
NC
33
1
2
3
4
5
6
7
8
9
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3/PGM
RC0/T1OSO/T1CKI
32
31
30
29
28
27
26
OSC2/CLKOUT
OSC1/CLKIN
VSS
PIC16F77
PIC16F74
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS
RA4/T0CKI
25
24
23
10
11
2002 Microchip Technology Inc.
DS30325B-page 3
PIC16F7X
Table of Contents
1.0 Device Overview......................................................................................................................................................................... 5
2.0 Memory Organization................................................................................................................................................................ 13
3.0 Reading Program Memory........................................................................................................................................................ 29
4.0 I/O Ports.................................................................................................................................................................................... 31
5.0 Timer0 Module.......................................................................................................................................................................... 43
6.0 Timer1 Module.......................................................................................................................................................................... 47
7.0 Timer2 Module.......................................................................................................................................................................... 51
8.0 Capture/Compare/PWM Modules............................................................................................................................................. 53
9.0 Synchronous Serial Port (SSP) Module.................................................................................................................................... 59
10.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) ................................................................................... 69
11.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................ 83
12.0 Special Features of the CPU .................................................................................................................................................... 89
13.0 Instruction Set Summary......................................................................................................................................................... 105
14.0 Development Support ............................................................................................................................................................. 113
15.0 Electrical Characteristics......................................................................................................................................................... 119
16.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 141
17.0 Packaging Information ............................................................................................................................................................ 151
Appendix A: Revision History ........................................................................................................................................................ 161
Appendix B: Device Differences .................................................................................................................................................... 161
Appendix C: Conversion Considerations ....................................................................................................................................... 162
Index ................................................................................................................................................................................................. 163
On-Line Support................................................................................................................................................................................ 169
Reader Response ............................................................................................................................................................................. 170
PIC16F7X Product Identification System.......................................................................................................................................... 171
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An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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DS30325B-page 4
2002 Microchip Technology Inc.
PIC16F7X
The available features are summarized in Table 1-1.
Block diagrams of the PIC16F73/76 and PIC16F74/77
devices are provided in Figure 1-1 and Figure 1-2,
respectively. The pinouts for these device families are
listed in Table 1-2 and Table 1-3.
1.0
DEVICE OVERVIEW
This document contains device specific information
about the following devices:
• PIC16F73
• PIC16F74
• PIC16F76
• PIC16F77
Additional information may be found in the PICmicro™
Mid-Range Reference Manual (DS33023), which may
be obtained from your local Microchip Sales Represen-
tative or downloaded from the Microchip website. The
Reference Manual should be considered a complemen-
tary document to this data sheet, and is highly recom-
mended reading for a better understanding of the device
architecture and operation of the peripheral modules.
PIC16F73/76 devices are available only in 28-pin pack-
ages, while PIC16F74/77 devices are available in
40-pin and 44-pin packages. All devices in the
PIC16F7X family share common architecture, with the
following differences:
• The PIC16F73 and PIC16F76 have one-half of
the total on-chip memory of the PIC16F74 and
PIC16F77
• The 28-pin devices have 3 I/O ports, while the
40/44-pin devices have 5
• The 28-pin devices have 11 interrupts, while the
40/44-pin devices have 12
• The 28-pin devices have 5 A/D input channels,
while the 40/44-pin devices have 8
• The Parallel Slave Port is implemented only on
the 40/44-pin devices
TABLE 1-1:
PIC16F7X DEVICE FEATURES
Key Features
PIC16F73
PIC16F74
PIC16F76
PIC16F77
Operating Frequency
RESETS (and Delays)
DC - 20 MHz
DC - 20 MHz
DC - 20 MHz
DC - 20 MHz
POR, BOR
POR, BOR
POR, BOR
POR, BOR
(PWRT, OST)
(PWRT, OST)
(PWRT, OST)
(PWRT, OST)
FLASH Program Memory
(14-bit words)
4K
4K
8K
8K
Data Memory (bytes)
Interrupts
192
192
368
368
11
12
11
12
I/O Ports
Ports A,B,C
Ports A,B,C,D,E
Ports A,B,C
Ports A,B,C,D,E
Timers
3
3
3
3
Capture/Compare/PWM Modules
Serial Communications
Parallel Communications
8-bit Analog-to-Digital Module
Instruction Set
2
SSP, USART
—
2
2
SSP, USART
—
2
SSP, USART
PSP
SSP, USART
PSP
5 Input Channels 8 Input Channels 5 Input Channels 8 Input Channels
35 Instructions
35 Instructions
35 Instructions
35 Instructions
Packaging
28-pin DIP
28-pin SOIC
28-pin SSOP
28-pin MLF
40-pin PDIP
44-pin PLCC
44-pin TQFP
28-pin DIP
28-pin SOIC
28-pin SSOP
28-pin MLF
40-pin PDIP
44-pin PLCC
44-pin TQFP
2002 Microchip Technology Inc.
DS30325B-page 5
PIC16F7X
FIGURE 1-1:
PIC16F73 AND PIC16F76 BLOCK DIAGRAM
13
8
PORTA
PORTB
PORTC
Data Bus
Program Counter
RA0/AN0
RA1/AN1
RA2/AN2/
FLASH
Program
Memory
RAM
File
Registers
8 Level Stack
(13-bit)
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
Program
Bus
14
RAM Addr(1)
9
RB0/INT
RB1
Addr MUX
Instruction reg
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
Indirect
Addr
7
Direct Addr
8
FSR reg
STATUS reg
8
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
3
MUX
Power-up
Timer
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Oscillator
Instruction
Decode &
Control
Start-up Timer
ALU
Power-on
Reset
8
Timing
Generation
Watchdog
Timer
W reg
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Reset
MCLR VDD, VSS
Timer0
CCP1
Timer1
CCP2
Timer2
8-bit A/D
Synchronous
Serial Port
USART
Device
Program FLASH
Data Memory
PIC16F73
PIC16F76
4K
8K
192 Bytes
368 Bytes
Note 1: Higher order bits are from the STATUS register.
DS30325B-page 6
2002 Microchip Technology Inc.
PIC16F7X
FIGURE 1-2:
PIC16F74 AND PIC16F77 BLOCK DIAGRAM
13
8
PORTA
Data Bus
RAM
Program Counter
RA0/AN0
RA1/AN1
RA2/AN2
FLASH
Program
Memory
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
8 Level Stack
(13-bit)
File
Registers
Program
Bus
14
RAM Addr(1)
PORTB
9
RB0/INT
RB1
RB2
RB3/PGM
RB4
Addr MUX
Instruction reg
Indirect
Addr
7
Direct Addr
8
RB5
FSR reg
RB6/PGC
RB7/PGD
STATUS reg
8
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
3
MUX
Power-up
Timer
Oscillator
Start-up Timer
Instruction
Decode &
Control
ALU
RC6/TX/CK
RC7/RX/DT
Power-on
Reset
8
PORTD
Timing
Generation
Watchdog
Timer
W reg
RD0/PSP0
RD1/PSP1
RD2/PSP2
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Reset
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
MCLR VDD, VSS
PORTE
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
Timer0
CCP1
Timer1
CCP2
Timer2
8-bit A/D
Synchronous
Serial Port
USART
Parallel Slave Port
Device
Program FLASH
Data Memory
192 Bytes
PIC16F74
PIC16F77
4K
8K
368 Bytes
Note 1: Higher order bits are from the STATUS register.
2002 Microchip Technology Inc.
DS30325B-page 7
PIC16F7X
TABLE 1-2:
PIC16F73 AND PIC16F76 PINOUT DESCRIPTION
DIP
SSOP
SOIC
Pin#
MLF
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
(3)
OSC1/CLKI
OSC1
9
6
ST/CMOS
Oscillator crystal or external clock input.
I
I
Oscillator crystal input or external clock source input. ST
buffer when configured in RC mode. Otherwise CMOS.
External clock source input. Always associated with pin
function OSC1 (see OSC1/CLKI, OSC2/CLKO pins).
CLKI
OSC2/CLKO
OSC2
10
7
—
Oscillator crystal or clock output.
O
O
Oscillator crystal output.
Connects to crystal or resonator in Crystal Oscillator
mode.
In RC mode, OSC2 pin outputs CLKO, which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
CLKO
MCLR/VPP
MCLR
1
26
ST
Master Clear (input) or programming voltage (output).
Master Clear (Reset) input. This pin is an active low
RESET to the device.
I
VPP
P
Programming voltage input.
PORTA is a bi-directional I/O port.
RA0/AN0
RA0
2
3
4
5
27
28
1
TTL
TTL
TTL
TTL
I/O
I
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
Digital I/O.
Analog input 1.
AN1
RA2/AN2
RA2
I/O
I
Digital I/O.
Analog input 2.
AN2
RA3/AN3/VREF
RA3
2
I/O
Digital I/O.
AN3
VREF
I
I
Analog input 3.
A/D reference voltage input.
RA4/T0CKI
RA4
6
7
4
5
ST
I/O
I
Digital I/O – Open drain when configured as output.
Timer0 external clock input.
T0CKI
RA5/SS/AN4
RA5
TTL
I/O
Digital I/O.
SS
AN4
I
I
SPI slave select input.
Analog input 4.
Legend:
I = input
— = Not used
O = output
TTL = TTL input
I/O = input/output
ST = Schmitt Trigger input
P = power
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
DS30325B-page 8
2002 Microchip Technology Inc.
PIC16F7X
TABLE 1-2:
PIC16F73 AND PIC16F76 PINOUT DESCRIPTION (CONTINUED)
DIP
SSOP
SOIC
Pin#
MLF
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
RB0/INT
RB0
21
18
TTL/ST
I/O
I
Digital I/O.
External interrupt.
INT
I/O
I/O
RB1
RB2
22
23
24
19
20
21
TTL
TTL
TTL
Digital I/O.
Digital I/O.
RB3/PGM
RB3
I/O
I/O
Digital I/O.
PGM
Low voltage ICSP programming enable pin.
I/O
I/O
RB4
RB5
25
26
27
22
23
24
TTL
TTL
Digital I/O.
Digital I/O.
(2)
(2)
RB6/PGC
RB6
TTL/ST
I/O
I/O
Digital I/O.
PGC
In-Circuit Debugger and ICSP programming clock.
RB7/PGD
RB7
28
25
TTL/ST
I/O
I/O
Digital I/O.
PGD
In-Circuit Debugger and ICSP programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC0
11
12
8
9
ST
ST
I/O
O
I
Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
T1OSO
T1CKI
RC1/T1OSI/CCP2
RC1
I/O
I
Digital I/O.
Timer1 oscillator input.
T1OSI
CCP2
I/O
Capture2 input, Compare2 output, PWM2 output.
RC2/CCP1
RC2
13
14
10
11
ST
ST
I/O
I/O
Digital I/O.
CCP1
Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL
RC3
I/O
I/O
I/O
Digital I/O.
SCK
SCL
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I C mode.
2
RC4/SDI/SDA
RC4
15
12
ST
I/O
I
I/O
Digital I/O.
SDI
SDA
SPI data in.
2
I C data I/O.
RC5/SDO
RC5
16
17
13
14
ST
ST
I/O
O
Digital I/O.
SPI data out.
SDO
RC6/TX/CK
RC6
TX
CK
I/O
O
I/O
Digital I/O.
USART asynchronous transmit.
USART 1 synchronous clock.
RC7/RX/DT
18
15
ST
RC7
RX
DT
I/O
I
I/O
Digital I/O.
USART asynchronous receive.
USART synchronous data.
VSS
VDD
8, 19
20
5, 16
P
P
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
17
Legend:
I = input
— = Not used
O = output
TTL = TTL input
I/O = input/output
ST = Schmitt Trigger input
P = power
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
2002 Microchip Technology Inc.
DS30325B-page 9
PIC16F7X
TABLE 1-3:
PIC16F74 AND PIC16F77 PINOUT DESCRIPTION
DIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
(4)
OSC1/CLKI
OSC1
13
14
30
ST/CMOS
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode. Otherwise
CMOS.
I
I
CLKI
External clock source input. Always associated with pin
function OSC1 (see OSC1/CLKI, OSC2/CLKO pins).
OSC2/CLKO
OSC2
14
15
31
—
Oscillator crystal or clock output.
Oscillator crystal output.
O
O
Connects to crystal or resonator in Crystal Oscillator
mode.
In RC mode, OSC2 pin outputs CLKO, which has 1/4
the frequency of OSC1 and denotes the instruction
cycle rate.
CLKO
MCLR/VPP
MCLR
1
2
18
ST
Master Clear (input) or programming voltage (output).
Master Clear (Reset) input. This pin is an active low
RESET to the device.
I
VPP
P
Programming voltage input.
PORTA is a bi-directional I/O port.
RA0/AN0
RA0
2
3
4
5
3
4
5
6
19
20
21
22
TTL
TTL
TTL
TTL
I/O
I
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
Digital I/O.
Analog input 1.
AN1
RA2/AN2
RA2
I/O
I
Digital I/O.
Analog input 2.
AN2
RA3/AN3/VREF
RA3
I/O
Digital I/O.
AN3
VREF
I
I
Analog input 3.
A/D reference voltage input.
RA4/T0CKI
RA4
6
7
7
8
23
24
ST
I/O
I
Digital I/O – Open drain when configured as output.
Timer0 external clock input.
T0CKI
RA5/SS/AN4
RA5
TTL
I/O
Digital I/O.
SS
AN4
I
I
SPI slave select input.
Analog input 4.
Legend:
I = input
— = Not used
O = output
TTL = TTL input
I/O = input/output
ST = Schmitt Trigger input
P = power
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
DS30325B-page 10
2002 Microchip Technology Inc.
PIC16F7X
TABLE 1-3:
PIC16F74 AND PIC16F77 PINOUT DESCRIPTION (CONTINUED)
DIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
RB0/INT
RB0
33
36
8
TTL/ST
I/O
I
Digital I/O.
External interrupt.
INT
I/O
I/O
RB1
RB2
34
35
36
37
38
39
9
TTL
TTL
TTL
Digital I/O.
Digital I/O.
10
11
RB3/PGM
RB3
I/O
I/O
Digital I/O.
PGM
Low voltage ICSP programming enable pin.
I/O
I/O
RB4
RB5
37
38
39
41
42
43
14
15
16
TTL
TTL
Digital I/O.
Digital I/O.
(2)
(2)
RB6/PGC
RB6
TTL/ST
I/O
I/O
Digital I/O.
PGC
In-Circuit Debugger and ICSP programming clock.
RB7/PGD
RB7
40
44
17
TTL/ST
I/O
I/O
Digital I/O.
PGD
In-Circuit Debugger and ICSP programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC0
15
16
16
18
32
35
ST
ST
I/O
O
I
Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
T1OSO
T1CKI
RC1/T1OSI/CCP2
RC1
I/O
I
Digital I/O.
Timer1 oscillator input.
T1OSI
CCP2
I/O
Capture2 input, Compare2 output, PWM2 output.
RC2/CCP1
RC2
17
18
19
20
36
37
ST
ST
I/O
I/O
Digital I/O.
CCP1
Capture1 input/Compare1 output/PWM1 output
RC3/SCK/SCL
RC3
I/O
I/O
I/O
Digital I/O
SCK
SCL
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I C mode.
2
RC4/SDI/SDA
RC4
23
25
42
ST
I/O
I
I/O
Digital I/O.
SDI
SDA
SPI data in.
2
I C data I/O.
RC5/SDO
RC5
24
25
26
27
43
44
ST
ST
I/O
O
Digital I/O.
SPI data out.
SDO
RC6/TX/CK
RC6
TX
CK
I/O
O
I/O
Digital I/O.
USART asynchronous transmit.
USART 1 synchronous clock.
RC7/RX/DT
26
29
1
ST
RC7
RX
DT
I/O
I
I/O
Digital I/O.
USART asynchronous receive.
USART synchronous data.
Legend:
I = input
— = Not used
O = output
TTL = TTL input
I/O = input/output
ST = Schmitt Trigger input
P = power
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
2002 Microchip Technology Inc.
DS30325B-page 11
PIC16F7X
TABLE 1-3:
PIC16F74 AND PIC16F77 PINOUT DESCRIPTION (CONTINUED)
DIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
PORTD is a bi-directional I/O port or parallel slave port
when interfacing to a microprocessor bus.
(3)
RD0/PSP0
RD0
19
20
21
22
27
28
29
30
21
22
23
24
30
31
32
33
38
39
40
41
2
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
I/O
I/O
Digital I/O.
Parallel Slave Port data.
PSP0
(3)
(3)
(3)
(3)
(3)
(3)
(3)
RD1/PSP1
RD1
I
I/O
I/O
Digital I/O.
Parallel Slave Port data.
PSP1
RD2/PSP2
RD2
I
I/O
I/O
Digital I/O.
Parallel Slave Port data.
PSP2
RD3/PSP3
RD3
I/O
I/O
Digital I/O.
Parallel Slave Port data.
PSP3
RD4/PSP4
RD4
I/O
I/O
Digital I/O.
Parallel Slave Port data.
PSP4
RD5/PSP5
RD5
3
I/O
I/O
Digital I/O.
Parallel Slave Port data.
PSP5
RD6/PSP6
RD6
4
I/O
I/O
Digital I/O.
Parallel Slave Port data.
PSP6
RD7/PSP7
RD7
5
I/O
I/O
Digital I/O.
Parallel Slave Port data.
PSP7
PORTE is a bi-directional I/O port.
(3)
(3)
(3)
RE0/RD/AN5
RE0
8
9
9
25
26
27
ST/TTL
ST/TTL
ST/TTL
I/O
I
I
Digital I/O.
Read control for parallel slave port .
Analog input 5.
RD
AN5
RE1/WR/AN6
RE1
10
11
I/O
I
I
Digital I/O.
Write control for parallel slave port .
Analog input 6.
WR
AN6
RE2/CS/AN7
RE2
10
I/O
Digital I/O.
CS
AN7
I
I
Chip select control for parallel slave port .
Analog input 7.
VSS
VDD
NC
12,31 13,34
11,32 12,35
6,29
7,28
P
P
—
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
—
1,17,2 12,13,
8, 40 33, 34
These pins are not internally connected. These pins should
be left unconnected.
Legend:
I = input
— = Not used
O = output
TTL = TTL input
I/O = input/output
ST = Schmitt Trigger input
P = power
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
DS30325B-page 12
2002 Microchip Technology Inc.
PIC16F7X
2.2
Data Memory Organization
2.0
MEMORY ORGANIZATION
The Data Memory is partitioned into multiple banks,
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>)
and RP0 (STATUS<5>) are the bank select bits:
There are two memory blocks in each of these
PICmicro® MCUs. The Program Memory and Data
Memory have separate buses so that concurrent
access can occur and is detailed in this section. The
Program Memory can be read internally by user code
(see Section 3.0).
RP1:RP0
Bank
00
01
10
11
0
1
2
3
Additional information on device memory may be found
in the PICmicro Mid-Range Reference Manual
(DS33023).
2.1
Program Memory Organization
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
The PIC16F7X devices have a 13-bit program counter
capable of addressing an 8K word x 14-bit program
memory space. The PIC16F77/76 devices have
8K words of FLASH program memory and the
PIC16F73/74 devices have 4K words. The program
memory maps for PIC16F7X devices are shown in
Figure 2-1. Accessing a location above the physically
implemented address will cause a wraparound.
2.2.1
GENERAL PURPOSE REGISTER
FILE
The RESET Vector is at 0000h and the Interrupt Vector
is at 0004h.
The register file (shown in Figure 2-2 and Figure 2-3)
can be accessed either directly, or indirectly, through
the File Select Register FSR.
FIGURE 2-1:
PROGRAM MEMORY MAPS AND STACKS FOR PIC16F7X DEVICES
PIC16F76/77
PIC16F73/74
PC<12:0>
PC<12:0>
13
13
CALL, RETURN
CALL, RETURN
RETFIE, RETLW
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 1
Stack Level 2
Stack Level 8
Stack Level 8
RESET Vector
Interrupt Vector
0000h
0000h
RESET Vector
Interrupt Vector
0004h
0005h
0004h
0005h
Page 0
Page 0
On-Chip
Program
Memory
07FFh
0800h
07FFh
0800h
Page 1
Page 2
Page 3
Page 1
On-Chip
Program
Memory
0FFFh
1000h
0FFFh
1000h
Unimplemented
Read as ‘0’
17FFh
1800h
1FFFh
1FFFh
2002 Microchip Technology Inc.
DS30325B-page 13
PIC16F7X
FIGURE 2-2:
PIC16F77/76 REGISTER FILE MAP
File
Address
File
Address
File
Address
File
Address
Indirect addr.(*)
Indirect addr.(*)
OPTION_REG
PCL
Indirect addr.(*)
80h
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
Indirect addr.(*)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
TMR0
TMR0
PCL
OPTION_REG 81h
PCL
STATUS
FSR
PCL
STATUS
FSR
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
STATUS
FSR
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(1)
PORTE(1)
PCLATH
INTCON
PIR1
TRISA
TRISB
TRISC
TRISD(1)
TRISE(1)
TRISB
PORTB
PCLATH
INTCON
PCLATH
INTCON
PMCON1
PCLATH
INTCON
PIE1
PMDATA
PMADR
PIR2
PIE2
TMR1L
TMR1H
T1CON
TMR2
PCON
PMDATH
PMADRH
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
PR2
SSPADD
SSPSTAT
General
Purpose
Register
General
Purpose
Register
RCSTA
TXREG
TXSTA
16 Bytes
16 Bytes
SPBRG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
ADCON1
1A0h
A0h
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
80 Bytes
80 Bytes
80 Bytes
1EFh
1F0h
96 Bytes
EFh
F0h
16Fh
170h
accesses
70h - 7Fh
accesses
70h-7Fh
accesses
70h-7Fh
17Fh
1FFh
7Fh
FFh
Bank 3
Bank 1
Bank 2
Bank 0
Unimplemented data memory locations, read as ’0’.
*
Not a physical register.
Note 1: These registers are not implemented on 28-pin devices.
DS30325B-page 14
2002 Microchip Technology Inc.
PIC16F7X
FIGURE 2-3:
PIC16F74/73 REGISTER FILE MAP
File
Address
File
Address
File
Address
File
Address
Indirect addr.(*)
Indirect addr.(*)
180h
OPTION_REG
181h
Indirect addr.(*)
80h
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
Indirect addr.(*)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
TMR0
PCL
TMR0
PCL
OPTION_REG 81h
PCL
STATUS
FSR
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
PCL
STATUS
FSR
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
STATUS
FSR
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(1)
PORTE(1)
PCLATH
INTCON
PIR1
TRISA
TRISB
TRISC
TRISD(1)
TRISE(1)
TRISB
PORTB
PCLATH
INTCON
PCLATH
INTCON
PMCON1
PCLATH
INTCON
PIE1
PMDATA
PMADR
PIR2
PIE2
TMR1L
TMR1H
T1CON
TMR2
PCON
PMDATH
PMADRH
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
PR2
SSPADD
SSPSTAT
RCSTA
TXREG
TXSTA
SPBRG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
ADCON1
1A0h
120h
A0h
General
Purpose
Register
General
Purpose
Register
accesses
20h-7Fh
accesses
A0h - FFh
1EFh
1F0h
96 Bytes
96 Bytes
16Fh
170h
17Fh
1FFh
7Fh
FFh
Bank 3
Bank 1
Bank 2
Bank 0
Unimplemented data memory locations, read as ’0’.
*
Not a physical register.
Note 1: These registers are not implemented on 28-pin devices.
2002 Microchip Technology Inc.
DS30325B-page 15
PIC16F7X
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY
Value on:
POR,
BOR
Details
on page
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0
(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
27, 96
45, 96
26, 96
00h
01h
TMR0
PCL
Timer0 Module Register
xxxx xxxx
0000 0000
(4)
Program Counter (PC) Least Significant Byte
02h
(4)
STATUS
IRP
Indirect Data Memory Address Pointer
PORTA Data Latch when written: PORTA pins when read
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
xxxx xxxx
19, 96
27, 96
03h
(4)
FSR
04h
05h
06h
07h
PORTA
PORTB
PORTC
PORTD
—
—
--0x 0000
xxxx xxxx
xxxx xxxx
32, 96
34, 96
35, 96
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
(5)
xxxx xxxx
---- -xxx
---0 0000
0000 000x
36, 96
39, 96
26, 96
21, 96
23, 96
08h
(5)
PORTE
PCLATH
INTCON
—
—
—
—
—
—
—
—
RE2
RE1
RE0
09h
(1,4)
Write Buffer for the upper 5 bits of the Program Counter
0Ah
(4)
GIE
PEIE
ADIF
—
TMR0IE
RCIF
—
INTE
TXIF
—
RBIE
SSPIF
—
TMR0IF
CCP1IF
—
INTF
TMR2IF
—
RBIF
0Bh
(3)
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
PIR1
TMR1IF 0000 0000
PSPIF
PIR2
—
CCP2IF ---- ---0
xxxx xxxx
24, 96
50, 96
50, 96
47, 96
52, 96
52, 96
TMR1L
TMR1H
T1CON
TMR2
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000
Timer2 Module Register
0000 0000
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
—
TOUTPS3 TOUTPS2 TOUTPS TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx 64, 68, 96
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0 0000 0000
61, 96
56, 96
56, 96
54, 96
70, 96
74, 96
76, 96
58, 96
58, 96
54, 96
88, 96
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx
xxxx xxxx
—
—
CCP1X
SREN
CCP1Y
CREN
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000
SPEN
RX9
—
FERR
OERR
RX9D
0000 -00x
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
USART Transmit Data Register
USART Receive Data Register
Capture/Compare/PWM Register2 (LSB)
Capture/Compare/PWM Register2 (MSB)
—
—
CCP2X
CCP2Y
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000
A/D Result Register Byte
xxxx xxxx
GO/
DONE
1Fh
ADCON0
ADCS1 ADCS0
CHS2
CHS1
CHS0
—
ADON
0000 00-0
83, 96
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter during branches (CALLor GOTO).
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
DS30325B-page 16
2002 Microchip Technology Inc.
PIC16F7X
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on:
POR,
BOR
Details
on page
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 1
(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
27, 96
80h
81h
OPTION_REG RBPU
INTEDG
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect data memory address pointer
PORTA Data Direction Register
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 20, 44, 96
(4)
PCL
0000 0000
0001 1xxx
26, 96
19, 96
82h
(4)
STATUS
PD
Z
DC
C
83h
(4)
FSR
xxxx xxxx
--11 1111
1111 1111
1111 1111
1111 1111
27, 96
32, 96
34, 96
35, 96
36, 96
84h
85h
86h
87h
TRISA
TRISB
TRISC
TRISD
—
—
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
(5)
88h
(5)
TRISE
IBF
—
OBF
—
IBOV
—
PSPMODE
—
PORTE Data Direction Bits
0000 -111
---0 0000
0000 000x
38, 96
21, 96
23, 96
89h
(1,4)
PCLATH
INTCON
Write Buffer for the upper 5 bits of the Program Counter
8Ah
(4)
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
8Bh
(3)
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
PIE1
PIE2
PCON
—
ADIE
—
RCIE
—
TXIE
—
SSPIE
—
CCP1IE
TMR2IE
—
TMR1IE 0000 0000
CCP2IE ---- ---0
22, 96
24, 97
25, 97
—
PSPIE
—
—
—
—
—
—
—
—
POR
BOR
---- --qq
Unimplemented
—
—
—
Unimplemented
—
—
Unimplemented
—
—
PR2
SSPADD
Timer2 Period Register
1111 1111
0000 0000
52, 97
68, 97
2
Synchronous Serial Port (I C mode) Address Register
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
60, 97
—
—
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
TXSTA
SPBRG
—
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
69, 97
71, 97
Baud Rate Generator Register
Unimplemented
0000 0000
—
—
—
—
—
—
Unimplemented
—
Unimplemented
—
Unimplemented
—
Unimplemented
ADCON1
—
—
—
—
—
PCFG2
PCFG1
PCFG0 -----000
84, 97
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter during branches (CALLor GOTO).
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
2002 Microchip Technology Inc.
DS30325B-page 17
PIC16F7X
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on:
POR,
BOR
Details
on page
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 2
(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
27, 96
45, 96
26, 96
100h
101h
TMR0
PCL
Timer0 Module Register
xxxx xxxx
0000 0000
(4)
Program Counter (PC) Least Significant Byte
102h
(4)
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
19, 96
103h
(4)
FSR
—
Indirect Data Memory Address Pointer
Unimplemented
xxxx xxxx
27, 96
—
104h
105h
106h
107h
108h
109h
—
PORTB
—
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx
34, 96
—
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
(1,4)
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
INTE RBIE TMR0IF INTF RBIF
---0 0000
21, 96
10Ah
(4)
INTCON
PMDATA
PMADR
GIE
PEIE
TMR0IE
0000 000x
23, 96
10Bh
10Ch
10Dh
10Eh
10Fh
Data Register Low Byte
Address Register Low Byte
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
29, 97
29, 97
29, 97
PMDATH
PMADRH
—
—
—
—
Data Register High Byte
Address Register High Byte
—
29, 97
Bank 3
(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
27, 96
180h
181h
OPTION_REG RBPU
INTEDG
Program Counter (PC) Least Significant Byte
IRP RP1 RP0 TO
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 20, 44, 96
(4)
PCL
0000 0000
0001 1xxx
xxxx xxxx
26, 96
19, 96
27, 96
182h
(4)
STATUS
PD
Z
DC
C
183h
(4)
FSR
—
Indirect Data Memory Address Pointer
Unimplemented
184h
185h
186h
187h
188h
189h
—
—
34, 96
—
TRISB
—
PORTB Data Direction Register
Unimplemented
1111 1111
—
—
—
—
Unimplemented
—
—
Unimplemented
—
(1,4)
Write Buffer for the upper 5 bits of the Program Counter
PCLATH
—
—
PEIE
—
—
TMR0IE
—
---0 0000
0000 000x
21, 96
23, 96
29, 97
18Ah
(4)
INTCON
GIE
INTE
RBIE
TMR0IF
INTF
RBIF
RD
18Bh
(6)
18Ch
18Dh
18Eh
18Fh
PMCON1
—
—
—
—
1--- ---0
—
—
—
—
—
Unimplemented
Reserved maintain clear
Reserved maintain clear
0000 0000
0000 0000
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter during branches (CALLor GOTO).
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
DS30325B-page 18
2002 Microchip Technology Inc.
PIC16F7X
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
2.2.2.1
STATUS Register
The STATUS register contains the arithmetic status of
the ALU, the RESET status and the bank select bits for
data memory.
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C, or DC bits from the STATUS register.
For other instructions not affecting any status bits, see
the "Instruction Set Summary."
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC, or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable, therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1:
STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0
IRP
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 7
bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1= Bank 2, 3 (100h - 1FFh)
0= Bank 0, 1 (00h - FFh)
bit 6-5
RP1:RP0: Register Bank Select bits (used for direct addressing)
11= Bank 3 (180h - 1FFh)
10= Bank 2 (100h - 17Fh)
01= Bank 1 (80h - FFh)
00= Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4
bit 3
bit 2
bit 1
bit 0
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWFinstructions)
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWFinstructions)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit
- n = Value at POR reset
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
2002 Microchip Technology Inc.
DS30325B-page 19
PIC16F7X
2.2.2.2
OPTION_REG Register
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
The OPTION_REG register is a readable and writable
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
able register known also as the prescaler), the External
INT Interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2:
OPTION_REG REGISTER (ADDRESS 81h, 181h)
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
RBPU: PORTB Pull-up Enable bit
1= PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 1
1 : 2
1 : 4
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
- n = Value at POR reset
W = Writable bit
U = Unimplemented bit, read as ‘0’
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
DS30325B-page 20
2002 Microchip Technology Inc.
PIC16F7X
2.2.2.3
INTCON Register
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The INTCON register is a readable and writable regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
REGISTER 2-3:
INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
R/W-0
INTE
R/W-0
RBIE
R/W-0
R/W-0
INTF
R/W-x
RBIF
TMR0IE
TMR0IF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
GIE: Global Interrupt Enable bit
1= Enables all unmasked interrupts
0= Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1= Enables the RB0/INT external interrupt
0= Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1= The RB0/INT external interrupt occurred (must be cleared in software)
0= The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch
condition and allow flag bit RBIF to be cleared.
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
2002 Microchip Technology Inc.
DS30325B-page 21
PIC16F7X
2.2.2.4
PIE1 Register
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
The PIE1 register contains the individual enable bits for
the peripheral interrupts.
REGISTER 2-4:
PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
PSPIE(1)
bit 7
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
R/W-0
R/W-0
TMR1IE
bit 0
CCP1IE
TMR2IE
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D converter interrupt
0= Disables the A/D converter interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
SSPIE: Synchronous Serial Port Interrupt Enable bit
1= Enables the SSP interrupt
0= Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1: PSPIE is reserved on 28-pin devices; always maintain this bit clear.
Legend:
R = Readable bit
- n = Value at POR reset
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
DS30325B-page 22
2002 Microchip Technology Inc.
PIC16F7X
2.2.2.5
PIR1 Register
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate interrupt
bits are clear prior to enabling an interrupt.
The PIR1 register contains the individual flag bits for
the peripheral interrupts.
REGISTER 2-5:
PIR1 REGISTER (ADDRESS 0Ch)
R/W-0
R/W-0
ADIF
R-0
R-0
R/W-0
SSPIF
R/W-0
R/W-0
R/W-0
TMR1IF
bit 0
(1)
PSPIF
bit 7
RCIF
TXIF
CCP1IF
TMR2IF
(1)
bit 7
bit 6
bit 5
bit 4
bit 3
PSPIF : Parallel Slave Port Read/Write Interrupt Flag bit
1= A read or a write operation has taken place (must be cleared in software)
0= No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion is completed (must be cleared in software)
0= The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1= The USART receive buffer is full
0= The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1= The USART transmit buffer is empty
0= The USART transmit buffer is full
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1= The SSP interrupt condition has occurred, and must be cleared in software before
returning from the Interrupt Service Routine. The conditions that will set this bit are:
SPI
A transmission/reception has taken place.
2
I C Slave
A transmission/reception has taken place.
2
I C Master
A transmission/reception has taken place.
The initiated START condition was completed by the SSP module.
The initiated STOP condition was completed by the SSP module.
The initiated Restart condition was completed by the SSP module.
The initiated Acknowledge condition was completed by the SSP module.
A START condition occurred while the SSP module was IDLE (multi-master system).
A STOP condition occurred while the SSP module was IDLE (multi-master system).
0= No SSP interrupt condition has occurred
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Note 1: PSPIF is reserved on 28-pin devices; always maintain this bit clear.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
2002 Microchip Technology Inc.
DS30325B-page 23
PIC16F7X
2.2.2.6
PIE2 Register
The PIE2 register contains the individual enable bits for
the CCP2 peripheral interrupt.
REGISTER 2-6:
PIE2 REGISTER (ADDRESS 8Dh)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
CCP2IE
bit 0
—
—
—
—
—
—
—
bit 7
bit 7-1
bit 0
Unimplemented: Read as '0'
CCP2IE: CCP2 Interrupt Enable bit
1= Enables the CCP2 interrupt
0= Disables the CCP2 interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
2.2.2.7
PIR2 Register
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The PIR2 register contains the flag bits for the CCP2
interrupt.
REGISTER 2-7:
PIR2 REGISTER (ADDRESS 0Dh)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
CCP2IF
bit 0
—
—
—
—
—
—
—
bit 7
bit 7-1
bit 0
Unimplemented: Read as '0'
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
DS30325B-page 24
2002 Microchip Technology Inc.
PIC16F7X
2.2.2.8
PCON Register
Note: BOR is unknown on POR. It must be set by
the user and checked on subsequent
RESETS to see if BOR is clear, indicating
a brown-out has occurred. The BOR status
bit is not predictable if the brown-out circuit
is disabled (by clearing the BODEN bit in
the configuration word).
The Power Control (PCON) register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watchdog Reset
(WDT) and an external MCLR Reset.
REGISTER 2-8:
PCON REGISTER (ADDRESS 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
POR
R/W-1
BOR
—
—
—
—
—
—
bit 7
bit 0
bit 7-2
bit 1
Unimplemented: Read as '0'
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
2002 Microchip Technology Inc.
DS30325B-page 25
PIC16F7X
2.3
PCL and PCLATH
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
The program counter (PC) is 13 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any RESET, the upper bits of the
PC will be cleared. Figure 2-4 shows the two situations
for the loading of the PC. The upper example in the fig-
ure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the fig-
ure shows how the PC is loaded during a CALLor GOTO
instruction (PCLATH<4:3> → PCH).
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an inter-
rupt address.
2.4
Program Memory Paging
PIC16F7X devices are capable of addressing a contin-
uous 8K word block of program memory. The CALLand
GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page.
When doing a CALL or GOTO instruction, the upper 2
bits of the address are provided by PCLATH<4:3>.
When doing a CALLor GOTOinstruction, the user must
ensure that the page select bits are programmed so
that the desired program memory page is addressed. If
a return from a CALL instruction (or interrupt) is exe-
cuted, the entire 13-bit PC is popped off the stack.
Therefore, manipulation of the PCLATH<4:3> bits are
not required for the RETURNinstructions (which POPs
the address from the stack).
FIGURE 2-4:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
Instruction with
PCL as
Destination
PC
8
PCLATH<4:0>
PCLATH
5
ALU
PCH
12 11 10
PC
PCL
Note: The contents of the PCLATH are
unchanged after a RETURN or RETFIE
instruction is executed. The user must
setup the PCLATH for any subsequent
CALLSor GOTOS.
8
7
0
GOTO,CALL
PCLATH<4:3>
PCLATH
11
2
Opcode <10:0>
Example 2-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the Interrupt
Service Routine (if interrupts are used).
2.3.1
COMPUTED GOTO
EXAMPLE 2-1:
CALL OF A SUBROUTINE
IN PAGE 1 FROM PAGE 0
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
ORG
BCF
BSF
0x500
PCLATH,4
PCLATH,3 ;Select page 1
;(800h-FFFh)
Application Note, “Implementing
a Table Read"
CALL SUB1_P1 ;Call subroutine in
:
(AN556).
;page 1 (800h-FFFh)
:
ORG
2.3.2
STACK
0x900
;page 1 (800h-FFFh)
SUB1_P1
RETURN
The PIC16F7X family has an 8-level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed, or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
:
:
:
;called subroutine
;page 1 (800h-FFFh)
;return to Call
;subroutine in page 0
;(000h-7FFh)
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
DS30325B-page 26
2002 Microchip Technology Inc.
PIC16F7X
EXAMPLE 2-2:
INDIRECT ADDRESSING
2.5 Indirect Addressing, INDF and FSR
Registers
MOVLW
MOVWF
0x20
;initialize pointer
;to RAM
FSR
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
NEXT
CLRF
INCF
BTFSS
GOTO
INDF
FSR,F
FSR,4
NEXT
;clear INDF register
;inc pointer
;all done?
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF register
indirectly results in a no operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 2-5.
;no clear next
CONTINUE
:
;yes continue
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
FIGURE 2-5:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
From Opcode
Indirect Addressing
7
RP1:RP0
6
0
0
IRP
FSR Register
Bank Select
Location Select
Bank Select Location Select
00
01
80h
10
100h
11
00h
180h
Data
Memory
(1)
7Fh
Bank 0
FFh
Bank 1
17Fh
Bank 2
1FFh
Bank 3
Note 1: For register file map detail, see Figure 2-2.
2002 Microchip Technology Inc.
DS30325B-page 27
PIC16F7X
NOTES:
DS30325B-page 28
2002 Microchip Technology Inc.
PIC16F7X
When interfacing to the program memory block, the
PMDATH:PMDATA registers form a two-byte word,
which holds the 14-bit data for reads. The
PMADRH:PMADR registers form a two-byte word,
which holds the 13-bit address of the FLASH location
being accessed. These devices can have up to 8K
words of program FLASH, with an address range from
0h to 3FFFh. The unused upper bits in both the
PMDATH and PMADRH registers are not implemented
and read as “0’s”.
3.0
READING PROGRAM MEMORY
The FLASH Program Memory is readable during nor-
mal operation over the entire VDD range. It is indirectly
addressed through Special Function Registers (SFR).
Up to 14-bit numbers can be stored in memory for use
as calibration parameters, serial numbers, packed 7-bit
ASCII, etc. Executing a program memory location con-
taining data that forms an invalid instruction results in a
NOP.
There are five SFRs used to read the program and
memory. These registers are:
3.1
PMADR
• PMCON1
• PMDATA
• PMDATH
• PMADR
The address registers can address up to a maximum of
8K words of program FLASH.
When selecting a program address value, the MSByte
of the address is written to the PMADRH register and
the LSByte is written to the PMADR register. The upper
MSbits of PMADRH must always be clear.
• PMADRH
The program memory allows word reads. Program
memory access allows for checksum calculation and
reading calibration tables.
3.2
PMCON1 Register
PMCON1 is the control register for memory accesses.
The control bit RD initiates read operations. This bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the read operation.
REGISTER 3-1:
PMCON1 REGISTER (ADDRESS 18Ch)
R-1
reserved
bit 7
U-0
U-0
U-0
U-x
U-0
U-0
R/S-0
RD
—
—
—
—
—
—
bit 0
bit 7
Reserved: Read as ‘1’
bit 6-1
bit 0
Unimplemented: Read as '0'
RD: Read Control bit
1= Initiates a FLASH read, RD is cleared in hardware. The RD bit can only be set (not cleared)
in software.
0= FLASH read completed
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
2002 Microchip Technology Inc.
DS30325B-page 29
PIC16F7X
3.3
Reading the FLASH Program
Memory
3.4
Operation During Code Protect
FLASH program memory has its own code protect
mechanism. External Read and Write operations by
programmers are disabled if this mechanism is
enabled.
A program memory location may be read by writing two
bytes of the address to the PMADR and PMADRH reg-
isters and then setting control bit RD (PMCON1<0>).
Once the read control bit is set, the microcontroller will
use the next two instruction cycles to read the data. The
data is available in the PMDATA and PMDATH regis-
ters after the second NOPinstruction. Therefore, it can
be read as two bytes in the following instructions. The
PMDATA and PMDATH registers will hold this value
until the next read operation.
The microcontroller can read and execute instructions
out of the internal FLASH program memory, regardless
of the state of the code protect configuration bits.
EXAMPLE 3-1:
FLASH PROGRAM READ
BSF
BCF
STATUS, RP1
STATUS, RP0
ADDRH, W
PMADRH
ADDRL, W
PMADR
;
; Bank 2
;
MOVF
MOVWF
MOVF
MOVWF
BSF
; MSByte of Program Address to read
;
; LSByte of Program Address to read
; Bank 3 Required
STATUS, RP0
Required
Sequence
BSF
NOP
NOP
PMCON1, RD
; EEPROM Read Sequence
; memory is read in the next two cycles after BSF PMCON1,RD
;
BCF
MOVF
MOVF
STATUS, RP0
PMDATA, W
PMDATH, W
; Bank 2
; W = LSByte of Program PMDATA
; W = MSByte of Program PMDATA
TABLE 3-1:
REGISTERS ASSOCIATED WITH PROGRAM FLASH
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
10Dh
10Fh
10Ch
10Eh
18Ch
PMADR Address Register Low Byte
PMADRH
PMDATA Data Register Low Byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1--- ---0 1--- ---0
—
—
—
Address Register High Byte
PMDATH
PMCON1
—
—
—
Data Register High Byte
(1)
—
—
—
—
—
—
RD
Legend: x= unknown, u= unchanged, r = reserved, -= unimplemented read as '0'. Shaded cells are not used during FLASH access.
Note 1: This bit always reads as a ‘1’.
DS30325B-page 30
2002 Microchip Technology Inc.
PIC16F7X
FIGURE 4-1:
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
4.0
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Data Bus
D
Q
Q
VDD
P
WR Port
CK
Additional information on I/O ports may be found in the
PICmicro™
Mid-Range
Reference
Manual,
Data Latch
(DS33023).
I/O pin(1)
N
D
Q
Q
4.1
PORTA and the TRISA Register
PORTA is a 6-bit wide, bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= ‘1’) will make the corresponding PORTA
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISA bit (= ‘0’) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
WR TRIS
RD TRIS
RD PORT
VSS
Analog
Input
CK
TRIS Latch
Mode
TTL
Input
Buffer
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
Q
D
EN
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
To A/D Converter
Note 1: I/O pins have protection diodes to VDD and VSS.
Other PORTA pins are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
FIGURE 4-2:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
Data Bus
D
Q
Q
Note: On a Power-on Reset, these pins are con-
figured as analog inputs and read as '0'.
WR PORT
CK
I/O pin(1)
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set, when using them as analog inputs.
N
Data Latch
D
Q
VSS
WRTRIS
RD TRIS
Schmitt
Trigger
Input
Q
CK
EXAMPLE 4-1:
INITIALIZING PORTA
TRIS Latch
Buffer
BCF
STATUS, RP0
;
BCF
CLRF
STATUS, RP1
PORTA
; Bank0
; Initialize PORTA by
; clearing output
; data latches
Q
D
BSF
STATUS, RP0
0x06
ADCON1
0xCF
; Select Bank 1
; Configure all pins
; as digital inputs
; Value used to
; initialize data
; direction
MOVLW
MOVWF
MOVLW
EN
RD PORT
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6>are always
; read as ’0’.
TMR0 Clock Input
Note 1: I/O pin has protection diodes to VSS only.
2002 Microchip Technology Inc.
DS30325B-page 31
PIC16F7X
TABLE 4-1:
Name
PORTA FUNCTIONS
Bit#
Buffer
Function
RA0/AN0
bit0
bit1
bit2
bit3
bit4
bit5
TTL
TTL
TTL
TTL
ST
Input/output or analog input.
Input/output or analog input.
Input/output or analog input.
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
Input/output or analog input or VREF.
Input/output or external clock input for Timer0. Output is open drain type.
Input/output or slave select input for synchronous serial port or analog input.
TTL
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 4-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on: Value on all
Address Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other
RESETS
--0x 0000 --0u 0000
--11 1111 --11 1111
---- -000 ---- -000
05h
85h
9Fh
PORTA
TRISA
—
—
—
—
—
—
RA5
RA4
RA3
RA2
RA1
RA0
PORTA Data Direction Register
PCFG2 PCFG1 PCFG0
ADCON1
—
—
—
Legend: x= unknown, u= unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note: When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of
the following modes where PCFG2:PCFG0 = 100, 101, 11x.
DS30325B-page 32
2002 Microchip Technology Inc.
PIC16F7X
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
4.2
PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= ‘1’) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISB bit (= ‘0’) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
This interrupt on mismatch feature, together with soft-
ware configureable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the Embedded
Control Handbook, “Implementing Wake-up on Key
Stroke” (AN552).
FIGURE 4-3:
BLOCK DIAGRAM OF
RB3:RB0 PINS
VDD
RBPU(2)
Weak
Pull-up
P
Data Latch
RB0/INT is an external interrupt input pin and is config-
ured using the INTEDG bit (OPTION_REG<6>).
Data Bus
WR Port
D
Q
I/O
pin(1)
RB0/INT is discussed in detail in Section 12.11.1.
CK
TRIS Latch
FIGURE 4-4:
BLOCK DIAGRAM OF
RB7:RB4 PINS
D
Q
TTL
Input
Buffer
WR TRIS
CK
VDD
RBPU(2)
Weak
P
Pull-up
RD TRIS
RD Port
RB0/INT
Data Latch
Data Bus
WR Port
D
Q
Q
D
I/O
pin(1)
CK
TRIS Latch
EN
D
Q
WR TRIS
RD TRIS
TTL
Input
Buffer
Schmitt Trigger
Buffer
RD Port
CK
ST
Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
Latch
Q
Q
D
Four of the PORTB pins (RB7:RB4) have an inter-
rupt-on-change feature. Only pins configured as inputs
can cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the inter-
rupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are ORed together to generate the RB Port
Change Interrupt with flag bit RBIF (INTCON<0>).
RD Port
EN
Q1
Set RBIF
D
RD Port
Q3
From other
RB7:RB4 pins
EN
RB7:RB6 in Serial Programming mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
2002 Microchip Technology Inc.
DS30325B-page 33
PIC16F7X
TABLE 4-3:
PORTB FUNCTIONS
Name
Bit#
Buffer
Function
RB0/INT
bit0
TTL/ST(1)
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1
RB2
RB3
RB4
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB5
RB6
RB7
bit5
bit6
bit7
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
TTL/ST(2)
TTL/ST(2)
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up. Serial programming clock.
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 4-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
06h, 106h
86h, 186h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
PS2
RB1
PS1
RB0 xxxx xxxx uuuu uuuu
TRISB
PORTB Data Direction Register
RBPU INTEDG T0CS T0SE PSA
1111 1111 1111 1111
81h, 181h
OPTION_REG
PS0 1111 1111 1111 1111
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.
DS30325B-page 34
2002 Microchip Technology Inc.
PIC16F7X
FIGURE 4-5:
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE)
4.3
PORTC and the TRISC Register
PORTC is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= ‘1’) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISC bit (= ‘0’) will
make the corresponding PORTC pin an output (i.e., put
the contents of the output latch on the selected pin).
Port/Peripheral Select(2)
Peripheral Data Out
Data Bus
VDD
P
0
1
D
Q
WR Port
Q
CK
PORTC is multiplexed with several peripheral functions
(Table 4-5). PORTC pins have Schmitt Trigger input
buffers.
Data Latch
I/O
pin(1)
D
Q
Q
WR TRIS
RD TRIS
CK
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is
in effect while the peripheral is enabled,
read-modify-write instructions (BSF, BCF, XORWF)
with TRISC as destination should be avoided. The user
should refer to the corresponding peripheral section for
the correct TRIS bit settings, and to Section 13.1 for
additional information on read-modify-write operations.
N
TRIS Latch
VSS
Schmitt
Trigger
Peripheral
OE(3)
Q
D
EN
RD Port
Peripheral Input
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port data
and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
TABLE 4-5:
Name
PORTC FUNCTIONS
Bit# Buffer Type
Function
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
bit0
bit1
ST
ST
Input/output port pin or Timer1 oscillator output/Timer1 clock input.
Input/output port pin or Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output.
RC2/CCP1
bit2
bit3
ST
ST
Input/output port pin or Capture1 input/Compare1 output/PWM1 output.
RC3 can also be the synchronous serial clock for both SPI and I2C
RC3/SCK/SCL
modes.
RC4/SDI/SDA
RC5/SDO
bit4
bit5
bit6
ST
ST
ST
RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode).
Input/output port pin or Synchronous Serial Port data output.
RC6/TX/CK
Input/output port pin or USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
bit7
ST
Input/output port pin or USART Asynchronous Receive or
Synchronous Data.
Legend: ST = Schmitt Trigger input
TABLE 4-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on:
POR,
BOR
Value on
all other
RESETS
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
07h
87h
PORTC RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0 xxxx xxxx uuuu uuuu
TRISC PORTC Data Direction Register
1111 1111 1111 1111
Legend: x= unknown, u= unchanged
2002 Microchip Technology Inc.
DS30325B-page 35
PIC16F7X
FIGURE 4-6:
PORTD BLOCK DIAGRAM
(IN I/O PORT MODE)
4.4
PORTD and TRISD Registers
This section is not applicable to the PIC16F73 or
PIC16F76.
Data Bus
WR Port
D
Q
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configureable as an input or
output.
I/O pin(1)
CK
Data Latch
PORTD can be configured as an 8-bit wide micro-
processor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL.
D
Q
Schmitt
Trigger
Input
WR TRIS
RD TRIS
CK
TRIS Latch
Buffer
Q
D
EN
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 4-7:
PORTD FUNCTIONS
Name
Bit#
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Buffer Type
Function
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
Input/output port pin or parallel slave port bit0
Input/output port pin or parallel slave port bit1
Input/output port pin or parallel slave port bit2
Input/output port pin or parallel slave port bit3
Input/output port pin or parallel slave port bit4
Input/output port pin or parallel slave port bit5
Input/output port pin or parallel slave port bit6
Input/output port pin or parallel slave port bit7
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 4-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
RD3
—
Bit 2
Bit 1
Bit 0
08h
88h
89h
PORTD
TRISD
TRISE
RD7
RD6
RD5
RD4
RD2
RD1
RD0
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 -111 0000 -111
PORTD Data Direction Register
IBF OBF IBOV PSPMODE
PORTE Data Direction bits
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PORTD.
DS30325B-page 36
2002 Microchip Technology Inc.
PIC16F7X
FIGURE 4-7:
PORTE BLOCK DIAGRAM
(IN I/O PORT MODE)
4.5
PORTE and TRISE Register
This section is not applicable to the PIC16F73 or
PIC16F76.
Data Bus
WR Port
D
Q
PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7, which are individually configureable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
I/O pin(1)
CK
Data Latch
D
Q
I/O PORTE becomes control inputs for the micro-
processor port when bit PSPMODE (TRISE<4>) is set.
In this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs). Ensure ADCON1 is configured for digital I/O. In
this mode, the input buffers are TTL.
WR TRIS
RD TRIS
Schmitt
Trigger
Input
CK
TRIS Latch
Buffer
Register 4-1 shows the TRISE register, which also con-
trols the parallel slave port operation.
Q
D
PORTE pins are multiplexed with analog inputs. When
selected as an analog input, these pins will read as ’0’s.
EN
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
Note: On a Power-on Reset, these pins are con-
figured as analog inputs and read as ‘0’.
2002 Microchip Technology Inc.
DS30325B-page 37
PIC16F7X
REGISTER 4-1:
TRISE REGISTER (ADDRESS 89h)
R-0
IBF
R-0
R/W-0
IBOV
R/W-0
U-0
R/W-1
Bit2
R/W-1
Bit1
R/W-1
Bit0
OBF
PSPMODE
—
bit 7
bit 0
bit 7
Parallel Slave Port Status/Control bits:
IBF: Input Buffer Full Status bit
1= A word has been received and is waiting to be read by the CPU
0= No word has been received
bit 6
bit 5
OBF: Output Buffer Full Status bit
1= The output buffer still holds a previously written word
0= The output buffer has been read
IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1= A write occurred when a previously input word has not been read
(must be cleared in software)
0= No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1= Parallel Slave Port mode
0= General Purpose I/O mode
bit 3
bit 2
Unimplemented: Read as '0'
PORTE Data Direction bits:
Bit2: Direction Control bit for pin RE2/CS/AN7
1= Input
0= Output
bit 1
bit 0
Bit1: Direction Control bit for pin RE1/WR/AN6
1= Input
0= Output
Bit0: Direction Control bit for pin RE0/RD/AN5
1= Input
0= Output
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
DS30325B-page 38
2002 Microchip Technology Inc.
PIC16F7X
TABLE 4-9:
PORTE FUNCTIONS
Name
Bit#
Buffer Type
Function
ST/TTL(1)
Input/output port pin or read control input in Parallel Slave Port mode or
analog input.
RE0/RD/AN5
bit0
For RD (PSP mode):
1= IDLE
0= Read operation. Contents of PORTD register output to PORTD I/O
pins (if chip selected).
Input/output port pin or write control input in Parallel Slave Port mode
or analog input.
For WR (PSP mode):
1= IDLE
RE1/WR/AN6
RE2/CS/AN7
bit1
bit2
ST/TTL(1)
0= Write operation. Value of PORTD I/O pins latched into PORTD
register (if chip selected).
ST/TTL(1)
Input/output port pin or chip select control input in Parallel Slave Port
mode or analog input.
For CS (PSP mode):
1= Device is not selected
0= Device is selected
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 4-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on:
POR,
Value on all
Addr
Name
Bit 7
Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
other
BOR
RESETS
09h
89h
9Fh
PORTE
TRISE
—
IBF
—
—
—
—
—
—
—
RE2
RE1
RE0
---- -xxx
0000 -111
---- -uuu
0000 -111
---- -000
OBF IBOV PSPMODE
PORTE Data Direction bits
ADCON1
—
—
—
PCFG2 PCFG1 PCFG0 ---- -000
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by PORTE.
2002 Microchip Technology Inc.
DS30325B-page 39
PIC16F7X
When either the CS or RD pins are detected high, the
PORTD outputs are disabled, and the interrupt flag bit
PSPIF is set on the Q4 clock cycle following the next
Q2 cycle, indicating that the read is complete. OBF
remains low until firmware writes new data to PORTD.
4.6
Parallel Slave Port
The Parallel Slave Port (PSP) is not implemented on
the PIC16F73 or PIC16F76.
PORTD operates as an 8-bit wide Parallel Slave Port,
or Microprocessor Port, when control bit PSPMODE
(TRISE<4>) is set. In Slave mode, it is asynchronously
readable and writable by an external system using the
read control input pin RE0/RD, the write control input
pin RE1/WR, and the chip select control input pin
RE2/CS.
When not in PSP mode, the IBF and OBF bits are held
clear. Flag bit IBOV remains unchanged. The PSPIF bit
must be cleared by the user in firmware; the interrupt
can be disabled by clearing the interrupt enable bit
PSPIE (PIE1<7>).
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
bit PSPMODE enables port pin RE0/RD to be the RD
input, RE1/WR to be the WR input and RE2/CS to be
the CS (chip select) input. For this functionality, the cor-
responding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (i.e., set).
The A/D port configuration bits PCFG3:PCFG0
(ADCON1<3:0>) must be set to configure pins
RE2:RE0 as digital I/O.
FIGURE 4-8:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
Data Bus
D
Q
WR
Port
RDx
pin
CK
TTL
Q
D
There are actually two 8-bit latches, one for data output
(external reads) and one for data input (external
writes). The firmware writes 8-bit data to the PORTD
output data latch and reads data from the PORTD input
data latch (note that they have the same address). In
this mode, the TRISD register is ignored, since the
external device is controlling the direction of data flow.
RD
Port
EN
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
An external write to the PSP occurs when the CS and
WR lines are both detected low. Firmware can read the
actual data on the PORTD pins during this time. When
either the CS or WR lines become high (level trig-
gered), the data on the PORTD pins is latched, and the
Input Buffer Full (IBF) status flag bit (TRISE<7>) and
interrupt flag bit PSPIF (PIR1<7>) are set on the Q4
clock cycle, following the next Q2 cycle to signal the
write is complete (Figure 4-9). Firmware clears the IBF
flag by reading the latched PORTD data, and clears the
PSPIF bit.
Read
RD
CS
WR
TTL
Chip Select
TTL
Write
TTL
Note: I/O pin has protection diodes to VDD and VSS.
The Input Buffer Overflow (IBOV) status flag bit
(TRISE<5>) is set if an external write to the PSP occurs
while the IBF flag is set from a previous external write.
The previous PORTD data is overwritten with the new
data. IBOV is cleared by reading PORTD and clearing
IBOV.
A read from the PSP occurs when both the CS and RD
lines are detected low. The data in the PORTD output
latch is output to the PORTD pins. The Output Buffer
Full (OBF) status flag bit (TRISE<6>) is cleared imme-
diately (Figure 4-10), indicating that the PORTD latch is
being read, or has been read by the external bus. If
firmware writes new data to the output latch during this
time, it is immediately output to the PORTD pins, but
OBF will remain cleared.
DS30325B-page 40
2002 Microchip Technology Inc.
PIC16F7X
FIGURE 4-9:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 4-10:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 4-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
08h
PORTD
PORTE
TRISE
PIR1
Port data latch when written: Port pins when read
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
0000 -111 0000 -111
09h
89h
0Ch
—
—
—
—
—
—
RE2
RE1
RE0
IBF
OBF IBOV PSPMODE
PORTE Data Direction Bits
(1)
(1)
ADIF RCIF
ADIE RCIE
TXIF
TXIE
—
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PSPIF
8Ch
9Fh
PIE1
PSPIE
ADCON1
—
—
—
—
PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
2002 Microchip Technology Inc.
DS30325B-page 41
PIC16F7X
NOTES:
DS30325B-page 42
2002 Microchip Technology Inc.
PIC16F7X
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment, either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed in detail in Section 5.2.
5.0
TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The pres-
caler is not readable or writable. Section 5.3 details the
operation of the prescaler.
Additional information on the Timer0 module is avail-
able in the PICmicro™ Mid-Range MCU Family Refer-
ence Manual (DS33023).
5.1
Timer0 Interrupt
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
TMR0IF (INTCON<2>). The interrupt can be masked
by clearing bit TMR0IE (INTCON<5>). Bit TMR0IF
must be cleared in software by the Timer0 module
Interrupt Service Routine, before re-enabling this inter-
rupt. The TMR0 interrupt cannot awaken the processor
from SLEEP, since the timer is shut-off during SLEEP.
Timer0 operation is controlled through the
OPTION_REG register (Register 5-1 on the following
page). Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0 mod-
ule will increment every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
FIGURE 5-1:
BLOCK DIAGRAM OF THE TIMER0 MODULE AND PRESCALER
Data Bus
CLKOUT (= FOSC/4)
8
M
U
X
1
0
0
1
M
U
X
RA4/T0CKI
pin
SYNC
2
TMR0 reg
Cycles
T0SE
T0CS
Set Flag bit TMR0IF
PSA
on Overflow
PRESCALER
0
1
8-bit Prescaler
M
U
X
8
Watchdog
Timer
8 - to - 1MUX
PS2:PS0
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
2002 Microchip Technology Inc.
DS30325B-page 43
PIC16F7X
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
5.2
Using Timer0 with an External
Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accom-
plished by sampling the prescaler output on the Q2 and
REGISTER 5-1:
OPTION_REG REGISTER
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
bit 7
bit 0
bit 7
bit 6
bit 5
RBPU: PORTB Pull-up Enable bit (see Section 2.2.2.2)
INTEDG: Interrupt Edge Select bit (see Section 2.2.2.2)
T0CS: TMR0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
Note: To avoid an unintended device RESET, the instruction sequences shown in
Example 5-1 and Example 5-2 (page 45) must be executed when changing the pres-
caler assignment between Timer0 and the WDT. This sequence must be followed
even if the WDT is disabled.
DS30325B-page 44
2002 Microchip Technology Inc.
PIC16F7X
however, these lines must be used to set a temporary
value. The final 1:1 value is then set in lines 10 and 11
(highlighted). (Line numbers are included in the exam-
ple for illustrative purposes only, and are not part of the
actual code.)
5.3
Prescaler
There is only one prescaler available on the microcon-
troller; it is shared exclusively between the Timer0
module and the Watchdog Timer. The usage of the
prescaler is also mutually exclusive: that is, a prescaler
assignment for the Timer0 module means that there is
no prescaler for the Watchdog Timer, and vice versa.
This prescaler is not readable or writable (see
Figure 5-1).
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF1, MOVWF1,
BSF1,x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
Examples of code for assigning the prescaler assign-
ment are shown in Example 5-1 and Example 5-2.
Note that when the prescaler is being assigned to the
WDT with ratios other than 1:1, lines 2 and 3 (high-
lighted) are optional. If a prescale ratio of 1:1 is to used,
Note: Writing to TMR0 when the prescaler is
assigned to Timer0, will clear the prescaler
count but will not change the prescaler
assignment.
EXAMPLE 5-1:
CHANGING THE PRESCALER ASSIGNMENT FROM TIMER0 TO WDT
1) BSF
STATUS, RP0
; Bank1
2) MOVLW
3) MOVWF
4) BCF
5) CLRF
6) BSF
7) MOVLW
8) MOVWF
9) CLRWDT
10) MOVLW
11) MOVWF
12) BCF
b’xx0x0xxx’
; Select clock source and prescale value of
; other than 1:1
; Bank0
; Clear TMR0 and prescaler
; Bank1
; Select WDT, do not change prescale value
OPTION_REG
STATUS, RP0
TMR0
STATUS, RP1
b’xxxx1xxx’
OPTION_REG
; Clears WDT and prescaler
; Select new prescale value and WDT
b’xxxx1xxx’
OPTION_REG
STATUS, RP0
; Bank0
EXAMPLE 5-2:
CHANGING THE PRESCALER ASSIGNMENT FROM WDT TO TIMER0
CLRWDT
BSF
MOVLW
MOVWF
BCF
; Clear WDT and prescaler
; Bank1
; Select TMR0, new prescale
; value and clock source
; Bank0
STATUS, RP0
b’xxxx0xxx’
OPTION_REG
STATUS, RP0
TABLE 5-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h,101h
TMR0
Timer0 Module Register
GIE PEIE TMR0IE INTE
OPTION_REG RBPU INTEDG T0CS T0SE
xxxx xxxx uuuu uuuu
0Bh,8Bh,
10Bh,18Bh
INTCON
RBIE TMR0IF INTF
PSA PS2 PS1
RBIF 0000 000x 0000 000u
PS0 1111 1111 1111 1111
81h,181h
Legend: x= unknown, u= unchanged, -= unimplemented locations read as ’0’. Shaded cells are not used by Timer0.
2002 Microchip Technology Inc.
DS30325B-page 45
PIC16F7X
NOTES:
DS30325B-page 46
2002 Microchip Technology Inc.
PIC16F7X
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
6.0
TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L), which are
readable and writable. The TMR1 Register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 Interrupt, if enabled,
is generated on overflow, which is latched in interrupt
flag bit TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit TMR1IE (PIE1<0>).
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Timer1 also has an internal “RESET input”. This
RESET can be generated by either of the two CCP
modules as the special event trigger (see Sections 8.1
and 8.2). Register 6-1 shows the Timer1 Control
register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC<1:0> value is
ignored and these pins read as ‘0’.
Timer1 can operate in one of two modes:
• As a timer
• As a counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
REGISTER 6-1:
T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 0
bit 7
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable Control bit
1= Oscillator is enabled
0= Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain)
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
2002 Microchip Technology Inc.
DS30325B-page 47
PIC16F7X
6.1
Timer1 Operation in Timer Mode
6.2
Timer1 Counter Operation
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect, since the internal clock is
always in sync.
Timer1 may operate in Asynchronous or Synchronous
mode, depending on the setting of the TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.
FIGURE 6-1:
TIMER1 INCREMENTING EDGE
T1CKI
(Default high)
T1CKI
(Default low)
Note: Arrows indicate counter increments.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The pres-
caler stage is an asynchronous ripple counter.
6.3
Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2, when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when
bit T1OSCEN is cleared.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut-off. The
prescaler, however, will continue to increment.
FIGURE 6-2:
TIMER1 BLOCK DIAGRAM
Set Flag bit
TMR1IF on
Overflow
Synchronized
0
TMR1
Clock Input
TMR1L
TMR1H
1
TMR1ON
On/Off
T1SYNC
T1OSC
(2)
RC0/T1OSO/T1CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
FOSC/4
Internal
Clock
0
(1)
(2)
RC1/T1OSI/CCP2
2
Q Clock
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
2: For the PIC16F73/76, the Schmitt Trigger is not implemented in External Clock mode.
DS30325B-page 48
2002 Microchip Technology Inc.
PIC16F7X
6.4.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
6.4
Timer1 Operation in
Asynchronous Counter Mode
Reading TMR1H or TMR1L, while the timer is running
from an external asynchronous clock, will ensure a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself, poses certain problems, since
the timer may overflow between the reads.
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in soft-
ware are needed to read/write the timer (Section 6.4.1).
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
In Asynchronous Counter mode, Timer1 cannot be
used as a time-base for capture or compare operations.
Reading the 16-bit value requires some care. The
example code provided in Example 6-1 and
Example 6-2 demonstrates how to write to and read
Timer1 while it is running in Asynchronous mode.
EXAMPLE 6-1:
WRITING A 16-BIT FREE-RUNNING TIMER
; All interrupts are disabled
CLRF
TMR1L
; Clear Low byte, Ensures no rollover into TMR1H
MOVLW
MOVWF
MOVLW
MOVWF
HI_BYTE
TMR1H, F
LO_BYTE
TMR1H, F
; Value to load into TMR1H
; Write High byte
; Value to load into TMR1L
; Write Low byte
; Re-enable the Interrupt (if required)
CONTINUE
; Continue with your code
EXAMPLE 6-2:
READING A 16-BIT FREE-RUNNING TIMER
; All interrupts are disabled
MOVF
MOVWF
MOVF
MOVWF
MOVF
TMR1H, W
TMPH
TMR1L, W
TMPL
; Read high byte
; Read low byte
TMR1H, W
; Read high byte
SUBWF
BTFSC
GOTO
TMPH,
STATUS,Z
CONTINUE
W
; Sub 1st read with 2nd read
; Is result = 0
; Good 16-bit read
; TMR1L may have rolled over between the read of the high and low bytes.
; Reading the high and low bytes now will read a good value.
MOVF
MOVWF
MOVF
MOVWF
CONTINUE
TMR1H, W
TMPH
TMR1L, W
TMPL
; Read high byte
; Read low byte
; Re-enable the Interrupt (if required)
; Continue with your code
2002 Microchip Technology Inc.
DS30325B-page 49
PIC16F7X
TABLE 6-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
6.5
Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for use with a 32 kHz crystal. Table 6-1 shows the
capacitor selection for the Timer1 oscillator.
Capacitors Used:
Osc Type Frequency
OSC1
OSC2
LP
32 kHz
100 kHz
200 kHz
47 pF
33 pF
15 pF
47 pF
33 pF
15 pF
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
were not optimized.
6.6
Resetting Timer1 using a CCP
Trigger Output
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
If the CCP1 or CCP2 module is configured in Compare
mode to generate “special event trigger”
(CCP1M3:CCP1M0 = ‘1011’), this signal will reset
a
See the notes (below) table for additional information.
Timer1.
Commonly Used Crystals:
Note: The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
32.768 kHz
100 kHz
Epson C-001R32.768K-A
Epson C-2 100.00 KC-P
STD XTL 200.000 kHz
200 kHz
Timer1 must be configured for either Timer or Synchro-
nized Counter mode, to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external components.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL regis-
ter pair effectively becomes the period register for
Timer1.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other RESETS, the register
is unaffected.
6.7
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
6.8
Timer1 Prescaler
TMR1H and TMR1L registers are not reset to 00h on a
POR, or any other RESET, except by the CCP1 and
CCP2 special event triggers.
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
TABLE 6-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
10Bh,18Bh
GIE
PEIE TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
(1)
0Ch
8Ch
0Eh
0Fh
10h
PIR1
PIE1
PSPIF
PSPIE
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
(1)
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 Register
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
DS30325B-page 50
2002 Microchip Technology Inc.
PIC16F7X
7.1
Timer2 Prescaler and Postscaler
7.0
TIMER2 MODULE
The prescaler and postscaler counters are cleared
when any of the following occurs:
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mode of the CCP module(s). The TMR2 reg-
ister is readable and writable, and is cleared on any
device RESET.
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (POR, MCLR Reset, WDT
Reset or BOR)
The input clock (FOSC/4) has a prescale option of 1:1,
1:4
or
1:16,
selected
by
control
bits
TMR2 is not cleared when T2CON is written.
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
7.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
SSP module, which optionally uses it to generate shift
clock.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
FIGURE 7-1:
TIMER2 BLOCK DIAGRAM
Sets Flag
TMR2
Output(1)
Reset
bit TMR2IF
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Prescaler
TMR2 reg
FOSC/4
1:1, 1:4, 1:16
Register 7-1 shows the Timer2 control register.
Postscaler
2
Comparator
1:1 to 1:16
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
EQ
T2CKPS1:
T2CKPS0
4
PR2 reg
T2OUTPS3:
T2OUTPS0
Note 1: TMR2 register output can be software selected by the
SSP module as a baud clock.
2002 Microchip Technology Inc.
DS30325B-page 51
PIC16F7X
REGISTER 7-1:
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
0010= 1:3 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
TABLE 7-1:
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 000x 0000 000u
0Bh,8Bh,
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
10Bh, 18Bh
(1)
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
-000 0000 -000 0000
1111 1111 1111 1111
0Ch
8Ch
11h
12h
92h
PIR1
PSPIF
PSPIE
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
CCP1IF TMR2IF TMR1IF
(1)
PIE1
SSPIE CCP1IE TMR2IE TMR1IE
TMR2
T2CON
PR2
Timer2 Module Register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
—
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
DS30325B-page 52
2002 Microchip Technology Inc.
PIC16F7X
8.2
CCP2 Module
8.0
CAPTURE/COMPARE/PWM
MODULES
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP2CON register controls
the operation of CCP2. The special event trigger is
generated by a compare match; it will clear both
TMR1H and TMR1L registers, and start an A/D conver-
sion (if the A/D module is enabled).
Each Capture/Compare/PWM (CCP) module contains
a 16-bit register which can operate as a:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
Additional information on CCP modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023) and in Application Note AN594,
“Using the CCP Modules” (DS00594).
Both the CCP1 and CCP2 modules are identical in
operation, with the exception being the operation of the
special event trigger. Table 8-1 and Table 8-2 show the
resources and interactions of the CCP module(s). In
the following sections, the operation of a CCP module
is described with respect to CCP1. CCP2 operates the
same as CCP1, except where noted.
TABLE 8-1:
CCP MODE - TIMER
RESOURCES REQUIRED
8.1
CCP1 Module
CCP Mode
Capture
Compare
PWM
Timer Resource
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is
generated by a compare match and will clear both
TMR1H and TMR1L registers.
Timer1
Timer1
Timer2
TABLE 8-2:
INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
Capture
Same TMR1 time-base.
Same TMR1 time-base.
Same TMR1 time-base.
Compare
Compare
PWM
Compare
PWM
The PWMs will have the same frequency and update rate (TMR2 interrupt).
The rising edges are aligned.
PWM
PWM
Capture
None.
None.
Compare
2002 Microchip Technology Inc.
DS30325B-page 53
PIC16F7X
REGISTER 8-1:
CCP1CON REGISTER/CCP2CON REGISTER (ADDRESS: 17h/1Dh)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CCPxX
CCPxY
CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 0
bit 7
Unimplemented: Read as '0'
bit 7-6
bit 5-4
CCPxX:CCPxY: PWM Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCPx Mode Select bits
0000= Capture/Compare/PWM disabled (resets CCPx module)
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, set output on match (CCPxIF bit is set)
1001= Compare mode, clear output on match (CCPxIF bit is set)
1010= Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is
unaffected)
1011= Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected);
CCP1 clears Timer1; CCP2 clears Timer1 and starts an A/D conversion (if A/D module
is enabled)
11xx= PWM mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
DS30325B-page 54
2002 Microchip Technology Inc.
PIC16F7X
8.3.4
CCP PRESCALER
8.3
Capture Mode
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. Any RESET will clear
the prescaler counter.
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as one of the fol-
lowing and is configured by CCPxCON<3:0>:
• Every falling edge
• Every rising edge
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
• Every 4th rising edge
• Every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. The
interrupt flag must be cleared in software. If another
capture occurs before the value in register CCPR1 is
read, the old captured value is overwritten by the new
captured value.
EXAMPLE 8-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
;Turn CCP module off
CLRF
CCP1CON
MOVLW
NEW_CAPT_PS;Load the W reg with
;the new prescaler
8.3.1
CCP PIN CONFIGURATION
;move value and CCP ON
;Load CCP1CON with this
;value
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
MOVWF
CCP1CON
Note: If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a
capture condition.
8.4
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
FIGURE 8-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
• Driven high
• Driven low
Set Flag bit CCP1IF
(PIR1<2>)
Prescaler
• Remains unchanged
÷ 1, 4, 16
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
RC2/CCP1
pin
CCPR1H
CCPR1L
Capture
Enable
and
Edge Detect
FIGURE 8-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
TMR1H
TMR1L
CCP1CON<3:0>
Q’s
CCP1CON<3:0>
Mode Select
8.3.2
TIMER1 MODE SELECTION
Set Flag bit CCP1IF
Timer1 must be running in Timer mode or Synchro-
nized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
(PIR1<2>)
CCPR1H CCPR1L
Comparator
Q
S
R
Output
Logic
Match
RC2/CCP1
Pin
8.3.3
SOFTWARE INTERRUPT
TMR1H TMR1L
TRISC<2>
Output Enable
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
Special Event Trigger
Special Event Trigger will:
•
•
•
clear TMR1H and TMR1L registers
NOT set interrupt flag bit TMR1F (PIR1<0>)
(for CCP2 only) set the GO/DONE bit (ADCON0<2>)
2002 Microchip Technology Inc.
DS30325B-page 55
PIC16F7X
8.4.1
CCP PIN CONFIGURATION
8.4.4
SPECIAL EVENT TRIGGER
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the PORTC
I/O data latch.
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
8.4.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
Note: The special event trigger from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
8.4.3
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCP1IF or CCP2IF bit is
set, causing a CCP interrupt (if enabled).
TABLE 8-3:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
10Bh,18Bh
GIE
PEIE TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF 0000 000x 0000 000u
(1)
0Ch
0Dh
8Ch
8Dh
87h
0Eh
0Fh
10h
15h
16h
17h
1Bh
1Ch
1Dh
PIR1
PSPIF
ADIF
—
RCIF
—
TXIF
—
SSPIF
—
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR2
—
—
—
(1)
PIE1
PSPIE
—
ADIE
—
RCIE
—
TXIE
—
SSPIE
—
PIE2
—
—
CCP2IE ---- ---0 ---- ---0
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TRISC
TMR1L
TMR1H
T1CON
PORTC Data Direction Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCPR1L Capture/Compare/PWM Register1 (LSB)
CCPR1H Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1CON
—
—
CCP1X
CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCPR2L Capture/Compare/PWM Register2 (LSB)
CCPR2H Capture/Compare/PWM Register2 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2CON
—
—
CCP2X
CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.
Note 1: The PSP is not implemented on the PIC16F73/76; always maintain these bits clear.
DS30325B-page 56
2002 Microchip Technology Inc.
PIC16F7X
8.5.1
PWM PERIOD
8.5
PWM Mode (PWM)
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
In Pulse Width Modulation mode, the CCPx pin pro-
duces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiplexed with the PORTC data latch, the
TRISC<2> bit must be cleared to make the CCP1 pin
an output.
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
Figure 8-3 shows a simplified block diagram of the
CCP module in PWM mode.
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 8.5.3.
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
FIGURE 8-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Note: The Timer2 postscaler (see Section 8.3) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different fre-
quency than the PWM output.
CCP1CON<5:4>
Duty Cycle Registers
CCPR1L
8.5.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
CCPR1H (Slave)
Comparator
R
S
Q
RC2/CCP1
(1)
TMR2
(Note 1)
PWM duty cycle = (CCPR1L:CCP1CON<5:4>)•
TOSC • (TMR2 prescale value)
TRISC<2>
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read only register.
Note 1: The 8-bit timer is concatenated with the 2-bit inter-
nal Q clock or the 2 bits of the prescaler to create the
10-bit time-base.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
A PWM output (Figure 8-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
When the CCPR1H and 2-bit latch match TMR2, con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
FIGURE 8-4:
PWM OUTPUT
The maximum PWM resolution (bits) for a given PWM
frequency is given by the formula:
TMR2
RESET
TMR2
RESET
Period
FOSC
log( )
FPWM
Resolution
bits
=
log(2)
Duty Cycle
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
2002 Microchip Technology Inc.
DS30325B-page 57
PIC16F7X
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
8.5.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
1. Set the PWM period by writing to the PR2 register.
5. Configure the CCP1 module for PWM operation.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
TABLE 8-4:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
Timer Prescale (1, 4, 16)
PR2 Value
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
0xFF
10
0xFF
10
0x17
5.5
Maximum Resolution (bits)
TABLE 8-5:
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
10Bh,18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
(1)
0Ch
0Dh
8Ch
8Dh
87h
11h
92h
12h
15h
16h
17h
1Bh
1Ch
1Dh
PIR1
PSPIF
—
ADIF
—
RCIF
—
TXIF
—
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR2
—
—
—
(1)
PIE1
PSPIE
—
ADIE
—
RCIE
—
TXIE
—
PIE2
—
—
—
CCP2IE ---- ---0 ---- ---0
1111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
TRISC
TMR2
PR2
PORTC Data Direction Register
Timer2 Module Register
Timer2 Module Period Register
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCPR1L Capture/Compare/PWM Register1 (LSB)
CCPR1H Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1CON
—
—
CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCPR2L Capture/Compare/PWM Register2 (LSB)
CCPR2H Capture/Compare/PWM Register2 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2CON
—
—
CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
DS30325B-page 58
2002 Microchip Technology Inc.
PIC16F7X
9.2
SPI Mode
9.0
9.1
SYNCHRONOUS SERIAL PORT
(SSP) MODULE
This section contains register definitions and opera-
tional characteristics of the SPI module. Additional
information on the SPI module can be found in the
PICmicro™ Mid-Range MCU Family Reference Man-
ual (DS33023A).
SSP Module Overview
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The SSP module can
operate in one of two modes:
SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. To accom-
plish communication, typically three pins are used:
• Serial Data Out (SDO) RC5/SDO
• Serial Data In (SDI) RC4/SDI/SDA
• Serial Clock (SCK) RC3/SCK/SCL
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
An overview of I2C operations and additional informa-
tion on the SSP module can be found in the PICmicro™
Additionally, a fourth pin may be used when in a Slave
mode of operation:
Mid-Range
(DS33023).
MCU
Family
Reference Manual
• Slave Select (SS) RA5/SS/AN4
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the fol-
lowing to be specified:
Refer to Application Note AN578, “Use of the SSP
Module in the I 2C Multi-Master Environment”
(DS00578).
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (IDLE state of SCK)
• Clock edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
2002 Microchip Technology Inc.
DS30325B-page 59
PIC16F7X
REGISTER 9-1:
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
SMP: SPI Data Input Sample Phase bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time (Microwire®)
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
I2C mode:
This bit must be maintained clear
bit 6
CKE: SPI Clock Edge Select bit (Figure 9-2, Figure 9-3, and Figure 9-4)
SPI mode, CKP = 0:
1= Data transmitted on rising edge of SCK (Microwire® alternate)
0= Data transmitted on falling edge of SCK
SPI mode, CKP = 1:
1= Data transmitted on falling edge of SCK (Microwire® default)
0= Data transmitted on rising edge of SCK
I2C mode:
This bit must be maintained clear
bit 5
bit 4
D/A: Data/Address bit (I2C mode only)
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
P: STOP bit (I2C mode only)
This bit is cleared when the SSP module is disabled, or when the START bit is detected last.
SSPEN is cleared.
1= Indicates that a STOP bit has been detected last (this bit is ’0’ on RESET)
0= STOP bit was not detected last
bit 3
bit 2
S: START bit (I2C mode only)
This bit is cleared when the SSP module is disabled, or when the STOP bit is detected last.
SSPEN is cleared.
1= Indicates that a START bit has been detected last (this bit is ’0’ on RESET)
0= START bit was not detected last
R/W: Read/Write bit Information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from
the address match to the next START bit, STOP bit, or ACK bit.
1= Read
0 = Write
bit 1
bit 0
UA: Update Address bit (10-bit I2C mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I2C modes):
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
Transmit (I2C mode only):
1= Transmit in progress, SSPBUF is full
0= Transmit complete, SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
DS30325B-page 60
2002 Microchip Technology Inc.
PIC16F7X
REGISTER 9-2:
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 0
bit 7
bit 7
bit 6
WCOL: Write Collision Detect bit
1= The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0= No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1= A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In
Master mode, the overflow bit is not set since each new reception (and transmission) is
initiated by writing to the SSPBUF register.
0= No overflow
In I2C mode:
1= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV
is a “don’t care” in Transmit mode. SSPOV must be cleared in software in either mode.
0= No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
1= Enables serial port and configures SCK, SDO, and SDI as serial port pins
0= Disables serial port and configures these pins as I/O port pins
In I2C mode:
1= Enables the serial port and configures the SDA and SCL pins as serial port pins
0= Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1= IDLE state for clock is a high level (Microwire® default)
0= IDLE state for clock is a low level (Microwire® alternate)
In I2C mode:
SCK release control
1= Enable clock
0= Holds clock low (clock stretch). (Used to ensure data setup time.)
bit 3-0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000= SPI Master mode, clock = FOSC/4
0001= SPI Master mode, clock = FOSC/16
0010= SPI Master mode, clock = FOSC/64
0011= SPI Master mode, clock = TMR2 output/2
0100= SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101= SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110= I2C Slave mode, 7-bit address
0111= I2C Slave mode, 10-bit address
1011= I2C Firmware Controlled Master mode (slave IDLE)
1110= I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled
1111= I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
2002 Microchip Technology Inc.
DS30325B-page 61
PIC16F7X
To enable the serial port, SSP enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
ister, and then set bit SSPEN. This configures the SDI,
SDO, SCK, and SS pins as serial port pins. For the pins
to behave as the serial port function, they must have
their data direction bits (in the TRISC register) appro-
priately programmed. That is:
FIGURE 9-1:
SSP BLOCK DIAGRAM
(SPI MODE)
Internal
Data Bus
Read
Write
SSPBUF reg
SSPSR reg
• SDI must have TRISC<4> set
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
cleared
Shift
Clock
RC4/SDI/SDA
RC5/SDO
bit0
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set and ADCON must
be configured such that RA5 is a digital I/O
Peripheral OE
.
Control
Enable
SS
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON<3:0> = 0100),
the SPI module will reset if the SS pin is set
to VDD.
RA5/SS/AN4
Edge
Select
2: If the SPI is used in Slave mode with
CKE = '1', then the SS pin control must be
enabled.
2
Clock Select
SSPM3:SSPM0
4
3: When the SPI is in Slave mode with SS
pin control enabled (SSPCON<3:0> =
‘0100’), the state of the SS pin can affect
the state read back from the TRISC<5>
bit. The Peripheral OE signal from the
SSP module into PORTC controls the
state that is read back from the
TRISC<5> bit (see Section 4.3 for infor-
mation on PORTC). If Read-Modify-Write
instructions, such as BSF are performed
on the TRISC register while the SS pin is
high, this will cause the TRISC<5> bit to
be set, thus disabling the SDO output.
TMR2 Output
2
Edge
Select
TCY
Prescaler
4, 16, 64
RC3/SCK/
SCL
TRISC<3>
DS30325B-page 62
2002 Microchip Technology Inc.
PIC16F7X
FIGURE 9-2:
SPI MODE TIMING, MASTER MODE
SCK (CKP = 0,
CKE = 0)
SCK (CKP = 0,
CKE = 1)
SCK (CKP = 1,
CKE = 0)
SCK (CKP = 1,
CKE = 1)
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDO
SDI (SMP = 0)
bit7
bit0
SDI (SMP = 1)
SSPIF
bit7
bit0
FIGURE 9-3:
SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
SS (optional)
SCK (CKP = 0)
SCK (CKP = 1)
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDO
SDI (SMP = 0)
bit7
bit0
SSPIF
FIGURE 9-4:
SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SS
SCK (CKP = 0)
SCK (CKP = 1)
SDO
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDI (SMP = 0)
SSPIF
bit7
bit0
2002 Microchip Technology Inc.
DS30325B-page 63
PIC16F7X
TABLE 9-1:
REGISTERS ASSOCIATED WITH SPI OPERATION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh.
10Bh,18Bh
INTCON
PIR1
GIE
PEIE TMR0IE INTE RBIE TMR0IF
INTF
RBIF
0000 000x 0000 000u
(1)
0Ch
PSPIF
PSPIE
ADIF
ADIE
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
(1)
8Ch
87h
PIE1
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
13h
14h
85h
94h
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
SSPCON WCOL
SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
TRISA
—
—
PORTA Data Direction Register
D/A R/W
--11 1111 --11 1111
0000 0000 0000 0000
SSPSTAT
SMP
CKE
P
S
UA
BF
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
DS30325B-page 64
2002 Microchip Technology Inc.
PIC16F7X
The SSPCON register allows control of the I2C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Slave mode (7-bit address), with START and
STOP bit interrupts enabled to support Firmware
Master mode
2
9.3
SSP I C Operation
The SSP module in I2C mode, fully implements all slave
functions, except general call support, and provides
interrupts on START and STOP bits in hardware to facil-
itate firmware implementations of the master functions.
The SSP module implements the standard mode speci-
fications as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the RC3/
SCK/SCL pin, which is the clock (SCL), and the RC4/
SDI/SDA pin, which is the data (SDA). The user must
configure these pins as inputs or outputs through the
TRISC<4:3> bits.
• I2C Slave mode (10-bit address), with START and
STOP bit interrupts enabled to support Firmware
Master mode
• I2C START and STOP bit interrupts enabled to
support Firmware Master mode, Slave is IDLE
The SSP module functions are enabled by setting SSP
enable bit SSPEN (SSPCON<5>).
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits. Pull-up resistors must be
provided externally to the SCL and SDA pins for proper
operation of the I2C module.
Additional information on SSP I2C operation can be
found in the PICmicro™ Mid-Range MCU Family Ref-
erence Manual (DS33023A).
FIGURE 9-5:
SSP BLOCK DIAGRAM
(I2C MODE)
Internal
Data Bus
Read
Write
SSPBUF reg
RC3/SCK/SCL
9.3.1
SLAVE MODE
Shift
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
Clock
SSPSR reg
RC4/
SDI/
SDA
MSb
LSb
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
Addr Match
Match Detect
SSPADD reg
There are certain conditions that will cause the SSP
module not to give this ACK pulse. They include (either
or both):
Set, RESET
S, P bits
(SSPSTAT reg)
START and
STOP bit Detect
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
The SSP module has five registers for I2C operation.
These are the:
b) The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
• SSP Control Register (SSPCON)
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 9-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit BF is cleared by reading the SSPBUF reg-
ister, while bit SSPOV is cleared through software.
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly accessible
• SSP Address Register (SSPADD)
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirements of the
SSP module, are shown in timing parameter #100 and
parameter #101.
2002 Microchip Technology Inc.
DS30325B-page 65
PIC16F7X
The sequence of events for 10-bit address is as fol-
lows, with steps 7 - 9 for slave-transmitter:
9.3.1.1
Addressing
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condi-
tion, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
1. Receive first (high) byte of address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of address (bits
SSPIF, BF, and UA are set).
a) The SSPSR register value is loaded into the
SSPBUF register.
5. Update the SSPADD register with the first (high)
byte of address, if match releases SCL line, this
will clear bit UA.
b) The buffer full bit, BF is set.
c) An ACK pulse is generated.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
7. Receive Repeated START condition.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
In 10-bit Address mode, two address bytes need to be
received by the slave (Figure 9-7). The five Most Sig-
nificant bits (MSbs) of the first address byte specify if
this is a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write so the slave device will receive the sec-
ond address byte. For a 10-bit address, the first byte
would equal ‘1111 0 A9 A8 0’, where A9and A8are
the two MSbs of the address.
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
TABLE 9-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
Set bit SSPIF
Generate ACK
(SSP Interrupt occurs
Pulse
SSPSR → SSPBUF
if enabled)
BF
SSPOV
0
1
1
0
0
0
1
1
Yes
No
No
No
Yes
No
No
No
Yes
Yes
Yes
Yes
Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
9.3.1.2
Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON<6>) is set. This is an error
condition due to the user’s firmware.
DS30325B-page 66
2002 Microchip Technology Inc.
PIC16F7X
FIGURE 9-6:
I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
R/W=0
Receiving Address
A7 A6 A5 A4
Receiving Data
Receiving Data
ACK
9
ACK
9
ACK
9
SDA
SCL
A3 A2 A1
D7 D6 D5 D4 D3 D2
D0
8
D7 D6
D5
D4 D3
D2
D0
8
D1
7
D1
7
3
7
1
2
4
5
4
3
6
5
6
1
2
3
6
1
2
4
8
5
P
S
SSPIF (PIR1<3>)
Cleared in software
Bus Master
terminates
transfer
BF (SSPSTAT<0>)
SSPBUF register is read
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
9.3.1.3
Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR regis-
ter. Then, pin RC3/SCK/SCL should be enabled by set-
ting bit CKP (SSPCON<4>). The master must monitor
the SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretch-
ing the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time (Figure 9-7).
As a slave-transmitter, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
the data transfer is complete. When the ACK is latched
by the slave, the slave logic is reset (resets SSPSTAT
register) and the slave then monitors for another occur-
rence of the START bit. If the SDA line was low (ACK),
the transmit data must be loaded into the SSPBUF reg-
ister, which also loads the SSPSR register. Then pin
RC3/SCK/SCL should be enabled by setting bit CKP.
FIGURE 9-7:
I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Receiving Address
R/W = 1
ACK
Transmitting Data
ACK
9
SDA
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
SCL
S
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
P
SCL held low
while CPU
responds to SSPIF
Data in
sampled
Cleared in software
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
From SSP Interrupt
Service Routine
SSPBUF is written in software
CKP (SSPCON<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
2002 Microchip Technology Inc.
DS30325B-page 67
PIC16F7X
9.3.2
MASTER MODE
9.3.3
MULTI-MASTER MODE
Master mode of operation is supported in firmware
using interrupt generation on the detection of the
START and STOP conditions. The STOP (P) and
START (S) bits are cleared from a RESET or when the
SSP module is disabled. The STOP (P) and START (S)
bits will toggle based on the START and STOP condi-
tions. Control of the I2C bus may be taken when the P
bit is set, or the bus is IDLE and both the S and P bits
are clear.
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions, allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the SSP module is disabled. The STOP (P) and
START (S) bits will toggle based on the START and
STOP conditions. Control of the I2C bus may be taken
when bit P (SSPSTAT<4>) is set, or the bus is IDLE
and both the S and P bits clear. When the bus is busy,
enabling the SSP Interrupt will generate the interrupt
when the STOP condition occurs.
In Master mode, the SCL and SDA lines are manipu-
lated by clearing the corresponding TRISC<4:3> bit(s).
The output level is always low, irrespective of the
value(s) in PORTC<4:3>. So when transmitting data, a
’1’ data bit must have the TRISC<4> bit set (input) and
a ’0’ data bit must have the TRISC<4> bit cleared (out-
put). The same scenario is true for the SCL line with the
TRISC<3> bit. Pull-up resistors must be provided
externally to the SCL and SDA pins for proper opera-
tion of the I2C module.
In Multi-Master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, these are:
• Address Transfer
• Data Transfer
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt will occur if enabled):
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address trans-
fer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be gener-
ated. If arbitration was lost during the data transfer
stage, the device will need to retransfer the data at a
later time.
• START condition
• STOP condition
• Data transfer byte transmitted/received
Master mode of operation can be done with either the
Slave mode IDLE (SSPM3:SSPM0 = 1011), or with the
Slave active. When both Master and Slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
TABLE 9-3:
REGISTERS ASSOCIATED WITH I2C OPERATION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
INTCON
GIE
PEIE TMR0IE INTE
RBIE TMR0IF INTF
RBIF
0000 000x
0000 000u
10Bh,18Bh
(1)
0Ch
8Ch
13h
93h
14h
94h
87h
PIR1
PIE1
PSPIF
PSPIE
ADIF
ADIE
RCIF
RCIE
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
(1)
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
0000 0000
0000 0000
0000 0000
1111 1111
uuuu uuuu
0000 0000
0000 0000
0000 0000
2
SSPADD Synchronous Serial Port (I C mode) Address Register
SSPCON
SSPSTAT
TRISC
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
(2)
(2)
SMP
CKE
D/A
P
S
R/W
UA
BF
PORTC Data Direction Register
1111 1111
2
Legend: x= unknown, u= unchanged, -= unimplemented locations read as ’0’. Shaded cells are not used by SSP module in I C mode.
Note 1: PSPIF and PSPIE are reserved on the PIC16F73/76; always maintain these bits clear.
2
2: Maintain these bits clear in I C mode.
DS30325B-page 68
2002 Microchip Technology Inc.
PIC16F7X
The USART can be configured in the following modes:
10.0 UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Com-
munications Interface or SCI.) The USART can be con-
figured as a full duplex asynchronous system that can
communicate with peripheral devices, such as CRT ter-
minals and personal computers, or it can be configured
as a half duplex synchronous system that can commu-
nicate with peripheral devices, such as A/D or D/A inte-
grated circuits, serial EEPROMs, etc.
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to
be set in order to configure pins RC6/TX/CK and
RC7/RX/DT as the Universal Synchronous Asynchro-
nous Receiver Transmitter.
REGISTER 10-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
R/W-0
BRGH
R-1
R/W-0
TX9D
—
TRMT
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
Note: SREN/CREN overrides TXEN in Sync mode.
bit 4
SYNC: USART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
bit 3
bit 2
Unimplemented: Read as '0'
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of Transmit Data
Can be parity bit
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
2002 Microchip Technology Inc.
DS30325B-page 69
PIC16F7X
REGISTER 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
U-0
R-0
R-0
R-x
—
FERR
OERR
RX9D
bit 7
bit 0
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0= Serial port disabled
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - Slave:
Don’t care
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables continuous receive
0= Disables continuous receive
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
bit 2
Unimplemented: Read as '0'
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREG register and receive next valid byte)
0= No framing error
bit 1
bit 0
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of Received Data
Can be parity bit (parity to be calculated by firmware)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
DS30325B-page 70
2002 Microchip Technology Inc.
PIC16F7X
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
10.1 USART Baud Rate Generator
(BRG)
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 10-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in Master mode (internal clock).
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
10.1.1
SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 10-1. From this, the error in
baud rate can be determined.
TABLE 10-1: BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
Baud Rate = FOSC/(16(X+1))
N/A
X = value in SPBRG (0 to 255)
TABLE 10-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on:
POR,
BOR
Value on
all other
RESETS
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
0000 -010 0000 -010
0000 -00x 0000 -00x
0000 0000 0000 0000
98h
18h
99h
TXSTA
CSRC TX9 TXEN SYNC
—
—
BRGH TRMT TX9D
FERR OERR RX9D
RCSTA SPEN RX9 SREN CREN
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented, read as '0'. Shaded cells are not used by the BRG.
2002 Microchip Technology Inc.
DS30325B-page 71
PIC16F7X
TABLE 10-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz
FOSC = 16 MHz
FOSC = 10 MHz
BAUD
RATE
SPBRG
VALUE
(DECIMAL)
SPBRG
VALUE
(DECIMAL)
SPBRG
VALUE
(DECIMAL)
%
%
%
BAUD
ERROR
BAUD
ERROR
BAUD
ERROR
1200
2400
1,221
2,404
1.73%
0.16%
-1.36%
1.73%
1.73%
8.51%
1.73%
8.51%
-9.58%
25.00%
255
129
32
15
7
1,202
2,404
0.16%
0.16%
0.16%
0.16%
-6.99%
8.51%
8.51%
-13.19%
8.51%
0.00%
207
103
25
12
6
1,202
2,404
0.16%
0.16%
129
64
15
7
9600
9,470
9,615
9,766
1.73%
19,200
38,400
57,600
76,800
96,000
115,200
250,000
19,531
39,063
62,500
78,125
104,167
104,167
312,500
19,231
35,714
62,500
83,333
83,333
125,000
250,000
19,531
39,063
52,083
78,125
78,125
78,125
156,250
1.73%
1.73%
3
4
3
-9.58%
1.73%
2
3
2
1
2
2
-18.62%
-32.18%
-37.50%
1
2
1
1
0
0
0
FOSC = 4 MHz
FOSC = 3.6864 MHz
FOSC = 3.579545 MHz
BAUD
RATE
SPBRG
VALUE
(DECIMAL)
SPBRG
VALUE
(DECIMAL)
SPBRG
VALUE
(DECIMAL)
%
%
%
BAUD
ERROR
BAUD
ERROR
BAUD
ERROR
300
300
0.16%
0.16%
207
51
25
6
300
0.00%
0.00%
0.00%
0.00%
0.00%
-25.00%
191
47
23
5
301
1,190
2,432
9,322
18,643
27,965
0.23%
-0.83%
1.32%
185
46
22
5
1200
1,202
1,200
2,400
9,600
19,200
28,800
2400
2,404
0.16%
9600
8,929
-6.99%
8.51%
-2.90%
-2.90%
-27.17%
19,200
38,400
57,600
76,800
20,833
31,250
62,500
62,500
2
2
2
-18.62%
8.51%
1
1
1
0
57,600
—
0.00%
—
0
—
55,930
—
-2.90%
—
0
—
-18.62%
0
TABLE 10-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 20 MHz
FOSC = 16 MHz
FOSC = 10 MHz
BAUD
RATE
SPBRG
VALUE
(DECIMAL)
SPBRG
VALUE
(DECIMAL)
SPBRG
VALUE
(DECIMAL)
%
%
%
BAUD
ERROR
BAUD
ERROR
BAUD
ERROR
2400
9600
—
—
—
—
—
—
2,441
9,615
1.73%
0.16%
-1.36%
1.73%
-1.36%
1.73%
-6.99%
8.51%
-16.67%
4.17%
255
64
32
15
10
7
9,615
19,231
37,879
56,818
78,125
96,154
113,636
250,000
312,500
0.16%
0.16%
-1.36%
-1.36%
1.73%
0.16%
-1.36%
0.00%
4.17%
129
64
32
21
15
12
10
4
9,615
19,231
38,462
58,824
76,923
100,000
111,111
250,000
333,333
0.16%
0.16%
0.16%
2.12%
0.16%
4.17%
-3.55%
0.00%
11.11%
103
51
25
16
12
9
19,200
38,400
57,600
76,800
96,000
115,200
250,000
300,000
18,939
39,063
56,818
78,125
89,286
125,000
208,333
312,500
6
8
4
3
2
3
2
1
FOSC = 4 MHz
FOSC = 3.6864 MHz
FOSC = 3.579545 MHz
BAUD
RATE
(K)
SPBRG
VALUE
(DECIMAL)
SPBRG
VALUE
SPBRG
VALUE
%
%
%
BAUD
ERROR
BAUD
ERROR
BAUD
ERROR
(DECIMAL)
(DECIMAL)
1200
2400
1,202
2,404
0.16%
0.16%
0.16%
0.16%
-6.99%
8.51%
8.51%
-13.19%
8.51%
0.00%
207
103
25
12
6
1,200
2,400
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
20.00%
0.00%
-7.84%
191
95
23
11
5
1,203
2,406
0.23%
0.23%
185
92
22
11
5
9600
9,615
9,600
9,727
1.32%
19,200
38,400
57,600
76,800
96,000
115,200
250,000
19,231
35,714
62,500
83,333
83,333
125,000
250,000
19,200
38,400
57,600
76,800
115,200
115,200
230,400
18,643
37,287
55,930
74,574
111,861
111,861
223,722
-2.90%
-2.90%
-2.90%
-2.90%
16.52%
-2.90%
-10.51%
3
3
3
2
2
2
2
1
1
1
1
1
0
0
0
DS30325B-page 72
2002 Microchip Technology Inc.
PIC16F7X
are set. The TXIF interrupt can be enabled/disabled by
setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF
will be set, regardless of the state of enable bit TXIE and
cannot be cleared in software. It will reset only when new
data is loaded into the TXREG register. While flag bit
TXIF indicates the status of the TXREG register, another
bit TRMT (TXSTA<1>) shows the status of the TSR reg-
ister. Status bit TRMT is a read only bit, which is set one
instruction cycle after the TSR register becomes empty,
and is cleared one instruction cycle after the TSR regis-
ter is loaded. No interrupt logic is tied to this bit, so the
user has to poll this bit in order to determine if the TSR
register is empty.
10.2 USART Asynchronous Mode
In this mode, the USART uses standard non-return-to-
zero (NRZ) format (one START bit, eight or nine data
bits, and one STOP bit). The most common data format
is 8-bits. An on-chip, dedicated, 8-bit baud rate gener-
ator can be used to derive standard baud rate frequen-
cies from the oscillator. The USART transmits and
receives the LSb first. The USART’s transmitter and
receiver are functionally independent, but use the
same data format and baud rate. The baud rate gener-
ator produces a clock, either x16 or x64 of the bit shift
rate, depending on bit BRGH (TXSTA<2>). Parity is not
supported by the hardware, but can be implemented in
software (and stored as the ninth data bit). Asynchro-
nous mode is stopped during SLEEP.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
is set. TXIF is cleared by loading TXREG.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur until
the TXREG register has been loaded with data and the
baud rate generator (BRG) has produced a shift clock
(Figure 10-2). The transmission can also be started by
first loading the TXREG register and then setting enable
bit TXEN. Normally, when transmission is first started,
the TSR register is empty. At that point, transfer to the
TXREG register will result in an immediate transfer to
TSR, resulting in an empty TXREG. A back-to-back
transfer is thus possible (Figure 10-3). Clearing enable
bit TXEN during a transmission will cause the transmis-
sion to be aborted and will reset the transmitter. As a
result, the RC6/TX/CK pin will revert to hi-impedance.
The USART Asynchronous module consists of the fol-
lowing important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
10.2.1
USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 10-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data by firmware. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new data
from the TXREG register (if available). Once the TXREG
register transfers the data to the TSR register, the
TXREG register is empty. One instruction cycle later,
flag bit TXIF (PIR1<4>) and flag bit TRMT (TXSTA<1>)
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be writ-
ten before writing the 8-bit data to the TXREG register.
This is because a data write to the TXREG register can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). In such a case, an incor-
rect ninth data bit may be loaded in the TSR register.
FIGURE 10-1:
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXREG Register
TXIF
TXIE
8
MSb
(8)
LSb
Pin Buffer
and Control
0
•
• •
TSR Register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
SPBRG
TRMT
SPEN
TX9
TX9D
Baud Rate Generator
2002 Microchip Technology Inc.
DS30325B-page 73
PIC16F7X
Steps to follow when setting up an Asynchronous
Transmission:
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 10.1).
7. Load data to the TXREG register (starts
transmission).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
8. If using interrupts, ensure that GIE and PEIE in
the INTCON register are set.
3. If interrupts are desired, then set enable bit TXIE.
4. If 9-bit transmission is desired, then set transmit
bit TX9.
FIGURE 10-2:
ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
START Bit
Bit 0
Bit 1
Word 1
Bit 7/8
STOP Bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Word 1
Transmit Shift Reg
Reg. Empty Flag)
FIGURE 10-3:
ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
TXIF bit
(Interrupt Reg. Flag)
START Bit
START Bit
Word 2
Bit 0
Bit 1
Word 1
Bit 7/8
Bit 0
STOP Bit
TRMT bit
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
(Transmit Shift
Reg. Empty Flag)
Note: This timing diagram shows two consecutive transmissions.
TABLE 10-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE TMR0IE INTE
RBIE TMR0IF
INTF
RBIF
0000 000x 0000 000u
(1)
0Ch
18h
19h
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
TXREG USART Transmit Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
DS30325B-page 74
2002 Microchip Technology Inc.
PIC16F7X
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
the STOP bit of the third byte, if the RCREG register is
still full, the overrun error bit OERR (RCSTA<1>) will be
set. The word in the RSR will be lost. The RCREG reg-
ister can be read twice to retrieve the two bytes in the
FIFO. Overrun bit OERR has to be cleared in software.
This is done by resetting the receive logic (CREN is
cleared and then set). If bit OERR is set, transfers from
the RSR register to the RCREG register are inhibited
and no further data will be received, therefore, it is
essential to clear error bit OERR if it is set. Framing
error bit FERR (RCSTA<2>) is set if a STOP bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values, therefore, it is essential for the user to read the
RCSTA register before reading RCREG register, in
order not to lose the old FERR and RX9D information.
10.2.2
USART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 10-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter oper-
ates at the bit rate, or at FOSC.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG register (if
it is empty). If the transfer is complete, flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double buffered register (i.e., it is a two deep FIFO). It
FIGURE 10-4:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
FOSC
SPBRG
RSR Register
LSb
MSb
÷64
or
÷16
0
Baud Rate Generator
1
7
STOP (8)
START
• • •
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG Register
FIFO
8
RCIF
RCIE
Interrupt
Data Bus
2002 Microchip Technology Inc.
DS30325B-page 75
PIC16F7X
FIGURE 10-5:
ASYNCHRONOUS RECEPTION
START
bit
START
bit
START
bit7/8 STOP bit
bit
RX (pin)
bit0
bit1
STOP
bit
STOP
bit
bit0
bit7/8
bit7/8
Rcv Shift
Reg
Rcv Buffer Reg
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set. An overrun error indicates an error in user firmware.
Steps to follow when setting up an Asynchronous
Reception:
6. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE is set.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 10.1).
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
8. Read the 8-bit received data by reading the
RCREG register.
3. If interrupts are desired, then set enable bit
RCIE.
9. If any error occurred, clear the error by clearing
enable bit CREN.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
10. If using interrupts, ensure that GIE and PEIE in
the INTCON register are set.
TABLE 10-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE TMR0IE INTE
RBIE TMR0IF
INTF
RBIF
0000 000x 0000 000u
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
RCREG USART Receive Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
DS30325B-page 76
2002 Microchip Technology Inc.
PIC16F7X
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to hi-
impedance. If either bit CREN or bit SREN is set during
a transmission, the transmission is aborted and the DT
pin reverts to a hi-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic, however, is not
reset, although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SREN is set (to interrupt an on-going transmission
and receive a single word), then after the single word is
received, bit SREN will be cleared and the serial port
will revert back to transmitting, since bit TXEN is still
set. The DT line will immediately switch from Hi-
impedance Receive mode to transmit and start driving.
To avoid this, bit TXEN should be cleared.
10.3 USART Synchronous Master
Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
10.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
The USART transmitter block diagram is shown in
Figure 10-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCYCLE), the TXREG is empty and inter-
rupt bit TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit, which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not
available to the user.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 10.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that GIE and PEIE in
the INTCON register are set.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is
stable around the falling edge of the synchronous clock
(Figure 10-6). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 10-7). This is advantageous when slow
baud rates are selected, since the BRG is kept in
RESET when bits TXEN, CREN and SREN are clear.
Setting enable bit TXEN will start the BRG, creating a
shift clock immediately. Normally, when transmission is
first started, the TSR register is empty, so a transfer to
the TXREG register will result in an immediate transfer
to TSR, resulting in an empty TXREG. Back-to-back
transfers are possible.
2002 Microchip Technology Inc.
DS30325B-page 77
PIC16F7X
FIGURE 10-6:
SYNCHRONOUS TRANSMISSION
Q1Q2 Q3Q4 Q1Q2Q3Q4Q1 Q2Q3 Q4Q1Q2Q3 Q4Q1Q2Q3Q4
Q3Q4 Q1Q2 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
RC7/RX/DT
pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
Word 1
RC6/TX/CK
pin
Write to
TXREG reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT
TRMT bit
’1’
’1’
TXEN bit
Note: Sync Master mode; SPBRG = ’0’. Continuous transmission of two 8-bit words.
FIGURE 10-7:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit0
bit2
bit1
bit6
bit7
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 10-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE TMR0IE INTE RBIE TMR0IF
INTF
RBIF
0000 000x 0000 000u
(1)
0Ch
18h
19h
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
TXREG USART Transmit Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
DS30325B-page 78
2002 Microchip Technology Inc.
PIC16F7X
receive data. Reading the RCREG register will load bit
RX9D with a new value, therefore, it is essential for the
user to read the RCSTA register before reading RCREG,
in order not to lose the old RX9D information.
10.3.2
USART SYNCHRONOUS MASTER
RECEPTION
Once synchronous mode is selected, reception is
enabled by setting either enable bit SREN (RCSTA<5>),
or enable bit CREN (RCSTA<4>). Data is sampled on
the RC7/RX/DT pin on the falling edge of the clock. If
enable bit SREN is set, then only a single word is
received. If enable bit CREN is set, the reception is con-
tinuous until CREN is cleared. If both bits are set, CREN
takes precedence. After clocking the last bit, the
received data in the Receive Shift Register (RSR) is
transferred to the RCREG register (if it is empty). When
the transfer is complete, interrupt flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE (PIE1<5>).
Flag bit RCIF is a read only bit, which is reset by the
hardware. In this case, it is reset when the RCREG reg-
ister has been read and is empty. The RCREG is a dou-
ble buffered register (i.e., it is a two deep FIFO). It is
possible for two bytes of data to be received and trans-
ferred to the RCREG FIFO and a third byte to begin shift-
ing into the RSR register. On the clocking of the last bit
of the third byte, if the RCREG register is still full, then
overrun error bit OERR (RCSTA<1>) is set. The word in
the RSR will be lost. The RCREG register can be read
twice to retrieve the two bytes in the FIFO. Bit OERR has
to be cleared in software (by clearing bit CREN). If bit
OERR is set, transfers from the RSR to the RCREG are
inhibited, so it is essential to clear bit OERR if it is set.
The ninth receive bit is buffered the same way as the
Steps to follow when setting up a Synchronous Master
Reception:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 10.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that GIE and PEIE in
the INTCON register are set.
FIGURE 10-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2Q3Q4 Q1Q2Q3Q4 Q1 Q2Q3Q4 Q1Q2Q3 Q4Q1 Q2Q3 Q4 Q1Q2 Q3Q4Q1Q2Q3 Q4 Q1Q2 Q3Q4Q1 Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4
RC7/RX/DT pin
RC6/TX/CK pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Write to
bit SREN
SREN bit
CREN bit
’0’
’0’
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = ’1’ and bit BRG = ’0’.
2002 Microchip Technology Inc.
DS30325B-page 79
PIC16F7X
TABLE 10-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on
all other
RESETS
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE TMR0IE INTE
RBIE TMR0IF
INTF
RBIF
0000 000x 0000 000u
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN
—
FERR
OERR
RX9D 0000 -00x 0000 -00x
RCREG USART Receive Register
0000 0000 0000 0000
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented, read as '0'. Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
Follow these steps when setting up a Synchronous
Slave Transmission:
10.4 USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master
1. Enable the synchronous slave serial port by set-
mode, in that the shift clock is supplied externally at the
ting bits SYNC and SPEN and clearing bit
RC6/TX/CK pin (instead of being supplied internally in
Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, then set enable bit
TXIE.
10.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
4. If 9-bit transmission is desired, then set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
The operation of the Synchronous Master and Slave
modes are identical except in the case of the SLEEP
mode.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
8. If using interrupts, ensure that GIE and PEIE in
the INTCON register are set.
a) The first word will immediately transfer to the
TSR register and transmit when the master
device drives the CK line.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the inter-
rupt vector (0004h).
DS30325B-page 80
2002 Microchip Technology Inc.
PIC16F7X
TABLE 10-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE TMR0IE INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
(1)
0Ch
18h
19h
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN ADDEN FERR
OERR
RX9D 0000 000x 0000 000x
TXREG USART Transmit Register
0000 0000 0000 0000
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented, read as '0'. Shaded cells are not used for synchronous slave transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
Follow these steps when setting up a Synchronous
Slave Reception:
10.4.2
USART SYNCHRONOUS SLAVE
RECEPTION
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode. Bit SREN is a “don't care” in Slave mode.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
If receive is enabled by setting bit CREN prior to the
SLEEPinstruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
5. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrupts, ensure that GIE and PEIE in
the INTCON register are set.
TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE TMR0IE INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN ADDEN FERR
OERR
RX9D 0000 000x 0000 000x
RCREG USART Receive Register
0000 0000 0000 0000
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices, always maintain these bits clear.
2002 Microchip Technology Inc.
DS30325B-page 81
PIC16F7X
NOTES:
DS30325B-page 82
2002 Microchip Technology Inc.
PIC16F7X
The A/D module has three registers. These registers
are:
11.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
• A/D Result Register ((ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 ((ADCON1)
The 8-bit analog-to-digital (A/D) converter module has
five inputs for the PIC16F73/76 and eight for the
PIC16F74/77.
The ADCON0 register, shown in Register 11-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 11-2, configures the func-
tions of the port pins. The port pins can be configured
as analog inputs (RA3 can also be a voltage reference),
or as digital I/O.
The A/D allows conversion of an analog input signal to
a corresponding 8-bit digital number. The output of the
sample and hold is the input into the converter, which
generates the result via successive approximation. The
analog reference voltage is software selectable to
either the device’s positive supply voltage (VDD), or the
voltage level on the RA3/AN3/VREF pin.
Additional information on using the A/D module can be
found in the PICmicro™ Mid-Range MCU Family Ref-
erence Manual (DS33023) and in Application Note,
AN546 (DS00546).
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To oper-
ate in SLEEP, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
REGISTER 11-1: ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0
ADCS1
bit 7
R/W-0
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
U-0
R/W-0
ADON
bit 0
ADCS0
GO/DONE
—
bit 7-6
bit 5-3
ADCS1:ADCS0: A/D Conversion Clock Select bits
00= FOSC/2
01= FOSC/8
10= FOSC/32
11= FRC (clock derived from the internal A/D module RC oscillator)
CHS2:CHS0: Analog Channel Select bits
000= Channel 0 (RA0/AN0)
001= Channel 1 (RA1/AN1)
010= Channel 2 (RA2/AN2)
011= Channel 3 (RA3/AN3)
100= Channel 4 (RA5/AN4)
101= Channel 5 (RE0/AN5)(1)
110= Channel 6 (RE1/AN6)(1)
111= Channel 7 (RE2/AN7)(1)
bit 2
GO/DONE: A/D Conversion Status bit
If ADON = 1:
1= A/D conversion in progress (setting this bit starts the A/D conversion)
0= A/D conversion not in progress (this bit is automatically cleared by hardware when the
A/D conversion is complete)
bit 1
bit 0
Unimplemented: Read as '0'
ADON: A/D On bit
1= A/D converter module is operating
0= A/D converter module is shut-off and consumes no operating current
Note 1: A/D channels 5, 6 and 7 are implemented on the PIC16F74/77 only.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
2002 Microchip Technology Inc.
DS30325B-page 83
PIC16F7X
REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
PCFG2
PCFG1 PCFG0
bit 0
bit 7
bit 7-3
bit 2-0
Unimplemented: Read as '0'
PCFG2:PCFG0: A/D Port Configuration Control bits
PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 RE0(1) RE1(1) RE2(1) VREF
000
001
010
011
100
101
11x
A
A
A
A
A
A
D
A
A
A
A
A
A
D
A
A
A
A
D
D
D
A
A
A
A
D
D
D
A
VREF
A
A
A
D
D
D
D
D
A
A
D
D
D
D
D
A
A
D
D
D
D
D
VDD
RA3
VDD
RA3
VDD
RA3
VDD
VREF
A
VREF
D
A = Analog input
D = Digital I/O
Note 1: RE0, RE1 and RE2 are implemented on the PIC16F74/77 only.
Legend:
R = Readable bit
- n = Value at POR reset
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
DS30325B-page 84
2002 Microchip Technology Inc.
PIC16F7X
The following steps should be followed for doing an
A/D conversion:
4. Wait for at least an appropriate acquisition
period.
5. Start conversion:
1. Configure the A/D module:
• Set GO/DONE bit (ADCON0)
• Configure analog pins, voltage reference,
and digital I/O (ADCON1)
6. Wait for the A/D conversion to complete, by
either:
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure the A/D interrupt (if desired):
• Clear ADIF bit
• Polling for the GO/DONE bit to be cleared
(interrupts disabled)
OR
• Set ADIE bit
• Waiting for the A/D interrupt
• Set PEIE bit
7. Read A/D result register (ADRES), and clear bit
ADIF if required.
• Set GIE bit
8. For next conversion, go to step 3 or step 4, as
required.
3. Select an A/D input channel (ADCON0).
FIGURE 11-1:
A/D BLOCK DIAGRAM
CHS2:CHS0
111
(1)
RE2/AN7
110
(1)
RE1/AN6
101
(1)
RE0/AN5
100
RA5/AN4
VIN
011
(Input Voltage)
RA3/AN3/VREF
010
RA2/AN2
A/D
Converter
001
RA1/AN1
000
VDD
RA0/AN0
000or
010or
100or
11x
VREF
(Reference
Voltage)
001or
011or
101
PCFG2:PCFG0
Note 1: Not available on PIC16F73/76.
2002 Microchip Technology Inc.
DS30325B-page 85
PIC16F7X
The maximum recommended impedance for ana-
log sources is 10 kΩ. After the analog input channel is
selected (changed), the acquisition period must pass
before the conversion can be started.
11.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 11-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
Figure 11-2. The source impedance affects the offset
voltage at the analog input (due to pin leakage current).
To calculate the minimum acquisition time, TACQ, see
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023). In general, however, given a max-
imum source impedance of 10 kΩ and at a temperature
of 100°C, TACQ will be no more than 16 µsec.
FIGURE 11-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
RS
CHOLD
= DAC Capacitance
= 51.2 pF
CPIN
5 pF
VA
I leakage
± 500 nA
VT = 0.6V
VSS
Legend CPIN
VT
= input capacitance
= threshold voltage
6V
5V
VDD 4V
3V
= leakage current at the pin due to
various junctions
I leakage
2V
= interconnect resistance
= sampling switch
RIC
SS
5 6 7 8 9 10 11
Sampling Switch
= sample/hold capacitance (from DAC)
CHOLD
(kΩ)
TABLE 11-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD)
ADCS1:ADCS0
Maximum Device Frequency
Max.
Operation
2TOSC
8TOSC
00
01
10
11
1.25 MHz
5 MHz
32TOSC
RC(1, 2, 3)
20 MHz
(Note 1)
Note 1: The RC source has a typical TAD time of 4 µs but can vary between 2-6 µs.
2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only
recommended for SLEEP operation.
3: For extended voltage devices (LC), please refer to the Electrical Specifications section.
DS30325B-page 86
2002 Microchip Technology Inc.
PIC16F7X
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRES register will
NOT be changed, and the ADIF flag will not be set.
11.2 Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.0 TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selectable. The four possible options for TAD are:
After the GO/DONE bit is cleared at either the end of a
conversion, or by firmware, another conversion can be
initiated by setting the GO/DONE bit. Users must still
take into account the appropriate acquisition time for
the application.
• 2 TOSC (FOSC/2)
• 8 TOSC (FOSC/8)
11.5 A/D Operation During SLEEP
• 32 TOSC (FOSC/32)
• Internal RC oscillator (2-6 µs)
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = ‘11’). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared,
and the result loaded into the ADRES register. If the
A/D interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
as small as possible, but no less than 1.6 µs.
11.3 Configuring Analog Port Pins
The ADCON1, TRISA and TRISE registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bits set (input). If the TRIS bit is cleared (out-
put), the digital output level (VOH or VOL) will be
converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
When the A/D clock source is another clock option (not
RC), a SLEEPinstruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in SLEEP, ensure the SLEEP
instruction immediately follows the instruc-
tion that sets the GO/DONE bit.
2: Analog levels on any pin that is defined as
a digital input, but not as an analog input,
may cause the digital input buffer to con-
sume current that is out of the device’s
specification.
11.6 Effects of a RESET
A device RESET forces all registers to their RESET
state. The A/D module is disabled and any conversion
in progress is aborted. All A/D input pins are configured
as analog inputs.
11.4 A/D Conversions
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
The ADRES register will contain unknown data after a
Power-on Reset.
Setting the GO/DONE bit begins an A/D conversion.
When the conversion completes, the 8-bit result is
placed in the ADRES register, the GO/DONE bit is
cleared, and the ADIF flag (PIR<6>) is set.
If both the A/D interrupt bit ADIE (PIE1<6>) and the
peripheral interrupt enable bit PEIE (INTCON<6>) are
set, the device will wake from SLEEP whenever ADIF
is set by hardware. In addition, an interrupt will also
occur if the global interrupt bit GIE (INTCON<7>) is set.
2002 Microchip Technology Inc.
DS30325B-page 87
PIC16F7X
with minimal software overhead (moving the ADRES to
the desired location). The appropriate analog input
channel must be selected and an appropriate acquisi-
tion time should pass before the “special event trigger”
sets the GO/DONE bit (starts a conversion).
11.7 Use of the CCP Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as 1011and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion,
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
TABLE 11-2: SUMMARY OF A/D REGISTERS
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh,
INTCON
GIE
PEIE TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF 0000 000x 0000 000u
10Bh, 18Bh
(1)
0Ch
0Dh
PIR1
PIR2
PSPIF
ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
—
—
—
—
—
—
—
(1)
8Ch
8Dh
1Eh
PIE1
PSPIE
ADIE
RCIE
TXIE
PIE2
—
—
—
—
—
—
—
CCP2IE ---- ---0 ---- ---0
ADRES
A/D Result Register
xxxx xxxx uuuu uuuu
1Fh
9Fh
05h
85h
ADCON0 ADCS1 ADCS0 CHS2
CHS1
—
CHS0 GO/DONE
—
ADON 0000 00-0 0000 00-0
ADCON1
PORTA
TRISA
—
—
—
—
—
—
—
—
PCFG2
RA2
PCFG1 PCFG0 ---- -000 ---- -000
RA5
RA4
RA3
RA1
RA0
RE0
--0x 0000 --0u 0000
--11 1111 --11 1111
PORTA Data Direction Register
(2)
09h
89h
PORTE
—
—
—
—
—
—
RE2
RE1
---- -xxx ---- -uuu
0000 -111 0000 -111
(2)
TRISE
IBF
OBF
IBOV PSPMODE
PORTE Data Direction Bits
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
2: These registers are reserved on the PIC16F73/76.
DS30325B-page 88
2002 Microchip Technology Inc.
PIC16F7X
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external RESET, Watchdog Timer Wake-up, or
through an interrupt.
12.0 SPECIAL FEATURES OF THE
CPU
These devices have a host of features intended to max-
imize system reliability, minimize cost through elimina-
tion of external components, provide power saving
operating modes and offer code protection. These are:
Several oscillator options are also made available to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. Configuration bits are used to select the
desired oscillator mode.
• Oscillator Selection
• RESET
Additional information on special features is available
in the PICmicro™ Mid-Range Reference Manual
(DS33023).
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
12.1 Configuration Bits
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
• Watchdog Timer (WDT)
• SLEEP
• Code Protection
• ID Locations
The user will note that address 2007h is beyond the
user program memory space, which can be accessed
only during programming.
• In-Circuit Serial Programming
These devices have a Watchdog Timer, which can be
enabled or disabled, using a configuration bit. It runs off
its own RC oscillator for added reliability.
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intended to keep the chip in RESET until the crystal
oscillator is stable. The other is the Power-up Timer
(PWRT), which provides a fixed delay of 72 ms (nomi-
nal) on power-up only. It is designed to keep the part in
RESET while the power supply stabilizes, and is
enabled or disabled, using a configuration bit. With
these two timers on-chip, most applications need no
external RESET circuitry.
2002 Microchip Technology Inc.
DS30325B-page 89
PIC16F7X
REGISTER 12-1: CONFIGURATION WORD (ADDRESS 2007h)(1)
U-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
U-0 R/P-1 R/P-1
R/P-1
R/P-1 R/P-1
—
BOREN
—
CP0 PWRTEN WDTEN FOSC1 FOSC0
bit0
bit13
bit 13-7
bit 6
Unimplemented: Read as ‘1’
BOREN: Brown-out Reset Enable bit
1 = BOR enabled
0 = BOR disabled
bit 5
bit 4
Unimplemented: Read as ‘1’
CP0: FLASH Program Memory Code Protection bit
1 = Code protection off
0 = All memory locations code protected
bit 3
PWRTEN: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 2
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: The erased (unprogrammed) value of the configuration word is 3FFFh.
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
DS30325B-page 90
2002 Microchip Technology Inc.
PIC16F7X
FIGURE 12-2:
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
12.2 Oscillator Configurations
12.2.1 OSCILLATOR TYPES
The PIC16F7X can be operated in four different oscil-
lator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
OSC1
Clock from
Ext. System
PIC16F7X
(HS Mode)
OSC2
• LP
• XT
• HS
• RC
Low Power Crystal
Open
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
12.2.2
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
TABLE 12-1: CERAMIC RESONATORS
(FOR DESIGN GUIDANCE
ONLY)
In XT, LP or HS modes, a crystal or ceramic resonator is
connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 12-1). The
PIC16F7X oscillator design requires the use of a parallel
cut crystal. Use of a series cut crystal may give a fre-
quency out of the crystal manufacturers specifications.
When in HS mode, the device can accept an external
clock source to drive the OSC1/CLKIN pin (Figure 12-2).
See Figure 15-1 or Figure 15-2 (depending on the part
number and VDD range) for valid external clock
frequencies.
Typical Capacitor Values Used:
Mode
Freq
OSC1
OSC2
XT
455 kHz
2.0 MHz
4.0 MHz
56 pF
47 pF
33 pF
56 pF
47 pF
33 pF
HS
8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
Capacitor values are for design guidance only.
FIGURE 12-1:
CRYSTAL/CERAMIC
RESONATOROPERATION
(HS, XT OR LP
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values were not optimized.
OSC CONFIGURATION)
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
(1)
C1
OSC1
To
Internal
Logic
XTAL
(3)
RF
See the notes at the bottom of page 92 for additional
information.
OSC2
SLEEP
PIC16F7X
(2)
RS
Resonators Used:
(1)
C2
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
Panasonic EFO-A455K04B
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
Murata Erie CSA16.00MX
Note 1: See Table 12-1 and Table 12-2 for recom-
mended values of C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the crystal chosen.
2002 Microchip Technology Inc.
DS30325B-page 91
PIC16F7X
TABLE 12-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
(FOR DESIGN GUIDANCE
ONLY)
12.2.3
RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (REXT) and capacitor (CEXT) values, and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C compo-
nents used. Figure 12-3 shows how the R/C combina-
tion is connected to the PIC16F7X.
Typical Capacitor Values
Crystal
Freq
Tested:
Osc Type
C1
C2
LP
XT
32 kHz
200 kHz
200 kHz
1 MHz
33 pF
15 pF
56 pF
15 pF
15 pF
15 pF
15 pF
15 pF
33 pF
15 pF
56 pF
15 pF
15 pF
15 pF
15 pF
15 pF
4 MHz
HS
4 MHz
FIGURE 12-3:
RC OSCILLATOR MODE
8 MHz
VDD
20 MHz
Capacitor values are for design guidance only.
REXT
Internal
OSC1
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
were not optimized.
Clock
CEXT
VSS
PIC16F7X
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
OSC2/CLKOUT
FOSC/4
Recommended values:
3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20pF
See the notes following this table for additional
information.
Crystals Used:
32 kHz
200 kHz
1 MHz
Epson C-001R32.768K-A
STD XTL 200.000KHz
ECS ECS-10-13-1
4 MHz
ECS ECS-40-20-1
8 MHz
EPSON CA-301 8.000M-C
EPSON CA-301 20.000M-C
20 MHz
Note 1: Higher capacitance increases the stability
of oscillator, but also increases the start-
up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external compo-
nents.
3: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
4: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
DS30325B-page 92
2002 Microchip Technology Inc.
PIC16F7X
Some registers are not affected in any RESET condi-
tion. Their status is unknown on POR and unchanged
in any other RESET. Most other registers are reset to a
“RESET state” on Power-on Reset (POR), on the
MCLR and WDT Reset, on MCLR Reset during
SLEEP, and Brown-out Reset (BOR). They are not
affected by a WDT Wake-up, which is viewed as the
resumption of normal operation. The TO and PD bits
are set or cleared differently in different RESET situa-
tions, as indicated in Table 12-4. These bits are used in
software to determine the nature of the RESET. See
Table 12-6 for a full description of RESET states of all
registers.
12.3 RESET
The PIC16F7X differentiates between various kinds of
RESET:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during SLEEP
• WDT Reset (during normal operation)
• WDT Wake-up (during SLEEP)
• Brown-out Reset (BOR)
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 12-4.
FIGURE 12-4:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
RESET
MCLR
SLEEP
WDT
WDT
Module
Time-out
Reset
VDD Rise
Detect
VDD
Power-on Reset
Brown-out
Reset
S
BODEN
OST/PWRT
OST
10-bit Ripple Counter
Chip_Reset
R
Q
OSC1
(1)
PWRT
10-bit Ripple Counter
On-chip
RC OSC
Enable PWRT
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2002 Microchip Technology Inc.
DS30325B-page 93
PIC16F7X
12.4 MCLR
12.6 Power-up Timer (PWRT)
PIC16F7X devices have a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in RESET as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an accept-
able level. A configuration bit is provided to enable/
disable the PWRT.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from previous devices of this family.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to VDD. The use of an RC
network, as shown in Figure 12-5, is suggested.
The power-up time delay will vary from chip to chip, due
to VDD, temperature and process variation. See DC
parameters for details (TPWRT, parameter #33).
12.7 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024 oscil-
lator cycles (from OSC1 input) delay after the PWRT
delay is over (if enabled). This helps to ensure that the
crystal oscillator or resonator has started and stabilized.
FIGURE 12-5:
RECOMMENDED MCLR
CIRCUIT
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset, or wake-up from
SLEEP.
VDD
PIC16F7X
R1
12.8 Brown-out Reset (BOR)
1 kΩ (or greater)
The configuration bit, BODEN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(parameter #35, about 100 µS), the brown-out situation
will reset the device. If VDD falls below VBOR for less
than TBOR, a RESET may not occur.
MCLR
C1
0.1 µF
(optional, not critical)
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer then keeps the device in RESET for
TPWRT (parameter #33, about 72 mS). If VDD should fall
below VBOR during TPWRT, the Brown-out Reset pro-
cess will restart when VDD rises above VBOR, with the
Power-up Timer Reset. The Power-up Timer is always
enabled when the Brown-out Reset circuit is enabled,
regardless of the state of the PWRT configuration bit.
12.5 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, tie the MCLR pin to VDD as
described in Section 12.4. A maximum rise time for
VDD is specified. See the Electrical Specifications for
details.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the device
must be held in RESET until the operating conditions
are met. For additional information, refer to Application
12.9 Time-out Sequence
On power-up, the time-out sequence is as follows: the
PWRT delay starts (if enabled) when a POR Reset
occurs. Then, OST starts counting 1024 oscillator
cycles when PWRT ends (LP, XT, HS). When the OST
ends, the device comes out of RESET.
Note,
AN607,
“Power-up
Trouble
Shooting”
(DS00607).
If MCLR is kept low long enough, all delays will expire.
Bringing MCLR high will begin execution immediately.
This is useful for testing purposes or to synchronize
more than one PIC16F7X device operating in parallel.
Table 12-5 shows the RESET conditions for the
STATUS, PCON and PC registers, while Table 12-6
shows the RESET conditions for all the registers.
DS30325B-page 94
2002 Microchip Technology Inc.
PIC16F7X
if bit BOR cleared, indicating a Brown-out Reset
occurred. When the Brown-out Reset is disabled, the
state of the BOR bit is unpredictable.
12.10 Power Control/Status Register
(PCON)
The Power Control/Status Register, PCON, has two
bits to indicate the type of RESET that last occurred.
Bit1 is POR (Power-on Reset Status bit). It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent RESETS to see
TABLE 12-3: TIME-OUT IN VARIOUS SITUATIONS
Power-up
Wake-up from
Oscillator Configuration
Brown-out
SLEEP
PWRTE = 0
72 ms + 1024 TOSC
72 ms
PWRTE = 1
XT, HS, LP
RC
1024 TOSC
72 ms + 1024 TOSC
72 ms
1024 TOSC
—
—
TABLE 12-4: STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
Significance
(PCON<1>) (PCON<0>) (STATUS<4>) (STATUS<3>)
0
0
0
1
1
1
1
1
x
x
x
0
1
1
1
1
1
0
x
1
0
0
u
1
1
x
0
1
1
0
u
0
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from
SLEEP
TABLE 12-5: RESET CONDITION FOR SPECIAL REGISTERS
Program
STATUS
Register
PCON
Register
Condition
Counter
Power-on Reset
000h
000h
0001 1xxx
000u uuuu
---- --0x
---- --uu
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset
000h
000h
0001 0uuu
0000 1uuu
uuu0 0uuu
0001 1uuu
---- --uu
---- --uu
---- --uu
---- --u0
WDT Wake-up
PC + 1
000h
Brown-out Reset
Interrupt wake-up from SLEEP
PC + 1(1)
uuu1 0uuu
---- --uu
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as '0'
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
2002 Microchip Technology Inc.
DS30325B-page 95
PIC16F7X
TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Power-on Reset,
Brown-out Reset
MCLR Reset,
WDT Reset
Wake-up via WDT or
Interrupt
Register
Devices
W
73
73
73
74
74
74
76
76
76
77
77
77
xxxx xxxx
N/A
uuuu uuuu
N/A
uuuu uuuu
N/A
INDF
TMR0
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
73
74
76
77
0000h
0000h
PC + 1(2)
STATUS
FSR
73
73
73
73
73
73
73
73
74
74
74
74
74
74
74
74
76
76
76
76
76
76
76
76
77
77
77
77
77
77
77
77
0001 1xxx
xxxx xxxx
--0x 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- -xxx
---0 0000
000q quuu(3)
uuuu uuuu
--0u 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---0 0000
uuuq quuu(3)
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---u uuuu
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
73
73
73
74
74
74
76
76
76
77
77
77
0000 000x
r000 0000
0000 0000
0000 000u
r000 0000
0000 0000
uuuu uuuu(1)
ruuu uuuu(1)
uuuu uuuu(1)
PIR2
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
---- ---0
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
-000 0000
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 -00x
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
0000 00-0
1111 1111
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
r000 0000
0000 0000
---- ---0
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0000
-000 0000
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
0000 -00x
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
0000 00-0
1111 1111
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
r000 0000
0000 0000
---- ---u(1)
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uu-u
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
ruuu uuuu
uuuu uuuu
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
OPTION_REG
TRISA
TRISB
TRISC
TRISD
TRISE
PIE1
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’, q= value depends on condition,
r= reserved, maintain clear
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
3: See Table 12-5 for RESET value for specific condition.
DS30325B-page 96
2002 Microchip Technology Inc.
PIC16F7X
TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on Reset,
Brown-out Reset
MCLR Reset,
WDT Reset
Wake-up via WDT or
Interrupt
Register
PIE2
Devices
73
73
73
73
73
73
73
73
73
73
73
73
73
74
74
74
74
74
74
74
74
74
74
74
74
74
76
76
76
76
76
76
76
76
76
76
76
76
76
77
77
77
77
77
77
77
77
77
77
77
77
77
---- ---0
---- --qq
1111 1111
--00 0000
0000 0000
0000 -010
0000 0000
---- -000
0--- 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
1--- ---0
---- ---0
---- --uu
1111 1111
--00 0000
0000 0000
0000 -010
0000 0000
---- -000
0--- 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
1--- ---0
---- ---u
---- --uu
1111 1111
--uu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
---- -uuu
u--- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
1--- ---u
PCON
PR2
SSPSTAT
SSPADD
TXSTA
SPBRG
ADCON1
PMDATA
PMADR
PMDATH
PMADRH
PMCON1
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ’0’, q= value depends on condition,
r= reserved, maintain clear
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
3: See Table 12-5 for RESET value for specific condition.
FIGURE 12-6:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH
RC NETWORK)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
2002 Microchip Technology Inc.
DS30325B-page 97
PIC16F7X
FIGURE 12-7:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 12-8:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 12-9:
SLOW RISE TIME (MCLR TIED TO VDD THROUGH RC NETWORK)
5V
1V
VDD
MCLR
0V
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30325B-page 98
2002 Microchip Technology Inc.
PIC16F7X
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
12.11 Interrupts
The PIC16F7X family has up to 12 sources of interrupt.
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
The peripheral interrupt flags are contained in the Spe-
cial Function Registers, PIR1 and PIR2. The corre-
sponding interrupt enable bits are contained in Special
Function Registers, PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in Special Function
Register, INTCON.
Note: Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. When bit GIE is enabled and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs, relative to
the current Q cycle. The latency is the same for one or
two-cycle instructions. Individual interrupt flag bits are
set, regardless of the status of their corresponding
mask bit, PEIE bit, or the GIE bit.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
FIGURE 12-10:
INTERRUPT LOGIC
PSPIF(1)
PSPIE(1)
Wake-up (If in SLEEP mode)
ADIF
ADIE
TMR0IF
TMR0IE
RCIF
RCIE
INTF
INTE
Interrupt to CPU
TXIF
TXIE
RBIF
RBIE
SSPIF
SSPIE
PEIE
GIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
Note 1: PSP interrupt is implemented only on PIC16F74/77 devices.
2002 Microchip Technology Inc.
DS30325B-page 99
PIC16F7X
12.11.1 INT INTERRUPT
12.12 Context Saving During Interrupts
External interrupt on the RB0/INT pin is edge triggered,
either rising, if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit GIE decides whether or not the pro-
cessor branches to the interrupt vector following wake-
up. See Section 12.14 for details on SLEEP mode.
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt (i.e., W, PCLATH and STA-
TUS registers). This will have to be implemented in
software, as shown in Example 12-1.
For the PIC16F73/74 devices, the register W_TEMP
must be defined in both banks 0 and 1 and must be
defined at the same offset from the bank base address
(i.e., If W_TEMP is defined at 20h in bank 0, it must
also be defined at A0h in bank 1.). The registers,
PCLATH_TEMP and STATUS_TEMP, are only defined
in bank 0.
Since the upper 16 bytes of each bank are common in
the PIC16F76/77 devices, temporary holding registers
W_TEMP, STATUS_TEMP and PCLATH_TEMP
should be placed in here. These 16 locations don’t
require banking and, therefore, make it easier for con-
text save and restore. The same code shown in
Example 12-1 can be used.
12.11.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit TMR0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit
TMR0IE (INTCON<5>). (Section 5.0)
12.11.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>), see
Section 4.2.
EXAMPLE 12-1:
SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
:
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
;Copy W to TEMP register
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
:(ISR)
:
;Insert user code here
MOVF
MOVWF
SWAPF
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Swap W_TEMP into W
DS30325B-page 100
2002 Microchip Technology Inc.
PIC16F7X
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
12.13 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscil-
lator, which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. That means that the WDT will
run, even if the clock on the OSC1/CLKIN and OSC2/
CLKOUT pins of the device has been stopped, for
example, by execution of a SLEEPinstruction.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and the postscaler, if
assigned to the WDT, and prevent it from
timing out and generating
RESET condition.
a device
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS regis-
ter will be cleared upon a Watchdog Timer time-out.
2: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but
the prescaler assignment is not changed.
The WDT can be permanently disabled by clearing
configuration bit, WDTE (Section 12.1).
FIGURE 12-11:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 5-1)
0
Postscaler
M
1
U
WDT Timer
X
8
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 5-1)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
TABLE 12-7: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
Bit 7
(1)
Bit 6
Bit 5
Bit 4
Bit 3
PWRTE(1) WDTE
PSA PS2
Bit 2
Bit 1
Bit 0
2007h
Config. bits
BODEN(1)
INTEDG
—
CP0
FOSC1
PS1
FOSC0
PS0
81h,181h
OPTION_REG RBPU
T0CS
T0SE
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for operation of these bits.
2002 Microchip Technology Inc.
DS30325B-page 101
PIC16F7X
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up
occurs, regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
the instruction after the SLEEPinstruction. If the GIE bit
is set (enabled), the device executes the instruction
after the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the execu-
tion of the instruction following SLEEP is not desirable,
the user should have a NOPafter the SLEEPinstruction.
12.14 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should also be considered.
12.14.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEPinstruction, the SLEEPinstruction will com-
plete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
The MCLR pin must be at a logic high level (VIHMC).
12.14.1 WAKE-UP FROM SLEEP
• If the interrupt occurs during or after the execu-
tion of a SLEEPinstruction, the device will imme-
diately wake-up from SLEEP. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
The device can wake-up from SLEEP through one of
the following events:
1. External RESET input on MCLR pin.
2. Watchdog Timer wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change or a
Peripheral Interrupt.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred and caused
wake-up.
To ensure that the WDT is cleared, a CLRWDTinstruc-
tion should be executed before a SLEEPinstruction.
The following peripheral interrupts can wake the device
from SLEEP:
1. PSP read or write (PIC16F74/77 only).
2. TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
3. CCP Capture mode interrupt.
4. Special event trigger (Timer1 in Asynchronous
mode, using an external clock).
5. SSP (START/STOP) bit detect interrupt.
6. SSP transmit or receive in Slave mode
(SPI/I2C).
7. USART RX or TX (Synchronous Slave mode).
8. A/D conversion (when A/D clock source is RC).
Other peripherals cannot generate interrupts, since
during SLEEP, no on-chip clocks are present.
DS30325B-page 102
2002 Microchip Technology Inc.
PIC16F7X
FIGURE 12-12:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(2)
TOST
CLKOUT(4)
INT pin
INTF Flag
Interrupt Latency
(INTCON<1>)
(Note 2)
GIE bit
Processor in
SLEEP
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
Fetched
Instruction
Executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(PC - 1)
Inst(0004h)
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024 TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine.
If GIE = ’0’, execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
For general information of serial programming, please
refer to the In-Circuit Serial Programming (ICSP™)
Guide (DS30277). For specific details on programming
commands and operations for the PIC16F7X devices,
please refer to the latest version of the PIC16F7X
FLASH Program Memory Programming Specification
(DS30324).
12.15 Program Verification/Code
Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
12.16 ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during program/verify. It is recom-
mended that only the 4 Least Significant bits of the ID
location are used.
FIGURE 12-13:
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
To Normal
Connections
12.17 In-Circuit Serial Programming
External
Connector
Signals
*
PIC16F7X
PIC16F7X microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done, with two lines for clock and data and three
other lines for power, ground, and the programming
voltage (see Figure 12-13 for an example). This allows
customers to manufacture boards with unprogrammed
devices, and then program the microcontroller just
before shipping the product. This also allows the most
recent firmware or a custom firmware to be pro-
grammed.
+5V
0V
VDD
VSS
VPP
MCLR/VPP
RB6
RB7
CLK
Data I/O
*
*
*
VDD
To Normal
Connections
* Isolation devices (as required).
2002 Microchip Technology Inc.
DS30325B-page 103
PIC16F7X
NOTES:
DS30325B-page 104
2002 Microchip Technology Inc.
PIC16F7X
For example, a “clrf PORTB” instruction will read
PORTB, clear all the data bits, then write the result
back to PORTB. This example would have the unin-
tended result that the condition that sets the RBIF flag
would be cleared for pins configured as inputs and
using the PORTB interrupt-on-change feature.
13.0 INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is
comprised of three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
TABLE 13-1: OPCODE FIELD
DESCRIPTIONS
Each PIC16 instruction is a 14-bit word divided into an
opcode, which specifies the instruction type and one or
more operands, which further specify the operation of
the instruction. The formats for each of the categories
are presented in Figure 13-1, while the various opcode
fields are summarized in Table 13-1.
Field
Description
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
Table 13-2 lists the instructions recognized by the
MPASMTM Assembler. A complete description of each
instruction is also available in the PICmicro™ Mid-
Range Reference Manual (DS33023).
Don't care location (= 0or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
For byte-oriented instructions, ‘f’ represents a file reg-
ister designator and ‘d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
PC
TO
PD
Program Counter
Time-out bit
Power-down bit
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the opera-
tion, while ‘f’ represents the address of the file in which
the bit is located.
FIGURE 13-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
For literal and control operations, ‘k’ represents an
eight- or eleven-bit constant or literal value
8
7
6
0
OPCODE
d
f (FILE #)
One instruction cycle consists of four oscillator periods;
for an oscillator frequency of 4 MHz, this gives a normal
instruction execution time of 1 µs. All instructions are
executed within a single instruction cycle, unless a con-
ditional test is true, or the program counter is changed
as a result of an instruction. When this occurs, the exe-
cution takes two instruction cycles, with the second
cycle executed as a NOP.
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9
b (BIT #)
7
6
0
OPCODE
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Note: To maintain upward compatibility with
future PIC16F7X products, do not use the
OPTIONand TRISinstructions.
Literal and control operations
All instruction examples use the format ‘0xhh’ to repre-
sent a hexadecimal number, where ‘h’ signifies a hexa-
decimal digit.
General
13
8
7
0
0
OPCODE
k (literal)
13.1 READ-MODIFY-WRITE
OPERATIONS
k = 8-bit immediate value
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
k (literal)
2002 Microchip Technology Inc.
DS30325B-page 105
PIC16F7X
TABLE 13-2: PIC16F7X INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Description
Operands
Status
Affected
Cycles
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00 0111 dfff ffff C,DC,Z
1,2
1,2
2
00 0101 dfff ffff
00 0001 lfff ffff
00 0001 0xxx xxxx
00 1001 dfff ffff
00 0011 dfff ffff
00 1011 dfff ffff
00 1010 dfff ffff
00 1111 dfff ffff
00 0100 dfff ffff
00 1000 dfff ffff
00 0000 lfff ffff
00 0000 0xx0 0000
00 1101 dfff ffff
00 1100 dfff ffff
Z
Z
Z
Z
Z
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
DECFSZ
INCF
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
Move W to f
No Operation
-
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
00 0010 dfff ffff C,DC,Z
00 1110 dfff ffff
00 0110 dfff ffff
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01 00bb bfff ffff
1,2
1,2
3
01 01bb bfff ffff
01 10bb bfff ffff
01 11bb bfff ffff
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11 111x kkkk kkkk C,DC,Z
11 1001 kkkk kkkk
10 0kkk kkkk kkkk
00 0000 0110 0100
10 1kkk kkkk kkkk
11 1000 kkkk kkkk
11 00xx kkkk kkkk
00 0000 0000 1001
11 01xx kkkk kkkk
00 0000 0000 1000
00 0000 0110 0011
Z
TO,PD
Z
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
TO,PD
11 110x kkkk kkkk C,DC,Z
11 1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023).
DS30325B-page 106
2002 Microchip Technology Inc.
PIC16F7X
13.2 Instruction Descriptions
ADDLW
Add Literal and W
BCF
Bit Clear f
Syntax:
[ label ] ADDLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] BCF f,b
Operands:
Operation:
Status Affected:
Description:
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
(W) + k → (W)
C, DC, Z
Operation:
0 → (f<b>)
Status Affected:
Description:
None
The contents of the W register
are added to the eight-bit literal ’k’
and the result is placed in the W
register.
Bit 'b' in register 'f' is cleared.
BSF
Bit Set f
ADDWF
Add W and f
Syntax:
[ label ] BSF f,b
Syntax:
[ label ] ADDWF f,d
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
1 → (f<b>)
Operation:
(W) + (f) → (destination)
Status Affected:
Description:
None
Status Affected: C, DC, Z
Bit 'b' in register 'f' is set.
Description:
Add the contents of the W register
with register ’f’. If ’d’ is 0, the result
is stored in the W register. If ’d’ is
1, the result is stored back in
register ’f’.
BTFSS
Bit Test f, Skip if Set
ANDLW
AND Literal with W
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
k
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
Status Affected:
Description:
(W) .AND. (k) → (W)
Operation:
skip if (f<b>) = 1
Z
Status Affected: None
The contents of W register are
AND’ed with the eight-bit literal
'k'. The result is placed in the W
register.
Description:
If bit 'b' in register 'f' is '0', the next
instruction is executed.
If bit 'b' is '1', then the next instruc-
tion is discarded and a NOPis
executed instead, making this a
2TCY instruction.
BTFSC
Bit Test, Skip if Clear
ANDWF
AND W with f
Syntax:
[ label ] BTFSC f,b
Syntax:
[ label ] ANDWF f,d
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
skip if (f<b>) = 0
Operation:
(W) .AND. (f) → (destination)
Status Affected: None
Status Affected:
Description:
Z
Description: If bit 'b' in register 'f' is '1', the next
AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W register. If 'd' is 1, the result
is stored back in register 'f'.
instruction is executed.
If bit 'b', in register 'f', is '0', the
next instruction is discarded, and
a NOPis executed instead, making
this a 2TCY instruction.
2002 Microchip Technology Inc.
DS30325B-page 107
PIC16F7X
CALL
Call Subroutine
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL
0 ≤ k ≤ 2047
k
Syntax:
[ label ] CLRWDT
Operands:
Operation:
Operands:
Operation:
None
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Status Affected: None
Status Affected: TO, PD
Description:
Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven-bit immedi-
ate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALLis
a two-cycle instruction.
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT. Status bits
TO and PD are set.
CLRF
Clear f
COMF
Complement f
Syntax:
[ label ] CLRF
0 ≤ f ≤ 127
f
Syntax:
[ label ] COMF f,d
Operands:
Operation:
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
00h → (f)
1 → Z
Operation:
(f) → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
The contents of register ’f’ are
cleared and the Z bit is set.
The contents of register ’f’ are
complemented. If ’d’ is 0, the
result is stored in W. If ’d’ is 1, the
result is stored back in register ’f’.
CLRW
Clear W
DECF
Decrement f
Syntax:
[ label ] CLRW
Syntax:
[ label ] DECF f,d
Operands:
Operation:
None
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
00h → (W)
1 → Z
Operation:
(f) - 1 → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
W register is cleared. Zero bit (Z)
is set.
Decrement register ’f’. If ’d’ is 0,
the result is stored in the W
register. If ’d’ is 1, the result is
stored back in register ’f’.
DS30325B-page 108
2002 Microchip Technology Inc.
PIC16F7X
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ] INCFSZ f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (destination);
skip if result = 0
Operation:
(f) + 1 → (destination),
skip if result = 0
Status Affected: None
Status Affected: None
Description:
The contents of register ’f’ are
Description:
The contents of register ’f’ are
decremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in
register ’f’.
incremented. If ’d’ is 0, the result is
placed in the W register. If ’d’ is 1,
the result is placed back in
register ’f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
then a NOPis executed instead,
making it a 2TCY instruction.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
a NOPis executed instead, making
it a 2TCY instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR Literal with W
Syntax:
[ label ] GOTO k
0 ≤ k ≤ 2047
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
Operands:
Operation:
Operands:
Operation:
Status Affected:
Description:
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
(W) .OR. k → (W)
Z
Status Affected: None
The contents of the W register are
OR’ed with the eight-bit literal 'k'.
The result is placed in the W
register.
Description:
GOTOis an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTOis a two-
cycle instruction.
IORWF
Inclusive OR W with f
INCF
Increment f
Syntax:
[ label ] IORWF f,d
Syntax:
[ label ] INCF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) .OR. (f) → (destination)
Operation:
(f) + 1 → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Inclusive OR the W register with
register 'f'. If 'd' is 0, the result is
placed in the W register. If 'd' is 1,
the result is placed back in
register 'f'.
The contents of register ’f’ are
incremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in
register ’f’.
2002 Microchip Technology Inc.
DS30325B-page 109
PIC16F7X
MOVF
Move f
NOP
No Operation
Syntax:
[ label ] MOVF f,d
Syntax:
[ label ] NOP
None
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
No operation
Operation:
(f) → (destination)
Status Affected: None
Status Affected:
Description:
Z
Description:
No operation.
The contents of register f are
moved to a destination dependant
upon the status of d. If d = 0,
destination is W register. If d = 1,
the destination is file register f itself.
d = 1 is useful to test a file register,
since status flag Z is affected.
MOVLW
Move Literal to W
RETFIE
Return from Interrupt
Syntax:
[ label ] MOVLW k
0 ≤ k ≤ 255
k → (W)
Syntax:
[ label ] RETFIE
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
None
TOS → PC,
1 → GIE
None
Status Affected: None
The eight-bit literal ’k’ is loaded
into W register. The don’t cares
will assemble as 0’s.
MOVWF
Move W to f
RETLW
Return with Literal in W
Syntax:
[ label ] MOVWF
0 ≤ f ≤ 127
(W) → (f)
f
Syntax:
[ label ] RETLW
0 ≤ k ≤ 255
k
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
k → (W);
TOS → PC
None
Status Affected: None
Description:
Move data from W register to
register 'f'.
The W register is loaded with the
eight-bit literal 'k'. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
DS30325B-page 110
2002 Microchip Technology Inc.
PIC16F7X
RLF
Rotate Left f through Carry
SLEEP
Syntax:
[ label ] RLF f,d
Syntax:
[ label ] SLEEP
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
None
00h → WDT,
0 → WDT prescaler,
1 → TO,
Operation:
See description below
C
Status Affected:
Description:
0 → PD
The contents of register ’f’are rotated
one bit to the left through the Carry
Flag. If ’d’ is 0, the result is placed in
the W register. If ’d’ is 1, the result is
stored back in register ’f’.
Status Affected:
Description:
TO, PD
The power-down status bit, PD is
cleared. Time-out status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
C
Register f
The processor is put into SLEEP
mode with the oscillator stopped.
RETURN
Return from Subroutine
SUBLW
Subtract W from Literal
Syntax:
[ label ] RETURN
None
Syntax:
[ label ] SUBLW k
0 ≤ k ≤ 255
Operands:
Operation:
Operands:
Operation:
TOS → PC
k - (W) → (W)
Status Affected: None
Status Affected: C, DC, Z
Description:
Return from subroutine. The stack
Description:
The W register is subtracted (2’s
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
complement method) from the
eight-bit literal 'k'. The result is
placed in the W register.
RRF
Rotate Right f through Carry
SUBWF
Subtract W from f
Syntax:
[ label ] RRF f,d
Syntax:
[ label ] SUBWF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
See description below
C
Operation:
(f) - (W) → (destination)
Status Affected:
Description:
Status Affected: C, DC, Z
The contents of register ’f’ are
rotated one bit to the right through
the Carry Flag. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in
register ’f’.
Description: Subtract (2’s complement method)
W register from register 'f'. If 'd' is 0,
the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
C
Register f
2002 Microchip Technology Inc.
DS30325B-page 111
PIC16F7X
SWAPF
Swap Nibbles in f
XORWF
Exclusive OR W with f
Syntax:
[ label ] SWAPF f,d
Syntax:
[ label ] XORWF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Operation:
(W) .XOR. (f) → (destination)
Status Affected:
Description:
Z
Status Affected: None
Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0, the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
Description:
The upper and lower nibbles of
register ’f’ are exchanged. If ’d’ is
0, the result is placed in the W
register. If ’d’ is 1, the result is
placed in register ’f’.
XORLW
Exclusive OR Literal with W
Syntax:
[ label ] XORLW k
0 ≤ k ≤ 255
Operands:
Operation:
Status Affected:
Description:
(W) .XOR. k → (W)
Z
The contents of the W register
are XOR’ed with the eight-bit
literal 'k'. The result is placed in
the W register.
DS30325B-page 112
2002 Microchip Technology Inc.
PIC16F7X
The MPLAB IDE allows you to:
14.0 DEVELOPMENT SUPPORT
• Edit your source files (either assembly or ‘C’)
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools (auto-
matically updates all project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- absolute listing file
- machine code
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
The ability to use MPLAB IDE with multiple debugging
tools allows users to easily switch from the cost-
effective simulator to a full-featured emulator with
minimal retraining.
• Simulators
- MPLAB SIM Software Simulator
• Emulators
14.2 MPASM Assembler
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
• In-Circuit Debugger
The MPASM assembler is a full-featured universal
macro assembler for all PICmicro MCU’s.
- MPLAB ICD
The MPASM assembler has a command line interface
and a Windows shell. It can be used as a stand-alone
application on a Windows 3.x or greater system, or it
can be used through MPLAB IDE. The MPASM assem-
bler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
detail memory usage and symbol reference, an abso-
lute LST file that contains source lines and generated
machine code, and a COD file for debugging.
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Entry-Level Development
Programmer
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 17 Demonstration Board
- KEELOQ® Demonstration Board
The MPASM assembler features include:
• Integration into MPLAB IDE projects.
• User-defined macros to streamline assembly
code.
14.1 MPLAB Integrated Development
Environment Software
• Conditional assembly for multi-purpose source
files.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. The MPLAB IDE is a Windows®-based
application that contains:
• Directives that allow complete control over the
assembly process.
14.3 MPLAB C17 and MPLAB C18
C Compilers
• An interface to debugging tools
- simulator
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI ‘C’ compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers, respectively. These compilers provide
powerful integration capabilities and ease of use not
found with other compilers.
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor
• A project manager
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• Customizable toolbar and key mapping
• A status bar
• On-line help
2002 Microchip Technology Inc.
DS30325B-page 113
PIC16F7X
14.4 MPLINK Object Linker/
MPLIB Object Librarian
14.6 MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can also
link relocatable objects from pre-compiled libraries,
using directives from a linker script.
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PICmicro
microcontrollers (MCUs). Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment (IDE),
which allows editing, building, downloading and source
debugging from a single environment.
The MPLIB object librarian is a librarian for pre-
compiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine will be linked in with the application. This allows
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLINK object linker features include:
• Integration with MPASM assembler and MPLAB
C17 and MPLAB C18 C compilers.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows environment were chosen to best
make these features available to you, the end user.
• Allows all memory areas to be defined as sections
to provide link-time flexibility.
The MPLIB object librarian features include:
• Easier linking because single libraries can be
included instead of many smaller files.
• Helps keep code maintainable by grouping
related modules together.
14.7 ICEPIC In-Circuit Emulator
• Allows libraries to be created and modules to be
added, listed, replaced, deleted or extracted.
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit One-
Time-Programmable (OTP) microcontrollers. The mod-
ular system can support different subsets of PIC16C5X
or PIC16CXXX products through the use of inter-
changeable personality modules, or daughter boards.
The emulator is capable of emulating without target
application circuitry being present.
14.5 MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC-hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user-defined key press, to any of the pins. The
execution can be performed in single step, execute
until break, or trace mode.
The MPLAB SIM simulator fully supports symbolic debug-
ging using the MPLAB C17 and the MPLAB C18 C com-
pilers and the MPASM assembler. The software simulator
offers the flexibility to develop and debug code outside of
the laboratory environment, making it an excellent multi-
project software development tool.
DS30325B-page 114
2002 Microchip Technology Inc.
PIC16F7X
14.8 MPLAB ICD In-Circuit Debugger
14.11 PICDEM 1 Low Cost PICmicro
Demonstration Board
Microchip’s In-Circuit Debugger, MPLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based on the FLASH PICmicro MCUs and can be used
to develop for this and other PICmicro microcontrollers.
The MPLAB ICD utilizes the in-circuit debugging capa-
bility built into the FLASH devices. This feature, along
with Microchip’s In-Circuit Serial ProgrammingTM proto-
col, offers cost-effective in-circuit FLASH debugging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by watch-
ing variables, single-stepping and setting break points.
Running at full speed enables testing hardware in real-
time.
The PICDEM 1 demonstration board is a simple board
which demonstrates the capabilities of several of
Microchip’s microcontrollers. The microcontrollers sup-
ported are: PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcon-
trollers provided with the PICDEM 1 demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulator and download the firmware to the emu-
lator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simu-
lated analog input, push button switches and eight
LEDs connected to PORTB.
14.9 PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions
and error messages, keys to enter commands and a
modular detachable socket assembly to support various
package types. In stand-alone mode, the PRO MATE II
device programmer can read, verify, or program
PICmicro devices. It can also set code protection in this
mode.
14.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PICDEM 2 demonstration board is a simple dem-
onstration board that supports the PIC16C62,
PIC16C64, PIC16C65, PIC16C73 and PIC16C74
microcontrollers. All the necessary hardware and soft-
ware is included to run the basic demonstration pro-
grams. The user can program the sample
microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches, a potentiometer for simulated analog input, a
serial EEPROM to demonstrate usage of the I2CTM bus
and separate headers for connection to an LCD
module and a keypad.
14.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient.
The PICSTART Plus development programmer sup-
ports all PICmicro devices with up to 40 pins. Larger pin
count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.
2002 Microchip Technology Inc.
DS30325B-page 115
PIC16F7X
14.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
14.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. All neces-
sary hardware is included to run basic demo programs,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM 17 dem-
onstration board supports downloading of programs to
and executing out of external FLASH memory on board.
The PICDEM 17 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMASTER emulator and all of the sample programs
can be run and modified using either emulator. Addition-
ally, a generous prototype area is available for user
hardware.
The PICDEM 3 demonstration board is a simple dem-
onstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-pin PLCC microcontrollers with an LCD Mod-
ule. All the necessary hardware and software is
included to run the basic demonstration programs. The
user can program the sample microcontrollers pro-
vided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer, or a PICSTART Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding hardware and connecting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commons and 12 segments, that is capable of display-
ing time, temperature and day of the week. The
PICDEM 3 demonstration board provides an additional
RS-232 interface and Windows software for showing
the demultiplexed LCD signals on a PC. A simple serial
interface allows the user to construct a hardware
demultiplexer for the LCD signals.
14.15 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS eval-
uation kit includes a LCD display to show changing
codes, a decoder to decode transmissions and a pro-
gramming interface to program test transmitters.
DS30325B-page 116
2002 Microchip Technology Inc.
PIC16F7X
TABLE 14-1: DEVELOPMENT TOOLS FROM MICROCHIP
0 1 5 2 P M C
X X X C R M F
H C S X X X
X X C 9 3
/ X X C 2 5
/ X X C 2 4
X X X F 8 C 1 P I
X X C 8 2 C 1 P I
X 7 X 7 C 1 C I P
X 4 1 7 C I C P
X 9 X 6 C 1 C I P
X 8 X 6 F 1 C I P
X 8 1 6 C I C P
X 7 X 6 C 1 C I P
X 7 1 6 C I C P
X 6 2 1 6 C I F P
X
X X C 6 C 1 P I
X 6 1 6 C I C P
X 5 1 6 C I C P
0 0 1 4 C I 0 P
X
X X C 2 C 1 P I
s o l T e o r a w f t S o s r o t a u l E m e r u b g e g D s m e a r m o g P r r
s t K l a i E d v n a s d r a B o o m D e
2002 Microchip Technology Inc.
DS30325B-page 117
PIC16F7X
NOTES:
DS30325B-page 118
2002 Microchip Technology Inc.
PIC16F7X
15.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.................................................................................................................-55 to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4) ......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +6.5V
Voltage on MCLR with respect to VSS (Note 2) ..............................................................................................0 to +13.5V
Voltage on RA4 with respect to Vss...................................................................................................................0 to +12V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3)...................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3)..............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3) .................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3) ............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spikes at the MCLR pin may cause latchup. A series resistor of greater than 1 kΩ should be used
to pull MCLR to VDD, rather than tying the pin directly to VDD.
3: PORTD and PORTE are not implemented on the PIC16F73/76 devices.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2002 Microchip Technology Inc.
DS30325B-page 119
PIC16F7X
FIGURE 15-1:
PIC16F7X VOLTAGE-FREQUENCY GRAPH
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
16 MHz
20 MHz
Frequency
FIGURE 15-2:
PIC16LF7X VOLTAGE-FREQUENCY GRAPH
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
4 MHz
10 MHz
Frequency
FMAX = (12 MHz/V) (VDDAPPMIN - 2.5V) + 4 MHz
Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
Note 2: FMAX has a maximum frequency of 10 MHz.
DS30325B-page 120
2002 Microchip Technology Inc.
PIC16F7X
15.1 DC Characteristics: PIC16F73/74/76/77 (Industrial, Extended)
PIC16LF73/74/76/77 (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC16LF73/74/76/77
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
PIC16F73/74/76/77
(Industrial, Extended)
Param
Sym
No.
Characteristic
Min Typ† Max Units
Conditions
VDD
Supply Voltage
PIC16LF7X 2.5
D001
—
—
—
5.5
5.5
5.5
V
V
V
A/D in use, -40°C to +85°C
A/D in use, 0°C to +85°C
A/D not used, -40°C to +85°C
2.2
2.0
D001
D001A
PIC16F7X 4.0
-
-
5.5
5.5
V
V
All configurations
BOR enabled (Note 7)
VBOR*
D002* VDR
RAM Data Retention
Voltage (Note 1)
-
-
1.5
-
V
D003 VPOR VDD Start Voltage to
ensure internal Power-on
Reset signal
VSS
-
V
See section on Power-on Reset for details
D004* SVDD VDD Rise Rate to ensure
internal Power-on Reset
signal
0.05
-
-
V/ms See section on Power-on Reset for details
D005 VBOR Brown-out Reset Voltage 3.65
4.0 4.35
V
BODEN bit in configuration word enabled
Legend: Shading of rows is to assist in readability of of the table.
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from-rail to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from character-
ization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
2002 Microchip Technology Inc.
DS30325B-page 121
PIC16F7X
15.1 DC Characteristics: PIC16F73/74/76/77 (Industrial, Extended)
PIC16LF73/74/76/77 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC16LF73/74/76/77
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
PIC16F73/74/76/77
(Industrial, Extended)
Param
Sym
No.
Characteristic
Min Typ† Max Units
Conditions
IDD
Supply Current (Notes 2, 5)
D010
PIC16LF7X
—
—
0.4 2.0
mA XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
µA LP osc configuration
D010A
20
48
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D010
D013
PIC16F7X
-
0.9
5.2
4
mA XT, RC osc configuration
FOSC = 4 MHz, VDD = 5.5V (Note 4)
mA HS osc configuration
—
15
FOSC = 20 MHz, VDD = 5.5V
D015* ∆IBOR Brown-out
Reset Current (Note 6)
Power-down Current (Notes 3, 5)
—
25 200
µA BOR enabled, VDD = 5.0V
D020
IPD
PIC16LF7X
—
—
2.0
0.1
30
5
µA VDD = 3.0V, WDT enabled, -40°C to +85°C
µA VDD = 3.0V, WDT disabled, -40°C to +85°C
D021
D020
D021
D021A
PIC16F7X
—
—
—
—
5.0
0.1
10.5 57
1.5 42
25 200
42
19
µA VDD = 4.0V, WDT enabled, -40°C to +85°C
µA VDD = 4.0V, WDT disabled, -40°C to +85°C
µA VDD = 4.0V, WDT enabled, -40°C to +125°C
µA VDD = 4.0V, WDT disabled, -40°C to +125°C
D023* ∆IBOR Brown-out
Reset Current (Note 6)
Legend: Shading of rows is to assist in readability of of the table.
—
µA BOR enabled, VDD = 5.0V
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from-rail to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from character-
ization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
DS30325B-page 122
2002 Microchip Technology Inc.
PIC16F7X
15.2 DC Characteristics: PIC16F73/74/76/77 (Industrial, Extended)
PIC16LF73/74/76/77 (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC Specification,
Section 15.1.
DC CHARACTERISTICS
Param
Sym
Characteristic
Min
Typ† Max Units
Conditions
No.
VIL
Input Low Voltage
I/O ports:
D030
D030A
D031
with TTL buffer
VSS
VSS
VSS
—
—
—
0.15VDD
0.8V
V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
0.2VDD
D032
D033
MCLR, OSC1 (in RC mode)
OSC1 (in XT and LP mode)
OSC1 (in HS mode)
Input High Voltage
I/O ports:
VSS
VSS
VSS
—
—
—
0.2VDD
0.3V
V
V
V
(Note 1)
0.3VDD
VIH
D040
with TTL buffer
2.0
—
—
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
D040A
0.25VDD
+ 0.8V
For entire VDD range
D041
with Schmitt Trigger buffer
0.8VDD
—
VDD
V
For entire VDD range
D042
MCLR
0.8VDD
1.6V
—
—
VDD
VDD
VDD
VDD
400
V
V
V
V
D042A
OSC1 (in XT and LP mode)
OSC1 (in HS mode)
OSC1 (in RC mode)
0.7VDD
0.9VDD
50
—
D043
D070
—
(Note 1)
IPURB PORTB Weak Pull-up Current
IIL
250
µA VDD = 5V, VPIN = VSS
Input Leakage Current (Notes 2, 3)
D060
I/O ports
—
—
±1
µA Vss ≤ VPIN ≤ VDD, pin at
hi-impedance
D061
D063
MCLR, RA4/T0CKI
OSC1
—
—
—
—
±5
±5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS and LP
osc configuration
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
2002 Microchip Technology Inc.
DS30325B-page 123
PIC16F7X
15.2 DC Characteristics: PIC16F73/74/76/77 (Industrial, Extended)
PIC16LF73/74/76/77 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Param
Operating voltage VDD range as described in DC Specification,
Section 15.1.
Sym
Characteristic
Min
Typ† Max Units
Conditions
No.
VOL
Output Low Voltage
D080
D083
I/O ports
—
—
0.6
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
OSC2/CLKOUT (RC osc config)
—
—
—
—
0.6
0.6
V
V
VOH
Output High Voltage
D090
D092
I/O ports (Note 3)
VDD - 0.7
—
—
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +125°C
OSC2/CLKOUT (RC osc config) VDD - 0.7
VDD - 0.7
—
—
—
—
V
V
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
D150* VOD Open Drain High Voltage
—
—
—
12
15
V
RA4 pin
Capacitive Loading Specs on Output Pins
D100
COSC2 OSC2 pin
—
pF In XT, HS and LP modes when
external clock is used to drive
OSC1
D101
D102
CIO
CB
All I/O pins and OSC2
(in RC mode)
—
—
—
—
50
pF
SCL, SDA in I2C mode
Program FLASH Memory
Endurance
400
pF
D130
D131
EP
100
2.0
1000
—
E/W 25°C at 5V
VPR
VDD for Read
—
5.5
V
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS30325B-page 124
2002 Microchip Technology Inc.
PIC16F7X
15.3 Timing Parameter Symbology
The timing parameter symbols have been created
using one of the following formats:
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
T
Time
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
ST
DAT
STA
Hold
SU
Setup
DATA input hold
START condition
STO
STOP condition
FIGURE 15-3:
LOAD CONDITIONS
Load Condition 1
VDD/2
Load Condition 2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF
15 pF
for all pins except OSC2, but including PORTD and PORTE outputs as ports
for OSC2 output
Note: PORTD and PORTE are not implemented on the PIC16F73/76 devices.
2002 Microchip Technology Inc.
DS30325B-page 125
PIC16F7X
FIGURE 15-4:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
4
Q1
OSC1
1
3
4
3
2
CLKOUT
TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
Symbol
Characteristic
Min Typ†
Max
Units
Conditions
No.
FOSC
External CLKIN Frequency
(Note 1)
DC
DC
DC
DC
0.1
—
—
—
—
—
1
20
32
4
MHz XT osc mode
MHz HS osc mode
kHz LP osc mode
MHz RC osc mode
MHz XT osc mode
Oscillator Frequency
(Note 1)
4
4
5
—
—
20
200
MHz HS osc mode
kHz LP osc mode
1
TOSC
External CLKIN Period
(Note 1)
1000
50
—
—
—
—
ns XT osc mode
ns HS osc mode
ms LP osc mode
ns RC osc mode
ns XT osc mode
ns HS osc mode
ms LP osc mode
ns TCY = 4/FOSC
5
—
—
Oscillator Period
(Note 1)
250
250
50
—
—
—
10,000
250
—
—
5
—
2
3
TCY
Instruction Cycle Time
(Note 1)
200
TCY
DC
TosL,
TosH
External Clock in (OSC1)
High or Low Time
500
2.5
15
—
—
—
—
—
—
—
—
—
—
25
50
15
ns XT oscillator
ms LP oscillator
ns HS oscillator
ns XT oscillator
ns LP oscillator
ns HS oscillator
4
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time
—
—
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions, with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at "min." values with an
external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "max." cycle time
limit is "DC" (no clock) for all devices.
DS30325B-page 126
2002 Microchip Technology Inc.
PIC16F7X
FIGURE 15-5:
CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
14
12
18
19
16
I/O Pin
(Input)
15
17
I/O Pin
(Output)
New Value
Old Value
20, 21
Note: Refer to Figure 15-3 for load conditions.
TABLE 15-2: CLKOUT AND I/O TIMING REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ†
Max
Units Conditions
10*
11*
12*
13*
14*
15*
16*
17*
18*
TosH2ckL OSC1↑ to CLKOUT↓
TosH2ckH OSC1↑ to CLKOUT↑
—
—
—
—
—
75
75
35
35
—
200
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns
200
TckR
TckF
CLKOUT rise time
CLKOUT fall time
100
100
TckL2ioV CLKOUT↓ to Port out valid
TioV2ckH Port in valid before CLKOUT↑
0.5TCY + 20
TOSC + 200
—
—
—
TckH2ioI
Port in hold after CLKOUT↑
0
—
TosH2ioV OSC1↑ (Q1 cycle) to Port out valid
—
100
—
255
—
TosH2ioI
OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
Standard (F)
100
200
ns
Extended (LF)
—
—
ns
19*
20*
TioV2osH Port input valid to OSC1↑ (I/O in setup time)
0
—
—
10
—
10
—
—
—
—
40
ns
ns
ns
ns
ns
ns
ns
TioR
Port output rise time
Port output fall time
INT pin high or low time
Standard (F)
Extended (LF)
Standard (F)
Extended (LF)
—
145
40
21*
TioF
—
—
145
—
22††* Tinp
23††* Trbp
TCY
TCY
RB7:RB4 change INT high or low time
—
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
†† These parameters are asynchronous events, not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKOUT output is 4 x TOSC.
2002 Microchip Technology Inc.
DS30325B-page 127
PIC16F7X
FIGURE 15-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note: Refer to Figure 15-3 for load conditions.
FIGURE 15-7:
BROWN-OUT RESET TIMING
VBOR
VDD
35
TABLE 15-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
No.
30
TmcL
MCLR Pulse Width (low)
2
7
—
—
µs
VDD = 5V, -40°C to +85°C
31*
TWDT
Watchdog Timer Time-out Period
(No Prescaler)
18
33
ms VDD = 5V, -40°C to +85°C
32
TOST
Oscillation Start-up Timer Period
Power-up Timer Period
—
1024 TOSC
72
—
—
TOSC = OSC1 period
33*
TPWRT
28
132
ms VDD = 5V, -40°C to +85°C
µs
34
TIOZ
I/O Hi-Impedance from MCLR Low
or Watchdog Timer Reset
—
—
2.1
35
TBOR
Brown-out Reset Pulse Width
100
—
—
µs
VDD ≤ VBOR (D005)
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS30325B-page 128
2002 Microchip Technology Inc.
PIC16F7X
FIGURE 15-8:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RC0/T1OSO/T1CKI
46
45
47
48
TMR0 or TMR1
Note: Refer to Figure 15-3 for load conditions.
TABLE 15-4: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Symbol
Characteristic
T0CKI High Pulse Width
Min
Typ† Max Units
Conditions
40* Tt0H
41* Tt0L
42* Tt0P
No Prescaler
With Prescaler
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5TCY + 20
10
—
—
—
—
—
—
—
—
—
—
—
—
ns Must also meet
parameter 42
ns
T0CKI Low Pulse Width
T0CKI Period
0.5TCY + 20
10
ns Must also meet
parameter 42
ns
ns
TCY + 40
Greater of:
20 or TCY + 40
N
ns N = prescale value
(2, 4, ..., 256)
45* Tt1H
46* Tt1L
47* Tt1P
T1CKI High Time Synchronous, Prescaler = 1
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns Must also meet
parameter 47
Synchronous,
Standard(F)
15
ns
ns
ns
ns
Prescaler = 2,4,8
Extended(LF)
25
Asynchronous Standard(F)
Extended(LF)
30
50
T1CKI Low Time Synchronous, Prescaler = 1
0.5TCY + 20
ns Must also meet
parameter 47
Synchronous,
Standard(F)
15
25
30
50
ns
ns
ns
ns
Prescaler = 2,4,8
Extended(LF)
Asynchronous Standard(F)
Extended(LF)
T1CKI Input
Period
Synchronous
Standard(F)
Greater of:
30 or TCY + 40
N
ns N = prescale value
(1, 2, 4, 8)
Extended(LF)
Greater of:
50 or TCY + 40
N
N = prescale value
(1, 2, 4, 8)
Asynchronous Standard(F)
Extended(LF)
60
100
DC
—
—
—
—
—
ns
ns
Ft1
Timer1 Oscillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN)
200
kHz
48
TCKEZtmr1 Delay from External Clock Edge to Timer Increment
These parameters are characterized but not tested.
2 TOSC
—
7 TOSC
—
*
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
2002 Microchip Technology Inc.
DS30325B-page 129
PIC16F7X
FIGURE 15-9:
CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
RC1/T1OSI/CCP2
and RC2/CCP1
(Capture Mode)
50
51
52
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
53
54
Note: Refer to Figure 15-3 for load conditions.
TABLE 15-5: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Param
Symbol
Characteristic
Min
Typ† Max Units Conditions
No.
50* TccL
CCP1 and CCP2 No Prescaler
input low time
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Standard(F)
10
With Prescaler
Extended(LF)
20
0.5TCY + 20
10
51* TccH
CCP1 and CCP2 No Prescaler
input high time
Standard(F)
With Prescaler
Extended(LF)
20
52* TccP
53* TccR
CCP1 and CCP2 input period
3TCY + 40
N
ns N = prescale
value (1,4 or 16)
CCP1 and CCP2 output rise time Standard(F)
Extended(LF)
—
—
—
—
10
25
10
25
25
50
25
45
ns
ns
ns
ns
54* TccF
CCP1 and CCP2 output fall time Standard(F)
Extended(LF)
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
DS30325B-page 130
2002 Microchip Technology Inc.
PIC16F7X
FIGURE 15-10:
PARALLEL SLAVE PORT TIMING (PIC16F74/77 DEVICES ONLY)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 15-3 for load conditions.
TABLE 15-6: PARALLEL SLAVE PORT REQUIREMENTS (PIC16F74/77 DEVICES ONLY)
Parameter
Symbol
Characteristic
Min Typ† Max Units
Conditions
No.
62
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)
20
25
—
—
—
—
ns
ns Extended range
only
63*
64
TwrH2dtI WR↑ or CS↑ to data in invalid
Standard(F)
20
—
—
—
—
ns
ns
(hold time)
Extended(LF) 35
TrdL2dtV RD↓ and CS↓ to data out valid
TrdH2dtI RD↑ or CS↓ to data out invalid
—
—
—
—
80
90
ns
ns Extended range
only
65
10
—
30
ns
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
2002 Microchip Technology Inc.
DS30325B-page 131
PIC16F7X
FIGURE 15-11:
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
Bit6 - - - - - -1
Bit6 - - - -1
LSb
SDO
SDI
75, 76
MSb In
74
LSb In
73
Note: Refer to Figure 15-3 for load conditions.
FIGURE 15-12:
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
Bit6 - - - - - -1
Bit6 - - - -1
SDO
SDI
75, 76
MSb In
74
LSb In
Note: Refer to Figure 15-3 for load conditions.
DS30325B-page 132
2002 Microchip Technology Inc.
PIC16F7X
FIGURE 15-13:
SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
LSb
SDO
SDI
Bit6 - - - - - -1
Bit6 - - - -1
77
75, 76
MSb In
74
LSb In
73
Note: Refer to Figure 15-3 for load conditions.
FIGURE 15-14:
SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
Bit6 - - - - - -1
Bit6 - - - -1
LSb
SDO
SDI
75, 76
77
MSb In
74
LSb In
Note: Refer to Figure 15-3 for load conditions.
2002 Microchip Technology Inc.
DS30325B-page 133
PIC16F7X
TABLE 15-7: SPI MODE REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ† Max Units Conditions
70* TssL2scH, SS↓ to SCK↓ or SCK↑ input
TCY
—
—
ns
TssL2scL
71* TscH
72* TscL
SCK input high time (Slave mode)
SCK input low time (Slave mode)
TCY + 20
TCY + 20
100
—
—
—
—
—
—
ns
ns
ns
73* TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
74* TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
—
—
ns
75* TdoR
SDO data output rise time
Standard(F)
Extended(LF)
—
—
10
25
25
50
ns
ns
76* TdoF
SDO data output fall time
—
10
25
50
ns
ns
77* TssH2doZ SS↑ to SDO output hi-impedance
10
—
78* TscR
SCK output rise time
(Master mode)
Standard(F)
Extended(LF)
—
—
10
25
25
50
ns
ns
79* TscF
SCK output fall time (Master mode)
—
10
25
ns
80* TscH2doV, SDO data output valid after
TscL2doV SCK edge
Standard(F)
Extended(LF)
—
—
—
—
50
145
ns
ns
81* TdoV2scH, SDO data output setup to SCK edge
TdoV2scL
Tcy
—
—
ns
82* TssL2doV SDO data output valid after SS↓ edge
—
—
—
50
ns
ns
83* TscH2ssH, SS ↑ after SCK edge
1.5TCY + 40
—
TscL2ssH
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 15-15:
I2C BUS START/STOP BITS TIMING
SCL
SDA
91
93
90
92
STOP
Condition
START
Condition
Note: Refer to Figure 15-3 for load conditions.
DS30325B-page 134
2002 Microchip Technology Inc.
PIC16F7X
TABLE 15-8: I2C BUS START/STOP BITS REQUIREMENTS
Param
Symbol
Characteristic
Min Typ Max Units
Conditions
No.
90*
TSU:STA START condition 100 kHz mode
Setup time 400 kHz mode
THD:STA START condition 100 kHz mode
4700
600
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for Repeated
START condition
91*
92*
93
4000
600
ns After this period, the first clock
pulse is generated
Hold time
TSU:STO STOP condition
Setup time
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
ns
THD:STO STOP condition
Hold time
4000
600
ns
*
These parameters are characterized but not tested.
FIGURE 15-16:
I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 15-3 for load conditions.
2002 Microchip Technology Inc.
DS30325B-page 135
PIC16F7X
TABLE 15-9: I2C BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
100 kHz mode
Min
Max Units
Conditions
100*
THIGH
Clock high time
4.0
—
—
µs
µs
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
Device must operate at a
minimum of 10 MHz
SSP Module
1.5TCY
4.7
—
—
101*
TLOW
Clock low time
100 kHz mode
µs
µs
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
Device must operate at a
minimum of 10 MHz
SSP Module
1.5TCY
—
102*
103*
90*
TR
TF
SDA and SCL rise 100 kHz mode
—
1000
ns
ns
time
400 kHz mode
20 + 0.1CB 300
CB is specified to be from
10 - 400 pF
SDA and SCL fall
time
100 kHz mode
400 kHz mode
—
300
ns
ns
20 + 0.1CB 300
CB is specified to be from
10 - 400 pF
TSU:STA
THD:STA
START condition
setup time
100 kHz mode
400 kHz mode
4.7
0.6
—
—
µs
µs
Only relevant for
Repeated START
condition
91*
106*
107*
92*
START condition
hold time
100 kHz mode
400 kHz mode
4.0
0.6
0
—
—
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
After this period the first
clock pulse is generated
THD:DAT Data input hold time 100 kHz mode
400 kHz mode
—
0
0.9
—
TSU:DAT
TSU:STO
TAA
Data input setup
time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
(Note 2)
—
STOP condition
setup time
—
—
109*
110*
Output valid from
clock
3500
—
(Note 1)
—
TBUF
Bus free time
4.7
1.3
—
Time the bus must be free
before a new transmission
can start
—
CB
Bus capacitive loading
—
400
pF
*
These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the
requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it
must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
Standard mode I2C bus specification), before the SCL line is released.
DS30325B-page 136
2002 Microchip Technology Inc.
PIC16F7X
FIGURE 15-17:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
122
Note: Refer to Figure 15-3 for load conditions.
TABLE 15-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
Symbol
Characteristic
Min Typ† Max Units Conditions
No.
120
TckH2dtV SYNC XMIT (MASTER &
SLAVE)
Standard(F)
—
—
—
—
—
—
—
—
—
—
—
—
80
100
45
ns
ns
ns
ns
ns
ns
Clock high to data out valid
Extended(LF)
121
122
Tckrf
Tdtrf
Clock out rise time and fall Standard(F)
time (Master mode)
Extended(LF)
50
Data out rise time and fall Standard(F)
time
45
Extended(LF)
50
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 15-18:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
125
RC7/RX/DT
pin
126
Note: Refer to Figure 15-3 for load conditions.
TABLE 15-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
Symbol
Characteristic
Min
Typ†
Max
Units Conditions
No.
125
TdtV2ckL SYNC RCV (MASTER & SLAVE)
Data setup before CK↓ (DT setup time)
15
15
—
—
—
—
ns
ns
126
TckL2dtl
Data hold after CK↓ (DT hold time)
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
2002 Microchip Technology Inc.
DS30325B-page 137
PIC16F7X
TABLE 15-12: A/D CONVERTER CHARACTERISTICS: PIC16F7X (INDUSTRIAL, EXTENDED)
PIC16LF7X (INDUSTRIAL)
Param
No.
Sym
Characteristic
Resolution PIC16F7X
Min
Typ†
Max
Units
Conditions
A01 NR
—
—
8 bits
bit VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
PIC16LF7X
A02 EABS Total absolute error
—
—
—
—
8 bits
< ±1
bit VREF = VDD = 2.2V
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A03 EIL
A04 EDL
A05 EFS
A06 EOFF
Integral linearity error
Differential linearity error
Full scale error
—
—
—
—
—
—
< ±1
< ±1
< ±1
< ±1
—
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
—
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
—
—
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
Offset error
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10
—
Monotonicity (Note 3)
guaranteed
—
VSS ≤ VAIN ≤ VREF
A20 VREF
Reference voltage
2.5
2.2
—
—
5.5
5.5
V
V
-40°C to +125°C
0°C to +125°C
A25 VAIN
A30 ZAIN
Analog input voltage
VSS - 0.3
—
—
VREF + 0.3
10.0
V
Recommended impedance of
analog voltage source
—
kΩ
A40 IAD
A/D conversion PIC16F7X
—
—
180
90
—
—
µA Average current
consumption when A/D
is on (Note 1).
current (VDD)
PIC16LF7X
µA
A50 IREF
VREF input current (Note 2)
N/A
—
—
—
±5
500
µA During VAIN acquisition.
µA During A/D Conversion
cycle.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current
spec includes any such leakage from the A/D module.
2: VREF current is from the RA3 pin or the VDD pin, whichever is selected as a reference input.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
DS30325B-page 138
2002 Microchip Technology Inc.
PIC16F7X
FIGURE 15-19:
A/D CONVERSION TIMING
BSF ADCON0, GO
134
1 TCY
(TOSC/2)(1)
131
130
Q4
132
A/D CLK
7
6
5
4
3
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEPinstruction
to be executed.
TABLE 15-13: A/D CONVERSION REQUIREMENTS
Param
Sym
Characteristic
Min
Typ† Max Units
Conditions
No.
130 TAD A/D clock period
PIC16F7X
1.6
2.0
—
—
—
—
µs TOSC based, VREF ≥ 3.0V
PIC16LF7X
µs TOSC based,
2.0V ≤ VREF ≤ 5.5V
PIC16F7X
2.0
3.0
9
4.0
6.0
—
6.0
9.0
9
µs A/D RC mode
µs A/D RC mode
TAD
PIC16LF7X
131 TCNV Conversion time (not including
S/H time) (Note 1)
132 TACQ Acquisition time
5*
—
—
µs The minimum time is the
amplifier settling time. This
may be used if the “new” input
voltage has not changed by
more than 1 LSb (i.e.,
20.0 mV @ 5.12V) from the
last sampled voltage (as
stated on CHOLD).
134 TGO Q4 to A/D clock start
—
TOSC/2
—
—
If the A/D clock source is
selected as RC, a time of TCY
is added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.1 for minimum conditions.
2002 Microchip Technology Inc.
DS30325B-page 139
PIC16F7X
NOTES:
DS30325B-page 140
2002 Microchip Technology Inc.
PIC16F7X
16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein are
not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified oper-
ating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean - 3σ)
respectively, where σ is a standard deviation, over the whole temperature range.
FIGURE 16-1:
TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
6
Typical: statistical mean @ 25°C
5
4
3
2
1
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0
4
6
8
10
12
14
16
18
20
FOSC (M Hz)
FIGURE 16-2:
MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)
8
7
6
5
4
3
2
1
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0
4
6
8
10
12
14
16
18
20
FOSC (M Hz)
2002 Microchip Technology Inc.
DS30325B-page 141
PIC16F7X
FIGURE 16-3:
TYPICAL IDD vs. FOSC OVER VDD (XT MODE)
0.9
Typical: statistical mean @ 25°C
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
FIGURE 16-4:
MAXIMUM IDD vs. FOSC OVER VDD (XT MODE)
1.2
Typical: statistical mean @ 25°C
1.0
0.8
0.6
0.4
0.2
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
DS30325B-page 142
2002 Microchip Technology Inc.
PIC16F7X
FIGURE 16-5:
TYPICAL IDD vs. FOSC OVER VDD (LP MODE)
55
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
50
45
40
35
5.5V
5.0V
4.5V
4.0V
3.5V
30
25
20
3.0V
2.5V
2.0V
15
10
30
40
50
60
70
80
90
100
FOSC (kHz)
FIGURE 16-6:
MAXIMUM IDD vs. FOSC OVER VDD (LP MODE)
100
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
5.5V
5.0V
90
80
70
4.5V
4.0V
60
50
40
30
3.5V
3.0V
2.5V
2.0V
20
30
40
50
60
70
80
90
100
FOSC (kHz)
2002 Microchip Technology Inc.
DS30325B-page 143
PIC16F7X
FIGURE 16-7:
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 20 pF, 25°C)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Operation above 4 MHz is not recomended
10 kΩ
100 kΩ
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-8:
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 100 pF, 25°C)
5.0
Operation above 4 MHz is not recomended
4.0
3.0
2.0
1.0
5.1 kΩ
10 kΩ
100 kΩ
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS30325B-page 144
2002 Microchip Technology Inc.
PIC16F7X
FIGURE 16-9:
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 300 pF, 25°C)
300
250
200
150
100
50
3.3 kΩ
Ω
5.1 k
Ω
10 k
Ω
100 k
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-10:
IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
100
Max 125°C
10
Max 85°C
1
Typ 25°C
0.1
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
0.01
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2002 Microchip Technology Inc.
DS30325B-page 145
PIC16F7X
FIGURE 16-11:
∆IBOR vs. VDD OVER TEMPERATURE
1,000
Max (125˚C)
Typ (25˚C)
Device in
SLEEP
Indeterminant
State
Device in
RESET
100
Note: Device current in RESET
depends on Oscillator mode,
frequency and circuit.
Max (125˚C)
Typ (25˚C)
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
10
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
DD (V)
FIGURE 16-12:
TYPICAL AND MAXIMUM ∆IWDT vs. VDD OVER TEMPERATURE
100
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
Max (125˚C)
Typ (25˚C)
10
1
0.1
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
DD (V)
DS30325B-page 146
2002 Microchip Technology Inc.
PIC16F7X
FIGURE 16-13:
TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40°C TO 125°C)
50
45
40
35
30
25
20
15
10
5
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
Max
(125°C)
Typ
(25°C)
Min
(-40°C)
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-14:
AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40°C TO 125°C)
50
45
40
35
30
25
20
15
10
5
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
125°C
85°C
25°C
-40°C
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2002 Microchip Technology Inc.
DS30325B-page 147
PIC16F7X
FIGURE 16-15:
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40°C TO 125°C)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
Max
Typ (25°C)
Min
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
1.5
1.0
0.5
0.0
0
5
10
15
20
25
IOH (-mA)
FIGURE 16-16:
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40°C TO 125°C)
3.5
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
3.0
2.5
2.0
1.5
1.0
0.5
Max
Typ (25°C)
Min
0.0
0
5
10
15
20
25
IOH (-mA)
DS30325B-page 148
2002 Microchip Technology Inc.
PIC16F7X
FIGURE 16-17:
TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40°C TO 125°C)
1.0
0.9
Max (125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Max (85°C)
Typ (25°C)
Min (-40°C)
0
5
10
15
20
25
IOL (-mA)
FIGURE 16-18:
TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40°C TO 125°C)
3.0
Max (125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
2.5
2.0
1.5
1.0
0.5
0.0
Max (85°C)
Typ (25°C)
Min (-40°C)
0
5
10
15
20
25
IOL (-mA)
2002 Microchip Technology Inc.
DS30325B-page 149
PIC16F7X
FIGURE 16-19:
MINIMUM AND MAXIMUM VIN vs. VDD, (TTL INPUT, -40°C TO 125°C)
1.5
1.4
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
VTH Max (-40°C)
VTH Typ (25°C)
VTH Min (125°C)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-20:
MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40°C TO 125°C)
4.0
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VIH Max (125°C)
VIH Min (-40°C)
VIL Max (-40°C)
VIL Min (125°C)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS30325B-page 150
2002 Microchip Technology Inc.
PIC16F7X
17.0 PACKAGING INFORMATION
17.1 Package Marking Information
28-Lead PDIP (Skinny DIP)
Example
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
PIC16F77-I/SP
YYWWNNN
0210017
28-Lead SOIC
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
PIC16F76-I/SO
0210017
YYWWNNN
28-Lead SSOP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16F73
-I/SS
YYWWNNN
0210017
28-Lead MLF
Example
1
1
XXXXXXXX
XXXXXXXX
PIC16F73
-I/ML
YYWWNNN
0210017
Legend: XX...X Customer specific information*
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
2002 Microchip Technology Inc.
DS30325B-page 151
PIC16F7X
Package Marking Information (Cont’d)
40-Lead PDIP
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
PIC16F77-I/P
0210017
44-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC16F77
-I/PT
0210017
44-Lead PLCC
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC16F77
-I/L
0210017
DS30325B-page 152
2002 Microchip Technology Inc.
PIC16F7X
17.2 Package Details
The following sections give the technical details of the packages.
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
L
A
c
B1
β
A1
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.100
.150
.130
2.54
3.81
3.30
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A
A2
A1
E
.140
.160
3.56
4.06
.125
.015
.300
.275
1.345
.125
.008
.040
.016
.320
.135
3.18
0.38
7.62
6.99
34.16
3.18
0.20
1.02
3.43
.310
.285
1.365
.130
.012
.053
.019
.350
10
.325
.295
1.385
.135
.015
.065
.022
.430
15
7.87
7.24
8.26
7.49
35.18
3.43
0.38
1.65
0.56
10.92
15
E1
D
34.67
3.30
Tip to Seating Plane
Lead Thickness
L
c
0.29
Upper Lead Width
B1
B
1.33
Lower Lead Width
0.41
8.13
5
0.48
8.89
10
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
5
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
2002 Microchip Technology Inc.
DS30325B-page 153
PIC16F7X
28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
E1
p
D
B
2
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
28
28
.050
.099
.091
.008
.407
.295
.704
.020
.033
4
1.27
2.50
2.31
0.20
10.34
7.49
17.87
0.50
0.84
4
Overall Height
A
.093
.104
2.36
2.64
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.288
.695
.010
.016
0
.094
.012
.420
.299
.712
.029
.050
8
2.24
0.10
10.01
7.32
17.65
0.25
0.41
0
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle Top
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.013
.020
15
0.23
0.36
0
0.28
0.42
12
0.33
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
DS30325B-page 154
2002 Microchip Technology Inc.
PIC16F7X
28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
E
E1
p
D
B
2
n
1
α
A
c
A2
A1
φ
L
β
Units
INCHES
NOM
MILLIMETERS*
NOM MAX
Dimension Limits
MIN
MAX
MIN
n
p
Number of Pins
Pitch
28
28
.026
.073
.068
.006
.309
.207
.402
.030
.007
4
0.65
1.85
1.73
0.15
7.85
5.25
10.20
0.75
0.18
101.60
0.32
5
Overall Height
A
.068
.078
1.73
1.98
Molded Package Thickness
Standoff
A2
A1
E
.064
.002
.299
.201
.396
.022
.004
0
.072
.010
.319
.212
.407
.037
.010
8
1.63
0.05
7.59
5.11
10.06
0.56
0.10
0.00
0.25
0
1.83
0.25
8.10
5.38
10.34
0.94
0.25
203.20
0.38
10
§
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
c
Lead Thickness
Foot Angle
φ
Lead Width
B
α
β
.010
0
.013
5
.015
10
Mold Draft Angle Top
Mold Draft Angle Bottom
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-150
Drawing No. C04-073
2002 Microchip Technology Inc.
DS30325B-page 155
PIC16F7X
28-Lead Plastic Micro Leadframe Package (MF) 6x6 mm Body (MLF)
EXPOSED
METAL
E
E1
PADS
Q
D1
D
D2
p
2
1
B
n
R
E2
BOTTOM VIEW
CH x 45
L
TOP VIEW
α
A2
A
A1
A3
Units
Dimension Limits
INCHES
NOM
MILLIMETERS*
NOM
MIN
MAX
MIN
MAX
n
Number of Pins
Pitch
28
28
p
.026 BSC
.033
0.65 BSC
0.85
Overall Height
A
A2
A1
A3
E
.039
1.00
Molded Package Thickness
Standoff
.026
.031
.002
0.65
0.80
0.05
.000
.140
.0004
0.00
0.01
0.20 REF.
Base Thickness
Overall Width
.008 REF.
.236 BSC
.226 BSC
6.00 BSC
5.75 BSC
Molded Package Width
Exposed Pad Width
Overall Length
E1
E2
D
.146
.152
3.55
3.70
3.85
.236 BSC
.226 BSC
6.00 BSC
5.75 BSC
Molded Package Length
Exposed Pad Length
Lead Width
D1
D2
B
.140
.009
.020
.005
.012
.009
.146
.152
.014
.030
.010
.026
.024
12
3.55
0.23
0.50
0.13
0.30
0.24
3.70
3.85
0.35
0.75
0.23
0.65
0.60
12
.011
.024
.007
.016
.017
0.28
0.60
0.17
0.40
0.42
Lead Length
L
Tie Bar Width
R
Tie Bar Length
Q
Chamfer
CH
α
Mold Draft Angle Top
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC equivalent: pending
Drawing No. C04-114
DS30325B-page 156
2002 Microchip Technology Inc.
PIC16F7X
28-Lead Plastic Micro Leadframe Package (MF) 6x6 mm Body (MLF) (Continued)
M
B
L
M
p
PACKAGE
EDGE
SOLDER
MASK
Units
INCHES
NOM
MILLIMETERS*
NOM
Dimension Limits
p
MIN
MAX
MIN
MAX
Pitch
.026 BSC
.011
0.65 BSC
0.28
Pad Width
B
L
.009
.014
0.23
0.35
Pad Length
.020
.005
.024
.030
.006
0.50
0.13
0.60
0.75
0.15
Pad to Solder Mask
M
*Controlling Parameter
Drawing No. C04-2114
2002 Microchip Technology Inc.
DS30325B-page 157
PIC16F7X
40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)
E1
D
2
α
n
1
E
A2
A
L
c
B1
B
β
A1
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
40
MAX
n
p
Number of Pins
Pitch
40
.100
.175
.150
2.54
Top to Seating Plane
A
.160
.190
.160
4.06
3.56
4.45
3.81
4.83
4.06
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.140
.015
.595
.530
2.045
.120
.008
.030
.014
.620
5
0.38
15.11
13.46
51.94
3.05
0.20
0.76
0.36
15.75
5
.600
.545
2.058
.130
.012
.050
.018
.650
10
.625
.560
2.065
.135
.015
.070
.022
.680
15
15.24
13.84
52.26
3.30
0.29
1.27
0.46
16.51
10
15.88
14.22
52.45
3.43
0.38
1.78
0.56
17.27
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
§
eB
α
β
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
5
10
15
5
10
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
DS30325B-page 158
2002 Microchip Technology Inc.
PIC16F7X
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
1
B
n
°
CH x 45
α
A
c
φ
β
A1
A2
L
(F)
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Pins
Pitch
44
.031
11
0.80
11
Pins per Side
Overall Height
n1
A
.039
.037
.002
.018
.043
.039
.004
.024
.039
3.5
.047
1.00
0.95
1.10
1.00
0.10
0.60
1.20
Molded Package Thickness
Standoff
A2
A1
L
(F)
φ
.041
.006
.030
1.05
0.15
0.75
§
0.05
0.45
1.00
0
Foot Length
Footprint (Reference)
Foot Angle
0
.463
.463
.390
.390
.004
.012
.025
5
7
.482
.482
.398
.398
.008
.017
.045
15
3.5
12.00
12.00
10.00
10.00
0.15
0.38
0.89
10
7
12.25
12.25
10.10
10.10
0.20
0.44
1.14
15
Overall Width
E
D
.472
.472
.394
.394
.006
.015
.035
10
11.75
11.75
9.90
9.90
0.09
0.30
0.64
5
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
CH
α
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
2002 Microchip Technology Inc.
DS30325B-page 159
PIC16F7X
44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
E
E1
#leads=n1
D
D1
n 1 2
CH2 x 45°
CH1 x 45°
α
A3
A2
A
35°
B1
B
c
A1
β
p
E2
D2
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Pins
Pitch
44
.050
11
1.27
11
Pins per Side
Overall Height
n1
A
.165
.145
.020
.024
.040
.000
.685
.685
.650
.650
.590
.590
.008
.026
.013
0
.173
.153
.028
.029
.045
.005
.690
.690
.653
.653
.620
.620
.011
.029
.020
5
.180
4.19
3.68
0.51
0.61
1.02
0.00
17.40
17.40
16.51
16.51
14.99
14.99
0.20
0.66
0.33
0
4.39
3.87
0.71
0.74
1.14
0.13
17.53
17.53
16.59
16.59
15.75
15.75
0.27
0.74
0.51
5
4.57
Molded Package Thickness
Standoff
A2
A1
A3
CH1
CH2
E
.160
.035
.034
.050
.010
.695
.695
.656
.656
.630
.630
.013
.032
.021
10
4.06
0.89
0.86
1.27
0.25
17.65
17.65
16.66
16.66
16.00
16.00
0.33
0.81
0.53
10
§
Side 1 Chamfer Height
Corner Chamfer 1
Corner Chamfer (others)
Overall Width
Overall Length
D
Molded Package Width
Molded Package Length
Footprint Width
E1
D1
E2
D2
c
Footprint Length
Lead Thickness
Upper Lead Width
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
B1
B
α
β
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-048
DS30325B-page 160
2002 Microchip Technology Inc.
PIC16F7X
APPENDIX A: REVISION HISTORY
APPENDIX B: DEVICE
DIFFERENCES
Version
Date
Revision Description
The differences between the devices in this data sheet
are listed in Table B-1.
A
2000 This is a new data sheet. How-
ever, these devices are similar to
the PIC16C7X devices found in
the PIC16C7X Data Sheet
(DS30390) or the PIC16F87X
devices (DS30292).
B
2001 Final data sheet. Includes device
characterization data. Addition of
extended temperature devices.
Addition of 28-pin MLF package.
Minor typographic revisions
throughout.
TABLE B-1:
DEVICE DIFFERENCES
Difference
PIC16F73
PIC16F74
PIC16F76
PIC16F77
FLASH Program Memory
(14-bit words)
4K
4K
8K
8K
Data Memory (bytes)
I/O Ports
192
3
192
5
368
3
368
5
A/D
5 channels,
8 bits
8 channels,
8 bits
5 channels,
8 bits
8 channels,
8 bits
Parallel Slave Port
Interrupt Sources
Packages
no
11
yes
12
no
11
yes
12
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin MLF
40-pin PDIP
44-pin TQFP
44-pin PLCC
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin MLF
40-pin PDIP
44-pin TQFP
44-pin PLCC
2002 Microchip Technology Inc.
DS30325B-page 161
PIC16F7X
APPENDIX C: CONVERSION
CONSIDERATIONS
Considerations for converting from previous versions
of devices to the ones listed in this data sheet are listed
in Table C-1.
TABLE C-1:
CONVERSION CONSIDERATIONS
PIC16C7X
Characteristic
PIC16F87X
PIC16F7X
Pins
28/40
3
28/40
3
28/40
3
Timers
Interrupts
Communication
11 or 12
13 or 14
11 or 12
PSP, USART, SSP
(SPI, I2C Slave)
PSP, USART, SSP
PSP, USART, SSP
(SPI, I2C Slave)
(SPI, I2C Master/Slave)
Frequency
A/D
20 MHz
20 MHz
10-bit
2
20 MHz
8-bit
2
8-bit
CCP
2
Program Memory
4K, 8K EPROM
4K, 8K FLASH
4K, 8K FLASH
(1,000 E/W cycles)
(100 E/W cycles typical)
RAM
192, 368 bytes
192, 368 bytes
128, 256 bytes
192, 368 bytes
EEPROM Data
Other
None
—
None
—
In-Circuit Debugger,
Low Voltage Programming
DS30325B-page 162
2002 Microchip Technology Inc.
PIC16F7X
INDEX
PORTD (In I/O Port Mode) ........................................ 36
PORTD and PORTE (Parallel Slave Port) ................ 40
PORTE (In I/O Port Mode) ........................................ 37
PWM Mode ............................................................... 57
RC Oscillator Mode ................................................... 92
Recommended MCLR Circuit ................................... 94
Reset Circuit .............................................................. 93
A
A/D
A/D Conversion Status (GO/DONE Bit) ..................... 83
Acquisition Requirements .......................................... 86
ADCON0 Register ..................................................... 83
ADCON1 Register ..................................................... 83
ADRES Register ........................................................ 83
Analog Port Pins ...................................... 8, 10, 12, 39
Analog-to-Digital Converter ....................................... 83
Associated Registers ................................................. 88
Configuring Analog Port Pins .................................... 87
Configuring the Interrupt ............................................ 85
Configuring the Module ............................................. 85
Conversion Clock ...................................................... 87
Conversion Requirements ....................................... 139
Conversions ............................................................... 87
Converter Characteristics ........................................ 138
Effects of a RESET .................................................... 87
Faster Conversion - Lower Resolution
2
SSP (I C Mode) ........................................................ 65
SSP (SPI Mode) ........................................................ 62
Timer0/WDT Prescaler .............................................. 43
Timer1 ....................................................................... 48
Timer2 ....................................................................... 51
Typical In-Circuit Serial Programming
Connection .............................................. 103
USART
Receive ............................................................. 75
USART Transmit ....................................................... 73
Watchdog Timer (WDT) .......................................... 101
BOR. See Brown-out Reset
BRGH bit ........................................................................... 71
Brown-out Reset (BOR) ..........................89, 93, 94, 95, 96
Trade-off .................................................... 87
Internal Sampling Switch (Rss) Impedance ............... 86
Operation During SLEEP ........................................... 87
Source Impedance .................................................... 86
Using the CCP Trigger .............................................. 88
Absolute Maximum Ratings ............................................. 119
ACK Pulse .................................................................. 65, 66
ADCON0 Register ............................................................. 83
GO/DONE Bit ............................................................ 83
ADCON1 Register ............................................................. 83
ADRES Register ................................................................ 83
Analog Port Pins. See A/D
C
Capture/Compare/PWM (CCP)
Associated Registers ..........................................56, 58
Capture Mode ........................................................... 55
Prescaler ........................................................... 55
CCP Pin Configuration ........................................55, 56
CCP1
RC2/CCP1 Pin ..............................................9, 11
CCP2
RC1/T1OSI/CCP2 Pin ...................................9, 11
Compare Mode ......................................................... 55
Software Interrupt Mode .................................... 56
Special Trigger Output ...................................... 56
Timer1 Mode Selection ..................................... 56
Example PWM Frequencies and Resolutions ........... 58
Interaction of Two CCP Modules .............................. 53
PWM Duty Cycle ....................................................... 57
PWM Mode ............................................................... 57
PWM Period .............................................................. 57
Setup for PWM Operation ......................................... 58
Special Event Trigger and A/D Conversions ............. 56
Timer Resources ....................................................... 53
CCP1 Module .................................................................... 53
CCP2 Module .................................................................... 53
CCPR1H Register ............................................................. 53
CCPR1L Register .............................................................. 53
CCPxM<3:0> bits .............................................................. 54
CCPxX and CCPxY bits .................................................... 54
CKE bit .............................................................................. 60
CKP bit .............................................................................. 61
Code Examples
Application Notes
AN552 (Implementing Wake-up on Key Strokes
Using PIC16F7X) ...................................... 33
AN556 (Implementing a Table Read) ........................ 26
2
AN578 (Use of the SSP Module in the I C
Multi-Master Environment) ........................ 59
AN607 (Power-up Trouble Shooting) ........................ 94
Assembler
MPASM Assembler ................................................. 113
B
Banking, Data Memory ...................................................... 13
BF bit ................................................................................. 60
Block Diagrams
A/D ............................................................................. 85
Analog Input Model .................................................... 86
Capture Mode Operation ........................................... 55
Compare .................................................................... 55
Crystal/Ceramic Resonator Operation (HS, XT
or LP Osc Configuration) ........................... 91
External Clock Input Operation
(HS Osc Configuration) ............................. 91
Interrupt Logic ............................................................ 99
PIC16F73 and PIC16F76 ............................................ 6
PIC16F74 and PIC16F77 ............................................ 7
PORTA
RA3:RA0 and RA5 Port Pins ............................. 31
RA4/T0CKI Pin .................................................. 31
PORTB
RB3:RB0 Port Pins ............................................ 33
RB7:RB4 Port Pins ............................................ 33
PORTC (Peripheral Output Override) ........................ 35
Call of a Subroutine in Page 1 from Page 0 .............. 26
Changing Between Capture Prescalers .................... 55
Changing Prescaler Assignment to Timer0 ............... 45
Changing Prescaler Assignment to WDT .................. 45
FLASH Program Read .............................................. 30
Indirect Addressing ................................................... 27
Initializing PORTA ..................................................... 31
Reading a 16-bit Free-Running Timer ....................... 49
Saving STATUS, W, and PCLATH Registers
in RAM .................................................... 100
Writing a 16-bit Free-Running Timer ......................... 49
2002 Microchip Technology Inc.
DS30325B-page 163
PIC16F7X
Code Protection ........................................................ 89, 103
Computed GOTO ...............................................................26
Configuration Bits ..............................................................89
Continuous Receive Enable (CREN Bit) ............................70
Conversion Considerations ..............................................162
CLRWDT ................................................................. 108
COMF ...................................................................... 108
DECF ....................................................................... 108
DECFSZ .................................................................. 109
GOTO ...................................................................... 109
INCF ........................................................................ 109
INCFSZ ................................................................... 109
IORLW ..................................................................... 109
IORWF .................................................................... 109
MOVF ...................................................................... 110
MOVLW ................................................................... 110
MOVWF ................................................................... 110
NOP ......................................................................... 110
RETFIE .................................................................... 110
RETLW .................................................................... 110
RETURN ................................................................. 111
RLF .......................................................................... 111
RRF ......................................................................... 111
SLEEP ..................................................................... 111
SUBLW .................................................................... 111
SUBWF ................................................................... 111
SWAPF .................................................................... 112
XORLW ................................................................... 112
XORWF ................................................................... 112
Summary Table ....................................................... 106
INT Interrupt (RB0/INT). See Interrupt Sources
D
D/A bit ................................................................................60
Data Memory .....................................................................13
Bank Select (RP1:RP0 bits) .......................................13
General Purpose Registers .......................................13
Register File Map, PIC16F74/73 ...............................15
Register File Map, PIC16F77/76 ...............................14
Special Function Registers ........................................16
Data/Address bit (D/A) .......................................................60
DC and AC Characteristics
Graphs and Tables ..................................................141
DC Characteristics ...........................................................121
Development Support ......................................................113
Device Differences ...........................................................161
Device Overview ..................................................................5
Features .......................................................................5
Direct Addressing ..............................................................27
E
Electrical Characteristics .................................................119
Errata ...................................................................................4
External Clock Input (RA4/T0CKI). See Timer0
INTCON Register .............................................................. 21
GIE bit ....................................................................... 21
INTE bit ..................................................................... 21
INTF bit ...................................................................... 21
RBIF bit ...............................................................21, 33
TMR0IE bit ................................................................ 21
External Interrupt Input (RB0/INT). See Interrupt Sources
F
Firmware Instructions ......................................................105
FSR Register .....................................................................27
2
2
Inter-Integrated Circuit (I C). See I C Mode
Interrupt Sources .........................................................89, 99
Interrupt-on-Change (RB7:RB4) ................................ 33
RB0/INT Pin, External ..................................9, 11, 100
TMR0 Overflow ....................................................... 100
USART Receive/Transmit Complete ......................... 69
Interrupts
I
I/O Ports .............................................................................31
2
I C Mode
Addressing .................................................................66
Associated Registers .................................................68
Master Mode ..............................................................68
Mode Selection ..........................................................65
Multi-Master Mode .....................................................68
Operation ...................................................................65
Reception ...................................................................66
Slave Mode
Synchronous Serial Port Interrupt ............................. 23
Interrupts, Context Saving During ................................... 100
Interrupts, Enable bits
Global Interrupt Enable (GIE bit) .........................21, 99
Interrupt-on-Change (RB7:RB4) Enable (RBIE bit) . 100
RB0/INT Enable (INTE bit) ........................................ 21
TMR0 Overflow Enable (TMR0IE bit) ........................ 21
Interrupts, Flag bits
SCL and SDA pins .............................................65
Transmission .............................................................67
ICEPIC In-Circuit Emulator ..............................................114
ID Locations .....................................................................103
In-Circuit Serial Programming (ICSP) ..............................103
INDF Register ....................................................................27
Indirect Addressing ............................................................27
FSR Register .............................................................13
Instruction Format ............................................................105
Instruction Set ..................................................................105
ADDLW ....................................................................107
ADDWF ....................................................................107
ANDLW ....................................................................107
ANDWF ....................................................................107
BCF ..........................................................................107
BSF ..........................................................................107
BTFSC .....................................................................107
BTFSS .....................................................................107
CALL ........................................................................108
CLRF .......................................................................108
CLRW ......................................................................108
Interrupt-on Change (RB7:RB4) Flag
(RBIF bit) ................................................... 21
Interrupt-on-Change (RB7:RB4) Flag
(RBIF bit) ....................................21, 33, 100
RB0/INT Flag (INTF bit) ............................................ 21
TMR0 Overflow Flag (TMR0IF bit) .......................... 100
K
KEELOQ Evaluation and Programming Tools ................... 116
L
Load Conditions .............................................................. 125
Loading of PC .................................................................... 26
DS30325B-page 164
2002 Microchip Technology Inc.
PIC16F7X
PICSTART Plus Entry Level
M
Development Programmer ...................................... 115
PIE1 Register .................................................................... 22
PIE2 Register .................................................................... 24
Pinout Descriptions
PIC16F73/PIC16F76 ...............................................8–9
PIC16F74/PIC16F77 ...........................................10–12
PIR1 Register .................................................................... 23
PIR2 Register .................................................................... 24
PMADR Register ............................................................... 29
PMADRH Register ............................................................ 29
POP ................................................................................... 26
POR. See Power-on Reset
PORTA ..........................................................................8, 10
Analog Port Pins ...................................................8, 10
Associated Registers ................................................ 32
PORTA Register ....................................................... 31
RA4/T0CKI Pin ......................................................8, 10
RA5/SS/AN4 Pin ...................................................8, 10
TRISA Register ......................................................... 31
PORTA Register ................................................................ 31
PORTB ..........................................................................9, 11
Associated Registers ................................................ 34
PORTB Register ....................................................... 33
Pull-up Enable (RBPU bit) ......................................... 20
RB0/INT Edge Select (INTEDG bit) .......................... 20
RB0/INT Pin, External .................................. 9, 11, 100
RB7:RB4 Interrupt-on-Change ................................ 100
RB7:RB4 Interrupt-on-Change Enable
Master Clear (MCLR) .................................................... 8, 10
MCLR Reset, Normal Operation ...................93, 95, 96
MCLR Reset, SLEEP ...................................93, 95, 96
Operation and ESD Protection .................................. 94
MCLR/VPP Pin ..................................................................... 8
MCLR/VPP Pin ................................................................... 10
Memory Organization ........................................................ 13
Data Memory ............................................................. 13
Program Memory ....................................................... 13
Program Memory and Stack Maps ............................ 13
MPLAB C17 and MPLAB C18 C Compilers .................... 113
MPLAB ICD In-Circuit Debugger ..................................... 115
MPLAB ICE High Performance Universal In-Circuit
Emulator with MPLAB IDE ....................................... 114
MPLAB Integrated Development
Environment Software ............................................. 113
MPLINK Object Linker/MPLIB Object Librarian ............... 114
O
OPCODE Field Descriptions ............................................ 105
OPTION_REG Register ..................................................... 20
INTEDG bit ................................................................ 20
PS2:PS0 bits ............................................................. 20
PSA bit ....................................................................... 20
RBPU bit .................................................................... 20
T0CS bit ..................................................................... 20
T0SE bit ..................................................................... 20
OSC1/CLKI Pin ............................................................. 8, 10
OSC2/CLKO Pin ........................................................... 8, 10
Oscillator Configuration ..................................................... 89
Oscillator Configurations .................................................... 91
Crystal Oscillator/Ceramic Resonators ...................... 91
HS ....................................................................... 91, 95
LP ....................................................................... 91, 95
RC ................................................................91, 92, 95
XT ....................................................................... 91, 95
Oscillator, WDT ................................................................ 101
(RBIE bit) ................................................ 100
RB7:RB4 Interrupt-on-Change Flag
(RBIF bit) .................................... 21, 33, 100
TRISB Register ......................................................... 33
PORTB Register ................................................................ 33
PORTC ..........................................................................9, 11
Associated Registers ................................................ 35
PORTC Register ....................................................... 35
RC0/T1OSO/T1CKI Pin ........................................9, 11
RC1/T1OSI/CCP2 Pin ...........................................9, 11
RC2/CCP1 Pin ......................................................9, 11
RC3/SCK/SCL Pin ................................................9, 11
RC4/SDI/SDA Pin .................................................9, 11
RC5/SDO Pin ........................................................9, 11
RC6/TX/CK Pin .............................................. 9, 11, 70
RC7/RX/DT Pin ....................................... 9, 11, 70, 71
TRISC Register ......................................................... 35
PORTC Register ............................................................... 35
PORTD .............................................................................. 12
Associated Registers ................................................ 36
Parallel Slave Port (PSP) Function ........................... 36
PORTD Register ....................................................... 36
TRISD Register ......................................................... 36
PORTD Register ............................................................... 36
PORTE .............................................................................. 12
Analog Port Pins .................................................12, 39
Associated Registers ................................................ 39
Input Buffer Full Status (IBF bit) ................................ 38
Input Buffer Overflow (IBOV bit) ................................ 38
PORTE Register ....................................................... 37
PSP Mode Select (PSPMODE bit) ......................36, 37
RE0/RD/AN5 Pin .................................................12, 39
RE1/WR/AN6 Pin ................................................12, 39
RE2/CS/AN7 Pin .................................................12, 39
TRISE Register ......................................................... 37
P
P (STOP) bit ...................................................................... 60
Packaging ........................................................................ 151
Paging, Program Memory .................................................. 26
Parallel Slave Port
Associated Registers ................................................. 41
Parallel Slave Port (PSP) ............................................ 36, 40
RE0/RD/AN5 Pin ................................................ 12, 39
RE1/WR/AN6 Pin ............................................... 12, 39
RE2/CS/AN7 Pin ................................................ 12, 39
Select (PSPMODE bit) ....................................... 36, 37
PCFG0 bit .......................................................................... 84
PCFG1 bit .......................................................................... 84
PCFG2 bit .......................................................................... 84
PCL Register ..................................................................... 26
PCLATH Register .............................................................. 26
PCON Register ........................................................... 25, 95
POR Bit ...................................................................... 25
PICDEM 1 Low Cost PICmicro
Demonstration Board ............................................... 115
PICDEM 17 Demonstration Board ................................... 116
PICDEM 2 Low Cost PIC16CXX
Demonstration Board ............................................... 115
PICDEM 3 Low Cost PIC16CXXX
Demonstration Board ............................................... 116
2002 Microchip Technology Inc.
DS30325B-page 165
PIC16F7X
PORTE Register ................................................................37
Postscaler, WDT
RCSTA Register
CREN bit ................................................................... 70
Assignment (PSA bit) .................................................20
Rate Select (PS2:PS0 bits) ........................................20
Power-down Mode. See SLEEP
OERR bit ................................................................... 70
SPEN bit .................................................................... 69
SREN bit .................................................................... 70
RD0/PSP0 Pin ................................................................... 12
RD1/PSP1 Pin ................................................................... 12
RD2/PSP2 Pin ................................................................... 12
RD3/PSP3 Pin ................................................................... 12
RD4/PSP4 Pin ................................................................... 12
RD5/PSP5 Pin ................................................................... 12
RD6/PSP6 Pin ................................................................... 12
RD7/PSP7 Pin ................................................................... 12
RE0/RD/AN5 Pin ............................................................... 12
RE1/WR/AN6 Pin .............................................................. 12
RE2/CS/AN7 Pin ............................................................... 12
Read-Modify-Write Operations ........................................ 105
Receive Overflow Indicator bit (SSPOV) ........................... 61
Register File ...................................................................... 13
Registers
Power-on Reset (POR) ..................................89, 93, 95, 96
Oscillator Start-up Timer (OST) .......................... 89, 94
POR Status (POR bit) ................................................25
Power Control (PCON) Register ................................95
Power-down (PD bit) ..................................................93
Power-up Timer (PWRT) .................................... 89, 94
Time-out (TO bit) ................................................ 19, 93
PR2 Register .....................................................................51
Prescaler, Timer0
Assignment (PSA bit) .................................................20
Rate Select (PS2:PS0 bits) ........................................20
PRO MATE II Universal Device Programmer ..................115
Program Counter
RESET Conditions .....................................................95
Program Memory ...............................................................29
Associated Registers .................................................30
Interrupt Vector ..........................................................13
Memory and Stack Maps ...........................................13
Operation During Code Protect .................................30
Organization ..............................................................13
Paging ........................................................................26
PMADR Register .......................................................29
PMADRH Register .....................................................29
Reading FLASH .........................................................30
Reading, PMADR Register ........................................29
Reading, PMADRH Register .....................................29
Reading, PMCON1 Register ......................................29
Reading, PMDATA Register ......................................29
Reading, PMDATH Register ......................................29
RESET Vector ...........................................................13
Program Verification ........................................................103
Programming Pin (VPP) ................................................ 8, 10
Programming, Device Instructions ...................................105
PUSH .................................................................................26
ADCON0 (A/D Control 0) .......................................... 83
ADCON0 (A/D Control 0) Register ............................ 83
ADCON1 (A/D Control 1) .......................................... 83
ADCON1 (A/D Control 1) Register ............................ 84
ADRES (A/D Result) ................................................. 83
CCP1CON/CCP2CON (CCP Control) Registers ...... 54
Configuration Word Register ..................................... 90
Initialization Conditions (table) ............................96–97
INTCON (Interrupt Control) ....................................... 21
INTCON (Interrupt Control) Register ......................... 21
OPTION_REG ........................................................... 20
OPTION_REG Register ......................................20, 44
PCON (Power Control) .............................................. 25
PCON (Power Control) Register ............................... 25
PIE1 (Peripheral Interrupt Enable 1) ......................... 22
PIE1 (Peripheral Interrupt Enable 1) Register ........... 22
PIE2 (Peripheral Interrupt Enable 2) ......................... 24
PIE2 (Peripheral Interrupt Enable 2) Register ........... 24
PIR1 (Peripheral Interrupt Request 1) ....................... 23
PIR1 (Peripheral Interrupt Request 1) Register ........ 23
PIR2 (Peripheral Interrupt Request 2) ....................... 24
PIR2 (Peripheral Interrupt Request 2) Register ........ 24
PMCON1 (Program Memory Control 1)
R
R/W bit ..................................................................60, 66, 67
RA0/AN0 Pin ................................................................. 8, 10
RA1/AN1 Pin ................................................................. 8, 10
RA2/AN2 Pin ................................................................. 8, 10
RA3/AN3/VREF Pin ....................................................... 8, 10
RA4/T0CKI Pin ............................................................. 8, 10
RA5/SS/AN4 Pin ........................................................... 8, 10
RAM. See Data Memory
RB0/INT Pin .................................................................. 9, 11
RB1 Pin ......................................................................... 9, 11
RB2 Pin ......................................................................... 9, 11
RB3/PGM Pin ............................................................... 9, 11
RB4 Pin ......................................................................... 9, 11
RB5 Pin ......................................................................... 9, 11
RB6/PGC Pin ................................................................ 9, 11
RB7/PGD Pin ................................................................ 9, 11
RC0/T1OSO/T1CKI Pin ................................................ 9, 11
RC1/T1OSI/CCP2 Pin .................................................. 9, 11
RC2/CCP1 Pin .............................................................. 9, 11
RC3/SCK/SCL Pin ........................................................ 9, 11
RC4/SDI/SDA Pin ......................................................... 9, 11
RC5/SDO Pin ................................................................ 9, 11
RC6/TX/CK Pin ............................................................. 9, 11
RC7/RX/DT Pin ............................................................. 9, 11
Register ..................................................... 29
RCSTA (Receive Status and Control) Register ......... 70
Special Function, Summary ................................16–18
SSPCON (Sync Serial Port Control) Register ........... 61
SSPSTAT (Sync Serial Port Status) Register ........... 60
STATUS Register ...................................................... 19
T1CON (Timer 1 Control) Register ............................ 47
T2CON (Timer2 Control) Register ............................. 52
TRISE Register ......................................................... 38
TXSTA (Transmit Status and Control) Register ........ 69
RESET ........................................................................89, 93
Brown-out Reset (BOR). See Brown-out Reset (BOR)
MCLR Reset. See MCLR
Power-on Reset (POR). See Power-on Reset (POR)
RESET Conditions for All Registers .......................... 96
RESET Conditions for PCON Register ..................... 95
RESET Conditions for Program Counter ................... 95
RESET Conditions for STATUS Register .................. 95
RESET
WDT Reset. See Watchdog Timer (WDT)
Revision History .............................................................. 161
DS30325B-page 166
2002 Microchip Technology Inc.
PIC16F7X
Timer1 ............................................................................... 47
Associated Registers ................................................ 50
Asynchronous Counter Mode .................................... 49
Capacitor Selection ................................................... 50
Counter Operation ..................................................... 48
Operation in Timer Mode .......................................... 48
Oscillator ................................................................... 50
Prescaler ................................................................... 50
RC0/T1OSO/T1CKI Pin ........................................9, 11
RC1/T1OSI/CCP2 Pin ...........................................9, 11
Resetting of Timer1 Registers ................................... 50
Resetting Timer1 using a CCP Trigger Output ......... 50
Synchronized Counter Mode ..................................... 48
TMR1H Register ....................................................... 49
TMR1L Register ........................................................ 49
Timer2 ............................................................................... 51
Associated Registers ................................................ 52
Output ....................................................................... 51
Postscaler ................................................................. 51
Prescaler ................................................................... 51
Prescaler and Postscaler .......................................... 51
Timing Diagrams
S
S (START) bit .................................................................... 60
SCI. See USART
SCL .................................................................................... 65
Serial Communication Interface. See USART
SLEEP ................................................................89, 93, 102
SMP bit .............................................................................. 60
Software Simulator (MPLAB SIM) ................................... 114
Special Features of the CPU ............................................. 89
Special Function Registers ...................................16, 16–18
Speed, Operating ................................................................. 1
SPI Mode ........................................................................... 59
Associated Registers ................................................. 64
Serial Clock (SCK pin) ............................................... 59
Serial Data In (SDI pin) .............................................. 59
Serial Data Out (SDO pin) ......................................... 59
Slave Select ............................................................... 59
SSP
Overview
RA5/SS/AN4 Pin ................................................... 8, 10
RC3/SCK/SCL Pin ................................................ 9, 11
RC4/SDI/SDA Pin ................................................. 9, 11
RC5/SDO Pin ....................................................... 9, 11
A/D Conversion ....................................................... 139
Brown-out Reset ..................................................... 128
Capture/Compare/PWM (CCP1 and CCP2) ........... 130
CLKOUT and I/O ..................................................... 127
External Clock ......................................................... 126
2
SSP I C Operation ............................................................. 65
Slave Mode ................................................................ 65
SSPEN bit .......................................................................... 61
SSPIF bit ............................................................................ 23
SSPM<3:0> bits ................................................................. 61
SSPOV bit .......................................................................... 61
Stack .................................................................................. 26
Overflows ................................................................... 26
Underflow .................................................................. 26
STATUS Register
DC Bit ........................................................................ 19
IRP Bit ....................................................................... 19
PD Bit ........................................................................ 93
TO Bit ................................................................. 19, 93
Z Bit ........................................................................... 19
Synchronous Serial Port Enable bit (SSPEN) ................... 61
Synchronous Serial Port Interrupt bit (SSPIF) ................... 23
Synchronous Serial Port Mode Select bits
2
I C Bus Data ........................................................... 135
2
I C Bus START/STOP bits ...................................... 134
2
I C Reception (7-bit Address) ................................... 67
2
I C Transmission (7-bit Address) .............................. 67
Parallel Slave Port ................................................... 131
Parallel Slave Port Read Waveforms ........................ 41
Parallel Slave Port Write Waveforms ........................ 41
Power-up Timer ....................................................... 128
PWM Output .............................................................. 57
RESET .................................................................... 128
Slow Rise Time (MCLR Tied to VDD Through
RC Network) ............................................. 98
SPI Master Mode (CKE = 0, SMP = 0) .................... 132
SPI Master Mode (CKE = 1, SMP = 1) .................... 132
SPI Mode (Master Mode) .......................................... 63
SPI Mode (Slave Mode with CKE = 0) ...................... 63
SPI Mode (Slave Mode with CKE = 1) ...................... 63
SPI Slave Mode (CKE = 0) ...................................... 133
SPI Slave Mode (CKE = 1) ...................................... 133
Start-up Timer ......................................................... 128
Time-out Sequence on Power-up (MCLR Not
(SSPM<3:0>) ............................................................. 61
Synchronous Serial Port. See SSP
T
T1CKPS0 bit ...................................................................... 47
T1CKPS1 bit ...................................................................... 47
T1OSCEN bit ..................................................................... 47
T1SYNC bit ........................................................................ 47
T2CKPS0 bit ...................................................................... 52
T2CKPS1 bit ...................................................................... 52
TAD ..................................................................................... 87
Time-out Sequence ........................................................... 94
Timer0 ................................................................................ 43
Associated Registers ................................................. 45
Clock Source Edge Select (T0SE bit) ........................ 20
Clock Source Select (T0CS bit) ................................. 20
External Clock ........................................................... 44
Interrupt ..................................................................... 43
Overflow Enable (TMR0IE bit) ................................... 21
Overflow Flag (TMR0IF bit) ..................................... 100
Overflow Interrupt .................................................... 100
Prescaler ................................................................... 45
RA4/T0CKI Pin, External Clock ............................ 8, 10
T0CKI ........................................................................ 44
Tied to VDD)
Case 1 ............................................................... 98
Case 2 ............................................................... 98
Time-out Sequence on Power-up (MCLR Tied to Vdd
Through RC Network) ............................... 97
Timer0 ..................................................................... 129
Timer1 ..................................................................... 129
USART Asynchronous Master Transmission ............ 74
USART Asynchronous Master Transmission
(Back to Back) ........................................... 74
USART Asynchronous Reception ............................. 76
USART Synchronous Receive (Master/Slave) ........ 137
USART Synchronous Reception
(Master Mode, SREN) ............................... 79
USART Synchronous Transmission .......................... 78
USART Synchronous Transmission
(Master/Slave) ......................................... 137
2002 Microchip Technology Inc.
DS30325B-page 167
PIC16F7X
USART Synchronous Transmission
Baud Rate Generator (BRG) ..................................... 71
Baud Rate Formula ........................................... 71
Baud Rates, Asynchronous Mode
(Through TXEN) ........................................78
Wake-up from SLEEP via Interrupt ..........................103
Watchdog Timer ......................................................128
Timing Parameter Symbology .........................................125
Timing Requirements
(BRGH = 0) ....................................... 72
Baud Rates, Asynchronous Mode
(BRGH = 1) ....................................... 72
Capture/Compare/PWM (CCP1 and CCP2) ............130
CLKOUT and I/O .....................................................127
External Clock ..........................................................126
Sampling ........................................................... 71
Mode Select (SYNC Bit) ............................................ 69
Overrun Error (OERR Bit) ......................................... 70
RC6/TX/CK Pin .....................................................9, 11
RC7/RX/DT Pin .....................................................9, 11
Serial Port Enable (SPEN Bit) ................................... 69
Single Receive Enable (SREN Bit) ............................ 70
Synchronous Master Mode ....................................... 77
Synchronous Master Reception ................................ 79
Associated Registers ........................................ 80
Synchronous Master Transmission ........................... 77
Associated Registers ........................................ 78
Synchronous Slave Mode ......................................... 80
Synchronous Slave Reception .................................. 81
Associated Registers ........................................ 81
Synchronous Slave Transmission ............................. 80
Associated Registers ........................................ 81
Transmit Data, 9th Bit (TX9D) ................................... 69
Transmit Enable (TXEN bit) ...................................... 69
Transmit Enable, Nine-bit (TX9 bit) ........................... 69
Transmit Shift Register Status (TRMT bit) ................ 69
2
I C Bus Data ............................................................136
I2C Bus START/STOP Bits .....................................135
Parallel Slave Port ...................................................131
RESET, Watchdog Timer, Oscillator
Start-up Timer, Power-up Timer
and Brown-out Reset ...............................128
SPI Mode .................................................................134
Timer0 and Timer1 External Clock ..........................129
USART Synchronous Receive .................................137
USART Synchronous Transmission ........................137
TMR1CS bit .......................................................................47
TMR1ON bit .......................................................................47
TMR2ON bit .......................................................................52
TOUTPS<3:0> bits ............................................................52
TRISA Register ..................................................................31
TRISB Register ..................................................................33
TRISC Register ..................................................................35
TRISD Register ..................................................................36
TRISE Register ..................................................................37
IBF Bit ........................................................................38
IBOV Bit .....................................................................38
PSPMODE bit ..................................................... 36, 37
TXSTA Register
W
Wake-up from SLEEP ...............................................89, 102
Interrupts .............................................................95, 96
MCLR Reset .............................................................. 96
WDT Reset ................................................................ 96
Wake-up Using Interrupts ................................................ 102
Watchdog Timer (WDT) ............................................89, 101
Associated Registers ............................................... 101
Enable (WDTE Bit) .................................................. 101
Postscaler. See Postscaler, WDT
Programming Considerations .................................. 101
RC Oscillator ........................................................... 101
Time-out Period ....................................................... 101
WDT Reset, Normal Operation ....................93, 95, 96
WDT Reset, SLEEP .....................................93, 95, 96
WCOL bit ........................................................................... 61
Write Collision Detect bit (WCOL) ..................................... 61
WWW, On-Line Support ...................................................... 4
SYNC bit ....................................................................69
TRMT bit ....................................................................69
TX9 bit .......................................................................69
TX9D bit .....................................................................69
TXEN bit ....................................................................69
U
UA ......................................................................................60
Universal Synchronous Asynchronous
Receiver Transmitter. See USART
Update Address bit, UA .....................................................60
USART ...............................................................................69
Asynchronous Mode ..................................................73
Asynchronous Receiver .............................................75
Asynchronous Reception ...........................................76
Associated Registers .........................................76
Asynchronous Transmission
Associated Registers .........................................74
Asynchronous Transmitter .........................................73
DS30325B-page 168
2002 Microchip Technology Inc.
PIC16F7X
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2002 Microchip Technology Inc.
DS30325B-page 169
PIC16F7X
READER RESPONSE
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DS30325B-page 170
2002 Microchip Technology Inc.
PIC16F7X
PIC16F7X PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature Package
Range
Pattern
a)
b)
c)
PIC16F77-I/P 301 = Industrial temp., PDIP
package, normal VDD limits, QTP pattern #301.
PIC16LF76-I/SO = Industrial temp., SOIC
package, Extended VDD limits.
PIC16F74-E/P = Extended temp., PDIP
package, normal VDD limits.
Device
PIC16F7X(1), PIC16F7XT(1); VDD range 4.0V to 5.5V
PIC16LF7X(1), PIC16LF7XT(1); VDD range 2.0V to 5.5V
Temperature Range
Package
I
E
=
=
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
Note 1:
2:
F
= CMOS FLASH
LF = Low Power CMOS FLASH
ML
PT
SO
SP
P
L
SS
=
=
=
=
=
=
=
MLF (Micro Lead Frame)
TQFP (Thin Quad Flatpack)
T
= in tape and reel - SOIC, PLCC,
SSOP, TQFP packages only.
SOIC
Skinny Plastic DIP
PDIP
PLCC
SSOP
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
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DS30325B-page 171
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Web Address: http://www.microchip.com
Australia
Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Korea
Rocky Mountain
China - Beijing
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966 Fax: 480-792-7456
Microchip Technology Consulting (Shanghai)
Co., Ltd., Beijing Liaison Office
Unit 915
Bei Hai Wan Tai Bldg.
Atlanta
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 82-2-554-7200 Fax: 82-2-558-5934
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100 Fax: 86-10-85282104
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-334-8870 Fax: 65-334-8850
Taiwan
Microchip Technology Taiwan
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 770-640-0034 Fax: 770-640-0307
China - Chengdu
Boston
Microchip Technology Consulting (Shanghai)
Co., Ltd., Chengdu Liaison Office
Rm. 2401, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Chengdu 610016, China
Tel: 86-28-6766200 Fax: 86-28-6766599
China - Fuzhou
Microchip Technology Consulting (Shanghai)
Co., Ltd., Fuzhou Liaison Office
Unit 28F, World Trade Plaza
No. 71 Wusi Road
Fuzhou 350001, China
Tel: 86-591-7503506 Fax: 86-591-7503521
China - Shanghai
Microchip Technology Consulting (Shanghai)
Co., Ltd.
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
China - Shenzhen
Microchip Technology Consulting (Shanghai)
Co., Ltd., Shenzhen Liaison Office
Rm. 1315, 13/F, Shenzhen Kerry Centre,
Renminnan Lu
Shenzhen 518001, China
Tel: 86-755-2350361 Fax: 86-755-2366086
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3848 Fax: 978-692-3821
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818-7423 Fax: 972-818-2924
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Denmark
Microchip Technology Nordic ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Kokomo
France
2767 S. Albright Road
Kokomo, Indiana 46902
Tel: 765-864-8360 Fax: 765-864-8387
Los Angeles
Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
Germany
New York
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Microchip Technology GmbH
Gustav-Heinemann Ring 125
D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Tel: 631-273-5305 Fax: 631-273-5335
San Jose
Hong Kong
Italy
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Microchip Technology Hongkong Ltd.
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699 Fax: 905-673-6509
India
Microchip Technology Inc.
India Liaison Office
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
01/18/02
DS30325B-page 172
2002 Microchip Technology Inc.
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