PIC16F87X-10EPQ [MICROCHIP]
28/40-Pin 8-Bit CMOS FLASH Microcontrollers; 40分之28引脚8位CMOS闪存微控制器
| 型号： | PIC16F87X-10EPQ |
| 厂家： | 
MICROCHIP |
| 描述： | 28/40-Pin 8-Bit CMOS FLASH Microcontrollers |
| 文件： | 总218页 (文件大小：2308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC16F87X
28/40-Pin 8-Bit CMOS FLASH Microcontrollers
Devices Included in this Data Sheet:
Pin Diagram
PDIP
• PIC16F873
• PIC16F874
• PIC16F876
• PIC16F877
MCLR/VPP
RA0/AN0
1
40
39
38
37
36
35
34
33
32
31
30
29
28
RB7/PGD
RB6/PGC
2
Microcontroller Core Features:
RA1/AN1
RA2/AN2/VREF-
3
RB5
4
RB4
• High performance RISC CPU
RA3/AN3/VREF+
RA4/T0CKI
RB3/PGM
RB2
5
6
• Only 35 single word instructions to learn
RA5/AN4/SS
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
7
RB1
• All single cycle instructions except for program
branches which are two cycle
8
RB0/INT
VDD
9
10
11
12
13
14
15
16
17
18
19
20
VSS
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
RD7/PSP7
RD6/PSP6
RD5/PSP5
VSS
• Up to 8K x 14 words of FLASH Program Memory,
Up to 368 x 8 bytes of Data Memory (RAM)
Up to 256 x 8 bytes of EEPROM Data Memory
OSC1/CLKIN
OSC2/CLKOUT
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
27
26
25
24
23
22
21
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
• Pinout compatible to the PIC16C73B/74B/76/77
• Interrupt capability (up to 14 sources)
• Eight level deep hardware stack
RC3/SCK/SCL
RD0/PSP0
RC4/SDI/SDA
RD3/PSP3
RD1/PSP1
RD2/PSP2
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
Peripheral Features:
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during SLEEP via external
crystal/clock
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Low power, high speed CMOS FLASH/EEPROM
technology
• Two Capture, Compare, PWM modules
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• Fully static design
• In-Circuit Serial Programming(ICSP)via two
pins
• Single 5V In-Circuit Serial Programming capability
• In-Circuit Debugging via two pins
• 10-bit multi-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with SPI (Master
mode) and I2C(Master/Slave)
• Processor read/write access to program memory
• Wide operating voltage range: 2.0V to 5.5V
• High Sink/Source Current: 25 mA
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI) with 9-bit address
detection
• Commercial, Industrial and Extended temperature
ranges
• Parallel Slave Port (PSP) 8-bits wide, with
external RD, WR and CS controls (40/44-pin only)
• Low-power consumption:
• Brown-out detection circuitry for
Brown-out Reset (BOR)
- < 0.6 mA typical @ 3V, 4 MHz
- 20 A typical @ 3V, 32 kHz
- < 1 A typical standby current
1998-2013 Microchip Technology Inc.
DS30292D-page 1
PIC16F87X
Pin Diagrams
PDIP, SOIC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
MCLR/VPP
RA0/AN0
RA1/AN1
2
3
4
5
6
7
8
9
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
VSS
10
11
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
12
13
14
RC3/SCK/SCL
PLCC
RA4/T0CKI
RA5/AN4/SS
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
39
38
37
36
35
34
33
32
31
30
29
RB3/PGM
RB2
7
8
RB1
9
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
10
11
12
13
14
15
16
17
PIC16F877
PIC16F874
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CK1
NC
QFP
NC
33
1
2
3
4
5
6
7
8
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3/PGM
RC0/T1OSO/T1CKI
32
31
30
29
28
27
26
OSC2/CLKOUT
OSC1/CLKIN
VSS
PIC16F877
PIC16F874
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS
RA4/T0CKI
9
10
11
25
24
23
DS30292D-page 2
1998-2013 Microchip Technology Inc.
PIC16F87X
Key Features
PIC® MCU Mid-Range Reference
Manual (DS33023)
PIC16F873
PIC16F874
PIC16F876
PIC16F877
Operating Frequency
RESETS (and Delays)
DC - 20 MHz
DC - 20 MHz
DC - 20 MHz
DC - 20 MHz
POR, BOR
POR, BOR
POR, BOR
POR, BOR
(PWRT, OST)
(PWRT, OST)
(PWRT, OST)
(PWRT, OST)
FLASH Program Memory
(14-bit words)
4K
4K
8K
8K
Data Memory (bytes)
EEPROM Data Memory
Interrupts
192
192
368
368
128
128
256
256
13
14
13
14
I/O Ports
Ports A,B,C
Ports A,B,C,D,E
Ports A,B,C
Ports A,B,C,D,E
Timers
3
3
3
3
Capture/Compare/PWM Modules
Serial Communications
Parallel Communications
10-bit Analog-to-Digital Module
Instruction Set
2
MSSP, USART
—
2
2
MSSP, USART
—
2
MSSP, USART
PSP
MSSP, USART
PSP
5 input channels 8 input channels 5 input channels 8 input channels
35 instructions
35 instructions
35 instructions
35 instructions
1998-2013 Microchip Technology Inc.
DS30292D-page 3
PIC16F87X
Table of Contents
1.0 Device Overview ................................................................................................................................................... 5
2.0 Memory Organization.......................................................................................................................................... 11
3.0 I/O Ports.............................................................................................................................................................. 29
4.0 Data EEPROM and FLASH Program Memory.................................................................................................... 41
5.0 Timer0 Module .................................................................................................................................................... 47
6.0 Timer1 Module .................................................................................................................................................... 51
7.0 Timer2 Module .................................................................................................................................................... 55
8.0 Capture/Compare/PWM Modules ....................................................................................................................... 57
9.0 Master Synchronous Serial Port (MSSP) Module............................................................................................... 65
10.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ........................................ 95
11.0 Analog-to-Digital Converter (A/D) Module......................................................................................................... 111
12.0 Special Features of the CPU............................................................................................................................. 119
13.0 Instruction Set Summary................................................................................................................................... 135
14.0 Development Support ....................................................................................................................................... 143
15.0 Electrical Characteristics................................................................................................................................... 149
16.0 DC and AC Characteristics Graphs and Tables................................................................................................ 177
17.0 Packaging Information ...................................................................................................................................... 189
Appendix A: Revision History .................................................................................................................................... 197
Appendix B: Device Differences ................................................................................................................................ 197
Appendix C: Conversion Considerations ................................................................................................................... 198
Index .......................................................................................................................................................................... 199
On-Line Support......................................................................................................................................................... 207
Reader Response ...................................................................................................................................................... 208
PIC16F87X Product Identification System................................................................................................................. 209
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DS30292D-page 4
1998-2013 Microchip Technology Inc.
PIC16F87X
There are four devices (PIC16F873, PIC16F874,
PIC16F876 and PIC16F877) covered by this data
sheet. The PIC16F876/873 devices come in 28-pin
packages and the PIC16F877/874 devices come in
40-pin packages. The Parallel Slave Port is not
implemented on the 28-pin devices.
1.0
DEVICE OVERVIEW
This document contains device specific information.
Additional information may be found in the PIC® MCU
Mid-Range Reference Manual (DS33023), which may
be obtained from your local Microchip Sales Represen-
tative or downloaded from the Microchip website. The
Reference Manual should be considered a complemen-
tary document to this data sheet, and is highly recom-
mended reading for a better understanding of the device
architecture and operation of the peripheral modules.
The following device block diagrams are sorted by pin
number; 28-pin for Figure 1-1 and 40-pin for Figure 1-2.
The 28-pin and 40-pin pinouts are listed in Table 1-1
and Table 1-2, respectively.
FIGURE 1-1:
PIC16F873 AND PIC16F876 BLOCK DIAGRAM
Program
FLASH
Data
EEPROM
Device
Data Memory
PIC16F873
PIC16F876
4K
8K
192 Bytes
368 Bytes
128 Bytes
256 Bytes
8
13
PORTA
PORTB
Data Bus
Program Counter
RA0/AN0
RA1/AN1
FLASH
Program
Memory
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RAM
File
Registers
8 Level Stack
(13-bit)
RA5/AN4/SS
Program
Bus
14
RAM Addr(1)
9
RB0/INT
RB1
RB2
RB3/PGM
RB4
Addr MUX
Instruction reg
Indirect
Addr
7
Direct Addr
8
RB5
FSR reg
RB6/PGC
RB7/PGD
STATUS reg
8
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
3
MUX
Power-up
Timer
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Oscillator
Instruction
Decode &
Control
Start-up Timer
ALU
Power-on
Reset
8
Watchdog
Timer
Timing
Generation
W reg
Brown-out
Reset
OSC1/CLKIN
OSC2/CLKOUT
In-Circuit
Debugger
Low Voltage
Programming
VDD, VSS
Timer2
MCLR
Timer0
Timer1
10-bit A/D
Synchronous
Serial Port
Data EEPROM
USART
CCP1,2
Note 1: Higher order bits are from the STATUS register.
1998-2013 Microchip Technology Inc.
DS30292D-page 5
PIC16F87X
FIGURE 1-2:
PIC16F874 AND PIC16F877 BLOCK DIAGRAM
Program
FLASH
Data
EEPROM
Device
Data Memory
PIC16F874
PIC16F877
4K
8K
192 Bytes
368 Bytes
128 Bytes
256 Bytes
13
8
PORTA
Data Bus
RAM
Program Counter
FLASH
RA0/AN0
RA1/AN1
Program
Memory
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
8 Level Stack
(13-bit)
File
Registers
RA5/AN4/SS
Program
Bus
14
PORTB
RAM Addr(1)
9
RB0/INT
RB1
RB2
RB3/PGM
RB4
Addr MUX
Instruction reg
Indirect
Addr
7
Direct Addr
8
RB5
FSR reg
RB6/PGC
RB7/PGD
STATUS reg
8
PORTC
PORTD
PORTE
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
3
MUX
Power-up
Timer
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
Oscillator
Start-up Timer
Instruction
Decode &
Control
ALU
Power-on
Reset
RC6/TX/CK
8
RC7/RX/DT
Timing
Generation
Watchdog
Timer
W reg
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Reset
RD0/PSP0
RD1/PSP1
RD2/PSP2
In-Circuit
Debugger
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
Low-Voltage
Programming
Parallel Slave Port
MCLR VDD, VSS
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
Timer0
Timer1
Timer2
10-bit A/D
USART
Synchronous
Serial Port
Data EEPROM
CCP1,2
Note 1: Higher order bits are from the STATUS register.
DS30292D-page 6
1998-2013 Microchip Technology Inc.
PIC16F87X
TABLE 1-1:
PIC16F873 AND PIC16F876 PINOUT DESCRIPTION
DIP
Pin#
SOIC
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
(3)
OSC1/CLKIN
9
9
I
ST/CMOS
—
Oscillator crystal input/external clock source input.
OSC2/CLKOUT
10
10
O
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
MCLR/VPP
1
1
I/P
ST
Master Clear (Reset) input or programming voltage input. This
pin is an active low RESET to the device.
PORTA is a bi-directional I/O port.
RA0 can also be analog input0.
RA1 can also be analog input1.
RA0/AN0
2
3
4
2
3
4
I/O
I/O
I/O
TTL
TTL
TTL
RA1/AN1
RA2/AN2/VREF-
RA2 can also be analog input2 or negative analog
reference voltage.
RA3/AN3/VREF+
RA4/T0CKI
5
6
7
5
6
7
I/O
I/O
I/O
TTL
ST
RA3 can also be analog input3 or positive analog
reference voltage.
RA4 can also be the clock input to the Timer0
module. Output is open drain type.
RA5/SS/AN4
TTL
RA5 can also be analog input4 or the slave select
for the synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
RB0/INT
RB1
21
22
23
24
25
26
27
21
22
23
24
25
26
27
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL/ST
TTL
RB0 can also be the external interrupt pin.
RB2
TTL
RB3/PGM
RB4
TTL
RB3 can also be the low voltage programming input.
Interrupt-on-change pin.
TTL
RB5
TTL
Interrupt-on-change pin.
(2)
RB6/PGC
TTL/ST
Interrupt-on-change pin or In-Circuit Debugger pin. Serial
programming clock.
(2)
RB7/PGD
28
28
I/O
TTL/ST
Interrupt-on-change pin or In-Circuit Debugger pin. Serial
programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
11
12
13
14
15
11
12
13
14
15
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1 can also be the Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output.
RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL
RC4/SDI/SDA
RC3 can also be the synchronous serial clock input/output
2
for both SPI and I C modes.
RC4 can also be the SPI Data In (SPI mode) or
2
data I/O (I C mode).
RC5/SDO
16
17
16
17
I/O
I/O
ST
ST
RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK
RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
18
18
I/O
ST
RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
VSS
8, 19
20
8, 19
20
P
P
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
VDD
Legend: I = input
O = output
— = Not used
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
1998-2013 Microchip Technology Inc.
DS30292D-page 7
PIC16F87X
TABLE 1-2:
PIC16F874 AND PIC16F877 PINOUT DESCRIPTION
DIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
(4)
OSC1/CLKIN
13
14
14
15
30
31
I
ST/CMOS
—
Oscillator crystal input/external clock source input.
OSC2/CLKOUT
O
Oscillator crystal output. Connects to crystal or resonator
in crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
MCLR/VPP
1
2
18
I/P
ST
Master Clear (Reset) input or programming voltage input.
This pin is an active low RESET to the device.
PORTA is a bi-directional I/O port.
RA0 can also be analog input0.
RA1 can also be analog input1.
RA0/AN0
2
3
4
3
4
5
19
20
21
I/O
I/O
I/O
TTL
TTL
TTL
RA1/AN1
RA2/AN2/VREF-
RA2 can also be analog input2 or negative
analog reference voltage.
RA3/AN3/VREF+
RA4/T0CKI
5
6
7
6
7
8
22
23
24
I/O
I/O
I/O
TTL
ST
RA3 can also be analog input3 or positive
analog reference voltage.
RA4 can also be the clock input to the Timer0 timer/
counter. Output is open drain type.
RA5/SS/AN4
TTL
RA5 can also be analog input4 or the slave select for
the synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be soft-
ware programmed for internal weak pull-up on all inputs.
(1)
RB0/INT
RB1
33
34
35
36
37
38
39
36
37
38
39
41
42
43
8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL/ST
TTL
RB0 can also be the external interrupt pin.
9
RB2
10
11
14
15
16
TTL
RB3/PGM
RB4
TTL
RB3 can also be the low voltage programming input.
Interrupt-on-change pin.
TTL
RB5
TTL
Interrupt-on-change pin.
(2)
RB6/PGC
TTL/ST
Interrupt-on-change pin or In-Circuit Debugger pin.
Serial programming clock.
(2)
RB7/PGD
40
44
17
I/O
TTL/ST
Interrupt-on-change pin or In-Circuit Debugger pin.
Serial programming data.
Legend: I = input
O = output
— = Not used
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS30292D-page 8
1998-2013 Microchip Technology Inc.
PIC16F87X
TABLE 1-2:
PIC16F874 AND PIC16F877 PINOUT DESCRIPTION (CONTINUED)
DIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
15
16
17
18
23
16
18
19
20
25
32
35
36
37
42
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
RC0 can also be the Timer1 oscillator output or a
Timer1 clock input.
RC1 can also be the Timer1 oscillator input or
Capture2 input/Compare2 output/PWM2 output.
RC2 can also be the Capture1 input/Compare1
output/PWM1 output.
RC3/SCK/SCL
RC4/SDI/SDA
RC3 can also be the synchronous serial clock input/
2
output for both SPI and I C modes.
RC4 can also be the SPI Data In (SPI mode) or
2
data I/O (I C mode).
RC5/SDO
24
25
26
27
43
44
I/O
I/O
ST
ST
RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK
RC6 can also be the USART Asynchronous Transmit
or Synchronous Clock.
RC7/RX/DT
26
29
1
I/O
ST
RC7 can also be the USART Asynchronous Receive
or Synchronous Data.
PORTD is a bi-directional I/O port or parallel slave port
when interfacing to a microprocessor bus.
(3)
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
19
20
21
22
27
28
29
30
21
22
23
24
30
31
32
33
38
39
40
41
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
(3)
(3)
(3)
(3)
(3)
(3)
(3)
3
4
5
PORTE is a bi-directional I/O port.
(3)
(3)
(3)
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
8
9
9
25
26
27
I/O
I/O
I/O
ST/TTL
ST/TTL
ST/TTL
RE0 can also be read control for the parallel slave
port, or analog input5.
10
11
RE1 can also be write control for the parallel slave
port, or analog input6.
10
RE2 can also be select control for the parallel slave
port, or analog input7.
VSS
VDD
NC
12,31
11,32
—
13,34
12,35
6,29
7,28
P
P
—
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
1,17,28, 12,13,
40 33,34
These pins are not internally connected. These pins
should be left unconnected.
Legend: I = input
O = output
— = Not used
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
1998-2013 Microchip Technology Inc.
DS30292D-page 9
PIC16F87X
NOTES:
DS30292D-page 10
1998-2013 Microchip Technology Inc.
PIC16F87X
2.1
Program Memory Organization
2.0
MEMORY ORGANIZATION
The PIC16F87X devices have a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. The PIC16F877/876 devices have 8K x 14
words of FLASH program memory, and the
PIC16F873/874 devices have 4K x 14. Accessing a
location above the physically implemented address will
cause a wraparound.
There are three memory blocks in each of the
PIC16F87X MCUs. The Program Memory and Data
Memory have separate buses so that concurrent
access can occur and is detailed in this section. The
EEPROM data memory block is detailed in Section 4.0.
Additional information on device memory may be found
in the PIC® MCU Mid-Range Reference Manual,
(DS33023).
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
FIGURE 2-1:
PIC16F877/876 PROGRAM
MEMORY MAP AND
STACK
FIGURE 2-2:
PIC16F874/873 PROGRAM
MEMORY MAP AND
STACK
PC<12:0>
13
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 1
Stack Level 2
Stack Level 8
Stack Level 8
RESET Vector
0000h
RESET Vector
0000h
Interrupt Vector
Page 0
0004h
0005h
Interrupt Vector
Page 0
0004h
0005h
On-Chip
Program
Memory
07FFh
0800h
07FFh
0800h
Page 1
Page 1
On-Chip
Program
Memory
0FFFh
1000h
0FFFh
1000h
Page 2
Page 3
17FFh
1800h
1FFFh
1FFFh
1998-2013 Microchip Technology Inc.
DS30292D-page 11
PIC16F87X
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
2.2
Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>)
and RP0 (STATUS<5>) are the bank select bits.
RP1:RP0
Bank
Note: EEPROM Data Memory description can be
found in Section 4.0 of this data sheet.
00
01
10
11
0
1
2
3
2.2.1
GENERAL PURPOSE REGISTER
FILE
The register file can be accessed either directly, or indi-
rectly through the File Select Register (FSR).
DS30292D-page 12
1998-2013 Microchip Technology Inc.
PIC16F87X
FIGURE 2-3:
PIC16F877/876 REGISTER FILE MAP
File
Address
File
Address
File
Address
File
Address
Indirect addr.(*)
Indirect addr.(*)
180h
OPTION_REG
181h
Indirect addr.(*)
Indirect addr.(*)
OPTION_REG
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
TMR0
PCL
TMR0
PCL
PCL
STATUS
FSR
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
PCL
STATUS
FSR
STATUS
FSR
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(1)
PORTE(1)
PCLATH
INTCON
PIR1
TRISA
TRISB
TRISC
TRISD(1)
TRISE(1)
PCLATH
INTCON
PIE1
TRISB
PORTB
PCLATH
INTCON
EECON1
EECON2
Reserved(2)
Reserved(2)
PCLATH
INTCON
EEDATA
EEADR
PIE2
PIR2
TMR1L
PCON
EEDATH
EEADRH
TMR1H
T1CON
TMR2
SSPCON2
PR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
SSPADD
SSPSTAT
General
Purpose
Register
General
Purpose
Register
TXSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
SPBRG
16 Bytes
16 Bytes
ADRESL
ADCON1
ADCON0
1A0h
A0h
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
80 Bytes
80 Bytes
80 Bytes
1EFh
1F0h
96 Bytes
EFh
F0h
16Fh
170h
accesses
70h - 7Fh
accesses
70h-7Fh
accesses
70h-7Fh
17Fh
1FFh
7Fh
FFh
Bank 3
Bank 1
Bank 2
Bank 0
Unimplemented data memory locations, read as '0'.
* Not a physical register.
Note 1: These registers are not implemented on the PIC16F876.
2: These registers are reserved, maintain these registers clear.
1998-2013 Microchip Technology Inc.
DS30292D-page 13
PIC16F87X
FIGURE 2-4:
PIC16F874/873 REGISTER FILE MAP
File
Address
File
Address
File
Address
File
Address
Indirect addr.(*)
Indirect addr.(*)
OPTION_REG
PCL
Indirect addr.(*)
Indirect addr.(*)
OPTION_REG
PCL
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
TMR0
PCL
TMR0
PCL
STATUS
FSR
STATUS
FSR
STATUS
FSR
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(1)
PORTE(1)
PCLATH
INTCON
PIR1
TRISA
TRISB
PORTB
TRISB
TRISC
TRISD(1)
TRISE(1)
PCLATH
INTCON
PIE1
PCLATH
INTCON
PCLATH
INTCON
EEDATA
EEADR
EECON1
EECON2
Reserved(2)
Reserved(2)
PIR2
PIE2
TMR1L
TMR1H
T1CON
TMR2
PCON
EEDATH
EEADRH
SSPCON2
PR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
SSPADD
SSPSTAT
TXSTA
SPBRG
ADRESL
ADCON1
ADCON0
1A0h
120h
A0h
General
Purpose
Register
General
Purpose
Register
accesses
20h-7Fh
accesses
A0h - FFh
1EFh
1F0h
96 Bytes
96 Bytes
16Fh
170h
17Fh
1FFh
7Fh
FFh
Bank 3
Bank 1
Bank 2
Bank 0
Unimplemented data memory locations, read as '0'.
* Not a physical register.
Note 1: These registers are not implemented on the PIC16F873.
2: These registers are reserved, maintain these registers clear.
DS30292D-page 14
1998-2013 Microchip Technology Inc.
PIC16F87X
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral features section.
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY
Value on:
POR,
Details
on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
page:
Bank 0
00h(3)
01h
02h(3)
03h(3)
04h(3)
05h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
--0x 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- -xxx
---0 0000
0000 000x
27
47
26
18
27
29
31
33
35
36
26
20
22
24
52
52
51
55
55
TMR0
PCL
Program Counter (PC) Least Significant Byte
STATUS
FSR
IRP
Indirect Data Memory Address Pointer
PORTA Data Latch when written: PORTA pins when read
RP1
RP0
TO
PD
Z
DC
C
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
—
—
06h
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
07h
08h(4)
09h(4)
0Ah(1,3)
0Bh(3)
0Ch
—
—
—
—
—
—
—
—
RE2
RE1
RE0
Write Buffer for the upper 5 bits of the Program Counter
GIE
PSPIF(3)
PEIE
ADIF
(5)
T0IE
RCIF
—
INTE
TXIF
EEIF
RBIE
SSPIF
BCLIF
T0IF
CCP1IF
—
INTF
TMR2IF
—
RBIF
TMR1IF 0000 0000
CCP2IF -r-0 0--0
xxxx xxxx
0Dh
PIR2
—
0Eh
TMR1L
TMR1H
T1CON
TMR2
Holding register for the Least Significant Byte of the 16-bit TMR1 Register
Holding register for the Most Significant Byte of the 16-bit TMR1 Register
0Fh
xxxx xxxx
10h
—
—
T1CKPS1 T1CKPS0 T1OSCEN
T1SYNC
TMR1CS TMR1ON --00 0000
11h
Timer2 Module Register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0
Synchronous Serial Port Receive Buffer/Transmit Register
0000 0000
12h
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
—
TMR2ON T2CKPS1 T2CKPS0 -000 0000
xxxx xxxx 70, 73
13h
14h
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0 0000 0000
67
57
15h
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx
xxxx xxxx
16h
57
17h
—
—
CCP1X
SREN
CCP1Y
CREN
CCP1M3
ADDEN
CCP1M2
FERR
CCP1M1 CCP1M0 --00 0000
58
18h
SPEN
RX9
OERR
RX9D
0000 000x
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
96
19h
USART Transmit Data Register
USART Receive Data Register
99
1Ah
101
57
1Bh
Capture/Compare/PWM Register2 (LSB)
Capture/Compare/PWM Register2 (MSB)
1Ch
57
1Dh
—
—
CCP2X
A/D Result Register High Byte
ADCS1 ADCS0 CHS2
CCP2Y
CCP2M3
CHS0
CCP2M2
CCP2M1 CCP2M0 --00 0000
58
1Eh
xxxx xxxx
116
111
1Fh
CHS1
GO/DONE
—
ADON
0000 00-0
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’.
5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
1998-2013 Microchip Technology Inc.
DS30292D-page 15
PIC16F87X
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on:
POR,
Details
on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
page:
Bank 1
80h(3)
81h
82h(3)
83h(3)
84h(3)
85h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
---0 0000
0000 000x
27
19
26
18
27
29
31
33
35
37
26
20
21
23
25
—
—
68
55
OPTION_REG
PCL
RBPU
Program Counter (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect Data Memory Address Pointer
PORTA Data Direction Register
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
STATUS
FSR
PD
Z
DC
C
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
—
—
86h
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
87h
88h(4)
89h(4)
8Ah(1,3)
8Bh(3)
8Ch
IBF
—
OBF
—
IBOV
—
PSPMODE
—
PORTE Data Direction Bits
Write Buffer for the upper 5 bits of the Program Counter
GIE
PSPIE(2)
—
PEIE
ADIE
(5)
T0IE
RCIE
—
INTE
TXIE
EEIE
—
RBIE
SSPIE
BCLIE
—
T0IF
CCP1IE
—
INTF
TMR2IE
—
RBIF
TMR1IE 0000 0000
CCP2IE -r-0 0--0
8Dh
PIE2
8Eh
PCON
—
—
—
—
—
POR
BOR
SEN
BF
---- --qq
—
8Fh
Unimplemented
Unimplemented
90h
—
—
91h
SSPCON2
PR2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
R/W
RSEN
UA
0000 0000
1111 1111
92h
Timer2 Period Register
Synchronous Serial Port (I2C mode) Address Register
93h
SSPADD
SSPSTAT
—
0000 0000 73, 74
94h
SMP
CKE
D/A
P
S
0000 0000
66
—
95h
Unimplemented
Unimplemented
Unimplemented
—
96h
—
—
—
97h
—
—
—
98h
TXSTA
SPBRG
—
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
95
97
—
99h
Baud Rate Generator Register
Unimplemented
0000 0000
9Ah
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
—
9Dh
—
Unimplemented
—
9Eh
ADRESL
ADCON1
A/D Result Register Low Byte
xxxx xxxx
116
112
9Fh
ADFM
—
—
—
PCFG3
PCFG2
PCFG1
PCFG0 0---0000
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’.
5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
DS30292D-page 16
1998-2013 Microchip Technology Inc.
PIC16F87X
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on:
POR,
Details
on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
page:
Bank 2
100h(3)
101h
102h(3)
103h(3)
104h(3)
105h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
—
27
47
26
18
27
—
31
—
—
—
26
20
41
41
41
41
TMR0
PCL
STATUS
FSR
—
Program Counter's (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
Unimplemented
106h
PORTB
—
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx
—
107h
Unimplemented
Unimplemented
Unimplemented
108h
—
—
109h
—
—
10Ah(1,3) PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
INTE RBIE T0IF INTF RBIF
---0 0000
0000 000x
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
10Bh(3)
10Ch
10Dh
10Eh
INTCON
EEDATA
EEADR
GIE
PEIE
T0IE
EEPROM Data Register Low Byte
EEPROM Address Register Low Byte
EEDATH
EEADRH
—
—
—
—
EEPROM Data Register High Byte
EEPROM Address Register High Byte
10Fh
—
Bank 3
180h(3)
181h
182h(3)
183h(3)
184h(3)
185h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
—
27
19
26
18
27
—
31
—
—
—
26
20
OPTION_REG
RBPU
Program Counter (PC) Least Significant Byte
IRP RP1 RP0 TO
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
PCL
STATUS
FSR
—
PD
Z
DC
C
Indirect Data Memory Address Pointer
Unimplemented
186h
TRISB
—
PORTB Data Direction Register
Unimplemented
1111 1111
—
187h
188h
—
Unimplemented
—
189h
—
Unimplemented
—
18Ah(1,3) PCLATH
18Bh(3)
—
—
PEIE
—
—
T0IE
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
0000 000x
INTCON
EECON1
EECON2
—
GIE
INTE
—
RBIE
T0IF
INTF
WR
RBIF
RD
18Ch
EEPGD
WRERR
WREN
x--- x000 41, 42
18Dh
EEPROM Control Register2 (not a physical register)
Reserved maintain clear
---- ----
0000 0000
0000 0000
41
—
—
18Eh
18Fh
—
Reserved maintain clear
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
3: These registers can be addressed from any bank.
4: PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as ‘0’.
5: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
1998-2013 Microchip Technology Inc.
DS30292D-page 17
PIC16F87X
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
2.2.2.1
STATUS Register
The STATUS register contains the arithmetic status of
the ALU, the RESET status and the bank select bits for
data memory.
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions not affecting any status bits, see the
“Instruction Set Summary."
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable, therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1:
STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0
IRP
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 7
bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1= Bank 2, 3 (100h - 1FFh)
0= Bank 0, 1 (00h - FFh)
bit 6-5
RP1:RP0: Register Bank Select bits (used for direct addressing)
11= Bank 3 (180h - 1FFh)
10= Bank 2 (100h - 17Fh)
01= Bank 1 (80h - FFh)
00= Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4
bit 3
bit 2
bit 1
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)
(for borrow, the polarity is reversed)
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high, or low order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS30292D-page 18
1998-2013 Microchip Technology Inc.
PIC16F87X
2.2.2.2
OPTION_REG Register
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
The OPTION_REG Register is a readable and writable
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
able register known also as the prescaler), the External
INT Interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2:
OPTION_REG REGISTER (ADDRESS 81h, 181h)
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
RBPU: PORTB Pull-up Enable bit
1= PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 1
1 : 2
1 : 4
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
Note: When using low voltage ICSP programming (LVP) and the pull-ups on PORTB are enabled, bit 3
in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper oper-
ation of the device
1998-2013 Microchip Technology Inc.
DS30292D-page 19
PIC16F87X
2.2.2.3
INTCON Register
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The INTCON Register is a readable and writable regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
REGISTER 2-3:
INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
GIE: Global Interrupt Enable bit
1= Enables all unmasked interrupts
0= Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1= Enables the RB0/INT external interrupt
0= Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1= The RB0/INT external interrupt occurred (must be cleared in software)
0= The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set
the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared
(must be cleared in software).
0= None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS30292D-page 20
1998-2013 Microchip Technology Inc.
PIC16F87X
2.2.2.4
PIE1 Register
The PIE1 register contains the individual enable bits for
the peripheral interrupts.
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
REGISTER 2-4:
PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
PSPIE(1)
bit 7
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
R/W-0
R/W-0
CCP1IE TMR2IE TMR1IE
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D converter interrupt
0= Disables the A/D converter interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
SSPIE: Synchronous Serial Port Interrupt Enable bit
1= Enables the SSP interrupt
0= Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Note 1: PSPIE is reserved on PIC16F873/876 devices; always maintain this bit clear.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
1998-2013 Microchip Technology Inc.
DS30292D-page 21
PIC16F87X
2.2.2.5
PIR1 Register
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate interrupt
bits are clear prior to enabling an interrupt.
The PIR1 register contains the individual flag bits for
the peripheral interrupts.
REGISTER 2-5:
PIR1 REGISTER (ADDRESS 0Ch)
R/W-0
PSPIF(1)
bit 7
R/W-0
ADIF
R-0
R-0
TXIF
R/W-0
SSPIF
R/W-0
R/W-0
R/W-0
RCIF
CCP1IF
TMR2IF
TMR1IF
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit
1= A read or a write operation has taken place (must be cleared in software)
0= No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed
0= The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1= The USART receive buffer is full
0= The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1= The USART transmit buffer is empty
0= The USART transmit buffer is full
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1= The SSP interrupt condition has occurred, and must be cleared in software before returning
from the Interrupt Service Routine. The conditions that will set this bit are:
• SPI
- A transmission/reception has taken place.
•
I2C Slave
- A transmission/reception has taken place.
• I2C Master
- A transmission/reception has taken place.
- The initiated START condition was completed by the SSP module.
- The initiated STOP condition was completed by the SSP module.
- The initiated Restart condition was completed by the SSP module.
- The initiated Acknowledge condition was completed by the SSP module.
- A START condition occurred while the SSP module was idle (Multi-Master system).
- A STOP condition occurred while the SSP module was idle (Multi-Master system).
0= No SSP interrupt condition has occurred.
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Note 1: PSPIF is reserved on PIC16F873/876 devices; always maintain this bit clear.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS30292D-page 22
1998-2013 Microchip Technology Inc.
PIC16F87X
2.2.2.6
PIE2 Register
The PIE2 register contains the individual enable bits for
the CCP2 peripheral interrupt, the SSP bus collision
interrupt, and the EEPROM write operation interrupt.
REGISTER 2-6:
PIE2 REGISTER (ADDRESS 8Dh)
U-0
—
R/W-0
U-0
—
R/W-0
EEIE
R/W-0
BCLIE
U-0
—
U-0
—
R/W-0
CCP2IE
bit 0
Reserved
bit 7
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as '0'
Reserved: Always maintain this bit clear
Unimplemented: Read as '0'
EEIE: EEPROM Write Operation Interrupt Enable
1= Enable EE Write Interrupt
0= Disable EE Write Interrupt
bit 3
BCLIE: Bus Collision Interrupt Enable
1= Enable Bus Collision Interrupt
0= Disable Bus Collision Interrupt
bit 2-1
bit 0
Unimplemented: Read as '0'
CCP2IE: CCP2 Interrupt Enable bit
1= Enables the CCP2 interrupt
0= Disables the CCP2 interrupt
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
1998-2013 Microchip Technology Inc.
DS30292D-page 23
PIC16F87X
.
2.2.2.7
PIR2 Register
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The PIR2 register contains the flag bits for the CCP2
interrupt, the SSP bus collision interrupt and the
EEPROM write operation interrupt.
REGISTER 2-7:
PIR2 REGISTER (ADDRESS 0Dh)
U-0
—
R/W-0
U-0
—
R/W-0
EEIF
R/W-0
BCLIF
U-0
—
U-0
—
R/W-0
CCP2IF
bit 0
Reserved
bit 7
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as '0'
Reserved: Always maintain this bit clear
Unimplemented: Read as '0'
EEIF: EEPROM Write Operation Interrupt Flag bit
1= The write operation completed (must be cleared in software)
0= The write operation is not complete or has not been started
bit 3
BCLIF: Bus Collision Interrupt Flag bit
1= A bus collision has occurred in the SSP, when configured for I2C Master mode
0= No bus collision has occurred
bit 2-1
bit 0
Unimplemented: Read as '0'
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS30292D-page 24
1998-2013 Microchip Technology Inc.
PIC16F87X
2.2.2.8
PCON Register
Note: BOR is unknown on POR. It must be set by
the user and checked on subsequent
RESETS to see if BOR is clear, indicating
a brown-out has occurred. The BOR status
bit is a “don’t care” and is not predictable if
the brown-out circuit is disabled (by clear-
ing the BODEN bit in the configuration
word).
The Power Control (PCON) Register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watchdog Reset
(WDT), and an external MCLR Reset.
REGISTER 2-8:
PCON REGISTER (ADDRESS 8Eh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
POR
R/W-1
BOR
bit 7
bit 0
bit 7-2
bit 1
Unimplemented: Read as '0'
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
1998-2013 Microchip Technology Inc.
DS30292D-page 25
PIC16F87X
2.3
PCL and PCLATH
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any RESET, the upper bits of the
PC will be cleared. Figure 2-5 shows the two situations
for the loading of the PC. The upper example in the fig-
ure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> PCH). The lower example in the fig-
ure shows how the PC is loaded during a CALLor GOTO
instruction (PCLATH<4:3> PCH).
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an inter-
rupt address.
2.4
Program Memory Paging
All PIC16F87X devices are capable of addressing a
continuous 8K word block of program memory. The
CALL and GOTO instructions provide only 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALLor GOTOinstruction,
the upper 2 bits of the address are provided by
PCLATH<4:3>. When doing a CALL or GOTO instruc-
tion, the user must ensure that the page select bits are
programmed so that the desired program memory
page is addressed. If a return from a CALLinstruction
(or interrupt) is executed, the entire 13-bit PC is popped
off the stack. Therefore, manipulation of the
PCLATH<4:3> bits is not required for the return instruc-
tions (which POPs the address from the stack).
FIGURE 2-5:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
Instruction with
PCL as
Destination
PC
8
PCLATH<4:0>
PCLATH
5
ALU
PCH
12 11 10
PC
PCL
Note: The contents of the PCLATH register are
unchanged after a RETURN or RETFIE
instruction is executed. The user must
rewrite the contents of the PCLATH regis-
ter for any subsequent subroutine calls or
GOTOinstructions.
8
7
0
GOTO,CALL
PCLATH<4:3>
PCLATH
11
2
Opcode <10:0>
Example 2-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the Interrupt
Service Routine (if interrupts are used).
2.3.1
COMPUTED GOTO
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
EXAMPLE 2-1:
CALL OF A SUBROUTINE
IN PAGE 1 FROM PAGE 0
ORG 0x500
BCF PCLATH,4
BSF PCLATH,3 ;Select page 1
;(800h-FFFh)
CALL SUB1_P1 ;Call subroutine in
application note, “Implementing
(AN556).
a Table Read"
:
:
;page 1 (800h-FFFh)
;page 1 (800h-FFFh)
2.3.2
STACK
The PIC16F87X family has an 8-level deep x 13-bit wide
hardware stack. The stack space is not part of either pro-
gram or data space and the stack pointer is not readable
or writable. The PC is PUSHed onto the stack when a
CALL instruction is executed, or an interrupt causes a
branch. The stack is POPed in the event of a
RETURN,RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
ORG 0x900
SUB1_P1
:
;called subroutine
;page 1 (800h-FFFh)
:
RETURN
;return to
;Call subroutine
;in page 0
;(000h-7FFh)
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
DS30292D-page 26
1998-2013 Microchip Technology Inc.
PIC16F87X
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
2.5
Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
EXAMPLE 2-2:
INDIRECT ADDRESSING
MOVLW 0x20
MOVWF FSR
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF register itself, indirectly
(FSR = '0') will read 00h. Writing to the INDF register
indirectly results in a no operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 2-6.
NEXT
CLRF INDF
INCF FSR,F
BTFSS FSR,4
GOTO NEXT
CONTINUE
:
;yes continue
FIGURE 2-6:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
From Opcode
Indirect Addressing
7
RP1:RP0
6
0
0
IRP
FSR register
Bank Select
Location Select
Bank Select Location Select
00
01
80h
10
100h
11
00h
180h
Data
Memory
(1)
7Fh
Bank 0
FFh
Bank 1
17Fh
Bank 2
1FFh
Bank 3
Note 1: For register file map detail, see Figure 2-3.
1998-2013 Microchip Technology Inc.
DS30292D-page 27
PIC16F87X
NOTES:
DS30292D-page 28
1998-2013 Microchip Technology Inc.
PIC16F87X
FIGURE 3-1:
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
3.0
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Data Latch
Data
Bus
D
Q
VDD
WR
Additional information on I/O ports may be found in the
PIC® MCU Mid-Range Reference Manual, (DS33023).
Port
Q
CK
I/O pin(1)
P
TRIS Latch
3.1
PORTA and the TRISA Register
N
D
Q
PORTA is a 6-bit wide, bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
WR
TRIS
VSS
Analog
Input
Q
CK
Mode
RD
TRIS
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
TTL
Input
Buffer
Q
D
EN
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
RD Port
To A/D Converter
Note 1: I/O pins have protection diodes to VDD and VSS.
Other PORTA pins are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
FIGURE 3-2:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
Note: On a Power-on Reset, these pins are con-
Data
Bus
Data Latch
figured as analog inputs and read as '0'.
D
Q
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
WR
Port
Q
CK
I/O pin(1)
N
TRIS Latch
D
Q
VSS
EXAMPLE 3-1:
INITIALIZING PORTA
WR
TRIS
Schmitt
Trigger
Input
Q
CK
BCF
STATUS, RP0
;
BCF
STATUS, RP1 ; Bank0
CLRF
PORTA
; Initialize PORTA by
; clearing output
; data latches
Buffer
RD
TRIS
BSF
STATUS, RP0 ; Select Bank 1
MOVLW
MOVWF
MOVLW
0x06
ADCON1
0xCF
; Configure all pins
; as digital inputs
; Value used to
Q
D
; initialize data
; direction
; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6>are always
; read as '0'.
EN
RD Port
MOVWF
TRISA
TMR0 Clock Input
Note 1: I/O pin has protection diodes to VSS only.
1998-2013 Microchip Technology Inc.
DS30292D-page 29
PIC16F87X
TABLE 3-1:
Name
PORTA FUNCTIONS
Bit#
Buffer
Function
RA0/AN0
bit0
bit1
bit2
bit3
bit4
bit5
TTL
TTL
TTL
TTL
ST
Input/output or analog input.
Input/output or analog input.
Input/output or analog input.
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
Input/output or analog input or VREF.
Input/output or external clock input for Timer0. Output is open drain type.
Input/output or slave select input for synchronous serial port or analog input.
TTL
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 3-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on: Value on all
Address Name
Bit 7 Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other
RESETS
--0x 0000 --0u 0000
--11 1111 --11 1111
--0- 0000 --0- 0000
05h
85h
9Fh
PORTA
TRISA
—
—
—
—
—
RA5
RA4
RA3
RA2
RA1
RA0
PORTA Data Direction Register
PCFG3 PCFG2 PCFG1 PCFG0
ADCON1 ADFM
—
—
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'.
Shaded cells are not used by PORTA.
Note: When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of
the following modes, where PCFG3:PCFG0 = 0100,0101, 011x, 1101, 1110, 1111.
DS30292D-page 30
1998-2013 Microchip Technology Inc.
PIC16F87X
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
3.2
PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISB bit (= 0) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
Three pins of PORTB are multiplexed with the Low
Voltage Programming function: RB3/PGM, RB6/PGC
and RB7/PGD. The alternate functions of these pins
are described in the Special Features Section.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
This interrupt-on-mismatch feature, together with soft-
ware configureable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the Embedded
Control Handbook, “Implementing Wake-up on Key
Strokes” (AN552).
FIGURE 3-3:
BLOCK DIAGRAM OF
RB3:RB0 PINS
RB0/INT is an external interrupt input pin and is config-
ured using the INTEDG bit (OPTION_REG<6>).
VDD
RBPU(2)
Weak
RB0/INT is discussed in detail in Section 12.10.1.
P
Pull-up
Data Latch
Data Bus
WR Port
FIGURE 3-4:
BLOCK DIAGRAM OF
RB7:RB4 PINS
D
Q
I/O
pin(1)
CK
TRIS Latch
VDD
RBPU(2)
Weak
P
D
Q
Pull-up
TTL
Input
Buffer
Data Latch
WR TRIS
Data Bus
WR Port
CK
D
Q
I/O
pin(1)
CK
TRIS Latch
RD TRIS
RD Port
D
Q
Q
D
WR TRIS
RD TRIS
TTL
CK
EN
Input
Buffer
ST
Buffer
RB0/INT
RB3/PGM
Latch
Schmitt Trigger
Buffer
RD Port
Q
Q
D
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
EN
Q1
Set RBIF
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
D
Four of the PORTB pins, RB7:RB4, have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
RD Port
Q3
From other
RB7:RB4 pins
EN
RB7:RB6
In Serial Programming Mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
1998-2013 Microchip Technology Inc.
DS30292D-page 31
PIC16F87X
TABLE 3-3:
PORTB FUNCTIONS
Name
Bit#
Buffer
Function
RB0/INT
bit0
TTL/ST(1)
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1
bit1
bit2
bit3
TTL
TTL
TTL
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
RB2
RB3/PGM(3)
Input/output pin or programming pin in LVP mode. Internal software
programmable weak pull-up.
RB4
bit4
bit5
bit6
bit7
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB5
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB6/PGC
RB7/PGD
TTL/ST(2)
TTL/ST(2)
Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin.
Internal software programmable weak pull-up. Serial programming clock.
Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin.
Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: Low Voltage ICSP Programming (LVP) is enabled by default, which disables the RB3 I/O function. LVP
must be disabled to enable RB3 as an I/O pin and allow maximum compatibility to the other 28-pin and
40-pin mid-range devices.
TABLE 3-4:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on: Value on
Name
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR,
BOR
all other
RESETS
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
1111 1111 1111 1111
06h, 106h PORTB
86h, 186h TRISB
RB7
RB6
RB5
RB4 RB3 RB2 RB1 RB0
PORTB Data Direction Register
81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.
DS30292D-page 32
1998-2013 Microchip Technology Inc.
PIC16F87X
FIGURE 3-6:
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<4:3>
3.3
PORTC and the TRISC Register
PORTC is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISC bit (= 0) will
make the corresponding PORTC pin an output (i.e., put
the contents of the output latch on the selected pin).
Port/Peripheral Select(2)
Peripheral Data Out
Data Bus
0
VDD
D
Q
P
I/O
WR
Port
pin(1)
1
PORTC is multiplexed with several peripheral functions
(Table 3-5). PORTC pins have Schmitt Trigger input
buffers.
When the I2C module is enabled, the PORTC<4:3>
pins can be configured with normal I2C levels, or with
SMBus levels by using the CKE bit (SSPSTAT<6>).
Q
CK
Data Latch
D
Q
Q
WR
TRIS
CK
N
TRIS Latch
Vss
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISC as
destination, should be avoided. The user should refer
to the corresponding peripheral section for the correct
TRIS bit settings.
RD
TRIS
Schmitt
Trigger
Peripheral
OE(3)
Q
D
Schmitt
Trigger
EN
with
RD
Port
SMBus
levels
0
SSPl Input
1
CKE
SSPSTAT<6>
FIGURE 3-5:
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<2:0>,
RC<7:5>
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port data
and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
Port/Peripheral Select(2)
Peripheral Data Out
Data Bus
VDD
P
0
1
D
Q
Q
I/O
WR
pin(1)
Port
CK
Data Latch
D
Q
Q
WR
TRIS
CK
N
TRIS Latch
VSS
RD
TRIS
Schmitt
Trigger
Peripheral
OE(3)
Q
D
EN
RD
Port
Peripheral Input
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port
data and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
1998-2013 Microchip Technology Inc.
DS30292D-page 33
PIC16F87X
TABLE 3-5:
PORTC FUNCTIONS
Name
Bit# Buffer Type
Function
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
bit0
bit1
ST
ST
Input/output port pin or Timer1 oscillator output/Timer1 clock input.
Input/output port pin or Timer1 oscillator input or Capture2 input/
Compare2 output/PWM2 output.
RC2/CCP1
bit2
bit3
ST
ST
Input/output port pin or Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL
RC3 can also be the synchronous serial clock for both SPI
and I2C modes.
RC4/SDI/SDA
RC5/SDO
bit4
bit5
bit6
ST
ST
ST
RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode).
Input/output port pin or Synchronous Serial Port data output.
RC6/TX/CK
Input/output port pin or USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
bit7
ST
Input/output port pin or USART Asynchronous Receive or
Synchronous Data.
Legend: ST = Schmitt Trigger input
TABLE 3-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on: Value on all
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other
RESETS
xxxx xxxx
1111 1111
uuuu uuuu
1111 1111
07h
87h
PORTC RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
TRISC PORTC Data Direction Register
Legend: x= unknown, u= unchanged
DS30292D-page 34
1998-2013 Microchip Technology Inc.
PIC16F87X
FIGURE 3-7:
PORTD BLOCK DIAGRAM
(IN I/O PORT MODE)
3.4
PORTD and TRISD Registers
PORTD and TRISD are not implemented on the
PIC16F873 or PIC16F876.
I/O pin(1)
Data
Bus
Data Latch
D
Q
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configureable as an input or
output.
WR
Port
CK
TRIS Latch
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL.
D
Q
WR
TRIS
Schmitt
Trigger
Input
CK
Buffer
RD
TRIS
Q
D
EN
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 3-7:
Name
PORTD FUNCTIONS
Bit#
Buffer Type
Function
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
Input/output port pin or parallel slave port bit0.
Input/output port pin or parallel slave port bit1.
Input/output port pin or parallel slave port bit2.
Input/output port pin or parallel slave port bit3.
Input/output port pin or parallel slave port bit4.
Input/output port pin or parallel slave port bit5.
Input/output port pin or parallel slave port bit6.
Input/output port pin or parallel slave port bit7.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 3-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on: Value on
Address Name Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
RD3
—
Bit 2
Bit 1
Bit 0
POR,
BOR
all other
RESETS
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 -111 0000 -111
08h
88h
89h
PORTD RD7 RD6 RD5
RD4
RD2
RD1
RD0
TRISD
TRISE
PORTD Data Direction Register
IBF OBF IBOV PSPMODE
PORTE Data Direction Bits
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by PORTD.
1998-2013 Microchip Technology Inc.
DS30292D-page 35
PIC16F87X
FIGURE 3-8:
PORTE BLOCK DIAGRAM
(IN I/O PORT MODE)
3.5
PORTE and TRISE Register
PORTE and TRISE are not implemented on the
PIC16F873 or PIC16F876.
I/O pin(1)
Data
Bus
Data Latch
PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6,
and RE2/CS/AN7) which are individually configureable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
D
Q
WR
Port
CK
TRIS Latch
The PORTE pins become the I/O control inputs for the
microprocessor port when bit PSPMODE (TRISE<4>) is
set. In this mode, the user must make certain that the
TRISE<2:0> bits are set, and that the pins are configured
as digital inputs. Also ensure that ADCON1 is configured
for digital I/O. In this mode, the input buffers are TTL.
D
Q
WR
TRIS
Schmitt
Trigger
Input
CK
Buffer
RD
TRIS
Register 3-1 shows the TRISE register, which also con-
trols the parallel slave port operation.
PORTE pins are multiplexed with analog inputs. When
selected for analog input, these pins will read as '0's.
Q
D
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
EN
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
Note: On a Power-on Reset, these pins are con-
figured as analog inputs, and read as ‘0’.
TABLE 3-9:
Name
PORTE FUNCTIONS
Bit# Buffer Type
Function
I/O port pin or read control input in Parallel Slave Port mode or analog input:
RD
RE0/RD/AN5
bit0
ST/TTL(1) 1 = Idle
0 = Read operation. Contents of PORTD register are output to PORTD
I/O pins (if chip selected)
I/O port pin or write control input in Parallel Slave Port mode or analog input:
WR
RE1/WR/AN6 bit1
ST/TTL(1) 1= Idle
0= Write operation. Value of PORTD I/O pins is latched into PORTD
register (if chip selected)
I/O port pin or chip select control input in Parallel Slave Port mode or analog input:
CS
RE2/CS/AN7
bit2
ST/TTL(1)
1= Device is not selected
0= Device is selected
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 3-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
RESETS
09h
89h
9Fh
PORTE
TRISE
—
—
OBF
—
—
—
—
—
RE2
RE1
RE0
---- -xxx ---- -uuu
IBF
IBOV PSPMODE
PORTE Data Direction Bits 0000 -111 0000 -111
ADCON1 ADFM
—
—
PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by PORTE.
DS30292D-page 36
1998-2013 Microchip Technology Inc.
PIC16F87X
REGISTER 3-1:
TRISE REGISTER (ADDRESS 89h)
R-0
IBF
R-0
R/W-0
IBOV
R/W-0
U-0
—
R/W-1
Bit2
R/W-1
Bit1
R/W-1
Bit0
OBF
PSPMODE
bit 7
bit 0
Parallel Slave Port Status/Control Bits:
bit 7
bit 6
bit 5
IBF: Input Buffer Full Status bit
1= A word has been received and is waiting to be read by the CPU
0= No word has been received
OBF: Output Buffer Full Status bit
1= The output buffer still holds a previously written word
0= The output buffer has been read
IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1= A write occurred when a previously input word has not been read (must be cleared in
software)
0= No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1= PORTD functions in Parallel Slave Port mode
0= PORTD functions in general purpose I/O mode
bit 3
bit 2
Unimplemented: Read as '0'
PORTE Data Direction Bits:
Bit2: Direction Control bit for pin RE2/CS/AN7
1= Input
0= Output
bit 1
bit 0
Bit1: Direction Control bit for pin RE1/WR/AN6
1= Input
0= Output
Bit0: Direction Control bit for pin RE0/RD/AN5
1= Input
0= Output
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
1998-2013 Microchip Technology Inc.
DS30292D-page 37
PIC16F87X
When not in PSP mode, the IBF and OBF bits are held
clear. However, if flag bit IBOV was previously set, it
must be cleared in firmware.
3.6
Parallel Slave Port
The Parallel Slave Port (PSP) is not implemented on
the PIC16F873 or PIC16F876.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the user in firmware and the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7>).
PORTD operates as an 8-bit wide Parallel Slave Port or
microprocessor port, when control bit PSPMODE
(TRISE<4>) is set. In Slave mode, it is asynchronously
readable and writable by the external world through RD
control input pin RE0/RD and WR control input pin
RE1/WR.
FIGURE 3-9:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE
PORT)
The PSP can directly interface to an 8-bit microproces-
sor data bus. The external microprocessor can read or
write the PORTD latch as an 8-bit latch. Setting bit
PSPMODE enables port pin RE0/RD to be the RD
input, RE1/WR to be the WR input and RE2/CS to be
the CS (chip select) input. For this functionality, the cor-
responding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (set). The
Data Bus
D
Q
WR
Port
RDx
pin
CK
A/D
port
configuration
bits
PCFG3:PCFG0
(ADCON1<3:0>) must be set to configure pins
RE2:RE0 as digital I/O.
TTL
Q
D
There are actually two 8-bit latches: one for data out-
put, and one for data input. The user writes 8-bit data
to the PORTD data latch and reads data from the port
pin latch (note that they have the same address). In this
mode, the TRISD register is ignored, since the external
device is controlling the direction of data flow.
RD
Port
EN
One bit of PORTD
Set Interrupt Flag
PSPIF(PIR1<7>)
A write to the PSP occurs when both the CS and WR
lines are first detected low. When either the CS or WR
lines become high (level triggered), the Input Buffer Full
(IBF) status flag bit (TRISE<7>) is set on the Q4 clock
cycle, following the next Q2 cycle, to signal the write is
complete (Figure 3-10). The interrupt flag bit PSPIF
(PIR1<7>) is also set on the same Q4 clock cycle. IBF
can only be cleared by reading the PORTD input latch.
The Input Buffer Overflow (IBOV) status flag bit
(TRISE<5>) is set if a second write to the PSP is
attempted when the previous byte has not been read
out of the buffer.
Read
TTL
RD
CS
WR
Chip Select
TTL
Write
TTL
Note 1: I/O pins have protection diodes to VDD and VSS.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The Output Buffer Full
(OBF) status flag bit (TRISE<6>) is cleared immedi-
ately (Figure 3-11), indicating that the PORTD latch is
waiting to be read by the external bus. When either the
CS or RD pin becomes high (level triggered), the inter-
rupt flag bit PSPIF is set on the Q4 clock cycle, follow-
ing the next Q2 cycle, indicating that the read is
complete. OBF remains low until data is written to
PORTD by the user firmware.
DS30292D-page 38
1998-2013 Microchip Technology Inc.
PIC16F87X
FIGURE 3-10:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 3-11:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 3-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on
all other
RESETS
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
08h
09h
89h
0Ch
8Ch
9Fh
PORTD
PORTE
TRISE
PIR1
Port Data Latch when written: Port pins when read
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
0000 -111 0000 -111
—
IBF
—
—
—
—
—
RE2
RE1
RE0
OBF IBOV PSPMODE
PORTE Data Direction Bits
(1)
(1)
PSPIF
PSPIE
ADIF RCIF
ADIE RCIE
TXIF
TXIE
—
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
PIE1
ADCON1
ADFM
—
—
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear.
1998-2013 Microchip Technology Inc.
DS30292D-page 39
PIC16F87X
NOTES:
DS30292D-page 40
1998-2013 Microchip Technology Inc.
PIC16F87X
The EEPROM data memory allows byte read and write
operations without interfering with the normal operation
of the microcontroller. When interfacing to EEPROM
data memory, the EEADR register holds the address to
be accessed. Depending on the operation, the EEDATA
register holds the data to be written, or the data read, at
the address in EEADR. The PIC16F873/874 devices
have 128 bytes of EEPROM data memory and there-
fore, require that the MSb of EEADR remain clear. The
EEPROM data memory on these devices do not wrap
around to 0, i.e., 0x80 in the EEADR does not map to
0x00. The PIC16F876/877 devices have 256 bytes of
EEPROM data memory and therefore, uses all 8-bits of
the EEADR.
4.0
DATA EEPROM AND FLASH
PROGRAM MEMORY
The Data EEPROM and FLASH Program Memory are
readable and writable during normal operation over the
entire VDD range. These operations take place on a sin-
gle byte for Data EEPROM memory and a single word
for Program memory. A write operation causes an
erase-then-write operation to take place on the speci-
fied byte or word. A bulk erase operation may not be
issued from user code (which includes removing code
protection).
Access to program memory allows for checksum calcu-
lation. The values written to program memory do not
need to be valid instructions. Therefore, up to 14-bit
numbers can be stored in memory for use as calibra-
tion parameters, serial numbers, packed 7-bit ASCII,
etc. Executing a program memory location containing
data that form an invalid instruction, results in the exe-
cution of a NOPinstruction.
The FLASH program memory allows non-intrusive
read access, but write operations cause the device to
stop executing instructions, until the write completes.
When interfacing to the program memory, the
EEADRH:EEADR registers form a two-byte word,
which holds the 13-bit address of the memory location
being accessed. The register combination of
EEDATH:EEDATA holds the 14-bit data for writes, or
reflects the value of program memory after a read oper-
ation. Just as in EEPROM data memory accesses, the
value of the EEADRH:EEADR registers must be within
the valid range of program memory, depending on the
device: 0000h to 1FFFh for the PIC16F873/874, or
0000h to 3FFFh for the PIC16F876/877. Addresses
outside of this range do not wrap around to 0000h (i.e.,
4000h does not map to 0000h on the PIC16F877).
The EEPROM Data memory is rated for high erase/
write cycles (specification D120). The FLASH program
memory is rated much lower (specification D130),
because EEPROM data memory can be used to store
frequently updated values. An on-chip timer controls
the write time and it will vary with voltage and tempera-
ture, as well as from chip to chip. Please refer to the
specifications for exact limits (specifications D122 and
D133).
A byte or word write automatically erases the location
and writes the new value (erase before write). Writing
to EEPROM data memory does not impact the opera-
tion of the device. Writing to program memory will
cease the execution of instructions until the write is
complete. The program memory cannot be accessed
during the write. During the write operation, the oscilla-
tor continues to run, the peripherals continue to func-
tion and interrupt events will be detected and
essentially “queued” until the write is complete. When
the write completes, the next instruction in the pipeline
is executed and the branch to the interrupt vector will
take place, if the interrupt is enabled and occurred dur-
ing the write.
4.1
EECON1 and EECON2 Registers
The EECON1 register is the control register for config-
uring and initiating the access. The EECON2 register is
not a physically implemented register, but is used
exclusively in the memory write sequence to prevent
inadvertent writes.
There are many bits used to control the read and write
operations to EEPROM data and FLASH program
memory. The EEPGD bit determines if the access will
be a program or data memory access. When clear, any
subsequent operations will work on the EEPROM data
memory. When set, all subsequent operations will
operate in the program memory.
Read and write access to both memories take place
indirectly through a set of Special Function Registers
(SFR). The six SFRs used are:
Read operations only use one additional bit, RD, which
initiates the read operation from the desired memory
location. Once this bit is set, the value of the desired
memory location will be available in the data registers.
This bit cannot be cleared by firmware. It is automati-
cally cleared at the end of the read operation. For
EEPROM data memory reads, the data will be avail-
able in the EEDATA register in the very next instruction
cycle after the RD bit is set. For program memory
reads, the data will be loaded into the
EEDATH:EEDATA registers, following the second
instruction after the RD bit is set.
• EEDATA
• EEDATH
• EEADR
• EEADRH
• EECON1
• EECON2
1998-2013 Microchip Technology Inc.
DS30292D-page 41
PIC16F87X
Write operations have two control bits, WR and WREN,
and two status bits, WRERR and EEIF. The WREN bit
is used to enable or disable the write operation. When
WREN is clear, the write operation will be disabled.
Therefore, the WREN bit must be set before executing
a write operation. The WR bit is used to initiate the write
operation. It also is automatically cleared at the end of
the write operation. The interrupt flag EEIF is used to
determine when the memory write completes. This flag
must be cleared in software before setting the WR bit.
For EEPROM data memory, once the WREN bit and
the WR bit have been set, the desired memory address
in EEADR will be erased, followed by a write of the data
in EEDATA. This operation takes place in parallel with
the microcontroller continuing to execute normally.
When the write is complete, the EEIF flag bit will be set.
For program memory, once the WREN bit and the WR
bit have been set, the microcontroller will cease to exe-
cute instructions. The desired memory location pointed
to by EEADRH:EEADR will be erased. Then, the data
value in EEDATH:EEDATA will be programmed. When
complete, the EEIF flag bit will be set and the microcon-
troller will continue to execute code.
The WRERR bit is used to indicate when the
PIC16F87X device has been reset during a write oper-
ation. WRERR should be cleared after Power-on
Reset. Thereafter, it should be checked on any other
RESET. The WRERR bit is set when a write operation
is interrupted by a MCLR Reset, or a WDT Time-out
Reset, during normal operation. In these situations, fol-
lowing a RESET, the user should check the WRERR bit
and rewrite the memory location, if set. The contents of
the data registers, address registers and EEPGD bit
are not affected by either MCLR Reset, or WDT Time-
out Reset, during normal operation.
REGISTER 4-1:
EECON1 REGISTER (ADDRESS 18Ch)
R/W-x
U-0
—
U-0
—
U-0
—
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
EEPGD
WRERR
bit 7
bit 0
bit 7
EEPGD: Program/Data EEPROM Select bit
1= Accesses program memory
0= Accesses data memory
(This bit cannot be changed while a read or write operation is in progress)
bit 6-4
bit 3
Unimplemented: Read as '0'
WRERR: EEPROM Error Flag bit
1= A write operation is prematurely terminated
(any MCLR Reset or any WDT Reset during normal operation)
0= The write operation completed
bit 2
bit 1
WREN: EEPROM Write Enable bit
1= Allows write cycles
0= Inhibits write to the EEPROM
WR: Write Control bit
1= Initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.)
0= Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read. (RD is cleared in hardware. The RD bit can only be set (not
cleared) in software.)
0= Does not initiate an EEPROM read
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS30292D-page 42
1998-2013 Microchip Technology Inc.
PIC16F87X
The steps to write to EEPROM data memory are:
4.2
Reading the EEPROM Data
Memory
1. If step 10 is not implemented, check the WR bit
to see if a write is in progress.
Reading EEPROM data memory only requires that the
desired address to access be written to the EEADR
register and clear the EEPGD bit. After the RD bit is set,
data will be available in the EEDATA register on the
very next instruction cycle. EEDATA will hold this value
until another read operation is initiated or until it is writ-
ten by firmware.
2. Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the PIC16F87X device.
3. Write the 8-bit data value to be programmed in
the EEDATA register.
4. Clear the EEPGD bit to point to EEPROM data
memory.
The steps to reading the EEPROM data memory are:
5. Set the WREN bit to enable program operations.
6. Disable interrupts (if enabled).
1. Write the address to EEDATA. Make sure that
the address is not larger than the memory size
of the PIC16F87X device.
7. Execute the special five instruction sequence:
• Write 55h to EECON2 in two steps (first to W,
then to EECON2)
2. Clear the EEPGD bit to point to EEPROM data
memory.
• Write AAh to EECON2 in two steps (first to
W, then to EECON2)
3. Set the RD bit to start the read operation.
4. Read the data from the EEDATA register.
• Set the WR bit
8. Enable interrupts (if using interrupts).
EXAMPLE 4-1:
EEPROM DATA READ
9. Clear the WREN bit to disable program opera-
tions.
BSF
BCF
STATUS, RP1
STATUS, RP0
ADDR, W
;
;Bank 2
;Write address
;to read from
;Bank 3
MOVF
MOVWF EEADR
BSF
BCF
BSF
BCF
10. At the completion of the write cycle, the WR bit
is cleared and the EEIF interrupt flag bit is set.
(EEIF must be cleared by firmware.) If step 1 is
not implemented, then firmware should check
for EEIF to be set, or WR to clear, to indicate the
end of the program cycle.
STATUS, RP0
EECON1, EEPGD ;Point to Data memory
EECON1, RD
STATUS, RP0
;Start read operation
;Bank 2
MOVF
EEDATA, W
;W = EEDATA
EXAMPLE 4-2:
EEPROM DATA WRITE
BSF
BSF
STATUS, RP1
STATUS, RP0
;
;Bank 3
;Wait for
;write to finish
;Bank 2
;Address to
;write to
;Data to
;write
;Bank 3
4.3
Writing to the EEPROM Data
Memory
BTFSC EECON1, WR
GOTO
BCF
MOVF
MOVWF EEADR
MOVF
MOVWF EEDATA
BSF
BCF
BSF
$-1
STATUS, RP0
ADDR, W
There are many steps in writing to the EEPROM data
memory. Both address and data values must be written
to the SFRs. The EEPGD bit must be cleared, and the
WREN bit must be set, to enable writes. The WREN bit
should be kept clear at all times, except when writing to
the EEPROM data. The WR bit can only be set if the
WREN bit was set in a previous operation, i.e., they
both cannot be set in the same operation. The WREN
bit should then be cleared by firmware after the write.
Clearing the WREN bit before the write actually com-
pletes will not terminate the write in progress.
VALUE, W
STATUS, RP0
EECON1, EEPGD ;Point to Data memory
EECON1, WREN ;Enable writes
;Only disable interrupts
BCF
INTCON, GIE
;if already enabled,
;otherwise discard
;Write 55h to
;EECON2
;Write AAh to
MOVLW 0x55
MOVWF EECON2
MOVLW 0xAA
MOVWF EECON2
BSF
BSF
BCF
Writes to EEPROM data memory must also be pref-
aced with a special sequence of instructions, that pre-
vent inadvertent write operations. This is a sequence of
five instructions that must be executed without interrup-
tions. The firmware should verify that a write is not in
progress, before starting another cycle.
;EECON2
EECON1, WR
;Start write operation
;Only enable interrupts
;if using interrupts,
;otherwise discard
INTCON, GIE
EECON1, WREN ;Disable writes
1998-2013 Microchip Technology Inc.
DS30292D-page 43
PIC16F87X
4.4
Reading the FLASH Program
Memory
4.5
Writing to the FLASH Program
Memory
Reading FLASH program memory is much like that of
EEPROM data memory, only two NOPinstructions must
be inserted after the RD bit is set. These two instruction
cycles that the NOP instructions execute, will be used
by the microcontroller to read the data out of program
Writing to FLASH program memory is unique, in that
the microcontroller does not execute instructions while
programming is taking place. The oscillator continues
to run and all peripherals continue to operate and
queue interrupts, if enabled. Once the write operation
completes (specification D133), the processor begins
executing code from where it left off. The other impor-
tant difference when writing to FLASH program mem-
ory, is that the WRT configuration bit, when clear,
prevents any writes to program memory (see Table 4-1).
memory
and
insert
the
value
into
the
EEDATH:EEDATA registers. Data will be available fol-
lowing the second NOP instruction. EEDATH and
EEDATA will hold their value until another read opera-
tion is initiated, or until they are written by firmware.
The steps to reading the FLASH program memory are:
Just like EEPROM data memory, there are many steps
in writing to the FLASH program memory. Both address
and data values must be written to the SFRs. The
EEPGD bit must be set, and the WREN bit must be set
to enable writes. The WREN bit should be kept clear at
all times, except when writing to the FLASH Program
memory. The WR bit can only be set if the WREN bit
was set in a previous operation, i.e., they both cannot
be set in the same operation. The WREN bit should
then be cleared by firmware after the write. Clearing the
WREN bit before the write actually completes will not
terminate the write in progress.
1. Write the address to EEADRH:EEADR. Make
sure that the address is not larger than the mem-
ory size of the PIC16F87X device.
2. Set the EEPGD bit to point to FLASH program
memory.
3. Set the RD bit to start the read operation.
4. Execute two NOPinstructions to allow the micro-
controller to read out of program memory.
5. Read the data from the EEDATH:EEDATA
registers.
Writes to program memory must also be prefaced with
a special sequence of instructions that prevent inad-
vertent write operations. This is a sequence of five
instructions that must be executed without interruption
for each byte written. These instructions must then be
followed by two NOPinstructions to allow the microcon-
troller to setup for the write operation. Once the write is
complete, the execution of instructions starts with the
instruction after the second NOP.
EXAMPLE 4-3:
FLASH PROGRAM READ
BSF
STATUS, RP1
;
;Bank 2
;Write the
;address bytes
;for the desired
;address to read
;Bank 3
BCF
MOVF
STATUS, RP0
ADDRL, W
MOVWF EEADR
MOVF
ADDRH,W
MOVWF EEADRH
BSF
BSF
BSF
NOP
NOP
BCF
MOVF
STATUS, RP0
EECON1, EEPGD ;Point to Program memory
EECON1, RD
The steps to write to program memory are:
;Start read operation
;Required two NOPs
;
;Bank 2
;DATAL = EEDATA
1. Write the address to EEADRH:EEADR. Make
sure that the address is not larger than the mem-
ory size of the PIC16F87X device.
STATUS, RP0
EEDATA, W
2. Write the 14-bit data value to be programmed in
the EEDATH:EEDATA registers.
MOVWF DATAL
;
MOVF
EEDATH,W
;DATAH = EEDATH
;
MOVWF DATAH
3. Set the EEPGD bit to point to FLASH program
memory.
4. Set the WREN bit to enable program operations.
5. Disable interrupts (if enabled).
6. Execute the special five instruction sequence:
• Write 55h to EECON2 in two steps (first to W,
then to EECON2)
• Write AAh to EECON2 in two steps (first to W,
then to EECON2)
• Set the WR bit
7. Execute two NOPinstructions to allow the micro-
controller to setup for write operation.
8. Enable interrupts (if using interrupts).
9. Clear the WREN bit to disable program
operations.
DS30292D-page 44
1998-2013 Microchip Technology Inc.
PIC16F87X
At the completion of the write cycle, the WR bit is
cleared and the EEIF interrupt flag bit is set. (EEIF
must be cleared by firmware.) Since the microcontroller
does not execute instructions during the write cycle, the
firmware does not necessarily have to check either
EEIF, or WR, to determine if the write had finished.
4.7
Protection Against Spurious
Writes
There are conditions when the device may not want to
write to the EEPROM data memory or FLASH program
memory. To protect against these spurious write condi-
tions, various mechanisms have been built into the
PIC16F87X devices. On power-up, the WREN bit is
cleared and the Power-up Timer (if enabled) prevents
writes.
EXAMPLE 4-4:
FLASH PROGRAM WRITE
BSF
BCF
MOVF
STATUS, RP1
STATUS, RP0
ADDRL, W
;
;Bank 2
;Write address
The write initiate sequence, and the WREN bit
together, help prevent any accidental writes during
brown-out, power glitches, or firmware malfunction.
MOVWF EEADR
;of desired
MOVF
MOVWF EEADRH
ADDRH, W
;program memory
;location
MOVF
MOVWF EEDATA
VALUEL, W
;Write value to
;program at
4.8
Operation While Code Protected
MOVF
MOVWF EEDATH
BSF
BSF
BSF
VALUEH, W
;desired memory
;location
;Bank 3
The PIC16F87X devices have two code protect mecha-
nisms, one bit for EEPROM data memory and two bits for
FLASH program memory. Data can be read and written
to the EEPROM data memory, regardless of the state of
the code protection bit, CPD. When code protection is
enabled and CPD cleared, external access via ICSP is
disabled, regardless of the state of the program memory
code protect bits. This prevents the contents of EEPROM
data memory from being read out of the device.
STATUS, RP0
EECON1, EEPGD ;Point to Program memory
EECON1, WREN ;Enable writes
;Only disable interrupts
BCF
INTCON, GIE
;if already enabled,
;otherwise discard
;Write 55h to
;EECON2
;Write AAh to
MOVLW 0x55
MOVWF EECON2
MOVLW 0xAA
MOVWF EECON2
BSF
NOP
NOP
The state of the program memory code protect bits,
CP0 and CP1, do not affect the execution of instruc-
tions out of program memory. The PIC16F87X devices
can always read the values in program memory,
regardless of the state of the code protect bits. How-
ever, the state of the code protect bits and the WRT bit
will have different effects on writing to program mem-
ory. Table 4-1 shows the effect of the code protect bits
and the WRT bit on program memory.
;EECON2
EECON1, WR
;Start write operation
;Two NOPs to allow micro
;to setup for write
;Only enable interrupts
;if using interrupts,
;otherwise discard
BSF
BCF
INTCON, GIE
EECON1, WREN ;Disable writes
Once code protection has been enabled for either
EEPROM data memory or FLASH program memory,
only a full erase of the entire device will disable code
protection.
4.6
Write Verify
The PIC16F87X devices do not automatically verify the
value written during a write operation. Depending on
the application, good programming practice may dic-
tate that the value written to memory be verified against
the original value. This should be used in applications
where excessive writes can stress bits near the speci-
fied endurance limits.
1998-2013 Microchip Technology Inc.
DS30292D-page 45
PIC16F87X
4.9
FLASH Program Memory Write
Protection
The configuration word contains a bit that write protects
the FLASH program memory, called WRT. This bit can
only be accessed when programming the PIC16F87X
device via ICSP. Once write protection is enabled, only
an erase of the entire device will disable it. When
enabled, write protection prevents any writes to FLASH
program memory. Write protection does not affect pro-
gram memory reads.
TABLE 4-1:
READ/WRITE STATE OF INTERNAL FLASH PROGRAM MEMORY
Configuration Bits
Internal
Read
Internal
Write
Memory Location
ICSP Read
ICSP Write
CP1
CP0
WRT
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
x
0
0
1
1
0
0
1
1
0
1
All program memory
Unprotected areas
Protected areas
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
No
No
No
Yes
No
No
Yes
No
Yes
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Unprotected areas
Protected areas
Yes
No
Unprotected areas
Protected areas
Yes
No
Unprotected areas
Protected areas
Yes
No
All program memory
All program memory
Yes
Yes
TABLE 4-2:
REGISTERS ASSOCIATED WITH DATA EEPROM/PROGRAM FLASH
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
10Bh, 18Bh
10Dh
10Fh
10Ch
10Eh
18Ch
18Dh
8Dh
EEADR
EEPROM Address Register, Low Byte
EEPROM Address, High Byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
x--- x000 x--- u000
EEADRH
—
—
—
EEDATA EEPROM Data Register, Low Byte
EEDATH
—
—
—
EEPROM Data Register, High Byte
WRERR WREN
EECON1 EEPGD
—
—
WR
RD
EECON2 EEPROM Control Register2 (not a physical register)
—
—
PIE2
PIR2
—
—
(1)
(1)
—
—
EEIE
EEIF
BCLIE
BCLIF
—
—
—
—
CCP2IE
CCP2IF
-r-0 0--0 -r-0 0--0
-r-0 0--0 -r-0 0--0
0Dh
Legend: x= unknown, u= unchanged, r= reserved, -= unimplemented, read as '0'.
Shaded cells are not used during FLASH/EEPROM access.
Note 1: These bits are reserved; always maintain these bits clear.
DS30292D-page 46
1998-2013 Microchip Technology Inc.
PIC16F87X
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment either on every rising, or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit, T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed in detail in Section 5.2.
5.0
TIMER0 MODULE
The Timer0 module timer/counter has the following fea-
tures:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The pres-
caler is not readable or writable. Section 5.3 details the
operation of the prescaler.
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
5.1
Timer0 Interrupt
Additional information on the Timer0 module is avail-
able in the PIC® MCU Mid-Range Family Reference
Manual (DS33023).
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module Interrupt Ser-
vice Routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP, since the timer is shut-off during SLEEP.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0 mod-
ule will increment every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
FIGURE 5-1:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
CLKOUT (= FOSC/4)
8
M
U
X
1
0
0
1
M
U
X
RA4/T0CKI
pin
SYNC
2
TMR0 Reg
Cycles
T0SE
T0CS
Set Flag Bit T0IF
on Overflow
PSA
PRESCALER
0
1
8-bit Prescaler
M
U
X
Watchdog
Timer
8
8 - to - 1MUX
PS2:PS0
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
1998-2013 Microchip Technology Inc.
DS30292D-page 47
PIC16F87X
Timer0 module means that there is no prescaler for the
Watchdog Timer, and vice-versa. This prescaler is not
readable or writable (see Figure 5-1).
5.2
Using Timer0 with an External
Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF1, MOVWF1,
BSF1,x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
Note: Writing to TMR0, when the prescaler is
assigned to Timer0, will clear the prescaler
count, but will not change the prescaler
assignment.
5.3
Prescaler
There is only one prescaler available, which is mutually
exclusively shared between the Timer0 module and the
Watchdog Timer. A prescaler assignment for the
REGISTER 5-1:
OPTION_REG REGISTER
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
bit 7
bit 0
bit 7
bit 6
bit 5
RBPU
INTEDG
T0CS: TMR0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
Note: To avoid an unintended device RESET, the instruction sequence shown in the PIC® MCU Mid-Range Fam-
ily Reference Manual (DS33023) must be executed when changing the prescaler assignment from Timer0
to the WDT. This sequence must be followed even if the WDT is disabled.
DS30292D-page 48
1998-2013 Microchip Technology Inc.
PIC16F87X
TABLE 5-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on: Value on
Address
Name
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR,
BOR
all other
RESETS
xxxx xxxx uuuu uuuu
0000 000x 0000 000u
01h,101h
TMR0
INTCON
Timer0 Module’s Register
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
0Bh,8Bh,
10Bh,18Bh
1111 1111 1111 1111
81h,181h
OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1
PS0
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'.
Shaded cells are not used by Timer0.
1998-2013 Microchip Technology Inc.
DS30292D-page 49
PIC16F87X
NOTES:
DS30292D-page 50
1998-2013 Microchip Technology Inc.
PIC16F87X
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
6.0
TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L), which are
readable and writable. The TMR1 Register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 Interrupt, if enabled,
is generated on overflow, which is latched in interrupt
flag bit TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit TMR1IE (PIE1<0>).
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Timer1 also has an internal “RESET input”. This
RESET can be generated by either of the two CCP
modules (Section 8.0). Register 6-1 shows the Timer1
control register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC<1:0> value is
ignored, and these pins read as ‘0’.
Timer1 can operate in one of two modes:
• As a timer
• As a counter
Additional information on timer modules is available in
the PIC® MCU Mid-Range Family Reference Manual
(DS33023).
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
REGISTER 6-1:
T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 0
bit 7
bit 7-6
bit 5-4
Unimplemented: Read as '0'
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable Control bit
1= Oscillator is enabled
0= Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain)
T1SYNC: Timer1 External Clock Input Synchronization Control bit
When TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
1998-2013 Microchip Technology Inc.
DS30292D-page 51
PIC16F87X
6.1
Timer1 Operation in Timer Mode
6.2
Timer1 Counter Operation
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect, since the internal clock is
always in sync.
Timer1 may operate in either a Synchronous, or an
Asynchronous mode, depending on the setting of the
TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.
FIGURE 6-1:
TIMER1 INCREMENTING EDGE
T1CKI
(Default High)
T1CKI
(Default Low)
Note: Arrows indicate counter increments.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple-counter.
6.3
Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2, when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when
bit T1OSCEN is cleared.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut-off. The
prescaler, however, will continue to increment.
FIGURE 6-2:
TIMER1 BLOCK DIAGRAM
Set Flag bit
TMR1IF on
Overflow
Synchronized
0
TMR1
Clock Input
TMR1L
TMR1H
1
TMR1ON
On/Off
T1SYNC
T1OSC
RC0/T1OSO/T1CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
FOSC/4
Internal
Clock
0
(1)
(2)
Oscillator
RC1/T1OSI/CCP2
2
Q Clock
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
DS30292D-page 52
1998-2013 Microchip Technology Inc.
PIC16F87X
TABLE 6-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
6.4
Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt-on-overflow, which will wake-up
the processor. However, special precautions in soft-
ware are needed to read/write the timer (Section 6.4.1).
Osc Type
Freq.
C1
C2
LP
32 kHz
100 kHz
200 kHz
33 pF
15 pF
15 pF
33 pF
15 pF
15 pF
These values are for design guidance only.
Crystals Tested:
In Asynchronous Counter mode, Timer1 cannot be
used as a time-base for capture or compare opera-
tions.
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
100 kHz
200 kHz
Epson C-2 100.00 KC-P ± 20 PPM
STD XTL 200.000 kHz ± 20 PPM
6.4.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Note 1: Higher capacitance increases the stability
of oscillator, but also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external components.
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock, will guarantee a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself, poses certain problems, since
the timer may overflow between the reads.
6.6
Resetting Timer1 using a CCP
Trigger Output
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
If the CCP1 or CCP2 module is configured in Compare
mode to generate “special event trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
a
Timer1.
Note: The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
Reading the 16-bit value requires some care. Exam-
ples 12-2 and 12-3 in the PIC® MCU Mid-Range Family
Reference Manual (DS33023) show how to read and
write Timer1 when it is running in Asynchronous mode.
Timer1 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
6.5
Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator, rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for use with a 32 kHz crystal. Table 6-1 shows the
capacitor selection for the Timer1 oscillator.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL regis-
ter pair effectively becomes the period register for
Timer1.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
1998-2013 Microchip Technology Inc.
DS30292D-page 53
PIC16F87X
6.7
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
6.8
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
TMR1H and TMR1L registers are not reset to 00h on a
POR, or any other RESET, except by the CCP1 and
CCP2 special event triggers.
T1CON register is reset to 00h on a Power-on Reset,
or a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other RESETS, the register
is unaffected.
TABLE 6-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh,
10Bh, 18Bh
0000 000x 0000 000u
INTCON
GIE
PEIE
ADIF
ADIE
T0IE
RCIF
RCIE
INTE
TXIF
TXIE
RBIE
SSPIF
SSPIE
T0IF
INTF
RBIF
0Ch
PIR1
PSPIF(1)
PSPIE(1)
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --uu uuuu
8Ch
PIE1
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
0Fh
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
T1CON T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
10h
—
—
Legend:
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear.
DS30292D-page 54
1998-2013 Microchip Technology Inc.
PIC16F87X
Register 7-1 shows the Timer2 control register.
7.0
TIMER2 MODULE
Additional information on timer modules is available in
the PIC® MCU Mid-Range Family Reference Manual
(DS33023).
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mode of the CCP module(s). The TMR2 reg-
ister is readable and writable, and is cleared on any
device RESET.
FIGURE 7-1:
TIMER2 BLOCK DIAGRAM
Sets Flag
bit TMR2IF
The input clock (FOSC/4) has a prescale option of 1:1,
TMR2
Output(1)
RESET
1:4,
or
1:16,
selected
by
control
bits
T2CKPS1:T2CKPS0 (T2CON<1:0>).
Prescaler
1:1, 1:4, 1:16
TMR2 Reg
FOSC/4
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
Postscaler
1:1 to 1:16
2
Comparator
EQ
T2CKPS1:
T2CKPS0
4
PR2 Reg
T2OUTPS3:
T2OUTPS0
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
Note 1:TMR2 register output can be software selected by the
SSP module as a baud clock.
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON<2>), to minimize power consumption.
REGISTER 7-1:
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as '0'
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
0010= 1:3 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
1998-2013 Microchip Technology Inc.
DS30292D-page 55
PIC16F87X
7.1
Timer2 Prescaler and Postscaler
7.2
Output of TMR2
The prescaler and postscaler counters are cleared
when any of the following occurs:
The output of TMR2 (before the postscaler) is fed to the
SSP module, which optionally uses it to generate shift
clock.
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (POR, MCLR Reset, WDT
Reset, or BOR)
TMR2 is not cleared when T2CON is written.
TABLE 7-1:
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh,
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
10Bh,18Bh
0Ch
PIR1
PSPIF(1)
PSPIE(1)
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
0000 0000 0000 0000
8Ch
PIE1
11h
TMR2
T2CON
PR2
Timer2 Module’s Register
12h
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h
Timer2 Period Register
1111 1111 1111 1111
Legend:
x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear.
DS30292D-page 56
1998-2013 Microchip Technology Inc.
PIC16F87X
CCP2 Module:
8.0
CAPTURE/COMPARE/PWM
MODULES
Capture/Compare/PWM Register2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. The special event trigger is
generated by a compare match and will reset Timer1
and start an A/D conversion (if the A/D module is
enabled).
Each Capture/Compare/PWM (CCP) module contains
a 16-bit register which can operate as a:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
Additional information on CCP modules is available in
the PIC® MCU Mid-Range Family Reference Manual
(DS33023) and in application note AN594, “Using the
CCP Modules” (DS00594).
Both the CCP1 and CCP2 modules are identical in
operation, with the exception being the operation of the
special event trigger. Table 8-1 and Table 8-2 show the
resources and interactions of the CCP module(s). In
the following sections, the operation of a CCP module
is described with respect to CCP1. CCP2 operates the
same as CCP1, except where noted.
TABLE 8-1:
CCP MODE - TIMER
RESOURCES REQUIRED
CCP1 Module:
CCP Mode
Capture
Compare
PWM
Timer Resource
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is
generated by a compare match and will reset Timer1.
Timer1
Timer1
Timer2
TABLE 8-2:
INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
Compare
PWM
Capture
Same TMR1 time-base
Compare The compare should be configured for the special event trigger, which clears TMR1
Compare The compare(s) should be configured for the special event trigger, which clears TMR1
PWM
The PWMs will have the same frequency and update rate (TMR2 interrupt)
None
PWM
Capture
PWM
Compare None
1998-2013 Microchip Technology Inc.
DS30292D-page 57
PIC16F87X
REGISTER 8-1:
CCP1CON REGISTER/CCP2CON REGISTER (ADDRESS: 17h/1Dh)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CCPxX
CCPxY
CCPxM3
CCPxM2 CCPxM1 CCPxM0
bit 0
bit 7
bit 7-6
bit 5-4
Unimplemented: Read as '0'
CCPxX:CCPxY: PWM Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCPx Mode Select bits
0000= Capture/Compare/PWM disabled (resets CCPx module)
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, set output on match (CCPxIF bit is set)
1001= Compare mode, clear output on match (CCPxIF bit is set)
1010= Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is
unaffected)
1011= Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1
resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is
enabled)
11xx= PWM mode
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS30292D-page 58
1998-2013 Microchip Technology Inc.
PIC16F87X
8.1.2
TIMER1 MODE SELECTION
8.1
Capture Mode
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as one of the fol-
lowing:
• Every falling edge
• Every rising edge
8.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF, following any such
change in operating mode.
• Every 4th rising edge
• Every 16th rising edge
The type of event is configured by control bits
CCP1M3:CCP1M0 (CCPxCON<3:0>). When a cap-
ture is made, the interrupt request flag bit CCP1IF
(PIR1<2>) is set. The interrupt flag must be cleared in
software. If another capture occurs before the value in
register CCPR1 is read, the old captured value is over-
written by the new value.
8.1.4
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. Any RESET will clear
the prescaler counter.
8.1.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
Note: If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a cap-
ture condition.
FIGURE 8-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
EXAMPLE 8-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
; Turn CCP module off
Set Flag bit CCP1IF
(PIR1<2>)
RC2/CCP1
pin
CLRF
CCP1CON
Prescaler
MOVLW
NEW_CAPT_PS ; Load the W reg with
; the new prescaler
1, 4, 16
CCPR1H
CCPR1L
; move value and CCP ON
MOVWF
CCP1CON
; Load CCP1CON with this
; value
Capture
Enable
and
edge detect
TMR1H
TMR1L
CCP1CON<3:0>
Qs
1998-2013 Microchip Technology Inc.
DS30292D-page 59
PIC16F87X
8.2.2
TIMER1 MODE SELECTION
8.2
Compare Mode
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
8.2.3
SOFTWARE INTERRUPT MODE
• Remains unchanged
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set, causing
a CCP interrupt (if enabled).
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
8.2.4
SPECIAL EVENT TRIGGER
FIGURE 8-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
Special Event Trigger
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
Set Flag bit CCP1IF
(PIR1<2>)
RC2/CCP1
pin
CCPR1H CCPR1L
Note: The special event trigger from the
CCP1and CCP2 modules will not set inter-
rupt flag bit TMR1IF (PIR1<0>).
Q
S
R
Output
Logic
Comparator
Match
TRISC<2>
Output Enable
TMR1H TMR1L
CCP1CON<3:0>
Mode Select
8.2.1
CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the PORTC I/O
data latch.
DS30292D-page 60
1998-2013 Microchip Technology Inc.
PIC16F87X
8.3.1
PWM PERIOD
8.3
PWM Mode (PWM)
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
In Pulse Width Modulation mode, the CCPx pin pro-
duces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
Figure 8-3 shows a simplified block diagram of the
CCP module in PWM mode.
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 8.3.3.
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
FIGURE 8-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Note: The Timer2 postscaler (see Section 7.1) is
not used in the determination of the PWM
frequency. The postscaler could be used
to have a servo update rate at a different
frequency than the PWM output.
CCP1CON<5:4>
Duty Cycle Registers
CCPR1L
8.3.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
CCPR1H (Slave)
Comparator
RC2/CCP1
Q
R
S
(Note 1)
TMR2
PWM duty cycle =(CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 prescale value)
TRISC<2>
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
Note 1: The 8-bit timer is concatenated with 2-bit internal Q
clock, or 2 bits of the prescaler, to create 10-bit time-
base.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitch-free PWM operation.
A PWM output (Figure 8-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
When the CCPR1H and 2-bit latch match TMR2, con-
catenated with an internal 2-bit Q clock, or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
FIGURE 8-4:
PWM OUTPUT
The maximum PWM resolution (bits) for a given PWM
frequency is given by the formula:
Period
FOSC
log( )
FPWM
Resolution
bits
=
Duty Cycle
log(2)
TMR2 = PR2
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TMR2 = Duty Cycle
TMR2 = PR2
1998-2013 Microchip Technology Inc.
DS30292D-page 61
PIC16F87X
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
8.3.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
1. Set the PWM period by writing to the PR2
register.
5. Configure the CCP1 module for PWM operation.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
TABLE 8-3:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
1.22 kHz 4.88 kHz 19.53 kHz
78.12kHz
156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
0xFFh
10
4
1
1
0x3Fh
8
1
0x1Fh
7
1
0xFFh
10
0xFFh
10
0x17h
5.5
Maximum Resolution (bits)
TABLE 8-4:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Value on:
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
all other
RESETS
0Bh,8Bh,
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000u
10Bh, 18Bh
(1)
0Ch
0Dh
8Ch
8Dh
87h
0Eh
0Fh
10h
15h
16h
17h
1Bh
1Ch
1Dh
PIR1
PSPIF
—
ADIF
—
RCIF
—
TXIF
—
SSPIF
—
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR2
—
—
(1)
PIE1
PSPIE
—
ADIE
—
RCIE
—
TXIE
—
SSPIE
—
PIE2
—
—
CCP2IE ---- ---0 ---- ---0
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TRISC
TMR1L
TMR1H
T1CON
PORTC Data Direction Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCPR1L Capture/Compare/PWM Register1 (LSB)
CCPR1H Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1CON
—
—
CCP1X
CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCPR2L Capture/Compare/PWM Register2 (LSB)
CCPR2H Capture/Compare/PWM Register2 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2CON
—
—
CCP2X
CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.
Note 1: The PSP is not implemented on the PIC16F873/876; always maintain these bits clear.
DS30292D-page 62
1998-2013 Microchip Technology Inc.
PIC16F87X
TABLE 8-5:
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on: Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
all other
RESETS
0Bh,8Bh,
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
10Bh, 18Bh
(1)
0Ch
0Dh
8Ch
8Dh
87h
11h
92h
12h
15h
16h
17h
1Bh
1Ch
1Dh
PIR1
PSPIF
—
ADIF
—
RCIF
—
TXIF
—
SSPIF
—
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR2
—
—
(1)
PIE1
PSPIE
—
ADIE
—
RCIE
—
TXIE
—
SSPIE
—
PIE2
—
—
CCP2IE ---- ---0 ---- ---0
1111 1111 1111 1111
TRISC
TMR2
PR2
PORTC Data Direction Register
Timer2 Module’s Register
0000 0000 0000 0000
Timer2 Module’s Period Register
1111 1111 1111 1111
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCPR1L Capture/Compare/PWM Register1 (LSB)
CCPR1H Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1CON
—
—
CCP1X
CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCPR2L Capture/Compare/PWM Register2 (LSB)
CCPR2H Capture/Compare/PWM Register2 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2CON
—
—
CCP2X
CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear.
1998-2013 Microchip Technology Inc.
DS30292D-page 63
PIC16F87X
NOTES:
DS30292D-page 64
1998-2013 Microchip Technology Inc.
PIC16F87X
9.0
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
Figure 9-1 shows a block diagram for the SPI mode,
while Figure 9-5 and Figure 9-9 show the block dia-
grams for the two different I2C modes of operation.
The Application Note AN734, “Using the PIC® MCU
SSP for Slave I2CTM Communication” describes the
slave operation of the MSSP module on the
PIC16F87X devices. AN735, “Using the PIC® MCU
MSSP Module for I2CTM Communications” describes
the master operation of the MSSP module on the
PIC16F87X devices.
1998-2013 Microchip Technology Inc.
DS30292D-page 65
PIC16F87X
REGISTER 9-1:
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 94h)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
SMP: Sample bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in slave mode
2
In I C Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high speed mode (400 kHz)
bit 6
CKE: SPI Clock Edge Select (Figure 9-2, Figure 9-3 and Figure 9-4)
SPI mode:
For CKP = 0
1= Data transmitted on rising edge of SCK
0= Data transmitted on falling edge of SCK
For CKP = 1
1= Data transmitted on falling edge of SCK
0= Data transmitted on rising edge of SCK
2
In I C Master or Slave mode:
1= Input levels conform to SMBus spec
2
0= Input levels conform to I C specs
2
bit 5
bit 4
D/A: Data/Address bit (I C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: STOP bit
2
(I C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1= Indicates that a STOP bit has been detected last (this bit is '0' on RESET)
0= STOP bit was not detected last
bit 3
bit 2
S: START bit
2
(I C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1= Indicates that a START bit has been detected last (this bit is '0' on RESET)
0= START bit was not detected last
2
R/W: Read/Write bit Information (I C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next START bit, STOP bit or not ACK bit.
2
In I C Slave mode:
1= Read
0= Write
2
In I C Master mode:
1= Transmit is in progress
0= Transmit is not in progress
Logical OR of this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode.
2
bit 1
bit
UA: Update Address (10-bit I C mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
2
Receive (SPI and I C modes):
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
2
Transmit (I C mode only):
1= Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full
0= Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS30292D-page 66
1998-2013 Microchip Technology Inc.
PIC16F87X
REGISTER 9-2:
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
Master mode:
1= A write to SSPBUF was attempted while the I2C conditions were not valid
0= No collision
Slave mode:
1= SSPBUF register is written while still transmitting the previous word (must be cleared in
software)
0= No collision
bit 6
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1= A new byte is received while SSPBUF holds previous data. Data in SSPSR is lost on overflow. In Slave
mode, the user must read the SSPBUF, even if only transmitting data, to avoid overflows. In Master
mode, the overflow bit is not set, since each operation is initiated by writing to the SSPBUF register.
(Must be cleared in software.)
0= No overflow
2
In I C mode:
1= A byte is received while the SSPBUF is holding the previous byte. SSPOV is a "don’t care" in Transmit
mode. (Must be cleared in software.)
0= No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In SPI mode,
When enabled, these pins must be properly configured as input or output
1= Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0= Disables serial port and configures these pins as I/O port pins
2
In I C mode,
When enabled, these pins must be properly configured as input or output
1= Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0= Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1= Idle state for clock is a high level
0= Idle state for clock is a low level
2
In I C Slave mode:
SCK release control
1= Enable clock
0= Holds clock low (clock stretch). (Used to ensure data setup time.)
2
In I C Master mode:
Unused in this mode
bit 3-0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000= SPI Master mode, clock = FOSC/4
0001= SPI Master mode, clock = FOSC/16
0010= SPI Master mode, clock = FOSC/64
0011= SPI Master mode, clock = TMR2 output/2
0100= SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101= SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
2
0110= I C Slave mode, 7-bit address
2
0111= I C Slave mode, 10-bit address
2
1000= I C Master mode, clock = FOSC / (4 * (SSPADD+1))
2
1011= I C Firmware Controlled Master mode (slave idle)
2
1110= I C Firmware Controlled Master mode, 7-bit address with START and STOP bit interrupts enabled
2
1111= I C Firmware Controlled Master mode, 10-bit address with START and STOP bit interrupts enabled
1001, 1010, 1100, 1101= Reserved
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
1998-2013 Microchip Technology Inc.
DS30292D-page 67
PIC16F87X
REGISTER 9-3:
SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 91h)
R/W-0
GCEN
R/W-0
R/W-0
R/W-0
R/W-0
RCEN
R/W-0
PEN
R/W-0
RSEN
R/W-0
SEN
ACKSTAT ACKDT
ACKEN
bit 7
bit 0
bit 7
bit 6
GCEN: General Call Enable bit (In I2C Slave mode only)
1= Enable interrupt when a general call address (0000h) is received in the SSPSR
0= General call address disabled
ACKSTAT: Acknowledge Status bit (In I2C Master mode only)
In Master Transmit mode:
1= Acknowledge was not received from slave
0= Acknowledge was received from slave
bit 5
bit 4
ACKDT: Acknowledge Data bit (In I2C Master mode only)
In Master Receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the
end of a receive.
1= Not Acknowledge
0= Acknowledge
ACKEN: Acknowledge Sequence Enable bit (In I2C Master mode only)
In Master Receive mode:
1= Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0= Acknowledge sequence idle
bit 3
bit 2
RCEN: Receive Enable bit (In I2C Master mode only)
1= Enables Receive mode for I2C
0= Receive idle
PEN: STOP Condition Enable bit (In I2C Master mode only)
SCK Release Control:
1= Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0= STOP condition idle
bit 1
bit 0
RSEN: Repeated START Condition Enable bit (In I2C Master mode only)
1= Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by hardware.
0= Repeated START condition idle
SEN: START Condition Enable bit (In I2C Master mode only)
1= Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0= START condition idle
Note:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE
mode, this bit may not be set (no spooling), and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS30292D-page 68
1998-2013 Microchip Technology Inc.
PIC16F87X
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
9.1
SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish communi-
cation, typically three pins are used:
FIGURE 9-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
Internal
Data Bus
Read
Write
Additionally, a fourth pin may be used when in a Slave
mode of operation:
SSPBUF Reg
• Slave Select (SS)
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
SSPSR Reg
Shift
Clock
SDI
bit0
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
SDO
• Data input sample phase
(middle or end of data output time)
Control
Enable
SS
• Clock edge
(output data on rising/falling edge of SCK)
SS
Edge
Select
• Clock Rate (Master mode only)
2
• Slave Select mode (Slave mode only)
Clock Select
Figure 9-4 shows the block diagram of the MSSP mod-
ule when in SPI mode.
SSPM3:SSPM0
SMP:CKE
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
isters, and then set bit SSPEN. This configures the
SDI, SDO, SCK and SS pins as serial port pins. For the
pins to behave as the serial port function, some must
have their data direction bits (in the TRIS register)
appropriately programmed. That is:
4
TMR2 Output
2
2
Edge
Select
TOSC
Prescaler
4, 16, 64
SCK
Data to TX/RX in SSPSR
Data Direction bit
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
cleared
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set and register
ADCON1 (see Section 11.0: A/D Module) must be
set in a way that pin RA5 is configured as a digital
I/O
1998-2013 Microchip Technology Inc.
DS30292D-page 69
PIC16F87X
Figure 9-6, Figure 9-8 and Figure 9-9, where the MSb is
transmitted first. In Master mode, the SPI clock rate (bit
rate) is user programmable to be one of the following:
9.1.1
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 9-5) is to broad-
cast data by the software protocol.
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI
module is only going to receive, the SDO output could
be disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “line activity monitor”.
This allows a maximum bit clock frequency (at 20 MHz)
of 5.0 MHz.
Figure 9-6 shows the waveforms for Master mode.
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
shown.
The clock polarity is selected by appropriately program-
ming bit CKP (SSPCON<4>). This then, would give
waveforms for SPI communication as shown in
FIGURE 9-2:
SPI MODE TIMING, MASTER MODE
SCK (CKP = 0,
CKE = 0)
SCK (CKP = 0,
CKE = 1)
SCK (CKP = 1,
CKE = 0)
SCK (CKP = 1,
CKE = 1)
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDO
SDI (SMP = 0)
bit7
bit0
SDI (SMP = 1)
SSPIF
bit7
bit0
DS30292D-page 70
1998-2013 Microchip Technology Inc.
PIC16F87X
While in SLEEP mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from SLEEP.
9.1.2
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the last
bit is latched, the interrupt flag bit SSPIF (PIR1<3>) is set.
Note 1: When the SPI module is in Slave
mode with SS pin control enabled
(SSPCON<3:0> = 0100), the SPI module
will reset if the SS pin is set to VDD.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
2: If the SPI is used in Slave mode with
CKE = '1', then SS pin control must be
enabled.
FIGURE 9-3:
SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
SS (optional)
SCK (CKP = 0)
SCK (CKP = 1)
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDO
SDI (SMP = 0)
bit7
bit0
SSPIF
FIGURE 9-4:
SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SS
SCK (CKP = 0)
SCK (CKP = 1)
SDO
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDI (SMP = 0)
SSPIF
bit7
bit0
1998-2013 Microchip Technology Inc.
DS30292D-page 71
PIC16F87X
TABLE 9-1:
REGISTERS ASSOCIATED WITH SPI OPERATION
Value on:
POR, BOR MCLR, WDT
Value on:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
0Ch
8Ch
13h
14h
PIR1
PIE1
PSPIF
PSPIE
ADIF
ADIE
RCIF
RCIE
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
(1)
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
SMP CKE D/A R/W UA BF 0000 0000 0000 0000
SSPCON
SSPSTAT
94h
P
S
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: These bits are reserved on PCI16F873/876 devices; always maintain these bits clear.
DS30292D-page 72
1998-2013 Microchip Technology Inc.
PIC16F87X
The SSPCON register allows control of the I2C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Master mode, clock = OSC/4 (SSPADD +1)
• I2C firmware modes (provided for compatibility to
other mid-range products)
Before selecting any I2C mode, the SCL and SDA pins
must be programmed to inputs by setting the appropri-
ate TRIS bits. Selecting an I2C mode by setting the
SSPEN bit, enables the SCL and SDA pins to be used
as the clock and data lines in I2C mode. Pull-up resis-
tors must be provided externally to the SCL and SDA
pins for the proper operation of the I2C module.
2
9.2
MSSP I C Operation
The MSSP module in I2C mode, fully implements all
master and slave functions (including general call sup-
port) and provides interrupts on START and STOP bits in
hardware, to determine a free bus (multi-master func-
tion). The MSSP module implements the standard mode
specifications, as well as 7-bit and 10-bit addressing.
Refer to Application Note AN578, "Use of the SSP
Module in the I 2C Multi-Master Environment."
A "glitch" filter is on the SCL and SDA pins when the pin
is an input. This filter operates in both the 100 kHz and
400 kHz modes. In the 100 kHz mode, when these pins
are an output, there is a slew rate control of the pin that
is independent of device frequency.
FIGURE 9-5:
I2C SLAVE MODE BLOCK
DIAGRAM
The CKE bit (SSPSTAT<6:7>) sets the levels of the
SDA and SCL pins in either Master or Slave mode.
When CKE = 1, the levels will conform to the SMBus
specification. When CKE = 0, the levels will conform to
the I2C specification.
Internal
Data Bus
Read
Write
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START (S) or STOP (P) bit, specifies if the received
byte was data or address, if the next byte is the com-
pletion of 10-bit address, and if this will be a read or
write data transfer.
SSPBUF Reg
SCL
SDA
Shift
Clock
SSPSR Reg
SSPBUF is the register to which the transfer data is
written to, or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create a doubled buffered
receiver. This allows reception of the next byte to begin
before reading the last byte of received data. When the
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and bit
SSPOV (SSPCON<6>) is set and the byte in the
SSPSR is lost.
MSb
LSb
Addr Match
Match Detect
SSPADD Reg
START and
Set, Reset
S, P bits
(SSPSTAT Reg)
STOP bit Detect
Two pins are used for data transfer. These are the SCL
pin, which is the clock, and the SDA pin, which is the
data. The SDA and SCL pins are automatically config-
ured when the I2C mode is enabled. The SSP module
functions are enabled by setting SSP Enable bit
SSPEN (SSPCON<5>).
The SSPADD register holds the slave address. In
10-bit mode, the user needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0).
The MSSP module has six registers for I2C operation.
They are the:
• SSP Control Register (SSPCON)
• SSP Control Register2 (SSPCON2)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly
accessible
• SSP Address Register (SSPADD)
1998-2013 Microchip Technology Inc.
DS30292D-page 73
PIC16F87X
For a 10-bit address, the first byte would equal
‘1111 0 A9 A8 0’, where A9and A8are the two MSbs
of the address. The sequence of events for a 10-bit
address is as follows, with steps 7-9 for slave-transmitter:
9.2.1
SLAVE MODE
In Slave mode, the SCL and SDA pins must be config-
ured as inputs. The MSSP module will override the
input state with the output data, when required (slave-
transmitter).
1. Receive first (high) byte of Address (bits SSPIF,
BF and UA (SSPSTAT<1>) are set).
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
2. Update the SSPADD register with the second
(low) byte of Address (clears bit UA and
releases the SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
There are certain conditions that will cause the MSSP
module not to give this ACK pulse. These are if either
(or both):
4. Receive second (low) byte of Address (bits
SSPIF, BF and UA are set).
5. Update the SSPADD register with the first (high)
byte of Address. This will clear bit UA and
release the SCL line.
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
b) The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
If the BF bit is set, the SSPSR register value is not
loaded into the SSPBUF, but bit SSPIF and SSPOV are
set. Table 9-2 shows what happens when a data trans-
fer byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit BF is cleared by reading the SSPBUF reg-
ister, while bit SSPOV is cleared through software.
7. Receive Repeated Start condition.
8. Receive first (high) byte of Address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Note: Following the Repeated START condition
(step 7) in 10-bit mode, the user only
needs to match the first 7-bit address. The
user does not update the SSPADD for the
second half of the address.
The SCL clock input must have a minimum high and
low time for proper operation. The high and low times
of the I2C specification, as well as the requirement of
the MSSP module, is shown in timing parameter #100
and parameter #101 of the electrical specifications.
9.2.1.2
Slave Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
9.2.1.1
Addressing
Once the MSSP module has been enabled, it waits for
a START condition to occur. Following the START con-
dition, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON<6>) is set. This is an error
condition due to user firmware.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the received byte.
a) The SSPSR register value is loaded into the
SSPBUF register on the falling edge of the 8th
SCL pulse.
Note: The SSPBUF will be loaded if the SSPOV
bit is set and the BF flag is cleared. If a
read of the SSPBUF was performed, but
the user did not clear the state of the
SSPOV bit before the next receive
occurred, the ACK is not sent and the
SSPBUF is updated.
b) The buffer full bit, BF, is set on the falling edge
of the 8th SCL pulse.
c) An ACK pulse is generated.
d) SSP interrupt flag bit, SSPIF (PIR1<3>), is set
(interrupt is generated if enabled) on the falling
edge of the 9th SCL pulse.
In 10-bit address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write so
the slave device will receive the second address byte.
DS30292D-page 74
1998-2013 Microchip Technology Inc.
PIC16F87X
TABLE 9-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
Generate ACK
Pulse
SSPSR SSPBUF
BF
SSPOV
0
1
1
0
0
0
1
1
Yes
No
Yes
No
No
No
Yes
Yes
Yes
Yes
No
Yes
Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
An SSP interrupt is generated for each data transfer
byte. The SSPIF flag bit must be cleared in software
and the SSPSTAT register is used to determine the sta-
tus of the byte transfer. The SSPIF flag bit is set on the
falling edge of the ninth clock pulse.
9.2.1.3
Slave Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and the SCL pin is held low.
The transmit data must be loaded into the SSPBUF
register, which also loads the SSPSR register. Then,
the SCL pin should be enabled by setting bit CKP
(SSPCON<4>). The master must monitor the SCL pin
prior to asserting another clock pulse. The slave
devices may be holding off the master by stretching the
clock. The eight data bits are shifted out on the falling
edge of the SCL input. This ensures that the SDA sig-
nal is valid during the SCL high time (Figure 9-7).
As a slave-transmitter, the ACK pulse from the master
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line is high (not ACK), then the
data transfer is complete. When the not ACK is latched
by the slave, the slave logic is reset and the slave then
monitors for another occurrence of the START bit. If the
SDA line was low (ACK), the transmit data must be
loaded into the SSPBUF register, which also loads the
SSPSR register. Then the SCL pin should be enabled
by setting the CKP bit.
FIGURE 9-6:
I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
R/W=0
ACK
Not
ACK
Receiving Address
A7 A6 A5 A4
Receiving Data
Receiving Data
ACK
9
SDA
A3 A2 A1
D7 D6 D5 D4 D3 D2
D0
8
D7 D6
D5
D4 D3
D2
D0
8
D1
7
D1
7
3
9
7
1
2
4
5
4
3
6
9
5
6
1
2
3
6
1
2
4
8
5
P
SCL
S
SSPIF
Bus Master
Terminates
Transfer
BF (SSPSTAT<0>)
Cleared in software
SSPBUF register is read
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
1998-2013 Microchip Technology Inc.
DS30292D-page 75
PIC16F87X
FIGURE 9-7:
I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
R/W = 0
R/W = 1
Receiving Address
Transmitting Data Not ACK
ACK
SDA
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
SCL
S
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
P
SCL held low
while CPU
responds to SSPIF
Data in
sampled
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is written in software
From SSP Interrupt
Service Routine
CKP (SSPCON<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written to,
before the CKP bit can be set)
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit),
the SSPIF flag is set.
9.2.2
GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master. The exception is the general call address, which
can address all devices. When this address is used, all
devices should, in theory, respond with an acknowledge.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
SSPBUF to determine if the address was device spe-
cific, or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match, and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when GCEN is set, while the slave is config-
ured in 10-bit address mode, then the second half of
the address is not necessary, the UA bit will not be set,
and the slave will begin receiving data after the
Acknowledge (Figure 9-8).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0.
The general call address is recognized when the Gen-
eral Call Enable bit (GCEN) is enabled (SSPCON2<7>
is set). Following a START bit detect, 8 bits are shifted
into SSPSR and the address is compared against
SSPADD. It is also compared to the general call
address and fixed in hardware.
FIGURE 9-8:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT MODE)
Address is compared to General Call Address
after ACK, set interrupt flag
Receiving data
D5 D4 D3 D2 D1
ACK
R/W = 0
ACK
General Call Address
SDA
SCL
D7 D6
D0
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
9
S
SSPIF
BF
(SSPSTAT<0>)
Cleared in software
SSPBUF is read
'0'
'1'
SSPOV
(SSPCON<6>)
GCEN
(SSPCON2<7>)
DS30292D-page 76
1998-2013 Microchip Technology Inc.
PIC16F87X
9.2.3
SLEEP OPERATION
9.2.4
EFFECTS OF A RESET
While in SLEEP mode, the I2C module can receive
addresses or data. When an address match or com-
plete byte transfer occurs, wake the processor from
SLEEP (if the SSP interrupt is enabled).
A RESET disables the SSP module and terminates the
current transfer.
TABLE 9-3:
REGISTERS ASSOCIATED WITH I2C OPERATION
Value on:
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
PEIE
ADIF
Bit 5
T0IE
RCIF
Bit 4
INTE
TXIF
Bit 3
Bit 2
Bit 1
Bit 0
MCLR,
WDT
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000u
(1)
0Ch
PIR1
PSPIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
(1)
8Ch
0Dh
8Dh
13h
14h
91h
PIE1
PSPIE
—
ADIE
(2)
RCIE
—
TXIE
EEIF
EEIE
PIR2
BCLIF
BCLIE
—
—
—
—
CCP2IF -r-0 0--0 -r-0 0--0
CCP2IE -r-0 0--0 -r-0 0--0
xxxx xxxx uuuu uuuu
PIE2
—
(2)
—
SSPBUF
SSPCON
SSPCON2
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
GCEN
SSPOV
SSPEN
CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
ACKSTAT ACKDT ACKEN RCEN
PEN
RSEN
SEN
0000 0000 0000 0000
0000 0000 0000 0000
2
93h
94h
SSPADD
SSPSTAT
I C Slave Address/Master Baud Rate Register
SMP CKE D/A
P
S
R/W
UA
BF
0000 0000 0000 0000
2
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used by the SSP in I C mode.
Note 1: These bits are reserved on PIC16F873/876 devices; always maintain these bits clear.
2: These bits are reserved on these devices; always maintain these bits clear.
1998-2013 Microchip Technology Inc.
DS30292D-page 77
PIC16F87X
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (an SSP interrupt will occur if
enabled):
9.2.5
MASTER MODE
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET, or when the MSSP module is
disabled. Control of the I2C bus may be taken when the
P bit is set, or the bus is idle, with both the S and P bits
clear.
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated START
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
2
FIGURE 9-9:
SSP BLOCK DIAGRAM (I C MASTER MODE)
Internal
Data Bus
SSPM3:SSPM0,
SSPADD<6:0>
Read
Write
SSPBUF
SSPSR
Baud
Rate
Generator
SDA
Shift
Clock
SDA in
MSb
LSb
START bit, STOP bit,
Acknowledge
Generate
SCL
START bit Detect,
STOP bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL in
Bus Collision
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
In Multi-Master operation, the SDA line must be moni-
tored for arbitration to see if the signal level is the
expected output level. This check is performed in hard-
ware, with the result placed in the BCLIF bit.
9.2.6
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the MSSP module is disabled. Control of the I2C
bus may be taken when bit P (SSPSTAT<4>) is set, or
the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP Interrupt will gener-
ate the interrupt when the STOP condition occurs.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A START Condition
• A Repeated START Condition
• An Acknowledge Condition
DS30292D-page 78
1998-2013 Microchip Technology Inc.
PIC16F87X
I2C MASTER MODE SUPPORT
SSPBUF. Once the given operation is complete (i.e.,
transmission of the last data bit is followed by ACK), the
internal clock will automatically stop counting and the
SCL pin will remain in its last state.
9.2.7
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. Once Master mode is enabled, the user
has six options:
A typical transmit sequence would go as follows:
a) User generates a START condition by setting
the START enable bit (SEN) in SSPCON2.
• Assert a START condition on SDA and SCL.
• Assert a Repeated START condition on SDA and
SCL.
b) SSPIF is set. The module will wait the required
start time before any other operation takes place.
• Write to the SSPBUF register initiating transmis-
sion of data/address.
c) User loads SSPBUF with address to transmit.
d) Address is shifted out the SDA pin until all 8 bits
are transmitted.
• Generate a STOP condition on SDA and SCL.
• Configure the I2C port to receive data.
e) MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
• Generate an Acknowledge condition at the end of
a received byte of data.
Note: The MSSP Module, when configured in I2C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
initiate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
f) MSSP module generates an interrupt at the end
of the ninth clock cycle by setting SSPIF.
g) User loads SSPBUF with eight bits of data.
h) DATA is shifted out the SDA pin until all 8 bits are
transmitted.
i) MSSP module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register (SSPCON2<6>).
j) MSSP module generates an interrupt at the end
of the ninth clock cycle by setting the SSPIF bit.
9.2.7.1
I2C Master Mode Operation
k) User generates a STOP condition by setting the
STOP enable bit, PEN, in SSPCON2.
The master device generates all of the serial clock
pulses and the START and STOP conditions. A trans-
fer is ended with a STOP condition or with a Repeated
START condition. Since the Repeated START condi-
tion is also the beginning of the next serial transfer, the
I2C bus will not be released.
l) Interrupt is generated once the STOP condition
is complete.
9.2.8
BAUD RATE GENERATOR
In I2C Master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 9-10). When the BRG is loaded with this value,
the BRG counts down to 0 and stops until another reload
has taken place. The BRG count is decremented twice
per instruction cycle (TCY), on the Q2 and Q4 clock.
In I2C Master mode, the BRG is reloaded automatically. If
clock arbitration is taking place, the BRG will be reloaded
when the SCL pin is sampled high (Figure 9-11).
In Master Transmitter mode, serial data is output through
SDA, while SCL outputs the serial clock. The first byte
transmitted contains the slave address of the receiving
device (7 bits) and the Read/Write (R/W) bit. In this case,
the R/W bit will be logic '0'. Serial data is transmitted 8 bits
at a time. After each byte is transmitted, an Acknowledge
bit is received. START and STOP conditions are output
to indicate the beginning and the end of a serial transfer.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic '1'. Thus, the first byte transmitted is a 7-bit slave
address followed by a '1' to indicate receive bit. Serial
data is received via SDA, while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each
byte is received, an Acknowledge bit is transmitted.
START and STOP conditions indicate the beginning
and end of transmission.
Note: Baud Rate = FOSC / (4 * (SSPADD + 1) )
FIGURE 9-10:
BAUD RATE GENERATOR
BLOCK DIAGRAM
SSPM3:SSPM0
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Reload
The baud rate generator used for SPI mode operation
is now used to set the SCL clock frequency for either
100 kHz, 400 kHz, or 1 MHz I2C operation. The baud
rate generator reload value is contained in the lower 7
bits of the SSPADD register. The baud rate generator
will automatically begin counting on a write to the
Control
FOSC/4
BRG Down Counter
CLKOUT
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FIGURE 9-11:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL de-asserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
SCL
BRG decrements
(on Q2 and Q4 cycles)
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place, and BRG starts its count
BRG
Reload
9.2.9
I2C MASTER MODE START
CONDITION TIMING
Note: If, at the beginning of START condition, the
SDA and SCL pins are already sampled
low, or if during the START condition the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag (BCLIF) is
set, the START condition is aborted, and
the I2C module is reset into its IDLE state.
To initiate a START condition, the user sets the START
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the baud rate genera-
tor is reloaded with the contents of SSPADD<6:0> and
starts its count. If SCL and SDA are both sampled high
when the baud rate generator times out (TBRG), the
SDA pin is driven low. The action of the SDA being
driven low while SCL is high is the START condition,
and causes the S bit (SSPSTAT<3>) to be set. Follow-
ing this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (TBRG), the
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware. The baud rate generator is suspended,
leaving the SDA line held low, and the START condition
is complete.
9.2.9.1
WCOL Status Flag
If the user writes the SSPBUF when a START
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
FIGURE 9-12:
FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
Write to SEN bit occurs here
SDA = 1,
At completion of START bit,
Hardware clears SEN bit
and sets SSPIF bit
SCL = 1
TBRG
TBRG
Write to SSPBUF occurs here
2nd Bit
1st Bit
SDA
TBRG
SCL
TBRG
S
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I2C MASTER MODE REPEATED
START CONDITION TIMING
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode), or eight bits of data (7-bit
mode).
9.2.10
A Repeated START condition occurs when the RSEN
bit (SSPCON2<1>) is programmed high and the I2C
module is in the IDLE state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sam-
pled low, the baud rate generator is loaded with the
contents of SSPADD<6:0> and begins counting. The
SDA pin is released (brought high) for one baud rate
generator count (TBRG). When the baud rate generator
times out, if SDA is sampled high, the SCL pin will be
de-asserted (brought high). When SCL is sampled high
the baud rate generator is reloaded with the contents of
SSPADD<6:0> and begins counting. SDA and SCL
must be sampled high for one TBRG. This action is then
followed by assertion of the SDA pin (SDA is low) for
one TBRG, while SCL is high. Following this, the RSEN
bit in the SSPCON2 register will be automatically
cleared and the baud rate generator will not be
reloaded, leaving the SDA pin held low. As soon as a
START condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
notbesetuntilthebaudrategeneratorhastimedout.
9.2.10.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated
START sequence is in progress, then WCOL is set and
the contents of the buffer are unchanged (the write
doesn’t occur).
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated
START condition occurs if:
•
•
SDA is sampled low when SCL
goes from low to high.
SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
FIGURE 9-13:
REPEAT START CONDITION WAVEFORM
Set S (SSPSTAT<3>)
Write to SSPCON2
SDA = 1,
SCL = 1
occurs here
At completion of START bit,
hardware clears RSEN bit
and sets SSPIF
SDA = 1,
SCL (no change)
TBRG TBRG
TBRG
1st bit
SDA
Write to SSPBUF occurs here
Falling edge of ninth clock
End of Xmit
TBRG
SCL
TBRG
Sr = Repeated START
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9.2.11
I2C MASTER MODE
TRANSMISSION
9.2.11.1
BF Status Flag
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
Transmission of a data byte, a 7-bit address, or either
half of a 10-bit address, is accomplished by simply writ-
ing a value to SSPBUF register. This action will set the
Buffer Full flag (BF) and allow the baud rate generator
to begin counting and start the next transmission. Each
bit of address/data will be shifted out onto the SDA pin
after the falling edge of SCL is asserted (see data hold
time spec). SCL is held low for one baud rate generator
rollover count (TBRG). Data should be valid before SCL
is released high (see data setup time spec). When the
SCL pin is released high, it is held that way for TBRG.
The data on the SDA pin must remain stable for that
duration and some hold time after the next falling edge
of SCL. After the eighth bit is shifted out (the falling
edge of the eighth clock), the BF flag is cleared and the
master releases SDA allowing the slave device being
addressed to respond with an ACK bit during the ninth
bit time, if an address match occurs or if data was
received properly. The status of ACK is read into the
ACKDT on the falling edge of the ninth clock. If the
master receives an Acknowledge, the Acknowledge
Status bit (ACKSTAT) is cleared. If not, the bit is set.
After the ninth clock, the SSPIF is set and the master
clock (baud rate generator) is suspended until the next
data byte is loaded into the SSPBUF, leaving SCL low
and SDA unchanged (Figure 9-14).
9.2.11.2
WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
9.2.11.3
ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0), and is set when the slave does not Acknowl-
edge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL, until all seven
address bits and the R/W bit are completed. On the fall-
ing edge of the eighth clock, the master will de-assert
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared, and the baud rate generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
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2
FIGURE 9-14:
I C MASTER MODE TIMING (TRANSMISSION, 7 OR 10-BIT ADDRESS)
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9.2.12
I2C MASTER MODE RECEPTION
9.2.12.1
BF Status Flag
In receive operation, BF is set when an address or data
byte is loaded into SSPBUF from SSPSR. It is cleared
when SSPBUF is read.
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2<3>).
Note: The SSP module must be in an IDLE state
before the RCEN bit is set, or the RCEN bit
will be disregarded.
9.2.12.2
SSPOV Status Flag
In receive operation, SSPOV is set when 8 bits are
received into the SSPSR, and the BF flag is already set
from a previous reception.
The baud rate generator begins counting, and on each
rollover, the state of the SCL pin changes (high to low/
low to high), and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag is set,
the SSPIF is set, and the baud rate generator is sus-
pended from counting, holding SCL low. The SSP is
now in IDLE state, awaiting the next command. When
the buffer is read by the CPU, the BF flag is automati-
cally cleared. The user can then send an Acknowledge
bit at the end of reception, by setting the Acknowledge
Sequence Enable bit, ACKEN (SSPCON2<4>).
9.2.12.3
WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), then WCOL is set and the contents of the buffer
are unchanged (the write doesn’t occur).
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2
FIGURE 9-15:
I C MASTER MODE TIMING (RECEPTION, 7-BIT ADDRESS)
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rate generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automati-
cally cleared, the baud rate generator is turned off,
and the SSP module then goes into IDLE mode
(Figure 9-16).
9.2.13
ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
is presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The baud
rate generator then counts for one rollover period
(TBRG), and the SCL pin is de-asserted high. When the
SCL pin is sampled high (clock arbitration), the baud
9.2.13.1
WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 9-16:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
Write to SSPCON2
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
TBRG
SDA
SCL
D0
ACK
8
9
SSPIF
Cleared in
software
Set SSPIF at the end
of receive
Cleared in
software
Set SSPIF at the end
of Acknowledge sequence
Note: TBRG = one baud rate generator period.
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while SCL is high, the P bit (SSPSTAT<4>) is set. A
TBRG later, the PEN bit is cleared and the SSPIF bit is
set (Figure 9-17).
9.2.14
STOP CONDITION TIMING
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator times
out, the SCL pin will be brought high, and one TBRG
(baud rate generator rollover count) later, the SDA pin
will be de-asserted. When the SDA pin is sampled high
Whenever the firmware decides to take control of the
bus, it will first determine if the bus is busy by checking
the S and P bits in the SSPSTAT register. If the bus is
busy, then the CPU can be interrupted (notified) when
a STOP bit is detected (i.e., bus is free).
9.2.14.1
WCOL Status Flag
If the user writes the SSPBUF when a STOP sequence
is in progress, then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
FIGURE 9-17:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
Write to SSPCON2
Set PEN
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
TBRG
SCL
ACK
SDA
P
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup STOP condition
Note: TBRG = one baud rate generator period.
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9.2.15
CLOCK ARBITRATION
9.2.16
SLEEP OPERATION
Clock arbitration occurs when the master, during any
receive, transmit, or Repeated START/STOP condi-
tion, de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count in the event that the clock
is held low by an external device (Figure 9-18).
While in SLEEP mode, the I2C module can receive
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from SLEEP (if the SSP interrupt is enabled).
9.2.17
EFFECTS OF A RESET
A RESET disables the SSP module and terminates the
current transfer.
FIGURE 9-18:
CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
BRG overflow,
Release SCL,
If SCL = 1, Load BRG with
BRG overflow occurs,
Release SCL, Slave device holds SCL low
SSPADD<6:0>, and start count
to measure high time interval
SCL = 1, BRG starts counting
clock high interval
SCL
SCL line sampled once every machine cycle (TOSC 4).
Hold off BRG until SCL is sampled high.
SDA
TBRG
TBRG
TBRG
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If a START, Repeated START, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de-asserted, and the respective control bits in
the SSPCON2 register are cleared. When the user ser-
vices the bus collision Interrupt Service Routine, and if
the I2C bus is free, the user can resume communication
by asserting a START condition.
9.2.18
MULTI -MASTER
COMMUNICATION,
BUS COLLISION, AND
BUS ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a '1' on SDA, by letting SDA float high and
another master asserts a '0'. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a '1' and the data sampled on the SDA pin = '0',
a bus collision has taken place. The master will set the
Bus Collision Interrupt Flag, BCLIF and reset the I2C
port to its IDLE state (Figure 9-19).
The master will continue to monitor the SDA and SCL
pins and if a STOP condition occurs, the SSPIF bit will
be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is idle and the S and P bits are
cleared.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted, and
the SSPBUF can be written to. When the user services
the bus collision Interrupt Service Routine, and if the
I2C bus is free, the user can resume communication by
asserting a START condition.
FIGURE 9-19:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master.
SDA line pulled low
by another source
Data changes
while SCL = 0
Bus collision has occurred.
SDA released
by master
SDA
SCL
Set bus collision
interrupt
BCLIF
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If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 9-22). If, however, a '1' is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to 0. During this time, if the SCL pins are
sampled as '0', a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
9.2.18.1
Bus Collision During a START
Condition
During a START condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the START condition (Figure 9-20).
b) SCL is sampled low before SDA is asserted low
(Figure 9-21).
During a START condition, both the SDA and the SCL
pins are monitored. If either the SDA pin or the SCL pin
is already low, then these events all occur:
Note: The reason that bus collision is not a factor
during a START condition is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision, because the two masters must be
allowed to arbitrate the first address follow-
ing the START condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
START, or STOP conditions.
• the START condition is aborted,
• and the BCLIF flag is set,
• and the SSP module is reset to its IDLE state
(Figure 9-20).
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data '1' during the START condition.
FIGURE 9-20:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
SEN
Set SEN, enable START
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.
SSP module reset into IDLE state.
SDA sampled low before
START condition.
Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
BCLIF
SSPIF and BCLIF are
cleared in software
S
SSPIF
SSPIF and BCLIF are
cleared in software
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FIGURE 9-21:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable START
sequence if SDA = 1, SCL = 1
SCL
SEN
SCL = 0 before SDA = 0,
Bus collision occurs, Set BCLIF
SCL = 0 before BRG time-out,
Bus collision occurs, Set BCLIF
BCLIF
Interrupts cleared
in software
S
'0'
'0'
'0'
'0'
SSPIF
FIGURE 9-22:
BRG RESET DUE TO SDA COLLISION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Set SSPIF
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SDA
SCL
s
SCL pulled low after BRG
Time-out
SEN
Set SEN, enable START
sequence if SDA = 1, SCL = 1
'0'
BCLIF
S
SSPIF
Interrupts cleared
in software
SDA = 0, SCL = 1
Set SSPIF
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SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high to low before the BRG
times out, no bus collision occurs, because no two
masters can assert SDA at exactly the same time.
9.2.18.2
Bus Collision During a Repeated
START Condition
During a Repeated START condition, a bus collision
occurs if:
If, however, SCL goes from high to low before the BRG
times out and SDA has not already been asserted, a
bus collision occurs. In this case, another master is
attempting to transmit a data’1’ during the Repeated
START condition.
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low, indi-
cating that another master is attempting to trans-
mit a data ’1’.
If at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low, the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated START condition is
complete (Figure 9-23).
When the user de-asserts SDA and the pin is allowed
to float high, the BRG is loaded with SSPADD<6:0>
and counts down to 0. The SCL pin is then de-asserted,
and when sampled high, the SDA pin is sampled. If
SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data’0’). If, however,
FIGURE 9-23:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software
'0'
'0'
'0'
S
'0'
SSPIF
FIGURE 9-24:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
Set BCLIF. Release SDA and SCL.
BCLIF
RSEN
Interrupt cleared
in software
'0'
'0'
'0'
'0'
S
SSPIF
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The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the baud rate generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data '0'. If the SCL pin is sampled low before
SDA is allowed to float high, a bus collision occurs. This
is a case of another master attempting to drive a data
'0' (Figure 9-25).
9.2.18.3
Bus Collision During a STOP
Condition
Bus collision occurs during a STOP condition if:
a) After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is de-asserted, SCL is sam-
pled low before SDA goes high.
FIGURE 9-25:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
low after TBRG,
Set BCLIF
TBRG
TBRG
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
'0'
'0'
'0'
'0'
SSPIF
FIGURE 9-26:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL
SCL goes low before SDA goes high,
Set BCLIF
Assert SDA
PEN
BCLIF
P
'0'
'0'
SSPIF
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example, with a supply voltage of VDD = 5V±10% and
VOL max = 0.4V at 3 mA, Rpmin = (5.5-0.4)/0.003 = 1.7 k
VDD as a function of Rp is shown in Figure 9-27. The
desired noise margin of 0.1VDD for the low level limits
the maximum value of Rs. Series resistors are optional
and used to improve ESD susceptibility.
9.3
Connection Considerations for
I C Bus
2
For standard-mode I2C bus devices, the values of
resistors Rp and Rs in Figure 9-27 depend on the fol-
lowing parameters:
• Supply voltage
The bus capacitance is the total capacitance of wire,
connections, and pins. This capacitance limits the max-
imum value of Rp due to the specified rise time
(Figure 9-27).
• Bus capacitance
• Number of connected devices
(input current + leakage current)
The SMP bit is the slew rate control enabled bit. This bit
is in the SSPSTAT register, and controls the slew rate
of the I/O pins when in I2C mode (master or slave).
The supply voltage limits the minimum value of resistor
Rp, due to the specified minimum sink current of 3 mA at
VOL max = 0.4V, for the specified output stages. For
FIGURE 9-27:
SAMPLE DEVICE CONFIGURATION FOR I2C BUS
VDD + 10%
DEVICE
R
R
p
p
R
R
s
s
SDA
SCL
C =10 - 400 pF
b
2
Note: I C devices with input levels related to VDD must have one common supply line to which the pull-up resistor is also
connected.
DS30292D-page 94
1998-2013 Microchip Technology Inc.
PIC16F87X
The USART can be configured in the following modes:
10.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to
be set in order to configure pins RC6/TX/CK and
RC7/RX/DT as the Universal Synchronous Asynchro-
nous Receiver Transmitter.
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Com-
munications Interface or SCI.) The USART can be con-
figured as a full duplex asynchronous system that can
communicate with peripheral devices such as CRT ter-
minals and personal computers, or it can be configured
as a half duplex synchronous system that can commu-
nicate with peripheral devices such as A/D or D/A inte-
grated circuits, serial EEPROMs etc.
The USART module also has a multi-processor com-
munication capability using 9-bit address detection.
REGISTER 10-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
—
R/W-0
BRGH
R-1
R/W-0
TX9D
TRMT
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4
SYNC: USART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
bit 3
bit 2
Unimplemented: Read as '0'
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of Transmit Data, can be parity bit
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
1998-2013 Microchip Technology Inc.
DS30292D-page 95
PIC16F87X
REGISTER 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
R-0
R-0
R-x
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0= Serial port disabled
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave:
Don’t care
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables continuous receive
0= Disables continuous receive
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection, enables interrupt and load of the receive buffer when
RSR<8> is set
0= Disables address detection, all bytes are received, and ninth bit can be used as parity bit
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREG register and receive next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of Received Data (can be parity bit, but must be calculated by user firmware)
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS30292D-page 96
1998-2013 Microchip Technology Inc.
PIC16F87X
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
10.1 USART Baud Rate Generator
(BRG)
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 10-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in Master mode (internal clock).
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
10.1.1
SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 10-1. From this, the error in
baud rate can be determined.
TABLE 10-1: BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
Baud Rate = FOSC/(16(X+1))
N/A
X = value in SPBRG (0 to 255)
TABLE 10-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
98h
TXSTA
RCSTA
SPBRG
CSRC
SPEN
TX9
RX9
TXEN
SYNC
—
BRGH
FERR
TRMT TX9D 0000 -010 0000 -010
OERR RX9D 0000 000x 0000 000x
0000 0000 0000 0000
18h
99h
SREN CREN
ADDEN
Baud Rate Generator Register
Legend: x = unknown, -= unimplemented, read as '0'. Shaded cells are not used by the BRG.
1998-2013 Microchip Technology Inc.
DS30292D-page 97
PIC16F87X
TABLE 10-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz
FOSC = 16 MHz
FOSC = 10 MHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
SPBRG
%
%
%
value
KBAUD
ERROR
KBAUD
ERROR
KBAUD ERROR
(decimal)
(decimal)
(decimal)
0.3
1.2
-
-
-
255
129
31
15
9
-
-
-
207
103
25
12
8
-
-
-
129
64
15
7
1.221
1.75
0.17
1.73
1.72
8.51
3.34
8.51
-
1.202
0.17
0.17
0.16
0.16
3.55
6.29
8.51
-
1.202
0.17
0.17
1.73
1.72
8.51
6.99
9.58
-
2.4
2.404
2.404
2.404
9.6
9.766
9.615
9.766
19.2
28.8
33.6
57.6
HIGH
LOW
19.531
31.250
34.722
62.500
1.221
19.231
27.778
35.714
62.500
0.977
19.531
31.250
31.250
52.083
0.610
4
8
6
4
4
3
2
255
0
255
0
255
0
312.500
-
250.000
-
156.250
-
FOSC = 4 MHz
FOSC = 3.6864 MHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
(decimal)
%
%
ERROR
ERROR
KBAUD
(decimal)
KBAUD
0.3
1.2
0.300
1.202
2.404
8.929
20.833
31.250
-
0
207
51
25
6
0.3
1.2
0
0
0
0
0
0
-
191
47
23
5
0.17
0.17
6.99
8.51
8.51
-
2.4
2.4
9.6
9.6
19.2
28.8
33.6
57.6
HIGH
LOW
2
19.2
28.8
-
2
1
1
-
-
62.500
0.244
62.500
8.51
-
0
57.6
0.225
57.6
0
-
0
255
0
255
0
-
-
TABLE 10-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 20 MHz
FOSC = 16 MHz
FOSC = 10 MHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
SPBRG
value
%
%
%
KBAUD
ERROR
KBAUD
ERROR
KBAUD
ERROR
(decimal)
(decimal)
(decimal)
0.3
1.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.4
-
-
-
-
-
-
2.441
9.615
19.531
28.409
32.895
56.818
2.441
625.000
1.71
0.16
1.72
1.36
2.10
1.36
-
255
64
31
21
18
10
255
0
9.6
9.615
19.231
29.070
33.784
59.524
4.883
1250.000
0.16
0.16
0.94
0.55
3.34
-
129
64
42
36
20
255
0
9.615
19.231
29.412
33.333
58.824
3.906
1000.000
0.16
0.16
2.13
0.79
2.13
-
103
51
33
29
16
255
0
19.2
28.8
33.6
57.6
HIGH
LOW
-
-
FOSC = 4 MHz
FOSC = 3.6864 MHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
%
%
ERROR
ERROR
KBAUD
(decimal) KBAUD
(decimal)
0.3
1.2
-
-
-
207
103
25
12
8
-
-
-
191
95
23
11
7
1.202
0.17
0.17
0.16
0.16
3.55
6.29
8.51
-
1.2
0
2.4
2.404
2.4
0
9.6
9.615
9.6
0
19.2
28.8
33.6
57.6
HIGH
LOW
19.231
27.798
35.714
62.500
0.977
19.2
28.8
32.9
57.6
0.9
0
0
6
2.04
6
3
0
-
3
255
0
255
0
250.000
-
230.4
-
DS30292D-page 98
1998-2013 Microchip Technology Inc.
PIC16F87X
enabled/disabled by setting/clearing enable bit TXIE
( PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. Status bit TRMT
is a read only bit, which is set when the TSR register is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR reg-
ister is empty.
10.2 USART Asynchronous Mode
In this mode, the USART uses standard non-return-to-
zero (NRZ) format (one START bit, eight or nine data
bits, and one STOP bit). The most common data format
is 8-bits. An on-chip, dedicated, 8-bit baud rate gener-
ator can be used to derive standard baud rate frequen-
cies from the oscillator. The USART transmits and
receives the LSb first. The transmitter and receiver are
functionally independent, but use the same data format
and baud rate. The baud rate generator produces a
clock, either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA<2>). Parity is not supported by
the hardware, but can be implemented in software (and
stored as the ninth data bit). Asynchronous mode is
stopped during SLEEP.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set. TXIF is cleared by loading TXREG.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift clock (Figure 10-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
transfer to the TXREG register will result in an immedi-
ate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 10-3).
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. As a result, the RC6/TX/CK pin will revert
to hi-impedance.
The USART Asynchronous module consists of the fol-
lowing important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
10.2.1
USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 10-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
flag bit TXIF (PIR1<4>) is set. This interrupt can be
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can result in an immediate transfer of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit may be loaded in the TSR
register.
FIGURE 10-1:
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG Register
8
TXIE
MSb
(8)
LSb
0
Pin Buffer
and Control
TSR Register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
SPBRG
TRMT
SPEN
TX9
Baud Rate Generator
TX9D
1998-2013 Microchip Technology Inc.
DS30292D-page 99
PIC16F87X
When setting up an Asynchronous Transmission,
follow these steps:
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 10.1).
7. Load data to the TXREG register (starts trans-
mission).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
8. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, then set transmit
bit TX9.
FIGURE 10-2:
ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
START Bit
Bit 0
Bit 1
Word 1
Bit 7/8
STOP Bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 10-3:
ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
START Bit
START Bit
Word 2
Bit 0
Bit 1
Word 1
Bit 7/8
Bit 0
STOP Bit
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
Note:
This timing diagram shows two consecutive transmissions.
TABLE 10-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
TXIF
RBIE
T0IF
INTF
R0IF
0000 000x 0000 000u
(1)
0Ch
18h
19h
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
TXREG USART Transmit Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873/876; always maintain these bits clear.
DS30292D-page 100
1998-2013 Microchip Technology Inc.
PIC16F87X
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
the STOP bit of the third byte, if the RCREG register is
still full, the overrun error bit OERR (RCSTA<1>) will be
set. The word in the RSR will be lost. The RCREG reg-
ister can be read twice to retrieve the two bytes in the
FIFO. Overrun bit OERR has to be cleared in software.
This is done by resetting the receive logic (CREN is
cleared and then set). If bit OERR is set, transfers from
the RSR register to the RCREG register are inhibited,
and no further data will be received. It is therefore,
essential to clear error bit OERR if it is set. Framing
error bit FERR (RCSTA<2>) is set if a STOP bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values, therefore, it is essential for the user to read the
RCSTA register before reading the RCREG register in
order not to lose the old FERR and RX9D information.
10.2.2
USART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 10-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter, operating at x16 times the
baud rate; whereas, the main receive serial shifter
operates at the bit rate or at FOSC.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG register (if
it is empty). If the transfer is complete, flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit, which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double buffered register (i.e., it is a two deep FIFO). It
FIGURE 10-4:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
FOSC
SPBRG
64
or
16
RSR Register
MSb
LSb
START
Baud Rate Generator
7
1
0
STOP (8)
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D RCREG Register
SPEN
FIFO
8
RCIF
RCIE
Interrupt
Data Bus
1998-2013 Microchip Technology Inc.
DS30292D-page 101
PIC16F87X
FIGURE 10-5:
ASYNCHRONOUS RECEPTION
START
bit
START
bit
START
bit7/8 STOP bit
bit
RX (pin)
bit0
bit1
STOP
bit
STOP
bit
bit0
bit7/8
bit7/8
Rcv Shift
Reg
Rcv Buffer Reg
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
When setting up an Asynchronous Reception, follow
these steps:
6. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE is set.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 10.1).
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
8. Read the 8-bit received data by reading the
RCREG register.
3. If interrupts are desired, then set enable bit
RCIE.
9. If any error occurred, clear the error by clearing
enable bit CREN.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
10. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 10-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
TXIF
RBIE
T0IF
INTF
R0IF
0000 000x 0000 000u
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
SSPIF CCP1IF TMR2IF TMR1IF
FERR OERR RX9D
0000 0000 0000 0000
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
RCSTA
SREN CREN
—
RCREG USART Receive Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE
SYNC BRGH TRMT TX9D
TXSTA
TXEN
—
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
DS30292D-page 102
1998-2013 Microchip Technology Inc.
PIC16F87X
• Flag bit RCIF will be set when reception is com-
plete, and an interrupt will be generated if enable
bit RCIE was set.
10.2.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
When setting up an Asynchronous Reception with
Address Detect Enabled:
• Read the RCSTA register to get the ninth bit and
determine if any error occurred during reception.
• Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired, set
bit BRGH.
• Read the 8-bit received data by reading the
RCREG register, to determine if the device is
being addressed.
• Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
• If any error occurred, clear the error by clearing
enable bit CREN.
• If interrupts are desired, then set enable bit RCIE.
• Set bit RX9 to enable 9-bit reception.
• If the device has been addressed, clear the
ADDEN bit to allow data bytes and address bytes
to be read into the receive buffer, and interrupt the
CPU.
• Set ADDEN to enable address detect.
• Enable the reception by setting enable bit CREN.
FIGURE 10-6:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
FOSC
SPBRG
64
or
16
RSR Register
MSb
LSb
0
Baud Rate Generator
7
1
STOP (8)
START
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
8
SPEN
RX9
Enable
Load of
ADDEN
Receive
Buffer
RX9
ADDEN
RSR<8>
8
RX9D
RCREG Register
FIFO
8
RCIF
RCIE
Interrupt
Data Bus
1998-2013 Microchip Technology Inc.
DS30292D-page 103
PIC16F87X
FIGURE 10-7:
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
START
bit
START
bit8 STOP bit
bit
RC7/RX/DT (pin)
bit0
bit1
STOP
bit
bit0
bit8
Load RSR
Read
Word 1
RCREG
Bit8 = 0, Data Byte
Bit8 = 1, Address Byte
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer)
because ADDEN = 1.
FIGURE 10-8:
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
START
bit
START
bit
RC7/RX/DT (pin)
bit0
bit1
STOP
bit
bit8 STOP
bit
bit0
bit8
Load RSR
Read
Word 1
RCREG
Bit8 = 1, Address Byte
Bit8 = 0, Data Byte
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer)
because ADDEN was not updated and still = 0.
TABLE 10-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
TXIF
RBIE
T0IF
INTF
R0IF
0000 000x 0000 000u
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN ADDEN FERR
OERR
RX9D 0000 000x 0000 000x
RCREG USART Receive Register
0000 0000 0000 0000
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
DS30292D-page 104
1998-2013 Microchip Technology Inc.
PIC16F87X
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to hi-
impedance. If either bit CREN or bit SREN is set during
a transmission, the transmission is aborted and the DT
pin reverts to a hi-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic, however, is not
reset, although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SREN is set (to interrupt an on-going transmission
and receive a single word), then after the single word is
received, bit SREN will be cleared and the serial port
will revert back to transmitting, since bit TXEN is still
set. The DT line will immediately switch from hi-
impedance Receive mode to transmit and start driving.
To avoid this, bit TXEN should be cleared.
10.3 USART Synchronous
Master Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
10.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
The USART transmitter block diagram is shown in
Figure 10-6. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and inter-
rupt bit TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not
available to the user.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 10.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is sta-
ble around the falling edge of the synchronous clock
(Figure 10-9). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 10-10). This is advantageous when slow
baud rates are selected, since the BRG is kept in
RESET when bits TXEN, CREN and SREN are clear.
Setting enable bit TXEN will start the BRG, creating a
shift clock immediately. Normally, when transmission is
first started, the TSR register is empty, so a transfer to
the TXREG register will result in an immediate transfer
to TSR, resulting in an empty TXREG. Back-to-back
transfers are possible.
1998-2013 Microchip Technology Inc.
DS30292D-page 105
PIC16F87X
TABLE 10-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on:
POR,
Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
other
BOR
RESETS
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
R0IF
0000 000x 0000 000u
(1)
0Ch
18h
19h
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF
FERR OERR RX9D
0000 0000 0000 0000
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
RCSTA
SREN CREN
—
TXREG USART Transmit Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
TXEN SYNC BRGH TRMT TX9D
TXSTA
—
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission.
Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
FIGURE 10-9:
SYNCHRONOUS TRANSMISSION
Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
Q3Q4 Q1Q2 Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3 Q4Q1Q2Q3Q4Q1 Q2Q3 Q4
RC7/RX/DT pin
RC6/TX/CK pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
Word 1
Write to
TXREG reg
Write Word1
Write Word2
TXIF bit
(Interrupt Flag)
TRMT bit
'1'
'1'
TXEN bit
Note: Sync Master mode; SPBRG = '0'. Continuous transmission of two 8-bit words.
FIGURE 10-10:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit0
bit2
bit1
bit6
bit7
RC6/TX/CK pin
Write to
TXREG Reg
TXIF bit
TRMT bit
TXEN bit
DS30292D-page 106
1998-2013 Microchip Technology Inc.
PIC16F87X
receive bit is buffered the same way as the receive
data. Reading the RCREG register will load bit RX9D
with a new value, therefore, it is essential for the user
to read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
10.3.2
USART SYNCHRONOUS MASTER
RECEPTION
Once synchronous mode is selected, reception is
enabled by setting either enable bit SREN
(RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the recep-
tion is continuous until CREN is cleared. If both bits are
set, CREN takes precedence. After clocking the last bit,
the received data in the Receive Shift Register (RSR)
is transferred to the RCREG register (if it is empty).
When the transfer is complete, interrupt flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit, which is
reset by the hardware. In this case, it is reset when the
RCREG register has been read and is empty. The
RCREG is a double buffered register (i.e., it is a two
deep FIFO). It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full, then overrun error bit OERR
(RCSTA<1>) is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so
it is essential to clear bit OERR if it is set. The ninth
When setting up a Synchronous Master Reception:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 10.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 10-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on:
POR,
BOR
Value on all
other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
R0IF
0000 000x 0000 000u
(1)
0Ch
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF
FERR OERR RX9D
0000 0000 0000 0000
0000 -00x 0000 -00x
0000 0000 0000 0000
18h
1Ah
8Ch
98h
99h
RCSTA
SREN CREN
—
RCREG USART Receive Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented, read as '0'. Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
1998-2013 Microchip Technology Inc.
DS30292D-page 107
PIC16F87X
FIGURE 10-11:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2Q3Q4 Q1Q2Q3Q4 Q1 Q2Q3Q4 Q1Q2Q3 Q4Q1 Q2Q3 Q4 Q1Q2 Q3Q4Q1Q2Q3 Q4 Q1Q2 Q3Q4Q1 Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4
bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
RC7/RX/DT pin
RC6/TX/CK pin
Write to
bit SREN
SREN bit
CREN bit
'0'
'0'
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC Master mode with bit SREN = '1' and bit BRG = '0'.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the inter-
rupt vector (0004h).
10.4 USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
When setting up a Synchronous Slave Transmission,
follow these steps:
1. Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
10.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
2. Clear bits CREN and SREN.
3. If interrupts are desired, then set enable bit
TXIE.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP mode.
4. If 9-bit transmission is desired, then set bit TX9.
If two words are written to the TXREG and then the
5. Enable the transmission by setting enable bit
TXEN.
SLEEPinstruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
7. Start transmission by loading data to the TXREG
register.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
8. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on all
other
RESETS
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
TXIF
RBIE
T0IF
INTF
R0IF
0000 000x 0000 000u
(1)
0Ch
18h
19h
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN ADDEN FERR
OERR
RX9D 0000 000x 0000 000x
TXREG USART Transmit Register
0000 0000 0000 0000
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x= unknown, -= unimplemented, read as '0'. Shaded cells are not used for synchronous slave transmission.
Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
DS30292D-page 108
1998-2013 Microchip Technology Inc.
PIC16F87X
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
10.4.2
USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode. Bit SREN is a “don't care” in Slave mode.
5. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
If receive is enabled by setting bit CREN prior to the
SLEEPinstruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
When setting up a Synchronous Slave Reception, fol-
low these steps:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
TABLE 10-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on:
POR,
BOR
Value on all
other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
TXIF
RBIE
T0IF
INTF
R0IF
0000 000x 0000 000u
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN ADDEN FERR
OERR
RX9D 0000 000x 0000 000x
RCREG USART Receive Register
0000 0000 0000 0000
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x= unknown, -= unimplemented, read as '0'. Shaded cells are not used for synchronous slave reception.
Note 1: Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices, always maintain these bits clear.
1998-2013 Microchip Technology Inc.
DS30292D-page 109
PIC16F87X
NOTES:
DS30292D-page 110
1998-2013 Microchip Technology Inc.
PIC16F87X
The A/D module has four registers. These registers
are:
11.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register0 (ADCON0)
• A/D Control Register1 (ADCON1)
The Analog-to-Digital (A/D) Converter module has five
inputs for the 28-pin devices and eight for the other
devices.
The analog input charges a sample and hold capacitor.
The output of the sample and hold capacitor is the input
into the converter. The converter then generates a dig-
ital result of this analog level via successive approxima-
tion. The A/D conversion of the analog input signal
results in a corresponding 10-bit digital number. The
A/D module has high and low voltage reference input
that is software selectable to some combination of VDD,
VSS, RA2, or RA3.
The ADCON0 register, shown in Register 11-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 11-2, configures the func-
tions of the port pins. The port pins can be configured
as analog inputs (RA3 can also be the voltage refer-
ence), or as digital I/O.
Additional information on using the A/D module can be
found in the PIC® MCU Mid-Range Family Reference
Manual (DS33023).
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To oper-
ate in SLEEP, the A/D clock must be derived from the
A/D’s internal RC oscillator.
REGISTER 11-1: ADCON0 REGISTER (ADDRESS: 1Fh)
R/W-0
R/W-0
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
U-0
—
R/W-0
ADON
ADCS1
ADCS0
GO/DONE
bit 7
bit 0
bit 7-6
bit 5-3
ADCS1:ADCS0: A/D Conversion Clock Select bits
00= FOSC/2
01= FOSC/8
10= FOSC/32
11= FRC (clock derived from the internal A/D module RC oscillator)
CHS2:CHS0: Analog Channel Select bits
000= channel 0, (RA0/AN0)
001= channel 1, (RA1/AN1)
010= channel 2, (RA2/AN2)
011= channel 3, (RA3/AN3)
100= channel 4, (RA5/AN4)
(1)
101= channel 5, (RE0/AN5)
110= channel 6, (RE1/AN6)
111= channel 7, (RE2/AN7)
(1)
(1)
bit 2
GO/DONE: A/D Conversion Status bit
If ADON = 1:
1= A/D conversion in progress (setting this bit starts the A/D conversion)
0= A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D
conversion is complete)
bit 1
bit 0
Unimplemented: Read as '0'
ADON: A/D On bit
1= A/D converter module is operating
0= A/D converter module is shut-off and consumes no operating current
Note 1: These channels are not available on PIC16F873/876 devices.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
1998-2013 Microchip Technology Inc.
DS30292D-page 111
PIC16F87X
REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0
U-0
—
R/W-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7
ADFM: A/D Result Format Select bit
1= Right justified. 6 Most Significant bits of ADRESH are read as ‘0’.
0= Left justified. 6 Least Significant bits of ADRESL are read as ‘0’.
bit 6-4
bit 3-0
Unimplemented: Read as '0'
PCFG3:PCFG0: A/D Port Configuration Control bits:
(1)
(1)
(1)
PCFG3: AN7
PCFG0
AN6
AN5
AN4
RA5
AN3
RA3
AN2
RA2
AN1
RA1
AN0
RA0
CHAN/
Refs
VREF+ VREF-
(2)
RE2
RE1
RE0
0000
0001
0010
0011
0100
0101
011x
1000
1001
1010
1011
1100
1101
1110
1111
A
A
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
D
D
D
A
A
A
A
A
D
D
D
A
VREF+
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
VDD
RA3
VDD
RA3
VDD
RA3
VDD
RA3
VDD
RA3
RA3
RA3
RA3
VDD
RA3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RA2
VSS
VSS
RA2
RA2
RA2
VSS
RA2
8/0
7/1
5/0
4/1
3/0
2/1
0/0
6/2
6/0
5/1
4/2
3/2
2/2
1/0
1/2
VREF+
A
VREF+
D
VREF+ VREF-
A
A
A
VREF+
VREF+ VREF-
VREF+ VREF-
VREF+ VREF-
D
D
VREF+ VREF-
A = Analog input
D = Digital I/O
Note 1: These channels are not available on PIC16F873/876 devices.
2: This column indicates the number of analog channels available as A/D inputs and
the number of analog channels used as voltage reference inputs.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’0’ = Bit is cleared
x = Bit is unknown
The ADRESH:ADRESL registers contain the 10-bit
result of the A/D conversion. When the A/D conversion
is complete, the result is loaded into this A/D result reg-
ister pair, the GO/DONE bit (ADCON0<2>) is cleared
and the A/D interrupt flag bit ADIF is set. The block dia-
gram of the A/D module is shown in Figure 11-1.
To determine sample time, see Section 11.1. After this
acquisition time has elapsed, the A/D conversion can
be started.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
DS30292D-page 112
1998-2013 Microchip Technology Inc.
PIC16F87X
These steps should be followed for doing an A/D
Conversion:
3. Wait the required acquisition time.
4. Start conversion:
1. Configure the A/D module:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Configure analog pins/voltage reference and
digital I/O (ADCON1)
• Polling for the GO/DONE bit to be cleared
(with interrupts enabled); OR
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Waiting for the A/D interrupt
6. Read
A/D
result
register
pair
(ADRESH:ADRESL), clear bit ADIF if required.
7. For the next conversion, go to step 1 or step 2,
as required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before the next acquisition starts.
• Set ADIE bit
• Set PEIE bit
• Set GIE bit
FIGURE 11-1:
A/D BLOCK DIAGRAM
CHS2:CHS0
111
(1)
RE2/AN7
110
(1)
RE1/AN6
101
(1)
RE0/AN5
100
RA5/AN4
VAIN
011
(Input Voltage)
RA3/AN3/VREF+
010
RA2/AN2/VREF-
A/D
Converter
001
RA1/AN1
000
VDD
RA0/AN0
VREF+
(Reference
Voltage)
PCFG3:PCFG0
VREF-
(Reference
Voltage)
VSS
PCFG3:PCFG0
Note 1: Not available on PIC16F873/876 devices.
1998-2013 Microchip Technology Inc.
DS30292D-page 113
PIC16F87X
After the analog input channel is selected (changed),
this acquisition must be done before the conversion
can be started.
11.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 11-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
Figure 11-2. The maximum recommended imped-
ance for analog sources is 10 k. As the impedance
is decreased, the acquisition time may be decreased.
To calculate the minimum acquisition time,
Equation 11-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the PIC® MCU Mid-Range Reference Manual
(DS33023).
EQUATION 11-1: ACQUISITION TIME
TACQ
= Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
= TAMP + TC + TCOFF
= 2s + TC + [(Temperature -25°C)(0.05s/°C)]
= CHOLD (RIC + RSS + RS) In(1/2047)
= - 120pF (1k + 7k + 10k) In(0.0004885)
= 16.47s
TC
TACQ
= 2s + 16.47s + [(50°C -25C)(0.05s/C)
= 19.72s
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leak-
age specification.
4: After a conversion has completed, a 2.0TAD delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
FIGURE 11-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC 1k
RSS
RS
CHOLD
= DAC capacitance
= 120 pF
CPIN
5 pF
VA
I LEAKAGE
± 500 nA
VT = 0.6V
VSS
Legend CPIN
VT
= input capacitance
= threshold voltage
6V
5V
I LEAKAGE = leakage current at the pin due to
VDD 4V
3V
various junctions
2V
RIC
SS
= interconnect resistance
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
5 6 7 8 9 1011
Sampling Switch
(k)
DS30292D-page 114
1998-2013 Microchip Technology Inc.
PIC16F87X
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 s.
11.2 Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires a minimum 12TAD per 10-bit
conversion. The source of the A/D conversion clock is
software selected. The four possible options for TAD
are:
Table 11-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
• 2TOSC
• 8TOSC
• 32TOSC
• Internal A/D module RC oscillator (2-6 s)
TABLE 11-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD)
ADCS1:ADCS0
Maximum Device Frequency
Max.
Operation
2TOSC
8TOSC
00
01
10
11
1.25 MHz
5 MHz
32TOSC
RC(1, 2, 3)
20 MHz
(Note 1)
Note 1: The RC source has a typical TAD time of 4 s, but can vary between 2-6 s.
2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recom-
mended for SLEEP operation.
3: For extended voltage devices (LC), please refer to the Electrical Characteristics (Sections 15.1 and 15.2).
11.3 Configuring Analog Port Pins
The ADCON1 and TRIS registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
Note 1: When reading the port register, any pin
configured as an analog input channel will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
2: Analog levels on any pin that is defined as
a digital input (including the AN7:AN0
pins), may cause the input buffer to con-
sume current that is out of the device
specifications.
1998-2013 Microchip Technology Inc.
DS30292D-page 115
PIC16F87X
acquisition is started. After this 2TAD wait, acquisition
on the selected channel is automatically started. The
GO/DONE bit can then be set to start the conversion.
11.4 A/D Conversions
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2TAD wait is required before the next
In Figure 11-3, after the GO bit is set, the first time seg-
ment has a minimum of TCY and a maximum of TAD.
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 11-3:
A/D CONVERSION TAD CYCLES
TCY to TAD
TAD1 TAD2 TAD3
T
AD
4
TAD6
b5
T
AD
7
T
AD
8
T
AD
9
TAD10 TAD11
b1 b0
TAD5
b6
b9
b8
b7
b4
b3
b2
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
ADRES is loaded
GO bit is cleared
ADIF bit is set
Holding capacitor is connected to analog input
Format Select bit (ADFM) controls this justification.
Figure 11-4 shows the operation of the A/D result justi-
fication. The extra bits are loaded with ’0’s’. When an
A/D result will not overwrite these locations (A/D dis-
able), these registers may be used as two general
purpose 8-bit registers.
11.4.1
A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
FIGURE 11-4:
A/D RESULT JUSTIFICATION
10-bit Result
ADFM = 0
ADFM = 1
0
7
7
2 1 0 7
0 7 6 5
0
0000 00
0000 00
ADRESH
ADRESL
ADRESH
ADRESL
10-bit Result
10-bit Result
Left Justified
Right Justified
DS30292D-page 116
1998-2013 Microchip Technology Inc.
PIC16F87X
Turning off the A/D places the A/D module in its lowest
current consumption state.
11.5 A/D Operation During SLEEP
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D
module will then be turned off, although the ADON bit
will remain set.
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To allow the con-
version to occur during SLEEP, ensure the
SLEEPinstruction immediately follows the
instruction that sets the GO/DONE bit.
11.6 Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off, and
any conversion is aborted. All A/D input pins are con-
figured as analog inputs.
When the A/D clock source is another clock option (not
RC), a SLEEPinstruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
The value that is in the ADRESH:ADRESL registers is
not modified for
a
Power-on Reset. The
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
TABLE 11-2: REGISTERS/BITS ASSOCIATED WITH A/D
Value on
POR,
BOR
Value on
MCLR,
WDT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh,
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
10Bh,18Bh
(1)
0Ch
8Ch
1Eh
9Eh
1Fh
9Fh
85h
05h
PIR1
PIE1
PSPIF
PSPIE
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
xxxx xxxx uuuu uuuu
(1)
ADRESH A/D Result Register High Byte
ADRESL A/D Result Register Low Byte
ADCON0 ADCS1 ADCS0 CHS2
xxxx xxxx uuuu uuuu
CHS1
—
CHS0 GO/DONE
PCFG3 PCFG2
—
ADON 0000 00-0 0000 00-0
ADCON1
TRISA
ADFM
—
—
—
—
PCFG1 PCFG0 --0-0000 --0- 0000
PORTA Data Direction Register
PORTA Data Latch when written: PORTA pins when read
--11 1111 --11 1111
PORTA
TRISE
—
—
--0x 0000 --0u 0000
0000 -111 0000 -111
---- -xxx ---- -uuu
(1)
89h
IBF
—
OBF
—
IBOV PSPMODE
—
—
PORTE Data Direction bits
RE2 RE1 RE0
(1)
09h
PORTE
—
—
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note 1: These registers/bits are not available on the 28-pin devices.
1998-2013 Microchip Technology Inc.
DS30292D-page 117
PIC16F87X
NOTES:
DS30292D-page 118
1998-2013 Microchip Technology Inc.
PIC16F87X
SLEEP mode is designed to offer a very low current
Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
Wake-up, or through an interrupt.
12.0 SPECIAL FEATURES OF THE
CPU
All PIC16F87X devices have a host of features
intended to maximize system reliability, minimize cost
through elimination of external components, provide
power saving operating modes and offer code protec-
tion. These are:
Several oscillator options are also made available to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. A set of configuration bits is used to
select various options.
• Oscillator Selection
• RESET
Additional information on special features is available
in the PIC® MCU Mid-Range Reference Manual,
(DS33023).
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
12.1 Configuration Bits
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. The erased, or unprogrammed
value of the configuration word is 3FFFh. These bits
are mapped in program memory location 2007h.
• Watchdog Timer (WDT)
• SLEEP
• Code Protection
• ID Locations
It is important to note that address 2007h is beyond the
user program memory space, which can be accessed
only during programming.
• In-Circuit Serial Programming
• Low Voltage In-Circuit Serial Programming
• In-Circuit Debugger
PIC16F87X devices have a Watchdog Timer, which
can be shut-off only through configuration bits. It runs
off its own RC oscillator for added reliability.
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intended to keep the chip in RESET until the crystal
oscillator is stable. The other is the Power-up Timer
(PWRT), which provides a fixed delay of 72 ms (nomi-
nal) on power-up only. It is designed to keep the part in
RESET while the power supply stabilizes. With these
two timers on-chip, most applications need no external
RESET circuitry.
1998-2013 Microchip Technology Inc.
DS30292D-page 119
PIC16F87X
REGISTER 12-1: CONFIGURATION WORD (ADDRESS 2007h)(1)
CP1
CP0
DEBUG
—
WRT
CPD
LVP
BODEN
CP1
CP0
PWRTE
WDTE
F0SC1
F0SC0
bit0
bit13
(2)
bit 13-12,
bit 5-4
CP1:CP0: FLASH Program Memory Code Protection bits
11= Code protection off
10= 1F00h to 1FFFh code protected (PIC16F877, 876)
10= 0F00h to 0FFFh code protected (PIC16F874, 873)
01= 1000h to 1FFFh code protected (PIC16F877, 876)
01= 0800h to 0FFFh code protected (PIC16F874, 873)
00= 0000h to 1FFFh code protected (PIC16F877, 876)
00= 0000h to 0FFFh code protected (PIC16F874, 873)
bit 11
DEBUG: In-Circuit Debugger Mode
1= In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins
0= In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger.
bit 10
bit 9
Unimplemented: Read as ‘1’
WRT: FLASH Program Memory Write Enable
1= Unprotected program memory may be written to by EECON control
0= Unprotected program memory may not be written to by EECON control
bit 8
bit 7
bit 6
bit 3
bit 2
bit 1-0
CPD: Data EE Memory Code Protection
1= Code protection off
0= Data EEPROM memory code protected
LVP: Low Voltage In-Circuit Serial Programming Enable bit
1= RB3/PGM pin has PGM function, low voltage programming enabled
0= RB3 is digital I/O, HV on MCLR must be used for programming
(3)
BODEN: Brown-out Reset Enable bit
1= BOR enabled
0= BOR disabled
(3)
PWRTE: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
FOSC1:FOSC0: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
Note 1: The erased (unprogrammed) value of the configuration word is 3FFFh.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
3: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled.
DS30292D-page 120
1998-2013 Microchip Technology Inc.
PIC16F87X
FIGURE 12-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
12.2 Oscillator Configurations
12.2.1 OSCILLATOR TYPES
CONFIGURATION)
The PIC16F87X can be operated in four different oscil-
lator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
OSC1
Clock from
Ext. System
• LP
• XT
• HS
• RC
Low Power Crystal
PIC16F87X
OSC2
Crystal/Resonator
Open
High Speed Crystal/Resonator
Resistor/Capacitor
12.2.2
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 12-1). The
PIC16F87X oscillator design requires the use of a par-
allel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifica-
tions. When in XT, LP or HS modes, the device can
have an external clock source to drive the OSC1/
CLKIN pin (Figure 12-2).
TABLE 12-1: CERAMIC RESONATORS
Ranges Tested:
Mode
Freq.
OSC1
OSC2
XT
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF 68 - 100 pF
15 - 68 pF
15 - 68 pF
15 - 68 pF
15 - 68 pF
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
FIGURE 12-1:
CRYSTAL/CERAMIC
RESONATOROPERATION
(HS, XT OR LP
These values are for design guidance only.
See notes following Table 12-2.
Resonators Used:
OSC CONFIGURATION)
455 kHz Panasonic EFO-A455K04B
0.3%
(1)
C1
OSC1
2.0 MHz
4.0 MHz
8.0 MHz
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
0.5%
0.5%
0.5%
0.5%
To
Internal
Logic
XTAL
(3)
RF
OSC2
16.0 MHz Murata Erie CSA16.00MX
SLEEP
PIC16F87X
(2)
R
All resonators used did not have built-in capacitors.
s
(1)
C2
Note 1: See Table 12-1 and Table 12-2 for recom-
mended values of C1 and C2.
2: A series resistor (R ) may be required for AT
s
strip cut crystals.
3: RF varies with the crystal chosen.
1998-2013 Microchip Technology Inc.
DS30292D-page 121
PIC16F87X
TABLE 12-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
12.2.3
RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (REXT) and capacitor (CEXT) values, and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C compo-
nents used. Figure 12-3 shows how the R/C combina-
tion is connected to the PIC16F87X.
Crystal
Freq.
Cap. Range Cap. Range
Osc Type
C1
C2
LP
32 kHz
200 kHz
200 kHz
1 MHz
33 pF
15 pF
33 pF
15 pF
XT
HS
47-68 pF
15 pF
47-68 pF
15 pF
4 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
15-33 pF
15-33 pF
20 MHz
FIGURE 12-3:
RC OSCILLATOR MODE
These values are for design guidance only.
See notes following this table.
VDD
Crystals Used
32 kHz
200 kHz
1 MHz
4 MHz
8 MHz
Epson C-001R32.768K-A
STD XTL 200.000KHz
ECS ECS-10-13-1
± 20 PPM
± 20 PPM
± 50 PPM
± 50 PPM
REXT
Internal
OSC1
Clock
CEXT
VSS
PIC16F87X
ECS ECS-40-20-1
EPSON CA-301 8.000M-C ± 30 PPM
OSC2/CLKOUT
FOSC/4
Recommended values:
20 MHz EPSON CA-301 20.000M- ± 30 PPM
C
3 k REXT 100 k
CEXT > 20pF
Note 1: Higher capacitance increases the stability
of oscillator, but also increases the start-
up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external components.
3: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
4: When migrating from other PIC® MCU
devices, oscillator performance should be
verified.
DS30292D-page 122
1998-2013 Microchip Technology Inc.
PIC16F87X
SLEEP, and Brown-out Reset (BOR). They are not
affected by a WDT Wake-up, which is viewed as the
resumption of normal operation. The TO and PD bits
are set or cleared differently in different RESET situa-
tions as indicated in Table 12-4. These bits are used in
software to determine the nature of the RESET. See
Table 12-6 for a full description of RESET states of all
registers.
12.3 RESET
The PIC16F87X differentiates between various kinds of
RESET:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during SLEEP
• WDT Reset (during normal operation)
• WDT Wake-up (during SLEEP)
• Brown-out Reset (BOR)
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 12-4.
These devices have a MCLR noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
Some registers are not affected in any RESET condi-
tion. Their status is unknown on POR and unchanged
in any other RESET. Most other registers are reset to a
“RESET state” on Power-on Reset (POR), on the
MCLR and WDT Reset, on MCLR Reset during
It should be noted that a WDT Reset does not drive
MCLR pin low.
FIGURE 12-4:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
SLEEP
WDT
WDT
Module
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset
S
BODEN
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter
R
Q
OSC1
(1)
On-chip
RC OSC
PWRT
10-bit Ripple Counter
Enable PWRT
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
1998-2013 Microchip Technology Inc.
DS30292D-page 123
PIC16F87X
12.4 Power-On Reset (POR)
12.7 Brown-out Reset (BOR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, tie the MCLR pin directly
(or through a resistor) to VDD. This will eliminate
external RC components usually needed to create a
Power-on Reset. A maximum rise time for VDD is spec-
ified. See Electrical Specifications for details.
The configuration bit, BODEN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(parameter #35, about 100S), the brown-out situation
will reset the device. If VDD falls below VBOR for less
than TBOR, a RESET may not occur.
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer then keeps the device in RESET for
TPWRT (parameter #33, about 72mS). If VDD should fall
below VBOR during TPWRT, the Brown-out Reset pro-
cess will restart when VDD rises above VBOR with the
Power-up Timer Reset. The Power-up Timer is always
enabled when the Brown-out Reset circuit is enabled,
regardless of the state of the PWRT configuration bit.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the device
must be held in RESET until the operating conditions
are met. Brown-out Reset may be used to meet the
start-up conditions. For additional information, refer to
Application Note, AN007, “Power-up Trouble Shoot-
ing”, (DS00007).
12.8 Time-out Sequence
12.5 Power-up Timer (PWRT)
On power-up, the time-out sequence is as follows: The
PWRT delay starts (if enabled) when a POR Reset
occurs. Then OST starts counting 1024 oscillator
cycles when PWRT ends (LP, XT, HS). When the OST
ends, the device comes out of RESET.
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in RESET as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an accept-
able level. A configuration bit is provided to enable/dis-
able the PWRT.
If MCLR is kept low long enough, the time-outs will
expire. Bringing MCLR high will begin execution imme-
diately. This is useful for testing purposes or to synchro-
nize more than one PIC16F87X device operating in
parallel.
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation. See DC
parameters for details (TPWRT, parameter #33).
Table 12-5 shows the RESET conditions for the STA-
TUS, PCON and PC registers, while Table 12-6 shows
the RESET conditions for all the registers.
12.6 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a delay of
1024 oscillator cycles (from OSC1 input) after the
PWRT delay is over (if PWRT is enabled). This helps to
ensure that the crystal oscillator or resonator has
started and stabilized.
12.9 Power Control/Status Register
(PCON)
The Power Control/Status Register, PCON, has up to
two bits depending upon the device.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or Wake-up from
SLEEP.
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent RESETS to see if
bit BOR cleared, indicating a BOR occurred. When the
Brown-out Reset is disabled, the state of the BOR bit is
unpredictable and is, therefore, not valid at any time.
Bit1 is POR (Power-on Reset Status bit). It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
TABLE 12-3: TIME-OUT IN VARIOUS SITUATIONS
Power-up
Wake-up from
Oscillator Configuration
Brown-out
SLEEP
PWRTE = 0
PWRTE = 1
XT, HS, LP
RC
72 ms + 1024TOSC
72 ms
1024TOSC
—
72 ms + 1024TOSC
72 ms
1024TOSC
—
DS30292D-page 124
1998-2013 Microchip Technology Inc.
PIC16F87X
TABLE 12-4: STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
0
0
1
1
1
1
1
x
x
x
0
1
1
1
1
1
0
x
1
0
0
u
1
1
x
0
1
1
0
u
0
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Legend: x= don’t care, u = unchanged
TABLE 12-5: RESET CONDITION FOR SPECIAL REGISTERS
Program
STATUS
Register
PCON
Register
Condition
Counter
Power-on Reset
000h
000h
0001 1xxx
000u uuuu
0001 0uuu
0000 1uuu
uuu0 0uuu
0001 1uuu
uuu1 0uuu
---- --0x
---- --uu
---- --uu
---- --uu
---- --uu
---- --u0
---- --uu
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset
000h
000h
WDT Wake-up
PC + 1
Brown-out Reset
000h
PC + 1(1)
Interrupt wake-up from SLEEP
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as '0'
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
1998-2013 Microchip Technology Inc.
DS30292D-page 125
PIC16F87X
TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset
Wake-up via WDT or
Interrupt
Register
Devices
W
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
xxxx xxxx
N/A
uuuu uuuu
N/A
uuuu uuuu
N/A
INDF
TMR0
xxxx xxxx
0000h
uuuu uuuu
0000h
uuuu uuuu
PC + 1(2)
PCL
STATUS
FSR
0001 1xxx
xxxx xxxx
--0x 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- -xxx
---0 0000
0000 000x
r000 0000
0000 0000
-r-0 0--0
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
-000 0000
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 000x
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
0000 00-0
1111 1111
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
r000 0000
0000 0000
000q quuu(3)
uuuu uuuu
--0u 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---0 0000
0000 000u
r000 0000
0000 0000
-r-0 0--0
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0000
-000 0000
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
0000 000x
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
0000 00-0
1111 1111
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
r000 0000
0000 0000
uuuq quuu(3)
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---u uuuu
uuuu uuuu(1)
ruuu uuuu(1)
uuuu uuuu(1)
-r-u u--u(1)
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uu-u
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
ruuu uuuu
uuuu uuuu
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
OPTION_REG
TRISA
TRISB
TRISC
TRISD
TRISE
PIE1
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as '0', q= value depends on condition,
r= reserved, maintain clear
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 12-5 for RESET value for specific condition.
DS30292D-page 126
1998-2013 Microchip Technology Inc.
PIC16F87X
TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset
Wake-up via WDT or
Interrupt
Register
PIE2
Devices
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
873 874 876 877
-r-0 0--0
---- --qq
1111 1111
0000 0000
--00 0000
0000 -010
0000 0000
xxxx xxxx
0--- 0000
0--- 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
x--- x000
---- ----
-r-0 0--0
---- --uu
1111 1111
0000 0000
--00 0000
0000 -010
0000 0000
uuuu uuuu
0--- 0000
0--- 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
u--- u000
---- ----
-r-u u--u
---- --uu
1111 1111
uuuu uuuu
--uu uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
u--- uuuu
u--- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u--- uuuu
---- ----
PCON
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ADRESL
ADCON1
EEDATA
EEADR
EEDATH
EEADRH
EECON1
EECON2
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as '0', q= value depends on condition,
r= reserved, maintain clear
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 12-5 for RESET value for specific condition.
FIGURE 12-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
1998-2013 Microchip Technology Inc.
DS30292D-page 127
PIC16F87X
FIGURE 12-6:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 12-7:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 12-8:
SLOW RISE TIME (MCLR TIED TO VDD)
5V
1V
VDD
MCLR
0V
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30292D-page 128
1998-2013 Microchip Technology Inc.
PIC16F87X
The RB0/INT pin interrupt, the RB port change inter-
rupt, and the TMR0 overflow interrupt flags are con-
tained in the INTCON register.
12.10 Interrupts
The PIC16F87X family has up to 14 sources of inter-
rupt. The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has indi-
vidual and global interrupt enable bits.
The peripheral interrupt flags are contained in the spe-
cial function registers, PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers, PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
Note: Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit, or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two-cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit, PEIE bit, or GIE bit.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
FIGURE 12-9:
INTERRUPT LOGIC
EEIF
EEIE
PSPIF
PSPIE
Wake-up (If in SLEEP mode)
ADIF
ADIE
T0IF
T0IE
INTF
INTE
RCIF
RCIE
Interrupt to CPU
TXIF
TXIE
RBIF
RBIE
SSPIF
SSPIE
PEIE
GIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
BCLIF
BCLIE
The following table shows which devices have which interrupts.
Device
T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF EEIF BCLIF CCP2IF
PIC16F876/873 Yes Yes Yes
PIC16F877/874 Yes Yes Yes
—
Yes
Yes
Yes Yes
Yes Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1998-2013 Microchip Technology Inc.
DS30292D-page 129
PIC16F87X
12.10.1 INT INTERRUPT
12.11 Context Saving During Interrupts
External interrupt on the RB0/INT pin is edge triggered,
either rising, if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit, GIE, decides whether or not the
processor branches to the interrupt vector following
wake-up. See Section 12.13 for details on SLEEP
mode.
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt, (i.e., W register and STATUS
register). This will have to be implemented in software.
For the PIC16F873/874 devices, the register W_TEMP
must be defined in both banks 0 and 1 and must be
defined at the same offset from the bank base address
(i.e., If W_TEMP is defined at 0x20 in bank 0, it must
also be defined at 0xA0 in bank 1). The registers,
PCLATH_TEMP and STATUS_TEMP, are only defined
in bank 0.
Since the upper 16 bytes of each bank are common in
the PIC16F876/877 devices, temporary holding regis-
ters W_TEMP, STATUS_TEMP, and PCLATH_TEMP
should be placed in here. These 16 locations don’t
require banking and therefore, make it easier for con-
text save and restore. The same code shown in
Example 12-1 can be used.
12.10.2 TMR0 INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>) (Section 5.0).
12.10.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>)
(Section 3.2).
EXAMPLE 12-1:
SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
:
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
;Copy W to TEMP register
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
:(ISR)
:
;(Insert user code here)
MOVF
MOVWF
SWAPF
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Swap W_TEMP into W
DS30292D-page 130
1998-2013 Microchip Technology Inc.
PIC16F87X
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
12.12 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscil-
lator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. That means that the WDT will
run, even if the clock on the OSC1/CLKIN and OSC2/
CLKOUT pins of the device has been stopped, for
example, by execution of a SLEEPinstruction.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and the postscaler, if
assigned to the WDT, and prevent it from
timing out and generating
RESET condition.
a device
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS regis-
ter will be cleared upon a Watchdog Timer time-out.
2: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but
the prescaler assignment is not changed.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 12.1).
FIGURE 12-10:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 5-1)
0
Postscaler
M
1
U
WDT Timer
X
8
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 5-1)
0
1
MUX
PSA
WDT
Time-out
Note:
PSA and PS2:PS0 are bits in the OPTION_REG register.
TABLE 12-7: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
Bit 7
(1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2007h
Config. bits
BODEN(1)
INTEDG
CP1
CP0
PWRTE(1)
PSA
WDTE
PS2
FOSC1
PS1
FOSC0
PS0
81h,181h OPTION_REG RBPU
T0CS
T0SE
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for operation of these bits.
1998-2013 Microchip Technology Inc.
DS30292D-page 131
PIC16F87X
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOPafter the SLEEPinstruction.
12.13 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should also be considered.
12.13.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEPinstruction, the SLEEPinstruction will com-
plete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
The MCLR pin must be at a logic high level (VIHMC).
12.13.1 WAKE-UP FROM SLEEP
• If the interrupt occurs during or after the execu-
tion of a SLEEPinstruction, the device will imme-
diately wake-up from SLEEP. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
The device can wake-up from SLEEP through one of
the following events:
1. External RESET input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change or
peripheral interrupt.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and cause a “wake-up”. The TO and PD bits
in the STATUS register can be used to determine the
cause of device RESET. The PD bit, which is set on
power-up, is cleared when SLEEPis invoked. The TO
bit is cleared if a WDT time-out occurred and caused
wake-up.
To ensure that the WDT is cleared, a CLRWDTinstruc-
tion should be executed before a SLEEPinstruction.
The following peripheral interrupts can wake the device
from SLEEP:
1. PSP read or write (PIC16F874/877 only).
2. TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
3. CCP Capture mode interrupt.
4. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
5. SSP (START/STOP) bit detect interrupt.
6. SSP transmit or receive in Slave mode
(SPI/I2C).
7. USART RX or TX (Synchronous Slave mode).
8. A/D conversion (when A/D clock source is RC).
9. EEPROM write operation completion
Other peripherals cannot generate interrupts since dur-
ing SLEEP, no on-chip clocks are present.
DS30292D-page 132
1998-2013 Microchip Technology Inc.
PIC16F87X
FIGURE 12-11:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(2)
TOST
CLKOUT(4)
INT pin
INTF Flag
Interrupt Latency(2)
(INTCON<1>)
GIE bit
Processor in
SLEEP
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
Fetched
Instruction
Executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(PC - 1)
Inst(0004h)
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = '1' assumed. In this case, after wake- up, the processor jumps to the interrupt routine.
If GIE = '0', execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
12.14 In-Circuit Debugger
12.15 Program Verification/Code
Protection
When the DEBUG bit in the configuration word is pro-
grammed to a '0', the In-Circuit Debugger functionality
is enabled. This function allows simple debugging func-
tions when used with MPLAB® ICD. When the micro-
controller has this feature enabled, some of the
resources are not available for general use. Table 12-8
shows which features are consumed by the back-
ground debugger.
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
12.16 ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during program/verify. It is recom-
mended that only the 4 Least Significant bits of the ID
location are used.
TABLE 12-8: DEBUGGER RESOURCES
I/O pins
RB6, RB7
1 level
Stack
Program Memory
Address 0000h must be NOP
Last 100h words
Data Memory
0x070 (0x0F0, 0x170, 0x1F0)
0x1EB - 0x1EF
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, GND,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip, or one of
the third party development tool companies.
1998-2013 Microchip Technology Inc.
DS30292D-page 133
PIC16F87X
12.17 In-Circuit Serial Programming
Note 1: The High Voltage Programming mode is
always available, regardless of the state
of the LVP bit, by applying VIHH to the
MCLR pin.
PIC16F87X microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware, or a custom firm-
ware to be programmed.
2: While in Low Voltage ICSP mode, the
RB3 pin can no longer be used as a gen-
eral purpose I/O pin.
3: When using low voltage ICSP program-
ming (LVP) and the pull-ups on PORTB
are enabled, bit 3 in the TRISB register
must be cleared to disable the pull-up on
RB3 and ensure the proper operation of
the device.
When using ICSP, the part must be supplied at 4.5V to
5.5V, if a bulk erase will be executed. This includes
reprogramming of the code protect, both from an on-
state to off-state. For all other cases of ICSP, the part
may be programmed at the normal operating voltages.
This means calibration values, unique user IDs, or user
code can be reprogrammed or added.
4: RB3 should not be allowed to float if LVP
is enabled. An external pull-down device
should be used to default the device to
normal operating mode. If RB3 floats
high, the PIC16F87X device will enter
Programming mode.
For complete details of serial programming, please
refer to the EEPROM Memory Programming Specifica-
tion for the PIC16F87X (DS39025).
5: LVP mode is enabled by default on all
devices shipped from Microchip. It can be
disabled by clearing the LVP bit in the
CONFIG register.
12.18 Low Voltage ICSP Programming
The LVP bit of the configuration word enables low volt-
age ICSP programming. This mode allows the micro-
controller to be programmed via ICSP using a VDD
source in the operating voltage range. This only means
that VPP does not have to be brought to VIHH, but can
instead be left at the normal operating voltage. In this
mode, the RB3/PGM pin is dedicated to the program-
ming function and ceases to be a general purpose I/O
pin. During programming, VDD is applied to the MCLR
pin. To enter Programming mode, VDD must be applied
to the RB3/PGM, provided the LVP bit is set. The LVP
bit defaults to on (‘1’) from the factory.
6: Disabling LVP will provide maximum com-
patibility to other PIC16CXXX devices.
If Low Voltage Programming mode is not used, the LVP
bit can be programmed to a '0' and RB3/PGM becomes
a digital I/O pin. However, the LVP bit may only be pro-
grammed when programming is entered with VIHH on
MCLR. The LVP bit can only be charged when using
high voltage on MCLR.
It should be noted, that once the LVP bit is programmed
to 0, only the High Voltage Programming mode is avail-
able and only High Voltage Programming mode can be
used to program the device.
When using low voltage ICSP, the part must be supplied
at 4.5V to 5.5V, if a bulk erase will be executed. This
includes reprogramming of the code protect bits from an
on-state to off-state. For all other cases of low voltage
ICSP, the part may be programmed at the normal oper-
ating voltage. This means calibration values, unique
user IDs, or user code can be reprogrammed or added.
DS30292D-page 134
1998-2013 Microchip Technology Inc.
PIC16F87X
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 s. If a conditional test is true, or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 s.
13.0 INSTRUCTION SET SUMMARY
Each PIC16F87X instruction is a 14-bit word, divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16F87X instruction
set summary in Table 13-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 13-1
shows the opcode field descriptions.
For byte-oriented instructions, 'f' represents a file reg-
ister designator and 'd' represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
Table 13-2 lists the instructions recognized by the
MPASMTM assembler.
Figure 13-1 shows the general formats that the instruc-
tions can have.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
Note: To maintain upward compatibility with
future PIC16F87X products, do not use the
OPTIONand TRISinstructions.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the address of the
file in which the bit is located.
All examples use the following format to represent a
hexadecimal number:
0xhh
For literal and control operations, 'k' represents an
where h signifies a hexadecimal digit.
eight or eleven bit constant or literal value.
FIGURE 13-1:
GENERAL FORMAT FOR
INSTRUCTIONS
TABLE 13-1: OPCODE FIELD
DESCRIPTIONS
Byte-oriented file register operations
13
8
7
6
0
Field
Description
OPCODE
d
f (FILE #)
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit address within an 8-bit file register
Literal field, constant data or label
Bit-oriented file register operations
13 10 9
b (BIT #)
7
6
0
Don't care location (= 0or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
OPCODE
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
Literal and control operations
General
PC
TO
PD
Program Counter
Time-out bit
13
8
7
0
0
OPCODE
k (literal)
Power-down bit
k = 8-bit immediate value
The instruction set is highly orthogonal and is grouped
into three basic categories:
CALL and GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
• Byte-oriented operations
• Bit-oriented operations
k (literal)
• Literal and control operations
A description of each instruction is available in the PIC®
MCU Mid-Range Reference Manual, (DS33023).
1998-2013 Microchip Technology Inc.
DS30292D-page 135
PIC16F87X
TABLE 13-2: PIC16F87X INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Description
Operands
Status
Affected
Cycles
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00 0111 dfff ffff C,DC,Z
1,2
1,2
2
00 0101 dfff ffff
00 0001 lfff ffff
00 0001 0xxx xxxx
00 1001 dfff ffff
00 0011 dfff ffff
00 1011 dfff ffff
00 1010 dfff ffff
00 1111 dfff ffff
00 0100 dfff ffff
00 1000 dfff ffff
00 0000 lfff ffff
00 0000 0xx0 0000
00 1101 dfff ffff
00 1100 dfff ffff
Z
Z
Z
Z
Z
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
DECFSZ
INCF
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
Move W to f
No Operation
-
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
00 0010 dfff ffff C,DC,Z
00 1110 dfff ffff
00 0110 dfff ffff
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01 00bb bfff ffff
1,2
1,2
3
01 01bb bfff ffff
01 10bb bfff ffff
01 11bb bfff ffff
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11 111x kkkk kkkk C,DC,Z
11 1001 kkkk kkkk
10 0kkk kkkk kkkk
00 0000 0110 0100
10 1kkk kkkk kkkk
11 1000 kkkk kkkk
11 00xx kkkk kkkk
00 0000 0000 1001
11 01xx kkkk kkkk
00 0000 0000 1000
00 0000 0110 0011
Z
TO,PD
Z
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
TO,PD
11 110x kkkk kkkk C,DC,Z
11 1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PIC® MCU Mid-Range Family Ref-
erence Manual (DS33023).
DS30292D-page 136
1998-2013 Microchip Technology Inc.
PIC16F87X
13.1 Instruction Descriptions
ADDLW
Add Literal and W
BCF
Bit Clear f
Syntax:
[label] ADDLW
0 k 255
k
Syntax:
[label] BCF f,b
Operands:
Operation:
Status Affected:
Description:
Operands:
0 f 127
0 b 7
(W) + k (W)
C, DC, Z
Operation:
0 (f<b>)
Status Affected:
Description:
None
The contents of the W register
are added to the eight bit literal 'k'
and the result is placed in the W
register.
Bit 'b' in register 'f' is cleared.
BSF
Bit Set f
ADDWF
Add W and f
Syntax:
[label] BSF f,b
Syntax:
[label] ADDWF f,d
Operands:
0 f 127
0 b 7
Operands:
0 f 127
d
Operation:
1 (f<b>)
Operation:
(W) + (f) (destination)
Status Affected:
Description:
None
Status Affected: C, DC, Z
Bit 'b' in register 'f' is set.
Description:
Add the contents of the W register
with register 'f'. If 'd' is 0, the result
is stored in the W register. If 'd' is
1, the result is stored back in
register 'f'.
BTFSS
Bit Test f, Skip if Set
ANDLW
AND Literal with W
Syntax:
[label] BTFSS f,b
Syntax:
[label] ANDLW
0 k 255
k
Operands:
0 f 127
0 b < 7
Operands:
Operation:
Status Affected:
Description:
(W) .AND. (k) (W)
Operation:
skip if (f<b>) = 1
Z
Status Affected: None
The contents of W register are
AND’ed with the eight bit literal
'k'. The result is placed in the W
register.
Description:
If bit 'b' in register 'f' is '0', the next
instruction is executed.
If bit 'b' is '1', then the next instruc-
tion is discarded and a NOPis
executed instead, making this a
2TCY instruction.
BTFSC
Bit Test, Skip if Clear
ANDWF
AND W with f
Syntax:
[label] BTFSC f,b
Syntax:
[label] ANDWF f,d
Operands:
0 f 127
0 b 7
Operands:
0 f 127
d
Operation:
skip if (f<b>) = 0
Operation:
(W) .AND. (f) (destination)
Status Affected: None
Status Affected:
Description:
Z
Description: If bit 'b' in register 'f' is '1', the next
AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W register. If 'd' is 1, the result
is stored back in register 'f'.
instruction is executed.
If bit 'b', in register 'f', is '0', the
next instruction is discarded, and
a NOPis executed instead, making
this a 2TCY instruction.
1998-2013 Microchip Technology Inc.
DS30292D-page 137
PIC16F87X
CALL
Call Subroutine
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL k
0 k 2047
Syntax:
[ label ] CLRWDT
Operands:
Operation:
Operands:
Operation:
None
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Affected: None
Status Affected: TO, PD
Description:
Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven-bit immedi-
ate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALLis
a two-cycle instruction.
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets
the prescaler of the WDT. Status
bits TO and PD are set.
CLRF
Clear f
COMF
Complement f
Syntax:
[label] CLRF
0 f 127
f
Syntax:
[ label ] COMF f,d
Operands:
Operation:
Operands:
0 f 127
d [0,1]
00h (f)
1 Z
Operation:
(f) (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
The contents of register 'f' are
cleared and the Z bit is set.
The contents of register 'f' are
complemented. If 'd' is 0, the
result is stored in W. If 'd' is 1, the
result is stored back in register 'f'.
CLRW
Clear W
DECF
Decrement f
Syntax:
[ label ] CLRW
Syntax:
[label] DECF f,d
Operands:
Operation:
None
Operands:
0 f 127
d [0,1]
00h (W)
1 Z
Operation:
(f) - 1 (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
W register is cleared. Zero bit (Z)
is set.
Decrement register 'f'. If 'd' is 0,
the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
DS30292D-page 138
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PIC16F87X
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ] INCFSZ f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
Operation:
(f) + 1 (destination),
skip if result = 0
skip if result = 0
Status Affected: None
Status Affected: None
Description:
The contents of register 'f' are
Description:
The contents of register 'f' are
decremented. If 'd' is 0, the result
is placed in the W register. If 'd' is
1, the result is placed back in
register 'f'.
incremented. If 'd' is 0, the result is
placed in the W register. If 'd' is 1,
the result is placed back in
register 'f'.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
then a NOPis executed instead
making it a 2TCY instruction.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
a NOPis executed instead, making
it a 2TCY instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR Literal with W
Syntax:
[ label ] GOTO k
0 k 2047
Syntax:
[ label ] IORLW k
0 k 255
Operands:
Operation:
Operands:
Operation:
Status Affected:
Description:
k PC<10:0>
PCLATH<4:3> PC<12:11>
(W) .OR. k (W)
Z
Status Affected: None
The contents of the W register are
OR’ed with the eight bit literal 'k'.
The result is placed in the W
register.
Description:
GOTOis an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTOis a two-
cycle instruction.
IORWF
Inclusive OR W with f
INCF
Increment f
Syntax:
[ label ] IORWF f,d
Syntax:
[ label ] INCF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(W) .OR. (f) (destination)
Operation:
(f) + 1 (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Inclusive OR the W register with
register 'f'. If 'd' is 0 the result is
placed in the W register. If 'd' is 1
the result is placed back in
register 'f'.
The contents of register 'f' are
incremented. If 'd' is 0, the result
is placed in the W register. If 'd' is
1, the result is placed back in
register 'f'.
1998-2013 Microchip Technology Inc.
DS30292D-page 139
PIC16F87X
MOVF
Move f
NOP
No Operation
Syntax:
[ label ] MOVF f,d
Syntax:
[ label ] NOP
None
Operands:
0 f 127
d [0,1]
Operands:
Operation:
No operation
Operation:
(f) (destination)
Status Affected: None
Status Affected:
Description:
Z
Description:
No operation.
The contents of register f are
moved to a destination dependant
upon the status of d. If d = 0,
destination is W register. If d = 1,
the destination is file register f itself.
d = 1 is useful to test a file register,
since status flag Z is affected.
MOVLW
Move Literal to W
RETFIE
Return from Interrupt
Syntax:
[ label ] MOVLW k
0 k 255
k (W)
Syntax:
[ label ] RETFIE
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
None
TOS PC,
1 GIE
None
Status Affected: None
The eight bit literal 'k' is loaded
into W register. The don’t cares
will assemble as 0’s.
MOVWF
Move W to f
RETLW
Return with Literal in W
Syntax:
[ label ] MOVWF
0 f 127
(W) (f)
f
Syntax:
[ label ] RETLW k
0 k 255
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
k (W);
TOS PC
None
Status Affected: None
Move data from W register to
register 'f'.
Description: The W register is loaded with the
eight bit literal 'k'. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
DS30292D-page 140
1998-2013 Microchip Technology Inc.
PIC16F87X
RLF
Rotate Left f through Carry
SLEEP
Syntax:
[ label ] RLF f,d
Syntax:
[ label ] SLEEP
Operands:
0 f 127
d [0,1]
Operands:
Operation:
None
00h WDT,
0 WDT prescaler,
1 TO,
Operation:
See description below
C
Status Affected:
Description:
0 PD
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0, the result is placed in
the W register. If 'd' is 1, the result is
stored back in register 'f'.
Status Affected:
Description:
TO, PD
The power-down status bit, PD is
cleared. Time-out status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
C
Register f
The processor is put into SLEEP
mode with the oscillator stopped.
RETURN
Return from Subroutine
SUBLW
Subtract W from Literal
Syntax:
[ label ] RETURN
None
Syntax:
[ label ] SUBLW k
0 k 255
Operands:
Operation:
Operands:
Operation:
TOS PC
k - (W) W)
Status Affected: None
Status Affected: C, DC, Z
Description:
Return from subroutine. The stack
Description:
The W register is subtracted (2’s
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
complement method) from the
eight-bit literal 'k'. The result is
placed in the W register.
RRF
Rotate Right f through Carry
SUBWF
Subtract W from f
Syntax:
[ label ] RRF f,d
Syntax:
[ label ] SUBWF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
See description below
C
Operation:
(f) - (W) destination)
Status Affected:
Description:
Status
Affected:
C, DC, Z
The contents of register 'f' are
rotated one bit to the right through
the Carry Flag. If 'd' is 0, the result
is placed in the W register. If 'd' is
1, the result is placed back in
register 'f'.
Description:
Subtract (2’s complement method)
W register from register 'f'. If 'd' is 0,
the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
C
Register f
1998-2013 Microchip Technology Inc.
DS30292D-page 141
PIC16F87X
SWAPF
Swap Nibbles in f
XORWF
Exclusive OR W with f
Syntax:
[ label ] SWAPF f,d
Syntax:
[label] XORWF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Operation:
(W) .XOR. (f) destination)
Status Affected:
Description:
Z
Status Affected: None
Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0, the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
Description:
The upper and lower nibbles of
register 'f' are exchanged. If 'd' is
0, the result is placed in the W
register. If 'd' is 1, the result is
placed in register 'f'.
XORLW
Exclusive OR Literal with W
Syntax:
[label] XORLW k
0 k 255
Operands:
Operation:
Status Affected:
Description:
(W) .XOR. k W)
Z
The contents of the W register
are XOR’ed with the eight-bit lit-
eral 'k'. The result is placed in
the W register.
DS30292D-page 142
1998-2013 Microchip Technology Inc.
PIC16F87X
The MPLAB IDE allows you to:
14.0 DEVELOPMENT SUPPORT
• Edit your source files (either assembly or ‘C’)
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools (auto-
matically updates all project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- absolute listing file
- machine code
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
The ability to use MPLAB IDE with multiple debugging
tools allows users to easily switch from the cost-
effective simulator to a full-featured emulator with
minimal retraining.
• Simulators
- MPLAB SIM Software Simulator
• Emulators
14.2 MPASM Assembler
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
• In-Circuit Debugger
The MPASM assembler is a full-featured universal
macro assembler for all PIC® MCUs.
- MPLAB ICD for PIC16F87X
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Entry-Level Development
Programmer
The MPASM assembler has a command line interface
and a Windows shell. It can be used as a stand-alone
application on a Windows 3.x or greater system, or it
can be used through MPLAB IDE. The MPASM assem-
bler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
detail memory usage and symbol reference, an abso-
lute LST file that contains source lines and generated
machine code, and a COD file for debugging.
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 17 Demonstration Board
- KEELOQ® Demonstration Board
The MPASM assembler features include:
• Integration into MPLAB IDE projects.
• User-defined macros to streamline assembly
code.
14.1 MPLAB Integrated Development
Environment Software
• Conditional assembly for multi-purpose source
files.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. The MPLAB IDE is a Windows®-based
application that contains:
• Directives that allow complete control over the
assembly process.
14.3 MPLAB C17 and MPLAB C18
C Compilers
• An interface to debugging tools
- simulator
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI ‘C’ compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers, respectively. These compilers provide
powerful integration capabilities and ease of use not
found with other compilers.
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor
• A project manager
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• Customizable toolbar and key mapping
• A status bar
• On-line help
1998-2013 Microchip Technology Inc.
DS30292D-page 143
PIC16F87X
14.4 MPLINK Object Linker/
MPLIB Object Librarian
14.6 MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can also
link relocatable objects from pre-compiled libraries,
using directives from a linker script.
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC MCU
microcontrollers (MCUs). Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment (IDE),
which allows editing, building, downloading and source
debugging from a single environment.
The MPLIB object librarian is a librarian for pre-
compiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine will be linked in with the application. This allows
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PIC microcontrollers.
The MPLINK object linker features include:
• Integration with MPASM assembler and MPLAB
C17 and MPLAB C18 C compilers.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows environment were chosen to best
make these features available to you, the end user.
• Allows all memory areas to be defined as sections
to provide link-time flexibility.
The MPLIB object librarian features include:
• Easier linking because single libraries can be
included instead of many smaller files.
• Helps keep code maintainable by grouping
related modules together.
14.7 ICEPIC In-Circuit Emulator
• Allows libraries to be created and modules to be
added, listed, replaced, deleted or extracted.
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit One-
Time-Programmable (OTP) microcontrollers. The mod-
ular system can support different subsets of PIC16C5X
or PIC16CXXX products through the use of inter-
changeable personality modules, or daughter boards.
The emulator is capable of emulating without target
application circuitry being present.
14.5 MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC-hosted environment by simulating the
PIC MCU series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user-defined key press, to any of the pins. The
execution can be performed in single step, execute
until break, or trace mode.
The MPLAB SIM simulator fully supports symbolic debug-
ging using the MPLAB C17 and the MPLAB C18 C com-
pilers and the MPASM assembler. The software simulator
offers the flexibility to develop and debug code outside of
the laboratory environment, making it an excellent multi-
project software development tool.
DS30292D-page 144
1998-2013 Microchip Technology Inc.
PIC16F87X
14.8 MPLAB ICD In-Circuit Debugger
14.11 PICDEM 1 Low Cost PIC MCU
Demonstration Board
Microchip's In-Circuit Debugger, MPLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based on the FLASH PIC16F87X and can be used to
develop for this and other PIC microcontrollers from the
PIC16CXXX family. The MPLAB ICD utilizes the in-cir-
cuit debugging capability built into the PIC16F87X. This
The PICDEM 1 demonstration board is a simple board
which demonstrates the capabilities of several of
Microchip’s microcontrollers. The microcontrollers sup-
ported are: PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcon-
trollers provided with the PICDEM 1 demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulator and download the firmware to the emu-
lator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simu-
lated analog input, push button switches and eight
LEDs connected to PORTB.
feature, along with Microchip's
In-Circuit Serial
ProgrammingTM protocol, offers cost-effective in-circuit
FLASH debugging from the graphical user interface of
the MPLAB Integrated Development Environment. This
enables a designer to develop and debug source code
by watching variables, single-stepping and setting
break points. Running at full speed enables testing
hardware in real-time.
14.9 PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions
and error messages, keys to enter commands and a
modular detachable socket assembly to support various
package types. In stand-alone mode, the PRO MATE II
device programmer can read, verify, or program PIC
devices. It can also set code protection in this mode.
14.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PICDEM 2 demonstration board is a simple dem-
onstration board that supports the PIC16C62,
PIC16C64, PIC16C65, PIC16C73 and PIC16C74
microcontrollers. All the necessary hardware and soft-
ware is included to run the basic demonstration pro-
grams. The user can program the sample
microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches, a potentiometer for simulated analog input, a
serial EEPROM to demonstrate usage of the I2CTM bus
and separate headers for connection to an LCD
module and a keypad.
14.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient.
The PICSTART Plus development programmer sup-
ports all PIC devices with up to 40 pins. Larger pin
count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.
1998-2013 Microchip Technology Inc.
DS30292D-page 145
PIC16F87X
14.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
14.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. All neces-
sary hardware is included to run basic demo programs,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM 17 dem-
onstration board supports downloading of programs to
and executing out of external FLASH memory on board.
The PICDEM 17 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMASTER emulator and all of the sample programs
can be run and modified using either emulator. Addition-
ally, a generous prototype area is available for user
hardware.
The PICDEM 3 demonstration board is a simple dem-
onstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-pin PLCC microcontrollers with an LCD Mod-
ule. All the necessary hardware and software is
included to run the basic demonstration programs. The
user can program the sample microcontrollers pro-
vided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer, or a PICSTART Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding hardware and connecting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commons and 12 segments, that is capable of display-
ing time, temperature and day of the week. The
PICDEM 3 demonstration board provides an additional
RS-232 interface and Windows software for showing
the demultiplexed LCD signals on a PC. A simple serial
interface allows the user to construct a hardware
demultiplexer for the LCD signals.
14.15 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS eval-
uation kit includes a LCD display to show changing
codes, a decoder to decode transmissions and a pro-
gramming interface to program test transmitters.
DS30292D-page 146
1998-2013 Microchip Technology Inc.
PIC16F87X
TABLE 14-1: DEVELOPMENT TOOLS FROM MICROCHIP
0 1 5 2 P M C
X X X C R M F
H C S X X X
X X C 9 3
/ X X C 2 5
/ X X C 2 4
X X C 8 2 C 1 P I
X 7 X 7 C 1 C I P
X 4 1 7 C I C P
X 9 X 6 C 1 C I P
X 8 X 6 F 1 C I P
X 8 1 6 C I C P
X 7 X 6 C 1 C I P
X 7 1 6 C I C P
X 6 2 1 6 C I F P
X X X C 6 C 1 P I
X 6 1 6 C I C P
X 5 1 6 C I C P
0 0 1 4 C I 0 P
X X X C 2 C 1 P I
s o l T e o r a w f t S o s r o t a u l E m r e g g u b D e s r e m m a o g P r r
s t K l a i E d v n a s d r a B o o m D e
1998-2013 Microchip Technology Inc.
DS30292D-page 147
PIC16F87X
NOTES:
DS30292D-page 148
1998-2013 Microchip Technology Inc.
PIC16F87X
15.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.................................................................................................................-55 to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4) ....................................... -0.3 V to (VDD + 0.3 V)
Voltage on VDD with respect to VSS ........................................................................................................... -0.3 to +7.5 V
Voltage on MCLR with respect to VSS (Note 2) ................................................................................................0 to +14 V
Voltage on RA4 with respect to Vss.................................................................................................................0 to +8.5 V
Total power dissipation (Note 1) ..............................................................................................................................1.0 W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk byPORTA, PORTB, and PORTE (combined) (Note 3)...................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3)..............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3) .................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3) ............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL)
2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin, rather than
pulling this pin directly to VSS.
3: PORTD and PORTE are not implemented on PIC16F873/876 devices.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1998-2013 Microchip Technology Inc.
DS30292D-page 149
PIC16F87X
FIGURE 15-1:
PIC16F87X-20 VOLTAGE-FREQUENCY GRAPH
(COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ONLY)
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
16 MHz
20 MHz
Frequency
FIGURE 15-2:
PIC16LF87X-04 VOLTAGE-FREQUENCY GRAPH
(COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ONLY)
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
4 MHz
10 MHz
Frequency
FMAX = (6.0 MHz/V) (VDDAPPMIN - 2.0 V) + 4 MHz
Note 1: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
Note 2: FMAX has a maximum frequency of 10MHz.
DS30292D-page 150
1998-2013 Microchip Technology Inc.
PIC16F87X
FIGURE 15-3:
PIC16F87X-04VOLTAGE-FREQUENCYGRAPH(ALLTEMPERATURERANGES)
6.0 V
5.5 V
5.0 V
PIC16F87X-04
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
4 MHz
Frequency
FIGURE 15-4:
PIC16F87X-10 VOLTAGE-FREQUENCY GRAPH
(EXTENDED TEMPERATURE RANGE ONLY)
6.0 V
5.5 V
5.0 V
PIC16F87X-10
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
10 MHz
Frequency
1998-2013 Microchip Technology Inc.
DS30292D-page 151
PIC16F87X
15.1 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial)
PIC16F873/874/876/877-20 (Commercial, Industrial)
PIC16LF873/874/876/877-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC16LF873/874/876/877-04
Operating temperature -40°C TA +85°C for industrial
(Commercial, Industrial)
0°C TA +70°C for commercial
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
0°C TA +70°C for commercial
PIC16F873/874/876/877-04
PIC16F873/874/876/877-20
(Commercial, Industrial)
Param Symbol
No.
Characteristic/
Min
Typ† Max Units
Conditions
Device
VDD
Supply Voltage
D001
16LF87X
2.0
—
—
5.5
V
LP, XT, RC osc configuration
(DC to 4 MHz)
D001
16F87X
4.0
4.5
5.5
5.5
5.5
—
V
V
V
V
LP, XT, RC osc configuration
HS osc configuration
BOR enabled, FMAX = 14 MHz(7)
D001A
VBOR
—
D002
D003
VDR
RAM Data Retention
Voltage(1)
1.5
VPOR VDD Start Voltage to
ensure internal Power-on
Reset signal
—
VSS
—
—
V
See section on Power-on Reset for
details
D004
D005
SVDD VDD Rise Rate to ensure 0.05
internal Power-on Reset
signal
—
V/ms See section on Power-on Reset for
details
VBOR Brown-out Reset
3.7
4.0
4.35
V
BODEN bit in configuration word
enabled
Voltage
Legend: Rows with standard voltage device data only are shaded for improved readability.
†
Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance
only, and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading, switching rate, oscillator type, internal code execution pattern and temperature also have an impact
on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
DS30292D-page 152
1998-2013 Microchip Technology Inc.
PIC16F87X
15.1 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial)
PIC16F873/874/876/877-20 (Commercial, Industrial)
PIC16LF873/874/876/877-04 (Commercial, Industrial)
(Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
0°C TA +70°C for commercial
PIC16LF873/874/876/877-04
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
0°C TA +70°C for commercial
PIC16F873/874/876/877-04
PIC16F873/874/876/877-20
(Commercial, Industrial)
Param Symbol
No.
Characteristic/
Min
Typ† Max Units
Conditions
Device
IDD
Supply Current(2,5)
D010
16LF87X
—
—
—
0.6
1.6
20
2.0
4
mA XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V
D010
16F87X
mA RC osc configurations
FOSC = 4 MHz, VDD = 5.5V
D010A
16LF87X
35
A LP osc configuration
FOSC = 32 kHz, VDD = 3.0V,
WDT disabled
D013
16F87X
—
—
7
15
mA HS osc configuration,
FOSC = 20 MHz, VDD = 5.5V
D015
IBOR Brown-out
Reset Current(6)
85
200
A BOR enabled, VDD = 5.0V
Legend: Rows with standard voltage device data only are shaded for improved readability.
†
Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance
only, and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading, switching rate, oscillator type, internal code execution pattern and temperature also have an impact
on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
1998-2013 Microchip Technology Inc.
DS30292D-page 153
PIC16F87X
15.1 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial)
PIC16F873/874/876/877-20 (Commercial, Industrial)
PIC16LF873/874/876/877-04 (Commercial, Industrial)
(Continued)
Standard Operating Conditions (unless otherwise stated)
PIC16LF873/874/876/877-04
Operating temperature -40°C TA +85°C for industrial
(Commercial, Industrial)
0°C TA +70°C for commercial
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
0°C TA +70°C for commercial
PIC16F873/874/876/877-04
PIC16F873/874/876/877-20
(Commercial, Industrial)
Param Symbol
No.
Characteristic/
Min
Typ† Max Units
Conditions
Device
IPD
Power-down Current(3,5)
D020
16LF87X
—
—
—
—
7.5
10.5
0.9
1.5
0.9
1.5
85
30
42
5
A VDD = 3.0V, WDT enabled,
-40C to +85C
D020
D021
D021
D021A
D021A
D023
16F87X
16LF87X
16F87X
16LF87X
16F87X
A VDD = 4.0V, WDT enabled,
-40C to +85C
A VDD = 3.0V, WDT enabled,
0C to +70C
16
5
A VDD = 4.0V, WDT enabled,
-40C to +85C
A VDD = 3.0V, WDT enabled,
-40C to +85C
19
200
A VDD = 4.0V, WDT enabled,
-40C to +85C
IBOR Brown-out
Reset Current(6)
—
A BOR enabled, VDD = 5.0V
Legend: Rows with standard voltage device data only are shaded for improved readability.
†
Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance
only, and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading, switching rate, oscillator type, internal code execution pattern and temperature also have an impact
on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
DS30292D-page 154
1998-2013 Microchip Technology Inc.
PIC16F87X
15.2 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial)
PIC16F873/874/876/877-20 (Commercial, Industrial)
PIC16LF873/874/876/877-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
0°C TA +70°C for commercial
DC CHARACTERISTICS
Operating voltage VDD range as described in DC specification
(Section 15.1)
Param
Sym
No.
Characteristic
Min
Typ† Max Units
Conditions
VIL
Input Low Voltage
I/O ports
with TTL buffer
D030
D030A
D031
D032
D033
Vss
Vss
Vss
VSS
VSS
—
—
—
—
—
—
—
—
0.15VDD
0.8V
0.2VDD
0.2VDD
0.3VDD
V
V
V
V
V
For entire VDD range
4.5V VDD 5.5V
with Schmitt Trigger buffer
MCLR, OSC1 (in RC mode)
OSC1 (in XT, HS and LP)
Ports RC3 and RC4
(Note 1)
D034
D034A
with Schmitt Trigger buffer
with SMBus
Vss
-0.5
0.3VDD
0.6
V
V
For entire VDD range
for VDD = 4.5 to 5.5V
VIH Input High Voltage
I/O ports
—
—
—
D040
D040A
with TTL buffer
2.0
VDD
VDD
V
V
4.5V VDD 5.5V
For entire VDD range
0.25VDD
+ 0.8V
0.8VDD
0.8VDD
0.7VDD
0.9VDD
D041
D042
D042A
D043
with Schmitt Trigger buffer
MCLR
OSC1 (XT, HS and LP)
OSC1 (in RC mode)
Ports RC3 and RC4
—
—
—
—
VDD
VDD
VDD
VDD
V
V
V
V
For entire VDD range
(Note 1)
D044
D044A
D070
with Schmitt Trigger buffer
with SMBus
IPURB PORTB Weak Pull-up Current
0.7VDD
1.4
50
—
—
250
VDD
5.5
400
V
V
For entire VDD range
for VDD = 4.5 to 5.5V
A VDD = 5V, VPIN = VSS,
-40°C TO +85°C
Input Leakage Current(2, 3)
IIL
D060
I/O ports
—
—
1
A Vss VPIN VDD,
Pin at hi-impedance
D061
D063
MCLR, RA4/T0CKI
OSC1
—
—
—
—
5
5
A Vss VPIN VDD
A Vss VPIN VDD, XT, HS
and LP osc configuration
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F87X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
1998-2013 Microchip Technology Inc.
DS30292D-page 155
PIC16F87X
15.2 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial)
PIC16F873/874/876/877-20 (Commercial, Industrial)
PIC16LF873/874/876/877-04 (Commercial, Industrial)
(Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
DC CHARACTERISTICS
0°C TA +70°C for commercial
Operating voltage VDD range as described in DC specification
(Section 15.1)
Param
Sym
No.
Characteristic
Min
Typ† Max Units
Conditions
VOL Output Low Voltage
D080
D083
I/O ports
—
—
—
—
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40C to +85C
IOL = 1.6 mA, VDD = 4.5V,
-40C to +85C
OSC2/CLKOUT (RC osc config)
VOH Output High Voltage
D090
D092
D150*
I/O ports(3)
VDD - 0.7
—
—
—
—
—
V
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40C to +85C
IOH = -1.3 mA, VDD = 4.5V,
-40C to +85C
OSC2/CLKOUT (RC osc config) VDD - 0.7
VOD Open-Drain High Voltage
Capacitive Loading Specs on
Output Pins
—
—
8.5
RA4 pin
D100
COSC2 OSC2 pin
—
15
pF In XT, HS and LP modes when
external clock is used to drive
OSC1
D101
D102
CIO All I/O pins and OSC2 (RC mode)
CB
—
—
—
—
50
400
pF
pF
SCL, SDA (I2C mode)
Data EEPROM Memory
Endurance
D120
D121
ED
100K
VMIN
—
—
—
5.5
E/W 25C at 5V
V
VDRW VDD for read/write
Using EECON to read/write
VMIN = min. operating voltage
D122
TDEW Erase/write cycle time
—
4
8
ms
Program FLASH Memory
D130
D131
D132A
EP
VPR VDD for read
VDD for erase/write
Endurance
1000
VMIN
VMIN
—
—
—
—
5.5
5.5
E/W 25C at 5V
V
V
VMIN = min operating voltage
Using EECON to read/write,
VMIN = min. operating voltage
D133
TPEW Erase/Write cycle time
—
4
8
ms
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F87X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS30292D-page 156
1998-2013 Microchip Technology Inc.
PIC16F87X
15.3 DC Characteristics: PIC16F873/874/876/877-04 (Extended)
PIC16F873/874/876/877-10 (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
PIC16F873/874/876/877-04
PIC16F873/874/876/877-20
(Extended)
Param Symbol
No.
Characteristic/
Min
Typ† Max Units
Conditions
Device
VDD
Supply Voltage
D001
4.0
4.5
—
5.5
5.5
5.5
—
V
V
V
V
LP, XT, RC osc configuration
HS osc configuration
BOR enabled, FMAX = 10 MHz(7)
D001A
D001A
D002
VBOR
—
VDR
RAM Data Retention
Voltage(1)
1.5
D003
D004
VPOR VDD Start Voltage to
ensure internal Power-on
Reset signal
—
VSS
—
—
V
See section on Power-on Reset for
details
SVDD VDD Rise Rate to ensure 0.05
internal Power-on Reset
signal
—
V/ms See section on Power-on Reset for
details
D005
†
VBOR Brown-out Reset
3.7
4.0
4.35
V
BODEN bit in configuration word
enabled
Voltage
Data is “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance
only, and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading, switching rate, oscillator type, internal code execution pattern and temperature also have an impact
on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from
characterization and is for design guidance only. This is not tested.
6: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
1998-2013 Microchip Technology Inc.
DS30292D-page 157
PIC16F87X
15.3 DC Characteristics: PIC16F873/874/876/877-04 (Extended)
PIC16F873/874/876/877-10 (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
PIC16F873/874/876/877-04
PIC16F873/874/876/877-20
(Extended)
Param Symbol
No.
Characteristic/
Min
Typ† Max Units
Conditions
Device
IDD
Supply Current(2,5)
D010
—
—
—
1.6
7
4
mA RC osc configurations
FOSC = 4 MHz, VDD = 5.5V
D013
15
mA HS osc configuration,
FOSC = 10 MHz, VDD = 5.5V
D015
IBOR Brown-out
85
200
A BOR enabled, VDD = 5.0V
Reset Current(6)
IPD
Power-down Current(3,5)
D020A
D021B
D023
10.5
1.5
85
60
30
A VDD = 4.0V, WDT enabled
A VDD = 4.0V, WDT disabled
A BOR enabled, VDD = 5.0V
IBOR Brown-out
Reset Current(6)
—
200
†
Data is “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance
only, and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading, switching rate, oscillator type, internal code execution pattern and temperature also have an impact
on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from
characterization and is for design guidance only. This is not tested.
6: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
DS30292D-page 158
1998-2013 Microchip Technology Inc.
PIC16F87X
15.4 DC Characteristics: PIC16F873/874/876/877-04 (Extended)
PIC16F873/874/876/877-10 (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Operating voltage VDD range as described in DC specification
(Section 15.1)
DC CHARACTERISTICS
Param
Sym
No.
Characteristic
Min
Typ† Max Units
Conditions
VIL Input Low Voltage
I/O ports
with TTL buffer
D030
D030A
D031
D032
D033
Vss
Vss
Vss
VSS
VSS
—
—
—
—
—
0.15VDD
0.8V
0.2VDD
0.2VDD
0.3VDD
V
V
V
V
V
For entire VDD range
4.5V VDD 5.5V
with Schmitt Trigger buffer
MCLR, OSC1 (in RC mode)
OSC1 (in XT, HS and LP)
Ports RC3 and RC4
(Note 1)
D034
D034A
with Schmitt Trigger buffer
with SMBus
Vss
-0.5
—
—
0.3VDD
0.6
V
V
For entire VDD range
for VDD = 4.5 to 5.5V
VIH Input High Voltage
I/O ports
—
—
—
D040
D040A
with TTL buffer
2.0
VDD
VDD
V
V
4.5V VDD 5.5V
For entire VDD range
0.25VDD
+ 0.8V
0.8VDD
0.8VDD
0.7VDD
0.9VDD
D041
D042
D042A
D043
with Schmitt Trigger buffer
MCLR
—
—
—
—
VDD
VDD
VDD
VDD
V
V
V
V
For entire VDD range
OSC1 (XT, HS and LP)
OSC1 (in RC mode)
Ports RC3 and RC4
with Schmitt Trigger buffer
with SMBus
(Note 1)
D044
D044A
0.7VDD
1.4
—
—
VDD
5.5
V
V
For entire VDD range
for VDD = 4.5 to 5.5V
D070A IPURB PORTB Weak Pull-up Current
50
250
400
A VDD = 5V, VPIN = VSS,
Input Leakage Current(2, 3)
IIL
D060
I/O ports
-
-
1
A Vss VPIN VDD,
Pin at hi-impedance
D061
D063
MCLR, RA4/T0CKI
OSC1
-
-
-
-
5
5
A Vss VPIN VDD
A Vss VPIN VDD, XT, HS
and LP osc configuration
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F87X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
1998-2013 Microchip Technology Inc.
DS30292D-page 159
PIC16F87X
15.4 DC Characteristics: PIC16F873/874/876/877-04 (Extended)
PIC16F873/874/876/877-10 (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Operating voltage VDD range as described in DC specification
(Section 15.1)
DC CHARACTERISTICS
Param
Sym
No.
Characteristic
Min
Typ† Max Units
Conditions
VOL Output Low Voltage
I/O ports
OSC2/CLKOUT (RC osc config)
VOH Output High Voltage
D080A
D083A
—
—
—
—
0.6
0.6
V
V
IOL = 7.0 mA, VDD = 4.5V
IOL = 1.2 mA, VDD = 4.5V
D090A
D092A
D150*
I/O ports(3)
VDD - 0.7
—
—
—
—
—
8.5
V
V
V
IOH = -2.5 mA, VDD = 4.5V
IOH = -1.0 mA, VDD = 4.5V
RA4 pin
OSC2/CLKOUT (RC osc config) VDD - 0.7
VOD Open Drain High Voltage
Capacitive Loading Specs on Output Pins
—
D100
COSC2 OSC2 pin
—
—
15
pF In XT, HS and LP modes when
external clock is used to drive
OSC1
D101
D102
CIO All I/O pins and OSC2 (RC mode)
CB SCL, SDA (I2C mode)
Data EEPROM Memory
ED Endurance
—
—
—
—
50
400
pF
pF
D120
D121
100K
VMIN
—
—
—
5.5
E/W 25C at 5V
V
VDRW VDD for read/write
Using EECON to read/write
VMIN = min. operating voltage
D122
TDEW Erase/write cycle time
Program FLASH Memory
EP Endurance
—
4
8
ms
D130
D131
D132A
1000
VMIN
VMIN
—
—
—
—
5.5
5.5
E/W 25C at 5V
V
V
VPR VDD for read
VMIN = min operating voltage
Using EECON to read/write,
VMIN = min. operating voltage
VDD for erase/write
D133
TPEW Erase/Write cycle time
—
4
8
ms
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F87X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
DS30292D-page 160
1998-2013 Microchip Technology Inc.
PIC16F87X
15.5 Timing Parameter Symbology
The timing parameter symbols have been created fol-
lowing one of the following formats:
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
T
Time
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
ST
DAT
STA
Hold
SU
Setup
DATA input hold
START condition
STO
STOP condition
FIGURE 15-5:
LOAD CONDITIONS
Load Condition 1
VDD/2
Load Condition 2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464
CL = 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports,
15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on PIC16F873/876 devices.
1998-2013 Microchip Technology Inc.
DS30292D-page 161
PIC16F87X
FIGURE 15-6:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
4
Q1
OSC1
1
3
4
3
2
CLKOUT
TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
Sym
Characteristic
Min Typ†
Max
Units
Conditions
No.
FOSC External CLKIN Frequency
DC
DC
DC
DC
DC
DC
0.1
4
—
—
—
—
—
—
—
—
4
4
MHz XT and RC osc mode
MHz HS osc mode (-04)
MHz HS osc mode (-10)
MHz HS osc mode (-20)
kHz LP osc mode
(Note 1)
10
20
200
4
Oscillator Frequency
(Note 1)
MHz RC osc mode
4
MHz XT osc mode
10
MHz HS osc mode (-10)
4
5
—
—
20
200
MHz HS osc mode (-20)
kHz LP osc mode
1
TOSC External CLKIN Period
250
250
100
50
—
—
—
—
—
—
—
—
—
—
—
TCY
—
—
ns XT and RC osc mode
ns HS osc mode (-04)
ns HS osc mode (-10)
ns HS osc mode (-20)
s LP osc mode
(Note 1)
—
—
5
—
Oscillator Period
(Note 1)
250
250
250
100
50
—
ns RC osc mode
10,000
—
ns XT osc mode
ns HS osc mode (-04)
ns HS osc mode (-10)
ns HS osc mode (-20)
s LP osc mode
250
250
—
5
2
3
TCY Instruction Cycle Time
200
DC
ns TCY = 4/FOSC
(Note 1)
TosL, External Clock in (OSC1) High or 100
TosH Low Time
—
—
—
—
—
—
—
—
—
25
50
15
ns XT oscillator
s LP oscillator
ns HS oscillator
ns XT oscillator
ns LP oscillator
ns HS oscillator
2.5
15
4
†
TosR, External Clock in (OSC1) Rise or
TosF Fall Time
—
—
—
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions, with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at "min." values with an
external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "max." cycle time
limit is "DC" (no clock) for all devices.
DS30292D-page 162
1998-2013 Microchip Technology Inc.
PIC16F87X
FIGURE 15-7:
CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
14
12
16
18
19
I/O Pin
(Input)
15
17
I/O Pin
(Output)
New Value
Old Value
20, 21
Note: Refer to Figure 15-5 for load conditions.
TABLE 15-2: CLKOUT AND I/O TIMING REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ†
Max
Units Conditions
10*
11*
TosH2ckL OSC1 to CLKOUT
—
—
75
75
200
200
ns (Note 1)
ns (Note 1)
TosH2ck OSC1 to CLKOUT
H
12*
13*
14*
15*
16*
17*
TckR
TckF
CLKOUT rise time
CLKOUT fall time
—
—
—
35
35
—
100
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns
100
TckL2ioV CLKOUT to Port out valid
TioV2ckH Port in valid before CLKOUT
TckH2ioI Port in hold after CLKOUT
0.5TCY + 20
TOSC + 200
—
—
—
0
—
TosH2ioV OSC1 (Q1 cycle) to
—
100
255
Port out valid
18*
TosH2ioI OSC1 (Q2 cycle) to
Port input invalid (I/O in
hold time)
Standard (F)
Extended (LF)
100
200
—
—
—
—
ns
ns
19*
20*
TioV2osH Port input valid to OSC1(I/O in setup time)
0
—
—
10
—
10
—
—
—
—
40
ns
ns
ns
ns
ns
ns
ns
TioR
Port output rise time
Port output fall time
INT pin high or low time
Standard (F)
Extended (LF)
Standard (F)
Extended (LF)
—
145
40
21*
TioF
—
—
145
—
22††*
23††*
Tinp
Trbp
TCY
TCY
RB7:RB4 change INT high or low time
—
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
1998-2013 Microchip Technology Inc.
DS30292D-page 163
PIC16F87X
FIGURE 15-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note: Refer to Figure 15-5 for load conditions.
FIGURE 15-9:
BROWN-OUT RESET TIMING
VBOR
VDD
35
TABLE 15-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
Symbol
Characteristic
Min
Typ†
Max
Units
Conditions
No.
30
TmcL MCLR Pulse Width (low)
2
7
—
—
s
VDD = 5V, -40°C to +85°C
31*
Twdt
Tost
Watchdog Timer Time-out Period
(No Prescaler)
18
33
ms VDD = 5V, -40°C to +85°C
32
Oscillation Start-up Timer Period
—
1024 TOSC
72
—
—
TOSC = OSC1 period
33*
Tpwrt Power-up Timer Period
28
132
ms VDD = 5V, -40°C to +85°C
34
TIOZ
I/O Hi-impedance from MCLR Low
—
—
2.1
s
or Watchdog Timer Reset
35
TBOR
Brown-out Reset pulse width
100
—
—
s
VDD VBOR (D005)
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
DS30292D-page 164
1998-2013 Microchip Technology Inc.
PIC16F87X
FIGURE 15-10:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RC0/T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 15-5 for load conditions.
TABLE 15-4: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Symbol
Characteristic
T0CKI High Pulse Width
Min
Typ† Max Units
Conditions
40*
Tt0H
No Prescaler
With Prescaler
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
ns Must also meet
parameter 42
10
ns
41*
42*
Tt0L
Tt0P
T0CKI Low Pulse Width
T0CKI Period
0.5TCY + 20
ns Must also meet
parameter 42
10
ns
ns
TCY + 40
Greater of:
20 or TCY + 40
ns N = prescale value
(2, 4,..., 256)
N
45*
46*
47*
Tt1H
Tt1L
Tt1P
T1CKI High Time Synchronous, Prescaler = 1
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns Must also meet
parameter 47
Synchronous,
Prescaler = 2,4,8
Standard(F)
Extended(LF)
Standard(F)
Extended(LF)
15
ns
ns
ns
ns
25
Asynchronous
30
50
T1CKI Low Time Synchronous, Prescaler = 1
0.5TCY + 20
ns Must also meet
parameter 47
Synchronous,
Prescaler = 2,4,8
Standard(F)
Extended(LF)
Standard(F)
Extended(LF)
Standard(F)
15
ns
ns
ns
ns
25
Asynchronous
30
50
T1CKI input
period
Synchronous
Greater of:
30 OR TCY + 40
ns N = prescale value
(1, 2, 4, 8)
N
Extended(LF)
Greater of:
50 OR TCY + 40
N = prescale value
(1, 2, 4, 8)
N
60
Asynchronous
Standard(F)
—
—
—
—
—
ns
ns
Extended(LF)
100
DC
Ft1
Timer1 oscillator input frequency range
200 kHz
(oscillator enabled by setting bit T1OSCEN)
48
*
TCKEZtmr1 Delay from external clock edge to timer increment
These parameters are characterized but not tested.
2TOSC
—
7TOSC
—
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
1998-2013 Microchip Technology Inc.
DS30292D-page 165
PIC16F87X
FIGURE 15-11:
CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
RC1/T1OSI/CCP2
and RC2/CCP1
(Capture Mode)
50
51
52
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
53
Note: Refer to Figure 15-5 for load conditions.
54
TABLE 15-5: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Param
No.
Sym
Characteristic
Min
Typ† Max Units
Conditions
50*
TccL CCP1 and CCP2 No Prescaler
input low time
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Standard(F)
10
With Prescaler
Extended(LF)
20
0.5TCY + 20
10
51*
TccH CCP1 and CCP2 No Prescaler
input high time
Standard(F)
With Prescaler
Extended(LF)
20
52*
53*
TccP CCP1 and CCP2 input period
3TCY + 40
N
ns N = prescale
value (1, 4 or 16)
TccR CCP1 and CCP2 output rise time Standard(F)
Extended(LF)
—
—
—
—
10
25
10
25
25
50
25
45
ns
ns
ns
ns
54*
*
TccF CCP1 and CCP2 output fall time
Standard(F)
Extended(LF)
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
DS30292D-page 166
1998-2013 Microchip Technology Inc.
PIC16F87X
FIGURE 15-12:
PARALLEL SLAVE PORT TIMING (PIC16F874/877 ONLY)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 15-5 for load conditions.
TABLE 15-6: PARALLEL SLAVE PORT REQUIREMENTS (PIC16F874/877 ONLY)
Parameter
Symbol
Characteristic
Min Typ† Max Units Conditions
No.
62
TdtV2wrH Data in valid before WR or CS (setup time)
20
25
—
—
—
—
ns
ns Extended
Range Only
63*
64
TwrH2dtI WR or CS to data–in invalid (hold time) Standard(F)
Extended(LF)
20
35
—
—
—
—
ns
ns
TrdL2dtV RD and CS to data–out valid
—
—
—
—
80
90
ns
ns Extended
Range Only
65
TrdH2dtI RD or CS to data–out invalid
10
—
30
ns
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
1998-2013 Microchip Technology Inc.
DS30292D-page 167
PIC16F87X
FIGURE 15-13:
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
BIT6 - - - - - -1
MSb
LSb
SDO
SDI
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note: Refer to Figure 15-5 for load conditions.
FIGURE 15-14:
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
BIT6 - - - - - -1
BIT6 - - - -1
SDO
SDI
75, 76
MSb IN
74
LSb IN
Note: Refer to Figure 15-5 for load conditions.
DS30292D-page 168
1998-2013 Microchip Technology Inc.
PIC16F87X
FIGURE 15-15:
SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
BIT6 - - - - - -1
LSb
SDO
SDI
77
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note: Refer to Figure 15-5 for load conditions.
FIGURE 15-16:
SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
BIT6 - - - - - -1
BIT6 - - - -1
LSb
SDO
SDI
75, 76
77
MSb IN
74
LSb IN
Note: Refer to Figure 15-5 for load conditions.
1998-2013 Microchip Technology Inc.
DS30292D-page 169
PIC16F87X
TABLE 15-7: SPI MODE REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ†
Max Units Conditions
70*
TssL2scH, SS to SCK or SCK input
Tcy
—
—
ns
TssL2scL
71*
72*
73*
TscH
TscL
SCK input high time (Slave mode)
SCK input low time (Slave mode)
TCY + 20
TCY + 20
100
—
—
—
—
—
—
ns
ns
ns
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
74*
75*
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
—
—
ns
TdoR
SDO data output rise time
Standard(F)
—
—
10
25
25
50
ns
ns
Extended(LF)
76*
77*
78*
TdoF
SDO data output fall time
—
10
—
25
50
ns
ns
TssH2doZ SS to SDO output hi-impedance
10
TscR
SCK output rise time (Master mode) Standard(F)
Extended(LF)
—
—
10
25
25
50
ns
ns
79*
80*
TscF
SCK output fall time (Master mode)
—
10
25
ns
ns
TscH2doV, SDO data output valid after SCK
TscL2doV edge
Standard(F)
Extended(LF)
—
—
—
—
50
145
81*
TdoV2scH, SDO data output setup to SCK edge
TdoV2scL
Tcy
—
—
ns
82*
83*
TssL2doV SDO data output valid after SS edge
—
—
—
50
—
ns
ns
TscH2ssH, SS after SCK edge
1.5TCY + 40
TscL2ssH
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
FIGURE 15-17:
I2C BUS START/STOP BITS TIMING
SCL
93
91
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 15-5 for load conditions.
DS30292D-page 170
1998-2013 Microchip Technology Inc.
PIC16F87X
TABLE 15-8: I2C BUS START/STOP BITS REQUIREMENTS
Parameter
Symbol
Characteristic
Min Typ Max Units
Conditions
No.
90
Tsu:sta
START condition
Setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
Only relevant for Repeated
START condition
91
92
93
Thd:sta START condition
Hold time
4000
600
After this period, the first clock
pulse is generated
Tsu:sto
STOP condition
Setup time
4700
600
Thd:sto STOP condition
Hold time
4000
600
FIGURE 15-18:
I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 15-5 for load conditions.
1998-2013 Microchip Technology Inc.
DS30292D-page 171
PIC16F87X
TABLE 15-9: I2C BUS DATA REQUIREMENTS
Param
No.
Sym
Characteristic
100 kHz mode
Min
4.0
0.6
Max
—
Units
s
Conditions
100
Thigh
Clock high time
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
—
s
Device must operate at a
minimum of 10 MHz
SSP Module
0.5TCY
4.7
—
—
101
Tlow
Clock low time
100 kHz mode
s
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
Device must operate at a
minimum of 10 MHz
SSP Module
0.5TCY
—
—
102
103
Tr
Tf
SDA and SCL rise
time
100 kHz mode
400 kHz mode
1000
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
SDA and SCL fall time 100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
90
91
Tsu:sta
START condition
setup time
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
s
s
s
s
ns
s
ns
ns
s
s
ns
ns
s
s
Only relevant for Repeated
START condition
Thd:sta START condition hold 100 kHz mode
—
After this period, the first clock
pulse is generated
time
400 kHz mode
—
106
107
92
Thd:dat Data input hold time
100 kHz mode
400 kHz mode
—
0
0.9
—
Tsu:dat Data input setup time 100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
(Note 2)
—
Tsu:sto STOP condition setup 100 kHz mode
—
time
400 kHz mode
—
109
110
Taa
Output valid from
clock
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
3500
—
(Note 1)
—
Tbuf
Bus free time
4.7
1.3
—
Time the bus must be free
before a new transmission
can start
—
Cb
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2
2
2: A fast mode (400 kHz) I C bus device can be used in a standard mode (100 kHz) I C bus system, but the requirement that
Tsu:dat 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
2
TR max.+ Tsu:dat = 1000 + 250 = 1250 ns (according to the standard mode I C bus specification) before the SCL line is
released.
DS30292D-page 172
1998-2013 Microchip Technology Inc.
PIC16F87X
FIGURE 15-19:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
Pin
121
121
RC7/RX/DT
Pin
120
122
Note: Refer to Figure 15-5 for load conditions.
TABLE 15-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max Units Conditions
120
TckH2dtV SYNC XMIT (MASTER &
SLAVE)
Standard(F)
—
—
—
—
—
—
—
—
—
—
—
—
80
100
45
ns
ns
ns
ns
ns
ns
Clock high to data out valid
Extended(LF)
121
122
†
Tckrf
Tdtrf
Clock out rise time and fall time Standard(F)
(Master mode)
Extended(LF)
50
Data out rise time and fall time Standard(F)
Extended(LF)
45
50
Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
FIGURE 15-20:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
125
pin
RC7/RX/DT
pin
126
Note: Refer to Figure 15-5 for load conditions.
TABLE 15-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
Sym
Characteristic
Min
Typ†
Max
Units Conditions
No.
125
TdtV2ckL SYNC RCV (MASTER & SLAVE)
Data setup before CK (DT setup
time)
15
15
—
—
—
—
ns
ns
126
TckL2dtl Data hold after CK (DT hold time)
†
Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
1998-2013 Microchip Technology Inc.
DS30292D-page 173
PIC16F87X
TABLE 15-12: PIC16F87X-04 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC16F87X-10 (EXTENDED)
PIC16F87X-20 (COMMERCIAL, INDUSTRIAL)
PIC16LF87X-04 (COMMERCIAL, INDUSTRIAL)
Param
No.
Sym
NR
Characteristic
Resolution
Integral linearity error
Min
—
Typ†
—
Max
10-bits
< ± 1
< ± 1
< ± 2
< ± 1
Units
Conditions
A01
bit
VREF = VDD = 5.12V,
VSS VAIN VREF
A03
A04
A06
A07
EIL
—
—
LSb VREF = VDD = 5.12V,
VSS VAIN VREF
EDL Differential linearity error
EOFF Offset error
—
—
LSb VREF = VDD = 5.12V,
VSS VAIN VREF
—
—
LSb VREF = VDD = 5.12V,
VSS VAIN VREF
EGN Gain error
—
—
LSb VREF = VDD = 5.12V,
VSS VAIN VREF
(3)
A10
A20
—
Monotonicity
—
guaranteed
—
—
—
V
VSS VAIN VREF
VREF Reference voltage (VREF+ - VREF-)
2.0
VDD + 0.3
Absolute minimum electrical
spec. To ensure 10-bit
accuracy.
A21 VREF+ Reference voltage High
AVDD - 2.5V
AVSS - 0.3V
VSS - 0.3 V
—
AVDD + 0.3V
VREF+ - 2.0V
VREF + 0.3 V
10.0
V
V
A22
A25
A30
VREF- Reference voltage low
VAIN Analog input voltage
—
—
V
ZAIN Recommended impedance of
analog voltage source
k
A40
A50
IAD
A/D conversion
current (VDD)
Standard
Extended
—
—
10
220
90
—
—
A Average current consumption
when A/D is on (Note 1)
A
IREF VREF input current (Note 2)
—
1000
A During VAIN acquisition.
Based on differential of VHOLD
to VAIN to charge CHOLD, see
Section 11.1.
—
—
10
A During A/D Conversion cycle
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes.
DS30292D-page 174
1998-2013 Microchip Technology Inc.
PIC16F87X
FIGURE 15-21:
A/D CONVERSION TIMING
BSF ADCON0, GO
1 TCY
(1)
(TOSC/2)
131
130
Q4
132
A/D CLK
9
8
7
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
TABLE 15-13: A/D CONVERSION REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
130
TAD A/D clock period
Standard(F)
Extended(LF)
Standard(F)
Extended(LF)
1.6
3.0
2.0
3.0
—
—
—
—
s TOSC based, VREF 3.0V
s TOSC based, VREF 2.0V
s A/D RC mode
s A/D RC mode
TAD
4.0
6.0
—
6.0
9.0
12
131
132
TCNV Conversion time (not including S/H time)
(Note 1)
TACQ Acquisition time
(Note 2)
40
—
—
—
s
10*
s The minimum time is the
amplifier settling time. This may
be used if the "new" input volt-
age has not changed by more
than 1 LSb (i.e., 20.0 mV @
5.12V) from the last sampled
voltage (as stated on CHOLD).
134
TGO Q4 to A/D clock start
—
TOSC/2 §
—
—
If the A/D clock source is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
§
This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.1 for minimum conditions.
1998-2013 Microchip Technology Inc.
DS30292D-page 175
PIC16F87X
NOTES:
DS30292D-page 176
1998-2013 Microchip Technology Inc.
PIC16F87X
16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented is outside specified operating range (i.e., outside specified VDD range).
This is for information only and devices are ensured to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period
of time and matrix samples. 'Typical' represents the mean of the distribution at 25C. 'max' or 'min' represents
(mean + 3) or (mean - 3) respectively, where is standard deviation, over the whole temperature range.
FIGURE 16-1:
TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
7
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
6
5
4
3
2
1
0
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
4
6
8
10
12
F OSC (M H z )
14
16
18
20
FIGURE 16-2:
MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)
8
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
7
6
5
4
3
2
1
0
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
4
6
8
10
12
(M Hz )
14
16
18
20
F
O SC
1998-2013 Microchip Technology Inc.
DS30292D-page 177
PIC16F87X
FIGURE 16-3:
TYPICAL IDD vs. FOSC OVER VDD (XT MODE)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
FIGURE 16-4:
MAXIMUM IDD vs. FOSC OVER VDD (LP MODE)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
DS30292D-page 178
© 1998-2013 Microchip Technology Inc.
PIC16F87X
FIGURE 16-5:
TYPICAL IDD vs. FOSC OVER VDD (LP MODE)
90
80
70
60
50
40
30
20
10
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0
20
30
40
50
60
70
80
90
100
OSC
F
(kHz)
FIGURE 16-6:
MAXIMUM IDD vs. FOSC OVER VDD (XT MODE)
120
110
100
90
5.5V
5.0V
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
80
4.5V
70
4.0V
60
3.5V
3.0V
50
40
2.5V
2.0V
30
20
10
0
20
30
40
50
60
70
80
90
100
OSC
F
(kHz)
1998-2013 Microchip Technology Inc.
DS30292D-page 179
PIC16F87X
FIGURE 16-7:
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 20 pF, 25C)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
3.3k
5.1k
10k
100k
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-8:
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 100 pF, 25C)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
3.3k
5.1k
10k
100k
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS30292D-page 180
© 1998-2013 Microchip Technology Inc.
PIC16F87X
FIGURE 16-9:
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 300 pF, 25C)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
3.3k
5.1k
10k
100k
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-10:
IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
100.00
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
Max (125C)
Max (85C)
10.00
1.00
0.10
Typ (25C)
0.01
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
1998-2013 Microchip Technology Inc.
DS30292D-page 181
PIC16F87X
FIGURE 16-11:
IBOR vs. VDD OVER TEMPERATURE
1.2
Note: Device current in RESET
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
depends on oscillator mode,
frequency and circuit.
1.0
0.8
0.6
0.4
0.2
0.0
Max Reset
Indeterminate
State
Typ Reset (25C)
Device in Sleep
Device in Reset
Max Sleep
Typ Sleep (25C)
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-12:
TYPICAL AND MAXIMUMITMR1 vs. VDD OVER TEMPERATURE
(-10C TO 70C, TIMER1 WITH OSCILLATOR, XTAL=32 kHZ, C1 AND C2=50 pF)
90
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
80
70
60
50
40
30
20
10
0
Max
Typ (25C)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS30292D-page 182
© 1998-2013 Microchip Technology Inc.
PIC16F87X
FIGURE 16-13:
TYPICAL AND MAXIMUM IWDT vs. VDD OVER TEMPERATURE
14
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
12
10
8
Max (85C)
Typ (25C)
6
4
2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-14:
TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40C TO 125C)
60
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
50
40
30
20
10
Max (125C)
Typ (25C)
Min (-40C)
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
(V)
DD
1998-2013 Microchip Technology Inc.
DS30292D-page 183
PIC16F87X
FIGURE 16-15:
AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40C TO 125C)
50
45
40
35
30
25
20
15
10
5
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
125C
85C
25C
-40C
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-16:
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD=5V, -40C TO 125C)
5.0
4.5
4.0
3.5
3.0
Max (-40C)
Typ (25C)
Min (125C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
2.5
2.0
0
5
10
15
20
25
IOH (-mA)
DS30292D-page 184
© 1998-2013 Microchip Technology Inc.
PIC16F87X
FIGURE 16-17:
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD=3V, -40C TO 125C)
3.0
2.5
2.0
1.5
1.0
0.5
Max (-40C)
Typ (25C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Min (125C)
0.0
0
5
10
15
20
25
IOH (-mA)
FIGURE 16-18:
TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD=5V, -40C TO 125C)
2.0
1.8
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Max (125C)
Typ (25C)
Min (-40C)
0
5
10
15
20
25
IOL (-mA)
1998-2013 Microchip Technology Inc.
DS30292D-page 185
PIC16F87X
FIGURE 16-19:
TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD=3V, -40C TO 125C)
3.0
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
2.5
2.0
1.5
1.0
0.5
0.0
Max (125C)
Typ (25C)
Min (-40C)
0
5
10
15
20
25
IOL (-mA)
FIGURE 16-20:
MINIMUM AND MAXIMUM VIN vs. VDD, (TTL INPUT, -40C TO 125C)
1.8
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Max (-40C)
Min (125C)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS30292D-page 186
© 1998-2013 Microchip Technology Inc.
PIC16F87X
FIGURE 16-21:
MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO 125C)
4.5
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Max High (125C)
Min High (-40C)
Max Low (125C)
Min Low (-40C)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-22:
MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40C TO 125C)
3.5
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Max High (125C)
Min High (-40C)
Max Low (125C)
Min Low (25C)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
1998-2013 Microchip Technology Inc.
DS30292D-page 187
PIC16F87X
NOTES:
DS30292D-page 188
© 1998-2013 Microchip Technology Inc.
PIC16F87X
17.0 PACKAGING INFORMATION
17.1 Package Marking Information
28-Lead PDIP (Skinny DIP)
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
PIC16F876-20/SP
0117HAT
YYWWNNN
28-Lead SOIC
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
PIC16F876-04/SO
YYWWNNN
0110SAA
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
)
3
e
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
1998-2013 Microchip Technology Inc.
DS30292D-page 189
PIC16F87X
Package Marking Information (Cont’d)
40-Lead PDIP
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
PIC16F877-04/P
0112SAA
YYWWNNN
44-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC16F877
-04/PT
0111HAT
44-Lead MQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC16F877
-20/PQ
0104SAT
44-Lead PLCC
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
PIC16F877
-20/L
YYWWNNN
0103SAT
DS30292D-page 190
1998-2013 Microchip Technology Inc.
PIC16F87X
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
D
2
n
1
E
A2
L
A
c
B1
A1
eB
B
p
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.100
.150
.130
2.54
3.81
3.30
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A
A2
A1
E
.140
.160
3.56
4.06
.125
.015
.300
.275
1.345
.125
.008
.040
.016
.320
.135
3.18
0.38
7.62
6.99
34.16
3.18
0.20
1.02
3.43
.310
.285
1.365
.130
.012
.053
.019
.350
10
.325
.295
1.385
.135
.015
.065
.022
.430
15
7.87
7.24
8.26
7.49
35.18
3.43
0.38
1.65
0.56
10.92
15
E1
D
34.67
3.30
Tip to Seating Plane
Lead Thickness
L
c
0.29
Upper Lead Width
B1
B
1.33
Lower Lead Width
0.41
8.13
5
0.48
8.89
10
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
5
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
1998-2013 Microchip Technology Inc.
DS30292D-page 191
PIC16F87X
28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
p
D
B
2
n
1
h
45
c
A2
A
L
A1
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
28
28
.050
.099
.091
.008
.407
.295
.704
.020
.033
4
1.27
2.50
2.31
0.20
10.34
7.49
17.87
0.50
0.84
4
Overall Height
A
.093
.104
2.36
2.64
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.288
.695
.010
.016
0
.094
.012
.420
.299
.712
.029
.050
8
2.24
0.10
10.01
7.32
17.65
0.25
0.41
0
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
Foot Angle Top
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.013
.020
15
0.23
0.36
0
0.28
0.42
12
0.33
0.51
15
B
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
DS30292D-page 192
1998-2013 Microchip Technology Inc.
PIC16F87X
40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
D
2
n
1
E
A2
A
L
c
B1
B
A1
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
40
MAX
n
p
Number of Pins
Pitch
40
.100
.175
.150
2.54
Top to Seating Plane
A
.160
.190
.160
4.06
3.56
4.45
3.81
4.83
4.06
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.140
.015
.595
.530
2.045
.120
.008
.030
.014
.620
5
0.38
15.11
13.46
51.94
3.05
0.20
0.76
0.36
15.75
5
.600
.545
2.058
.130
.012
.050
.018
.650
10
.625
.560
2.065
.135
.015
.070
.022
.680
15
15.24
13.84
52.26
3.30
0.29
1.27
0.46
16.51
10
15.88
14.22
52.45
3.43
0.38
1.78
0.56
17.27
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
§
eB
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
5
10
15
5
10
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
1998-2013 Microchip Technology Inc.
DS30292D-page 193
PIC16F87X
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
#leads=n1
p
D1
D
2
1
B
n
CH x 45
A
c
A1
A2
L
(F)
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Pins
Pitch
44
.031
11
0.80
11
Pins per Side
Overall Height
n1
A
.039
.037
.002
.018
.043
.039
.004
.024
.039
3.5
.047
1.00
0.95
1.10
1.00
0.10
0.60
1.20
Molded Package Thickness
Standoff
A2
A1
L
(F)
.041
.006
.030
1.05
0.15
0.75
§
0.05
0.45
1.00
0
Foot Length
Footprint (Reference)
Foot Angle
0
.463
.463
.390
.390
.004
.012
.025
5
7
.482
.482
.398
.398
.008
.017
.045
15
3.5
12.00
12.00
10.00
10.00
0.15
0.38
0.89
10
7
12.25
12.25
10.10
10.10
0.20
0.44
1.14
15
Overall Width
E
D
.472
.472
.394
.394
.006
.015
.035
10
11.75
11.75
9.90
9.90
0.09
0.30
0.64
5
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
CH
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
DS30292D-page 194
1998-2013 Microchip Technology Inc.
PIC16F87X
44-Lead Plastic Metric Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.15 mm Lead Form (MQFP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
#leads=n1
p
D1
D
2
1
B
c
n
CH x 45
A1
A
(F)
L
A2
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Pins
Pitch
44
.031
11
0.80
11
Pins per Side
Overall Height
n1
A
.079
.077
.002
.029
.086
.080
.006
.035
.063
3.5
.093
2.00
1.95
2.18
2.03
0.15
0.88
1.60
3.5
2.35
Molded Package Thickness
Standoff
A2
A1
L
(F)
.083
.010
.041
2.10
0.25
1.03
§
0.05
0.73
Foot Length
Footprint (Reference)
Foot Angle
0
.510
.510
.390
.390
.005
.012
.025
5
7
.530
.530
.398
.398
.009
.018
.045
15
0
12.95
12.95
9.90
9.90
0.13
0.30
0.64
5
7
13.45
13.45
10.10
10.10
0.23
0.45
1.14
15
Overall Width
E
D
.520
.520
.394
.394
.007
.015
.035
10
13.20
13.20
10.00
10.00
0.18
0.38
0.89
10
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
CH
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-022
Drawing No. C04-071
1998-2013 Microchip Technology Inc.
DS30292D-page 195
PIC16F87X
44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
#leads=n1
D
D1
n 1 2
CH2 x 45
CH1 x 45
A3
A2
A
35
B1
B
c
A1
p
E2
D2
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Pins
Pitch
44
.050
11
1.27
11
Pins per Side
Overall Height
n1
A
.165
.145
.020
.024
.040
.000
.685
.685
.650
.650
.590
.590
.008
.026
.013
0
.173
.153
.028
.029
.045
.005
.690
.690
.653
.653
.620
.620
.011
.029
.020
5
.180
4.19
3.68
0.51
0.61
1.02
0.00
17.40
17.40
16.51
16.51
14.99
14.99
0.20
0.66
0.33
0
4.39
3.87
0.71
0.74
1.14
0.13
17.53
17.53
16.59
16.59
15.75
15.75
0.27
0.74
0.51
5
4.57
Molded Package Thickness
Standoff
A2
A1
A3
CH1
CH2
E
.160
.035
.034
.050
.010
.695
.695
.656
.656
.630
.630
.013
.032
.021
10
4.06
0.89
0.86
1.27
0.25
17.65
17.65
16.66
16.66
16.00
16.00
0.33
0.81
0.53
10
§
Side 1 Chamfer Height
Corner Chamfer 1
Corner Chamfer (others)
Overall Width
Overall Length
D
Molded Package Width
Molded Package Length
Footprint Width
E1
D1
E2
D2
c
Footprint Length
Lead Thickness
Upper Lead Width
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
B1
B
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-048
DS30292D-page 196
1998-2013 Microchip Technology Inc.
PIC16F87X
APPENDIX A: REVISION HISTORY
APPENDIX B: DEVICE
DIFFERENCES
Version
Date
Revision Description
The differences between the devices in this data sheet
are listed in Table B-1.
A
1998
This is a new data sheet.
However, these devices are
similar to the PIC16C7X
devices found in the
TABLE B-1:
DEVICE DIFFERENCES
PIC16C7X Data Sheet
(DS30390). Data Memory
Map for PIC16F873/874,
moved ADFM bit from
Difference
PIC16F876/873
PIC16F877/874
A/D
5 channels,
10-bits
8 channels,
10-bits
ADCON1<5> to ADCON1<7>.
B
C
1999
2000
FLASH EEPROM access
information.
Parallel
no
yes
DC characteristics updated.
DC performance graphs
added.
Slave Port
Packages
28-pin PDIP,
28-pin windowed
CERDIP, 28-pin
SOIC
40-pin PDIP,
44-pin TQFP,
44-pin MQFP,
44-pin PLCC
D
2013
Added a note to each package
drawing.
1998-2013 Microchip Technology Inc.
DS30292D-page 197
PIC16F87X
APPENDIX C: CONVERSION
CONSIDERATIONS
Considerations for converting from previous versions
of devices to the ones listed in this data sheet are listed
in Table C-1.
TABLE C-1:
Characteristic
CONVERSION
CONSIDERATIONS
PIC16C7X
PIC16F87X
Pins
Timers
28/40
3
28/40
3
Interrupts
11 or 12
13 or 14
Communication
PSP, USART,
SSP (SPI, I2C
Slave)
PSP, USART,
SSP (SPI, I2C
Master/Slave)
Frequency
Voltage
A/D
20 MHz
2.5V - 5.5V
8-bit
20 MHz
2.0V - 5.5V
10-bit
CCP
2
2
Program
Memory
4K, 8K
EPROM
4K, 8K
FLASH
RAM
EEPROM data
Other
192, 368
bytes
192, 368
bytes
None
128, 256
bytes
In-Circuit
Debugger,
Low Voltage
Programming
DS30292D-page 198
1998-2013 Microchip Technology Inc.
PIC16F87X
INDEX
PIC16F874/PIC16F877 ............................................... 6
PORTA
RA3:RA0 and RA5 Pins ..................................... 29
RA4/T0CKI Pin .................................................. 29
PORTB
RB3:RB0 Port Pins ............................................ 31
RB7:RB4 Port Pins ............................................ 31
PORTC
A
A/D ................................................................................... 111
Acquisition Requirements ........................................ 114
ADCON0 Register .................................................... 111
ADCON1 Register .................................................... 112
ADIF bit .................................................................... 112
Analog Input Model Block Diagram .......................... 114
Analog Port Pins .......................................7, 8, 9, 36, 38
Associated Registers and Bits ................................. 117
Block Diagram .......................................................... 113
Calculating Acquisition Time .................................... 114
Configuring Analog Port Pins ................................... 115
Configuring the Interrupt .......................................... 113
Configuring the Module ............................................ 113
Conversion Clock ..................................................... 115
Conversions ............................................................. 116
Delays ...................................................................... 114
Effects of a RESET .................................................. 117
GO/DONE bit ........................................................... 112
Internal Sampling Switch (Rss) Impedence ............. 114
Operation During SLEEP ......................................... 117
Result Registers ....................................................... 116
Sampling Requirements ........................................... 114
Source Impedence ................................................... 114
Time Delays ............................................................. 114
Absolute Maximum Ratings ............................................. 149
ACK .................................................................................... 74
Acknowledge Data bit ........................................................ 68
Acknowledge Pulse ............................................................ 74
Acknowledge Sequence Enable bit .................................... 68
Acknowledge Status bit ...................................................... 68
ADRES Register ........................................................ 15, 111
Analog Port Pins. See A/D
Peripheral Output Override (RC 0:2, 5:7) .......... 33
Peripheral Output Override (RC 3:4) ................. 33
PORTD ...................................................................... 35
PORTD and PORTE (Parallel Slave Port) ................. 38
PORTE ...................................................................... 36
PWM Mode ................................................................ 61
RESET Circuit .......................................................... 123
2
SSP (I C Mode) ......................................................... 73
SSP (SPI Mode) ........................................................ 69
Timer0/WDT Prescaler .............................................. 47
Timer1 ....................................................................... 52
Timer2 ....................................................................... 55
USART Asynchronous Receive ............................... 101
USART Asynchronous Receive (9-bit Mode) .......... 103
USART Transmit ........................................................ 99
Watchdog Timer ...................................................... 131
BOR. See Brown-out Reset
BRG ................................................................................... 79
BRGH bit ............................................................................ 97
Brown-out Reset (BOR) ............................ 119, 123, 125, 126
BOR Status (BOR Bit) ............................................... 25
Buffer Full bit, BF ............................................................... 74
Bus Arbitration ................................................................... 89
Bus Collision Section ......................................................... 89
Bus Collision During a Repeated START Condition .......... 92
Bus Collision During a START Condition .......................... 90
Bus Collision During a STOP Condition ............................ 93
Bus Collision Interrupt Flag bit, BCLIF ............................... 24
Analog-to-Digital Converter. See A/D
Application Notes
AN552 (Implementing Wake-up on Key Strokes
Using PIC16CXXX) .................................... 31
AN556 (Implementing a Table Read) ........................ 26
AN578 (Use of the SSP Module in the I2C
C
Capture/Compare/PWM (CCP) ......................................... 57
Associated Registers
Multi-Master Environment) ......................... 73
Capture, Compare and Timer1 .......................... 62
PWM and Timer2 ............................................... 63
Capture Mode ............................................................ 59
Block Diagram ................................................... 59
CCP1CON Register ........................................... 58
CCP1IF .............................................................. 59
Prescaler ........................................................... 59
CCP Timer Resources ............................................... 57
CCP1
RC2/CCP1 Pin ..................................................7, 9
CCP2
RC1/T1OSI/CCP2 Pin ......................................7, 9
Compare
Special Trigger Output of CCP1 ........................ 60
Special Trigger Output of CCP2 ........................ 60
Compare Mode .......................................................... 60
Block Diagram ................................................... 60
Software Interrupt Mode .................................... 60
Special Event Trigger ........................................ 60
Interaction of Two CCP Modules (table) .................... 57
Architecture
PIC16F873/PIC16F876 Block Diagram ....................... 5
PIC16F874/PIC16F877 Block Diagram ....................... 6
Assembler
MPASM Assembler .................................................. 143
B
Banking, Data Memory ................................................. 12, 18
Baud Rate Generator ......................................................... 79
BCLIF ................................................................................. 24
BF ............................................................................74, 82, 84
Block Diagrams
A/D ........................................................................... 113
A/D Converter .......................................................... 113
Analog Input Model .................................................. 114
Baud Rate Generator ................................................. 79
Capture Mode ............................................................ 59
Compare Mode .......................................................... 60
2
I C Master Mode ........................................................ 78
2
I C Module ................................................................. 73
2
I C Slave Mode .......................................................... 73
Interrupt Logic .......................................................... 129
PIC16F873/PIC16F876 ................................................ 5
1998-2013 Microchip Technology Inc.
DS30292D-page 199
PIC16F87X
PWM Mode ................................................................61
Block Diagram ....................................................61
Duty Cycle ..........................................................61
Example Frequencies/Resolutions (Table) ........62
PWM Period .......................................................61
Special Event Trigger and A/D Conversions ..............60
CCP. See Capture/Compare/PWM
E
Electrical Characteristics .................................................. 149
Errata ................................................................................... 4
External Clock Input (RA4/T0CKI). See Timer0
External Interrupt Input (RB0/INT). See Interrupt Sources
F
CCP1CON ..........................................................................17
CCP2CON ..........................................................................17
CCPR1H Register .................................................. 15, 17, 57
CCPR1L Register ......................................................... 17, 57
CCPR2H Register ........................................................ 15, 17
CCPR2L Register ......................................................... 15, 17
CCPxM0 bit ........................................................................58
CCPxM1 bit ........................................................................58
CCPxM2 bit ........................................................................58
CCPxM3 bit ........................................................................58
CCPxX bit ...........................................................................58
CCPxY bit ...........................................................................58
CKE ....................................................................................66
CKP ....................................................................................67
Clock Polarity Select bit, CKP ............................................67
Code Examples
Call of a Subroutine in Page 1 from Page 0 ...............26
EEPROM Data Read .................................................43
EEPROM Data Write ..................................................43
FLASH Program Read ...............................................44
FLASH Program Write ...............................................45
Indirect Addressing ....................................................27
Initializing PORTA ......................................................29
Saving STATUS, W and PCLATH Registers ...........130
Code Protected Operation
Firmware Instructions ....................................................... 135
FLASH Program Memory ................................................... 41
Associated Registers ................................................. 46
Code Protection ......................................................... 45
Configuration Bits and Read/Write State ................... 46
Reading ..................................................................... 44
Special Function Registers ........................................ 41
Spurious Write Protection .......................................... 45
Write Protection ......................................................... 46
Write Verify ................................................................ 45
Writing to .................................................................... 44
FSR Register ....................................................15, 16, 17, 27
G
General Call Address Sequence ........................................ 76
General Call Address Support ........................................... 76
General Call Enable bit ...................................................... 68
I
I/O Ports ............................................................................. 29
2
I C ...................................................................................... 73
2
I C Bus
Connection Considerations ........................................ 94
Sample Device Configuration .................................... 94
I C Master Mode Reception ............................................... 84
I C Master Mode Repeated START Condition .................. 81
I C Mode Selection ............................................................ 73
2
2
Data EEPROM and FLASH Program Memory ...........45
Code Protection ....................................................... 119, 133
Computed GOTO ...............................................................26
Configuration Bits .............................................................119
Configuration Word ..........................................................120
Conversion Considerations ..............................................198
2
2
I C Module
Acknowledge Sequence Timing ................................ 86
Addressing ................................................................. 74
Associated Registers ................................................. 77
Baud Rate Generator ................................................. 79
Block Diagram ........................................................... 78
BRG Block Diagram ................................................... 79
BRG Reset due to SDA Collision ............................... 91
BRG Timing ............................................................... 80
Bus Arbitration ........................................................... 89
Bus Collision .............................................................. 89
Acknowledge ..................................................... 89
Repeated START Condition .............................. 92
Repeated START Condition Timing
D
D/A .....................................................................................66
Data EEPROM ...................................................................41
Associated Registers .................................................46
Code Protection .........................................................45
Reading ......................................................................43
Special Functions Registers .......................................41
Spurious Write Protection ..........................................45
Write Verify .................................................................45
Writing to ....................................................................43
Data Memory ......................................................................12
Bank Select (RP1:RP0 Bits) ................................. 12, 18
General Purpose Registers ........................................12
Register File Map ................................................. 13, 14
Special Function Registers ........................................15
Data/Address bit, D/A .........................................................66
DC and AC Characteristics Graphs and Tables ...............177
DC Characteristics
(Case1) .............................................. 92
Repeated START Condition Timing
(Case2) .............................................. 92
START Condition ............................................... 90
START Condition Timing ..............................90, 91
STOP Condition ................................................. 93
STOP Condition Timing (Case1) ....................... 93
STOP Condition Timing (Case2) ....................... 93
Transmit Timing ................................................. 89
Bus Collision Timing .................................................. 89
Clock Arbitration ........................................................ 88
Clock Arbitration Timing (Master Transmit) ............... 88
Conditions to not give ACK Pulse .............................. 74
General Call Address Support ................................... 76
Master Mode .............................................................. 78
Master Mode 7-bit Reception Timing ......................... 85
Master Mode Block Diagram ..................................... 78
Commercial and Industrial ............................... 152–156
Extended .......................................................... 157–160
Development Support ......................................................143
Device Differences ...........................................................197
Device Overview ..................................................................5
Direct Addressing ...............................................................27
DS30292D-page 200
1998-2013 Microchip Technology Inc.
PIC16F87X
Master Mode Operation ............................................. 79
Master Mode START Condition ................................. 80
Master Mode Transmission ........................................ 82
Master Mode Transmit Sequence .............................. 79
Multi-Master Communication ..................................... 89
Multi-master Mode ..................................................... 78
Operation ................................................................... 73
Repeat START Condition Timing ............................... 81
Slave Mode ................................................................ 74
Block Diagram .................................................... 73
Slave Reception ......................................................... 74
Slave Transmission .................................................... 75
SSPBUF ..................................................................... 73
STOP Condition Receive or Transmit Timing ............ 87
STOP Condition Timing ............................................. 87
Waveforms for 7-bit Reception .................................. 75
Waveforms for 7-bit Transmission ............................. 76
INT Interrupt (RB0/INT). See Interrupt Sources
INTCON ............................................................................. 17
INTCON Register ............................................................... 20
GIE Bit ....................................................................... 20
INTE Bit ..................................................................... 20
INTF Bit ..................................................................... 20
PEIE Bit ..................................................................... 20
RBIE Bit ..................................................................... 20
RBIF Bit ................................................................20, 31
T0IE Bit ...................................................................... 20
T0IF Bit ...................................................................... 20
2
Inter-Integrated Circuit (I C) .............................................. 65
Internal Sampling Switch (Rss) Impedence ..................... 114
Interrupt Sources ......................................................119, 129
Block Diagram ......................................................... 129
Interrupt-on-Change (RB7:RB4 ) ............................... 31
RB0/INT Pin, External .......................................7, 8, 130
TMR0 Overflow ........................................................ 130
USART Receive/Transmit Complete ......................... 95
Interrupts
2
I C Module Address Register, SSPADD ............................ 73
I C Slave Mode .................................................................. 74
2
ICEPIC In-Circuit Emulator .............................................. 144
ID Locations ............................................................. 119, 133
In-Circuit Serial Programming (ICSP) ...................... 119, 134
INDF ................................................................................... 17
INDF Register .........................................................15, 16, 27
Indirect Addressing ............................................................ 27
FSR Register ............................................................. 12
Instruction Format ............................................................ 135
Instruction Set .................................................................. 135
ADDLW .................................................................... 137
ADDWF .................................................................... 137
ANDLW .................................................................... 137
ANDWF .................................................................... 137
BCF .......................................................................... 137
BSF .......................................................................... 137
BTFSC ..................................................................... 137
BTFSS ..................................................................... 137
CALL ........................................................................ 138
CLRF ........................................................................ 138
CLRW ...................................................................... 138
CLRWDT .................................................................. 138
COMF ...................................................................... 138
DECF ....................................................................... 138
DECFSZ ................................................................... 139
GOTO ...................................................................... 139
INCF ......................................................................... 139
INCFSZ .................................................................... 139
IORLW ..................................................................... 139
IORWF ..................................................................... 139
MOVF ....................................................................... 140
MOVLW ................................................................... 140
MOVWF ................................................................... 140
NOP ......................................................................... 140
RETFIE .................................................................... 140
RETLW .................................................................... 140
RETURN .................................................................. 141
RLF .......................................................................... 141
RRF .......................................................................... 141
SLEEP ..................................................................... 141
SUBLW .................................................................... 141
SUBWF .................................................................... 141
SWAPF .................................................................... 142
XORLW .................................................................... 142
XORWF .................................................................... 142
Summary Table ........................................................ 136
Bus Collision Interrupt ................................................ 24
Synchronous Serial Port Interrupt .............................. 22
Interrupts, Context Saving During .................................... 130
Interrupts, Enable Bits
Global Interrupt Enable (GIE Bit) ........................20, 129
Interrupt-on-Change (RB7:RB4) Enable
(RBIE Bit) ................................................. 130
Interrupt-on-Change (RB7:RB4) Enable
(RBIE Bit) ................................................... 20
Peripheral Interrupt Enable (PEIE Bit) ....................... 20
RB0/INT Enable (INTE Bit) ........................................ 20
TMR0 Overflow Enable (T0IE Bit) ............................. 20
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit) ................................................. 130
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit) ..............................................20, 31
RB0/INT Flag (INTF Bit) ............................................ 20
TMR0 Overflow Flag (T0IF Bit) ...........................20, 130
K
KEELOQ Evaluation and Programming Tools ................... 146
L
Loading of PC .................................................................... 26
M
Master Clear (MCLR) ........................................................7, 8
MCLR Reset, Normal Operation ...............123, 125, 126
MCLR Reset, SLEEP ................................123, 125, 126
Memory Organization
Data Memory ............................................................. 12
Program Memory ....................................................... 11
MPLAB C17 and MPLAB C18 C Compilers .................... 143
MPLAB ICD In-Circuit Debugger ..................................... 145
MPLAB ICE High Performance Universal In-Circuit
Emulator with MPLAB IDE ............................................... 144
MPLAB Integrated Development Environment Software . 143
MPLINK Object Linker/MPLIB Object Librarian ............... 144
Multi-Master Communication ............................................. 89
Multi-Master Mode ............................................................. 78
1998-2013 Microchip Technology Inc.
DS30292D-page 201
PIC16F87X
PORTA .......................................................................7, 8, 17
Analog Port Pins .......................................................7, 8
Associated Registers ................................................. 30
Block Diagram
O
On-Line Support ...............................................................207
OPCODE Field Descriptions ............................................135
OPTION_REG Register ............................................... 19, 48
INTEDG Bit ................................................................19
PS2:PS0 Bits ..............................................................19
PSA Bit .......................................................................19
T0CS Bit .....................................................................19
T0SE Bit .....................................................................19
OSC1/CLKIN Pin .............................................................. 7, 8
OSC2/CLKOUT Pin .......................................................... 7, 8
Oscillator Configuration ....................................................119
HS .................................................................... 121, 124
LP ..................................................................... 121, 124
RC ............................................................ 121, 122, 124
XT ..................................................................... 121, 124
Oscillator, WDT ................................................................131
Oscillators
RA3:RA0 and RA5 Pins ..................................... 29
RA4/T0CKI Pin .................................................. 29
Initialization ................................................................ 29
PORTA Register ...................................................15, 29
RA3
RA0 and RA5 Port Pins ..................................... 29
RA4/T0CKI Pin .........................................................7, 8
RA5/SS/AN4 Pin .......................................................7, 8
TRISA Register .......................................................... 29
PORTB .......................................................................7, 8, 17
Associated Registers ................................................. 32
Block Diagram
RB3:RB0 Port Pins ............................................ 31
RB7:RB4 Port Pins ............................................ 31
PORTB Register ...................................................15, 31
RB0/INT Edge Select (INTEDG Bit) .......................... 19
RB0/INT Pin, External .......................................7, 8, 130
RB7:RB4 Interrupt on Change ................................. 130
RB7:RB4 Interrupt on Change Enable
(RBIE Bit) ................................................. 130
RB7:RB4 Interrupt on Change Flag
(RBIF Bit) ................................................. 130
RB7:RB4 Interrupt-on-Change Enable
Capacitor Selection ..................................................122
Crystal and Ceramic Resonators .............................121
RC ............................................................................122
P
P (STOP bit) .......................................................................66
Package Marking Information ..........................................189
Packaging Information .....................................................189
Paging, Program Memory ............................................ 11, 26
Parallel Slave Port (PSP) ......................................... 9, 35, 38
Associated Registers .................................................39
Block Diagram ............................................................38
RE0/RD/AN5 Pin .............................................. 9, 36, 38
RE1/WR/AN6 Pin ............................................. 9, 36, 38
RE2/CS/AN7 Pin .............................................. 9, 36, 38
Read Waveforms .......................................................39
Select (PSPMODE Bit) ..............................35, 36, 37, 38
Write Waveforms ........................................................39
PCL Register .......................................................... 15, 16, 26
PCLATH Register ..............................................15, 16, 17, 26
PCON Register .......................................................... 25, 124
BOR Bit ......................................................................25
POR Bit ......................................................................25
PIC16F876 Pinout Description .............................................7
PIC16F87X Product Identification System .......................209
PICDEM 1 Low Cost PIC MCU
Demonstration Board ...................................................145
PICDEM 17 Demonstration Board ...................................146
PICDEM 2 Low Cost PIC16CXX
Demonstration Board ...................................................145
PICDEM 3 Low Cost PIC16CXXX
Demonstration Board ...................................................146
PICSTART Plus Entry Level
Development Programmer ...........................................145
PIE1 Register .....................................................................21
PIE2 Register .....................................................................23
Pinout Descriptions
(RBIE Bit) ................................................... 20
RB7:RB4 Interrupt-on-Change Flag
(RBIF Bit) ..............................................20, 31
TRISB Register .....................................................17, 31
PORTC .......................................................................7, 9, 17
Associated Registers ................................................. 34
Block Diagrams
Peripheral Output Override
(RC 0:2, 5:7) ...................................... 33
Peripheral Output Override
(RC 3:4) ............................................. 33
PORTC Register ...................................................15, 33
RC0/T1OSO/T1CKI Pin ............................................7, 9
RC1/T1OSI/CCP2 Pin ..............................................7, 9
RC2/CCP1 Pin ..........................................................7, 9
RC3/SCK/SCL Pin ....................................................7, 9
RC4/SDI/SDA Pin .....................................................7, 9
RC5/SDO Pin ............................................................7, 9
RC6/TX/CK Pin ...................................................7, 9, 96
RC7/RX/DT Pin .............................................7, 9, 96, 97
TRISC Register .....................................................33, 95
PORTD .....................................................................9, 17, 38
Associated Registers ................................................. 35
Block Diagram ........................................................... 35
Parallel Slave Port (PSP) Function ............................ 35
PORTD Register ...................................................15, 35
TRISD Register .......................................................... 35
PIC16F873/PIC16F876 ................................................7
PIC16F874/PIC16F877 ................................................8
PIR1 Register .....................................................................22
PIR2 Register .....................................................................24
POP ....................................................................................26
POR. See Power-on Reset
DS30292D-page 202
1998-2013 Microchip Technology Inc.
PIC16F87X
PORTE ........................................................................... 9, 17
Analog Port Pins ...............................................9, 36, 38
Associated Registers ................................................. 36
Block Diagram ............................................................ 36
Input Buffer Full Status (IBF Bit) ................................ 37
Input Buffer Overflow (IBOV Bit) ................................ 37
Output Buffer Full Status (OBF Bit) ............................ 37
PORTE Register .................................................. 15, 36
PSP Mode Select (PSPMODE Bit) ...........35, 36, 37, 38
RE0/RD/AN5 Pin ...............................................9, 36, 38
RE1/WR/AN6 Pin ..............................................9, 36, 38
RE2/CS/AN7 Pin ...............................................9, 36, 38
TRISE Register .......................................................... 36
Postscaler, WDT
Registers
ADCON0 (A/D Control 0) ......................................... 111
ADCON1 (A/D Control 1) ......................................... 112
CCP1CON (CCP Control 1) ....................................... 58
EECON2 .................................................................... 41
FSR ........................................................................... 27
INTCON ..................................................................... 20
OPTION_REG ......................................................19, 48
PCON (Power Control) .............................................. 25
PIE1 (Peripheral Interrupt Enable 1) .......................... 21
PIE2 (Peripheral Interrupt Enable 2) .......................... 23
PIR1 (Peripheral Interrupt Request 1) ....................... 22
PIR2 (Peripheral Interrupt Request 2) ....................... 24
RCSTA (Receive Status and Control) ....................... 96
Special Function, Summary ....................................... 15
SSPCON2 (Sync Serial Port Control 2) ..................... 68
STATUS .................................................................... 18
T1CON (Timer1 Control) ........................................... 51
T2CON (Timer 2 Control)
Assignment (PSA Bit) ................................................ 19
Rate Select (PS2:PS0 Bits) ....................................... 19
Power-down Mode. See SLEEP
Power-on Reset (POR) .....................119, 123, 124, 125, 126
Oscillator Start-up Timer (OST) ....................... 119, 124
POR Status (POR Bit) ................................................ 25
Power Control (PCON) Register .............................. 124
Power-down (PD Bit) ......................................... 18, 123
Power-up Timer (PWRT) ................................. 119, 124
Time-out (TO Bit) ............................................... 18, 123
Time-out Sequence on Power-up .................... 127, 128
PR2 Register ................................................................ 16, 55
Prescaler, Timer0
Timer2
T2CON Register ........................................ 55
TRISE ........................................................................ 37
TXSTA (Transmit Status and Control) ....................... 95
Repeated START Condition Enable bit ............................. 68
RESET ......................................................................119, 123
Block Diagram ......................................................... 123
MCLR Reset. See MCLR
Assignment (PSA Bit) ................................................ 19
Rate Select (PS2:PS0 Bits) ....................................... 19
PRO MATE II Universal Device Programmer .................. 145
Program Counter
RESET
Brown-out Reset (BOR). See Brown-out Reset (BOR)
Power-on Reset (POR). See Power-on Reset (POR)
RESET Conditions for PCON Register .................... 125
RESET Conditions for Program Counter ................. 125
RESET Conditions for STATUS Register ................ 125
WDT Reset. See Watchdog Timer (WDT)
RESET Conditions ................................................... 125
Program Memory ............................................................... 11
Interrupt Vector .......................................................... 11
Paging .................................................................. 11, 26
Program Memory Map ............................................... 11
RESET Vector ............................................................ 11
Program Verification ......................................................... 133
Programming Pin (VPP) .................................................... 7, 8
Programming, Device Instructions ................................... 135
PSP. See Parallel Slave Port. ............................................ 38
Pulse Width Modulation.SeeCapture/Compare/PWM,
PWM Mode.
Revision History ............................................................... 197
S
S (START bit) .................................................................... 66
Sales and Support ........................................................... 209
SCI. See USART
SCK ................................................................................... 69
SCL .................................................................................... 74
SDA ................................................................................... 74
SDI ..................................................................................... 69
SDO ................................................................................... 69
Serial Clock, SCK .............................................................. 69
Serial Clock, SCL ............................................................... 74
Serial Communication Interface. See USART
Serial Data Address, SDA ................................................. 74
Serial Data In, SDI ............................................................. 69
Serial Data Out, SDO ........................................................ 69
Slave Select, SS ................................................................ 69
SLEEP ..............................................................119, 123, 132
SMP ................................................................................... 66
Software Simulator (MPLAB SIM) ................................... 144
SPBRG Register ................................................................ 16
Special Features of the CPU ........................................... 119
Special Function Registers ................................................ 15
Special Function Registers (SFRs) .................................... 15
Data EEPROM and FLASH Program Memory .......... 41
Speed, Operating ................................................................. 1
PUSH ................................................................................. 26
R
R/W .................................................................................... 66
R/W bit ............................................................................... 74
R/W bit ............................................................................... 74
RAM. See Data Memory
RCREG .............................................................................. 17
RCSTA Register ........................................................... 17, 96
ADDEN Bit ................................................................. 96
CREN Bit .................................................................... 96
FERR Bit .................................................................... 96
OERR Bit ................................................................... 96
RX9 Bit ....................................................................... 96
RX9D Bit .................................................................... 96
SPEN Bit .............................................................. 95, 96
SREN Bit .................................................................... 96
Read/Write bit, R/W ........................................................... 66
Reader Response ............................................................ 208
Receive Enable bit ............................................................. 68
Receive Overflow Indicator bit, SSPOV ............................. 67
Register File ....................................................................... 12
Register File Map ......................................................... 13, 14
1998-2013 Microchip Technology Inc.
DS30292D-page 203
PIC16F87X
SPI
Synchronous Serial Port .................................................... 65
Synchronous Serial Port Enable bit, SSPEN ..................... 67
Synchronous Serial Port Interrupt ...................................... 22
Synchronous Serial Port Mode Select bits,
Master Mode ..............................................................70
Master Mode Timing ..................................................70
Serial Clock ................................................................69
Serial Data In .............................................................69
Serial Data Out ...........................................................69
Serial Peripheral Interface (SPI) ................................65
Slave Mode Timing ....................................................71
Slave Mode Timing Diagram ......................................71
Slave Select ...............................................................69
SPI Clock ...................................................................70
SPI Mode ...................................................................69
SPI Clock Edge Select, CKE ..............................................66
SPI Data Input Sample Phase Select, SMP .......................66
SPI Mode
SSPM3:SSPM0 ............................................................. 67
T
T1CKPS0 bit ...................................................................... 51
T1CKPS1 bit ...................................................................... 51
T1CON ............................................................................... 17
T1CON Register ................................................................ 17
T1OSCEN bit ..................................................................... 51
T1SYNC bit ........................................................................ 51
T2CKPS0 bit ...................................................................... 55
T2CKPS1 bit ...................................................................... 55
T2CON Register ...........................................................17, 55
TAD ................................................................................... 115
Time-out Sequence ......................................................... 124
Timer0 ................................................................................ 47
Associated Registers ................................................. 49
Clock Source Edge Select (T0SE Bit) ....................... 19
Clock Source Select (T0CS Bit) ................................. 19
External Clock ............................................................ 48
Interrupt ..................................................................... 47
Overflow Enable (T0IE Bit) ........................................ 20
Overflow Flag (T0IF Bit) ......................................20, 130
Overflow Interrupt .................................................... 130
Prescaler .................................................................... 48
RA4/T0CKI Pin, External Clock ................................7, 8
T0CKI ......................................................................... 48
WDT Prescaler Block Diagram .................................. 47
Timer1 ................................................................................ 51
Associated Registers ................................................. 54
Asynchronous Counter Mode .................................... 53
Reading and Writing to ...................................... 53
Block Diagram ........................................................... 52
Counter Operation ..................................................... 52
Operation in Timer Mode ........................................... 52
Oscillator .................................................................... 53
Capacitor Selection ............................................ 53
Prescaler .................................................................... 54
RC0/T1OSO/T1CKI Pin ............................................7, 9
RC1/T1OSI/CCP2 Pin ..............................................7, 9
Resetting of Timer1 Registers ................................... 54
Resetting Timer1 using a CCP Trigger Output .......... 53
Synchronized Counter Mode ..................................... 52
T1CON ....................................................................... 51
T1CON Register ........................................................ 51
TMR1H ...................................................................... 53
TMR1L ....................................................................... 53
Timer2 ................................................................................ 55
Associated Registers ................................................. 56
Block Diagram ........................................................... 55
Output ........................................................................ 56
Postscaler .................................................................. 55
Prescaler .................................................................... 55
T2CON ....................................................................... 55
Timing Diagrams
Associated Registers .................................................72
SPI Module
Slave Mode ................................................................71
SS ......................................................................................69
SSP ....................................................................................65
Block Diagram (SPI Mode) .........................................69
RA5/SS/AN4 Pin ...................................................... 7, 8
RC3/SCK/SCL Pin ................................................... 7, 9
RC4/SDI/SDA Pin .................................................... 7, 9
RC5/SDO Pin ........................................................... 7, 9
SPI Mode ...................................................................69
SSPADD .............................................................. 73, 74
SSPBUF ............................................................... 70, 73
SSPCON2 ..................................................................68
SSPSR ................................................................. 70, 74
SSPSTAT ...................................................................73
2
SSP I C
2
SSP I C Operation .....................................................73
SSP Module
SPI Master Mode .......................................................70
SPI Slave Mode .........................................................71
SSPCON1 Register ....................................................73
SSP Overflow Detect bit, SSPOV ......................................74
SSPADD Register ..............................................................16
SSPBUF ................................................................. 17, 73, 74
SSPBUF Register ..............................................................15
SSPCON Register ..............................................................15
SSPCON1 ..........................................................................73
SSPCON2 Register ............................................................68
SSPEN ...............................................................................67
SSPIF ........................................................................... 22, 74
SSPM3:SSPM0 ..................................................................67
SSPOV ................................................................... 67, 74, 84
SSPSTAT ...........................................................................73
SSPSTAT Register ............................................................16
Stack ..................................................................................26
Overflows ...................................................................26
Underflow ...................................................................26
START bit (S) .....................................................................66
START Condition Enable bit ..............................................68
STATUS Register ...............................................................18
C Bit ...........................................................................18
DC Bit .........................................................................18
IRP Bit ........................................................................18
PD Bit ................................................................. 18, 123
RP1:RP0 Bits .............................................................18
TO Bit ................................................................. 18, 123
Z Bit ............................................................................18
STOP bit (P) .......................................................................66
STOP Condition Enable bit ................................................68
A/D Conversion ........................................................ 175
Acknowledge Sequence Timing ................................ 86
Baud Rate Generator with Clock Arbitration .............. 80
BRG Reset Due to SDA Collision .............................. 91
Brown-out Reset ...................................................... 164
Bus Collision
START Condition Timing ................................... 90
DS30292D-page 204
1998-2013 Microchip Technology Inc.
PIC16F87X
Bus Collision During a Repeated
START Condition (Case 1) ........................ 92
Bus Collision During a Repeated
START Condition (Case2) ......................... 92
Bus Collision During a START
Condition (SCL = 0) ................................... 91
TXSTA Register ................................................................. 95
BRGH Bit ................................................................... 95
CSRC Bit ................................................................... 95
SYNC Bit ................................................................... 95
TRMT Bit .................................................................... 95
TX9 Bit ....................................................................... 95
TX9D Bit .................................................................... 95
TXEN Bit .................................................................... 95
Bus Collision During a STOP Condition ..................... 93
Bus Collision for Transmit and Acknowledge ............. 89
Capture/Compare/PWM ........................................... 166
CLKOUT and I/O ...................................................... 163
U
2
UA ...................................................................................... 66
Universal Synchronous Asynchronous Receiver
Transmitter. See USART
I C Bus Data ............................................................ 171
2
I C Bus START/STOP bits ...................................... 170
2
I C Master Mode First START Bit Timing .................. 80
2
Update Address, UA .......................................................... 66
USART ............................................................................... 95
Address Detect Enable (ADDEN Bit) ......................... 96
Asynchronous Mode .................................................. 99
Asynchronous Receive ............................................ 101
Associated Registers ....................................... 102
Block Diagram ................................................. 101
Asynchronous Receive (9-bit Mode) ........................ 103
Associated Registers ....................................... 104
Block Diagram ................................................. 103
Timing Diagram ............................................... 104
Asynchronous Receive with Address Detect.
I C Master Mode Reception Timing ........................... 85
2
I C Master Mode Transmission Timing ...................... 83
Master Mode Transmit Clock Arbitration .................... 88
Power-up Timer ....................................................... 164
Repeat START Condition .......................................... 81
RESET ..................................................................... 164
SPI Master Mode ....................................................... 70
SPI Slave Mode (CKE = 1) ........................................ 71
SPI Slave Mode Timing (CKE = 0) ............................. 71
Start-up Timer .......................................................... 164
STOP Condition Receive or Transmit ........................ 87
Time-out Sequence on Power-up .................... 127, 128
Timer0 ...................................................................... 165
Timer1 ...................................................................... 165
USART Asynchronous Master Transmission ........... 100
USART Asynchronous Reception ............................ 102
USART Synchronous Receive ................................. 173
USART Synchronous Reception .............................. 108
USART Synchronous Transmission ................ 106, 173
USART, Asynchronous Reception ........................... 104
Wake-up from SLEEP via Interrupt .......................... 133
Watchdog Timer ....................................................... 164
TMR0 ................................................................................. 17
TMR0 Register ................................................................... 15
TMR1CS bit ........................................................................ 51
TMR1H ............................................................................... 17
TMR1H Register ................................................................ 15
TMR1L ............................................................................... 17
TMR1L Register ................................................................. 15
TMR1ON bit ....................................................................... 51
TMR2 ................................................................................. 17
TMR2 Register ................................................................... 15
TMR2ON bit ....................................................................... 55
TOUTPS0 bit ...................................................................... 55
TOUTPS1 bit ...................................................................... 55
TOUTPS2 bit ...................................................................... 55
TOUTPS3 bit ...................................................................... 55
TRISA Register .................................................................. 16
TRISB Register .................................................................. 16
TRISC Register .................................................................. 16
TRISD Register .................................................................. 16
TRISE Register .......................................................16, 36, 37
IBF Bit ........................................................................ 37
IBOV Bit ..................................................................... 37
OBF Bit ...................................................................... 37
PSPMODE Bit ...........................................35, 36, 37, 38
TXREG ............................................................................... 17
SeeAsynchronous Receive (9-bit Mode).
Asynchronous Reception ......................................... 102
Asynchronous Transmitter ......................................... 99
Baud Rate Generator (BRG) ..................................... 97
Baud Rate Formula ........................................... 97
Baud Rates, Asynchronous Mode (BRGH=0) ... 98
High Baud Rate Select (BRGH Bit) ................... 95
Sampling ............................................................ 97
Clock Source Select (CSRC Bit) ................................ 95
Continuous Receive Enable (CREN Bit) .................... 96
Framing Error (FERR Bit) .......................................... 96
Mode Select (SYNC Bit) ............................................ 95
Overrun Error (OERR Bit) .......................................... 96
RC6/TX/CK Pin .........................................................7, 9
RC7/RX/DT Pin .........................................................7, 9
RCSTA Register ........................................................ 96
Receive Data, 9th bit (RX9D Bit) ............................... 96
Receive Enable, 9-bit (RX9 Bit) ................................. 96
Serial Port Enable (SPEN Bit) ..............................95, 96
Single Receive Enable (SREN Bit) ............................ 96
Synchronous Master Mode ...................................... 105
Synchronous Master Reception ............................... 107
Associated Registers ....................................... 107
Synchronous Master Transmission ......................... 105
Associated Registers ....................................... 106
Synchronous Slave Mode ........................................ 108
Synchronous Slave Reception ................................. 109
Associated Registers ....................................... 109
Synchronous Slave Transmit ................................... 108
Associated Registers ....................................... 108
Transmit Block Diagram ............................................ 99
Transmit Data, 9th Bit (TX9D) ................................... 95
Transmit Enable (TXEN Bit) ...................................... 95
Transmit Enable, Nine-bit (TX9 Bit) ........................... 95
Transmit Shift Register Status (TRMT Bit) ................ 95
TXSTA Register ......................................................... 95
1998-2013 Microchip Technology Inc.
DS30292D-page 205
PIC16F87X
W
Wake-up from SLEEP .............................................. 119, 132
Interrupts .......................................................... 125, 126
MCLR Reset .............................................................126
Timing Diagram ........................................................133
WDT Reset ...............................................................126
Watchdog Timer (WDT) ........................................... 119, 131
Block Diagram ..........................................................131
Enable (WDTE Bit) ...................................................131
Postscaler. See Postscaler, WDT
Programming Considerations ...................................131
RC Oscillator ............................................................131
Time-out Period ........................................................131
WDT Reset, Normal Operation ................ 123, 125, 126
WDT Reset, SLEEP ................................. 123, 125, 126
Waveform for General Call Address Sequence .................76
WCOL ................................................... 67, 80, 82, 84, 86, 87
WCOL Status Flag .............................................................80
Write Collision Detect bit, WCOL .......................................67
Write Verify
Data EEPROM and FLASH Program Memory ...........45
WWW, On-Line Support .......................................................4
DS30292D-page 206
1998-2013 Microchip Technology Inc.
PIC16F87X
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
1998-2013 Microchip Technology Inc.
DS30292D-page 207
PIC16F87X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
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Reader Response
Total Pages Sent
RE:
From:
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Literature Number:
DS30292D
Device:
PIC16F87X
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30292D-page 208
1998-2013 Microchip Technology Inc.
PIC16F87X
PIC16F87X PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature Package
Range
Pattern
a)
PIC16F877 - 20/P 301 = Commercial temp.,
PDIP package, 4 MHz, normal VDD limits, QTP
pattern #301.
b)
c)
PIC16LF876 - 04I/SO = Industrial temp., SOIC
package, 200 kHz, Extended VDD limits.
PIC16F877 - 10E/P = Extended temp., PDIP
package, 10MHz, normal VDD limits.
Device
PIC16F87X(1), PIC16F87XT(2); VDD range 4.0V to 5.5V
PIC16LF87X(1), PIC16LF87XT(2 ); VDD range 2.0V to 5.5V
Frequency Range
Temperature Range
Package
04
10
20
=
=
=
4 MHz
10 MHz
20 MHz
blank =
I
E
0C to +70C (Commercial)
-40C to +85C (Industrial)
-40C to +125C (Extended)
=
=
Note 1:
2:
F
= CMOS FLASH
PQ
PT
SO
SP
P
=
=
=
=
=
=
MQFP (Metric PQFP)
TQFP (Thin Quad Flatpack)
SOIC
Skinny plastic DIP
PDIP
LF = Low Power CMOS FLASH
T
= in tape and reel - SOIC, PLCC,
MQFP, TQFP packages only.
L
PLCC
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
1998-2013 Microchip Technology Inc.
DS30292D-page 209
PIC16F87X
NOTES:
DS30292D-page 210
1998-2013 Microchip Technology Inc.
PIC16F87X
NOTES:
1998-2013 Microchip Technology Inc.
DS30292D-page 211
PIC16F87X
NOTES:
DS30292D-page 212
1998-2013 Microchip Technology Inc.
PIC16F87X
NOTES:
1998-2013 Microchip Technology Inc.
DS30292D-page 213
PIC16F87X
NOTES:
DS30292D-page 214
1998-2013 Microchip Technology Inc.
PIC16F87X
NOTES:
1998-2013 Microchip Technology Inc.
DS30292D-page 215
PIC16F87X
DS30292D-page 216
1998-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
32
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 1998-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620769294
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
1998-2013 Microchip Technology Inc.
DS30292D-page 217
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
www.microchip.com
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Korea - Seoul
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Los Angeles
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Fax: 886-7-330-9305
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Toronto
Mississauga, Ontario,
Canada
China - Xiamen
Tel: 905-673-0699
Fax: 905-673-6509
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
11/29/12
DS30292D-page 218
1998-2013 Microchip Technology Inc.
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