PIC16LC716T-20E/P [MICROCHIP]
8-Bit CMOS Microcontrollers with A/D Converter and Capture/Compare/PWM; 8位CMOS微控制器与A / D转换器和捕捉/比较/ PWM
| 型号： | PIC16LC716T-20E/P |
| 厂家： | 
MICROCHIP |
| 描述： | 8-Bit CMOS Microcontrollers with A/D Converter and Capture/Compare/PWM |
| 文件： | 总108页 (文件大小：1705K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC16C712/716
8-Bit CMOS Microcontrollers with A/D Converter
and Capture/Compare/PWM
Devices included in this Data Sheet:
• PIC16C712 • PIC16C716
Pin Diagrams
18-pin PDIP, SOIC, Windowed CERDIP
Microcontroller Core Features:
RA1/AN1
RA0/AN0
RA2/AN2
RA3/AN3/VREF
1
2
3
4
5
18
17
16
15
14
• High-performance RISC CPU
• Only 35 single word instructions to learn
OSC1/CLKIN
OSC2/CLKOUT
VDD
RA4/T0CKI
MCLR/VPP
• All single cycle instructions except for program
branches which are two cycle
VSS
RB0/INT
RB1/T1OSO/T1CKI
RB7
RB6
6
7
8
9
13
12
11
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
RB5
RB4
RB2/T1OSI
RB3/CCP1
10
Program
Memory
Device
Data Memory
PIC16C712
PIC16C716
1K
2K
128
128
20-pin SSOP
• Interrupt capability
(up to 7 internal/external interrupt sources)
RA1/AN1
RA0/AN0
OSC1/CLKIN
OSC2/CLKOUT
VDD
RA2/AN2
RA3/AN3/VREF
1
20
19
18
17
16
2
3
4
5
RA4/T0CKI
MCLR/VPP
• Eight level deep hardware stack
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
VSS
VSS
RB0/INT
VDD
RB7
RB6
6
15
7
14
13
RB1/T1OSO/T1CKI
8
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
12
11
RB5
RB4
9
RB2/T1OSI
RB3/CCP1
10
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Brown-out detection circuitry for
Brown-out Reset (BOR)
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Timer1: 16-bit timer/counter with prescaler
can be incremented during sleep via external
crystal/clock
• Low-power, high-speed CMOS EPROM
technology
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Fully static design
• Capture, Compare, PWM module
• In-Circuit Serial Programming (ICSP)
• Wide operating voltage range: 2.5V to 5.5V
• High Sink/Source Current 25/25 mA
• Capture is 16-bit, max. resolution is 12.5 ns,
Compare is 16-bit, max. resolution is 200 ns,
PWM maximum resolution is 10-bit
• 8-bit multi-channel Analog-to-Digital converter
• Commercial, Industrial and Extended temperature
ranges
• Low-power consumption:
- < 2 mA @ 5V, 4 MHz
- 22.5 µA typical @ 3V, 32 kHz
- < 1 µA typical standby current
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 1
PIC16C712/716
Key Features
PICmicro™ Mid-Range Reference Manual
PIC16C712
PIC16C716
(DS33023)
Operating Frequency
Resets (and Delays)
Program Memory (14-bit words)
Data Memory (bytes)
Interrupts
DC - 20 MHz
DC - 20 MHz
POR, BOR (PWRT, OST)
POR, BOR (PWRT, OST)
1K
2K
128
128
7
7
I/O Ports
Ports A,B
Ports A,B
Timers
3
3
Capture/Compare/PWM modules
8-bit Analog-to-Digital Module
1
1
4 input channels
4 input channels
PIC16C7XX FAMILY OF DEVICES
PIC16C710 PIC16C71 PIC16C711
PIC16C712
PIC16C715
PIC16C716 PIC16C72A PIC16C73B
Maximum Frequency
of Operation (MHz)
20
20
20
20
20
20
20
20
Clock
EPROM Program
Memory
(x14 words)
512
1K
1K
1K
2K
2K
2K
4K
Memory
Data Memory (bytes)
Timer Module(s)
36
36
68
128
128
128
128
192
TMR0
TMR0
TMR0
TMR0
TMR1
TMR2
TMR0
TMR0
TMR1
TMR2
TMR0
TMR1
TMR2
TMR0
TMR1
TMR2
Capture/Compare/
PWM Module(s)
—
—
4
—
—
4
—
—
4
1
—
4
—
—
4
1
—
4
1
SPI/I2C
5
2
Peripherals
Serial Port(s)
SPI/I2C,
USART
(SPI/I2C, USART)
A/D Converter (8-bit)
Channels
5
Interrupt Sources
I/O Pins
4
13
4
13
4
13
7
13
4
13
7
13
8
22
11
22
Voltage Range (Volts)
2.5-6.0
Yes
3.0-6.0
Yes
2.5-6.0
Yes
2.5-5.5
Yes
2.5-5.5
Yes
2.5-5.5
Yes
2.5-5.5
Yes
2.5-5.5
Yes
In-Circuit Serial
Programming
Features
Brown-out Reset
Packages
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
18-pin DIP,
SOIC;
18-pin DIP, 18-pin DIP,
SOIC SOIC;
18-pin DIP,
SOIC;
18-pin DIP,
SOIC;
18-pin DIP,
SOIC;
28-pin SDIP, 28-pin SDIP,
SOIC, SSOP SOIC
20-pin SSOP
20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP
DS41106A-page 2
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
Table of Contents
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
Device Overview.................................................................................................................................................. 5
Memory Organization .......................................................................................................................................... 9
I/O Ports ............................................................................................................................................................ 21
Timer0 Module................................................................................................................................................... 29
Timer1 Module................................................................................................................................................... 31
Timer2 Module................................................................................................................................................... 36
Capture/Compare/PWM (CCP) Module(s) ........................................................................................................ 39
Analog-to-Digital Converter (A/D) Module......................................................................................................... 45
Special Features of the CPU............................................................................................................................. 51
10.0 Instruction Set Summary ................................................................................................................................... 67
11.0 Development Support........................................................................................................................................ 69
12.0 Electrical Characteristics ................................................................................................................................... 75
13.0 DC and AC Characteristics Graphs and Tables................................................................................................ 91
14.0 Packaging Information....................................................................................................................................... 93
Revision History ........................................................................................................................................................... 99
Conversion Considerations .......................................................................................................................................... 99
Migration from Base-line to Mid-Range Devices .......................................................................................................... 99
Index ........................................................................................................................................................................... 101
On-Line Support.......................................................................................................................................................... 105
Reader Response....................................................................................................................................................... 106
PIC16C712/716 Product Identification System........................................................................................................... 107
To Our Valued Customers
Most Current Data Sheet
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
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An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revi-
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Corrections to this Data Sheet
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We appreciate your assistance in making this a better document.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 3
PIC16C712/716
NOTES:
DS41106A-page 4
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
ommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
1.0
DEVICE OVERVIEW
This document contains device-specific information.
Additional information may be found in the PICmicro™
Mid-Range Reference Manual, (DS33023), which may
be obtained from your local Microchip Sales Represen-
tative or downloaded from the Microchip website. The
Reference Manual should be considered a comple-
mentary document to this data sheet, and is highly rec-
There are two devices (PIC16C712, PIC16C716) cov-
ered by this datasheet.
Figure 1-1 is the block diagram for both devices. The
pinouts are listed in Table 1-1.
FIGURE 1-1: PIC16C712/716 BLOCK DIAGRAM
13
8
PORTA
Data Bus
EPROM
Program Counter
1K X 14
or
2K x 14
Program
Memory
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RAM
8 Level Stack
(13-bit)
128 x 8
File
Registers
Program
Bus
14
RAM Addr(1)
PORTB
9
Addr MUX
RB0/INT
Instruction reg
RB1/T1OSO/T1CKI
RB2/T1OSI
RB3/CCP1
Indirect
Addr
7
Direct Addr
8
FSR reg
RB4
RB5
RB6
RB7
STATUS reg
8
3
MUX
Power-up
Timer
Oscillator
Instruction
Decode &
Control
Start-up Timer
ALU
Power-on
Reset
8
OSC1/CLKIN
OSC2/CLKOUT
Timing
Generation
Watchdog
Timer
W reg
Brown-out
Reset
MCLR VDD, VSS
Timer1
Timer0
Timer2
CCP1
A/D
Note 1: Higher order bits are from the STATUS register.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 5
PIC16C712/716
TABLE 1-1
Pin
PIC16C712/716 PINOUT DESCRIPTION
PIC16C712/716
Pin
Buffer
Type
Name
DIP, SOIC
SSOP
Type
Description
Master clear (reset) input. This pin is an
MCLR/VPP
MCLR
4
4
I
ST
active low reset to the device.
Programming voltage input
VPP
P
OSC1/CLKIN
OSC1
16
18
17
I
I
ST
Oscillator crystal input or external clock
source input. ST buffer when configured in
RC mode. CMOS otherwise.
CLKIN
CMOS
External clock source input.
OSC2/CLKOUT
OSC2
15
O
O
—
—
Oscillator crystal output. Connects to
crystal or resonator in crystal oscillator
mode.
In RC mode, OSC2 pin outputs CLKOUT
which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
CLKOUT
PORTA is a bi-directional I/O port.
RA0/AN0
RA0
17
18
1
19
20
1
I/O
I
TTL
Analog
Digital I/O
Analog input 0
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O
Analog input 1
AN1
RA2/AN2
RA2
I/O
I
TTL
Analog
Digital I/O
Analog input 2
AN2
RA3/AN3/VREF
RA3
2
2
I/O
TTL
Digital I/O
AN3
VREF
I
I
Analog
Analog
Analog input 3
A/D Reference Voltage input.
RA4/T0CKI
RA4
3
3
I/O
I
ST/OD
ST
Digital I/O. Open drain when configured
as output.
Timer0 external clock input
T0CKI
Legend: TTL = TTL-compatible input
ST = Schmitt Trigger input with CMOS levels
OD = Open drain output
SM = SMBus compatible input. An external resistor is required if this pin is used as an output
CMOS = CMOS compatible input or output
NPU = N-channel pull-up
No-P diode = No P-diode to VDD
I = input
PU = Weak internal pull-up
AN = Analog input or output
O = output
P = Power
L = LCD Driver
DS41106A-page 6
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
TABLE 1-1
Pin
PIC16C712/716 PINOUT DESCRIPTION (Cont.’d)
PIC16C712/716
Pin
Buffer
Type
Name
DIP, SOIC
SSOP
Type
Description
PORTB is a bi-directional I/O port. PORTB
can be software programmed for internal
weak pull-ups on all inputs.
RB0/INT
RB0
6
7
7
8
I/O
I
TTL
ST
Digital I/O
External Interrupt
INT
RB1/T1OSO/T1CKI
RB1
T1OSO
I/O
O
TTL
—
Digital I/O
Timer1 oscillator output. Connects to
crystal in oscillator mode.
Timer1 external clock input.
T1CKI
I
ST
RB2/T1OSI
RB2
8
9
9
I/O
I
TTL
—
Digital I/O
Timer1 oscillator input. Connects to
crystal in oscillator mode.
T1OSI
RB3/CCP1
RB3
10
I/O
I/O
TTL
ST
Digital I/O
CCP1
Capture1 input, Compare1 output, PWM1
output.
RB4
RB5
RB6
10
11
12
12
12
13
I/O
I/O
I/O
TTL
TTL
TTL
Digital I/O
Interrupt on change pin.
Digital I/O
Interrupt on change pin.
Digital I/O
Interrupt on change pin.
ICSP programming clock.
I
ST
RB7
13
14
I/O
TTL
Digital I/O
Interrupt on change pin.
ICSP programming data.
I/O
P
ST
—
—
VSS
VDD
5
5, 6
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
14
15, 16
P
Legend: TTL = TTL-compatible input
ST = Schmitt Trigger input with CMOS levels
OD = Open drain output
SM = SMBus compatible input. An external resistor is required if this pin is used as an output
CMOS = CMOS compatible input or output
NPU = N-channel pull-up
No-P diode = No P-diode to VDD
I = input
PU = Weak internal pull-up
AN = Analog input or output
O = output
P = Power
L = LCD Driver
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 7
PIC16C712/716
NOTES:
DS41106A-page 8
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
FIGURE 2-2: PROGRAM MEMORY MAP
AND STACK OF PIC16C716
2.0
MEMORY ORGANIZATION
There are two memory blocks in each of these
PICmicro® microcontroller devices. Each block (Pro-
gram Memory and Data Memory) has its own bus so
that concurrent access can occur.
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
Additional information on device memory may be found
in the PICmicro
(DS33023).
Mid-Range Reference Manual,
Stack Level 1
Stack Level 8
2.1
Program Memory Organization
The PIC16C712/716 has a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. PIC16C712 has 1K x 14 words of program
memory and PIC16C716 has 2K x 14 words of program
memory. Accessing a location above the physically
implemented address will cause a wraparound.
Reset Vector
0000h
Interrupt Vector
0004h
0005h
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK OF THE
On-chip Program
Memory
PIC16C712
PC<12:0>
07FFh
0800h
CALL, RETURN
RETFIE, RETLW
13
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
0000h
Interrupt Vector
0004h
0005h
On-chip Program
Memory
03FFh
0400h
1FFFh
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 9
PIC16C712/716
2.2
Data Memory Organization
FIGURE 2-3: REGISTER FILE MAP
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
File
Address
File
Address
80h
(1)
(1)
00h
INDF
INDF
OPTION_REG
PCL
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
TMR0
PCL
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
RP1(1)
RP0
(STATUS<6:5>)
STATUS
FSR
STATUS
FSR
= 00 → Bank0
= 01 → Bank1
= 10 → Bank2 (not implemented)
= 11 → Bank3 (not implemented)
PORTA
PORTB
DATACCP
TRISA
TRISB
TRISCCP
Note 1: Maintain this bit clear to ensure upward compati-
bility with future products.
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some “high use” special function
registers from one bank may be mirrored in another
bank for code reduction and quicker access.
TMR1L
TRM1H
T1CON
TRM2
PCON
2.2.1
GENERAL PURPOSE REGISTER FILE
T2CON
PR2
The register file can be accessed either directly, or indi-
rectly through the File Select Register FSR
(Section 2.5).
CCPR1L
CCPR1H
17h CCP1CON
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
ADRES
ADCON0
ADCON1
General
Purpose
Registers
32 Bytes
General
Purpose
Registers
96 Bytes
BFh
C0h
7Fh
FFh
Bank 0
Bank 1
Unimplemented data memory locations,
read as ’0’.
Note 1: Not a physical register.
DS41106A-page 10
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
2.2.2
SPECIAL FUNCTION REGISTERS
The special function registers can be classified into two
sets; core (CPU) and peripheral. Those registers asso-
ciated with the core functions are described in detail in
this section. Those related to the operation of the
peripheral features are described in detail in that
peripheral feature section.
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
give in Table 2-1.
TABLE 2-1
SPECIAL FUNCTION REGISTER SUMMARY
Value on: Value on all
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other resets
(4)
Bank 0
00h
INDF(1)
TMR0
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
rr01 1xxx rr0q quuu
xxxx xxxx uuuu uuuu
--xx xxxx --xu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx xxxx xuxu
01h
02h
PCL(1)
Program Counter's (PC) Least Significant Byte
03h
STATUS(1)
FSR(1)
IRP(4)
RP1(4)
RP0
TO
PD
Z
DC
C
04h
Indirect data memory address pointer
(7)
05h
PORTA(5,6)
—
—
—
PORTA Data Latch when written: PORTA pins when read
06h
PORTB(5,6) PORTB Data Latch when written: PORTB pins when read
(7)
(7)
(7)
(7)
(7)
(7)
DCCP
DT1CK
07h
DATACCP
—
—
—
—
—
—
—
08h-09h
0Ah
Unimplemented
—
—
—
PCLATH(1,2)
INTCON(1)
PIR1
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
0000 000x 0000 000u
0Bh
GIE
—
PEIE
ADIF
T0IE
—
INTE
—
RBIE
—
T0IF
INTF
RBIF
0Ch
0Dh
0Eh
CCP1IF
TMR2IF
TMR1IF -0-- 0000 -0-- 0000
—
Unimplemented
—
—
TMR1L
TMR1H
T1CON
TMR2
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0Fh
10h
—
—
T1CKPS1
T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON --00 0000 --uu uuuu
11h
Timer2 module’s register
0000 0000 0000 0000
12h
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h-14h
15h
CCPR1L
CCPR1H
CCP1CON
—
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
16h
17h
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h-1Dh
1Eh
Unimplemented
—
—
ADRES
ADCON0
A/D Result Register
ADCS1 ADCS0
xxxx xxxx uuuu uuuu
0000 00-0 0000 00-0
1Fh
CHS2
CHS1
CHS0
GO/DONE
—
ADON
Legend: x= unknown, u= unchanged, q= value depends on condition, -= unimplemented, read as ’0’,
Shaded locations are unimplemented, read as ’0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved. Always maintain these bits clear.
5: On any device reset, these pins are configured as inputs.
6: This is the value that will be in the port output latch.
7: Reserved bits; Do Not Use.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 11
PIC16C712/716
TABLE 2-1
SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Value on: Value on all
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other resets
(4)
Bank 1
80h
INDF(1)
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
1111 1111 1111 1111
OPTION_
REG
81h
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
82h
PCL(1)
STATUS(1)
FSR(1)
TRISA
TRISB
TRISCCP
—
Program Counter’s (PC) Least Significant Byte
IRP(4) RP1(4)
RP0 TO
0000 0000 0000 0000
rr01 1xxx rr0q quuu
xxxx xxxx uuuu uuuu
--x1 1111 --x1 1111
1111 1111 1111 1111
xxxx x1x1 xxxx x1x1
83h
PD
Z
DC
C
84h
Indirect data memory address pointer
(7)
85h
—
—
—
PORTA Data Direction Register
86h
PORTB Data Direction Register
(7)
(7)
(7)
(7)
(7)
(7)
—
—
—
—
—
TT1CK
TCCP
87h
—
88h-89h
8Ah
Unimplemented
—
—
—
PCLATH(1,2)
INTCON(1)
PIE1
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
0000 000x 0000 000u
8Bh
GIE
—
PEIE
ADIE
T0IE
—
INTE
—
RBIE
—
T0IF
INTF
RBIF
8Ch
CCP1IE
TMR2IE
TMR1IE -0-- -000 -0-- -000
8Dh
—
Unimplemented
—
—
—
8Eh
PCON
—
—
—
—
—
—
POR
BOR
---- --qq ---- --uu
8Fh-91h
92h
Unimplemented
—
—
PR2
Timer2 Period Register
Unimplemented
1111 1111 1111 1111
93h-9Eh
9Fh
—
—
—
ADCON1
—
—
—
—
—
PCFG2
PCFG1
PCFG0
---- -000 ---- -000
Legend: x= unknown, u= unchanged, q= value depends on condition, -= unimplemented, read as ’0’,
Shaded locations are unimplemented, read as ’0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved. Always maintain these bits clear.
5: On any device reset, these pins are configured as inputs.
6: This is the value that will be in the port output latch.
7: Reserved bits; Do Not Use.
DS41106A-page 12
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
2.2.2.1
STATUS REGISTER
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions, not affecting any status bits, see the
"Instruction Set Summary."
The STATUS register, shown in Figure 2-4, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: These devices do not use bits IRP and
RP1 (STATUS<7:6>). Maintain these bits
clear to ensure upward compatibility with
future products.
Note 2: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUSwill clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
FIGURE 2-4: STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0
IRP
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
R = Readable bit
W = Writable bit
bit7
bit0
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh) - not implemented, maintain clear
0 = Bank 0, 1 (00h - FFh) - not implemented, maintain clear
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
01= Bank 1 (80h - FFh)
00= Bank 0 (00h - 7Fh)
Each bank is 128 bytes
Note: RP1 = not implemented, maintain clear
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
TO: Time-out bit
1 = After power-up, CLRWDTinstruction, or SLEEPinstruction
0 = A WDT time-out occurred
PD: Power-down bit
1 = After power-up or by the CLRWDTinstruction
0 = By execution of the SLEEPinstruction
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions) (for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 13
PIC16C712/716
2.2.2.2
OPTION_REG REGISTER
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
The OPTION_REG register is a readable and writable
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
able register known also as the prescaler), the External
INT Interrupt, TMR0 and the weak pull-ups on PORTB.
FIGURE 2-5: OPTION_REG REGISTER (ADDRESS 81h)
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
R
= Readable bit
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6:
bit 5:
bit 4:
bit 3:
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
DS41106A-page 14
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
2.2.2.3
INTCON REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The INTCON Register is a readable and writable regis-
ter which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
FIGURE 2-6: INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
R
= Readable bit
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
IINTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 15
PIC16C712/716
2.2.2.4
PIE1 REGISTER
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
This register contains the individual enable bits for the
peripheral interrupts.
FIGURE 2-7: PIE1 REGISTER (ADDRESS 8Ch)
U-0
R/W-0
ADIE
U-0
U-0
R/W-0
R/W-0
R/W-0
TMR2IE TMR1IE
bit0
R/W-0
—
—
—
—
CCP1IE
R
= Readable bit
W = Writable bit
bit7
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
Unimplemented: Read as ‘0’
bit 6:
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5-3: Unimplemented: Read as ‘0’
bit 2:
bit 1:
bit 0:
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
DS41106A-page 16
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
2.2.2.5
PIR1 REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
This register contains the individual flag bits for the
peripheral interrupts.
FIGURE 2-8: PIR1 REGISTER (ADDRESS 0Ch)
U-0
R/W-0
ADIF
U-0
U-0
R/W-0
R/W-0
R/W-0
TMR2IF TMR1IF
bit0
R/W-0
—
—
—
—
CCP1IF
R
= Readable bit
W = Writable bit
bit7
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
Unimplemented: Read as ‘0’
ADIF: A/D Converter Interrupt Flag bit
bit 6:
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5-3: Unimplemented: Read as ‘0’
bit 2:
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1:
bit 0:
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 17
PIC16C712/716
2.2.2.6
PCON REGISTER
Note: If the BODEN configuration bit is set, BOR
is ’1’ on Power-on Reset. If the BODEN
configuration bit is clear, BOR is unknown
on Power-on Reset.
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR) to an external MCLR Reset or WDT Reset.
These devices contain an additional bit to differentiate
a Brown-out Reset condition from a Power-on Reset
condition.
The BOR status bit is a "don't care" and is
not necessarily predictable if the brown-out
circuit is disabled (the BODEN configura-
tion bit is clear). BOR must then be set by
the user and checked on subsequent
resets to see if it is clear, indicating a
brown-out has occurred.
FIGURE 2-9: PCON REGISTER (ADDRESS 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-q
—
—
—
—
—
—
POR
BOR
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
bit7
bit0
- n = Value at POR reset
bit 7-2: Unimplemented: Read as ’0’
bit 1:
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
DS41106A-page 18
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
2.3
PCL and PCLATH
2.4
Program Memory Paging
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<12:8>
bits and is not directly readable or writable. All updates
to the PCH register go through the PCLATH register.
The CALL and GOTO instructions provide 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALLor GOTOinstruction,
the upper bit of the address is provided by
PCLATH<3>. When doing a CALLor GOTOinstruction,
the user must ensure that the page select bit is pro-
grammed so that the desired program memory page is
addressed. If a return from a CALLinstruction (or inter-
rupt) is executed, the entire 13-bit PC is pushed onto
the stack. Therefore, manipulation of the PCLATH<3>
bit is not required for the return instructions (which
POPs the address from the stack).
2.3.1
STACK
The stack allows a combination of up to 8 program calls
and interrupts to occur. The stack contains the return
address from this branch in program execution.
Midrange devices have an 8 level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not modified when the stack is PUSHed or
POPed.
After the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 19
PIC16C712/716
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
2.5
Indirect Addressing, INDF and FSR
Registers
The INDF register is not a physical register. Address-
ing INDF actually addresses the register whose
address is contained in the FSR register (FSR is a
pointer). This is indirect addressing.
EXAMPLE 2-2: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
movlw 0x20 ;initialize pointer
movwf FSR
clrf
incf
;
to RAM
INDF ;clear INDF register
FSR ;inc pointer
EXAMPLE 2-1: INDIRECT ADDRESSING
• Register file 05 contains the value 10h
• Register file 06 contains the value 0Ah
• Load the value 05 into the FSR register
• A read of the INDF register will return the value of
10h
NEXT
btfss FSR,4 ;all done?
goto
:
NEXT ;NO, clear next
;YES, continue
CONTINUE
• Increment the value of the FSR register by one
(FSR = 06)
• A read of the INDR register now will return the
value of 0Ah.
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-10. However, IRP is not used in the
PIC16C712/716.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
FIGURE 2-10: DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
from opcode
7
RP1:RP0
6
0
0
IRP
FSR register
(2)
(2)
bank select
location select
bank select
location select
00
01
80h
10
100h
11
00h
180h
(3)
(3)
Data
Memory(1)
7Fh
FFh
17Fh
1FFh
Bank 0
Bank 1 Bank 2
Bank 3
Note 1: For register file map detail see Figure 2-3.
2: Maintain clear for upward compatibility with future products.
3: Not implemented.
DS41106A-page 20
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other RA port pins have TTL input levels and full
CMOS output drivers.
3.0
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
PORTA pins, RA3:0, are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
Additional information on I/O ports may be found in the
PICmicro™
(DS33023).
Mid-Range
Reference
Manual,
3.1
PORTA and the TRISA Register
Note: On a Power-on Reset, these pins are con-
figured as analog inputs and read as '0'.
PORTA is a 5-bit wide bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin
an input, (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISA bit (=0) will
make the corresponding PORTA pin an output, (i.e., put
the contents of the output latch on the selected pin).
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 3-1: INITIALIZING PORTA
BCF
CLRF
STATUS, RP0
;
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore a write to a port implies that the port pins are
read, the value is modified, and then written to the port
data latch.
PORTA
; Initialize PORTA by
; clearing output
; data latches
BSF
STATUS, RP0 ; Select Bank 1
MOVLW 0xEF
; Value used to
; initialize data
; direction
MOVWF TRISA
; Set RA<3:0> as inputs
; RA<4> as outputs
BCF
STATUS, RP0 ; Return to Bank 0
FIGURE 3-1: BLOCK DIAGRAM OF RA3:RA0
DATA
BUS
D
Q
Q
VDD
VDD
WR
PORT
CK
P
N
Data Latch
I/O pin
D
Q
WR
TRIS
VSS
VSS
Q
CK
Analog
input
mode
TRIS Latch
TTL
Input
Buffer
RD TRIS
Q
D
EN
RD PORT
To A/D Converter
1998 Microchip Technology Inc.
Preliminary
DS41106A-page 21
PIC16C712/716
FIGURE 3-2: BLOCK DIAGRAM OF RA4/T0CKI PIN
DATA
D
Q
Q
BUS
WR
PORT
CK
I/O Pin
N
Data Latch
D
Q
VSS
VSS
WR
TRIS
Schmitt
Trigger
Input
Q
CK
TRIS Latch
Buffer
RD TRIS
Q
D
EN
RD PORT
TMR0 Clock Input
TABLE 3-1
Name
PORTA FUNCTIONS
Bit#
Buffer Function
RA0/AN0
bit0
bit1
bit2
bit3
TTL
TTL
TTL
TTL
Input/output or analog input
Input/output or analog input
Input/output or analog input
Input/output or analog input or VREF
RA1/AN1
RA2/AN2
RA3/AN3/VREF
Input/output or external clock input for Timer0
Output is open drain type
RA4/T0CKI
bit4
ST
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 3-2
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
POR,
BOR
Value on all
other resets
Address Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Bit 1
Bit 0
(1)
05h
85h
9Fh
PORTA
TRISA
—
—
—
—
—
—
—
—
RA4 RA3
RA2
RA1
RA0
--xx xxxx
--11 1111
--xu uuuu
--11 1111
---- -000
(1)
PORTA Data Direction Register
ADCON1
—
—
—
PCFG2 PCFG1 PCFG0 ---- -000
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by
PORTA.
Note 1: Reserved bits; Do Not Use.
DS41106A-page 22
Preliminary
1998 Microchip Technology Inc.
PIC16C712/716
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
3.2
PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin
an input, (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output, (i.e.,
put the contents of the output latch on the selected pin).
EXAMPLE 3-1: INITIALIZING PORTB
BCF
STATUS, RP0
;
CLRF
PORTB
; Initialize PORTB by
; clearing output
; data latches
BSF
STATUS, RP0 ; Select Bank 1
MOVLW 0xCF
; Value used to
; initialize data
; direction
MOVWF TRISB
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
FIGURE 3-3: BLOCK DIAGRAM OF RB0 PIN
VDD
RBPU(1)
VDD
weak
P
pull-up
Data Latch
DATA BUS
D
Q
I/O
pin
WR PORT
CK
TRIS Latch
D
Q
VSS
TTL
Input
WR TRIS
CK
Buffer
RD TRIS
Q
D
EN
RD PORT
RB0/INT
Schmitt Trigger
Buffer
RD PORT
Note 1:
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 23
PIC16C712/716
PORTB pins RB3:RB1 are multiplexed with several
peripheral functions (Table 3-3). PORTB pins RB3:RB0
have Schmitt Trigger input buffers.
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTB pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISB as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
rupt in the following manner:
a) Any read or write of PORTB will end the mis-
match condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e. any RB7:RB4 pin con-
figured as an output is excluded from the interrupt on
change comparison). The input pins, RB7:RB4, are
compared with the old value latched on the last read of
FIGURE 3-4: BLOCK DIAGRAM OF RB1/T1OSO/T1CKI PIN
RBPU(1)
T1OSCEN
T1CS
DATA BUS
RD
DATACCP
DATACCP<0>
VDD
weak
D
Q
WR
VDD
P
Q
CK
pull-up
DATACCP
TRISCCP<0>
1
0
D
Q
Q
RB1/T1OSO/T1CKI
WR
TRISCCP
CK
PORTB<1>
1
0
D
Q
Q
VSS
WR
PORTB
CK
TRISB<1>
D
Q
WR TRISB
T1OSCEN
TMR1CS
CK
Q
1
0
TTL Buffer
RD PORTB
T1CLKIN
ST
Buffer
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
DS41106A-page 24
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
FIGURE 3-5: BLOCK DIAGRAM OF RB2/T1OSI PIN
VDD
RBPU(1)
weak
pull-up
P
T1OSCEN
VDD
PORTB<2>
DATA BUS
D
Q
Q
RB1/T1OSO/T1CKI
WR PORTB
CK
VSS
TRISB<2>
D
Q
WR TRISB
T1OSCEN
CK
Q
RD PORTB
TTL Buffer
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
FIGURE 3-6: BLOCK DIAGRAM OF RB3/CCP1 PIN
RBPU(1)
CCPON
CCPIN
1
DATA BUS
RD
DATACCP
0
CCPON
DATACCP<2>
1
0
D
Q
Q
VDD
weak
WR
DATACCP
CK
P
TRISCCP<2>
pull-up
VDD
D
Q
WR
TRISCCP
1
0
Q
CK
RB3/CCP1
CCP
Output
Mode
PORTB<3>
1
0
D
Q
Q
VSS
WR
PORTB
CK
TRISB<3>
D
Q
WR
TRISB
Q
CK
CCPON
1
0
RD PORTB
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s)
TTL Buffer
and clear the RBPU bit (OPTION_REG<7>).
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 25
PIC16C712/716
FIGURE 3-7: BLOCK DIAGRAM OF RB7:RB4 PINS
VDD
weak
RBPU(1)
VDD
P
pull-up
Data Latch
DATA BUS
D
Q
I/O
pin
WR PORT
CK
TRIS Latch
D
Q
VSS
WR TRIS
TTL
Buffer
CK
ST
Buffer
RD TRIS
Latch
Q
Q
D
EN
Q1
RD PORT
Set RBIF
D
From other
RB7:RB4 pins
RD PORT
Q3
EN
RB7:RB6 in serial programming mode
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
TABLE 3-3
PORTB FUNCTIONS
Name
Bit#
Buffer
Function
RB0/INT
bit0
TTL/ST(1)
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
TTL/ST(1)
RB1/T1OS0/
T1CKI
bit1
Input/output pin or Timer 1 oscillator output, or Timer 1 clock input. Internal
software programmable weak pull-up. See Timer1 section for detailed
operation.
TTL/ST(1)
TTL/ST(1)
RB2/T1OSI
RB3/CCP1
bit2
bit3
Input/output pin or Timer 1 oscillator input. Internal software programmable
weak pull-up. See Timer1 section for detailed operation.
Input/output pin or Capture 1 input, or Compare 1 output, or PWM1 output.
Internal software programmable weak pull-up. See CCP1 section for
detailed operation.
RB4
RB5
RB6
RB7
bit4
bit5
bit6
bit7
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
TTL/ST(2)
TTL/ST(2)
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming clock.
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt or peripheral input.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
DS41106A-page 26
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
TABLE 3-4
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on:
POR,
BOR
Value on all
other resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
06h
86h
81h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
PS1
RB0
PS0
xxxx xxxx
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
TRISB
PORTB Data Direction Register
OPTION_REG RBPU
INTEDG
T0CS T0SE PSA
PS2
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 27
PIC16C712/716
NOTES:
DS41106A-page 28
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
Additional information on external clock requirements
is available in the PICmicro™ Mid-Range Reference
Manual, (DS33023).
4.0
TIMER0 MODULE
The Timer0 module timer/counter has the following fea-
tures:
4.2
Prescaler
• 8-bit timer/counter
• Readable and writable
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer, respectively (Figure 4-2). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available, which is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer and
vice-versa.
• Internal or external clock select
• Edge select for external clock
• 8-bit software programmable prescaler
• Interrupt on overflow from FFh to 00h
Figure 4-1 is a simplified block diagram of the Timer0
module.
Additional information on timer modules is available in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
The prescaler is not readable or writable.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
4.1
Timer0 Operation
Timer0 can operate as a timer or as a counter.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In timer mode, the Timer0 mod-
ule will increment every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
Setting bit PSA will assign the prescaler to the Watch-
dog Timer (WDT). When the prescaler is assigned to
the WDT, prescale values of 1:1, 1:2, ..., 1:128 are
selectable.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In counter mode, Timer0 will
increment on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed below.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF
1,x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the WDT.
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
FIGURE 4-1: TIMER0 BLOCK DIAGRAM
Data Bus
FOSC/4
0
1
PSout
8
1
0
Sync with
Internal
clocks
TMR0
Programmable
RA4/T0CKI
pin
PSout
(2)
Prescaler
(1)
(2 cycle delay)
T0SE
3
Set interrupt
flag bit T0IF
on overflow
(1)
(1)
PS2, PS1, PS0
PSA
(1)
T0CS
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 29
PIC16C712/716
4.2.1
SWITCHING PRESCALER ASSIGNMENT
4.3
Timer0 Interrupt
The prescaler assignment is fully under software con-
trol, i.e., it can be changed “on the fly” during program
execution.
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt ser-
vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP.
Note: To avoid an unintended device RESET, a
specific instruction sequence (shown in
the PICmicro™ Mid-Range Reference
Manual, DS33023) must be executed
when changing the prescaler assignment
from Timer0 to the WDT. This sequence
must be followed even if the WDT is dis-
abled.
FIGURE 4-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
8
CLKOUT (=Fosc/4)
M
U
X
1
0
0
1
M
U
X
RA4/T0CKI
pin
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
Set flag bit T0IF
on Overflow
PSA
0
1
8-bit Prescaler
M
U
X
Watchdog
Timer
8
8 - to - 1MUX
PS2:PS0
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
TABLE 4-1
REGISTERS ASSOCIATED WITH TIMER0
Value on:
POR,
BOR
Value on all
other resets
Address
Name
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h
TMR0
Timer0 module’s register
GIE PEIE T0IE INTE
xxxx xxxx uuuu uuuu
RBIF 0000 000x 0000 000u
0Bh,8Bh
81h
INTCON
RBIE
PSA
T0IF
PS2
INTF
PS1
OPTION_REG RBPU INTEDG T0CS T0SE
PS0
1111 1111 1111 1111
--11 1111 --11 1111
(1)
85h
TRISA
—
—
—
Bit 4 PORTA Data Direction Register
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by Timer0.
Note 1: Reserved bit; Do Not Use.
DS41106A-page 30
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
5.1
Timer1 Operation
5.0
TIMER1 MODULE
The Timer1 module timer/counter has the following fea-
tures:
Timer1 can operate in one of these modes:
• As a timer
• 16-bit timer/counter
(Two 8-bit registers; TMR1H and TMR1L)
• As a synchronous counter
• As an asynchronous counter
• Readable and writable (Both registers)
• Internal or external clock select
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
• Interrupt on overflow from FFFFh to 0000h
• Reset from CCP module trigger
In timer mode, Timer1 increments every instruction
cycle. In counter mode, it increments on every rising
edge of the external clock input.
Timer1 has a control register, shown in Figure 5-1.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RB2/T1OSI and RB1/T1OSO/T1CKI pins
become inputs. That is, the TRISB<2:1> value is
ignored.
Figure 5-2 is a simplified block diagram of the Timer1
module.
Additional information on timer modules is available in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
Timer1 also has an internal “reset input”. This reset can
be generated by the CCP module (Section 7.0).
FIGURE 5-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit0
bit7
- n = Value at POR reset
bit 7-6: Unimplemented: Read as ’0’
bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3:
bit 2:
T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off
Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1:
bit 0:
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RB1/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 31
PIC16C712/716
FIGURE 5-2: TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow
Synchronized
clock input
0
TMR1
TMR1L
TMR1H
T1OSC
1
TMR1ON
on/off
T1SYNC
RB1/T1OSO/T1CKI
RB2/T1OSI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
FOSC/4
Internal
Clock
0
(1)
Oscillator
2
SLEEP input
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
5.2
Timer1 Module and PORTB Operation
When Timer1 is configured as timer running from the
main oscillator, PORTB<2:1> operate as normal I/O
lines. When Timer1 is configured to function as a
counter however, the clock source selection may affect
the operation of PORTB<2:1>. Multiplexing details of
the Timer1 clock selection on PORTB are shown in Fig-
ure 3-4 and Figure 3-5.
The clock source for Timer1 in the counter mode can
be from one of the following:
1. External
circuit
connected
to
the
RB1/T1OSO/T1CKI pin
2. Firmware controlled DATACCP<0> bit, DT1CKI
3. Timer1 oscillator
Table 5-1 shows the details of Timer1 mode selections,
control bit settings, TMR1 and PORTB operations.
DS41106A-page 32
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
TABLE 5-1
TMR1
TMR1 MODULE AND PORTB OPERATION
Module Clock Source
Mode
Control Bits
TMR1 Module Operation
PORTB<2:1> Operation
Off
N/A
T1CON = --xx 0x00 Off
PORTB<2:1> function as normal
I/O
Timer
Fosc/4
T1CON = --xx 0x01 TMR1 module uses the main
oscillator as clock source.
PORTB<2:1> function as normal
I/O
TMR1ON can turn on or turn off
Timer1.
External circuit T1CON = --xx 0x11
TMR1 module uses the external PORTB<2> functions as normal
TR1SCCP = ---- -x-1 signal on the
RB1/T1OSO/T1CKI pin as a
I/O. PORTB<1> always reads 0
when configured as input . If
clock source. TMR1ON can turn PORTB<1> is configured as out-
on or turn off Timer1. DT1CK
can read the signal on the
RB1/T1OSO/T1CKI pin.
put, reading PORTB<1> will read
the data latch. Writing to
PORTB<1> will always store the
result in the data latch, but not to
the RB1/T1OSO/T1CKI pin. If
the TMR1CS bit is cleared
(TMR1 reverts to the timer
mode), then pin PORTB<1> will
be driven with the value in the
data latch.
Firmware
T1CON = --xx 0x11
DATACCP<0> bit drives
TR1SCCP = ---- -x-0 RB1/T1OSO/T1CKI and pro-
duces the TMR1 clock source.
TMR1ON can turn on or turn off
Timer1. The DATACCP<0> bit,
DT1CK, can read and write to
the RB1/T1OSO/T1CKI pin.
Counter
Timer1 oscillator T1CON = --xx 1x11 RB1/T1OSO/T1CKI and
PORTB<2:1> always read 0
RB2/T1OSI are configured as a when configured as inputs. If
2 pin crystal oscillator.
PORTB<2:1> are configured as
outputs, reading PORTB<2:1>
will read the data latches. Writing
to PORTB<2:1> will always store
the result in the data latches, but
RB1/T1OSI/T1CKI is the clock
input for TMR1. TMR1ON can
turn on or turn off Timer1.
DATACCP<1> bit, DT1CK,
always reads 0 as input and can not to the RB2/T1OSI and
not write to the
RB1/T1OSO/T1CK1 pin.
RB1/T1OSO/T1CKI pins. If the
TMR1CS and T1OSCEN bits are
cleared (TMR1 reverts to the
timer mode and TMR1 oscillator
is disabled), then pin
PORTB<2:1> will be driven with
the value in the data latches.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 33
PIC16C712/716
5.3
Timer1 Oscillator
5.4
Timer1 Interrupt
A crystal oscillator circuit is built in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 5-2 shows the capacitor
selection for the Timer1 oscillator.
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit TMR1IF (PIR1<0>).
This interrupt can be enabled/disabled by setting/clear-
ing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
5.5
Resetting Timer1 using a CCP Trigger
Output
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
If the CCP module is configured in compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
TABLE 5-2
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
Osc Type
Freq
C1
C2
Note: The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
LP
32 kHz
100 kHz
200 kHz
33 pF
15 pF
15 pF
33 pF
15 pF
15 pF
Timer1 must be configured for either timer or synchro-
nized counter mode to take advantage of this feature. If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
These values are for design guidance only.
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1, the write will take prece-
dence.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropri-
ate values of external components.
In this mode of operation, the CCPR1H:CCPR1L regis-
ters pair effectively becomes the period register for
Timer1.
TABLE 5-3
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
POR,
BOR
Value on
all other
resets
Address Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 000x 0000 000u
-0-- -000 -0-- -000
-0-- -000 -0-- -000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --uu uuuu
---- -x-x ---- -u-u
---- -1-1 ---- -1-1
0Bh,8Bh INTCON
GIE PEIE
T0IE
—
INTE
—
RBIE
—
T0IF
INTF
RBIF
0Ch
8Ch
0Eh
0Fh
10h
07h
87h
PIR1
—
—
ADIF
ADIE
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
PIE1
—
—
—
TMR1L
TMR1H
T1CON
DATACCP
TRISCCP
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
—
—
—
—
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
—
—
—
—
—
—
DCCP
TCCP
—
—
DT1CK
TT1CK
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
DS41106A-page 34
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
NOTES:
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 35
PIC16C712/716
Timer2 has a control register, shown in Figure 6-1.
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
6.0
TIMER2 MODULE
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
Figure 6-2 is a simplified block diagram of the Timer2
module.
• 8-bit period register (PR2)
• Readable and writable (Both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match of PR2
Additional information on timer modules is available in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
FIGURE 6-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit0
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
bit7
- n = Value at POR reset
bit 7:
Unimplemented: Read as '0'
bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
0010= 1:3 Postscale
0011= 1:4 Postscale
0100= 1:5 Postscale
0101= 1:6 Postscale
0110= 1:7 Postscale
0111= 1:8 Postscale
1000= 1:9 Postscale
1001= 1:10 Postscale
1010= 1:11 Postscale
1011= 1:12 Postscale
1100= 1:13 Postscale
1101= 1:14 Postscale
1110= 1:15 Postscale
1111= 1:16 Postscale
bit 2:
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
FIGURE 6-2: TIMER2 BLOCK DIAGRAM
Sets flag
TMR2
bit TMR2IF
output
Reset
Prescaler
1:1, 1:4, 1:16
TMR2 reg
FOSC/4
Postscaler
2
Comparator
1:1 to 1:16
EQ
4
PR2 reg
DS41106A-page 36
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
6.1
Timer2 Operation
6.2
Timer2 Interrupt
Timer2 can be used as the PWM time-base for PWM
mode of the CCP module.
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is ini-
tialized to FFh upon reset.
The TMR2 register is readable and writable, and is
cleared on any device reset.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4
or
1:16,
selected
by
control
bits
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device reset (Power-on Reset, MCLR reset,
Watchdog Timer reset, or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
TABLE 6-1
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on
POR,
BOR
Value on
all other
resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 000x 0000 000u
-00- -000 0000 -000
-0-- -000 0000 -000
0Bh,8Bh
0Ch
INTCON
PIR1
GIE
PEIE
T0IE
INTE
RBIE
—
T0IF
INTF
RBIF
—
ADIF
—
—
CCP1IF
TMR2IF
TMR1IF
8Ch
PIE1
—
ADIE
—
—
CCP1IE
TMR2IE
TMR1IE
—
0000 0000 0000 0000
-000 0000 -000 0000
1111 1111 1111 1111
11h
TMR2
T2CON
PR2
Timer2 module’s register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
12h
—
92h
Legend:
x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 37
PIC16C712/716
NOTES:
DS41106A-page 38
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
Additional information on the CCP module is available
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
7.0
CAPTURE/COMPARE/PWM
(CCP) MODULE(S)
Each CCP (Capture/Compare/PWM) module contains
a 16-bit register, which can operate as a 16-bit capture
register, as a 16-bit compare register or as a PWM
master/slave Duty Cycle register. Table 7-1 shows the
timer resources of the CCP module modes.
TABLE 7-1
CCP MODE - TIMER
RESOURCE
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
Capture/Compare/PWM Register 1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
FIGURE 7-1: CCP1CON REGISTER (ADDRESS 17h)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit0
R = Readable bit
W = Writable bit
bit7
U = Unimplemented bit, read
as ‘0’
- n =Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5-4: DC1B1:DC1B0: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
bit 3-0: CCP1M3:CCP1M0: CCP1 Mode Select bits
0000= Capture/Compare/PWM off (resets CCP1 module)
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, set output on match (CCP1IF bit is set)
1001= Compare mode, clear output on match (CCP1IF bit is set)
1010= Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected)
1011= Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 and starts an A/D
conversion (if A/D module is enabled))
11xx= PWM mode
FIGURE 7-2: TRISCCP Register (ADDRESS 87h)
R/W-1
—
R/W-1
—
R/W-1
—
R/W-1
—
R/W-1
—
R/W-1
TCCP
R/W-1
—
R/W-1
TT1CK
R = Readable bit
W = Writable bit
bit7
bit0
U = Unimplemented bit, read
as ‘0’
- n =Value at POR reset
bit 7-3:
bit 2:
Reserved bits; Do Not Use
TCCP - Tri state control bit for CCP
0 = Output pin driven
1 = Output pin tristated
bit 1:
bit 0:
Reserved bit; Do Not Use
TT1CK - Tri state control bit for T1CKI pin
0 = T1CKI pin is an output
1 = T1CKI pin is an input
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 39
PIC16C712/716
7.1.4
CCP PRESCALER
7.1
Capture Mode
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in capture mode,
the prescaler counter is cleared. This means that any
reset will clear the prescaler counter.
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RB3/CCP1. An event is defined as:
• every falling edge
• every rising edge
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 7-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
• every 4th rising edge
• every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
EXAMPLE 7-1: CHANGING BETWEEN
CAPTURE PRESCALERS
FIGURE 7-3: CAPTURE MODE OPERATION
BLOCK DIAGRAM
CLRF
CCP1CON
;Turn CCP module off
MOVLW NEW_CAPT_PS ;Load the W reg with
; the new prescaler
Set flag bit CCP1IF
; mode value and CCP ON
;Load CCP1CON with this
; value
(PIR1<2>)
Prescaler
÷ 1, 4, 16
MOVWF CCP1CON
RB3/CCP1
Pin
CCPR1H
CCPR1L
TMR1L
Capture
Enable
and
edge detect
TMR1H
CCP1CON<3:0>
Q’s
7.1.1
CCP PIN CONFIGURATION
In Capture mode, the CCP output must be disabled by
setting the TRISCCP<2> bit.
Note: If the RB3/CCP1 is configured as an output
by clearing the TRISCCP<2> bit, a write to
the DCCP bit can cause a capture condi-
tion.
7.1.2
TIMER1 MODE SELECTION
Timer1 must be running in timer mode or synchronized
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode, the capture
operation may not work.
7.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
DS41106A-page 40
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
7.2.1
CCP PIN CONFIGURATION
7.2
Compare Mode
The user must configure the RB3/CCP1 pin as the CCP
output by clearing the TRISCCP<2> bit.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RB3/CCP1 pin is
either:
Note: Clearing the CCP1CON register will force
the RB3/CCP1 compare output latch to the
default low level. This is neither the PORTB
I/O data latch nor the DATACCP latch.
• driven High
• driven Low
• remains Unchanged
7.2.2
TIMER1 MODE SELECTION
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
FIGURE 7-4: COMPARE MODE
OPERATION BLOCK
DIAGRAM
7.2.3
SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>)
which starts an A/D conversion
7.2.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
Special Event Trigger
Set flag bit CCP1IF
(PIR1<2>)
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
CCPR1H CCPR1L
Q
S
R
Output
Logic
Comparator
match
RB3/CCP1
Pin
The special event trigger output of CCP1 also starts an
A/D conversion (if the A/D module is enabled).
TRISCCP<2>
Output Enable
TMR1H TMR1L
CCP1CON<3:0>
Mode Select
Note: The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
TABLE 7-2
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Value on
POR,
BOR
Value on
all other
resets
Address Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
07h
DATACCP
—
GIE
—
—
—
T0IE
—
—
INTE
—
—
RBIE
—
DCCP
T0IF
—
TT1CK xxxx xxxx xxxx xuxu
RBIF 0000 000x 0000 000u
0Bh,8Bh
0Ch
0Eh
0Fh
INTCON
PIR1
PEIE
ADIF
INTF
CCP1IF TMR2IF TMR1IF -0-- -000 -0-- -000
TMR1L
TMR1H
T1CON
CCPR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
10h
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h
Capture/Compare/PWM register1 (LSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
16h
CCPR1H Capture/Compare/PWM register1 (MSB)
17h
CCP1CON
TRISCCP
PIE1
—
—
—
—
—
DC1B1
—
DC1B0
—
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
87h
—
—
TCCP
—
TT1CK xxxx x1x1 xxxx x1x1
8Ch
ADIE
—
—
CCP1IE TMR2IE TMR1IE -0-- -000 -0-- -000
Legend: x= unknown, u= unchanged, -= unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 41
PIC16C712/716
7.3.1
PWM PERIOD
7.3
PWM Mode
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTB data latch,
the TRISCCP<2> bit must be cleared to make the
CCP1 pin an output.
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is neither the PORTB I/O
data latch nor the DATACCP latch.
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
Figure 7-5 shows a simplified block diagram of the CCP
module in PWM mode.
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 7.3.3.
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
FIGURE 7-5: SIMPLIFIED PWM BLOCK
DIAGRAM
Note: The Timer2 postscaler (see Section 6.0) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different fre-
quency than the PWM output.
CCP1CON<5:4>
Duty cycle registers
CCPR1L
7.3.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
CCPR1H (Slave)
Q
R
S
Comparator
TMR2
RB3/CCP1
(Note 1)
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
Tosc • (TMR2 prescale value)
TRISCCP<2>
Comparator
Clear Timer,
CCP1 pin and
latch D.C.
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
PR2
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
A PWM output (Figure 7-6) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
FIGURE 7-6: PWM OUTPUT
Maximum PWM resolution (bits) for a given PWM
frequency:
Period = PR2+1
FOSC
FPWM
log
(
)
=
bits
Duty Cycle
log(2)
TMR2 = PR2
Note: If the PWM duty cycle value is longer than
the PWM period the CCP1 pin will not be
cleared.
TMR2 = Duty Cycle (CCPR1H)
TMR2 = PR2
For an example PWM period and duty cycle calcula-
tion, see the PICmicro™ Mid-Range Reference
Manual, (DS33023).
DS41106A-page 42
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
7.3.3
SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 regis-
ter.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISCCP<2> bit.
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
TABLE 7-3
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
0xFF
10
0xFF
10
0x17
5.5
Maximum Resolution (bits)
TABLE 7-4
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
all other
resets
—
—
—
—
—
xxxx xxxx xxxx xuxu
0000 000x 0000 000u
07h
DATACCP
INTCON
PIR1
DCCP
T0IF
—
DT1CK
0Bh,8Bh
0Ch
11h
GIE
PEIE
T0IE
INTE
RBIE
INTF
RBIF
—
ADIF
—
—
—
CCP1IF TMR2IF TMR1IF -0-- -000 -0-- -000
TMR2
Timer2 module’s register
0000 0000 0000 0000
12h
T2CON
CCPR1L
CCPR1H
CCP1CON
TRISCCP
PIE1
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h
Capture/Compare/PWM register1 (LSB)
Capture/Compare/PWM register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
16h
17h
—
—
—
—
—
DC1B1
—
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
87h
—
—
—
—
TCCP
—
TT1CK xxxx x1x1 xxxx x1x1
8Ch
92h
ADIE
—
CCP1IE TMR2IE TMR1IE -0-- -000 -0-- -000
PR2
Timer2 module’s period register
1111 1111 1111 1111
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 43
PIC16C712/716
7.4
CCP1 Module and PORTB Operation
When the CCP module is disabled, PORTB<3> oper-
ates as a normal I/O pin. When the CCP module is
enabled, PORTB<3> operation is affected. Multiplex-
ing details of the CCP1 module are shown on
PORTB<3>, refer to Figure 3.6.
.
Table 7-5 below shows the effects of the CCP module
operation on PORTB<3>
TABLE 7-5
CCP1 MODULE AND PORTB OPERATION
CCP1
Module
Mode
Control Bits
CCP1 Module Operation
PORTB<3> Operation
Off
CCP1CON = --xx 0000 Off
PORTB<3> functions as normal I/O.
Capture
CCP1CON = --xx 01xx The CCP1 module will capture an event PORTB<3> always reads 0 when config-
TR1SCCP = ---- -1-x on the RB3/CCP1 pin which is driven by ured as input. If PORTB<3> is config-
an external circuit. The DCCP bit can
read the signal on the RB3/CCP1 pin.
ured as output, reading PORTB<3> will
read the data latch. Writing to
PORTB<3> will always store the result in
the data latch, but it does not drive the
RB3/CCP1 pin.
CCP1CON = --xx 01xx The CCP1 module will capture an event
TR1SCCP = ---- -0-x
on the RB3/CCP1 pin which is driven by
the DCCP bit. The DCCP bit can read
the signal on the RB3/CCP1 pin.
Compare
PWM
CCP1CON = --xx 10xx The CCP1 module produces an output
TR1SCCP = ---- -0-x
on the RB3/CCP1 pin when a compare
event occurs. The DCCP bit can read
the signal on the RB3/CCP1 pin.
CCP1CON = --xx 11xx The CCP1 module produces the PWM
TR1SCCP = ---- -0-x
signal on the RB3/CCP1 pin. The DCCP
bit can read the signal on the RB3/CCP1
pin.
DS41106A-page 44
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
Additional information on the A/D module is available in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
8.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The analog-to-digital (A/D) converter module has four
inputs.
The A/D module has three registers. These registers
are:
The A/D allows conversion of an analog input signal to
a corresponding 8-bit digital number (refer to Applica-
tion Note AN546 for use of A/D Converter). The output
of the sample and hold is the input into the converter,
which generates the result via successive approxima-
tion. The analog reference voltage is software select-
able to either the device’s positive supply voltage (VDD)
or the voltage level on the RA3/AN3/VREF pin.
• A/D Result Register (ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off, and any
conversion is aborted.
The ADCON0 register, shown in Figure 8-1, controls
the operation of the A/D module. The ADCON1 regis-
ter, shown in Figure 8-2, configures the functions of the
port pins. The port pins can be configured as analog
inputs (RA3 can also be a voltage reference) or as dig-
ital I/O.
The A/D converter has a unique feature of being able to
operate while the device is in SLEEP mode. To operate
in sleep, the A/D conversion clock must be derived from
the A/D’s internal RC oscillator.
FIGURE 8-1: ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0 R/W-0 R/W-0
ADCS1 ADCS0 CHS2
bit7
R/W-0
CHS1
R/W-0
R/W-0
U-0
—
R/W-0
ADON
CHS0 GO/DONE
R =Readable bit
W = Writable bit
U =Unimplemented bit,
read as ‘0’
bit0
- n = Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00= FOSC/2
01= FOSC/8
10= FOSC/32
11= FRC (clock derived from the internal ADC RC oscillator)
bit 5-3: CHS2:CHS0: Analog Channel Select bits
000= channel 0, (RA0/AN0)
001= channel 1, (RA1/AN1)
010= channel 2, (RA2/AN2)
011= channel 3, (RA3/AN3)
1xx= reserved, do not use
bit 2:
GO/DONE: A/D Conversion Status bit
If ADON = 1
1= A/D conversion in progress (setting this bit starts the A/D conversion)
0= A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conver-
sion is complete)
bit 1:
bit 0:
Unimplemented: Read as '0'
ADON: A/D On bit
1= A/D converter module is operating
0= A/D converter module is shutoff and consumes no operating current
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 45
PIC16C712/716
FIGURE 8-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
PCFG2
PCFG1
PCFG0
R =Readable bit
W = Writable bit
U =Unimplemented bit,
read as ‘0’
bit7
bit0
- n = Value at POR
reset
bit 7-3: Unimplemented: Read as '0'
bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits
PCFG2:PCFG0
RA0
RA1
RA2
RA3
VREF
0x0
0x1
100
101
11x
A
A
A
A
VDD
RA3
VDD
RA3
VDD
A
A
A
D
A
A
A
D
A
D
D
D
VREF
A
VREF
D
A = Analog input
D = Digital I/O
DS41106A-page 46
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
The ADRES register contains the result of the A/D con-
version. When the A/D conversion is complete, the
result is loaded into the ADRES register, the GO/DONE
bit (ADCON0<2>) is cleared and the A/D interrupt flag
bit ADIF is set. The block diagram of the A/D module is
shown in Figure 8-3.
1. Configure the A/D module:
• Configure analog pins/voltage reference/
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
The value that is in the ADRES register is not modified
for a Power-on Reset. The ADRES register will contain
unknown data after a Power-on Reset.
• Set ADIE bit
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 8.1.
After this acquisition time has elapsed, the A/D conver-
sion can be started. The following steps should be fol-
lowed for doing an A/D conversion:
• Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result register (ADRES), clear bit
ADIF if required.
7. For the next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
FIGURE 8-3: A/D BLOCK DIAGRAM
CHS2:CHS0
VIN
011
(Input voltage)
RA3/AN3/VREF
010
RA2/AN2
A/D
Converter
001
RA1/AN1
000
VDD
RA0/AN0
000or
010or
VREF
100or
110or 111
(Reference
voltage)
001or
011or
101
PCFG2:PCFG0
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 47
PIC16C712/716
To calculate the minimum acquisition time, TACQ, see
the PICmicro™ Mid-Range Reference Manual,
(DS33023). This equation calculates the acquisition
time to within 1/2 LSb error (512 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified accuracy.
8.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 8-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
source impedance affects the offset voltage at the ana-
log input (due to pin leakage current). The maximum
recommended impedance for analog sources is 10
kΩ. After the analog input channel is selected
(changed) this acquisition must be done before the
conversion can be started.
Note: When the conversion is started, the hold-
ing capacitor is disconnected from the
input pin.
FIGURE 8-4: ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
Rs
SS
RIC ≤ 1k
RSS
CHOLD
= DAC capacitance
= 51.2 pF
CPIN
VA
I leakage
± 500 nA
VT = 0.6V
5 pF
VSS
Legend CPIN
VT
= input capacitance
= threshold voltage
6V
5V
VDD 4V
3V
I leakage = leakage current at the pin due to
various junctions
2V
RIC
SS
= interconnect resistance
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
5 6 7 8 9 10 11
Sampling Switch
(kΩ)
DS41106A-page 48
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
8.2
Selecting the A/D Conversion Clock
8.3
Configuring Analog Port Pins
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.5TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selectable. The four possible options for TAD are:
The ADCON1 and TRISA registers control the opera-
tion of the A/D port pins. The port pins that are desired
as analog inputs must have their corresponding TRIS
bits set (input). If the TRIS bit is cleared (output), the
digital output level (VOH or VOL) will be converted.
• 2TOSC
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
• 8TOSC
• 32TOSC
• Internal RC oscillator
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs, will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
Table 8-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
Note 2: Analog levels on any pin that is defined as
a digital input (including the AN3:AN0
pins), may cause the input buffer to con-
sume current that is out of the devices
specification.
TABLE 8-1
TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
Device Frequency
Operation
2TOSC
ADCS1:ADCS0
20 MHz
5 MHz
1.25 MHz
1.6 µs
333.33 kHz
100 ns(2)
400 ns(2)
400 ns(2)
1.6 µs
00
01
10
11
6 µs
24 µs(3)
96 µs(3)
2 - 6 µs(1)
8TOSC
6.4 µs
25.6 µs(3)
2 - 6 µs(1,4)
32TOSC
1.6 µs
6.4 µs
RC(5)
2 - 6 µs(1,4)
2 - 6 µs(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The RC source has a typical TAD time of 4 µs.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for
sleep operation only.
5: For extended voltage devices (LC), please refer to Electrical Specifications section.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 49
PIC16C712/716
GO/DONE bit will be set, starting the A/D conversion,
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with minimal software overhead (moving the ADRES to
the desired location). The appropriate analog input
channel must be selected and the minimum acquisition
done before the “special event trigger” sets the
GO/DONE bit (starts a conversion).
8.4
A/D Conversions
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
8.5
Use of the CCP Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP1 module. This requires that the
CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be pro-
grammed as 1011and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
TABLE 8-2
SUMMARY OF A/D REGISTERS
Value on
POR,
BOR
Value on all
other Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
--xx xxxx --xu uuuu
0000 000x 0000 000u
05h
PORTA
—
—
—
RA4
RA3
RA2
T0IF
RA1
RA0
INTCON
GIE
PEIE
T0IE
—
INTE
RBIE
INTF
RBIF
0Bh,8Bh
0Ch
1Eh
PIR1
ADIF
—
—
CCP1IF
TMR2IF TMR1IF -0-- -000 -0-- -000
—
ADRES
A/D Result Register
xxxx xxxx uuuu uuuu
ADCON0 ADCS1 ADCS0 CHS2
CHS1
CHS0 GO/DONE
—
ADON 0000 00-0 0000 00-0
1Fh
(1)
---1 1111 ---1 1111
85h
TRISA
PIE1
—
—
—
PORTA Data Direction Register
ADIE
—
—
—
—
—
CCP1IE TMR2IE TMR1IE -0-- -000 -0-- 0000
PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
8Ch
9Fh
—
—
ADCON1
—
—
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: Reserved bits; Do Not Use.
DS41106A-page 50
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
the part in reset while the power supply stabilizes. With
these two timers on-chip, most applications need no
external reset circuitry.
9.0
SPECIAL FEATURES OF THE
CPU
The PIC16C712/716 devices have a host of features
intended to maximize system reliability, minimize cost
through elimination of external components, provide
power saving operating modes and offer code protec-
tion. These are:
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost, while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
• OSC Selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
Additional information on special features is available in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
9.1
Configuration Bits
• Watchdog Timer (WDT)
• SLEEP
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
• Code protection
• ID locations
• In-Circuit Serial Programming™ (ICSP)
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h -
3FFFh), which can be accessed only during program-
ming.
These devices have a Watchdog Timer, which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay on power-up only and is designed to keep
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 51
PIC16C712/716
FIGURE 9-1: CONFIGURATION WORD
CP1 CP0 CP1 CP0 CP1 CP0
—
BODEN CP1 CP0 PWRTE WDTE
FOSC1 FOSC0
bit0
Register:CONFIG
Address2007h
bit13
(2)
bit 13-8, 5-4: CP1:CP0: Code Protection bits
Code Protection for 2K Program memory (PIC16C716)
11= Programming code protection off
10= 0400h - 07FFh code protected
01= 0200h - 07FFh code protected
00= 0000h - 07FFh code protected
bit 13-8, 5-4:
Code Protection for 1K Program memory (PIC16C712)
11= Programming code protection off
10= Programming code protection off
01= 0200h - 03FFh code protected
00= 0000h - 03FFh code protected
bit 7:
bit 6:
Unimplemented: Read as ’1’
BODEN: Brown-out Reset Enable bit
(1)
1= BOR enabled
0= BOR disabled
PWRTE: Power-up Timer Enable bit
(1)
bit 3:
1= PWRT disabled
0= PWRT enabled
bit 2:
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
Note 1:Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2:All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
DS41106A-page 52
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
9.2
Oscillator Configurations
TABLE 9-1
CERAMIC RESONATORS
9.2.1
OSCILLATOR TYPES
Ranges Tested:
Mode Freq
XT
The PIC16CXXX can be operated in four different oscil-
lator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
OSC1
OSC2
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
• LP
• XT
• HS
• RC
Low Power Crystal
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
Crystal/Resonator
These values are for design guidance only. See
notes at bottom of page.
High Speed Crystal/Resonator
Resistor/Capacitor
TABLE 9-2
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
9.2.2
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
Crystal
Freq
Cap. Range
C1
Cap. Range
C2
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 9-2). The
PIC16CXXX oscillator design requires the use of a par-
allel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifica-
tions. When in XT, LP or HS modes, the device can
have an external clock source to drive the
OSC1/CLKIN pin (Figure 9-3).
Osc Type
LP
32 kHz
200 kHz
200 kHz
1 MHz
33 pF
15 pF
33 pF
15 pF
XT
HS
47-68 pF
15 pF
47-68 pF
15 pF
4 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
15-33 pF
15-33 pF
FIGURE 9-2: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
20 MHz
These values are for design guidance only. See
notes at bottom of page.
OSC CONFIGURATION)
C1(1)
OSC1
Note 1: Recommended values of C1 and C2 are
identical to the ranges tested (Table 9-1).
2: Higher capacitance increases the stability
of the oscillator, but also increases the start-
up time.
To
internal
logic
XTAL
RS(2)
RF(3)
SLEEP
OSC2
3: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropri-
ate values of external components.
4: Rs may be required in HS mode, as well as
XT mode to avoid overdriving crystals with
low drive level specification.
C2(1)
PIC16C7XX
Note 1: See Table 9-1 and Table 9-2 for recom-
mended values of C1 and C2.
2: A series resistor (RS) may be required for
AT strip cut crystals.
3: RF varies with the crystal chosen.
FIGURE 9-3: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
OSC1
OSC2
Clock from
ext. system
PIC16C7XX
Open
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 53
PIC16C712/716
9.2.3
RC OSCILLATOR
9.3
Reset
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (REXT) and capacitor (CEXT) values and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C compo-
nents used. Figure 9-4 shows how the R/C combina-
tion is connected to the PIC16CXXX.
The PIC16CXXX differentiates between various kinds
of reset:
• Power-on Reset (POR)
• MCLR reset during normal operation
• MCLR reset during SLEEP
• WDT Reset (during normal operation)
• WDT Wake-up (during SLEEP)
• Brown-out Reset (BOR)
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR reset during SLEEP and
Brown-out Reset (BOR). They are not affected by a
WDT Wake-up, which is viewed as the resumption of
normal operation. The TO and PD bits are set or
cleared differently in different reset situations as indi-
cated in Table 9-4. These bits are used in software to
determine the nature of the reset. See Table 9-6 for a
full description of reset states of all registers.
FIGURE 9-4: RC OSCILLATOR MODE
VDD
Rext
Internal
OSC1
clock
Cext
PIC16C7XX
A simplified block diagram of the on-chip reset circuit is
shown in Figure 9-6.
VSS
OSC2/CLKOUT
Fosc/4
The PICmicro microcontrollers have a MCLR noise fil-
ter in the MCLR reset path. The filter will detect and
ignore small pulses.
Recommended values: 3 kΩ ≤ Rext ≤ 100 kΩ
Cext > 20pF
It should be noted that a WDT Reset does not drive
MCLR pin low.
DS41106A-page 54
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
9.4
Power-On Reset (POR)
9.5
Power-up Timer (PWRT)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (to a level of 1.5V - 2.1V). To take
advantage of the POR, just tie the MCLR pin directly (or
through a resistor) to VDD. This will eliminate external
RC components usually needed to create a Power-on
Reset. A maximum rise time for VDD is specified
(parameter D004). For a slow rise time, see Figure 9-5.
The Power-up Timer provides a fixed nominal time-out
(parameter #33), on power-up only, from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in reset as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an accept-
able level. A configuration bit is provided to enable/dis-
able the PWRT.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature,...) must be met to ensure oper-
ation. If these conditions are not met, the device must
be held in reset until the operating conditions are met.
Brown-out Reset may be used to meet the start-up con-
ditions.
The power-up time delay will vary from chip to chip due
to VDD, temperature, and process variation. See DC
parameters for details.
9.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and stabi-
lized.
FIGURE 9-5: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
VDD VDD
R
9.7
Brown-Out Reset (BOD)
R1
The PIC16C712/716 members have on-chip Brown-out
Reset circuitry. A configuration bit, BODEN, can disable
(if clear/programmed) or enable (if set) the Brown-out
Reset circuitry. If VDD falls below 4.0V, refer to VBOR
parameter D005(VBOR) for a time greater than param-
eter (TBOR) in Table 12-6. The brown-out situation will
reset the chip. A reset is not guaranteed to occur if VDD
falls below 4.0V for less than parameter (TBOR).
MCLR
PIC16C7XX
C
Note 1: External Power-on Reset circuit is required
only if VDD power-up slope is too slow. The
diode D helps discharge the capacitor
quickly when VDD powers down.
On any reset (Power-on, Brown-out, Watchdog, etc.)
the chip will remain in Reset until VDD rises above
VBOR. The Power-up Timer will now be invoked and will
keep the chip in reset an additional 72 ms.
2: R < 40 kΩ is recommended to make sure
that voltage drop across R does not violate
the device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin break-
down due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
If VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above VBOR, the Power-Up Timer will execute a
72 ms reset. The Power-up Timer should always be
enabled when Brown-out Reset is enabled. Figure 9-7
shows typical Brown-out situations.
For operations where the desired brown-out voltage is
other than 4V, an external brown-out circuit must be
used. Figure 9-8, 9-9 and 9-10 show examples of exter-
nal brown-out protection circuits.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 55
PIC16C712/716
FIGURE 9-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
SLEEP
WDT
WDT
Module
Time-out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset
S
R
BODEN
OST/PWRT
OST
10-bit Ripple counter
Chip_Reset
Q
OSC1
(1)
On-chip
RC OSC
PWRT
10-bit Ripple counter
PWRT
See Table 9-3 for time-out
situations.
Enable PWRT
Enable OST
BODEN
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
FIGURE 9-7: BROWN-OUT SITUATIONS
VDD
VBOR
Internal
Reset
72 ms
VDD
VBOR
Internal
<72 ms
Reset
72 ms
VDD
VBOR
Internal
Reset
72 ms
DS41106A-page 56
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
FIGURE 9-8: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
FIGURE 9-10: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 3
VDD
VDD
VDD
33k
MCP809
Vss
VDD
Q1
bypass
capacitor
10k
MCLR
VDD
40k
RST
PIC16C7XX
MCLR
PIC16C7XX
This brown-out protection circuit employs
Microchip Technology’s MCP809 microcontroller
supervisor. The MCP8XX and MCP1XX families
of supervisors provide push-pull and open
collector outputs with both high and low active
reset pins. There are 7 different trip point
selections to accommodate 5V and 3V systems
Note 1: This circuit will activate reset when VDD
goes below (Vz + 0.7V) where
Vz = Zener voltage.
2: Internal Brown-out Reset circuitry
should be disabled when using this cir-
cuit.
9.8
Time-out Sequence
FIGURE 9-9: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
On power-up the time-out sequence is as follows: First
PWRT time-out is invoked after the POR time delay has
expired. Then OST is activated. The total time-out will
vary based on oscillator configuration and the status of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 9-11,
Figure 9-12, and Figure 9-13 depict time-out
sequences on power-up.
VDD
VDD
R1
Q1
MCLR
R2
40k
PIC16C7XX
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 9-13). This is useful for testing purposes or to
synchronize more than one PIC16CXXX device operat-
ing in parallel.
Note 1: This brown-out circuit is less expensive,
albeit less accurate. Transistor Q1 turns
Table 9-5 shows the reset conditions for some special
function registers, while Table 9-6 shows the reset con-
ditions for all the registers.
off when VDD is below a certain level
such that:
R1
= 0.7 V
VDD x
R1 + R2
9.9
Power Control/Status Register
(PCON)
2: Internal brown-out reset should be dis-
abled when using this circuit.
3: Resistors should be adjusted for the
characteristics of the transistor.
The Power Control/Status Register, PCON has two
bits.
Bit0 is Brown-out Reset Status bit, BOR. If the BODEN
configuration bit is set, BOR is ’1’ on Power-on Reset.
If the BODEN configuration bit is clear, BOR is
unknown on Power-on Reset.
The BOR status bit is a "don't care" and is not neces-
sarily predictable if the brown-out circuit is disabled (the
BODEN configuration bit is clear). BOR must then be
set by the user and checked on subsequent resets to
see if it is clear, indicating a brown-out has occurred.
Bit1 is POR (Power-on Reset Status bit). It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 57
PIC16C712/716
TABLE 9-3
TIME-OUT IN VARIOUS SITUATIONS
Power-up
PWRTE = 0
Wake-up from
SLEEP
Oscillator Configuration
Brown-out
PWRTE = 1
1024TOSC
—
XT, HS, LP
RC
72 ms + 1024TOSC
72 ms
72 ms + 1024TOSC
1024TOSC
72 ms
—
TABLE 9-4
STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
0
0
1
1
1
1
1
x
x
x
0
1
1
1
1
1
0
x
1
0
0
u
1
1
x
0
1
1
0
u
0
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 9-5
RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Condition
Power-on Reset
000h
000h
0001 1xxx
000u uuuu
0001 0uuu
0000 1uuu
uuu0 0uuu
0001 1uuu
uuu1 0uuu
---- --0x
---- --uu
---- --uu
---- --uu
---- --uu
---- --u0
---- --uu
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset
000h
000h
WDT Wake-up
PC + 1
Brown-out Reset
000h
Interrupt wake-up from SLEEP
PC + 1(1)
Legend: u= unchanged, x= unknown, -= unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
DS41106A-page 58
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
TABLE 9-6
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS OF THE PIC16C712/716
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
W
xxxx xxxx
N/A
uuuu uuuu
N/A
uuuu uuuu
N/A
INDF
TMR0
PCL
xxxx xxxx
0000h
uuuu uuuu
0000h
uuuu uuuu
PC + 1(2)
000q quuu(3)
uuuu uuuu
--xx xxxx
uuuq quuu(3)
uuuu uuuu
--xu uuuu
STATUS
FSR
0001 1xxx
xxxx xxxx
--0x 0000
PORTA(4)
PORTB(5)
DATACCP
PCLATH
INTCON
xxxx xxxx
uuuu uuuu
uuuu uuuu
---- -x-x
---0 0000
0000 -00x
---- -u-u
---0 0000
0000 -00u
---- -u-u
---u uuuu
uuuu -uuu(1)
---- uuuu(1)
---- 0000
-0-- 0000
---- 0000
-0-- 0000
PIR1
-u-- uuuu(1)
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uu-u
uuuu uuuu
--uu uuuu
uuuu uuuu
xxxx xuxu
---- uuuu
-u-- uuuu
---- --uq
1111 1111
---- -uuu
TMR1L
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
-000 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
0000 00-0
1111 1111
--11 1111
1111 1111
xxxx x1x1
---- 0000
-0-- 0000
---- --0q
1111 1111
---- -000
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0000
-000 0000
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
0000 00-0
1111 1111
--11 1111
1111 1111
xxxx x1x1
---- 0000
-0-- 0000
---- --uq
1111 1111
---- -000
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
ADRES
ADCON0
OPTION_REG
TRISA
TRISB
TRISCCP
PIE1
PCON
PR2
ADCON1
Legend:
u
= unchanged,
x = unknown, -= unimplemented bit, read as ’0’, q= value depends on condition
Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
3: See Table 9-5 for reset value for specific condition.
4: On any device reset, these pins are configured as inputs.
5: This is the value that will be in the port output latch.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 59
PIC16C712/716
FIGURE 9-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 9-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 9-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS41106A-page 60
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
The peripheral interrupt flags are contained in the spe-
cial function registers, PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers, PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister, INTCON.
9.10
Interrupts
The PIC16C712/716 devices have up to 7 sources of
interrupt. The interrupt control register (INTCON)
records individual interrupt requests in flag bits. It also
has individual and global interrupt enable bits.
Note: Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit or the GIE bit.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
FIGURE 9-14: INTERRUPT LOGIC
Wake-up (If in SLEEP mode)
Interrupt to CPU
T0IF
T0IE
INTF
INTE
ADIF
ADIE
RBIF
RBIE
PEIE
GIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 61
PIC16C712/716
9.10.1 INT INTERRUPT
9.11
Context Saving During Interrupts
External interrupt on RB0/INT pin is edge triggered,
either rising if bit INTEDG (OPTION_REG<6>) is set,
or falling if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 9.13 for details on SLEEP mode.
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt, (i.e., W register and STATUS
register). This will have to be implemented in software.
Example 9-1 stores and restores the W and STATUS
registers. The register, W_TEMP, must be defined in
each bank and must be defined at the same offset from
the bank base address (i.e., if W_TEMP is defined at
0x20 in bank 0, it must also be defined at 0xA0 in bank
1).
The example:
a) Stores the W register.
b) Stores the STATUS register in bank 0.
c) Stores the PCLATH register.
9.10.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 4.0)
d) Executes the interrupt service routine code
(User-generated).
e) Restores the STATUS register (and bank select
bit).
f) Restores the W and PCLATH registers.
9.10.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 3.2)
EXAMPLE 9-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
BCF
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
STATUS, IRP
FSR, W
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
;Return to Bank 0
;Copy FSR to W
MOVF
MOVWF
:
FSR_TEMP
;Copy FSR from W to FSR_TEMP
:(ISR)
:
MOVF
MOVWF
SWAPF
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Swap W_TEMP into W
DS41106A-page 62
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
WDT time-out period values may be found in the Elec-
trical Specifications section under TWDT (parameter
#31). Values for the WDT prescaler (actually a
postscaler, but shared with the Timer0 prescaler) may
be assigned using the OPTION_REG register.
9.12
Watchdog Timer (WDT)
The Watchdog Timer is as a free running, on-chip, RC
oscillator which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device have been stopped,
for example, by execution of a SLEEPinstruction.
Note: The CLRWDTand SLEEPinstructions clear
the WDT and the postscaler, if assigned to
the WDT, and prevent it from timing out and
generating a device RESET condition.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS register
will be cleared upon a Watchdog Timer time-out.
.
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 9.1).
FIGURE 9-15: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 4-2)
0
Postscaler
8
M
1
U
WDT Timer
X
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 4-2)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
FIGURE 9-16: SUMMARY OF WATCHDOG TIMER REGISTERS
Address Name
Bits 13:8
Bit 7
Bit 6
BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0
INTEDG T0CS T0SE PSA PS2 PS1 PS0
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2007h
Config. bits
(1)
—
OPTION_REG
81h
N/A
RBPU
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 9-1 for operation of these bits.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 63
PIC16C712/716
Other peripherals cannot generate interrupts, since
during SLEEP, no on-chip clocks are present.
9.13
Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOPafter the SLEEPinstruction.
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D and the disable external clocks. Pull all I/O pins,
that are hi-impedance inputs, high or low externally to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
9.13.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
The MCLR pin must be at a logic high level (VIHMC).
9.13.1 WAKE-UP FROM SLEEP
• If the interrupt occurs before the execution of a
SLEEPinstruction, the SLEEPinstruction will com-
plete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
The device can wake up from SLEEP through one of
the following events:
• If the interrupt occurs during or after the execu-
tion of a SLEEPinstruction, the device will imme-
diately wake up from sleep. The SLEEPinstruction
will be completely executed before the wake-up.
Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
1. External reset input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change, or some
peripheral interrupts.
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up, is cleared when SLEEPis invoked. The TO
bit is cleared if a WDT time-out occurred (and caused
wake-up).
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDTinstruc-
tion should be executed before a SLEEPinstruction.
The following peripheral interrupts can wake the device
from SLEEP:
1. TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
2. CCP capture mode interrupt.
3. Special event trigger (Timer1 in asynchronous
mode using an external clock).
DS41106A-page 64
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
FIGURE 9-17: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
TOST(2)
INTF flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
Inst(PC - 1)
fetched
Instruction
executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(0004h)
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
9.14
Program Verification/Code Protection
9.16
In-Circuit Serial Programming™
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
PIC16CXXX microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming volt-
age. This allows customers to manufacture boards with
unprogrammed devices, and then program the micro-
controller just before shipping the product. This also
allows the most recent firmware or a custom firmware
to be programmed.
Note: Microchip does not recommend code pro-
tecting windowed devices.
9.15
ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during program/verify. It is recom-
mended that only the 4 least significant bits of the ID
location are used.
For complete details on serial programming, please
refer to the In-Circuit Serial Programming (ICSP™)
Guide, (DS30277).
For ROM devices, these values are submitted along
with the ROM code.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 65
PIC16C712/716
NOTES:
DS41106A-page 66
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.
10.0 INSTRUCTION SET SUMMARY
Each PIC16CXXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXXX instruc-
tion set summary in Table 10-2 lists byte-oriented, bit-
oriented, and literal and control operations. Table 10-
1 shows the opcode field descriptions.
Table 10-2 lists the instructions recognized by the
MPASM assembler.
Figure 10-1 shows the general formats that the instruc-
tions can have.
Note: To maintain upward compatibility with
future PIC16CXXX products, do not use
the OPTIONand TRISinstructions.
For byte-oriented instructions, ’f’ represents a file reg-
ister designator and ’d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
All examples use the following format to represent a
hexadecimal number:
The destination designator specifies where the result of
the operation is to be placed. If ’d’ is zero, the result is
placed in the W register. If ’d’ is one, the result is placed
in the file register specified in the instruction.
0xhh
where h signifies a hexadecimal digit.
FIGURE 10-1: GENERAL FORMAT FOR
INSTRUCTIONS
For bit-oriented instructions, ’b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ’f’ represents the number of the
file in which the bit is located.
Byte-oriented file register operations
13
8
7
6
0
0
OPCODE
d
f (FILE #)
For literal and control operations, ’k’ represents an
eight or eleven bit constant or literal value.
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
TABLE 10-1
OPCODE FIELD
DESCRIPTIONS
Bit-oriented file register operations
13 10 9
b (BIT #)
Field
Description
7
6
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
OPCODE
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Bit address within an 8-bit file register
Literal field, constant data or label
Don’t care location (= 0 or 1)
Literal and control operations
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
General
13
8
7
0
0
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
OPCODE
k (literal)
k = 8-bit immediate value
PC
TO
PD
Z
Program Counter
Time-out bit
Power-down bit
Zero bit
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
k (literal)
DC
C
Digit Carry bit
Carry bit
The instruction set is highly orthogonal and is grouped
into three basic categories:
A description of each instruction is available in the
PICmicro™
(DS33023).
Mid-Range
Reference
Manual,
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 67
PIC16C712/716
TABLE 10-2
PIC16CXXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
Status
Affected
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d Add W and f
f, d AND W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111 dfff ffff C,DC,Z
1,2
1,2
2
0101 dfff ffff
0001 lfff ffff
0001 0000 0011
1001 dfff ffff
0011 dfff ffff
1011 dfff ffff
1010 dfff ffff
1111 dfff ffff
0100 dfff ffff
1000 dfff ffff
0000 lfff ffff
0000 0xx0 0000
1101 dfff ffff
1100 dfff ffff
Z
Z
Z
Z
Z
f
-
Clear f
Clear W
f, d Complement f
f, d Decrement f
f, d Decrement f, Skip if 0
f, d Increment f
f, d Increment f, Skip if 0
f, d Inclusive OR W with f
f, d Move f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
DECFSZ
INCF
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
1,2
f
-
Move W to f
No Operation
f, d Rotate Left f through Carry
f, d Rotate Right f through Carry
f, d Subtract W from f
f, d Swap nibbles in f
f, d Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
0010 dfff ffff C,DC,Z
1110 dfff ffff
0110 dfff ffff Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b Bit Clear f
f, b Bit Set f
f, b Bit Test f, Skip if Clear
f, b Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01 00bb bfff ffff
01 01bb bfff ffff
01 10bb bfff ffff
01 11bb bfff ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11 111x kkkk kkkk C,DC,Z
11 1001 kkkk kkkk
10 0kkk kkkk kkkk
Z
00 0000 0110 0100 TO,PD
10 1kkk kkkk kkkk
Inclusive OR literal with W
Move literal to W
11 1000 kkkk kkkk
11 00xx kkkk kkkk
00 0000 0000 1001
11 01xx kkkk kkkk
00 0000 0000 1000
Z
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
00 0000 0110 0011 TO,PD
11 110x kkkk kkkk C,DC,Z
11 1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS41106A-page 68
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
11.3
ICEPIC: Low-Cost PICmicro
In-Circuit Emulator
11.0 DEVELOPMENT SUPPORT
11.1
Development Tools
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC12CXXX, PIC16C5X and PIC16CXXX
families of 8-bit OTP microcontrollers.
The PICmicro microcontrollers are supported with a
full range of hardware and software development tools:
• MPLAB -ICE Real-Time In-Circuit Emulator
ICEPIC is designed to operate on PC-compatible
machines ranging from 386 through Pentium based
machines under Windows 3.x, Windows 95, or Win-
dows NT environment. ICEPIC features real time, non-
intrusive emulation.
• ICEPIC Low-Cost PIC16C5X and PIC16CXXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
11.4
PRO MATE II: Universal Programmer
• SIMICE
The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In stand-
alone mode the PRO MATE II can read, verify or pro-
• MPLAB SIM Software Simulator
• MPLAB-C17 (C Compiler)
• Fuzzy Logic Development System
(fuzzyTECH −MP)
• KEELOQ® Evaluation Kits and Programmer
11.2
MPLAB-ICE: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
gram
PIC12CXXX,
PIC14C000,
PIC16C5X,
PIC16CXXX and PIC17CXX devices. It can also set
configuration and code-protect bits in this mode.
11.5
PICSTART Plus Entry Level
Development System
The MPLAB-ICE Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers (MCUs). MPLAB-ICE is sup-
plied with the MPLAB Integrated Development Environ-
ment (IDE), which allows editing, “make” and
download, and source debugging from a single envi-
ronment.
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is not
recommended for production programming.
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different pro-
cessors. The universal architecture of the MPLAB-ICE
allows expansion to support all new Microchip micro-
controllers.
PICSTART Plus supports all PIC12CXXX, PIC14C000,
PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
PIC16C923, PIC16C924 and PIC17C756 may be sup-
ported with an adapter socket. PICSTART Plus is CE
compliant.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced fea-
tures that are generally found on more expensive devel-
opment tools. The PC compatible 386 (and higher)
machine platform and Microsoft Windows 3.x or
Windows 95 environment were chosen to best make
these features available to you, the end user.
MPLAB-ICE
is
available
in
two
versions.
MPLAB-ICE 1000 is a basic, low-cost emulator system
with simple trace capabilities. It shares processor mod-
ules with the MPLAB-ICE 2000. This is a full-featured
emulator system with enhanced trace, trigger, and data
monitoring features. Both systems will operate across
the entire operating speed range of the PICmicro MCU.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 69
PIC16C712/716
11.6
SIMICE Entry-Level Hardware
Simulator
11.8
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
SIMICE is an entry-level hardware development sys-
tem designed to operate in a PC-based environment
with Microchip’s simulator MPLAB™-SIM. Both SIM-
ICE and MPLAB-SIM run under Microchip Technol-
ogy’s MPLAB Integrated Development Environment
(IDE) software. Specifically, SIMICE provides hardware
simulation for Microchip’s PIC12C5XX, PIC12CE5XX,
and PIC16C5X families of PICmicro 8-bit microcontrol-
lers. SIMICE works in conjunction with MPLAB-SIM to
provide non-real-time I/O port emulation. SIMICE
enables a developer to run simulator code for driving
the target system. In addition, the target system can
provide input to the simulator code. This capability
allows for simple and interactive debugging without
having to manually generate MPLAB-SIM stimulus
files. SIMICE is a valuable debugging tool for entry-
level system development.
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-Plus, and easily test firmware.
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connec-
tion to an LCD module and a keypad.
11.7
PICDEM-1 Low-Cost PICmicro
Demonstration Board
11.9
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and download the
firmware to the emulator for testing. Additional proto-
type area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an addi-
tional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
DS41106A-page 70
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
11.10 MPLAB Integrated Development
Environment Software
11.12 Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PICmicro series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The input/
output radix can be set by the user and the execution
can be performed in; single step, execute until break, or
in a trace mode.
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPASM. The Software Simulator
offers the low cost flexibility to develop and debug code
outside of the laboratory environment making it an
excellent multi-project software development tool.
- simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
MPLAB allows you to:
11.13 MPLAB-C17 Compiler
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Debug using:
- source files
The MPLAB-C17 Code Development System is a
complete ANSI ‘C’ compiler and integrated develop-
ment environment for Microchip’s PIC17CXXX family of
microcontrollers. The compiler provides powerful inte-
gration capabilities and ease of use not found with
other compilers.
- absolute listing file
For easier source level debugging, the compiler pro-
vides symbol information that is compatible with the
MPLAB IDE memory display.
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
11.14 Fuzzy Logic Development System
(fuzzyTECH-MP)
11.11 Assembler (MPASM)
fuzzyTECH-MP fuzzy logic development tool is avail-
able in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, Edition for imple-
menting more complex systems.
The MPASM Universal Macro Assembler is a PC-
hosted symbolic assembler. It supports all microcon-
troller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, condi-
tional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
Both versions include Microchip’s fuzzyLAB demon-
stration board for hands-on experience with fuzzy logic
systems implementation.
11.15 SEEVAL Evaluation and
Programming System
MPASM allows full symbolic debugging from MPLAB-
ICE, Microchip’s Universal Emulator System.
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in trade-
off analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
MPASM has the following features to assist in develop-
ing software for specific use applications.
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol, and
special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal source
and listing formats.
MPASM provides a rich directive language to support
programming of the PICmicro. Directives are helpful in
making the development of your assemble source code
shorter and more maintainable.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 71
PIC16C712/716
11.16 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS eval-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
DS41106A-page 72
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
TABLE 11-1
DEVELOPMENT TOOLS FROM MICROCHIP
y
z
u
s t
o d u P c r o t r u l m a E
s l o o
a r e f t T w S o
s r e m m a o r g P r
s
B o o a r d D e m
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 73
PIC16C712/716
NOTES:
DS41106A-page 74
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
12.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2).......................................................................................... 0V to +13.25V
Voltage on RA4 with respect to Vss............................................................................................................... 0V to +8.5V
Total power dissipation (Note 1)(PDIP and SOIC) ....................................................................................................1.0W
Total power dissipation (Note 1)(SSOP) .................................................................................................................0.65W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA and PORTB (combined).................................................................................200 mA
Maximum current sourced by PORTA and PORTB (combined)............................................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin rather
than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 75
PIC16C712/716
FIGURE 12-1: PIC16C712/716 VOLTAGE-FREQUENCY GRAPH, -40°C < TA < +125°C
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 12-2: PIC16LC712/716 VOLTAGE-FREQUENCY GRAPH, 0°C < TA < +70°C
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
DS41106A-page 76
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
12.1
DC Characteristics:
PIC16C712/716-04 (Commercial, Industrial, Extended)
PIC16C712/716-20 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0°C ≤ TA ≤
-40°C ≤ TA ≤
-40°C ≤ TA ≤
+70°C for commercial
+85°C for industrial
+125°C for extended
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Supply Voltage
Min
Typ† Max Units
Conditions
D001
D001A
VDD
4.0
VBOR*
-
-
5.5
5.5
V
V
BOR enabled (Note 7)
(1)
D002*
D003
VDR
-
-
1.5
-
-
V
RAM Data Retention Voltage
VPOR
VDD Start Voltage to ensure inter-
VSS
V
See section on Power-on Reset for details
nal Power-on Reset signal
D004*
D004A*
SVDD
VDD Rise Rate to ensure internal
Power-on Reset signal
0.05
TBD
-
-
-
-
V/ms PWRT enabled (PWRTE bit clear)
PWRT disabled (PWRTE bit set)
See section on Power-on Reset for details
D005
VBOR
IDD
Brown-out Reset
voltage trip point
3.65
-
4.35
V
BODEN bit set
(2,5)
D010
D013
-
-
0.8
4.0
2.5
8.0
mA FOSC = 4 MHz, VDD = 4.0V
mA FOSC = 20 MHz, VDD = 4.0V
Supply Current
(3,5)
D020
IPD
-
-
-
-
10.5
1.5
1.5
42
16
19
19
µA
µA
µA
µA
VDD = 4.0V, WDT enabled,-40°C to +85°C
VDD = 4.0V, WDT disabled, 0°C to +70°C
VDD = 4.0V, WDT disabled,-40°C to +85°C
VDD = 4.0V, WDT disabled,-40°C to +125°C
Power-down Current
D021
D021B
2.5
(6)
Module Differential Current
D022*
D022A* ∆IBOR
∆IWDT
-
-
6.0
TBD
20
200
µA
µA
WDTE bit set, VDD = 4.0V
BODEN bit set, VDD = 5.0V
Watchdog Timer
Brown-out Reset
1A
FOSC
LP Oscillator Operating Frequency
RC Oscillator Operating Frequency
XT Oscillator Operating Frequency
HS Oscillator Operating Frequency
0
0
0
0
—
—
—
—
200
4
4
KHz All temperatures
MHz All temperatures
MHz All temperatures
MHz All temperatures
20
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-
sumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the
part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by the formula Ir =
VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for
design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base
IDD or IPD measurement.
7: This is the voltage where the device enters the Brown-out Reset. When BOR is enabled, the device will operate correctly to
this trip point.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 77
PIC16C712/716
12.2
DC Characteristics: PIC16LC712/716-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤
Max Units
DC CHARACTERISTICS
+85°C for industrial
Param
No.
Sym
Characteristic
Supply Voltage
RAM Data Retention Voltage
Min
Typ†
Conditions
D001
VDD
2.5
VBOR*
-
-
5.5
5.5
V
V
BOR enabled (Note 7)
(1)
D002*
D003
VDR
-
-
1.5
-
-
V
VPOR
VDD Start Voltage to ensure inter-
VSS
V
See section on Power-on Reset for details
nal Power-on Reset signal
D004*
D004A*
SVDD
VDD Rise Rate to ensure internal
Power-on Reset signal
0.05
TBD
-
-
-
-
V/ms PWRT enabled (PWRTE bit clear)
PWRT disabled (PWRTE bit set)
See section on Power-on Reset for details
D005
VBOR
IDD
Brown-out Reset
voltage trip point
3.65
-
4.35
V
BODEN bit set
(2,5)
D010
-
-
2.0
3.8
48
mA XT, RC osc modes
FOSC = 4 MHz, VDD = 3.0V (Note 4)
LP osc mode
Supply Current
D010A
22.5
µA
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
(3,5)
D020
D021
D021A
IPD
-
-
-
7.5
0.9
0.9
30
5
5
µA
µA
µA
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
Power-down Current
(6)
Module Differential Current
D022*
D022A* ∆IBOR
∆IWDT
-
-
6.0
TBD
20
200
µA
µA
WDTE bit set, VDD = 4.0V
BODEN bit set, VDD = 5.0V
Watchdog Timer
Brown-out Reset
1A FOSC
LP Oscillator Operating Frequency
RC Oscillator Operating Frequency
XT Oscillator Operating Frequency
HS Oscillator Operating Frequency
0
0
0
0
—
—
—
—
200
4
4
KHz All temperatures
MHz All temperatures
MHz All temperatures
MHz All temperatures
20
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-
sumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the
part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by the formula Ir
= VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is
for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base
IDD or IPD measurement.
7: This is the voltage where the device enters the Brown-out Reset. When BOR is enabled, the device will operate correctly to
this trip point.
DS41106A-page 78
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
12.3
DC Characteristics:
PIC16C712/716-04 (Commercial, Industrial, Extended)
PIC16C712716-20 (Commercial, Industrial, Extended)
PIC16LC712/716-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0°C ≤ TA ≤
-40°C ≤ TA ≤
+70°C for commercial
+85°C for industrial
DC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC spec Section 12.1
and Section 12.2
Param Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
Input Low Voltage
I/O ports
VIL
D030
D030A
D031
D032
D033
with TTL buffer
VSS
VSS
VSS
Vss
Vss
-
-
-
-
-
0.8V
V
V
V
V
V
4.5V ≤ VDD ≤ 5.5V
otherwise
0.15VDD
0.2VDD
0.2VDD
0.3VDD
with Schmitt Trigger buffer
MCLR, OSC1 (in RC mode)
OSC1 (in XT, HS and LP
modes)
Note1
Input High Voltage
I/O ports
VIH
-
-
-
D040
D040A
with TTL buffer
2.0
0.25VDD
+ 0.8V
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
otherwise
D041
D042
D042A
D043
with Schmitt Trigger buffer 0.8VDD
-
-
-
-
VDD
VDD
VDD
VDD
V
V
V
V
For entire VDD range
Note1
MCLR
0.8VDD
OSC1 (XT, HS and LP modes) 0.7VDD
OSC1 (in RC mode)
Input Leakage Current (Notes
2, 3)
0.9VDD
D060
IIL
I/O ports
-
-
±1
µA Vss ≤ VPIN ≤ VDD,
Pin at hi-impedance
D061
D063
MCLR, RA4/T0CKI
OSC1
-
-
-
-
±5
±5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD,
XT, HS and LP osc modes
µA VDD = 5V, VPIN = VSS
D070
D080
IPURB PORTB weak pull-up current
50
-
250
400
0.6
0.6
0.6
0.6
Output Low Voltage
I/O ports
VOL
-
-
-
-
V
V
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
-
D083
OSC2/CLKOUT
(RC osc mode)
-
-
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmi-
cro be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input volt-
ages.
3: Negative current is defined as current sourced by the pin.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 79
PIC16C712/716
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0°C ≤ TA ≤
-40°C ≤ TA ≤
+70°C for commercial
+85°C for industrial
DC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC spec Section 12.1
and Section 12.2
Param Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
Output High Voltage
D090
VOH
I/O ports (Note 3)
VDD-0.7
VDD-0.7
VDD-0.7
VDD-0.7
-
-
-
-
-
-
-
-
V
V
V
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
D092
OSC2/CLKOUT (RC osc
mode)
-
-
D150* VOD
Open-Drain High Voltage
Capacitive Loading Specs
on Output Pins
8.5
RA4 pin
D100
D101
COSC2 OSC2 pin
-
-
-
-
15
50
pF In XT, HS and LP modes when
external clock is used to drive
OSC1.
CIO
All I/O pins and OSC2 (in RC
mode)
pF
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmi-
cro be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input volt-
ages.
3: Negative current is defined as current sourced by the pin.
DS41106A-page 80
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
12.4
AC (Timing) Characteristics
12.4.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
using one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
T
Time
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 81
PIC16C712/716
12.4.2 TIMING CONDITIONS
The temperature and voltages specified in Table 12-1
apply to all timing specifications, unless otherwise
noted. Figure 12-1 specifies the load conditions for the
timing specifications.
TABLE 12-1
TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
AC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 12.1 and Section 12.2.
LC parts operate for commercial/industrial temp’s only.
FIGURE 12-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1 Load condition 2
VDD/2
CL
RL
Pin
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins except OSC2/CLKOUT
15 pF for OSC2 output
VSS
DS41106A-page 82
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
12.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 12-2: EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
Q1
Q4
OSC1
3
3
1
4
4
2
CLKOUT
TABLE 12-2
EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No.
Sym Characteristic
Min
Typ†
Max
Units Conditions
1A
FOSC
External CLKIN Frequency
(Note 1)
DC
DC
DC
DC
DC
0.1
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
4
MHz RC and XT osc modes
MHz HS osc mode (-04)
MHz HS osc mode (-20)
kHz LP osc mode
20
200
4
Oscillator Frequency
(Note 1)
MHz RC osc mode
4
MHz XT osc mode
20
200
—
MHz HS osc mode
5
kHz LP osc mode
1
TOSC
External CLKIN Period
(Note 1)
250
250
50
ns
ns
ns
µs
ns
ns
ns
ns
µs
ns
ns
µs
ns
ns
ns
ns
RC and XT osc modes
HS osc mode (-04)
HS osc mode (-20)
LP osc mode
—
—
5
—
Oscillator Period
(Note 1)
250
250
250
50
—
RC osc mode
XT osc mode
10,000
250
250
—
HS osc mode (-04)
HS osc mode (-20)
LP osc mode
5
2
TCY
Instruction Cycle Time (Note 1)
200
100
2.5
15
DC
—
TCY = 4/FOSC
3*
TosL,
TosH
External Clock in (OSC1) High or
Low Time
XT oscillator
—
LP oscillator
—
HS oscillator
4*
TosR,
TosF
External Clock in (OSC1) Rise or
Fall Time
—
25
50
15
XT oscillator
—
LP oscillator
—
HS oscillator
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at "min." values with an external
clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 83
PIC16C712/716
FIGURE 12-3: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
12
19
18
14
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 12-1 for load conditions.
TABLE 12-3
CLKOUT AND I/O TIMING REQUIREMENTS
Param Sym
No.
Characteristic
Min
Typ†
Max
Units Conditions
10*
11*
TosH2ckL OSC1↑ to CLKOUT↓
TosH2ckH OSC1↑ to CLKOUT↑
—
75
75
35
35
—
—
—
50
—
—
—
10
—
10
—
—
—
200
200
100
100
ns
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
—
12*
TckR
TckF
CLKOUT rise time
CLKOUT fall time
—
13*
—
14*
TckL2ioV CLKOUT ↓ to Port out valid
TioV2ckH Port in valid before CLKOUT ↑
—
0.5TCY + 20 ns
15*
Tosc + 200
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16*
TckH2ioI
Port in hold after CLKOUT ↑
0
—
17*
TosH2ioV OSC1↑ (Q1 cycle) to Port out valid
150
—
18*
TosH2ioI
OSC1↑ (Q2 cycle) to Port input Standard
100
200
0
invalid (I/O in hold time)
18A*
19*
Extended (LC)
—
TioV2osH Port input valid to OSC1↑ (I/O in setup time)
—
20*
TioR
Port output rise time
Port output fall time
INT pin high or low time
Standard
—
40
80
40
80
—
20A*
21*
Extended (LC)
Standard
—
TioF
—
21A*
Extended (LC)
—
22††* TINP
23††* TRBP
TCY
TCY
RB7:RB4 change INT high or low time
—
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
†† These parameters are asynchronous events not related to any internal clock edge.
Note1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS41106A-page 84
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
FIGURE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 12-1 for load conditions.
FIGURE 12-5: BROWN-OUT RESET TIMING
BVDD
VDD
35
TABLE 12-4
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
30
TmcL MCLR Pulse Width (low)
2
—
—
µs VDD = 5V, -40°C to +125°C
31*
TWDT
Watchdog Timer Time-out Period
(No Prescaler)
7
18
33
ms
VDD = 5V, -40°C to +125°C
32
33*
34
TOST
Oscillation Start-up Timer Period
—
28
—
1024 TOSC
—
—
ms
µs
TOSC = OSC1 period
TPWRT Power-up Timer Period
72
—
132
2.1
VDD = 5V, -40°C to +125°C
TIOZ
I/O Hi-impedance from MCLR
Low or WDT reset
35
TBOR
Brown-out Reset Pulse Width
100
—
—
VDD ≤ BVDD (D005)
µs
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 85
PIC16C712/716
FIGURE 12-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 12-1 for load conditions.
TABLE 12-5
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max Units Conditions
40*
Tt0H
T0CKI High Pulse Width
No Prescaler
0.5TCY + 20
—
—
ns Must also meet
parameter 42
With Prescaler
No Prescaler
10
0.5TCY + 20
10
—
—
—
—
—
—
—
—
—
—
ns
41*
42*
Tt0L
Tt0P
T0CKI Low Pulse Width
T0CKI Period
ns Must also meet
parameter 42
With Prescaler
No Prescaler
With Prescaler
ns
ns
TCY + 40
Greater of:
20 or TCY + 40
ns N = prescale value
(2, 4,..., 256)
N
0.5TCY + 20
15
45*
46*
47*
Tt1H
Tt1L
Tt1P
T1CKI High Time Synchronous, Prescaler = 1
—
—
—
—
—
—
ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
ns
ns
Standard
25
Extended (LC)
Asynchronous
30
—
—
—
—
—
—
—
—
—
—
ns
ns
Standard
50
Extended (LC)
T1CKI Low Time
Synchronous, Prescaler = 1
0.5TCY + 20
ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
15
25
ns
ns
Standard
Extended (LC)
Asynchronous
30
50
—
—
—
—
—
—
ns
ns
Standard
Extended (LC)
Standard
T1CKI input period Synchronous
Greater of:
30 OR TCY + 40
N
ns N = prescale value
(1, 2, 4, 8)
Greater of:
50 OR TCY + 40
N
N = prescale value
(1, 2, 4, 8)
Extended (LC)
Asynchronous
60
100
DC
—
—
—
—
—
ns
ns
Standard
Extended (LC)
Ft1
Timer1 oscillator input frequency range
200
kHz
(oscillator enabled by setting bit T1OSCEN)
48
*
TCKEZtmr1 Delay from external clock edge to timer increment
2Tosc
—
7Tosc
—
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS41106A-page 86
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
FIGURE 12-7: CAPTURE/COMPARE/PWM TIMINGS
CCP1
(Capture Mode)
50
51
52
54
CCP1
(Compare or PWM Mode)
53
Note: Refer to Figure 12-1 for load conditions.
TABLE 12-6
CAPTURE/COMPARE/PWM REQUIREMENTS
Param
No.
Sym Characteristic
Min
Typ† Max Units Conditions
50*
TccL CCP1 input low
time
No Prescaler
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
With Prescaler Standard
10
Extended (LC)
20
51*
TccH
No Prescaler
0.5TCY + 20
CCP1 input high
time
With Prescaler Standard
10
20
Extended (LC)
52*
53*
TccP
3TCY + 40
ns N = prescale value
(1,4, or 16)
CCP1 input period
N
TccR CCP1 output rise time
TccF CCP1 output fall time
Standard
—
—
—
—
10
25
10
25
25
45
25
45
ns
ns
ns
ns
Extended (LC)
Standard
54*
Extended (LC)
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 87
PIC16C712/716
TABLE 12-7
A/D CONVERTER CHARACTERISTICS:
PIC16C712/716-04 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC16C712/716-20 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC16LC712/716-04 (COMMERCIAL, INDUSTRIAL)
Param Sym Characteristic
No.
Min
Typ†
Max
Units
Conditions
A01
NR Resolution
—
—
—
—
—
—
—
—
—
—
—
—
—
8-bits
bit VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A02 EABS Total Absolute error
< ± 1
< ± 1
< ± 1
< ± 1
LSb
LSb
LSb
LSb
A03
A04
A05
EIL Integral linearity error
EDL Differential linearity error
EFS Full scale error
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A06 EOFF Offset error
A10 Monotonicity
A20 VREF Reference voltage
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
< ± 1
—
LSb
—
—
guaranteed
(Note 3)
VSS ≤ VAIN ≤ VREF
2.5V
VSS - 0.3
—
—
—
—
VDD + 0.3
VREF + 0.3
10.0
V
V
A25
A30
VAIN Analog input voltage
ZAIN Recommended impedance of
kΩ
analog voltage source
A40
A50
IAD A/D conversion current Standard
(VDD)
—
—
180
90
—
—
µA Average current consump-
tion when A/D is on.
(Note 1)
Extended (LC)
µA
IREF VREF input current (Note 2)
10
—
1000
µA During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD, see Section 9.1.
—
—
10
µA During A/D Conversion
cycle
2:
3:
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are
for design guidance only and are not tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes.
DS41106A-page 88
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
FIGURE 12-8: A/D CONVERSION TIMING
BSF ADCON0, GO
1 Tcy
(TOSC/2) (1)
134
131
130
Q4
132
A/D CLK
7
6
5
4
3
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This
allows the SLEEPinstruction to be executed.
TABLE 12-8
A/D CONVERSION REQUIREMENTS
Param Sym Characteristic
Min
Typ†
Max
Units
Conditions
No.
Standard
130
TAD A/D clock period
1.6
2.0
2.0
3.0
11
—
—
—
—
µs
µs
TOSC based, VREF ≥ 3.0V
Extended (LC)
Standard
TOSC based, VREF full range
4.0
6.0
—
6.0
9.0
11
µs A/D RC Mode
Extended (LC)
µs A/D RC Mode
TAD
131
132
TCNV Conversion time (not including S/H time)
(Note 1)
TACQ Acquisition time
Note 2
5*
20
—
—
—
µs
µs The minimum time is the amplifier
settling time. This may be used if
the "new" input voltage has not
changed by more than 1 LSb (i.e.,
20.0 mV @ 5.12V) from the last
sampled voltage (as stated on
CHOLD).
134
135
TGO Q4 to A/D clock start
—
TOSC/2 §
—
—
—
If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEPinstruction to be
executed.
TSWC Switching from convert → sample time
1.5 §
—
TAD
:
* These parameters are characterized but not tested.
:
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
:
§ This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 9.1 for min conditions.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 89
PIC16C712/716
NOTES:
DS41106A-page 90
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
13.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are guaranteed to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period
of time and matrix samples. ’Typical’ represents the mean of the distribution at 25°C. ’Max’ or ’min’ represents
(mean + 3σ) or (mean - 3σ) respectively, where σ is standard deviation, over the whole temperature range.
Graphs and Tables not available at this time.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 91
PIC16C712/716
NOTES:
DS41106A-page 92
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
14.0 PACKAGING INFORMATION
14.1
Package Marking Information
18-Lead PDIP
Example
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
AABBCDE
PIC16C716-04/P
9917HAT
18-Lead CERDIP Windowed
16C716
/JW
XXXXXXXX
XXXXXXXX
9917CAT
AABBCDE
18-Lead SOIC
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16C712
-20/SO
9910/SAA
AABBCDE
20-Lead SSOP
Example
PIC16C712
XXXXXXXXXX
XXXXXXXXXX
-20I/SS025
AABBCDE
9917SBP
Legend: MM...M Microchip part number information
XX...X Customer specific information*
AA
BB
C
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
O = Outside Vendor
C = 5” Line
S = 6” Line
H = 8” Line
D
E
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line thus limiting the number of available
characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 93
PIC16C712/716
Package Type: K04-007 18-Lead Plastic Dual In-line (P) – 300 mil
E
D
2
α
n
1
E1
A1
L
A
R
c
A2
B1
β
p
B
eB
Units
INCHES*
NOM
0.300
18
MILLIMETERS
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Molded Package Width
Radius to Radius Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
MAX
MIN
NOM
7.62
18
MAX
n
p
B
B1
R
c
A
A1
A2
L
D
E
E1
eB
α
0.100
0.018
0.060
0.005
0.010
0.155
0.095
0.020
0.130
0.895
0.255
0.250
0.349
10
2.54
0.013
0.023
0.33
1.40
0.46
1.52
0.13
0.25
3.94
2.41
0.51
3.30
22.73
6.48
6.35
8.85
10
0.58
†
0.055
0.000
0.005
0.110
0.075
0.000
0.125
0.890
0.245
0.230
0.310
5
0.065
0.010
0.015
0.155
0.115
0.020
0.135
0.900
0.265
0.270
0.387
15
1.65
0.25
0.38
3.94
2.92
0.51
3.43
22.86
6.73
6.86
9.83
15
0.00
0.13
2.79
1.91
0.00
3.18
22.61
6.22
5.84
7.87
5
‡
‡
β
5
10
15
5
10
15
* Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent: MS-001 AC
DS41106A-page 94
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
Package Type: K04-010 18-Lead Ceramic Dual In-line with Window (JW) – 300 mil
E
D
W2
2
1
n
W1
E1
A
A1
R
L
c
A2
B1
eB
p
B
Units
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
INCHES*
NOM
0.300
18
MILLIMETERS
MIN
MAX
MIN
NOM
7.62
18
MAX
n
p
B
B1
R
c
A
A1
A2
L
D
E
E1
eB
W1
W2
0.098
0.100
0.019
0.055
0.013
0.010
0.183
0.111
0.023
0.138
0.900
0.298
0.270
0.385
0.140
0.200
0.102
2.49
0.41
2.54
0.47
1.40
0.32
0.25
4.64
2.82
0.57
3.49
22.86
7.56
6.86
9.78
0.14
0.2
2.59
0.016
0.050
0.010
0.008
0.175
0.091
0.015
0.125
0.880
0.285
0.255
0.345
0.130
0.190
0.021
0.060
0.015
0.012
0.190
0.131
0.030
0.150
0.920
0.310
0.285
0.425
0.150
0.210
0.53
1.52
0.38
0.30
4.83
3.33
0.76
3.81
23.37
7.87
7.24
10.80
0.15
0.21
1.27
0.25
0.20
4.45
2.31
0.00
3.18
22.35
7.24
6.48
8.76
0.13
0.19
Package Width
Radius to Radius Width
Overall Row Spacing
Window Width
Window Length
* Controlling Parameter.
JEDEC equivalent:
MO-036 AE
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 95
PIC16C712/716
Package Type: K04-051 18-Lead Plastic Small Outline (SO) – Wide, 300 mil
E1
p
E
D
2
B
1
n
X
α
45°
L
R2
c
A
A1
R1
φ
β
L1
A2
Units
Dimension Limits
Pitch
INCHES*
NOM
0.050
18
MILLIMETERS
MIN
MAX
MIN
NOM
1.27
18
MAX
p
n
A
A1
A2
Number of Pins
Overall Pack. Height
Shoulder Height
Standoff
Molded Package Length
Molded Package Width
Outside Dimension
Chamfer Distance
Shoulder Radius
Gull Wing Radius
Foot Length
0.093
0.099
0.058
0.008
0.456
0.296
0.407
0.020
0.005
0.005
0.016
4
0.104
2.36
1.22
2.50
1.47
0.19
11.58
7.51
10.33
0.50
0.13
0.13
0.41
4
2.64
1.73
0.28
11.73
7.59
10.64
0.74
0.25
0.25
0.53
8
0.048
0.004
0.450
0.292
0.394
0.010
0.005
0.005
0.011
0
0.068
0.011
0.462
0.299
0.419
0.029
0.010
0.010
0.021
8
0.10
11.43
7.42
10.01
0.25
0.13
0.13
0.28
0
‡
D
E
‡
E1
X
R1
R2
L
Foot Angle
φ
Radius Centerline
Lead Thickness
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
*
L1
c
B
α
β
0.010
0.009
0.014
0
0.015
0.011
0.017
12
0.020
0.012
0.019
15
0.25
0.23
0.36
0
0.38
0.27
0.42
12
0.51
0.30
0.48
15
†
0
12
15
0
12
15
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent: MS-013 AB
DS41106A-page 96
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
Package Type: K04-072 20-Lead Plastic Shrink Small Outine (SS) – 5.30 mm
E1
E
p
D
B
2
1
n
α
L
R2
c
A
A1
R1
φ
L1
A2
β
Units
Dimension Limits
Pitch
INCHES
NOM
0.026
MILLIMETERS*
MIN
MAX
MIN
NOM
0.65
20
MAX
p
n
A
A1
A2
D
E
E1
R1
R2
L
Number of Pins
Overall Pack. Height
Shoulder Height
Standoff
Molded Package Length
Molded Package Width
Outside Dimension
Shoulder Radius
Gull Wing Radius
Foot Length
20
0.073
0.036
0.005
0.283
0.208
0.306
0.005
0.005
0.020
4
0.068
0.078
1.73
0.66
1.86
0.91
0.13
7.20
5.29
7.78
0.13
0.13
0.51
4
1.99
0.026
0.002
0.278
0.205
0.301
0.005
0.005
0.015
0
0.046
0.008
0.289
0.212
0.311
0.010
0.010
0.025
8
1.17
0.21
7.33
5.38
7.90
0.25
0.25
0.64
8
0.05
7.07
5.20
7.65
0.13
0.13
0.38
0
‡
‡
Foot Angle
φ
Radius Centerline
Lead Thickness
Lower Lead Width
Mold Draft Angle Top
L1
c
B
α
β
0.000
0.005
0.010
0
0.005
0.007
0.012
5
0.010
0.009
0.015
10
0.00
0.13
0.25
0
0.13
0.18
0.32
5
0.25
0.22
0.38
10
†
Mold Draft Angle Bottom
0
5
10
0
5
10
*
Controlling Parameter.
†
‡
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent: MO-150 AE
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 97
PIC16C712/716
NOTES:
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 98
PIC16C712/716
11. Two separate timers, Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) are
included for more reliable power-up. These tim-
ers are invoked selectively to avoid unnecessary
delays on power-up and wake-up.
APPENDIX A: REVISION HISTORY
Version Date
Revision Description
A
2/99 This is a new data sheet. However,
the devices described in this data
sheet are the upgrades to the
12. PORTB has weak pull-ups and interrupt on
change feature.
13. T0CKI pin is also a port pin (RA4) now.
14. FSR is made a full eight bit register.
devices found in the PIC16C6X
Data Sheet, DS30234, and the
PIC16C7X Data Sheet, DS30390.
15. “In-circuit serial programming” is made possible.
The user can program PIC16CXX devices using
only five pins: VDD, VSS, MCLR/VPP, RB6 (clock)
and RB7 (data in/out).
APPENDIX B: CONVERSION
CONSIDERATIONS
16. PCON status register is added with a Power-on
Reset status bit (POR).
There are no previous versions of this device.
17. Code protection scheme is enhanced such that
portions of the program memory can be pro-
tected, while the remainder is unprotected.
APPENDIX C: MIGRATION FROM
BASE-LINE TO
MID-RANGE DEVICES
This section discusses how to migrate from a baseline
device (i.e., PIC16C5X) to a mid-range device (i.e.,
PIC16CXXX).
18. Brown-out protection circuitry has been added.
Controlled by configuration word bit BODEN.
Brown-out reset ensures the device is placed in
a reset condition if VDD dips below a fixed set-
point.
To convert code written for PIC16C5X to PIC16CXXX,
the user should take the following steps:
The following are the list of modifications over the
PIC16C5X microcontroller family:
1. Remove any program memory page select
operations (PA2, PA1, PA0 bits) for CALL, GOTO.
1. Instruction word length is increased to 14-bits.
This allows larger page sizes both in program
memory (2K now as opposed to 512 before) and
register file (128 bytes now versus 32 bytes
before).
2. Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
3. Eliminate any data memory page switching.
Redefine data variables to reallocate them.
2. A PC high latch register (PCLATH) is added to
handle program memory paging. Bits PA2, PA1,
PA0 are removed from STATUS register.
4. Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
5. Change reset vector to 0000h.
3. Data memory paging is redefined slightly.
STATUS register is modified.
4. Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW.
Two instructions TRIS and OPTION are being
phased out although they are kept for compati-
bility with PIC16C5X.
5. OPTION_REG and TRIS registers are made
addressable.
6. Interrupt capability is added. Interrupt vector is
at 0004h.
7. Stack size is increased to 8 deep.
8. Reset vector is changed to 0000h.
9. Reset of all registers is revisited. Five different
reset (and wake-up) types are recognized. Reg-
isters are reset differently.
10. Wake up from SLEEP through interrupt is
added.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 99
PIC16C712/716
NOTES:
DS41106A-page 100
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
Code Protection ........................................................... 51, 65
CP1:CP0 Bits ............................................................. 52
Compare (CCP Module) .................................................... 41
Block Diagram ........................................................... 41
CCP Pin Configuration .............................................. 41
CCPR1H:CCPR1L Registers .................................... 41
Software Interrupt ...................................................... 41
Special Event Trigger .................................... 34, 41, 50
Timer1 Mode Selection .............................................. 41
Configuration Bits .............................................................. 51
Conversion Considerations ................................................ 99
INDEX
A
A/D ..................................................................................... 45
A/D Converter Enable (ADIE Bit) ............................... 16
A/D Converter Flag (ADIF Bit) ............................. 17, 47
A/D Converter Interrupt, Configuring ......................... 47
ADCON0 Register ................................................ 11, 45
ADCON1 Register .......................................... 12, 45, 46
ADRES Register ............................................ 11, 45, 47
Analog Port Pins, Configuring .................................... 49
Block Diagram ............................................................ 47
Block Diagram, Analog Input Model ........................... 48
Channel Select (CHS2:CHS0 Bits) ............................ 45
Clock Select (ADCS1:ADCS0 Bits) ............................ 45
Configuring the Module .............................................. 47
Conversion Clock (TAD) ............................................. 49
Conversion Status (GO/DONE Bit) ...................... 45, 47
Conversions ............................................................... 50
Converter Characteristics .......................................... 88
Module On/Off (ADON Bit) ......................................... 45
Port Configuration Control (PCFG2:PCFG0 Bits) ...... 46
Sampling Requirements ............................................. 48
Special Event Trigger (CCP) ................................ 41, 50
Timing Diagram .......................................................... 89
Absolute Maximum Ratings ............................................... 75
ADCON0 Register ........................................................ 11, 45
ADCS1:ADCS0 Bits ................................................... 45
ADON Bit ................................................................... 45
CHS2:CHS0 Bits ........................................................ 45
GO/DONE Bit ....................................................... 45, 47
ADCON1 Register .................................................. 12, 45, 46
PCFG2:PCFG0 Bits ................................................... 46
ADRES Register .................................................... 11, 45, 47
Architecture
D
Data Memory ..................................................................... 10
Bank Select (RP1:RP0 Bits) ................................ 10, 13
General Purpose Registers ....................................... 10
Register File Map ...................................................... 10
Special Function Registers ........................................ 11
DC Characteristics ....................................................... 77, 79
Development Support ........................................................ 69
Development Tools ............................................................ 69
Direct Addressing .............................................................. 20
E
Electrical Characteristics ................................................... 75
Errata ................................................................................... 3
External Power-on Reset Circuit ........................................ 55
F
Family of Devices
PIC16C7XX ................................................................. 2
Firmware Instructions ........................................................ 67
Fuzzy Logic Dev. System (fuzzyTECH -MP) ................... 71
I
I/O Ports ............................................................................ 21
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ........... 69
ID Locations ................................................................. 51, 65
In-Circuit Serial Programming (ICSP) .......................... 51, 65
Indirect Addressing ............................................................ 20
FSR Register ................................................. 10, 11, 20
INDF Register ............................................................ 11
Instruction Format .............................................................. 67
Instruction Set .................................................................... 67
Summary Table ......................................................... 68
INTCON Register ......................................................... 11, 15
GIE Bit ....................................................................... 15
INTE Bit ..................................................................... 15
INTF Bit ..................................................................... 15
PEIE Bit ..................................................................... 15
RBIE Bit ..................................................................... 15
RBIF Bit ............................................................... 15, 24
T0IE Bit ...................................................................... 15
T0IF Bit ...................................................................... 15
Interrupt Sources ......................................................... 51, 61
A/D Conversion Complete ......................................... 47
Block Diagram ........................................................... 61
Capture Complete (CCP) .......................................... 40
Compare Complete (CCP) ........................................ 41
Interrupt on Change (RB7:RB4 ) ............................... 24
RB0/INT Pin, External ............................................... 62
TMR0 Overflow .................................................... 30, 62
TMR1 Overflow .................................................... 31, 34
TMR2 to PR2 Match .................................................. 37
TMR2 to PR2 Match (PWM) ................................ 36, 42
Interrupts, Context Saving During ...................................... 62
Interrupts, Enable Bits
PIC16C62B/PIC16C72A Block Diagram ...................... 5
Assembler
MPASM Assembler .................................................... 71
B
Banking, Data Memory ................................................ 10, 13
Brown-Out Detect (BOD) ................................................... 55
Brown-out Reset (BOR) ................................... 51, 54, 58, 59
BOR Enable (BODEN Bit) .......................................... 52
BOR Status (BOR Bit) ................................................ 18
Timing Diagram .......................................................... 85
C
Capture (CCP Module) ...................................................... 40
Block Diagram ............................................................ 40
CCP Pin Configuration ............................................... 40
CCPR1H:CCPR1L Registers ..................................... 40
Changing Between Capture Prescalers ..................... 40
Software Interrupt ...................................................... 40
Timer1 Mode Selection .............................................. 40
Capture/Compare/PWM (CCP) .......................................... 39
CCP1CON Register ............................................. 11, 39
CCPR1H Register ................................................ 11, 39
CCPR1L Register ................................................ 11, 39
Enable (CCP1IE Bit) .................................................. 16
Flag (CCP1IF Bit) ....................................................... 17
Timer Resources ........................................................ 39
Timing Diagram .......................................................... 87
CCP1CON Register ........................................................... 39
CCP1M3:CCP1M0 Bits .............................................. 39
CCP1X:CCP1Y Bits ................................................... 39
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 101
PIC16C712/716
A/D Converter Enable (ADIE Bit) ...............................16
CCP1 Enable (CCP1IE Bit) .................................. 16, 40
Global Interrupt Enable (GIE Bit) ......................... 15, 61
Interrupt on Change (RB7:RB4)
Pin Functions
MCLR/Vpp ................................................................... 6
RA0/AN0 ...................................................................... 6
RA1/AN1 ...................................................................... 6
RA2/AN2 ...................................................................... 6
RA3/AN3/Vref .............................................................. 6
RA4/T0CKI .................................................................. 6
RB0/INT ....................................................................... 7
RB1 .............................................................................. 7
RB2 .............................................................................. 7
RB3 .............................................................................. 7
RB4 .............................................................................. 7
RB5 .............................................................................. 7
RB6 .............................................................................. 7
RB7 .............................................................................. 7
Vdd .............................................................................. 7
Vss ............................................................................... 7
Enable (RBIE Bit) ................................................. 15, 62
Peripheral Interrupt Enable (PEIE Bit) .......................15
RB0/INT Enable (INTE Bit) ........................................15
TMR0 Overflow Enable (T0IE Bit) ..............................15
TMR1 Overflow Enable (TMR1IE Bit) ........................16
TMR2 to PR2 Match Enable (TMR2IE Bit) ................16
Interrupts, Flag Bits
A/D Converter Flag (ADIF Bit) ............................. 17, 47
CCP1 Flag (CCP1IF Bit) ................................ 17, 40, 41
Interrupt on Change (RB7:RB4)
Flag (RBIF Bit) ............................................... 15, 24, 62
RB0/INT Flag (INTF Bit) .............................................15
TMR0 Overflow Flag (T0IF Bit) ............................ 15, 62
TMR1 Overflow Flag (TMR1IF Bit) ............................17
TMR2 to PR2 Match Flag (TMR2IF Bit) .....................17
Pinout Descriptions
PIC16C62B/PIC16C72A .............................................. 6
PIR1 Register .............................................................. 11, 17
ADIF Bit ..................................................................... 17
CCP1IF Bit ................................................................. 17
TMR1IF Bit ................................................................. 17
TMR2IF Bit ................................................................. 17
Pointer, FSR ...................................................................... 20
PORTA
Initialization ................................................................ 21
PORTA Register .................................................. 11, 21
RA3:RA0 and RA5 Port Pins ..................................... 21
RA4/T0CKI Pin .......................................................... 22
TRISA Register .................................................... 12, 21
PORTB
K
KeeLoq Evaluation and Programming Tools ...................72
M
Master Clear (MCLR)
MCLR Reset, Normal Operation ....................54, 58, 59
MCLR Reset, SLEEP .....................................54, 58, 59
Memory Organization
Data Memory .............................................................10
Program Memory .........................................................9
MPLAB Integrated Development Environment Software ...71
O
Initialization ................................................................ 23
PORTB Register .................................................. 11, 23
Pull-up Enable (RBPU Bit) ......................................... 14
RB0/INT Edge Select (INTEDG Bit) .......................... 14
RB0/INT Pin, External ................................................ 62
RB3:RB0 Port Pins .................................................... 23
RB7:RB4 Interrupt on Change ................................... 62
RB7:RB4 Interrupt on Change Enable (RBIE Bit) 15, 62
RB7:RB4 Interrupt on Change
OPCODE Field Descriptions ..............................................67
OPTION_REG Register ...............................................12, 14
INTEDG Bit ................................................................14
PS2:PS0 Bits ....................................................... 14, 29
PSA Bit ................................................................. 14, 29
RBPU Bit ....................................................................14
T0CS Bit ............................................................... 14, 29
T0SE Bit ............................................................... 14, 29
Oscillator Configuration ................................................ 51, 53
HS ........................................................................ 53, 58
LP ......................................................................... 53, 58
RC .................................................................. 53, 54, 58
Selection (FOSC1:FOSC0 Bits) .................................52
XT ........................................................................ 53, 58
Oscillator, Timer1 ......................................................... 31, 34
Oscillator, WDT ..................................................................63
Flag (RBIF Bit) ............................................... 15, 24, 62
RB7:RB4 Port Pins .................................................... 26
TRISB Register .................................................... 12, 23
PORTC
Block Diagram ..................................................... 24, 25
TRISC Register .......................................................... 12
Postscaler, Timer2
Select (TOUTPS3:TOUTPS0 Bits) ............................ 36
Postscaler, WDT ................................................................ 29
Assignment (PSA Bit) .......................................... 14, 29
Block Diagram ........................................................... 30
Rate Select (PS2:PS0 Bits) ................................. 14, 29
Switching Between Timer0 and WDT ........................ 30
Power-on Reset (POR) .............................. 51, 54, 55, 58, 59
Oscillator Start-up Timer (OST) ........................... 51, 55
POR Status (POR Bit) ............................................... 18
Power Control (PCON) Register ................................ 57
Power-down (PD Bit) ........................................... 13, 54
Power-on Reset Circuit, External ............................... 55
Power-up Timer (PWRT) ..................................... 51, 55
PWRT Enable (PWRTE Bit) ...................................... 52
Time-out (TO Bit) ................................................. 13, 54
Time-out Sequence ................................................... 57
Time-out Sequence on Power-up .............................. 60
Timing Diagram ......................................................... 85
P
Packaging ..........................................................................93
Paging, Program Memory ..............................................9, 19
PCON Register ............................................................ 18, 57
BOR Bit ......................................................................18
POR Bit ......................................................................18
PICDEM-1 Low-Cost PICmicro Demo Board .....................70
PICDEM-2 Low-Cost PIC16CXX Demo Board ..................70
PICDEM-3 Low-Cost PIC16CXXX Demo Board ................70
PICSTART Plus Entry Level Development System ........69
PIE1 Register ............................................................... 12, 16
ADIE Bit .....................................................................16
CCP1IE Bit .................................................................16
TMR1IE Bit .................................................................16
TMR2IE Bit .................................................................16
DS41106A-page 102
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
Prescaler, Capture ............................................................. 40
Prescaler, Timer0 ............................................................... 29
Assignment (PSA Bit) .......................................... 14, 29
Block Diagram ............................................................ 30
Rate Select (PS2:PS0 Bits) ................................. 14, 29
Switching Between Timer0 and WDT ........................ 30
Prescaler, Timer1 ............................................................... 32
Select (T1CKPS1:T1CKPS0 Bits) .............................. 31
Prescaler, Timer2 ............................................................... 42
Select (T2CKPS1:T2CKPS0 Bits) .............................. 36
PRO MATE II Universal Programmer ............................. 69
Product Identification System .......................................... 107
Program Counter
PCL Register ........................................................ 11, 19
PCLATH Register .......................................... 11, 19, 62
Reset Conditions ........................................................ 58
Program Memory ................................................................. 9
Interrupt Vector ............................................................ 9
Paging .................................................................... 9, 19
Program Memory Map ................................................. 9
Reset Vector ................................................................ 9
Program Verification .......................................................... 65
Programming, Device Instructions ..................................... 67
PWM (CCP Module) .......................................................... 42
Block Diagram ............................................................ 42
CCPR1H:CCPR1L Registers ..................................... 42
Duty Cycle .................................................................. 42
Example Frequencies/Resolutions ............................ 43
Output Diagram .......................................................... 42
Period ......................................................................... 42
Set-Up for PWM Operation ........................................ 43
TMR2 to PR2 Match ............................................ 36, 42
TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 16
TMR2 to PR2 Match Flag (TMR2IF Bit) ..................... 17
T
T1CON Register .......................................................... 11, 31
T1CKPS1:T1CKPS0 Bits ........................................... 31
T1OSCEN Bit ............................................................ 31
T1SYNC Bit ............................................................... 31
TMR1CS Bit ............................................................... 31
TMR1ON Bit .............................................................. 31
T2CON Register .......................................................... 11, 36
T2CKPS1:T2CKPS0 Bits ........................................... 36
TMR2ON Bit .............................................................. 36
TOUTPS3:TOUTPS0 Bits ......................................... 36
Timer0 ............................................................................... 29
Block Diagram ........................................................... 29
Clock Source Edge Select (T0SE Bit) ................. 14, 29
Clock Source Select (T0CS Bit) .......................... 14, 29
Overflow Enable (T0IE Bit) ........................................ 15
Overflow Flag (T0IF Bit) ...................................... 15, 62
Overflow Interrupt ................................................ 30, 62
Timing Diagram ......................................................... 86
TMR0 Register .......................................................... 11
Timer1 ............................................................................... 31
Block Diagram ........................................................... 32
Capacitor Selection ................................................... 34
Clock Source Select (TMR1CS Bit) ........................... 31
External Clock Input Sync (T1SYNC Bit) ................... 31
Module On/Off (TMR1ON Bit) ................................... 31
Oscillator .............................................................. 31, 34
Oscillator Enable (T1OSCEN Bit) .............................. 31
Overflow Enable (TMR1IE Bit) .................................. 16
Overflow Flag (TMR1IF Bit) ....................................... 17
Overflow Interrupt ................................................ 31, 34
Special Event Trigger (CCP) ............................... 34, 41
T1CON Register .................................................. 11, 31
Timing Diagram ......................................................... 86
TMR1H Register .................................................. 11, 31
TMR1L Register .................................................. 11, 31
Timer2
Q
Q-Clock .............................................................................. 42
Block Diagram ........................................................... 36
PR2 Register ................................................. 12, 36, 42
T2CON Register .................................................. 11, 36
TMR2 Register .................................................... 11, 36
TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 16
TMR2 to PR2 Match Flag (TMR2IF Bit) .................... 17
TMR2 to PR2 Match Interrupt ........................ 36, 37, 42
Timing Diagrams
Time-out Sequence on Power-up .............................. 60
Wake-up from SLEEP via Interrupt ........................... 65
Timing Diagrams and Specifications ................................. 83
A/D Conversion ......................................................... 89
Brown-out Reset (BOR) ............................................. 85
Capture/Compare/PWM (CCP) ................................. 87
CLKOUT and I/O ....................................................... 84
External Clock ........................................................... 83
Oscillator Start-up Timer (OST) ................................. 85
Power-up Timer (PWRT) ........................................... 85
Reset ......................................................................... 85
Timer0 and Timer1 .................................................... 86
Watchdog Timer (WDT) ............................................. 85
R
RAM. See Data Memory
Register File ....................................................................... 10
Register File Map ............................................................... 10
Reset ............................................................................ 51, 54
Block Diagram ............................................................ 56
Reset Conditions for All Registers ............................. 59
Reset Conditions for PCON Register ......................... 58
Reset Conditions for Program Counter ...................... 58
Reset Conditions for STATUS Register ..................... 58
Timing Diagram .......................................................... 85
Revision History ................................................................. 99
S
SEEVAL Evaluation and Programming System .............. 71
SLEEP ................................................................... 51, 54, 64
Software Simulator (MPLAB-SIM) ..................................... 71
Special Features of the CPU ............................................. 51
Special Function Registers ................................................ 11
Speed, Operating ................................................................. 1
Stack .................................................................................. 19
STATUS Register .................................................. 11, 13, 62
C Bit ........................................................................... 13
DC Bit ......................................................................... 13
IRP Bit ........................................................................ 13
PD Bit ................................................................... 13, 54
RP1:RP0 Bits ............................................................. 13
TO Bit ................................................................... 13, 54
Z Bit ............................................................................ 13
W
W Register ......................................................................... 62
Wake-up from SLEEP .................................................. 51, 64
Interrupts ............................................................. 58, 59
MCLR Reset .............................................................. 59
Timing Diagram ......................................................... 65
WDT Reset ................................................................ 59
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 103
PIC16C712/716
Watchdog Timer (WDT) ...............................................51, 63
Block Diagram ............................................................63
Enable (WDTE Bit) ...............................................52, 63
Programming Considerations ....................................63
RC Oscillator ..............................................................63
Time-out Period .........................................................63
Timing Diagram ..........................................................85
WDT Reset, Normal Operation ...................... 54, 58, 59
WDT Reset, SLEEP .......................................54, 58, 59
WWW, On-Line Support .......................................................3
DS41106A-page 104
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip’s development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-786-7302 for the rest of the world.
981103
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
Trademarks: The Microchip name, logo, PIC, PICmicro,
PICSTART, PICMASTER and PRO MATE are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries. FlexROM, MPLAB and fuzzy-
LAB are trademarks and SQTP is a service mark of Micro-
chip in the U.S.A.
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
All other trademarks mentioned herein are the property of
their respective companies.
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Sys-
tems, technical information and more
• Listing of seminars and events
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 105
PIC16C712/716
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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RE:
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FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
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Literature Number:
DS41106A
Device:
PIC16C712/716
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS41106A-page 106
Preliminary
1999 Microchip Technology Inc.
PIC16C712/716
PIC16C712/716 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X
/XX
XXX
PART NO.
Device
-XX
Examples:
Frequency Temperature Package
Range Range
Pattern
a) PIC16C716 - 04/P 301 = Commercial temp.,
PDIP package, 4 MHz, normal VDD limits, QTP
pattern #301.
b)
PIC16LC712 - 04I/SO = Industrial temp., SOIC
package, 200 kHz, Extended VDD limits.
Device
PIC16C712(1), PIC16C712T(2);VDD range 4.0V to 5.5V
PIC16LC712(1), PIC16LC712T(2);VDD range 2.5V to 5.5V
PIC16C716(1), PIC16C716T(2);VDD range 4.0V to 5.5V
PIC16LC716(1), PIC16LC716T(2);VDD range 2.5V to 5.5V
c)
PIC16C712 - 20I/P = Industrial temp., PDIP
package, 20MHz, normal VDD limits.
Frequency Range
04
20
= 4 MHz
= 20 MHz
Note 1:
C
= CMOS
LC = Low Power CMOS
2:
3:
4:
T
= in tape and reel - SOIC, SSOP
packages only.
LC extended temperature device is not
offered.
LC is not offered at 20 MHz
Temperature Range
blank
I
E
=
=
=
0°C to
70°C (Commercial)
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
Package
Pattern
JW
SO
P
=
=
=
=
Windowed CERDIP
SOIC
PDIP
SSOP
SS
QTP, SQTP, Code or Special Requirements
(blank otherwise)
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type (including LC devices).
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 107
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
ASIA/PACIFIC (continued)
Corporate Office
Toronto
Singapore
Microchip Technology Inc.
Microchip Technology Inc.
Microchip Technology Singapore Pte Ltd.
200 Middle Road
2355 West Chandler Blvd.
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Tel: 480-786-7200 Fax: 480-786-7277
Technical Support: 480-786-7627
Web Address: http://www.microchip.com
5925 Airport Road, Suite 200
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Tel: 905-405-6279 Fax: 905-405-6253
#07-02 Prime Centre
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Tel: 65-334-8870 Fax: 65-334-8850
Taiwan, R.O.C
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific
Unit 2101, Tower 2
Atlanta
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Beijing
United Kingdom
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Batiment A - ler Etage
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Germany
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Shanghai
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Italy
Los Angeles
Arizona Microchip Technology SRL
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Microchip Technology Inc.
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Tel: 949-263-1888 Fax: 949-263-1338
New York
Microchip Technology Inc.
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Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
11/15/99
San Jose
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.
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