PIC16LC717-E/P [MICROCHIP]
8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PDIP18, 0.300 INCH, PLASTIC, MS-001, DIP-18;
| 型号： | PIC16LC717-E/P |
| 厂家： | 
MICROCHIP |
| 描述： | 8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PDIP18, 0.300 INCH, PLASTIC, MS-001, DIP-18 可编程只读存储器 光电二极管 |
| 文件： | 总220页 (文件大小：3585K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M
PIC16C717/770/771
Data Sheet
18/20-Pin, 8-Bit CMOS Microcontrollers
with 10/12-bit A/D
2002 Microchip Technology Inc.
DS41120B
®
Note the following details of the code protection feature on PICmicro MCUs.
•
•
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
•
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, MPLAB, PIC, PICmicro, PICMASTER, PICSTART,
PRO MATE, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microID,
microPort, Migratable Memory, MPASM, MPLIB, MPLINK,
MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select
Mode and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A.
Serialized Quick Term Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
DS41120B - page ii
2002 Microchip Technology Inc.
PIC16C717/770/771
18/20-Pin, 8-Bit CMOS Microcontrollers with 10/12-Bit A/D
M
Microcontroller Core Features:
Pin Diagram
20-Pin PDIP, SOIC, SSOP
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
20
19
18
17
16
15
14
13
1
2
RB3/CCP1/P1A
RB2/SCK/SCL
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD
RA0/AN0
RA1/AN1/LVDIN
3
RA4/T0CKI
RA5/MCLR/VPP
4
VSS
AVSS
5
Memory
AVDD
6
A/D
A/D
Device
Pins
RB7/T1OSI/P1D
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RB0/AN4/INT
7
Program Data
Resolution Channels
x14
2K
2K
4K
x8
8
RB6/T1OSO/T1CKI/P1C
RB5/SDO/P1B
12
11
9
PIC16C717
PIC16C770
PIC16C771
256 18, 20
10 bits
12 bits
12 bits
6
6
6
10
RB4/SDI/SDA
RB1/AN5/SS
256
256
20
20
Peripheral Features:
• Interrupt capability (up to 10 internal/external
interrupt sources)
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during SLEEP via external
crystal/clock
• Eight level deep hardware stack
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Enhanced Capture, Compare, PWM (ECCP)
module
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
- Enhanced PWM:
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Selectable oscillator options:
- INTRC - Internal RC, dual speed (4 MHz and
37 kHz nominal) dynamically switchable for
power savings
- ER - External resistor, dual speed (user
selectable frequency and 37 kHz nominal)
dynamically switchable for power savings
- EC - External clock
- Single, Half-Bridge and Full-Bridge Output
modes
- Digitally programmable deadband delay
• Analog-to-Digital converter:
- PIC16C770/771 12-bit resolution
- PIC16C717 10-bit resolution
- HS - High speed crystal/resonator
- XT - Crystal/resonator
- LP - Low power crystal
• On-chip absolute bandgap voltage reference
generator
• Low power, high speed CMOS EPROM
technology
• Programmable Brown-out Reset (PBOR)
circuitry
• In-Circuit Serial Programming™ (ICSP™)
• Wide operating voltage range: 2.5V to 5.5V
• Programmable Low-Voltage Detection (PLVD)
circuitry
• 15 I/O pins with individual control for:
- Direction (15 pins)
• Master Synchronous Serial Port (MSSP) with two
modes of operation:
- Digital/Analog input (6 pins)
- PORTB interrupt on change (8 pins)
- PORTB weak pull-up (8 pins)
- High voltage open drain (1 pin)
- 3-wire SPI™ (supports all 4 SPI modes)
- I2C™ compatible including Master mode
support
• Program Memory Read (PMR) capability for look-
up table, character string storage and checksum
calculation purposes
• Commercial and Industrial temperature ranges
• Low power consumption:
- < 2 mA @ 4V, 4 MHz
- 11 µA typical @ 2.5V, 37 kHz
- < 1 µA typical standby current
2002 Microchip Technology Inc.
DS41120B-page 1
PIC16C717/770/771
Pin Diagrams
18-Pin PDIP, SOIC
20-Pin SSOP
RA0/AN0
20
19
18
17
16
15
14
13
1
2
RB3/CCP1/P1A
RB2/SCK/SCL
18
17
16
15
14
13
12
11
10
RA0/AN0
1
2
3
4
5
6
7
8
9
RB3/CCP1/P1A
RB2/SCK/SCL
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD
RA1/AN1/LVDIN
RA1/AN1/LVDIN
RA4/T0CKI
3
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
RA4/T0CKI
RA5/MCLR/VPP
4
RA5/MCLR/VPP
(1)
(2)
VSS
VDD
5
VSS
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RB0/AN4/INT
(1)
(2)
VSS
VDD
6
RB7/T1OSI/P1D
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RB0/AN4/INT
RB7/T1OSI/P1D
RB6/T1OSO/T1CKI/P1C
RB5/SDO/P1B
7
RB6/T1OSO/T1CKI/P1C
RB5/SDO/P1B
8
9
12
11
RB1/AN5/SS
RB4/SDI/SDA
RB1/AN5/SS
10
RB4/SDI/SDA
Note 1: VSS pins 5 and 6 must be tied together.
2: VDD pins 15 and 16 must be tied together.
Key Features
PICmicroTM Mid-Range MCU Family
Reference Manual, (DS33023)
PIC16C717
PIC16C770
PIC16C771
Operating Frequency
RESETS (and Delays)
DC - 20 MHz
DC - 20 MHz
DC - 20 MHz
POR, BOR, MCLR,
WDT (PWRT, OST)
POR, BOR, MCLR,
WDT (PWRT, OST)
POR, BOR, MCLR,
WDT (PWRT, OST)
Program Memory (14-bit words)
Data Memory (bytes)
Interrupts
2K
2K
4K
256
256
256
10
10
10
I/O Ports
Ports A,B
Ports A,B
Ports A,B
Timers
3
1
3
1
3
1
Enhanced Capture/Compare/PWM (ECCP)
modules
Serial Communications
MSSP
MSSP
MSSP
12-bit Analog-to-Digital Module
6 input channels
6 input channels
–
10-bit Analog-to-Digital Module
Instruction Set
6 input channels
35 Instructions
–
–
35 Instructions
35 Instructions
DS41120B-page 2
2002 Microchip Technology Inc.
PIC16C717/770/771
Table of Contents
1.0 Device Overview ...................................................................................................................................................... 5
2.0 Memory Organization............................................................................................................................................... 9
3.0 I/O Ports................................................................................................................................................................. 25
4.0 Program Memory Read (PMR) .............................................................................................................................. 41
5.0 Timer0 Module....................................................................................................................................................... 45
6.0 Timer1 Module....................................................................................................................................................... 47
7.0 Timer2 Module....................................................................................................................................................... 51
8.0 Enhanced Capture/Compare/PWM (ECCP) Modules............................................................................................ 53
9.0 Master Synchronous Serial Port (MSSP) Module.................................................................................................. 65
10.0 Voltage Reference Module and Low-voltage Detect.......................................................................................... 101
11.0 Analog-to-Digital Converter (A/D) Module.......................................................................................................... 105
12.0 Special Features of the CPU ............................................................................................................................. 117
13.0 Instruction Set Summary.................................................................................................................................... 133
14.0 Development Support ........................................................................................................................................ 141
15.0 Electrical Characteristics.................................................................................................................................... 147
16.0 DC and AC Characteristics Graphs and Tables................................................................................................. 179
17.0 Packaging Information ....................................................................................................................................... 197
APPENDIX A: Revision History ............................................................................................................................... 207
APPENDIX B: Device Differences ............................................................................................................................ 208
Index .......................................................................................................................................................................... 209
On-Line Support.......................................................................................................................................................... 215
Reader Response....................................................................................................................................................... 216
PIC16C717/770/771 Product Identification System.................................................................................................... 217
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It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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We welcome your feedback.
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
•
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•
Microchip’s Worldwide Web site; http://www.microchip.com
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2002 Microchip Technology Inc.
DS41120B-page 3
PIC16C717/770/771
NOTES:
DS41120B-page 4
2002 Microchip Technology Inc.
PIC16C717/770/771
sheet, and is highly recommended reading for a better
understanding of the device architecture and operation
of the peripheral modules.
1.0
DEVICE OVERVIEW
This document contains device-specific information.
Additional information may be found in the PICmicroTM
Mid-Range MCU Family Reference Manual,
(DS33023), which may be obtained from your local
Microchip Sales Representative or downloaded from
the Microchip website. The Reference Manual should
be considered a complementary document to this data
There are three devices (PIC16C717, PIC16C770 and
PIC16C771) covered by this data sheet. The
PIC16C717 device comes in 18/20-pin packages and
the PIC16C770/771 devices come in 20-pin packages.
The following two figures are device block diagrams of
the PIC16C717 and the PIC16C770/771.
FIGURE 1-1:
PIC16C717 BLOCK DIAGRAM
13
8
PORTA
Data Bus
Program Counter
EPROM
RA0/AN0
RA1/AN1/LVDIN
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RA4/T0CKI
RA5/MCLR/VPP
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
Program
Memory
RAM
File
Registers
8 Level Stack
(13-bit)
2K x 14
256 x 8
Program
Bus
14
Program Memory
Read (PMR)
RAM
Addr(1)
9
Addr MUX
Instruction reg
PORTB
7
Indirect
Addr
RB0/AN4/INT
RB1/AN5/SS
Direct Addr
8
RB2/SCK/SCL
RB3/CCP1/P1A
RB4/SDI/SDA
RB5/SDO/P1B
RB6/T1OSO/T1CKI/P1C
RB7/T1OSI/P1D
FSR reg
STATUS reg
8
Internal
4 MHz, 37 kHz
and ER mode
3
MUX
Instruction
Decode &
Control
Power-up
Timer
ALU
Timing
Generation
Oscillator
Start-up Timer
8
OSC1/CLKIN
OSC2/CLKOUT
Power-on
Reset
W reg
VDD, VSS
Watchdog
Timer
Brown-out
Reset
10-bit
Bandgap
Low-voltage
ADC
Reference
Detect
Timer0
Timer1
Timer2
Master
Synchronous
Serial Port (MSSP)
Enhanced CCP
(ECCP)
Note 1: Higher order bits are from the STATUS register.
2002 Microchip Technology Inc.
DS41120B-page 5
PIC16C717/770/771
FIGURE 1-2:
PIC16C770/771 BLOCK DIAGRAM
13
8
PORTA
Data Bus
Program Counter
RA0/AN0
EPROM
RA1/AN1/LVDIN
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RA4/T0CKI
RA5/MCLR/VPP
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
Program
RAM
File
Registers
Memory(2)
8 Level Stack
(13-bit)
256 x 8
Program
Bus
14
Program Memory
Read (PMR)
RAM
Addr(1)
9
Addr MUX
Instruction reg
PORTB
7
Indirect
Addr
Direct Addr
RB0/AN4/INT
RB1/AN5/SS
8
RB2/SCK/SCL
RB3/CCP1/P1A
RB4/SDI/SDA
RB5/SDO/P1B
RB6/T1OSO/T1CKI/P1C
RB7/T1OSI/P1D
FSR reg
STATUS reg
8
Internal
4 MHz, 37 kHz
and ER mode
3
MUX
Instruction
Decode &
Control
Power-up
Timer
ALU
Timing
Generation
Oscillator
Start-up Timer
8
OSC1/CLKIN
OSC2/CLKOUT
Power-on
Reset
W reg
VDD, VSS
Watchdog
Timer
Brown-out
Reset
AVDD
AVSS
12-bit
ADC
Bandgap
Reference
Low-voltage
Detect
Timer0
Timer1
Timer2
Master
Synchronous
Serial Port (MSSP)
Enhanced CCP
(ECCP)
Note 1: Higher order bits are from the STATUS register.
2: Program memory for PIC16C770 is 2K x 14. Program memory for PIC16C771 is 4K x 14.
DS41120B-page 6
2002 Microchip Technology Inc.
PIC16C717/770/771
TABLE 1-1:
Name
PIC16C717/770/771 PINOUT DESCRIPTION
Input
Type
Output
Type
Function
Description
RA0
AN0
ST
AN
ST
AN
AN
ST
AN
AN
CMOS
Bi-directional I/O
RA0/AN0
A/D input
RA1
CMOS
Bi-directional I/O
RA1/AN1/LVDIN
AN1
A/D input
LVDIN
RA2
LVD input reference
Bi-directional I/O
CMOS
AN2
A/D input
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
VREF-
VRL
Negative analog reference input
Internal voltage reference low output
Bi-directional I/O
AN
RA3
ST
AN
AN
CMOS
AN3
A/D input
VREF+
VRH
RA4
Positive analog reference input
Internal voltage reference high output
Bi-directional I/O
AN
OD
ST
ST
RA4/T0CKI
T0CKI
RA5
TMR0 clock input
ST
Input port
RA5/MCLR/VPP
MCLR
VPP
ST
Master clear
Power
ST
Programming voltage
Bi-directional I/O
RA6
CMOS
XTAL
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
RB0/AN4/INT
OSC2
CLKOUT
RA7
Crystal/resonator
CMOS
CMOS
FOSC/4 output
ST
XTAL
ST
Bi-directional I/O
OSC1
CLKIN
RB0
Crystal/resonator
External clock input/ER resistor connection
(1)
TTL
AN
CMOS
CMOS
Bi-directional I/O
AN4
A/D input
INT
ST
Interrupt input
(1)
RB1
TTL
AN
Bi-directional I/O
RB1/AN5/SS
AN5
A/D input
SS
ST
SSP slave select input
(1)
RB2
TTL
ST
CMOS
CMOS
OD
Bi-directional I/O
RB2/SCK/SCL
RB3/CCP1/P1A
RB4/SDI/SDA
SCK
SCL
Serial clock I/O for SPI
2
ST
Serial clock I/O for I C
(1)
RB3
TTL
ST
CMOS
CMOS
CMOS
CMOS
Bi-directional I/O
CCP1
P1A
Capture 1 input/Compare 1 output
PWM P1A output
(1)
RB4
TTL
ST
Bi-directional I/O
SDI
Serial data in for SPI
2
SDA
RB5
ST
OD
Serial data I/O for I C
(1)
TTL
CMOS
CMOS
CMOS
Bi-directional I/O
RB5/SDO/P1B
SDO
P1B
Serial data out for SPI
PWM P1B output
Note 1: Bit programmable pull-ups.
2: Only in PIC16C770/771 devices.
2002 Microchip Technology Inc.
DS41120B-page 7
PIC16C717/770/771
TABLE 1-1:
Name
PIC16C717/770/771 PINOUT DESCRIPTION (CONTINUED)
Input
Type
Output
Type
Function
Description
(1)
RB6
T1OSO
T1CKI
P1C
TTL
CMOS
XTAL
Bi-directional I/O
Crystal/Resonator
TMR1 clock input
PWM P1C output
RB6/T1OSO/T1CKI/P1C
RB7/T1OSI/P1D
CMOS
CMOS
CMOS
(1)
RB7
TTL
Bi-directional I/O
T1OSI
P1D
XTAL
TMR1 crystal/resonator
PWM P1D output
CMOS
VSS
VDD
VSS
Power
Power
Power
Power
Ground reference for logic and I/O pins
Positive supply for logic and I/O pins
Ground reference for analog
VDD
(2)
AVSS
AVSS
AVDD
(2)
AVDD
Positive supply for analog
Note 1: Bit programmable pull-ups.
2: Only in PIC16C770/771 devices.
DS41120B-page 8
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 2-2: PROGRAM MEMORY MAP
AND STACK OF THE
2.0
MEMORY ORGANIZATION
There are two memory blocks in each of these PICmi-
cro® microcontrollers. Each block (Program Memory
and Data Memory) has its own bus, so that concurrent
access can occur.
PIC16C771
PC<12:0>
Additional information on device memory may be found
in the PICmicro Mid-Range MCU Family Reference
Manual, (DS33023).
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
2.1
Program Memory Organization
The PIC16C717/770/771 devices have a 13-bit pro-
gram counter capable of addressing an 8K x 14 pro-
gram memory space. The PIC16C717 and the
PIC16C770 have 2K x 14 words of program memory.
The PIC16C771 has 4K x 14 words of program mem-
ory. Accessing a location above the physically imple-
mented address will cause a wrap-around.
Stack Level 8
RESET Vector
0000h
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
Interrupt Vector
Page 0
0004h
0005h
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK OF THE
On-chip
Program
Memory
07FFh
0800h
PIC16C717 AND PIC16C770
Page 1
PC<12:0>
0FFFh
1000h
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
3FFFh
Stack Level 8
2.2
Data Memory Organization
The data memory is partitioned into multiple banks,
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
RESET Vector
0000h
RP1 RP0
(STATUS<6:5>)
Interrupt Vector
Page 0
0004h
0005h
= 00 → Bank0
= 01 → Bank1
= 10 → Bank2
= 11 → Bank3
On-chip
Program
Memory
07FFh
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some frequently used special func-
tion registers from one bank are mirrored in another
bank for code reduction and quicker access.
3FFFh
2.2.1
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indi-
rectly, through the File Select Register FSR.
2002 Microchip Technology Inc.
DS41120B-page 9
PIC16C717/770/771
FIGURE 2-3: REGISTER FILE MAP
File
Address
File
Address
File
Address
File
Address
Indirect addr.(*)
TMR0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
Indirect addr.(*)
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
Indirect addr.(*)
TMR0
Indirect addr.(*)
OPTION_REG
PCL
80h
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
OPTION_REG
PCL
PCL
PCL
STATUS
FSR
STATUS
FSR
STATUS
FSR
STATUS
FSR
PORTA
PORTB
TRISA
TRISB
PORTB
TRISB
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
PCLATH
PCLATH
INTCON
PMCON1
INTCON
PMDATL
PIR2
PMADRL
PMDATH
PMADRH
PIE2
TMR1L
TMR1H
T1CON
TMR2
PCON
SSPCON2
PR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
SSPADD
SSPSTAT
WPUB
IOCB
P1DEL
REFCON
LVDCON
ANSEL
ADRESL
ADCON1
ADRESH
ADCON0
A0h
1A0h
General
Purpose
Register
80 Bytes
General
Purpose
Register
General
Purpose
Register
80 Bytes
96 Bytes
1EFh
1F0h
EFh
F0h
16Fh
170h
accesses
70h - 7Fh
accesses
70h - 7Fh
accesses
70h-7Fh
7Fh
FFh
17Fh
1FFh
Bank 0
Bank 1
Bank 2
Bank 3
Unimplemented data memory locations, read as ’0’.
*
Not a physical register.
DS41120B-page 10
2002 Microchip Technology Inc.
PIC16C717/770/771
The special function registers can be classified into two
sets; core (CPU) and peripheral. Those registers asso-
ciated with the core functions are described in detail in
this section. Those related to the operation of the
peripheral features are described in detail in that
peripheral feature section.
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY
Value on: Details
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
on
Page:
Bank 0
00h(3)
01h
INDF
TMR0
PCL
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
xxxx 0000
xxxx xx11
—
23
45
22
14
23
25
33
—
02h(3)
03h(3)
04h(3)
05h
Program Counter's (PC) Least Significant Byte
STATUS
FSR
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
PORTA
PORTB
—
RA7
RA6
RB6
RA5
RB5
RA4
RB4
RA3
RB3
RA2
RB2
RA1
RB1
RA0
RB0
06h
RB7
07h
Unimplemented
Unimplemented
Unimplemented
—
08h
—
—
—
09h
—
—
—
0Ah(1,3) PCLATH
—
—
T0IE
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
0000 000x
22
16
18
20
47
47
47
51
51
70
67
54
54
53
—
0Bh(3)
0Ch
0Dh
0Eh
0Fh
10h
11h
INTCON
PIR1
GIE
—
PEIE
ADIF
—
INTE
—
RBIE
SSPIF
BCLIF
T0IF
CCP1IF
—
INTF
TMR2IF
—
RBIF
TMR1IF -0---0000
PIR2
LVDIF
—
—
—
0--- 0---
xxxx xxxx
xxxx xxxx
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
—
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
—
—
T1CKPS1
T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON --00 0000
Timer2 module’s register
TOUTPS3 TOUTPS2
Synchronous Serial Port Receive Buffer/Transmit Register
0000 0000
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
—
TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
PWM1M1 PWM1M0
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADRESH
ADCON0
A/D High Byte Result Register
ADCS1 ADCS0 CHS2
xxxx xxxx
107
107
CHS1
CHS0
GO/DONE
CHS3
ADON
0000 0000
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
2002 Microchip Technology Inc.
DS41120B-page 11
PIC16C717/770/771
TABLE 2-1:
Address Name
Bank 1
PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on: Details
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
on
Page:
80h(3)
81h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
1111 1111
1111 1111
—
23
15
22
14
23
25
33
—
OPTION_REG RBPU
INTEDG
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO
T0CS
T0SE
PSA
PS2
PS1
PS0
82h(3)
83h(3)
84h(3)
85h
PCL
STATUS
FSR
TRISA
TRISB
—
PD
Z
DC
C
Indirect data memory address pointer
PORTA Data Direction Register
PORTB Data Direction Register
Unimplemented
86h
87h
88h
—
Unimplemented
—
—
89h
—
Unimplemented
—
—
8Ah(1,3) PCLATH
—
GIE
—
—
PEIE
ADIE
—
—
T0IE
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
0000 000x
22
16
17
19
21
—
8Bh(3)
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
INTCON
PIE1
INTE
—
RBIE
SSPIE
BCLIE
OSCF
T0IF
CCP1IE
—
INTF
TMR2IE
—
RBIF
TMR1IE -0-- 0000
PIE2
LVDIE
—
—
—
—
0--- 0---
---- 1-qq
—
PCON
—
—
—
—
—
POR
BOR
Unimplemented
Unimplemented
—
—
—
SSPCON2
PR2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
R/W
RSEN
UA
SEN
BF
0000 0000
1111 1111
0000 0000
0000 0000
1111 1111
1111 0000
0000 0000
—
69
52
76
66
34
34
62
—
Timer2 Period Register
SSPADD
SSPSTAT
WPUB
IOCB
Synchronous Serial Port (I2C mode) Address Register
SMP
CKE
D/A
P
S
PORTB Weak Pull-up Control
PORTB Interrupt on Change Control
PWM 1 Delay value
P1DEL
—
Unimplemented
—
Unimplemented
—
—
—
Unimplemented
—
—
REFCON
LVDCON
ANSEL
ADRESL
ADCON1
VRHEN
—
VRLEN
—
VRHOEN
BGST
VRLOEN
LVDEN
—
—
—
—
0000 ----
--00 0101
--11 1111
xxxx xxxx
0000 ----
102
101
25
107
107
LVV3
LVV2
LVV1
LVV0
Analog Channel Select
—
—
A/D Low Byte Result Register
ADFM VCFG2 VCFG1
VCFG0
—
—
—
—
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
DS41120B-page 12
2002 Microchip Technology Inc.
PIC16C717/770/771
TABLE 2-1:
Address Name
Bank 2
PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on: Details
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
on
Page:
100h(3)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000
xxxx xxxx
0000 0000
23
45
22
101h
TMR0
PCL
102h(3)
103h(3)
Program Counter's (PC) Least Significant Byte
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
14
104h(3)
105h
106h
107h
108h
109h
FSR
—
Indirect data memory address pointer
Unimplemented
xxxx xxxx
23
—
33
—
—
—
—
PORTB
—
PORTB Data Latch when written: PORTB pins when read
xxxx xx11
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
10Ah(1,3)
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
INTE RBIE T0IF INTF RBIF
---0 0000
22
16
10Bh(3)
10Ch
10Dh
10Eh
10Fh
INTCON
PMDATL
PMADRL
PMDATH
PMADRH
GIE
PEIE
T0IE
0000 000x
xxxx xxxx
xxxx xxxx
--xx xxxx
---- xxxx
Program memory read data low
Program memory read address low
—
—
—
—
Program memory read data high
Program memory read address high
—
—
110h-
11Fh
—
Unimplemented
—
—
Bank 3
180h(3)
181h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
23
15
22
14
23
OPTION_REG RBPU
INTEDG
Program Counter's (PC) Least Significant Byte
IRP RP1 RP0 TO
T0CS
T0SE
PSA
PS2
PS1
PS0
182h(3)
183h(3)
PCL
STATUS
FSR
PD
Z
DC
C
184h(3)
185h
186h
187h
188h
189h
Indirect data memory address pointer
—
TRISB
—
Unimplemented
—
—
33
—
—
—
PORTB Data Direction Register
Unimplemented
1111 1111
—
—
—
—
Unimplemented
—
Unimplemented
18Ah(1,3)
Write Buffer for the upper 5 bits of the Program Counter
PCLATH
INTCON
PMCON1
—
GIE
—
PEIE
—
—
T0IE
—
---0 0000
0000 000x
1--- ---0
22
16
18Bh(3)
18Ch
INTE
RBIE
T0IF
INTF
RBIF
RD
Reserved
—
—
—
—
18Dh-
18Fh
—
Unimplemented
—
—
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
2002 Microchip Technology Inc.
DS41120B-page 13
PIC16C717/770/771
2.2.2.1
STATUS REGISTER
For example, CLRF STATUSwill clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
The STATUS register, shown in Register 2-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions not affecting any status bits, see the
"Instruction Set Summary."
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1: STATUS REGISTER (STATUS: 03h, 83h, 103h, 183h)
R/W-0
IRP
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 7
bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1= Bank 2, 3 (100h - 1FFh)
0= Bank 0, 1 (00h - FFh)
bit 6-5
RP<1:0>: Register Bank Select bits (used for direct addressing)
11= Bank 3 (180h - 1FFh)
10= Bank 2 (100h - 17Fh)
01= Bank 1 (80h - FFh)
00= Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4
bit 3
bit 2
bit 1
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions) (for borrow the polarity
is reversed)
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS41120B-page 14
2002 Microchip Technology Inc.
PIC16C717/770/771
2.2.2.2
OPTION_REG REGISTER
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
The OPTION_REG register is a readable and writable
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
able register known also as the prescaler), the External
INT Interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2: OPTION REGISTER (OPTION_REG: 81h, 181h)
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
RBPU: PORTB Pull-up Enable bit(1)
1= PORTB weak pull-ups are disabled
0= PORTB weak pull-ups are enabled by the WPUB register
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Note 1: Individual weak pull-up on RB pins can be enabled/disabled from the weak pull-up
PORTB Register (WPUB).
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
2002 Microchip Technology Inc.
DS41120B-page 15
PIC16C717/770/771
2.2.2.3
INTCON REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The INTCON Register is a readable and writable regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
REGISTER 2-3: INTERRUPT CONTROL REGISTER (INTCON: 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
GIE: Global Interrupt Enable bit
1= Enables all un-masked interrupts
0= Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1= Enables all un-masked peripheral interrupts
0= Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1= Enables the RB0/INT external interrupt
0= Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit(1)
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1= The RB0/INT external interrupt occurred (must be cleared in software)
0= The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit(1)
1= At least one of the RB<7:0> pins changed state (must be cleared in software)
0= None of the RB<7:0> pins have changed state
Note 1: Individual RB pin interrupt-on-change can be enabled/disabled from the
Interrupt-on-Change PORTB register (IOCB).
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS41120B-page 16
2002 Microchip Technology Inc.
PIC16C717/770/771
2.2.2.4
PIE1 REGISTER
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 2-4: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (PIE1: 8Ch)
U-0
R/W-0
ADIE
U-0
U-0
R/W-0
SSPIE
R/W-0
R/W-0
R/W-0
TMR1IE
bit 0
—
—
—
CCP1IE
TMR2IE
bit 7
bit 7
bit 6
Unimplemented: Read as ’0’
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
bit 5-4
bit 3
Unimplemented: Read as ’0’
SSPIE: Synchronous Serial Port Interrupt Enable bit
1= Enables the SSP interrupt
0= Disables the SSP interrupt
bit 2
bit 1
bit 0
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2002 Microchip Technology Inc.
DS41120B-page 17
PIC16C717/770/771
2.2.2.5
PIR1 REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
This register contains the individual flag bits for the
peripheral interrupts.
REGISTER 2-5: PERIPHERAL INTERRUPT REGISTER 1 (PIR1: 0Ch)
U-0
R/W-0
ADIF
U-0
U-0
R/W-0
SSPIF
R/W-0
R/W-0
R/W-0
—
—
—
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’.
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed
0= The A/D conversion is not complete
bit 5-4
bit 3
Unimplemented: Read as ’0’
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1= The SSP interrupt condition has occurred, and must be cleared in software before returning
from the Interrupt Service Routine. The conditions that will set this bit are:
SPI
A transmission/reception has taken place.
I2C Slave / Master
A transmission/reception has taken place.
I2C Master
The initiated START condition was completed by the SSP module.
The initiated STOP condition was completed by the SSP module.
The initiated Restart condition was completed by the SSP module.
The initiated Acknowledge condition was completed by the SSP module.
A START condition occurred while the SSP module was IDLE (Multi-master system).
A STOP condition occurred while the SSP module was IDLE (Multi-master system).
0= No SSP interrupt condition has occurred.
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare Mode
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS41120B-page 18
2002 Microchip Technology Inc.
PIC16C717/770/771
2.2.2.6
PIE2 REGISTER
This register contains the individual enable bits for the
SSP bus collision and low voltage detect interrupts.
REGISTER 2-6: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (PIE2: 8Dh)
R/W-0
LVDIE
U-0
U-0
U-0
R/W-0
BCLIE
U-0
U-0
U-0
—
—
—
—
—
—
bit 7
bit 0
bit 7
LVDIE: Low Voltage Detect Interrupt Enable bit
1= LVD Interrupt is enabled
0= LVD Interrupt is disabled
bit 6-4
bit 3
Unimplemented: Read as '0'
BCLIE: Bus Collision Interrupt Enable bit
1= Bus Collision interrupt is enabled
0= Bus Collision interrupt is disabled
bit 2-0
Unimplemented: Read as '0'
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2002 Microchip Technology Inc.
DS41120B-page 19
PIC16C717/770/771
.
2.2.2.7
PIR2 REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
This register contains the SSP Bus Collision and low-
voltage detect interrupt flag bits.
REGISTER 2-7: PERIPHERAL INTERRUPT REGISTER 2 (PIR2: 0Dh)
R/W-0
LVDIF
U-0
U-0
U-0
R/W-0
BCLIF
U-0
U-0
U-0
—
—
—
—
—
—
bit 7
bit 0
bit 7
LVDIF: Low Voltage Detect Interrupt Flag bit
1= The supply voltage has fallen below the specified LVD voltage (must be cleared in software)
0= The supply voltage is greater than the specified LVD voltage
bit 6-4
bit 3
Unimplemented: Read as '0'
BCLIF: Bus Collision Interrupt Flag bit
1= A bus collision has occurred while the SSP module configured in I2C Master was
transmitting (must be cleared in software)
0= No bus collision occurred
bit 2-0
Unimplemented: Read as '0'
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS41120B-page 20
2002 Microchip Technology Inc.
PIC16C717/770/771
2.2.2.8
PCON REGISTER
Note: BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent RESETS to see if BOR is
clear, indicating a brown-out has occurred.
The BOR status bit is a don’t care and is
not necessarily predictable if the brown-out
circuit is disabled (by clearing the BODEN
bit in the Configuration word).
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR) to an external MCLR Reset or WDT Reset.
Those devices with brown-out detection circuitry con-
tain an additional bit to differentiate a Brown-out Reset
condition from a Power-on Reset condition.
The PCON register also contains the frequency select
bit of the INTRC or ER oscillator.
REGISTER 2-8: POWER CONTROL REGISTER (PCON: 8Eh)
U-0
U-0
U-0
U-0
R/W-1
OSCF
U-0
R/W-q
POR
R/W-q
BOR
—
—
—
—
—
bit 7
bit 0
bit 7-4
bit 3
Unimplemented: Read as '0'
OSCF: Oscillator Speed bit
INTRC Mode
1= 4 MHz nominal
0= 37 kHz nominal
ER Mode
1= Oscillator frequency depends on the external resistor value on the OSC1 pin.
0= 37 kHz nominal
All other modes
x= Ignored
bit 2
bit 1
Unimplemented: Read as '0'
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit (See Section 2.2.2.8 Note)
1= No Brown-out Reset occurred
bit 0
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
q = Value depends on conditions
R = Readable bit
- n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
2002 Microchip Technology Inc.
DS41120B-page 21
PIC16C717/770/771
2.3
PCL and PCLATH
2.4
Stack
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<12:8>
bits and is not directly readable or writable. All updates
to the PCH register occur through the PCLATH register.
The stack allows a combination of up to 8 program calls
and interrupts to occur. The stack contains the return
address from this branch in program execution.
Mid-range devices have an 8-level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not modified when the stack is PUSHed or
POPed.
2.3.1
PROGRAM MEMORY PAGING
PIC16C717/770/771 devices are capable of address-
ing a continuous 8K word block of program memory.
The CALLand GOTOinstructions provide only 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALLor GOTOinstruction,
the upper 2 bits of the address are provided by
PCLATH<4:3>. When doing a CALL or GOTO instruc-
tion, the user must ensure that the page select bits are
programmed so that the desired program memory
page is addressed. A return instruction pops a PC
address off the stack onto the PC register. Therefore,
manipulation of the PCLATH<4:3> bits are not required
for the return instructions (which POPs the address
from the stack).
After the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
FIGURE 2-4:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
12
PCL
8 7
0
Instruction with
PCL as
Destination
8
PCLATH<4:0>
ALU
5
PCLATH
PCL
PCH
12 1110
0
8 7
GOTO, CALL
11
PCLATH<4:3>
PCLATH
Opcode <10:0>
2
DS41120B-page 22
2002 Microchip Technology Inc.
PIC16C717/770/771
The INDF register is not a physical register. Address-
ing INDF actually addresses the register whose
address is contained in the FSR register (FSR is a
pointer). This is indirect addressing.
EXAMPLE 2-1:
How to Clear RAM Using
Indirect Addressing
movlw
movwf
0x20
;initialize pointer
FSR
; to RAM
NEXT
clrf
incf
btfss
goto
INDF
FSR
FSR,4
NEXT
;clear INDF register
;inc pointer
;all done?
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
;NO, clear next
CONTINUE
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-1.
:
;YES, continue
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-5.
FIGURE 2-5: DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
from opcode
7
RP1:RP0
6
0
0
IRP
FSR register
bank select
location select
bank select
location select
00
01
80h
10
100h
11
00h
180h
Data
Memory(1)
7Fh
Bank 0
FFh
Bank 1
17Fh
Bank 2
1FFh
Bank 3
Note 1: For register file map detail see Figure 2-3.
2002 Microchip Technology Inc.
DS41120B-page 23
PIC16C717/770/771
NOTES:
DS41120B-page 24
2002 Microchip Technology Inc.
PIC16C717/770/771
present on a pin, the pin must be configured as an ana-
log input to prevent unnecessary current draw from the
power supply. The Analog Select Register (ANSEL)
allows the user to individually select the Digital/Analog
mode on these pins. When the Analog mode is active,
the port pin will always read 0.
3.0
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the
PICmicro™ Mid-Range MCU Family Reference Man-
ual, (DS33023).
Note 1: On a Power-on Reset, the ANSEL regis-
ter configures these mixed-signal pins as
Analog mode.
2: If a pin is configured as Analog mode, the
RA pin will always read '0' and RB pin will
always read '1', even if the digital output is
active.
3.1
I/O Port Analog/Digital Mode
The PIC16C717/770/771 have two I/O ports: PORTA
and PORTB. Some of these port pins are mixed-signal
(can be digital or analog). When an analog signal is
REGISTER 3-1: ANALOG SELECT REGISTER (ANSEL: 9Dh)
R/W-1
R/W-1
R/W-1
ANS5
R/W-1
ANS4
R/W-1
ANS3
R/W-1
ANS2
R/W-1
ANS1
R/W-1
ANS0
—
—
bit 7
bit 0
bit 7-6
bit 5-0
Reserved: Do not use
ANS<5:0>: Analog Select between analog or digital function on pins AN<5:0>, respectively.
0= Digital I/O. Pin is assigned to port or special function.
1= Analog Input. Pin is assigned as analog input.
Note: Setting a pin to an analog input disables the digital input buffer on the pin. The cor-
responding TRIS bit should be set to Input mode when using pins as analog inputs.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
these pins as analog input/output, the ANSEL register
must have the proper value to individually select the
Analog mode of the corresponding pins.
3.2
PORTA and the TRISA Register
PORTA is a 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
Hi-impedance mode). Clearing a TRISA bit (=0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Note: Upon RESET, the ANSEL register config-
ures the RA<3:0> pins as analog inputs.
All RA<3:0> pins will read as '0'.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified, and then written to the port
data latch.
Pin RA5 is multiplexed with the device RESET (MCLR)
and programming input (VPP) functions. The RA5/
MCLR/VPP input only pin has a Schmitt Trigger input
buffer. All other RA port pins have Schmitt Trigger input
buffers and full CMOS output buffers.
Pins RA<3:0> are multiplexed with analog functions,
such as analog inputs to the A/D converter, analog
VREF inputs, and the onboard bandgap reference out-
puts. When the analog peripherals are using any of
Pins RA6 and RA7 are multiplexed with the oscillator
input and output functions.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
2002 Microchip Technology Inc.
DS41120B-page 25
PIC16C717/770/771
EXAMPLE 3-1:
Initializing PORTA
BCF
STATUS, RP0
; Select Bank 0
CLRF
PORTA
; Initialize PORTA by
; clearing output
; data latches
BSF
MOVLW
STATUS, RP0
0Fh
; Select Bank 1
; Value used to
; initialize data
; direction
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<7:4> as outputs. RA<7:6>availability depends on oscillator selection.
; Set RA<1:0> as analog inputs, RA<7:2> are digital I/O
MOVLW
MOVWF
BCF
03
ANSEL
STATUS, RP0
; Return to Bank 0
FIGURE 3-1: BLOCK DIAGRAM OF RA0/AN0, RA1/AN1/LVDIN
Data Latch
Data
Bus
D
Q
VDD
VDD
P
WR
PORT
Q
CK
TRIS Mode
N
D
Q
WR
TRIS
VSS
VSS
Q
CK
RD
TRIS
Analog Select
Schmitt
Trigger
D
Q
WR
ANSEL
Q
CK
Q
D
EN
RD
PORT
To A/D Converter input or LVD Module input
DS41120B-page 26
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 3-2: BLOCK DIAGRAM OF RA2/AN2/VREF-/VRL AND RA3/AN3/VREF+/VRH
Data Latch
D
Data
Bus
Q
VDD
VDD
P
WR
PORT
Q
CK
TRIS Mode
N
D
Q
WR
TRIS
VSS
VSS
Q
CK
RD
TRIS
Analog Select
D
Q
Schmitt
Trigger
WR
ANSEL
Q
CK
Q
D
EN
RD
PORT
To A/D Converter input
and VREF+, VREF- inputs
VRH, VRL outputs
(From VREF-LVD-BOR Module)
VRH, VRL output enable
Sense input for
VRH, VRL amplifier
2002 Microchip Technology Inc.
DS41120B-page 27
PIC16C717/770/771
FIGURE 3-3: BLOCK DIAGRAM OF RA4/T0CKI
Data Latch
Data
Bus
D
Q
WR
Port
Q
CK
TRIS Latch
N
D
Q
WR
TRIS
VSS
Q
CK
VSS
RD
TRIS
Schmitt Trigger
Input Buffer
Q
D
EN
RD
PORT
TMR0 clock input
DS41120B-page 28
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 3-4: BLOCK DIAGRAM OF RA5/MCLR/VPP
To MCLR Circuit
MCLR Filter
Program Mode
HV Detect
Data
Bus
VSS
RD
TRIS
VSS
Schmitt
Trigger
Q
D
EN
RD PORT
2002 Microchip Technology Inc.
DS41120B-page 29
PIC16C717/770/771
FIGURE 3-5: BLOCK DIAGRAM OF RA6/OSC2/CLKOUT PIN
(INTRC or ER) and CLKOUT
From OSC1
CLKOUT (Fosc/4)
Oscillator
Circuit
1
0
VDD
Data
Bus
VDD
P
D
Q
Q
WR
PORTA
CK
VSS
Data Latch
D
Q
N
WR
TRISA
CK
Q
TRIS Latch
VSS
Schmitt Trigger
Input Buffer
RD TRISA
EC or [(ER or INTRC) and CLKOUT]
Q
D
EN
RD PORTA
DS41120B-page 30
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 3-6: BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN
To OSC2
Oscillator
Circuit
VDD
To Chip Clock Drivers
VDD
Schmitt Trigger
Input Buffer
Data
Bus
D
Q
Q
EC Mode
P
WR
PORTA
CK
Data Latch
D
Q
N
WR
TRISA
CK
Q
TRIS Latch
INTRC
Vss
INTRC
RD TRISA
Schmitt Trigger
Input Buffer
Q
D
EN
RD PORTA
2002 Microchip Technology Inc.
DS41120B-page 31
PIC16C717/770/771
TABLE 3-1:
PORTA FUNCTIONS
Input
Type
Output
Type
Name
Function
Description
RA0
AN0
ST
AN
ST
AN
AN
ST
AN
AN
CMOS
Bi-directional I/O
A/D input
RA0/AN0
RA1
CMOS
Bi-directional I/O
A/D input
RA1/AN1/LVDIN
AN1
LVDIN
RA2
LVD input reference
Bi-directional I/O
A/D input
CMOS
AN2
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
VREF-
VRL
Negative analog reference input
Internal voltage reference low output
Bi-directional I/O
AN
RA3
ST
AN
AN
CMOS
AN3
A/D input
VREF+
VRH
Positive analog reference input
Internal voltage reference high output
Bi-directional I/O
AN
OD
RA4
ST
ST
RA4/T0CKI
T0CKI
RA5
TMR0 clock input
ST
Input port
RA5/MCLR/VPP
MCLR
VPP
ST
Master clear
Power
ST
Programming voltage
Bi-directional I/O
RA6
CMOS
XTAL
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
OSC2
CLKOUT
RA7
Crystal/resonator
CMOS
CMOS
FOSC/4 output
ST
Bi-directional I/O
OSC1
CLKIN
XTAL
ST/AN
Crystal/resonator
External clock input/ER resistor connection
TABLE 3-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on:
POR,
Value on all
other
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
RESETS
xxxx 0000 uuuu 0000
1111 1111 1111 1111
05h
85h
9Dh
PORTA
TRISA
ANSEL
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
PORTA Data Direction Register
ANS5 ANS4
—
—
ANS3
ANS2
ANS1
ANS0
--11 1111 --11 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ’0’. Shaded cells are not used by PORTA.
DS41120B-page 32
2002 Microchip Technology Inc.
PIC16C717/770/771
Each of the PORTB pins, if configured as input, also
has an interrupt-on-change feature, which can be indi-
vidually selected from the IOCB register. The RBIE bit
in the INTCON register functions as a global enable bit
to turn on/off the interrupt-on-change feature. The
selected inputs are compared to the old value latched
on the last read of PORTB. The "mismatch" outputs are
OR’ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
3.3
PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
Hi-impedance mode). Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
rupt in the following manner:
EXAMPLE 3-2:
Initializing PORTB
BCF
STATUS, RP0;
CLRF
PORTB
; Initialize PORTB by
; clearing output
; data latches
a) Any read or write of PORTB. This will end the
mismatch condition.
BSF
STATUS, RP0; Select Bank 1
a) Clear flag bit RBIF.
MOVLW
0xCF
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
; Set RB<1:0> as analog
inputs
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
MOVWF
MOVLW
TRISB
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
0x30
MOVWF
BCF
ANSEL
;
STATUS, RP0; Return to Bank 0
Each of the PORTB pins has an internal pull-up, which
can be individually enabled from the WPUB register. A
single global enable bit can turn on/off the enabled pull-
ups. Clearing the RBPU bit, (OPTION_REG<7>),
enables the weak pull-up resistors. The weak pull-up is
automatically turned off when the port pin is configured
as an output. The pull-ups are disabled on a Power-on
Reset.
2002 Microchip Technology Inc.
DS41120B-page 33
PIC16C717/770/771
REGISTER 3-2: WEAK PULL-UP PORTB REGISTER (WPUB: 95h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2 WPUB1 WPUB0
bit 0
bit 7
bit 7-0
WPUB<7:0>: PORTB Weak Pull-Up Control bits
1= Weak pull-up enabled
0= Weak pull-up disabled
Note 1: For the WPUB register setting to take effect, the RBPU bit in the OPTION_REG
register must be cleared.
2: The weak pull-up device is automatically disabled if the pin is in Output mode
(TRIS = 0).
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
REGISTER 3-3: INTERRUPT-ON-CHANGE PORTB REGISTER (IOCB: 96h)
R/W-1
IOCB7
R/W-1
IOCB6
R/W-1
IOCB5
R/W-1
IOCB4
R/W-0
IOCB3
R/W-0
IOCB2
R/W-0
IOCB1
R/W-0
IOCB0
bit 7
bit 0
bit 7-0
IOCB<7:0>: Interrupt-on-Change PORTB Control bits
1= Interrupt-on-change enabled
0= Interrupt-on-change disabled
Note: The interrupt enable bits GIE and RBIE in the INTCON Register must be set for indi-
vidual interrupts to be recognized.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS41120B-page 34
2002 Microchip Technology Inc.
PIC16C717/770/771
The RB0 pin is multiplexed with the A/D converter ana-
log input 4 and the external interrupt input (RB0/AN4/
INT). When the pin is used as analog input, the ANSEL
register must have the proper value to select the RB0
pin as Analog mode.
The RB1 pin is multiplexed with the A/D converter ana-
log input 5 and the MSSP module slave select input
(RB1/AN5/SS). When the pin is used as analog input,
the ANSEL register must have the proper value to
select the RB1 pin as Analog mode.
Note: Upon RESET, the ANSEL register config-
ures the RB1 and RB0 pins as analog inputs.
Both RB1 and RB0 pins will read as ’1’.
FIGURE 3-7: BLOCK DIAGRAM OF RB0/AN4/INT, RB1/AN5/SS PIN
WPUB Reg
Data Bus
Q
D
WR
WPUB
CK
Q
VDD
RBPU
weak
pull-up
P
VDD
PORTB Reg
D
Q
VDD
P
WR
PORT
CK
Q
TRIS Reg
N
D
Q
WR
TRIS
VSS
CK
Q
RD
TRIS
VSS
Analog Select
D
Q
Q
WR
ANSEL
CK
TTL
IOCB Reg
D
Q
Schmitt
WR
IOCB
Set
RBIF
Trigger
Q
Q
D
CK
Q
Q1
From
RB<7:0> pins
EN
Q
D
Q3
D
EN
RD
PORT
EN
To INT input or MSSP module
To A/D Converter
2002 Microchip Technology Inc.
DS41120B-page 35
PIC16C717/770/771
FIGURE 3-8: BLOCK DIAGRAM OF RB2/SCK/SCL, RB3/CCP1/P1A, RB4/SDI/SDA,
RB5/SDO/P1B
WPUB Reg
Data Bus
D
Q
WR
WPUB
CK
Q
VDD
Spec. Func En.
RBPU
VDD
weak
pull-up
P
SDA, SDO, SCK, CCP1, P1A, P1B
PORTB Reg
VDD
P
1
0
D
Q
WR
PORT
CK
Q
N
TRIS Reg
VSS
D
Q
WR
TRIS
VSS
CK
Q
RD
TRIS
TTL
IOCB Reg
Schmitt
Trigger
D
Q
WR
IOCB
Set
RBIF
Q
Q
D
CK
Q
Q1
From
RB<7:0> pins
EN
Q
D
D
Q3
EN
EN
RD
PORT
SCK, SCL, CC, SDI, SDA inputs
DS41120B-page 36
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 3-9: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI/P1C
WPUB Reg
Data Bus
VDD
D
Q
RBPU
WR
WPUB
P
weak pull-up
CK
Q
VDD
P
D
Q
VDD
WR PORTB
WR TRISB
CK
Q
Data Latch
D
Q
Q
N
CK
TRIS Latch
VSS
TTL
RD TRISB
T1OSCEN
Input
Buffer
RD PORTB
IOCB Reg
D
Q
WR
IOCB
CK
Q
CMOS
TMR1 Clock
Schmitt
Trigger
Serial programming clock
From RB7
TMR1 Oscillator
Q
D
Q1
EN
Set RBIF
Q
D
From
RB<7:0> pins
RD Port
Q3
EN
Note: The TMR1 oscillator enable (T1OSCEN = 1) overrides the RB6 I/O port and P1C functions.
2002 Microchip Technology Inc.
DS41120B-page 37
PIC16C717/770/771
FIGURE 3-10: BLOCK DIAGRAM OF THE RB7/T1OSI/P1D
VDD
RBPU
TMR1 Oscillator
weak pull-up
P
To RB6
WPUB Reg
Data Bus
D
Q
T1OSCEN
WR
WPUB
CK
Q
VDD
VDD
P
D
Q
Q
WR PORTB
WR TRISB
CK
Data Latch
D
Q
Q
N
CK
TRIS Latch
VSS
RD TRISB
T10SCEN
TTL
Input
Buffer
RD PORTB
IOCB Reg
D
Q
WR
IOCB
CK
Q
Serial programming input
Q
Q
D
Schmitt Trigger
Set RBIF
Q1
EN
D
From
RB<7:0> pins
RD Port
Q3
EN
Note: The TMR1 oscillator enable (T1OSCEN = 1) overrides the RB7 I/O port and P1D functions.
DS41120B-page 38
2002 Microchip Technology Inc.
PIC16C717/770/771
TABLE 3-3:
PORTB FUNCTIONS
Input
Type
Output
Type
Name
Function
Description
(1)
RB0
AN4
INT
TTL
AN
ST
CMOS
Bi-directional I/O
RB0/AN4/INT
RB1/AN5/SS
A/D input
Interrupt input
Bi-directional I/O
A/D input
(1)
RB1
AN5
SS
TTL
AN
ST
CMOS
SSP slave select input
(1)
RB2
SCK
SCL
RB3
CCP1
P1A
TTL
ST
CMOS
CMOS
OD
Bi-directional I/O
RB2/SCK/SCL
RB3/CCP1/P1A
RB4/SDI/SDA
RB5/SDO/P1B
Serial clock I/O for SPI
2
ST
Serial clock I/O for I C
(1)
TTL
ST
CMOS
CMOS
CMOS
CMOS
Bi-directional I/O
Capture 1 input/Compare 1 output
PWM P1A output
(1)
RB4
SDI
TTL
ST
Bi-directional I/O
Serial data in for SPI
2
SDA
RB5
SDO
P1B
ST
OD
Serial data I/O for I C
(1)
TTL
CMOS
CMOS
CMOS
CMOS
XTAL
Bi-directional I/O
Serial data out for SPI
PWM P1B output
(1)
RB6
T1OSO
T1CKI
P1C
RB7
T1OSI
P1D
TTL
Bi-directional I/O
Crystal/Resonator
TMR1 clock input
PWM P1C output
RB6/T1OSO/T1CKI/P1C
CMOS
CMOS
CMOS
(1)
TTL
Bi-directional I/O
RB7/T1OSI/P1D
XTAL
TMR1 crystal/resonator
PWM P1D output
CMOS
Note 1: Bit programmable pull-ups.
TABLE 3-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on: Value on all
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other
RESETS
xxxx xx11 uuuu uu11
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 0000 1111 0000
--11 1111 --11 1111
06h, 106h PORTB
86h, 186h TRISB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
PORTB Data Direction Register
T0SE
PORTB Weak Pull-up Control
PORTB Interrupt on Change Control
ANS5 ANS4
81h, 181h OPTION_REG RBPU INTEDG T0CS
PSA
PS2
PS1
PS0
95h
96h
9Dh
WPUB
IOCB
ANSEL
—
—
ANS3
ANS2
ANS1
ANS0
Legend: x= unknown, u = unchanged. Shaded cells are not used by PORTB.
2002 Microchip Technology Inc.
DS41120B-page 39
PIC16C717/770/771
NOTES:
DS41120B-page 40
2002 Microchip Technology Inc.
PIC16C717/770/771
When interfacing the program memory block, the
PMDATH & PMDATL registers form a 2-byte word,
which holds the 14-bit data. The PMADRH & PMADRL
registers form a 2-byte word, which holds the 12-bit
address of the program memory location being
accessed. Mid-range devices have up to 8K words of
program EPROM with an address range from 0h to
3FFFh. When the device contains less memory than
the full address range of the PMADRH:PMARDL regis-
ters, the Most Significant bits of the PMADRH register
are ignored.
4.0
PROGRAM MEMORY READ
(PMR)
Program memory is readable during normal operation
(full VDD range). It is indirectly addressed through the
Special Function Registers:
• PMCON1
• PMDATH
• PMDATL
• PMADRH
• PMADRL
4.1
PMCON1 REGISTER
PMCON1 is the control register for program memory
accesses.
Control bit RD initiates a read operation. This bit cannot
be cleared, only set, in software. It is cleared in hard-
ware at completion of the read operation.
REGISTER 4-1: PROGRAM MEMORY READ CONTROL REGISTER 1 (PMCON1: 18Ch)
R-1
Reserved
bit 7
U-0
U-0
U-0
U-0
U-0
U-0
R/S-0
RD
—
—
—
—
—
—
bit 0
bit 7
Reserved: Read as ‘1’
bit 6-1
bit 0
Unimplemented: Read as '0'
RD: Read Control bit
1= Initiates a Program memory read (read takes 2 cycles). RD is cleared in hardware.
0= Reserved
Legend:
S = Settable (cleared in hardware)
R = Readable bit
- n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
4.2
PMDATH AND PMDATL
REGISTERS
The PMDATH:PMDATL registers are loaded with the
contents of program memory addressed by the
PMADRH and PMADRL registers upon completion of a
Program Memory Read command.
2002 Microchip Technology Inc.
DS41120B-page 41
PIC16C717/770/771
REGISTER 4-2: PROGRAM MEMORY DATA HIGH (PMDATH: 10Eh)
U-0
U-0
R-x
R-x
R-x
R-x
R-x
R-x
—
—
PMD13
PMD12
PMD11
PMD10
PMD9
PMD8
bit 7
Unimplemented: Read as '0'
bit 0
bit 7-6
bit 5-0
PMD<13:8>: The value of the program memory word pointed to by PMADRH and PMADRL
after a Program Memory Read command.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
REGISTER 4-3: PROGRAM MEMORY DATA LOW (PMDATL: 10Ch)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
PMD7
PMD6
PMD5
PMD4
PMD3
PMD2
PMD1
PMD0
bit 7
bit 0
bit 7-0
PMD<7:0>: The value of the program memory word pointed to by PMADRH and PMADRL after
a Program Memory Read command.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
REGISTER 4-4: PROGRAM MEMORY ADDRESS HIGH (PMADRH: 10Fh)
U-0
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
PMA9
R/W-x
PMA8
—
—
—
—
PMA11
PMA10
bit 7
bit 0
bit 7-4
bit 3-0
Unimplemented: Read as '0'
PMA<11:8>: PMR Address bits
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
REGISTER 4-5: PROGRAM MEMORY ADDRESS LOW (PMADRL: 10Dh)
R/W-x
PMA7
R/W-x
PMA6
R/W-x
PMA5
R/W-x
PMA4
R/W-x
PMA3
R/W-x
PMA2
R/W-x
PMA1
R/W-x
PMA0
bit 7
bit 0
bit 7-0
PMA<7:0>: PMR Address bits
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS41120B-page 42
2002 Microchip Technology Inc.
PIC16C717/770/771
the “BSF PMCON1,RD” instruction to be ignored. The data
is available, in the very next cycle, in the PMDATH and
PMDATL registers; therefore it can be read as 2 bytes
in the following instructions. PMDATH and PMDATL
registers will hold this value until another Program
Memory Read or until it is written to by the user.
4.3
READING THE EPROM PROGRAM
MEMORY
To read a program memory location, the user must
write 2 bytes of the address to the PMADRH and
PMADRL registers, then set control bit RD
(PMCON1<0>). Once the read control bit is set, the
Program Memory Read (PMR) controller will use the
second instruction cycle after to read the data. This
causes the second instruction immediately following
Note: The two instructions that follow setting the
PMCON1 read bit must be NOPs.
EXAMPLE 4-1:
OTP PROGRAM MEMORY Read
BSF
STATUS, RP1
;
BCF
STATUS, RP0
MS_PROG_PM_ADDR
PMADRH
LS_PROG_PM_ADDR
PMADRL
STATUS, RP0
PMCON1, RD
; Bank 2
;
MOVLW
MOVWF
MOVLW
MOVWF
BSF
; MS Byte of Program Memory Address to read
;
; LS Byte of Program Memory Address to read
; Bank 3
BSF
; Program Memory Read
NOP
NOP
; This instruction must be an NOP
; This instruction must be an NOP
; PMDATH:PMDATL now has the data
next instruction
4.4
OPERATION DURING CODE
PROTECT
When the device is code protected, the CPU can still
perform the Program Memory Read function.
FIGURE 4-1: PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Program
Memory
ADDR
PMADRH,PMADRL
PC
PC+1
PC+3
PC+4
PC+5
BSF PMCON1,RD
Executed here
INSTR(PC-1)
Executed here
INSTR(PC+1)
Executed here
Forced NOP
Executed here
INSTR(PC+3)
Executed here
INSTR(PC+4)
Executed here
RD bit
PMDATH
PMDATL
register
2002 Microchip Technology Inc.
DS41120B-page 43
PIC16C717/770/771
TABLE 4-1:
PROGRAM MEMORY READ REGISTER SUMMARY
Value on:
POR,
Value on all
other
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
RESETS
1--- ---0 1--- ---0
--xx xxxx --uu uuuu
xxxx xxxx uuuu uuuu
---- xxxx ---- uuuu
xxxx xxxx uuuu uuuu
18Ch
10Eh
10Ch
10Fh
10Dh
PMCON1 Reserved
—
—
—
—
—
—
—
RD
PMDATH
PMDATL
PMADRH
PMADRL
—
PMD13 PMD12 PMD11 PMD10 PMD9
PMD8
PMD0
PMA8
PMA0
PMD7
—
PMD6
—
PMD5
—
PMD4
—
PMD3
PMA11 PMA10 PMA9
PMA3 PMA2 PMA1
PMD2
PMD1
PMA7
PMA6
PMA5
PMA4
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Program Memory Read.
DS41120B-page 44
2002 Microchip Technology Inc.
PIC16C717/770/771
Additional information on external clock requirements
is available in the PICmicro™ Mid-Range MCU Family
Reference Manual, (DS33023).
5.0
TIMER0 MODULE
The Timer0 module timer/counter has the following fea-
tures:
5.2
Prescaler
• 8-bit timer/counter
• Readable and writable
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 5-2). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available which is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer, and
vice-versa.
• Internal or external clock select
• Edge select for external clock
• 8-bit software programmable prescaler
• Interrupt on overflow from FFh to 00h
Figure 5-1 is a simplified block diagram of the Timer0
module.
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual, (DS33023).
The prescaler is not readable or writable.
The PSA and PS<2:0> bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
5.1
Timer0 Operation
Timer0 can operate as a timer or as a counter.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0 mod-
ule will increment every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
Setting bit PSA will assign the prescaler to the Watch-
dog Timer (WDT). When the prescaler is assigned to
the WDT, prescale values of 1:1, 1:2, ..., 1:128 are
selectable.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed in below.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF 1, x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the WDT.
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
FIGURE 5-1: TIMER0 BLOCK DIAGRAM
Data Bus
Fosc/4
0
1
PSout
8
1
0
Sync with
Internal
clocks
TMR0
Programmable
Prescaler
RA4/T0CKI
pin
PSout
(2 Tcy delay)
T0SE
3
Set interrupt
flag bit T0IF
on overflow
PS2, PS1, PS0
PSA
T0CS
Note 1: T0CS, T0SE, PSA, PS<2:0> (OPTION_REG<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 5-2 for detailed block diagram).
2002 Microchip Technology Inc.
DS41120B-page 45
PIC16C717/770/771
5.2.1
SWITCHING PRESCALER
ASSIGNMENT
5.3
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt ser-
vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP.
The prescaler assignment is fully under software con-
trol (i.e., it can be changed “on-the-fly” during program
execution).
Note: To avoid an unintended device RESET, a
specific instruction sequence (shown in the
PICmicro™ Mid-Range Reference Man-
ual, DS33023) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must
be followed even if the WDT is disabled.
FIGURE 5-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
8
CLKOUT (= Fosc/4)
M
U
X
1
0
0
1
M
U
X
RA4/T0CKI
Pin
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
Set flag bit T0IF
on Overflow
PSA
0
1
8-bit Prescaler
M
U
X
Watchdog
Timer
8
8 - to - 1MUX
PS<2:0>
PSA
1
0
WDT Enable Bit
M U X
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS<2:0> are (OPTION_REG<5:0>).
TABLE 5-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on:
POR,
BOR
Value on all
other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h,101h
TMR0
Timer0 register
GIE PEIE
xxxx xxxx uuuu uuuu
0Bh,8Bh,
10Bh,18Bh
INTCON
T0IE INTE
RBIE
PSA
T0IF
PS2
INTF
PS1
RBIF 0000 000x 0000 000u
1111 1111 1111 1111
81h,181h
85h
OPTION_REG RBPU INTEDG T0CS T0SE
TRISA PORTA Data Direction Register
PS0
1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ’0’. Shaded cells are not used by Timer0.
DS41120B-page 46
2002 Microchip Technology Inc.
PIC16C717/770/771
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual, (DS33023).
6.0
TIMER1 MODULE
The Timer1 module timer/counter has the following fea-
tures:
6.1
Timer1 Operation
• 16-bit timer/counter
(Two 8-bit registers; TMR1H and TMR1L)
Timer1 can operate in one of these modes:
• Readable and writable (Both registers)
• Internal or external clock select
• As a timer
• As a synchronous counter
• As an asynchronous counter
• Interrupt on overflow from FFFFh to 0000h
• RESET from ECCP module trigger
The Operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
Timer1 has a control register, shown in Register 6-1.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
Figure 6-2 is a simplified block diagram of the Timer1
module.
REGISTER 6-1: TIMER1 CONTROL REGISTER (T1CON: 10h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1CKPS1
—
—
T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 0
bit 7
Unimplemented: Read as '0'
bit 7-6
bit 5-4
T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable Control bit
1= Oscillator is enabled
0= Oscillator is shut off(1)
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RB6/T1OSO/T1CKI /P1C (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Note 1: The oscillator inverter and feedback resistor are turned off to eliminate power drain.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2002 Microchip Technology Inc.
DS41120B-page 47
PIC16C717/770/771
6.1.1
TIMER1 COUNTER OPERATION
In this mode, Timer1 is being incremented via an exter-
nal source. Increments occur on a rising edge. After
Timer1 is enabled in Counter mode, the module must
first have a falling edge before the counter begins to
increment.
FIGURE 6-1: TIMER1 INCREMENTING EDGE
T1CKI
(Initially high)
First falling edge
of the T1ON enabled
T1CKI
(Initially low)
First falling edge
of the T1ON enabled
Note: Arrows indicate counter increments.
FIGURE 6-2: TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow
Synchronized
clock input
0
TMR1
TMR1L
TMR1H
T1OSC
1
TMR1ON
on/off
T1SYNC
RB6/T1OSO/T1CKI/P1C
RB7/T1OSI/P1D
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator(1)
Fosc/4
Internal
Clock
0
2
SLEEP input
T1CKPS<1:0>
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS41120B-page 48
2002 Microchip Technology Inc.
PIC16C717/770/771
6.2
Timer1 Oscillator
6.3
Timer1 Interrupt
A crystal oscillator circuit is built in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 6-1 shows the capacitor
selection for the Timer1 oscillator.
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit TMR1IF (PIR1<0>).
This interrupt can be enabled/disabled by setting/clear-
ing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
6.4
Resetting Timer1 using a CCP
Trigger Output
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
If the ECCP module is configured in Compare mode to
generate a “special event trigger" (CCP1M<3:0> =
1011), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
TABLE 6-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
Note: The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Osc Type
Freq
C1
C2
LP
32 kHz
100 kHz
200 kHz
33 pF
15 pF
15 pF
33 pF
15 pF
15 pF
Timer1 must be configured for either timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
These values are for design guidance only.
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from ECCP, the write will take prece-
dence.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external components.
In this mode of operation, the CCPR1H:CCPR1L regis-
ters pair effectively becomes the period register for
Timer1.
TABLE 6-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 000x 0000 000u
0Bh,8Bh,
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
10Bh,18Bh
-0-- 0000 -0-- 0000
-0-- 0000 -0-- 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --uu uuuu
0Ch
8Ch
0Eh
0Fh
10h
PIR1
PIE1
—
—
ADIF
ADIE
—
—
—
—
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
T1CON
—
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC TMR1CS TMR1ON
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by the Timer1 module.
2002 Microchip Technology Inc.
DS41120B-page 49
PIC16C717/770/771
NOTES:
DS41120B-page 50
2002 Microchip Technology Inc.
PIC16C717/770/771
7.1
Timer2 Operation
7.0
TIMER2 MODULE
Timer2 can be used as the PWM time-base for PWM
mode of the ECCP module.
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
The TMR2 register is readable and writable, and is
cleared on any device RESET.
• 8-bit period register (PR2)
• Readable and writable (Both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match of PR2
The input clock (FOSC/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits T2CKPS<1:0>
(T2CON<1:0>).
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
• SSP module optional use of TMR2 output to gen-
erate clock shift
Timer2 has a control register, shown in Register 7-1.
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
The prescaler and postscaler counters are cleared
when any of the following occurs:
Figure 7-1 is a simplified block diagram of the Timer2
module.
• a write to the TMR2 register
• a write to the T2CON register
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual, (DS33023).
• any device RESET (Power-on Reset, MCLR
Reset, Watchdog Timer Reset, or Brown-out
Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 7-1:
TIMER2 CONTROL REGISTER (T2CON1: 12h)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as '0'
bit 6-3
TOUTPS<3:0>: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2002 Microchip Technology Inc.
DS41120B-page 51
PIC16C717/770/771
FIGURE 7-1:
Timer2 Block Diagram
7.2
Timer2 Interrupt
Sets flag
bit TMR2IF
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
TMR2
output (1)
RESET
Prescaler
1:1, 1:4, 1:16
TMR2 reg
Fosc/4
Postscaler
1:1 to 1:16
2
Comparator
7.3
Output of TMR2
EQ
4
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate shift clock.
PR2 reg
Note: TMR2 register output can be software
selected by the SSP Module as a baud
clock.
TABLE 7-1:
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 000x 0000 000u
0Bh,8Bh,
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
10Bh,18Bh
-0-- 0000 -0-- 0000
-0-- 0000 -0-- 0000
0000 0000 0000 0000
-000 0000 -000 0000
1111 1111 1111 1111
0Ch
8Ch
11h
12h
92h
PIR1
—
ADIF
ADIE
—
—
—
—
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
PIE1
—
TMR2
T2CON
PR2
Timer2 register
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by the Timer2 module.
DS41120B-page 52
2002 Microchip Technology Inc.
PIC16C717/770/771
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON and P1DEL reg-
isters control the operation of ECCP. All are readable
and writable.
8.0
ENHANCED CAPTURE/
COMPARE/PWM (ECCP)
MODULES
The ECCP (Enhanced Capture/Compare/PWM)
module contains a 16-bit register which can operate as
a 16-bit capture register, as a 16-bit compare register
or as a PWM master/slave Duty Cycle register.
Table 8-1 shows the timer resources of the ECCP mod-
ule modes.
REGISTER 8-1: CCP1 CONTROL REGISTER (CCP1CON: 17h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PWM1M1 PWM1M0 DC1B1
bit 7
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 0
bit 7-6
PWM1M<1:0>: PWM Output Configuration
CCP1M<3:2> = 00, 01, 10
xx= P1A assigned as Capture input, Compare output. P1B, P1C, P1D assigned as Port pins.
CCP1M<3:2> = 11
00= Single output. P1A modulated. P1B, P1C, P1D assigned as Port pins.
01= Full-bridge output forward. P1D modulated. P1A active. P1B, P1C inactive.
10= Half-bridge output. P1A, P1B modulated with deadband control. P1C, P1D assigned as
Port pins.
11= Full-bridge output reverse. P1B modulated. P1C active. P1A, P1D inactive.
bit 5-4
bit 3-0
DC1B<1:0>: PWM Duty Cycle Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in
CCPRnL.
CCP1M<3:0>: ECCP Mode Select bits
0000= Capture/Compare/PWM off (resets ECCP module)
0001= Unused (reserved)
0010= Compare mode, toggle output on match (CCP1IF bit is set)
0011= Unused (reserved)
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, set output on match (CCP1IF bit is set)
1001= Compare mode, clear output on match (CCP1IF bit is set)
1010= Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is
unaffected)
1011= Compare mode, trigger special event (CCP1IF bit is set; ECCP resets TMR1, and starts
an A/D conversion, if the A/D module is enabled.)
1100= PWM mode. P1A, P1C active high. P1B, P1D active high.
1101= PWM mode. P1A, P1C active high. P1B, P1D active low.
1110= PWM mode. P1A, P1C active low. P1B, P1D active high.
1111= PWM mode. P1A, P1C active low. P1B, P1D active low.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2002 Microchip Technology Inc.
DS41120B-page 53
PIC16C717/770/771
TABLE 8-1:
ECCP MODE - TIMER
RESOURCE
EXAMPLE 8-1:
Changing Between
Capture Prescalers
; Turn ECCP module off
CLRF
CCP1CON
ECCP Mode
Capture
Compare
PWM
Timer Resource
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
Timer1
Timer1
Timer2
; value and ECCP ON
; Load CCP1CON with
; this value
MOVWF CCP1CON
8.1
Capture Mode
FIGURE 8-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
In Capture mode, CCPR1H:CCPR1L captures the 16-
bit value of the TMR1 register when an event occurs on
pin CCP1. An event is defined as:
Set flag bit CCP1IF
(PIR1<2>)
• every falling edge
• every rising edge
Prescaler
³ 1, 4, 16
• every 4th rising edge
• every 16th rising edge
RB3/CCP1/
P1A Pin
CCPR1H
CCPR1L
Capture
Enable
and
edge detect
An event is selected by control bits CCP1M<3:0>
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
TMR1H
TMR1L
CCP1CON<3:0>
Q’s
8.2
Compare Mode
8.1.1
CCP1 PIN CONFIGURATION
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCP1 pin is:
In Capture mode, the CCP1 pin should be configured
as an input by setting the TRISB<3> bit.
• driven High
Note: If the RB3/CCP1/P1A pin is configured as
an output, a write to the port can cause a
capture condition.
• driven Low
• toggle output (High to Low or Low to High)
• remains Unchanged
8.1.2
TIMER1 MODE SELECTION
The action on the pin is based on the value of control
bits CCP1M<3:0>. At the same time, interrupt flag bit
CCP1IF is set.
Timer1 must be running in Timer mode or Synchro-
nized Counter mode. In Asynchronous Counter mode,
the capture operation may not work.
Changing the ECCP mode select bits to the clear out-
put on Match mode (CCP1M<3.0> = “1000”) presets
the CCP1 output latch to the logic 1 level. Changing the
ECCP mode select bits to the clear output on Match
mode (CCP1M<3:0> = “1001”) presets the CCP1 out-
put latch to the logic 0 level.
8.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in Operating mode.
8.2.1
CCP1 PIN CONFIGURATION
The user must configure the CCP1 pin as an output by
clearing the appropriate TRISB bit.
8.1.4
ECCP PRESCALER
There are three prescaler settings, specified by bits
CCP1M<3:0>. Whenever the ECCP module is turned
off or the ECCP module is not in Capture mode, the
prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.
Note: Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the port data
latch.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
8.2.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the ECCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
DS41120B-page 54
2002 Microchip Technology Inc.
PIC16C717/770/771
8.2.3
SOFTWARE INTERRUPT MODE
FIGURE 8-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
When generate software interrupt is chosen, the CCP1
pin is not affected. Only an ECCP interrupt is generated
(if enabled).
Special event trigger will:
RESET Timer1, but not set interrupt flag bit
TMR1IF (PIR1<0>).
8.2.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
Special Event Trigger
The special event trigger output of ECCP resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
Set flag bit CCP1IF
(PIR1<2>)
CCPR1H CCPR1L
Q
S
R
Output
Logic
The special event trigger output of ECCP module will
also start an A/D conversion if the A/D module is
enabled.
Comparator
match
RB3/CCP1/
P1A Pin
TRISB<3>
Output Enable
TMR1H TMR1L
CCP1CON<3:0>
Mode Select
Note: The special event trigger will not set the
interrupt flag bit TMR1IF (PIR1<0>).
TABLE 8-2:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Value on
POR,
BOR
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE
PEIE
ADIF
ADIE
T0IE
RCIF
RCIE
INTE
TXIF
TXIE
RBIE
SSPIF
SSPIE
T0IF
INTF
RBIF
0000 000x
0000 0000
0000 0000
1111 1111
xxxx xxxx
xxxx xxxx
--00 0000
0000 000u
0000 0000
0000 0000
1111 1111
uuuu uuuu
uuuu uuuu
--uu uuuu
PSPIF(1)
PSPIE(1)
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
PIE1
TRISB
PORTB Data Direction Register
TMR1L
TMR1H
T1CON
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1register
—
—
T1CKPS
1
T1CKP
S0
T1OSCEN
T1SYNC
TMR1CS
CCP1M1
TMR1O
N
CCPR1L
CCPR1H
CCP1CON
Capture/Compare/PWM register1 (LSB)
Capture/Compare/PWM register1 (MSB)
xxxx xxxx
xxxx xxxx
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
PWM1M1
PWM1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M0
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.
2002 Microchip Technology Inc.
DS41120B-page 55
PIC16C717/770/771
8.3
PWM Mode
In Pulse Width Modulation (PWM) mode, the ECCP
module produces up to a 10-bit resolution PWM output.
Figure 8-3 shows the simplified PWM block diagram.
FIGURE 8-3:
SIMPLIFIED PWM BLOCK DIAGRAM
PWM1M1<1:0> CCP1M<3:0>
CCP1CON<5:4>
Duty cycle registers
2
4
CCPR1L
CCP1/P1A
P1B
RB3/CCP1/P1A
RB5/SDO/P1B
TRISB<3>
TRISB<5>
TRISB<6>
TRISB<7>
CCPR1H (Slave)
Comparator
OUTPUT
CONTROLLER
Q
R
S
RB6/T1OSO/T1CKI/
P1C
P1C
(Note 1)
TMR2
P1D
RB7/T1OSI/P1D
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
P1DEL
Note: 8-bit timer TMR2 is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time-base.
8.3.1
PWM PERIOD
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
PWM PERIOD = [(PR2) + 1] • 4 • TOSC •
(TMR2 PRESCALE VALUE)
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note: The Timer2 postscaler (see Section 7.0) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different fre-
quency than the PWM output.
DS41120B-page 56
2002 Microchip Technology Inc.
PIC16C717/770/771
8.3.2
PWM DUTY CYCLE
FIGURE 8-4:
SINGLE PWM OUTPUT
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
Period
CCP1(2)
Duty Cycle
(1)
(1)
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: Output signal is shown as asserted high.
FIGURE 8-5:
EXAMPLE OF SINGLE
OUTPUT APPLICATION
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
PIC16C717/770/771
Using PWM as
a D/A Converter
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
R
CCP1
Vout
Maximum PWM resolution (bits) for a given PWM fre-
quency:
C
FOSC
log ---------------
FPWM
= ----------------------------- bits
Using PWM to
V+
log(2)
Drive a Power
Load
PIC16C717/770/771
CCP1
L
O
A
D
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
8.3.3
PWM OUTPUT CONFIGURATIONS
The PWM1M1 bits in the CCP1CON register allows
one of the following configurations:
In the Half-Bridge Output mode, two pins are used as
outputs. The RB3/CCP1/P1A pin has the PWM output
signal, while the RB5/SDO/P1B pin has the comple-
mentary PWM output signal. This mode can be used
for half-bridge applications, as shown on Figure 8-7, or
for full-bridge applications, where four power switches
are being modulated with two PWM signal.
• Single output
• Half-Bridge output
• Full-Bridge output, Forward mode
• Full-Bridge output, Reverse mode
In the Single Output mode, the RB3/CCP1/P1A pin is
used as the PWM output. Since the CCP1 output is
multiplexed with the PORTB<3> data latch, the
TRISB<3> bit must be cleared to make the CCP1 pin
an output.
Since the P1A and P1B outputs are multiplexed with
the PORTB<3> and PORTB<5> data latches, the
TRISB<3> and TRISB<5> bits must be cleared to con-
figure P1A and P1B as outputs.
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through cur-
rent in bridge power devices. See Section 8.3.5 for
more details of the deadband delay operations.
2002 Microchip Technology Inc.
DS41120B-page 57
PIC16C717/770/771
The PWM output polarities must be selected before the
PWM outputs are enabled. Charging the polarity con-
figuration while the PWM outputs are active is not rec-
ommended, since it may result in unpredictable
operation.
8.3.4
OUTPUT POLARITY
CONFIGURATION
The CCP1M<1:0> bits in the CCP1CON register allow
user to choose the logic conventions (asserted high/
low) for each of the outputs. See Register 8-1 for fur-
ther details.
FIGURE 8-6: HALF-BRIDGE PWM OUTPUT
Period
Period
Duty Cycle
P1A(2)
P1B(2)
td
td
(1)
(1)
(1)
td = Deadband Delay
Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: Output signals are shown as asserted high.
DS41120B-page 58
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 8-7: EXAMPLE OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
V+
PIC16C717/770/771
FET
DRIVER
+
V
-
P1A
+
-
LOAD
FET
DRIVER
+
V
-
P1B
V-
V+
PIC16C717/770/771
FET
DRIVER
FET
DRIVER
P1A
+
-
LOAD
FET
DRIVER
FET
DRIVER
P1B
V-
2002 Microchip Technology Inc.
DS41120B-page 59
PIC16C717/770/771
In Full-Bridge Output mode, four pins are used as out-
puts; however, only two outputs are active at a time. In
the Forward mode, RB3/CCP1/P1A pin is continuously
active, and RB7/T1OSI/P1D pin is modulated. In the
Reverse mode, RB6/T1OSO/T1CKI/P1C pin is contin-
uously active, and RB5/SDO/P1B pin is modulated.
P1A, P1B, P1C and P1D outputs are multiplexed with
PORTB<3> and PORTB<5:7> data latches. TRISB<3>
and TRISB<5:7> bits must be cleared to make the P1A,
P1B, P1C, and P1D pins output.
FIGURE 8-8: FULL-BRIDGE PWM OUTPUT
FORWARD MODE
Period
(2)
1
0
P1A
Duty Cycle
1
0
(2)
(2)
P1B
1
0
P1C
1
0
(2)
P1D
(1)
(1)
REVERSE MODE
Period
Duty Cycle
1
0
(2)
(2)
P1A
P1B
1
0
1
0
(2)
(2)
P1C
P1D
1
0
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: Output signal is shown as asserted high.
DS41120B-page 60
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 8-9: EXAMPLE OF FULL-BRIDGE APPLICATION
V+
PIC16C717/770/771
FET
DRIVER
FET
DRIVER
P1D
+
-
LOAD
P1C
FET
DRIVER
FET
DRIVER
P1A
P1B
V-
2002 Microchip Technology Inc.
DS41120B-page 61
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shorting the bridge supply. To avoid this potentially
destructive shoot-through current from flowing during
switching, turning on the power switch is normally
delayed to allow the other switch to completely turn off.
8.3.5
PROGRAMMABLE DEADBAND
DELAY
In half-bridge or full-bridge applications, driven by half-
bridge outputs (see Figure 8-7), the power switches
normally require longer time to turn off than to turn on.
If both the upper and lower power switches are
switched at the same time (one turned on, and the
other turned off), both switches will be on for a short
period of time, until one switch completely turns off.
During this time, a very high current, called shoot-
through current, will flow through both power switches,
In the Half-Bridge Output mode, a digitally program-
mable deadband delay is available to avoid shoot-
through current from destroying the bridge power
switches. The delay occurs at the signal transition from
the non-active state to the active state. See Figure 8-6
for illustration. The P1DEL register sets the amount of
delay.
REGISTER 8-2: PWM DELAY REGISTER (P1DEL: 97H)
R/W-0
P1DEL7
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
P1DEL0
bit 0
P1DEL6
P1DEL5
P1DEL4
P1DEL3
P1DEL2
P1DEL1
bit 7-0
P1DEL<7:0>: PWM Delay Count for Half-Bridge Output Mode: Number of FOSC/4 (Tosc•4)
cycles between the P1A transition and the P1B transition.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
modulated outputs, P1A and P1C signals, will transition
to the new direction TOSC, 4•TOSC or 16•TOSC (for
Timer2 prescale T2CKRS<1:0> = 00, 01 and 1x
respectively) earlier, before the end of the period. Dur-
ing this transition cycle, the modulated outputs, P1B
and P1D, will go to the inactive state. See Figure 8-10
for illustration.
8.3.6
DIRECTION CHANGE IN FULL-
BRIDGE OUTPUT MODE
In the Full-Bridge Output mode, the PWM1M1 bit in the
CCP1CON register allows user to control the Forward/
Reverse direction. When the application firmware
changes this direction control bit, the ECCP module will
assume the new direction on the next PWM cycle. The
current PWM cycle still continues, however, the non-
FIGURE 8-10: PWM DIRECTION CHANGE
(1)
PERIOD
PERIOD
SIGNAL
DC
P1A (Active High)
P1B (Active High)
P1C (Active High)
(2)
P1D (Active High)
Note 1: The Direction bit in the ECCP Control Register (CCP1CON<PWM1M1>) is written anytime during the PWM cycle.
2: The P1A and P1C signals switch TOSC, 4*Tosc or 16*TOSC, depending on the Timer2 prescaler value, earlier when
changing direction. The modulated P1B and P1D signals are inactive at this time.
DS41120B-page 62
2002 Microchip Technology Inc.
PIC16C717/770/771
Note that in the Full-Bridge Output mode, the ECCP
module does not provide any deadband delay. In gen-
eral, since only one output is modulated at a time,
deadband delay is not required. However, there is a sit-
uation where a deadband delay might be required. This
situation occurs when all of the following conditions are
true:
example, since the turn off time of the power devices is
longer than the turn on time, a shoot-through current
flows through the power devices, QB and QD, for the
duration of t= toff-ton. The same phenomenon will occur
to power devices, QC and QB, for PWM direction
change from reverse to forward.
If changing PWM direction at high duty cycle is required
for the user’s application, one of the following require-
ments must be met:
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn off time of the power switch, including
the power device and driver circuit, is greater
than turn on time.
1. Avoid changing PWM output direction at or near
100% duty cycle.
2. Use switch drivers that compensate for the slow
turn off of the power devices. The total turn off
time (toff) of the power device and the driver
must be less than the turn on time (ton).
Figure 8-11 shows an example, where the PWM direc-
tion changes from forward to reverse at a near 100%
duty cycle. At time t1, the output P1A and P1D become
inactive, while output P1C becomes active. In this
FIGURE 8-11: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
FORWARD PERIOD
REVERSE PERIOD
1
0
P1A
P1B
1
0
(PWM)
1
0
P1C
1
0
P1D
(PWM)
t
on
1
0
External Switch C
t
off
1
0
External Switch D
Potential
Shoot Through
Current
t = t - t
1
0
off on
t
1
Note 1: All signals are shown as active high.
2: ton is the turn on delay of power switch and driver.
3: toff is the turn off delay of power switch and driver.
2002 Microchip Technology Inc.
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8.3.7
SYSTEM IMPLEMENTATION
8.3.9
SET UP FOR PWM OPERATION
When the ECCP module is used in the PWM mode, the
application hardware must use the proper external pull-
up and/or pull-down resistors on the PWM output pins.
When the microcontroller powers up, all of the I/O pins
are in the high-impedance state. The external pull-up
and pull-down resistors must keep the power switch
devices in the off state until the microcontroller drives
the I/O pins with the proper signal levels, or activates
the PWM output(s).
The following steps should be taken when configuring
the ECCP module for PWM operation:
1. Configure the PWM module:
a) Disable the CCP1/P1A, P1B, P1C and/or
P1D outputs by setting the respective
TRISB bits.
b) Set the PWM period by loading the PR2
register.
c) Set the PWM duty cycle by loading the
CCPR1L register and CCP1CON<5:4>
bits.
8.3.8
START-UP CONSIDERATIONS
Prior to enabling the PWM outputs, the P1A, P1B, P1C
and P1D latches may not be in the proper states.
Enabling the TRISB bits for output at the same time
with the CCP module may cause damage to the power
switch devices. The CCP1 module must be enabled in
the proper Output mode with the TRISB bits enabled as
inputs. Once the CCP1 completes a full PWM cycle,
the P1A, P1B, P1C and P1D output latches are prop-
erly initialized. At this time, the TRISB bits can be
enabled for outputs to start driving the power switch
devices. The completion of a full PWM cycle is indi-
cated by the TMR2IF bit going from a ’0’ to a ’1’.
d) Configure the ECCP module for the desired
PWM operation by loading the CCP1CON
register. With the CCP1M<3:0> bits select
the active high/low levels for each PWM
output. With the PWM1M<1:0> bits select
one of the available Output modes: Single,
Half-Bridge, Full-Bridge, Forward or Full-
Bridge Reverse.
e) For Half-Bridge Output mode, set the dead-
band delay by loading the P1DEL register.
2. Configure and start TMR2:
a) Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit in the PIR1 register.
b) Set the TMR2 prescale value by loading the
T2CKPS<1:0> bits in the T2CON register.
c) Enable Timer2 by setting the TMR2ON bit
in the T2CON register.
3. Enable PWM outputs after a new cycle has
started:
a) Wait until TMR2 overflows (TMR2IF bit
becomes a ’1’). The new PWM cycle begins
here.
b) Enable the CCP1/P1A, P1B, P1C and/or
P1D pin outputs by clearing the respective
TRISB bits.
TABLE 8-3:
REGISTERS ASSOCIATED WITH PWM
Value on
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
10Bh, 18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
8Ch
PIR1
PIE1
—
—
ADIF
ADIE
—
—
—
—
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF -0-- 0000 -0-- 0000
TMR1IE -0-- 0000 -0-- 0000
1111 1111 1111 1111
86h, 186h TRISB
PORTB Data Direction Register
Timer2 register
11h
TMR2
PR2
0000 0000 0000 0000
92h
Timer2 period register
1111 1111 1111 1111
12h
T2CON
CCPR1L
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h
Capture/Compare/PWM register1 (LSB)
PWM1M0 DC1B1 DC1B0
PWM1 Delay value
xxxx xxxx uuuu uuuu
CCP1M0 0000 0000 0000 0000
0000 0000 0000 0000
17h
CCP1CON PWM1M1
P1DEL
CCP1M3
CCP1M2
CCP1M1
97h
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by ECCP module in PWM mode.
Legend:
DS41120B-page 64
2002 Microchip Technology Inc.
PIC16C717/770/771
9.0
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, etc. The MSSP module can operate in one
of two modes:
• Serial Peripheral Interface (SPI™)
• Inter-Integrated Circuit (I2C™)
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REGISTER 9-1: SYNC SERIAL PORT STATUS REGISTER (SSPSTAT: 94h)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
SMP: Sample bit
SPI Master Mode
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in Slave mode
2
In I C Master or Slave mode:
1= Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for High Speed mode (400 kHz)
bit 6
CKE: SPI Clock Edge Select (Figure 9-3, Figure 9-5, and Figure 9-6)
CKP = 0
1= Data transmitted on rising edge of SCK
0= Data transmitted on falling edge of SCK
CKP = 1
1= Data transmitted on falling edge of SCK
0= Data transmitted on rising edge of SCK
2
bit 5
bit 4
D/A: Data/Address bit (I C mode only)
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
P: STOP bit
2
(I C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1= Indicates that a STOP bit has been detected last (this bit is ’0’ on RESET)
0= STOP bit was not detected last
bit 3
bit 2
S: START bit
2
(I C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1= Indicates that a START bit has been detected last (this bit is ’0’ on RESET)
0= START bit was not detected last
2
R/W: Read/Write bit information (I C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next START bit, STOP bit, or NACK bit.
2
In I C Slave mode:
1= Read
0= Write
2
In I C Master mode:
1= Transmit is in progress
0= Transmit is not in progress.
ORing this bit with SEN, RSEN, PEN, RCEN, or AKEN will indicate if the MSSP is in IDLE mode
2
bit 1
bit 0
UA: Update Address (10-bit I C mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
2
Receive (SPI and I C modes)
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
2
Transmit (I C mode only)
1= Data Transmit in progress (does not include the ACK and STOP bits), SSPBUF is full
0= Data Transmit complete (does not include the ACK and STOP bits), SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS41120B-page 66
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REGISTER 9-2: SYNC SERIAL PORT CONTROL REGISTER (SSPCON: 14h)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
Master Mode:
1= A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started
0= No collision
Slave Mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be
cleared in software)
0= No collision
bit 6
SSPOV: Receive Overflow Indicator bit
In SPI mode
1= A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave
mode, the user must read the SSPBUF, even if only transmitting data, to avoid setting over-
flow. In Master mode, the overflow bit is not set since each new reception (and transmis-
sion) is initiated by writing to the SSPBUF register. (Must be cleared in software).
0= No overflow
In I2C mode
1= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a
"don’t care" in Transmit mode. (Must be cleared in software).
0= No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, the I/O pins must be properly configured as input or output.
In SPI mode
1= Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port
pins
0= Disables serial port and configures these pins as I/O port pins
In I2C mode
1= Enables the serial port and configures the SDA and SCL pins as the source of the serial
port pins
0= Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
In SPI mode
1= IDLE state for clock is a high level
0= IDLE state for clock is a low level
In I2C Slave mode SCK release control
1= Enable clock
0= Holds clock low (clock stretch) (used to ensure data setup time)
In I2C Master mode
Unused in this mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2002 Microchip Technology Inc.
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REGISTER 9-2: SYNC SERIAL PORT CONTROL REGISTER (SSPCON: 14h) (CONTINUED)
bit 3-0
SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000= SPI Master mode, clock = FOSC/4
0001= SPI Master mode, clock = FOSC/16
0010= SPI Master mode, clock = FOSC/64
0011= SPI Master mode, clock = TMR2 output/2
0100= SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101= SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110= I2C Slave mode, 7-bit address
0111= I2C Slave mode, 10-bit address
1000= I2C Master mode, clock = FOSC / (4 • (SSPADD+1) )
1001= Reserved
1010= Reserved
1011= Firmware controlled Master mode (slave idle)
1100= Reserved
1101= Reserved
1110= 7-bit Slave mode with START and STOP condition interrupts
1111= 10-bit Slave mode with START and STOP condition interrupts
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS41120B-page 68
AdvanceInformation
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REGISTER 9-3: SYNC SERIAL PORT CONTROL REGISTER2 (SSPCON2: 91h)
R/W-0
GCEN
R/W-0
R/W-0
R/W-0
R/W-0
RCEN
R/W-0
PEN
R/W-0
RSEN
R/W-0
SEN
ACKSTAT ACKDT
ACKEN
bit 7
bit 0
bit 7
bit 6
GCEN: General Call Enable bit (In I2C Slave mode only)
1= Enable interrupt when a general call address (0000h) is received in the SSPSR.
0= General call address disabled.
ACKSTAT: Acknowledge Status bit (In I2C Master mode only)
In Master Transmit mode:
1= Acknowledge was not received from slave
0= Acknowledge was received from slave
bit 5
bit 4
ACKDT: Acknowledge Data bit (In I2C Master mode only)
In Master Receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of
a receive.
1= Not Acknowledge (NACK)
0= Acknowledge (ACK)
ACKEN: Acknowledge Sequence Enable bit (In I2C Master mode only).
In Master Receive mode:
1= Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0= Acknowledge sequence IDLE
bit 3
bit 2
RCEN: Receive Enable bit (In I2C Master mode only).
1= Enables Receive mode for I2C
0= Receive IDLE
PEN: STOP Condition Enable bit (In I2C Master mode only).
SCK Release Control
1= Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0= STOP condition IDLE
bit 1
bit 0
RSEN: Repeated START Condition Enabled bit (In I2C Master mode only)
1= Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by
hardware.
0= Repeated START condition IDLE
SEN: START Condition Enabled bit (In I2C Master mode only)
1= Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0= START condition IDLE
Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE
mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
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FIGURE 9-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
9.1
SPI Mode
The SPI mode allows eight bits of data to be synchro-
nously transmitted and received simultaneously. All
four modes of SPI are supported. To accomplish com-
munication, typically three pins are used:
Internal
Data Bus
Read
Write
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
SSPBUF reg
Additionally, a fourth pin may be used when in a Slave
mode of operation:
SSPSR reg
Shift
SDI
bit0
• Slave Select (SS)
Clock
9.1.1
OPERATION
SDO
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
Control
SS
Enable
SS
Edge
Select
• Master Mode (SCK is the clock output)
• Slave Mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
2
Clock Select
• Data input sample phase
(middle or end of data output time)
SSPM<3:0>
• Clock edge
(output data on rising/falling edge of SCK)
SMP:CKE
2
4
TMR2 Output
2
Edge
Select
• Clock Rate (Master mode only)
Tosc
Prescaler
4, 16, 64
• Slave Select Mode (Slave mode only)
SCK
Figure 9-1 shows the block diagram of the MSSP mod-
ule when in SPI mode.
Data to TX/RX in SSPSR
Data direction bit
The MSSP consists of a transmit/receive Shift Register
(SSPSR) and a Buffer Register (SSPBUF). The
SSPSR shifts the data in and out of the device, MSb
first. The SSPBUF holds the data that was written to the
SSPSR, until the received data is ready. Once the eight
bits of data have been received, that byte is moved to
the SSPBUF register. Then the buffer full detect bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF
(PIR1<3>), are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit WCOL (SSPCON<7>) will be
set. User software must clear the WCOL bit so that it
can be determined if the following write(s) to the SSP-
BUF register completed successfully.
DS41120B-page 70
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2002 Microchip Technology Inc.
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When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
full bit, BF (SSPSTAT<0>), indicates when the SSP-
BUF has been loaded with the received data (transmis-
sion is complete). When the SSPBUF is read, bit BF is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the MSSP Interrupt is used to
determine when the transmission/reception has com-
pleted. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 9-1 shows the loading of the SSP-
BUF (SSPSR) for data transmission.
9.1.2
ENABLING SPI I/O
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
isters, and then set bit SSPEN. This configures the
SDI, SDO, SCK and SS pins as serial port pins. For the
pins to behave as the serial port function, some must
have their data direction bits (in the TRIS register)
appropriately programmed. That is:
• SDI is automatically controlled by the SPI module
• SDO must have TRISB<5> cleared
• SCK (Master mode) must have TRISB<2>
cleared
• SCK (Slave mode) must have TRISB<2> set
EXAMPLE 9-1:
Loading the SSPBUF
(SSPSR) Register
STATUS, RP0 ;Specify Bank 1
• SS must have TRISB<1> set, and ANSEL<5>
cleared
BSF
Any serial port function that is not desired may be over-
ridden by programming the corresponding data direc-
tion (TRIS) register to the opposite value.
LOOP BTFSS SSPSTAT, BF
;Has data been
;received
;(xmit complete)?
;No
GOTO LOOP
BCF
STATUS, RP0
;Specify Bank 0
;Save SSPBUF...
;...in user RAM
;Get next TXDATA
;New data to xmit
9.1.3
TYPICAL CONNECTION
MOVF SSPBUF, W
MOVWF RXDATA
MOVF TXDATA, W
MOVWF SSPBUF
Figure 9-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge, and latched on the opposite
edge of the clock. Both processors should be pro-
grammed to same Clock Polarity (SSPCON<4>), then
both controllers would send and receive data at the
same time. Whether the data is meaningful (or dummy
data) depends on the application software. This leads
to three scenarios for data transmission:
The SSPSR is not directly readable or writable, and
can only be accessed by addressing the SSPBUF reg-
ister. Additionally, the MSSP STATUS register
(SSPSTAT) indicates the various status conditions.
• Master sends data — Slave sends dummy data
• Master sends data — Slave sends data
• Master sends dummy data — Slave sends data
FIGURE 9-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xxb
SDO
SPI Slave SSPM<3:0> = 010xb
SDI
Serial Input Buffer
(SSPBUF)
Serial Input Buffer
(SSPBUF)
SDI
SDO
Shift Register
Shift Register
(SSPSR)
(SSPSR)
LSb
MSb
MSb
LSb
Serial Clock
SCK
SCK
PROCESSOR 1
PROCESSOR 2
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PIC16C717/770/771
Figure 9-3, Figure 9-5 and Figure 9-6, where the MSb
is transmitted first. In Master mode, the SPI clock rate
(bit rate) is user programmable to be one of the follow-
ing:
9.1.4
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 9-2) is to broad-
cast data by the software protocol.
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI
module is only going to receive, the SDO output could
be disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “line activity monitor”.
This allows a maximum bit clock frequency (at 20 MHz)
of 8.25 MHz.
Figure 9-3 shows the waveforms for Master mode.
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
shown.
The clock polarity is selected by appropriately program-
ming bit CKP (SSPCON<4>). This then would give
waveforms for SPI communication as shown in
FIGURE 9-3:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
bit6
bit6
bit2
bit2
bit5
bit5
bit4
bit4
bit1
bit1
bit0
bit0
SDO
(CKE = 0)
bit7
bit7
bit3
bit3
SDO
(CKE = 1)
SDI
(SMP = 0)
bit0
bit7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit0
bit7
Input
Sample
(SMP = 1)
SSPIF
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
DS41120B-page 72
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2002 Microchip Technology Inc.
PIC16C717/770/771
SDO pin is driven. When the SS pin goes high, the
SDO pin is no longer driven, even if in the middle of
a transmitted byte, and becomes a floating output.
External pull-up/ pull-down resistors may be desir-
able, depending on the application.
9.1.5
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched the interrupt flag bit SSPIF (PIR1<3>)
is set.
Note 1: When the SPI module is in Slave mode
with SS pin control enabled, (SSP-
CON<3:0> = 0100) the SPI module will
RESET if the SS pin is set to VDD.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
2: If the SPI is used in Slave Mode with
CKE = ’1’, then SS pin control must be
enabled.
While in SLEEP mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from SLEEP.
When the SPI module RESETS, the bit counter is
forced to 0. This can be done by either forcing the SS
pin to a high level or clearing the SSPEN bit.
9.1.6
SLAVE SELECT
SYNCHRONIZATION
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control
enabled (SSPCON<3:0> = 0100). The pin must not
be driven low for the SS pin to function as an input.
TRISB<1> must be set. When the SS pin is low,
transmission and reception are enabled and the
FIGURE 9-4:
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit6
bit7
bit7
bit0
bit0
SDO
bit7
SDI
(SMP = 0)
bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
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PIC16C717/770/771
FIGURE 9-5:
SPI SLAVE MODE WAVEFORM (CKE = 0)
SS
optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit6
bit2
bit5
bit4
bit1
bit0
SDO
bit7
bit3
SDI
(SMP = 0)
bit0
bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
FIGURE 9-6:
SPI SLAVE MODE WAVEFORM (CKE = 1)
SS
not optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
bit6
bit2
bit5
bit4
bit1
bit0
bit0
SDO
bit7
bit7
bit3
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
DS41120B-page 74
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2002 Microchip Technology Inc.
PIC16C717/770/771
9.1.7
SLEEP OPERATION
9.1.8
EFFECTS OF A RESET
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
Normal mode, the module will continue to transmit/
receive data.
A RESET disables the MSSP module and terminates
the current transfer.
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode and data to be
shifted into the SPI transmit/receive shift register.
When all eight bits have been received, the SSPIF
interrupt flag bit will be set and if enabled will wake the
device from SLEEP.
TABLE 9-1:
REGISTERS ASSOCIATED WITH SPI OPERATION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR MCLR, WDT
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
8Ch
13h
14h
94h
9Dh
86h
PIR1
PIE1
—
—
ADIF
ADIE
—
—
—
—
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF -0-- 0000 -0-- 0000
TMR1IE -0-- 0000 -0-- 0000
xxxx xxxx uuuu uuuu
SSPBUF
SSPCON
SSPSTAT
ANSEL
TRISB
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
SMP
SSPOV
CKE
SSPEN
D/A
CKP
P
SSPM3
S
SSPM2
R/W
SSPM1
UA
SSPM0 0000 0000 0000 0000
BF
0000 0000 0000 0000
--11 1111 --11 1111
1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by the MSSP in SPI mode.
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PIC16C717/770/771
2
transferred from the SSPSR register to the SSPBUF
register and flag bit SSPIF is set. If another complete
byte is received before the SSPBUF register is read a
receiver overflow occurs, in which case, the SSPOV bit
(SSPCON<6>) is set and the byte in the SSPSR is lost.
9.2
MSSP I C Operation
The MSSP module in I2C mode fully implements all
master and slave functions (including general call sup-
port) and provides interrupts on START and STOP bits
in hardware to determine when the bus is free (multi-
master function). The MSSP module implements the
Standard mode specifications, as well as 7-bit and 10-
bit addressing.
FIGURE 9-7: I2C SLAVE MODE BLOCK
DIAGRAM
Internal
Data Bus
Two pins are used to transfer data. They are the SCL
pin (clock) and the SDA pin (data). The MSSP module
functions are enabled by setting SSP Enable bit
SSPEN (SSPCON<5>). The SCL and SDA pins are
"glitch" filtered when operating as inputs. This filter
functions in both the 100 kHz and 400 kHz modes.
When these pins operate as outputs in the 100 kHz
mode, there is a slew rate control of the pin that is inde-
pendent of device frequency.
Before selecting any I2C mode, the SCL and SDA pins
must be programmed as inputs by setting the appropri-
ate TRIS bits. This allows the MSSP module to configure
and drive the I/O pins as required by the I2C protocol.
Read
Write
RB2/SCK/
SCL
SSPBUF reg
SSPSR reg
Shift
Clock
RB4/SDI/
SDA
MSb
LSb
Addr Match
Match detect
SSPADD reg
The MSSP module has six registers for I2C operation.
They are listed below.
Set, RESET
S, P bits
START and
STOP bit detect
• SSP Control Register (SSPCON)
(SSPSTAT reg)
• SSP Control Register2 (SSPCON2)
• SSP STATUS Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly accessible
• SSP Address Register (SSPADD)
The SSPCON register allows for control of the I2C
operation. Four mode selection bits (SSPCON<3:0>)
configure the MSSP as any one of the following I2C
modes:
9.2.1
UPWARD COMPATIBILITY WITH
SSP MODULE
The MSSP module includes three SSP modes of oper-
ation to maintain upward compatibility with the SSP
module. These modes are:
• Firmware controlled Master mode (slave idle)
• 7-bit Slave mode with START and STOP
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Master mode
condition interrupts.
• 10-bit Slave mode with START and STOP
condition interrupts.
SCL Freq = FOSC / [4 • (SSPADD + 1)]
The firmware controlled Master mode enables the
START and STOP condition interrupts but all other I2C
functions are generated through firmware including:
• I2C Slave mode with START and STOP interrupts
(7-bit address)
• I2C Slave mode with START and STOP interrupts
(10-bit address)
• Generating the START and STOP conditions
• Generating the SCL clock
• Firmware Controlled Master mode
• Supplying the SDA bits in the proper time and
phase relationship to the SCL signal.
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START (S) or STOP (P) bit. It specifies whether the
received byte was data or address, if the next byte is
the completion of 10-bit address, and if this will be a
read or write data transfer.
In firmware controlled Master mode, the SCL and SDA
lines are manipulated by clearing and setting the corre-
sponding TRIS bits. The output level is always low irre-
spective of the value(s) in the PORT register. A ‘1’ is
output by setting the TRIS bit and a ‘0’ is output by
clearing the TRIS bit
SSPBUF is the register to which the transfer data is
written, and from which the transfer data is read. The
SSPSR register shifts the data in or out of the device.
In receive operations, the SSPBUF and SSPSR create
a doubled, buffered receiver. This allows reception of
the next byte to begin before reading the last byte of
received data. When the complete byte is received, it is
The 7-bit and 10-bit Slave modes with START and
STOP condition interrupts operate identically to the
MSSP Slave modes except that START and STOP
conditions generate SSPIF interrupts.
DS41120B-page 76
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2002 Microchip Technology Inc.
PIC16C717/770/771
For more information about these SSP modes see Sec-
tion 15 of the PICmicro™ Mid-Range MCU Family Ref-
erence Manual (DS33023).
9.2.2.2
10-BIT ADDRESSING
In 10-bit mode, the basic receive and transmit opera-
tions are the same as in the 7-bit mode. However, the
criteria for address match are more complex.
9.2.2
SLAVE MODE
Two address bytes need to be received by the slave.
The five Most Significant bits (MSbs) of the first
address byte specify that this is a 10-bit address. The
LSb of the first received address byte is the R/W bit,
which must be zero, specifying a write so the slave
device will receive the second address byte. For a 10-
bit address, the first byte equals ‘11110 A9 A8 0’,
where A9 and A8 are the two MSbs of the address. The
sequence of events for a 10-bit address is as follows,
with steps 7 through 9 applicable only to the slave-
transmitter:
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse.
Then, it loads the SSPBUF register with the received
value currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module to generate a NACK pulse in lieu of
the ACK pulse:
a) The buffer full bit BF (SSPSTAT<0>) is set
before the transfer is received.
b) The overflow bit SSPOV (SSPCON<6>) is set
before the transfer is received.
1. Receive first (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
If the BF bit is set, the SSPSR register value is not
loaded into the SSPBUF. However, both the SSPIF and
SSPOV bits are set. Table 9-2 shows what happens
when a data transfer byte is received, given the status
of bits BF and SSPOV. The shaded cells show the con-
dition where user software did not properly clear the
overflow condition. The BF flag bit is cleared by reading
the SSPBUF register. The SSPOV flag bit is cleared
through software.
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
5. Update the SSPADD register with the first (high)
byte of Address. This will clear bit UA and
release the SCL line.
The SCL clock input must have a minimum high and
low time for proper operation. The high and low times
of the I2C specification as well as the requirements of
the MSSP module are shown in timing parameters
#100 and #101 of the Electrical Specifications.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive Repeated START condition.
8. Receive first (high) byte of Address with R/W bit
set to 1 (bits SSPIF and BF are set). This also
puts the MSSP module in the Slave-transmit
mode.
9.2.2.1
7-BIT ADDRESSING
Once the MSSP module has been enabled
(SSPEN=1), the slave module waits for a START con-
dition to occur. Following the START condition, eight
bits are shifted into the SSPSR register. All incoming
bits are sampled on the rising edge of the clock (SCL)
line. The received address (register SSPSR<7:1>) is
compared to the stored address (register
SSPADD<7:1>). SSPSR<0> is the R/W bit and is not
considered in the comparison. Comparison is made on
the falling edge of the eighth clock (SCL) pulse. If the
addresses match, and the BF and SSPOV bits are
clear, the following events occur:
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Note: Following the Repeated START condition
(step 7) in 10-bit mode, the user only
needs to match the first 7-bit address. The
user does not update the SSPADD for the
second half of the address.
a) The SSPSR register value is transferred to the
SSPBUF register on the falling edge of the
eighth SCL pulse.
b) The buffer full bit; BF is set on the falling edge of
the eighth SCL pulse.
c) An ACK pulse is generated during the ninth
clock cycle.
d) SSP interrupt flag bit; SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
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9.2.2.3
SLAVE RECEPTION
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the received byte.
When the R/W bit of the address byte is clear
(SSPSR<0> = 0) and an address match occurs, the R/
W bit of the SSPSTAT register is cleared. The received
address is loaded into the SSPBUF register on the fall-
ing edge of the eighth SCL pulse.
Note: The SSPBUF will be loaded if the SSPOV
bit is set and the BF flag is cleared. If a
read of the SSPBUF was performed, but
the user did not clear the state of the
SSPOV bit before the next receive
occurred, the ACK is not sent and the SSP-
BUF is updated.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) or
bit SSPOV (SSPCON<6>) is set.
TABLE 9-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
Set bit SSPIF
Generate ACK
Pulse
(SSP Interrupt occurs
if enabled)
BF
SSPOV
SSPSR → SSPBUF
0
1
1
0
0
0
1
1
Yes
No
Yes
No
No
No
Yes
Yes
Yes
Yes
No
Yes
Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
FIGURE 9-8:
I2C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Receiving Address R/W=0 ACK
A3 A2 A1
Receiving Data
Receiving Data
ACK
NACK
A7 A6 A5 A4
SDA
D5
D2
6
D0
8
D5
3
D2
6
D0
8
D7 D6
D4 D3
D1
7
D7 D6
D4 D3
D1
7
3
9
7
1
2
4
9
5
4
3
6
9
5
1
2
1
2
4
8
5
P
SCL
S
SSPIF
Bus Master
terminates
transfer
BF (SSPSTAT<0>)
Cleared in software
SSPBUF register is read
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
NACK is sent because of overflow
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FIGURE 9-9:
I2C SLAVE MODE FOR RECEPTION (10-BIT ADDRESS)
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9.2.2.4
SLAVE TRANSMISSION
sending a NACK. If the SDA line is high (NACK), then
the data transfer is complete. When the NACK is
latched by the slave, the slave logic is RESET which
also resets the R/W bit to ’0’. The slave module then
monitors for another occurrence of the START bit. The
slave firmware knows not to load another byte into the
SSPBUF register by sensing that the buffer is empty
(BF = 0) and the R/W bit has gone low. If the SDA line
is low (ACK), the R/W bit remains high indicating that
the next transmit data must be loaded into the SSPBUF
register.
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the SSP-
STAT register is set. The received address is loaded
into the SSPBUF register on the falling edge of the
eighth SCL pulse. The ACK pulse will be sent on the
ninth bit, and the SCL pin is held low. The slave module
automatically stretches the clock by holding the SCL
line low so that the master will be unable to assert
another clock pulse until the slave is finished preparing
the transmit data. The transmit data must be loaded
into the SSPBUF register, which also loads the SSPSR
register. The CKP bit (SSPCON<4>) must then be set
to release the SCL pin from the forced low condition.
The eight data bits are shifted out on the falling edges
of the SCL input. This ensures that the SDA signal is
valid during the SCL high time (Figure 9-10).
An MSSP interrupt (SSPIF flag) is generated for each
data transfer byte on the falling edge of the ninth clock
pulse. The SSPIF flag bit must be cleared in software.
The SSPSTAT register is used to determine the status
of the byte transfer.
For more information about the I2C Slave mode, refer
to Application Note AN734, “Using the PICmicro® SSP
for Slave I2C™ Communication”.
The ACK or NACK signal from the master-receiver is
latched on the rising edge of the ninth SCL input pulse.
The master-receiver terminates slave transmission by
FIGURE 9-10:
I2C SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
R/W ← 0
Transmitting Data
Receiving Address
NACK
R/W = 1
SDA
A7 A6 A5 A4 A3 A2 A1
ACK
D7 D6 D5 D4 D3 D2 D1 D0
SCL
S
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
P
SCL held low
Data in
sampled
Master terminates transmission
by responding with NACK
until SSPBUF
is written
SSPIF
BF (SSPSTAT<0>)
cleared in software
SSPBUF is written in software
From SSP interrupt
service routine
CKP (SSPCON<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
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2
FIGURE 9-11:
I C SLAVE MODE WAVEFORMS FOR TRANSMISSION (10-BIT ADDRESS)
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into the SSPSR, and the address is compared against
SSPADD. It is also compared to the general call
address, fixed in hardware.
9.2.3
GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master. The exception is the general call address,
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit),
the SSPIF flag is set.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
SSPBUF to determine if the address was device spe-
cific or a general call address.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0
If the general call address is sampled with GCEN set
and the slave configured in 10-bit Address mode, the
second half of the address is not necessary. The UA bit
will not be set and the slave will begin receiving data
after the Acknowledge (Figure 9-12).
The general call address is recognized when the Gen-
eral Call Enable bit (GCEN) is set (SSPCON2<7> is
set). Following a START bit detect, eight bits are shifted
FIGURE 9-12:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7- OR 10-BIT MODE)
Address is compared to General Call Address
after ACK, set interrupt flag
Receiving data
R/W = 0
General Call Address
ACK
9
ACK
SDA
SCL
D7 D6
D5 D4
D3 D2 D1
D0
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
S
SSPIF
BF
(SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV
(SSPCON<6>)
’0’
’1’
GCEN
(SSPCON2<7>)
DS41120B-page 82
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9.2.4
SLEEP OPERATION
9.2.6
MASTER MODE
While in SLEEP mode, the I2C slave module can
receive addresses or data. When an address match or
complete byte transfer occurs, it wakes the processor
from SLEEP (if the SSP interrupt bit is enabled).
Master mode operation supports interrupt generation
on the detection of the START and STOP conditions.
The STOP (P) and START (S) bits are cleared from a
RESET or when the MSSP module is disabled. Control
of the I2C bus may be taken when the P bit is set or the
bus is idle with both the S and P bits clear.
9.2.5
EFFECTS OF A RESET
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
A RESET disables the MSSP module and terminates
the current transfer.
The following events will cause SSP Interrupt Flag bit
(SSPIF) to be set (SSP Interrupt, if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated START
2
FIGURE 9-13:
MSSP BLOCK DIAGRAM (I C MASTER MODE)
Internal
Data Bus
SSPM<3:0>,
SSPADD<6:0>
Read
Write
SSPBUF
SSPSR
Baud
Rate
Generator
SDA
Shift
Clock
SDA in
MSb
LSb
START bit, STOP bit,
Acknowledge
Generate
SCL
START bit detect,
STOP bit detect
Write collision detect
Clock Arbitration
State counter for
end of XMIT/RCV
SCL in
Bus Collision
Set/RESET, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
RESET ACKSTAT, PEN (SSPCON2)
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9.2.7
MULTI-MASTER OPERATION
9.2.9
BAUD RATE GENERATOR
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the MSSP module is disabled. Control of the I2C
bus may be taken when bit P (SSPSTAT<4>) is set, or
the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP Interrupt will gener-
ate the interrupt when the STOP condition occurs.
The baud rate generator used for SPI mode operation
is used in the I2C Master mode to set the SCL clock fre-
quency. Standard SCL clock frequencies are 100 kHz,
400 kHz, and 1 MHz. One of these frequencies can be
achieved by setting the SSPADD register to the appro-
priate number for the selected Fosc frequency. One
half of the SCL period is equal to
[(SSPADD+1) •2]/Fosc.
The baud rate generator reload value is contained in
the lower seven bits of the SSPADD register (Figure 9-
14). When the BRG is loaded with this value, the BRG
counts down to 0 and stops until another reload occurs.
The BRG count is decremented twice per instruction
cycle (TCY) on the Q2 and Q4 clock.
In multi-master operation, the SDA line must be moni-
tored for arbitration to see if the signal level is the
expected output level. This check is performed in hard-
ware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
In I2C Master mode, the BRG is reloaded automatically
provided that the SCL line is sampled high. For exam-
ple, if Clock Arbitration is taking place, the BRG reload
will be suppressed until the SCL line is released by the
slave allowing the pin to float high (Figure 9-15).
• Address Transfer
• Data Transfer
• A START Condition
• A Repeated START Condition
• An Acknowledge Condition
FIGURE 9-14:
BAUD RATE GENERATOR
BLOCK DIAGRAM
Refer to Application Note AN578, "Use of the SSP
Module in the I2C™ Multi-Master Environment."
SSPM<3:0>
SSPADD<6:0>
9.2.8
I2C MASTER OPERATION
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. Once Master mode is enabled, the user
has six options.
SSPM<3:0>
SCL
Reload
Control
Reload
1. Assert a START condition on SDA and SCL.
Fosc/2
BRG Down Counter
BRG CLKOUT
2. Assert a Repeated START condition on SDA
and SCL.
3. Write to the SSPBUF register initiating transmis-
sion of data/address.
4. Generate a STOP condition on SDA and SCL.
5. Configure the I2C port to receive data.
6. Generate an Acknowledge condition at the end
of a received byte of data.
The master device generates all serial clock pulses and
the START and STOP conditions. A transfer is ended
with a STOP condition or with a Repeated START con-
dition. Since the Repeated START condition is also the
beginning of the next serial transfer, the I2C bus will not
be released.
Note: The MSSP Module, when configured in I2C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
initiate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to, and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
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FIGURE 9-15:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL de-asserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
SCL
BRG decrements
(on Q2 and Q4 cycles)
BRG
value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place, and BRG starts its count.
BRG
reload
9.2.10
I2C MASTER MODE START
CONDITION TIMING
Note: If at the beginning of START condition, the
SDA and SCL pins are already sampled
low, or if during the START condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs.
Thus, the Bus Collision Interrupt Flag
(BCLIF) is set, the START condition is
aborted, and the I2C module is RESET into
its IDLE state.
To initiate a START condition, the user sets the START
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, indicating that the bus
is available, the baud rate generator is loaded with the
contents of SSPADD<6:0> and starts its count. If SCL
and SDA are both sampled high when the baud rate
generator times out (TBRG) indicating the bus is still
available, the SDA pin is driven low. The SDA transition
from high to low while SCL is high is the START condi-
tion. This causes the S bit (SSPSTAT<3>) to be set.
When the S bit is set, the baud rate generator is
reloaded with the contents of SSPADD<6:0> and
resumes its count. When the baud rate generator times
out (TBRG) the START condition is complete, concur-
rent with the following events:
9.2.10.1 WCOL STATUS FLAG
If the user writes the SSPBUF when a START
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
Note: Because queueing of events is not
allowed, writing to the lower five bits of
SSPCON2 is disabled until the START
condition is complete.
• The SEN bit (SSPCON2<0>) is automatically
cleared by hardware,
• The baud rate generator is suspended leaving the
SDA line held low.
• The SSPIF flag is set.
FIGURE 9-16:
FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
Write to SEN bit occurs here.
SDA = 1,
At completion of START bit,
Hardware clears SEN bit
and sets SSPIF bit
SCL = 1
TBRG
TBRG
Write to SSPBUF occurs here
2nd Bit
1st Bit
SDA
TBRG
SCL
TBRG
S
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I2C MASTER MODE REPEATED
START CONDITION TIMING
Immediately following the SSPIF bit transition to true,
the user may write the SSPBUF with the 7-bit address
in 7-bit mode, or the default first address in 10-bit
mode. After the first eight bits are transmitted and an
ACK is received, the user may then perform one of the
following:
9.2.11
A Repeated START condition occurs when the RSEN
bit (SSPCON2<1>) is set high while the I2C module is
in the idle state. When the RSEN bit is set, the SCL pin
is asserted low. When the SCL pin is sampled low, the
baud rate generator is loaded with the contents of
SSPADD<6:0> and begins counting. The SDA pin is
released (brought high) for one baud rate generator
count (TBRG). When the baud rate generator times out,
if SDA is sampled high, the SCL pin will be de-asserted
(brought high). When SCL is sampled high, the baud
rate generator is reloaded with the contents of
SSPADD<6:0> and begins counting. SDA and SCL
must be sampled high for one TBRG period. This action
is then followed by assertion of the SDA pin (SDA is
low) for one TBRG period while SCL is high. As soon as
a START condition is detected on the SDA and SCL
pins, the S bit (SSPSTAT<3>) will be set. Following
this, the baud rate generator is reloaded with the con-
tents of SSPAD<6:0> and begins counting. When the
BRG times out a third time, the RSEN bit in the
SSPCON2 register is automatically cleared and SCL is
pulled low. The SSPIF flag is set, which indicates the
Restart sequence is complete.
• Transmit an additional eight bits of address (if the
user transmitted the first half of a 10-bit address
with R/W = 0),
• Transmit eight bits of data (if the user transmitted
a 7-bit address with R/W = 0), or
• Receive eight bits of data (if the user transmitted
either the first half of a 10-bit address or a 7-bit
address with R/W = 1).
9.2.11.1 WCOL STATUS FLAG
If the user writes the SSPBUF when a Repeated
START sequence is in progress, then WCOL is set and
the contents of the buffer are unchanged (the write
doesn’t occur).
Note: Because queueing of events is not
allowed, writing of the lower five bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
Note 1: If RSEN is set while another event is in
progress, it will not take effect. Queuing of
events is not allowed.
2: A bus collision during the Repeated
START condition occurs if either of the
following is true:
a) SDA is sampled low when SCL
goes from low to high.
b) SCL goes low before SDA is
asserted low. This may indicate
that another master is attempting
to transmit a data “1”.
FIGURE 9-17:
REPEAT START CONDITION WAVEFORM
Set S (SSPSTAT<3>)
Write to SSPCON2
occurs here.
SDA = 1,
SDA = 1,
SCL = 1
At completion of START bit,
hardware clears RSEN bit
and sets SSPIF
SCL (no change)
TBRG TBRG
TBRG
1st Bit
SDA
Write to SSPBUF occurs here.
TBRG
Falling edge of ninth clock
End of Xmit
SCL
TBRG
Sr = Repeated START
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I2C MASTER MODE
TRANSMISSION
A typical transmit sequence would go as follows:
9.2.12
a) The user generates a START Condition by set-
ting the START enable bit (SEN) in SSPCON2.
In Master-transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains seven bits of address
data and the Read/Write (R/W) bit. In this case, the R/
W bit will be logic ’0’. Subsequent serial data is trans-
mitted eight bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the
end of a serial transfer.
b) SSPIF is set at the completion of the START
sequence.
c) The user resets the SSPIF bit and loads the
SSPBUF with seven bits of address plus R/W bit
to transmit.
d) Address and R/W is shifted out the SDA pin until
all eight bits are transmitted.
e) The MSSP Module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register (SSPCON2<6>).
Transmission of a data byte, a 7-bit address, or either
half of a 10-bit address is accomplished by simply writ-
ing a value to the SSPBUF register. This action will set
the buffer full flag (BF) and allow the baud rate genera-
tor to begin counting and start the next transmission.
Each bit of address/data will be shifted out onto the
SDA pin after the falling edge of SCL is asserted (see
data hold time spec). SCL is held low for one baud rate
generator roll over count (TBRG). Data should be valid
before SCL is released high (see data setup time
spec). When the SCL pin is released high, it is held that
way for TBRG, the data on the SDA pin must remain sta-
ble for that duration and some hold time after the next
falling edge of SCL. After the eighth bit is shifted out
(the falling edge of the eighth clock), the BF flag is
cleared and the master releases SDA. This allows the
slave device being addressed to respond with an ACK
bit during the ninth bit time. The status of ACK is read
into the ACKDT on the rising edge of the ninth clock. If
the master receives an Acknowledge, the Acknowl-
edge status bit (ACKSTAT) is cleared. Otherwise, the
bit is set. The SSPIF is set on the falling edge of the
ninth clock, and the master clock (baud rate generator)
is suspended until the next data byte is loaded into the
SSPBUF leaving SCL low and SDA unchanged
(Figure 9-18).
f) The module generates an interrupt at the end of
the ninth clock cycle by setting SSPIF.
g) The user resets the SSPIF bit and loads the
SSPBUF with eight bits of data.
h) DATA is shifted out the SDA pin until all eight bits
are transmitted.
i) The MSSP Module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
j) The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
k) The user resets the SSPIF bit and generates a
STOP condition by setting the STOP enable bit
PEN in SSPCON2.
l) SSPIF is set when the STOP condition is complete.
9.2.12.1 BF STATUS FLAG
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all eight bits are shifted out.
9.2.12.2 WCOL STATUS FLAG
If the user writes the SSPBUF when a transmit is
already in progress (i.e. SSPSR is still shifting out a
data byte), then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
9.2.12.3 ACKSTAT STATUS FLAG
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0), and is set when the slave does not Acknowl-
edge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
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2
FIGURE 9-18:
I CMASTERMODEWAVEFORMSFORTRANSMISSION(7OR10-BITADDRESS)
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I2C MASTER MODE RECEPTION
A typical receive sequence would go as follows:
9.2.13
a) The user generates a START Condition by set-
ting the START enable bit (SEN) in SSPCON2.
In Master-receive mode, the first byte transmitted con-
tains seven bits of address data and the R/W bit. In this
case, the R/W bit will be logic ’1’. Thus, the first byte
transmitted is a 7-bit slave address followed by a ’1’ to
indicate receive. Serial data is received via SDA, while
SCL outputs the serial clock. Serial data is received
eight bits at a time. After each byte is received, an
Acknowledge bit is transmitted. The START condition
indicates the beginning of a transmission. The master-
receiver terminates slave transmission by responding
to the last byte with a NACK Acknowledge and follows
this with a STOP condition to indicate to other masters
that the bus is free.
b) SSPIF is set at the completion of the START
sequence.
c) The user resets the SSPIF bit and loads the
SSPBUF with seven bits of address in the MSbs
and the LSb (R/W bit) set to '1' for receive.
d) Address and R/W is shifted out the SDA pin until
all eight bits are transmitted.
e) The MSSP Module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register (SSPCON2<6>).
f) The module generates an interrupt at the end of
the ninth clock cycle by setting SSPIF.
Master mode reception is enabled by setting the
receive enable bit, RCEN (SSPCON2<3>), immedi-
ately following the Acknowledge sequence.
g) The user resets the SSPIF bit and sets the
RCEN bit to enable reception.
Note: The MSSP Module must be in an IDLE
STATE before the RCEN bit is set or the
RCEN bit will be disregarded.
h) DATA is shifted into the SDA pin until all eight
bits are received.
i) The MSSP module sets the SSPIF bit and clears
the RCEN bit at the falling edge of the eighth
clock.
The baud rate generator begins counting, and on each
rollover, the state of the SCL pin changes (high to low/
low to high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the following events
occur:
j) The user resets the SSPIF bit and sets the
ACKDT bit to '0' (ACK), if another byte is antici-
pated. Otherwise, the ACKDT bit is set to '1'
(NACK) to terminate reception. The user sets
ADKEN to start the Acknowledge sequence.
• The receive enable bit is automatically cleared.
• The contents of the SSPSR are loaded into the
SSPBUF.
k) The MSSP module sets the SSPIF bit at the
completion of the Acknowledge.
• The BF flag is set.
• The SSPIF is set.
l) If a NACK was sent in step ( j), then the user pro-
ceeds with step ( m). Otherwise, reception con-
tinues by repeating steps ( g) through ( j).
• The baud rate generator is suspended from
counting, holding SCL low.
m) The user generates a STOP condition by setting
the STOP enable bit PEN in SSPCON2.
The SSP is now in IDLE state, awaiting the next com-
mand. When the buffer is read by the CPU, the BF flag
is automatically cleared. The user can then send an
Acknowledge bit at the end of reception by clearing the
ACKDT bit (SSPCON2<5>) and setting the Acknowl-
edge sequence enable bit, ACKEN (SSPCON2<4>).
n) SSPIF is set when the STOP condition is complete.
9.2.13.1 BF STATUS FLAG
In receive operation, BF is set when an address or data
byte is loaded into SSPBUF from SSPSR. It is cleared
by hardware when SSPBUF is read.
9.2.13.2 SSPOV STATUS FLAG
In receive operation, SSPOV is set when eight bits are
received into the SSPSR and the BF flag is already set
from a previous reception.
9.2.13.3 WCOL STATUS FLAG
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), then WCOL is set and the contents of the buffer
are unchanged (the write doesn’t occur).
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2
FIGURE 9-19:
I C MASTER WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
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arbitration), the baud rate generator is reloaded and
counts for another TBRG. At the completion of the TBRG
period, the following events occur (see Figure 9-20):
9.2.14
ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge sequence enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
ACKDT (SSPCON2<5>) is presented on the SDA pin.
If the user wishes to generate an Acknowledge (ACK),
then the ACKDT bit should be cleared. Otherwise, the
user should set the ACKDT bit (NACK) before starting
an Acknowledge sequence. The baud rate generator is
then loaded from SSPADD<6:0> and counts for one
rollover period (TBRG). The SCL pin is then de-asserted
(pulled high). When the SCL pin is sampled high (clock
• The SCL pin is pulled low.
• The ACKEN bit is automatically cleared.
• The baud rate generator is turned off.
• The MSSP module goes into IDLE mode.
9.2.14.1 WCOL STATUS FLAG
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 9-20:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
Write to SSPCON2
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
TBRG
SDA
SCL
D0
ACK
8
9
SSPIF
Cleared in
software
SSPIF occurs at the
end of receive
Cleared in
software
SSPIF occurs at the end
of Acknowledge sequence
Note: TBRG = one baud rate generator period.
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times out (TBRG) the STOP condition is complete and
the PEN bit is cleared and the SSPIF bit is set
(Figure 9-21).
9.2.15
STOP CONDITION TIMING
The master asserts a STOP condition on the SDA and
SCL pins at the end of a receive/transmit by setting the
Stop Sequence Enable bit PEN (SSPCON2<2>). At the
end of a receive/transmit plus Acknowledge, the SCL
line is held low immediately following the falling edge of
the ninth SCL pulse. When the PEN bit is set, the mas-
ter will assert the SDA line low. When the SDA line is
sampled low, the baud rate generator is loaded from
SSPADD<6:0> and counts down to 0. When the baud
rate generator times out, the SCL pin is brought high,
the BRG is reloaded and one TBRG (baud rate genera-
tor rollover count) later, the SDA pin is de-asserted.
The SDA pin transition from low to high while SCL is
high is the STOP condition and causes the P bit (SSP-
STAT<4>) to be set. Following this the baud rage gen-
erator is reloaded with the contents of SSPADD<6:0>
and resumes its count. When the baud rate generator
Whenever the firmware decides to take control of the
bus, it should first determine if the bus is busy by check-
ing the S and P bits in the SSPSTAT register. When the
MSSP module detects a START or STOP condition the
SSPIF flag is set. If the bus is busy (S bit is set), then
the CPU can be configured to be interrupted when
when the bus is free by enabling the SSPIF interrupt to
detect the STOP bit.
9.2.15.1 WCOL STATUS FLAG
If the user writes the SSPBUF when a STOP sequence
is in progress, then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
FIGURE 9-21:
STOP CONDITION RECEIVE OR TRANSMIT MODE
Write to SSPCON2
Set PEN
P bit (SSPSTAT<4>) is set
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
TBRG
SCL
NACK
SDA
P
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup STOP condition.
Note: TBRG = one baud rate generator period.
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SCL pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count in the event that the clock
is held low by an external device (Figure 9-22).
9.2.16
CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or repeated START/STOP condition,
de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
FIGURE 9-22:
CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
SSPADD<6:0>, and start count
to measure high time interval
SCL = 1 BRG starts counting
clock high interval.
SCL
SCL line sampled once every machine cycle (Tosc • 4).
Hold off BRG until SCL is sampled high.
SDA
TBRG
TBRG
TBRG
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A bus collision during a START, Repeated START,
STOP or Acknowledge condition results in the following
events:
9.2.17
MULTI -MASTER
COMMUNICATION, BUS
COLLISION, AND BUS
ARBITRATION
• The condition is aborted.
• The SDA and SCL lines are de-asserted.
• The respective control bits in the SSPCON2 regis-
ter are cleared.
Multi-master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, bus arbitration is initiated when one mas-
ter outputs a ’1’ on SDA (by letting SDA float high) and
another master asserts a ’0’. If the expected data on
SDA is a ’1’ and the data sampled on the SDA pin = ’0’,
then a bus collision has taken place. The master that
expected a ‘1’ will set the Bus Collision Interrupt Flag,
BCLIF, and reset the I2C port to its IDLE state.
(Figure 9-23).
When the user services the bus collision interrupt ser-
vice routine, and if the I2C bus is free, the user can
resume communication by asserting a START condi-
tion.
The Master will continue to monitor the SDA and SCL
pins, and if a STOP condition occurs, the SSPIF bit will
be set.
A bus collision during transmit results in the following
events:
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when bus collision occurred.
• The transmission is halted.
• The BF flag is cleared
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is idle and the S and P bits are
cleared.
• The SDA and SCL lines are de-asserted
• The restriction on writing to the SSPBUF during
transmission is lifted.
When the user services the bus collision interrupt ser-
vice routine, and if the I2C bus is free, the user can
resume communication by asserting a START condi-
tion.
FIGURE 9-23:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high
data doesn’t match what is driven
by the master.
SDA line pulled low
by another source
Data changes
while SCL = 0
Bus collision has occurred.
SDA released
by master
SDA
SCL
Set bus collision
interrupt.
BCLIF
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9.2.17.1 BUS COLLISION DURING A START
CONDITION
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data ’1’ during the START condition.
During a START condition, a bus collision occurs if:
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 9-26). If however a ’1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to 0, and during this time, if the SCL pin is
sampled as ’0’, a bus collision does not occur. At the
end of the BRG count the SCL pin is asserted low.
a) SDA or SCL are sampled low at the beginning of
the START condition (Figure 9-24).
b) SCL is sampled low before SDA is asserted low.
(Figure 9-25).
During a START condition both the SDA and the SCL
pins are monitored.
If:
Note: The reason that bus collision is not a factor
during a START condition is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision, because the two masters must be
allowed to arbitrate the first address follow-
ing the START condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, REPEATED
START or STOP conditions.
the SDA pin is already low
or the SCL pin is already low,
then:
the START condition is aborted,
and the BCLIF flag is set,
and the SSP module is reset to its IDLE state
(Figure 9-24).
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
FIGURE 9-24:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1
SDA
SCL
SEN
Set SEN, enable START
condition if SDA = 1, SCL=1
SEN cleared automatically because of bus collision.
SSP module reset into IDLE state.
SDA sampled low before
START condition.
Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1
BCLIF
SSPIF and BCLIF are
cleared in software.
S
SSPIF
SSPIF and BCLIF are
cleared in software.
2002 Microchip Technology Inc.
Advance Information
DS41120B-page 95
PIC16C717/770/771
FIGURE 9-25:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
SCL
SEN
Set SEN, enable START
sequence if SDA = 1, SCL = 1
SCL = 0 before SDA = 0,
Bus collision occurs, Set BCLIF.
SCL = 0 before BRG time out,
Bus collision occurs, Set BCLIF.
BCLIF
Interrupts cleared
in software.
S
’0’
’0’
’0’
’0’
SSPIF
FIGURE 9-26:
BRG RESET DUE TO SDA COLLISION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Set SSPIF
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA
SDA
SCL
SEN
s
SCL pulled low after BRG
Time-out
Set SEN, enable START
sequence if SDA = 1, SCL = 1
’0’
BCLIF
S
SSPIF
Interrupts cleared
in software.
SDA = 0, SCL = 1
Set SSPIF
DS41120B-page 96
AdvanceInformation
2002 Microchip Technology Inc.
PIC16C717/770/771
9.2.17.2 BUS COLLISION DURING A REPEATED
START CONDITION
’0’). If however SDA is sampled high, then the BRG is
reloaded and begins counting. If SDA goes from high to
low before the BRG times out, no bus collision occurs,
because no two masters can assert SDA at exactly the
same time.
During a Repeated START condition, a bus collision
occurs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
If, however, SCL goes from high to low before the BRG
times out and SDA has not already been asserted, then
a bus collision occurs. In this case, another master is
attempting to transmit a data ’1’ during the Repeated
START condition.
b) SCL goes low before SDA is asserted low, indi-
cating that another master is attempting to trans-
mit a data ’1’.
When the master module de-asserts SDA and the pin
is allowed to float high, the BRG is loaded with
SSPADD<6:0>, and counts down to ‘0’. The SCL pin is
then de-asserted, and when sampled high, the SDA pin
is sampled. If SDA is low, a bus collision has occurred
(i.e., another master is attempting to transmit a data
If at the end of the BRG time-out both SCL and SDA are
still high, the SDA pin is driven low, the BRG is
reloaded, and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated START condition is com-
plete (Figure 9-27).
FIGURE 9-27:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL
RSEN
BCLIF
Cleared in software
’0’
’0’
’0’
S
’0’
SSPIF
FIGURE 9-28:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
Set BCLIF. Release SDA and SCL
BCLIF
RSEN
Interrupt cleared
in software
’0’
’0’
’0’
’0’
S
SSPIF
2002 Microchip Technology Inc.
Advance Information
DS41120B-page 97
PIC16C717/770/771
9.2.17.3 BUS COLLISION DURING A STOP
CONDITION
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the baud rate generator is loaded with SSPADD<6:0>
and counts down to ‘0’. After the BRG times out SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data '0' (Figure 9-29). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master attempt-
ing to drive a data '0' (Figure 9-30).
Bus collision occurs during a STOP condition if:
a) After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is de-asserted, SCL is sam-
pled low before SDA goes high.
FIGURE 9-29:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
low after TBRG,
Set BCLIF
TBRG
TBRG
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
’0’
’0’
’0’
’0’
SSPIF
FIGURE 9-30:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high
Set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
’0’
’0’
SSPIF
DS41120B-page 98
AdvanceInformation
2002 Microchip Technology Inc.
PIC16C717/770/771
example, with a supply voltage of VDD = 5V+10% and
VOL max = 0.4V at 3 mA, Rp min = (5.5-0.4)/0.003 =
1.7 kΩ. VDD as a function of Rp is shown in Figure 9-31.
The desired noise margin of 0.1VDD for the low level
limits the maximum value of Rs. Series resistors are
optional and used to improve ESD susceptibility.
9.2.18
CONNECTION CONSIDERATIONS
FOR I2C BUS
For Standard mode I2C bus devices, the values of
resistors Rp and Rs in Figure 9-31 depends on the fol-
lowing parameters
• Supply voltage
The bus capacitance is the total capacitance of wire,
connections, and pins. This capacitance limits the max-
imum value of Rp due to the specified rise time
(Figure 9-31).
• Bus capacitance
• Number of connected devices (input current +
leakage current).
The SMP bit is the slew rate control enabled bit. This bit
is in the SSPSTAT register, and controls the slew rate
of the I/O pins when in I2C mode (master or slave).
The supply voltage limits the minimum value of resistor
Rp due to the specified minimum sink current of 3 mA
at VOL max = 0.4V for the specified output stages. For
FIGURE 9-31:
SAMPLE DEVICE CONFIGURATION FOR I2C BUS
VDD + 10%
DEVICE
Rp
Rp
Rs
Rs
SDA
SCL
Cb=10 pF to 400 pF
2
Note: I C devices with input levels related to VDD must have one common supply line to which the pull-up resistor is also
connected.
TABLE 9-3:
REGISTERS ASSOCIATED WITH I2C OPERATION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR MCLR, WDT
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
8Ch
0Dh
8Dh
13h
14h
91h
94h
93h
PIR1
PIE1
—
ADIF
ADIE
—
—
—
—
—
—
—
—
—
SSPIF
SSPIE
BCLIF
BCLIE
CCP1IF
CCP1IE
—
TMR2IF
TMR2IE
—
TMR1IF -0-- 0000 -0-- 0000
TMR1IE -0-- 0000 -0-- 0000
CCP2IF 0--- 0--0 0--- 0--0
CCP2IE 0--- 0--0 0--- 0--0
xxxx xxxx uuuu uuuu
—
PIR2
LVDIF
LVDIE
PIE2
—
—
—
SSPBUF
SSPCON
SSPCON2
SSPSTAT
SSPADD
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
SSPOV
SSPEN
CKP
SSPM3
RCEN
S
SSPM2
PEN
SSPM1
RSEN
UA
SSPM0
SEN
BF
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
GCEN ACKSTAT ACKDT ACKEN
SMP CKE D/A
P
R/W
Synchronous Serial Port (I2C Mode) Address Register
Legend:
x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the MSSP in I2C mode.
2002 Microchip Technology Inc.
Advance Information
DS41120B-page 99
PIC16C717/770/771
NOTES:
DS41120B-page 100
AdvanceInformation
2002 Microchip Technology Inc.
PIC16C717/770/771
The source for the reference voltages comes from the
bandgap reference circuit. The bandgap circuit is ener-
gized anytime the reference voltage is required by the
other sub-modules, and is powered down when not in
use. The control registers for this module are LVDCON
and REFCON, as shown in Register 10-1 and
Figure 10-2.
10.0 VOLTAGE REFERENCE
MODULE AND LOW-VOLTAGE
DETECT
The Voltage Reference module provides reference
voltages for the Brown-out Reset circuitry, the Low-volt-
age Detect circuitry and the A/D converter.
REGISTER 10-1: LOW-VOLTAGE DETECT CONTROL REGISTER (LVDCON: 9Ch)
U-0
U-0
R-0
R/W-0
R/W-0
LV3
R/W-1
LV2
R/W-0
LV1
R/W-1
LV0
—
—
BGST
LVDEN
bit 7
bit 0
bit 7-6
bit 5
Unimplemented: Read as '0'
BGST: Bandgap Stable Status Flag bit
1= Indicates that the bandgap voltage is stable, and LVD interrupt is reliable
0= Indicates that the bandgap voltage is not stable, and LVD interrupt should not be enabled
bit 4
LVDEN: Low-voltage Detect Power Enable bit
1= Enables LVD, powers up bandgap circuit and reference generator
0= Disables LVD, powers down bandgap circuit if unused by BOR or VRH/VRL
bit 3-0
LV<3:0>: Low Voltage Detection Limit bits(1)
1111= External analog input is used
1110= 4.5V
1101= 4.2V
1100= 4.0V
1011= 3.8V
1010= 3.6V
1001= 3.5V
1000= 3.3V
0111= 3.0V
0110= 2.8V
0101= 2.7V
0100= 2.5V
0011= Reserved. Do not use.
0010= Reserved. Do not use.
0001= Reserved. Do not use.
0000= Reserved. Do not use.
Note: These are the minimum trip points for the LVD. See Table 15-8 for the trip point tol-
erances. Selection of reserved setting may result in an inadvertent interrupt.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
2002 Microchip Technology Inc.
DS41120B-page 101
PIC16C717/770/771
REGISTER 10-2: VOLTAGE REFERENCE CONTROL REGISTER (REFCON: 9BH)
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
VRHEN
VRLEN VRHOEN VRLOEN
—
—
—
—
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3-0
VRHEN: Voltage Reference High Enable bit (VRH = 4.096V nominal)
1= Enabled, powers up reference generator
0= Disabled, powers down reference generator if unused by LVD, BOR, or VRL
VRLEN: Voltage Reference Low Enable bit (VRL = 2.048V nominal)
1= Enabled, powers up reference generator
0= Disabled, powers down reference generator if unused by LVD, BOR, or VRH
VRHOEN: High Voltage Reference Output Enable bit(1)
1= Enabled, VRH analog reference is output on RA3 if enabled (VRHEN = 1)
0= Disabled, analog reference is used internally only(1)
VRLOEN: Low Voltage Reference Output Enable bit
1= Enabled, VRL analog reference is output on RA2 if enabled (VRLEN = 1)
0= Disabled, analog reference is used internally only
Unimplemented: Read as '0’
Note 1: RA2 and RA3 must be configured as analog inputs when the VREF output functions
are enabled (See ANSEL on page 25).
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
DS41120B-page 102
2002 Microchip Technology Inc.
PIC16C717/770/771
The VRL reference is enabled by setting control bit
VRLEN (REFCON<6>). When this bit is set, the gain
amplifier is enabled. After a specified start-up time a
stable reference of 2.048V nominal is generated and
can be used by the A/D converter as a reference input.
10.1 Bandgap Voltage Reference
The bandgap module generates a stable voltage refer-
ence of over a range of temperatures and device sup-
ply voltages. This module is enabled anytime any of the
following are enabled:
Each voltage reference is available for external use via
VRL and VRH pins.
• Brown-out Reset
• Low-voltage Detect
Each reference, if enabled, can be output on an exter-
nal pin by setting the VRHOEN (high reference output
enable) or VRLOEN (low reference output enable) con-
trol bit. If the reference is not enabled, the VRHOEN
and VRLOEN bits will have no effect on the corre-
sponding pin. The device specific pin can then be used
as general purpose I/O.
• Either of the internal analog references (VRH,
VRL)
Whenever the above are all disabled, the bandgap
module is disabled and draws no current.
10.2 Internal VREF for A/D Converter
Note: If VRH or VRL is enabled and the other ref-
erence (VRL or VRH), the BOR, and the
LVD modules are not enabled, the band-
gap will require a start-up time before the
bandgap reference is stable. Before using
the internal VRH or VRL reference, ensure
that the bandgap reference voltage is sta-
ble by monitoring the BGST bit in the LVD-
CON register. The voltage references will
not be reliable until the bandgap is stable
as shown by BGST being set.
The bandgap output voltage is used to generate two
stable references for the A/D converter module. These
references are enabled in software to provide the user
with the means to turn them on and off in order to min-
imize current consumption. Each reference can be indi-
vidually enabled.
The VRH reference is enabled with control bit VRHEN
(REFCON<7>). When this bit is set, the gain amplifier
is enabled. After a specified start-up time a stable ref-
erence of 4.096V nominal is generated and can be
used by the A/D converter as a reference input.
FIGURE 10-1: BLOCK DIAGRAM OF LVD AND VOLTAGE REFERENCE CIRCUIT
LVDCON
REFCON
VDD
LVDEN
VRHEN + VRLEN
generates
LVDIF
RA1/AN1/LVDIN
VRH
BODEN
BGAP
VRL
LVDEN
2002 Microchip Technology Inc.
DS41120B-page 103
PIC16C717/770/771
Once the LV bits have been programmed for the spec-
ified trip voltage, the low-voltage detect circuitry is then
enabled by setting the LVDEN (LVDCON<4>) bit.
10.3 Low Voltage Detect (LVD)
This module is used to generate an interrupt when the
supply voltage falls below a specified “trip” voltage.
This module operates completely under software
control. This allows a user to power the module on
and off to periodically monitor the supply voltage, and
thus minimize total current consumption.
If the bandgap reference voltage is previously unused
by either the brown-out circuitry or the voltage refer-
ence circuitry, then the bandgap circuit requires a time
to start-up and become stable before a low voltage con-
dition can be reliably detected. The low-voltage inter-
rupt flag is prevented from being set until the bandgap
has reached a stable reference voltage.
The LVD module is enabled by setting the LVDEN bit in
the LVDCON register. The “trip point” voltage is the
minimum supply voltage level at which the device can
operate before the LVD module asserts an interrupt.
When the supply voltage is equal to or less than the trip
point, the module will generate an interrupt signal set-
ting interrupt flag bit LVDIF. If interrupt enable bit LVDIE
was set, then an interrupt is generated. The LVD inter-
rupt can wake the device from SLEEP. The "trip point"
voltage is software programmable to any one of 16 val-
ues, five of which are reserved (See Figure 10-1). The
trip point is selected by programming the LV<3:0> bits
(LVDCON<3:0>).
When the bandgap is stable the BGST (LVDCON<5>)
bit is set indicating that the low-voltage interrupt flag bit
is released to be set if VDD is equal to or less than the
LVD trip point.
10.3.1 EXTERNAL ANALOG VOLTAGE INPUT
The LVD module has an additional feature that allows
the user to supply the trip voltage to the module from
an external source. This mode is enabled when
LV<3:0> = 1111. When these bits are set the compar-
ator input is multiplexed from an external input pin
(RA1/AN1/LVDIN).
Note: The LVDIF bit can not be cleared until the
supply voltage rises above the LVD trip
point. If interrupts are enabled, clear the
LVDIE bit once the first LVD interrupt
occurs to prevent reentering the interrupt
service routine immediately after exiting
the ISR.
DS41120B-page 104
2002 Microchip Technology Inc.
PIC16C717/770/771
The A/D module has four registers. These registers
are:
11.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
• A/D Result Register Low ADRESL
• A/D Result Register High ADRESH
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
The analog-to-digital (A/D) converter module has six
inputs for the PIC16C717/770/771.
The PIC16C717 analog-to-digital converter (A/D)
allows conversion of an analog input signal to a corre-
sponding 10-bit digital value, while the A/D converter
in the PIC16C770/771 allows conversion to a corre-
sponding 12-bit digital value. The A/D module has up
to 6 analog inputs, which are multiplexed into one
sample and hold. The output of the sample and hold is
the input into the converter, which generates the result
via successive approximation. The analog reference
voltages are software selectable to either the device’s
analog positive and negative supply voltages (AVDD/
AVSS), the voltage level on the VREF+ and VREF- pins,
or internal voltage references if enabled (VRH, VRL).
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off and
any conversion is aborted.
11.1 Control Registers
The ADCON0 register, shown in Register 11-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 11-2, configures the func-
tions of the port pins, the voltage reference configura-
tion and the result format. The ANSEL register, shown
in Register 3-1, selects between the Analog or Digital
Port Pin modes. The port pins can be configured as
analog inputs or as digital I/O.
The A/D converter can be triggered by setting the GO/
DONE bit, or by the special event Compare mode of
the ECCP module. When conversion is complete, the
GO/DONE bit returns to ’0’, the ADIF bit in the PIR1
register is set, and an A/D interrupt will occur, if
enabled.
The combination of the ADRESH and ADRESL regis-
ters contain the result of the A/D conversion. The reg-
ister pair is referred to as the ADRES register. When
the A/D conversion is complete, the result is loaded
into ADRES, the GO/DONE bit (ADCON0<2>) is
cleared, and the A/D interrupt flag ADIF is set. The
block diagram of the A/D module is shown in
Figure 11-3.
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To oper-
ate in SLEEP, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
2002 Microchip Technology Inc.
DS41120B-page 105
PIC16C717/770/771
REGISTER 11-1: A/D CONTROL REGISTER 0 (ADCON0: 1Fh).
R/W-0
R/W-0
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
CHS3
R/W-0
ADON
ADCS1
ADCS0
GO/DONE
bit 7
bit 0
bit 7-6
ADCS<1:0>: A/D Conversion Clock Select bits
If internal VRL and/or VRH are not used for A/D reference (VCFG<2:0> = 000, 001, 011
or 101):
00= FOSC/2
01= FOSC/8
10= FOSC/32
11= FRC (clock derived from a dedicated RC oscillator)
If internal VRL and/or VRH are used for A/D reference (VCFG<2:0> = 010, 100, 110or 111):
00= FOSC/16
01= FOSC/64
10= FOSC/256
11= FRC/8
bit 5-3,1
CHS:<3:0>: Analog Channel Select bits
0000= channel 00 (AN0)
0001= channel 01 (AN1)
0010= channel 02 (AN2)
0011= channel 03 (AN3)
0100= channel 04 (AN4)
0101= channel 05 (AN5)
0110= reserved, do not select
0111= reserved, do not select
1000= reserved, do not select
1001= reserved, do not select
1010= reserved, do not select
1011= reserved, do not select
1100= reserved, do not select
1101= reserved, do not select
1110= reserved, do not select
1111= reserved, do not select
bit 2
bit 0
GO/DONE: A/D Conversion Status bit
1= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0= A/D conversion completed/not in progress
ADON: A/D On bit
1= A/D converter module is operating
0= A/D converter is shutoff and consumes no operating current
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
’1’ = Bit is set
DS41120B-page 106
2002 Microchip Technology Inc.
PIC16C717/770/771
REGISTER 11-2:
A/D CONTROL REGISTER 1 (ADCON1: 9Fh)
R/W-0
ADFM
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VCFG2
VCFG1
VCFG0 Reserved Reserved Reserved Reserved
bit 0
bit 7
bit 7
ADFM: A/D Result Format Select bit
1= Right justified
0= Left justified
bit 6-4
VCFG<2:0>: Voltage Reference Configuration bits
A/D VREF+
A/D VREF-
(1)
(2)
000
001
010
011
100
101
110
111
AVDD
AVSS
External VREF+
Internal VRH
External VREF+
Internal VRH
External VREF-
Internal VRL
(2)
AVSS
(2)
AVSS
(1)
AVDD
External VREF-
Internal VRL
AVSS
(1)
AVDD
Internal VRL
bit 3-0
Reserved: Do not use.
Note 1: This parameter is VDD for the PIC16C717.
2: This parameter is VSS for the PIC16C717.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
The value that is in the ADRESH and ADRESL regis-
ters are not modified for a Power-on Reset. The
ADRESH and ADRESL registers will contain unknown
data after a Power-on Reset.
The A/D conversion results can be left justified (ADFM
bit cleared), or right justified (ADFM bit set).
Figure 11-1 through Figure 11-2 show the A/D result
data format of the PIC16C717/770/771.
FIGURE 11-1: PIC16C770/771 12-BIT A/D RESULT FORMATS
ADRESH (1Eh)
ADRESL (9Eh)
LSB
Left Justified
MSB
(ADFM = 0)
bit7
bit7
12-bit A/D Result
Unused
Right Justified
(ADFM = 1)
MSB
LSB
bit7
bit7
Unused
12-bit A/D Result
2002 Microchip Technology Inc.
DS41120B-page 107
PIC16C717/770/771
FIGURE 11-2: PIC16C717 10-BIT A/D RESULT FORMAT
(ADFM = 0)
MSB
bit7
LSB
bit7
bit7
10-bit A/D Result
MSB
Unused
(ADFM = 1)
LSB
bit7
Unused
10-bit A/D Result
Unused
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS and ANSEL bits
selected as an input. To determine acquisition time, see
Section 11.6. After this acquisition time has elapsed,
the A/D conversion can be started. The following steps
should be followed for doing an A/D conversion:
11.2.2
CONFIGURING THE REFERENCE
VOLTAGES
The VCFG bits in the ADCON1 register configure the
A/D module reference inputs. The reference high input
can come from an internal reference (VRH) or (VRL),
an external reference (VREF+), or AVDD. The low refer-
ence input can come from an internal reference (VRL),
an external reference (VREF-), or AVSS. If an external
reference is chosen for the reference high or reference
low inputs, the port pin that multiplexes the incoming
external references is configured as an analog input,
regardless of the values contained in the A/D port con-
figuration bits (PCFG<3:0>).
11.2 Configuring the A/D Module
11.2.1
CONFIGURING ANALOG PORT
PINS
The ANSEL and TRIS registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bit
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted. The proper
ANSEL bits must be set (analog input) to disable the
digital input buffer.
The A/D operation is independent of the state of the
TRIS bits and the ANSEL bits.
Note 1: When reading the PORTA register, all pins
configured as analog input channels will
read as ’0’.
2: When reading the PORTB register, all
pins configured as analog pins on
PORTB will be read as ’1’.
3: Analog levels on any pin that is defined as
a digital input, including the ANx pins, may
cause the input buffer to consume current
that is out of the devices specification.
DS41120B-page 108
2002 Microchip Technology Inc.
PIC16C717/770/771
After the A/D module has been configured as desired
and the analog input channels have their correspond-
ing TRIS bits selected for port inputs, the selected
channel must be acquired before conversion is
started. The A/D conversion cycle can be initiated by
setting the GO/DONE bit. The A/D conversion begins
and lasts for 13TAD. The following steps should be fol-
lowed for performing an A/D conversion:
4. Wait the required acquisition time.
5. START conversion
• Set GO/DONE bit (ADCON0)
6. Wait 13TAD until A/D conversion is complete, by
either:
• Polling for the GO/DONE bit to be cleared
OR
1. Configure port pins:
• Waiting for the A/D interrupt
• Configure Analog Input mode (ANSEL)
• Configure pin as input (TRISA or TRISB)
2. Configure the A/D module
7. Read A/D Result registers (ADRESH and
ADRESL), clear ADIF if required.
8. For next conversion, go to step 1, step 2 or step
3 as required.
• Configure A/D Result Format / voltage refer-
ence (ADCON1)
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRESH and
ADRESL registers will be updated with the partially
completed A/D conversion value. That is, the
ADRESH and ADRESL registers will contain the value
of the current incomplete conversion.
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
3. Configure A/D interrupt (if required)
• Clear ADIF bit
Note: Do not set the ADON bit and the GO/
DONE bit in the same instruction. Doing so
will cause the GO/DONE bit to be automat-
ically cleared.
• Set ADIE bit
• Set PEIE bit
• Set GIE bit
FIGURE 11-3:
A/D BLOCK DIAGRAM
CHS<3:0>
VAIN
RB1/AN5/SS
(INPUT VOLTAGE)
RB0/AN4/INT
RA3/AN3/VREF+/VRH
RA2/AN2/VREF-/VRL
RA1/AN1
AVDD
RA0/AN0
VREF+
VRH
VRL
(REFERENCE
VOLTAGE +)
VCFG<2:0>
A/D
CONVERTER
VREF-
VRL
(REFERENCE
VOLTAGE -)
AVSS
VCFG<2:0>
2002 Microchip Technology Inc.
DS41120B-page 109
PIC16C717/770/771
If the VRH or VRL are used for the A/D converter refer-
ence, then the TAD requirement is automatically
increased by a factor of 8.
11.3 Selecting the A/D Conversion
Clock
The A/D conversion cycle requires 13TAD: 1 TAD for set-
tling time, and 12 TAD for conversion. The source of the
A/D conversion clock is software selected. If neither the
internal VRH nor VRL are used for the A/D converter,
the four possible options for TAD are:
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs. Table 11-1 shows the resultant TAD times
derived from the device operating frequencies and the
A/D clock source selected.
• 2 TOSC
The ADIF bit is set on the rising edge of the 14th TAD.
The GO/DONE bit is cleared on the falling edge of the
14th TAD.
• 8 TOSC
• 32 TOSC
• A/D RC oscillator
TABLE 11-1: TAD vs. DEVICE OPERATING FREQUENCIES
A/D Reference
A/D Clock Source (TAD)
Source
Device Frequency
Operation
2 TOSC
ADCS<1:0>
20 MHz
100 ns(2)
400 ns(2)
1.6 µs
5 MHz
4 MHz
500 ns(2)
2.0 µs
1.25 MHz
1.6 µs
6.4 µs
00
01
10
11
00
01
10
11
400 ns(2)
External VREF or
Analog Supply
8 TOSC
1.6 µs
32 TOSC
A/D RC
6.4 µs(3)
8.0 µs(3)
2 - 6 µs(1,4)
4 µs(2)
25.6 µs(3)
2 - 6 µs(1,4)
12.8 µs
2 - 6 µs(1,4)
800 ns(2)
3.2 µs(2)
2 - 6 µs(1,4)
3.2 µs(2)
Internal VRH or 16 TOSC
51.2 µs(3)
204.8 µs(3)
16 - 48 µs(4,5)
VRL
64 TOSC
12.8 µs
16 µs
256 TOSC
A/D RC
12.8 µs
16 - 48 µs(4,5)
51.2 µs(3)
16 - 48 µs(4,5)
64 µs(3)
16 - 48 µs(4,5)
Legend: Shaded cells are outside of recommended range.
Note 1: The A/D RC source has a typical TAD time of 4 µs for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the conversion will be
performed during SLEEP.
5: A/D RC clock source has a typical TAD time of 32 µs for VDD > 3.0V.
DS41120B-page 110
2002 Microchip Technology Inc.
PIC16C717/770/771
11.4 A/D Conversions
Example 11-1 shows an example that performs an A/D
conversion. The port pins are configured as analog
inputs. The analog reference VREF+ is the device AVDD
and the analog reference VREF- is the device AVSS.
The A/D interrupt is enabled and the A/D conversion
clock is TRC. The conversion is performed on the AN0
channel.
EXAMPLE 11-1: PERFORMING AN A/D CONVERSION
BSF
STATUS, RP0
;Select Bank 1
CLRF
MOVLW
MOVWF
MOVWF
BSF
ADCON1
0x01
ANSEL
TRISA
PIE1, ADIE
STATUS, RP0
0xC1
;Configure A/D Voltage Reference
;disable AN0 digital input buffer
;RA0 is input mode
;Enable A/D interrupt
;Select Bank 0
;RC clock, A/D is on,
;Ch 0 is selected
;
;Clear A/D Int Flag
;Enable Peripheral
;Enable All Interrupts
BCF
MOVLW
MOVWF
BCF
BSF
ADCON0
PIR1, ADIF
INTCON, PEIE
INTCON, GIE
BSF
;
; Ensure that the required sampling time for the
; selected input channel has lapsed. Then the
; conversion may be started.
BSF
ADCON0, GO
:
;Start A/D Conversion
;The ADIF bit will be
;set and the GO/DONE bit
;cleared upon completion-
;of the A/D conversion.
:
; Wait for A/D completion and read ADRESH:ADRESL for result.
2002 Microchip Technology Inc.
DS41120B-page 111
PIC16C717/770/771
11.5 A/D Converter Module Operation
Figure 11-4 shows the flowchart of the A/D converter
module.
FIGURE 11-4: FLOW CHART OF A/D OPERATION
ADON = 0
Yes
ADON = 0?
No
Sample
Selected Channel
Yes
GO = 0?
No
Yes
Yes
Start of A/D
Conversion Delayed
1 Instruction Cycle
Finish Conversion
GO = 0
SLEEP
A/D Clock
= RC?
Instruction?
ADIF = 1
No
No
Yes
From SLEEP?
Yes
Instruction?
Wake-up
Abort Conversion
GO = 0
Finish Conversion
GO = 0
SLEEP
ADIF = 0
ADIF = 1
No
No
SLEEP
Power-down A/D
Finish Conversion
GO = 0
Stay in SLEEP
Power-down A/D
ADIF = 1
DS41120B-page 112
2002 Microchip Technology Inc.
PIC16C717/770/771
EXAMPLE 11-2:
A/D SAMPLING TIME
EQUATION
11.6 A/D Sample Requirements
11.6.1
RECOMMENDED SOURCE
IMPEDANCE
VREF
----------------
VHOLD = VREF –
16384
–TC
-------------------------------------------------------------------
The maximum recommended impedance for ana-
log sources is 2.5 kΩ. This value is calculated based
on the maximum leakage current of the input pin. The
leakage current is 100 nA max., and the analog input
voltage cannot be varied by more than 1/4 LSb or
250 µV due to leakage. This places a requirement on
the input impedance of 250 µV/100 nA = 2.5 kΩ.
CHOLD(RIC + RSS + RS)
VREF
----------------
16384
VREF –
= (VREF) 1 – e
–TC
-------------------------------------------------------------------
CHOLD(RIC + RSS + RS)
1
----------------
= (VREF) 1 – e
VREF1 –
16384
Solving for TC:
TC = –CHOLD(1k + RSS + RS)ln
11.6.2
SAMPLING TIME CALCULATION
1
----------------
16384
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 11-5. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
Figure 11-5. The maximum recommended imped-
ance for analog sources is 2.5 kΩ. After the analog
input channel is selected (changed) this sampling must
be done before the conversion can be started.
Figure 11-3 shows the calculation of the minimum time
required to charge CHOLD. This calculation is based on
the following system assumptions:
CHOLD = 25 pF
RS = 2.5 kΩ
1/4 LSb error
VDD = 5V → RSS = 10 kΩ (worst case)
Temp (system Max.) = 50°C
To calculate the minimum sampling time, Equation 11-
2 may be used. This equation assumes that 1/4 LSb
error is used (16384 steps for the A/D). The 1/4 LSb
error is the maximum error allowed for the A/D to meet
its specified resolution.
Note 1:The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
2:The charge holding capacitor (CHOLD) is
not discharged after each conversion.
The CHOLD is assumed to be 25 pF for the 12-bit
A/D.
3:The maximum recommended impedance
for analog sources is 2.5 kΩ. This is
required to meet the pin leakage specifi-
cation.
2002 Microchip Technology Inc.
DS41120B-page 113
PIC16C717/770/771
EXAMPLE 11-3:
CALCULATING THE
MINIMUM
REQUIRED SAMPLE TIME
TACQ =
TACQ =
Amplifier Settling Time
+ Holding Capacitor Charging Time
+Temperature offset
†
5 µs
+ TC
+ [(Temp - 25°C)(0.05 µs/°C)] †
TC = Holding Capacitor Charging Time
TC = (CHOLD) (RIC + RSS + RS) In (1/16384)
TC = -25 pF (1 kΩ +10 kΩ + 2.5 kΩ) In (1/16384)
TC = -25 pF (13.5 kΩ) In (1/16384)
TC = -0.338 (-9.704)µs
TC = 3.3 µs
TACQ =
5 µs
+ 3.3 µs
+ [(50°C - 25°C)(0.05 µs / °C)]
TACQ =
TACQ =
8.3 µs + 1.25 µs
9.55 µs
† The temperature coefficient is only required for
temperatures > 25°C.
FIGURE 11-5: ANALOG INPUT MODEL
VDD
Sampling
Switch
Vt = 0.6V
Port Pin
SS
RIC ~ 1k
RSS
~
RS
CPIN
5 pF
VA
ILEAKAGE
± 100 nA
CHOLD = 25 pF
VSS
VT = 0.6V
Legend CPIN
VT
= input capacitance
= threshold voltage
6V
5V
ILEAKAGE = leakage current at the pin due to
various junctions
VDD 4V
3V
2V
RIC
SS
= interconnect resistance
= sampling switch
CHOLD
= sample/hold capacitance
5 6 7 8 9 10 11
Sampling Switch (RSS)
( kΩ )
DS41120B-page 114
2002 Microchip Technology Inc.
PIC16C717/770/771
11.7 Use of the ECCP Trigger
11.9 Faster Conversion - Lower
Resolution Trade-off
An A/D conversion can be started by the “special
event trigger” of the CCP module. This requires that
the CCP1M<3:0> bits be programmed as 1011band
that the A/D module is enabled (ADON is set). When
the trigger occurs, the GO/DONE bit will be set on Q2
to start the A/D conversion and the Timer1 counter will
be reset to zero. Timer1 is RESET to automatically
repeat the A/D conversion cycle, with minimal soft-
ware overhead (moving the ADRESH and ADRESL to
the desired location). The appropriate analog input
channel must be selected before the “special event
trigger” sets the GO/DONE bit (starts a conversion
cycle).
Not all applications require a result with 12 bits of reso-
lution, but may instead require a faster conversion
time. The A/D module allows users to make the trade-
off of conversion speed to resolution. Regardless of
the resolution required, the acquisition time is the
same. To speed up the conversion, the A/D module
may be halted by clearing the GO/DONE bit after the
desired number of bits in the result have been con-
verted. Once the GO/DONE bit has been cleared, all
of the remaining A/D result bits are ‘0’. The equation
to determine the time before the GO/DONE bit can be
switched is as follows:
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still RESET the Timer1 counter.
Conversion time = (N+1)TAD
Where: N = number of bits of resolution required,
and 1TAD is the amplifier settling time.
Since TAD is based from the device oscillator, the user
must use some method (a timer, software loop, etc.) to
determine when the A/D GO/DONE bit may be
cleared. Table 11-4 shows a comparison of time
required for a conversion with 4 bits of resolution, ver-
sus the normal 12-bit resolution conversion. The
example is for devices operating at 20 MHz. The A/D
clock is programmed for 32 TOSC.
11.8 Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off, and
any conversion is aborted. The value that is in the
ADRESH and ADRESL registers are not modified.
The ADRESH and ADRESL registers will contain
unknown data after a Power-on Reset.
EXAMPLE 11-4:
4-BIT vs. 12-BIT
CONVERSION TIME
Example
4-Bit Example:
Conversion Time = (N + 1) TAD
= (4 + 1) TAD
= (5)(1.6 µS)
= 8 µS
12-Bit Example:
Conversion Time = (N + 1) TAD
= (12 + 1) TAD
= (13)(1.6 µS)
= 20.8 µS
2002 Microchip Technology Inc.
DS41120B-page 115
PIC16C717/770/771
Turning off the A/D places the A/D module in its lowest
current consumption state.
11.10 A/D Operation During SLEEP
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be configured for RC
(ADCS<1:0> = 11b). With the RC clock source
selected, when the GO/DONE bit is set the A/D module
waits one instruction cycle before starting the conver-
sion cycle. This allows the SLEEPinstruction to be exe-
cuted, which eliminates all digital switching noise
during the sample and conversion. When the conver-
sion cycle is completed the GO/DONE bit is cleared,
and the result loaded into the ADRESH and ADRESL
registers. If the A/D interrupt is enabled, the device will
wake-up from SLEEP. If the A/D interrupt is not
enabled, the A/D module will then be turned off,
although the ADON bit will remain set.
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be configured to
RC (ADCS<1:0> = 11).
11.11 Connection Considerations
Since the analog inputs employ ESD protection, they
have diodes to VDD and VSS. This requires that the
analog input must be between VDD and VSS. If the input
voltage exceeds this range by greater than 0.3V (either
direction), one of the diodes becomes forward biased
and it may damage the device if the input current spec-
ification is exceeded.
An external RC filter is sometimes added for anti-alias-
ing of the input signal. The R component should be
selected to ensure that the total source impedance is
kept under the 2.5 kΩ recommended specification. It is
recommended that any external components con-
nected to an analog input pin (capacitor, zener diode,
etc.) have very little leakage current.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction causes the present conver-
sion to be aborted and the A/D module is turned off,
though the ADON bit will remain set.
TABLE 11-2: SUMMARY OF A/D REGISTERS
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
-0-- 0000 -0-- 0000
-0-- 0000 -0-- 0000
PIR1
PIE1
ADIF
ADIE
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF TMR1IF
TMR2IE TMR1IE
—
—
—
—
—
—
0Ch
8Ch
1Eh
9Eh
9Bh
1Fh
9Fh
05h
06h
85h
86h
9Dh
17h
ADRESH
ADRESL
REFCON
ADCON0
ADCON1
PORTA
A/D High Byte Result Register
A/D Low Byte Result Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 ---- 0000 ----
0000 0000 0000 0000
0000 ---- 0000 ----
000x 0000 000u 0000
xxxx xx11 uuuu uu11
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
0000 0000 0000 0000
VRHEN VRLEN VRHOEN VRLOEN
—
—
—
CHS3
—
—
ADON
—
ADCS1 ADCS0
ADFM VCFG2
CHS2
CHS1
CHS0 GO/DONE
VCFG1
VCFG0
—
—
PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read
PORTA Data Direction Register
PORTB
TRISA
TRISB
PORTB Data Direction Register
ANSEL
—
—
—
—
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
CCP1CON
—
—
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used for A/D conversion.
DS41120B-page 116
2002 Microchip Technology Inc.
PIC16C717/770/771
12.1 Configuration Bits
12.0 SPECIAL FEATURES OF THE
CPU
These devices have a host of features intended to max-
imize system reliability, minimize cost through elimina-
tion of external components, provide power saving
operating modes and offer code protection. These are:
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space.
• Oscillator Selection
• RESET
Some of the core features provided may not be neces-
sary to each application that a device may be used for.
The configuration word bits allow these features to be
configured/enabled/disabled as necessary. These fea-
tures include code protection, Brown-out Reset and its
trip point, the Power-up Timer, the watchdog timer and
the devices Oscillator mode. As can be seen in
Register 12-1, some additional configuration word bits
have been provided for Brown-out Reset trip point
selection.
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Low-voltage detection
• SLEEP
• Code protection
• ID locations
• In-circuit serial programming (ICSP)
These devices have a Watchdog Timer, which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in RESET until the crystal oscillator is stable.
The other is the Power-up Timer (PWRT), which pro-
vides a fixed delay of 72 ms (nominal) on power-up
type RESETS only (POR, BOR), designed to keep the
part in RESET while the power supply stabilizes. With
these two timers on-chip, most applications need no
external RESET circuitry.
SLEEP mode is designed to offer a very low current
Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
Wake-up, or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The INTRC and ER oscillator options
save system cost while the LP crystal option saves
power. A set of configuration bits are used to select var-
ious options.
Additional information on special features is available
in the PICmicro™ Mid-Range MCU Family Reference
Manual, (DS33023).
2002 Microchip Technology Inc.
DS41120B-page 117
PIC16C717/770/771
REGISTER 12-1: CONFIGURATION WORD FOR 16C717/770/771 DEVICE
CP
CP
BORV1 BORV0
CP
CP
—
BODEN MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0
bit0
bit13
bit 13-12,
9-8
CP: Program Memory Code Protection
1= Code protection off
(2)
0= All program memory is protected
bit 11-10:
BORV<1:0>: Brown-out Reset Voltage bits
00= VBOR set to 4.5V
01= VBOR set to 4.2V
10= VBOR set to 2.7V
11= VBOR set to 2.5V
bit 7:
bit 6:
Unimplemented: Read as '1'
(1)
BODEN: Brown-out Detect Reset Enable bit
1= Brown-out Detect Reset enabled
0= Brown-out Detect Reset disabled
bit 5:
MCLRE: RA5/MCLR pin function select
1= RA5/MCLR pin function is MCLR
0= RA5/MCLR pin function is digital input, MCLR internally tied to VDD
(1)
bit 4:
PWRTE: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
bit 3:
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
bit 2-0:
FOSC<2:0>: Oscillator Selection bits
000= LP oscillator: Crystal/Resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
001= XT oscillator: Crystal/Resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
010= HS oscillator: Crystal/Resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
011= EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN function on RA7/OSC1/CLKIN
100= INTRC oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
101= INTRC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
110= ER oscillator: I/O function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN
111= ER oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN
Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT), regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP bits must be given the same value to enable code protection.
Legend
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS41120B-page 118
2002 Microchip Technology Inc.
PIC16C717/770/771
TABLE 12-1: CERAMIC RESONATORS
Ranges Tested:
12.2 Oscillator Configurations
12.2.1 OSCILLATOR TYPES
Mode
XT
Freq
OSC1
OSC2
The PIC16C717/770/771 can be operated in eight dif-
ferent Oscillator modes. The user can program three
configuration bits (FOSC<2:0>) to select one of these
eight modes:
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
• LP
• XT
• HS
• ER
Low Power Crystal
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
Crystal/Resonator
These values are for design guidance only. See
notes at bottom of page.
High Speed Crystal/Resonator
External Resistor (with and without
CLKOUT)
All resonators used did not have built-in capacitors.
• INTRC Internal 4 MHz (with and without
TABLE 12-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
CLKOUT)
• EC
External Clock
Crystal
Freq
Cap. Range
C1
Cap. Range
C2
Osc Type
12.2.2
LP, XT AND HS MODES
In LP, XT or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 12-1). The
PIC16C717/770/771 oscillator design requires the use
of a parallel cut crystal. Use of a series cut crystal may
give a frequency out of the crystal manufacturers spec-
ifications.
LP
32 kHz
200 kHz
200 kHz
1 MHz
33 pF
15 pF
33 pF
15 pF
XT
HS
47-68 pF
15 pF
47-68 pF
15 pF
4 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
15-33 pF
15-33 pF
FIGURE 12-1:
CRYSTAL/CERAMIC
RESONATOROPERATION
(HS, XT OR LP
20 MHz
These values are for design guidance only. See
notes at bottom of page.
OSC CONFIGURATION)
C1(1)
OSC1
Note 1: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropri-
ate values of external components.
2: Higher capacitance increases the stability of
oscillator but also increases the start-up
time.
To
internal
logic
XTAL
RF(3)
OSC2
SLEEP
PIC16C717/770/771
RS(2)
C2(1)
12.2.3
EC MODE
Note1: See Table 12-1 and Table 12-2 for recom-
mended values of C1 and C2.
In applications where the clock source is external, the
PIC16C717/770/771 should be programmed to select
the EC (External Clock) mode. In this mode, the RA6/
OSC2/CLKOUT pin is available as an I/O pin. See
Figure 12-2 for illustration.
2: A series resistor (RS) may be required for
AT strip cut crystals.
3: RF varies with the Crystal mode chosen.
FIGURE 12-2:
EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
OSC1
Clock from
ext. system
PIC16C717/770/771
RA6
I/O
2002 Microchip Technology Inc.
DS41120B-page 119
PIC16C717/770/771
12.2.6 CLKOUT
12.2.4
ER MODE
For timing insensitive applications, the ER (External
Resistor) Clock mode offers additional cost savings.
Only one external component, a resistor connected to
the OSC1 pin and VSS, is needed to set the operating
frequency of the internal oscillator. The resistor draws
a DC bias current which controls the oscillation fre-
quency. In addition to the resistance value, the oscilla-
tor frequency will vary from unit to unit, and as a
function of supply voltage and temperature. Since the
controlling parameter is a DC current and not a capac-
itance, the particular package type and lead frame will
not have a significant effect on the resultant frequency.
In the INTRC and ER modes, the PIC16C717/770/771
can be configured to provide a clock out signal by pro-
gramming the configuration word. The oscillator fre-
quency, divided by 4, can be used for test purposes or
to synchronize other logic.
In the INTRC and ER modes, if the CLKOUT output is
enabled, CLKOUT is held low during RESET.
12.2.7
DUAL SPEED OPERATION FOR ER
AND INTRC MODES
A software programmable dual speed oscillator is avail-
able in either ER or INTRC Oscillator modes. This fea-
ture allows the applications to dynamically toggle the
oscillator speed between normal and slow frequencies.
The nominal slow frequency is 37 kHz. In ER mode, the
slow speed operation is fixed and does not vary with
resistor size. Applications that require low current
power savings, but cannot tolerate putting the part into
SLEEP, may use this mode.
Figure 12-3 shows how the controlling resistor is con-
nected to the PIC16C717/770/771. For REXT values
below 38 kΩ, the oscillator operation may become
unstable, or stop completely. For very high REXT values
(e.g. 1M), the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend keeping
REXT between 38 kΩ and 1 MΩ.
The OSCF bit in the PCON register is used to control
Dual Speed mode. See the PCON Register,
Register 2-8, for details.
FIGURE 12-3:
EXTERNAL RESISTOR
PIC16C717/770/771
When changing the INTRC or ER internal oscillator
speed, there is a period of time when the processor is
inactive. When the speed changes from fast to slow,
the processor inactive period is in the range of 100 µS
to 300 µS. For speed change from slow to fast, the pro-
cessor is in active for 1.25 µS to 3.25 µS.
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
REXT
The Electrical Specification section shows the relation-
ship between the REXT resistance value and the oper-
ating frequency as well as frequency variations due to
operating temperature for given REXT and VDD values.
The ER Oscillator mode has two options that control
the OSC2 pin. The first allows it to be used as a general
purpose I/O port. The other configures the pin as CLK-
OUT. The ER oscillator does not run during RESET.
12.2.5
INTRC MODE
The internal RC oscillator provides a fixed 4 MHz (nom-
inal) system clock at VDD = 5V and 25°C, see “Electri-
cal Specifications” section for information on variation
over voltage and temperature. The INTRC oscillator
does not run during RESET.
DS41120B-page 120
2002 Microchip Technology Inc.
PIC16C717/770/771
Some registers are not affected in any RESET condi-
tion. Their status is unknown on a Power-up Reset and
unchanged in any other RESET. Most other registers
are placed into an initialized state upon RESET, how-
ever they are not affected by a WDT Reset during
SLEEP, because this is considered a WDT Wake-up,
which is viewed as the resumption of normal operation.
12.3 RESET
The PIC16C717/770/771 devices have several differ-
ent RESETS. These RESETS are grouped into two
classifications; power-up and non-power-up. The
power-up type RESETS are the Power-on and Brown-
out Resets which assume the device VDD was below its
normal operating range for the device’s configuration.
The non power-up type RESETS assume normal oper-
ating limits were maintained before/during and after the
RESET.
Several status bits have been provided to indicate
which RESET occurred (see Table 12-4). See
Table 12-6 for a full description of RESET states of all
registers.
• Power-on Reset (POR)
A simplified block diagram of the On-Chip Reset circuit
is shown in Figure 12-4.
• Programmable Brown-out Reset (PBOR)
• MCLR Reset during normal operation
• MCLR Reset during SLEEP
These devices have a MCLR noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
• WDT Reset (during normal operation)
It should be noted that a WDT Reset does not drive
MCLR pin low.
FIGURE 12-4:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
RESET
MCLR
SLEEP
Time-out
WDT
Module
VDD rise
detect
Power-on Reset
VDD
Programmable
Brown-out
S
BODEN
OST/PWRT
OST
Chip_Reset
Q
R
10-bit Ripple counter
OSC1
PWRT
10-bit Ripple counter
Dedicated
Oscillator
Enable PWRT
Enable OST
2002 Microchip Technology Inc.
DS41120B-page 121
PIC16C717/770/771
12.4 Power-On Reset (POR)
12.5 Power-up Timer (PWRT)
A Power-on Reset pulse is generated on-chip when a
VDD rise is detected (in the range of 1.5V - 2.1V).
Enable the internal MCLR feature to eliminate external
RC components usually needed to create a Power-on
Reset. A maximum rise time for VDD is specified. See
Electrical Specifications for details. For a long rise time,
enable external MCLR function and use circuit as
shown in Figure 12-5.
The Power-up Timer provides a fixed TPWRT time-out
on power-up type RESETS only. For a POR, the PWRT
is invoked when the POR pulse is generated. For a
BOR, the PWRT is invoked when the device exits the
RESET condition (VDD rises above BOR trip point).
The Power-up Timer operates on an internal RC oscil-
lator. The chip is kept in RESET as long as the PWRT
is active. The PWRT’s time delay is designed to allow
VDD to rise to an acceptable level. A configuration bit is
provided to enable/disable the PWRT for the POR only.
For a BOR the PWRT is always available regardless of
the configuration bit setting.
Two delay timers, (PWRT on OST), have been pro-
vided which hold the device in RESET after a POR
(dependent upon device configuration) so that all oper-
ational parameters have been met prior to releasing the
device to resume/begin normal operation.
The power-up time delay will vary from chip-to-chip due
to VDD, temperature and process variation. See DC
parameters for details.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the device
must be held in RESET until the operating conditions
are met. Brown-out Reset may be used to meet the
start-up conditions, or if necessary an external POR cir-
cuit may be implemented to delay end of RESET for as
long as needed.
12.6 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal oscil-
lator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on a power-up type RESET or a wake-
up from SLEEP.
FIGURE 12-5:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD RAMP)
12.7 Programmable Brown-Out Reset
(PBOR)
VDD
VDD
The Programmable Brown-out Reset module is used to
generate a RESET when the supply voltage falls below
a specified trip voltage. The trip voltage is configurable
to any one of four voltages provided by the BORV<1:0>
configuration word bits.
D
R
R1
MCLR
PIC16C717/770/771
C
Configuration bit, BODEN, can disable (if clear/pro-
grammed) or enable (if set) the Brown-out Reset cir-
cuitry. If VDD falls below the specified trip point for
longer than TBOR, (parameter #35), the brown-out situ-
ation will RESET the chip. A RESET may not occur if
VDD falls below the trip point for less than TBOR. The
chip will remain in Brown-out Reset until VDD rises
above VBOR. The Power-up Timer will be invoked at
that point and will keep the chip in RESET an additional
TPWRT. If VDD drops below VBOR while the Power-up
Timer is running, the chip will go back into a Brown-out
Reset and the Power-up Timer will be re-initialized.
Once VDD rises above VBOR, the Power-up Timer will
again begin a TPWRT time delay. Even though the
PWRT is always enabled when brown-out is enabled,
the PWRT configuration word bit should be cleared
(enabled) when brown-out is enabled.
Note 1: External Power-on Reset circuit is
required only if VDD power-up slope is too
slow. The diode D helps discharge the
capacitor quickly when VDD powers down.
2: R < 40 kΩ is recommended to make sure
that voltage drop across R does not violate
the device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin break-
down due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
4: External MCLR must be enabled
(MCLRE = 1).
DS41120B-page 122
2002 Microchip Technology Inc.
PIC16C717/770/771
Table 12-5 shows the RESET conditions for some spe-
cial function registers, while Table 12-6 shows the
RESET conditions for all the registers.
12.8 Time-out Sequence
On power-up, the time-out sequence is as follows:
First PWRT time-out is invoked by the POR pulse.
When the PWRT delay expires, the Oscillator Start-up
Timer is activated. The total time-out will vary based on
oscillator configuration and the status of the PWRT.
For example, in RC mode with the PWRT disabled,
there will be no time-out at all. Figure 12-6, Figure 12-
7, Figure 12-8 and Figure 12-9 depict time-out
sequences on power-up.
12.9 Power Control/STATUS Register
(PCON)
The Power Control/STATUS Register, PCON, has two
status bits that provide indication of which power-up
type RESET occurred.
Bit0 is Brown-out Reset Status bit, BOR. The BOR bit
is unknown upon a POR. BOR must be set by the user
and checked on subsequent RESETS to see if bit BOR
cleared, indicating a BOR occurred.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 12-8). This is useful for testing purposes or to
synchronize more than one PICmicro® microcontroller
operating in parallel.
Bit1 is POR (Power-on Reset Status bit). It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
TABLE 12-3: TIME-OUT IN VARIOUS SITUATIONS
Power-up
Wake-up from
Oscillator Configuration
Brown-out
SLEEP
PWRTE = 0
TPWRT + 1024TOSC
TPWRT
PWRTE = 1
XT, HS, LP
1024TOSC
TPWRT + 1024TOSC
TPWRT
1024TOSC
EC, ER, INTRC
—
—
TABLE 12-4: STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
0
0
1
1
1
1
1
x
x
x
0
1
1
1
1
1
0
x
1
0
0
u
1
1
x
0
1
1
0
u
0
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 12-5: RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Condition
Power-on Reset
000h
000h
0001 1xxx
000u uuuu
0001 0uuu
0000 1uuu
uuu0 0uuu
0001 1uuu
uuu1 0uuu
uuu1 0uuu
---- 1-0x
---- 1-uu
---- 1-uu
---- 1-uu
---- u-uu
---- 1-u0
---- u-uu
---- u-uu
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset
000h
000h
WDT Wake-up
PC + 1
000h
Brown-out Reset
Interrupt wake-up from SLEEP, GIE = 0
Interrupt wake-up from SLEEP, GIE = 1
PC + 1
0004h
Legend: u= unchanged, x= unknown, -= unimplemented bit read as '0'.
2002 Microchip Technology Inc.
DS41120B-page 123
PIC16C717/770/771
TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Power-on Reset or
Brown-out Reset
MCLR Reset or
WDT Reset
Wake-up via WDT or
Interrupt
W
xxxx xxxx
0000 0000
xxxx xxxx
0000h
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000h
uuuu uuuu
uuuu uuuu
uuuu uuuu
INDF
TMR0
PCL
PC + 1(1)
000q quuu(2)
uuuu uuuu
uuuu 0000
uuuu uu11
---0 0000
0000 000u
-0-- 0000
0--- 0---
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0000
-000 0000
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
0000 0000
1111 1111
1111 1111
1111 1111
-0-- 0000
0--- 0---
---- 1-uu
1111 1111
0000 0000
0000 0000
1111 1111
1111 0000
uuuq quuu(2)
uuuu uuuu
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuqq
-0-- uuuu
q--- q---
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u-- uuuu
u--- u---
---- u-uu
1111 1111
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
STATUS
0001 1xxx
FSR
xxxx xxxx
xxxx 0000
xxxx xx11
---0 0000
0000 000x
-0-- 0000
0--- 0---
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
-000 0000
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
0000 0000
1111 1111
1111 1111
1111 1111
-0-- 0000
0--- 0---
---- 1-qq
1111 1111
0000 0000
0000 0000
1111 1111
1111 0000
PORTA
PORTB
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
ADRESH
ADCON0
OPTION_REG
TRISA
TRISB
PIE1
PIE2
PCON
PR2
SSPADD
SSPSTAT
WPUB
IOCB
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as ’0’, q= value depends on condition
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
2: See Table 12-5 for RESET value for specific condition.
DS41120B-page 124
2002 Microchip Technology Inc.
PIC16C717/770/771
TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Power-on Reset or
Brown-out Reset
MCLR Reset or
WDT Reset
Wake-up via WDT or
Interrupt
P1DEL
0000 0000
0000 ----
--00 0101
--11 1111
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--xx xxxx
---- xxxx
1--- ---0
0000 0000
0000 ----
--00 0101
--11 1111
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
--uu uuuu
---- uuuu
1--- ---0
uuuu uuuu
uuuu ----
--uu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
---- uuuu
1--- ---0
REFCON
LVDCON
ANSEL
ADRESL
ADCON1
PMDATL
PMADRL
PMDATH
PMADRH
PMCON1
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as ’0’, q= value depends on condition
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
2: See Table 12-5 for RESET value for specific condition.
FIGURE 12-6:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
2002 Microchip Technology Inc.
DS41120B-page 125
PIC16C717/770/771
FIGURE 12-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 12-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 12-9: SLOW VDD RISE TIME (MCLR TIED TO VDD)
5V
0V
VDD
MCLR
INTERNAL POR
TPWRT
(1)
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
Note 1: Time dependent on oscillator circuit
DS41120B-page 126
2002 Microchip Technology Inc.
PIC16C717/770/771
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
12.10 Interrupts
The devices have up to 11 sources of interrupt. The
interrupt control register (INTCON) records individual
interrupt requests in flag bits. It also has individual and
global interrupt enable bits.
The peripheral interrupt flags are contained in the spe-
cial function registers PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
Note: Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
A Global Interrupt Enable bit, GIE (INTCON<7>),
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set regardless of the status of their
corresponding mask bit or the GIE bit
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
FIGURE 12-10:
INTERRUPT LOGIC
LVDIF
LVDIE
Wake-up (If in SLEEP mode)
ADIF
ADIE
T0IF
T0IE
INTF
INTE
Interrupt to CPU
RBIF
RBIE
SSPIF
SSPIE
CCP1IF
CCP1IE
PEIE
GIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
BCLIF
BCLIE
2002 Microchip Technology Inc.
DS41120B-page 127
PIC16C717/770/771
12.10.1 INT INTERRUPT
12.11 Context Saving During Interrupts
External interrupt on RB0/INT pin is edge triggered:
either rising if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 12.13 for details on SLEEP mode.
During an interrupt, only the PC is saved on the stack.
At the very least, W and STATUS should be saved to
preserve the context for the interrupted program. All
registers that may be corrupted by the ISR, such as
PCLATH or FSR, should be saved.
Example 12-1 stores and restores the STATUS, W and
PCLATH registers. The register, W_TEMP, is defined in
Common RAM, the last 16 bytes of each bank that may
be accessed from any bank. The STATUS_TEMP and
PCLATH_TEMP are defined in bank 0.
The example:
a) Stores the W register.
b) Stores the STATUS register in bank 0.
c) Stores the PCLATH register in bank 0.
d) Executes the ISR code.
12.10.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 2.2.2.3)
e) Restores the PCLATH register.
f) Restores the STATUS register
g) Restores W.
12.10.3 PORTB INTCON CHANGE
Note
that
W_TEMP,
STATUS_TEMP
and
PCLATH_TEMP are defined in the common RAM area
(70h - 7Fh) to avoid register bank switching during con-
text save and restore.
An input change on PORTB<7:0> sets flag bit RBIF
(INTCON<0>). The PORTB pin(s) which can individu-
ally generate interrupt is selectable in the IOCB regis-
ter. The interrupt can be enabled/disabled by setting/
clearing
enable
bit
RBIE
(INTCON<4>).
(Section 2.2.2.3)
EXAMPLE 12-1:
Saving STATUS, W, and PCLATH Registers in RAM
#define
#define
#define
org
W_TEMP
STATUS_TEMP
PCLATH_TEMP
0x04
0x70
0x71
0x72
; start at Interrupt Vector
; Save W register
MOVWF
W_TEMP
MOVF
MOVWF
MOVF
MOVWF
:
STATUS,w
STATUS_TEMP
PCLATH,w
PCLATH_TEMP
; save STATUS
; save PCLATH
(Interrupt Service Routine)
:
MOVF
MOVWF
MOVF
MOVWF
SWAPF
SWAPF
RETFIE
PCLATH_TEMP,w
PCLATH
STATUS_TEMP,w
STATUS
W_TEMP,f
W_TEMP,w
;
; swapf loads W without affecting STATUS flags
DS41120B-page 128
2002 Microchip Technology Inc.
PIC16C717/770/771
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS regis-
ter will be cleared upon a Watchdog Timer time-out.
12.12 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscil-
lator, which does not require any external components.
This oscillator is independent from the processor clock.
If enabled, the WDT will run even if the main clock of
the device has been stopped, for example, by execu-
tion of a SLEEPinstruction.
The WDT can be permanently disabled by program-
ming the configuration bit WDTE to ’0’ (Section 12.1).
WDT time-out period values may be found in Table 15-
4. Values for the WDT prescaler may be assigned using
the OPTION_REG register.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
Note: The SLEEPinstruction clears the WDT and
the postscaler, if assigned to the WDT,
restarting the WDT period.
FIGURE 12-11:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 5-2)
0
Postscaler
M
U
X
1
WDT Timer
8
(1)
8 - to - 1 MUX
PS<2:0>
PSA
WDT
Enable Bit
(2)
To TMR0 (Figure 5-2)
0
1
(1)
MUX
PSA
WDT
Time-out
Note 1: PSA and PS<2:0> are bits in the OPTION_REG register.
2: WDTE bit in the configuration word.
TABLE 12-7: SUMMARY OF WATCHDOG TIMER REGISTERS
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Config. bits(1)
2007h
—
BODEN
INTEDG
MCLRE PWRTE
T0CS T0SE
WDTE FOSC2 FOSC1
PSA PS2 PS1
FOSC0
PS0
81h,181h OPTION_REG RBPU
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for the full description of the configuration word bits.
2002 Microchip Technology Inc.
DS41120B-page 129
PIC16C717/770/771
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOPafter the SLEEPinstruction.
12.13 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
12.13.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
For lowest current consumption in this mode, place all
I/O pins at either VDD, or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D, disable external clocks. Pull all I/O pins, that
are hi-impedance inputs, high or low externally to avoid
switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
• If the interrupt occurs before the execution of a
SLEEPinstruction, the SLEEPinstruction will com-
plete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
• If the interrupt occurs during or after the execu-
tion of a SLEEPinstruction, the device will imme-
diately wake-up from SLEEP. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
12.13.1 WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1. External RESET input on MCLR pin.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change, or some
Peripheral Interrupts.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device RESET. The PD bit, which is set on
power-up, is cleared when SLEEPis invoked. The TO
bit is cleared if a WDT time-out occurred (and caused
wake-up).
If a peripheral can wake the device from SLEEP, then
to ensure that the WDT is cleared, a CLRWDTinstruc-
tion should be executed before a SLEEPinstruction.
The following peripheral interrupts can wake the device
from SLEEP:
1. TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
2. CCP Capture mode interrupt.
3. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
4. SSP (START/STOP) bit detect interrupt.
5. SSP transmit or receive in Slave mode
(SPI/I2C).
6. A/D conversion (when A/D clock source is RC).
7. Low Voltage detect.
Other peripherals cannot generate interrupts since dur-
ing SLEEP, no on-chip clocks are present.
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
DS41120B-page 130
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 12-12:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(1)
TOST
CLKOUT(3)
INT pin
INTF flag
(INTCON<1>)
Interrupt Latency(2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
Instruction
fetched
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
Instruction
executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(PC - 1)
Inst(0004h)
Note 1: TOST = 1024TOSC (drawing not to scale) This delay applies to LP, XT and HS modes only.
2: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.
3: CLKOUT is not available in these osc modes, but shown here for timing reference.
12.14 Program Verification/Code
Protection
12.16 In-Circuit Serial Programming
(ICSP™)
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
PIC16CXXX microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
Note: Microchip does not recommend code pro-
tecting windowed devices. Code protected
devices are not reprogrammable.
12.15 ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are read-
able and writable during program/verify. It is recom-
mended that only the 4 Least Significant bits of the ID
location are used.
For complete details of serial programming, please
refer to the In-Circuit Serial Programming (ICSP™)
Guide, (DS30277).
2002 Microchip Technology Inc.
DS41120B-page 131
PIC16C717/770/771
NOTES:
DS41120B-page 132
2002 Microchip Technology Inc.
PIC16C717/770/771
Table 13-2 lists the instructions recognized by the
MPASM™ assembler.
13.0 INSTRUCTION SET SUMMARY
Each PIC16CXXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 13-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 13-1
shows the opcode field descriptions.
Figure 13-1 shows the general formats that the instruc-
tions can have.
Note: To maintain upward compatibility with
future PIC16CXXX products, do not use
the OPTIONand TRISinstructions.
All examples use the following format to represent a
hexadecimal number:
For byte-oriented instructions, ’f’ represents a file reg-
ister designator and ’d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
0xhh
where h signifies a hexadecimal digit.
The destination designator specifies where the result of
the operation is to be placed. If ’d’ is zero, the result is
placed in the W register. If ’d’ is one, the result is placed
in the file register specified in the instruction.
FIGURE 13-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8
7
6
0
For bit-oriented instructions, ’b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ’f’ represents the number of the
file in which the bit is located.
OPCODE
d
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
For literal and control operations, ’k’ represents an
eight or eleven bit constant or literal value.
Bit-oriented file register operations
13 10 9
b (BIT #)
7
6
0
TABLE 13-1: OPCODE FIELD
DESCRIPTIONS
OPCODE
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Field
Description
f
W
b
Register file address (0x00 to 0x7F)
Working register (accumulator)
Literal and control operations
Bit address within an 8-bit file register
Literal field, constant data or label
General
k
13
8
7
0
0
x
Don’t care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
OPCODE
k (literal)
k = 8-bit immediate value
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
PC
TO
PD
Program Counter
Time-out bit
k (literal)
Power-down bit
The instruction set is highly orthogonal and is grouped
into three basic categories:
A description of each instruction is available in the
PICmicro™ Mid-Range MCU Family Reference Man-
ual, (DS33023).
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.
2002 Microchip Technology Inc.
DS41120B-page 133
PIC16C717/770/771
TABLE 13-2: PIC16CXXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
Status
Affected
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d Add W and f
f, d AND W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111 dfff ffff C,DC,Z
1,2
1,2
2
0101 dfff ffff
0001 lfff ffff
0001 0000 0011
1001 dfff ffff
0011 dfff ffff
1011 dfff ffff
1010 dfff ffff
1111 dfff ffff
0100 dfff ffff
1000 dfff ffff
0000 lfff ffff
0000 0xx0 0000
1101 dfff ffff
1100 dfff ffff
Z
Z
Z
Z
Z
f
-
Clear f
Clear W
f, d Complement f
f, d Decrement f
f, d Decrement f, Skip if 0
f, d Increment f
f, d Increment f, Skip if 0
f, d Inclusive OR W with f
f, d Move f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
DECFSZ
INCF
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
1,2
f
-
Move W to f
No Operation
f, d Rotate Left f through Carry
f, d Rotate Right f through Carry
f, d Subtract W from f
f, d Swap nybbles in f
f, d Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
0010 dfff ffff C,DC,Z
1110 dfff ffff
0110 dfff ffff Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b Bit Clear f
f, b Bit Set f
f, b Bit Test f, Skip if Clear
f, b Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01 00bb bfff ffff
01 01bb bfff ffff
01 10bb bfff ffff
01 11bb bfff ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11 111x kkkk kkkk C,DC,Z
11 1001 kkkk kkkk
10 0kkk kkkk kkkk
Z
00 0000 0110 0100 TO,PD
10 1kkk kkkk kkkk
Inclusive OR literal with W
Move literal to W
11 1000 kkkk kkkk
11 00xx kkkk kkkk
00 0000 0000 1001
11 01xx kkkk kkkk
00 0000 0000 1000
Z
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
00 0000 0110 0011 TO,PD
11 110x kkkk kkkk C,DC,Z
11 1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS41120B-page 134
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13.1 Instruction Descriptions
ADDLW
Add Literal and W
ANDWF
AND W with f
Syntax:
[label] ADDLW
0 ≤ k ≤ 255
k
Syntax:
[label] ANDWF f,d
Operands:
Operation:
Status Affected:
Description:
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
(W) + k → (W)
C, DC, Z
Operation:
(W) .AND. (f) → (destination)
Status Affected:
Description:
Z
The contents of the W register
are added to the eight bit literal ’k’
and the result is placed in the W
register.
AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W register. If 'd' is 1, the result
is stored back in register 'f'.
BCF
Bit Clear f
ADDWF
Syntax:
Add W and f
Syntax:
Operands:
[label] BCF f,b
[label] ADDWF f,d
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
0 → (f<b>)
Operation:
(W) + (f) → (destination)
Status Affected:
Description:
None
Status Affected: C, DC, Z
Bit 'b' in register 'f' is cleared.
Description:
Add the contents of the W register
with register ’f’. If ’d’ is 0, the result
is stored in the W register. If ’d’ is
1, the result is stored back in reg-
ister ’f’.
ANDLW
AND Literal with W
BSF
Bit Set f
Syntax:
[label] ANDLW
0 ≤ k ≤ 255
k
Syntax:
Operands:
[label] BSF f,b
Operands:
Operation:
Status Affected:
Description:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
(W) .AND. (k) → (W)
Operation:
1 → (f<b>)
Z
Status Affected:
Description:
None
The contents of W register are
AND’ed with the eight bit literal
'k'. The result is placed in the W
register.
Bit 'b' in register 'f' is set.
2002 Microchip Technology Inc.
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BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[label] BTFSS f,b
Syntax:
[label] CLRF
0 ≤ f ≤ 127
f
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
00h → (f)
1 → Z
Operation:
skip if (f<b>) = 1
Status Affected: None
Status Affected:
Description:
Z
Description:
If bit ’b’ in register ’f’ is ’0’, the next
The contents of register ’f’ are
instruction is executed.
cleared and the Z bit is set.
If bit ’b’ is ’1’, then the next instruc-
tion is discarded and a NOPis exe-
cuted instead making this a 2TCY
instruction.
BTFSC
Bit Test, Skip if Clear
CLRW
Clear W
Syntax:
[label] BTFSC f,b
Syntax:
[ label ] CLRW
None
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
Operation:
00h → (W)
1 → Z
Operation:
skip if (f<b>) = 0
Status Affected: None
Status Affected:
Description:
Z
Description:
If bit ’b’ in register ’f’ is ’1’, the next
W register is cleared. Zero bit (Z)
is set.
instruction is executed.
If bit ’b’, in register ’f’, is ’0’, the
next instruction is discarded, and
a NOPis executed instead, making
this a 2TCY instruction.
CLRWDT
Syntax:
Clear Watchdog Timer
[ label ] CLRWDT
None
CALL
Call Subroutine
Syntax:
[ label ] CALL
0 ≤ k ≤ 2047
k
Operands:
Operation:
Operands:
Operation:
00h → WDT
0 → WDT prescaler,
1 → TO
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
1 → PD
Status Affected: None
Status Affected: TO, PD
Description:
Call Subroutine. First, return
Description: CLRWDTinstruction resets the
address (PC+1) is pushed onto
the stack. The eleven bit immedi-
ate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALLis
a two cycle instruction.
Watchdog Timer. It also resets the
prescaler of the WDT. Status bits
TO and PD are set.
DS41120B-page 136
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COMF
Complement f
GOTO
Unconditional Branch
[ label ] GOTO k
0 ≤ k ≤ 2047
Syntax:
Operands:
[ label ] COMF f,d
Syntax:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Operation:
(f) → (destination)
Status Affected:
Description:
Z
Status Affected: None
The contents of register ’f’ are
complemented. If ’d’ is 0, the
result is stored in W. If ’d’ is 1, the
result is stored back in register ’f’.
Description:
GOTOis an unconditional branch.
The eleven bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTOis a two
cycle instruction.
DECF
Decrement f
INCF
Increment f
Syntax:
Operands:
[label] DECF f,d
Syntax:
Operands:
[ label ] INCF f,d
0 ≤ f ≤ 127
d ∈ [0,1]
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (destination)
Operation:
(f) + 1 → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Decrement register ’f’. If ’d’ is 0,
the result is stored in the W regis-
ter. If ’d’ is 1, the result is stored
back in register ’f’.
The contents of register ’f’ are
incremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
DECFSZ
Syntax:
Decrement f, Skip if 0
INCFSZ
Syntax:
Increment f, Skip if 0
[ label ] DECFSZ f,d
[ label ] INCFSZ f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (destination);
skip if result = 0
Operation:
(f) + 1 → (destination),
skip if result = 0
Status Affected: None
Status Affected: None
Description: The contents of register ’f’ are
Description: The contents of register ’f’ are
decremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
incremented. If ’d’ is 0, the result is
placed in the W register. If ’d’ is 1,
the result is placed back in regis-
ter ’f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
then a NOPis executed instead
making it a 2TCY instruction.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
a NOPis executed instead making
it a 2TCY instruction.
2002 Microchip Technology Inc.
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IORLW
Inclusive OR Literal with W
[ label ] IORLW k
0 ≤ k ≤ 255
MOVLW
Move Literal to W
[ label ] MOVLW k
0 ≤ k ≤ 255
Syntax:
Syntax:
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
Status Affected:
Description:
(W) .OR. k → (W)
Z
k → (W)
None
The contents of the W register are
OR’ed with the eight bit literal 'k'.
The result is placed in the W reg-
ister.
The eight bit literal 'k' is loaded
into W register. The don’t cares
will assemble as 0’s.
IORWF
Inclusive OR W with f
MOVWF
Move W to f
Syntax:
[ label ] IORWF f,d
Syntax:
[ label ] MOVWF
0 ≤ f ≤ 127
(W) → (f)
f
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
Status Affected:
Description:
Operation:
(W) .OR. (f) → (destination)
None
Status Affected:
Description:
Z
Move data from W register to reg-
ister 'f'.
Inclusive OR the W register with
register 'f'. If 'd' is 0 the result is
placed in the W register. If 'd' is 1
the result is placed back in regis-
ter 'f'.
NOP
No Operation
[ label ] NOP
None
MOVF
Move f
Syntax:
Syntax:
Operands:
[ label ] MOVF f,d
Operands:
Operation:
0 ≤ f ≤ 127
d ∈ [0,1]
No operation
Operation:
(f) → (destination)
Status Affected: None
Description: No operation.
Status Affected:
Description:
Z
The contents of register f are
moved to a destination dependant
upon the status of d. If d = 0, des-
tination is W register. If d = 1, the
destination is file register f itself. d
= 1 is useful to test a file register
since status flag Z is affected.
DS41120B-page 138
2002 Microchip Technology Inc.
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RETFIE
Return from Interrupt
[ label ] RETFIE
None
RLF
Rotate Left f through Carry
Syntax:
Syntax:
[ label ] RLF f,d
Operands:
Operation:
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
TOS → PC,
1 → GIE
Operation:
See description below
C
Status Affected: None
Status Affected:
Description:
The contents of register ’f’ are
rotated one bit to the left through
the Carry Flag. If ’d’ is 0, the
result is placed in the W register.
If ’d’ is 1, the result is stored back
in register ’f’.
C
Register f
RETLW
Return with Literal in W
RRF
Rotate Right f through Carry
Syntax:
[ label ] RETLW k
0 ≤ k ≤ 255
Syntax:
Operands:
[ label ] RRF f,d
Operands:
Operation:
0 ≤ f ≤ 127
d ∈ [0,1]
k → (W);
TOS → PC
Operation:
See description below
C
Status Affected: None
Status Affected:
Description:
Description:
The W register is loaded with the
The contents of register ’f’ are
rotated one bit to the right through
the Carry Flag. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
eight bit literal ’k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two cycle instruction.
C
Register f
SLEEP
RETURN
Syntax:
Return from Subroutine
[ label ] RETURN
None
Syntax:
[ label
]
SLEEP
Operands:
Operation:
Operands:
Operation:
None
TOS → PC
00h → WDT,
Status Affected: None
0 → WDT prescaler,
1 → TO,
Description: Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two cycle
instruction.
0 → PD
Status Affected:
Description:
TO, PD
The power-down status bit, PD
is cleared. Time-out status bit,
TO is set. Watchdog Timer and
its prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
See Section 12.8 for more
details.
2002 Microchip Technology Inc.
DS41120B-page 139
PIC16C717/770/771
SUBLW
Subtract W from Literal
XORLW
Exclusive OR Literal with W
Syntax:
[ label ]
Syntax:
[label]
SUBLW k
XORLW k
Operands:
Operation:
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
k - (W) → (W)
Operation:
(W) .XOR. k → (W)
Status Affected: C, DC, Z
Status Affected:
Description:
Z
Description:
The W register is subtracted (2’s
The contents of the W register
are XOR’ed with the eight bit lit-
eral 'k'. The result is placed in
the W register.
complement method) from the
eight bit literal 'k'. The result is
placed in the W register.
XORWF
Syntax:
Exclusive OR W with f
SUBWF
Subtract W from f
Syntax:
[ label ]
[label] XORWF f,d
SUBWF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) .XOR. (f) → (destination)
Operation:
(f) - (W) → (destination)
Status Affected:
Description:
Z
Status Affected: C, DC, Z
Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0, the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
Description:
Subtract (2’s complement method)
W register from register 'f'. If 'd' is 0,
the result is stored in the W regis-
ter. If 'd' is 1, the result is stored
back in register 'f'.
SWAPF
Syntax:
Swap Nybbles in f
[ label ] SWAPF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Status Affected: None
Description:
The upper and lower nybbles of
register 'f' are exchanged. If 'd' is
0, the result is placed in W regis-
ter. If 'd' is 1, the result is placed in
register 'f'.
DS41120B-page 140
2002 Microchip Technology Inc.
PIC16C717/770/771
The MPLAB IDE allows you to:
14.0 DEVELOPMENT SUPPORT
• Edit your source files (either assembly or ‘C’)
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools (auto-
matically updates all project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- absolute listing file
- machine code
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
The ability to use MPLAB IDE with multiple debugging
tools allows users to easily switch from the cost-
effective simulator to a full-featured emulator with
minimal retraining.
• Simulators
- MPLAB SIM Software Simulator
• Emulators
14.2 MPASM Assembler
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
• In-Circuit Debugger
The MPASM assembler is a full-featured universal
macro assembler for all PICmicro MCU’s.
- MPLAB ICD
The MPASM assembler has a command line interface
and a Windows shell. It can be used as a stand-alone
application on a Windows 3.x or greater system, or it
can be used through MPLAB IDE. The MPASM assem-
bler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
detail memory usage and symbol reference, an abso-
lute LST file that contains source lines and generated
machine code, and a COD file for debugging.
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Entry-Level Development
Programmer
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 17 Demonstration Board
- KEELOQ® Demonstration Board
The MPASM assembler features include:
• Integration into MPLAB IDE projects.
• User-defined macros to streamline assembly
code.
14.1 MPLAB Integrated Development
Environment Software
• Conditional assembly for multi-purpose source
files.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. The MPLAB IDE is a Windows®-based
application that contains:
• Directives that allow complete control over the
assembly process.
14.3 MPLAB C17 and MPLAB C18
C Compilers
• An interface to debugging tools
- simulator
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI ‘C’ compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers, respectively. These compilers provide
powerful integration capabilities and ease of use not
found with other compilers.
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor
• A project manager
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• Customizable toolbar and key mapping
• A status bar
• On-line help
2002 Microchip Technology Inc.
DS41120B-page 141
PIC16C717/770/771
14.4 MPLINK Object Linker/
MPLIB Object Librarian
14.6 MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can also
link relocatable objects from pre-compiled libraries,
using directives from a linker script.
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PICmicro
microcontrollers (MCUs). Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment (IDE),
which allows editing, building, downloading and source
debugging from a single environment.
The MPLIB object librarian is a librarian for pre-
compiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine will be linked in with the application. This allows
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLINK object linker features include:
• Integration with MPASM assembler and MPLAB
C17 and MPLAB C18 C compilers.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows environment were chosen to best
make these features available to you, the end user.
• Allows all memory areas to be defined as sections
to provide link-time flexibility.
The MPLIB object librarian features include:
• Easier linking because single libraries can be
included instead of many smaller files.
• Helps keep code maintainable by grouping
related modules together.
14.7 ICEPIC In-Circuit Emulator
• Allows libraries to be created and modules to be
added, listed, replaced, deleted or extracted.
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit One-
Time-Programmable (OTP) microcontrollers. The mod-
ular system can support different subsets of PIC16C5X
or PIC16CXXX products through the use of inter-
changeable personality modules, or daughter boards.
The emulator is capable of emulating without target
application circuitry being present.
14.5 MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC-hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user-defined key press, to any of the pins. The
execution can be performed in single step, execute
until break, or Trace mode.
The MPLAB SIM simulator fully supports symbolic debug-
ging using the MPLAB C17 and the MPLAB C18 C com-
pilers and the MPASM assembler. The software simulator
offers the flexibility to develop and debug code outside of
the laboratory environment, making it an excellent multi-
project software development tool.
DS41120B-page 142
2002 Microchip Technology Inc.
PIC16C717/770/771
14.8 MPLAB ICD In-Circuit Debugger
14.11 PICDEM 1 Low Cost PICmicro
Demonstration Board
Microchip’s In-Circuit Debugger, MPLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based on the FLASH PICmicro MCUs and can be used
to develop for this and other PICmicro microcontrollers.
The MPLAB ICD utilizes the in-circuit debugging capa-
bility built into the FLASH devices. This feature, along
with Microchip’s In-Circuit Serial ProgrammingTM proto-
col, offers cost-effective in-circuit FLASH debugging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by watch-
ing variables, single-stepping and setting break points.
Running at full speed enables testing hardware in real-
time.
The PICDEM 1 demonstration board is a simple board
which demonstrates the capabilities of several of
Microchip’s microcontrollers. The microcontrollers sup-
ported are: PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcon-
trollers provided with the PICDEM 1 demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulator and download the firmware to the emu-
lator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simu-
lated analog input, push button switches and eight
LEDs connected to PORTB.
14.9 PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
Stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions
and error messages, keys to enter commands and a
modular detachable socket assembly to support various
package types. In Stand-alone mode, the PRO MATE II
device programmer can read, verify, or program
PICmicro devices. It can also set code protection in this
mode.
14.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PICDEM 2 demonstration board is a simple dem-
onstration board that supports the PIC16C62,
PIC16C64, PIC16C65, PIC16C73 and PIC16C74
microcontrollers. All the necessary hardware and soft-
ware is included to run the basic demonstration pro-
grams. The user can program the sample
microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches, a potentiometer for simulated analog input, a
serial EEPROM to demonstrate usage of the I2CTM bus
and separate headers for connection to an LCD
module and a keypad.
14.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient.
The PICSTART Plus development programmer sup-
ports all PICmicro devices with up to 40 pins. Larger pin
count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.
2002 Microchip Technology Inc.
DS41120B-page 143
PIC16C717/770/771
14.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
14.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. All neces-
sary hardware is included to run basic demo programs,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM 17 dem-
onstration board supports downloading of programs to
and executing out of external FLASH memory on board.
The PICDEM 17 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMASTER emulator and all of the sample programs
can be run and modified using either emulator. Addition-
ally, a generous prototype area is available for user
hardware.
The PICDEM 3 demonstration board is a simple dem-
onstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-pin PLCC microcontrollers with an LCD Mod-
ule. All the necessary hardware and software is
included to run the basic demonstration programs. The
user can program the sample microcontrollers pro-
vided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer, or a PICSTART Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding hardware and connecting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commons and 12 segments, that is capable of display-
ing time, temperature and day of the week. The
PICDEM 3 demonstration board provides an additional
RS-232 interface and Windows software for showing
the demultiplexed LCD signals on a PC. A simple serial
interface allows the user to construct a hardware
demultiplexer for the LCD signals.
14.15 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS eval-
uation kit includes a LCD display to show changing
codes, a decoder to decode transmissions and a pro-
gramming interface to program test transmitters.
DS41120B-page 144
2002 Microchip Technology Inc.
PIC16C717/770/771
TABLE 14-1: DEVELOPMENT TOOLS FROM MICROCHIP
0 1 5 2 P M C
X X X C R M F
H C S X X X
X X C 9 3
/ X X C 2 5
/ X X C 2 4
X X X F 8 C 1 P I
X X C 8 2 C 1 P I
X 7 X 7 C 1 C I P
X 4 1 7 C I C P
X 9 X 6 C 1 C I P
X 8 X 6 F 1 C I P
X 8 1 6 C I C P
X 7 X 6 C 1 C I P
X 7 1 6 C I C P
X 6 2 1 6 C I F P
X
X X C 6 C 1 P I
X 6 1 6 C I C P
X 5 1 6 C I C P
0 0 1 4 C I 0 P
X
X X C 2 C 1 P I
s o l T e o r a w f t S o s r o t a u l E m e r u b g e g D s m e a r m o g P r r
s t K l a i E d v n a s d r a B o o m D e
2002 Microchip Technology Inc.
DS41120B-page 145
PIC16C717/770/771
NOTES:
DS41120B-page 146
2002 Microchip Technology Inc.
PIC16C717/770/771
15.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.................................................................................................................-55 to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V
Maximum voltage between AVDD and VDD pins................................................................................................................. 0.3V
Maximum voltage between AVSS and VSS pins ................................................................................................................. 0.3V
Voltage on MCLR with respect to VSS........................................................................................................ -0.3V to +8.5V
Voltage on RA4 with respect to Vss......................................................................................................... -0.3V to +10.5V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA and PORTB (combined).................................................................................200 mA
Maximum current sourced by PORTA and PORTB (combined) ...........................................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2002 Microchip Technology Inc.
DS41120B-page 147
PIC16C717/770/771
FIGURE 15-1:
PIC16C717/770/771 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +85°C
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
VDD
(Volts)
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 15-2:
PIC16LC717/770/771 VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +70°C
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
VDD
(Volts)
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
DS41120B-page 148
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 15-3:
PIC16LC717/770/771 VOLTAGE-FREQUENCY GRAPH,
-40°C ≤ TA ≤ 0°C, +70°C ≤ TA ≤ +85°C
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
VDD
(Volts)
0
4
10
Frequency (MHz)
20
25
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2002 Microchip Technology Inc.
DS41120B-page 149
PIC16C717/770/771
15.1 DC Characteristics: PIC16C717/770/771 (Commercial, Industrial, Extended)
PIC16LC717/770/771 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
PIC16LC717/770/771
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
PIC16C717/770/771
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param. Sym
No.
Characteristic
Min Typ† Max Units
Conditions
D001
D001
VDD
VDD
Supply Voltage
2.5
4.0
—
—
—
5.5
5.5
—
V
V
V
Supply Voltage
D002* VDR
RAM Data Retention
Voltage(1)
1.5
D002* VDR
D003* VPOR
RAM Data Retention
Voltage(1)
—
—
1.5
—
—
V
V
VSS
VDD start voltage to
ensure internal Power-
on Reset signal
See section on Power-on Reset for details
See section on Power-on Reset for details
VSS
—
D003* VPOR
D004* SVDD
D004* SVDD
VDD start voltage to
ensure internal Power-
on Reset signal
—
—
—
—
V
VDD rise rate to ensure
internal Power-on Reset
signal
0.05
0.05
V/ms See section on Power-on Reset for details.
PWRT enabled
VDD rise rate to ensure
internal Power-on Reset
signal
—
V/ms See section on Power-on Reset for details.
PWRT enabled
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
DS41120B-page 150
2002 Microchip Technology Inc.
PIC16C717/770/771
15.1 DC Characteristics: PIC16C717/770/771 (Commercial, Industrial, Extended)
PIC16LC717/770/771 (Commercial, Industrial, Extended)
(Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
PIC16LC717/770/771
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
PIC16C717/770/771
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param. Sym
No.
Characteristic
Min Typ† Max Units
Conditions
Supply Current(2)
IDD
D010D
D010E
PIC16LC7XX
1.0
2.0
3.0
mA FOSC = 10 MHz, VDD = 3V, -40°C to 85°C
FOSC = 10 MHz, VDD = 3V, -40°C to 125°C
D010G
0.36 1.0
mA FOSC = 4 MHz, VDD = 2.5V, -40°C to 125°C
µA FOSC = 32 kHz, VDD = 2.5V, -40°C to 125°C
D010K
IDD
11
45
Supply Current(2)
PIC16C7XX
D010
D010A
4.0
2.5
7.5
12.0
mA FOSC = 20 MHz, VDD = 5.5V, -40°C to 85°C
FOSC = 20 MHz, VDD = 5.5V, -40°C to 125°C
D010B
D010C
5.0
6.0
mA FOSC = 20 MHz, VDD = 4V, -40°C to 85°C
FOSC = 20 MHz, VDD = 4V, -40°C to 125°C
D010F
0.55 1.5
mA FOSC = 4 MHz, VDD = 4V, -40°C to 125°C
D010H
D010J
30
80
95
µA FOSC = 32 kHz, VDD = 4V, -40°C to 85°C
FOSC = 32 kHz, VDD = 4V, -40°C to 125°C
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
2002 Microchip Technology Inc.
DS41120B-page 151
PIC16C717/770/771
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
PIC16LC717/770/771
-40°C ≤ TA ≤ +125°C for extended
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
PIC16C717/770/771
-40°C ≤ TA ≤ +125°C for extended
Param. Sym
No.
Characteristic
Min Typ† Max Units
Conditions
Power-down Current(3)
PIC16LC7XX
IPD
D020D
D020E
0.3
2.0
5.0
µA VDD = 3V, -40°C to 85°C
VDD = 3V, -40°C to 125°C
D020F
D020G
0.1
1.4
1.5
3.0
µA VDD = 2.5V, -40°C to 85°C
VDD = 2.5V, -40°C to 125°C
D020
PIC16C7XX
4.0
8.0
µA VDD = 5.5V, -40°C to 85°C
VDD = 5.5V, -40°C to 125°C
D020A
D020B
D020C
1.0
3.5
6.0
µA VDD = 4V, -40°C to 85°C
VDD = 4V, -40°C to 125°C
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
DS41120B-page 152
2002 Microchip Technology Inc.
PIC16C717/770/771
15.1 DC Characteristics: PIC16C717/770/771 (Commercial, Industrial, Extended)
PIC16LC717/770/771 (Commercial, Industrial, Extended)
(Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
PIC16LC717/770/771
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
PIC16C717/770/771
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param. Sym
No.
Characteristic
Min Typ† Max Units
Conditions
Base plus Module current
Watchdog Timer
D021A
D021
D021
D025
D025
D025
D026*
D026*
IWDT
IWDT
IWDT
2
5
10
20
20
9
µA VDD = 3V, -40°C to 125°C
µA VDD = 4V, -40°C to 125°C
µA VDD = 4V, -40°C to 125°C
µA VDD = 3V, -40°C to 125°C
µA VDD = 4V, -40°C to 125°C
µA VDD = 4V, -40°C to 125°C
µA VDD = 5.5V, A/D on, not converting
µA VDD = 5.5V, A/D on, not converting
Watchdog Timer
Watchdog Timer
5
IT1OSC Timer1 Oscillator
IT1OSC Timer1 Oscillator
IT1OSC Timer1 Oscillator
3
4
12
12
4
IAD
IAD
ADC Converter
ADC Converter
300
300
55
D027
IPLVD Programmable Low
Voltage Detect
125
150
µA VDD = 4V, -40°C to 85°C
VDD = 4V, -40°C to 125°C
D027A
D027
IPLVD Programmable Low
Voltage Detect
55
55
55
125
150
µA VDD = 4V, -40°C to 85°C
VDD = 4V, -40°C to 125°C
D027A
D028
IPBOR Programmable Brown-
out Reset
125
150
µA VDD = 5V, -40°C to 85°C
VDD = 5V, -40°C to 125°C
D028A
D028
IPBOR Programmable Brown-
out Reset
125
150
µA VDD = 5V, -40°C to 85°C
VDD = 5V, -40°C to 125°C
D028A
D029
IVRH
IVRH
IVRL
IVRL
Voltage reference High
Voltage reference High
Voltage reference Low
Voltage reference Low
200 750
1.0
µA VDD = 5V, -40°C to 85°C
mA VDD = 5V, -40°C to 125°C
D029A
D029
200 750
1.0
µA VDD = 5V, -40°C to 85°C
mA VDD = 5V, -40°C to 125°C
D029A
D030
200 750
1.0
µA VDD = 4V, -40°C to 85°C
mA VDD = 4V, -40°C to 125°C
D030A
D030
200 750
1.0
µA VDD = 4V, -40°C to 85°C
mA VDD = 4V, -40°C to 125°C
D030A
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
2002 Microchip Technology Inc.
DS41120B-page 153
PIC16C717/770/771
15.2 DC Characteristics: PIC16C717/770/771 & PIC16LC717/770/771 (Commercial,
Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Operating voltage VDD range as described in Section 15.1 and
Section 15.2.
Param. Sym
No.
Characteristic
Min
Typ† Max Units
Conditions
Input Low Voltage
VIL I/O ports
D030
D030A
D031
D032
with TTL buffer
VSS
VSS
VSS
VSS
—
—
—
—
0.15VDD
0.8V
0.2VDD
0.2VDD
V
V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
with Schmitt Trigger buffer
MCLR
D033
OSC1 (in XT, HS, LP and EC)
VSS
—
0.3VDD
V
Input High Voltage
VIH I/O ports
with TTL buffer
—
D040
D040A
2.0
(0.25VDD
+ 0.8V)
—
—
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
D041
D042
D042A
with Schmitt Trigger buffer 0.8VDD
—
—
—
VDD
VDD
VDD
400
V
V
V
For entire VDD range
MCLR
OSC1 (XT, HS, LP and EC)
0.8VDD
0.7VDD
50
D070 IPURB PORTB weak pull-up current
per pin
250
µA VDD = 5V, VPIN = VSS
Input Leakage Current (1,2)
D060
D060A
IIL I/O ports (with digital functions)
IIL I/O ports (with analog func-
—
—
—
—
1
100
µA Vss ≤ VPIN ≤ VDD, Pin at hi-impedance
nA Vss ≤ VPIN ≤ VDD, Pin at hi-impedance
tions)
D061
D063
RA5/MCLR/VPP
OSC1
—
—
—
—
5
5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS, LP and EC
osc configuration
Output Low Voltage
VOL I/O ports
Output High Voltage
I/O ports(2)
VOH
D080
D090
—
—
0.6
V
IOL = 8.5 mA, VDD = 4.5V
VDD - 0.7
—
—
—
V
V
IOH = -3.0 mA, VDD = 4.5V
RA4 pin
D150* VOD Open Drain High Voltage
Capacitive Loading Specs on
Output Pins*
—
10.5
D100
COS OSC2 pin
—
—
15
pF In XT, HS and LP modes when exter-
C2
nal clock is used to drive OSC1.
D101
D102
CIO All I/O pins and OSC2 (in RC
—
—
—
—
50
400
pF
pF
mode) SCL, SDA in I2C mode
CB
—
—
—
—
CVRH VRH pin
CVRL VRL pin
200
200
pF VRH output enabled
pF VRL output enabled
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
2: Negative current is defined as current sourced by the pin.
DS41120B-page 154
2002 Microchip Technology Inc.
PIC16C717/770/771
15.3 AC Characteristics: PIC16C717/770/771 & PIC16LC717/770/771
(Commercial, Industrial, Extended)
15.3.1
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created using one of the following formats:
1. TppS2ppS
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
2. TppS
T
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
I2C (I2C specifications only)
AA
output access
Bus free
High
BUF
High
Low
Low
TCC:ST (I2C specifications only)
CC
HD
ST
DAT
STA
Hold
SU
Setup
DATA input hold
START condition
STO
STOP condition
2002 Microchip Technology Inc.
DS41120B-page 155
PIC16C717/770/771
FIGURE 15-4:
LOAD CONDITIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF
15 pF
for all pins except OSC2
for OSC2 output
DS41120B-page 156
2002 Microchip Technology Inc.
PIC16C717/770/771
15.3.2
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 15-5:
CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
(1)
CLKOUT
13
14
12
18
19
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 15-4 for load conditions.
TABLE 15-1: CLKOUT AND I/O TIMING REQUIREMENTS
Param.
No.
Sym
Characteristic
Min
Typ†
Max
Unit Conditions
s
12*
TckR
TckF
CLKOUT rise time
CLKOUT fall time
—
—
—
35
35
—
—
—
50
100
ns
ns
ns
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
Note 1
13*
14*
15*
16*
17*
100
TckL2ioV CLKOUT ↓ to Port out valid
TioV2ckH Port in valid before CLKOUT ↑
0.5TCY + 20
0.25TCY + 25
—
—
TckH2ioI
Port in hold after CLKOUT ↑
0
TosH2ioV OSC1↑ (Q1 cycle) to
—
150
Port out valid
PIC16C717/770/771
PIC16LC717/770/771
18*
TosH2ioI
OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
100
200
—
—
—
—
ns
ns
19*
20*
TioV2osH Port input valid to OSC1↑ (I/O in setup time)
0
—
—
10
—
10
—
—
—
—
25
60
25
60
—
—
ns
ns
ns
ns
ns
ns
ns
PIC16C717/770/771
PIC16LC717/770/771
PIC16C717/770/771
PIC16LC717/770/771
TioR
Port output rise time
Port output fall time
INT pin high or low time
—
21*
TioF
—
—
22††*
23††*
Tinp
Trbp
TCY
TCY
RB<7:0> change INT high or low time
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken ER or INTRC w/CLKOUT mode where CLKOUT output is 4 x TOSC.
2002 Microchip Technology Inc.
DS41120B-page 157
PIC16C717/770/771
FIGURE 15-6:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
4
Q1
OSC1
1
3
4
3
2
TABLE 15-2: EXTERNAL CLOCK TIMING REQUIREMENTS
Param No. Sym Characteristic Min Typ†
Max
Units Conditions
1A
FOSC
External CLKIN Frequency
(Note 1)
DC
DC
DC
DC
0.1*
—
—
—
—
—
4
20
20
200
4
MHz XT mode
MHz EC mode
MHz HS mode
kHz LP mode
MHz XT mode
Oscillator Frequency
(Note 1)
4*
5*
—
—
20
200
MHz HS mode
kHz LP mode
1
TOSC
External CLKIN Period
(Note 1)
250
50
50
5
—
—
—
—
—
—
—
TCY
—
—
—
—
—
ns
ns
ns
µs
ns
ns
µs
ns
ns
µs
ns
XT mode
EC mode
HS mode
LP mode
XT mode
HS mode
LP mode
TCY = 4/FOSC
XT mode
LP mode
HS mode
EC mode
XT mode
LP mode
HS mode
EC mode
—
—
Oscillator Period
(Note 1)
250
50
5
10,000*
250*
—
2
TCY
Instruction Cycle Time (Note 1)
200
DC
—
3*
TosL,
TosH
External Clock in (OSC1) High or Low 100
Time
2.5
—
15
—
4*
TosR,
TosF
External Clock in (OSC1) Rise or Fall
Time
—
—
—
—
—
—
25
50
15
ns
ns
ns
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at "Max. Frequency" values with a square wave applied to the OSC1/CLKIN
pin.
When an external clock input is used, the "Min." frequency (or Max. TCY) limit is "DC" (no clock) for all devices.
DS41120B-page 158
2002 Microchip Technology Inc.
PIC16C717/770/771
TABLE 15-3: CALIBRATED INTERNAL RC FREQUENCIES - PIC16C717/770/771 AND
PIC16LC717/770/771
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Operating Voltage VDD range is described in Section and Section
Parameter
Sym
Typ(1)*
Characteristic
Min
Max Units
Conditions
No.
Internal Calibrated RC Frequency 3.65 4.00
Internal RC Frequency* 3.55 4.00
4.28 MHz VDD = 5.0V
4.31 MHz VDD = 2.5V
FIRC
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
FIGURE 15-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 15-4 for load conditions.
FIGURE 15-8:
BROWN-OUT RESET TIMING
VBOR
VDD
35
2002 Microchip Technology Inc.
DS41120B-page 159
PIC16C717/770/771
TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ†
Max Units
Conditions
30*
31*
TMCL
MCLR Pulse Width (low)
2
7
—
—
µs
VDD = 5V, -40°C to +85°C
VDD = 5V, -40°C to +85°C
TWDT
Watchdog Timer Time-out Period
(No Prescaler)
18
33
ms
32*
33*
34*
TOST
Oscillation Start-up Timer Period
Power up Timer Period
—
28
—
1024 TOSC
—
—
ms
µs
TOSC = OSC1 period
TPWRT
72
132
2.1
VDD = 5V, -40°C to +85°C
TIOZ
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
—
35*
TBOR
Brown-out Reset pulse width
100
—
—
µs
VDD ≤ VBOR (D005)
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 15-9:
BROWN-OUT RESET CHARACTERISTICS
VDD
VBOR
(device not in Brown-out Reset)
(device in Brown-out Reset)
RESET (due to BOR)
72 ms time-out
FIGURE 15-10:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RB6/T1OSO/T1CKI/PIC
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 15-4 for load conditions.
DS41120B-page 160
2002 Microchip Technology Inc.
PIC16C717/770/771
TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param.
No.
Sym Characteristic
Min
Typ† Max Units Conditions
40*
Tt0H
T0CKI High Pulse Width
No Prescaler
0.5TCY + 20
—
—
ns Must also meet
parameter 42
With Prescaler
No Prescaler
10
0.5TCY + 20
10
—
—
—
—
—
—
—
—
—
—
ns
41*
42*
Tt0L
Tt0P
T0CKI Low Pulse Width
T0CKI Period
ns Must also meet
parameter 42
With Prescaler
No Prescaler
With Prescaler
ns
ns
TCY + 40
Greater of:
20 or TCY + 40
ns N = prescale value
(2, 4, ..., 256)
N
0.5TCY + 20
15
45*
46*
47*
Tt1H
Tt1L
Tt1P
T1CKI High Time
T1CKI Low Time
Synchronous, Prescaler = 1
—
—
—
—
—
—
ns Must also meet
parameter 47
Synchronous, PIC16C717/770/771
ns
ns
Prescaler =
2,4,8
PIC16LC717/770/771
25
Asynchronous PIC16C717/770/771
PIC16LC717/770/771
30
—
—
—
—
—
—
—
—
—
—
ns
ns
50
0.5TCY + 20
15
Synchronous, Prescaler = 1
ns Must also meet
parameter 47
Synchronous, PIC16C717/770/771
ns
ns
Prescaler =
2,4,8
PIC16LC717/770/771
25
Asynchronous PIC16C717/770/771
PIC16LC717/770/771
30
50
—
—
—
—
—
—
ns
ns
T1CKI input period Synchronous PIC16C717/770/771 Greater of:
30 OR TCY + 40
ns N = prescale value
(1, 2, 4, 8)
N
PIC16LC717/770/771 Greater of:
—
—
ns N = prescale value
(1, 2, 4, 8)
50 OR TCY + 40
N
Asynchronous PIC16C717/770/771
PIC16LC717/770/771
60
100
DC
—
—
—
—
—
50
ns
ns
Ft1
Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN)
kHz
48
*
Tcke2tmr1 Delay from external clock edge to timer increment
2Tosc
—
7Tosc
—
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 15-11:
ENHANCED CAPTURE/COMPARE/PWM TIMINGS (ECCP)
RB3/CCP1/P1A
(Capture Mode)
50
51
52
RB3/CCP1/P1A
(Compare or PWM Mode)
53
Note: Refer to Figure 15-4 for load conditions.
54
2002 Microchip Technology Inc.
DS41120B-page 161
PIC16C717/770/771
TABLE 15-6: ENHANCED CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP)
Param. Sym Characteristic
No.
Min
Typ† Max Units Conditions
50*
51*
TccL CCP1 input low
time
No Prescaler
0.5TCY + 20
—
—
ns
PIC16C717/770/771
PIC16LC717/770/771
10
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
With Prescaler
No Prescaler
20
0.5TCY + 20
10
TccH
CCP1 input high
time
PIC16C717/770/771
PIC16LC717/770/771
With Prescaler
20
52*
53*
TccP
3TCY + 40
N
ns N = prescale value
(1, 4 or 16)
CCP1 input period
PIC16C717/770/771
PIC16LC717/770/771
PIC16C717/770/771
PIC16LC717/770/771
TccR CCP1 output fall time
TccF CCP1 output fall time
—
—
—
—
10
25
10
25
25
45
25
45
ns
ns
ns
ns
54*
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS41120B-page 162
2002 Microchip Technology Inc.
PIC16C717/770/771
15.4 Analog Peripherals Characteristics: PIC16C717/770/771 & PIC16LC717/770/771
(Commercial, Industrial, Extended)
15.4.1
BANDGAP MODULE
FIGURE 15-12:
BANDGAP START-UP TIME
VBGAP
VBGAP = 1.2V
(internal use only)
Enable Bandgap
Bandgap stable
TBGAP
TABLE 15-7: BANDGAP START-UP TIME
Param.
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
36*
TBGAP
Bandgap start-up time
—
19
33
µS Defined as the time between the
instant that the bandgap is
enabled and the moment that
the bandgap reference voltage
is stable.
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
2002 Microchip Technology Inc.
DS41120B-page 163
PIC16C717/770/771
15.4.2
LOW VOLTAGE DETECT MODULE (LVD)
FIGURE 15-13:
LOW VOLTAGE DETECT CHARACTERISTICS
VDD
VLVD
(LVDIF set by hardware)
LVDIF
(LVDIF can be cleared in software anytime during
the gray area)
TABLE 15-8: ELECTRICAL CHARACTERISTICS: LVD
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial
DC CHARACTERISTICS
Operating voltage VDD range as described in DC Characteristics Section 15.1.
Param.
No.
Characteristic
Symbol
Min Typ† Max Units
Conditions
D420*
LVD Voltage
LVV = 0100
LVV = 0101
LVV = 0110
LVV = 0111
LVV = 1000
LVV = 1001
LVV = 1010
LVV = 1011
LVV = 1100
LVV = 1101
LVV = 1110
2.5
2.7
2.8
3.0
3.3
3.5
3.6
3.8
4.0
4.2
4.5
2.58 2.66
2.78 2.86
2.89 2.98
V
V
V
V
V
V
V
V
V
V
V
3.1
3.2
3.41 3.52
3.61 3.72
3.72 3.84
3.92 4.04
4.13 4.26
4.33 4.46
4.64 4.78
VLVD
*
These parameters are characterized but not tested.
Note 1: Production tested at Tamb = 25°C. Specifications over temperature limits ensured by characterization.
DS41120B-page 164
2002 Microchip Technology Inc.
PIC16C717/770/771
15.4.3
PROGRAMMABLE BROWN-OUT RESET MODULE (PBOR)
TABLE 15-9: DC CHARACTERISTICS: PBOR
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC Characteristics Section 15.1.
Param.
No.
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
2.5
2.58
2.66
D005
BOR Voltage
BORV<1:0> = 11
BORV<1:0> = 10
BORV<1:0> = 01
BORV<1:0> = 00
2.7
4.2
4.5
2.78
4.33
4.64
2.86
4.46
4.78
VBOR
V
15.4.4
VREF MODULE
TABLE 15-10: DC CHARACTERISTICS: VREF
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param. Symbol
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC Characteristics
Section 15.1.
Characteristic
Min
Typ†
Max
Units
Conditions
No.
D400
VRL
VRH
Output Voltage
Output Voltage
2.0
4.0
1.9
4.0
—
2.048
4.096
2.048
4.096
—
2.1
4.2
2.2
4.3
5
V
V
VDD ≥ 2.7V, -40°C ≤ TA ≤ +85°C
VDD ≥ 4.5V, -40°C ≤ TA ≤ +85°C
VDD ≥ 2.7V, -40°C ≤ TA ≤ +125°C
VDD ≥ 4.5V, -40°C ≤ TA ≤ +125°C
D400A VRL
VRH
V
V
D404* IVREFSO External Load Source
D405* IVREFSI External Load Sink
mA
mA
pF
—
—
-5
*
CL
External Capacitor Load
—
—
200
1
D406* ∆Vout/ VRH Load Regulation
∆Iout
—
0.6
mV/mA VDD ≥ 5V ISOURCE = 0 mA to 5 mA
ISINK = 0 mA to 5 mA
—
1
4
VRL Load Regulation
—
0.6
1
VDD ≥ 3V ISOURCE = 0 mA to 5 mA
ISINK = 0 mA to 5 mA
—
2
4
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are
for design guidance only and are not tested.
2002 Microchip Technology Inc.
DS41120B-page 165
PIC16C717/770/771
15.4.5
A/D CONVERTER MODULE
TABLE 15-11: PIC16C770/771 AND PIC16LC770/771 A/D CONVERTER CHARACTERISTICS:
Param. Sym Characteristic
No.
Min
Typ†
Max
Units
Conditions
A01
NR
Resolution
—
—
12 bits
bit Min. resolution for A/D is 1 mV,
VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A03
A04
EIL
Integral error
—
—
—
—
LSb VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
±2
VREF- ≤ VAIN ≤ VREF+
EDL
Differential error
LSb No missing codes to 12 bits
VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
+2
-1
VREF- ≤ VAIN ≤ VREF+
A06
A07
EOFF Offset error
—
—
—
—
LSb VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
±2
VREF- ≤ VAIN ≤ VREF+
EGN
Gain Error
LSb VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
±2
VREF- ≤ VAIN ≤ VREF+
A10
—
Monotonicity
—
Note 3
—
—
AVSS ≤ VAIN ≤ VREF+
A20*
VREF Reference voltage
(VREF+ - VREF-)
4.096
—
VDD
+0.3V
V
Absolute minimum electrical spec to
ensure 12-bit accuracy.
A21*
A22*
A25*
A30*
VREF+ Reference V High
(AVDD or VREF+)
VREF-
AVSS
VREFL
—
—
—
—
—
AVDD
VREF+
VREFH
2.5
V
V
Min. resolution for A/D is 1 mV
VREF- Reference V Low
(AVSS or VREF-)
Min. resolution for A/D is 1 mV
VAIN
Analog input volt-
age
V
ZAIN
Recommended
kΩ
impedance of ana-
log voltage source
A50*
IREF
VREF input current
(Note 2)
—
—
10
µA During VAIN acquisition.
Based on differential of VHOLD to
VAIN.
To charge CHOLD see Section 11.0.
During A/D conversion cycle.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current
spec includes any such leakage from the A/D module.
2: VREF input current is from External VREF+, or VREF-, or AVSS, or AVDD pin, whichever is selected as refer-
ence input.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
DS41120B-page 166
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 15-14:
PIC16C770/771 AND PIC16LC770/771 A/D CONVERSION TIMING (NORMAL
MODE)
BSF ADCON0, GO
134
Q4
1/2 TCY
131
130
A/D CLK
11
10
9
8
3
2
1
0
A/D DATA
ADRES
NEW_DATA
DONE
OLD_DATA
ADIF
GO
SAMPLING STOPPED
132
SAMPLE
Note 1: If the A/D RC clock source is selected, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
2002 Microchip Technology Inc.
DS41120B-page 167
PIC16C717/770/771
TABLE 15-12: PIC16C770/771 AND PIC16LC770/771 A/D CONVERSION REQUIREMENTS
(NORMAL MODE)
Parameter Sym Characteristic
No.
Min
Typ†
Max
Units
Conditions
130*(3)
TAD
A/D clock period
1.6
3.0
—
—
—
—
µs Tosc based, VREF ≥ 2.5V
µs Tosc based, VREF full range
ADCS<1:0> = 11
(A/D RC mode)
3.0
2.0
—
6.0
4.0
9.0
6.0
—
µs At VDD = 2.5V
µs At VDD = 5.0V
131*
132*
TCNV
TACQ
Conversion time
(not including
acquisition time)
(Note 1)
13TAD
TAD
Acquisition Time
Note 2
11.5
—
—
µs
5*
—
µs The minimum time is the ampli-
fier settling time. This may be
used if the “new” input voltage
has not changed by more than
1LSb (i.e., 1mV @ 4.096V) from
the last sampled voltage (as
stated on CHOLD).
134*
TGO
Q4 to A/D clock
start
—
TOSC/2
—
—
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.6 for minimum conditions.
3: These numbers multiplied by 8 if VRH or VRL is selected as A/D reference.
DS41120B-page 168
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 15-15:
PIC16C770/771 AND PIC16LC770/771 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
134
131
Q4
130
A/D CLK
11
10
9
3
2
1
0
8
A/D DATA
OLD_DATA
NEW_DATA
DONE
ADRES
ADIF
GO
SAMPLING STOPPED
132
SAMPLE
Note 1: If the A/D RC clock source is selected, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
TABLE 15-13: PIC16C770/771 AND PIC16LC770/771 A/D CONVERSION REQUIREMENT
(SLEEP MODE)
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
(3)
TAD
A/D Internal RC
oscillator period
ADCS<1:0> = 11 (RC mode)
At VDD= 3.0V
130*
3.0
2.0
—
6.0
4.0
9.0
6.0
—
µs
µs
—
At VDD = 5.0V
131*
132*
TCNV
TACQ
Conversion time (not
including acquisition
time) (Note 1)
13TAD
Acquisition Time
(Note 2)
11.5
—
—
µs
µs
5*
—
The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1LSb (i.e.,
1mV @ 4.096V) from the last sam-
pled voltage (as stated on CHOLD).
134*
TGO
Q4 to A/D clock start
—
TOSC/2 + TCY
—
—
If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEPinstruction to be
executed.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.6 for minimum conditions.
3: These numbers multiplied by 8 if VRH or VRL is selected as A/D reference.
2002 Microchip Technology Inc.
DS41120B-page 169
PIC16C717/770/771
TABLE 15-14: PIC16C717 AND PIC16LC717 A/D CONVERTER CHARACTERISTICS:
Param.
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
A01
NR
Resolution
—
—
10 bits
bit
Min. resolution for A/D is 4.1 mV,
VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A03
A04
EIL
Integral error
—
—
—
—
LSb VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
±1
±1
VREF- ≤ VAIN ≤ VREF+
EDL
Differential error
LSb No missing codes to 10 bits
VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A06
A07
EOFF
EGN
Offset error
Gain Error
—
—
—
—
LSb VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
±2
±1
VREF- ≤ VAIN ≤ VREF+
LSb VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A10
—
Monotonicity
—
Note 3
—
—
AVSS ≤ VAIN ≤ VREF+
A20*
VREF
Reference voltage
(VREF+ - VREF-)
4.096
—
VDD +0.3V
V
Absolute minimum electrical spec to
ensure 10-bit accuracy.
A21*
A22*
VREF+ Reference V High
(AVDD or VREF+)
VREF-
AVSS
—
—
AVDD
V
V
Min. resolution for A/D is 4.1 mV
VREF-
Reference V Low
(AVSS or VREF-)
VREF+
Min. resolution for A/D is 4.1 mV
A25*
A30*
VAIN
ZAIN
Analog input voltage
VREFL
—
—
VREFH
2.5
V
Recommended
—
kΩ
impedance of analog
voltage source
A50*
IREF
VREF input current
—
—
10
µA
During VAIN acquisition.
(Note 2)
Based on differential of VHOLD to VAIN.
To charge CHOLD see Section 11.0.
During A/D conversion cycle.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than leakage current. The power-down current spec includes any such
leakage from the A/D module.
2: VREF current is from External VREF+, or VREF-, or AVSS, or AVDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
DS41120B-page 170
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 15-16:
PIC16C717 A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
134
Q4
1/2 TCY
131
130
A/D CLK
9
8
7
6
3
2
1
0
A/D DATA
ADRES
NEW_DATA
DONE
OLD_DATA
ADIF
GO
SAMPLING STOPPED
132
SAMPLE
Note 1: If the A/D RC clock source is selected, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
TABLE 15-15: PIC16C717 AND PIC16LC717 A/D CONVERSION REQUIREMENT (NORMAL MODE)
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
(3)
TAD
A/D clock period
1.6
3.0
—
—
—
—
µs
µs
Tosc based, VREF ≥ 2.5V
130*
Tosc based, VREF full range
ADCS<1:0> = 11 (A/D RC mode)
At VDD = 2.5V
3.0
2.0
—
6.0
4.0
9.0
6.0
—
µs
µs
At VDD = 5.0V
131*
132*
TCNV
TACQ
Conversion time (not
including
acquisition time)
(Note 1)
11TAD
TAD
Acquisition Time
(Note 2)
11.5
—
—
µs
µs
5*
—
The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1LSb (i.e.,
1mV @ 4.096V) from the last sam-
pled voltage (as stated on CHOLD).
134*
TGO
Q4 to A/D clock start
—
TOSC/2
—
—
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.6 for minimum conditions.
3:These numbers multiplied by 8 if VRH or VRL is selected as A/D reference.
2002 Microchip Technology Inc.
DS41120B-page 171
PIC16C717/770/771
FIGURE 15-17:
PIC16C717 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
134
131
Q4
130
A/D CLK
9
8
7
3
2
1
0
6
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
132
SAMPLE
Note 1: If the A/D RC clock source is selected, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
TABLE 15-16: PIC16C717 AND PIC16LC717 A/D CONVERSION REQUIREMENT (SLEEP MODE)
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
(3)
TAD
A/D clock period
3.0
6.0
9.0
µs
ADCS<1:0> = 11 (A/D RC mode)
At VDD = 3.0V
130*
2.0
4.0
6.0
µs
At VDD = 5.0V
131*
132*
TCNV
TACQ
Conversion time (not
including acquisition
time) (Note 1)
—
11TAD
—
—
Acquisition Time
(Note 2)
11.5
—
—
µs
µs
5*
—
The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1LSb (i.e.,
1mV @ 4.096V) from the last sam-
pled voltage (as stated on CHOLD).
134*
TGO
Q4 to A/D clock start
—
TOSC/2 + TCY
—
—
If the A/D RC clock source is
selected, a time of TCY is added
before the A/D clock starts. This
allows the SLEEPinstruction to be
executed.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.6 for minimum conditions.
3: These numbers multiplied by 8 if VRH or VRL is selected as A/D reference.
DS41120B-page 172
2002 Microchip Technology Inc.
PIC16C717/770/771
15.5 Master SSP SPI Mode Timing Waveforms and Requirements
FIGURE 15-18:
SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
BIT6 - - - - - -1
LSb
SDO
SDI
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note: Refer to Figure 15-4 for load conditions.
TABLE 15-17: SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param.
Symbol Characteristic
Min
Typ† Max Units Conditions
No.
70*
TssL2scH,
TssL2scL
TCY
—
—
ns
SS↓ to SCK↓ or SCK↑ input
71*
71A*
72*
TscH
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
—
—
—
ns
40
1.25TCY + 30
40
ns Note 1
ns
TscL
SCK input low time
(Slave mode)
72A*
73*
ns Note 1
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge
100
—
—
—
—
ns
73A* TB2B
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40
ns Note 1
74*
75*
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
100
—
—
ns
TdoR
SDO data output rise time PIC16CXXX
PIC16LCXXX
—
—
—
—
—
—
—
—
10
20
10
10
20
10
—
—
25
45
25
25
45
25
50
100
ns
ns
ns
ns
ns
ns
ns
ns
76*
78*
TdoF
TscR
SDO data output fall time
SCK output rise time
(Master mode)
PIC16CXXX
PIC16LCXXX
79*
80*
TscF
SCK output fall time (Master mode)
TscH2doV, SDO data output valid
TscL2doV after SCK edge
PIC16CXXX
PIC16LCXXX
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
2002 Microchip Technology Inc.
DS41120B-page 173
PIC16C717/770/771
FIGURE 15-19:
SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
BIT6 - - - - - -1
BIT6 - - - -1
LSb
MSb
SDO
SDI
75, 76
MSb IN
74
LSb IN
Note: Refer to Figure 15-4 for load conditions.
TABLE 15-18: SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
Symbol Characteristic
Min
Typ† Max Units Conditions
No.
71*
TscH
TscL
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
—
—
—
—
—
ns
71A*
72*
40
1.25TCY + 30
40
ns Note 1
SCK input low time
(Slave mode)
ns
72A*
73*
ns Note 1
TdiV2scH, Setup time of SDI data input to SCK
100
ns
TdiV2scL
edge
73A* TB2B
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40
—
—
ns Note 1
74*
75*
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
100
—
—
ns
TdoR
SDO data output rise
time
PIC16CXXX
—
10
20
10
10
20
10
—
—
25
45
25
25
45
25
50
100
ns
ns
ns
ns
ns
ns
ns
ns
PIC16LCXXX
76*
78*
TdoF
TscR
SDO data output fall time
—
—
SCK output rise time
(Master mode)
PIC16CXXX
PIC16LCXXX
79*
80*
TscF
SCK output fall time (Master mode)
—
—
TscH2doV, SDO data output valid
TscL2doV after SCK edge
PIC16CXXX
PIC16LCXXX
81*
*
TdoV2scH,
TdoV2scL
SDO data output setup to SCK edge
TCY
—
—
ns
These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS41120B-page 174
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 15-20:
SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
LSb
SDO
SDI
BIT6 - - - - - -1
77
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note: Refer to Figure 15-4 for load conditions.
TABLE 15-19: SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)
Param.
No.
Symbol
Characteristic
Min
Typ† Max Units
Conditions
70*
TssL2scH,
TssL2scL
TCY
—
—
ns
SS↓ to SCK↓ or SCK↑ input
71*
71A*
72*
TscH
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
—
—
—
ns
ns
ns
ns
40
1.25TCY + 30
40
Note 1
TscL
SCK input low time
(Slave mode)
72A*
73*
Note 1
Note 1
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge
100
—
—
—
—
ns
ns
73A*
74*
TB2B
Last clock edge of Byte1 to the 1st clock edge
of Byte2
1.5TCY + 40
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
100
—
—
ns
75*
TdoR
SDO data output rise time
SDO data output fall time
PIC16CXXX
—
10
20
10
—
10
20
10
—
—
—
25
45
25
50
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC16LCXXX
76*
77*
78*
TdoF
—
10
—
TssH2doZ
TscR
SS↑ to SDO output hi-impedance
SCK output rise time (Master PIC16CXXX
mode)
PIC16LCXXX
79*
80*
TscF
SCK output fall time (Master mode)
—
—
TscH2doV,
TscL2doV
SDO data output valid after
SCK edge
PIC16CXXX
PIC16LCXXX
83*
TscH2ssH,
TscL2ssH
1.5TCY + 40
SS ↑ after SCK edge
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
2002 Microchip Technology Inc.
DS41120B-page 175
PIC16C717/770/771
FIGURE 15-21:
SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
BIT6 - - - - - -1
BIT6 - - - -1
LSb
SDO
SDI
75, 76
77
MSb IN
74
LSb IN
Note: Refer to Figure 15-4 for load conditions.
TABLE 15-20: SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Typ† Max Units
Conditions
70*
TssL2scH,
TssL2scL
TCY
—
—
ns
SS↓ to SCK↓ or SCK↑ input
71*
71A*
72*
TscH
TscL
TB2B
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
40
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
Note 1
SCK input low time
(Slave mode)
1.25TCY + 30
40
72A*
73A*
Note 1
Note 1
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40
74*
75*
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
100
—
—
ns
TdoR
SDO data output rise time PIC16CXXX
PIC16LCXXX
—
10
20
10
—
25
45
25
50
ns
ns
ns
ns
76*
77*
TdoF
SDO data output fall time
—
TssH2doZ
10
SS↑ to SDO output hi-impedance
78*
TscR
SCK output rise time (Mas- PIC16CXXX
—
10
20
10
—
—
—
—
—
25
45
ns
ns
ns
ns
ns
ns
ns
ns
ter mode)
PIC16LCXXX
—
79*
80*
TscF
SCK output fall time (Master mode)
—
25
TscH2doV,
TscL2doV
SDO data output valid after PIC16CXXX
—
50
SCK edge
PIC16LCXXX
—
100
50
82*
83*
TssL2doV
SDO data output valid after PIC16CXXX
—
—
SS↓ edge
PIC16LCXXX
100
—
TscH2ssH,
TscL2ssH
1.5TCY + 40
SS ↑ after SCK edge
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS41120B-page 176
2002 Microchip Technology Inc.
PIC16C717/770/771
2
15.6 Master SSP I C Mode Timing Waveforms and Requirements
FIGURE 15-22:
MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS
SCL
SDA
93
91
90
92
STOP
Condition
START
Condition
Note: Refer to Figure 15-4 for load conditions.
TABLE 15-21: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS
Param.
No.
Symbol Characteristic
Min
Typ Max Units
Conditions
90*
TSU:STA START condition 100 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
—
Only relevant for a Repeated
START
condition
Setup time
400 kHz mode
ns
ns
ns
ns
(1)
1 MHz mode
91*
92*
93*
THD:STA START condition 100 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
—
After this period the first clock
pulse is generated
Hold time
400 kHz mode
(1)
1 MHz mode
TSU:STO STOP condition
Setup time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
—
(1)
1 MHz mode
THD:STO STOP condition
Hold time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
—
2
(1)
1 MHz mode
*
These parameters are characterized but not tested. For the value required by the I C specification, please refer to the PICmi-
TM
cro Mid-Range MCU Family Reference Manual (DS33023).
2
Maximum pin capacitance = 10 pF for all I C pins.
FIGURE 15-23:
MASTER SSP I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
91
92
107
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 15-4 for load conditions.
2002 Microchip Technology Inc.
DS41120B-page 177
PIC16C717/770/771
TABLE 15-22: MASTER SSP I2C BUS DATA REQUIREMENTS
Param.
No.
Symbol Characteristic
Min
Max
Units
Conditions
100*
THIGH
TLOW
TR
Clock high time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
ms
ms
ms
(1)
1 MHz mode
101*
102*
103*
90*
Clock low time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
ms
ms
ms
(1)
1 MHz mode
SDA and SCL
rise time
100 kHz mode
400 kHz mode
—
20 + 0.1Cb
—
1000
300
300
ns
ns
ns
Cb is specified to be from
10 to 400 pF
(1)
1 MHz mode
TF
SDA and SCL
fall time
100 kHz mode
400 kHz mode
—
20 + 0.1Cb
—
300
300
100
ns
ns
ns
Cb is specified to be from
10 to 400 pF
(1)
1 MHz mode
TSU:STA START condition
setup time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
ms
ms
ms
Only relevant for Repeated
START
condition
(1)
1 MHz mode
91*
THD:STA START condition
hold time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
ms
ms
ms
After this period the first clock
pulse is generated
(1)
1 MHz mode
106*
107*
92*
THD:DAT Data input
hold time
100 kHz mode
400 kHz mode
0
0
TBD
—
0.9
—
ns
ms
ns
(1)
1 MHz mode
TSU:DAT Data input
setup time
100 kHz mode
400 kHz mode
250
100
TBD
—
—
—
ns
ns
ns
Note 2
(1)
1 MHz mode
TSU:STO STOP condition
setup time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
ms
ms
ms
(1)
1 MHz mode
109*
110
TAA
TBUF
Cb
Output valid from
clock
100 kHz mode
400 kHz mode
—
—
—
3500
1000
—
ns
ns
ns
(1)
1 MHz mode
Bus free time
100 kHz mode
400 kHz mode
4.7 ‡
1.3 ‡
TBD‡
—
—
—
ms
ms
ms
Time the bus must be free
before a new transmission
can start
(1)
1 MHz mode
D102 ‡
Bus capacitive loading
—
400
pF
2
*
These parameters are characterized but not tested. For the value required by the I C specification, please refer to the
TM
PICmicro Mid-Range MCU Family Reference Manual (DS33023).
‡
These parameters are for design guidance only and are not tested, nor characterized.
2
Note 1: Maximum pin capacitance = 10 pF for all I C pins.
2
2
2: A Fast mode I C bus device can be used in a Standard mode I C bus system, but (TSU:DAT) ≥ 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
[(TR) + (TSU:DAT) = 1000 + 250 = 1250 ns], for 100 kHz mode, before the SCL line is released.
DS41120B-page 178
2002 Microchip Technology Inc.
PIC16C717/770/771
16.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples
and are provided for informational purposes only. The performance characteristics listed herein are not tested or
guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside
specified power supply range) and therefore outside the warranted range.
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ ) or
(mean - 3σ) respectively, where σ is a standard deviation, over the whole temperature range.
The FOSC IDD was determined using an external sinusoidal clock source with a peak amplitude ranging from VSS to VDD.
FIGURE 16-1:
MAXIMUM IDD VS. FOSC OVER VDD (HS MODE)
6.0
5.0
4.0
3.0
2.0
1.0
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
0.0
4.00
6.00
8.00
10.00
12.00
14.00
16.00
18.00
20.00
FOSC (MHz)
2002 Microchip Technology Inc.
DS41120B-page 179
PIC16C717/770/771
FIGURE 16-2:
TYPICAL IDD VS. FOSC OVER VDD (HS MODE)
6.0
5.0
4.0
3.0
2.0
1.0
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
0.0
4.00
6.00
8.00
10.00
12.00
14.00
16.00
18.00
20.00
FOSC (MHz)
FIGURE 16-3:
MAXIMUM IDD VS. FOSC OVER VDD (XT MODE)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
0.0
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
FOSC (MHz)
DS41120B-page 180
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 16-4:
TYPICAL IDD VS. FOSC OVER VDD (XT MODE)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
0.0
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
FOSC (MHz)
FIGURE 16-5:
MAXIMUM IDD VS. FOSC OVER VDD (LP MODE)
0.140
0.120
0.100
0.080
0.060
0.040
0.020
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
0.000
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
FOSC (MHz)
2002 Microchip Technology Inc.
DS41120B-page 181
PIC16C717/770/771
FIGURE 16-6:
TYPICAL IDD VS. FOSC OVER VDD (LP MODE)
0.120
5.5V
0.100
0.080
0.060
0.040
0.020
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
0.000
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
FOSC (MHz)
FIGURE 16-7:
MAXIMUM IDD VS. FOSC OVER VDD (EC MODE)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
0.0
0.00
2.00
4.00
6.00
8.00
10.00
12.00
14.00
16.00
18.00
20.00
FOSC (MHz)
DS41120B-page 182
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 16-8:
TYPICAL IDD VS. FOSC OVER VDD (EC MODE)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
0.0
0.00
2.00
4.00
6.00
8.00
10.00
12.00
14.00
16.00
18.00
20.00
FOSC (MHz)
FIGURE 16-9:
MAXIMUM IDD VS. FOSC OVER VDD (ER MODE)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
R = 38.3 kΩ
R = 100 kΩ
R = 200 kΩ
R = 499 kΩ
R = 1 MΩ
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2002 Microchip Technology Inc.
DS41120B-page 183
PIC16C717/770/771
FIGURE 16-10:
TYPICAL IDD VS. FOSC OVER VDD (ER MODE)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
R = 38.3 kΩ
R = 100 kΩ
R = 200 kΩ
R = 499 kΩ
R = 1 MΩ
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-11:
TYPICAL FOSC VS. VDD (ER MODE)
10.0
R = 38.3 kΩ
R= 100kΩ
1.0
R = 200 kΩ
R = 499 kΩ
R = 1 MΩ
0.1
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41120B-page 184
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 16-12:
MAXIMUM IDD VS. VDD (INTRC 37 kHZ MODE)
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
Max (-40 °C)
Typ (25 °C)
0.00
2.5
3.0
3.5
4.0
VDD (Volts)
4.5
5.0
5.5
FIGURE 16-13:
TYPICAL IDD VS. VDD (INTRC 37 kHZ MODE)
0.14
0.12
0.10
0.08
0.06
0.04
0.02
-40 °C
25 °C
85 °C
125 °C
0.00
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2002 Microchip Technology Inc.
DS41120B-page 185
PIC16C717/770/771
FIGURE 16-14:
INTERNAL RC FOSC VS. VDD OVER TEMPERATURE (37 kHZ)
0.060
0.055
0.050
0.045
0.040
0.035
0.030
0.025
Max (125 °C)
Typ (25 °C)
Min(-40° C)
0.020
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
FIGURE 16-15:
MAXIMUM AND TYPICAL IDD VS. VDD (INTRC 4 MHz MODE)
1.6
1.4
1.2
1.0
0.8
0.6
Max (-40 °C)
Typ (25 °C)
0.4
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (Volts)
DS41120B-page 186
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 16-16:
TYPICAL IDD VS. VDD (INTRC 4 MHz MODE)
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
125 °C
25 °C
85 °C
-40 °C
0.4
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (Volts)
FIGURE 16-17:
INTERNAL RC FOSC VS. VDD OVER TEMPERATURE (4 MHz)
4.15
4.10
4.05
4.00
3.95
3.90
3.85
Max (125 °C)
Typ (25 °C)
Min (-40 °C)
3.80
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2002 Microchip Technology Inc.
DS41120B-page 187
PIC16C717/770/771
FIGURE 16-18:
MAXIMUM IPD VS. VDD (-40°C TO +125°C)
10
+125°C
1
+85°C
+25°C
-40°C
0.1
0.01
2.5
3.0
3.5
4.0
4.5
5.0
5.5
DD
V
(V)
DS41120B-page 188
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 16-19:
TYPICAL AND MAXIMUM ∆IWDT VS. VDD (-40°C TO +125°C)
16.0
14.0
12.0
10.0
8.0
Max (-40°C)
Typ (25°C)
6.0
4.0
2.0
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2002 Microchip Technology Inc.
DS41120B-page 189
PIC16C717/770/771
FIGURE 16-20:
TYPICAL AND MAXIMUM ∆ITMR1 VS. VDD (32 KHZ, -40°C TO +125°C)
150.0
130.0
110.0
90.0
Max (-40°C)
Typ (25°C)
70.0
50.0
30.0
10.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-21:
TYPICAL AND MAXIMUM ∆IVRL VS. VDD (-40°C TO +125°C)
350.0
330.0
310.0
290.0
270.0
250.0
230.0
210.0
190.0
170.0
Max (125°C)
Max (85°C)
Typ (25°C)
150.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41120B-page 190
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 16-22:
TYPICAL AND MAXIMUM ∆IVRH VS. VDD (-40°C TO +125°C)
380.0
360.0
340.0
320.0
300.0
280.0
260.0
240.0
220.0
Max (125°C)
Max (85°C)
Typ (25°C)
200.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-23:
TYPICAL AND MAXIMUM ∆ILVD VS. VDD (-40°C TO +125°C) (LVD TRIP = 3.0V)
75.0
70.0
65.0
60.0
55.0
50.0
45.0
40.0
35.0
Max (125°C)
Max (85°C)
Typ (25°C)
30.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2002 Microchip Technology Inc.
DS41120B-page 191
PIC16C717/770/771
FIGURE 16-24:
TYPICAL AND MAXIMUM ∆ILVD VS. VDD (-40°C TO +125°C) (LVD TRIP = 4.5V)
75.0
70.0
65.0
60.0
55.0
50.0
45.0
40.0
35.0
Max (125°C)
Max (85°C)
Typ (25°C)
30.0
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
FIGURE 16-25:
TYPICAL AND MAXIMUM ∆IBOR VS. VDD (-40°C TO +125°C) (VBOR = 2.5V)
90.0
Max (125°C)
80.0
70.0
60.0
50.0
40.0
30.0
Typ (25°C)
Max (125°C)
Typ (25°C)
Device in RESET Indeterminate
2.5
Device inSSLEEP
2.0
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41120B-page 192
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 16-26:
TYPICAL AND MAXIMUM ∆IBOR VS. VDD (-40°C TO +125°C) (VBOR = 4.5V)
170.0
150.0
130.0
110.0
90.0
Max (125 °C)
Typ (25 °C)
70.0
Max (125 °C)
50.0
Typ (25C)
Device in
RESET
Device inSLEEP
Indeterminate
30.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-27:
VOL VS. IOL (-40°C TO +125°C, VDD = 3.0V)
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Max (125°C)
Typ (25°C)
Min (-40°C)
0.0
0.0
5.0
10.0
15.0
20.0
25.0
IOL (mA)
2002 Microchip Technology Inc.
DS41120B-page 193
PIC16C717/770/771
FIGURE 16-28:
VOL VS. IOL (-40°C TO +125°C, VDD = 5.0V)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Max (125°C)
Typ (25°C)
Min (-40°C)
0.0
0.0
5.0
10.0
15.0
20.0
25.0
IOL (mA)
FIGURE 16-29:
VOH VS. IOH (-40°C TO +125°C, VDD = 3.0V)
3.0
2.5
2.0
1.5
1.0
Max (-40°C)
Min (125°C)
Typ (25°C)
0.5
0.0
-2.0
-4.0
-6.0
-8.0
IOH (mA)
-10.0
-12.0
-14.0
-16.0
DS41120B-page 194
2002 Microchip Technology Inc.
PIC16C717/770/771
FIGURE 16-30:
VOH VS. IOH (-40°C TO +125°C, VDD = 5.0V)
5.0
4.5
4.0
3.5
3.0
2.5
Max (-40°C)
Typ (25°C)
Min (125°C)
2.0
0.0
-5.0
-10.0
-15.0
-20.0
-25.0
IOH (mA)
FIGURE 16-31:
MINIMUM AND MAXIMUM VIH/VIL VS. VDD (TTL INPUT,-40°C TO +125°C)
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
Max (-40°C)
Min (125°C)
0.8
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2002 Microchip Technology Inc.
DS41120B-page 195
PIC16C717/770/771
FIGURE 16-32:
MINIMUM AND MAXIMUM VIH/VIL VS. VDD (ST INPUT,-40°C TO +125°C)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Max High (125°C)
Min High (-40°C)
Max Low (-40°C)
Min Low (125°C)
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-33:
TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD VS. VDD (-40°C TO +125°C)
35.0
30.0
25.0
20.0
15.0
Max (125°C)
Max (85°C)
Typ (25°C)
Min (-40°C)
10.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41120B-page 196
2002 Microchip Technology Inc.
PIC16C717/770/771
17.0 PACKAGING INFORMATION
17.1 Package Marking Information
18-Lead PDIP
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
PIC16C717/P
9917017
18-Lead CERDIP Windowed
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
PIC16C717/JW
9905017
18-Lead SOIC
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16C717/SO
YYWWNNN
9910017
Example
20-Lead PDIP
PIC16C770/P
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
9917017
Legend: XX...X Customer specific information*
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
2002 Microchip Technology Inc.
DS41120B-page 197
PIC16C717/770/771
17.1 Package Marking Information (Cont’d)
20-Lead SSOP
Example
PIC16C770
XXXXXXXXXXX
XXXXXXXXXXX
20I/SS
YYWWNNN
9917017
20-Lead CERDIP Windowed
Example
PIC16C770/JW
9905017
XXXXXXXX
XXXXXXXX
YYWWNNN
20-Lead SOIC
Example
XXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXX
PIC16C771/SO
YYWWNNN
9910017
DS41120B-page 198
2002 Microchip Technology Inc.
PIC16C717/770/771
17.2 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
1
α
n
E
A2
L
A
c
A1
B1
β
p
B
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.890
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
22.61
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.898
.130
.012
.058
.018
.370
10
.325
.260
.905
.135
.015
.070
.022
.430
15
7.94
6.35
22.80
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
22.99
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-007
2002 Microchip Technology Inc.
DS41120B-page 199
PIC16C717/770/771
17.3 18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP)
E1
D
W2
2
1
n
W1
E
A2
A
c
L
A1
B1
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.100
.183
.160
.023
.313
.290
.900
.138
.010
.055
.019
.385
.140
.200
2.54
Top to Seating Plane
Ceramic Package Height
Standoff
A
.170
.195
4.32
3.94
4.64
4.06
0.57
7.94
7.37
22.86
3.49
0.25
1.40
0.47
9.78
3.56
5.08
4.95
A2
A1
.155
.015
.300
.285
.880
.125
.008
.050
.016
.345
.130
.190
.165
.030
.325
.295
.920
.150
.012
.060
.021
.425
.150
.210
4.19
0.76
8.26
7.49
23.37
3.81
0.30
1.52
0.53
10.80
3.81
5.33
0.38
7.62
7.24
22.35
3.18
0.20
1.27
0.41
8.76
3.30
4.83
Shoulder to Shoulder Width
Ceramic Pkg. Width
Overall Length
E
E1
D
L
Tip to Seating Plane
Lead Thickness
c
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Window Width
B1
B
eB
W1
W2
Window Length
*Controlling Parameter
JEDEC Equivalent: MO-036
Drawing No. C04-010
DS41120B-page 200
2002 Microchip Technology Inc.
PIC16C717/770/771
17.4 18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
p
E1
D
2
1
B
n
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.050
.099
.091
.008
.407
.295
.454
.020
.033
4
1.27
Overall Height
A
.093
.104
2.36
2.24
2.50
2.31
0.20
10.34
7.49
11.53
0.50
0.84
4
2.64
2.39
0.30
10.67
7.59
11.73
0.74
1.27
8
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.291
.446
.010
.016
0
.094
.012
.420
.299
.462
.029
.050
8
§
0.10
10.01
7.39
11.33
0.25
0.41
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.012
.020
15
0.23
0.36
0
0.27
0.42
12
0.30
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-051
2002 Microchip Technology Inc.
DS41120B-page 201
PIC16C717/770/771
17.5 20-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
α
n
1
E
A2
A
L
c
A1
β
B1
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
20
MAX
n
p
Number of Pins
Pitch
20
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.295
.240
1.025
.120
.008
.055
.014
.310
5
.145
3.68
0.38
7.49
6.10
26.04
3.05
0.20
1.40
0.36
7.87
5
.310
.250
1.033
.130
.012
.060
.018
.370
10
.325
.260
1.040
.140
.015
.065
.022
.430
15
7.87
6.35
26.24
3.30
0.29
1.52
0.46
9.40
10
8.26
6.60
26.42
3.56
0.38
1.65
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-019
DS41120B-page 202
2002 Microchip Technology Inc.
PIC16C717/770/771
17.6 20-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP)
DRAWING NOT AVAILABLE
2002 Microchip Technology Inc.
DS41120B-page 203
PIC16C717/770/771
17.7 20-Lead Plastic Small Outline (SO) – Wide, 300 mi (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
A1
L
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
20
20
.050
.099
.091
.008
.407
.295
.504
.020
.033
4
1.27
2.50
2.31
0.20
10.34
7.49
12.80
0.50
0.84
4
Overall Height
A
.093
.088
.004
.394
.291
.496
.010
.016
0
.104
2.36
2.64
Molded Package Thickness
Standoff
A2
A1
E
.094
.012
.420
.299
.512
.029
.050
8
2.24
0.10
10.01
7.39
12.60
0.25
0.41
0
2.39
0.30
10.67
7.59
13.00
0.74
1.27
8
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.013
.020
15
0.23
0.36
0
0.28
0.42
12
0.33
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-094
DS41120B-page 204
2002 Microchip Technology Inc.
PIC16C717/770/771
17.8 20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
E
E1
p
D
B
2
1
n
α
c
A2
A
φ
L
A1
β
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
20
MAX
n
p
Number of Pins
Pitch
20
.026
.073
.068
.006
.309
.207
.284
.030
.007
4
0.65
Overall Height
A
.068
.078
1.73
1.63
1.85
1.73
0.15
7.85
5.25
7.20
0.75
0.18
101.60
0.32
5
1.98
1.83
0.25
8.18
5.38
7.34
0.94
0.25
203.20
0.38
10
Molded Package Thickness
Standoff
A2
A1
E
.064
.002
.299
.201
.278
.022
.004
0
.072
.010
.322
.212
.289
.037
.010
8
§
0.05
7.59
5.11
7.06
0.56
0.10
0.00
0.25
0
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
c
Lead Thickness
Foot Angle
φ
Lead Width
B
α
β
.010
0
.013
5
.015
10
Mold Draft Angle Top
Mold Draft Angle Bottom
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No. C04-072
2002 Microchip Technology Inc.
DS41120B-page 205
PIC16C717/770/771
NOTES:
DS41120B-page 206
2002 Microchip Technology Inc.
PIC16C717/770/771
APPENDIX A: REVISION HISTORY
Version
Date
Revision Description
A
09/14/99
This is a new data sheet. However, the devices described in this data sheet are
the upgrades to the devices found in the PIC16C7X Data Sheet, DS30390E.
B
2/8/02
Electrical Characteristics tables completed and characteristics graphs added.
MSSP I2C (Section 9.2) rewritten. General minor changes and corrections.
2002 Microchip Technology Inc.
DS41120B-page 207
PIC16C717/770/771
APPENDIX B: DEVICE
DIFFERENCES
The differences between the devices in this data sheet
are listed in Table B-1.
TABLE B-1:
Difference
DEVICE DIFFERENCES
PIC16C717
PIC16C770
PIC16C771
Program Memory
A/D
2K
2K
4K
6 channels, 10 bits
Not available
6 channels, 12 bits
Available
6 channels, 12 bits
Available
Dedicated AVDD
and AVSS
Packages
18-pin PDIP, 18-pin windowed
CERDIP, 18-pin SOIC,
20-pin SSOP
20-pin PDIP, 20-pin
windowed CERDIP, 20-pin
SOIC, 20-pin SSOP
20-pin PDIP, 20-pin windowed
CERDIP, 20-pin SOIC,
20-pin SSOP
DS41120B-page 208
2002 Microchip Technology Inc.
PIC16C717/770/771
INDEX
A
C
A/D.................................................................................... 105
A/D Converter Enable (ADIE Bit)................................ 17
ADCON0 Register..................................................... 105
ADCON1 Register............................................. 105, 107
ADRES Register ....................................................... 105
Block Diagram........................................................... 109
Configuring Analog Port............................................ 108
Conversion time........................................................ 115
Conversions.............................................................. 111
converter characteristics................... 164, 165, 166, 170
Faster Conversion - Lower Resolution Tradeoff ....... 115
Internal Sampling Switch (Rss) Impedence.............. 113
Operation During Sleep ............................................ 116
Sampling Requirements............................................ 113
Sampling Time.......................................................... 113
Source Impedance.................................................... 113
Special Event Trigger (ECCP) .................................... 55
A/D Conversion Clock....................................................... 110
ACK..................................................................................... 77
Acknowledge Data bit, AKD................................................ 69
Acknowledge Sequence Enable bit, AKE ........................... 69
Acknowledge Status bit, AKS ............................................. 69
ACKSTAT ........................................................................... 87
ADCON0 Register............................................................. 105
ADCON1 Register..................................................... 105, 107
ADRES.............................................................................. 105
ADRES Register ........................................... 11, 12, 105, 116
AKD..................................................................................... 69
AKE..................................................................................... 69
AKS..................................................................................... 69
Analog-to-Digital Converter. See A/D
Capture (ECCP Module)..................................................... 54
Block Diagram ............................................................ 54
CCPR1H:CCPR1L Registers ..................................... 54
Changing Between Capture Prescalers ..................... 54
ECCP Pin Configuration............................................. 54
Software Interrupt....................................................... 54
Timer1 Mode Selection............................................... 54
Capture/Compare/PWM (ECCP)
Capture Mode. See Capture
Compare Mode. See Compare
PWM Mode. See PWM
CCP1CON .......................................................................... 13
CCP2CON .......................................................................... 13
CCPR1H Register......................................................... 11, 13
CCPR1L Register ............................................................... 13
CCPR2H Register............................................................... 13
CCPR2L Register ............................................................... 13
CKE .................................................................................... 66
CKP .................................................................................... 67
Clock Polarity Select bit, CKP............................................. 67
Code Examples
Loading the SSPBUF register .................................... 71
Code Protection........................................................ 117, 131
Compare (ECCP Module)................................................... 54
Block Diagram ............................................................ 55
CCPR1H:CCPR1L Registers ..................................... 54
ECCP Pin Configuration............................................. 54
Software Interrupt....................................................... 55
Special Event Trigger ........................................... 49, 55
Timer1 Mode Selection............................................... 54
Configuration Bits ............................................................. 117
Application Note AN578, "Use of the SSP Module
in the I2C Multi-Master Environment." ............................. 84
Architecture
D
D/A...................................................................................... 66
Data Memory ........................................................................ 9
Bank Select (RP Bits)............................................. 9, 14
General Purpose Registers .......................................... 9
Register File Map ....................................................... 10
Special Function Registers......................................... 11
Data/Address bit, D/A ......................................................... 66
DC Characteristics
PIC16C717/770/771................................. 150, 151, 153
Development Support....................................................... 141
Device Differences............................................................ 208
Direct Addressing ............................................................... 23
PIC16C717/PIC16C717 Block Diagram ....................... 5
PIC16C770/771/PIC16C770/771 Block Diagram ......... 6
Assembler
MPASM Assembler................................................... 141
B
Banking, Data Memory ................................................... 9, 14
Baud Rate Generator.......................................................... 84
BF ..................................................................... 66, 77, 87, 89
Block Diagrams
Baud Rate Generator.................................................. 84
2
I C Master Mode......................................................... 83
E
2
I C Module.................................................................. 76
Enhanced Capture/Compare/PWM (ECCP)
RA3:RA0 and RA5 Port Pins .................... 26, 28, 29, 35
CCP1
2
SSP (I C Mode) .......................................................... 76
CCPR1H Register .............................................. 53
CCPR1L Register............................................... 53
Enable (CCP1IE Bit)........................................... 17
Timer Resources ........................................................ 54
Errata.................................................................................... 3
External Power-on Reset Circuit....................................... 122
SSP (SPI Mode).......................................................... 70
BOR. See Brown-out Reset
BRG .................................................................................... 84
Brown-out Reset (BOR).................................... 117, 123, 124
Buffer Full bit, BF ................................................................ 77
Buffer Full Status bit, BF ..................................................... 66
Bus Arbitration .................................................................... 94
Bus Collision During a RESTART Condition....................... 97
Bus Collision During a Start Condition................................ 95
Bus Collision During a Stop Condition ................................ 98
Bus Collision Section .......................................................... 94
F
Firmware Instructions ....................................................... 133
FSR Register.......................................................... 11, 12, 13
G
GCE.................................................................................... 69
General Call Address Sequence ........................................ 82
General Call Address Support............................................ 82
General Call Enable bit, GCE............................................. 69
2002 Microchip Technology Inc.
DS41120B-page 209
PIC16C717/770/771
BTFSS ...................................................................... 136
CALL......................................................................... 136
CLRF ........................................................................ 136
CLRW ....................................................................... 136
CLRWDT .................................................................. 136
COMF ....................................................................... 137
DECF........................................................................ 137
DECFSZ ................................................................... 137
GOTO ....................................................................... 137
INCF ......................................................................... 137
INCFSZ..................................................................... 137
IORLW...................................................................... 138
IORWF...................................................................... 138
MOVF ....................................................................... 138
MOVLW .................................................................... 138
MOVWF.................................................................... 138
NOP.......................................................................... 138
RETFIE..................................................................... 139
RETLW ..................................................................... 139
RETURN................................................................... 139
RLF........................................................................... 139
RRF .......................................................................... 139
SLEEP ...................................................................... 139
SUBLW..................................................................... 140
SUBWF..................................................................... 140
SWAPF..................................................................... 140
XORLW .................................................................... 140
XORWF .................................................................... 140
Summary Table ........................................................ 134
INT Interrupt (RB0/INT). See Interrupt Sources
I
I/O Ports..............................................................................25
2
I C.......................................................................................76
2
I C Master Mode Reception................................................89
2
I C Master Mode Restart Condition ....................................86
2
I C Mode Selection .............................................................76
2
I C Module
Acknowledge Sequence timing...................................91
Addressing ..................................................................77
Baud Rate Generator..................................................84
Block Diagram.............................................................83
BRG Block Diagram....................................................84
BRG Reset due to SDA Collision................................96
BRG Timing ................................................................85
Bus Arbitration ............................................................94
Bus Collision ...............................................................94
Acknowledge.......................................................94
Restart Condition ................................................97
Restart Condition Timing (Case1).......................97
Restart Condition Timing (Case2).......................97
Start Condition ....................................................95
Start Condition Timing .................................. 95, 96
Stop Condition ....................................................98
Stop Condition Timing (Case1)...........................98
Stop Condition Timing (Case2)...........................98
Transmit Timing ..................................................94
Bus Collision timing.....................................................94
Clock Arbitration..........................................................93
Clock Arbitration Timing (Master Transmit).................93
Conditions to not give ACK Pulse ...............................77
General Call Address Support ....................................82
Master Mode...............................................................83
Master Mode 7-bit Reception timing ...........................90
Master Mode Operation ..............................................84
Master Mode Start Condition ......................................85
Master Mode Transmission.........................................87
Master Mode Transmit Sequence...............................84
Multi-Master Communication ......................................94
Multi-master Mode ......................................................84
Operation ....................................................................76
Repeat Start Condition timing .....................................86
Slave Mode.................................................................76
Slave Reception..........................................................78
Slave Transmission.....................................................80
SSPBUF......................................................................76
Stop Condition Receive or Transmit timing.................92
Stop Condition timing..................................................92
Waveforms for 7-bit Reception ...................................78
Waveforms for 7-bit Transmission ..............................80
INTCON.............................................................................. 13
INTCON Register................................................................ 16
GIE Bit ........................................................................ 16
INTE Bit ...................................................................... 16
INTF Bit ...................................................................... 16
PEIE Bit ...................................................................... 16
RBIE Bit ...................................................................... 16
RBIF Bit ................................................................ 16, 33
T0IE Bit....................................................................... 16
T0IF Bit....................................................................... 16
2
Inter-Integrated Circuit (I C) ............................................... 65
internal sampling switch (Rss) impedence ....................... 113
Interrupt Sources ...................................................... 117, 127
Block Diagram .......................................................... 127
Capture Complete (ECCP) ......................................... 54
Compare Complete (ECCP) ....................................... 55
RB0/INT Pin, External............................................... 128
TMR0 Overflow................................................... 46, 128
TMR1 Overflow..................................................... 47, 49
TMR2 to PR2 Match ................................................... 52
TMR2 to PR2 Match (PWM)................................. 51, 56
Interrupts
2
I C Slave Mode...................................................................76
ICEPIC In-Circuit Emulator ...............................................142
ID Locations ..............................................................117, 131
In-Circuit Serial Programming (ICSP) ....................... 117, 131
INDF....................................................................................13
INDF Register ............................................................... 11, 12
Indirect Addressing .............................................................23
FSR Register ................................................................9
Instruction Format .............................................................133
Instruction Set ...................................................................133
ADDLW .....................................................................135
ADDWF.....................................................................135
ANDLW .....................................................................135
ANDWF.....................................................................135
BCF...........................................................................135
BSF...........................................................................135
BTFSC ......................................................................136
Synchronous Serial Port Interrupt............................... 18
Interrupts, Context Saving During..................................... 128
Interrupts, Enable Bits
A/D Converter Enable (ADIE Bit)................................ 17
CCP1 Enable (CCP1IE Bit) .................................. 17, 54
Global Interrupt Enable (GIE Bit)........................ 16, 127
Interrupt-on-Change (RB7:RB4) Enable
(RBIE Bit)........................................................ 16, 128
Peripheral Interrupt Enable (PEIE Bit)........................ 16
PSP Read/Write Enable (PSPIE Bit) .......................... 17
RB0/INT Enable (INTE Bit)......................................... 16
SSP Enable (SSPIE Bit) ............................................. 17
TMR0 Overflow Enable (T0IE Bit) .............................. 16
TMR1 Overflow Enable (TMR1IE Bit)......................... 17
DS41120B-page 210
2002 Microchip Technology Inc.
PIC16C717/770/771
TMR2 to PR2 Match Enable (TMR2IE Bit) ................. 17
USART Receive Enable (RCIE Bit) ...................... 17, 18
Interrupts, Flag Bits
PICDEM 3 Low Cost PIC16CXXX
Demonstration Board.................................................... 144
PICSTART Plus Entry Level
CCP1 Flag (CCP1IF Bit)............................................. 54
Interrupt on Change (RB7:RB4) Flag
(RBIF Bit) .................................................. 16, 33, 128
RB0/INT Flag (INTF Bit).............................................. 16
TMR0 Overflow Flag (T0IF Bit)........................... 16, 128
INTRC Mode ..................................................................... 120
Development Programmer............................................ 143
PIE1 Register ..................................................................... 17
ADIE Bit...................................................................... 17
CCP1IE Bit ................................................................. 17
PSPIE Bit.................................................................... 17
RCIE Bit................................................................ 17, 18
SSPIE Bit.................................................................... 17
TMR1IE Bit ................................................................. 17
TMR2IE Bit ................................................................. 17
PIE2 Register ..................................................................... 19
Pinout Descriptions
K
KEELOQ Evaluation and Programming Tools .................... 144
L
LVDCON ........................................................................... 101
PIC16C770................................................................... 7
PIC16C770/771............................................................ 7
PIC16C771................................................................... 7
PIR1 Register ..................................................................... 18
PIR2 Register ..................................................................... 20
Pointer, FSR ....................................................................... 23
POR. See Power-on Reset
PORTA ............................................................................... 13
Initialization................................................................. 26
PORTA Register......................................................... 25
TRISA Register........................................................... 25
PORTA Register......................................................... 11, 116
PORTB ............................................................................... 13
Initialization................................................................. 33
PORTB Register......................................................... 33
Pull-up Enable (RBPU Bit).......................................... 15
RB0/INT Edge Select (INTEDG Bit) ........................... 15
RB0/INT Pin, External .............................................. 128
RB7:RB4 Interrupt on Change.................................. 128
RB7:RB4 Interrupt on Change Enable
(RBIE Bit)........................................................ 16, 128
RB7:RB4 Interrupt on Change Flag
(RBIF Bit).................................................. 16, 33, 128
TRISB Register........................................................... 33
PORTB Register......................................................... 11, 116
Postscaler, Timer2
Select (TOUTPS Bits)................................................. 51
Postscaler, WDT................................................................. 45
Assignment (PSA Bit)........................................... 15, 45
Block Diagram ............................................................ 46
Rate Select (PS Bits)............................................ 15, 45
Switching Between Timer0 and WDT......................... 46
Power-down Mode. See SLEEP
Power-on Reset (POR)..................... 117, 121, 122, 123, 124
Oscillator Start-up Timer (OST)........................ 117, 122
Power Control (PCON) Register............................... 123
Power-down (PD Bit).................................................. 14
Power-on Reset Circuit, External ............................. 122
Power-up Timer (PWRT).................................. 117, 122
Time-out (TO Bit)........................................................ 14
Time-out Sequence .................................................. 123
Time-out Sequence on Power-up..................... 125, 126
PR2 Register ...................................................................... 12
Prescaler, Capture.............................................................. 54
Prescaler, Timer0 ............................................................... 45
Assignment (PSA Bit)........................................... 15, 45
Block Diagram ............................................................ 46
Rate Select (PS Bits)............................................ 15, 45
Switching Between Timer0 and WDT......................... 46
Prescaler, Timer1 ............................................................... 48
Select (T1CKPS Bits) ................................................. 47
M
Master Clear (MCLR)
MCLR Reset, Normal Operation............... 121, 123, 124
MCLR Reset, SLEEP................................ 121, 123, 124
Memory Organization
Data Memory ................................................................ 9
Program Memory .......................................................... 9
MPLAB C17 and MPLAB C18 C Compilers...................... 141
MPLAB ICD In-Circuit Debugger ...................................... 143
MPLAB ICE High Performance Universal In-Circuit
Emulator with MPLAB IDE............................................ 142
MPLAB Integrated Development Environment Software .. 141
MPLINK Object Linker/MPLIB Object Librarian ................ 142
Multi-Master Communication .............................................. 94
Multi-Master Mode .............................................................. 84
O
OPCODE Field Descriptions............................................. 133
OPTION_REG Register ...................................................... 15
INTEDG Bit ................................................................. 15
PS Bits .................................................................. 15, 45
PSA Bit.................................................................. 15, 45
RBPU Bit..................................................................... 15
T0CS Bit................................................................ 15, 45
T0SE Bit................................................................ 15, 45
Oscillator Configuration..................................................... 119
CLKOUT ................................................................... 120
Dual Speed Operation for ER and
INTRC Modes ....................................................... 120
EC..................................................................... 119, 123
ER..................................................................... 119, 123
ER Mode................................................................... 120
HS..................................................................... 119, 123
INTRC............................................................... 119, 123
LP...................................................................... 119, 123
XT ..................................................................... 119, 123
Oscillator, Timer1.......................................................... 47, 49
Oscillator, WDT................................................................. 129
P
P.......................................................................................... 66
Packaging ......................................................................... 197
Paging, Program Memory............................................... 9, 22
Parallel Slave Port (PSP)
Read/Write Enable (PSPIE Bit)................................... 17
PCL Register................................................................. 11, 12
PCLATH Register ................................................... 11, 12, 13
PCON Register ........................................................... 21, 123
PICDEM 1 Low Cost PICmicro
Demonstration Board .................................................... 143
PICDEM 17 Demonstration Board .................................... 144
PICDEM 2 Low Cost PIC16CXX
Demonstration Board .................................................... 143
2002 Microchip Technology Inc.
DS41120B-page 211
PIC16C717/770/771
Prescaler, Timer2................................................................57
Select (T2CKPS Bits)..................................................51
PRO MATE II Universal Device Programmer ...................143
Program Counter
S
S ......................................................................................... 66
SAE..................................................................................... 69
SCK .................................................................................... 70
SCL..................................................................................... 76
SDA .................................................................................... 76
SDI...................................................................................... 70
SDO.................................................................................... 70
Serial Data In, SDI.............................................................. 70
Serial Data Out, SDO ......................................................... 70
Slave Select Synchronization ............................................. 73
Slave Select, SS................................................................. 70
SLEEP .............................................................. 117, 121, 130
SMP.................................................................................... 66
Software Simulator (MPLAB SIM) .................................... 142
SPE..................................................................................... 69
Special Event Trigger. See Compare
PCL Register...............................................................22
PCLATH Register ............................................... 22, 128
Reset Conditions.......................................................123
Program Memory ..................................................................9
Interrupt Vector .............................................................9
Paging.....................................................................9, 22
Program Memory Map ..................................................9
READ (PMR)...............................................................43
Reset Vector .................................................................9
Program Verification..........................................................131
Programmable Brown-out Reset (PBOR) ................. 121, 122
Programming, Device Instructions ....................................133
PWM (CCP Module)
TMR2 to PR2 Match ...................................................51
TMR2 to PR2 Match Enable (TMR2IE Bit) .................17
PWM (ECCP Module) .........................................................56
Block Diagram.............................................................56
CCPR1H:CCPR1L Registers......................................56
Duty Cycle...................................................................57
Output Diagram...........................................................57
Period..........................................................................56
TMR2 to PR2 Match ...................................................56
Special Features of the CPU ............................................ 117
Special Function Registers................................................. 11
PIC16C717 ................................................................. 11
PIC16C717/770/771 ................................................... 11
PIC16C770 ................................................................. 11
PIC16C771 ................................................................. 11
Speed, Operating.................................................................. 1
SPI
Master Mode............................................................... 72
Serial Clock................................................................. 70
Serial Data In.............................................................. 70
Serial Data Out ........................................................... 70
Serial Peripheral Interface (SPI)................................. 65
Slave Select................................................................ 70
SPI clock..................................................................... 72
SPI Mode.................................................................... 70
SPI Clock Edge Select, CKE .............................................. 66
SPI Data Input Sample Phase Select, SMP ....................... 66
SPI Master/Slave Connection............................................. 71
SPI Module
Q
Q Clock ...............................................................................57
R
R/W .....................................................................................66
R/W bit ................................................................................80
R/W bit ................................................................................78
R/W bit ................................................................................77
RAM. See Data Memory
RCE,Receive Enable bit, RCE............................................69
RCREG ...............................................................................13
RCSTA Register..................................................................13
Read/Write bit, R/W ............................................................66
Receive Overflow Indicator bit, SSPOV..............................67
REFCON...........................................................................102
Register File..........................................................................9
Register File Map................................................................10
Registers
FSR Summary ............................................................13
INDF Summary ...........................................................13
INTCON Summary......................................................13
PCL Summary.............................................................13
PCLATH Summary .....................................................13
PORTB Summary .......................................................13
SSPSTAT............................................................ 66, 101
STATUS Summary .....................................................13
TMR0 Summary..........................................................13
TRISB Summary.........................................................13
Reset......................................................................... 117, 121
Block Diagram...........................................................121
Brown-out Reset (BOR). See Brown-out Reset (BOR)
MCLR Reset. See MCLR
Master/Slave Connection............................................ 71
Slave Mode................................................................. 73
Slave Select Synchronization ..................................... 73
Slave Synch Timnig.................................................... 73
SS....................................................................................... 70
SSP..................................................................................... 65
Block Diagram (SPI Mode) ......................................... 70
Enable (SSPIE Bit) ..................................................... 17
SPI Mode.................................................................... 70
SSPADD..................................................................... 77
SSPBUF ............................................................... 72, 76
SSPCON .................................................................... 67
SSPCON2 ............................................................ 69, 70
SSPSR ................................................................. 72, 77
SSPSTAT ..................................................... 66, 76, 101
TMR2 Output for Clock Shift................................. 51, 52
2
SSP I C
2
SSP I C Operation ..................................................... 76
SSP Module
SPI Master Mode........................................................ 72
SPI Master./Slave Connection.................................... 71
SPI Slave Mode.......................................................... 73
SSPCON1 Register.................................................... 76
SSP Overflow Detect bit, SSPOV....................................... 77
SSPADD Register............................................................... 12
SSPBUF ................................................................. 13, 76, 77
SSPBUF Register............................................................... 11
SSPCON............................................................................. 67
SSPCON Register .............................................................. 11
Power-on Reset (POR). See Power-on Reset (POR)
Reset Conditions for All Registers ............................124
Reset Conditions for PCON Register........................123
Reset Conditions for Program Counter.....................123
Reset Conditions for STATUS Register....................123
WDT Reset. See Watchdog Timer (WDT)
Restart Condition Enabled bit, RSE....................................69
Revision History ................................................................207
RSE.....................................................................................69
DS41120B-page 212
2002 Microchip Technology Inc.
PIC16C717/770/771
SSPCON1........................................................................... 76
SSPCON2..................................................................... 69, 70
SSPEN................................................................................ 67
SSPIF............................................................................ 18, 78
SSPM.................................................................................. 68
SSPOV.................................................................... 67, 77, 89
SSPSTAT.............................................................. 66, 76, 101
SSPSTAT Register ............................................................. 12
Stack................................................................................... 22
Start bit (S).......................................................................... 66
Start Condition Enabled bit, SAE ........................................ 69
STATUS Register ................................................. 14, 15, 128
C Bit ............................................................................ 14
DC Bit.................................................................... 14, 15
IRP Bit......................................................................... 14
PD Bit.......................................................................... 14
RP Bits........................................................................ 14
TO Bit.......................................................................... 14
Z Bit............................................................................. 14
Status Register ................................................................... 14
Stop bit (P) .......................................................................... 66
Stop Condition Enable bit ................................................... 69
Synchronous Serial Port ..................................................... 65
Synchronous Serial Port Enable bit, SSPEN ...................... 67
Synchronous Serial Port Interrupt....................................... 18
Synchronous Serial Port Mode Select bits, SSPM ............. 68
Timer2
Block Diagram ............................................................ 52
Postscaler. See Postscaler, Timer2
PR2 Register ........................................................ 51, 56
Prescaler. See Prescaler, Timer2
SSP Clock Shift .................................................... 51, 52
T2CON Register......................................................... 51
TMR2 Register ........................................................... 51
TMR2 to PR2 Match Enable (TMR2IE Bit)................. 17
TMR2 to PR2 Match Interrupt......................... 51, 52, 56
Timing Diagrams
Acknowledge Sequence Timing ................................. 91
Baud Rate Generator with Clock Arbitration............... 85
BRG Reset Due to SDA Collision............................... 96
Brown-out Reset....................................................... 159
Bus Collision
Start Condition Timing........................................ 95
Bus Collision During a Restart Condition
(Case 1).................................................................. 97
Bus Collision During a Restart Condition
(Case2)................................................................... 97
Bus Collision During a Start Condition
(SCL = 0)................................................................ 96
Bus Collision During a Stop Condition........................ 98
Bus Collision for Transmit and Acknowledge ............. 94
Capture/Compare/PWM ........................................... 161
CLKOUT and I/O ...................................................... 157
External Clock Timing............................................... 157
T
T1CON................................................................................ 13
T1CON Register ........................................................... 13, 47
T1CKPS Bits............................................................... 47
T1OSCEN Bit.............................................................. 47
T1SYNC Bit................................................................. 47
TMR1CS Bit................................................................ 47
TMR1ON Bit................................................................ 47
T2CON Register ........................................................... 13, 51
T2CKPS Bits............................................................... 51
TMR2ON Bit................................................................ 51
TOUTPS Bits .............................................................. 51
Timer0
2
I C Bus Data............................................................. 177
2
I C Master Mode First Start bit timing ........................ 85
2
I C Master Mode Reception timing............................. 90
2
I C Master Mode Transmission timing ....................... 88
Master Mode Transmit Clock Arbitration .................... 93
Power-up Timer........................................................ 159
Repeat Start Condition ............................................... 86
Reset ........................................................................ 159
Slave Synchronization................................................ 73
Start-up Timer........................................................... 159
Stop Condition Receive or Transmit........................... 92
Time-out Sequence on Power-up..................... 125, 126
Timer0 ...................................................................... 160
Timer1 ...................................................................... 160
Wake-up from SLEEP via Interrupt .......................... 131
Watchdog Timer ....................................................... 159
TMR0.................................................................................. 13
TMR0 Register.................................................................... 11
TMR1H ............................................................................... 13
TMR1H Register................................................................. 11
TMR1L................................................................................ 13
TMR1L Register.................................................................. 11
TMR2.................................................................................. 13
TMR2 Register.................................................................... 11
TRISA Register........................................................... 12, 116
TRISB Register........................................................... 12, 116
TXREG ............................................................................... 13
Block Diagram............................................................. 45
Clock Source Edge Select (T0SE Bit)................... 15, 45
Clock Source Select (T0CS Bit)............................ 15, 45
Overflow Enable (T0IE Bit) ......................................... 16
Overflow Flag (T0IF Bit)...................................... 16, 128
Overflow Interrupt ............................................... 46, 128
Prescaler. See Prescaler, Timer0
Timer1................................................................................. 47
Block Diagram............................................................. 48
Capacitor Selection..................................................... 49
Clock Source Select (TMR1CS Bit) ............................ 47
External Clock Input Sync (T1SYNC Bit).................... 47
Module On/Off (TMR1ON Bit)..................................... 47
Oscillator............................................................... 47, 49
Oscillator Enable (T1OSCEN Bit) ............................... 47
Overflow Enable (TMR1IE Bit).................................... 17
Overflow Interrupt ................................................. 47, 49
Prescaler. See Prescaler, Timer1
U
Update Address, UA........................................................... 66
Special Event Trigger (ECCP) .............................. 49, 55
T1CON Register ......................................................... 47
TMR1H Register ......................................................... 47
TMR1L Register.......................................................... 47
USART
Receive Enable (RCIE Bit) ................................... 17, 18
2002 Microchip Technology Inc.
DS41120B-page 213
PIC16C717/770/771
W
W Register ........................................................................128
Wake-up from SLEEP............................................... 117, 130
Interrupts........................................................... 123, 124
MCLR Reset .............................................................124
Timing Diagram.........................................................131
WDT Reset ...............................................................124
Watchdog Timer (WDT) ............................................ 117, 129
Block Diagram...........................................................129
Enable (WDTE Bit)....................................................129
Postscaler. See Postscaler, WDT
Programming Considerations ...................................129
RC Oscillator.............................................................129
Time-out Period ........................................................129
WDT Reset, Normal Operation .................121, 123, 124
WDT Reset, SLEEP.......................................... 123, 124
Waveform for General Call Address Sequence ..................82
WCOL ...................................................67, 85, 87, 89, 91, 92
WCOL Status Flag ..............................................................85
Write Collision Detect bit, WCOL ........................................67
WWW, On-Line Support........................................................3
DS41120B-page 214
2002 Microchip Technology Inc.
PIC16C717/770/771
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PIC16C717/770/771
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Advance Information
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PIC16C717/770/771
PIC16C717/770/771 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
a) PIC16C771/P Commercial Temp.,
PDIP package, normal VDD limits
Temperature Package
Range
Pattern
Device
PIC16C771
:
VDD range 4.0V to 5.5V
PIC16C771T : VDD range 4.0V to 5.5V (Tape/Reel)
PIC16LC771 : VDD range 2.5V to 5.5V
PIC16LC771T: VDD range 2.5V to 5.5V (Tape/Reel)
Temperature Range:
Package
-
=
=
=
0°C to +70°C
I
-40°C to +85°C
-40°C to +125°C
E
JW
SO
P
=
=
=
=
Windowed CERDIP
SOIC
PDIP
SSOP
SS
Pattern
QTP, SQTP, Code or Special Requirements. Blank for OTP
and Windowed devices.
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type.
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Addison, TX 75001
Tel: 972-818-7423 Fax: 972-818-2924
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Denmark
Microchip Technology Nordic ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Kokomo
France
2767 S. Albright Road
Kokomo, Indiana 46902
Tel: 765-864-8360 Fax: 765-864-8387
Los Angeles
Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
Germany
New York
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Microchip Technology GmbH
Gustav-Heinemann Ring 125
D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Tel: 631-273-5305 Fax: 631-273-5335
San Jose
Hong Kong
Italy
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Microchip Technology Hongkong Ltd.
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699 Fax: 905-673-6509
India
Microchip Technology Inc.
India Liaison Office
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
01/18/02
DS41120B-page 218
2002 Microchip Technology Inc.
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