PIC16LF1776T-I/MX [MICROCHIP]
IC MCU 8BIT 14KB FLASH 28UQFN;型号: | PIC16LF1776T-I/MX |
厂家: | MICROCHIP |
描述: | IC MCU 8BIT 14KB FLASH 28UQFN 时钟 外围集成电路 |
文件: | 总16页 (文件大小:135K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PIC16(L)F1773/6/7/8/9
28/40/44-Pin, 8-Bit Flash Microcontroller Product Brief
Description
PIC16(L)F177X microcontrollers feature a high level of integration of intelligent analog and digital peripherals for a wide
range of applications, such as lighting, power supplies, battery charging, motor control and other general purpose
applications. These devices deliver multiple op amps, 5-/10-bit DACs, high-speed comparators, 10-bit ADC, 10-/16-bit
PWMs, programmable ramp generator (PRG) and other peripherals that can be connected internally to create closed
loop systems without using pins or PCB area. The 10-/16-bit PWMs, digital signal modulators and tri-state output op
amp can be used together to create a LED dimming engine for lighting applications. The peripheral pin select (PPS)
functionality provides flexibility, eases PCB layout and peripheral utilization by allowing digital peripheral pin mapping
to an I/O.
Core Features
eXtreme Low-Power (XLP) Features
• Sleep mode: 50 nA @ 1.8V, typical
• Watchdog Timer: 500 nA @ 1.8V, typical
• Secondary Oscillator: 500 nA @ 32 kHz
• Operating Current:
• C Compiler Optimized RISC Architecture
• Only 49 Instructions
• Operating Speed:
- DC – 32 MHz clock input
- 125 ns minimum instruction cycle
• Interrupt Capability
-
-
8 uA @ 31 kHz, 1.8V, typical
32 uA/MHz @ 1.8V, typical
• 16-Level Deep Hardware Stack
• Five 8-Bit Timers
Intelligent Analog Peripherals
• Three 16-Bit Timers
• 10-Bit Analog-to-Digital Converter (ADC):
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRT)
• Brown-out Reset (BOR) with Selectable Trip Point
• Extend Watchdog Timer (EWDT):
- Low-power 31 kHz WDT
- Up to 28 external channels
- Conversion available during Sleep
• Up to Four Operational Amplifiers (OPA):
- Selectable internal and external channels
- Tri-state output
- Software selectable pre-scaler
- Software selectable enable
- Part of LED dimming engine
- Selectable internal and external channels
• Up to Eight High-Speed Comparators (HS Comp):
- Up to nine external inverting inputs
- Up to 12 external noninverting inputs
- Fixed voltage reference at inverting and
noninverting input(s)
- Comparator outputs externally accessible
• Digital-to-Analog Converters (DAC):
- Up to four 10-bit resolution DACs
- 10-bit resolution, rail-to-rail
Memory
• Up to 28 Kbytes Program Flash Memory (PFM)
• Up to 2 Kbytes Data RAM
• Direct, Indirect and Relative Addressing modes
• High-Endurance Flash (HEF):
- 128B of nonvolatile data storage
- 100K Erase/Write cycles
- Conversion during Sleep
- Internal connections to ADCs and HS
Comparators
Operating Characteristics
• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF1773/6/7/8/9)
- 2.3V to 5.5V (PIC16F1773/6/7/8/9)
• Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
• Voltage Reference:
- Fixed Voltage Reference (FVR)
- 1.024V, 2.048V and 4.096V output levels
• Zero-Cross Detector (ZCD):
- Detect high-voltage AC signal
• Up to Four Programmable Ramp Generators
(PRG):
- Slope compensation
- Ramp generation
• Two High-Current Drive I/Os:
- Up to 100 mA sink or source @ 5V
2015 Microchip Technology Inc.
Advance Information
DS40001790A-page 1
PIC16(L)F1773/6/7/8/9
• Peripheral Pin Select (PPS):
- I/O remapping of digital peripherals
• Serial Communications:
- Enhanced USART (EUSART)
- SPI, I2C™, RS-232, RS-485, LIN compatible
- Auto-Baud Detect, auto-wake-up on start
• Up to 38 I/O Pins:
- Individually programmable pull-ups
- Slew rate control
- Interrupt-on-change with edge-select
Digital Peripherals
• Up to Four Configurable Logic Cells (CLC):
- Integrated combinational and state logic
• Up to Four Complementary Output Generators
(COG):
- Push-pull, Full-Bridge and Steering modes
• Up to Four Capture/Compare/PWM (CCP)
Modules
• Pulse-Width Modulator (PWM):
- Up to four 16-bit PWMs
- Independent timers
Clocking Structure
- Multiple output modes (edge-, center-aligned,
set and toggle on register match)
- User settings for phase, duty cycle, period,
offset and polarity
• Precision Internal Oscillator:
- ±1% at calibration
- Selectable frequency range 32 MHz to
31 kHz
- 16-bit timer capability
- Up to four 10-bit PWMs
• 31 kHz Low-Power Internal Oscillator
• 4x Phase-Locked Loop (PLL) for up to 32 MHz
Internal Operation
• External Oscillator Block with Three External
Clock modes up to 32 MHz
• Up to Four Data Signal Modulators (DSM):
- Modulates a carrier signal with a digital data
to create custom carrier synchronized output
waveforms
- Part of LED dimming engine
TABLE 1:
PIC16(L)F1773/6/7/8/9 FAMILY TYPES
Device
PIC16(L)F1773 (A) 7K
PIC16(L)F1776 (A) 14K
PIC16(L)F1777 (B) 14K
4K 128 512 25 5/3
8K 128 1K 25 5/3
8K 128 1K 36 5/3
6
6
8
6
8
17 3/3
17 3/3
28 4/4
17 3/3
28 4/4
3
3
4
3
4
3/3
3/3
4/4
3/3
4/4
3
3
4
3
4
4
4
4
4
4
3
3
4
3
4
1
1
1
1
1
3
3
4
3
4
3
3
4
3
4
2
2
2
2
2
Y
Y
Y
Y
Y
1
1
1
1
1
1
1
1
1
1
I
I
I
I
I
PIC16(L)F1778 (B) 28K 16K 128 2K 25 5/3
PIC16(L)F1779 (B) 28K 16K 128 2K 36 5/3
Note 1: One pin is input-only.
2: I – Debugging integrated on chip
Data Sheet Index:
A: Future Release
B: Future Release
PIC16(L)F1773/6 Data Sheet, 24-Pin, 8-bit Flash Microcontrollers
PIC16(L)F1777/8/9 Data Sheet, 24/40/44-Pin, 8-bit Flash Microcontrollers
Note:
For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
DS40001790A-page 2
Advance Information
2015 Microchip Technology Inc.
PIC16(L)F1773/6/7/8/9
TABLE 2:
PACKAGES
Packages
SPDIP
PDIP
SOIC
SSOP
UQFN
TQFP
PIC16(L)F1773
PIC16(L)F1776
PIC16(L)F1777
PIC16(L)F1778
PIC16(L)F1779
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Note:
Pin details are subject to change.
2015 Microchip Technology Inc.
Advance Information
DS40001790A-page 3
PIC16(L)F1773/6/7/8/9
PIN DIAGRAMS
FIGURE 1:
28-PIN SPDIP, SOIC, SSOP
RB7/ICSPDAT
RB6/ICSPCLK
RB5
28
27
26
25
1
2
3
4
5
6
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RA4
RB4
RB3
RB2
24
23
22
21
RB1
RB0
RA5
VSS
7
8
9
20 VDD
19 VSS
RA7
RA6
RC0
RC1
RC2
10
11
RC7
18
17 RC6
12
13
14
RC5
RC4
16
15
RC3
Note:
See Table 3 for location of all peripheral functions.
FIGURE 2:
28-PIN UQFN (6x6x0.5 mm)
28 27 26
24 23 22
25
RB3
RA2
RA3
RA4
RA5
VSS
1
2
3
4
5
6
7
21
20
19
18
RB2
RB1
RB0
PIC16(L)F1773/6/8
17 VDD
RA7
RA6
VSS
16
15
RC7
8
9 10 11 12 13 14
Note:
See Table 3 for location of all peripheral functions.
DS40001790A-page 4
Advance Information
2015 Microchip Technology Inc.
PIC16(L)F1773/6/7/8/9
FIGURE 3:
40-PIN PDIP
RB7/ICSPDAT
RB6/ICSPCLK
VPP/MCLR/RE3
40
39
1
2
3
4
5
6
RA0
RA1
RA2
RA3
RA4
38 RB5
37
RB4
36
35
RB3
RB2
RB1
RB0
VDD
RA5
RE0
34
33
32
31
30
7
8
9
RE1
RE2
VDD
VSS
VSS
10
11
RD7
RD6
29
12
RA7
RA6
RD5
RD4
RC7
28
27
26
25
13
14
15
16
RC0
RC1
RC2
RC3
RD0
RD1
RC6
RC5
24
23
17
18
RC4
RD3
RD2
22
21
19
20
Note:
See Table 4 for location of all peripheral functions.
FIGURE 4:
40-PIN UQFN (5x5x0.5 mm)
33 32
34
31
30
38
37 36 35
40 39
RC7
RD4
1
2
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RD5
3
29
28
27
26
25
24
23
22
21
4
RD6
RD7
5
VSS
VDD
RB0
RB1
RB2
PIC16(L)F1777/9
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20
Note:
See Table 4 for location of all peripheral functions.
2015 Microchip Technology Inc.
Advance Information
DS40001790A-page 5
PIC16(L)F1773/6/7/8/9
FIGURE 5:
44-PIN TQFP (4x4 mm)
41 40 39
38
37 36 35 34
44 43
42
RC7
RD4
33
32
31
30
NC
1
2
3
4
RC0
RA6
RA7
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RB3
VSS
VDD
RE2
RE1
RE0
RA5
RA4
29
28
5
6
PIC16(L)F1777/9
27
26
25
24
23
7
8
9
10
11
12 1314
15 16 17 18 19 20 21 22
Note:
See Table 4 for location of all peripheral functions.
DS40001790A-page 6
Advance Information
2015 Microchip Technology Inc.
PIN ALLOCATION TABLES
TABLE 3:
28-PIN ALLOCATION TABLE (PIC16(L)F1773/6/8)
(1)
RA0
RA1
2
3
27
28
AN0
AN1
—
—
—
—
—
C1IN0-
C2IN0-
C3IN0-
C4IN0-
C5IN0-
C6IN0-
—
—
—
—
—
—
—
—
—
—
—
CLCIN1
CLCIN2
—
—
—
—
—
—
IOC
IOC
—
—
—
—
—
—
(1)
OPA1OUT
OPA2IN1+
OPA2IN1-
C1IN1-
C2IN1-
C3IN1-
C4IN1-
PRG1IN0
PRG2IN1
RA2
RA3
RA4
4
5
6
1
2
3
AN2
VREF-
DAC1REF0-
DAC2REF0- DAC1OUT1
DAC3REF0-
DAC4REF0-
DAC5REF0-
—
—
C1IN0+
C2IN0+
C3IN0+
C4IN0+
C5IN0+
C6IN0+
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOC
IOC
IOC
—
—
—
—
—
—
—
—
—
DAC7REF0-
(1)
AN3
VREF+
DAC1REF0+
DAC2REF0+
DAC3REF0+
DAC4REF0+
DAC5REF0+
DAC7REF0+
—
C1IN1+
MD1CL
(1)
(1)
(1)
—
—
DAC4OUT1 OPA1IN0+
DAC2OUT1 OPA1IN0-
—
—
PRG1R
T0CKI
MD1CH
(1)
(1)
RA5
RA6
7
4
7
AN4
—
—
—
—
—
PRG1F
—
—
—
—
—
—
—
—
—
—
MD1MOD
—
—
—
SS
—
IOC
IOC
—
—
—
—
—
10
—
—
CLKOUT
C6IN1+
—
OSC2
RA7
9
6
—
—
—
—
CLKIN
—
—
—
—
—
—
—
—
—
—
IOC
—
—
OSC1
Note
1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection register.
2:
3:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
TABLE 3:
28-PIN ALLOCATION TABLE (PIC16(L)F1773/6/8) (CONTINUED)
(1)
(1)
RB0
RB1
21
22
18
19
AN12
AN10
HIB0
HIB1
—
—
—
C2IN1+
ZCD
—
—
—
—
—
—
—
—
COG1IN
—
—
—
—
—
—
—
—
IOC
IOC
—
—
—
—
—
—
OPA2OUT
OPA1IN1+
OPA1IN1-
C1IN3-
C2IN3-
C3IN3-
C4IN3-
PRG1IN1
PRG2IN0
COG2IN
(1)
RB2
23
20
AN8
—
DAC3OUT1 OPA2IN0-
—
—
—
—
—
—
COG3IN
—
—
—
—
IOC
—
—
—
(1)
(1)
RB3
RB4
24
25
21
22
AN9
—
—
—
—
OPA2IN0+
—
C1IN2-
C2IN2-
C3IN2-
—
—
—
—
—
—
—
—
—
—
—
—
—
MD3CL
—
—
—
—
IOC
IOC
—
—
—
—
—
—
(1)
ADCACT
C3IN1+
T5G
MD3CH
(1)
(1)
(1)
RB5
26
23
AN13
DAC5REF1-
DAC7REF1-
—
—
—
C4IN2-
—
—
T1G
—
—
CCP3
—
—
MD3MOD
—
—
IOC
—
—
—
(1)
(1)
RB6
RB7
27
28
24
25
—
—
DAC5REF1+
DAC7REF1+
—
—
C4IN1+
C5IN1+
—
—
—
—
—
—
—
—
—
—
CLCIN3
CLCIN4
—
—
—
—
—
—
IOC
IOC
—
—
—
—
ICSPCLK
ICDCLK
(1)
—
DAC1OUT2
DAC2OUT2
DAC5OUT2
DAC3OUT2
DAC4OUT2
DAC7OUT2
T6CKI
ICSPDAT
ICDDAT
Note
1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection register.
2:
3:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
TABLE 3:
28-PIN ALLOCATION TABLE (PIC16(L)F1773/6/8) (CONTINUED)
(1)
RC0
11
8
—
—
DAC5OUT1
—
—
—
—
—
T1CKI
T3CKI
T3G
—
—
—
—
—
—
—
IOC
—
—
—
(1)
(1)
(2)
(1)
(1)
RC1
RC2
12
13
9
—
—
—
DAC7OUT1
—
—
—
—
—
PRG2R
—
—
—
CCP2
CCP1
—
—
—
—
—
—
—
—
—
—
IOC
IOC
—
—
—
—
—
—
(1)
(1)
(1)
10
AN14
C5IN2-
C6IN2-
PRG2F
—
T5CKI
T2CKI
(1)
(1)
RC3
14
11
AN15
—
—
—
C1IN4-
C2IN4-
C3IN4-
C4IN4-
C5IN4-
C6IN4-
—
—
—
—
—
MD2CL
—
SDI
SDA
,
IOC
—
—
—
(1,3)
(1)
(1)
(1)
(1)
(1)
RC4
15
12
AN16
—
—
—
C5IN3-
C6IN3-
—
PRG3R
T8CKI
—
—
—
—
MD2CH
—
—
SCL ,
SCK
IOC
—
—
—
(1,3)
(1)
(1)
RC5
RC6
16
17
13
14
AN17
AN18
—
—
—
—
OPA3IN0+
OPA3OUT
—
—
—
PRG3F
T4CKI
—
—
—
—
—
—
—
—
—
MD2MOD
—
—
IOC
IOC
—
—
—
—
—
—
(1)
C5IN1-
C6IN1-
PRG3IN0
CK
—
(1,3)
RC7
RE3
18
1
15
26
AN19
—
—
—
—
—
OPA3IN0-
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RX
—
—
IOC
IOC
—
—
—
—
—
—
MCLR
ICD
VDD
VSS
VSS
OUT
20
8
17
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD
VSS
VSS
—
19
—
16
—
—
(2)
(3)
C1OUT
C2OUT
C3OUT
C4OUT
C5OUT
C6OUT
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
CCP1
CCP2
CCP3
COG1A
COG1B
COG1C
COG1D
COG2A
COG2B
COG2C
COG2D
COG3A
COG3B
COG3C
COG3D
CLC1OUT
CLC2OUT
CLC3OUT
CLC4OUT
MD1OUT
MD2OUT
MD3OUT
DT
SDO
(3)
TX
CK
SDA
SCK
(3)
SCL
Note
1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection register.
2:
3:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
TABLE 4:
40/44-PIN ALLOCATION TABLE (PIC16(L)F1777/9)
RA0
2
17 19
AN0
—
—
—
—
—
C1IN0-
C2IN0-
C3IN0-
C4IN0-
C5IN0-
C6IN0-
C7IN0-
C8IN0-
—
—
—
—
—
—
—
—
—
—
IOC
—
—
—
RA1
RA2
3
4
18 20
AN1
AN2
OPA1OUT
OPA2IN1+
OPA2IN1-
C1IN1-
C2IN1-
C3IN1-
C4IN1-
—
—
PRG1IN0
PRG2IN1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOC
IOC
—
—
—
—
—
—
19 21
DAC1REF0- DAC1OUT1
DAC2REF0-
DAC3REF0-
DAC4REF0-
DAC5REF0-
DAC6REF0-
DAC7REF0-
DAC8REF0-
—
C1IN0+
C2IN0+
C3IN0+
C4IN0+
C5IN0+
C6IN0+
C7IN0+
C8IN0+
—
(1)
RA3
RA4
5
20 22
AN3
DAC1REF0+
DAC2REF0+
DAC3REF0+
DAC4REF0+
DAC5REF0+
DAC6REF0+
DAC7REF0+
DAC8REF0+
—
—
—
C1IN1+
—
—
—
—
—
—
—
MD1CL
—
—
—
—
IOC
IOC
—
—
—
—
—
—
(1)
(1)
(1)
6
7
21 23
22 24
—
—
OPA1IN0+
—
—
—
PRG1R
T0CKI
—
—
—
—
MD1CH
(1)
(1)
RA5
RA6
AN4
—
—
—
DAC2OUT1 OPA1IN0-
—
—
PRG1F
—
—
—
—
—
—
—
—
—
—
MD1MOD
—
—
—
SS
—
IOC
IOC
—
—
—
—
—
14 29 31
—
—
CLKOUT
C6IN1+
—
OSC2
RA7
13 28 30
—
—
—
—
CLKIN
—
—
—
—
—
—
—
—
—
—
IOC
—
—
OSC1
Note
1:
2:
3:
Default peripheral input. Input can be moved to any other pin with the PPS input selection register.
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
TABLE 4:
40/44-PIN ALLOCATION TABLE (PIC16(L)F1777/9) (CONTINUED)
(1)
(1)
(1)
(1)
(1)
(1)
RB0
RB1
RB2
33
34
8
9
8
9
AN12
AN10
AN8
HIB0
HIB1
—
—
—
—
—
C2IN1+ ZCD
—
—
—
—
—
—
—
CCP4
—
COG1IN
COG2IN
COG3IN
—
—
—
MD4CL
—
—
—
—
—
—
IOC
INT
—
—
—
—
—
—
—
—
—
(1)
(1)
OPA2OUT
OPA1IN1+
OPA1IN1-
C1IN3-
C2IN3-
C3IN3-
C4IN3-
—
—
PRG4R
MD4CH
IOC
IOC
(1)
35 10 10
OPA2IN0-
—
PRG4F
—
MD4MOD
(1)
(1)
RB3
RB4
36 11 11
AN9
—
—
—
—
OPA2IN0+
—
C1IN2-
C2IN2-
C3IN2-
—
—
—
—
—
—
—
—
—
COG4IN
—
—
MD3CL
—
—
—
—
IOC
IOC
—
—
—
—
—
—
(1)
(1)
37 12 14 ADCACT
C3IN1+
T5G
—
MD3CH
(1)
(1)
(1)
RB5
38 13 15
AN13
DAC5REF1-
DAC7REF1-
—
—
C4IN2-
—
—
T1G
—
CCP3
—
—
MD3MOD
—
—
IOC
—
—
—
RB6
RB7
39 14 16
40 15 17
—
—
DAC5REF1+
DAC7REF1+
—
—
—
C4IN1+
C5IN1+
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOC
IOC
—
—
—
—
ICSPCLK
ICDCLK
(1)
—
DACxOUT2
T6CKI
ICSPDAT
ICDDAT
(1)
(1)
RC0
15 30 32
—
—
DAC5OUT1
—
—
—
—
—
T1CKI
T3CKI
T3G
—
—
—
—
—
—
—
IOC
—
—
—
(1)
(1)
(1)
(1)
(1)
RC1
RC2
RC3
RC4
Note
16 31 35
17 32 36
18 33 37
23 38 42
—
—
—
—
—
DAC7OUT1
—
—
—
—
—
—
—
—
PRG2R
PRG2F
—
SOSCO
—
—
—
—
CCP2
CCP1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOC
IOC
IOC
IOC
—
—
—
—
—
—
—
—
—
—
—
—
(1)
AN14
AN15
AN16
—
—
—
C5IN2-
C6IN2-
T5CKI
(1)
(1)
(1)
—
T2CKI
MD2CL
SDI
,
(1,3)
SDA
(1)
(1)
(1)
(1)
C5IN3-
C6IN3-
PRG3R
T8CKI
—
MD2CH
SCL
SCK
,
(1,3)
1:
2:
3:
Default peripheral input. Input can be moved to any other pin with the PPS input selection register.
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
TABLE 4:
40/44-PIN ALLOCATION TABLE (PIC16(L)F1777/9) (CONTINUED)
(1)
(1)
(1)
RC5
RC6
24 39 43
25 40 44
AN17
AN18
—
—
—
—
OPA3IN0+
—
—
—
PRG3F
T4CKI
—
—
—
—
—
—
—
—
—
MD2MOD
—
—
—
—
IOC
IOC
—
—
—
—
—
—
(1)
OPA3OUT
OPA4IN1+
OPA4IN1-
C5IN1-
C6IN1-
C7IN1-
C8IN1-
PRG3IN0
PRG4IN1
CK
(1,3)
RC7
26
1
1
AN19
—
—
OPA3IN0-
—
—
—
—
—
—
—
—
—
—
—
RX
IOC
—
—
—
RD0
RD1
19 34 38
20 35 39
AN20
AN21
—
—
—
—
OPA4IN0+
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OPA4OUT
OPA3IN1+
OPA3IN1-
C1IN4-
C2IN4-
C3IN4-
C4IN4-
C5IN4-
C6IN4-
C7IN4-
C8IN4-
PRG3IN1
PRG4IN0
—
RD2
RD3
RD4
RD5
21 36 40
22 37 41
AN22
AN23
AN24
AN25
—
—
—
—
—
—
—
—
OPA4IN0-
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C8IN2-
C7IN2-
27
28
2
3
2
3
C7IN3-
C8IN3-
RD6
RD7
29
30
4
5
4
5
AN26
AN27
—
—
—
—
—
—
C7IN1+
C8IN1+
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RE0
RE1
8
9
23 25
24 26
AN5
AN6
DAC6REF1+
DAC8REF1+
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOC
IOC
—
—
—
—
—
—
—
DAC6REF1-
DAC8REF1-
RE2
RE3
10 25 27
AN7
—
—
—
DAC6OUT1
DAC8OUT1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOC
IOC
—
—
—
—
1
16 18
MCLR
ICD
VDD
VDD
VSS
VSS
Note
11
7
7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD
VDD
VSS
VSS
32 26 28
12
31 27 29
6
6
1:
2:
3:
Default peripheral input. Input can be moved to any other pin with the PPS input selection register.
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
TABLE 4:
40/44-PIN ALLOCATION TABLE (PIC16(L)F1777/9) (CONTINUED)
(2)
(3)
OUT
—
—
—
—
—
—
—
C1OUT
C2OUT
C3OUT
C4OUT
C5OUT
C6OUT
C7OUT
C8OUT
—
—
—
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
CCP1
CCP2
CCP3
CCP4
COG1A
COG1B
COG1C
COG1D
COG2A
COG2B
COG2C
COG2D
COG3A
COG3B
COG3C
COG3D
COG4A
COG4B
COG4C
COG4D
CLC1OUT
CLC2OUT
CLC3OUT
CLC4OUT
MD1OUT
MD2OUT
MD3OUT
MD4OUT
DT
TX
CK
SDO
—
—
—
—
(3)
SDA
SCK
(3)
SCL
Note
1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection register.
2:
3:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
PIC16(L)F1773/6/7/8/9
NOTES:
DS40001790A-page 14
Advance Information
2015 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
32
OptoLyzer, PIC, PICSTART, PIC logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2015, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-63277-450-7
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2015 Microchip Technology Inc.
Advance Information
DS40001790A-page 15
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01/27/15
DS40001790A-page 16
Advance Information
2015 Microchip Technology Inc.
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