PIC16LF1827-I/MV_技术文档

PIC16F/LF1826/27

Data Sheet

18/20/28-Pin Flash Microcontrollers

with nanoWatt XLP Technology

 2010 Microchip Technology Inc.

Preliminary

DS41391C

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,

TSHARC, UniWinDriver, WiperLock and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-60932-285-4

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS41391C-page 2

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

18/20/28-Pin Flash Microcontrollers with nanoWatt XLP Technology

High-Performance RISC CPU:

Extreme Low-Power Management

PIC16LF1826/27 with nanoWatt XLP:

• C Compiler Optimized Architecture

• 256 bytes Data EEPROM

• Sleep mode: 30 nA

• Up to 4 Kbytes Linear Program Memory

Addressing

• Watchdog Timer: 500 nA

• Timer1 Oscillator: 600 nA @ 32 kHz

• Up to 384 bytes Linear Data Memory Addressing

• Interrupt Capability with Automatic Context Saving

• 16-Level Deep Hardware Stack with Optional

Overflow/Underflow Reset

• Direct, Indirect and Relative Addressing modes:

- Two full 16-bit File Select Registers (FSRs)

- FSRs can read program and data memory

Analog Features:

• Analog-to-Digital Converter (ADC) Module:

- 10-bit resolution, 12 channels

- Auto acquisition capability

- Conversion available during Sleep

• Analog Comparator Module:

- Two rail-to-rail analog comparators

- Power mode control

- Software controllable hysteresis

• Voltage Reference Module:

- Fixed Voltage Reference (FVR) with 1.024V,

2.048V and 4.096V output levels

- 5-bit rail-to-rail resistive DAC with positive

and negative reference selection

Flexible Oscillator Structure:

• Precision 32 MHz Internal Oscillator Block:

- Factory calibrated to ± 1%, typical

- Software selectable frequencies range of

31 kHz to 32 MHz

• 31 kHz Low-Power Internal Oscillator

• Four Crystal modes up to 32 MHz

• Three External Clock modes up to 32 MHz

• 4X Phase Lock Loop (PLL)

• Fail-Safe Clock Monitor:

- Allows for safe shutdown if peripheral clock

stops

• Two-Speed Oscillator Start-up

• Reference Clock Module:

Peripheral Highlights:

• 15 I/O Pins and 1 Input Only Pin:

- High current sink/source 25 mA/25 mA

- Programmable weak pull-ups

- Programmable interrupt-on- change pins

• Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler

• Enhanced Timer1:

- Programmable clock output frequency and

duty-cycle

- 16-bit timer/counter with prescaler

- External Gate Input mode

Special Microcontroller Features:

- Dedicated, low-power 32 kHz oscillator driver

• Up to three Timer2-types: 8-Bit Timer/Counter with

8-Bit Period Register, Prescaler and Postscaler

• Up to two Capture, Compare, PWM (CCP) Modules

• Up to two Enhanced CCP (ECCP) Modules:

- Software selectable time bases

- Auto-shutdown and auto-restart

- PWM steering

• 1.8V-5.5V Operation – PIC16F1826/27

• 1.8V-3.6V Operation – PIC16LF1826/27

• Self-Programmable under Software Control

• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

• Programmable Brown-out Reset (BOR)

• Extended Watchdog Timer (WDT):

- Programmable period from 1ms to 268s

• Programmable Code Protection

• Up to two Master Synchronous Serial Port

(MSSP) with SPI and I²C^TMwith:

• In-Circuit Serial Programming™ (ICSP™) via

two pins

- 7-bit address masking

- SMBus/PMBus^TMcompatibility

• In-Circuit Debug (ICD) via two pins

• Enhance Low-Voltage Programming

• Power-Saving Sleep mode

• Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) Module

• mTouch™ Sensing Oscillator Module:

- Up to 12 input channels

• Data Signal Modulator Module:

- Selectable modulator and carrier sources

• SR Latch:

- Multiple Set/Reset input options

- Emulates 555 Timer applications

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 3

PIC16F/LF1826/27

PIC16F/LF1826/27 Family Types

Program

Memory

Data

Memory

PIC16LF1826

PIC16F1826

PIC16LF1827

PIC16F1827

2K

4K

256

16

12

2

2/1

4/1

1

2

1

—

1

—

2

Yes

256

384

1

2

Note 1: One pin is input only.

DS41391C-page 4

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

Pin Diagram – 28-Pin QFN/UQFN (PIC16F/LF1826/27)

QFN/UQFN

RA5/ MCLR/VPP/SS1⁽¹⁾

VSS

RA7/OSC1/CLKIN/P1C⁽¹⁾/CCP2^(1,2)/P2A^(1,2)

RA6/OSC2/CLKOUT/CLKR/P1D⁽¹⁾/P2B^(1,2)/SDO1⁽¹⁾

VDD

1

21

2

3

20

19

NC

PIC16F/LF1826/27

4

18 NC

17

VSS

5

6

7

VDD

RB7/AN6/CPS6/T1OSO/P1D⁽¹⁾/P2B^(1,2)/MDCIN1/ICSPDAT

RB6/AN5/CPS5/T1CKI/T1OSI/P1C⁽¹⁾/CCP2^(1,2)/P2A^(1,2)/ICSPCLK

16

NC

RB0/SRI/T1G/CCP1⁽¹⁾/P1A⁽¹⁾/INT/SRI/FLT0

15

Note 1: Pin feature is dependent on device configuration.

2: ECCP2, CCP3, CCP4, MSSP2 functions are only available on the PIC16F/LF1827.

DS41391C-page 6

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

Table of Contents

1.0 Device Overview ........................................................................................................................................................................ 11

2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 17

3.0 Memory Organization................................................................................................................................................................. 19

4.0 Device Configuration .................................................................................................................................................................. 49

5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 55

6.0 Reference Clock Module ............................................................................................................................................................ 73

7.0 Resets ........................................................................................................................................................................................ 77

8.0 Interrupts .................................................................................................................................................................................... 85

9.0 Power-Down Mode (Sleep) ...................................................................................................................................................... 101

10.0 Watchdog Timer (WDT) ........................................................................................................................................................... 103

11.0 Data EEPROM and Flash Program Memory Control............................................................................................................... 107

12.0 I/O Ports ................................................................................................................................................................................... 121

13.0 Interrupt-on-Change................................................................................................................................................................. 133

14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 137

15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 139

16.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 153

17.0 SR Latch................................................................................................................................................................................... 159

18.0 Comparator Module.................................................................................................................................................................. 165

19.0 Timer0 Module ......................................................................................................................................................................... 175

21.0 Timer1 Module ......................................................................................................................................................................... 179

22.0 Timer2/4/6 Modules.................................................................................................................................................................. 191

23.0 Data Signal Modulator (DSM) .................................................................................................................................................. 195

24.0 Capture/Compare/PWM (ECCP1, ECCP2, ECCP3, CCP4) Modules...................................................................................... 205

25.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 233

26.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 287

27.0 Capacitive Sensing Module...................................................................................................................................................... 317

28.0 In-Circuit Serial Programming™ (ICSP™) ................................................................................................................................ 325

29.0 Instruction Set Summary.......................................................................................................................................................... 329

30.0 Electrical Specifications............................................................................................................................................................ 343

31.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 377

32.0 Development Support............................................................................................................................................................... 379

33.0 Packaging Information.............................................................................................................................................................. 383

Appendix A: Revision History............................................................................................................................................................. 393

Appendix B: Device Differences......................................................................................................................................................... 393

Index .................................................................................................................................................................................................. 395

The Microchip Web Site..................................................................................................................................................................... 403

Customer Change Notification Service .............................................................................................................................................. 403

Customer Support.............................................................................................................................................................................. 403

Reader Response .............................................................................................................................................................................. 404

Product Identification System............................................................................................................................................................. 405

DS41391C-page 8

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.

We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)

• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277

When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include

literature number) you are using.

Customer Notification System

Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 9

PIC16F/LF1826/27

NOTES:

DS41391C-page 10

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

1.0

DEVICE OVERVIEW

The PIC16F/LF1826/27 are described within this data

sheet. They are available in 18/20/28-pin packages.

Figure 1-1 shows

a

block diagram of the

PIC16F/LF1826/27 devices. Table 1-2 shows the

pinout descriptions.

Reference Table 1-1 for peripherals available per

device.

TABLE 1-1:

DEVICE PERIPHERAL

SUMMARY

Peripheral

ADC

●

Capacitive Sensing Module

●

Digital-to-Analog Converter (DAC)

Digital Signal Modulator (DSM)

EUSART

Fixed Voltage Reference (FVR)

Reference Clock Module

SR Latch

Capture/Compare/PWM Modules

ECCP1

●

ECCP2

CCP3

CCP4

Comparators

C1

●

C2

Master Synchronous Serial Ports

MSSP1

●

MSSP2

Timers

Timer0

Timer1

Timer2

Timer4

Timer6

●

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 11

PIC16F/LF1826/27

FIGURE 1-1:

PIC16F/LF1826/27 BLOCK DIAGRAM

Program

Flash Memory

EEPROM

RAM

CLKR

Clock

Reference

Timing

Generation

OSC2/CLKO

OSC1/CLKI

PORTA

PORTB

CPU

INTRC

Oscillator

(Figure 2-1)

MCLR

SR

Latch

ADC

10-Bit

Timer2-

Types

Timer0

MSSPx

Timer1

DAC

FVR

Comparators

Modulator

ECCPx

CCPx

EUSART

CapSense

Note 1:

2:

See applicable chapters for more information on peripherals.

See Table 1-1 for peripherals available on specific devices.

DS41391C-page 12

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 1-2:

PIC16F/LF1826/27 PINOUT DESCRIPTION

Input Output

Function

Name

Description

Type

RA0/AN0/CPS0/C12IN0-/

SDO2

RA0

AN0

TTL

AN

—

CMOS General purpose I/O.

(2)

—

A/D Channel 0 input.

CPS0

C12IN0-

SDO2

RA1

Capacitive sensing input 0.

Comparator C1 or C2 negative input.

CMOS SPI data output.

(2)

RA1/AN1/CPS1/C12IN1-/SS2

TTL

AN

ST

TTL

AN

—

CMOS General purpose I/O.

AN1

—

A/D Channel 1 input.

CPS1

C12IN1-

SS2

Capacitive sensing input 1.

Comparator C1 or C2 negative input.

Slave Select input 2.

RA2/AN2/CPS2/C12IN2-/

C12IN+/VREF-/DACOUT

RA2

CMOS General purpose I/O.

AN2

—

AN

A/D Channel 2 input.

CPS2

C12IN2-

C12IN+

VREF-

DACOUT

RA3

Capacitive sensing input 2.

Comparator C1 or C2 negative input.

Comparator C1 or C2 positive input.

A/D Negative Voltage Reference input.

Voltage Reference output.

RA3/AN3/CPS3/C12IN3-/C1IN+/

TTL

AN

—

CMOS General purpose I/O.

(2)

VREF+/C1OUT/CCP3 /SRQ

AN3

—

A/D Channel 3 input.

CPS3

C12IN3-

C1IN+

VREF+

C1OUT

CCP3

SRQ

Capacitive sensing input 3.

Comparator C1 or C2 negative input.

Comparator C1 positive input.

A/D Voltage Reference input.

CMOS Comparator C1 output.

CMOS Capture/Compare/PWM3.

CMOS SR latch non-inverting output.

CMOS General purpose I/O.

ST

—

RA4/AN4/CPS4/C2OUT/T0CKI/

RA4

TTL

AN

—

(2)

CCP4 /SRNQ

AN4

—

A/D Channel 4 input.

CPS4

C2OUT

T0CKI

CCP4

SRNQ

RA5

Capacitive sensing input 4.

CMOS Comparator C2 output.

Timer0 clock input.

ST

—

CMOS Capture/Compare/PWM4.

CMOS SR latch inverting output.

CMOS General purpose I/O.

(1,2)

RA5/MCLR/VPP/SS1

TTL

ST

HV

ST

MCLR

VPP

—

Master Clear with internal pull-up.

Programming voltage.

SS1

Slave Select input 1.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output

OD = Open Drain

2

TTL = TTL compatible input ST

HV = High Voltage

= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C

levels

XTAL = Crystal

Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register.

2: Functions are only available on the PIC16F/LF1827.

3: Default function location.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 13

PIC16F/LF1826/27

TABLE 1-2:

PIC16F/LF1826/27 PINOUT DESCRIPTION (CONTINUED)

Input Output

Name

Function

Description

Type

RA6/OSC2/CLKOUT/CLKR/

RA6

OSC2

CLKOUT

CLKR

P1D

TTL

—

CMOS General purpose I/O.

(1)

(1,2)

(1)

P1D /P2B

/SDO1

XTAL Crystal/Resonator (LP, XT, HS modes).

CMOS FOSC/4 output.

—

CMOS Clock Reference Output.

CMOS PWM output.

—

P2B

—

CMOS PWM output.

SDO1

RA7

—

CMOS SPI data output 1.

CMOS General purpose I/O.

(1)

RA7/OSC1/CLKIN/P1C

/

TTL

XTAL

CMOS

—

(1,2)

CCP2

/P2A

OSC1

CLKIN

P1C

—

Crystal/Resonator (LP, XT, HS modes).

External clock input (EC mode).

CMOS PWM output.

CCP2

P2A

ST

CMOS Capture/Compare/PWM2.

CMOS PWM output.

—

(1)

RB0/T1G/CCP1 /P1A /INT/

SRI/FLT0

RB0

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

T1G

CCP1

P1A

INT

ST

—

Timer1 Gate input.

CMOS Capture/Compare/PWM1.

CMOS PWM output.

ST

TTL

—

External interrupt.

SRI

SR latch input.

FLT0

RB1

ECCP Auto-Shutdown Fault input.

(1,3)

RB1/AN11/CPS11/RX

/

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

(1,3)

DT

/SDA1/SDI1

AN11

CPS11

RX

AN

ST

—

A/D Channel 11 input.

Capacitive sensing input 11.

USART asynchronous input.

DT

CMOS USART synchronous data.

2

SDA1

SDI1

RB2

I C™

OD

—

I C™ data input/output 1.

SPI data input 1.

CMOS

TTL

RB2/AN10/CPS10/MDMIN/

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

(1,3)

(1)

TX

/CK

/RX /DT /

(2)

(1,3)

SDA2 /SDI2 /SDO1

AN10

CPS10

MDMIN

TX

AN

—

A/D Channel 10 input.

Capacitive sensing input 10.

CMOS Modulator source input.

—

CMOS USART asynchronous transmit.

CMOS USART synchronous clock.

CK

ST

RX

—

USART asynchronous input.

DT

CMOS USART synchronous data.

2

SDA2

SDI2

SDO1

I C™

OD

—

I C™ data input/output 2.

SPI data input 2.

ST

—

CMOS SPI data output 1.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output

OD = Open Drain

2

TTL = TTL compatible input ST

HV = High Voltage

= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C

levels

XTAL = Crystal

Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register.

2: Functions are only available on the PIC16F/LF1827.

3: Default function location.

DS41391C-page 14

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 1-2:

PIC16F/LF1826/27 PINOUT DESCRIPTION (CONTINUED)

Input Output

Name

Function

Description

Type

RB3/AN9/CPS9/MDOUT/

RB3

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

(1,3)

CCP1

/P1A

AN9

CPS9

MDOUT

CCP1

P1A

AN

—

A/D Channel 9 input.

Capacitive sensing input 9.

CMOS Modulator output.

CMOS Capture/Compare/PWM1.

CMOS PWM output.

ST

—

RB4/AN8/CPS8/SCL1/SCK1/

MDCIN2

RB4

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN8

CPS8

SCL1

SCK1

MDCIN2

RB5

AN

—

A/D Channel 8 input.

Capacitive sensing input 8.

2

I C™

OD

I C™ clock 1.

ST

CMOS SPI clock 1.

—

Modulator Carrier Input 2.

(1)

RB5/AN7/CPS7/P1B/TX /CK

SCL2 /SCK2 /SS1

/

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

(2)

(1,3)

AN7

CPS7

P1B

TX

AN

—

A/D Channel 7 input.

Capacitive sensing input 7.

CMOS PWM output.

—

CMOS USART asynchronous transmit.

CK

ST

CMOS USART synchronous clock.

2

SCL2

SCK2

SS1

RB6

I C™

OD

I C™ clock 2.

ST

CMOS SPI clock 2.

—

Slave Select input 1.

RB6/AN5/CPS5/T1CKI/T1OSI/

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

(1,3)

(1,2,3)

P1C

/CCP2

/P2A

/

ICSPCLK

AN5

CPS5

T1CKI

T1OSO

P1C

AN

ST

—

A/D Channel 5 input.

Capacitive sensing input 5.

Timer1 clock input.

XTAL

—

XTAL Timer1 oscillator connection.

CMOS PWM output.

CCP2

P2A

ST

CMOS Capture/Compare/PWM2.

CMOS PWM output.

—

ICSPCLK

RB7

ST

—

Serial Programming Clock.

RB7/AN6/CPS6/T1OSO/

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

(1,3)

(1,2,3)

P1D

/P2B

/MDCIN1/

ICSPDAT

AN6

CPS6

AN

XTAL

—

A/D Channel 6 input.

Capacitive sensing input 6.

T1OSO

P1D

XTAL Timer1 oscillator connection.

CMOS PWM output.

P2B

—

CMOS PWM output.

MDCIN1

ICSPDAT

ST

—

Modulator Carrier Input 1.

ST

CMOS ICSP™ Data I/O.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output

OD = Open Drain

2

TTL = TTL compatible input ST

HV = High Voltage

= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C

levels

XTAL = Crystal

Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register.

2: Functions are only available on the PIC16F/LF1827.

3: Default function location.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 15

PIC16F/LF1826/27

TABLE 1-2:

PIC16F/LF1826/27 PINOUT DESCRIPTION (CONTINUED)

Input Output

Name

Function

Description

Type

VDD

VSS

VDD

VSS

Power

—

Positive supply.

Ground reference.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output

OD = Open Drain

2

TTL = TTL compatible input ST

HV = High Voltage

= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C

levels

XTAL = Crystal

Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register.

2: Functions are only available on the PIC16F/LF1827.

3: Default function location.

DS41391C-page 16

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

2.0

ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range

8-bit CPU core. The CPU has 49 instructions. Interrupt

capability includes automatic context saving. The

hardware stack is 16 levels deep and has Overflow and

Underflow Reset capability. Direct, indirect, and relative

addressing modes are available. Two File Select

Registers (FSRs) provide the ability to read program

and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

2.1

Automatic Interrupt Context

Saving

During interrupts, certain registers are automatically

saved in shadow registers and restored when returning

from the interrupt. This saves stack space and user

code. See Section 8.5 “Automatic Context Saving”,

for more information.

2.2

16-level Stack with Overflow and

Underflow

These devices have an external stack memory 15 bits

wide and 16 words deep. A Stack Overflow or Under-

flow will set the appropriate bit (STKOVF or STKUNF)

in the PCON register, and if enabled will cause a soft-

ware Reset. See section Section 3.4 “Stack” for more

details.

2.3

File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs

can access all file registers and program memory,

which allows one data pointer for all memory. When an

FSR points to program memory, there is 1 additional

instruction cycle in instructions using INDF to allow the

data to be fetched. General purpose memory can now

also be addressed linearly, providing the ability to

access contiguous data larger than 80 bytes. There are

also new instructions to support the FSRs. See

Section 3.4 “Stack”for more details.

2.4

Instruction Set

There are 49 instructions for the enhanced mid-range

CPU to support the features of the CPU. See

Section 28.0 “Instruction Set Summary” for more

details.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 17

PIC16F/LF1826/27

FIGURE 2-1:

CORE BLOCK DIAGRAM

15

Configuration

15

8

Data Bus

RAM

Program Counter

Flash

Program

Memory

186-LLeevveellSStatacckk

(153-bit)

Program

Bus

14

RAM Addr

Program Memory

Read (PMR)

12

Addr MUX

IInnssttrruuccttiioonnRreegg

Indirect

Addr

7

Direct Addr

12

5

BSR Reg

FSR reg

15

FSR0 Reg

reg

FSR1 Reg

FSR reg

15

SSTTAATTUUSSRreegg

8

3

MUX

Power-up

Timer

Oscillator

Instruction

DDeeccooddeea&nd

Control

Start-up Timer

ALU

Power-on

Reset

OSC1/CLKIN

8

Timing

Generation

Watchdog

Timer

W reg

OSC2/CLKOUT

Brown-out

Reset

Internal

Oscillator

Block

VDD

VSS

DS41391C-page 18

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

The following features are associated with access and

control of program memory and data memory:

3.0

MEMORY ORGANIZATION

There

are

three

types

of

memory

in

• PCL and PCLATH

• Stack

PIC16F/LF1826/27: Data Memory, Program Memory

and Data EEPROM Memory⁽¹⁾

.

• Indirect Addressing

• Program Memory

• Data Memory

3.1

Program Memory Organization

- Core Registers

The enhanced mid-range core has a 15-bit program

counter capable of addressing a 32K x 14 program

memory space. Table 3-1 shows the memory sizes

implemented for the PIC16F/LF1826/27 family.

Accessing a location above these boundaries will cause

a wrap-around within the implemented memory space.

The Reset vector is at 0000h and the interrupt vector is

at 0004h (see Figures 3-1 and 3-2).

- Special Function Registers

- General Purpose RAM

- Common RAM

- Device Memory Maps

- Special Function Registers Summary

• Data EEPROM memory⁽¹⁾

Note 1: The Data EEPROM Memory and the

method to access Flash memory through

the EECON registers is described in

Section 11.0 “Data EEPROM and Flash

Program Memory Control”.

TABLE 3-1:

DEVICE SIZES AND ADDRESSES

Device Program Memory Space (Words)

PIC16F/LF1826

Last Program Memory Address

2,048

4,096

07FFh

0FFFh

PIC16F/LF1827

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 19

PIC16F/LF1826/27

FIGURE 3-1:

PROGRAM MEMORY MAP

AND STACK FOR

FIGURE 3-2:

PROGRAM MEMORY MAP

AND STACK FOR

PIC16F/LF1826

PIC16F/LF1827

PC<14:0>

CALL, CALLW

RETURN, RETLW

Interrupt, RETFIE

CALL, CALLW

RETURN, RETLW

Interrupt, RETFIE

15

Stack Level 0

Stack Level 1

Stack Level 15

Reset Vector

Stack Level 15

Reset Vector

0000h

Interrupt Vector

Page 0

Interrupt Vector

Page 0

0004h

0005h

0004h

0005h

On-chip

Program

Memory

On-chip

Program

Memory

07FFh

0800h

07FFh

0800h

Rollover to Page 0

Wraps to Page 0

Page 1

0FFFh

1000h

Rollover to Page 0

Wraps to Page 0

Rollover to Page 1

Rollover to Page 0

7FFFh

DS41391C-page 20

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

3.1.1

READING PROGRAM MEMORY AS

DATA

There are two methods of accessing constants in pro-

gram memory. The first method is to use tables of

RETLW instructions. The second method is to set an

FSR to point to the program memory.

3.1.1.1

RETLWInstruction

The RETLWinstruction can be used to provide access

to tables of constants. The recommended way to create

such a table is shown in Example 3-1.

EXAMPLE 3-1:

RETLW INSTRUCTION

constants

brw

;Add Index in W to

;program counter to

;select data

retlw DATA0

retlw DATA1

retlw DATA2

retlw DATA3

;Index0 data

;Index1 data

my_function

;… LOTS OF CODE…

movlw DATA_INDEX

call constants

;… THE CONSTANT IS IN W

The BRWinstruction makes this type of table very sim-

ple to implement. If your code must remain portable

with previous generations of microcontrollers, then the

BRW instruction is not available so the older table read

method must be used.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 21

PIC16F/LF1826/27

3.1.1.2

Indirect Read with FSR

3.2.1

CORE REGISTERS

The program memory can be accessed as data by set-

ting bit 7 of the FSRxH register and reading the match-

ing INDFx register. The MOVIWinstruction will place the

lower 8 bits of the addressed word in the W register.

Writes to the program memory cannot be performed via

the INDF registers. Instructions that access the pro-

gram memory via the FSR require one extra instruction

cycle to complete. Example 3-2 demonstrates access-

ing the program memory via an FSR.

The core registers contain the registers that directly

affect the basic operation of the PIC16F/LF1826/27.

These registers are listed below:

• INDF0

• INDF1

• PCL

• STATUS

• FSR0 Low

• FSR0 High

• FSR1 Low

• FSR1 High

• BSR

The HIGH directive will set bit<7> if a label points to a

location in program memory.

EXAMPLE 3-2:

ACCESSING PROGRAM

MEMORY VIA FSR

• WREG

constants

• PCLATH

• INTCON

RETLW DATA0

RETLW DATA1

RETLW DATA2

RETLW DATA3

my_function

;Index0 data

;Index1 data

Note:

The core registers are the first 12

addresses of every data memory bank.

;… LOTS OF CODE…

MOVLW LOW constants

MOVWF FSR1L

MOVLW HIGH constants

MOVWF FSR1H

MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

3.2

Data Memory Organization

The data memory is partitioned in 32 memory banks

with 128 bytes in a bank. Each bank consists of

(Figure 3-3):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number

into the Bank Select Register (BSR). Unimplemented

memory will read as ‘0’. All data memory can be

accessed either directly (via instructions that use the

file registers) or indirectly via the two File Select

Registers (FSR). See Section 3.5 “Indirect

Addressing” for more information.

DS41391C-page 22

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

For example, CLRF STATUSwill clear the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’ (where u= unchanged).

3.2.1.1

STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not

affecting any Status bits (Refer to Section 28.0

“Instruction Set Summary”).

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

Note 1: The C and DC bits operate as Borrow and

Digit Borrow out bits, respectively, in

subtraction.

REGISTER 3-1:

STATUS: STATUS REGISTER

U-0

—

U-0

—

U-0

—

R-1/q

TO

R-1/q

PD

R/W-0/u

Z

R/W-0/u

DC⁽¹⁾

R/W-0/u

C⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-5

bit 4

Unimplemented: Read as ‘0’

TO: Time-out bit

1= After power-up, CLRWDTinstruction or SLEEPinstruction

0= A WDT time-out occurred

bit 3

bit 2

bit 1

bit 0

PD: Power-down bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit Carry/Digit Borrow bit⁽¹⁾

1= A carry-out from the 4th low-order bit of the result occurred

0= No carry-out from the 4th low-order bit of the result

C: Carry/Borrow bit⁽¹⁾

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order

bit of the source register.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 23

PIC16F/LF1826/27

3.2.2

SPECIAL FUNCTION REGISTER

3.2.5

DEVICE MEMORY MAPS

The Special Function Registers are registers used by

the application to control the desired operation of

peripheral functions in the device. The registers asso-

ciated with the operation of the peripherals are

described in the appropriate peripheral chapter of this

data sheet.

The memory maps for the device family are as shown

in Table 3-2.

TABLE 3-2:

Device

PIC16F/LF1826/27

MEMORY MAP TABLES

Banks

Table No.

0-7

8-15

16-23

24-31

31

Table 3-3

Table 3-4

Table 3-5

Table 3-6

Table 3-7

3.2.3

GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory

bank.

3.2.3.1

Linear Access to GPR

The general purpose RAM can be accessed in a

non-banked method via the FSRs. This can simplify

access to large memory structures. See Section 3.5.2

“Linear Data Memory” for more information.

3.2.4

COMMON RAM

There are 16 bytes of common RAM accessible from all

banks.

FIGURE 3-3:

BANKED MEMORY

PARTITIONING

Memory Region

7-bit Bank Offset

00h

Core Registers

(12 bytes)

0Bh

0Ch

Special Function Registers

(20 bytes maximum)

1Fh

20h

General Purpose RAM

(80 bytes maximum)

6Fh

70h

Common RAM

(16 bytes)

7Fh

DS41391C-page 24

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 3-7:

PIC16F/LF1826/27 MEMORY

MAP, BANK 31

3.2.6

SPECIAL FUNCTION REGISTERS

SUMMARY

The Special Function Register Summary for the device

family are as follows:

Bank 31

FA0h

Unimplemented

Read as ‘0’

Device

Bank(s)

Page No.

0

1

30

31

32

33

34

35

36

37

38

39

40

FE3h

FE4h

FE5h

FE6h

FE7h

FE8h

FE9h

FEAh

FEBh

FECh

FEDh

FEEh

FEFh

STATUS_SHAD

WREG_SHAD

BSR_SHAD

PCLATH_SHAD

FSR0L_SHAD

FSR0H_SHAD

FSR1L_SHAD

FSR1H_SHAD

—

2

3

4

PIC16F/LF1826/27

5

6

7

STKPTR

TOSL

8

9-30

31

TOSH

Legend:

= Unimplemented data memory locations,

read as ‘0’.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 29

PIC16F/LF1826/27

TABLE 3-8:

SPECIAL FUNCTION REGISTER SUMMARY

Value on all

other

Resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 0

000h⁽²⁾

INDF0

INDF1

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

001h⁽²⁾

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

002h⁽²⁾

003h⁽²⁾

004h⁽²⁾

005h⁽²⁾

006h⁽²⁾

007h⁽²⁾

008h⁽²⁾

009h⁽²⁾

00Ah⁽²⁾

00Bh⁽²⁾

00Ch

PCL

Program Counter (PC) Least Significant Byte

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

xxxx xxxx xxxx xxxx

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

—

TO

PD

Z

DC

C

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

—

BSR4

BSR3

BSR2

BSR1

BSR0

WREG

PCLATH

INTCON

PORTA

PORTB

—

Working Register

—

Write Buffer for the upper 7 bits of the Program Counter

GIE

RA7

PEIE

RA6

RB6

TMR0IE

RA5

INTE

RA4

RB4

IOCIE

RA3

TMR0IF

RA2

INTF

RA1

RB1

IOCIF

RA0

00Dh

RB7

RB5

RB3

RB2

RB0

00Eh

Unimplemented

TMR1GIF

OSFIF

—

00Fh

—

010h

—

011h

PIR1

ADIF

C2IF

—

RCIF

C1IF

TXIF

EEIF

CCP3IF

—

SSP1IF

BCL1IF

TMR6IF

—

CCP1IF

TMR2IF

—

TMR1IF 0000 0000 0000 0000

CCP2IF⁽¹⁾0000 0--0 0000 0--0

012h

PIR2

—

013h

PIR3⁽¹⁾

PIR4⁽¹⁾

TMR0

TMR1L

TMR1H

T1CON

T1GCON

—

CCP4IF

—

TMR4IF

BCL2IF

—

--00 0-0- --00 0-0-

014h

—

SSP2IF ---- --00 ---- --00

xxxx xxxx uuuu uuuu

015h

Timer0 Module Register

016h

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

017h

xxxx xxxx uuuu uuuu

018h

TMR1CS1

TMR1GE

TMR1CS0

T1GPOL

T1CKPS1

T1GTM

T1CKPS0 T1OSCEN T1SYNC

—

TMR1ON 0000 00-0 uuuu uu-u

T1GSS0 0000 0x00 uuuu uxuu

019h

T1GSPM

T1GGO/

DONE

T1GVAL

T1GSS1

01Ah

01Bh

01Ch

01Dh

01Eh

01Fh

TMR2

Timer2 Module Register

Timer2 Period Register

0000 0000 0000 0000

1111 1111 1111 1111

PR2

T2CON

—

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

Unimplemented

CPSON

—

CPSCON0

CPSCON1

—

CPSRNG1 CPSRNG0 CPSOUT

T0XCS

0--- 0000 0--- 0000

CPSCH3 CPSCH2 CPSCH1 CPSCH0 ---- 0000 ---- 0000

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: PIC16F/LF1827 only.

2: These registers can be addressed from any bank.

DS41391C-page 30

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 3-8:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 1

080h⁽²⁾

INDF0

INDF1

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

081h⁽²⁾

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

082h⁽²⁾

083h⁽²⁾

084h⁽²⁾

085h⁽²⁾

086h⁽²⁾

087h⁽²⁾

088h⁽²⁾

089h⁽²⁾

08Ah⁽²⁾

08Bh⁽²⁾

08Ch

PCL

Program Counter (PC) Least Significant Byte

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

—

TO

PD

Z

DC

C

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

—

BSR4

BSR3

BSR2

BSR1

BSR0

IOCIF

WREG

PCLATH

INTCON

TRISA

TRISB

—

Working Register

—

GIE

Write Buffer for the upper 7 bits of the Program Counter

PEIE

TMR0IE

TRISA5

TRISB5

INTE

IOCIE

TRISA3

TRISB3

TMR0IF

TRISA2

TRISB2

INTF

TRISA7

TRISB7

Unimplemented

TMR1GIE

OSFIE

TRISA6

TRISB6

TRISA4

TRISB4

TRISA1

TRISB1

TRISA0 1111 1111 1111 1111

TRISB0 1111 1111 1111 1111

08Dh

08Eh

—

08Fh

—

090h

—

091h

PIE1

ADIE

C2IE

—

RCIE

C1IE

TXIE

EEIE

SSP1IE

BCL1IE

TMR6IE

—

CCP1IE

—

TMR2IE

—

TMR1IE 0000 0000 0000 0000

CCP2IE⁽¹⁾0000 0--0 0000 0--0

092h

PIE2

093h

PIE3⁽¹⁾

PIE4⁽¹⁾

OPTION_REG

PCON

WDTCON

OSCTUNE

OSCCON

OSCSTAT

ADRESL

ADRESH

ADCON0

ADCON1

—

CCP4IE

—

CCP3IE

—

TMR4IE

BCL2IE

PS1

—

--00 0-0- --00 0-0-

094h

—

SSP2IE ---- --00 ---- --00

095h

WPUEN

STKOVF

—

INTEDG

STKUNF

—

TMR0CS

—

TMR0SE

—

PSA

PS2

RI

PS0

1111 1111 1111 1111

00-- 11qq qq-- qquu

096h

RMCLR

WDTPS2

TUN3

POR

BOR

097h

WDTPS4

TUN5

IRCF2

OSTS

WDTPS3

TUN4

IRCF1

HFIOFR

WDTPS1 WDTPS0 SWDTEN --01 0110 --01 0110

098h

—

TUN2

—

TUN1

SCS1

TUN0

SCS0

--00 0000 --00 0000

0011 1-00 0011 1-00

099h

SPLLEN

T1OSCR

IRCF3

PLLR

IRCF0

HFIOFL

09Ah

MFIOFR

LFIOFR

HFIOFS 10q0 0q00 qqqq qq0q

xxxx xxxx uuuu uuuu

09Bh

A/D Result Register Low

A/D Result Register High

09Ch

xxxx xxxx uuuu uuuu

09Dh

—

CHS4

CHS3

CHS2

CHS1

—

CHS0

GO/DONE

ADON

-000 0000 -000 0000

09Eh

ADFM

ADCS2

ADCS1

ADCS0

ADNREF ADPREF1 ADPREF0 0000 -000 0000 -000

09Fh

Unimplemented

—

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: PIC16F/LF1827 only.

2: These registers can be addressed from any bank.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 31

PIC16F/LF1826/27

TABLE 3-8:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 2

100h⁽²⁾

INDF0

INDF1

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

101h⁽²⁾

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

102h⁽²⁾

103h⁽²⁾

104h⁽²⁾

105h⁽²⁾

106h⁽²⁾

107h⁽²⁾

108h⁽²⁾

109h⁽²⁾

10Ah⁽²⁾

10Bh⁽²⁾

10Ch

10Dh

10Eh

PCL

Program Counter (PC) Least Significant Byte

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

xx-x xxxx uu-u uuuu

xxxx xxxx uuuu uuuu

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

—

TO

PD

Z

DC

C

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

—

BSR4

BSR3

BSR2

BSR1

BSR0

WREG

PCLATH

INTCON

LATA

Working Register

—

Write Buffer for the upper 7 bits of the Program Counter

GIE

PEIE

LATA6

LATB6

TMR0IE

—

INTE

LATA4

LATB4

IOCIE

LATA3

LATB3

TMR0IF

LATA2

LATB2

INTF

LATA1

LATB1

IOCIF

LATA0

LATB0

LATA7

LATB

LATB7

LATB5

—

Unimplemented

C1ON

—

10Fh

—

110h

—

111h

CM1CON0

CM1CON1

CM2CON0

CM2CON1

CMOUT

BORCON

FVRCON

DACCON0

DACCON1

SRCON0

SRCON1

—

C1OUT

C1INTN

C2OUT

C2INTN

—

C1OE

C1PCH1

C2OE

C2PCH1

—

C1POL

C1PCH0

C2POL

C2PCH0

—

C1SP

—

C1HYS

C1SYNC 0000 -100 0000 -100

112h

C1INTP

C2ON

C1NCH1 C1NCH0 0000 --00 0000 --00

C2HYS C2SYNC 0000 -100 0000 -100

113h

C2SP

—

114h

C2INTP

—

C2NCH1 C2NCH0 0000 --00 0000 --00

MC2OUT MC1OUT ---- --00 ---- --00

115h

—

116h

SBOREN

FVREN

—

BORRDY 1--- ---q u--- ---u

117h

FVRRDY

DACLPS

—

Reserved

DACOE

—

Reserved

—

CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 0qrr 0000 0qrr 0000

118h

DACEN

—

DACPSS1 DACPSS0

—

DACNSS 000- 00-0 000- 00-0

DACR0 ---0 0000 ---0 0000

119h

DACR4

SRCLK0

SRSC1E

DACR3

SRQEN

SRRPE

DACR2

DACR1

SRPS

11Ah

SRLEN

SRCLK2

SRSCKE

SRCLK1

SRSC2E

SRNQEN

SRPR

0000 0000 0000 0000

11Bh

SRSPE

SRRCKE SRRC2E SRRC1E 0000 0000 0000 0000

11Ch

Unimplemented

—

11Dh

APFCON0

APFCON1

—

RXDTSEL

—

SDO1SEL

—

SS1SEL

—

P2BSEL⁽¹⁾CCP2SEL⁽¹⁾P1DSEL

P1CSEL CCP1SEL 0000 0000 0000 0000

TXCKSEL ---- ---0 ---- ---0

11Eh

—

11Fh

Unimplemented

—

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: PIC16F/LF1827 only.

2: These registers can be addressed from any bank.

DS41391C-page 32

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 3-8:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 3

180h⁽²⁾

INDF0

INDF1

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

181h⁽²⁾

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

182h⁽²⁾

183h⁽²⁾

184h⁽²⁾

185h⁽²⁾

186h⁽²⁾

187h⁽²⁾

188h⁽²⁾

189h⁽²⁾

18Ah⁽²⁾

18Bh⁽²⁾

18Ch

PCL

Program Counter (PC) Least Significant Byte

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

—

TO

PD

Z

DC

C

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

—

BSR4

BSR3

BSR2

BSR1

BSR0

IOCIF

WREG

PCLATH

INTCON

ANSELA

ANSELB

—

Working Register

—

Write Buffer for the upper 7 bits of the Program Counter

GIE

PEIE

—

TMR0IE

—

INTE

IOCIE

ANSA3

ANSB3

TMR0IF

ANSA2

ANSB2

INTF

—

ANSA4

ANSB4

ANSA1

ANSB1

ANSA0 ---1 1111 ---1 1111

18Dh

ANSB7

ANSB6

ANSB5

—

1111 111- 1111 111-

18Eh

Unimplemented

—

18Fh

—

190h

—

191h

EEADRL

EEADRH

EEDATL

EEDATH

EECON1

EECON2

—

EEPROM / Program Memory Address Register Low Byte

EEPROM / Program Memory Address Register High Byte

EEPROM / Program Memory Read Data Register Low Byte

0000 0000 0000 0000

-000 0000 -000 0000

xxxx xxxx uuuu uuuu

--xx xxxx --uu uuuu

0000 x000 0000 q000

0000 0000 0000 0000

192h

—

193h

194h

—

EEPROM / Program Memory Read Data Register High Byte

195h

EEPGD

CFGS

LWLO

FREE

WRERR

WREN

WR

RD

196h

EEPROM control register 2

Unimplemented

197h

—

198h

—

Unimplemented

199h

RCREG

TXREG

SPBRGL

SPBRGH

RCSTA

TXSTA

BAUDCON

USART Receive Data Register

USART Transmit Data Register

0000 0000 0000 0000

0000 000x 0000 000x

0000 0010 0000 0010

19Ah

19Bh

Baud Rate Generator Data Register Low

Baud Rate Generator Data Register High

19Ch

19Dh

SPEN

CSRC

RX9

TX9

SREN

TXEN

—

CREN

SYNC

SCKP

ADDEN

SENDB

BRG16

FERR

BRGH

—

OERR

TRMT

WUE

RX9D

TX9D

19Eh

19Fh

ABDOVF

RCIDL

ABDEN 01-0 0-00 01-0 0-00

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: PIC16F/LF1827 only.

2: These registers can be addressed from any bank.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 33

PIC16F/LF1826/27

TABLE 3-8:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 4

200h⁽²⁾

INDF0

INDF1

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

201h⁽²⁾

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

202h⁽²⁾

203h⁽²⁾

204h⁽²⁾

205h⁽²⁾

206h⁽²⁾

207h⁽²⁾

208h⁽²⁾

209h⁽²⁾

20Ah⁽²⁾

20Bh⁽²⁾

20Ch

PCL

Program Counter (PC) Least Significant Byte

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

--1- ---- --1- ----

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

—

TO

PD

Z

DC

C

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

—

BSR4

BSR3

BSR2

BSR1

BSR0

WREG

PCLATH

INTCON

WPUA

Working Register

—

Write Buffer for the upper 7 bits of the Program Counter

GIE

PEIE

—

TMR0IE

WPUA5

WPUB5

INTE

—

IOCIE

—

TMR0IF

—

INTF

—

IOCIF

—

20Dh

WPUB

WPUB7

WPUB6

WPUB4

WPUB3

WPUB2

WPUB1

WPUB0 1111 1111 1111 1111

20Eh

—

Unimplemented

—

20Fh

—

210h

—

211h

SSP1BUF

SSP1ADD

SSP1MSK

SSP1STAT

SSP1CON1

SSP1CON2

SSP1CON3

—

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

1111 1111 1111 1111

0000 0000 0000 0000

212h

ADD7

MSK7

SMP

ADD6

MSK6

ADD5

MSK5

D/A

ADD4

MSK4

P

ADD3

MSK3

S

ADD2

MSK2

R/W

ADD1

MSK1

UA

ADD0

MSK0

BF

213h

214h

CKE

215h

WCOL

GCEN

ACKTIM

SSPOV

ACKSTAT

PCIE

SSPEN

ACKDT

SCIE

CKP

SSPM3

RCEN

SDAHT

SSPM2

PEN

SSPM1

RSEN

AHEN

SSPM0 0000 0000 0000 0000

216h

ACKEN

BOEN

SEN

0000 0000 0000 0000

217h

SBCDE

DHEN

218h

Unimplemented

—

219h

SSP2BUF⁽¹⁾Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

1111 1111 1111 1111

0000 0000 0000 0000

21Ah

SSP2ADD⁽¹⁾

SSP2MSK⁽¹⁾

SSP2STAT⁽¹⁾

SSP2CON1⁽¹⁾

SSP2CON2⁽¹⁾

SSP2CON3⁽¹⁾

ADD7

MSK7

SMP

ADD6

MSK6

ADD5

MSK5

D/A

ADD4

MSK4

P

ADD3

MSK3

S

ADD2

MSK2

R/W

ADD1

MSK1

UA

ADD0

MSK0

BF

21Bh

21Ch

CKE

21Dh

WCOL

GCEN

ACKTIM

SSPOV

ACKSTAT

PCIE

SSPEN

ACKDT

SCIE

CKP

SSPM3

RCEN

SDAHT

SSPM2

PEN

SSPM1

RSEN

AHEN

SSPM0 0000 0000 0000 0000

21Eh

ACKEN

BOEN

SEN

0000 0000 0000 0000

21Fh

SBCDE

DHEN

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: PIC16F/LF1827 only.

2: These registers can be addressed from any bank.

DS41391C-page 34

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 3-8:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 5

280h⁽²⁾

INDF0

INDF1

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

281h⁽²⁾

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

282h⁽²⁾

283h⁽²⁾

284h⁽²⁾

285h⁽²⁾

286h⁽²⁾

287h⁽²⁾

288h⁽²⁾

289h⁽²⁾

28Ah⁽²⁾

28Bh⁽²⁾

28Ch

PCL

Program Counter (PC) Least Significant Byte

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

STATUS

FSR0L

—

TO

PD

Z

DC

C

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

FSR0H

FSR1L

FSR1H

BSR

—

BSR4

BSR3

BSR2

BSR1

INTF

BSR0

IOCIF

WREG

Working Register

PCLATH

INTCON

—

Write Buffer for the upper 7 bits of the Program Counter

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

Unimplemented

—

28Dh

—

28Eh

—

28Fh

—

290h

—

291h

CCPR1L

CCPR1H

CCP1CON

PWM1CON

CCP1AS

PSTR1CON

—

Capture/Compare/PWM Register 1 (LSB)

Capture/Compare/PWM Register 1 (MSB)

xxxx xxxx uuuu uuuu

292h

293h

P1M1

P1RSEN

CCP1ASE

—

P1M0

P1DC6

CCP1AS2

—

DC1B1

P1DC5

CCP1AS1

—

DC1B0

P1DC4

CCP1M3

P1DC3

CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000

P1DC2 P1DC1 P1DC0 0000 0000 0000 0000

294h

295h

CCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 0000 0000

296h

STR1SYNC

STR1D

STR1C

STR1B

STR1A

---0 0001 ---0 0001

297h

Unimplemented

—

298h

CCPR2L⁽¹⁾

CCPR2H⁽¹⁾

CCP2CON⁽¹⁾

PWM2CON⁽¹⁾

CCP2AS⁽¹⁾

PSTR2CON⁽¹⁾

CCPTMRS⁽¹⁾

—

Capture/Compare/PWM Register 2 (LSB)

Capture/Compare/PWM Register 2 (MSB)

xxxx xxxx uuuu uuuu

299h

29Ah

P2M1

P2RSEN

CCP2ASE

—

P2M0

P2DC6

CCP2AS2

—

DC2B1

P2DC5

CCP2AS1

—

DC2B0

P2DC4

CCP2M3

P2DC3

CCP2M2 CCP2M1 CCP2M0 0000 0000 0000 0000

P2DC2 P2DC1 P2DC0 0000 0000 0000 0000

29Bh

29Ch

CCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 0000 0000

29Dh

STR2SYNC

C3TSEL0

STR2D

STR2C

STR2B

STR2A

---0 0001 ---0 0001

29Eh

C4TSEL1

C4TSEL0

C3TSEL1

C2TSEL1 C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000

29Fh

Unimplemented

—

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: PIC16F/LF1827 only.

2: These registers can be addressed from any bank.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 35

PIC16F/LF1826/27

TABLE 3-8:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 6

300h⁽²⁾

INDF0

INDF1

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

301h⁽²⁾

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

302h⁽²⁾

303h⁽²⁾

304h⁽²⁾

305h⁽²⁾

306h⁽²⁾

307h⁽²⁾

308h⁽²⁾

309h⁽²⁾

30Ah⁽²⁾

30Bh⁽²⁾

30Ch

PCL

Program Counter (PC) Least Significant Byte

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

STATUS

—

TO

PD

Z

DC

C

FSR0L

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

FSR0H

FSR1L

FSR1H

BSR

—

BSR4

BSR3

BSR2

BSR1

INTF

BSR0

IOCIF

WREG

Working Register

PCLATH

—

Write Buffer for the upper 7 bits of the Program Counter

INTCON

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

—

Unimplemented

—

30Dh

—

30Eh

—

30Fh

—

310h

—

311h

CCPR3L⁽¹⁾

CCPR3H⁽¹⁾

Capture/Compare/PWM Register 3 (LSB)

Capture/Compare/PWM Register 3 (MSB)

xxxx xxxx uuuu uuuu

312h

313h

CCP3CON⁽¹⁾

—

DC3B1

DC3B0

CCP3M3

CCP3M2 CCP3M1 CCP3M0 --00 0000 --00 0000

314h

—

Unimplemented

—

315h

—

316h

—

317h

—

318h

CCPR4L⁽¹⁾

CCPR4H⁽¹⁾

Capture/Compare/PWM Register 4 (LSB)

Capture/Compare/PWM Register 4 (MSB)

xxxx xxxx uuuu uuuu

319h

31Ah

CCP4CON⁽¹⁾

—

DC4B1

DC4B0

CCP4M3

CCP4M2 CCP4M1 CCP4M0 --00 0000 --00 0000

31Bh

—

Unimplemented

—

31Ch

31Dh

31Eh

31Fh

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: PIC16F/LF1827 only.

2: These registers can be addressed from any bank.

DS41391C-page 36

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 3-8:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 7

380h⁽²⁾

INDF0

INDF1

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

381h⁽²⁾

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

382h⁽²⁾

383h⁽²⁾

384h⁽²⁾

385h⁽²⁾

386h⁽²⁾

387h⁽²⁾

388h⁽²⁾

389h⁽²⁾

38Ah⁽²⁾

38Bh⁽²⁾

38Ch

PCL

Program Counter (PC) Least Significant Byte

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

—

TO

PD

Z

DC

C

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

—

BSR4

BSR3

BSR2

BSR1

INTF

BSR0

IOCIF

WREG

PCLATH

INTCON

—

Working Register

—

Write Buffer for the upper 7 bits of the Program Counter

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

Unimplemented

IOCBP7

—

38Dh

—

38Eh

—

38Fh

—

390h

—

391h

—

392h

—

393h

—

394h

IOCBP

IOCBN

IOCBF

—

IOCBP6

IOCBN6

IOCBF6

IOCBP5

IOCBN5

IOCBF5

IOCBP4

IOCBN4

IOCBF4

IOCBP3

IOCBN3

IOCBF3

IOCBP2

IOCBN2

IOCBF2

IOCBP1

IOCBN1

IOCBF1

IOCBP0 0000 0000 0000 0000

IOCBN0 0000 0000 0000 0000

IOCBF0 0000 0000 0000 0000

395h

IOCBN7

396h

IOCBF7

397h

Unimplemented

CLKREN

—

398h

—

399h

—

39Ah

CLKRCON

—

CLKROE

CLKRSLR

CLKRDC1 CLKRDC0 CLKRDIV2 CLKRDIV1 CLKRDIV0 0011 0000 0011 0000

39Bh

Unimplemented

MDEN

—

39Ch

MDCON

MDSRC

MDCARL

MDCARH

MDOE

—

MDSLR

—

MDOPOL

—

MDBIT

MDMS0 x--- xxxx u--- uuuu

MDCL0 xxx- xxxx uuu- uuuu

0010 ---0 0010 ---0

39Dh

MDMSODIS

—

MDMS3

MDCL3

MDCH3

MDMS2

MDCL2

MDCH2

MDMS1

MDCL1

MDCH1

39Eh

MDCLODIS MDCLPOL MDCLSYNC

MDCHODIS MDCHPOL MDCHSYNC

39Fh

MDCH0 xxx- xxxx uuu- uuuu

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: PIC16F/LF1827 only.

2: These registers can be addressed from any bank.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 37

PIC16F/LF1826/27

TABLE 3-8:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 8

400h⁽²⁾

INDF0

INDF1

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

401h⁽²⁾

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

402h⁽²⁾

403h⁽²⁾

404h⁽²⁾

405h⁽²⁾

406h⁽²⁾

407h⁽²⁾

408h⁽²⁾

409h⁽²⁾

40Ah⁽²⁾

40Bh⁽²⁾

40Ch

PCL

Program Counter (PC) Least Significant Byte

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

—

TO

PD

Z

DC

C

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

—

BSR4

BSR3

BSR2

BSR1

INTF

BSR0

IOCIF

Working Register

—

Write Buffer for the upper 7 bits of the Program Counter

PEIE TMR0IE INTE IOCIE

GIE

TMR0IF

Unimplemented

—

40Dh

—

40Eh

—

40Fh

—

410h

—

411h

—

412h

—

413h

—

414h

—

415h

TMR4⁽¹⁾

PR4⁽¹⁾

T4CON⁽¹⁾

—

Timer4 Module Register

Timer4 Period Register

0000 0000 0000 0000

1111 1111 1111 1111

416h

417h

—

T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 -000 0000

418h

Unimplemented

—

419h

—

Unimplemented

41Ah

—

Unimplemented

41Bh

—

Unimplemented

41Ch

TMR6⁽¹⁾

PR6⁽¹⁾

T6CON⁽¹⁾

—

Timer6 Module Register

Timer6 Period Register

0000 0000 0000 0000

1111 1111 1111 1111

41Dh

41Eh

—

T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0 -000 0000 -000 0000

41Fh

Unimplemented

—

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: PIC16F/LF1827 only.

2: These registers can be addressed from any bank.

DS41391C-page 38

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 3-8:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Banks 9-30

x00h/

INDF0

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

x80h⁽²⁾

x00h/

INDF1

PCL

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

x81h⁽²⁾

x02h/

Program Counter (PC) Least Significant Byte

x82h⁽²⁾

x03h/

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

—

TO

PD

Z

DC

C

x83h⁽²⁾

x04h/

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

x84h⁽²⁾

x05h/

x85h⁽²⁾

x06h/

x86h⁽²⁾

x07h/

x87h⁽²⁾

x08h/

—

BSR4

BSR3

BSR2

BSR1

INTF

BSR0

IOCIF

x88h⁽²⁾

x09h/

WREG

PCLATH

INTCON

—

Working Register

x89h⁽²⁾

x0Ah/

—

Write Buffer for the upper 7 bits of the Program Counter

PEIE TMR0IE INTE IOCIE

x8Ah⁽²⁾

x0Bh/

GIE

TMR0IF

x8Bh⁽²⁾

x0Ch/

x8Ch

—

Unimplemented

—

x1Fh/

x9Fh

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: PIC16F/LF1827 only.

2: These registers can be addressed from any bank.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 39

PIC16F/LF1826/27

TABLE 3-8:

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Value on all

other

Resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 31

F80h⁽²⁾

INDF0

INDF1

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

F81h⁽²⁾

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

F82h⁽²⁾

F83h⁽²⁾

F84h⁽²⁾

F85h⁽²⁾

F86h⁽²⁾

F87h⁽²⁾

F88h⁽²⁾

F89h⁽²⁾

F8Ah⁽²⁾

F8Bh⁽²⁾

PCL

Program Counter (PC) Least Significant Byte

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

---0 0000 ---0 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

0000 000x 0000 000u

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

—

TO

PD

Z

DC

C

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

—

BSR4

BSR3

BSR2

BSR1

INTF

BSR0

IOCIF

WREG

PCLATH

INTCON

—

Working Register

—

Write Buffer for the upper 7 bits of the Program Counter

GIE

PEIE

TMR0IE

—

INTE

—

IOCIE

—

TMR0IF

F8Ch

—

FE3h

Unimplemented

—

FE4h

FE5h

FE6h

FE7h

FE8h

FE9h

FEAh

FEBh

STATUS_

—

Z

DC

C

---- -xxx ---- -uuu

0000 0000 uuuu uuuu

---x xxxx ---u uuuu

-xxx xxxx uuuu uuuu

xxxx xxxx uuuu uuuu

SHAD

WREG_

SHAD

Working Register Shadow

BSR_

SHAD

—

Bank Select Register Shadow

PCLATH_

SHAD

Program Counter Latch High Register Shadow

FSR0L_

SHAD

Indirect Data Memory Address 0 Low Pointer Shadow

Indirect Data Memory Address 0 High Pointer Shadow

Indirect Data Memory Address 1 Low Pointer Shadow

Indirect Data Memory Address 1 High Pointer Shadow

Unimplemented

FSR0H_

SHAD

FSR1L_

SHAD

FSR1H_

SHAD

FECh

FEDh

FEEh

—

Current Stack pointer

---1 1111 ---1 1111

xxxx xxxx uuuu uuuu

-xxx xxxx -uuu uuuu

STKPTR

TOSL

Top-of-Stack Low byte

Top-of-Stack High byte

FEFh

—

TOSH

Legend:

x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: PIC16F/LF1827 only.

2: These registers can be addressed from any bank.

DS41391C-page 40

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

3.3.3

COMPUTED FUNCTION CALLS

3.3

PCL and PCLATH

A computed function CALLallows programs to maintain

tables of functions and provide another way to execute

state machines or look-up tables. When performing a

table read using a computed function CALL, care

should be exercised if the table location crosses a PCL

memory boundary (each 256-byte block).

The Program Counter (PC) is 15 bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<14:8>) is not directly

readable or writable and comes from PCLATH. On any

Reset, the PC is cleared. Figure 3-4 shows the five

situations for the loading of the PC.

If using the CALLinstruction, the PCH<2:0> and PCL

registers are loaded with the operand of the CALL

instruction. PCH<6:3> is loaded with PCLATH<6:3>.

FIGURE 3-4:

LOADING OF PC IN

DIFFERENT SITUATIONS

The CALLWinstruction enables computed calls by com-

bining PCLATH and W to form the destination address.

A computed CALLWis accomplished by loading the W

register with the desired address and executing CALLW.

The PCL register is loaded with the value of W and

PCH is loaded with PCLATH.

14

0

Instruction with

PCL as

Destination

PCH

PCL

PC

8

7

6

0

ALU Result

PCLATH

14

0

PCH

PCL

3.3.4

BRANCHING

GOTO, CALL

PC

The branching instructions add an offset to the PC.

This allows relocatable code and code that crosses

page boundaries. There are two forms of branching,

BRW and BRA. The PC will have incremented to fetch

the next instruction in both cases. When using either

branching instruction, a PCL memory boundary may be

crossed.

4

11

6

0

PCLATH

OPCODE <10:0>

14

0

PCH

PCL

CALLW

PC

7

8

6

W

PCLATH

If using BRW, load the W register with the desired

unsigned address and execute BRW. The entire PC will

be loaded with the address PC + 1 + W.

14

0

PCH

PCL

BRW

PC

If using BRA, the entire PC will be loaded with PC + 1 +,

the signed value of the operand of the BRAinstruction.

15

PC + W

14

PCL

BRA

PC

15

PC + OPCODE <8:0>

3.3.1

MODIFYING PCL

Executing any instruction with the PCL register as the

destination simultaneously causes the Program Coun-

ter PC<14:8> bits (PCH) to be replaced by the contents

of the PCLATH register. This allows the entire contents

of the program counter to be changed by writing the

desired upper 7 bits to the PCLATH register. When the

lower 8 bits are written to the PCL register, all 15 bits of

the program counter will change to the values con-

tained in the PCLATH register and those being written

to the PCL register.

3.3.2

COMPUTED GOTO

A computed GOTOis accomplished by adding an offset to

the program counter (ADDWF PCL). When performing a

table read using a computed GOTOmethod, care should

be exercised if the table location crosses a PCL memory

boundary (each 256-byte block). Refer to the Application

Note AN556, “Implementing a Table Read” (DS00556).

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 41

PIC16F/LF1826/27

3.4.1

ACCESSING THE STACK

3.4

Stack

The stack is available through the TOSH, TOSL and

STKPTR registers. STKPTR is the current value of the

Stack Pointer. TOSH:TOSL register pair points to the

TOP of the stack. Both registers are read/writable. TOS

is split into TOSH and TOSL due to the 15-bit size of the

PC. To access the stack, adjust the value of STKPTR,

which will position TOSH:TOSL, then read/write to

TOSH:TOSL. STKPTR is 5 bits to allow detection of

overflow and underflow.

All devices have a 16-level x 15-bit wide hardware

stack (refer to Figures 3-5 through 3-8). The stack

space is not part of either program or data space. The

PC is PUSHed onto the stack when CALL or CALLW

instructions are executed or an interrupt causes a

branch. The stack is POPed in the event of a RETURN,

RETLWor a RETFIEinstruction execution. PCLATH is

not affected by a PUSH or POP operation.

The stack operates as a circular buffer if the STVREN

bit = 0 (Configuration Word 2). This means that after

the stack has been PUSHed sixteen times, the seven-

teenth PUSH overwrites the value that was stored from

the first PUSH. The eighteenth PUSH overwrites the

second PUSH (and so on). The STKOVF and STKUNF

flag bits will be set on an Overflow/Underflow, regard-

less of whether the Reset is enabled.

Note:

Care should be taken when modifying the

STKPTR while interrupts are enabled.

During normal program operation, CALL, CALLWand

Interrupts will increment STKPTR while RETLW,

RETURN, and RETFIEwill decrement STKPTR. At any

time STKPTR can be inspected to see how much stack

is left. The STKPTR always points at the currently used

place on the stack. Therefore, a CALL or CALLW will

increment the STKPTR and then write the PC, and a

return will unload the PC and then decrement STKPTR.

Note 1: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, CALLW, RETURN, RETLW and

RETFIE instructions or the vectoring to

an interrupt address.

Reference Figure 3-5 through Figure 3-8 for examples

of accessing the stack.

FIGURE 3-5:

ACCESSING THE STACK EXAMPLE 1

Stack Reset Disabled

STKPTR = 0x1F

0x0F

0x0E

0x0D

TOSH:TOSL

(STVREN = 0)

0x0C

0x0B

0x0A

0x09

0x08

Initial Stack Configuration:

After Reset, the stack is empty. The

empty stack is initialized so the Stack

Pointer is pointing at 0x1F. If the Stack

Overflow/Underflow Reset is enabled, the

TOSH/TOSL registers will return ‘0’. If

the Stack Overflow/Underflow Reset is

disabled, the TOSH/TOSL registers will

return the contents of stack address 0x0F.

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

0x1F

Stack Reset Enabled

(STVREN = 1)

STKPTR = 0x1F

0x0000

TOSH:TOSL

DS41391C-page 42

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 3-6:

ACCESSING THE STACK EXAMPLE 2

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

This figure shows the stack configuration

after the first CALL or a single interrupt.

If a RETURN instruction is executed, the

return address will be placed in the

Program Counter and the Stack Pointer

decremented to the empty state (0x1F).

0x07

0x06

0x05

0x04

0x03

0x02

0x01

STKPTR = 0x00

Return Address

0x00

TOSH:TOSL

FIGURE 3-7:

ACCESSING THE STACK EXAMPLE 3

0x0F

0x0E

0x0D

After seven CALLs, or six CALLs and an

interrupt, the stack looks like the figure

on the left. A series of RETURN instructions

will repeatedly place the return addresses

into the Program Counter and pop the stack.

0x0C

0x0B

0x0A

0x09

0x08

0x07

STKPTR = 0x06

Return Address

0x06

0x05

0x04

0x03

0x02

TOSH:TOSL

0x01

0x00

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 43

PIC16F/LF1826/27

FIGURE 3-8:

ACCESSING THE STACK EXAMPLE 4

Return Address

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

Return Address

When the stack is full, the next CALL or

interrupt will set the Stack Pointer to

0x10. This is identical to address 0x00

so the stack will wrap and overwrite the

return address at 0x00. If the Stack

Overflow/Underflow Reset is enabled, a

Reset will occur and location 0x00 will

not be overwritten.

Return Address

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

STKPTR = 0x10

TOSH:TOSL

3.4.2

OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Word 2 is set to ‘1’,

the device will be reset if the stack is PUSHed beyond

the sixteenth level or POPed beyond the first level,

setting the appropriate bits (STKOVF or STKUNF,

respectively) in the PCON register.

3.5

Indirect Addressing

The INDFn registers are not physical registers. Any

instruction that accesses an INDFn register actually

accesses the register at the address specified by the

File Select Registers (FSR). If the FSRn address

specifies one of the two INDFn registers, the read will

return ‘0’ and the write will not occur (though Status bits

may be affected). The FSRn register value is created

by the pair FSRnH and FSRnL.

The FSR registers form a 16-bit address that allows an

addressing space with 65536 locations. These locations

are divided into three memory regions:

• Traditional Data Memory

• Linear Data Memory

• Program Flash Memory

DS41391C-page 44

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 3-9:

INDIRECT ADDRESSING

0x0000

Traditional

Data Memory

0x0FFF

0x1000

0x1FFF

0x2000

Reserved

Linear

Data Memory

0x29AF

0x29B0

Reserved

0x0000

FSR

Address

Range

0x7FFF

0x8000

Program

Flash Memory

0xFFFF

0x7FFF

Note:

Not all memory regions are completely implemented. Consult device memory tables for memory limits.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 45

PIC16F/LF1826/27

3.5.1

TRADITIONAL DATA MEMORY

The traditional data memory is a region from FSR

address 0x000 to FSR address 0xFFF. The addresses

correspond to the absolute addresses of all SFR, GPR

and common registers.

FIGURE 3-10:

TRADITIONAL DATA MEMORY MAP

Direct Addressing

From Opcode

Indirect Addressing

4

BSR

6

7

FSRxH

0

7

FSRxL

0

0 0 0 0

Location Select

Bank Select

Location Select

0000 0001 0010

1111

0x00

0x7F

Bank 0 Bank 1 Bank 2

Bank 31

DS41391C-page 46

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

3.5.2

LINEAR DATA MEMORY

3.5.3

PROGRAM FLASH MEMORY

The linear data memory is the region from FSR

address 0x2000 to FSR address 0x29AF. This region is

a virtual region that points back to the 80-byte blocks of

GPR memory in all the banks.

To make constant data access easier, the entire

program Flash memory is mapped to the upper half of

the FSR address space. When the MSB of FSRnH is

set, the lower 15 bits are the address in program

memory which will be accessed through INDF. Only the

lower 8 bits of each memory location is accessible via

INDF. Writing to the program Flash memory cannot be

accomplished via the FSR/INDF interface. All

instructions that access program Flash memory via the

FSR/INDF interface will require one additional

instruction cycle to complete.

Unimplemented memory reads as 0x00. Use of the

linear data memory region allows buffers to be larger

than 80 bytes because incrementing the FSR beyond

one bank will go directly to the GPR memory of the next

bank.

The 16 bytes of common memory are not included in

the linear data memory region.

FIGURE 3-12:

PROGRAM FLASH

MEMORY MAP

FIGURE 3-11:

LINEAR DATA MEMORY

MAP

7

0

FSRnH

FSRnL

7

1

7

0

FSRnH

FSRnL

0 0 1

Location Select

0x8000

0x0000

Location Select

0x2000

0x020

Bank 0

0x06F

0x0A0

Bank 1

0x0EF

0x120

Program

Flash

Memory

(low 8

bits)

Bank 2

0x16F

0xF20

Bank 30

0x7FFF

0xFFFF

0xF6F

0x29AF

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 47

PIC16F/LF1826/27

NOTES:

DS41391C-page 48

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

4.0

DEVICE CONFIGURATION

Device Configuration consists of Configuration Word 1

and Configuration Word 2, Code Protection and Device

ID.

4.1

Configuration Words

There are several Configuration Word bits that allow

different oscillator and memory protection options.

These are implemented as Configuration Word 1 at

8007h and Configuration Word 2 at 8008h.

Note:

The DEBUG bit in Configuration Word is

managed automatically by device

development tools including debuggers and

programmers. For normal device operation,

this bit should be maintained as a '1'.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 49

PIC16F/LF1826/27

REGISTER 4-1:

CONFIGURATION WORD 1

R/P-1/1

FCMEN

bit 13

R/P-1/1

IESO

R/P-1/1

CPD

R/P-1/1

CP

CLKOUTEN

BOREN1

BOREN0

bit 7

bit 0

R/P-1/1

MCLRE

bit 6

R/P-1/1

PWRTE

R/P-1/1

WDTE1

R/P-1/1

WDTE0

R/P-1/1

FOSC2

R/P-1/1

FOSC1

R/P-1/1

FOSC0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘1’

-n/n = Value at POR and BOR/Value at all other Resets

P = Programmable bit

bit 13

bit 12

bit 11

FCMEN: Fail-Safe Clock Monitor Enable bit

1= Fail-Safe Clock Monitor is enabled

0= Fail-Safe Clock Monitor is disabled

IESO: Internal External Switchover bit

1= Internal/External Switchover mode is enabled

0= Internal/External Switchover mode is disabled

CLKOUTEN: Clock Out Enable bit

If FOSC configuration bits are set to LP, XT, HS modes:

This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin.

All other FOSC modes:

1= CLKOUT function is disabled. I/O function on the CLKOUT pin.

0= CLKOUT function is enabled on the CLKOUT pin

(1)

bit 10-9

BOREN<1:0>: Brown-out Reset Enable bits

11= BOR enabled

10= BOR enabled during operation and disabled in Sleep

01= BOR controlled by SBOREN bit of the BORCON register

00= BOR disabled

(2)

bit 8

bit 7

bit 6

CPD: Data Code Protection bit

1= Data memory code protection is disabled

0= Data memory code protection is enabled

(3)

CP: Code Protection bit

1= Program memory code protection is disabled

0= Program memory code protection is enabled

MCLRE: RA5/MCLR/VPP Pin Function Select bit

If LVP bit = 1:

This bit is ignored.

If LVP bit = 0:

1= MCLR/VPP pin function is MCLR; Weak pull-up enabled.

0= MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of

WPUA register.

(1)

bit 5

PWRTE: Power-up Timer Enable bit

1= PWRT disabled

0= PWRT enabled

bit 4-3

WDTE<1:0>: Watchdog Timer Enable bit

11= WDT enabled

10= WDT enabled while running and disabled in Sleep

01= WDT controlled by the SWDTEN bit in the WDTCON register

00= WDT disabled

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: The entire data EEPROM will be erased when the code protection is turned off during an erase.

3: The entire program memory will be erased when the code protection is turned off.

DS41391C-page 50

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

REGISTER 4-1:

CONFIGURATION WORD 1 (CONTINUED)

bit 2-0

FOSC<2:0>: Oscillator Selection bits

111= ECH: External Clock, High-Power mode (4-32 MHz): device clock supplied to CLKIN pin

110= ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin

101= ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin

100= INTOSC oscillator: I/O function on CLKIN pin

011= EXTRC oscillator: External RC circuit connected to CLKIN pin

010= HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins

001= XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins

000= LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: The entire data EEPROM will be erased when the code protection is turned off during an erase.

3: The entire program memory will be erased when the code protection is turned off.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 51

PIC16F/LF1826/27

REGISTER 4-2:

CONFIGURATION WORD 2

R/P-1/1

U-1

—

R/P-1/1

BORV

R/P-1/1

PLLEN

U-1

—

(1)

(2)

LVP

DEBUG

STVREN

bit 13

bit 7

bit 0

U-1

—

U-1

—

R/P-1/1

U-1

—

U-1

—

R/P-1/1

WRT1

R/P-1/1

WRT0

Reserved

bit 6

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘1’

-n/n = Value at POR and BOR/Value at all other Resets

P = Programmable bit

(1)

bit 13

bit 12

LVP: Low-Voltage Programming Enable bit

1= Low-voltage programming enabled

0= High-voltage on MCLR must be used for programming

(2)

DEBUG: In-Circuit Debugger Mode bit

1= In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins

0= In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger

bit 11

bit 10

Unimplemented: Read as ‘1’

BORV: Brown-out Reset Voltage Selection bit

1= Brown-out Reset voltage set to 1.9V (typical)

0= Brown-out Reset voltage set to 2.5V (typical)

bit 9

bit 8

STVREN: Stack Overflow/Underflow Reset Enable bit

1= Stack Overflow or Underflow will cause a Reset

0= Stack Overflow or Underflow will not cause a Reset

PLLEN: PLL Enable bit

1= 4xPLL enabled

0= 4xPLL disabled

bit 7-5

bit 4

Unimplemented: Read as ‘1’

Reserved: This location should be programmed to a ‘1’.

Unimplemented: Read as ‘1’

bit 3-2

bit 1-0

WRT<1:0>: Flash Memory Self-Write Protection bits

2 kW Flash memory (PIC16F/LF1826 only):

11= Write protection off

10= 000h to 1FFh write-protected, 200h to 7FFh may be modified by EECON control

01= 000h to 3FFh write-protected, 400h to 7FFh may be modified by EECON control

00= 000h to 7FFh write-protected, no addresses may be modified by EECON control

4 kW Flash memory (PIC16F/LF1827 only):

11= Write protection off

10= 000h to 1FFh write-protected, 200h to FFFh may be modified by EECON control

01= 000h to 7FFh write-protected, 800h to FFFh may be modified by EECON control

00= 000h to FFFh write-protected, no addresses may be modified by EECON control

Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.

2: The DEBUG bit in Configuration Word is managed automatically by device development tools including debuggers and

programmers. For normal device operation, this bit should be maintained as a '1'.

DS41391C-page 52

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

4.2

Code Protection

Code protection allows the device to be protected from

unauthorized access. Program memory protection and

data EEPROM protection are controlled independently.

Internal access to the program memory and data

EEPROM are unaffected by any code protection

setting.

4.2.1

PROGRAM MEMORY PROTECTION

The entire program memory space is protected from

external reads and writes by the CP bit in Configuration

Word 1. When CP = 0, external reads and writes of

program memory are inhibited and a read will return all

‘0’s. The CPU can continue to read program memory,

regardless of the protection bit settings. Writing the

program memory is dependent upon the write

protection

setting.

See

Section 4.3

“Write

Protection” for more information.

4.2.2

DATA EEPROM PROTECTION

The entire data EEPROM is protected from external

reads and writes by the CPD bit. When CPD = 0, exter-

nal reads and writes of data EEPROM are inhibited.

The CPU can continue to read and write data EEPROM

regardless of the protection bit settings.

4.3

Write Protection

Write protection allows the device to be protected from

unintended self-writes. Applications, such as boot-

loader software, can be protected while allowing other

regions of the program memory to be modified.

The WRT<1:0> bits in Configuration Word 2 define the

size of the program memory block that is protected.

4.4

User ID

Four memory locations (8000h-8003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

readable and writable during normal execution. See

Section 11.5 “User ID, Device ID and Configuration

Word Access” for more information on accessing

these memory locations. For more information on

checksum calculation, see the “PIC16F/LF1826/27

Memory Programming Specification” (DS41390).

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 53

PIC16F/LF1826/27

4.5

Device ID and Revision ID

The memory location 8006h is where the Device ID and

Revision ID are stored. The upper nine bits hold the

Device ID. The lower five bits hold the Revision ID. See

Section 11.5 “User ID, Device ID and Configuration

Word Access” for more information on accessing

these memory locations.

Development tools, such as device programmers and

debuggers, may be used to read the Device ID and

Revision ID.

REGISTER 4-3:

DEVICEID: DEVICE ID REGISTER⁽¹⁾

R/P-1

DEV8

R/P-1

DEV7

R/P-1

DEV6

R/P-1

DEV5

R/P-1

DEV4

R/P-1

DEV3

R/P-1

DEV2

bit 13

bit 7

bit 0

R/P-1

DEV1

R/P-1

DEV0

R/P-1

REV4

R/P-1

REV3

R/P-1

REV2

R/P-1

REV1

R/P-1

REV0

bit 6

Legend:

P = Programmable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

R = Readable bit

-n = Value at POR

x = Bit is unknown

bit 13-5

bit 4-0

DEV<8:0>: Device ID bits

100111100= PIC16F1826

100111101= PIC16F1827

101000100= PIC16LF1826

101000101= PIC16LF1827

REV<4:0>: Revision ID bits

These bits are used to identify the revision.

Note 1: This location cannot be written.

DS41391C-page 54

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

The oscillator module can be configured in one of eight

clock modes.

5.0

5.1

OSCILLATOR MODULE (WITH

FAIL-SAFE CLOCK MONITOR)

1. ECL – External Clock Low Power mode

(0 MHz to 0.5 MHz)

Overview

2. ECM – External Clock Medium Power mode

(0.5 MHz to 4 MHz)

The oscillator module has a wide variety of clock

sources and selection features that allow it to be used

in a wide range of applications while maximizing perfor-

mance and minimizing power consumption. Figure 5-1

illustrates a block diagram of the oscillator module.

3. ECH – External Clock High Power mode

(4 MHz to 32 MHz)

4. LP – 32 kHz Low-Power Crystal mode.

5. XT – Medium Gain Crystal or Ceramic Resonator

Oscillator mode (up to 4 MHz)

Clock sources can be supplied from external oscillators,

quartz crystal resonators, ceramic resonators and

Resistor-Capacitor (RC) circuits. In addition, the system

clock source can be supplied from one of two internal

oscillators and PLL circuits, with a choice of speeds

selectable via software. Additional clock features

include:

6. HS – High Gain Crystal or Ceramic Resonator

mode (4 MHz to 20 MHz)

7. RC – External Resistor-Capacitor (RC).

8. INTOSC – Internal oscillator (31 kHz to 32 MHz).

Clock Source modes are selected by the FOSC<2:0>

bits in the Configuration Word 1. The FOSC bits

determine the type of oscillator that will be used when

the device is first powered.

• Selectable system clock source between external

or internal sources via software.

• Two-Speed Start-up mode, which minimizes

latency between external oscillator start-up and

code execution.

The EC clock mode relies on an external logic level

signal as the device clock source. The LP, XT, and HS

clock modes require an external crystal or resonator to

be connected to the device. Each mode is optimized for

a different frequency range. The RC clock mode

requires an external resistor and capacitor to set the

oscillator frequency.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP,

XT, HS, EC or RC modes) and switch

automatically to the internal oscillator.

• Oscillator Start-up Timer (OST) ensures stability

of crystal oscillator sources

The INTOSC internal oscillator block produces low,

medium, and high frequency clock sources, designated

LFINTOSC, MFINTOSC, and HFINTOSC. (see

Internal Oscillator Block, Figure 5-1). A wide selection

of device clock frequencies may be derived from these

three clock sources.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 55

PIC16F/LF1826/27

FIGURE 5-1:

SIMPLIFIED PIC^®MCU CLOCK SOURCE BLOCK DIAGRAM

External

Oscillator

LP, XT, HS, RC, EC

OSC2

Sleep

4 x PLL

Sleep

OSC1

Timer1

CPU and

Oscillator

T1OSC

FOSC<2:0> = 100

T1OSO

Peripherals

T1OSCEN

Enable

Oscillator

IRCF<3:0>

T1OSI

Internal Oscillator

16 MHz

8 MHz

4 MHz

Internal

Oscillator

Block

2 MHz

Clock

1 MHz

Control

HFPLL

500 kHz

250 kHz

125 kHz

62.5 kHz

31.25 kHz

16 MHz

(HFINTOSC)

FOSC<2:0> SCS<1:0>

500 kHz

Source

500 kHz

(MFINTOSC)

Clock Source Option

for other modules

31 kHz

Source

31 kHz

31 kHz (LFINTOSC)

WDT, PWRT, Fail-Safe Clock Monitor

Two-Speed Start-up and other modules

DS41391C-page 56

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in

operation after a Power-on Reset (POR) or wake-up

from Sleep. Because the PIC^®MCU design is fully

static, stopping the external clock input will have the

effect of halting the device while leaving all data intact.

Upon restarting the external clock, the device will

resume operation as if no time had elapsed.

5.2

Clock Source Types

Clock sources can be classified as external or internal.

External clock sources rely on external circuitry for the

clock source to function. Examples are: oscillator mod-

ules (EC mode), quartz crystal resonators or ceramic

resonators (LP, XT and HS modes) and Resis-

tor-Capacitor (RC) mode circuits.

Internal clock sources are contained internally within

the oscillator module. The internal oscillator block has

FIGURE 5-2:

EXTERNAL CLOCK (EC)

MODE OPERATION

two

internal

oscillators

and

a

dedicated

phase-locked-loop (HFPLL) that are used to generate

three internal system clock sources: the 16 MHz

High-Frequency Internal Oscillator (HFINTOSC), 500

kHZ (MFINTOSC) and the 31 kHz Low-Frequency

Internal Oscillator (LFINTOSC).

OSC1/CLKIN

PIC^®MCU

Clock from

Ext. System

OSC2/CLKOUT

(1)

FOSC/4 or

The system clock can be selected between external or

internal clock sources via the System Clock Select

(SCS) bits in the OSCCON register. See Section 5.3

“Clock Switching” for additional information.

I/O

Note 1: Output depends upon CLKOUTEN bit of the

Configuration Word 1.

5.2.1

EXTERNAL CLOCK SOURCES

5.2.1.2

LP, XT, HS Modes

An external clock source can be used as the device

system clock by performing one of the following

actions:

The LP, XT and HS modes support the use of quartz

crystal resonators or ceramic resonators connected to

OSC1 and OSC2 (Figure 5-3). The three modes select

a low, medium or high gain setting of the internal

inverter-amplifier to support various resonator types

and speed.

• Program the FOSC<2:0> bits in the Configuration

Word 1 to select an external clock source that will

be used as the default system clock upon a

device Reset.

LP Oscillator mode selects the lowest gain setting of the

internal inverter-amplifier. LP mode current consumption

is the least of the three modes. This mode is designed to

drive only 32.768 kHz tuning-fork type crystals (watch

crystals).

• Write the SCS<1:0> bits in the OSCCON register

to switch the system clock source to:

- Timer1 Oscillator during run-time, or

- An external clock source determined by the

value of the FOSC bits.

XT Oscillator mode selects the intermediate gain

setting of the internal inverter-amplifier. XT mode

current consumption is the medium of the three modes.

This mode is best suited to drive resonators with a

medium drive level specification.

See Section 5.3 “Clock Switching”for more informa-

tion.

5.2.1.1

EC Mode

The External Clock (EC) mode allows an externally

generated logic level signal to be the system clock

source. When operating in this mode, an external clock

source is connected to the OSC1 input.

OSC2/CLKOUT is available for general purpose I/O or

CLKOUT. Figure 5-2 shows the pin connections for EC

mode.

HS Oscillator mode selects the highest gain setting of the

internal inverter-amplifier. HS mode current consumption

is the highest of the three modes. This mode is best

suited for resonators that require a high drive setting.

Figure 5-3 and Figure 5-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

EC mode has 3 power modes to select from through

Configuration Word 1:

• High-power, 4-32 MHz (FOSC = 111)

• Medium power, 0.5-4 MHz (FOSC = 110)

• Low-power, 0-0.5 MHz (FOSC = 101)

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 57

PIC16F/LF1826/27

FIGURE 5-3:

QUARTZ CRYSTAL

OPERATION (LP, XT OR

HS MODE)

FIGURE 5-4:

CERAMIC RESONATOR

OPERATION

(XT OR HS MODE)

PIC^®MCU

OSC1/CLKIN

C1

To Internal

Logic

To Internal

Logic

Quartz

Crystal

(2)

Sleep

RF

(3)

(2)

RP

RF

Sleep

OSC2/CLKOUT

(1)

C2

RS

OSC2/CLKOUT

(1)

C2

RS

Ceramic

Resonator

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

ceramic resonators with low drive level.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 M to 10 M.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 M to 10 M.

3: An additional parallel feedback resistor (RP)

may be required for proper ceramic resonator

operation.

Note 1: Quartz crystal characteristics vary according

to type, package and manufacturer. The

user should consult the manufacturer data

sheets for specifications and recommended

application.

5.2.1.3

Oscillator Start-up Timer (OST)

If the oscillator module is configured for LP, XT or HS

modes, the Oscillator Start-up Timer (OST) counts

1024 oscillations from OSC1. This occurs following a

Power-on Reset (POR) and when the Power-up Timer

(PWRT) has expired (if configured), or a wake-up from

Sleep. During this time, the program counter does not

increment and program execution is suspended. The

OST ensures that the oscillator circuit, using a quartz

crystal resonator or ceramic resonator, has started and

is providing a stable system clock to the oscillator

module.

2: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC^®and PIC^®

Devices” (DS00826)

• AN849, “Basic PIC^®Oscillator Design”

(DS00849)

• AN943, “Practical PIC^®Oscillator

In order to minimize latency between external oscillator

start-up and code execution, the Two-Speed Clock

Start-up mode can be selected (see Section 5.4

“Two-Speed Clock Start-up Mode”).

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”

(DS00949)

5.2.1.4

4X PLL

The oscillator module contains a 4X PLL that can be

used with both external and internal clock sources to

provide a system clock source. The input frequency for

the 4X PLL must fall within specifications. See the PLL

Clock Timing Specifications in Section 29.0

“Electrical Specifications”

The 4X PLL may be enabled for use by one of two

methods:

1. Program the PLLEN bit in Configuration Word 2

to a ‘1’.

2. Write the SPLLEN bit in the OSCCON register to

a ‘1’. If the PLLEN bit in Configuration Word 2 is

programmed to a ‘1’, then the value of SPLLEN

is ignored.

DS41391C-page 58

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

5.2.1.5

TIMER1 Oscillator

5.2.1.6

External RC Mode

The Timer1 Oscillator is a separate crystal oscillator

that is associated with the Timer1 peripheral. It is opti-

mized for timekeeping operations with a 32.768 kHz

crystal connected between the T1OSO and T1OSI

device pins.

The external Resistor-Capacitor (RC) modes support

the use of an external RC circuit. This allows the

designer maximum flexibility in frequency choice while

keeping costs to a minimum when clock accuracy is not

required.

The Timer1 Oscillator can be used as an alternate sys-

tem clock source and can be selected during run-time

using clock switching. Refer to Section 5.3 “Clock

Switching” for more information.

The RC circuit connects to OSC1. OSC2/CLKOUT is

available for general purpose I/O or CLKOUT. The

function of the OSC2/CLKOUT pin is determined by the

state of the CLKOUTEN bit in Configuration Word 1.

Figure 5-5 shows the external RC mode connections.

FIGURE 5-5:

QUARTZ CRYSTAL

OPERATION (TIMER1

OSCILLATOR)

FIGURE 5-6:

EXTERNAL RC MODES

VDD

PIC^®MCU

REXT

OSC1/CLKIN

Internal

Clock

T1OSI

C1

To Internal

Logic

CEXT

VSS

32.768 kHz

Quartz

Crystal

OSC2/CLKOUT

(1)

FOSC/4 or I/O

T1OSO

C2

Recommended values: 10 k  REXT  100 k, <3V

3 k  REXT  100 k, 3-5V

CEXT > 20 pF, 2-5V

Note 1: Quartz crystal characteristics vary according

to type, package and manufacturer. The

user should consult the manufacturer data

sheets for specifications and recommended

application.

Note 1: Output depends upon CLKOUTEN bit of the

Configuration Word 1.

The RC oscillator frequency is a function of the supply

voltage, the resistor (REXT) and capacitor (CEXT) values

and the operating temperature. Other factors affecting

the oscillator frequency are:

2: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

• threshold voltage variation

• component tolerances

• packaging variations in capacitance

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC^®and PIC^®

Devices” (DS00826)

The user also needs to take into account variation due

to tolerance of external RC components used.

• AN849, “Basic PIC^®Oscillator Design”

(DS00849)

• AN943, “Practical PIC^®Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”

(DS00949)

• TB097, “Interfacing a Micro Crystal

MS1V-T1K 32.768 kHz Tuning Fork

Crystal to a PIC16F690/SS” (DS91097)

• AN1288, “Design Practices for

Low-Power External Oscillators”

(DS01288)

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 59

PIC16F/LF1826/27

5.2.2

INTERNAL CLOCK SOURCES

5.2.2.1

HFINTOSC

The device may be configured to use the internal oscil-

lator block as the system clock by performing one of the

following actions:

The High-Frequency Internal Oscillator (HFINTOSC) is

a factory calibrated 16 MHz internal clock source. The

frequency of the HFINTOSC can be altered via

software using the OSCTUNE register (Register 5-3).

• Program the FOSC<2:0> bits in Configuration

Word 1 to select the INTOSC clock source, which

will be used as the default system clock upon a

device Reset.

The output of the HFINTOSC connects to a postscaler

and multiplexer (see Figure 5-1). One of nine

frequencies derived from the HFINTOSC can be

selected via software using the IRCF<3:0> bits of the

OSCCON register. See Section 5.2.2.7 “Internal

Oscillator Clock Switch Timing” for more information.

• Write the SCS<1:0> bits in the OSCCON register

to switch the system clock source to the internal

oscillator during run-time. See Section 5.3

“Clock Switching”for more information.

The HFINTOSC is enabled by:

In INTOSC mode, OSC1/CLKIN is available for general

purpose I/O. OSC2/CLKOUT is available for general

purpose I/O or CLKOUT.

• Configure the IRCF<3:0> bits of the OSCCON

register for the desired HF frequency, and

• FOSC<2:0> = 100, or

The function of the OSC2/CLKOUT pin is determined

by the state of the CLKOUTEN bit in Configuration

Word 1.

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘1x’.

The High Frequency Internal Oscillator Ready bit

(HFIOFR) of the OSCSTAT register indicates when the

HFINTOSC is running and can be utilized.

The internal oscillator block has two independent

oscillators and a dedicated Phase-Locked Loop,

HFPLL that can produce one of three internal system

clock sources.

The High Frequency Internal Oscillator Status Locked

bit (HFIOFL) of the OSCSTAT register indicates when

the HFINTOSC is running within 2% of its final value.

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates at

16 MHz. The HFINTOSC source is generated

from the 500 kHz MFINTOSC source and the

dedicated Phase-Locked Loop, HFPLL. The

frequency of the HFINTOSC can be

user-adjusted via software using the OSCTUNE

register (Register 5-3).

The High Frequency Internal Oscillator Status Stable

bit (HFIOFS) of the OSCSTAT register indicates when

the HFINTOSC is running within 0.5% of its final value.

5.2.2.2

The

MFINTOSC

Medium-Frequency

Internal

Oscillator

(MFINTOSC) is a factory calibrated 500 kHz internal

clock source. The frequency of the MFINTOSC can be

altered via software using the OSCTUNE register

(Register 5-3).

2. The MFINTOSC (Medium-Frequency Internal

Oscillator) is factory calibrated and operates at

500 kHz. The frequency of the MFINTOSC can

be user-adjusted via software using the

OSCTUNE register (Register 5-3).

The output of the MFINTOSC connects to a postscaler

and multiplexer (see Figure 5-1). One of nine

frequencies derived from the MFINTOSC can be

selected via software using the IRCF<3:0> bits of the

OSCCON register. See Section 5.2.2.7 “Internal

Oscillator Clock Switch Timing” for more information.

3. The LFINTOSC (Low-Frequency Internal

Oscillator) is uncalibrated and operates at

31 kHz.

The MFINTOSC is enabled by:

• Configure the IRCF<3:0> bits of the OSCCON

register for the desired HF frequency, and

• FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘1x’

The Medium Frequency Internal Oscillator Ready bit

(MFIOFR) of the OSCSTAT register indicates when the

MFINTOSC is running and can be utilized.

DS41391C-page 60

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

5.2.2.3

Internal Oscillator Frequency

Adjustment

5.2.2.5

Internal Oscillator Frequency

Selection

The 500 kHz internal oscillator is factory calibrated.

This internal oscillator can be adjusted in software by

writing to the OSCTUNE register (Register 5-3). Since

the HFINTOSC and MFINTOSC clock sources are

derived from the 500 kHz internal oscillator a change in

the OSCTUNE register value will apply to both.

The system clock speed can be selected via software

using the Internal Oscillator Frequency Select bits

IRCF<3:0> of the OSCCON register.

The output of the 16 MHz HFINTOSC and 31 kHz

LFINTOSC connects to a postscaler and multiplexer

(see Figure 5-1). The Internal Oscillator Frequency

Select bits IRCF<3:0> of the OSCCON register select

the frequency output of the internal oscillators. One of

the following frequencies can be selected via software:

The default value of the OSCTUNE register is ‘0’. The

value is a 6-bit two’s complement number. A value of

1Fh will provide an adjustment to the maximum

frequency. A value of 20h will provide an adjustment to

the minimum frequency.

• 32 MHz (requires 4X PLL)

• 16 MHz

When the OSCTUNE register is modified, the oscillator

frequency will begin shifting to the new frequency. Code

execution continues during this shift. There is no

indication that the shift has occurred.

• 8 MHz

• 4 MHz

• 2 MHz

• 1 MHz

OSCTUNE does not affect the LFINTOSC frequency.

Operation of features that depend on the LFINTOSC

clock source frequency, such as the Power-up Timer

(PWRT), Watchdog Timer (WDT), Fail-Safe Clock

Monitor (FSCM) and peripherals, are not affected by the

change in frequency.

• 500 kHz (Default after Reset)

• 250 kHz

• 125 kHz

• 62.5 kHz

• 31.25 kHz

• 31 kHz (LFINTOSC)

5.2.2.4

LFINTOSC

Note:

Following any Reset, the IRCF<3:0> bits of

the OSCCON register are set to ‘0111’ and

the frequency selection is set to 500 kHz.

The user can modify the IRCF bits to

select a different frequency.

The Low-Frequency Internal Oscillator (LFINTOSC) is

an uncalibrated 31 kHz internal clock source.

The output of the LFINTOSC connects to a postscaler

and multiplexer (see Figure 5-1). Select 31 kHz, via

software, using the IRCF<3:0> bits of the OSCCON

register. See Section 5.2.2.7 “Internal Oscillator

Clock Switch Timing” for more information. The

LFINTOSC is also the frequency for the Power-up Timer

(PWRT), Watchdog Timer (WDT) and Fail-Safe Clock

Monitor (FSCM).

The IRCF<3:0> bits of the OSCCON register allow

duplicate selections for some frequencies. These dupli-

cate choices can offer system design trade-offs. Lower

power consumption can be obtained when changing

oscillator sources for a given frequency. Faster transi-

tion times can be obtained between frequency changes

that use the same oscillator source.

The LFINTOSC is enabled by selecting 31 kHz

(IRCF<3:0> bits of the OSCCON register = 000)as the

system clock source (SCS bits of the OSCCON

register = 1x), or when any of the following are

enabled:

• Configure the IRCF<3:0> bits of the OSCCON

register for the desired LF frequency, and

• FOSC<2:0> = 100, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘1x’

Peripherals that use the LFINTOSC are:

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor (FSCM)

The Low Frequency Internal Oscillator Ready bit

(LFIOFR) of the OSCSTAT register indicates when the

LFINTOSC is running and can be utilized.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 61

PIC16F/LF1826/27

5.2.2.6

32 MHz Internal Oscillator

Frequency Selection

5.2.2.7

Internal Oscillator Clock Switch

Timing

The Internal Oscillator Block can be used with the 4X

PLL associated with the External Oscillator Block to

produce a 32 MHz internal system clock source. The

following settings are required to use the 32 MHz inter-

nal clock source:

When switching between the HFINTOSC, MFINTOSC

and the LFINTOSC, the new oscillator may already be

shut down to save power (see Figure 5-6). If this is the

case, there is a delay after the IRCF<3:0> bits of the

OSCCON register are modified before the frequency

selection takes place. The OSCSTAT register will

reflect the current active status of the HFINTOSC,

MFINTOSC and LFINTOSC oscillators. The sequence

of a frequency selection is as follows:

• The FOSC bits in Configuration Word 1 must be

set to use the INTOSC source as the device sys-

tem clock (FOSC<2:0> = 100).

• The SCS bits in the OSCCON register must be

cleared to use the clock determined by

FOSC<2:0> in Configuration Word 1

(SCS<1:0> = 00).

1. IRCF<3:0> bits of the OSCCON register are

modified.

2. If the new clock is shut down, a clock start-up

delay is started.

• The IRCF bits in the OSCCON register must be

set to the 8 MHz HFINTOSC set to use

(IRCF<3:0> = 1110).

3. Clock switch circuitry waits for a falling edge of

the current clock.

• The SPLLEN bit in the OSCCON register must be

set to enable the 4xPLL, or the PLLEN bit of the

Configuration Word 2 must be programmed to a

‘1’.

4. The current clock is held low and the clock

switch circuitry waits for a rising edge in the new

clock.

5. The new clock is now active.

Note:

When using the PLLEN bit of the

Configuration Word 2, the 4xPLL cannot

be disabled by software and the 8 MHz

HFINTOSC option will no longer be

available.

6. The OSCSTAT register is updated as required.

7. Clock switch is complete.

See Figure 5-6 for more details.

If the internal oscillator speed is switched between two

clocks of the same source, there is no start-up delay

before the new frequency is selected. Clock switching

time delays are shown in Table 5-1.

The 4xPLL is not available for use with the internal

oscillator when the SCS bits of the OSCCON register

are set to ‘1x’. The SCS bits must be set to ‘00’ to use

the 4xPLL with the internal oscillator.

Start-up delay specifications are located in the

oscillator tables of Section 29.0 “Electrical

Specifications”.

DS41391C-page 62

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 5-7:

INTERNAL OSCILLATOR SWITCH TIMING

HFINTOSC/

MFINTOSC

LFINTOSC (FSCM and WDT disabled)

HFINTOSC/

MFINTOSC

Start-up Time

2-cycle Sync

Running

LFINTOSC

0

0

IRCF <3:0>

System Clock

HFINTOSC/

MFINTOSC

LFINTOSC (Either FSCM or WDT enabled)

HFINTOSC/

MFINTOSC

2-cycle Sync

Running

LFINTOSC

IRCF <3:0>

0

0

System Clock

LFINTOSC

HFINTOSC/MFINTOSC

LFINTOSC turns off unless WDT or FSCM is enabled

Running

LFINTOSC

Start-up Time 2-cycle Sync

HFINTOSC/

MFINTOSC

= 0

 0

IRCF <3:0>

System Clock

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 63

PIC16F/LF1826/27

5.3.3

TIMER1 OSCILLATOR

5.3

Clock Switching

The Timer1 Oscillator is a separate crystal oscillator

associated with the Timer1 peripheral. It is optimized

for timekeeping operations with a 32.768 kHz crystal

connected between the T1OSO and T1OSI device

pins.

The system clock source can be switched between

external and internal clock sources via software using

the System Clock Select (SCS) bits of the OSCCON

register. The following clock sources can be selected

using the SCS bits:

The Timer1 oscillator is enabled using the T1OSCEN

control bit in the T1CON register. See Section 21.0

“Timer1 Module with Gate Control” for more

information about the Timer1 peripheral.

• Default system oscillator determined by FOSC

bits in Configuration Word 1

• Timer1 32 kHz crystal oscillator

• Internal Oscillator Block (INTOSC)

5.3.4

TIMER1 OSCILLATOR READY

(T1OSCR) BIT

5.3.1

SYSTEM CLOCK SELECT (SCS)

BITS

The user must ensure that the Timer1 Oscillator is

ready to be used before it is selected as a system clock

source. The Timer1 Oscillator Ready (T1OSCR) bit of

the OSCSTAT register indicates whether the Timer1

oscillator is ready to be used. After the T1OSCR bit is

set, the SCS bits can be configured to select the Timer1

oscillator.

The System Clock Select (SCS) bits of the OSCCON

register selects the system clock source that is used for

the CPU and peripherals.

• When the SCS bits of the OSCCON register = 00,

the system clock source is determined by value of

the FOSC<2:0> bits in the Configuration Word 1.

• When the SCS bits of the OSCCON register = 01,

the system clock source is the Timer1 oscillator.

• When the SCS bits of the OSCCON register = 1x,

the system clock source is chosen by the internal

oscillator frequency selected by the IRCF<3:0>

bits of the OSCCON register. After a Reset, the

SCS bits of the OSCCON register are always

cleared.

Note:

Any automatic clock switch, which may

occur from Two-Speed Start-up or Fail-Safe

Clock Monitor, does not update the SCS

bits of the OSCCON register. The user can

monitor the OSTS bit of the OSCSTAT

register to determine the current system

clock source.

When switching between clock sources, a delay is

required to allow the new clock to stabilize. These oscil-

lator delays are shown in Table 5-1.

5.3.2

OSCILLATOR START-UP TIME-OUT

STATUS (OSTS) BIT

The Oscillator Start-up Time-out Status (OSTS) bit of

the OSCSTAT register indicates whether the system

clock is running from the external clock source, as

defined by the FOSC<2:0> bits in the Configuration

Word 1, or from the internal clock source. In particular,

OSTS indicates that the Oscillator Start-up Timer

(OST) has timed out for LP, XT or HS modes. The OST

does not reflect the status of the Timer1 Oscillator.

DS41391C-page 64

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

5.4.1

TWO-SPEED START-UP MODE

CONFIGURATION

5.4

Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power

savings by minimizing the latency between external

oscillator start-up and code execution. In applications

that make heavy use of the Sleep mode, Two-Speed

Start-up will remove the external oscillator start-up

time from the time spent awake and can reduce the

overall power consumption of the device. This mode

allows the application to wake-up from Sleep, perform

a few instructions using the INTOSC internal oscillator

block as the clock source and go back to Sleep without

waiting for the external oscillator to become stable.

Two-Speed Start-up mode is configured by the

following settings:

• IESO (of the Configuration Word 1) = 1; Inter-

nal/External Switchover bit (Two-Speed Start-up

mode enabled).

• SCS (of the OSCCON register) = 00.

• FOSC<2:0> bits in the Configuration Word 1

configured for LP, XT or HS mode.

Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, after

Power-up Timer (PWRT) has expired, or

Two-Speed Start-up provides benefits when the oscil-

lator module is configured for LP, XT, or HS modes.

The Oscillator Start-up Timer (OST) is enabled for

these modes and must count 1024 oscillations before

the oscillator can be used as the system clock source.

• Wake-up from Sleep.

If the oscillator module is configured for any mode

other than LP, XT or HS mode, then Two-Speed

Start-up is disabled. This is because the external clock

oscillator does not require any stabilization time after

POR or an exit from Sleep.

If the OST count reaches 1024 before the device

enters Sleep mode, the OSTS bit of the OSCSTAT reg-

ister is set and program execution switches to the

external oscillator. However, the system may never

operate from the external oscillator if the time spent

awake is very short.

Note:

Executing a SLEEP instruction will abort

the oscillator start-up time and will cause

the OSTS bit of the OSCSTAT register to

remain clear.

TABLE 5-1:

Switch From

OSCILLATOR SWITCHING DELAYS

Switch To

Frequency

Oscillator Delay

LFINTOSC⁽¹⁾

MFINTOSC⁽¹⁾

HFINTOSC⁽¹⁾

31 kHz

31.25 kHz-500 kHz

31.25 kHz-16 MHz

Sleep/POR

Oscillator Warm-up Delay (TWARM)

Sleep/POR

LFINTOSC

EC, RC⁽¹⁾

DC – 32 MHz

2 cycles

1 cycle of each

Timer1 Oscillator

LP, XT, HS⁽¹⁾

Sleep/POR

32 kHz-20 MHz

1024 Clock Cycles (OST)

MFINTOSC⁽¹⁾

31.25 kHz-500 kHz

31.25 kHz-16 MHz

Any clock source

2 s (approx.)

HFINTOSC⁽¹⁾

Any clock source

PLL inactive

LFINTOSC⁽¹⁾

Timer1 Oscillator

PLL active

31 kHz

1 cycle of each

32 kHz

1024 Clock Cycles (OST)

2 ms (approx.)

16-32 MHz

Note 1: PLL inactive.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 65

PIC16F/LF1826/27

5.4.2

TWO-SPEED START-UP

SEQUENCE

5.4.3

CHECKING TWO-SPEED CLOCK

STATUS

1. Wake-up from Power-on Reset or Sleep.

Checking the state of the OSTS bit of the OSCSTAT

register will confirm if the microcontroller is running

from the external clock source, as defined by the

FOSC<2:0> bits in the Configuration Word 1, or the

internal oscillator.

2. Instructions begin execution by the internal

oscillator at the frequency set in the IRCF<3:0>

bits of the OSCCON register.

3. OST enabled to count 1024 clock cycles.

4. OST timed out, wait for falling edge of the

internal oscillator.

5. OSTS is set.

6. System clock held low until the next falling edge

of new clock (LP, XT or HS mode).

7. System clock is switched to external clock

source.

FIGURE 5-8:

TWO-SPEED START-UP

INTOSC

TOST

OSC1

0

1

1022 1023

OSC2

Program Counter

PC - N

PC + 1

PC

System Clock

DS41391C-page 66

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

5.5.3

FAIL-SAFE CONDITION CLEARING

5.5

Fail-Safe Clock Monitor

The Fail-Safe condition is cleared after a Reset,

executing a SLEEPinstruction or changing the SCS bits

of the OSCCON register. When the SCS bits are

changed, the OST is restarted. While the OST is

running, the device continues to operate from the

INTOSC selected in OSCCON. When the OST times

out, the Fail-Safe condition is cleared and the device

will be operating from the external clock source. The

Fail-Safe condition must be cleared before the OSFIF

flag can be cleared.

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue operating should the external oscillator fail.

The FSCM can detect oscillator failure any time after

the Oscillator Start-up Timer (OST) has expired. The

FSCM is enabled by setting the FCMEN bit in the

Configuration Word 1. The FSCM is applicable to all

external Oscillator modes (LP, XT, HS, EC, Timer1

Oscillator and RC).

FIGURE 5-9:

FSCM BLOCK DIAGRAM

5.5.4

RESET OR WAKE-UP FROM SLEEP

Clock Monitor

Latch

The FSCM is designed to detect an oscillator failure

after the Oscillator Start-up Timer (OST) has expired.

The OST is used after waking up from Sleep and after

any type of Reset. The OST is not used with the EC or

RC Clock modes so that the FSCM will be active as

soon as the Reset or wake-up has completed. When

the FSCM is enabled, the Two-Speed Start-up is also

enabled. Therefore, the device will always be executing

code while the OST is operating.

External

Clock

S

Q

LFINTOSC

Oscillator

÷ 64

R

Q

31 kHz

(~32 s)

488 Hz

(~2 ms)

Sample Clock

Note:

Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active

during oscillator start-up (i.e., after exiting

Reset or Sleep). After an appropriate

amount of time, the user should check the

Status bits in the OSCSTAT register to

verify the oscillator start-up and that the

system clock switchover has successfully

completed.

Clock

Failure

Detected

5.5.1

FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by

comparing the external oscillator to the FSCM sample

clock. The sample clock is generated by dividing the

LFINTOSC by 64. See Figure 5-8. Inside the fail

detector block is a latch. The external clock sets the

latch on each falling edge of the external clock. The

sample clock clears the latch on each rising edge of the

sample clock. A failure is detected when an entire

half-cycle of the sample clock elapses before the

external clock goes low.

5.5.2

FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the

device clock to an internal clock source and sets the bit

flag OSFIF of the PIR2 register. Setting this flag will

generate an interrupt if the OSFIE bit of the PIE2

register is also set. The device firmware can then take

steps to mitigate the problems that may arise from a

failed clock. The system clock will continue to be

sourced from the internal clock source until the device

firmware successfully restarts the external oscillator

and switches back to external operation.

The internal clock source chosen by the FSCM is

determined by the IRCF<3:0> bits of the OSCCON

register. This allows the internal oscillator to be

configured before a failure occurs.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 67

PIC16F/LF1826/27

FIGURE 5-10:

FSCM TIMING DIAGRAM

Sample Clock

Oscillator

Failure

System

Clock

Output

Clock Monitor Output

(Q)

Failure

Detected

OSCFIF

Test

Note:

The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

DS41391C-page 68

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

5.6

Oscillator Control Registers

REGISTER 5-1:

OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1

IRCF<3:0>

R/W-0/0

SPLLEN

bit 7

U-0

—

R/W-0/0

SCS<1:0>

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

SPLLEN: Software PLL Enable bit

If PLLEN in Configuration Word 1 = 1:

SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements)

If PLLEN in Configuration Word 1 = 0:

1= 4x PLL Is enabled

0 = 4x PLL is disabled

bit 6-3

IRCF<3:0>: Internal Oscillator Frequency Select bits

000x=31 kHz LF

0010=31.25 kHz MF

0011=31.25 kHz HF⁽¹⁾

0100=62.5 kHz MF

0101=125 kHz MF

0110=250 kHz MF

0111=500 kHz MF (default upon Reset)

1000=125 kHz HF⁽¹⁾

1001=250 kHz HF⁽¹⁾

1010=500 kHz HF⁽¹⁾

1011=1 MHz HF

1100=2 MHz HF

1101=4 MHz HF

1110=8 MHz or 32 MHz HF(see Section 5.2.2.1 “HFINTOSC”)

1111=16 MHz HF

bit 2

Unimplemented: Read as ‘0’

bit 1-0

SCS<1:0>: System Clock Select bits

1x= Internal oscillator block

01= Timer1 oscillator

00= Clock determined by FOSC<2:0> in Configuration Word 1.

Note 1: Duplicate frequency derived from HFINTOSC.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 69

PIC16F/LF1826/27

REGISTER 5-2:

OSCSTAT: OSCILLATOR STATUS REGISTER

R-1/q

T1OSCR

bit 7

R-0/q

PLLR

R-q/q

R-0/q

R-q/q

R-0/0

R-0/q

OSTS

HFIOFR

HFIOFL

MFIOFR

LFIOFR

HFIOFS

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Conditional

bit 7

T1OSCR: Timer1 Oscillator Ready bit

If T1OSCEN = 1:

1= Timer1 oscillator is ready

0= Timer1 oscillator is not ready

If T1OSCEN = 0:

1= Timer1 clock source is always ready

bit 6

bit 5

PLLR 4x PLL Ready bit

1= 4x PLL is ready

0= 4x PLL is not ready

OSTS: Oscillator Start-up Time-out Status bit

1= Running from the clock defined by the FOSC<2:0> bits of the Configuration Word 1

0= Running from an internal oscillator (FOSC<2:0> = 100)

bit 4

bit 3

bit 2

bit 1

bit 0

HFIOFR: High Frequency Internal Oscillator Ready bit

1= HFINTOSC is ready

0= HFINTOSC is not ready

HFIOFL: High Frequency Internal Oscillator Locked bit

1= HFINTOSC is at least 2% accurate

0= HFINTOSC is not 2% accurate

MFIOFR: Medium Frequency Internal Oscillator Ready bit

1= MFINTOSC is ready

0= MFINTOSC is not ready

LFIOFR: Low Frequency Internal Oscillator Ready bit

1= LFINTOSC is ready

0= LFINTOSC is not ready

HFIOFS: High Frequency Internal Oscillator Stable bit

1= HFINTOSC is at least 0.5% accurate

0= HFINTOSC is not 0.5% accurate

DS41391C-page 70

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

REGISTER 5-3:

OSCTUNE: OSCILLATOR TUNING REGISTER

U-0

—

U-0

—

R/W-0/0

bit 0

TUN<5:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

TUN<4:0>: Frequency Tuning bits

011111= Maximum frequency

011110=

•

000001=

000000= Oscillator module is running at the factory-calibrated frequency.

111111=

•

100000= Minimum frequency

TABLE 5-2:

SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OSCCON

OSCSTAT

OSCTUNE

PIE2

SPLLEN

T1OSCR

—

IRCF3

PLLR

—

IRCF2

OSTS

TUN5

C1IE

IRCF1

HFIOFR

TUN4

EEIE

IRCF0

HFIOFL

TUN3

—

MFIOFR

TUN2

—

SCS1

LFIOFR

TUN1

—

SCS0

HFIOFS

TUN0

69

70

71

(1)

OSFIE

OSFIF

C2IE

C2IF

BCL1IE

BCL1IF

CCP2IE

CCP2IF

94

(1)

C1IF

EEIF

—

PIR2

97

T1CON

TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN

T1SYNC

—

TMR1ON

187

Legend:

— = unimplemented locations read as ‘0’. Shaded cells are not used by clock sources.

Note 1: PIC16F/LF1827 only.

TABLE 5-3:

SUMMARY OF CONFIGURATION WORD ASSOCIATED WITH CLOCK SOURCES

Register

on Page

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

13:8

7:0

—

FCMEN

PWRTE

IESO

CLKOUTEN BOREN1

WDTE0 FOSC2

BOREN0

FOSC1

CPD

CONFIG1

50

CP

MCLRE

WDTE1

FOSC0

Legend:

— = unimplemented locations read as ‘0’. Shaded cells are not used by clock sources.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 71

PIC16F/LF1826/27

NOTES:

DS41391C-page 72

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

6.3

Conflicts with the CLKR pin

6.0

REFERENCE CLOCK MODULE

There are two cases when the reference clock output

signal cannot be output to the CLKR pin, if:

The Reference Clock module provides the ability to

send a divided clock to the clock output pin of the

device (CLKR) and provide a secondary internal clock

source to the Modulator module. This module is avail-

able in all oscillator configurations and allows the user

to select a greater range of clock submultiples to drive

external devices in the application. The reference clock

module includes the following features:

• LP, XT, or HS oscillator mode is selected.

• CLKOUT function is enabled.

Even if either of these cases are true, the module can

still be enabled and the reference clock signal may be

used in conjunction with the Modulator module.

• System clock is the source

• Available in all oscillator configurations

• Programmable clock divider

• Output enable to a port pin

• Selectable duty cycle

6.3.1

OSCILLATOR MODES

If LP, XT, or HS oscillator modes are selected, the

OSC2/CLKR pin must be used as an oscillator input pin

and the CLKR output cannot be enabled. See

Section 5.2 “Clock Source Types” for more

information on different oscillator modes.

• Slew rate control

The Reference Clock module is controlled by the

CLKRCON register (Register 6-1) and is enabled when

setting the CLKREN bit. To output the divided clock sig-

nal to the CLKR port pin, the CLKROE bit must be set.

The CLKRDIV<2:0> bits enable the selection of 8 dif-

ferent clock divider options. The CLKRDC<1:0> bits

can be used to modify the duty cycle of the output

clock⁽¹⁾. The CLKRSLR bit controls slew rate limiting.

6.3.2

CLKOUT FUNCTION

The CLKOUT function has a higher priority than the

Reference Clock module. Therefore, if the CLKOUT

function is enabled by the CLKOUTEN bit in Configura-

tion Word 1, FOSC/4 will always be output on the port

pin. Reference Section 4.0 “Device Configuration”

for more information.

Note 1: If the base clock rate is selected without a

divider, the output clock will always have

a duty cycle equal to that of the source

clock, unless a 0% duty cycle is selected.

If the clock divider is set to base clock/2,

then 25% and 75% duty cycle accuracy

will be dependent upon the source clock.

6.4

Operation During Sleep

As the Reference Clock module relies on the system

clock as its source, and the system clock is disabled in

Sleep, the module does not function in Sleep, even if

an external clock source or the Timer1 clock source is

configured as the system clock. The module outputs

will remain in their current state until the device exits

Sleep.

For information on using the reference clock output

with the Modulator module, see Section 22.0 “Data

Signal Modulator”.

6.1

Slew Rate

The slew rate limitation on the output port pin can be

disabled. The Slew Rate limitation can be removed by

clearing the CLKRSLR bit in the CLKRCON register.

6.2

Effects of a Reset

Upon any device Reset, the reference clock module is

disabled. The user's firmware is responsible for

initializing the module before enabling the output. The

registers are reset to their default values.

 2009 Microchip Technology Inc.

Preliminary

DS41391C-page 73

PIC16F/LF1826/27

REGISTER 6-1:

CLKRCON: REFERENCE CLOCK CONTROL REGISTER

R/W-0/0

CLKREN

bit 7

R/W-0/0

R/W-1/1

R/W-0/0

bit 0

CLKROE

CLKRSLR

CLKRDC<1:0>

CLKRDIV<2:0>

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

CLKREN: Reference Clock Module Enable bit

1= Reference Clock module is enabled

0= Reference Clock module is disabled

bit 6

CLKROE: Reference Clock Output Enable bit⁽³⁾

1= Reference Clock output is enabled on CLKR pin

0= Reference Clock output disabled on CLKR pin

bit 5

CLKRSLR: Reference Clock Slew Rate Control limiting enable bit

1= Slew Rate limiting is enabled

0= Slew Rate limiting is disabled

bit 4-3

CLKRDC<1:0>: Reference Clock Duty Cycle bits

11= Clock outputs duty cycle of 75%

10= Clock outputs duty cycle of 50%

01= Clock outputs duty cycle of 25%

00= Clock outputs duty cycle of 0%

bit 2-0

CLKRDIV<2:0> Reference Clock Divider bits

111= Base clock value divided by 128

110= Base clock value divided by 64

101= Base clock value divided by 32

100= Base clock value divided by 16

011= Base clock value divided by 8

010= Base clock value divided by 4

001= Base clock value divided by 2⁽¹⁾

000= Base clock value⁽²⁾

Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle.

2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0%

is selected.

3: To route CLKR to pin, CLKOUTEN of Configuration Word 1 = 1is required. CLKOUTEN of Configuration

Word 1 = 0will result in FOSC/4. See Section 6.3 “Conflicts with the CLKR pin” for details.

DS41391C-page 74

Preliminary

 2009 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 6-1:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES

Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

CLKRCON

CLKREN

CLKROE CLKRSLR CLKRDC1 CLKRDC0

CLKRDIV2 CLKRDIV1 CLKRDIV0

74

Legend:

— = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.

TABLE 6-2:

SUMMARY OF CONFIGURATION WORD WITH REFERENCE CLOCK SOURCES

Register

on Page

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

13:8

7:0

—

FCMEN

PWRTE

IESO

CLKOUTEN BOREN1

WDTE0 FOSC2

BOREN0

FOSC1

CPD

CONFIG1

50

CP

MCLRE

WDTE1

FOSC0

Legend:

— = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.

 2009 Microchip Technology Inc.

Preliminary

DS41391C-page 75

PIC16F/LF1826/27

NOTES:

DS41391C-page 76

Preliminary

 2009 Microchip Technology Inc.

PIC16F/LF1826/27

7.0

RESETS

There are multiple ways to reset this device:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• MCLR Reset

• WDT Reset

• RESETinstruction

• Stack Overflow

• Stack Underflow

• Programming mode exit

To allow VDD to stabilize, an optional power-up timer

can be enabled to extend the Reset time after a BOR

or POR event.

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 7-1.

FIGURE 7-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Programming Mode Exit

RESET Instruction

Stack Overflow/Underflow Reset

Stack

Pointer

External Reset

MCLRE

MCLR

Sleep

WDT

Time-out

Device

Reset

Power-on

Reset

VDD

Brown-out

Reset

BOR

Enable

PWRT

64 ms

Zero

LFINTOSC

PWRTEN

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 77

PIC16F/LF1826/27

7.1

Power-on Reset (POR)

7.2

Brown-Out Reset (BOR)

The POR circuit holds the device in Reset until VDD has

reached an acceptable level for minimum operation.

Slow rising VDD, fast operating speeds or analog

performance may require greater than minimum VDD.

The PWRT, BOR or MCLR features can be used to

extend the start-up period until all device operation

conditions have been met.

The BOR circuit holds the device in Reset when Vdd

reaches a selectable minimum level. Between the

POR and BOR, complete voltage range coverage for

execution protection can be implemented.

The Brown-out Reset module has four operating

modes controlled by the BOREN<1:0> bits in Configu-

ration Word 1. The four operating modes are:

• BOR is always on

7.1.1

POWER-UP TIMER (PWRT)

• BOR is off when in Sleep

• BOR is controlled by software

• BOR is always off

The Power-up Timer provides a nominal 64 ms time-

out on POR or Brown-out Reset.

The device is held in Reset as long as PWRT is active.

The PWRT delay allows additional time for the VDD to

rise to an acceptable level. The Power-up Timer is

enabled by clearing the PWRTE bit in Configuration

Word 1.

Refer to Table 7-3 for more information.

The Brown-out Reset voltage level is selectable by

configuring the BORV bit in Configuration Word 2.

A VDD noise rejection filter prevents the BOR from trig-

gering on small events. If VDD falls below VBOR for a

duration greater than parameter TBORDC, the device

will reset. See Figure 7-3 for more information.

The Power-up Timer starts after the release of the POR

and BOR.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting” (DS00607).

TABLE 7-1:

BOR OPERATING MODES

Device

BOREN

Config bits

Operation upon

SBOREN

Device Mode

BOR Mode

Operation upon

release of POR

wake- up from

Sleep

BOR_ON (11)

BOR_NSLEEP (10)

BOR_SBOREN (01)

BOR_OFF (00)

X

1

0

X

Awake

Sleep

X

Active

Waits for BOR ready⁽¹⁾

Waits for BOR ready

Disabled

Active

Begins immediately

X

Disabled

X

Note 1: Even though this case specifically waits for the BOR, the BOR is already operating, so there is no delay in

start-up.

7.2.1

BOR IS ALWAYS ON

7.2.3

BOR CONTROLLED BY SOFTWARE

When the BOREN bits of Configuration Word 1 are set

to ‘11’, the BOR is always on. The device start-up will

be delayed until the BOR is ready and VDD is higher

than the BOR threshold.

When the BOREN bits of Configuration Word 1 are set

to ‘01’, the BOR is controlled by the SBOREN bit of the

BORCON register. The device start-up is not delayed

by the BOR ready condition or the VDD level.

BOR protection is active during Sleep. The BOR does

not delay wake-up from Sleep.

BOR protection begins as soon as the BOR circuit is

ready. The status of the BOR circuit is reflected in the

BORRDY bit of the BORCON register.

7.2.2

BOR IS OFF IN SLEEP

BOR protection is unchanged by Sleep.

When the BOREN bits of Configuration Word 1 are set

to ‘10’, the BOR is on, except in Sleep. The device

start-up will be delayed until the BOR is ready and VDD

is higher than the BOR threshold.

BOR protection is not active during Sleep. The device

wake-up will be delayed until the BOR is ready.

DS41391C-page 78

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 7-2:

BROWN-OUT READY

SBOREN

TBORRDY

BOR Protection Active

BORRDY

FIGURE 7-3:

BROWN-OUT SITUATIONS

VDD

VBOR

Internal

Reset

(1)

TPWRT

VDD

VBOR

Internal

Reset

< TPWRT

(1)

TPWRT

VDD

VBOR

Internal

Reset

(1)

TPWRT

Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.

REGISTER 7-1:

BORCON: BROWN-OUT RESET CONTROL REGISTER

R/W-1/u

SBOREN

bit 7

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

R-q/u

—

BORRDY

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

SBOREN: Software Brown-out Reset Enable bit

If BOREN <1:0> in Configuration Word 1  01:

SBOREN is read/write, but has no effect on the BOR.

If BOREN <1:0> in Configuration Word 1 = 01:

1= BOR Enabled

0= BOR Disabled

bit 6-1

bit 0

Unimplemented: Read as ‘0’

BORRDY: Brown-out Reset Circuit Ready Status bit

1= The Brown-out Reset circuit is active

0= The Brown-out Reset circuit is inactive

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 79

PIC16F/LF1826/27

7.3

MCLR

7.7

Programming Mode Exit

The MCLR is an optional external input that can reset

the device. The MCLR function is controlled by the

MCLRE bit of Configuration Word 1 and the LVP bit of

Configuration Word 2 (Table 7-2).

Upon exit of Programming mode, the device will

behave as if a POR had just occurred.

7.8

Power-Up Timer

The Power-up Timer optionally delays device execution

after a BOR or POR event. This timer is typically used to

allow VDD to stabilize before allowing the device to start

running.

TABLE 7-2:

MCLRE

MCLR CONFIGURATION

LVP

MCLR

0

1

x

0

1

Disabled

Enabled

The Power-up Timer is controlled by the PWRTE bit of

Configuration Word 1.

7.9

Start-up Sequence

7.3.1

MCLR ENABLED

Upon the release of a POR or BOR, the following must

occur before the device will begin executing:

When MCLR is enabled and the pin is held low, the

device is held in Reset. The MCLR pin is connected to

VDD through an internal weak pull-up.

1. Power-up Timer runs to completion (if enabled).

2. Oscillator start-up timer runs to completion (if

required for oscillator source).

The device has a noise filter in the MCLR Reset path.

The filter will detect and ignore small pulses.

3. MCLR must be released (if enabled).

Note:

A Reset does not drive the MCLR pin low.

The total time-out will vary based on oscillator

configuration and Power-up Timer configuration. See

Section 5.0 “Oscillator Module (With Fail-Safe Clock

Monitor)” for more information.

7.3.2

MCLR DISABLED

When MCLR is disabled, the pin functions as a general

purpose input and the internal weak pull-up is under

software control. See Section 12.2 “PORTA Registers”

for more information.

The Power-up Timer and oscillator start-up timer run

independently of MCLR Reset. If MCLR is kept low

long enough, the Power-up Timer and oscillator start-

up timer will expire. Upon bringing MCLR high, the

device will begin execution immediately (see Figure 7-

4). This is useful for testing purposes or to synchronize

more than one device operating in parallel.

7.4

Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware

does not issue a CLRWDTinstruction within the time-out

period. The TO and PD bits in the STATUS register are

changed to indicate the WDT Reset. See Section “”

for more information.

7.5

RESET Instruction

A RESETinstruction will cause a device Reset. The RI

bit in the PCON register will be set to ‘0’. See Table 7-4

for default conditions after a RESET instruction has

occurred.

7.6

Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or

Underflows. The STKOVF or STKUNF bits of the PCON

register indicate the Reset condition. These Resets are

enabled by setting the STVREN bit in Configuration Word

2. See Section 3.4.2 “Overflow/Underflow Reset” for

more information.

DS41391C-page 80

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 7-4:

RESET START-UP SEQUENCE

VDD

Internal POR

TPWRT

Power-Up Timer

MCLR

TMCLR

Internal RESET

Oscillator Modes

External Crystal

TOST

Oscillator Start-Up Timer

Oscillator

FOSC

Internal Oscillator

Oscillator

FOSC

External Clock (EC)

CLKIN

FOSC

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 81

PIC16F/LF1826/27

7.10 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and

PCON register are updated to indicate the cause of the

Reset. Table 7-3 and Table 7-4 show the Reset condi-

tions of these registers.

TABLE 7-3:

RESET STATUS BITS AND THEIR SIGNIFICANCE

STKOVF STKUNF RMCLR

RI

POR

BOR

TO

PD

Condition

0

u

1

u

0

u

1

u

0

u

1

u

0

u

0

u

x

0

u

1

0

x

1

0

1

u

1

u

1

x

0

1

u

0

u

0

u

Power-on Reset

Illegal, TO is set on POR

Illegal, PD is set on POR

Brown-out Reset

WDT Reset

WDT Wake-up from Sleep

Interrupt Wake-up from Sleep

MCLR Reset during normal operation

MCLR Reset during Sleep

RESETInstruction Executed

Stack Overflow Reset (STVREN = 1)

Stack Underflow Reset (STVREN = 1)

TABLE 7-4:

RESET CONDITION FOR SPECIAL REGISTERS⁽²⁾

Program

STATUS

Register

PCON

Register

Condition

Counter

Power-on Reset

0000h

---1 1000

---u uuuu

00-- 110x

uu-- 0uuu

MCLR Reset during normal operation

0000h

MCLR Reset during Sleep

WDT Reset

0000h

---1 0uuu

---0 uuuu

---0 0uuu

---1 1uuu

---1 0uuu

---u uuuu

uu-- 0uuu

uu-- uuuu

00-- 11u0

uu-- uuuu

uu-- u0uu

1u-- uuuu

u1-- uuuu

WDT Wake-up from Sleep

Brown-out Reset

PC + 1

0000h

Interrupt Wake-up from Sleep

RESETInstruction Executed

Stack Overflow Reset (STVREN = 1)

Stack Underflow Reset (STVREN = 1)

PC + 1⁽¹⁾

0000h

Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on

the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

2: If a Status bit is not implemented, that bit will be read as ‘0’.

DS41391C-page 82

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

7.11 Power Control (PCON) Register

The Power Control (PCON) register contains flag bits

to differentiate between a:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Reset Instruction Reset (RI)

• Stack Overflow Reset (STKOVF)

• Stack Underflow Reset (STKUNF)

• MCLR Reset (RMCLR)

The PCON register bits are shown in Register 7-2.

REGISTER 7-2:

PCON: POWER CONTROL REGISTER

R/W/HS-0/q R/W/HS-0/q

U-0

—

U-0

—

R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u

STKOVF

bit 7

STKUNF

RMCLR

RI

POR

BOR

bit 0

Legend:

HC = Bit is cleared by hardware

HS = Bit is set by hardware

U = Unimplemented bit, read as ‘0’

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

-m/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

STKOVF: Stack Overflow Flag bit

1= A Stack Overflow occurred

0= A Stack Overflow has not occurred or set to ‘0’ by firmware

STKUNF: Stack Underflow Flag bit

1= A Stack Underflow occurred

0= A Stack Underflow has not occurred or set to ‘0’ by firmware

bit 5-4

bit 3

Unimplemented: Read as ‘0’

RMCLR: MCLR Reset Flag bit

1= A MCLR Reset has not occurred or set to ‘1’ by firmware

0= A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs)

bit 2

bit 1

bit 0

RI: RESETInstruction Flag bit

1= A RESETinstruction has not been executed or set to ‘1’ by firmware

0= A RESETinstruction has been executed (set to ‘0’ in hardware upon executing a RESETinstruction)

POR: Power-on Reset Status bit

1= No Power-on Reset occurred

0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

BOR: Brown-out Reset Status bit

1= No Brown-out Reset occurred

0= A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset

occurs)

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 83

PIC16F/LF1826/27

TABLE 7-5:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Register

on Page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BORCON SBOREN

—

RMCLR

PD

—

RI

Z

—

POR

DC

BORRDY

BOR

79

83

PCON

STKOVF STKUNF

23

STATUS

WDTCON

—

TO

C

WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN

105

Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.

Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

DS41391C-page 84

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

8.0

INTERRUPTS

The interrupt feature allows certain events to preempt

normal program flow. Firmware is used to determine

the source of the interrupt and act accordingly. Some

interrupts can be configured to wake the MCU from

Sleep mode.

This chapter contains the following information for

Interrupts:

• Operation

• Interrupt Latency

• Interrupts During Sleep

• INT Pin

• Automatic Context Saving

Many peripherals produce Interrupts. Refer to the

corresponding chapters for details.

A block diagram of the interrupt logic is shown in

Figure 8-1 and Figure 8-2.

FIGURE 8-1:

INTERRUPT LOGIC

Wake-up (If in Sleep mode)

TMR0IF

TMR0IE

INTF

INTE

Interrupt to CPU

IOCIF

IOCIE

From Peripheral Interrupt

Logic (Figure 8-2)

PEIE

GIE

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 85

PIC16F/LF1826/27

FIGURE 8-2:

PERIPHERAL INTERRUPT LOGIC -

TMR1GIF

TMR1GIE

ADIF

ADIE

RCIF

RCIE

TXIF

TXIE

SSP1IF

SSP1IE

CCP1IF

CCP1IE

TMR2IF

TMR2IE

TMR1IF

TMR1IE

OSFIF

OSFIE

C2IF

C2IE

C1IF

C1IE

To Interrupt Logic

(Figure 5-1)

EEIF

EEIE

BCL1IF

BCL1IE

CCP2IF⁽¹⁾

CCP2IE⁽¹⁾

CCP4IF⁽¹⁾

CCP4IE⁽¹⁾

CCP3IF⁽¹⁾

CCP3IE⁽¹⁾

TMR6IF⁽¹⁾

TMR6IE⁽¹⁾

TMR4IF⁽¹⁾

TMR4IE⁽¹⁾

BCL2IF⁽¹⁾

BCL2IE⁽¹⁾

SSP2IF⁽¹⁾

SSP2IE⁽¹⁾

Note 1: These interrupts are available on PIC16F/LF1827 only

DS41391C-page 86

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

8.1

Operation

8.2

Interrupt Latency

Interrupts are disabled upon any device Reset. They

are enabled by setting the following bits:

Interrupt latency is defined as the time from when the

interrupt event occurs to the time code execution at the

interrupt vector begins. The latency for synchronous

interrupts is 3 or 4 instruction cycles. For asynchronous

interrupts, the latency is 3 to 5 instruction cycles,

depending on when the interrupt occurs. See Figure 8-3

and Figure 8.3 for more details.

• GIE bit of the INTCON register

• Interrupt Enable bit(s) for the specific interrupt

event(s)

• PEIE bit of the INTCON register (if the Interrupt

Enable bit of the interrupt event is contained in the

PIEx register)

The INTCON, PIR1, PIR2, PIR3 and PIR4 registers

record individual interrupts via interrupt flag bits. Inter-

rupt flag bits will be set, regardless of the status of the

GIE, PEIE and individual interrupt enable bits.

The following events happen when an interrupt event

occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the

stack

• Critical registers are automatically saved to the

shadow registers (See Section 8.5 “Automatic

Context Saving”)

• PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR)

should determine the source of the interrupt by polling

the interrupt flag bits. The interrupt flag bits must be

cleared before exiting the ISR to avoid repeated

interrupts. Because the GIE bit is cleared, any interrupt

that occurs while executing the ISR will be recorded

through its interrupt flag, but will not cause the

processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the

previous address from the stack, restoring the saved

context from the shadow registers and setting the GIE

bit.

For additional information on a specific interrupt’s

operation, refer to its peripheral chapter.

Note 1: Individual interrupt flag bits are set,

regardless of the state of any other

enable bits.

2: All interrupts will be ignored while the GIE

bit is cleared. Any interrupt occurring

while the GIE bit is clear will be serviced

when the GIE bit is set again.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 87

PIC16F/LF1826/27

FIGURE 8-3:

INTERRUPT LATENCY

OSC1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKOUT

Interrupt Sampled

during Q1

Interrupt

GIE

PC-1

PC

PC+1

0004h

NOP

0005h

PC

1 Cycle Instruction at PC

Execute

Inst(PC)

NOP

Inst(0004h)

Interrupt

GIE

PC+1/FSR

ADDR

New PC/

PC+1

PC-1

PC

0004h

NOP

0005h

PC

Execute

2 Cycle Instruction at PC

Inst(PC)

NOP

Inst(0004h)

Interrupt

GIE

PC-1

PC

FSR ADDR

INST(PC)

PC+1

NOP

PC+2

NOP

0004h

NOP

0005h

PC

Execute

3 Cycle Instruction at PC

Inst(0004h)

Inst(0005h)

Interrupt

GIE

PC-1

PC

FSR ADDR

INST(PC)

PC+1

NOP

PC+2

0004h

NOP

0005h

PC

NOP

Execute

3 Cycle Instruction at PC

NOP

Inst(0004h)

DS41391C-page 88

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 8-4:

INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

(3)

CLKOUT

(4)

INT pin

INTF

(1)

(2)

(5)

Interrupt Latency

GIE

INSTRUCTION FLOW

PC

PC + 1

—

0004h

0005h

PC

Inst (PC)

PC + 1

Instruction

Fetched

Inst (PC + 1)

Inst (0004h)

Inst (0005h)

Inst (0004h)

Instruction

Executed

Dummy Cycle

Inst (PC)

Inst (PC – 1)

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT not available in all oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 29.0 “Electrical Specifications”.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 89

PIC16F/LF1826/27

8.3

Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To

wake from Sleep, the peripheral must be able to

operate without the system clock. The interrupt source

must have the appropriate Interrupt Enable bit(s) set

prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the

processor will branch to the interrupt vector. Otherwise,

the processor will continue executing instructions after

the SLEEPinstruction. The instruction directly after the

SLEEP instruction will always be executed before

branching to the ISR. Refer to the Section 9.0 “Power-

Down Mode (Sleep)” for more details.

8.4

INT Pin

The INT pin can be used to generate an asynchronous

edge-triggered interrupt. This interrupt is enabled by

setting the INTE bit of the INTCON register. The

INTEDG bit of the OPTION register determines on which

edge the interrupt will occur. When the INTEDG bit is

set, the rising edge will cause the interrupt. When the

INTEDG bit is clear, the falling edge will cause the

interrupt. The INTF bit of the INTCON register will be set

when a valid edge appears on the INT pin. If the GIE and

INTE bits are also set, the processor will redirect

program execution to the interrupt vector.

8.5

Automatic Context Saving

Upon entering an interrupt, the return PC address is

saved on the stack. Additionally, the following registers

are automatically saved in the Shadow registers:

• W register

• STATUS register (except for TO and PD)

• BSR register

• FSR registers

• PCLATH register

Upon exiting the Interrupt Service Routine, these regis-

ters are automatically restored. Any modifications to

these registers during the ISR will be lost. If modifica-

tions to any of these registers are desired, the corre-

sponding Shadow register should be modified and the

value will be restored when exiting the ISR. The

Shadow registers are available in Bank 31 and are

readable and writable. Depending on the user’s appli-

cation, other registers may also need to be saved.

DS41391C-page 90

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

8.5.1

INTCON REGISTER

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE of the INTCON register.

User software should ensure the appropri-

ate interrupt flag bits are clear prior to

enabling an interrupt.

The INTCON register is a readable and writable

register, which contains the various enable and flag bits

for TMR0 register overflow, interrupt-on-change and

external INT pin interrupts.

REGISTER 8-1:

INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0

GIE

R/W-0/0

PEIE

R/W-0/0

TMR0IE

R/W-0/0

INTE

R/W-0/0

IOCIE

R/W-0/0

TMR0IF

R/W-0/0

INTF

R-0/0

IOCIF⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

GIE: Global Interrupt Enable bit

1= Enables all active interrupts

0= Disables all interrupts

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

PEIE: Peripheral Interrupt Enable bit

1= Enables all active peripheral interrupts

0= Disables all peripheral interrupts

TMR0IE: Timer0 Overflow Interrupt Enable bit

1= Enables the Timer0 interrupt

0= Disables the Timer0 interrupt

INTE: INT External Interrupt Enable bit

1= Enables the INT external interrupt

0= Disables the INT external interrupt

IOCIE: Interrupt-on-Change Enable bit

1= Enables the interrupt-on-change

0= Disables the interrupt-on-change

TMR0IF: Timer0 Overflow Interrupt Flag bit

1= TMR0 register has overflowed

0= TMR0 register did not overflow

INTF: INT External Interrupt Flag bit

1= The INT external interrupt occurred

0= The INT external interrupt did not occur

IOCIF: Interrupt-on-Change Interrupt Flag bit⁽¹⁾

1= When at least one of the interrupt-on-change pins changed state

0= None of the interrupt-on-change pins have changed state

Note 1: The IOCIF Flag bit is read only and cleared when all the interrupt-on-change flags in the IOCBF register

have been cleared by software.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 91

PIC16F/LF1826/27

8.5.2

PIE1 REGISTER

The PIE1 register contains the interrupt enable bits, as

shown in Register 8-2.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

REGISTER 8-2:

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0

TMR1GIE

bit 7

R/W-0/0

ADIE

R/W-0/0

RCIE

R/W-0/0

TXIE

R/W-0/0

SSP1IE

R/W-0/0

CCP1IE

R/W-0/0

TMR2IE

R/W-0/0

TMR1IE

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

TMR1GIE: Timer1 Gate Interrupt Enable bit

1= Enables the Timer1 Gate Acquisition interrupt

0= Disables the Timer1 Gate Acquisition interrupt

ADIE: A/D Converter (ADC) Interrupt Enable bit

1= Enables the ADC interrupt

0= Disables the ADC interrupt

RCIE: USART Receive Interrupt Enable bit

1= Enables the USART receive interrupt

0= Disables the USART receive interrupt

TXIE: USART Transmit Interrupt Enable bit

1= Enables the USART transmit interrupt

0= Disables the USART transmit interrupt

SSP1IE: Synchronous Serial Port 1 (MSSP1) Interrupt Enable bit

1= Enables the MSSP1 interrupt

0= Disables the MSSP1 interrupt

CCP1IE: CCP1 Interrupt Enable bit

1= Enables the CCP1 interrupt

0= Disables the CCP1 interrupt

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1= Enables the Timer2 to PR2 match interrupt

0= Disables the Timer2 to PR2 match interrupt

TMR1IE: Timer1 Overflow Interrupt Enable bit

1= Enables the Timer1 overflow interrupt

0= Disables the Timer1 overflow interrupt

DS41391C-page 92

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

8.5.3

PIE2 REGISTER

The PIE2 register contains the interrupt enable bits, as

shown in Register 8-3.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

REGISTER 8-3:

PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0/0

OSFIE

bit 7

R/W-0/0

C2IE

R/W-0/0

C1IE

R/W-0/0

EEIE

R/W-0/0

BCL1IE

U-0

—

U-0

—

R/W-0/0

CCP2IE⁽¹⁾

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

bit 3

OSFIE: Oscillator Fail Interrupt Enable bit

1= Enables the Oscillator Fail interrupt

0= Disables the Oscillator Fail interrupt

C2IE: Comparator C2 Interrupt Enable bit

1= Enables the Comparator C2 interrupt

0= Disables the Comparator C2 interrupt

C1IE: Comparator C1 Interrupt Enable bit

1= Enables the Comparator C1 interrupt

0= Disables the Comparator C1 interrupt

EEIE: EEPROM Write Completion Interrupt Enable bit

1= Enables the EEPROM Write Completion interrupt

0= Disables the EEPROM Write Completion interrupt

BCL1IE: MSSP1 Bus Collision Interrupt Enable bit

1= Enables the MSSP1 Bus Collision Interrupt

0= Disables the MSSP1 Bus Collision Interrupt

bit 2-1

bit 0

Unimplemented: Read as ‘0’

CCP2IE: CCP2 Interrupt Enable bit

1= Enables the CCP2 interrupt

0= Disables the CCP2 interrupt

Note 1: PIC16F/LF1827 only.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 93

PIC16F/LF1826/27

8.5.4

PIE3 REGISTER⁽¹⁾

The PIE3 register contains the interrupt enable bits, as

shown in Register 8-4.

Note 1: The PIE3 register is available only on the

PIC16F/LF1827 device.

2: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

REGISTER 8-4:

PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3⁽¹⁾

U-0

—

U-0

—

R/W-0/0

CCP4IE

R/W-0/0

CCP3IE

R/W-0/0

TMR6IE

U-0

—

R/W-0/0

TMR4IE

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5

Unimplemented: Read as ‘0’

CCP4IE: CCP4 Interrupt Enable bit

1= Enables the CCP4 interrupt

0= Disables the CCP4 interrupt

bit 4

bit 3

CCP3IE: CCP3 Interrupt Enable bit

1= Enables the CCP3 interrupt

0= Disables the CCP3 interrupt

TMR6IE: TMR6 to PR6 Match Interrupt Enable bit

1= Enables the TMR6 to PR6 Match interrupt

0= Disables the TMR6 to PR6 Match interrupt

bit 2

bit 1

Unimplemented: Read as ‘0’

TMR4IE: TMR4 to PR4 Match Interrupt Enable bit

1= Enables the TMR4 to PR4 Match interrupt

0= Disables the TMR4 to PR4 Match interrupt

bit 0

Unimplemented: Read as ‘0’

Note 1: This register is only available on PIC16F/LF1827.

DS41391C-page 94

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

8.5.5

PIE4 REGISTER⁽¹⁾

The PIE4 register contains the interrupt enable bits, as

shown in Register 8-5.

Note 1: The PIE4 register is available only on the

PIC16F/LF1827 device.

2: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

REGISTER 8-5:

PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

BCL2IE

R/W-0/0

SSP2IE

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-2

bit 1

Unimplemented: Read as ‘0’

BCL2IE: MSSP2 Bus Collision Interrupt Enable bit

1= Enables the MSSP2 Bus Collision Interrupt

0= Disables the MSSP2 Bus Collision Interrupt

bit 0

SSP2IE: Master Synchronous Serial Port 2 (MSSP2) Interrupt Enable bit

1= Enables the MSSP2 interrupt

0= Disables the MSSP2 interrupt

Note 1: This register is only available on PIC16F/LF1827.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 95

PIC16F/LF1826/27

8.5.6

PIR1 REGISTER

The PIR1 register contains the interrupt flag bits, as

shown in Register 8-6.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

REGISTER 8-6:

PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0/0

TMR1GIF

bit 7

R/W-0/0

ADIF

R-0/0

RCIF

R-0/0

TXIF

R/W-0/0

SSP1IF

R/W-0/0

CCP1IF

R/W-0/0

TMR2IF

R/W-0/0

TMR1IF

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

TMR1GIF: Timer1 Gate Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

ADIF: A/D Converter Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

RCIF: USART Receive Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

TXIF: USART Transmit Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

SSP1IF: Synchronous Serial Port 1 (MSSP1) Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

CCP1IF: CCP1 Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

TMR2IF: Timer2 to PR2 Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

TMR1IF: Timer1 Overflow Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

DS41391C-page 96

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

8.5.7

PIR2 REGISTER

The PIR2 register contains the interrupt flag bits, as

shown in Register 8-7.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

REGISTER 8-7:

PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0/0

OSFIF

R/W-0/0

C2IF

R/W-0/0

C1IF

R/W-0/0

EEIF

R/W-0/0

BCL1IF

U-0

—

U-0

—

R/W-0/0

CCP2IF⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

bit 3

OSFIF: Oscillator Fail Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

C2IF: Comparator C2 Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

C1IF: Comparator C1 Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

EEIF: EEPROM Write Completion Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

BCL1IF: MSSP1 Bus Collision Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

bit 2-1

bit 0

Unimplemented: Read as ‘0’

CCP2IF: CCP2 Interrupt Flag bit⁽¹⁾

1= Interrupt is pending

0= Interrupt is not pending

Note 1: PIC16F/LF1827 only.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 97

PIC16F/LF1826/27

8.5.8

PIR3 REGISTER⁽¹⁾

The PIR3 register contains the interrupt flag bits, as

shown in Register 8-8.

Note 1: The PIR3 register is available only on the

PIC16F/LF1827 device.

2: Interrupt flag bits are set when an inter-

rupt condition occurs, regardless of the

state of its corresponding enable bit or the

Global Enable bit, GIE, of the INTCON

register. User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

REGISTER 8-8:

PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3⁽¹⁾

U-0

—

U-0

—

R/W-0/0

CCP4IF

R/W-0/0

CCP3IF

R/W-0/0

TMR6IF

U-0

—

R/W-0/0

TMR4IF

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5

Unimplemented: Read as ‘0’

CCP4IF: CCP4 Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

bit 4

bit 3

CCP3IF: CCP3 Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

TMR6IF: TMR6 to PR6 Match Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

bit 2

bit 1

Unimplemented: Read as ‘0’

TMR4IF: TMR4 to PR4 Match Interrupt Flag bit

1= Interrupt is pending

0= Interrupt is not pending

bit 0

Unimplemented: Read as ‘0’

Note 1: This register is only available on PIC16F/LF1827.

DS41391C-page 98

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

8.5.9

PIR4 REGISTER⁽¹⁾

The PIR4 register contains the interrupt flag bits, as

shown in Register 8-9.

Note 1: The PIR4 register is available only on the

PIC16F/LF1827 device.

2: Interrupt flag bits are set when an inter-

rupt condition occurs, regardless of the

state of its corresponding enable bit or the

Global Enable bit, GIE, of the INTCON

register. User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

REGISTER 8-9:

PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W/HS-0/0 R/W/HS-0/0

BCL2IF SSP2IF

bit 0

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HS = Bit is set by hardware

bit 7-2

bit 1

Unimplemented: Read as ‘0’

BCL2IF: MSSP2 Bus Collision Interrupt Flag bit

1= A Bus Collision was detected (must be cleared in software)

0= No Bus collision was detected

bit 0

SSP2IF: Master Synchronous Serial Port 2 (MSSP2) Interrupt Flag bit

1= The Transmission/Reception/Bus Condition is complete (must be cleared in software)

0= Waiting to Transmit/Receive/Bus Condition in progress

Note 1: This register is only available on PIC16F/LF1827.

TABLE 8-1:

SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

OPTION_REG

PIE1

GIE

WPUEN

TMR1GIE

OSFIE

—

PEIE

INTEDG

ADIE

C2IE

—

TMR0IE

INTE

IOCIE

PSA

TMR0IF

PS2

INTF

PS1

IOCIF

PS0

91

177

92

93

94

95

96

97

98

99

TMR0CS TMR0SE

RCIE

C1IE

CCP4IE

—

TXIE

EEIE

CCP3IE

—

SSP1IE

BCL1IE

TMR6IE

—

CCP1IE

—

TMR2IE

—

TMR1IE

(1)

PIE2

CCP2IE

—

(1)

PIE3

—

TMR4IE

BCL2IE

TMR2IF

—

(1)

SSP2IE

TMR1IF

PIE4

—

TMR1GIF

OSFIF

ADIF

C2IF

RCIF

C1IF

TXIF

EEIF

SSP1IF

BCL1IF

CCP1IF

—

PIR1

PIR2

(1)

CCP2IF

(1)

PIR3

—

CCP4IF

—

CCP3IF

—

TMR6IF

—

TMR4IF

BCL2IF

—

(1)

SSP2IF

PIR4

Legend:

— = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts.

Note 1: PIC16F/LF1827 only.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 99

PIC16F/LF1826/27

NOTES:

DS41391C-page 100

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

9.1

Wake-up from Sleep

9.0

POWER-DOWN MODE (SLEEP)

The device can wake-up from Sleep through one of the

following events:

The Power-Down mode is entered by executing a

SLEEPinstruction.

1. External Reset input on MCLR pin, if enabled

2. BOR Reset, if enabled

Upon entering Sleep mode, the following conditions

exist:

3. POR Reset

1. WDT will be cleared but keeps running, if

enabled for operation during Sleep.

4. Watchdog Timer, if enabled

5. Any external interrupt

2. PD bit of the STATUS register is cleared.

3. TO bit of the STATUS register is set.

4. CPU clock is disabled.

6. Interrupts by peripherals capable of running dur-

ing Sleep (see individual peripheral for more

information)

5. 31 kHz LFINTOSC is unaffected and peripherals

that operate from it may continue operation in

Sleep.

The first three events will cause a device Reset. The

last three events are considered a continuation of pro-

gram execution. To determine whether a device Reset

or wake-up event occurred, refer to Section 7.10

“Determining the Cause of a Reset”.

6. Timer1 oscillator is unaffected and peripherals

that operate from it may continue operation in

Sleep.

7. ADC is unaffected, if the dedicated FRC clock is

selected.

When the SLEEPinstruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be enabled. Wake-up will

occur regardless of the state of the GIE bit. If the GIE

bit is disabled, the device continues execution at the

instruction after the SLEEPinstruction. If the GIE bit is

enabled, the device executes the instruction after the

SLEEPinstruction, the device will call the Interrupt Ser-

vice Routine. In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NOPafter the SLEEPinstruction.

8. Capacitive Sensing oscillator is unaffected.

9. I/O ports maintain the status they had before

SLEEPwas executed (driving high, low or high-

impedance).

10. Resets other than WDT are not affected by

Sleep mode.

Refer to individual chapters for more details on

peripheral operation during Sleep.

To minimize current consumption, the following condi-

tions should be considered:

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

• I/O pins should not be floating

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using 31 kHz LFINTOSC

• Modules using Timer1 oscillator

I/O pins that are high-impedance inputs should be

pulled to VDD or VSS externally to avoid switching cur-

rents caused by floating inputs.

Examples of internal circuitry that might be sourcing

current include modules such as the DAC and FVR

modules. See Section 16.0 “Digital-to-Analog

Converter (DAC) Module” and Section 14.0 “Fixed

Voltage Reference (FVR)” for more information on

these modules.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 101

PIC16F/LF1826/27

• If the interrupt occurs during or after the execu-

tion of a SLEEPinstruction

9.1.1

WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

- SLEEPinstruction will be completely exe-

cuted

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared

- TO bit of the STATUS register will be set

- PD bit of the STATUS register will be cleared.

• If the interrupt occurs before the execution of a

SLEEPinstruction

- SLEEPinstruction will execute as a NOP.

- WDT and WDT prescaler will not be cleared

- TO bit of the STATUS register will not be set

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEPinstruction completes. To

determine whether a SLEEPinstruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

- PD bit of the STATUS register will not be

cleared.

FIGURE 9-1:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1⁽¹⁾

(3)

CLKOUT⁽²⁾

TOST

Interrupt Latency⁽⁴⁾

Interrupt flag

GIE bit

(INTCON reg.)

Processor in

Sleep

Instruction Flow

PC

PC + 1

PC + 2

0004h

0005h

Instruction

Fetched

Inst(0004h)

Inst(PC + 1)

Inst(PC + 2)

Inst(0005h)

Inst(PC) = Sleep

Instruction

Executed

Dummy Cycle

Sleep

Inst(PC + 1)

Inst(PC - 1)

Inst(0004h)

Note 1:

XT, HS or LP Oscillator mode assumed.

CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference.

TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes.

2:

3:

4:

GIE = 1assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

TABLE 9-1:

SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Register on

Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

IOCBF

IOCBN

IOCBP

PIE1

GIE

IOCBF7

IOCBN7

IOCBP7

TMR1GIE

OSFIE

PEIE

IOCBF6

IOCBN6

IOCBP6

ADIE

TMR0IE

IOCBF5

IOCBN5

IOCBP5

RCIE

INTE

IOCBF4

IOCBN4

IOCBP4

TXIE

IOCIE

IOCBF3

IOCBN3

IOCBP3

SSP1IE

BCL1IE

—

TMR0IF

IOCBF2

IOCBN2

IOCBP2

CCP1IE

—

INTF

IOCBF1

IOCBN1

IOCBP1

TMR2IE

—

IOCIF

91

134

92

IOCBF0

IOCBN0

IOCBP0

TMR1IE

(1)

PIE2

C2IE

C1IE

EEIE

CCP2IE

SSP2IE

TMR1IF

93

(1)

BCL2IE

TMR2IF

—

PIE4

—

CCP1IF

—

95

TMR1GIF

OSFIF

ADIF

RCIF

TXIF

SSP1IF

BCL1IF

PIR1

PIR2

96

(1)

C2IF

C1IF

EEIF

CCP2IF

SSP2IF

97

(1)

BCL2IF

PIR4

—

Z

99

23

STATUS

TO

PD

DC

C

WDTCON

WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN

105

Legend:

— = unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode.

Note 1: PIC16F/LF1827 only.

DS41391C-page 102

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

10.0 WATCHDOG TIMER

The Watchdog Timer is a system timer that generates

a Reset if the firmware does not issue a CLRWDT

instruction within the time-out period. The Watchdog

Timer is typically used to recover the system from

unexpected events.

The WDT has the following features:

• Independent clock source

• Multiple operating modes

- WDT is always on

- WDT is off when in Sleep

- WDT is controlled by software

- WDT is always off

• Configurable time-out period is from 1 ms to 256

seconds (typical)

• Multiple Reset conditions

• Operation during Sleep

FIGURE 10-1:

WATCHDOG TIMER BLOCK DIAGRAM

WDTE<1:0> = 01

SWDTEN

23-bit Programmable

WDT Time-out

WDTE<1:0> = 11

LFINTOSC

Prescaler WDT

WDTE<1:0> = 10

Sleep

WDTPS<4:0>

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 103

PIC16F/LF1826/27

10.1 Independent Clock Source

10.3 Time-Out Period

The WDT derives its time base from the 31 kHz

LFINTOSC internal oscillator.

The WDTPS bits of the WDTCON register set the

time-out period from 1 ms to 256 seconds. After a

Reset, the default time-out period is 2 seconds.

10.2 WDT Operating Modes

10.4 Clearing the WDT

The Watchdog Timer module has four operating modes

controlled by the WDTE<1:0> bits in Configuration

Word 1. See Table 10-1.

The WDT is cleared when any of the following condi-

tions occur:

• Any Reset

10.2.1

WDT IS ALWAYS ON

• CLRWDTinstruction is executed

• Device enters Sleep

When the WDTE bits of Configuration Word 1 are set to

‘11’, the WDT is always on.

• Device wakes up from Sleep

• Oscillator fail event

WDT protection is active during Sleep.

• WDT is disabled

10.2.2

WDT IS OFF IN SLEEP

• Oscillator Start-up TImer (OST) is running

When the WDTE bits of Configuration Word 1 are set to

See Table 10-2 for more information.

‘10’, the WDT is on, except in Sleep.

WDT protection is not active during Sleep.

10.5 Operation During Sleep

10.2.3

WDT CONTROLLED BY SOFTWARE

When the device enters Sleep, the WDT is cleared. If

the WDT is enabled during Sleep, the WDT resumes

counting.

When the WDTE bits of Configuration Word 1 are set to

‘01’, the WDT is controlled by the SWDTEN bit of the

WDTCON register.

When the device exits Sleep, the WDT is cleared

again. The WDT remains clear until the OST, if

enabled, completes. See Section 5.0 “Oscillator

Module (With Fail-Safe Clock Monitor)” for more

information on the OST.

WDT protection is unchanged by Sleep. See

Table 10-1 for more details.

TABLE 10-1: WDT OPERATING MODES

When a WDT time-out occurs while the device is in

Sleep, no Reset is generated. Instead, the device

wakes up and resumes operation. The TO and PD bits

in the STATUS register are changed to indicate the

event. See Section 3.0 “Memory Organization” for

more information.

WDTE

Config bits

Device

Mode

WDT

Mode

SWDTEN

WDT_ON (11)

X

1

0

X

Active

WDT_NSLEEP (10)

WDT_SWDTEN (01)

WDT_OFF (00)

Awake

Sleep Disabled

X

Active

Disabled

TABLE 10-2: WDT CLEARING CONDITIONS

Conditions

WDT

WDTE<1:0> = 00

WDTE<1:0> = 01 and SWDTEN = 0

WDTE<1:0> = 10 and enter Sleep

CLRWDTCommand

Cleared

Oscillator Fail Detected

Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP

Cleared until the end of OST

Unaffected

Change INTOSC divider (IRCF bits)

DS41391C-page 104

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0

—

U-0

—

R/W-0/0

R/W-1/1

R/W-0/0

R/W-1/1

R/W-0/0

WDTPS<4:0>

SWDTEN

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-m/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-1

Unimplemented: Read as ‘0’

WDTPS<4:0>: Watchdog Timer Period Select bits

Bit Value = Prescale Rate

00000 = 1:32 (Interval 1 ms typ)

00001 = 1:64 (Interval 2 ms typ)

00010 = 1:128 (Interval 4 ms typ)

00011 = 1:256 (Interval 8 ms typ)

00100 = 1:512 (Interval 16 ms typ)

00101 = 1:1024 (Interval 32 ms typ)

00110 = 1:2048 (Interval 64 ms typ)

00111 = 1:4096 (Interval 128 ms typ)

01000 = 1:8192 (Interval 256 ms typ)

01001 = 1:16384 (Interval 512 ms typ)

01010 = 1:32768 (Interval 1s typ)

01011 = 1:65536 (Interval 2s typ) (Reset value)

01100 = 1:131072 (2¹⁷) (Interval 4s typ)

01101 = 1:262144 (2¹⁸) (Interval 8s typ)

01110 = 1:524288 (2¹⁹) (Interval 16s typ)

01111 = 1:1048576 (2²⁰) (Interval 32s typ)

10000 = 1:2097152 (2²¹) (Interval 64s typ)

10001 = 1:4194304 (2²²) (Interval 128s typ)

10010 = 1:8388608 (2²³) (Interval 256s typ)

10011 = Reserved. Results in minimum interval (1:32)

•

11111 = Reserved. Results in minimum interval (1:32)

bit 0

SWDTEN: Software Enable/Disable for Watchdog Timer bit

If WDTE<1:0> = 00:

This bit is ignored.

If WDTE<1:0> = 01:

1= WDT is turned on

0= WDT is turned off

If WDTE<1:0> = 1x:

This bit is ignored.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 105

PIC16F/LF1826/27

NOTES:

DS41391C-page 106

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

11.1 EEADRL and EEADRH Registers

11.0 DATA EEPROM AND FLASH

PROGRAM MEMORY

CONTROL

The EEADRH:EEADRL register pair can address up to

a maximum of 256 bytes of data EEPROM or up to a

maximum of 32K words of program memory.

The Data EEPROM and Flash program memory are

readable and writable during normal operation (full VDD

range). These memories are not directly mapped in the

register file space. Instead, they are indirectly

addressed through the Special Function Registers

(SFRs). There are six SFRs used to access these

memories:

When selecting a program address value, the MSB of

the address is written to the EEADRH register and the

LSB is written to the EEADRL register. When selecting

a EEPROM address value, only the LSB of the address

is written to the EEADRL register.

11.1.1

EECON1 AND EECON2 REGISTERS

• EECON1

• EECON2

• EEDATL

• EEDATH

• EEADRL

• EEADRH

EECON1 is the control register for EE memory

accesses.

Control bit EEPGD determines if the access will be a

program or data memory access. When clear, any

subsequent operations will operate on the EEPROM

memory. When set, any subsequent operations will

operate on the program memory. On Reset, EEPROM is

selected by default.

When interfacing the data memory block, EEDATL

holds the 8-bit data for read/write, and EEADRL holds

the address of the EEDATL location being accessed.

These devices have 256 bytes of data EEPROM with

an address range from 0h to 0FFh.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set, in

software. They are cleared in hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

When accessing the program memory block, the EED-

ATH:EEDATL register pair forms a 2-byte word that

holds the 14-bit data for read/write, and the EEADRL

and EEADRH registers form a 2-byte word that holds

the 15-bit address of the program memory location

being read.

The WREN bit, when set, will allow a write operation to

occur. On power-up, the WREN bit is clear. The

WRERR bit is set when a write operation is interrupted

by a Reset during normal operation. In these situations,

following Reset, the user can check the WRERR bit

and execute the appropriate error handling routine.

The EEPROM data memory allows byte read and write.

An EEPROM byte write automatically erases the loca-

tion and writes the new data (erase before write).

Interrupt flag bit EEIF of the PIR2 register is set when

write is complete. It must be cleared in the software.

The write time is controlled by an on-chip timer. The

write/erase voltages are generated by an on-chip

charge pump rated to operate over the voltage range of

the device for byte or word operations.

Reading EECON2 will read all ‘0’s. The EECON2 reg-

ister is used exclusively in the data EEPROM write

sequence. To enable writes, a specific pattern must be

written to EECON2.

Depending on the setting of the Flash Program

Memory Self Write Enable bits WRT<1:0> of the

Configuration Word 2, the device may or may not be

able to write certain blocks of the program memory.

However, reads from the program memory are always

allowed.

When the device is code-protected, the device

programmer can no longer access data or program

memory. When code-protected, the CPU may continue

to read and write the data EEPROM memory and Flash

program memory.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 107

PIC16F/LF1826/27

11.2.2

WRITING TO THE DATA EEPROM

MEMORY

11.2 Using the Data EEPROM

The data EEPROM is a high-endurance, byte address-

able array that has been optimized for the storage of

frequently changing information (e.g., program vari-

ables or other data that are updated often). When vari-

ables in one section change frequently, while variables

in another section do not change, it is possible to

exceed the total number of write cycles to the

EEPROM without exceeding the total number of write

cycles to a single byte. Refer to Section 29.0 “Electri-

cal Specifications”. If this is the case, then a refresh

of the array must be performed. For this reason, vari-

ables that change infrequently (such as constants, IDs,

calibration, etc.) should be stored in Flash program

memory.

To write an EEPROM data location, the user must first

write the address to the EEADRL register and the data

to the EEDATL register. Then the user must follow a

specific sequence to initiate the write for each byte.

The write will not initiate if the above sequence is not

followed exactly (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. Interrupts

should be disabled during this code segment.

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental

writes to data EEPROM due to errant (unexpected)

code execution (i.e., lost programs). The user should

keep the WREN bit clear at all times, except when

updating EEPROM. The WREN bit is not cleared

by hardware.

11.2.1

READING THE DATA EEPROM

MEMORY

After a write sequence has been initiated, clearing the

WREN bit will not affect this write cycle. The WR bit will

be inhibited from being set unless the WREN bit is set.

To read a data memory location, the user must write the

address to the EEADRL register, clear the EEPGD and

CFGS control bits of the EECON1 register, and then

set control bit RD. The data is available at the very next

cycle, in the EEDATL register; therefore, it can be read

in the next instruction. EEDATL will hold this value until

another read or until it is written to by the user (during

a write operation).

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. EEIF must be

cleared by software.

11.2.3

PROTECTION AGAINST SPURIOUS

WRITE

EXAMPLE 11-1:

DATA EEPROM READ

BANKSELEEADRL

;

There are conditions when the user may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built-in. On power-up, WREN is cleared. Also, the

Power-up Timer (64 ms duration) prevents EEPROM

write.

MOVLW DATA_EE_ADDR ;

MOVWF EEADRL ;Data Memory

;Address to read

BCF

BSF

MOVF

EECON1, CFGS ;Deselect Config space

EECON1, EEPGD;Point to DATA memory

EECON1, RD

EEDATL, W

;EE Read

;W = EEDATL

The write initiate sequence and the WREN bit together

help prevent an accidental write during:

• Brown-out

Note:

Data EEPROM can be read regardless of

the setting of the CPD bit.

• Power Glitch

• Software Malfunction

11.2.4

DATA EEPROM OPERATION

DURING CODE-PROTECT

Data memory can be code-protected by programming

the CPD bit in the Configuration Word 1 (Register 5-1)

to ‘0’.

When the data memory is code-protected, only the

CPU is able to read and write data to the data

EEPROM. It is recommended to code-protect the pro-

gram memory when code-protecting data memory.

This prevents anyone from replacing your program with

a program that will access the contents of the data

EEPROM.

DS41391C-page 108

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

EXAMPLE 11-2:

DATA EEPROM WRITE

BANKSEL EEADRL

;

MOVLW

MOVWF

MOVLW

MOVWF

BCF

DATA_EE_ADDR

EEADRL

DATA_EE_DATA

EEDATL

;

;Data Memory Address to write

;

;Data Memory Value to write

;Deselect Configuration space

EECON1, CFGS

BCF

EECON1, EEPGD ;Point to DATA memory

BSF

EECON1, WREN

;Enable writes

BCF

INTCON, GIE

55h

EECON2

0AAh

EECON2

EECON1, WR

INTCON, GIE

EECON1, WREN

EECON1, WR

$-2

;Disable INTs.

;

;Write 55h

;

MOVLW

MOVWF

MOVLW

MOVWF

BSF

BCF

BTFSC

GOTO

;Write AAh

;Set WR bit to begin write

;Enable Interrupts

;Disable writes

;Wait for write to complete

;Done

FIGURE 11-1:

FLASH PROGRAM MEMORY READ CYCLE EXECUTION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

PC + 1

EEADRH,EEADRL

PC + 3

PC+3

PC + 4

PC + 5

Flash ADDR

Flash Data

INSTR (PC)

INSTR (PC + 1)

EEDATH,EEDATL

INSTR (PC + 3)

INSTR (PC + 4)

BSF EECON1,RD

executed here

INSTR(PC - 1)

executed here

INSTR(PC + 1)

executed here

Forced NOP

executed here

INSTR(PC + 3)

executed here

INSTR(PC + 4)

executed here

RD bit

EEDATH

EEDATL

Register

EERHLT

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 109

PIC16F/LF1826/27

11.3.1

READING THE FLASH PROGRAM

MEMORY

11.3 Flash Program Memory Overview

It is important to understand the Flash program mem-

ory structure for erase and programming operations.

Flash Program memory is arranged in rows. A row con-

sists of a fixed number of 14-bit program memory

words. A row is the minimum block size that can be

erased by user software.

To read a program memory location, the user must:

1. Write the Least and Most Significant address

bits to the EEADRH:EEADRL register pair.

2. Clear the CFGS bit of the EECON1 register.

3. Set the EEPGD control bit of the EECON1

register.

Flash program memory may only be written or erased

if the destination address is in a segment of memory

that is not write-protected, as defined in bits WRT<1:0>

of Configuration Word 2.

4. Then, set control bit RD of the EECON1 register.

Once the read control bit is set, the program memory

Flash controller will use the second instruction cycle to

read the data. This causes the second instruction

immediately following the “BSF EECON1,RD” instruction

to be ignored. The data is available in the very next cycle,

in the EEDATH:EEDATL register pair; therefore, it can

be read as two bytes in the following instructions.

After a row has been erased, the user can reprogram

all or a portion of this row. Data to be written into the

program memory row is written to 14-bit wide data write

latches. These write latches are not directly accessible

to the user, but may be loaded via sequential writes to

the EEDATH:EEDATL register pair.

EEDATH:EEDATL register pair will hold this value until

another read or until it is written to by the user.

Note:

If the user wants to modify only a portion

of a previously programmed row, then the

contents of the entire row must be read

and saved in RAM prior to the erase.

Note 1: The two instructions following a program

memory read are required to be NOPs.

This prevents the user from executing a

two-cycle instruction on the next

instruction after the RD bit is set.

The number of data write latches is not equivalent to

the number of row locations. During programming, user

software will need to fill the set of write latches and ini-

tiate a programming operation multiple times in order to

fully reprogram an erased row. For example, a device

with a row size of 32 words and eight write latches will

need to load the write latches with data and initiate a

programming operation four times.

2: Flash program memory can be read

regardless of the setting of the CP bit.

The size of a program memory row and the number of

program memory write latches may vary by device.

See Table 11-1 for details.

TABLE 11-1: FLASH MEMORY

ORGANIZATION BY DEVICE

Erase Block

Number of

Device

(Row) Size/ Write Latches/

Boundary

PIC16F/LF1826/27

32 words,

EEADRL<4:0 EEADRL<4:0>

> = 00000 = 00000

DS41391C-page 110

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

EXAMPLE 11-3:

FLASH PROGRAM MEMORY READ

* This code block will read 1 word of program

* memory at the memory address:

PROG_ADDR_HI : PROG_ADDR_LO

*

data will be returned in the variables;

PROG_DATA_HI, PROG_DATA_LO

BANKSEL EEADRL

; Select Bank for EEPROM registers

MOVLW

MOVWF

MOVLW

MOVWL

PROG_ADDR_LO

EEADRL

PROG_ADDR_HI

EEADRH

;

; Store LSB of address

;

; Store MSB of address

BCF

BSF

BCF

BSF

NOP

BSF

EECON1,CFGS

EECON1,EEPGD

INTCON,GIE

EECON1,RD

; Do not select Configuration Space

; Select Program Memory

; Disable interrupts

; Initiate read

; Executed (Figure 11-1)

; Ignored (Figure 11-1)

; Restore interrupts

INTCON,GIE

MOVF

EEDATL,W

; Get LSB of word

MOVWF

MOVF

PROG_DATA_LO

EEDATH,W

; Store in user location

; Get MSB of word

MOVWF

PROG_DATA_HI

; Store in user location

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 111

PIC16F/LF1826/27

The following steps should be completed to load the

write latches and program a block of program memory.

These steps are divided into two parts. First, all write

latches are loaded with data except for the last program

memory location. Then, the last write latch is loaded

and the programming sequence is initiated. A special

unlock sequence is required to load a write latch with

data or initiate a Flash programming operation. This

unlock sequence should not be interrupted.

11.3.2

ERASING FLASH PROGRAM

MEMORY

While executing code, program memory can only be

erased by rows. To erase a row:

1. Load the EEADRH:EEADRL register pair with

the address of new row to be erased.

2. Clear the CFGS bit of the EECON1 register.

3. Set the EEPGD, FREE, and WREN bits of the

EECON1 register.

1. Set the EEPGD and WREN bits of the EECON1

register.

4. Write 55h, then AAh, to EECON2 (Flash

programming unlock sequence).

2. Clear the CFGS bit of the EECON1 register.

5. Set control bit WR of the EECON1 register to

begin the erase operation.

3. Set the LWLO bit of the EECON1 register. When

the LWLO bit of the EECON1 register is ‘1’, the

write sequence will only load the write latches

and will not initiate the write to Flash program

memory.

6. Poll the FREE bit in the EECON1 register to

determine when the row erase has completed.

See Example 11-4.

4. Load the EEADRH:EEADRL register pair with

the address of the location to be written.

After the “BSF EECON1,WR” instruction, the processor

requires two cycles to set up the erase operation. The

user must place two NOPinstructions after the WR bit is

set. The processor will halt internal operations for the

typical 2 ms erase time. This is not Sleep mode as the

clocks and peripherals will continue to run. After the

erase cycle, the processor will resume operation with

the third instruction after the EECON1 write instruction.

5. Load the EEDATH:EEDATL register pair with

the program memory data to be written.

6. Write 55h, then AAh, to EECON2, then set the

WR bit of the EECON1 register (Flash

programming unlock sequence). The write latch

is now loaded.

7. Increment the EEADRH:EEADRL register pair

to point to the next location.

11.3.3

WRITING TO FLASH PROGRAM

MEMORY

8. Repeat steps 5 through 7 until all but the last

write latch has been loaded.

Program memory is programmed using the following

steps:

9. Clear the LWLO bit of the EECON1 register.

When the LWLO bit of the EECON1 register is

‘0’, the write sequence will initiate the write to

Flash program memory.

1. Load the starting address of the word(s) to be

programmed.

2. Load the write latches with data.

10. Load the EEDATH:EEDATL register pair with

the program memory data to be written.

3. Initiate a programming operation.

4. Repeat steps 1 through 3 until all data is written.

11. Write 55h, then AAh, to EECON2, then set the

WR bit of the EECON1 register (Flash

programming unlock sequence). The entire

latch block is now written to Flash program

memory.

Before writing to program memory, the word(s) to be

written must be erased or previously unwritten. Pro-

gram memory can only be erased one row at a time. No

automatic erase occurs upon the initiation of the write.

Program memory can be written one or more words at

a time. The maximum number of words written at one

time is equal to the number of write latches. See

Figure 11-2 (block writes to program memory with 32

write latches) for more details. The write latches are

aligned to the address boundary defined by EEADRL

as shown in Table 11-1. Write operations do not cross

these boundaries. At the completion of a program

memory write operation, the write latches are reset to

contain 0x3FFF.

It is not necessary to load the entire write latch block

with user program data. However, the entire write latch

block will be written to program memory.

An example of the complete write sequence for eight

words is shown in Example 11-5. The initial address is

loaded into the EEADRH:EEADRL register pair; the

eight words of data are loaded using indirect addressing.

Note:

If the number of write latches is smaller

than the erase block size, the code

sequence provided in Example 11-5 must

be repeated multiple times to fully program

an erased program memory row.

DS41391C-page 112

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

After the “BSF EECON1,WR” instruction, the processor

requires two cycles to set up the write operation. The

user must place two NOPinstructions after the WR bit is

set. The processor will halt internal operations for the

typical 2 ms, only during the cycle in which the write

takes place (i.e., the last word of the block write). This

is not Sleep mode as the clocks and peripherals will

continue to run. The processor does not stall when

LWLO = 1, loading the write latches. After the write

cycle, the processor will resume operation with the third

instruction after the EECON1 write instruction.

FIGURE 11-2:

BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES

7

5

0

0 7

EEDATH

6

EEDATA

8

Last word of block

to be written

First word of block

to be written

14

EEADRL<4:0> = 00000

EEADRL<4:0> = 00001

EEADRL<4:0> = 00010

EEADRL<4:0> = 11111

Buffer Register

Program Memory

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 113

PIC16F/LF1826/27

EXAMPLE 11-4:

ERASING ONE ROW OF PROGRAM MEMORY -

; This row erase routine assumes the following:

; 1. A valid address within the erase block is loaded in ADDRH:ADDRL

; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F

BCF

INTCON,GIE

EEADRL

ADDRL,W

EEADRL

ADDRH,W

; Disable ints so required sequences will execute properly

; Load lower 8 bits of erase address boundary

; Load upper 6 bits of erase address boundary

BANKSEL

MOVF

MOVWF

MOVF

MOVWF

BSF

BCF

BSF

EEADRH

EECON1,EEPGD

EECON1,CFGS

EECON1,FREE

EECON1,WREN

; Point to program memory

; Not configuration space

; Specify an erase operation

; Enable writes

MOVLW

MOVWF

MOVLW

MOVWF

BSF

55h

EECON2

0AAh

EECON2

EECON1,WR

; Start of required sequence to initiate erase

; Write 55h

;

; Write AAh

; Set WR bit to begin erase

; Any instructions here are ignored as processor

; halts to begin erase sequence

; Processor will stop here and wait for erase complete.

NOP

; after erase processor continues with 3rd instruction

BCF

BSF

EECON1,WREN

INTCON,GIE

; Disable writes

; Enable interrupts

DS41391C-page 114

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

EXAMPLE 11-5:

WRITING TO FLASH PROGRAM MEMORY

; This write routine assumes the following:

; 1. The 16 bytes of data are loaded, starting at the address in DATA_ADDR

; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,

;

stored in little endian format

; 3. A valid starting address (the least significant bits = 000) is loaded in ADDRH:ADDRL

; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F

;

BCF

INTCON,GIE

EEADRH

ADDRH,W

EEADRH

ADDRL,W

EEADRL

; Disable ints so required sequences will execute properly

; Bank 3

; Load initial address

;

BANKSEL

MOVF

MOVWF

MOVF

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

LOW DATA_ADDR ; Load initial data address

FSR0L

HIGH DATA_ADDR ; Load initial data address

;

FSR0H

;

EECON1,EEPGD

EECON1,CFGS

EECON1,WREN

EECON1,LWLO

; Point to program memory

; Not configuration space

; Enable writes

BCF

BSF

; Only Load Write Latches

LOOP

MOVIW

MOVWF

MOVIW

MOVWF

FSR0++

EEDATL

FSR0++

EEDATH

; Load first data byte into lower

;

; Load second data byte into upper

;

MOVF

EEADRL,W

0x07

STATUS,Z

START_WRITE

; Check if lower bits of address are '000'

; Check if we're on the last of 8 addresses

;

; Exit if last of eight words,

;

XORLW

ANDLW

BTFSC

GOTO

MOVLW

MOVWF

MOVLW

MOVWF

BSF

55h

EECON2

0AAh

EECON2

EECON1,WR

; Start of required write sequence:

; Write 55h

;

; Write AAh

; Set WR bit to begin write

NOP

; Any instructions here are ignored as processor

; halts to begin write sequence

NOP

; Processor will stop here and wait for write to complete.

; After write processor continues with 3rd instruction.

INCF

GOTO

EEADRL,F

LOOP

; Still loading latches Increment address

; Write next latches

START_WRITE

BCF

EECON1,LWLO

; No more loading latches - Actually start Flash program

; memory write

MOVLW

55h

EECON2

0AAh

EECON2

EECON1,WR

; Start of required write sequence:

; Write 55h

;

MOVWF

MOVLW

MOVWF

BSF

; Write AAh

; Set WR bit to begin write

; Any instructions here are ignored as processor

; halts to begin write sequence

; Processor will stop here and wait for write complete.

NOP

; after write processor continues with 3rd instruction

; Disable writes

; Enable interrupts

BCF

BSF

EECON1,WREN

INTCON,GIE

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 115

PIC16F/LF1826/27

11.4 Modifying Flash Program Memory

11.5 User ID, Device ID and

Configuration Word Access

When modifying existing data in a program memory

row, and data within that row must be preserved, it must

first be read and saved in a RAM image. Program

memory is modified using the following steps:

Instead of accessing program memory or EEPROM

data memory, the User ID’s, Device ID/Revision ID and

Configuration Words can be accessed when CFGS = 1

in the EECON1 register. This is the region that would

be pointed to by PC<15> = 1, but not all addresses are

accessible. Different access may exist for reads and

writes. Refer to Table 11-2.

1. Load the starting address of the row to be mod-

ified.

2. Read the existing data from the row into a RAM

image.

When read access is initiated on an address outside

the parameters listed in Table 11-2, the EEDATH:EED-

ATL register pair is cleared.

3. Modify the RAM image to contain the new data

to be written into program memory.

4. Load the starting address of the row to be rewrit-

ten.

5. Erase the program memory row.

6. Load the write latches with data from the RAM

image.

7. Initiate a programming operation.

8. Repeat steps 6 and 7 as many times as required

to reprogram the erased row.

TABLE 11-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)

Address

Function

Read Access

Write Access

8000h-8003h

8006h

User IDs

Yes

No

Device ID/Revision ID

Configuration Words 1 and 2

8007h-8008h

EXAMPLE 11-3: CONFIGURATION WORD AND DEVICE ID ACCESS

* This code block will read 1 word of program memory at the memory address:

*

PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;

PROG_DATA_HI, PROG_DATA_LO

BANKSEL EEADRL

; Select correct Bank

;

; Store LSB of address

; Clear MSB of address

MOVLW

MOVWF

CLRF

PROG_ADDR_LO

EEADRL

EEADRH

BSF

BCF

BSF

NOP

BSF

EECON1,CFGS

INTCON,GIE

EECON1,RD

; Select Configuration Space

; Disable interrupts

; Initiate read

; Executed (See Figure 11-1)

; Ignored (See Figure 11-1)

; Restore interrupts

INTCON,GIE

MOVF

EEDATL,W

; Get LSB of word

MOVWF

MOVF

PROG_DATA_LO

EEDATH,W

; Store in user location

; Get MSB of word

MOVWF

PROG_DATA_HI

; Store in user location

DS41391C-page 116

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

11.6 Write Verify

Depending on the application, good programming

practice may dictate that the value written to the data

EEPROM or program memory should be verified (see

Example 11-6) to the desired value to be written.

Example 11-6 shows how to verify a write to EEPROM.

EXAMPLE 11-6:

EEPROM WRITE VERIFY

BANKSELEEDATL

;

MOVF

EEDATL, W ;EEDATL not changed

;from previous write

BSF

EECON1, RD ;YES, Read the

;value written

XORWF EEDATL, W ;

BTFSS STATUS, Z ;Is data the same

GOTO

:

WRITE_ERR ;No, handle error

;Yes, continue

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 117

PIC16F/LF1826/27

REGISTER 11-1: EEDATL: EEPROM DATA REGISTER

R/W-x/u

EEDAT<7:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-0

EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory

REGISTER 11-2: EEDATH: EEPROM DATA HIGH BYTE REGISTER

U-0

—

U-0

—

R/W-x/u

EEDAT<13:8>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

EEDAT<13:8>: Read/write value for Most Significant bits of program memory

REGISTER 11-3: EEADRL: EEPROM ADDRESS REGISTER

R/W-0/0

EEADR<7:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-0

EEADR<7:0>: Specifies the Least Significant bits for program memory address or EEPROM address

REGISTER 11-4: EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER

U-1

—

R/W-0/0

EEADR<14:8>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

Unimplemented: Read as ‘0’

EEADR<14:8>: Specifies the Most Significant bits for program memory address or EEPROM address

bit 6-0

DS41391C-page 118

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

REGISTER 11-5: EECON1: EEPROM CONTROL 1 REGISTER

R/W-0/0

EEPGD

R/W-0/0

CFGS

R/W-0/0

LWLO

R/W/HC-0/0

FREE

R/W-x/q

WRERR

R/W-0/0

WREN

R/S/HC-0/0 R/S/HC-0/0

WR RD

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

S = Bit can only be set

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

HC = Bit is cleared by hardware

bit 7

bit 6

bit 5

EEPGD: Flash Program/Data EEPROM Memory Select bit

1= Accesses program space Flash memory

0= Accesses data EEPROM memory

CFGS: Flash Program/Data EEPROM or Configuration Select bit

1= Accesses Configuration, User ID and Device ID Registers

0= Accesses Flash Program or data EEPROM Memory

LWLO: Load Write Latches Only bit

If CFGS = 1(Configuration space) OR CFGS = 0and EEPGD = 1 (program Flash):

1= The next WR command does not initiate a write; only the program memory latches are

updated.

0= The next WR command writes a value from EEDATH:EEDATL into program memory latches

and initiates a write of all the data stored in the program memory latches.

If CFGS = 0and EEPGD = 0: (Accessing data EEPROM)

LWLO is ignored. The next WR command initiates a write to the data EEPROM.

bit 4

FREE: Program Flash Erase Enable bit

If CFGS = 1(Configuration space) OR CFGS = 0and EEPGD = 1 (program Flash):

1= Performs an erase operation on the next WR command (cleared by hardware after comple-

tion of erase).

0= Performs a write operation on the next WR command.

If EEPGD = 0 and CFGS = 0: (Accessing data EEPROM)

FREE is ignored. The next WR command will initiate both a erase cycle and a write cycle.

bit 3

WRERR: EEPROM Error Flag bit

1= Condition indicates an improper program or erase sequence attempt or termination (bit is set

automatically on any set attempt (write ‘1’) of the WR bit).

0= The program or erase operation completed normally.

bit 2

bit 1

WREN: Program/Erase Enable bit

1= Allows program/erase cycles

0= Inhibits programming/erasing of program Flash and data EEPROM

WR: Write Control bit

1= Initiates a program Flash or data EEPROM program/erase operation.

The operation is self-timed and the bit is cleared by hardware once operation is complete.

The WR bit can only be set (not cleared) in software.

0= Program/erase operation to the Flash or data EEPROM is complete and inactive.

bit 0

RD: Read Control bit

1= Initiates an program Flash or data EEPROM read. Read takes one cycle. RD is cleared in

hardware. The RD bit can only be set (not cleared) in software.

0= Does not initiate a program Flash or data EEPROM data read.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 119

PIC16F/LF1826/27

REGISTER 11-6: EECON2: EEPROM CONTROL 2 REGISTER

W-0/0

bit 0

EEPROM Control Register 2

bit 7

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

S = Bit can only be set

‘1’ = Bit is set

bit 7-0

Data EEPROM Unlock Pattern bits

To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the

EECON1 register. The value written to this register is used to unlock the writes. There are specific

timing requirements on these writes. Refer to Section 11.2.2 “Writing to the Data EEPROM

Memory” for more information.

TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EECON1 EEPGD

CFGS

LWLO

FREE

WRERR

WREN

WR

RD

119

107*

118

EECON2 EEPROM Control Register 2 (not a physical register)

EEADRL EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0

EEADRH EEADRH6 EEADRH5 EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0

EEDATL EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDALT1 EEDATL0

—

EEDATH

INTCON

PIE2

—

EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0

GIE

PEIE

C2IE

C2IF

TMR0IE

C1IE

INTE

EEIE

EEIF

IOCIE

BCL1IE

BCL1IF

TMR0IF

INTF

—

IOCIF

CCP2IE

CCP2IF

91

93

97

OSFIE

OSFIF

—

PIR2

C1IF

—

Legend: — = unimplemented read as ‘0’. Shaded cells are not used by Data EEPROM module.

Page provides register information.

*

DS41391C-page 120

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

12.1 Alternate Pin Function

12.0 I/O PORTS

The Alternate Pin Function Control (APFCON0 and

APFCON1) registers are used to steer specific

peripheral input and output functions between different

pins. The APFCON0 and APFCON1 registers are

shown in Register 12-1 and Register 12-2. For this

device family, the following functions can be moved

between different pins.

Depending on the device selected and peripherals

enabled, there are two ports available. In general,

when a peripheral is enabled, that pin may not be used

as a general purpose I/O pin.

Each port has three registers for its operation. These

registers are:

• TRISx registers (data direction register)

• RX/DT

• PORTx registers (reads the levels on the pins of

the device)

• SDO1

• SS1 (Slave Select 1)

• P2B

• LATx registers (output latch)

The Data Latch (LATx registers) is useful for

read-modify-write operations on the value that the I/O

pins are driving.

• CCP2/P2A

• P1D

• P1C

A write operation to the LATx register has the same

affect as a write to the corresponding PORTx register.

A read of the LATx register reads of the values held in

the I/O PORT latches, while a read of the PORTx

register reads the actual I/O pin value.

• CCP1/P1A

• TX/CK

These bits have no effect on the values of any TRIS

register. PORT and TRIS overrides will be routed to the

correct pin. The unselected pin will be unaffected.

Ports with analog functions also have an ANSELx

register which can disable the digital input and save

power. A simplified model of a generic I/O port, without

the interfaces to other peripherals, is shown in

Figure 12-1.

FIGURE 12-1:

GENERIC I/O PORT

OPERATION

Read LATx

TRISx

D

Q

Write LATx

Write PORTx

CK

Data Register

VDD

Data Bus

Read PORTx

To peripherals

I/O pin

VSS

ANSELx

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 121

PIC16F/LF1826/27

REGISTER 12-1: APFCON0: ALTERNATE PIN FUNCTION CONTROL REGISTER 0

R/W-0/0

SS1SEL

R/W-0/0

P1DSEL

R/W-0/0

P1CSEL

R/W-0/0

(1)

RXDTSEL

SDO1SEL

P2BSEL

CCP2SEL

CCP1SEL

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

RXDTSEL: Pin Selection bit

0 = RX/DT function is on RB1

1 = RX/DT function is on RB2

SDO1SEL: Pin Selection bit

0 = SDO1 function is on RB2

1 = SDO1 function is on RA6

SS1SEL: Pin Selection bit

0 = SS1 function is on RB5

1 = SS1 function is on RA5

P2BSEL: Pin Selection bit

0 = P2B function is on RB7

1 = P2B function is on RA6

CCP2SEL: Pin Selection bit

0 = CCP2/P2A function is on RB6

1 = CCP2/P2A function is on RA7

P1DSEL: Pin Selection bit

0 = P1D function is on RB7

1 = P1D function is on RA6

P1CSEL: Pin Selection bit

0 = P1C function is on RB6

1 = P1C function is on RA7

CCP1SEL: Pin Selection bit

0 = CCP1/P1A function is on RB3

1 = CCP1/P1A function is on RB0

Note 1: PIC16F/LF1827 only.

REGISTER 12-2: APFCON1: ALTERNATE PIN FUNCTION CONTROL REGISTER 1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

TXCKSEL

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-1

bit 0

Unimplemented: Read as ‘0’

TXCKSEL: Pin Selection bit

0= TX/CK function is on RB2

1= TX/CK function is on RB5

DS41391C-page 122

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

12.2.2

ANSELA REGISTER

12.2 PORTA Registers

The ANSELA register (Register 12-7) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELA bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

PORTA is

a 8-bit wide, bidirectional port. The

corresponding data direction register is TRISA

(Register 12-4). Setting a TRISA bit (= 1) will make the

corresponding PORTA pin an input (i.e., disable the

output driver). Clearing a TRISA bit (= 0) will make the

corresponding PORTA pin an output (i.e., enables

output driver and puts the contents of the output latch

on the selected pin). The exception is RA5, which is

input only and its TRIS bit will always read as ‘1’.

Example 12-1 shows how to initialize PORTA.

The state of the ANSELA bits has no affect on digital

output functions. A pin with TRIS clear and ANSEL set

will still operate as a digital output, but the Input mode

will be analog. This can cause unexpected behavior

when executing read-modify-write instructions on the

affected port.

Reading the PORTA register (Register 12-3) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the PORT data latch (LATA).

The TRISA register (Register 12-4) controls the PORTA

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISA register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘0’.

The TRISA register (Register 12-4) controls the

PORTA pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits

in the TRISA register are maintained set when using

them as analog inputs. I/O pins configured as analog

input always read ‘0’.

Note:

The ANSELA register must be initialized to

configure an analog channel as a digital

input. Pins configured as analog inputs will

read ‘0’.

Note:

The ANSELA register must be initialized to

configure an analog channel as a digital

input. Pins configured as analog inputs will

read ‘0’.

EXAMPLE 12-1:

INITIALIZING PORTA

BANKSELPORTA

;

CLRF

BANKSELLATA

CLRF LATA

BANKSELANSELA

CLRF ANSELA

PORTA

;Init PORTA

;Data Latch

;

;digital I/O

BANKSELTRISA

MOVLW 0Ch

MOVWF TRISA

;

;Set RA<3:2> as inputs

;and set RA<7:4,1:0>

;as outputs

12.2.1

WEAK PULL-UPS

Each of the PORTA pins has an individually configurable

internal weak pull-up. Control bit WPUA<5> enables or

disables the pull-up (see Register 12-6). The weak

pull-up is automatically turned off when the port pin is

configured as an output. The pull-up is disabled on a

Power-on Reset by the WPUEN bit of the OPTION

register.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 123

PIC16F/LF1826/27

REGISTER 12-3: PORTA: PORTA REGISTER

R/W-x/x

RA7

R/W-x/x

RA6

R-x/x

RA5

R/W-x/x

RA4

R/W-x/x

RA3

R/W-x/x

RA2

R/W-x/x

RA1

R/W-x/x

RA0

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

(1)

bit 7-0

RA<7:0>: PORTA I/O Value bits

1= Port pin is > VIH

0= Port pin is < VIL

Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O

pin values.

REGISTER 12-4: TRISA: PORTA TRI-STATE REGISTER

R/W-1/1

TRISA7

R/W-1/1

TRISA6

R-1/1

R/W-1/1

TRISA4

R/W-1/1

TRISA3

R/W-1/1

TRISA2

R/W-1/1

TRISA1

R/W-1/1

TRISA0

TRISA5

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-6

TRISA<7:6>: PORTA Tri-State Control bit

1= PORTA pin configured as an input (tri-stated)

0= PORTA pin configured as an output

bit 5

TRISA5: RA5 Port Tri-State Control bit

This bit is always ‘1’ as RA5 is an input only

bit 4-0

TRISA<4:0>: PORTA Tri-State Control bit

1= PORTA pin configured as an input (tri-stated)

0= PORTA pin configured as an output

REGISTER 12-5: LATA: PORTA DATA LATCH REGISTER

R/W-x/u

LATA7

R/W-x/u

LATA6

U-0

—

R/W-x/u

LATA4

R/W-x/u

LATA3

R/W-x/u

LATA2

R/W-x/u

LATA1

R/W-x/u

LATA0

bit 0

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

(1)

bit 7-6

bit 5

LATA<7:6>: RA<7:6> Output Latch Value bits

Unimplemented: Read as ‘0

bit 4-0

LATA<4:0>: RA<4:0> Output Latch Value bits

Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O

pin values.

DS41391C-page 124

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

REGISTER 12-6: WPUA: WEAK PULL-UP PORTA REGISTER

U-0

—

U-0

—

R/W-1/1

WPUA5

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-6

bit 5

Unimplemented: Read as ‘0’

WPUA5: Weak Pull-up RA5 Control bit

If MCLRE in Configuration Word 1 = 0, MCLR is disabled):

1= Weak Pull-up enabled⁽¹⁾

0= Weak Pull-up disabled

If MCLRE in Configuration Word 1 = 1, MCLR is enabled):

Weak Pull-up is always enabled.

bit 4-0

Unimplemented: Read as ‘0’

Note 1: Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in configured as an output.

REGISTER 12-7: ANSELA: PORTA ANALOG SELECT REGISTER

U-0

—

U-0

—

U-0

—

R/W-1/1

ANSA4

R/W-1/1

ANSA3

R/W-1/1

ANSA2

R/W-1/1

ANSA1

R/W-1/1

ANSA0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

ANSA<4:0>: Analog Select between Analog or Digital Function on pins RA<4:0>, respectively

0= Digital I/O. Pin is assigned to port or digital special function.

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 125

PIC16F/LF1826/27

RA5

12.2.3

PORTA FUNCTIONS AND OUTPUT

PRIORITIES

Input only pin.

RA6

Each PORTA pin is multiplexed with other functions. The

pins, their combined functions and their output priorities

are briefly described here. For additional information,

refer to the appropriate section in this data sheet.

1. OSC2 (enabled by Configuration Word)

2. CLKOUT

3. CLKR

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the lowest number in

the following lists.

4. SDO1

5. P1D

6. P2B (PIC16F/LF1827 only)

7. RA6

Analog input functions, such as ADC, comparator and

CapSense inputs, are not shown in the priority lists.

These inputs are active when the I/O pin is set for

Analog mode using the ANSELx registers. Digital

output functions may control the pin when it is in Analog

mode with the priority shown below.

RA7

1. OSC1/CLKIN (enabled by Configuration Word)

2. P1C

3. CCP2 (PIC16F/LF1827 only)

4. P2A (PIC16F/LF1827 only)

5. RA7

RA0

1. SDO2 (PIC16F/LF1827 only)

2. RA0

RA1

1. SS2 (PIC16F/LF1827 only)

2. RA1

RA2

1. DACOUT (DAC)

2. RA2

RA3

1. SRQ (SR latch)

2. CCP3 (PIC16F/LF1827 only)

3. C1OUT (Comparator)

4. RA3

RA4

1. SRNQ (SR latch)

2. CCP4 (PIC16F/LF1827 only)

3. T0CKI

4. C2OUT (Comparator)

5. RA4

DS41391C-page 126

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELA

—

LATA7

WPUEN

RA7

—

LATA6

INTEDG

RA6

—

ANSA4

LATA4

TMR0SE

RA4

ANSA3

LATA3

PSA

ANSA2

LATA2

PS2

ANSA1

LATA1

PS1

ANSA0

LATA0

PS0

125

124

177

124

125

LATA

—

OPTION_REG

PORTA

TRISA

TMR0CS

RA5

RA3

RA2

RA1

RA0

TRISA7

—

TRISA6

—

TRISA5

WPUA5

TRISA4

—

TRISA3

—

TRISA2

—

TRISA1

—

TRISA0

—

WPUA

Legend:

— = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

TABLE 12-2: SUMMARY OF CONFIGURATION WORD ASSOCIATED WITH PORTA

Register

on Page

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

13:8

7:0

—

FCMEN

PWRTE

IESO

CLKOUTEN BOREN1

WDTE0 FOSC2

BOREN0

FOSC1

CPD

CONFIG1

50

CP

MCLRE

WDTE1

FOSC0

Legend:

— = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 127

PIC16F/LF1826/27

12.3.3

ANSELB REGISTER

12.3 PORTB and TRISB Registers

The ANSELB register (Register 12-12) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELB bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

PORTB is an 8-bit wide, bidirectional port. The

corresponding data direction register is TRISB

(Register 12-9). Setting a TRISB bit (= 1) will make the

corresponding PORTB pin an input (i.e., put the

corresponding output driver in a High-Impedance mode).

Clearing a TRISB bit (= 0) will make the corresponding

PORTB pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

Example 12-2 shows how to initialize PORTB.

The state of the ANSELB bits has no affect on digital

output functions. A pin with TRIS clear and ANSELB set

will still operate as a digital output, but the Input mode

will be analog. This can cause unexpected behavior

when executing read-modify-write instructions on the

affected port.

Reading the PORTB register (Register 12-8) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then written

to the PORT data latch.

The TRISB register (Register 12-9) controls the PORTB

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISB register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘0’.

The TRISB register (Register 12-9) controls the PORTB

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISB register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘0’. Example 12-2 shows how to initialize PORTB.

Note:

The ANSELB register must be initialized to

configure an analog channel as a digital

input. Pins configured as analog inputs will

read ‘0’.

EXAMPLE 12-2:

INITIALIZING PORTB

BANKSEL PORTB

;

CLRF

BANKSEL ANSELB

CLRF ANSELB

BANKSEL TRISB

PORTB

;Init PORTB

;Make RB<7:0> digital

;

MOVLW

B’11110000’ ;Set RB<7:4> as inputs

;and RB<3:0> as outputs

MOVWF

TRISB

;

12.3.1

INTERRUPT-ON-CHANGE

All of the PORTB pins are individually configurable as

an interrupt-on-change pin. Control bits IOCB<7:0>

enable or disable the interrupt function for each pin.

The interrupt-on-change feature is disabled on a

Power-on

Reset.

Reference

Section 13.0

“Interrupt-On-Change” for more information.

12.3.2

WEAK PULL-UPS

Each of the PORTB pins has an individually configurable

internal weak pull-up. Control bits WPUB<7:0> enable or

disable each pull-up (see Register 12-11). Each weak

pull-up is automatically turned off when the port pin is

configured as an output. All pull-ups are disabled on a

Power-on Reset by the WPUEN bit of the OPTION

register.

DS41391C-page 128

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

REGISTER 12-8: PORTB: PORTB REGISTER

R/W-x/x

RB7

R/W-x/x

RB6

R/W-x/x

RB5

R/W-x/x

RB4

R/W-x/x

RB3

R/W-x/x

RB2

R/W-x/x

RB1

R/W-x/x

RB0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

RB<7:0>: PORTB I/O Pin bit

1= Port pin is > VIH

0= Port pin is < VIL

REGISTER 12-9: TRISB: PORTB TRI-STATE REGISTER

R/W-1/1

TRISB7

R/W-1/1

TRISB6

R/W-1/1

TRISB5

R/W-1/1

TRISB4

R/W-1/1

TRISB3

R/W-1/1

TRISB2

R/W-1/1

TRISB1

R/W-1/1

TRISB0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

TRISB<7:0>: PORTB Tri-State Control bit

1= PORTB pin configured as an input (tri-stated)

0= PORTB pin configured as an output

REGISTER 12-10: LATB: PORTB DATA LATCH REGISTER

R/W-x/u

LATB7

R/W-x/u

LATB6

R/W-x/u

LATB5

R/W-x/u

LATB4

R/W-x/u

LATB3

R/W-x/u

LATB2

R/W-x/u

LATB1

R/W-x/u

LATB0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

LATB<7:0>: PORTB Output Latch Value bits⁽¹⁾

Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is

return of actual I/O pin values.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 129

PIC16F/LF1826/27

REGISTER 12-11: WPUB: WEAK PULL-UP PORTB REGISTER

R/W-1/1

WPUB7

R/W-1/1

WPUB6

R/W-1/1

WPUB5

R/W-1/1

WPUB4

R/W-1/1

WPUB3

R/W-1/1

WPUB2

R/W-1/1

WPUB1

R/W-1/1

WPUB0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

WPUB<7:0>: Weak Pull-up Register bits

1= Pull-up enabled

0= Pull-up disabled

Note 1: Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in configured as an output.

REGISTER 12-12: ANSELB: PORTB ANALOG SELECT REGISTER

R/W-1/1

ANSB7

R/W-1/1

ANSB6

R/W-1/1

ANSB5

R/W-1/1

ANSB4

R/W-1/1

ANSB3

R/W-1/1

ANSB2

R/W-1/1

ANSB1

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-1

ANSB<7:1>: Analog Select between Analog or Digital Function on Pins RB<7:1>, respectively

0= Digital I/O. Pin is assigned to port or digital special function.

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

bit 0

Unimplemented: Read as ‘0’

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

DS41391C-page 130

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

RB3

12.3.4

PORTB FUNCTIONS AND OUTPUT

PRIORITIES

1. MDOUT

2. CCP1/P1A

3. RB3

Each PORTB pin is multiplexed with other functions. The

pins, their combined functions and their output priorities

are briefly described here. For additional information,

refer to the appropriate section in this data sheet.

RB4

1. SCL1

2. SCK1

3. RB4

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the lowest number in

the following lists.

RB5

Analog input and some digital input functions are not

included in the list below. These input functions can

remain active when the pin is configured as an output.

Certain digital input functions, such as the EUSART RX

signal, override other port functions and are included in

the priority list.

1. SCL2 (PIC16F/LF1827 only)

2. TX/CK

3. SCK2 (PIC16F/LF1827 only)

4. P1B

5. RB5

RB6

RB0

1. ICSPCLK (Programming)

2. T1OSI

1. P1A

2. RB0

3. P1C

RB1

4. CCP2 (PIC16F/LF1827 only)

5. P2A (PIC16F/LF1827 only)

6. RB6

1. SDA1

2. RX/DT

3. RB1

RB7

RB2

1. ICSPDAT (Programming)

2. T1OSO

1. SDA2 (PIC16F/LF1827 only)

2. TX/CK

3. P1D

3. RX/DT

4. P2B (PIC16F/LF1827 only)

5. RB7

4. SDO1

5. RB2

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 131

PIC16F/LF1826/27

TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELB

LATB

ANSB7

LATB7

ANSB6

LATB6

INTEDG

RB6

ANSB5

LATB5

ANSB4

LATB4

ANSB3

LATB3

PSA

ANSB2

LATB2

PS2

ANSB1

LATB1

PS1

—

130

129

177

129

130

LATB0

PS0

OPTION_REG WPUEN

TMR0CS TMR0SE

PORTB

TRISB

RB7

RB5

RB4

RB3

RB2

RB1

RB0

TRISB7

WPUB7

TRISB6

WPUB6

TRISB5

WPUB5

TRISB4

WPUB4

TRISB3

WPUB3

TRISB2

WPUB2

TRISB1

WPUB1

TRISB0

WPUB0

WPUB

Legend:

— = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.

DS41391C-page 132

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

13.3 Interrupt Flags

13.0 INTERRUPT-ON-CHANGE

The IOCBFx bits located in the IOCBF register are

status flags that correspond to the Interrupt-on-change

pins of the port. If an expected edge is detected on an

appropriately enabled pin, then the status flag for that pin

will be set, and an interrupt will be generated if the IOCIE

bit is set. The IOCIF bit of the INTCON register reflects

the status of all IOCBFx bits.

The PORTB pins can be configured to operate as

Interrupt-on-change (IOC) pins. An interrupt can be

generated by detecting a signal that has either a rising

edge or a falling edge. Any individual PORTB pin can

be configured to generate an interrupt. The

interrupt-on-change module has the following features:

• Interrupt-on-change enable (Master Switch)

• Individual pin configuration

13.4 Clearing Interrupt Flags

• Rising and falling edge detection

• Individual pin interrupt flags

The individual status flags, (IOCBFx bits), can be

cleared by resetting them to zero. If another edge is

detected during this clearing operation, the associated

status flag will be set at the end of the sequence,

regardless of the value actually being written.

Figure 13-1 is a block diagram of the IOC module.

13.1 Enabling the Module

To allow individual port pins to generate an interrupt, the

IOCIE bit of the INTCON register must be set. If the

IOCIE bit is disabled, the edge detection on the pin will

still occur, but an interrupt will not be generated.

In order to ensure that no detected edge is lost while

clearing flags, only AND operations masking out known

changed bits should be performed. The following

sequence is an example of what should be performed.

EXAMPLE 13-1:

13.2 Individual Pin Configuration

MOVLW 0xff

XORWF IOCBF, W

ANDWF IOCBF, F

For each port pin, a rising edge detector and a falling

edge detector are present. To enable a pin to detect a

rising edge, the associated IOCBPx bit of the IOCBP

register is set. To enable a pin to detect a falling edge,

the associated IOCBNx bit of the IOCBN register is set.

13.5 Operation in Sleep

A pin can be configured to detect rising and falling

edges simultaneously by setting both the IOCBPx bit

and the IOCBNx bit of the IOCBP and IOCBN registers,

respectively.

The interrupt-on-change interrupt sequence will wake

the device from Sleep mode, if the IOCIE bit is set.

If an edge is detected while in Sleep mode, the IOCBF

register will be updated prior to the first instruction

executed out of Sleep.

FIGURE 13-1:

INTERRUPT-ON-CHANGE BLOCK DIAGRAM

IOCIE

IOCBFx

IOCBNx

D

Q

From all other IOCBFx

individual pin detectors

CK

R

IOC Interrupt to

CPU Core

RBx

IOCBPx

D

Q

CK

R

Q2 Clock Cycle

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 133

PIC16F/LF1826/27

REGISTER 13-1: IOCBP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER

R/W-0/0

IOCBP7

R/W-0/0

IOCBP6

R/W-0/0

IOCBP5

R/W-0/0

IOCBP4

R/W-0/0

IOCBP3

R/W-0/0

IOCBP2

R/W-0/0

IOCBP1

R/W-0/0

IOCBP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

IOCBP<7:0>: Interrupt-on-Change Positive Edge Enable bits

1= Interrupt-on-change enabled on the pin for a positive going edge. Associated Status bit and

interrupt flag will be set upon detecting an edge.

0= Interrupt-on-change disabled for the associated pin.

REGISTER 13-2: IOCBN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER

R/W-0/0

IOCBN7

R/W-0/0

IOCBN6

R/W-0/0

IOCBN5

R/W-0/0

IOCBN4

R/W-0/0

IOCBN3

R/W-0/0

IOCBN2

R/W-0/0

IOCBN1

R/W-0/0

IOCBN0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

IOCBN<7:0>: Interrupt-on-Change Negative Edge Enable bits

1= Interrupt-on-change enabled on the pin for a negative going edge. Associated Status bit and

interrupt flag will be set upon detecting an edge.

0= Interrupt-on-change disabled for the associated pin.

REGISTER 13-3: IOCBF: INTERRUPT-ON-CHANGE FLAG REGISTER

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0

IOCBF7

bit 7

IOCBF6

IOCBF5

IOCBF4

IOCBF3

IOCBF2

IOCBF1

IOCBF0

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HS - Bit is set in hardware

bit 7-0

IOCBF<7:0>: Interrupt-on-Change Flag bits

1= An enabled change was detected on the associated pin.

Set when IOCBPx = 1and a rising edge was detected on RBx, or when IOCBNx = 1and a falling

edge was detected on RBx.

0= No change was detected, or the user cleared the detected change.

DS41391C-page 134

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE

Register

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

ANSELB

INTCON

IOCBF

ANSB7

GIE

ANSB6

PEIE

ANSB5

ANSB4

INTE

ANSB3

IOCIE

ANSB2

ANSB1

INTF

—

130

91

TMR0IE

TMR0IF

IOCIF

IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0

IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0

IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

134

129

IOCBN

IOCBP

TRISB

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by interrupt-on-change.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 135

PIC16F/LF1826/27

NOTES:

DS41391C-page 136

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

14.1 Independent Gain Amplifiers

14.0 FIXED VOLTAGE REFERENCE

(FVR)

The output of the FVR supplied to the ADC,

Comparators, and DAC is routed through two

independent programmable gain amplifiers. Each

amplifier can be configured to amplify the reference

voltage by 1x, 2x or 4x, to produce the three possible

voltage levels.

The Fixed Voltage Reference, or FVR, is a stable

voltage reference, independent of VDD, with 1.024V,

2.048V or 4.096V selectable output levels. The output

of the FVR can be configured to supply a reference

voltage to the following:

The ADFVR<1:0> bits of the FVRCON register are

used to enable and configure the gain amplifier settings

for the reference supplied to the ADC module. Refer-

ence Section 15.0 “Analog-to-Digital Converter

(ADC) Module”for additional information.

• ADC input channel

• ADC positive reference

• Comparator positive input

• Digital-to-Analog Converter (DAC)

The FVR can be enabled by setting the FVREN bit of

the FVRCON register.

The CDAFVR<1:0> bits of the FVRCON register are

used to enable and configure the gain amplifier settings

for the reference supplied to the DAC and Comparator

module. Reference Section 16.0 “Digital-to-Analog

Converter (DAC) Module” and Section 18.0 “Com-

parator Module” for additional information.

14.2 FVR Stabilization Period

When the Fixed Voltage Reference module is enabled, it

requires time for the reference and amplifier circuits to

stabilize. Once the circuits stabilize and are ready for use,

the FVRRDY bit of the FVRCON register will be set. See

Section 29.0 “Electrical Specifications” for the

minimum delay requirement.

FIGURE 14-1:

VOLTAGE REFERENCE BLOCK DIAGRAM

ADFVR<1:0>

2

X1

X2

X4

FVR BUFFER1

(To ADC Module)

CDAFVR<1:0>

2

X1

X2

X4

FVR BUFFER2

(To Comparators, DAC)

+

_

FVREN

FVRRDY

1.024V Fixed

Reference

 2009 Microchip Technology Inc.

Preliminary

DS41391C-page 137

PIC16F/LF1826/27

REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER

R/W-0/0

FVREN

R-q/q

FVRRDY⁽¹⁾

R/W-0/0

Reserved

CDAFVR<1:0>

ADFVR<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

FVREN: Fixed Voltage Reference Enable bit

0= Fixed Voltage Reference is disabled

1= Fixed Voltage Reference is enabled

FVRRDY: Fixed Voltage Reference Ready Flag bit⁽¹⁾

0= Fixed Voltage Reference output is not ready or not enabled

1= Fixed Voltage Reference output is ready for use

bit 5-4

bit 3-2

Reserved: Read as ‘0’. Maintain these bits clear.

CDAFVR<1:0>: Comparator and DAC Fixed Voltage Reference Selection bit

00= Comparator and DAC Fixed Voltage Reference Peripheral output is off.

01= Comparator and DAC Fixed Voltage Reference Peripheral output is 1x (1.024V)

10= Comparator and DAC Fixed Voltage Reference Peripheral output is 2x (2.048V)⁽²⁾

11= Comparator and DAC Fixed Voltage Reference Peripheral output is 4x (4.096V)⁽²⁾

bit 1-0

ADFVR<1:0>: ADC Fixed Voltage Reference Selection bit

00= ADC Fixed Voltage Reference Peripheral output is off.

01= ADC Fixed Voltage Reference Peripheral output is 1x (1.024V)

10= ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)⁽²⁾

11= ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)⁽²⁾

Note 1: FVRRDY is always ‘1’ on devices with LDO (PIC16F1826/27).

2: Fixed Voltage Reference output cannot exceed VDD.

TABLE 14-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE FVR MODULE

Register

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FVRCON

FVREN

FVRRDY

Reserved Reserved CDAFVR1 CDAFVR0

ADFVR1

ADFVR0

138

Legend:

Shaded cells are unused by the FVR module.

DS41391C-page 138

Preliminary

 2009 Microchip Technology Inc.

PIC16F/LF1826/27

The ADC voltage reference is software selectable to be

either internally generated or externally supplied.

15.0 ANALOG-TO-DIGITAL

CONVERTER (ADC) MODULE

The ADC can generate an interrupt upon completion of

a conversion. This interrupt can be used to wake-up the

device from Sleep.

The Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 10-bit binary

representation of that signal. This device uses analog

inputs, which are multiplexed into a single sample and

hold circuit. The output of the sample and hold is

connected to the input of the converter. The converter

generates

a 10-bit binary result via successive

approximation and stores the conversion result into the

ADC result registers (ADRESH:ADRESL register pair).

Figure 15-1 shows the block diagram of the ADC.

FIGURE 15-1:

ADC BLOCK DIAGRAM

ADNREF = 1

VREF-

ADNREF = 0

VSS

VDD

ADPREF = 00

ADPREF = 11

VREF+

ADPREF = 10

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

ADC

10

GO/DONE

0= Left Justify

ADFM

1= Right Justify

ADON

16

11110

11111

DAC

FVR Buffer1

ADRESH ADRESL

VSS

CHS<4:0>

Note:

When ADON = 0, all multiplexer inputs are disconnected.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 139

PIC16F/LF1826/27

15.1.4

CONVERSION CLOCK

15.1 ADC Configuration

The source of the conversion clock is software select-

able via the ADCS bits of the ADCON1 register. There

are seven possible clock options:

When configuring and using the ADC the following

functions must be considered:

• Port configuration

• FOSC/2

• Channel selection

• FOSC/4

• ADC voltage reference selection

• ADC conversion clock source

• Interrupt control

• FOSC/8

• FOSC/16

• FOSC/32

• Result formatting

• FOSC/64

15.1.1

PORT CONFIGURATION

• FRC (dedicated internal oscillator)

The ADC can be used to convert both analog and

digital signals. When converting analog signals, the I/O

pin should be configured for analog by setting the

associated TRIS and ANSEL bits. Refer to

Section 12.0 “I/O Ports” for more information.

The time to complete one bit conversion is defined as

TAD. One full 10-bit conversion requires 11.5 TAD peri-

ods as shown in Figure 15-2.

For correct conversion, the appropriate TAD specification

must be met. Refer to the A/D conversion requirements

in Section 29.0 “Electrical Specifications” for more

information. Table 15-1 gives examples of appropriate

ADC clock selections.

Note:

Analog voltages on any pin that is defined

as a digital input may cause the input buf-

fer to conduct excess current.

Note:

Unless using the FRC, any changes in the

system clock frequency will change the

ADC clock frequency, which may

adversely affect the ADC result.

15.1.2

CHANNEL SELECTION

There are up to 14 channel selections available:

• AN<11:0> pins

• DAC Output

• FVR (Fixed Voltage Reference) Output

Refer to Section 16.0 “Digital-to-Analog Converter

(DAC) Module” and Section 14.0 “Fixed Voltage

Reference (FVR)” for more information on these

channel selections.

The CHS bits of the ADCON0 register determine which

channel is connected to the sample and hold circuit.

When changing channels, a delay is required before

starting the next conversion. Refer to Section 15.2

“ADC Operation” for more information.

15.1.3

ADC VOLTAGE REFERENCE

The ADPREF bits of the ADCON1 register provides

control of the positive voltage reference. The positive

voltage reference can be:

• VREF+ pin

• VDD

• FVR 2.028V

• FVR 4.096V (Not available on LF devices)

The ADNREF bits of the ADCON1 register provides

control of the negative voltage reference. The negative

voltage reference can be:

• VREF- pin

• VSS

See Section 14.0 “Fixed Voltage Reference (FVR)”

for more details on the fixed voltage reference.

DS41391C-page 140

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES

ADC Clock Period (TAD)

Device Frequency (FOSC)

ADC

ADCS<2:0>

Clock Source

32 MHz

20 MHz

16 MHz 8 MHz

4 MHz

1 MHz

(2)

Fosc/2

Fosc/4

Fosc/8

Fosc/16

Fosc/32

Fosc/64

FRC

000

100

001

101

010

110

x11

62.5ns

125 ns

0.5 s

100 ns

200 ns

400 ns

125 ns

250 ns

500 ns

1.0 s

2.0 s

4.0 s

2.0 s

4.0 s

(2)

(3)

0.5 s

1.0 s

2.0 s

4.0 s

8.0 s

16.0 s

32.0 s

64.0 s

(3)

800 ns

1.0 s

800 ns

1.6 s

1.0 s

2.0 s

(3)

8.0 s

(3)

2.0 s

3.2 s

4.0 s

8.0 s

16.0 s

(1,4)

1.0-6.0 s

Legend:

Shaded cells are outside of recommended range.

Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the

system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the

device in Sleep mode.

FIGURE 15-2:

ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

TCY - TAD

TAD8 TAD9 TAD10 TAD11

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7

b4

b1

b0

b9

b8

b7

b6

b5

b3

b2

Conversion starts

Holding capacitor is disconnected from analog input (typically 100 ns)

Set GO bit

On the following cycle:

ADRESH:ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 141

PIC16F/LF1826/27

15.1.5

INTERRUPTS

15.1.6

RESULT FORMATTING

The ADC module allows for the ability to generate an

interrupt upon completion of an Analog-to-Digital

conversion. The ADC Interrupt Flag is the ADIF bit in

the PIR1 register. The ADC Interrupt Enable is the

ADIE bit in the PIE1 register. The ADIF bit must be

cleared in software.

The 10-bit A/D conversion result can be supplied in two

formats, left justified or right justified. The ADFM bit of

the ADCON1 register controls the output format.

Figure 15-3 shows the two output formats.

Note 1: The ADIF bit is set at the completion of

every conversion, regardless of whether

or not the ADC interrupt is enabled.

2: The ADC operates during Sleep only

when the FRC oscillator is selected.

This interrupt can be generated while the device is

operating or while in Sleep. If the device is in Sleep, the

interrupt will wake-up the device. Upon waking from

Sleep, the next instruction following the SLEEPinstruc-

tion is always executed. If the user is attempting to

wake-up from Sleep and resume in-line code execu-

tion, the GIE and PEIE bits of the INTCON register

must be disabled. If the GIE and PEIE bits of the

INTCON register are enabled, execution will switch to

the Interrupt Service Routine.

Please refer to Section 15.1.5 “Interrupts” for more

information.

FIGURE 15-3:

10-BIT A/D CONVERSION RESULT FORMAT

ADRESH

ADRESL

LSB

(ADFM = 0)

MSB

bit 7

bit 0

bit 7

bit 0

10-bit A/D Result

Unimplemented: Read as ‘0’

(ADFM = 1)

MSB

LSB

bit 0

bit 7

Unimplemented: Read as ‘0’

10-bit A/D Result

DS41391C-page 142

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

15.2.4

ADC OPERATION DURING SLEEP

15.2 ADC Operation

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the FRC

option. When the FRC clock source is selected, the

ADC waits one additional instruction before starting the

conversion. This allows the SLEEP instruction to be

executed, which can reduce system noise during the

conversion. If the ADC interrupt is enabled, the device

will wake-up from Sleep when the conversion

completes. If the ADC interrupt is disabled, the ADC

module is turned off after the conversion completes,

although the ADON bit remains set.

15.2.1

STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a ‘1’. Setting the GO/

DONE bit of the ADCON0 register to a ‘1’ will start the

Analog-to-Digital conversion.

Note:

The GO/DONE bit should not be set in the

same instruction that turns on the ADC.

Refer to Section 15.2.6 “A/D Conver-

sion Procedure”.

When the ADC clock source is something other than

FRC, a SLEEP instruction causes the present conver-

sion to be aborted and the ADC module is turned off,

although the ADON bit remains set.

15.2.2

COMPLETION OF A CONVERSION

When the conversion is complete, the ADC module will:

• Clear the GO/DONE bit

• Set the ADIF Interrupt Flag bit

15.2.5

SPECIAL EVENT TRIGGER

• Update the ADRESH and ADRESL registers with

new conversion result

The Special Event Trigger of the CCPx/ECCPX module

allows periodic ADC measurements without software

intervention. When this trigger occurs, the GO/DONE

bit is set by hardware and the Timer1 counter resets to

zero.

15.2.3

TERMINATING A CONVERSION

If a conversion must be terminated before completion,

the GO/DONE bit can be cleared in software. The

ADRESH and ADRESL registers will be updated with

the partially complete Analog-to-Digital conversion

sample. Incomplete bits will match the last bit

converted.

TABLE 15-2: SPECIAL EVENT TRIGGER

Device

CCPx/ECCPx

PIC16F/LF1826

PIC16F/LF1827

ECCP1

CCP4

Note:

A device Reset forces all registers to their

Reset state. Thus, the ADC module is

turned off and any pending conversion is

terminated.

Using the Special Event Trigger does not assure proper

ADC timing. It is the user’s responsibility to ensure that

the ADC timing requirements are met.

Refer to Section 23.0 “Capture/Compare/PWM

Modules” for more information.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 143

PIC16F/LF1826/27

15.2.6

A/D CONVERSION PROCEDURE

EXAMPLE 15-1:

A/D CONVERSION

This is an example procedure for using the ADC to

perform an Analog-to-Digital conversion:

;This code block configures the ADC

;for polling, Vdd and Vss references, Frc

;clock and AN0 input.

;

1. Configure Port:

• Disable pin output driver (Refer to the TRIS

register)

;Conversion start & polling for completion

; are included.

;

• Configure pin as analog (Refer to the ANSEL

register)

BANKSEL

MOVLW

ADCON1

;

B’11110000’ ;Right justify, Frc

;clock

2. Configure the ADC module:

• Select ADC conversion clock

• Configure voltage reference

• Select ADC input channel

• Turn on ADC module

MOVWF

BANKSEL

BSF

BANKSEL

BSF

BANKSEL

MOVLW

MOVWF

CALL

BSF

BTFSC

GOTO

BANKSEL

MOVF

MOVWF

BANKSEL

MOVF

ADCON1

TRISA

TRISA,0

ANSEL

ANSEL,0

ADCON0

;Vdd and Vss Vref

;

;Set RA0 to input

;

;Set RA0 to analog

;

3. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

B’00000001’ ;Select channel AN0

ADCON0 ;Turn ADC On

SampleTime ;Acquisiton delay

ADCON0,ADGO ;Start conversion

ADCON0,ADGO ;Is conversion done?

• Enable ADC interrupt

• Enable peripheral interrupt

• Enable global interrupt⁽¹⁾

$-1

ADRESH

;No, test again

;

;Read upper 2 bits

;store in GPR space

;

4. Wait the required acquisition time⁽²⁾

.

5. Start conversion by setting the GO/DONE bit.

ADRESH,W

RESULTHI

ADRESL

ADRESL,W

RESULTLO

6. Wait for ADC conversion to complete by one of

the following:

;Read lower 8 bits

;Store in GPR space

• Polling the GO/DONE bit

MOVWF

• Waiting for the ADC interrupt (interrupts

enabled)

7. Read ADC Result.

8. Clear the ADC interrupt flag (required if interrupt

is enabled).

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep

and resume in-line code execution.

2: Refer to Section 15.3 “A/D Acquisition

Requirements”.

DS41391C-page 144

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

15.2.7

ADC REGISTER DEFINITIONS

The following registers are used to control the

operation of the ADC.

REGISTER 15-1: ADCON0: A/D CONTROL REGISTER 0

U-0

—

R/W-0/0

ADON

CHS<4:0>

GO/DONE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

bit 6-2

CHS<4:0>: Analog Channel Select bits

00000= AN0

00001= AN1

00010= AN2

00011= AN3

00100= AN4

00101= AN5

00110= AN6

00111= AN7

01000= AN8

01001= AN9

01010= AN10

01011= AN11

01100= Reserved. No channel connected.

•

11101= Reserved. No channel connected.

11110= DAC output⁽¹⁾

11111=FVR (Fixed Voltage Reference) Buffer 1 Output⁽²⁾

GO/DONE: A/D Conversion Status bit

bit 1

bit 0

1= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0= A/D conversion completed/not in progress

ADON: ADC Enable bit

1= ADC is enabled

0= ADC is disabled and consumes no operating current

Note 1: See Section 16.0 “Digital-to-Analog Converter (DAC) Module” for more information.

2: See Section 14.0 “Fixed Voltage Reference (FVR)” for more information.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 145

PIC16F/LF1826/27

REGISTER 15-2: ADCON1: A/D CONTROL REGISTER 1

R/W-0/0

ADFM

R/W-0/0

U-0

—

R/W-0/0

ADCS<2:0>

ADNREF

ADPREF<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

ADFM: A/D Result Format Select bit

1= Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is

loaded.

0= Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is

loaded.

bit 6-4

ADCS<2:0>: A/D Conversion Clock Select bits

000=FOSC/2

001=FOSC/8

010=FOSC/32

011=FRC (clock supplied from a dedicated RC oscillator)

100=FOSC/4

101=FOSC/16

110=FOSC/64

111=FRC (clock supplied from a dedicated RC oscillator)

bit 3

bit 2

Unimplemented: Read as ‘0’

ADNREF: A/D Negative Voltage Reference Configuration bit

0= VREF- is connected to VSS

1= VREF- is connected to external VREF- pin⁽¹⁾

bit 1-0

ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits

00= VREF+ is connected to VDD

01= Reserved

10= VREF+ is connected to external VREF+ pin⁽¹⁾

11= VREF+ is connected to internal Fixed Voltage Reference (FVR) module

Note 1: When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a

minimum voltage specification exists. See Section 29.0 “Electrical Specifications” for details.

DS41391C-page 146

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

REGISTER 15-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0

R/W-x/u

bit 0

ADRES<9:2>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

ADRES<9:2>: ADC Result Register bits

Upper 8 bits of 10-bit conversion result

REGISTER 15-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

ADRES<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-0

ADRES<1:0>: ADC Result Register bits

Lower 2 bits of 10-bit conversion result

Reserved: Do not use.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 147

PIC16F/LF1826/27

REGISTER 15-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

ADRES<9:8>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-2

bit 1-0

Reserved: Do not use.

ADRES<9:8>: ADC Result Register bits

Upper 2 bits of 10-bit conversion result

REGISTER 15-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1

R/W-x/u

bit 0

ADRES<7:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

ADRES<7:0>: ADC Result Register bits

Lower 8 bits of 10-bit conversion result

DS41391C-page 148

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

source impedance is decreased, the acquisition time

may be decreased. After the analog input channel is

selected (or changed), an A/D acquisition must be

done before the conversion can be started. To calculate

the minimum acquisition time, Equation 15-1 may be

used. This equation assumes that 1/2 LSb error is used

(1,024 steps for the ADC). The 1/2 LSb error is the

maximum error allowed for the ADC to meet its

specified resolution.

15.3 A/D Acquisition Requirements

For the ADC to meet its specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The Analog

Input model is shown in Figure 15-4. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD), refer

to Figure 15-4. The maximum recommended

impedance for analog sources is 10 k. As the

EQUATION 15-1: ACQUISITION TIME EXAMPLE

Temperature = 50°C and external impedance of 10k 5.0V VDD

Assumptions:

TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

= TAMP + TC + TCOFF

= 2µs + TC + Temperature - 25°C0.05µs/°C

The value for TC can be approximated with the following equations:

1





;[1] VCHOLD charged to within 1/2 lsb

^VAPPLIED^{1 – -------------------------- = VCHOLD}



2^{n + 1} – 1

–TC

---------





RC

VAPPLIED 1 – e

= V^CHOLD







;[2] VCHOLD charge response to VAPPLIED

;combining [1] and [2]



–Tc

--------









RC

1







^{= VAPPLIED}^{1 – --------------------------}

2^{n + 1} – 1

VAPPLIED 1 – e





Note: Where n = number of bits of the ADC.

Solving for TC:

TC = –CHOLDRIC + RSS + RS ln(1/511)

= –10pF1k + 7k + 10k ln(0.001957)

= 1.12µs

Therefore:

TACQ = 2µs + 1.12µs + 50°C- 25°C0.05µs/°C

= 4.42µs

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin

leakage specification.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 149

PIC16F/LF1826/27

FIGURE 15-4:

ANALOG INPUT MODEL

VDD

Analog

Input

Sampling

Switch

VT  0.6V

SS

RIC  1k

Rss

Rs

(1)

CPIN

5 pF

VA

I LEAKAGE

CHOLD = 10 pF

VSS/VREF-

VT  0.6V

6V

5V

RSS

VDD 4V

3V

Legend:

CHOLD

CPIN

= Sample/Hold Capacitance

= Input Capacitance

2V

I LEAKAGE = Leakage current at the pin due to

various junctions

5 6 7 8 9 1011

Sampling Switch

RIC

RSS

SS

VT

= Interconnect Resistance

= Resistance of Sampling Switch

= Sampling Switch

(k)

= Threshold Voltage

Note 1: Refer to Section 33.0 “Electrical Specifications”.

FIGURE 15-5:

ADC TRANSFER FUNCTION

Full-Scale Range

3FFh

3FEh

3FDh

3FCh

3FBh

03h

02h

01h

00h

Analog Input Voltage

1.5 LSB

0.5 LSB

Zero-Scale

Transition

VREF-

Full-Scale

Transition

VREF+

DS41391C-page 150

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 15-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

145

ADCON0

ADCON1

ADRESH

ADRESL

ANSELA

ANSELB

CCPxCON

INTCON

PIE1

—

CHS4

CHS3

CHS2

CHS1

—

CHS0

GO/DONE

ADON

ADFM

ADCS2

ADCS1

ADCS0

ADNREF ADPREF1 ADPREF0

A/D Result Register High

A/D Result Register Low

147, 148

125

—

ANSA4

ANSB4

DCxB0

INTE

ANSA3

ANSB3

CCPxM3

IOCE

ANSA2

ANSB2

CCPxM2

TMR0IF

CCP1IE

CCP1IF

TRISA2

TRISB2

ANSA1

ANSB1

CCPxM1

INTF

ANSA0

—

ANSB7

PxM1

ANSB6

PxM0

ANSB5

DCxB1

TMR0IE

RCIE

130

CCPxM0

IOCF

228

GIE

PEIE

91

TMR1GIE

TMR1GIF

TRISA7

TRISB7

FVREN

DACEN

—

ADIE

TXIE

SSP1IE

SSP1IF

TRISA3

TRISB3

TMR2IE

TMR2IF

TRISA1

TRISB1

TMR1IE

TMR1IF

TRISA0

TRISB0

ADFVR0

DACNSS

DACR0

92

PIR1

ADIF

RCIF

TXIF

96

TRISA

TRISA6

TRISB6

FVRRDY

DACLPS

—

TRISA5

TRISB5

TRISA4

TRISB4

124

TRISB

129

FVRCON

DACCON0

DACCON1

Legend:

Reserved Reserved CDAFVR1 CDAFVR0 ADFVR1

137

DACOE

—

DACPSS1 DACPSS0

DACR3 DACR2

—

157

DACR4

DACR1

157

— = unimplemented read as ‘0’. Shaded cells are not used for ADC module.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 151

PIC16F/LF1826/27

NOTES:

DS41391C-page 152

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

16.3.1

OUTPUT CLAMPED TO POSITIVE

VOLTAGE SOURCE

16.0 DIGITAL-TO-ANALOG

CONVERTER (DAC) MODULE

The DAC output voltage can be set to VSRC+ with the

least amount of power consumption by performing the

following:

The Digital-to-Analog Converter supplies a variable

voltage reference, ratiometric with the input source,

with 32 selectable output levels.

• Clearing the DACEN bit in the DACCON0 register.

• Setting the DACLPS bit in the DACCON0 register.

The input of the DAC can be connected to:

• External VREF pins

• Configuring the DACPSS bits to the proper

positive source.

• VDD supply voltage

• FVR (Fixed Voltage Reference)

• Configuring the DACR<4:0> bits to ‘11111’ in the

DACCON1 register.

The output of the DAC can be configured to supply a

reference voltage to the following:

This is also the method used to output the voltage level

from the FVR to an output pin. See Section 16.4 “DAC

Voltage Reference Output” for more information.

• Comparator positive input

• ADC input channel

• DACOUT pin

Reference Figure 16-1 for output clamping examples.

The Digital-to-Analog Converter (DAC) can be enabled

by setting the DACEN bit of the DACCON0 register.

16.3.2

OUTPUT CLAMPED TO NEGATIVE

VOLTAGE SOURCE

The DAC output voltage can be set to VSRC- with the

least amount of power consumption by performing the

following:

16.1 Output Voltage Selection

The DAC has 32 voltage level ranges. The 32 levels

are set with the DACR<4:0> bits of the DACCON1

register.

• Clearing the DACEN bit in the DACCON0 register.

• Clearing the DACLPS bit in the DACCON0 register.

The DAC output voltage is determined by the following

equations:

• Configuring the DACNSS bits to the proper

negative source.

• Configuring the DACR<4:0> bits to ‘00000’ in the

DACCON1 register.

EQUATION 16-1: DAC OUTPUT VOLTAGE

DACR<4:0>







+ VSRC-

This allows the comparator to detect a zero-crossing

while not consuming additional current through the DAC

module.

VOUT = VSOURCE+ – VSOURCE-  ------------------------------



5

2

Note:

VSOURCE+ can equal FVR Buffer 2, VDD or

VREF+. VSOURCE- can equal VSS or VREF-.

Reference Figure 16-1 for output clamping examples.

16.2 Ratiometric Output Level

The DAC output value is derived using a resistor ladder

with each end of the ladder tied to a positive and

negative voltage reference input source. If the voltage

of either input source fluctuates, a similar fluctuation will

result in the DAC output value.

The value of the individual resistors within the ladder

can be found in Section 29.0 “Electrical

Specifications”.

16.3 Low Power Voltage State

In order for the DAC module to consume the least

amount of power, one of the two voltage reference input

sources to the resistor ladder must be disconnected.

Either the positive voltage source, (VSRC+), or the

negative voltage source, (VSRC-) can be disabled.

The negative voltage source is disabled by setting the

DACLPS bit in the DACCON0 register. Clearing the

DACLPS bit in the DACCON0 register disables the

positive voltage source.

 2009 Microchip Technology Inc.

Preliminary

DS41391C-page 153

PIC16F/LF1826/27

FIGURE 16-1:

OUTPUT VOLTAGE CLAMPING EXAMPLES

Output Clamped to Positive Voltage Source

Output Clamped to Negative Voltage Source

VSRC+

R

DACR<4:0> = 11111

R

DACEN = 0

DACLPS = 1

DACEN = 0

DACLPS = 0

DAC Voltage Ladder

(see Figure 16-2)

DAC Voltage Ladder

(see Figure 16-2)

R

DACR<4:0> = 00000

VSRC-

DS41391C-page 154

Preliminary

 2009 Microchip Technology Inc.

PIC16F/LF1826/27

digital input threshold detector functions of that pin.

Reading the DACOUT pin when it has been configured

for DAC reference voltage output will always return a ‘0’.

16.4 DAC Voltage Reference Output

The DAC can be output to the DACOUT pin by setting

the DACOE bit of the DACCON0 register to ‘1’. Selecting

the DAC reference voltage for output on the DACOUT

pin automatically overrides the digital output buffer and

Due to the limited current drive capability, a buffer must

be used on the DAC voltage reference output for

external connections to DACOUT. Figure 16-3 shows

an example buffering technique.

FIGURE 16-2:

DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM

Digital-to-Analog Converter (DAC)

FVR BUFFER2

VSRC+

VDD

DACR<4:0>

5

VREF+

R

DACPSS<1:0>

2

R

DACEN

DACLPS

32

Steps

DAC

(To Comparator and

ADC Modules)

R

DACOUT

DACOE

DACNSS

VREF-

VSS

VSRC-

 2009 Microchip Technology Inc.

Preliminary

DS41391C-page 155

PIC16F/LF1826/27

FIGURE 16-3:

VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

PIC^®MCU

DAC

Module

R

+

–

Buffered DAC Output

DACOUT

Voltage

Reference

Output

Impedance

16.5 Operation During Sleep

When the device wakes up from Sleep through an

interrupt or a Watchdog Timer time-out, the contents of

the DACCON0 register are not affected. To minimize

current consumption in Sleep mode, the voltage

reference should be disabled.

16.6 Effects of a Reset

A device Reset affects the following:

• DAC is disabled.

• DAC output voltage is removed from the

DACOUT pin.

• The DACR<4:0> range select bits are cleared.

DS41391C-page 156

Preliminary

 2009 Microchip Technology Inc.

PIC16F/LF1826/27

REGISTER 16-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0

R/W-0/0

DACEN

R/W-0/0

DACLPS

R/W-0/0

DACOE

U-0

—

R/W-0/0

U-0

—

R/W-0/0

DACPSS<1:0>

DACNSS

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7

bit 6

DACEN: DAC Enable bit

1= DAC is enabled

0= DAC is disabled

DACLPS: DAC Low-Power Voltage State Select bit

1= DAC Positive reference source selected

0= DAC Negative reference source selected

bit 5

DACOE: DAC Voltage Output Enable bit

1= DAC voltage level is also an output on the DACOUT pin

0= DAC voltage level is disconnected from the DACOUT pin

bit 4

Unimplemented: Read as ‘0’

bit 3-2

DACPSS<1:0>: DAC Positive Source Select bits

00= VDD

01= VREF+

10= FVR Buffer2 output

11= Reserved, do not use

bit 1

bit 0

Unimplemented: Read as ‘0’

DACNSS: DAC Negative Source Select bits

1= VREF-

0= VSS

REGISTER 16-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1

U-0

—

U-0

—

U-0

—

R/W-0/0

bit 0

DACR<4:0>

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

DACR<4:0>: DAC Voltage Output Select bits

VOUT = ((VSRC+) - (VSRC-))*(DACR<4:0>/(2⁵)) + VSRC-

Note 1: The output select bits are always right justified to ensure that any number of bits can be used without

affecting the register layout.

 2009 Microchip Technology Inc.

Preliminary

DS41391C-page 157

PIC16F/LF1826/27

TABLE 16-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE

Register

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FVRCON

DACCON0

DACCON1

Legend:

FVREN

DACEN

—

FVRRDY

DACLPS

—

Reserved Reserved CDAFVR1 CDAFVR0

ADFVR1

—

ADFVR0

DACNSS

DACR0

138

157

DACOE

—

DACPSS1 DACPSS0

DACR3 DACR2

DACR4

DACR1

— = unimplemented, read as ‘0’. Shaded cells are unused with the DAC module.

DS41391C-page 158

Preliminary

 2009 Microchip Technology Inc.

PIC16F/LF1826/27

17.2 Latch Output

17.0 SR LATCH

The SRQEN and SRNQEN bits of the SRCON0 regis-

ter control the Q and Q latch outputs. Both of the SR

latch outputs may be directly output to an I/O pin at the

same time.

The module consists of a single SR latch with multiple

Set and Reset inputs as well as separate latch outputs.

The SR latch module includes the following features:

• Programmable input selection

• SR latch output is available externally

• Separate Q and Q outputs

The applicable TRIS bit of the corresponding port must

be cleared to enable the port pin output driver.

• Firmware Set and Reset

17.3 Effects of a Reset

The SR latch can be used in a variety of analog appli-

cations, including oscillator circuits, one-shot circuit,

hysteretic controllers, and analog timing applications.

Upon any device Reset, the SR latch output is not ini-

tialized to a known state. The user’s firmware is

responsible for initializing the latch output before

enabling the output pins.

17.1 Latch Operation

The latch is a Set-Reset latch that does not depend on a

clock source. Each of the Set and Reset inputs are

active-high. The latch can be Set or Reset by:

• Software control (SRPS and SRPR bits)

• Comparator C1 output (SYNCC1OUT)

• Comparator C2 output (SYNCC2OUT)

• SRI pin

• Programmable clock (SRCLK)

The SRPS and the SRPR bits of the SRCON0 register

may be used to Set or Reset the SR latch, respectively.

The latch is Reset-dominant. Therefore, if both Set and

Reset inputs are high, the latch will go to the Reset

state. Both the SRPS and SRPR bits are self resetting

which means that a single write to either of the bits is all

that is necessary to complete a latch Set or Reset oper-

ation.

The output from Comparator C1 or C2 can be used as

the Set or Reset inputs of the SR latch. The output of

either Comparator can be synchronized to the Timer1

clock source. See Section 18.0 “Comparator Mod-

ule” and Section 20.0 “Timer1 Module with Gate

Control” for more information.

An external source on the SRI pin can be used as the

Set or Reset inputs of the SR latch.

An internal clock source is available that can periodically

Set or Reset the SR latch. The SRCLK<2:0> bits in the

SRCON0 register are used to select the clock source

period. The SRSCKE and SRRCKE bits of the SRCON1

register enable the clock source to Set or Reset the SR

latch, respectively.

Note:

Enabling both the Set and Reset inputs

from any one source at the same time may

result in indeterminate operation, as the

Reset dominance cannot be assured.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 159

PIC16F/LF1826/27

FIGURE 17-1:

SR LATCH SIMPLIFIED BLOCK DIAGRAM

SRLEN

SRQEN

SRPS

Pulse

(2)

Gen

SRI

S

Q

SRSPE

SRCLK

SRQ

SRSCKE

(3)

SYNCC2OUT

SRSC2E

(3)

SYNCC1OUT

SRSC1E

SR

(1)

Latch

SRPR

Pulse

(2)

Gen

SRI

SRRPE

SRCLK

R

Q

SRNQ

SRRCKE

SRLEN

(3)

SYNCC2OUT

SRNQEN

SRRC2E

(3)

SYNCC1OUT

SRRC1E

Note 1: If R = 1and S = 1simultaneously, Q = 0, Q = 1

2: Pulse generator causes a 1 Q-state pulse width.

3: Name denotes the connection point at the comparator output.

DS41391C-page 160

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 17-1: SRCLK FREQUENCY TABLE

SRCLK

Divider

FOSC = 32 MHz FOSC = 20 MHz FOSC = 16 MHz FOSC = 4 MHz

FOSC = 1 MHz

111

110

101

100

011

010

001

000

512

256

128

64

32

16

8

62.5 kHz

125 kHz

250 kHz

500 kHz

1 MHz

39.0 kHz

78.1 kHz

156 kHz

313 kHz

625 kHz

1.25 MHz

2.5 MHz

5 MHz

31.3 kHz

62.5 kHz

125 kHz

250 kHz

500 kHz

1 MHz

7.81 kHz

15.6 kHz

31.25 kHz

62.5 kHz

125 kHz

250 kHz

500 kHz

1 MHz

1.95 kHz

3.90 kHz

7.81 kHz

15.6 kHz

31.3 kHz

62.5 kHz

125 kHz

250 kHz

2 MHz

4 MHz

2 MHz

4

8 MHz

4 MHz

REGISTER 17-1: SRCON0: SR LATCH CONTROL 0 REGISTER

R/W-0/0

SRLEN

R/W-0/0

SRQEN

R/W-0/0

R/S-0/0

SRPS

R/S-0/0

SRPR

bit 0

SRCLK<2:0>

SRNQEN

bit 7

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

S = Bit is set only

bit 7

SRLEN: SR Latch Enable bit

1= SR latch is enabled

0= SR latch is disabled

SRCLK<2:0>: SR Latch Clock Divider bits

bit 6-4

000= Generates a 1 FOSC wide pulse every 4th FOSC cycle clock

001= Generates a 1 FOSC wide pulse every 8th FOSC cycle clock

010= Generates a 1 FOSC wide pulse every 16th FOSC cycle clock

011= Generates a 1 FOSC wide pulse every 32nd FOSC cycle clock

100= Generates a 1 FOSC wide pulse every 64th FOSC cycle clock

101= Generates a 1 FOSC wide pulse every 128th FOSC cycle clock

110= Generates a 1 FOSC wide pulse every 256th FOSC cycle clock

111= Generates a 1 FOSC wide pulse every 512th FOSC cycle clock

bit 3

bit 2

SRQEN: SR Latch Q Output Enable bit

If SRLEN = 1:

1= Q is present on the SRQ pin

0= External Q output is disabled

If SRLEN = 0:

SR latch is disabled

SRNQEN: SR Latch Q Output Enable bit

If SRLEN = 1:

1= Q is present on the SRnQ pin

0= External Q output is disabled

If SRLEN = 0:

SR latch is disabled

(1)

bit 1

bit 0

SRPS: Pulse Set Input of the SR Latch bit

1= Pulse set input for 1 Q-clock period

0= No effect on set input.

(1)

SRPR: Pulse Reset Input of the SR Latch bit

1= Pulse Reset input for 1 Q-clock period

0= No effect on Reset input.

Note 1: Set only, always reads back ‘0’.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 161

PIC16F/LF1826/27

REGISTER 17-2: SRCON1: SR LATCH CONTROL 1 REGISTER

R/W-0/0

SRSPE

R/W-0/0

SRSC2E

R/W-0/0

SRSC1E

R/W-0/0

SRRPE

R/W-0/0

SRSCKE

SRRCKE

SRRC2E

SRRC1E

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

SRSPE: SR Latch Peripheral Set Enable bit

1= SR latch is set when the SRI pin is high.

0= SRI pin has no effect on the set input of the SR latch

SRSCKE: SR Latch Set Clock Enable bit

1= Set input of SR latch is pulsed with SRCLK

0= SRCLK has no effect on the set input of the SR latch

SRSC2E: SR Latch C2 Set Enable bit

1= SR latch is set when the C2 Comparator output is high

0= C2 Comparator output has no effect on the set input of the SR latch

SRSC1E: SR Latch C1 Set Enable bit

1= SR latch is set when the C1 Comparator output is high

0= C1 Comparator output has no effect on the set input of the SR latch

SRRPE: SR Latch Peripheral Reset Enable bit

1= SR latch is reset when the SRI pin is high.

0= SRI pin has no effect on the Reset input of the SR latch

SRRCKE: SR Latch Reset Clock Enable bit

1= Reset input of SR latch is pulsed with SRCLK

0= SRCLK has no effect on the Reset input of the SR latch

SRRC2E: SR Latch C2 Reset Enable bit

1= SR latch is reset when the C2 Comparator output is high

0= C2 Comparator output has no effect on the Reset input of the SR latch

SRRC1E: SR Latch C1 Reset Enable bit

1= SR latch is reset when the C1 Comparator output is high

0= C1 Comparator output has no effect on the Reset input of the SR latch

DS41391C-page 162

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 17-2: SUMMARY OF REGISTERS ASSOCIATED WITH SR LATCH MODULE

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELA

SRCON0

SRCON1

TRISA

—

ANSA4

ANSA3

ANSA2

ANSA1

SRPS

ANSA0

SRPR

125

161

162

124

SRLEN

SRSPE

TRISA7

SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN

SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E

TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the SR latch module.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 163

PIC16F/LF1826/27

NOTES:

DS41391C-page 164

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 18-1:

SINGLE COMPARATOR

18.0 COMPARATOR MODULE

Comparators are used to interface analog circuits to a

digital circuit by comparing two analog voltages and

providing a digital indication of their relative magnitudes.

Comparators are very useful mixed signal building

blocks because they provide analog functionality

independent of program execution. The analog

comparator module includes the following features:

VIN+

VIN-

+

Output

–

VIN-

VIN+

• Independent comparator control

• Programmable input selection

• Comparator output is available internally/externally

• Programmable output polarity

• Interrupt-on-change

Output

• Wake-up from Sleep

• Programmable Speed/Power optimization

• PWM shutdown

Note:

The black areas of the output of the

comparator represents the uncertainty

due to input offsets and response time.

• Programmable and fixed voltage reference

18.1

Comparator Overview

A single comparator is shown in Figure 18-1 along with

the relationship between the analog input levels and

the digital output. When the analog voltage at VIN+ is

less than the analog voltage at VIN-, the output of the

comparator is a digital low level. When the analog

voltage at VIN+ is greater than the analog voltage at

VIN-, the output of the comparator is a digital high level.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 165

PIC16F/LF1826/27

FIGURE 18-2:

COMPARATOR 1 MODULE SIMPLIFIED BLOCK DIAGRAM

CxNCH<1:0>

CxON⁽¹⁾

2

CxINTP

Interrupt

det

0

C12IN0-

C12IN1-

C12IN2-

C12IN3-

Set CxIF

1

CxINTN

Interrupt

det

MUX

(2)

2

3

CXPOL

CxVN

CxVP

-

CXOUT

To Data Bus

D

Q

Cx⁽³⁾

MCXOUT

+

Q1

EN

0

C1IN+

CxHYS

MUX

1

DAC

(2)

CxSP

To ECCP PWM Logic

CXOE

FVR Buffer2

C12IN+

2

3

CXSYNC

CxON

TRIS bit

CXOUT

CXPCH<1:0>

0

1

2

D

Q

(from Timer1)

T1CLK

To Timer1 or SR Latch

SYNCCXOUT

Note 1:

When CxON = 0, the Comparator will produce a ‘0’ at the output

When CxON = 0, all multiplexer inputs are disconnected.

Output of comparator can be frozen during debugging.

2:

3:

DS41391C-page 166

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 18-3:

COMPARATOR 2 MODULE SIMPLIFIED BLOCK DIAGRAM

CxNCH<1:0>

CxON⁽¹⁾

2

CxINTP

Interrupt

det

0

C12IN0-

C12IN1-

C12IN2-

C12IN3-

Set CxIF

1

CxINTN

Interrupt

det

MUX

(2)

2

3

CXPOL

CxVN

CxVP

-

CXOUT

To Data Bus

D

Q

Cx⁽³⁾

MCXOUT

+

Q1

EN

0

C12IN+

CxHYS

MUX

DAC

1

(2)

CxSP

To ECCP PWM Logic

CXOE

2

3

FVR Buffer2

CXSYNC

CxON

VSS

TRIS bit

CXOUT

CXPCH<1:0>

0

1

2

D

Q

(from Timer1)

T1CLK

To Timer1 or SR Latch

SYNCCXOUT

Note 1:

When CxON = 0, the Comparator will produce a ‘0’ at the output

When CxON = 0, all multiplexer inputs are disconnected.

Output of comparator can be frozen during debugging.

2:

3:

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 167

PIC16F/LF1826/27

18.2.3

COMPARATOR OUTPUT POLARITY

18.2 Comparator Control

Inverting the output of the comparator is functionally

equivalent to swapping the comparator inputs. The

polarity of the comparator output can be inverted by

setting the CxPOL bit of the CMxCON0 register.

Clearing the CxPOL bit results in a non-inverted output.

Each comparator has 2 control registers: CMxCON0 and

CMxCON1.

The CMxCON0 registers (see Register 18-1) contain

Control and Status bits for the following:

• Enable

Table 18-1 shows the output state versus input

conditions, including polarity control.

• Output selection

• Output polarity

TABLE 18-1: COMPARATOR OUTPUT

STATE VS. INPUT

• Speed/Power selection

• Hysteresis enable

• Output synchronization

CONDITIONS

Input Condition

CxPOL

CxOUT

The CMxCON1 registers (see Register 18-2) contain

Control bits for the following:

CxVN > CxVP

CxVN < CxVP

CxVN > CxVP

CxVN < CxVP

0

1

0

1

0

1

• Interrupt enable

• Interrupt edge polarity

• Positive input channel selection

• Negative input channel selection

18.2.4

COMPARATOR SPEED/POWER

SELECTION

18.2.1

COMPARATOR ENABLE

The trade-off between speed or power can be opti-

mized during program execution with the CxSP control

bit. The default state for this bit is ‘1’ which selects the

normal speed mode. Device power consumption can

be optimized at the cost of slower comparator propaga-

tion delay by clearing the CxSP bit to ‘0’.

Setting the CxON bit of the CMxCON0 register enables

the comparator for operation. Clearing the CxON bit

disables the comparator resulting in minimum current

consumption.

18.2.2

COMPARATOR OUTPUT

SELECTION

The output of the comparator can be monitored by

reading either the CxOUT bit of the CMxCON0 register

or the MCxOUT bit of the CMOUT register. In order to

make the output available for an external connection,

the following conditions must be true:

• CxOE bit of the CMxCON0 register must be set

• Corresponding TRIS bit must be cleared

• CxON bit of the CMxCON0 register must be set

Note 1: The CxOE bit of the CMxCON0 register

overrides the PORT data latch. Setting

the CxON bit of the CMxCON0 register

has no impact on the port override.

2: The internal output of the comparator is

latched with each instruction cycle.

Unless otherwise specified, external

outputs are not latched.

DS41391C-page 168

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

18.3 Comparator Hysteresis

18.5 Comparator Interrupt

A selectable amount of separation voltage can be

added to the input pins of each comparator to provide a

hysteresis function to the overall operation. Hysteresis

is enabled by setting the CxHYS bit of the CMxCON0

register.

An interrupt can be generated upon a change in the

output value of the comparator for each comparator, a

rising edge detector and a Falling edge detector are

present.

When either edge detector is triggered and its associ-

ated enable bit is set (CxINTP and/or CxINTN bits of

the CMxCON1 register), the Corresponding Interrupt

Flag bit (CxIF bit of the PIR2 register) will be set.

See Section 29.0 “Electrical Specifications” for

more information.

18.4 Timer1 Gate Operation

To enable the interrupt, you must set the following bits:

• CxON, CxPOL and CxSP bits of the CMxCON0

register

The output resulting from a comparator operation can

be used as a source for gate control of Timer1. See

Section 20.6 “Timer1 Gate” for more information.

This feature is useful for timing the duration or interval

of an analog event.

• CxIE bit of the PIE2 register

• CxINTP bit of the CMxCON1 register (for a rising

edge detection)

It is recommended that the comparator output be syn-

chronized to Timer1. This ensures that Timer1 does not

increment while a change in the comparator is occur-

ring.

• CxINTN bit of the CMxCON1 register (for a falling

edge detection)

• PEIE and GIE bits of the INTCON register

The associated interrupt flag bit, CxIF bit of the PIR2

register, must be cleared in software. If another edge is

detected while this flag is being cleared, the flag will still

be set at the end of the sequence.

18.4.1

COMPARATOR OUTPUT

SYNCHRONIZATION

The output from either comparator, C1 or C2, can be

synchronized with Timer1 by setting the CxSYNC bit of

the CMxCON0 register.

Note:

Although a comparator is disabled, an

interrupt can be generated by changing

the output polarity with the CxPOL bit of

the CMxCON0 register, or by switching the

comparator on or off with the CxON bit of

the CMxCON0 register.

Once enabled, the comparator output is latched on the

falling edge of the Timer1 source clock. If a prescaler is

used with Timer1, the comparator output is latched after

the prescaling function. To prevent a race condition, the

comparator output is latched on the falling edge of the

Timer1 clock source and Timer1 increments on the

rising edge of its clock source. See the Comparator

Block Diagram (Figure 18-2) and the Timer1 Block

Diagram (Figure 20-1) for more information.

18.6 Comparator Positive Input

Selection

Configuring the CxPCH<1:0> bits of the CMxCON1

register directs an internal voltage reference or an

analog pin to the non-inverting input of the comparator:

• C1IN+ or C2IN+ analog pin

• DAC

• FVR (Fixed Voltage Reference)

• VSS (Ground)

See Section 14.0 “Fixed Voltage Reference (FVR)”

for more information on the Fixed Voltage Reference

module.

See Section 16.0 “Digital-to-Analog Converter

(DAC) Module” for more information on the DAC input

signal.

Any time the comparator is disabled (CxON = 0), all

comparator inputs are disabled.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 169

PIC16F/LF1826/27

18.7 Comparator Negative Input

Selection

18.10 Analog Input Connection

Considerations

The CxNCH<1:0> bits of the CMxCON0 register direct

one of four analog pins to the comparator inverting

input.

A simplified circuit for an analog input is shown in

Figure 18-1. Since the analog input pins share their

connection with a digital input, they have reverse

biased ESD protection diodes to VDD and VSS. The

analog input, therefore, must be between VSS and VDD.

If the input voltage deviates from this range by more

than 0.6V in either direction, one of the diodes is for-

ward biased and a latch-up may occur.

Note:

To use CxIN+ and CxINx- pins as analog

input, the appropriate bits must be set in

the ANSEL register and the corresponding

TRIS bits must also be set to disable the

output drivers.

A maximum source impedance of 10 k is recommended

for the analog sources. Also, any external component

connected to an analog input pin, such as a capacitor or

a Zener diode, should have very little leakage current to

minimize inaccuracies introduced.

18.8 Comparator Response Time

The comparator output is indeterminate for a period of

time after the change of an input source or the selection

of a new reference voltage. This period is referred to as

the response time. The response time of the comparator

differs from the settling time of the voltage reference.

Therefore, both of these times must be considered when

determining the total response time to a comparator

input change. See the Comparator and Voltage Refer-

ence Specifications in Section 29.0 “Electrical Speci-

fications” for more details.

Note 1: When reading a PORT register, all pins

configured as analog inputs will read as a

‘0’. Pins configured as digital inputs will

convert as an analog input, according to

the input specification.

2: Analog levels on any pin defined as a

digital input, may cause the input buffer to

consume more current than is specified.

18.9 Interaction with ECCP Logic

The C1 and C2 comparators can be used as general

purpose comparators. Their outputs can be brought

out to the C1OUT and C2OUT pins. When the ECCP

Auto-Shutdown is active it can use one or both

comparator signals. If auto-restart is also enabled, the

comparators can be configured as a closed loop

analog feedback to the ECCP, thereby, creating an

analog controlled PWM.

Note:

When the Comparator module is first

initialized the output state is unknown.

Upon initialization, the user should verify

the output state of the comparator prior to

relying on the result, primarily when using

the result in connection with other

peripheral features, such as the ECCP

Auto-Shutdown mode.

DS41391C-page 170

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 18-4:

ANALOG INPUT MODEL

VDD

Analog

Input

VT  0.6V

RIC

Rs < 10K

To Comparator

(1)

ILEAKAGE

CPIN

5 pF

VA

VT  0.6V

Vss

Legend: CPIN

= Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions

RIC

RS

VA

= Interconnect Resistance

= Source Impedance

= Analog Voltage

VT

= Threshold Voltage

Note 1: See Section 29.0 “Electrical Specifications”

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 171

PIC16F/LF1826/27

REGISTER 18-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0

R/W-0/0

CxON

R-0/0

R/W-0/0

CxOE

R/W-0/0

CxPOL

U-0

—

R/W-1/1

CxSP

R/W-0/0

CxHYS

R/W-0/0

CxSYNC

CxOUT

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

CxON: Comparator Enable bit

1= Comparator is enabled and consumes no active power

0= Comparator is disabled

CxOUT: Comparator Output bit

If CxPOL = 1 (inverted polarity):

1= CxVP < CxVN

0= CxVP > CxVN

If CxPOL = 0 (non-inverted polarity):

1= CxVP > CxVN

0= CxVP < CxVN

bit 5

bit 4

CxOE: Comparator Output Enable bit

1= CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually

drive the pin. Not affected by CxON.

0= CxOUT is internal only

CxPOL: Comparator Output Polarity Select bit

1= Comparator output is inverted

0= Comparator output is not inverted

bit 3

bit 2

Unimplemented: Read as ‘0’

CxSP: Comparator Speed/Power Select bit

1= Comparator operates in normal power, higher speed mode

0= Comparator operates in low-power, low-speed mode

bit 1

bit 0

CxHYS: Comparator Hysteresis Enable bit

1= Comparator hysteresis enabled

0= Comparator hysteresis disabled

CxSYNC: Comparator Output Synchronous Mode bit

1= Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.

Output updated on the falling edge of Timer1 clock source.

0= Comparator output to Timer1 and I/O pin is asynchronous.

DS41391C-page 172

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

REGISTER 18-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1

R/W-0/0

CxINTP

R/W-0/0

CxINTN

R/W-0/0

U-0

—

U-0

—

R/W-0/0

CxPCH<1:0>

CxNCH<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

CxINTP: Comparator Interrupt on Positive Going Edge Enable bits

1= The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit

0= No interrupt flag will be set on a positive going edge of the CxOUT bit

bit 6

CxINTN: Comparator Interrupt on Negative Going Edge Enable bits

1= The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit

0= No interrupt flag will be set on a negative going edge of the CxOUT bit

bit 5-4

CxPCH<1:0>: Comparator Positive Input Channel Select bits

00= CxVP connects to CxIN+ pin

01= CxVP connects to DAC Voltage Reference

10= CxVP connects to FVR Voltage Reference

For C1:

11= CxVP connects to C12IN+ pin

For C2:

11= CxVP connects to VSS

bit 3-2

bit 1-0

Unimplemented: Read as ‘0’

CxNCH<1:0>: Comparator Negative Input Channel Select bits

00= CxVN connects to C12IN0- pin

01= CxVN connects to C12IN1- pin

10= CxVN connects to C12IN2- pin

11= CxVN connects to C12IN3- pin

REGISTER 18-3: CMOUT: COMPARATOR OUTPUT REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R-0/0

MC2OUT

MC1OUT

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-2

bit 1

Unimplemented: Read as ‘0’

MC2OUT: Mirror Copy of C2OUT bit

MC1OUT: Mirror Copy of C1OUT bit

bit 0

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 173

PIC16F/LF1826/27

TABLE 18-2: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELA

CMxCON0

CMxCON1

CMOUT

DACCON0

DACCON1

FVRCON

INTCON

LATA

—

CxOUT

CxINTN

—

CxOE

CxPCH1

—

ANSA4

CxPOL

CxPCH0

—

ANSA3

—

ANSA2

CxSP

—

ANSA1

CxHYS

ANSA0

CxSYNC

CxNCH0

125

172

173

157

138

91

CxON

CxNTP

—

CxNCH1

—

MC2OUT MC1OUT

DACEN

—

DACLPS

—

DACOE

—

DACPSS1 DACPSS0

DACR3 DACR2

—

DACNSS

DACR0

ADFVR0

IOCIF

DACR4

DACR1

FVREN

GIE

FVRRDY

PEIE

Reserved Reserved CDAFVR1 CDAFVR0 ADFVR1

TMR0IE

—

INTE

LATA4

EEIE

IOCIE

LATA3

BCL1IE

BCL1IF

RA3

TMR0IF

LATA2

—

INTF

LATA1

—

LATA7

OSFIE

OSFIF

RA7

LATA6

C2IE

LATA0

124

93

(1)

PIE2

C1IE

C1IF

CCP2IE

(1)

C2IF

EEIF

—

CCP2IF

PIR2

97

PORTA

RA6

RA5

RA4

RA2

RA1

RA0

124

TRISA

TRISA7

TRISA6

TRISA5

TRISA4

TRISA3

TRISA2

TRISA1

TRISA0

Legend:

— = unimplemented, read as ‘0’. Shaded cells are unused by the Comparator module.

Note 1: PIC16F/LF1827 only.

DS41391C-page 174

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

19.1.2

8-BIT COUNTER MODE

19.0 TIMER0 MODULE

In 8-Bit Counter mode, the Timer0 module will increment

on every rising or falling edge of the T0CKI pin or the

Capacitive Sensing Oscillator (CPSCLK) signal.

The Timer0 module is an 8-bit timer/counter with the

following features:

• 8-bit timer/counter register (TMR0)

• 8-bit prescaler (independent of Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow

8-Bit Counter mode using the T0CKI pin is selected by

setting the TMR0CS bit in the OPTION register to ‘1’

and resetting the T0XCS bit in the CPSCON0 register to

‘0’.

8-Bit Counter mode using the Capacitive Sensing

Oscillator (CPSCLK) signal is selected by setting the

TMR0CS bit in the OPTION register to ‘1’ and setting

the T0XCS bit in the CPSCON0 register to ‘1’.

• TMR0 can be used to gate Timer1

Figure 19-1 is a block diagram of the Timer0 module.

The rising or falling transition of the incrementing edge

for either input source is determined by the TMR0SE bit

in the OPTION register.

19.1 Timer0 Operation

The Timer0 module can be used as either an 8-bit timer

or an 8-bit counter.

19.1.1

8-BIT TIMER MODE

The Timer0 module will increment every instruction

cycle, if used without a prescaler. 8-Bit Timer mode is

selected by clearing the TMR0CS bit of the OPTION

register.

When TMR0 is written, the increment is inhibited for

two instruction cycles immediately following the write.

Note:

The value written to the TMR0 register can

be adjusted, in order to account for the two

instruction cycle delay when TMR0 is

written.

FIGURE 19-1:

BLOCK DIAGRAM OF THE TIMER0

FOSC/4

Data Bus

0

1

8

T0CKI

1

Sync

0

1

TMR0

2 TCY

0

From CPSCLK

Set Flag bit TMR0IF

TMR0SE

TMR0CS

8-bit

Prescaler

on Overflow

PSA

T0XCS

Overflow to Timer1

8

PS<2:0>

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 175

PIC16F/LF1826/27

19.1.3

SOFTWARE PROGRAMMABLE

PRESCALER

A software programmable prescaler is available for

exclusive use with Timer0. The prescaler is enabled by

clearing the PSA bit of the OPTION register.

Note:

The Watchdog Timer (WDT) uses its own

independent prescaler.

There are 8 prescaler options for the Timer0 module

ranging from 1:2 to 1:256. The prescale values are

selectable via the PS<2:0> bits of the OPTION register.

In order to have a 1:1 prescaler value for the Timer0

module, the prescaler must be disabled by setting the

PSA bit of the OPTION register.

The prescaler is not readable or writable. All instructions

writing to the TMR0 register will clear the prescaler.

19.1.4

TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0

register overflows from FFh to 00h. The TMR0IF

interrupt flag bit of the INTCON register is set every

time the TMR0 register overflows, regardless of

whether or not the Timer0 interrupt is enabled. The

TMR0IF bit can only be cleared in software. The Timer0

interrupt enable is the TMR0IE bit of the INTCON

register.

Note:

The Timer0 interrupt cannot wake the

processor from Sleep since the timer is

frozen during Sleep.

19.1.5

8-BIT COUNTER MODE

SYNCHRONIZATION

When in 8-Bit Counter mode, the incrementing edge on

the T0CKI pin must be synchronized to the instruction

clock. Synchronization can be accomplished by

sampling the prescaler output on the Q2 and Q4 cycles

of the instruction clock. The high and low periods of the

external clocking source must meet the timing

requirements as shown in Section 29.0 “Electrical

Specifications”.

19.1.6

OPERATION DURING SLEEP

Timer0 cannot operate while the processor is in Sleep

mode. The contents of the TMR0 register will remain

unchanged while the processor is in Sleep mode.

DS41391C-page 176

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

REGISTER 19-1: OPTION_REG: OPTION REGISTER

R/W-1/1

WPUEN

R/W-1/1

INTEDG

R/W-1/1

PSA

R/W-1/1

PS<2:0>

R/W-1/1

bit 0

TMR0CS

TMR0SE

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

WPUEN: Weak Pull-up Enable bit

1= All weak pull-ups are disabled (except MCLR, if it is enabled)

0= Weak pull-ups are enabled by individual WPUx latch values

INTEDG: Interrupt Edge Select bit

1= Interrupt on rising edge of RB0/INT pin

0= Interrupt on falling edge of RB0/INT pin

TMR0CS: Timer0 Clock Source Select bit

1= Transition on RA4/T0CKI pin

0= Internal instruction cycle clock (FOSC/4)

TMR0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on RA4/T0CKI pin

0= Increment on low-to-high transition on RA4/T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler is not assigned to the Timer0 module

0= Prescaler is assigned to the Timer0 module

PS<2:0>: Prescaler Rate Select bits

Bit Value

Timer0 Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

TABLE 19-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CPSCON0

INTCON

CPSON

GIE

—

CPSRNG1 CPSRNG0 CPSOUT T0XCS

320

91

PEIE

TMR0IE

INTE

IOCIE

PSA

TMR0IF

PS2

INTF

PS1

IOCIF

PS0

OPTION_REG WPUEN INTEDG TMR0CS TMR0SE

177

175*

124

TMR0

TRISA

Timer0 Module Register

TRISA7 TRISA6 TRISA5 TRISA4

TRISA3

TRISA2

TRISA1 TRISA0

Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module.

Page provides register information.

*

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 177

PIC16F/LF1826/27

NOTES:

DS41391C-page 178

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

• Gate Toggle Mode

20.0 TIMER1 MODULE WITH GATE

CONTROL

• Gate Single-pulse Mode

• Gate Value Status

The Timer1 module is a 16-bit timer/counter with the

following features:

• Gate Event Interrupt

Figure 20-1 is a block diagram of the Timer1 module.

• 16-bit timer/counter register pair (TMR1H:TMR1L)

• Programmable internal or external clock source

• 2-bit prescaler

• Dedicated 32 kHz oscillator circuit

• Optionally synchronized comparator out

• Multiple Timer1 gate (count enable) sources

• Interrupt on overflow

• Wake-up on overflow (external clock,

Asynchronous mode only)

• Time base for the Capture/Compare function

• Special Event Trigger (with CCP/ECCP)

• Selectable Gate Source Polarity

FIGURE 20-1:

TIMER1 BLOCK DIAGRAM

T1GSS<1:0>

T1G

T1GSPM

00

From Timer0

Overflow

0

01

10

11

T1G_IN

D

Data Bus

T1GVAL

0

1

D

Q

Comparator 1

SYNCC1OUT

Single Pulse

Acq. Control

RD

1

T1GCON

Q1 EN

Q

Comparator 2

SYNCC2OUT

Interrupt

Set

T1GGO/DONE

CK

R

TMR1ON

T1GTM

TMR1GIF

det

T1GPOL

TMR1GE

Set flag bit

TMR1IF on

Overflow

TMR1ON

To Comparator Module

TMR1⁽²⁾

EN

D

Synchronized

clock input

0

T1CLK

TMR1H

TMR1L

Q

1

TMR1CS<1:0>

T1SYNC

T1OSO

OUT

Cap. Sensing

Oscillator

11

10

Synchronize⁽³⁾

det

T1OSC

EN

Prescaler

1, 2, 4, 8

1

0

T1OSI

2

T1CKPS<1:0>

FOSC

Internal

Clock

01

00

FOSC/2

Internal

Clock

T1OSCEN

T1CKI

Sleep input

FOSC/4

Internal

Clock

(1)

To Clock Switching Modules

Note 1: ST Buffer is high speed type when using T1CKI.

2: Timer1 register increments on rising edge.

3: Synchronize does not operate while in Sleep.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 179

PIC16F/LF1826/27

20.1 Timer1 Operation

20.2 Clock Source Selection

The Timer1 module is a 16-bit incrementing counter

which is accessed through the TMR1H:TMR1L register

pair. Writes to TMR1H or TMR1L directly update the

counter.

The TMR1CS<1:0> and T1OSCEN bits of the T1CON

register are used to select the clock source for Timer1.

Table 20-2 displays the clock source selections.

20.2.1

INTERNAL CLOCK SOURCE

When used with an internal clock source, the module is

a timer and increments on every instruction cycle.

When used with an external clock source, the module

can be used as either a timer or counter and incre-

ments on every selected edge of the external source.

When the internal clock source is selected the

TMR1H:TMR1L register pair will increment on multiples

of FOSC as determined by the Timer1 prescaler.

When the FOSC internal clock source is selected, the

Timer1 register value will increment by four counts every

instruction clock cycle. Due to this condition, a 2 LSB

error in resolution will occur when reading the Timer1

value. To utilize the full resolution of Timer1, an

asynchronous input signal must be used to gate the

Timer1 clock input.

Timer1 is enabled by configuring the TMR1ON and

TMR1GE bits in the T1CON and T1GCON registers,

respectively. Table 20-1 displays the Timer1 enable

selections.

TABLE 20-1: TIMER1 ENABLE

SELECTIONS

The following asynchronous sources may be used:

• Asynchronous event on the T1G pin to Timer1

Gate

Timer1

Operation

TMR1ON

TMR1GE

• C1 or C2 comparator input to Timer1 Gate

0

1

0

1

0

1

Off

20.2.2

EXTERNAL CLOCK SOURCE

When the external clock source is selected, the Timer1

module may work as a timer or a counter.

Always On

Count Enabled

When enabled to count, Timer1 is incremented on the

rising edge of the external clock input T1CKI or the

capacitive sensing oscillator signal. Either of these

external clock sources can be synchronized to the

microcontroller system clock or they can run

asynchronously.

When used as a timer with a clock oscillator, an

external 32.768 kHz crystal can be used in conjunction

with the dedicated internal oscillator circuit.

Note:

In Counter mode, a falling edge must be

registered by the counter prior to the first

incrementing rising edge after any one or

more of the following conditions:

• Timer1 enabled after POR

• Write to TMR1H or TMR1L

• Timer1 is disabled

• Timer1 is disabled (TMR1ON = 0)

when T1CKI is high then Timer1 is

enabled (TMR1ON=1) when T1CKI is

low.

TABLE 20-2: CLOCK SOURCE SELECTIONS

TMR1CS1

TMR1CS0

T1OSCEN

Clock Source

0

1

0

1

0

x

0

1

System Clock (FOSC)

Instruction Clock (FOSC/4)

Capacitive Sensing Oscillator

External Clocking on T1CKI Pin

Osc.Circuit On T1OSI/T1OSO Pins

DS41391C-page 180

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

20.3 Timer1 Prescaler

20.6 Timer1 Gate

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

Timer1 can be configured to count freely or the count

can be enabled and disabled using Timer1 Gate

circuitry. This is also referred to as Timer1 Gate Enable.

Timer1 Gate can also be driven by multiple selectable

sources.

20.6.1

TIMER1 GATE ENABLE

20.4 Timer1 Oscillator

The Timer1 Gate Enable mode is enabled by setting

the TMR1GE bit of the T1GCON register. The polarity

of the Timer1 Gate Enable mode is configured using

the T1GPOL bit of the T1GCON register.

A dedicated low-power 32.768 kHz oscillator circuit is

built-in between pins T1OSI (input) and T1OSO

(amplifier output). This internal circuit is to be used in

conjunction with an external 32.768 kHz crystal.

When Timer1 Gate Enable mode is enabled, Timer1

will increment on the rising edge of the Timer1 clock

source. When Timer1 Gate Enable mode is disabled,

no incrementing will occur and Timer1 will hold the

current count. See Figure 20-3 for timing details.

The oscillator circuit is enabled by setting the

T1OSCEN bit of the T1CON register. The oscillator will

continue to run during Sleep.

Note:

The oscillator requires a start-up and

stabilization time before use. Thus,

T1OSCEN should be set and a suitable

delay observed prior to enabling Timer1.

TABLE 20-3: TIMER1 GATE ENABLE

SELECTIONS

T1CLK T1GPOL

T1G

Timer1 Operation

20.5 Timer1 Operation in

Asynchronous Counter Mode



0

1

0

1

0

1

Counts

Holds Count

Counts

If control bit T1SYNC of the T1CON register is set, the

external clock input is not synchronized. The timer

increments asynchronously to the internal phase

clocks. If external clock source is selected then the

timer will continue to run during Sleep and can

generate an interrupt on overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer (see

Section 20.5.1 “Reading and Writing Timer1 in

Asynchronous Counter Mode”).

20.6.2

TIMER1 GATE SOURCE

SELECTION

The Timer1 Gate source can be selected from one of

four different sources. Source selection is controlled by

the T1GSS bits of the T1GCON register. The polarity

for each available source is also selectable. Polarity

selection is controlled by the T1GPOL bit of the

T1GCON register.

Note:

When switching from synchronous to

asynchronous operation, it is possible to

skip an increment. When switching from

asynchronous to synchronous operation,

it is possible to produce an additional

increment.

TABLE 20-4: TIMER1 GATE SOURCES

T1GSS

Timer1 Gate Source

Timer1 Gate Pin

00

01

Overflow of Timer0

20.5.1

READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

(TMR0 increments from FFh to 00h)

10

11

Comparator 1 Output SYNCC1OUT

(optionally Timer1 synchronized output)

Reading TMR1H or TMR1L while the timer is running

from an external asynchronous clock will ensure a valid

read (taken care of in hardware). However, the user

should keep in mind that reading the 16-bit timer in two

8-bit values itself, poses certain problems, since the

timer may overflow between the reads.

Comparator 2 Output SYNCC2OUT

(optionally Timer1 synchronized output)

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may produce an

unpredictable value in the TMR1H:TMR1L register pair.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 181

PIC16F/LF1826/27

20.6.2.1

T1G Pin Gate Operation

20.6.4

TIMER1 GATE SINGLE-PULSE

MODE

The T1G pin is one source for Timer1 Gate Control. It

can be used to supply an external source to the Timer1

Gate circuitry.

When Timer1 Gate Single-Pulse mode is enabled, it is

possible to capture a single pulse gate event. Timer1

Gate Single-Pulse mode is first enabled by setting the

T1GSPM bit in the T1GCON register. Next, the

T1GGO/DONE bit in the T1GCON register must be set.

The Timer1 will be fully enabled on the next

incrementing edge. On the next trailing edge of the

pulse, the T1GGO/DONE bit will automatically be

cleared. No other gate events will be allowed to

increment Timer1 until the T1GGO/DONE bit is once

again set in software.See Example 20-5 for timing

details.

20.6.2.2

Timer0 Overflow Gate Operation

When Timer0 increments from FFh to 00h,

low-to-high pulse will automatically be generated and

internally supplied to the Timer1 Gate circuitry.

a

20.6.2.3

Comparator C1 Gate Operation

The output resulting from a Comparator 1 operation can

be selected as a source for Timer1 Gate Control. The

Comparator

1

output (SYNCC1OUT) can be

If the Single Pulse Gate mode is disabled by clearing the

T1GSPM bit in the T1GCON register, the T1GGO/DONE

bit should also be cleared.

synchronized to the Timer1 clock or left asynchronous.

For more information see Section 18.4.1 “Comparator

Output Synchronization”.

Enabling the Toggle mode and the Single-Pulse mode

simultaneously will permit both sections to work

together. This allows the cycle times on the Timer1

Gate source to be measured. See Figure 20-6 for

timing details.

20.6.2.4

Comparator C2 Gate Operation

The output resulting from a Comparator 2 operation

can be selected as a source for Timer1 Gate Control.

The Comparator 2 output (SYNCC2OUT) can be

synchronized to the Timer1 clock or left asynchronous.

For more information see Section 18.4.1 “Comparator

Output Synchronization”.

20.6.5

TIMER1 GATE VALUE STATUS

When Timer1 Gate Value Status is utilized, it is possible

to read the most current level of the gate control value.

The value is stored in the T1GVAL bit in the T1GCON

register. The T1GVAL bit is valid even when the Timer1

Gate is not enabled (TMR1GE bit is cleared).

20.6.3

TIMER1 GATE TOGGLE MODE

When Timer1 Gate Toggle mode is enabled, it is possi-

ble to measure the full-cycle length of a Timer1 gate

signal, as opposed to the duration of a single level

pulse.

20.6.6

TIMER1 GATE EVENT INTERRUPT

When Timer1 Gate Event Interrupt is enabled, it is pos-

sible to generate an interrupt upon the completion of a

gate event. When the falling edge of T1GVAL occurs,

the TMR1GIF flag bit in the PIR1 register will be set. If

the TMR1GIE bit in the PIE1 register is set, then an

interrupt will be recognized.

The Timer1 Gate source is routed through a flip-flop

that changes state on every incrementing edge of the

signal. See Figure 20-4 for timing details.

Timer1 Gate Toggle mode is enabled by setting the

T1GTM bit of the T1GCON register. When the T1GTM

bit is cleared, the flip-flop is cleared and held clear. This

is necessary in order to control which edge is

measured.

The TMR1GIF flag bit operates even when the Timer1

Gate is not enabled (TMR1GE bit is cleared).

Note:

Enabling Toggle mode at the same time as

changing the gate polarity may result in

indeterminate operation.

DS41391C-page 182

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

20.7 Timer1 Interrupt

20.9 ECCP/CCP Capture/Compare Time

Base

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the Timer1 interrupt flag bit of the PIR1 register is

set. To enable the interrupt on rollover, you must set

these bits:

The CCP modules use the TMR1H:TMR1L register

pair as the time base when operating in Capture or

Compare mode.

In Capture mode, the value in the TMR1H:TMR1L

register pair is copied into the CCPR1H:CCPR1L

register pair on a configured event.

• TMR1ON bit of the T1CON register

• TMR1IE bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

In Compare mode, an event is triggered when the value

CCPR1H:CCPR1L register pair matches the value in

the TMR1H:TMR1L register pair. This event can be a

Special Event Trigger.

The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

For

more

information,

see

Section 23.0

Note:

The TMR1H:TMR1L register pair and the

TMR1IF bit should be cleared before

enabling interrupts.

“Capture/Compare/PWM Modules”.

20.10 ECCP/CCP Special Event Trigger

When any of the CCP’s are configured to trigger a spe-

cial event, the trigger will clear the TMR1H:TMR1L reg-

ister pair. This special event does not cause a Timer1

interrupt. The CCP module may still be configured to

generate a CCP interrupt.

20.8 Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in

Asynchronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the

counter. To set up the timer to wake the device:

In this mode of operation, the CCPR1H:CCPR1L

register pair becomes the period register for Timer1.

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set

• T1SYNC bit of the T1CON register must be set

Timer1 should be synchronized and FOSC/4 should be

selected as the clock source in order to utilize the Spe-

cial Event Trigger. Asynchronous operation of Timer1

can cause a Special Event Trigger to be missed.

• TMR1CS bits of the T1CON register must be

configured

In the event that a write to TMR1H or TMR1L coincides

with a Special Event Trigger from the CCP, the write will

take precedence.

• T1OSCEN bit of the T1CON register must be

configured

The device will wake-up on an overflow and execute

the next instructions. If the GIE bit of the INTCON

register is set, the device will call the Interrupt Service

Routine.

For more information, see Section 15.2.5 “Special

Event Trigger”.

Timer1 oscillator will continue to operate in Sleep

regardless of the T1SYNC bit setting.

FIGURE 20-2:

TIMER1 INCREMENTING EDGE

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 183

PIC16F/LF1826/27

FIGURE 20-3:

TIMER1 GATE ENABLE MODE

TMR1GE

T1GPOL

T1G_IN

T1CKI

T1GVAL

Timer1

N

N + 1

N + 2

N + 3

N + 4

FIGURE 20-4:

TIMER1 GATE TOGGLE MODE

TMR1GE

T1GPOL

T1GTM

T1G_IN

T1CKI

T1GVAL

Timer1

N

N + 1 N + 2 N + 3 N + 4

N + 5 N + 6 N + 7 N + 8

DS41391C-page 184

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 20-5:

TIMER1 GATE SINGLE-PULSE MODE

TMR1GE

T1GPOL

T1GSPM

Cleared by hardware on

falling edge of T1GVAL

T1GGO/

DONE

Set by software

Counting enabled on

rising edge of T1G

T1G_IN

T1CKI

T1GVAL

Timer1

N

N + 1

N + 2

Cleared by

software

Set by hardware on

falling edge of T1GVAL

Cleared by software

TMR1GIF

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 185

PIC16F/LF1826/27

FIGURE 20-6:

TMR1GE

T1GPOL

TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE

T1GSPM

T1GTM

Cleared by hardware on

falling edge of T1GVAL

T1GGO/

DONE

Set by software

Counting enabled on

rising edge of T1G

T1G_IN

T1CKI

T1GVAL

Timer1

N + 4

N + 2 N + 3

N

N + 1

Set by hardware on

falling edge of T1GVAL

Cleared by

software

Cleared by software

TMR1GIF

DS41391C-page 186

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

20.11 Timer1 Control Register

The Timer1 Control register (T1CON), shown in

Register 21-1, is used to control Timer1 and select the

various features of the Timer1 module.

REGISTER 20-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0/u

T1SYNC

U-0

—

R/W-0/u

TMR1CS<1:0>

T1CKPS<1:0>

T1OSCEN

TMR1ON

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

TMR1CS<1:0>: Timer1 Clock Source Select bits

11=Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC)

10=Timer1 clock source is pin or oscillator:

If T1OSCEN = 0:

External clock from T1CKI pin (on the rising edge)

If T1OSCEN = 1:

Crystal oscillator on T1OSI/T1OSO pins

01=Timer1 clock source is system clock (FOSC)

00=Timer1 clock source is instruction clock (FOSC/4)

bit 5-4

T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11= 1:8 Prescale value

10= 1:4 Prescale value

01= 1:2 Prescale value

00= 1:1 Prescale value

bit 3

bit 2

T1OSCEN: LP Oscillator Enable Control bit

1= Dedicated Timer1 oscillator circuit enabled

0= Dedicated Timer1 oscillator circuit disabled

T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS<1:0> = 1X

1= Do not synchronize external clock input

0= Synchronize external clock input with system clock (FOSC)

TMR1CS<1:0> = 0X

This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X.

bit 1

bit 0

Unimplemented: Read as ‘0’

TMR1ON: Timer1 On bit

1= Enables Timer1

0= Stops Timer1

Clears Timer1 Gate flip-flop

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 187

PIC16F/LF1826/27

20.12 Timer1 Gate Control Register

The Timer1 Gate Control register (T1GCON), shown in

Register 21-2, is used to control Timer1 Gate.

REGISTER 20-2: T1GCON: TIMER1 GATE CONTROL REGISTER

R/W-0/u

T1GPOL

R/W-0/u

T1GTM

R/W-0/u

R/W/HC-0/u

R-x/x

R/W-0/u

TMR1GE

T1GSPM

T1GGO/

DONE

T1GVAL

T1GSS<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HC = Bit is cleared by hardware

bit 7

TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0:

This bit is ignored

If TMR1ON = 1:

1= Timer1 counting is controlled by the Timer1 gate function

0= Timer1 counts regardless of Timer1 gate function

bit 6

bit 5

T1GPOL: Timer1 Gate Polarity bit

1= Timer1 gate is active-high (Timer1 counts when gate is high)

0= Timer1 gate is active-low (Timer1 counts when gate is low)

T1GTM: Timer1 Gate Toggle Mode bit

1= Timer1 Gate Toggle mode is enabled

0= Timer1 Gate Toggle mode is disabled and toggle flip flop is cleared

Timer1 gate flip-flop toggles on every rising edge.

bit 4

T1GSPM: Timer1 Gate Single-Pulse Mode bit

1= Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate

0= Timer1 gate Single-Pulse mode is disabled

bit 3

T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit

1= Timer1 gate single-pulse acquisition is ready, waiting for an edge

0= Timer1 gate single-pulse acquisition has completed or has not been started

bit 2

T1GVAL: Timer1 Gate Current State bit

Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.

Unaffected by Timer1 Gate Enable (TMR1GE).

bit 1-0

T1GSS<1:0>: Timer1 Gate Source Select bits

00= Timer1 Gate pin

01= Timer0 overflow output

10= Comparator 1 optionally synchronized output (SYNCC1OUT)

11= Comparator 2 optionally synchronized output (SYNCC2OUT)

DS41391C-page 188

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 20-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELB

CCP1CON

INTCON

PIE1

ANSB7

PxM1

ANSB6

PxM0

PEIE

ADIE

ADIF

RB6

ANSB5

DCxB1

TMR0IE

RCIE

ANSB4

DCxB0

INTE

ANSB3

ANSB2

ANSB1

—

130

228

91

CCPxM3 CCPxM2 CCPxM1 CCPxM0

GIE

IOCIE

SSP1IE

SSP1IF

RB3

TMR0IF

INTF

IOCIF

TMR1GIE

TMR1GIF

RB7

TXIE

CCP1IE TMR2IE TMR1IE

CCP1IF TMR2IF TMR1IF

92

PIR1

RCIF

TXIF

96

PORTB

TMR1H

TMR1L

TRISB

RB5

RB4

RB2

RB1

RB0

129

179*

129

187

188

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1ON

—

T1CON

T1GCON

TMR1GE T1GPOL

T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0

DONE

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

Page provides register information.

*

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 189

PIC16F/LF1826/27

NOTES:

DS41391C-page 190

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

21.0 TIMER2/4/6 MODULES

There are up to three identical Timer2-type modules

available. To maintain pre-existing naming conventions,

the Timers are called Timer2, Timer4 and Timer6 (also

Timer2/4/6).

Note:

The ‘x’ variable used in this section is used

to designate Timer2, Timer4, or Timer6.

For example, TxCON references T2CON,

T4CON, or T6CON. PRx references PR2,

PR4, or PR6.

The Timer2/4/6 modules incorporate the following

features:

• 8-bit Timer and Period registers (TMRx and PRx,

respectively)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4, 1:16,

and 1:64)

• Software programmable postscaler (1:1 to 1:16)

• Interrupt on TMRx match with PRx, respectively

• Optional use as the shift clock for the MSSPx

modules (Timer2 only)

See Figure 21-1 for a block diagram of Timer2/4/6.

FIGURE 21-1:

TIMER2/4/6 BLOCK DIAGRAM

Sets Flag

bit TMRxIF

TMRx

Output

Prescaler

TMRx

Reset

EQ

FOSC/4

1:1, 1:4, 1:16, 1:64

Postscaler

1:1 to 1:16

2

Comparator

TxCKPS<1:0>

PRx

4

TxOUTPS<3:0>

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 191

PIC16F/LF1826/27

21.1 Timer2/4/6 Operation

21.3 Timer2/4/6 Output

The clock input to the Timer2/4/6 modules is the

system instruction clock (FOSC/4).

The unscaled output of TMRx is available primarily to

the CCP modules, where it is used as a time base for

operations in PWM mode.

TMRx increments from 00h on each clock edge.

Timer2 can be optionally used as the shift clock source

for the MSSPx modules operating in SPI mode.

Additional information is provided in Section 24.0

“Master Synchronous Serial Port (MSSP1 and

MSSP2) Module”.

A 4-bit counter/prescaler on the clock input allows direct

input, divide-by-4 and divide-by-16 prescale options.

These options are selected by the prescaler control bits,

TxCKPS<1:0> of the TxCON register. The value of

TMRx is compared to that of the Period register, PRx, on

each clock cycle. When the two values match, the

comparator generates a match signal as the timer

output. This signal also resets the value of TMRx to 00h

on the next cycle and drives the output

counter/postscaler (see Section 21.2 “Timer2/4/6

Interrupt”).

21.4 Timer2/4/6 Operation During Sleep

The Timer2/4/6 timers cannot be operated while the

processor is in Sleep mode. The contents of the TMRx

and PRx registers will remain unchanged while the

processor is in Sleep mode.

The TMRx and PRx registers are both directly readable

and writable. The TMRx register is cleared on any

device Reset, whereas the PRx register initializes to

FFh. Both the prescaler and postscaler counters are

cleared on the following events:

• a write to the TMRx register

• a write to the TxCON register

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• MCLR Reset

• Watchdog Timer (WDT) Reset

• Stack Overflow Reset

• Stack Underflow Reset

• RESETInstruction

Note:

TMRx is not cleared when TxCON is written.

21.2 Timer2/4/6 Interrupt

Timer2/4/6 can also generate an optional device

interrupt. The Timer2/4/6 output signal (TMRx-to-PRx

match)

provides

the

input

for

the

4-bit

counter/postscaler. This counter generates the TMRx

match interrupt flag which is latched in TMRxIF of the

PIRx register. The interrupt is enabled by setting the

TMRx Match Interrupt Enable bit, TMRxIE of the PIEx

register.

A range of 16 postscale options (from 1:1 through 1:16

inclusive) can be selected with the postscaler control

bits, TxOUTPS<3:0>, of the TxCON register.

DS41391C-page 192

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

REGISTER 21-1: TXCON: TIMER2/TIMER4/TIMER6 CONTROL REGISTER

U-0

—

R/W-0/0

TOUTPS<3:0>

TMRxON

TxCKPS<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

bit 6-3

TOUTPS<3:0>: Timer Output Postscaler Select bits

0000= 1:1 Postscaler

0001= 1:2 Postscaler

0010= 1:3 Postscaler

0011= 1:4 Postscaler

0100= 1:5 Postscaler

0101= 1:6 Postscaler

0110= 1:7 Postscaler

0111= 1:8 Postscaler

1000= 1:9 Postscaler

1001= 1:10 Postscaler

1010= 1:11 Postscaler

1011= 1:12 Postscaler

1100= 1:13 Postscaler

1101= 1:14 Postscaler

1110= 1:15 Postscaler

1111= 1:16 Postscaler

bit 2

TMRxON: Timerx On bit

1= Timerx is on

0= Timerx is off

bit 1-0

TxCKPS<1:0>: Timer2-type Clock Prescale Select bits

00= Prescaler is 1

01= Prescaler is 4

10= Prescaler is 16

11= Prescaler is 64

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 193

PIC16F/LF1826/27

TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

PEIE

ADIE

ADIF

—

TMR0IE

RCIE

INTE

TXIE

TXIF

IOCIE

SSP1IE

SSP1IF

TMR0IF

CCP1IE

CCP1IF

INTF

IOCIF

91

92

TMR1GIE

TMR1GIF

TMR2IE

TMR2IF

TMR1IE

TMR1IF

PIR1

RCIF

96

(1)

PIE3

—

CCP4IE

CCP4IF

CCP3IE

CCP3IF

TMR6IE

TMR6IF

—

TMR4IE

TMR4IF

—

94

(1)

PIR3

—

98

PR2

Timer2 Module Period Register

Timer4 Module Period Register

Timer6 Module Period Register

191*

193

191*

193*

PR4

PR6

T2CON

T4CON

T6CON

TMR2

TMR4

TMR6

—

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0

T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0

T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0

Holding Register for the 8-bit TMR2 Time Base

Holding Register for the 8-bit TMR4 Time Base

Holding Register for the 8-bit TMR6 Time Base

(1)

Legend:

— = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.

*

Page provides register information.

Note 1: PIC16F/LF1827 only.

DS41391C-page 194

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

Using this method, the DSM can generate the following

types of Key Modulation schemes:

22.0 DATA SIGNAL MODULATOR

The Data Signal Modulator (DSM) is a peripheral which

allows the user to mix a data stream, also known as a

modulator signal, with a carrier signal to produce a

modulated output.

• Frequency-Shift Keying (FSK)

• Phase-Shift Keying (PSK)

• On-Off Keying (OOK)

Additionally, the following features are provided within

the DSM module:

Both the carrier and the modulator signals are supplied

to the DSM module either internally, from the output of

a peripheral, or externally through an input pin.

• Carrier Synchronization

The modulated output signal is generated by perform-

ing a logical “AND” operation of both the carrier and

modulator signals and then provided to the MDOUT pin.

• Carrier Source Polarity Select

• Carrier Source Pin Disable

• Programmable Modulator Data

• Modulator Source Pin Disable

• Modulated Output Polarity Select

• Slew Rate Control

The carrier signal is comprised of two distinct and sep-

arate signals. A carrier high (CARH) signal and a car-

rier low (CARL) signal. During the time in which the

modulator (MOD) signal is in a logic high state, the

DSM mixes the carrier high signal with the modulator

signal. When the modulator signal is in a logic low

state, the DSM mixes the carrier low signal with the

modulator signal.

Figure 22-1 shows a Simplified Block Diagram of the

Data Signal Modulator peripheral.

FIGURE 22-1:

SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR

MDCH<3:0>

MDEN

EN

VSS

MDCIN1

MDCIN2

CLKR

0000

0001

0010

0011

0100

0101

0110

0111

1000

Data Signal

Modulator

CCP1

CARH

CCP2

CCP3

CCP4

MDCHPOL

Reserved

No Channel

Selected

*

1111

D

SYNC

MDMS<3:0>

Q

1

MDBIT

MDMIN

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

0011

*

0

CCP1

CCP2

CCP3

MDCHSYNC

CCP4

Comparator C1

Comparator C2

MSSP1 SDO1

MSSP2 SDO2

EUSART

MOD

MDOUT

MDOE

MDOPOL

Reserved

No Channel

Selected

*

1111

D

SYNC

MDCL<3:0>

Q

1

0

VSS

MDCIN1

MDCIN2

CLKR

0000

0001

0010

0011

0100

0101

0110

0111

1000

CCP1

CCP2

CARL

MDCLSYNC

CCP3

CCP4

Reserved

No Channel

Selected

MDCLPOL

*

1111

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 195

PIC16F/LF1826/27

22.1 DSM Operation

22.3 Carrier Signal Sources

The DSM module can be enabled by setting the MDEN

bit in the MDCON register. Clearing the MDEN bit in the

MDCON register, disables the DSM module by auto-

matically switching the carrier high and carrier low sig-

nals to the VSS signal source. The modulator signal

source is also switched to the MDBIT in the MDCON

register. This not only assures that the DSM module is

inactive, but that it is also consuming the least amount

of current.

The carrier high signal and carrier low signal can be

supplied from the following sources:

• CCP1 Signal

• CCP2 Signal

• CCP3 Signal

• CCP4 Signal

• Reference Clock Module Signal

• External Signal on MDCIN1 pin

• External Signal on MDCIN2 pin

• VSS

The values used to select the carrier high, carrier low,

and modulator sources held by the Modulation Source,

Modulation High Carrier, and Modulation Low Carrier

control registers are not affected when the MDEN bit is

cleared and the DSM module is disabled. The values

inside these registers remain unchanged while the

DSM is inactive. The sources for the carrier high, car-

rier low and modulator signals will once again be

selected when the MDEN bit is set and the DSM mod-

ule is again enabled and active.

The carrier high signal is selected by configuring the

MDCH <3:0> bits in the MDCARH register. The carrier

low signal is selected by configuring the MDCL <3:0>

bits in the MDCARL register.

22.4 Carrier Synchronization

During the time when the DSM switches between car-

rier high and carrier low signal sources, the carrier data

in the modulated output signal can become truncated.

To prevent this, the carrier signal can be synchronized

to the modulator signal. When synchronization is

enabled, the carrier pulse that is being mixed at the

time of the transition is allowed to transition low before

the DSM switches over to the next carrier source.

The modulated output signal can be disabled without

shutting down the DSM module. The DSM module will

remain active and continue to mix signals, but the out-

put value will not be sent to the MDOUT pin. During the

time that the output is disabled, the MDOUT pin will

remain low. The modulated output can be disabled by

clearing the MDOE bit in the MDCON register.

Synchronization is enabled separately for the carrier

high and carrier low signal sources. Synchronization for

the carrier high signal can be enabled by setting the

MDCHSYNC bit in the MDCARH register. Synchroniza-

tion for the carrier low signal can be enabled by setting

the MDCLSYNC bit in the MDCARL register.

22.2 Modulator Signal Sources

The modulator signal can be supplied from the follow-

ing sources:

• CCP1 Signal

• CCP2 Signal

Figure 22-1 through Figure 22-5 show timing diagrams

of using various synchronization methods.

• CCP3 Signal

• CCP4 Signal

• MSSP1 SDO1 Signal (SPI Mode Only)

• MSSP2 SDO2 Signal (SPI Mode Only)

• Comparator C1 Signal

• Comparator C2 Signal

• EUSART TX Signal

• External Signal on MDMIN1 pin

• MDBIT bit in the MDCON register

The modulator signal is selected by configuring the

MDMS <3:0> bits in the MDSRC register.

DS41391C-page 196

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 22-2:

ON OFF KEYING (OOK) SYNCHRONIZATION

Carrier Low (CARL)

Carrier High (CARH)

Modulator (MOD)

MDCHSYNC = 1

MDCLSYNC = 0

MDCHSYNC = 1

MDCLSYNC = 1

MDCHSYNC = 0

MDCLSYNC = 0

MDCHSYNC = 0

MDCLSYNC = 1

EXAMPLE 22-1:

NO SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 0)

Carrier High (CARH)

Carrier Low (CARL)

Modulator (MOD)

MDCHSYNC = 0

MDCLSYNC = 0

CARH

CARL

CARH

CARL

Active Carrier

State

FIGURE 22-3:

CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0)

Carrier High (CARH)

Carrier Low (CARL)

Modulator (MOD)

MDCHSYNC = 1

MDCLSYNC = 0

Active Carrier

State

CARH

CARL

both

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 197

PIC16F/LF1826/27

FIGURE 22-4:

CARRIER LOW SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 1)

Carrier High (CARH)

Carrier Low (CARL)

Modulator (MOD)

MDCHSYNC = 0

MDCLSYNC = 1

Active Carrier

State

CARH

CARL

CARH

CARL

FIGURE 22-5:

FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1)

Carrier High (CARH)

Carrier Low (CARL)

Modulator (MOD)

Falling edges

used to sync

MDCHSYNC = 1

MDCLSYNC = 1

Active Carrier

State

CARH

CARL

DS41391C-page 198

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

22.5 CARRIER SOURCE POLARITY

SELECT

22.12 Effects of a Reset

Upon any device Reset, the Data Signal Modulator

module is disabled. The user's firmware is responsible

for initializing the module before enabling the output.

The registers are reset to their default values.

The signal provided from any selected input source for

the carrier high and carrier low signals can be inverted.

Inverting the signal for the carrier high source is

enabled by setting the MDCHPOL bit of the MDCARH

register. Inverting the signal for the carrier low source is

enabled by setting the MDCLPOL bit of the MDCARL

register.

22.6 CARRIER SOURCE PIN DISABLE

Some peripherals assert control over their correspond-

ing output pin when they are enabled. For example,

when the CCP1 module is enabled, the output of CCP1

is connected to the CCP1 pin.

This default connection to a pin can be disabled by set-

ting the MDCHODIS bit in the MDCARH register for the

carrier high source and the MDCLODIS bit in the

MDCARL register for the carrier low source.

22.7 PROGRAMMABLE MODULATOR

DATA

The MDBIT of the MDCON register can be selected as

the source for the modulator signal. This gives the user

the ability to program the value used for modulation.

22.8 MODULATOR SOURCE PIN

DISABLE

The modulator source default connection to a pin can

be disabled by setting the MDMSODIS bit in the

MDSRC register.

22.9 MODULATED OUTPUT POLARITY

The modulated output signal provided on the MDOUT

pin can also be inverted. Inverting the modulated out-

put signal is enabled by setting the MDOPOL bit of the

MDCON register.

22.10 SLEW RATE CONTROL

The slew rate limitation on the output port pin can be

disabled. The slew rate limitation can be removed by

clearing the MDSLR bit in the MDCON register.

22.11 OPERATION IN SLEEP MODE

The DSM module is not affected by Sleep mode. The

DSM can still operate during Sleep, if the Carrier and

Modulator input sources are also still operable during

Sleep.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 199

PIC16F/LF1826/27

REGISTER 22-1: MDCON: MODULATION CONTROL REGISTER

R/W-0/0

MDEN

R/W-0/0

MDOE

R/W-1/1

MDSLR

R/W-0/0

R-0/0

U-0

—

U-0

—

R/W-0/0

MDBIT

MDOPOL

MDOUT

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

bit 3

MDEN: Modulator Module Enable bit

1= Modulator module is enabled and mixing input signals

0= Modulator module is disabled and has no output

MDOE: Modulator Module Pin Output Enable bit

1= Modulator pin output enabled

0= Modulator pin output disabled

MDSLR: MDOUT Pin Slew Rate Limiting bit

1= MDOUT pin slew rate limiting enabled

0= MDOUT pin slew rate limiting disabled

MDOPOL: Modulator Output Polarity Select bit

1= Modulator output signal is inverted

0= Modulator output signal is not inverted

MDOUT: Modulator Output bit

Displays the current output value of the Modulator module.⁽¹⁾

bit 2-1

bit 0

Unimplemented: Read as ‘0’

MDBIT: Allows software to manually set modulation source input to module⁽²⁾

Note 1: The modulated output frequency can be greater and asynchronous from the clock that updates this

register bit, the bit value may not be valid for higher speed modulator or carrier signals.

2: MDBIT must be selected as the modulation source in the MDSRC register for this operation.

DS41391C-page 200

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

REGISTER 22-2: MDSRC: MODULATION SOURCE CONTROL REGISTER

R/W-x/u

MDMSODIS

bit 7

U-0

—

U-0

—

U-0

—

R/W-x/u

bit 0

MDMS<3:0>

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

MDMSODIS: Modulation Source Output Disable

1= Output signal driving the peripheral output pin (selected by MDMS<3:0>) is disabled

0= Output signal driving the peripheral output pin (selected by MDMS<3:0>) is enabled

bit 6-4

bit 3-0

Unimplemented: Read as ‘0’

MDMS<3:0> Modulation Source Selection bits

1111= Reserved. No channel connected.

1110= Reserved. No channel connected.

1101= Reserved. No channel connected.

1100= Reserved. No channel connected.

1011= Reserved. No channel connected.

1010= EUSART TX output

1001= MSSP2 SDOx output

1000= MSSP1 SDOx output

0111= Comparator2 output

0110= Comparator1 output

0101= CCP4 output (PWM Output mode only)

0100= CCP3 output (PWM Output mode only)

0011= CCP2 output (PWM Output mode only)

0010= CCP1 output (PWM Output mode only)

0001= MDMIN port pin

0000= MDBIT bit of MDCON register is modulation source

Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 201

PIC16F/LF1826/27

REGISTER 22-3: MDCARH: MODULATION HIGH CARRIER CONTROL REGISTER

R/W-x/u

MDCHODIS

bit 7

R/W-x/u

U-0

—

R/W-x/u

bit 0

MDCHPOL MDCHSYNC

MDCH<3:0>

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

MDCHODIS: Modulator High Carrier Output Disable

1= Output signal driving the peripheral output pin (selected by MDCH<3:0>) is disabled

0= Output signal driving the peripheral output pin (selected by MDCH<3:0>) is enabled

MDCHPOL: Modulator High Carrier Polarity Select bit

1= Selected high carrier signal is inverted

0= Selected high carrier signal is not inverted

MDCHSYNC: Modulator High Carrier Synchronization Enable bit

1= Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the

low time carrier

0= Modulator Output is not synchronized to the high time carrier signal⁽¹⁾

bit 4

Unimplemented: Read as ‘0’

bit 3-0

MDCH<3:0> Modulator Data High Carrier Selection bits ⁽¹⁾

1111= Reserved. No channel connected.

•

1000= Reserved. No channel connected.

0111= CCP4 output (PWM Output mode only)

0110= CCP3 output (PWM Output mode only)

0101= CCP2 output (PWM Output mode only)

0100= CCP1 output (PWM Output mode only)

0011= Reference Clock module signal

0010= MDCIN2 port pin

0001= MDCIN1 port pin

0000= VSS

Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.

DS41391C-page 202

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

REGISTER 22-4: MDCARL: MODULATION LOW CARRIER CONTROL REGISTER

R/W-x/u

U-0

—

R/W-x/u

bit 0

MDCLODIS

MDCLPOL MDCLSYNC

MDCL<3:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

MDCLODIS: Modulator Low Carrier Output Disable

1= Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register)

is disabled

0= Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register)

is enabled

bit 6

bit 5

MDCLPOL: Modulator Low Carrier Polarity Select bit

1= Selected low carrier signal is inverted

0= Selected low carrier signal is not inverted

MDCLSYNC: Modulator Low Carrier Synchronization Enable bit

1= Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high

time carrier

0= Modulator Output is not synchronized to the low time carrier signal⁽¹⁾

bit 4

Unimplemented: Read as ‘0’

bit 3-0

MDCL<3:0> Modulator Data High Carrier Selection bits ⁽¹⁾

1111= Reserved. No channel connected.

•

1000= Reserved. No channel connected.

0111= CCP4 output (PWM Output mode only)

0110= CCP3 output (PWM Output mode only)

0101= CCP2 output (PWM Output mode only)

0100= CCP1 output (PWM Output mode only)

0011= Reference Clock module signal

0010= MDCIN2 port pin

0001= MDCIN1 port pin

0000= VSS

Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.

TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MDCARH MDCHODIS MDCHPOL MDCHSYNC

MDCARL MDCLODIS MDCLPOL MDCLSYNC

MDCH<3:0>

MDCL<3:0>

—

202

203

200

MDCON

MDSRC

Legend:

MDEN

MDOE

—

MDSLR

—

MDOPOL

MDOUT

MDBIT

—

MDMSODIS

MDMS<3:0>

—

201

— = unimplemented, read as ‘0’. Shaded cells are not used in the Data Signal Modulator mode.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 203

PIC16F/LF1826/27

NOTES:

DS41391C-page 204

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

23.0 CAPTURE/COMPARE/PWM

MODULES

Note 1: In devices with more than one CCP

module, it is very important to pay close

attention to the register names used. A

number placed after the module acronym

is used to distinguish between separate

modules. For example, the CCP1CON

and CCP2CON control the same

operational aspects of two completely

different CCP modules.

The Capture/Compare/PWM module is a peripheral

which allows the user to time and control different

events, and to generate Pulse-Width Modulation

(PWM) signals. In Capture mode, the peripheral allows

the timing of the duration of an event. The Compare

mode allows the user to trigger an external event when

a predetermined amount of time has expired. The

PWM mode can generate Pulse-Width Modulated

signals of varying frequency and duty cycle.

2: Throughout

this

section,

generic

references to a CCP module in any of its

operating modes may be interpreted as

being equally applicable to ECCP1,

ECCP2, CCP3 and CCP4. Register

names, module signals, I/O pins, and bit

names may use the generic designator 'x'

to indicate the use of a numeral to

distinguish a particular module, when

required.

This family of devices contains two Enhanced

Capture/Compare/PWM modules (ECCP1 and ECCP2,)

and two standard Capture/Compare/PWM modules

(CCP3 and CCP4).

The Capture and Compare functions are identical for all

four CCP modules (ECCP1, ECCP2, CCP3, and

CCP4). The only differences between CCP modules

are in the Pulse-Width Modulation (PWM) function. The

standard PWM function is identical in modules, CCP3

and CCP4. In CCP modules ECCP1 and ECCP2, the

Enhanced PWM function has slight variations from one

another. Full-Bridge ECCP modules have four

available I/O pins while Half-Bridge ECCP modules

only have two available I/O pins. See Table 23-1 for

more information.

TABLE 23-1: PWM RESOURCES

Device Name

ECCP1

ECCP2

CCP3

CCP4

Enhanced PWM

Full-Bridge

PIC16F/LF1826

Not Available

Enhanced PWM

Full-Bridge

Enhanced PWM

Half-Bridge

PIC16F/LF1827

Standard PWM

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 205

PIC16F/LF1826/27

23.1.2

TIMER1 MODE RESOURCE

23.1 Capture Mode

Timer1 must be running in Timer mode or Synchronized

Counter mode for the CCP module to use the capture

feature. In Asynchronous Counter mode, the capture

operation may not work.

The Capture mode function described in this section is

available and identical for CCP modules ECCP1,

ECCP2, CCP3 and CCP4.

Capture mode makes use of the 16-bit Timer1

resource. When an event occurs on the CCPx pin, the

16-bit CCPRxH:CCPRxL register pair captures and

stores the 16-bit value of the TMR1H:TMR1L register

pair, respectively. An event is defined as one of the

following and is configured by the CCPxM<3:0> bits of

the CCPxCON register:

See Section 20.0 “Timer1 Module with Gate Control”

for more information on configuring Timer1.

23.1.3

SOFTWARE INTERRUPT MODE

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCPxIE interrupt enable bit of the PIEx register clear to

avoid false interrupts. Additionally, the user should

clear the CCPxIF interrupt flag bit of the PIRx register

following any change in Operating mode.

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge

Note:

Clocking Timer1 from the system clock

(FOSC) should not be used in Capture

mode. In order for Capture mode to

recognize the trigger event on the CCPx

pin, Timer1 must be clocked from the

instruction clock (FOSC/4) or from an

external clock source.

When a capture is made, the Interrupt Request Flag bit

CCPxIF of the PIRx register is set. The interrupt flag

must be cleared in software. If another capture occurs

before the value in the CCPRxH, CCPRxL register pair

is read, the old captured value is overwritten by the new

captured value.

Figure 23-1 shows a simplified diagram of the Capture

operation.

23.1.4

CCP PRESCALER

There are four prescaler settings specified by the

CCPxM<3:0> bits of the CCPxCON register. Whenever

the CCP module is turned off, or the CCP module is not

in Capture mode, the prescaler counter is cleared. Any

Reset will clear the prescaler counter.

23.1.1

CCP PIN CONFIGURATION

In Capture mode, the CCPx pin should be configured

as an input by setting the associated TRIS control bit.

Also, the CCPx pin function can be moved to

alternative pins using the APFCON0 or APFCON1

register. Refer to Section 12.1 “Alternate Pin

Function” for more details.

Switching from one capture prescaler to another does not

clear the prescaler and may generate a false interrupt. To

avoid this unexpected operation, turn the module off by

clearing the CCPxCON register before changing the

prescaler. Example 12-1 demonstrates the code to

perform this function.

Note:

If the CCPx pin is configured as an output,

a write to the port can cause a capture

condition.

EXAMPLE 23-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

FIGURE 23-1:

CAPTURE MODE

OPERATION BLOCK

DIAGRAM

BANKSELCCPxCON

;Set Bank bits to point

;to CCPxCON

;Turn CCP module off

Set Flag bit CCPxIF

(PIRx register)

CLRF

CCPxCON

Prescaler

 1, 4, 16

MOVLW NEW_CAPT_PS;Load the W reg with

;the new prescaler

;move value and CCP ON

;Load CCPxCON with this

;value

CCPx

CCPRxH

CCPRxL

MOVWF CCPxCON

Capture

Enable

and

Edge Detect

TMR1H

TMR1L

CCPxM<3:0>

System Clock (FOSC)

DS41391C-page 206

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

23.1.5

CAPTURE DURING SLEEP

23.1.6

ALTERNATE PIN LOCATIONS

Capture mode depends upon the Timer1 module for

proper operation. There are two options for driving the

Timer1 module in Capture mode. It can be driven by the

instruction clock (FOSC/4), or by an external clock source.

This module incorporates I/O pins that can be moved to

other locations with the use of the Alternate Pin Func-

tion registers, APFCON0 and APFCON1. To determine

which pins can be moved and what their default loca-

tions are upon a Reset, see Section 12.1 “Alternate

Pin Function” for more information.

When Timer1 is clocked by FOSC/4, Timer1 will not

increment during Sleep. When the device wakes from

Sleep, Timer1 will continue from its previous state.

Capture mode will operate during Sleep when Timer1

is clocked by an external clock source.

TABLE 23-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(2)

APFCON0

CCPxCON

CCPRxL

CCPRxH

CMxCON0

CMxCON1

INTCON

PIE1

RXDTSEL SDO1SEL SS1SEL P2BSEL

CCP2SEL

P1DSEL

CCPxM2

P1CSEL CCP1SEL

122

228

206*

172

173

91

(1)

PxM1

PxM0

DCxB1

DCxB0

CCPxM3

CCPxM1

CCPxM0

Capture/Compare/PWM Register x Low Byte (LSB)

Capture/Compare/PWM Register x High Byte (MSB)

CxON

CxINTP

GIE

CxOUT

CxINTN

PEIE

CxOE

CxPCH1

TMR0IE

RCIE

CxPOL

CxPCH0

INTE

—

CxSP

—

CxHYS

CxNCH1

INTF

CxSYNC

CxNCH0

IOCIF

—

IOCIE

TMR0IF

CCP1IE

—

TMR1GIE

OSFIE

—

ADIE

TXIE

SSP1IE

BCL1IE

TMR6IE

SSP1IF

BCL1IF

TMR6IF

T1OSCEN

TMR2IE

—

TMR1IE

92

(2)

PIE2

C2IE

C1IE

EEIE

CCP2IE

—

93

(2)

PIE3

CCP4IE

RCIF

CCP3IE

TXIF

—

TMR4IE

TMR2IF

—

94

PIR1

PIR2

TMR1GIF

OSFIF

—

ADIF

C2IF

CCP1IF

—

TMR1IF

96

(2)

C1IF

EEIF

CCP2IF

—

97

(2)

PIR3

CCP4IF

CCP3IF

—

TMR4IF

—

98

T1CON

T1GCON

TMR1L

TMR1H

TRISA

TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0

TMR1GE T1GPOL T1GTM

T1SYNC

TMR1ON

T1GSS0

187

188

179*

124

129

T1GSPM T1GGO/DONE T1GVAL

T1GSS1

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

TRISA7

TRISB7

TRISA6

TRISB6

TRISA5

TRISB5

TRISA4

TRISB4

TRISA3

TRISB3

TRISA2

TRISB2

TRISA1

TRISB1

TRISA0

TRISB0

TRISB

Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by Capture mode.

Page provides register information.

*

Note 1: Applies to ECCP modules only.

2: PIC16F/LF1827 only.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 207

PIC16F/LF1826/27

23.2.2

TIMER1 MODE RESOURCE

23.2 Compare Mode

In Compare mode, Timer1 must be running in either Timer

mode or Synchronized Counter mode. The compare

operation may not work in Asynchronous Counter mode.

The Compare mode function described in this section

is available and identical for CCP modules ECCP1,

ECCP2, CCP3 and CCP4.

See Section 23.2.2 “Timer1 Mode Resource” for

more information on configuring Timer1.

Compare mode makes use of the 16-bit Timer1

resource. The 16-bit value of the CCPRxH:CCPRxL

register pair is constantly compared against the 16-bit

value of the TMR1H:TMR1L register pair. When a

match occurs, one of the following events can occur:

Note:

Clocking Timer1 from the system clock

(FOSC) should not be used in Compare

mode. In order for Compare mode to

recognize the trigger event on the CCPx

pin, TImer1 must be clocked from the

instruction clock (FOSC/4) or from an

external clock source.

• Toggle the CCPx output

• Set the CCPx output

• Clear the CCPx output

• Generate a Special Event Trigger

• Generate a Software Interrupt

23.2.3

SOFTWARE INTERRUPT MODE

The action on the pin is based on the value of the

CCPxM<3:0> control bits of the CCPxCON register. At

the same time, the interrupt flag CCPxIF bit is set.

When Generate Software Interrupt mode is chosen

(CCPxM<3:0> = 1010), the CCPx module does not

assert control of the CCPx pin (see the CCPxCON

register).

All Compare modes can generate an interrupt.

Figure 23-2 shows

Compare operation.

a simplified diagram of the

23.2.4

SPECIAL EVENT TRIGGER

When Special Event Trigger mode is chosen

(CCPxM<3:0> = 1011), the CCPx module does the

following:

FIGURE 23-2:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

• Resets Timer1

• Starts an ADC conversion if ADC is enabled

CCPxM<3:0>

Mode Select

The CCPx module does not assert control of the CCPx

pin in this mode.

Set CCPxIF Interrupt Flag

The Special Event Trigger output of the CCP occurs

immediately upon a match between the TMR1H,

TMR1L register pair and the CCPRxH, CCPRxL

register pair. The TMR1H, TMR1L register pair is not

reset until the next rising edge of the Timer1 clock. The

Special Event Trigger output starts an A/D conversion

(if the A/D module is enabled). This allows the

CCPRxH, CCPRxL register pair to effectively provide a

16-bit programmable period register for Timer1.

(PIRx)

4

CCPx

CCPRxH CCPRxL

Comparator

Q

S

R

Output

Logic

Match

TMR1H TMR1L

TRIS

Output Enable

Special Event Trigger

TABLE 23-3: SPECIAL EVENT TRIGGER

Device

CCPx/ECCPx

23.2.1

CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the associated TRIS bit.

PIC16F/LF1826

PIC16F/LF1827

ECCP1

CCP4

Also, the CCPx pin function can be moved to

alternative pins using the APFCON register. Refer to

Section 12.1 “Alternate Pin Function” for more

details.

Refer to Section 15.2.5 “Special Event Trigger” for

more information.

Note 1: The Special Event Trigger from the CCP

module does not set interrupt flag bit

TMR1IF of the PIR1 register.

Note:

Clearing the CCPxCON register will force

the CCPx compare output latch to the

default low level. This is not the PORT I/O

data latch.

2: Removing the match condition by

changing the contents of the CCPRxH

and CCPRxL register pair, between the

clock edge that generates the Special

Event Trigger and the clock edge that

generates the Timer1 Reset, will preclude

the Reset from occurring.

DS41391C-page 208

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

23.2.5

COMPARE DURING SLEEP

23.2.6

ALTERNATE PIN LOCATIONS

The Compare mode is dependent upon the system

clock (FOSC) for proper operation. Since FOSC is shut

down during Sleep mode, the Compare mode will not

function properly during Sleep.

This module incorporates I/O pins that can be moved to

other locations with the use of the alternate pin function

registers, APFCON0 and APFCON1. To determine

which pins can be moved and what their default loca-

tions are upon a Reset, see Section 12.1 “Alternate

Pin Function” for more information.

TABLE 23-4: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(2)

APFCON0

CCPxCON

CCPRxL

CCPRxH

CM1CON0

CM1CON1

CM2CON0

CM2CON1

INTCON

PIE1

RXDTSEL SDO1SEL SS1SEL P2BSEL

CCP2SEL

P1DSEL

CCPxM2

P1CSEL CCP1SEL

122

228

206*

172

173

172

173

91

(1)

PxM1

PxM0

DCxB1

DCxB0

CCPxM3

CCPxM1

CCPxM0

Capture/Compare/PWM Register x Low Byte (LSB)

Capture/Compare/PWM Register x High Byte (MSB)

C1ON

C1INTP

C2ON

C2INTP

GIE

C1OUT

C1INTN

C2OUT

C2INTN

PEIE

C1OE

C1PCH1

C2OE

C1POL

C1PCH0

C2POL

C2PCH0

INTE

—

C1SP

—

C1HYS

C1NCH1

C2HYS

C2NCH1

INTF

C1SYNC

C1NCH0

C2SYNC

C2NCH0

IOCIF

—

C2SP

—

C2PCH1

TMR0IE

RCIE

—

IOCIE

SSPIE

BCL1IE

TMR6IE

SSPIF

BCLIF

TMR6IF

T1OSCEN

TMR0IF

CCP1IE

—

TMR1GIE

OSFIE

—

ADIE

TXIE

TMR2IE

—

TMR1IE

92

(2)

PIE2

C2IE

C1IE

EEIE

CCP2IE

—

93

(2)

PIE3

CCP4IE

RCIF

CCP3IE

TXIF

—

TMR4IE

TMR2IF

—

94

PIR1

PIR2

TMR1GIF

OSFIF

—

ADIF

C2IF

CCP1IF

—

TMR1IF

96

(2)

C1IF

EEIF

CCP2IF

—

97

(2)

PIR3

CCP4IF

CCP3IF

—

TMR4IF

—

98

T1CON

T1GCON

TMR1L

TMR1H

TRISA

TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0

TMR1GE T1GPOL T1GTM

T1SYNC

TMR1ON

T1GSS0

187

188

179*

124

129

T1GSPM T1GGO/DONE T1GVAL

T1GSS1

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

TRISA7

TRISB7

TRISA6

TRISB6

TRISA5

TRISB5

TRISA4

TRISB4

TRISA3

TRISB3

TRISA2

TRISB2

TRISA1

TRISB1

TRISA0

TRISB0

TRISB

Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by Compare mode.

Page provides register information.

*

Note 1: Applies to ECCP modules only.

2: PIC16F/LF1827 only.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 209

PIC16F/LF1826/27

FIGURE 23-3:

CCP PWM OUTPUT SIGNAL

23.3 PWM Overview

Pulse-Width Modulation (PWM) is a scheme that

provides power to a load by switching quickly between

fully on and fully off states. The PWM signal resembles

a square wave where the high portion of the signal is

considered the on state and the low portion of the signal

is considered the off state. The high portion, also known

as the pulse width, can vary in time and is defined in

steps. A larger number of steps applied, which

lengthens the pulse width, also supplies more power to

the load. Lowering the number of steps applied, which

shortens the pulse width, supplies less power. The

PWM period is defined as the duration of one complete

cycle or the total amount of on and off time combined.

Period

Pulse Width

TMRx = PRx

TMRx = CCPRxH:CCPxCON<5:4>

TMRx = 0

FIGURE 23-4:

SIMPLIFIED PWM BLOCK

DIAGRAM

CCPxCON<5:4>

Duty Cycle Registers

PWM resolution defines the maximum number of steps

that can be present in a single PWM period. A higher

resolution allows for more precise control of the pulse

width time and in turn the power that is applied to the

load.

CCPRxL

CCPRxH⁽²⁾(Slave)

Comparator

CCPx

The term duty cycle describes the proportion of the on

time to the off time and is expressed in percentages,

where 0% is fully off and 100% is fully on. A lower duty

cycle corresponds to less power applied and a higher

duty cycle corresponds to more power applied.

R

S

Q

(1)

TMRx

TRIS

Figure 23-3 shows a typical waveform of the PWM

signal.

Comparator

PRx

Clear Timer,

toggle CCPx pin and

latch duty cycle

23.3.1

STANDARD PWM OPERATION

The standard PWM function described in this section is

available and identical for CCP modules ECCP1,

ECCP2, CCP3 and CCP4.

Note 1: The 8-bit timer TMRx register is concatenated

with the 2-bit internal system clock (FOSC), or

2 bits of the prescaler, to create the 10-bit time

base.

The standard PWM mode generates a Pulse-Width

modulation (PWM) signal on the CCPx pin with up to 10

bits of resolution. The period, duty cycle, and resolution

are controlled by the following registers:

2: In PWM mode, CCPRxH is a read-only register.

• PRx registers

• TxCON registers

• CCPRxL registers

• CCPxCON registers

Figure 23-4 shows a simplified block diagram of PWM

operation.

Note 1: The corresponding TRIS bit must be

cleared to enable the PWM output on the

CCPx pin.

2: Clearing the CCPxCON register will

relinquish control of the CCPx pin.

DS41391C-page 210

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

When TMRx is equal to PRx, the following three events

occur on the next increment cycle:

23.3.2

SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for standard PWM operation:

• TMRx is cleared

• The CCPx pin is set. (Exception: If the PWM duty

cycle = 0%, the pin will not be set.)

1. Disable the CCPx pin output driver by setting the

associated TRIS bit.

• The PWM duty cycle is latched from CCPRxL into

CCPRxH.

2. Load the PRx register with the PWM period

value.

3. Configure the CCP module for the PWM mode

by loading the CCPxCON register with the

appropriate values.

Note:

The Timer postscaler (see Section 21.1

“Timer2/4/6 Operation”) is not used in the

determination of the PWM frequency.

4. Load the CCPRxL register and the DCxBx bits

of the CCPxCON register, with the PWM duty

cycle value.

23.3.5

PWM DUTY CYCLE

The PWM duty cycle is specified by writing a 10-bit

value to multiple registers: CCPRxL register and

DCxB<1:0> bits of the CCPxCON register. The

CCPRxL contains the eight MSbs and the DCxB<1:0>

bits of the CCPxCON register contain the two LSbs.

CCPRxL and DCxB<1:0> bits of the CCPxCON

register can be written to at any time. The duty cycle

value is not latched into CCPRxH until after the period

completes (i.e., a match between PRx and TMRx

registers occurs). While using the PWM, the CCPRxH

register is read-only.

5. Configure and start Timer2/4/6:

• Select the Timer2/4/6 resource to be used

for PWM generation by setting the

CxTSEL<1:0> bits in the CCPTMRS

register.

• Clear the TMRxIF interrupt flag bit of the

PIRx register. See Note below.

• Configure the TxCKPS bits of the TxCON

register with the Timer prescale value.

• Enable the Timer by setting the TMRxON

bit of the TxCON register.

Equation 12-2 is used to calculate the PWM pulse

width.

6. Enable PWM output pin:

• Wait until the Timer overflows and the

TMRxIF bit of the PIRx register is set. See

Note below.

Equation 12-3 is used to calculate the PWM duty cycle

ratio.

• Enable the CCPx pin output driver by clear-

ing the associated TRIS bit.

EQUATION 23-2: PULSE WIDTH

Pulse Width = CCPRxL:CCPxCON<5:4> 

TOSC  (TMRx Prescale Value)

Note:

In order to send a complete duty cycle and

period on the first PWM output, the above

steps must be included in the setup

sequence. If it is not critical to start with a

complete PWM signal on the first output,

then step 6 may be ignored.

EQUATION 23-3: DUTY CYCLE RATIO

23.3.3

TIMER2/4/6 TIMER RESOURCE

CCPRxL:CCPxCON<5:4>

Duty Cycle Ratio = ----------------------------------------------------------------------

4PRx + 1

The PWM standard mode makes use of one of the 8-bit

Timer2/4/6 timer resources to specify the PWM period.

The CCPRxH register and a 2-bit internal latch are

used to double buffer the PWM duty cycle. This double

buffering is essential for glitchless PWM operation.

Configuring the CxTSEL<1:0> bits in the CCPTMRS

register selects which Timer2/4/6 timer is used.

23.3.4

PWM PERIOD

The 8-bit timer TMRx register is concatenated with either

the 2-bit internal system clock (FOSC), or 2 bits of the

prescaler, to create the 10-bit time base. The system

clock is used if the Timer2/4/6 prescaler is set to 1:1.

The PWM period is specified by the PRx register of

Timer2/4/6. The PWM period can be calculated using

the formula of Equation 12-1.

When the 10-bit time base matches the CCPRxH and

2-bit latch, then the CCPx pin is cleared (see

Figure 23-4).

EQUATION 23-1: PWM PERIOD

PWM Period = PRx + 1  4  TOSC 

(TMRx Prescale Value)

Note 1: TOSC = 1/FOSC

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 211

PIC16F/LF1826/27

23.3.6

PWM RESOLUTION

EQUATION 23-4: PWM RESOLUTION

The resolution determines the number of available duty

cycles for a given period. For example, a 10-bit resolution

will result in 1024 discrete duty cycles, whereas an 8-bit

resolution will result in 256 discrete duty cycles.

log4PRx + 1

Resolution = ----------------------------------------- bits

log2

The maximum PWM resolution is 10 bits when PRx is

255. The resolution is a function of the PRx register

value as shown by Equation 12-4.

Note:

If the pulse width value is greater than the

period the assigned PWM pin(s) will

remain unchanged.

TABLE 23-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 32 MHz)

PWM Frequency

1.95 kHz

7.81 kHz

31.25 kHz

125 kHz

250 kHz

333.3 kHz

Timer Prescale (1, 4, 16)

PRx Value

16

0xFF

10

4

1

0x3F

8

1

0x1F

7

1

0xFF

10

0xFF

10

0x17

6.6

Maximum Resolution (bits)

TABLE 23-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

PWM Frequency

1.22 kHz

4.88 kHz

19.53 kHz

78.12 kHz

156.3 kHz

208.3 kHz

Timer Prescale (1, 4, 16)

PRx Value

16

0xFF

10

4

1

0x3F

8

1

0x1F

7

1

0xFF

10

0xFF

10

0x17

6.6

Maximum Resolution (bits)

TABLE 23-7: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

PWM Frequency

1.22 kHz

4.90 kHz

19.61 kHz

76.92 kHz

153.85 kHz 200.0 kHz

Timer Prescale (1, 4, 16)

PRx Value

16

0x65

8

4

0x65

8

1

0x65

8

1

0x19

6

1

0x0C

5

1

0x09

5

Maximum Resolution (bits)

DS41391C-page 212

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

23.3.7

OPERATION IN SLEEP MODE

23.3.10 ALTERNATE PIN LOCATIONS

In Sleep mode, the TMRx register will not increment

and the state of the module will not change. If the CCPx

pin is driving a value, it will continue to drive that value.

When the device wakes up, TMRx will continue from its

previous state.

This module incorporates I/O pins that can be moved to

other locations with the use of the alternate pin function

registers, APFCON0 and APFCON1. To determine

which pins can be moved and what their default loca-

tions are upon a Reset, see Section 12.1 “Alternate

Pin Function” for more information.

23.3.8

CHANGES IN SYSTEM CLOCK

FREQUENCY

The PWM frequency is derived from the system clock

frequency. Any changes in the system clock frequency

will result in changes to the PWM frequency. See

Section 5.0 “Oscillator Module (With Fail-Safe

Clock Monitor)” for additional details.

23.3.9

EFFECTS OF RESET

Any Reset will force all ports to Input mode and the

CCP registers to their Reset states.

TABLE 23-8: SUMMARY OF REGISTERS ASSOCIATED WITH PWM

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(2)

APFCON0

CCPxCON

CCPxAS

CCPTMRS

INTCON

PRx

RXDTSEL SDO1SEL

SS1SEL

DCxB1

P2BSEL

CCP2SEL

P1DSEL

CCPxM2

P1CSEL

CCPxM1

CCP1SEL

CCPxM0

122

228

230

229

91

(1)

PxM1

PxM0

DCxB0

CCPxM3

CCPxASE CCPxAS2 CCPxAS1 CCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0

C4TSEL1

GIE

C4TSEL0

PEIE

C3TSEL1

TMR0IE

C3TSEL0

INTE

C2TSEL1

IOCIE

C2TSEL0

TMR0IF

C1TSEL1

INTF

C1TSEL0

IOCIF

Timerx Period Register

191*

232

231

193

191*

129

PSTRxCON

PWMxCON

TxCON

—

PxRSEN

—

STRxSYNC

PxDC4

STRxD

PxDC3

STRxC

PxDC2

STRxB

PxDC1

STRxA

PxDC0

PxDC6

PxDC5

TxOUTPS3 TxOUTPS2 TxOUTPS1 TxOUTPS0 TMRxON

TxCKPS1 TxCKPS0

TMRx

Timerx Module Register

TRISB7 TRISB6

TRISB

TRISB5

TRISB4

TRISB3

TRISB2

TRISB1

TRISB0

Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the PWM.

Page provides register information.

*

Note 1: Applies to ECCP modules only.

2: PIC16F/LF1827 only.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 213

PIC16F/LF1826/27

To select an Enhanced PWM Output mode, the PxM bits

of the CCPxCON register must be configured

appropriately.

23.4 PWM (Enhanced Mode)

The enhanced PWM function described in this section is

available for CCP modules ECCP1, ECCP2 and

ECCP3, with any differences between modules noted.

The PWM outputs are multiplexed with I/O pins and are

designated PxA, PxB, PxC and PxD. The polarity of the

PWM pins is configurable and is selected by setting the

CCPxM bits in the CCPxCON register appropriately.

The enhanced PWM mode generates a Pulse-Width

Modulation (PWM) signal on up to four different output

pins with up to 10 bits of resolution. The period, duty

cycle, and resolution are controlled by the following

registers:

Figure 23-5 shows an example of a simplified block

diagram of the Enhanced PWM module.

Figure 23-8 shows the pin assignments for various

Enhanced PWM modes.

• PRx registers

• TxCON registers

• CCPRxL registers

• CCPxCON registers

Note 1: The corresponding TRIS bit must be

cleared to enable the PWM output on the

CCPx pin.

The ECCP modules have the following additional PWM

registers which control Auto-shutdown, Auto-restart,

Dead-band Delay and PWM Steering modes:

2: Clearing the CCPxCON register will

relinquish control of the CCPx pin.

3: Any pin not used in the enhanced PWM

mode is available for alternate pin

functions, if applicable.

• CCPxAS registers

• PSTRxCON registers

• PWMxCON registers

4: To prevent the generation of an

incomplete waveform when the PWM is

first enabled, the ECCP module waits

until the start of a new PWM period before

generating a PWM signal.

The enhanced PWM module can generate the following

five PWM Output modes:

• Single PWM

• Half-Bridge PWM

• Full-Bridge PWM, Forward Mode

• Full-Bridge PWM, Reverse Mode

• Single PWM with PWM Steering Mode

FIGURE 23-5:

EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE

DCxB<1:0>

PxM<1:0>

CCPxM<3:0>

4

Duty Cycle Registers

2

CCPRxL

CCPx/PxA

PxB

TRISx

CCPRxH (Slave)

Comparator

PxB

Output

Controller

R

S

Q

PxC

(1)

TMRx

PxD

Comparator

PRx

Clear Timer,

toggle PWM pin and

latch duty cycle

PWMxCON

Note 1: The 8-bit timer TMRx register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time

base.

DS41391C-page 214

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 23-9: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES

ECCP Mode

PxM<1:0>

CCPx/PxA

PxB

PxC

PxD

Single

00

10

01

11

Yes⁽¹⁾

Yes

Yes⁽¹⁾

Yes

Yes⁽¹⁾

No

Yes⁽¹⁾

No

Half-Bridge

Full-Bridge, Forward

Full-Bridge, Reverse

Yes

Note 1: PWM Steering enables outputs in Single mode.

FIGURE 23-6:

EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH

STATE)

PRX+1

Pulse

Width

0

Signal

PxM<1:0>

Period

PxA Modulated

(Single Output)

00

10

Delay

PxA Modulated

PxB Modulated

PxA Active

(Half-Bridge)

PxB Inactive

(Full-Bridge,

Forward)

01

PxC Inactive

PxD Modulated

PxA Inactive

PxB Modulated

PxC Active

(Full-Bridge,

Reverse)

11

PxD Inactive

Relationships:

•

Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)

Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)

Delay = 4 * TOSC * (PWMxCON<6:0>)

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 215

PIC16F/LF1826/27

FIGURE 23-7:

EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)

PRx+1

Pulse

Width

0

Signal

PxM<1:0>

Period

PxA Modulated

PxB Modulated

PxA Active

(Single Output)

00

10

Delay

(Half-Bridge)

(Full-Bridge,

Forward)

PxB Inactive

PxC Inactive

PxD Modulated

PxA Inactive

PxB Modulated

PxC Active

01

(Full-Bridge,

Reverse)

11

PxD Inactive

Relationships:

•

Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value)

Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value)

Delay = 4 * TOSC * (PWMxCON<6:0>)

DS41391C-page 216

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

Since the PxA and PxB outputs are multiplexed with the

PORT data latches, the associated TRIS bits must be

cleared to configure PxA and PxB as outputs.

23.4.1

HALF-BRIDGE MODE

In Half-Bridge mode, two pins are used as outputs to

drive push-pull loads. The PWM output signal is output

on the CCPx/PxA pin, while the complementary PWM

output signal is output on the PxB pin (see

Figure 23-9). This mode can be used for Half-Bridge

applications, as shown in Figure 23-9, or for Full-Bridge

applications, where four power switches are being

modulated with two PWM signals.

FIGURE 23-8:

EXAMPLE OF

HALF-BRIDGE PWM

OUTPUT

Period

Pulse Width

In Half-Bridge mode, the programmable dead-band delay

can be used to prevent shoot-through current in

Half-Bridge power devices. The value of the PDC<6:0>

bits of the PWMxCON register sets the number of

instruction cycles before the output is driven active. If the

value is greater than the duty cycle, the corresponding

output remains inactive during the entire cycle. See

Section 23.4.5 “Programmable Dead-Band Delay

Mode” for more details of the dead-band delay

operations.

(2)

PxA

td

PxB

(1)

td = Dead-Band Delay

Note 1: At this time, the TMRx register is equal to the

PRx register.

2: Output signals are shown as active-high.

FIGURE 23-9:

EXAMPLE OF HALF-BRIDGE APPLICATIONS

Standard Half-Bridge Circuit (“Push-Pull”)

FET

Driver

+

-

PxA

Load

FET

Driver

+

-

PxB

Half-Bridge Output Driving a Full-Bridge Circuit

V+

FET

Driver

FET

Driver

PxA

Load

FET

Driver

PxB

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 217

PIC16F/LF1826/27

23.4.2

FULL-BRIDGE MODE

In Full-Bridge mode, all four pins are used as outputs.

An example of Full-Bridge application is shown in

Figure 23-10.

In the Forward mode, pin CCPx/PxA is driven to its active

state, pin PxD is modulated, while PxB and PxC will be

driven to their inactive state as shown in Figure 23-11.

In the Reverse mode, PxC is driven to its active state, pin

PxB is modulated, while PxA and PxD will be driven to

their inactive state as shown Figure 23-12.

PxA, PxB, PxC and PxD outputs are multiplexed with

the PORT data latches. The associated TRIS bits must

be cleared to configure the PxA, PxB, PxC and PxD

pins as outputs.

FIGURE 23-10:

EXAMPLE OF FULL-BRIDGE APPLICATION

V+

QC

QA

FET

Driver

FET

Driver

PxA

PxB

Load

FET

Driver

FET

Driver

PxC

PxD

QD

QB

V-

DS41391C-page 218

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 23-11:

EXAMPLE OF FULL-BRIDGE PWM OUTPUT

Forward Mode

Period

(2)

PxA

Pulse Width

(2)

PxB

(2)

PxC

(2)

PxD

(1)

Reverse Mode

Period

Pulse Width

(2)

PxA

(2)

PxB

(2)

PxC

(2)

PxD

(1)

Note 1: At this time, the TMRx register is equal to the PRx register.

2: Output signal is shown as active-high.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 219

PIC16F/LF1826/27

The Full-Bridge mode does not provide dead-band

delay. As one output is modulated at a time, dead-band

delay is generally not required. There is a situation

where dead-band delay is required. This situation

occurs when both of the following conditions are true:

23.4.2.1

Direction Change in Full-Bridge

Mode

In the Full-Bridge mode, the PxM1 bit in the CCPxCON

register allows users to control the forward/reverse

direction. When the application firmware changes this

direction control bit, the module will change to the new

direction on the next PWM cycle.

1. The direction of the PWM output changes when

the duty cycle of the output is at or near 100%.

2. The turn off time of the power switch, including

the power device and driver circuit, is greater

than the turn on time.

A direction change is initiated in software by changing

the PxM1 bit of the CCPxCON register. The following

sequence occurs four Timer cycles prior to the end of

the current PWM period:

Figure 23-13 shows an example of the PWM direction

changing from forward to reverse, at a near 100% duty

cycle. In this example, at time t1, the output PxA and

PxD become inactive, while output PxC becomes

active. Since the turn off time of the power devices is

longer than the turn on time, a shoot-through current

will flow through power devices QC and QD (see

Figure 23-10) for the duration of ‘t’. The same

phenomenon will occur to power devices QA and QB

for PWM direction change from reverse to forward.

• The modulated outputs (PxB and PxD) are placed

in their inactive state.

• The associated unmodulated outputs (PxA and

PxC) are switched to drive in the opposite

direction.

• PWM modulation resumes at the beginning of the

next period.

See Figure 23-13 for an illustration of this sequence.

If changing PWM direction at high duty cycle is required

for an application, two possible solutions for eliminating

the shoot-through current are:

1. Reduce PWM duty cycle for one PWM period

before changing directions.

2. Use switch drivers that can drive the switches off

faster than they can drive them on.

Other options to prevent shoot-through current may

exist.

FIGURE 23-12:

EXAMPLE OF PWM DIRECTION CHANGE

(1)

Period

Signal

PxA (Active-High)

PxB (Active-High)

Pulse Width

PxC (Active-High)

PxD (Active-High)

(2)

Pulse Width

Note 1: The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle.

2: When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The

modulated PxB and PxD signals are inactive at this time. The length of this time is four Timer counts.

DS41391C-page 220

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 23-13:

EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE

Forward Period

Reverse Period

t1

PxA

PxB

PW

PxC

PxD

PW

TON

External Switch C

External Switch D

TOFF

Potential

T = TOFF – TON

Shoot-Through Current

Note 1: All signals are shown as active-high.

2: TON is the turn on delay of power switch QC and its driver.

3: TOFF is the turn off delay of power switch QD and its driver.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 221

PIC16F/LF1826/27

23.4.3

ENHANCED PWM

AUTO-SHUTDOWN MODE

Note 1: The auto-shutdown condition is

a

The PWM mode supports an Auto-Shutdown mode that

will disable the PWM outputs when an external

shutdown event occurs. Auto-Shutdown mode places

the PWM output pins into a predetermined state. This

mode is used to help prevent the PWM from damaging

the application.

level-based signal, not an edge-based

signal. As long as the level is present, the

auto-shutdown will persist.

2: Writing to the CCPxASE bit of the

CCPxAS register is disabled while an

auto-shutdown condition persists.

The auto-shutdown sources are selected using the

CCPxAS<2:0> bits of the CCPxAS register. A shutdown

event may be generated by:

3: Once the auto-shutdown condition has

been removed and the PWM restarted

(either through firmware or auto-restart)

the PWM signal will always restart at the

beginning of the next PWM period.

• A logic ‘0’ on the INT pin

• A logic ‘1’ on a Comparator (Cx) output

4: Prior to an auto-shutdown event caused

by a comparator output or INT pin event,

a software shutdown can be triggered in

firmware by setting the CCPxASE bit of

the CCPxAS register to ‘1’. The

Auto-Restart feature tracks the active

A shutdown condition is indicated by the CCPxASE

(Auto-Shutdown Event Status) bit of the CCPxAS

register. If the bit is a ‘0’, the PWM pins are operating

normally. If the bit is a ‘1’, the PWM outputs are in the

shutdown state.

When a shutdown event occurs, two things happen:

status of

a shutdown caused by a

The CCPxASE bit is set to ‘1’. The CCPxASE will

remain set until cleared in firmware or an auto-restart

occurs (see Section 12.4.4 “Auto-Restart Mode”).

comparator output or INT pin event only. If

it is enabled at this time, it will immediately

clear this bit and restart the ECCP module

at the beginning of the next PWM period.

The enabled PWM pins are asynchronously placed in

their shutdown states. The PWM output pins are

grouped into pairs [PxA/PxC] and [PxB/PxD]. The state

of each pin pair is determined by the PSSxAC and

PSSxBD bits of the CCPxAS register. Each pin pair may

be placed into one of three states:

• Drive logic ‘1’

• Drive logic ‘0’

• Tri-state (high-impedance)

FIGURE 23-14:

PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PXRSEN = 0)

Missing Pulse

(Auto-Shutdown)

Missing Pulse

(CCPxASE not clear)

Timer

Overflow

Timer

Overflow

Timer

Overflow

Timer

Overflow

Timer

Overflow

PWM Period

PWM Activity

Start of

PWM Period

Shutdown Event

CCPxASE bit

PWM

Resumes

Shutdown

Event Occurs

Shutdown

Event Clears

CCPxASE

Cleared by

Firmware

DS41391C-page 222

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

If auto-restart is enabled, the CCPxASE bit will remain

set as long as the auto-shutdown condition is active.

When the auto-shutdown condition is removed, the

CCPxASE bit will be cleared via hardware and normal

operation will resume.

23.4.4

AUTO-RESTART MODE

The Enhanced PWM can be configured to automati-

cally restart the PWM signal once the auto-shutdown

condition has been removed. Auto-restart is enabled by

setting the PxRSEN bit in the PWMxCON register.

FIGURE 23-15:

PWM AUTO-SHUTDOWN WITH AUTO-RESTART (PXRSEN = 1)

Missing Pulse

(Auto-Shutdown)

Missing Pulse

(CCPxASE not clear)

Timer

Overflow

Timer

Overflow

Timer

Overflow

Timer

Overflow

Timer

Overflow

PWM Period

PWM Activity

Start of

PWM Period

Shutdown Event

CCPxASE bit

PWM

Resumes

Shutdown

Event Occurs

Shutdown

Event Clears

CCPxASE

Cleared by

Hardware

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 223

PIC16F/LF1826/27

23.4.5

PROGRAMMABLE DEAD-BAND

DELAY MODE

FIGURE 23-16:

EXAMPLE OF

HALF-BRIDGE PWM

OUTPUT

In Half-Bridge applications where all power switches

are modulated at the PWM frequency, the power

switches normally require more time to turn off than to

turn on. If both the upper and lower power switches are

switched at the same time (one turned on, and the

other turned off), both switches may be on for a short

period of time until one switch completely turns off.

Period

Pulse Width

(2)

PxA

td

During this brief interval,

a very high current

PxB

(shoot-through current) will flow through both power

switches, shorting the bridge supply. To avoid this

potentially destructive shoot-through current from

flowing during switching, turning on either of the power

switches is normally delayed to allow the other switch

to completely turn off.

(1)

td = Dead-Band Delay

Note 1: At this time, the TMRx register is equal to the

PRx register.

In Half-Bridge mode,

a

digitally programmable

2: Output signals are shown as active-high.

dead-band delay is available to avoid shoot-through

current from destroying the bridge power switches. The

delay occurs at the signal transition from the non-active

state to the active state. See Figure 23-16 for

illustration. The lower seven bits of the associated

PWMxCON register (Figure 23-4) sets the delay period

in terms of microcontroller instruction cycles (TCY or 4

TOSC).

FIGURE 23-17:

EXAMPLE OF HALF-BRIDGE APPLICATIONS

V+

Standard Half-Bridge Circuit (“Push-Pull”)

FET

Driver

+

V

-

PxA

Load

FET

Driver

+

V

-

PxB

V-

DS41391C-page 224

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

23.4.6

PWM STEERING MODE

In Single Output mode, PWM steering allows any of the

PWM pins to be the modulated signal. Additionally, the

same PWM signal can be simultaneously available on

multiple pins.

Once the Single Output mode is selected

(CCPxM<3:2> = 11 and PxM<1:0> = 00 of the

CCPxCON register), the user firmware can bring out

the same PWM signal to one, two, three or four output

pins by setting the appropriate STRx<D:A> bits of the

PSTRxCON register, as shown in Register 23-5.

Note:

The associated TRIS bits must be set to

output (‘0’) to enable the pin output driver

in order to see the PWM signal on the pin.

While the PWM Steering mode is active, CCPxM<1:0>

bits of the CCPxCON register select the PWM output

polarity for the Px<D:A> pins.

The PWM auto-shutdown operation also applies to

PWM Steering mode as described in Section 12.4.3

“Enhanced PWM Auto-shutdown mode”. An

auto-shutdown event will only affect pins that have

PWM outputs enabled.

FIGURE 23-18:

SIMPLIFIED STEERING

BLOCK DIAGRAM

STRxA

PxA Signal

CCPxM1

PxA pin

1

PORT Data

STRxB

0

TRIS

PxB pin

CCPxM0

1

PORT Data

STRxC

0

TRIS

PxC pin

1

CCPxM1

PORT Data

0

TRIS

STRxD

PxD pin

1

CCPxM0

PORT Data

0

TRIS

Note 1: Port outputs are configured as shown when

the CCPxCON register bits PxM<1:0> = 00

and CCPxM<3:2> = 11.

2: Single PWM output requires setting at least

one of the STRx bits.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 225

PIC16F/LF1826/27

configuration while the PWM pin output drivers are

enable is not recommended since it may result in

damage to the application circuits.

23.4.6.1

Steering Synchronization

The STRxSYNC bit of the PSTRxCON register gives

the user two selections of when the steering event will

happen. When the STRxSYNC bit is ‘0’, the steering

event will happen at the end of the instruction that

writes to the PSTRxCON register. In this case, the

output signal at the Px<D:A> pins may be an

incomplete PWM waveform. This operation is useful

when the user firmware needs to immediately remove

a PWM signal from the pin.

The PxA, PxB, PxC and PxD output latches may not be

in the proper states when the PWM module is

initialized. Enabling the PWM pin output drivers at the

same time as the Enhanced PWM modes may cause

damage to the application circuit. The Enhanced PWM

modes must be enabled in the proper Output mode and

complete a full PWM cycle before enabling the PWM

pin output drivers. The completion of a full PWM cycle

is indicated by the TMRxIF bit of the PIRx register

being set as the second PWM period begins.

When the STRxSYNC bit is ‘1’, the effective steering

update will happen at the beginning of the next PWM

period. In this case, steering on/off the PWM output will

always produce a complete PWM waveform.

Note:

When the microcontroller is released from

Reset, all of the I/O pins are in the

high-impedance state. The external cir-

cuits must keep the power switch devices

in the Off state until the microcontroller

drives the I/O pins with the proper signal

levels or activates the PWM output(s).

Figures 12-19 and 12-20 illustrate the timing diagrams

of the PWM steering depending on the STRxSYNC

setting.

23.4.7

START-UP CONSIDERATIONS

When any PWM mode is used, the application

hardware must use the proper external pull-up and/or

pull-down resistors on the PWM output pins.

23.4.8

ALTERNATE PIN LOCATIONS

This module incorporates I/O pins that can be moved to

other locations with the use of the alternate pin function

registers, APFCON0 and APFCON1. To determine

which pins can be moved and what their default loca-

tions are upon a Reset, see Section 12.1 “Alternate

Pin Function” for more information.

The CCPxM<1:0> bits of the CCPxCON register allow

the user to choose whether the PWM output signals are

active-high or active-low for each pair of PWM output

pins (PxA/PxC and PxB/PxD). The PWM output

polarities must be selected before the PWM pin output

drivers are enabled. Changing the polarity

FIGURE 23-19:

EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRxSYNC = 0)

PWM Period

PWM

STRx

P1<D:A>

PORT Data

P1n = PWM

FIGURE 23-20:

EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION

(STRxSYNC = 1)

PWM

STRx

P1<D:A>

PORT Data

P1n = PWM

DS41391C-page 226

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 23-10: SUMMARY OF REGISTERS ASSOCIATED WITH ENHANCED PWM

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(2)

APFCON0

CCPxCON

CCPxAS

CCPTMRS

INTCON

PIE1

RXDTSEL SDO1SEL

SS1SEL

P2BSEL

CCP2SEL

P1DSEL

P1CSEL

CCP1SEL

122

228

230

229

91

(1)

PxM<1:0>

DCxB<1:0>

CCPxM<3:0>

PSSxBD<1:0>

C1TSEL<1:0>

CCPxASE

CCPxAS<2:0>

PSSxAC<1:0>

C2TSEL<1:0>

C4TSEL<1:0>

C3TSEL<1:0>

GIE

TMR1GIE

OSFIE

—

PEIE

ADIE

C2IE

—

TMR0IE

RCIE

INTE

TXIE

EEIE

IOCIE

TMR0IF

CCP1IE

—

INTF

IOCIF

TMR1IE

CCP2IE

—

SSPIE

BCLIE

TMR2IE

—

92

PIE2

C1IE

93

PIE3

CCP4IE

RCIF

CCP3IE

TXIF

TMR6IE

SSPIF

—

TMR4IE

TMR2IF

—

94

PIR1

TMR1GIF

OSFIF

—

ADIF

C2IF

—

CCP1IF

—

TMR1IF

CCP2IF

—

96

PIR2

C1IF

EEIF

BCLIF

97

PIR3

CCP4IF

CCP3IF

TMR6IF

—

TMR4IF

98

PR2

191*

Timer2 Period Register

PR4

Timer4 Module Period Register

Timer6 Module Period Register

191*

232

231

PR6

PSTRxCON

PWMxCON

T2CON

T4CON

T6CON

TMR2

—

PxRSEN

—

STRxSYNC

STRxD

STRxC

STRxB

STRxA

PxDC<6:0>

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON

T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON

T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON

T2CKPS1 T2CKPS0

T4CKPS1 T4CKPS0

T6CKPS1 T6CKPS0

193

—

193

—

193

Holding Register for the 8-bit TMR2 Time Base

Holding Register for the 8-bit TMR4 Time Base

Holding Register for the 8-bit TMR6 Time Base

191*

124

(1)

TMR4

TMR6

TRISA

TRISB

TRISA7

TRISB7

TRISA6

TRISB6

TRISA5

TRISB5

TRISA4

TRISB4

TRISA3

TRISB3

TRISA2

TRISB2

TRISA1

TRISB1

TRISA0

TRISB0

129

Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.

Page provides register information.

*

Note 1: Applies to ECCP modules only.

2: PIC16F/LF1827 only.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 227

PIC16F/LF1826/27

REGISTER 23-1: CCPxCON: CCPx CONTROL REGISTER

R/W-00

PxM<1:0>

R/W-0/0

(1)

R/W-0/0

DCxB<1:0>

CCPxM<3:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Reset

(1)

bit 7-6

PxM<1:0>: Enhanced PWM Output Configuration bits

Capture mode:

Unused

Compare mode:

Unused

If CCPxM<3:2> = 00, 01, 10:

xx= PxA assigned as Capture/Compare input; PxB, PxC, PxD assigned as port pins

If CCPxM<3:2> = 11:

00= Single output; PxA modulated; PxB, PxC, PxD assigned as port pins

01= Full-Bridge output forward; PxD modulated; PxA active; PxB, PxC inactive

10= Half-Bridge output; PxA, PxB modulated with dead-band control; PxC, PxD assigned as port pins

11= Full-Bridge output reverse; PxB modulated; PxC active; PxA, PxD inactive

bit 5-4

DCxB<1:0>: PWM Duty Cycle Least Significant bits

Capture mode:

Unused

Compare mode:

Unused

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.

bit 3-0

CCPxM<3:0>: ECCPx Mode Select bits

0000= Capture/Compare/PWM off (resets ECCPx module)

0001= Reserved

0010= Compare mode: toggle output on match

0011= Reserved

0100= Capture mode: every falling edge

0101= Capture mode: every rising edge

0110= Capture mode: every 4th rising edge

0111= Capture mode: every 16th rising edge

1000= Compare mode: initialize ECCPx pin low; set output on compare match (set CCPxIF)

1001= Compare mode: initialize ECCPx pin high; clear output on compare match (set CCPxIF)

1010= Compare mode: generate software interrupt only; ECCPx pin reverts to I/O state

1011= Compare mode: Special Event Trigger (ECCPx resets TMR1 or TMR3, sets CCPxIF bit, ECCP2 trigger

(1)

also starts A/D conversion if A/D module is enabled)

CCP Modules only:

11xx= PWM mode

ECCP Modules only:

1100= PWM mode: PxA, PxC active-high; PxB, PxD active-high

1101= PWM mode: PxA, PxC active-high; PxB, PxD active-low

1110= PWM mode: PxA, PxC active-low; PxB, PxD active-high

1111= PWM mode: PxA, PxC active-low; PxB, PxD active-low

Note 1: These bits are not implemented on CCP<4:3>.

DS41391C-page 228

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

REGISTER 23-2: CCPTMRS: PWM TIMER SELECTION CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0>

R/W-0/0

bit 0

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-4

bit 3-2

bit 1-0

C4TSEL<1:0>: CCP4 Timer Selection

00= CCP4 is based off Timer 2 in PWM Mode

01= CCP4 is based off Timer 4 in PWM Mode

10= CCP4 is based off Timer 6 in PWM Mode

11= Reserved

C3TSEL<1:0>: CCP3 Timer Selection

00= CCP3 is based off Timer 2 in PWM Mode

01= CCP3 is based off Timer 4 in PWM Mode

10= CCP3 is based off Timer 6 in PWM Mode

11= Reserved

C2TSEL<1:0>: CCP2 Timer Selection

00= CCP2 is based off Timer 2 in PWM Mode

01= CCP2 is based off Timer 4 in PWM Mode

10= CCP2 is based off Timer 6 in PWM Mode

11= Reserved

C1TSEL<1:0>: CCP1 Timer Selection

00= CCP1 is based off Timer 2 in PWM Mode

01= CCP1 is based off Timer 4 in PWM Mode

10= CCP1 is based off Timer 6 in PWM Mode

11= Reserved

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 229

PIC16F/LF1826/27

REGISTER 23-3: CCPxAS: CCPx AUTO-SHUTDOWN CONTROL REGISTER

R/W-0/0

CCPxASE

CCPxAS<2:0>

PSSxAC<1:0>

PSSxBD<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

CCPxASE: CCPx Auto-Shutdown Event Status bit

1= A shutdown event has occurred; CCPx outputs are in shutdown state

0= CCPx outputs are operating

bit 6-4

CCxPAS<2:0>: CCPx Auto-Shutdown Source Select bits

000= Auto-shutdown is disabled

001= Comparator C1 output high⁽¹⁾

010= Comparator C2 output high⁽¹⁾

011= Either Comparator C1 or C2 high⁽¹⁾

100= VIL on INT pin

101= VIL on INT pin or Comparator C1 high⁽¹⁾

110= VIL on INT pin or Comparator C2 high⁽¹⁾

111= VIL on INT pin or Comparator C1 or Comparator C2 high⁽¹⁾

bit 3-2

bit 1-0

PSSxAC<1:0>: Pins PxA and PxC Shutdown State Control bits

00= Drive pins PxA and PxC to ‘0’

01= Drive pins PxA and PxC to ‘1’

1x= Pins PxA and PxC tri-state

PSSxBD<1:0>: Pins PxB and PxD Shutdown State Control bits

00= Drive pins PxB and PxD to ‘0’

01= Drive pins PxB and PxD to ‘1’

1x= Pins PxB and PxD tri-state

Note 1: If CxSYNC is enabled, the shutdown will be delayed by Timer1.

DS41391C-page 230

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

REGISTER 23-4: PWMxCON: ENHANCED PWM CONTROL REGISTER

R/W-0/0

PxRSEN

R/W-0/0

bit 0

PxDC<6:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

PxRSEN: PWM Restart Enable bit

1= Upon auto-shutdown, the CCPxASE bit clears automatically once the shutdown event goes away;

the PWM restarts automatically

0= Upon auto-shutdown, CCPxASE must be cleared in software to restart the PWM

bit 6-0

PxDC<6:0>: PWM Delay Count bits

PxDCx = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal

should transition active and the actual time it transitions active

Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe

mode is enabled.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 231

PIC16F/LF1826/27

REGISTER 23-5: PSTRxCON: PWM STEERING CONTROL REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

R/W-0/0

STRxD

R/W-0/0

STRxC

R/W-0/0

STRxB

R/W-1/1

STRxA

STRxSYNC

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-5

bit 4

Unimplemented: Read as ‘0’

STRxSYNC: Steering Sync bit

1= Output steering update occurs on next PWM period

0= Output steering update occurs at the beginning of the instruction cycle boundary

bit 3

bit 2

bit 1

bit 0

STRxD: Steering Enable bit D

1= PxD pin has the PWM waveform with polarity control from CCPxM<1:0>

0= PxD pin is assigned to port pin

STRxC: Steering Enable bit C

1= PxC pin has the PWM waveform with polarity control from CCPxM<1:0>

0= PxC pin is assigned to port pin

STRxB: Steering Enable bit B

1= PxB pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxB pin is assigned to port pin

STRxA: Steering Enable bit A

1= PxA pin has the PWM waveform with polarity control from CCPxM<1:0>

0= PxA pin is assigned to port pin

Note 1: The PWM Steering mode is available only when the CCPxCON register bits CCPxM<3:2> = 11and

PxM<1:0> = 00.

DS41391C-page 232

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

24.0 MASTER SYNCHRONOUS

SERIAL PORT (MSSP1 AND

MSSP2) MODULE

24.1 Master SSPx (MSSPx) Module

Overview

The Master Synchronous Serial Port (MSSPx) module

is a serial interface useful for communicating with other

peripheral or microcontroller devices. These peripheral

devices may be Serial EEPROMs, shift registers, dis-

play drivers, A/D converters, etc. The MSSPx module

can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I²C™)

The SPI interface supports the following modes and

features:

• Master mode

• Slave mode

• Clock Parity

• Slave Select Synchronization (Slave mode only)

• Daisy chain connection of slave devices

Figure 24-1 is a block diagram of the SPI interface

module.

FIGURE 24-1:

MSSPX BLOCK DIAGRAM (SPI MODE)

Data Bus

Read

Write

SSPxBUF Reg

SSPxSR Reg

SDIx

Shift

Clock

bit 0

SDOx

SSx

Control

Enable

SSx

2 (CKP, CKE)

Clock Select

Edge

Select

SSPxM<3:0>

4

TMR2 Output

(

)

2

SCKx

TOSC

Prescaler

4, 16, 64

Edge

Select

Baud Rate

Generator

(SSPxADD)

TRIS bit

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 233

PIC16F/LF1826/27

The I²C interface supports the following modes and

features:

The PIC16F1827 has two MSSP modules, MSSP1 and

MSSP2, each module operating independently from

the other.

• Master mode

• Slave mode

• Byte NACKing (Slave mode)

• Limited Multi-master support

• 7-bit and 10-bit addressing

• Start and Stop interrupts

• Interrupt masking

Note 1: In devices with more than one MSSP

module, it is very important to pay close

attention to SSPxCONx register names.

SSP1CON1 and SSP1CON2 registers

control different operational aspects of the

same module, while SSP1CON1 and

SSP2CON1 control the same features for

two different modules.

• Clock stretching

• Bus collision detection

• General call address matching

• Address masking

2: Throughout this section, generic refer-

ences to an MSSP module in any of its

operating modes may be interpreted as

being equally applicable to MSSP1 or

MSSP2. Register names, module I/O sig-

nals, and bit names may use the generic

designator ‘x’ to indicate the use of a

numeral to distinguish a particular module

when required.

• Address Hold and Data Hold modes

• Selectable SDAx hold times

Figure 24-2 is a block diagram of the I²C interface mod-

ule in Master mode. Figure 24-3 is a diagram of the I²C

interface module in Slave mode.

FIGURE 24-2:

MSSPX BLOCK DIAGRAM (I²C™ MASTER MODE)

Internal

data bus

[SSPxM 3:0]

Read

Write

SSPxBUF

SSPxSR

Baud rate

generator

(SSPxADD)

SDAx

Shift

Clock

SDAx in

MSb

LSb

Start bit, Stop bit,

Acknowledge

Generate (SSPxCON2)

SCLx

Start bit detect,

Stop bit detect

SCLx in

Bus Collision

Write collision detect

Clock arbitration

State counter for

Set/Reset: S, P, SSPxSTAT, WCOL, SSPxOV

Reset SEN, PEN (SSPxCON2)

Set SSPxIF, BCLxIF

end of XMIT/RCV

Address Match detect

DS41391C-page 234

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 24-3:

MSSPX BLOCK DIAGRAM (I²C™ SLAVE MODE)

Internal

Data Bus

Read

Write

SSPxBUF Reg

SSPxSR Reg

SCLx

SDAx

Shift

Clock

MSb

LSb

SSPxMSK Reg

Match Detect

SSPxADD Reg

Addr Match

Set, Reset

S, P bits

(SSPxSTAT Reg)

Start and

Stop bit Detect

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 235

PIC16F/LF1826/27

it's SDOx pin) and the slave device is reading this bit

and saving it as the LSb of its shift register, that the

slave device is also sending out the MSb from its shift

register (on its SDOx pin) and the master device is

reading this bit and saving it as the LSb of its shift

register.

24.2 SPI Mode Overview

The Serial Peripheral Interface (SPI) bus is

a

synchronous serial data communication bus that

operates in Full Duplex mode. Devices communicate in

a master/slave environment where the master device

initiates the communication.

A slave device is

After 8 bits have been shifted out, the master and slave

have exchanged register values.

controlled through a chip select known as Slave Select.

The SPI bus specifies four signal connections:

If there is more data to exchange, the shift registers are

loaded with new data and the process repeats itself.

• Serial Clock (SCKx)

• Serial Data Out (SDOx)

• Serial Data In (SDIx)

• Slave Select (SSx)

Whether the data is meaningful or not (dummy data),

depends on the application software. This leads to

three scenarios for data transmission:

Figure 24-1 shows the block diagram of the MSSPx

module when operating in SPI Mode.

• Master sends useful data and slave sends dummy

data.

• Master sends useful data and slave sends useful

data.

The SPI bus operates with a single master device and

one or more slave devices. When multiple slave

devices are used, an independent Slave Select con-

nection is required from the master device to each

slave device.

• Master sends dummy data and slave sends useful

data.

Transmissions may involve any number of clock

cycles. When there is no more data to be transmitted,

the master stops sending the clock signal and it dese-

lects the slave.

Figure 24-4 shows a typical connection between a

master device and multiple slave devices.

The master selects only one slave at a time. Most slave

devices have tri-state outputs so their output signal

appears disconnected from the bus when they are not

selected.

Every slave device connected to the bus that has not

been selected through its slave select line must disre-

gard the clock and transmission signals and must not

transmit out any data of its own.

Transmissions involve two shift registers, eight bits in

size, one in the master and one in the slave. With either

the master or the slave device, data is always shifted

out one bit at a time, with the Most Significant bit (MSb)

shifted out first. At the same time, a new Least

Significant bit (LSb) is shifted into the same register.

Figure 24-5 shows a typical connection between two

processors configured as master and slave devices.

Data is shifted out of both shift registers on the pro-

grammed clock edge and latched on the opposite edge

of the clock.

The master device transmits information out on its

SDOx output pin which is connected to, and received

by, the slave's SDIx input pin. The slave device trans-

mits information out on its SDOx output pin, which is

connected to, and received by, the master's SDIx input

pin.

To begin communication, the master device first sends

out the clock signal. Both the master and the slave

devices should be configured for the same clock polar-

ity.

The master device starts a transmission by sending out

the MSb from its shift register. The slave device reads

this bit from that same line and saves it into the LSb

position of its shift register.

During each SPI clock cycle, a full duplex data

transmission occurs. This means that while the master

device is sending out the MSb from its shift register (on

DS41391C-page 236

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 24-4:

SPI MASTER AND MULTIPLE SLAVE CONNECTION

SCKx

SDOx

SCKx

SDIx

SDOx

SSx

SPI Master

SPI Slave

#1

SDIx

General I/O

SCKx

SDIx

SDOx

SSx

SPI Slave

#2

SCKx

SDIx

SDOx

SSx

SPI Slave

#3

24.2.1 SPI MODE REGISTERS

The MSSPx module has five registers for SPI mode

operation. These are:

• MSSPx STATUS register (SSPxSTAT)

• MSSPx Control Register 1 (SSPxCON1)

• MSSPx Control Register 3 (SSPxCON3)

• MSSPx Data Buffer register (SSPxBUF)

• MSSPx Address register (SSPxADD)

• MSSPx Shift register (SSPxSR)

(Not directly accessible)

SSPxCON1 and SSPxSTAT are the control and STA-

TUS registers in SPI mode operation. The SSPxCON1

register is readable and writable. The lower 6 bits of

the SSPxSTAT are read-only. The upper two bits of the

SSPxSTAT are read/write.

In one SPI master mode, SSPxADD can be loaded

with a value used in the Baud Rate Generator. More

information on the Baud Rate Generator is available in

Section 24.7 “Baud Rate Generator”.

SSPxSR is the shift register used for shifting data in

and out. SSPxBUF provides indirect access to the

SSPxSR register. SSPxBUF is the buffer register to

which data bytes are written, and from which data

bytes are read.

In receive operations, SSPxSR and SSPxBUF

together create a buffered receiver. When SSPxSR

receives a complete byte, it is transferred to SSPxBUF

and the SSPxIF interrupt is set.

During transmission, the SSPxBUF is not buffered. A

write to SSPxBUF will write to both SSPxBUF and

SSPxSR.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 237

PIC16F/LF1826/27

24.2.2 SPI MODE OPERATION

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).

These control bits allow the following to be specified:

The MSSPx consists of a transmit/receive shift register

(SSPxSR) and a buffer register (SSPxBUF). The

SSPxSR shifts the data in and out of the device, MSb

first. The SSPxBUF holds the data that was written to

the SSPxSR until the received data is ready. Once the

8 bits of data have been received, that byte is moved to

the SSPxBUF register. Then, the Buffer Full Detect bit,

BF of the SSPxSTAT register, and the interrupt flag bit,

SSPxIF, are set. This double-buffering of the received

data (SSPxBUF) allows the next byte to start reception

before reading the data that was just received. Any

• Master mode (SCKx is the clock output)

• Slave mode (SCKx is the clock input)

• Clock Polarity (Idle state of SCKx)

• Data Input Sample Phase (middle or end of data

output time)

• Clock Edge (output data on rising/falling edge of

SCKx)

• Clock Rate (Master mode only)

write

to

the

SSPxBUF

register

during

• Slave Select mode (Slave mode only)

transmission/reception of data will be ignored and the

write collision detect bit WCOL of the SSPxCON1

register, will be set. User software must clear the

WCOL bit to allow the following write(s) to the

SSPxBUF register to complete successfully.

To enable the serial port, SSPx Enable bit, SSPxEN of

the SSPxCON1 register, must be set. To reset or recon-

figure SPI mode, clear the SSPxEN bit, re-initialize the

SSPxCONx registers and then set the SSPxEN bit.

This configures the SDIx, SDOx, SCKx and SSx pins

as serial port pins. For the pins to behave as the serial

port function, some must have their data direction bits

(in the TRIS register) appropriately programmed as fol-

lows:

When the application software is expecting to receive

valid data, the SSPxBUF should be read before the

next byte of data to transfer is written to the SSPxBUF.

The Buffer Full bit, BF of the SSPxSTAT register,

indicates when SSPxBUF has been loaded with the

received data (transmission is complete). When the

SSPxBUF is read, the BF bit is cleared. This data may

be irrelevant if the SPI is only a transmitter. Generally,

the MSSPx interrupt is used to determine when the

transmission/reception has completed. If the interrupt

method is not going to be used, then software polling

can be done to ensure that a write collision does not

occur.

• SDIx must have corresponding TRIS bit set

• SDOx must have corresponding TRIS bit cleared

• SCKx (Master mode) must have corresponding

TRIS bit cleared

• SCKx (Slave mode) must have corresponding

TRIS bit set

• SSx must have corresponding TRIS bit set

FIGURE 24-5:

SPI MASTER/SLAVE CONNECTION

SPI Master SSPxM<3:0> = 00xx

= 1010

SPI Slave SSPxM<3:0> = 010x

SDOx

SDIx

Serial Input Buffer

(SSPxBUF)

(BUF)

SDIx

SDOx

Shift Register

(SSPxSR)

Shift Register

(SSPxSR)

LSb

MSb

LSb

Serial Clock

SCKx

SSx

Slave Select

(optional)

General I/O

Processor 2

Processor 1

DS41391C-page 238

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

The clock polarity is selected by appropriately

programming the CKP bit of the SSPxCON1 register

and the CKE bit of the SSPxSTAT register. This then,

would give waveforms for SPI communication as

shown in Figure 24-6, Figure 24-8 and Figure 24-9,

where the MSB is transmitted first. In Master mode, the

SPI clock rate (bit rate) is user programmable to be one

of the following:

24.2.3

SPI MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCKx line. The master

determines when the slave (Processor 2, Figure 24-5)

is to broadcast data by the software protocol.

In Master mode, the data is transmitted/received as

soon as the SSPxBUF register is written to. If the SPI

is only going to receive, the SDOx output could be dis-

abled (programmed as an input). The SSPxSR register

will continue to shift in the signal present on the SDIx

pin at the programmed clock rate. As each byte is

received, it will be loaded into the SSPxBUF register as

if a normal received byte (interrupts and Status bits

appropriately set).

• FOSC/4 (or TCY)

• FOSC/16 (or 4 * TCY)

• FOSC/64 (or 16 * TCY)

• Timer2 output/2

• Fosc/(4 * (SSPxADD + 1))

Figure 24-6 shows the waveforms for Master mode.

When the CKE bit is set, the SDOx data is valid before

there is a clock edge on SCKx. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSPxBUF is loaded with the received

data is shown.

FIGURE 24-6:

SPI MODE WAVEFORM (MASTER MODE)

Write to

SSPxBUF

SCKx

(CKP = 0

CKE = 0)

SCKx

(CKP = 1

CKE = 0)

4 Clock

Modes

SCKx

(CKP = 0

CKE = 1)

SCKx

(CKP = 1

CKE = 1)

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

SDOx

(CKE = 0)

bit 7

bit 3

SDOx

(CKE = 1)

SDIx

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SDIx

(SMP = 1)

bit 0

bit 7

Input

Sample

(SMP = 1)

SSPxIF

SSPxSR to

SSPxBUF

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 239

PIC16F/LF1826/27

24.2.4

SPI SLAVE MODE

24.2.5

SLAVE SELECT

SYNCHRONIZATION

In Slave mode, the data is transmitted and received as

external clock pulses appear on SCKx. When the last

bit is latched, the SSPxIF interrupt flag bit is set.

The Slave Select can also be used to synchronize com-

munication. The Slave Select line is held high until the

master device is ready to communicate. When the

Slave Select line is pulled low, the slave knows that a

new transmission is starting.

Before enabling the module in SPI Slave mode, the clock

line must match the proper Idle state. The clock line can

be observed by reading the SCKx pin. The Idle state is

determined by the CKP bit of the SSPxCON1 register.

If the slave fails to receive the communication properly,

it will be reset at the end of the transmission, when the

Slave Select line returns to a high state. The slave is

then ready to receive a new transmission when the

Slave Select line is pulled low again. If the Slave Select

line is not used, there is a risk that the slave will even-

tually become out of sync with the master. If the slave

misses a bit, it will always be one bit off in future trans-

missions. Use of the Slave Select line allows the slave

and master to align themselves at the beginning of

each transmission.

While in Slave mode, the external clock is supplied by

the external clock source on the SCKx pin. This exter-

nal clock must meet the minimum high and low times

as specified in the electrical specifications.

While in Sleep mode, the slave can transmit/receive

data. The shift register is clocked from the SCKx pin

input and when a byte is received, the device will gen-

erate an interrupt. If enabled, the device will wake-up

from Sleep.

24.2.4.1 Daisy-Chain Configuration

The SSx pin allows a Synchronous Slave mode. The

SPI must be in Slave mode with SSx pin control

enabled (SSPxCON1<3:0> = 0100).

The SPI bus can sometimes be connected in a

daisy-chain configuration. The first slave output is con-

nected to the second slave input, the second slave

output is connected to the third slave input, and so on.

The final slave output is connected to the master input.

Each slave sends out, during a second group of clock

pulses, an exact copy of what was received during the

first group of clock pulses. The whole chain acts as

one large communication shift register. The

daisy-chain feature only requires a single Slave Select

line from the master device.

When the SSx pin is low, transmission and reception

are enabled and the SDOx pin is driven.

When the SSx pin goes high, the SDOx pin is no longer

driven, even if in the middle of a transmitted byte and

becomes a floating output. External pull-up/pull-down

resistors may be desirable depending on the applica-

tion.

Note 1: When the SPI is in Slave mode with SSx

pin control enabled (SSPxCON1<3:0> =

0100), the SPI module will reset if the SSx

pin is set to VDD.

Figure 24-7 shows the block diagram of a typical

Daisy-Chain connection when operating in SPI Mode.

In a daisy-chain configuration, only the most recent

byte on the bus is required by the slave. Setting the

BOEN bit of the SSPxCON3 register will enable writes

to the SSPxBUF register, even if the previous byte has

not been read. This allows the software to ignore data

that may not apply to it.

2: When the SPI is used in Slave mode with

CKE set; the user must enable SSx pin

control.

3: While operated in SPI Slave mode the

SMP bit of the SSPxSTAT register must

remain clear.

When the SPI module resets, the bit counter is forced

to ‘0’. This can be done by either forcing the SSx pin to

a high level or clearing the SSPxEN bit.

DS41391C-page 240

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 24-7:

SPI DAISY-CHAIN CONNECTION

SCK

SPI Master

SDOx

SDIx

SDOx

SSx

SPI Slave

#1

General I/O

SCK

SDIx

SDOx

SSx

SPI Slave

#2

SCK

SDIx

SDOx

SSx

SPI Slave

#3

FIGURE 24-8:

SLAVE SELECT SYNCHRONOUS WAVEFORM

SSx

SCKx

(CKP = 0

CKE = 0)

SCKx

(CKP = 1

CKE = 0)

Write to

SSPxBUF

Shift register SSPxSR

and bit count are reset

SSPxBUF to

SSPxSR

bit 6

bit 7

bit 0

SDOx

SDIx

bit 7

bit 0

bit 7

Input

Sample

SSPxIF

Interrupt

Flag

SSPxSR to

SSPxBUF

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 241

PIC16F/LF1826/27

FIGURE 24-9:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

SSx

Optional

SCKx

(CKP = 0

CKE = 0)

SCKx

(CKP = 1

CKE = 0)

Write to

SSPxBUF

Valid

bit 6

bit 2

bit 5

bit 4

bit 3

bit 1

bit 0

SDOx

bit 7

SDIx

bit 0

bit 7

Input

Sample

SSPxIF

Interrupt

Flag

SSPxSR to

SSPxBUF

Write Collision

detection active

FIGURE 24-10:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SSx

Not Optional

SCKx

(CKP = 0

CKE = 1)

SCKx

(CKP = 1

CKE = 1)

Write to

SSPxBUF

Valid

bit 6

bit 3

bit 2

bit 5

bit 4

bit 1

bit 0

SDOx

bit 7

SDIx

bit 0

Input

Sample

SSPxIF

Interrupt

Flag

SSPxSR to

SSPxBUF

Write Collision

detection active

DS41391C-page 242

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

24.2.6 SPI OPERATION IN SLEEP MODE

In SPI Master mode, when the Sleep mode is selected,

all module clocks are halted and the transmis-

sion/reception will remain in that state until the device

wakes. After the device returns to Run mode, the mod-

ule will resume transmitting and receiving data.

In SPI Master mode, module clocks may be operating

at a different speed than when in full power mode; in

the case of the Sleep mode, all clocks are halted.

Special care must be taken by the user when the

MSSPx clock is much faster than the system clock.

In SPI Slave mode, the SPI Transmit/Receive Shift

register operates asynchronously to the device. This

allows the device to be placed in Sleep mode and data

to be shifted into the SPI Transmit/Receive Shift

register. When all 8 bits have been received, the

MSSPx interrupt flag bit will be set and if enabled, will

wake the device.

In Slave mode, when MSSPx interrupts are enabled,

after the master completes sending data, an MSSPx

interrupt will wake the controller from Sleep.

If an exit from Sleep mode is not desired, MSSPx

interrupts should be disabled.

TABLE 24-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

APFCON0

ANSELA

ANSELB

INTCON

PIE1

RXDTSEL SDO1SEL

SS1SEL

—

P2BSEL

CCP2SEL

ANSA3

ANSB3

IOCIE

P1DSEL

ANSA2

ANSB2

TMR0IF

CCP1IE

CCP1IF

P1CSEL

ANSA1

ANSB1

INTF

CCP1SEL

ANSA0

—

122

125

130

91

—

ANSA4

ANSB4

INTE

ANSB7

GIE

ANSB6

PEIE

ADIE

ADIF

ANSB5

TMR0IE

RCIE

IOCIF

TMR1GIE

TMR1GIF

TXIE

SSP1IE

SSP1IF

TMR2IE

TMR2IF

TMR1IE

TMR1IF

92

PIR1

RCIF

TXIF

96

SSPxBUF

SSPxCON1

Synchronous Serial Port Receive Buffer/Transmit Register

237*

283

285

282

124

129

WCOL

SSPxOV

PCIE

SSPxEN

SCIE

CKP

SSPxM3

SSPxM2

SBCDE

SSPxM1

AHEN

SSPxM0

DHEN

SSPxCON3 ACKTIM

BOEN

SDAHT

SSPxSTAT

TRISA

SMP

CKE

D/A

P

S

R/W

UA

BF

TRISA7

TRISB7

TRISA6

TRISB6

TRISA5

TRISB5

TRISA4

TRISB4

TRISA3

TRISB3

TRISA2

TRISB2

TRISA1

TRISB1

TRISA0

TRISB0

TRISB

Legend:

— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSPx in SPI mode.

*

Page provides register information.

Note 1: PIC16F/LF1827 only.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 243

PIC16F/LF1826/27

I²C MASTER/

24.3 I²C MODE OVERVIEW

FIGURE 24-11:

SLAVE CONNECTION

The Inter-Integrated Circuit Bus (I²C) is a multi-master

serial data communication bus. Devices communicate

in a master/slave environment where the master

devices initiate the communication. A Slave device is

controlled through addressing.

VDD

SCLx

The I²C bus specifies two signal connections:

VDD

• Serial Clock (SCLx)

• Serial Data (SDAx)

Master

Slave

SDAx

Figure 24-11 shows the block diagram of the MSSPx

module when operating in I²C Mode.

Both the SCLx and SDAx connections are bidirectional

open-drain lines, each requiring pull-up resistors for the

supply voltage. Pulling the line to ground is considered

a logical zero and letting the line float is considered a

logical one.

The Acknowledge bit (ACK) is an active-low signal,

which holds the SDAx line low to indicate to the trans-

mitter that the slave device has received the transmit-

ted data and is ready to receive more.

Figure 24-11 shows a typical connection between two

processors configured as master and slave devices.

The I²C bus can operate with one or more master

devices and one or more slave devices.

The transition of a data bit is always performed while

the SCLx line is held low. Transitions that occur while

the SCLx line is held high are used to indicate Start and

Stop bits.

If the master intends to write to the slave, then it repeat-

edly sends out a byte of data, with the slave responding

after each byte with an ACK bit. In this example, the

master device is in Master Transmit mode and the

slave is in Slave Receive mode.

There are four potential modes of operation for a given

device:

• Master Transmit mode

(master is transmitting data to a slave)

• Master Receive mode

If the master intends to read from the slave, then it

repeatedly receives a byte of data from the slave, and

responds after each byte with an ACK bit. In this exam-

ple, the master device is in Master Receive mode and

the slave is Slave Transmit mode.

(master is receiving data from a slave)

• Slave Transmit mode

(slave is transmitting data to a master)

• Slave Receive mode

(slave is receiving data from the master)

On the last byte of data communicated, the master

device may end the transmission by sending a Stop bit.

If the master device is in Receive mode, it sends the

Stop bit in place of the last ACK bit. A Stop bit is indi-

cated by a low-to-high transition of the SDAx line while

the SCLx line is held high.

To begin communication, a master device starts out in

Master Transmit mode. The master device sends out a

Start bit followed by the address byte of the slave it

intends to communicate with. This is followed by a sin-

gle Read/Write bit, which determines whether the mas-

ter intends to transmit to or receive data from the slave

device.

In some cases, the master may want to maintain con-

trol of the bus and re-initiate another transmission. If

so, the master device may send another Start bit in

place of the Stop bit or last ACK bit when it is in receive

mode.

If the requested slave exists on the bus, it will respond

with an Acknowledge bit, otherwise known as an ACK.

The master then continues in either Transmit mode or

Receive mode and the slave continues in the comple-

ment, either in Receive mode or Transmit mode,

respectively.

The I²C bus specifies three message protocols;

• Single message where a master writes data to a

slave.

A Start bit is indicated by a high-to-low transition of the

SDAx line while the SCLx line is held high. Address and

data bytes are sent out, Most Significant bit (MSb) first.

The Read/Write bit is sent out as a logical one when the

master intends to read data from the slave, and is sent

out as a logical zero when it intends to write data to the

slave.

• Single message where a master reads data from

a slave.

• Combined message where a master initiates a

minimum of two writes, or two reads, or a

combination of writes and reads, to one or more

slaves.

DS41391C-page 244

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

When one device is transmitting a logical one, or letting

the line float, and a second device is transmitting a log-

ical zero, or holding the line low, the first device can

detect that the line is not a logical one. This detection,

when used on the SCLx line, is called clock stretching.

Clock stretching gives slave devices a mechanism to

control the flow of data. When this detection is used on

the SDAx line, it is called arbitration. Arbitration

ensures that there is only one master device communi-

cating at any single time.

24.3.2

ARBITRATION

Each master device must monitor the bus for Start and

Stop bits. If the device detects that the bus is busy, it

cannot begin a new message until the bus returns to an

Idle state.

However, two master devices may try to initiate a trans-

mission on or about the same time. When this occurs,

the process of arbitration begins. Each transmitter

checks the level of the SDAx data line and compares it

to the level that it expects to find. The first transmitter to

observe that the two levels don't match, loses arbitra-

tion, and must stop transmitting on the SDAx line.

24.3.1

CLOCK STRETCHING

When a slave device has not completed processing

data, it can delay the transfer of more data through the

process of Clock Stretching. An addressed slave

device may hold the SCLx clock line low after receiving

or sending a bit, indicating that it is not yet ready to con-

tinue. The master that is communicating with the slave

will attempt to raise the SCLx line in order to transfer

the next bit, but will detect that the clock line has not yet

been released. Because the SCLx connection is

open-drain, the slave has the ability to hold that line low

until it is ready to continue communicating.

For example, if one transmitter holds the SDAx line to

a logical one (lets it float) and a second transmitter

holds it to a logical zero (pulls it low), the result is that

the SDAx line will be low. The first transmitter then

observes that the level of the line is different than

expected and concludes that another transmitter is

communicating.

The first transmitter to notice this difference is the one

that loses arbitration and must stop driving the SDAx

line. If this transmitter is also a master device, it also

must stop driving the SCLx line. It then can monitor the

lines for a Stop condition before trying to reissue its

transmission. In the meantime, the other device that

has not noticed any difference between the expected

and actual levels on the SDAx line continues with it's

original transmission. It can do so without any compli-

cations, because so far, the transmission appears

exactly as expected with no other transmitter disturbing

the message.

Clock stretching allows receivers that cannot keep up

with a transmitter to control the flow of incoming data.

Slave Transmit mode can also be arbitrated, when a

master addresses multiple slaves, but this is less com-

mon.

If two master devices are sending a message to two dif-

ferent slave devices at the address stage, the master

sending the lower slave address always wins arbitra-

tion. When two master devices send messages to the

same slave address, and addresses can sometimes

refer to multiple slaves, the arbitration process must

continue into the data stage.

Arbitration usually occurs very rarely, but it is a neces-

sary process for proper multi-master support.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 245

PIC16F/LF1826/27

TABLE 24-2: I²C BUS TERMS

24.4 I²C MODE OPERATION

TERM

Description

All MSSPx I²C communication is byte oriented and

shifted out MSb first. Six SFR registers and 2 interrupt

flags interface the module with the PIC^®microcon-

troller and user software. Two pins, SDAx and SCLx,

are exercised by the module to communicate with

other external I²C devices.

Transmitter

The device which shifts data out

onto the bus.

Receiver

Master

The device which shifts data in

from the bus.

The device that initiates a transfer,

generates clock signals and termi-

nates a transfer.

24.4.1 BYTE FORMAT

All communication in I²C is done in 9-bit segments. A

byte is sent from a Master to a Slave or vice-versa, fol-

lowed by an Acknowledge bit sent back. After the 8th

falling edge of the SCLx line, the device outputting

data on the SDAx changes that pin to an input and

reads in an acknowledge value on the next clock

pulse.

Slave

The device addressed by the mas-

ter.

Multi-master

Arbitration

A bus with more than one device

that can initiate data transfers.

Procedure to ensure that only one

master at a time controls the bus.

Winning arbitration ensures that

the message is not corrupted.

The clock signal, SCLx, is provided by the master.

Data is valid to change while the SCLx signal is low,

and sampled on the rising edge of the clock. Changes

on the SDAx line while the SCLx line is high define

special conditions on the bus, explained below.

Synchronization Procedure to synchronize the

clocks of two or more devices on

the bus.

Idle

No master is controlling the bus,

and both SDAx and SCLx lines are

high.

24.4.2 DEFINITION OF I²C TERMINOLOGY

There is language and terminology in the description

of I²C communication that have definitions specific to

I²C. That word usage is defined below and may be

used in the rest of this document without explana-

tion. This table was adapted from the Phillips I²C

specification.

Active

Any time one or more master

devices are controlling the bus.

Addressed

Slave

Slave device that has received a

matching address and is actively

being clocked by a master.

Matching

Address

Address byte that is clocked into a

slave that matches the value

stored in SSPxADD.

24.4.3 SDAX AND SCLX PINS

Selection of any I²C mode with the SSPxEN bit set,

forces the SCLx and SDAx pins to be open-drain.

These pins should be set by the user to inputs by set-

ting the appropriate TRIS bits.

Write Request

Read Request

Slave receives a matching

address with R/W bit clear, and is

ready to clock in data.

Master sends an address byte with

the R/W bit set, indicating that it

wishes to clock data out of the

Slave. This data is the next and all

following bytes until a Restart or

Stop.

Note: Data is tied to output zero when an I²C mode

is enabled.

24.4.4 SDAX HOLD TIME

The hold time of the SDAx pin is selected by the

SDAHT bit of the SSPxCON3 register. Hold time is the

time SDAx is held valid after the falling edge of SCLx.

Setting the SDAHT bit selects a longer 300 ns mini-

mum hold time and may help on buses with large

capacitance.

Clock Stretching When a device on the bus hold

SCLx low to stall communication.

Bus Collision

Any time the SDAx line is sampled

low by the module while it is out-

putting and expected high state.

DS41391C-page 246

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

24.4.5 START CONDITION

24.4.7 RESTART CONDITION

The I²C specification defines a Start condition as a

transition of SDAx from a high to a low state while

SCLx line is high. A Start condition is always gener-

ated by the master and signifies the transition of the

bus from an Idle to an Active state. Figure 24-10

shows wave forms for Start and Stop conditions.

A Restart is valid any time that a Stop would be valid.

A master can issue a Restart if it wishes to hold the

bus after terminating the current transfer. A Restart

has the same effect on the slave that a Start would,

resetting all slave logic and preparing it to clock in an

address. The master may want to address the same or

another slave.

A bus collision can occur on a Start condition if the

module samples the SDAx line low before asserting it

low. This does not conform to the I²C Specification that

states no bus collision can occur on a Start.

In 10-bit Addressing Slave mode a Restart is required

for the master to clock data out of the addressed

slave. Once a slave has been fully addressed, match-

ing both high and low address bytes, the master can

issue a Restart and the high address byte with the

R/W bit set. The slave logic will then hold the clock

and prepare to clock out data.

24.4.6 STOP CONDITION

A Stop condition is a transition of the SDAx line from

low-to-high state while the SCLx line is high.

After a full match with R/W clear in 10-bit mode, a prior

match flag is set and maintained. Until a Stop condi-

tion, a high address with R/W clear, or high address

match fails.

Note: At least one SCLx low time must appear

before a Stop is valid, therefore, if the SDAx

line goes low then high again while the SCLx

line stays high, only the Start condition is

detected.

24.4.8 START/STOP CONDITION INTERRUPT

MASKING

The SCIE and PCIE bits of the SSPxCON3 register

can enable the generation of an interrupt in Slave

modes that do not typically support this function. Slave

modes where interrupt on Start and Stop detect are

already enabled, these bits will have no effect.

FIGURE 24-12:

I²C START AND STOP CONDITIONS

SDAx

SCLx

S

P

Change of

Data Allowed

Stop

Start

Condition

FIGURE 24-13:

I²C RESTART CONDITION

Sr

Change of

Data Allowed

Restart

Condition

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 247

PIC16F/LF1826/27

24.5 I²C SLAVE MODE OPERATION

24.4.9 ACKNOWLEDGE SEQUENCE

The 9th SCLx pulse for any transferred byte in I²C is

dedicated as an Acknowledge. It allows receiving

devices to respond back to the transmitter by pulling

the SDAx line low. The transmitter must release con-

trol of the line during this time to shift in the response.

The Acknowledge (ACK) is an active-low signal, pull-

ing the SDAx line low indicated to the transmitter that

the device has received the transmitted data and is

ready to receive more.

The MSSPx Slave mode operates in one of four

modes selected in the SSPxM bits of SSPxCON1 reg-

ister. The modes can be divided into 7-bit and 10-bit

Addressing mode. 10-bit Addressing modes operate

the same as 7-bit with some additional overhead for

handling the larger addresses.

Modes with Start and Stop bit interrupts operated the

same as the other modes with SSPxIF additionally

getting set upon detection of a Start, Restart, or Stop

condition.

The result of an ACK is placed in the ACKSTAT bit of

the SSPxCON2 register.

24.5.1 SLAVE MODE ADDRESSES

Slave software, when the AHEN and DHEN bits are

set, allow the user to set the ACK value sent back to

the transmitter. The ACKDT bit of the SSPxCON2 reg-

ister is set/cleared to determine the response.

The SSPxADD register (Register 24-6) contains the

Slave mode address. The first byte received after a

Start or Restart condition is compared against the

value stored in this register. If the byte matches, the

value is loaded into the SSPxBUF register and an

interrupt is generated. If the value does not match, the

module goes idle and no indication is given to the soft-

ware that anything happened.

Slave hardware will generate an ACK response if the

AHEN and DHEN bits of the SSPxCON3 register are

clear.

There are certain conditions where an ACK will not be

sent by the slave. If the BF bit of the SSPxSTAT regis-

ter or the SSPxOV bit of the SSPxCON1 register are

set when a byte is received.

The SSPx Mask register (Register 24-5) affects the

address matching process. See Section 24.5.9

“SSPx Mask Register” for more information.

When the module is addressed, after the 8th falling

edge of SCLx on the bus, the ACKTIM bit of the

SSPxCON3 register is set. The ACKTIM bit indicates

the acknowledge time of the active bus. The ACKTIM

Status bit is only active when the AHEN bit or DHEN

bit is enabled.

24.5.1.1 I²C Slave 7-bit Addressing Mode

In 7-bit Addressing mode, the LSb of the received data

byte is ignored when determining if there is an address

match.

24.5.1.2 I²C Slave 10-bit Addressing Mode

In 10-bit Addressing mode, the first received byte is

compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9

and A8 are the two MSb of the 10-bit address and

stored in bits 2 and 1 of the SSPxADD register.

After the acknowledge of the high byte the UA bit is set

and SCLx is held low until the user updates SSPxADD

with the low address. The low address byte is clocked

in and all 8 bits are compared to the low address value

in SSPxADD. Even if there is not an address match;

SSPxIF and UA are set, and SCLx is held low until

SSPxADD is updated to receive a high byte again.

When SSPxADD is updated the UA bit is cleared. This

ensures the module is ready to receive the high

address byte on the next communication.

A high and low address match as a write request is

required at the start of all 10-bit addressing communi-

cation. A transmission can be initiated by issuing a

Restart once the slave is addressed, and clocking in

the high address with the R/W bit set. The slave hard-

ware will then acknowledge the read request and pre-

pare to clock out data. This is only valid for a slave

after it has received a complete high and low address

byte match.

DS41391C-page 248

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

24.5.2 SLAVE RECEPTION

24.5.2.2 7-bit Reception with AHEN and DHEN

When the R/W bit of a matching received address byte

is clear, the R/W bit of the SSPxSTAT register is

cleared. The received address is loaded into the SSPx-

BUF register and acknowledged.

Slave device reception with AHEN and DHEN set

operate the same as without these options with extra

interrupts and clock stretching added after the 8th fall-

ing edge of SCLx. These additional interrupts allow the

slave software to decide whether it wants to ACK the

receive address or data byte, rather than the hard-

ware. This functionality adds support for PMBus™ that

was not present on previous versions of this module.

When the overflow condition exists for a received

address, then not Acknowledge is given. An overflow

condition is defined as either bit BF bit of the SSPx-

STAT register is set, or bit SSPxOV bit of the

SSPxCON1 register is set. The BOEN bit of the

SSPxCON3 register modifies this operation. For more

information see Register 24-4.

This list describes the steps that need to be taken by

slave software to use these options for I²C communi-

cation. Figure 24-15 displays a module using both

address and data holding. Figure 24-16 includes the

operation with the SEN bit of the SSPxCON2 register

set.

An MSSPx interrupt is generated for each transferred

data byte. Flag bit, SSPxIF, must be cleared by soft-

ware.

1. S bit of SSPxSTAT is set; SSPxIF is set if inter-

rupt on Start detect is enabled.

When the SEN bit of the SSPxCON2 register is set,

SCLx will be held low (clock stretch) following each

received byte. The clock must be released by setting

the CKP bit of the SSPxCON1 register, except

sometimes in 10-bit mode. See Section 24.2.3 “SPI

Master Mode” for more detail.

2. Matching address with R/W bit clear is clocked

in. SSPxIF is set and CKP cleared after the 8th

falling edge of SCLx.

3. Slave clears the SSPxIF.

4. Slave can look at the ACKTIM bit of the

SSPxCON3 register to determine if the SSPxIF

was after or before the ACK.

24.5.2.1 7-bit Addressing Reception

This section describes a standard sequence of events

for the MSSPx module configured as an I²C Slave in

7-bit Addressing mode. All decisions made by hard-

ware or software and their effect on reception.

Figure 24-13 and Figure 24-14 is used as a visual

reference for this description.

5. Slave reads the address value from SSPxBUF,

clearing the BF flag.

6. Slave sets ACK value clocked out to the master

by setting ACKDT.

7. Slave releases the clock by setting CKP.

This is a step by step process of what typically must

be done to accomplish I²C communication.

8. SSPxIF is set after an ACK, not after a NACK.

9. If SEN = 1 the slave hardware will stretch the

1. Start bit detected.

clock after the ACK.

2. S bit of SSPxSTAT is set; SSPxIF is set if inter-

rupt on Start detect is enabled.

10. Slave clears SSPxIF.

Note: SSPxIF is still set after the 9th falling edge of

SCLx even if there is no clock stretching and

BF has been cleared. Only if NACK is sent to

Master is SSPxIF not set

3. Matching address with R/W bit clear is received.

4. The slave pulls SDAx low sending an ACK to the

master, and sets SSPxIF bit.

5. Software clears the SSPxIF bit.

11. SSPxIF set and CKP cleared after 8th falling

edge of SCLx for a received data byte.

6. Software reads received address from SSPx-

BUF clearing the BF flag.

12. Slave looks at ACKTIM bit of SSPxCON3 to

determine the source of the interrupt.

7. If SEN = 1; Slave software sets CKP bit to

release the SCLx line.

13. Slave reads the received data from SSPxBUF

clearing BF.

8. The master clocks out a data byte.

9. Slave drives SDAx low sending an ACK to the

master, and sets SSPxIF bit.

14. Steps 7-14 are the same for each received data

byte.

10. Software clears SSPxIF.

15. Communication is ended by either the slave

sending an ACK = 1, or the master sending a

Stop condition. If a Stop is sent and Interrupt on

Stop Detect is disabled, the slave will only know

by polling the P bit of the SSTSTAT register.

11. Software reads the received byte from SSPx-

BUF clearing BF.

12. Steps 8-12 are repeated for all received bytes

from the Master.

13. Master sends Stop condition, setting P bit of

SSPxSTAT, and the bus goes idle.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 249

PIC16F/LF1826/27

FIGURE 24-14:

I²C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)

DS41391C-page 250

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 24-15:

I²C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 251

PIC16F/LF1826/27

FIGURE 24-16:

I²C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)

DS41391C-page 252

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 24-17:

I²C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 253

PIC16F/LF1826/27

24.5.3

SLAVE TRANSMISSION

24.5.3.2

7-bit Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPxSTAT register is set. The received address is

loaded into the SSPxBUF register, and an ACK pulse is

sent by the slave on the ninth bit.

A master device can transmit a read request to a

slave, and then clock data out of the slave. The list

below outlines what software for a slave will need to

do to accomplish

a

standard transmission.

Figure 24-17 can be used as a reference to this list.

Following the ACK, slave hardware clears the CKP bit

and the SCLx pin is held low (see Section 24.5.6

“Clock Stretching” for more detail). By stretching the

clock, the master will be unable to assert another clock

pulse until the slave is done preparing the transmit

data.

1. Master sends a Start condition on SDAx and

SCLx.

2. S bit of SSPxSTAT is set; SSPxIF is set if inter-

rupt on Start detect is enabled.

3. Matching address with R/W bit set is received by

the Slave setting SSPxIF bit.

The transmit data must be loaded into the SSPxBUF

register which also loads the SSPxSR register. Then

the SCLx pin should be released by setting the CKP bit

of the SSPxCON1 register. The eight data bits are

shifted out on the falling edge of the SCLx input. This

ensures that the SDAx signal is valid during the SCLx

high time.

4. Slave hardware generates an ACK and sets

SSPxIF.

5. SSPxIF bit is cleared by user.

6. Software reads the received address from

SSPxBUF, clearing BF.

7. R/W is set so CKP was automatically cleared

after the ACK.

The ACK pulse from the master-receiver is latched on

the rising edge of the ninth SCLx input pulse. This ACK

value is copied to the ACKSTAT bit of the SSPxCON2

register. If ACKSTAT is set (not ACK), then the data

transfer is complete. In this case, when the not ACK is

latched by the slave, the slave goes idle and waits for

another occurrence of the Start bit. If the SDAx line was

low (ACK), the next transmit data must be loaded into

the SSPxBUF register. Again, the SCLx pin must be

released by setting bit CKP.

8. The slave software loads the transmit data into

SSPxBUF.

9. CKP bit is set releasing SCLx, allowing the mas-

ter to clock the data out of the slave.

10. SSPxIF is set after the ACK response from the

master is loaded into the ACKSTAT register.

11. SSPxIF bit is cleared.

12. The slave software checks the ACKSTAT bit to

see if the master wants to clock out more data.

An MSSPx interrupt is generated for each data transfer

byte. The SSPxIF bit must be cleared by software and

the SSPxSTAT register is used to determine the status

of the byte. The SSPxIF bit is set on the falling edge of

the ninth clock pulse.

Note 1: If the master ACKs the clock will be

stretched.

2: ACKSTAT is the only bit updated on the

rising edge of SCLx (9th) rather than the

falling.

24.5.3.1

Slave Mode Bus Collision

13. Steps 9-13 are repeated for each transmitted

byte.

A slave receives a Read request and begins shifting

data out on the SDAx line. If a bus collision is detected

and the SBCDE bit of the SSPxCON3 register is set,

the BCLxIF bit of the PIRx register is set. Once a bus

collision is detected, the slave goes Idle and waits to be

addressed again. User software can use the BCLxIF bit

to handle a slave bus collision.

14. If the master sends a not ACK; the clock is not

held, but SSPxIF is still set.

15. The master sends a Restart condition or a Stop.

16. The slave is no longer addressed.

DS41391C-page 254

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 24-18:

I²C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 255

PIC16F/LF1826/27

24.5.3.3

7-bit Transmission with Address

Hold Enabled

Setting the AHEN bit of the SSPxCON3 register

enables additional clock stretching and interrupt gen-

eration after the 8th falling edge of a received match-

ing address. Once a matching address has been

clocked in, CKP is cleared and the SSPxIF interrupt is

set.

Figure 24-18 displays a standard waveform of a 7-bit

Address Slave Transmission with AHEN enabled.

1. Bus starts Idle.

2. Master sends Start condition; the S bit of SSPx-

STAT is set; SSPxIF is set if interrupt on Start

detect is enabled.

3. Master sends matching address with R/W bit

set. After the 8th falling edge of the SCLx line the

CKP bit is cleared and SSPxIF interrupt is gen-

erated.

4. Slave software clears SSPxIF.

5. Slave software reads ACKTIM bit of SSPxCON3

register, and R/W and D/A of the SSPxSTAT

register to determine the source of the interrupt.

6. Slave reads the address value from the SSPx-

BUF register clearing the BF bit.

7. Slave software decides from this information if it

wishes to ACK or not ACK and sets ACKDT bit

of the SSPxCON2 register accordingly.

8. Slave sets the CKP bit releasing SCLx.

9. Master clocks in the ACK value from the slave.

10. Slave hardware automatically clears the CKP bit

and sets SSPxIF after the ACK if the R/W bit is

set.

11. Slave software clears SSPxIF.

12. Slave loads value to transmit to the master into

SSPxBUF setting the BF bit.

Note: SSPxBUF cannot be loaded until after the

ACK.

13. Slave sets CKP bit releasing the clock.

14. Master clocks out the data from the slave and

sends an ACK value on the 9th SCLx pulse.

15. Slave hardware copies the ACK value into the

ACKSTAT bit of the SSPxCON2 register.

16. Steps 10-15 are repeated for each byte transmit-

ted to the master from the slave.

17. If the master sends a not ACK the slave

releases the bus allowing the master to send a

Stop and end the communication.

Note: Master must send a not ACK on the last byte

to ensure that the slave releases the SCLx

line to receive a Stop.

DS41391C-page 256

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 24-19:

I²C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 257

PIC16F/LF1826/27

24.5.4 SLAVE MODE 10-BIT ADDRESS

RECEPTION

24.5.5 10-BIT ADDRESSING WITH ADDRESS OR

DATA HOLD

This section describes a standard sequence of events

for the MSSPx module configured as an I²C Slave in

10-bit Addressing mode.

Reception using 10-bit addressing with AHEN or

DHEN set is the same as with 7-bit modes. The only

difference is the need to update the SSPxADD register

using the UA bit. All functionality, specifically when the

CKP bit is cleared and SCLx line is held low are the

same. Figure 24-20 can be used as a reference of a

slave in 10-bit addressing with AHEN set.

Figure 24-19 is used as a visual reference for this

description.

This is a step by step process of what must be done by

slave software to accomplish I²C communication.

Figure 24-21 shows a standard waveform for a slave

transmitter in 10-bit Addressing mode.

1. Bus starts Idle.

2. Master sends Start condition; S bit of SSPxSTAT

is set; SSPxIF is set if interrupt on Start detect is

enabled.

3. Master sends matching high address with R/W

bit clear; UA bit of the SSPxSTAT register is set.

4. Slave sends ACK and SSPxIF is set.

5. Software clears the SSPxIF bit.

6. Software reads received address from

SSPxBUF clearing the BF flag.

7. Slave loads low address into SSPxADD,

releasing SCLx.

8. Master sends matching low address byte to the

Slave; UA bit is set.

Note: Updates to the SSPxADD register are not

allowed until after the ACK sequence.

9. Slave sends ACK and SSPxIF is set.

Note: If the low address does not match, SSPxIF

and UA are still set so that the slave software

can set SSPxADD back to the high address.

BF is not set because there is no match.

CKP is unaffected.

10. Slave clears SSPxIF.

11. Slave reads the received matching address

from SSPxBUF clearing BF.

12. Slave loads high address into SSPxADD.

13. Master clocks a data byte to the slave and

clocks out the slaves ACK on the 9th SCLx

pulse; SSPxIF is set.

14. If SEN bit of SSPxCON2 is set, CKP is cleared

by hardware and the clock is stretched.

15. Slave clears SSPxIF.

16. Slave reads the received byte from SSPxBUF

clearing BF.

17. If SEN is set the slave sets CKP to release the

SCLx.

18. Steps 13-17 repeat for each received byte.

19. Master sends Stop to end the transmission.

DS41391C-page 258

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 24-20:

I²C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 259

PIC16F/LF1826/27

FIGURE 24-21:

I²C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)

DS41391C-page 260

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 24-22:

I²C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 261

PIC16F/LF1826/27

24.5.6 CLOCK STRETCHING

24.5.6.2 10-bit Addressing Mode

Clock stretching occurs when a device on the bus

holds the SCLx line low effectively pausing communi-

cation. The slave may stretch the clock to allow more

time to handle data or prepare a response for the mas-

ter device. A master device is not concerned with

stretching as anytime it is active on the bus and not

transferring data it is stretching. Any stretching done

by a slave is invisible to the master software and han-

dled by the hardware that generates SCLx.

In 10-bit Addressing mode, when the UA bit is set, the

clock is always stretched. This is the only time the

SCLx is stretched without CKP being cleared. SCLx is

released immediately after a write to SSPxADD.

Note: Previous versions of the module did not

stretch the clock if the second address byte

did not match.

24.5.6.3 Byte NACKing

The CKP bit of the SSPxCON1 register is used to con-

trol stretching in software. Any time the CKP bit is

cleared, the module will wait for the SCLx line to go

low and then hold it. Setting CKP will release SCLx

and allow more communication.

When AHEN bit of SSPxCON3 is set; CKP is cleared

by hardware after the 8th falling edge of SCLx for a

received matching address byte. When DHEN bit of

SSPxCON3 is set; CKP is cleared after the 8th falling

edge of SCLx for received data.

24.5.6.1 Normal Clock Stretching

Stretching after the 8th falling edge of SCLx allows the

slave to look at the received address or data and

decide if it wants to ACK the received data.

Following an ACK if the R/W bit of SSPxSTAT is set, a

read request, the slave hardware will clear CKP. This

allows the slave time to update SSPxBUF with data to

transfer to the master. If the SEN bit of SSPxCON2 is

set, the slave hardware will always stretch the clock

after the ACK sequence. Once the slave is ready; CKP

is set by software and communication resumes.

24.5.7 CLOCK SYNCHRONIZATION AND

THE CKP BIT

Any time the CKP bit is cleared, the module will wait

for the SCLx line to go low and then hold it. However,

clearing the CKP bit will not assert the SCLx output

low until the SCLx output is already sampled low.

Therefore, the CKP bit will not assert the SCLx line

until an external I²C master device has already

asserted the SCLx line. The SCLx output will remain

low until the CKP bit is set and all other devices on the

I²C bus have released SCLx. This ensures that a write

to the CKP bit will not violate the minimum high time

requirement for SCLx (see Figure 24-22).

Note 1: The BF bit has no effect on if the clock will

be stretched or not. This is different than

previous versions of the module that

would not stretch the clock, clear CKP, if

SSPxBUF was read before the 9th falling

edge of SCLx.

2: Previous versions of the module did not

stretch the clock for a transmission if

SSPxBUF was loaded before the 9th fall-

ing edge of SCLx. It is now always cleared

for read requests.

FIGURE 24-23:

CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDAx

SCLx

DX

DX ‚ – 1

Master device

asserts clock

CKP

Master device

releases clock

WR

SSPxCON1

DS41391C-page 262

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

24.5.8 GENERAL CALL ADDRESS SUPPORT

In 10-bit Address mode, the UA bit will not be set on

the reception of the general call address. The slave

will prepare to receive the second byte as data, just as

it would in 7-bit mode.

The addressing procedure for the I²C bus is such that

the first byte after the Start condition usually deter-

mines which device will be the slave addressed by the

master device. The exception is the general call

address which can address all devices. When this

address is used, all devices should, in theory, respond

with an acknowledge.

If the AHEN bit of the SSPxCON3 register is set, just

as with any other address reception, the slave hard-

ware will stretch the clock after the 8th falling edge of

SCLx. The slave must then set its ACKDT value and

release the clock with communication progressing as it

would normally.

The general call address is a reserved address in the

I²C protocol, defined as address 0x00. When the

GCEN bit of the SSPxCON2 register is set, the slave

module will automatically ACK the reception of this

address regardless of the value stored in SSPxADD.

After the slave clocks in an address of all zeros with

the R/W bit clear, an interrupt is generated and slave

software can read SSPxBUF and respond.

Figure 24-23 shows

sequence.

a

general call reception

FIGURE 24-24:

SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

Address is compared to General Call Address

after ACK, set interrupt

Receiving Data

D5 D4 D3 D2 D1

ACK

R/W = 0

ACK

General Call Address

SDAx

D7 D6

D0

8

SCLx

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

9

S

SSPxIF

BF (SSPxSTAT<0>)

Cleared by software

SSPxBUF is read

GCEN (SSPxCON2<7>)

’1’

24.5.9 SSPX MASK REGISTER

An SSPx Mask (SSPxMSK) register (Register 24-5) is

available in I²C Slave mode as a mask for the value

held in the SSPxSR register during an address

comparison operation. A zero (‘0’) bit in the SSPxMSK

register has the effect of making the corresponding bit

of the received address a “don’t care”.

This register is reset to all ‘1’s upon any Reset

condition and, therefore, has no effect on standard

SSPx operation until written with a mask value.

The SSPx Mask register is active during:

• 7-bit Address mode: address compare of A<7:1>.

• 10-bit Address mode: address compare of A<7:0>

only. The SSPx mask has no effect during the

reception of the first (high) byte of the address.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 263

PIC16F/LF1826/27

24.6.1 I²C MASTER MODE OPERATION

2

24.6 I C MASTER MODE

The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the beginning of the next serial transfer, the I²C bus will

not be released.

Master mode is enabled by setting and clearing the

appropriate SSPxM bits in the SSPxCON1 register and

by setting the SSPxEN bit. In Master mode, the SCLx

and SDAx lines are set as inputs and are manipulated

by the MSSPx hardware.

Master mode of operation is supported by interrupt

generation on the detection of the Start and Stop con-

ditions. The Stop (P) and Start (S) bits are cleared from

a Reset or when the MSSPx module is disabled. Con-

trol of the I²C bus may be taken when the P bit is set,

or the bus is Idle.

In Master Transmitter mode, serial data is output

through SDAx, while SCLx outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the Read/Write (R/W) bit.

In this case, the R/W bit will be logic ‘0’. Serial data is

transmitted 8 bits at a time. After each byte is transmit-

ted, an Acknowledge bit is received. Start and Stop

conditions are output to indicate the beginning and the

end of a serial transfer.

In Firmware Controlled Master mode, user code

conducts all I²C bus operations based on Start and

Stop bit condition detection. Start and Stop condition

detection is the only active circuitry in this mode. All

other communication is done by the user software

directly manipulating the SDAx and SCLx lines.

In Master Receive mode, the first byte transmitted con-

tains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case, the R/W bit will be

logic ‘1’. Thus, the first byte transmitted is a 7-bit slave

address followed by a ‘1’ to indicate the receive bit.

Serial data is received via SDAx, while SCLx outputs

the serial clock. Serial data is received 8 bits at a time.

After each byte is received, an Acknowledge bit is

transmitted. Start and Stop conditions indicate the

beginning and end of transmission.

The following events will cause the SSPx Interrupt Flag

bit, SSPxIF, to be set (SSPx interrupt, if enabled):

• Start condition detected

• Stop condition detected

• Data transfer byte transmitted/received

• Acknowledge transmitted/received

• Repeated Start generated

A Baud Rate Generator is used to set the clock fre-

quency output on SCLx. See Section 24.7 “Baud

Rate Generator” for more detail.

Note 1: The MSSPx module, when configured in

I²C Master mode, does not allow queue-

ing of events. For instance, the user is not

allowed to initiate a Start condition and

immediately write the SSPxBUF register

to initiate transmission before the Start

condition is complete. In this case, the

SSPxBUF will not be written to and the

WCOL bit will be set, indicating that a write

to the SSPxBUF did not occur

2: When in Master mode, Start/Stop detec-

tion is masked and an interrupt is gener-

ated when the SEN/PEN bit is cleared and

the generation is complete.

DS41391C-page 264

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

24.6.2 CLOCK ARBITRATION

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,

releases the SCLx pin (SCLx allowed to float high).

When the SCLx pin is allowed to float high, the Baud

Rate Generator (BRG) is suspended from counting

until the SCLx pin is actually sampled high. When the

SCLx pin is sampled high, the Baud Rate Generator is

reloaded with the contents of SSPxADD<7:0> and

begins counting. This ensures that the SCLx high time

will always be at least one BRG rollover count in the

event that the clock is held low by an external device

(Figure 24-25).

FIGURE 24-25:

BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDAx

DX

DX ‚ – 1

SCLx deasserted but slave holds

SCLx low (clock arbitration)

SCLx allowed to transition high

SCLx

BRG decrements on

Q2 and Q4 cycles

BRG

Value

03h

02h

01h

00h (hold off)

03h

02h

SCLx is sampled high, reload takes

place and BRG starts its count

BRG

Reload

24.6.3 WCOL STATUS FLAG

If the user writes the SSPxBUF when a Start, Restart,

Stop, Receive or Transmit sequence is in progress, the

WCOL is set and the contents of the buffer are

unchanged (the write doesn’t occur). Any time the

WCOL bit is set it indicates that an action on SSPxBUF

was attempted while the module was not Idle.

Note:

Because queueing of events is not

allowed, writing to the lower 5 bits of

SSPxCON2 is disabled until the Start

condition is complete.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 265

PIC16F/LF1826/27

2

24.6.4 I C MASTER MODE START

by hardware; the Baud Rate Generator is suspended,

leaving the SDAx line held low and the Start condition

is complete.

CONDITION TIMING

To initiate a Start condition, the user sets the Start

Enable bit, SEN bit of the SSPxCON2 register. If the

SDAx and SCLx pins are sampled high, the Baud Rate

Generator is reloaded with the contents of SSPx-

ADD<7:0> and starts its count. If SCLx and SDAx are

both sampled high when the Baud Rate Generator

times out (TBRG), the SDAx pin is driven low. The

action of the SDAx being driven low while SCLx is high

is the Start condition and causes the S bit of the

SSPxSTAT1 register to be set. Following this, the

Baud Rate Generator is reloaded with the contents of

SSPxADD<7:0> and resumes its count. When the

Baud Rate Generator times out (TBRG), the SEN bit of

the SSPxCON2 register will be automatically cleared

Note 1: If at the beginning of the Start condition,

the SDAx and SCLx pins are already sam-

pled low, or if during the Start condition,

the SCLx line is sampled low before the

SDAx line is driven low, a bus collision

occurs, the Bus Collision Interrupt Flag,

BCLxIF, is set, the Start condition is

aborted and the I²C module is reset into its

Idle state.

2: The Philips I²C Specification states that a

bus collision cannot occur on a Start.

FIGURE 24-26:

FIRST START BIT TIMING

Set S bit (SSPxSTAT<3>)

Write to SEN bit occurs here

At completion of Start bit,

hardware clears SEN bit

and sets SSPxIF bit

SDAx = 1,

SCLx = 1

TBRG

Write to SSPxBUF occurs here

SDAx

2nd bit

1st bit

TBRG

SCLx

S

TBRG

DS41391C-page 266

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

2

24.6.5 I C MASTER MODE REPEATED

SSPxCON2 register will be automatically cleared and

the Baud Rate Generator will not be reloaded, leaving

the SDAx pin held low. As soon as a Start condition is

detected on the SDAx and SCLx pins, the S bit of the

SSPxSTAT register will be set. The SSPxIF bit will not

be set until the Baud Rate Generator has timed out.

START CONDITION TIMING

A Repeated Start condition occurs when the RSEN bit

of the SSPxCON2 register is programmed high and the

Master state machine is no longer active. When the

RSEN bit is set, the SCLx pin is asserted low. When the

SCLx pin is sampled low, the Baud Rate Generator is

loaded and begins counting. The SDAx pin is released

(brought high) for one Baud Rate Generator count

(TBRG). When the Baud Rate Generator times out, if

SDAx is sampled high, the SCLx pin will be deasserted

(brought high). When SCLx is sampled high, the Baud

Rate Generator is reloaded and begins counting. SDAx

and SCLx must be sampled high for one TBRG. This

action is then followed by assertion of the SDAx pin

(SDAx = 0) for one TBRG while SCLx is high. SCLx is

asserted low. Following this, the RSEN bit of the

Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.

2: A bus collision during the Repeated Start

condition occurs if:

•

SDAx is sampled low when SCLx

goes from low-to-high.

•

SCLx goes low before SDAx is

asserted low. This may indicate that

another master is attempting to

transmit a data ‘1’.

FIGURE 24-27:

REPEAT START CONDITION WAVEFORM

S bit set by hardware

Write to SSPxCON2

occurs here

SDAx = 1,

At completion of Start bit,

hardware clears RSEN bit

and sets SSPxIF

SDAx = 1,

SCLx = 1

SCLx (no change)

TBRG

1st bit

SDAx

SCLx

Write to SSPxBUF occurs here

TBRG

Sr

Repeated Start

TBRG

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 267

PIC16F/LF1826/27

24.6.6 I²C MASTER MODE TRANSMISSION

24.6.6.3

ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit of the SSPxCON2

register is cleared when the slave has sent an Acknowl-

edge (ACK = 0) and is set when the slave does not

Acknowledge (ACK = 1). A slave sends an Acknowl-

edge when it has recognized its address (including a

general call), or when the slave has properly received

its data.

Transmission of a data byte, a 7-bit address or the

other half of a 10-bit address is accomplished by simply

writing a value to the SSPxBUF register. This action will

set the Buffer Full flag bit, BF and allow the Baud Rate

Generator to begin counting and start the next trans-

mission. Each bit of address/data will be shifted out

onto the SDAx pin after the falling edge of SCLx is

asserted. SCLx is held low for one Baud Rate Genera-

tor rollover count (TBRG). Data should be valid before

SCLx is released high. When the SCLx pin is released

high, it is held that way for TBRG. The data on the SDAx

pin must remain stable for that duration and some hold

time after the next falling edge of SCLx. After the eighth

bit is shifted out (the falling edge of the eighth clock),

the BF flag is cleared and the master releases SDAx.

This allows the slave device being addressed to

respond with an ACK bit during the ninth bit time if an

address match occurred, or if data was received prop-

erly. The status of ACK is written into the ACKSTAT bit

on the rising edge of the ninth clock. If the master

receives an Acknowledge, the Acknowledge Status bit,

ACKSTAT, is cleared. If not, the bit is set. After the ninth

clock, the SSPxIF bit is set and the master clock (Baud

Rate Generator) is suspended until the next data byte

is loaded into the SSPxBUF, leaving SCLx low and

SDAx unchanged (Figure 24-27).

24.6.6.4 Typical transmit sequence:

1. The user generates a Start condition by setting

the SEN bit of the SSPxCON2 register.

2. SSPxIF is set by hardware on completion of the

Start.

3. SSPxIF is cleared by software.

4. The MSSPx module will wait the required start

time before any other operation takes place.

5. The user loads the SSPxBUF with the slave

address to transmit.

6. Address is shifted out the SDAx pin until all 8 bits

are transmitted. Transmission begins as soon

as SSPxBUF is written to.

7. The MSSPx module shifts in the ACK bit from

the slave device and writes its value into the

ACKSTAT bit of the SSPxCON2 register.

8. The MSSPx module generates an interrupt at

the end of the ninth clock cycle by setting the

SSPxIF bit.

After the write to the SSPxBUF, each bit of the address

will be shifted out on the falling edge of SCLx until all

seven address bits and the R/W bit are completed. On

the falling edge of the eighth clock, the master will

release the SDAx pin, allowing the slave to respond

with an Acknowledge. On the falling edge of the ninth

clock, the master will sample the SDAx pin to see if the

address was recognized by a slave. The status of the

ACK bit is loaded into the ACKSTAT Status bit of the

SSPxCON2 register. Following the falling edge of the

ninth clock transmission of the address, the SSPxIF is

set, the BF flag is cleared and the Baud Rate Generator

is turned off until another write to the SSPxBUF takes

place, holding SCLx low and allowing SDAx to float.

9. The user loads the SSPxBUF with eight bits of

data.

10. Data is shifted out the SDAx pin until all 8 bits

are transmitted.

11. The MSSPx module shifts in the ACK bit from

the slave device and writes its value into the

ACKSTAT bit of the SSPxCON2 register.

12. Steps 8-11 are repeated for all transmitted data

bytes.

13. The user generates a Stop or Restart condition

by setting the PEN or RSEN bits of the

SSPxCON2 register. Interrupt is generated once

the Stop/Restart condition is complete.

24.6.6.1

BF Status Flag

In Transmit mode, the BF bit of the SSPxSTAT register

is set when the CPU writes to SSPxBUF and is cleared

when all 8 bits are shifted out.

24.6.6.2

WCOL Status Flag

If the user writes the SSPxBUF when a transmit is

already in progress (i.e., SSPxSR is still shifting out a

data byte), the WCOL is set and the contents of the buf-

fer are unchanged (the write doesn’t occur).

WCOL must be cleared by software before the next

transmission.

DS41391C-page 268

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

2

FIGURE 24-28:

I C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 269

PIC16F/LF1826/27

I²C MASTER MODE RECEPTION

24.6.7.4 Typical Receive Sequence:

24.6.7

Master mode reception is enabled by programming the

Receive Enable bit, RCEN bit of the SSPxCON2

register.

1. The user generates a Start condition by setting

the SEN bit of the SSPxCON2 register.

2. SSPxIF is set by hardware on completion of the

Start.

Note:

The MSSPx module must be in an Idle

state before the RCEN bit is set or the

RCEN bit will be disregarded.

3. SSPxIF is cleared by software.

4. User writes SSPxBUF with the slave address to

transmit and the R/W bit set.

The Baud Rate Generator begins counting and on each

rollover, the state of the SCLx pin changes

(high-to-low/low-to-high) and data is shifted into the

SSPxSR. After the falling edge of the eighth clock, the

receive enable flag is automatically cleared, the con-

tents of the SSPxSR are loaded into the SSPxBUF, the

BF flag bit is set, the SSPxIF flag bit is set and the Baud

Rate Generator is suspended from counting, holding

SCLx low. The MSSPx is now in Idle state awaiting the

next command. When the buffer is read by the CPU,

the BF flag bit is automatically cleared. The user can

then send an Acknowledge bit at the end of reception

by setting the Acknowledge Sequence Enable, ACKEN

bit of the SSPxCON2 register.

5. Address is shifted out the SDAx pin until all 8 bits

are transmitted. Transmission begins as soon

as SSPxBUF is written to.

6. The MSSPx module shifts in the ACK bit from

the slave device and writes its value into the

ACKSTAT bit of the SSPxCON2 register.

7. The MSSPx module generates an interrupt at

the end of the ninth clock cycle by setting the

SSPxIF bit.

8. User sets the RCEN bit of the SSPxCON2 regis-

ter and the Master clocks in a byte from the slave.

9. After the 8th falling edge of SCLx, SSPxIF and

BF are set.

10. Master clears SSPxIF and reads the received

byte from SSPxUF, clears BF.

24.6.7.1

BF Status Flag

In receive operation, the BF bit is set when an address

or data byte is loaded into SSPxBUF from SSPxSR. It

is cleared when the SSPxBUF register is read.

11. Master sets ACK value sent to slave in ACKDT

bit of the SSPxCON2 register and initiates the

ACK by setting the ACKEN bit.

24.6.7.2

SSPxOV Status Flag

12. Masters ACK is clocked out to the Slave and

SSPxIF is set.

In receive operation, the SSPxOV bit is set when 8 bits

are received into the SSPxSR and the BF flag bit is

already set from a previous reception.

13. User clears SSPxIF.

14. Steps 8-13 are repeated for each received byte

from the slave.

24.6.7.3

WCOL Status Flag

15. Master sends a not ACK or Stop to end

communication.

If the user writes the SSPxBUF when a receive is

already in progress (i.e., SSPxSR is still shifting in a

data byte), the WCOL bit is set and the contents of the

buffer are unchanged (the write doesn’t occur).

DS41391C-page 270

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

2

FIGURE 24-29:

I C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 271

PIC16F/LF1826/27

24.6.8

ACKNOWLEDGE SEQUENCE

TIMING

24.6.9

STOP CONDITION TIMING

A Stop bit is asserted on the SDAx pin at the end of a

receive/transmit by setting the Stop Sequence Enable

bit, PEN bit of the SSPxCON2 register. At the end of a

receive/transmit, the SCLx line is held low after the

falling edge of the ninth clock. When the PEN bit is set,

the master will assert the SDAx line low. When the

SDAx line is sampled low, the Baud Rate Generator is

reloaded and counts down to ‘0’. When the Baud Rate

Generator times out, the SCLx pin will be brought high

and one TBRG (Baud Rate Generator rollover count)

later, the SDAx pin will be deasserted. When the SDAx

pin is sampled high while SCLx is high, the P bit of the

SSPxSTAT register is set. A TBRG later, the PEN bit is

cleared and the SSPxIF bit is set (Figure 24-30).

An Acknowledge sequence is enabled by setting the

Acknowledge Sequence Enable bit, ACKEN bit of the

SSPxCON2 register. When this bit is set, the SCLx pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDAx pin. If the user wishes to

generate an Acknowledge, then the ACKDT bit should

be cleared. If not, the user should set the ACKDT bit

before starting an Acknowledge sequence. The Baud

Rate Generator then counts for one rollover period

(TBRG) and the SCLx pin is deasserted (pulled high).

When the SCLx pin is sampled high (clock arbitration),

the Baud Rate Generator counts for TBRG. The SCLx pin

is then pulled low. Following this, the ACKEN bit is auto-

matically cleared, the Baud Rate Generator is turned off

and the MSSPx module then goes into Idle mode

(Figure 24-29).

24.6.9.1

WCOL Status Flag

If the user writes the SSPxBUF when a Stop sequence

is in progress, then the WCOL bit is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

24.6.8.1

WCOL Status Flag

If the user writes the SSPxBUF when an Acknowledge

sequence is in progress, then WCOL is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

FIGURE 24-30:

ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here,

write to SSPxCON2

ACKEN automatically cleared

ACKEN = 1, ACKDT = 0

TBRG

ACK

TBRG

SDAx

SCLx

D0

8

9

SSPxIF

Cleared in

SSPxIF set at

the end of receive

software

Cleared in

software

SSPxIF set at the end

of Acknowledge sequence

Note: TBRG = one Baud Rate Generator period.

DS41391C-page 272

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 24-31:

STOP CONDITION RECEIVE OR TRANSMIT MODE

SCLx = 1for TBRG, followed by SDAx = 1for TBRG

after SDAx sampled high. P bit (SSPxSTAT<4>) is set.

Write to SSPxCON2,

set PEN

PEN bit (SSPxCON2<2>) is cleared by

hardware and the SSPxIF bit is set

Falling edge of

9th clock

TBRG

SCLx

ACK

SDAx

P

TBRG

SCLx brought high after TBRG

SDAx asserted low before rising edge of clock

to setup Stop condition

Note: TBRG = one Baud Rate Generator period.

24.6.10 SLEEP OPERATION

24.6.13 MULTI -MASTER COMMUNICATION,

BUS COLLISION AND BUS

While in Sleep mode, the I²C slave module can receive

addresses or data and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if the MSSPx interrupt is enabled).

ARBITRATION

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDAx pin, arbitration takes place when the master

outputs a ‘1’ on SDAx, by letting SDAx float high and

another master asserts a ‘0’. When the SCLx pin floats

high, data should be stable. If the expected data on

SDAx is a ‘1’ and the data sampled on the SDAx pin is

‘0’, then a bus collision has taken place. The master will

set the Bus Collision Interrupt Flag, BCLxIF and reset

the I²C port to its Idle state (Figure 24-31).

24.6.11 EFFECTS OF A RESET

A Reset disables the MSSPx module and terminates

the current transfer.

24.6.12 MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the

MSSPx module is disabled. Control of the I²C bus may

be taken when the P bit of the SSPxSTAT register is

set, or the bus is Idle, with both the S and P bits clear.

When the bus is busy, enabling the SSPx interrupt will

generate the interrupt when the Stop condition occurs.

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDAx and SCLx lines are deasserted and

the SSPxBUF can be written to. When the user ser-

vices the bus collision Interrupt Service Routine and if

the I²C bus is free, the user can resume communica-

tion by asserting a Start condition.

In multi-master operation, the SDAx line must be

monitored for arbitration to see if the signal level is the

expected output level. This check is performed by

hardware with the result placed in the BCLxIF bit.

If a Start, Repeated Start, Stop or Acknowledge condi-

tion was in progress when the bus collision occurred, the

condition is aborted, the SDAx and SCLx lines are deas-

serted and the respective control bits in the SSPxCON2

register are cleared. When the user services the bus col-

lision Interrupt Service Routine and if the I²C bus is free,

the user can resume communication by asserting a Start

condition.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

• A Start Condition

The master will continue to monitor the SDAx and SCLx

pins. If a Stop condition occurs, the SSPxIF bit will be set.

• A Repeated Start Condition

• An Acknowledge Condition

A write to the SSPxBUF will start the transmission of

data at the first data bit, regardless of where the

transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detection of Start and Stop conditions allows the deter-

mination of when the bus is free. Control of the I²C bus

can be taken when the P bit is set in the SSPxSTAT

register, or the bus is Idle and the S and P bits are

cleared.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 273

PIC16F/LF1826/27

FIGURE 24-32:

BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Sample SDAx. While SCLx is high,

data doesn’t match what is driven

by the master.

Data changes

while SCLx = 0

SDAx line pulled low

by another source

Bus collision has occurred.

SDAx released

by master

SDAx

SCLx

Set bus collision

interrupt (BCLxIF)

BCLxIF

DS41391C-page 274

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

If the SDAx pin is sampled low during this count, the

BRG is reset and the SDAx line is asserted early

(Figure 24-34). If, however, a ‘1’ is sampled on the

SDAx pin, the SDAx pin is asserted low at the end of

the BRG count. The Baud Rate Generator is then

reloaded and counts down to zero; if the SCLx pin is

sampled as ‘0’ during this time, a bus collision does not

occur. At the end of the BRG count, the SCLx pin is

asserted low.

24.6.13.1 Bus Collision During a Start

Condition

During a Start condition, a bus collision occurs if:

a) SDAx or SCLx are sampled low at the beginning

of the Start condition (Figure 24-32).

b) SCLx is sampled low before SDAx is asserted

low (Figure 24-33).

During a Start condition, both the SDAx and the SCLx

pins are monitored.

Note:

The reason that bus collision is not a factor

during a Start condition is that no two bus

masters can assert a Start condition at the

exact same time. Therefore, one master

will always assert SDAx before the other.

This condition does not cause a bus colli-

sion because the two masters must be

allowed to arbitrate the first address fol-

lowing the Start condition. If the address is

the same, arbitration must be allowed to

continue into the data portion, Repeated

Start or Stop conditions.

If the SDAx pin is already low, or the SCLx pin is

already low, then all of the following occur:

• the Start condition is aborted,

• the BCLxIF flag is set and

•

the MSSPx module is reset to its Idle state

(Figure 24-32).

The Start condition begins with the SDAx and SCLx

pins deasserted. When the SDAx pin is sampled high,

the Baud Rate Generator is loaded and counts down. If

the SCLx pin is sampled low while SDAx is high, a bus

collision occurs because it is assumed that another

master is attempting to drive a data ‘1’ during the Start

condition.

FIGURE 24-33:

BUS COLLISION DURING START CONDITION (SDAX ONLY)

SDAx goes low before the SEN bit is set.

Set BCLxIF,

S bit and SSPxIF set because

SDAx = 0, SCLx = 1.

SDAx

SCLx

SEN

Set SEN, enable Start

condition if SDAx = 1, SCLx = 1

SEN cleared automatically because of bus collision.

SSPx module reset into Idle state.

SDAx sampled low before

Start condition. Set BCLxIF.

S bit and SSPxIF set because

SDAx = 0, SCLx = 1.

BCLxIF

SSPxIF and BCLxIF are

cleared by software

S

SSPxIF

SSPxIF and BCLxIF are

cleared by software

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 275

PIC16F/LF1826/27

FIGURE 24-34:

BUS COLLISION DURING START CONDITION (SCLX = 0)

SDAx = 0, SCLx = 1

TBRG

SDAx

Set SEN, enable Start

sequence if SDAx = 1, SCLx = 1

SCLx

SEN

SCLx = 0before SDAx = 0,

bus collision occurs. Set BCLxIF.

SCLx = 0before BRG time-out,

bus collision occurs. Set BCLxIF.

BCLxIF

Interrupt cleared

by software

S

’0’

SSPxIF

FIGURE 24-35:

BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDAx = 0, SCLx = 1

Set S

Set SSPxIF

Less than TBRG

TBRG

SDAx pulled low by other master.

Reset BRG and assert SDAx.

SDAx

SCLx

S

SCLx pulled low after BRG

time-out

SEN

Set SEN, enable Start

sequence if SDAx = 1, SCLx = 1

’0’

BCLxIF

S

SSPxIF

Interrupts cleared

by software

SDAx = 0, SCLx = 1,

set SSPxIF

DS41391C-page 276

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

If SDAx is low, a bus collision has occurred (i.e., another

master is attempting to transmit a data ‘0’, Figure 24-35).

If SDAx is sampled high, the BRG is reloaded and

begins counting. If SDAx goes from high-to-low before

the BRG times out, no bus collision occurs because no

two masters can assert SDAx at exactly the same time.

24.6.13.2 Bus Collision During a Repeated

Start Condition

During a Repeated Start condition, a bus collision

occurs if:

a) A low level is sampled on SDAx when SCLx

goes from low level to high level.

If SCLx goes from high-to-low before the BRG times

out and SDAx has not already been asserted, a bus

collision occurs. In this case, another master is

attempting to transmit a data ‘1’ during the Repeated

Start condition, see Figure 24-36.

b) SCLx goes low before SDAx is asserted low,

indicating that another master is attempting to

transmit a data ‘1’.

When the user releases SDAx and the pin is allowed to

float high, the BRG is loaded with SSPxADD and

counts down to zero. The SCLx pin is then deasserted

and when sampled high, the SDAx pin is sampled.

If, at the end of the BRG time-out, both SCLx and SDAx

are still high, the SDAx pin is driven low and the BRG

is reloaded and begins counting. At the end of the

count, regardless of the status of the SCLx pin, the

SCLx pin is driven low and the Repeated Start

condition is complete.

FIGURE 24-36:

BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

SDAx

SCLx

Sample SDAx when SCLx goes high.

If SDAx = 0, set BCLxIF and release SDAx and SCLx.

RSEN

BCLxIF

Cleared by software

’0’

S

’0’

SSPxIF

FIGURE 24-37:

BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

TBRG

SDAx

SCLx

SCLx goes low before SDAx,

BCLxIF

RSEN

set BCLxIF. Release SDAx and SCLx.

Interrupt cleared

by software

’0’

S

SSPxIF

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 277

PIC16F/LF1826/27

The Stop condition begins with SDAx asserted low.

When SDAx is sampled low, the SCLx pin is allowed to

float. When the pin is sampled high (clock arbitration),

the Baud Rate Generator is loaded with SSPxADD and

counts down to 0. After the BRG times out, SDAx is

sampled. If SDAx is sampled low, a bus collision has

occurred. This is due to another master attempting to

drive a data ‘0’ (Figure 24-37). If the SCLx pin is

sampled low before SDAx is allowed to float high, a bus

collision occurs. This is another case of another master

attempting to drive a data ‘0’ (Figure 24-38).

24.6.13.3 Bus Collision During a Stop

Condition

Bus collision occurs during a Stop condition if:

a) After the SDAx pin has been deasserted and

allowed to float high, SDAx is sampled low after

the BRG has timed out.

b) After the SCLx pin is deasserted, SCLx is

sampled low before SDAx goes high.

FIGURE 24-38:

BUS COLLISION DURING A STOP CONDITION (CASE 1)

SDAx sampled

low after TBRG,

set BCLxIF

TBRG

SDAx

SDAx asserted low

SCLx

PEN

BCLxIF

P

’0’

SSPxIF

FIGURE 24-39:

BUS COLLISION DURING A STOP CONDITION (CASE 2)

TBRG

SDAx

SCLx goes low before SDAx goes high,

set BCLxIF

Assert SDAx

SCLx

PEN

BCLxIF

P

’0’

SSPxIF

DS41391C-page 278

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 24-3: REGISTERS ASSOCIATED WITH I²C™ OPERATION

Reset

Valueson

Page:

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

TMR1GIE

OSFIE

—

PEIE

ADIE

C2IE

—

TMR0IE

RCIE

C1IE

—

INTE

TXIE

EEIE

—

IOCIE

SSP1IE

BCL1IE

—

TMR0IF

CCP1IE

—

INTF

TMR2IE

—

IOCIF

91

92

TMR1IE

(1)

PIE2

CCP2IE

SSP2IE

TMR1IF

93

(1)

BCL2IE

TMR2IF

—

PIE4

—

CCP1IF

—

95

TMR1GIF

OSFIF

ADIF

C2IF

RCIF

C1IF

TXIF

EEIF

SSP1IF

BCL1IF

PIR1

PIR2

96

(1)

CCP2IF

SSP2IF

TRISA0

TRISB0

ADD0

97

(1)

BCL2IF

TRISA1

TRISB1

ADD1

PIR4

—

99

TRISA

TRISA7

TRISB7

ADD7

TRISA6

TRISB6

ADD6

TRISA5

TRISB5

ADD5

TRISA4

TRISB4

ADD4

TRISA3

TRISB3

ADD3

TRISA2

TRISB2

ADD2

124

129

286

237*

283

284

285

286

282

TRISB

SSPxADD

SSPxBUF

SSPxCON1

SSPxCON2

SSPxCON3

SSPxMSK

SSPxSTAT

MSSPx Receive Buffer/Transmit Register

WCOL

GCEN

ACKTIM

MSK7

SSPOV

ACKSTAT

PCIE

SSPEN

ACKDT

SCIE

CKP

ACKEN

BOEN

MSK4

P

SSPM3

RCEN

SDAHT

MSK3

S

SSPM2

PEN

SSPM1

RSEN

AHEN

MSK1

UA

SSPM0

SEN

SBCDE

MSK2

R/W

DHEN

MSK0

BF

MSK6

MSK5

D/A

SMP

CKE

2

Legend: —= unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I C™ mode.

Page provides register information.

Note 1: PIC16F/LF1827 only.

*

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 279

PIC16F/LF1826/27

module clock line. The logic dictating when the reload

signal is asserted depends on the mode the MSSPx is

being operated in.

24.7 BAUD RATE GENERATOR

The MSSPx module has a Baud Rate Generator avail-

able for clock generation in both I²C and SPI Master

modes. The Baud Rate Generator (BRG) reload value

is placed in the SSPxADD register (Register 24-6).

When a write occurs to SSPxBUF, the Baud Rate Gen-

erator will automatically begin counting down.

Table 24-4 demonstrates clock rates based on

instruction cycles and the BRG value loaded into

SSPxADD.

EQUATION 24-1:

Once the given operation is complete, the internal clock

will automatically stop counting and the clock pin will

remain in its last state.

FOSC

FCLOCK = -------------------------------------------------

SSPxADD + 14

An internal signal “Reload” in Figure 24-39 triggers the

value from SSPxADD to be loaded into the BRG

counter. This occurs twice for each oscillation of the

FIGURE 24-40:

BAUD RATE GENERATOR BLOCK DIAGRAM

SSPxM<3:0>

SSPxADD<7:0>

SSPxM<3:0>

SCLx

Reload

Control

Reload

BRG Down Counter

SSPxCLK

FOSC/2

Note: Values of 0x00, 0x01 and 0x02 are not valid

for SSPxADD when used as a Baud Rate

Generator for I²C. This is an implementation

limitation.

TABLE 24-4: MSSPX CLOCK RATE W/BRG

FCLOCK

(2 Rollovers of BRG)

FOSC

FCY

BRG Value

32 MHz

16 MHz

4 MHz

8 MHz

4 MHz

1 MHz

13h

19h

4Fh

09h

0Ch

27h

09h

400 kHz⁽¹⁾

308 kHz

100 kHz

400 kHz⁽¹⁾

308 kHz

100 kHz

Note 1: The I²C interface does not conform to the 400 kHz I²C specification (which applies to rates greater than

100 kHz) in all details, but may be used with care where higher rates are required by the application.

DS41391C-page 280

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

24.7.1

ALTERNATE PIN LOCATIONS

This module incorporates I/O pins that can be moved to

other locations with the use of the alternate pin function

registers, APFCON0 and APFCON1. To determine

which pins can be moved and what their default loca-

tions are upon a Reset, see Section 12.1 “Alternate

Pin Function” for more information.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 281

PIC16F/LF1826/27

REGISTER 24-1: SSPxSTAT: SSPx STATUS REGISTER

R/W-0/0

SMP

R/W-0/0

CKE

R-0/0

D/A

R-0/0

P

R-0/0

S

R-0/0

R/W

R-0/0

UA

R-0/0

BF

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

SMP: SPI Data Input Sample bit

SPI Master mode:

1= Input data sampled at end of data output time

0= Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode

2

In I C Master or Slave mode:

1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)

0 = Slew rate control enabled for high speed mode (400 kHz)

bit 6

CKE: SPI Clock Edge Select bit (SPI mode only)

In SPI Master or Slave mode:

1= Transmit occurs on transition from active to Idle clock state

0= Transmit occurs on transition from Idle to active clock state

2

In I C™ mode only:

1= Enable input logic so that thresholds are compliant with SM bus™ specification

0= Disable SM bus™ specific inputs

2

bit 5

bit 4

D/A: Data/Address bit (I C mode only)

1= Indicates that the last byte received or transmitted was data

0= Indicates that the last byte received or transmitted was address

P: Stop bit

2

(I C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.)

1= Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)

0= Stop bit was not detected last

bit 3

bit 2

S: Start bit

2

(I C mode only. This bit is cleared when the MSSPx module is disabled, SSPxEN is cleared.)

1= Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)

0= Start bit was not detected last

2

R/W: Read/Write bit information (I C mode only)

This bit holds the R/W bit information following the last address match. This bit is only valid from the address match

to the next Start bit, Stop bit, or not ACK bit.

2

In I C Slave mode:

1= Read

0= Write

2

In I C Master mode:

1= Transmit is in progress

0= Transmit is not in progress

OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Idle mode.

2

bit 1

bit 0

UA: Update Address bit (10-bit I C mode only)

1= Indicates that the user needs to update the address in the SSPxADD register

0= Address does not need to be updated

BF: Buffer Full Status bit

2

Receive (SPI and I C modes):

1= Receive complete, SSPxBUF is full

0= Receive not complete, SSPxBUF is empty

2

Transmit (I C mode only):

1= Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full

0= Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty

DS41391C-page 282

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

REGISTER 24-2: SSPxCON1: SSPx CONTROL REGISTER 1

R/C/HS-0/0

WCOL

R/C/HS-0/0

SSPxOV

R/W-0/0

SSPxEN

R/W-0/0

CKP

R/W-0/0

SSPxM<3:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HS = Bit is set by hardware C = User cleared

bit 7

WCOL: Write Collision Detect bit

Master mode:

1= A write to the SSPxBUF register was attempted while the I²C™ conditions were not valid for a transmission to be started

0= No collision

Slave mode:

1= The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software)

0= No collision

bit 6

SSPxOV: Receive Overflow Indicator bit⁽¹⁾

In SPI mode:

1= A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost.

Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid

setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the

SSPxBUF register (must be cleared in software).

0= No overflow

In I²C mode:

1= A byte is received while the SSPxBUF register is still holding the previous byte. SSPxOV is a “don’t care” in Transmit mode

(must be cleared in software).

0= No overflow

bit 5

SSPxEN: Synchronous Serial Port Enable bit

In both modes, when enabled, these pins must be properly configured as input or output

In SPI mode:

1= Enables serial port and configures SCKx, SDOx, SDIx and SSx as the source of the serial port pins⁽²⁾

0= Disables serial port and configures these pins as I/O port pins

In I²C mode:

1= Enables the serial port and configures the SDAx and SCLx pins as the source of the serial port pins⁽³⁾

0= Disables serial port and configures these pins as I/O port pins

bit 4

CKP: Clock Polarity Select bit

In SPI mode:

1= Idle state for clock is a high level

0= Idle state for clock is a low level

In I²C Slave mode:

SCLx release control

1= Enable clock

0= Holds clock low (clock stretch). (Used to ensure data setup time.)

In I²C Master mode:

Unused in this mode

bit 3-0

SSPxM<3:0>: Synchronous Serial Port Mode Select bits

0000= SPI Master mode, clock = FOSC/4

0001= SPI Master mode, clock = FOSC/16

0010= SPI Master mode, clock = FOSC/64

0011= SPI Master mode, clock = TMR2 output/2

0100= SPI Slave mode, clock = SCKx pin, SSx pin control enabled

0101= SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin

0110= I²C Slave mode, 7-bit address

0111= I²C Slave mode, 10-bit address

1000= I²C Master mode, clock = FOSC / (4 * (SSPxADD+1))⁽⁴⁾

1001= Reserved

1010= SPI Master mode, clock = FOSC/(4 * (SSPxADD+1))⁽⁵⁾

1011= I²C firmware controlled Master mode (Slave idle)

1100= Reserved

1101= Reserved

1110= I²C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

1111= I²C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

Note 1:

In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register.

When enabled, these pins must be properly configured as input or output.

When enabled, the SDAx and SCLx pins must be configured as inputs.

SSPxADD values of 0, 1 or 2 are not supported for I²C™ mode.

2:

3:

4:

5:

SSPxADD value of 0 is not supported. Use SSPxM = 0000 instead.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 283

PIC16F/LF1826/27

REGISTER 24-3: SSPxCON2: SSPx CONTROL REGISTER 2

R/W-0/0

GCEN

R-0/0

R/W-0/0

ACKDT

R/S/HS-0/0 R/S/HS-0/0

ACKEN RCEN

R/S/HS-0/0

PEN

R/S/HS-0/0 R/W/HS-0/0

RSEN SEN

bit 0

ACKSTAT

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HC = Cleared by hardware S = User set

bit 7

bit 6

bit 5

GCEN: General Call Enable bit (in I²C Slave mode only)

1= Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR

0= General call address disabled

ACKSTAT: Acknowledge Status bit (in I²C mode only)

1= Acknowledge was not received

0= Acknowledge was received

ACKDT: Acknowledge Data bit (in I²C mode only)

In Receive mode:

Value transmitted when the user initiates an Acknowledge sequence at the end of a receive

1= Not Acknowledge

0= Acknowledge

bit 4

ACKEN: Acknowledge Sequence Enable bit (in I²C Master mode only)

In Master Receive mode:

1= Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit.

Automatically cleared by hardware.

0= Acknowledge sequence idle

bit 3

bit 2

RCEN: Receive Enable bit (in I²C Master mode only)

1= Enables Receive mode for I²C

0= Receive idle

PEN: Stop Condition Enable bit (in I²C Master mode only)

SCKx Release Control:

1= Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.

0= Stop condition Idle

bit 1

bit 0

RSEN: Repeated Start Condition Enabled bit (in I²C Master mode only)

1= Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.

0= Repeated Start condition Idle

SEN: Start Condition Enabled bit (in I²C Master mode only)

In Master mode:

1= Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.

0= Start condition Idle

In Slave mode:

1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)

0= Clock stretching is disabled

Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I²C module is not in the Idle mode, this bit may not be

set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).

DS41391C-page 284

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

REGISTER 24-4: SSPxCON3: SSPx CONTROL REGISTER 3

R-0/0

R/W-0/0

PCIE

R/W-0/0

SCIE

R/W-0/0

BOEN

R/W-0/0

SDAHT

R/W-0/0

SBCDE

R/W-0/0

AHEN

R/W-0/0

DHEN

ACKTIM

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

ACKTIM: Acknowledge Time Status bit (I²C mode only)⁽³⁾

1= Indicates the I²C bus is in an Acknowledge sequence, set on 8^THfalling edge of SCLx clock

0= Not an Acknowledge sequence, cleared on 9^THrising edge of SCLx clock

PCIE: Stop Condition Interrupt Enable bit (I²C mode only)

1= Enable interrupt on detection of Stop condition

0= Stop detection interrupts are disabled⁽²⁾

SCIE: Start Condition Interrupt Enable bit (I²C mode only)

1= Enable interrupt on detection of Start or Restart conditions

0= Start detection interrupts are disabled⁽²⁾

BOEN: Buffer Overwrite Enable bit

In SPI Slave mode:⁽¹⁾

1= SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit

0= If new byte is received with BF bit of the SSPxSTAT register already set, SSPxOV bit of the

SSPxCON1 register is set, and the buffer is not updated

In I²C Master mode and SPI Master mode:

This bit is ignored.

In I²C Slave mode:

1= SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the

state of the SSPxOV bit only if the BF bit = 0.

0= SSPxBUF is only updated when SSPxOV is clear

bit 3

bit 2

SDAHT: SDAx Hold Time Selection bit (I²C mode only)

1= Minimum of 300 ns hold time on SDAx after the falling edge of SCLx

0= Minimum of 100 ns hold time on SDAx after the falling edge of SCLx

SBCDE: Slave Mode Bus Collision Detect Enable bit (I²C Slave mode only)

If on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the

BCLxIF bit of the PIR2 register is set, and bus goes idle

1= Enable slave bus collision interrupts

0= Slave bus collision interrupts are disabled

bit 1

bit 0

AHEN: Address Hold Enable bit (I²C Slave mode only)

1 = Following the 8th falling edge of SCLx for a matching received address byte; CKP bit of the

SSPxCON1 register will be cleared and the SCLx will be held low.

0= Address holding is disabled

DHEN: Data Hold Enable bit (I²C Slave mode only)

1= Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the CKP bit

of the SSPxCON1 register and SCLx is held low.

0= Data holding is disabled

Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPxOV is still set

when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF.

2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.

3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 285

PIC16F/LF1826/27

REGISTER 24-5: SSPxMSK: SSPx MASK REGISTER

R/W-1/1

MSK<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-1

bit 0

MSK<7:1>: Mask bits

1= The received address bit n is compared to SSPxADD<n> to detect I²C address match

0= The received address bit n is not used to detect I²C address match

MSK<0>: Mask bit for I²C Slave mode, 10-bit Address

I²C Slave mode, 10-bit address (SSPxM<3:0> = 0111or 1111):

1= The received address bit 0 is compared to SSPxADD<0> to detect I²C address match

0= The received address bit 0 is not used to detect I²C address match

I²C Slave mode, 7-bit address, the bit is ignored

REGISTER 24-6: SSPxADD: MSSPx ADDRESS AND BAUD RATE REGISTER (I²C MODE)

R/W-0/0

ADD<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

Master mode:

bit 7-0

ADD<7:0>: Baud Rate Clock Divider bits

SCLx pin clock period = ((ADD<7:0> + 1) *4)/FOSC

10-Bit Slave mode — Most Significant Address byte:

bit 7-3

Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pat-

tern sent by master is fixed by I²C specification and must be equal to ‘11110’. However, those bits are

compared by hardware and are not affected by the value in this register.

bit 2-1

bit 0

ADD<2:1>: Two Most Significant bits of 10-bit address

Not used: Unused in this mode. Bit state is a “don’t care”.

10-Bit Slave mode — Least Significant Address byte:

bit 7-0

ADD<7:0>: Eight Least Significant bits of 10-bit address

7-Bit Slave mode:

bit 7-1

bit 0

ADD<7:1>: 7-bit address

Not used: Unused in this mode. Bit state is a “don’t care”.

DS41391C-page 286

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

The EUSART module includes the following capabilities:

25.0 ENHANCED UNIVERSAL

SYNCHRONOUS

• Full-duplex asynchronous transmit and receive

• Two-character input buffer

ASYNCHRONOUS RECEIVER

TRANSMITTER (EUSART)

• One-character output buffer

• Programmable 8-bit or 9-bit character length

• Address detection in 9-bit mode

The Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) module is a serial I/O

communications peripheral. It contains all the clock

generators, shift registers and data buffers necessary

to perform an input or output serial data transfer

independent of device program execution. The

EUSART, also known as a Serial Communications

Interface (SCI), can be configured as a full-duplex

asynchronous system or half-duplex synchronous

• Input buffer overrun error detection

• Received character framing error detection

• Half-duplex synchronous master

• Half-duplex synchronous slave

• Programmable clock polarity in synchronous

modes

• Sleep operation

system.

Full-Duplex

mode

is

useful

for

The EUSART module implements the following

additional features, making it ideally suited for use in

Local Interconnect Network (LIN) bus systems:

communications with peripheral systems, such as CRT

terminals and personal computers. Half-Duplex

Synchronous mode is intended for communications

with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs or other microcontrollers.

These devices typically do not have internal clocks for

baud rate generation and require the external clock

signal provided by a master synchronous device.

• Automatic detection and calibration of the baud rate

• Wake-up on Break reception

• 13-bit Break character transmit

Block diagrams of the EUSART transmitter and

receiver are shown in Figure 25-1 and Figure 25-2.

FIGURE 25-1:

EUSART TRANSMIT BLOCK DIAGRAM

Data Bus

TXIE

Interrupt

TXIF

TXREG Register

8

TX/CK pin

MSb

(8)

LSb

0

Pin Buffer

and Control

• • •

Transmit Shift Register (TSR)

TXEN

TRMT

SPEN

Baud Rate Generator

BRG16

FOSC

÷ n

TX9

n

+ 1

Multiplier x4

x16 x64

TX9D

SYNC

BRGH

BRG16

1

X

1

0

1

0

1

0

SPBRGH

SPBRGL

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 287

PIC16F/LF1826/27

FIGURE 25-2:

EUSART RECEIVE BLOCK DIAGRAM

SPEN

CREN

OERR

RCIDL

RX/DT pin

RSR Register

MSb

Stop (8)

LSb

0

START

Pin Buffer

and Control

Data

Recovery

7

1

• • •

Baud Rate Generator

FOSC

RX9

÷ n

BRG16

n

+ 1

Multiplier

x4

x16 x64

SYNC

BRGH

BRG16

1

X

1

0

1

0

1

0

FIFO

SPBRGH

SPBRGL

X

RX9D

FERR

RCREG Register

8

Data Bus

RCIF

RCIE

Interrupt

The operation of the EUSART module is controlled

through three registers:

• Transmit Status and Control (TXSTA)

• Receive Status and Control (RCSTA)

• Baud Rate Control (BAUDCON)

These registers are detailed in Register 25-1,

Register 25-2 and Register 25-3, respectively.

When the receiver or transmitter section is not enabled

then the corresponding RX or TX pin may be used for

general purpose input and output.

DS41391C-page 288

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

25.1.1.2

Transmitting Data

25.1 EUSART Asynchronous Mode

A transmission is initiated by writing a character to the

TXREG register. If this is the first character, or the

previous character has been completely flushed from

the TSR, the data in the TXREG is immediately

transferred to the TSR register. If the TSR still contains

all or part of a previous character, the new character

data is held in the TXREG until the Stop bit of the

previous character has been transmitted. The pending

character in the TXREG is then transferred to the TSR

in one TCY immediately following the Stop bit

transmission. The transmission of the Start bit, data bits

and Stop bit sequence commences immediately

following the transfer of the data to the TSR from the

TXREG.

The EUSART transmits and receives data using the

standard non-return-to-zero (NRZ) format. NRZ is

implemented with two levels: a VOH mark state which

represents a ‘1’ data bit, and a VOL space state which

represents a ‘0’ data bit. NRZ refers to the fact that

consecutively transmitted data bits of the same value

stay at the output level of that bit without returning to a

neutral level between each bit transmission. An NRZ

transmission port idles in the mark state. Each character

transmission consists of one Start bit followed by eight

or nine data bits and is always terminated by one or

more Stop bits. The Start bit is always a space and the

Stop bits are always marks. The most common data

format is 8 bits. Each transmitted bit persists for a period

of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud

Rate Generator is used to derive standard baud rate

frequencies from the system oscillator. See Table 25-5

for examples of baud rate configurations.

25.1.1.3

Transmit Interrupt Flag

The TXIF interrupt flag bit of the PIR1 register is set

whenever the EUSART transmitter is enabled and no

character is being held for transmission in the TXREG.

In other words, the TXIF bit is only clear when the TSR

is busy with a character and a new character has been

queued for transmission in the TXREG. The TXIF flag bit

is not cleared immediately upon writing TXREG. TXIF

becomes valid in the second instruction cycle following

the write execution. Polling TXIF immediately following

the TXREG write will return invalid results. The TXIF bit

is read-only, it cannot be set or cleared by software.

The EUSART transmits and receives the LSb first. The

EUSART’s transmitter and receiver are functionally

independent, but share the same data format and baud

rate. Parity is not supported by the hardware, but can

be implemented in software and stored as the ninth

data bit.

25.1.1

EUSART ASYNCHRONOUS

TRANSMITTER

The TXIF interrupt can be enabled by setting the TXIE

interrupt enable bit of the PIE1 register. However, the

TXIF flag bit will be set whenever the TXREG is empty,

regardless of the state of TXIE enable bit.

The EUSART transmitter block diagram is shown in

Figure 25-1. The heart of the transmitter is the serial

Transmit Shift Register (TSR), which is not directly

accessible by software. The TSR obtains its data from

the transmit buffer, which is the TXREG register.

To use interrupts when transmitting data, set the TXIE

bit only when there is more data to send. Clear the

TXIE interrupt enable bit upon writing the last character

of the transmission to the TXREG.

25.1.1.1

Enabling the Transmitter

The EUSART transmitter is enabled for asynchronous

operations by configuring the following three control

bits:

• TXEN = 1

• SYNC = 0

• SPEN = 1

All other EUSART control bits are assumed to be in

their default state.

Setting the TXEN bit of the TXSTA register enables the

transmitter circuitry of the EUSART. Clearing the SYNC

bit of the TXSTA register configures the EUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTA register enables the EUSART and automatically

configures the TX/CK I/O pin as an output. If the TX/CK

pin is shared with an analog peripheral, the analog I/O

function must be disabled by clearing the corresponding

ANSEL bit.

Note 1: The TXIF Transmitter Interrupt flag is set

when the TXEN enable bit is set.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 289

PIC16F/LF1826/27

25.1.1.4

TSR Status

25.1.1.6

Asynchronous Transmission Set-up:

The TRMT bit of the TXSTA register indicates the

status of the TSR register. This is a read-only bit. The

TRMT bit is set when the TSR register is empty and is

cleared when a character is transferred to the TSR

register from the TXREG. The TRMT bit remains clear

until all bits have been shifted out of the TSR register.

No interrupt logic is tied to this bit, so the user has to

poll this bit to determine the TSR status.

1. Initialize the SPBRGH, SPBRGL register pair and

the BRGH and BRG16 bits to achieve the desired

baud rate (see Section 25.3 “EUSART Baud

Rate Generator (BRG)”).

2. Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

3. If 9-bit transmission is desired, set the TX9 con-

trol bit. A set ninth data bit will indicate that the 8

Least Significant data bits are an address when

the receiver is set for address detection.

Note:

The TSR register is not mapped in data

memory, so it is not available to the user.

4. Enable the transmission by setting the TXEN

control bit. This will cause the TXIF interrupt bit

to be set.

25.1.1.5

Transmitting 9-Bit Characters

The EUSART supports 9-bit character transmissions.

When the TX9 bit of the TXSTA register is set, the

EUSART will shift 9 bits out for each character transmit-

ted. The TX9D bit of the TXSTA register is the ninth,

and Most Significant, data bit. When transmitting 9-bit

data, the TX9D data bit must be written before writing

the 8 Least Significant bits into the TXREG. All nine bits

of data will be transferred to the TSR shift register

immediately after the TXREG is written.

5. If interrupts are desired, set the TXIE interrupt

enable bit of the PIE1 register. An interrupt will

occur immediately provided that the GIE and

PEIE bits of the INTCON register are also set.

6. If 9-bit transmission is selected, the ninth bit

should be loaded into the TX9D data bit.

7. Load 8-bit data into the TXREG register. This

will start the transmission.

A special 9-bit Address mode is available for use with

multiple receivers. See Section 25.1.2.7 “Address

Detection” for more information on the address mode.

FIGURE 25-3:

ASYNCHRONOUS TRANSMISSION

Write to TXREG

Word 1

BRG Output

(Shift Clock)

TX/CK

Start bit

bit 0

bit 1

Word 1

bit 7/8

Stop bit

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

1 TCY

Word 1

Transmit Shift Reg.

TRMT bit

(Transmit Shift

Reg. Empty Flag)

FIGURE 25-4:

ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)

Write to TXREG

Word 2

Start bit

Word 1

BRG Output

(Shift Clock)

TX/CK

Start bit

Word 2

bit 0

bit 1

bit 7/8

bit 0

Stop bit

1 TCY

Word 1

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

1 TCY

Word 1

Transmit Shift Reg.

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 2

Transmit Shift Reg.

Note:

This timing diagram shows two consecutive transmissions.

DS41391C-page 290

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Register on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

APFCON0

APFCON1

BAUDCON

INTCON

RXDTSEL

—

SDO1SEL

—

SS1SEL

—

P2BSEL⁽¹⁾CCP2SEL⁽¹⁾

P1DSEL

—

P1CSEL

—

CCP1SEL

TXCKSEL

ABDEN

122

298

101

—

ABDOVF

GIE

RCIDL

PEIE

—

SCKP

INTE

TXIE

TXIF

CREN

BRG16

IOCIE

SSPIE

SSPIF

ADDEN

—

WUE

INTF

TMR0IE

TMR0IF

IOCIF

PIE1

TMR1GIE

TMR1GIF

SPEN

ADIE

ADIF

RX9

RCIE

RCIF

SREN

CCP1IE

CCP1IF

FERR

TMR2IE

TMR2IF

OERR

TMR1IE

TMR1IF

RX9D

102

105

PIR1

RCSTA

SPBRGL

SPBRGH

TRISB

TXREG

TXSTA

297

BRG<7:0>

BRG<15:8>

299*

129

TRISB7

TRISB6

TRISB5

TRISB4

TRISB3

TRISB2

BRGH

TRISB1

TRMT

TRISB0

TX9D

EUSART Transmit Data Register

CSRC TX9 TXEN

289*

296

SYNC

SENDB

Legend:

*

Note 1:

— = unimplemented location, read as ‘0’. Shaded cells are not used for Asynchronous Transmission.

Page provides register information.

PIC16F/LF1827 only.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 291

PIC16F/LF1826/27

25.1.2

EUSART ASYNCHRONOUS

RECEIVER

25.1.2.2

Receiving Data

The receiver data recovery circuit initiates character

reception on the falling edge of the first bit. The first bit,

also known as the Start bit, is always a zero. The data

recovery circuit counts one-half bit time to the center of

the Start bit and verifies that the bit is still a zero. If it is

not a zero then the data recovery circuit aborts

character reception, without generating an error, and

resumes looking for the falling edge of the Start bit. If

the Start bit zero verification succeeds then the data

recovery circuit counts a full bit time to the center of the

next bit. The bit is then sampled by a majority detect

circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.

This repeats until all data bits have been sampled and

shifted into the RSR. One final bit time is measured and

the level sampled. This is the Stop bit, which is always

a ‘1’. If the data recovery circuit samples a ‘0’ in the

Stop bit position then a framing error is set for this

character, otherwise the framing error is cleared for this

character. See Section 25.1.2.4 “Receive Framing

Error” for more information on framing errors.

The Asynchronous mode is typically used in RS-232

systems. The receiver block diagram is shown in

Figure 25-2. The data is received on the RX/DT pin and

drives the data recovery block. The data recovery block

is actually a high-speed shifter operating at 16 times

the baud rate, whereas the serial Receive Shift

Register (RSR) operates at the bit rate. When all 8 or 9

bits of the character have been shifted in, they are

immediately transferred to

a

two character

First-In-First-Out (FIFO) memory. The FIFO buffering

allows reception of two complete characters and the

start of a third character before software must start

servicing the EUSART receiver. The FIFO and RSR

registers are not directly accessible by software.

Access to the received data is via the RCREG register.

25.1.2.1

Enabling the Receiver

The EUSART receiver is enabled for asynchronous

operation by configuring the following three control bits:

Immediately after all data bits and the Stop bit have

been received, the character in the RSR is transferred

to the EUSART receive FIFO and the RCIF interrupt

flag bit of the PIR1 register is set. The top character in

the FIFO is transferred out of the FIFO by reading the

RCREG register.

• CREN = 1

• SYNC = 0

• SPEN = 1

All other EUSART control bits are assumed to be in

their default state.

Setting the CREN bit of the RCSTA register enables the

receiver circuitry of the EUSART. Clearing the SYNC bit

of the TXSTA register configures the EUSART for

asynchronous operation. Setting the SPEN bit of the

RCSTA register enables the EUSART. The programmer

must set the corresponding TRIS bit to configure the

RX/DT I/O pin as an input.

Note:

If the receive FIFO is overrun, no additional

characters will be received until the overrun

condition is cleared. See Section 25.1.2.5

“Receive Overrun Error” for more

information on overrun errors.

25.1.2.3

Receive Interrupts

The RCIF interrupt flag bit of the PIR1 register is set

whenever the EUSART receiver is enabled and there is

an unread character in the receive FIFO. The RCIF

interrupt flag bit is read-only, it cannot be set or cleared

by software.

Note 1: If the RX/DT function is on an analog pin,

the corresponding ANSEL bit must be

cleared for the receiver to function.

RCIF interrupts are enabled by setting all of the

following bits:

• RCIE interrupt enable bit of the PIE1 register

• PEIE peripheral interrupt enable bit of the

INTCON register

• GIE global interrupt enable bit of the INTCON

register

The RCIF interrupt flag bit will be set when there is an

unread character in the FIFO, regardless of the state of

interrupt enable bits.

DS41391C-page 292

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

25.1.2.4

Receive Framing Error

25.1.2.7

Address Detection

Each character in the receive FIFO buffer has a

corresponding framing error Status bit. A framing error

indicates that a Stop bit was not seen at the expected

time. The framing error status is accessed via the

FERR bit of the RCSTA register. The FERR bit

represents the status of the top unread character in the

receive FIFO. Therefore, the FERR bit must be read

before reading the RCREG.

A special Address Detection mode is available for use

when multiple receivers share the same transmission

line, such as in RS-485 systems. Address detection is

enabled by setting the ADDEN bit of the RCSTA

register.

Address detection requires 9-bit character reception.

When address detection is enabled, only characters

with the ninth data bit set will be transferred to the

receive FIFO buffer, thereby setting the RCIF interrupt

bit. All other characters will be ignored.

The FERR bit is read-only and only applies to the top

unread character in the receive FIFO. A framing error

(FERR = 1) does not preclude reception of additional

characters. It is not necessary to clear the FERR bit.

Reading the next character from the FIFO buffer will

advance the FIFO to the next character and the next

corresponding framing error.

Upon receiving an address character, user software

determines if the address matches its own. Upon

address match, user software must disable address

detection by clearing the ADDEN bit before the next

Stop bit occurs. When user software detects the end of

the message, determined by the message protocol

used, software places the receiver back into the

Address Detection mode by setting the ADDEN bit.

The FERR bit can be forced clear by clearing the SPEN

bit of the RCSTA register which resets the EUSART.

Clearing the CREN bit of the RCSTA register does not

affect the FERR bit. A framing error by itself does not

generate an interrupt.

Note:

If all receive characters in the receive

FIFO have framing errors, repeated reads

of the RCREG will not clear the FERR bit.

25.1.2.5

Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its

entirety, is received before the FIFO is accessed. When

this happens the OERR bit of the RCSTA register is set.

The characters already in the FIFO buffer can be read

but no additional characters will be received until the

error is cleared. The error must be cleared by either

clearing the CREN bit of the RCSTA register or by

resetting the EUSART by clearing the SPEN bit of the

RCSTA register.

25.1.2.6

Receiving 9-bit Characters

The EUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set the EUSART

will shift 9 bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth and Most Significant data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the 8 Least Significant bits from

the RCREG.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 293

PIC16F/LF1826/27

25.1.2.8

Asynchronous Reception Set-up:

25.1.2.9

9-bit Address Detection Mode Set-up

1. Initialize the SPBRGH, SPBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 25.3 “EUSART

Baud Rate Generator (BRG)”).

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

1. Initialize the SPBRGH, SPBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 25.3 “EUSART

Baud Rate Generator (BRG)”).

2. Clear the ANSEL bit for the RX pin (if applicable).

3. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

2. Clear the ANSEL bit for the RX pin (if applicable).

4. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

3. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

5. If 9-bit reception is desired, set the RX9 bit.

6. Enable reception by setting the CREN bit.

4. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

7. The RCIF interrupt flag bit will be set when a

character is transferred from the RSR to the

receive buffer. An interrupt will be generated if

the RCIE interrupt enable bit was also set.

5. Enable 9-bit reception by setting the RX9 bit.

6. Enable address detection by setting the ADDEN

bit.

8. Read the RCSTA register to get the error flags

and, if 9-bit data reception is enabled, the ninth

data bit.

7. Enable reception by setting the CREN bit.

8. The RCIF interrupt flag bit will be set when a

character with the ninth bit set is transferred

from the RSR to the receive buffer. An interrupt

will be generated if the RCIE interrupt enable bit

was also set.

9. Get the received 8 Least Significant data bits

from the receive buffer by reading the RCREG

register.

10. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

9. Read the RCSTA register to get the error flags.

The ninth data bit will always be set.

10. Get the received 8 Least Significant data bits

from the receive buffer by reading the RCREG

register. Software determines if this is the

device’s address.

11. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

12. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and generate interrupts.

FIGURE 25-5:

ASYNCHRONOUS RECEPTION

Start

bit

Start

bit

Start

bit

RX/DT pin

bit 7/8

bit 0 bit 1

Stop

bit

Stop

bit

Stop

bit

bit 0

bit 7/8

Rcv Shift

Reg

Rcv Buffer Reg.

Word 2

RCREG

Word 1

RCREG

RCIDL

Read Rcv

Buffer Reg.

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Note:

This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,

causing the OERR (overrun) bit to be set.

DS41391C-page 294

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 25-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

APFCON0

APFCON1

BAUDCON

INTCON

PIE1

RXDTSEL SDO1SEL SS1SEL P2BSEL

CCP2SEL

—

P1DSEL

—

P1CSEL CCP1SEL

122

298

101

102

105

292*

297

299*

129

296

—

TXCKSEL

ABDEN

IOCIF

ABDOVF

GIE

RCIDL

PEIE

ADIE

ADIF

SCKP

INTE

TXIE

TXIF

BRG16

IOCIE

SSPIE

SSPIF

—

WUE

TMR0IE

RCIE

RCIF

TMR0IF

CCP1IE

CCP1IF

INTF

TMR1GIE

TMR1GIF

TMR2IE

TMR2IF

TMR1IE

TMR1IF

PIR1

RCREG

RCSTA

EUSART Receive Data Register

CREN ADDEN

BRG<7:0>

BRG<15:8>

SPEN

RX9

SREN

FERR

OERR

RX9D

SPBRGL

SPBRGH

TRISB

TRISB7

CSRC

TRISB6

TX9

TRISB5

TXEN

TRISB4

SYNC

TRISB3

SENDB

TRISB2

BRGH

TRISB1

TRMT

TRISB0

TX9D

TXSTA

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used for Asynchronous Reception.

*

Page provides register information.

Note 1: PIC16F/LF1827 only.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 295

PIC16F/LF1826/27

The first (preferred) method uses the OSCTUNE

register to adjust the INTOSC output. Adjusting the

value in the OSCTUNE register allows for fine resolution

changes to the system clock source. See Section 6.2.2

“Internal Clock Sources” for more information.

25.2 Clock Accuracy with

Asynchronous Operation

The factory calibrates the internal oscillator block out-

put (INTOSC). However, the INTOSC frequency may

drift as VDD or temperature changes, and this directly

affects the asynchronous baud rate. Two methods may

be used to adjust the baud rate clock, but both require

a reference clock source of some kind.

The other method adjusts the value in the Baud Rate

Generator. This can be done automatically with the

Auto-Baud Detect feature (see Section 25.3.1

“Auto-Baud Detect”). There may not be fine enough

resolution when adjusting the Baud Rate Generator to

compensate for a gradual change in the peripheral

clock frequency.

REGISTER 25-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-/0

CSRC

R/W-0/0

TX9

R/W-0/0

SYNC

R/W-0/0

SENDB

R/W-0/0

BRGH

R-1/1

R/W-0/0

TX9D

(1)

TXEN

TRMT

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care

Synchronous mode:

1= Master mode (clock generated internally from BRG)

0= Slave mode (clock from external source)

bit 6

bit 5

bit 4

bit 3

TX9: 9-bit Transmit Enable bit

1= Selects 9-bit transmission

0= Selects 8-bit transmission

(1)

TXEN: Transmit Enable bit

1= Transmit enabled

0= Transmit disabled

SYNC: EUSART Mode Select bit

1= Synchronous mode

0= Asynchronous mode

SENDB: Send Break Character bit

Asynchronous mode:

1= Send Sync Break on next transmission (cleared by hardware upon completion)

0= Sync Break transmission completed

Synchronous mode:

Don’t care

bit 2

BRGH: High Baud Rate Select bit

Asynchronous mode:

1= High speed

0= Low speed

Synchronous mode:

Unused in this mode

bit 1

bit 0

TRMT: Transmit Shift Register Status bit

1= TSR empty

0= TSR full

TX9D: Ninth bit of Transmit Data

Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode.

DS41391C-page 296

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

REGISTER 25-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER⁽¹⁾

R/W-0/0

SPEN

R/W-0/0

RX9

R/W-0/0

SREN

R/W-0/0

CREN

R/W-0/0

ADDEN

R-0/0

R-x/x

FERR

OERR

RX9D

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

SPEN: Serial Port Enable bit

1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

0= Serial port disabled (held in Reset)

RX9: 9-bit Receive Enable bit

1= Selects 9-bit reception

0= Selects 8-bit reception

SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode – Master:

1= Enables single receive

0= Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave

Don’t care

bit 4

CREN: Continuous Receive Enable bit

Asynchronous mode:

1= Enables receiver

0= Disables receiver

Synchronous mode:

1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0= Disables continuous receive

bit 3

ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1= Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set

0= Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 8-bit (RX9 = 0):

Don’t care

bit 2

bit 1

bit 0

FERR: Framing Error bit

1= Framing error (can be updated by reading RCREG register and receive next valid byte)

0= No framing error

OERR: Overrun Error bit

1= Overrun error (can be cleared by clearing bit CREN)

0= No overrun error

RX9D: Ninth bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 297

PIC16F/LF1826/27

REGISTER 25-3: BAUDCON: BAUD RATE CONTROL REGISTER

R-0/0

R-1/1

U-0

—

R/W-0/0

SCKP

R/W-0/0

BRG16

U-0

—

R/W-0/0

WUE

R/W-0/0

ABDEN

ABDOVF

RCIDL

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:

1= Auto-baud timer overflowed

0= Auto-baud timer did not overflow

Synchronous mode:

Don’t care

RCIDL: Receive Idle Flag bit

Asynchronous mode:

1= Receiver is Idle

0= Start bit has been received and the receiver is receiving

Synchronous mode:

Don’t care

bit 5

bit 4

Unimplemented: Read as ‘0’

SCKP: Synchronous Clock Polarity Select bit

Asynchronous mode:

1= Transmit inverted data to the TX/CK pin

0= Transmit non-inverted data to the TX/CK pin

Synchronous mode:

1= Data is clocked on rising edge of the clock

0= Data is clocked on falling edge of the clock

bit 3

BRG16: 16-bit Baud Rate Generator bit

1= 16-bit Baud Rate Generator is used

0= 8-bit Baud Rate Generator is used

bit 2

bit 1

Unimplemented: Read as ‘0’

WUE: Wake-up Enable bit

Asynchronous mode:

1= Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE

will automatically clear after RCIF is set.

0= Receiver is operating normally

Synchronous mode:

Don’t care

bit 0

ABDEN: Auto-Baud Detect Enable bit

Asynchronous mode:

1= Auto-Baud Detect mode is enabled (clears when auto-baud is complete)

0= Auto-Baud Detect mode is disabled

Synchronous mode:

Don’t care

DS41391C-page 298

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

EXAMPLE 25-1:

CALCULATING BAUD

RATE ERROR

25.3 EUSART Baud Rate Generator

(BRG)

For a device with FOSC of 16 MHz, desired baud rate

of 9600, Asynchronous mode, 8-bit BRG:

The Baud Rate Generator (BRG) is an 8-bit or 16-bit

timer that is dedicated to the support of both the

asynchronous and synchronous EUSART operation.

By default, the BRG operates in 8-bit mode. Setting the

BRG16 bit of the BAUDCON register selects 16-bit

mode.

FOSC

Desired Baud Rate = -----------------------------------------------------------------------

64[SPBRGH:SPBRGL] + 1

Solving for SPBRGH:SPBRGL:

FOSC

---------------------------------------------

Desired Baud Rate

X = --------------------------------------------- – 1

64

The SPBRGH, SPBRGL register pair determines the

period of the free running baud rate timer. In

Asynchronous mode the multiplier of the baud rate

period is determined by both the BRGH bit of the TXSTA

register and the BRG16 bit of the BAUDCON register. In

Synchronous mode, the BRGH bit is ignored.

16000000

-----------------------

9600

= ----------------------- – 1

64

= 25.042 = 25

Table 25-3 contains the formulas for determining the

baud rate. Example 25-1 provides a sample calculation

for determining the baud rate and baud rate error.

16000000

Calculated Baud Rate = --------------------------

6425 + 1

Typical baud rates and error values for various

asynchronous modes have been computed for your

convenience and are shown in Table 25-3. It may be

advantageous to use the high baud rate (BRGH = 1),

or the 16-bit BRG (BRG16 = 1) to reduce the baud rate

error. The 16-bit BRG mode is used to achieve slow

baud rates for fast oscillator frequencies.

= 9615

Calc. Baud Rate – Desired Baud Rate

Error = --------------------------------------------------------------------------------------------

Desired Baud Rate

9615 – 9600

= ---------------------------------- = 0 . 1 6 %

9600

Writing a new value to the SPBRGH, SPBRGL register

pair causes the BRG timer to be reset (or cleared). This

ensures that the BRG does not wait for a timer overflow

before outputting the new baud rate.

If the system clock is changed during an active receive

operation, a receive error or data loss may result. To

avoid this problem, check the status of the RCIDL bit to

make sure that the receive operation is Idle before

changing the system clock.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 299

PIC16F/LF1826/27

TABLE 25-3: BAUD RATE FORMULAS

Configuration Bits

Baud Rate Formula

BRG/EUSART Mode

SYNC

BRG16

BRGH

0

1

0

1

0

1

0

1

0

1

x

8-bit/Asynchronous

16-bit/Asynchronous

8-bit/Synchronous

16-bit/Synchronous

FOSC/[64 (n+1)]

FOSC/[16 (n+1)]

FOSC/[4 (n+1)]

Legend: x= Don’t care, n = value of SPBRGH, SPBRGL register pair

TABLE 25-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BAUDCON

RCSTA

ABDOVF RCIDL

—

SCKP

CREN

BRG16

ADDEN

—

WUE

ABDEN

RX9D

298

297

SPEN

CSRC

RX9

SREN

FERR

OERR

SPBRGL

SPBRGH

TXSTA

BRG<7:0>

BRG<15:8>

SYNC SENDB

299*

296

TX9

TXEN

BRGH

TRMT

TX9D

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator.

Page provides register information.

*

DS41391C-page 300

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 20.000 MHz FOSC = 18.432 MHz

FOSC = 32.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

300

1200

—

255

129

32

—

239

119

29

—

143

71

17

16

8

—

1221

2404

9470

10417

19.53k

1.73

0.16

-1.36

0.00

1.73

1200

2400

9600

10286

19.20k

0.00

-1.26

0.00

—

1200

2400

9600

10165

19.20k

0.00

-2.42

0.00

—

2400

2404

9615

10417

19.23k

0.16

0.00

0.16

207

51

47

25

9600

10417

19.2k

57.6k

115.2k

29

27

15

14

2

55.55k

—

-3.55

—

3

—

57.60k

—

7

57.60k

—

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

0.00

—

300

1200

—

1202

2404

9615

10417

—

0.16

0.00

—

103

51

12

11

300

1202

2404

—

0.16

—

207

51

25

—

5

300

1200

2400

9600

—

191

47

23

5

300

1202

—

0.16

—

51

12

—

2400

9600

—

10417

19.2k

57.6k

115.2k

10417

—

0.00

—

2

—

19.20k

0.00

—

0

—

57.60k

—

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 20.000 MHz FOSC = 18.432 MHz

FOSC = 32.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

—

300

1200

2400

9600

10417

19.2k

57.6k

—

71

65

35

11

5

9615

10417

19.23k

57.14k

0.16

0.00

0.16

-0.79

2.12

207

191

103

34

9615

10417

19.23k

56.82k

0.16

0.00

0.16

-1.36

129

119

64

9600

10378

19.20k

57.60k

115.2k

0.00

-0.37

0.00

119

110

59

19

9

9600

0.00

0.53

0.00

10473

19.20k

57.60k

115.2k

21

115.2k 117.64k

16

113.64k -1.36

10

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 301

PIC16F/LF1826/27

TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 8.000 MHz

FOSC = 4.000 MHz

FOSC = 3.6864 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

—

300

1200

—

1202

2404

9615

10417

19.23k

—

207

103

25

—

191

95

23

21

11

3

300

1202

2404

—

0.16

—

207

51

25

—

5

0.16

0.00

0.16

—

1200

0.00

0.53

0.00

2400

2404

9615

10417

19231

55556

—

0.16

0.00

0.16

-3.55

—

207

51

47

25

8

2400

9600

10417

19.2k

57.6k

115.2k

23

10473

19.2k

57.60k

115.2k

10417

—

0.00

—

12

—

1

—

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 20.000 MHz FOSC = 18.432 MHz

FOSC = 32.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

300

1200

300.0

1200

0.00

-0.02

-0.04

0.16

0.00

0.16

-0.79

2.12

6666

3332

832

207

191

103

34

300.0

1200

-0.01

-0.03

0.16

0.00

0.16

-1.36

4166

1041

520

129

119

64

300.0

1200

0.00

-0.37

0.00

3839

959

479

119

110

59

300.0

1200

0.00

0.53

0.00

2303

575

287

71

2400

2401

2399

2400

9600

9615

9600

10417

19.2k

57.6k

115.2k

10417

19.23k

57.14k

117.6k

10417

19.23k

56.818

10378

19.20k

57.60k

115.2k

10473

19.20k

57.60k

115.2k

65

35

21

19

11

16

113.636 -1.36

10

9

5

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

300

1200

299.9

1199

-0.02

-0.08

0.16

0.00

0.16

-3.55

—

1666

416

207

51

300.1

1202

2404

9615

10417

19.23k

—

0.04

0.16

0.00

0.16

—

832

207

103

25

300.0

1200

0.00

0.53

0.00

767

191

95

23

21

11

3

300.5

1202

2404

—

0.16

—

207

51

25

—

5

2400

2404

9615

10417

19.23k

55556

—

2400

9600

10417

19.2k

57.6k

115.2k

47

23

10473

19.20k

57.60k

115.2k

10417

—

0.00

—

25

12

—

8

—

1

—

DS41391C-page 302

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 25-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 20.000 MHz FOSC = 18.432 MHz

FOSC = 32.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

300

1200

300.0

1200

0.00

0.01

0.04

0.00

-0.08

0.64

26666

6666

3332

832

300.0

1200

0.00

-0.01

0.02

-0.03

0.00

0.16

-0.22

0.94

16665

4166

2082

520

479

259

86

300.0

1200

0.00

0.08

0.00

15359

3839

1919

479

441

239

79

300.0

1200

0.00

0.16

0.00

9215

2303

1151

287

264

143

47

2400

9600

9604

9597

9600

10417

19.2k

57.6k

115.2k

10417

19.18k

57.55k

115.9k

767

10417

19.23k

57.47k

116.3k

10425

19.20k

57.60k

115.2k

10433

19.20k

57.60k

115.2k

416

138

68

42

39

23

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

300

1200

300.0

1200

0.00

-0.02

0.04

0.16

0

6666

1666

832

207

191

103

34

300.0

1200

0.01

0.04

0.08

0.16

0.00

0.16

2.12

-3.55

3332

832

416

103

95

300.0

1200

0.00

0.53

0.00

3071

767

383

95

300.1

1202

2404

9615

10417

19.23k

—

0.04

0.16

0.00

0.16

—

832

207

103

25

2400

2401

2398

2400

9600

9615

9600

10417

19.2k

57.6k

115.2k

10417

19.23k

57.14k

117.6k

10417

19.23k

58.82k

111.1k

10473

19.20k

57.60k

115.2k

87

23

0.16

-0.79

2.12

51

47

12

16

15

—

16

8

7

—

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 303

PIC16F/LF1826/27

and SPBRGL registers are clocked at 1/8th the BRG

base clock rate. The resulting byte measurement is the

average bit time when clocked at full speed.

25.3.1

AUTO-BAUD DETECT

The EUSART module supports automatic detection

and calibration of the baud rate.

Note 1: If the WUE bit is set with the ABDEN bit,

auto-baud detection will occur on the byte

following the Break character (see

In the Auto-Baud Detect (ABD) mode, the clock to the

BRG is reversed. Rather than the BRG clocking the

incoming RX signal, the RX signal is timing the BRG.

The Baud Rate Generator is used to time the period of

a received 55h (ASCII “U”) which is the Sync character

for the LIN bus. The unique feature of this character is

that it has five rising edges including the Stop bit edge.

Section 25.3.3

“Auto-Wake-up

on

Break”).

2: It is up to the user to determine that the

incoming character baud rate is within the

range of the selected BRG clock source.

Some combinations of oscillator frequency

and EUSART baud rates are not possible.

Setting the ABDEN bit of the BAUDCON register starts

the auto-baud calibration sequence (Figure 25-6).

While the ABD sequence takes place, the EUSART

state machine is held in Idle. On the first rising edge of

the receive line, after the Start bit, the SPBRG begins

counting up using the BRG counter clock as shown in

Table 25-6. The fifth rising edge will occur on the RX pin

at the end of the eighth bit period. At that time, an

accumulated value totaling the proper BRG period is

left in the SPBRGH, SPBRGL register pair, the ABDEN

bit is automatically cleared and the RCIF interrupt flag

is set. The value in the RCREG needs to be read to

clear the RCIF interrupt. RCREG content should be

discarded. When calibrating for modes that do not use

the SPBRGH register the user can verify that the

SPBRGL register did not overflow by checking for 00h

in the SPBRGH register.

3: During the auto-baud process, the

auto-baud counter starts counting at 1.

Upon completion of the auto-baud

sequence, to achieve maximum accuracy,

subtract 1 from the SPBRGH:SPBRGL

register pair.

TABLE 25-6:

BRG16 BRGH

BRG COUNTER CLOCK RATES

BRG Base

Clock

BRG ABD

Clock

0

1

FOSC/64

FOSC/16

FOSC/512

FOSC/128

1

0

1

FOSC/16

FOSC/4

FOSC/128

FOSC/32

The BRG auto-baud clock is determined by the BRG16

and BRGH bits as shown in Table 25-6. During ABD,

both the SPBRGH and SPBRGL registers are used as

a 16-bit counter, independent of the BRG16 bit setting.

While calibrating the baud rate period, the SPBRGH

Note:

During the ABD sequence, SPBRGL and

SPBRGH registers are both used as a 16-bit

counter, independent of BRG16 setting.

FIGURE 25-6:

AUTOMATIC BAUD RATE CALIBRATION

XXXXh

0000h

001Ch

BRG Value

Edge #1

bit 1

Edge #2

bit 3

Edge #3

bit 5

Edge #4

bit 7

bit 6

Edge #5

Stop bit

RX pin

Start

bit 0

bit 2

bit 4

BRG Clock

Auto Cleared

Set by User

ABDEN bit

RCIDL

RCIF bit

(Interrupt)

Read

RCREG

XXh

1Ch

00h

SPBRGL

SPBRGH

Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.

DS41391C-page 304

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

25.3.2

AUTO-BAUD OVERFLOW

25.3.3.1

Special Considerations

During the course of automatic baud detection, the

ABDOVF bit of the BAUDCON register will be set if the

baud rate counter overflows before the fifth rising edge

is detected on the RX pin. The ABDOVF bit indicates

that the counter has exceeded the maximum count that

can fit in the 16 bits of the SPBRGH:SPBRGL register

pair. After the ABDOVF has been set, the counter con-

tinues to count until the fifth rising edge is detected on

the RX pin. Upon detecting the fifth RX edge, the hard-

ware will set the RCIF interrupt flag and clear the

ABDEN bit of the BAUDCON register. The RCIF flag

can be subsequently cleared by reading the RCREG

register. The ABDOVF flag of the BAUDCON register

can be cleared by software directly.

Break Character

To avoid character errors or character fragments during

a wake-up event, the wake-up character must be all

zeros.

When the wake-up is enabled the function works

independent of the low time on the data stream. If the

WUE bit is set and a valid non-zero character is

received, the low time from the Start bit to the first rising

edge will be interpreted as the wake-up event. The

remaining bits in the character will be received as a

fragmented character and subsequent characters can

result in framing or overrun errors.

Therefore, the initial character in the transmission must

be all ‘0’s. This must be 10 or more bit times, 13-bit

times recommended for LIN bus, or any number of bit

times for standard RS-232 devices.

To terminate the auto-baud process before the RCIF

flag is set, clear the ABDEN bit then clear the ABDOVF

bit of the BAUDCON register. The ABDOVF bit will

remain set if the ABDEN bit is not cleared first.

Oscillator Start-up Time

Oscillator start-up time must be considered, especially

in applications using oscillators with longer start-up

intervals (i.e., LP, XT or HS/PLL mode). The Sync

Break (or wake-up signal) character must be of

sufficient length, and be followed by a sufficient

interval, to allow enough time for the selected oscillator

to start and provide proper initialization of the EUSART.

25.3.3

AUTO-WAKE-UP ON BREAK

During Sleep mode, all clocks to the EUSART are

suspended. Because of this, the Baud Rate Generator

is inactive and a proper character reception cannot be

performed. The Auto-Wake-up feature allows the

controller to wake-up due to activity on the RX/DT line.

This feature is available only in Asynchronous mode.

WUE Bit

The Auto-Wake-up feature is enabled by setting the

WUE bit of the BAUDCON register. Once set, the normal

receive sequence on RX/DT is disabled, and the

EUSART remains in an Idle state, monitoring for a

wake-up event independent of the CPU mode. A

wake-up event consists of a high-to-low transition on the

RX/DT line. (This coincides with the start of a Sync Break

or a wake-up signal character for the LIN protocol.)

The wake-up event causes a receive interrupt by

setting the RCIF bit. The WUE bit is cleared in

hardware by a rising edge on RX/DT. The interrupt

condition is then cleared in software by reading the

RCREG register and discarding its contents.

To ensure that no actual data is lost, check the RCIDL

bit to verify that a receive operation is not in process

before setting the WUE bit. If a receive operation is not

occurring, the WUE bit may then be set just prior to

entering the Sleep mode.

The EUSART module generates an RCIF interrupt

coincident with the wake-up event. The interrupt is

generated synchronously to the Q clocks in normal CPU

operating modes (Figure 25-7), and asynchronously if

the device is in Sleep mode (Figure 25-8). The interrupt

condition is cleared by reading the RCREG register.

The WUE bit is automatically cleared by the low-to-high

transition on the RX line at the end of the Break. This

signals to the user that the Break event is over. At this

point, the EUSART module is in Idle mode waiting to

receive the next character.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 305

PIC16F/LF1826/27

FIGURE 25-7:

AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3Q4

OSC1

Auto Cleared

Bit set by user

WUE bit

RX/DT Line

RCIF

Cleared due to User Read of RCREG

Note 1: The EUSART remains in Idle while the WUE bit is set.

FIGURE 25-8:

AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q4

Q1Q2Q3 Q4 Q1Q2 Q3Q4 Q1Q2Q3

Q1

Q2 Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4

Auto Cleared

OSC1

Bit Set by User

WUE bit

RX/DT Line

Note 1

RCIF

Cleared due to User Read of RCREG

Sleep Command Executed

Sleep Ends

Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposcsignal is

still active. This sequence should not depend on the presence of Q clocks.

2: The EUSART remains in Idle while the WUE bit is set.

DS41391C-page 306

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

25.3.4

BREAK CHARACTER SEQUENCE

25.3.5

RECEIVING A BREAK CHARACTER

The EUSART module has the capability of sending the

special Break character sequences that are required by

the LIN bus standard. A Break character consists of a

Start bit, followed by 12 ‘0’ bits and a Stop bit.

The Enhanced EUSART module can receive a Break

character in two ways.

The first method to detect a Break character uses the

FERR bit of the RCSTA register and the Received data

as indicated by RCREG. The Baud Rate Generator is

assumed to have been initialized to the expected baud

rate.

To send a Break character, set the SENDB and TXEN

bits of the TXSTA register. The Break character trans-

mission is then initiated by a write to the TXREG. The

value of data written to TXREG will be ignored and all

‘0’s will be transmitted.

A Break character has been received when;

• RCIF bit is set

• FERR bit is set

• RCREG = 00h

The SENDB bit is automatically reset by hardware after

the corresponding Stop bit is sent. This allows the user

to preload the transmit FIFO with the next transmit byte

following the Break character (typically, the Sync

character in the LIN specification).

The second method uses the Auto-Wake-up feature

described in Section 25.3.3 “Auto-Wake-up on

Break”. By enabling this feature, the EUSART will

sample the next two transitions on RX/DT, cause an

RCIF interrupt, and receive the next data byte followed

by another interrupt.

The TRMT bit of the TXSTA register indicates when the

transmit operation is active or Idle, just as it does during

normal transmission. See Figure 25-9 for the timing of

the Break character sequence.

Note that following a Break character, the user will

typically want to enable the Auto-Baud Detect feature.

For both methods, the user can set the ABDEN bit of

the BAUDCON register before placing the EUSART in

Sleep mode.

25.3.4.1

Break and Sync Transmit Sequence

The following sequence will start a message frame

header made up of a Break, followed by an auto-baud

Sync byte. This sequence is typical of a LIN bus

master.

1. Configure the EUSART for the desired mode.

2. Set the TXEN and SENDB bits to enable the

Break sequence.

3. Load the TXREG with a dummy character to

initiate transmission (the value is ignored).

4. Write ‘55h’ to TXREG to load the Sync character

into the transmit FIFO buffer.

5. After the Break has been sent, the SENDB bit is

reset by hardware and the Sync character is

then transmitted.

When the TXREG becomes empty, as indicated by the

TXIF, the next data byte can be written to TXREG.

FIGURE 25-9:

SEND BREAK CHARACTER SEQUENCE

Write to TXREG

Dummy Write

BRG Output

(Shift Clock)

TX (pin)

Start bit

bit 0

bit 1

Break

bit 11

Stop bit

TXIF bit

(Transmit

Interrupt Flag)

TRMT bit

(Transmit Shift

Empty Flag)

SENDB Sampled Here

Auto Cleared

SENDB

(send Break

control bit)

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 307

PIC16F/LF1826/27

Clearing the SCKP bit sets the Idle state as low. When

the SCKP bit is cleared, the data changes on the rising

edge of each clock.

25.4 EUSART Synchronous Mode

Synchronous serial communications are typically used

in systems with a single master and one or more

slaves. The master device contains the necessary cir-

cuitry for baud rate generation and supplies the clock

for all devices in the system. Slave devices can take

advantage of the master clock by eliminating the inter-

nal clock generation circuitry.

25.4.1.3

Synchronous Master Transmission

Data is transferred out of the device on the RX/DT pin.

The RX/DT and TX/CK pin output drivers are automat-

ically enabled when the EUSART is configured for syn-

chronous master transmit operation.

There are two signal lines in Synchronous mode: a bidi-

rectional data line and a clock line. Slaves use the

external clock supplied by the master to shift the serial

data into and out of their respective receive and trans-

mit shift registers. Since the data line is bidirectional,

synchronous operation is half-duplex only. Half-duplex

refers to the fact that master and slave devices can

receive and transmit data but not both simultaneously.

The EUSART can operate as either a master or slave

device.

A transmission is initiated by writing a character to the

TXREG register. If the TSR still contains all or part of a

previous character the new character data is held in the

TXREG until the last bit of the previous character has

been transmitted. If this is the first character, or the pre-

vious character has been completely flushed from the

TSR, the data in the TXREG is immediately transferred

to the TSR. The transmission of the character com-

mences immediately following the transfer of the data

to the TSR from the TXREG.

Start and Stop bits are not used in synchronous trans-

missions.

Each data bit changes on the leading edge of the mas-

ter clock and remains valid until the subsequent leading

clock edge.

25.4.1

SYNCHRONOUS MASTER MODE

Note:

The TSR register is not mapped in data

memory, so it is not available to the user.

The following bits are used to configure the EUSART

for Synchronous Master operation:

• SYNC = 1

25.4.1.4

Synchronous Master Transmission

Set-up:

• CSRC = 1

• SREN = 0(for transmit); SREN = 1(for receive)

• CREN = 0(for transmit); CREN = 1(for receive)

• SPEN = 1

1. Initialize the SPBRGH, SPBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 25.3 “EUSART

Baud Rate Generator (BRG)”).

Setting the SYNC bit of the TXSTA register configures

the device for synchronous operation. Setting the CSRC

bit of the TXSTA register configures the device as a

master. Clearing the SREN and CREN bits of the RCSTA

register ensures that the device is in the Transmit mode,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

EUSART.

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. Disable Receive mode by clearing bits SREN

and CREN.

4. Enable Transmit mode by setting the TXEN bit.

5. If 9-bit transmission is desired, set the TX9 bit.

6. If interrupts are desired, set the TXIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

25.4.1.1

Master Clock

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device config-

ured as a master transmits the clock on the TX/CK line.

The TX/CK pin output driver is automatically enabled

when the EUSART is configured for synchronous

transmit or receive operation. Serial data bits change

on the leading edge to ensure they are valid at the trail-

ing edge of each clock. One clock cycle is generated

for each data bit. Only as many clock cycles are gener-

ated as there are data bits.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in the TX9D bit.

8. Start transmission by loading data to the TXREG

register.

25.4.1.2

Clock Polarity

A clock polarity option is provided for Microwire

compatibility. Clock polarity is selected with the SCKP

bit of the BAUDCON register. Setting the SCKP bit sets

the clock Idle state as high. When the SCKP bit is set,

the data changes on the falling edge of each clock.

DS41391C-page 308

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 25-10:

SYNCHRONOUS TRANSMISSION

RX/DT

bit 0

bit 1

bit 2

bit 7

bit 0

bit 1

Word 2

bit 7

Word 1

TX/CK pin

(SCKP = 0)

TX/CK pin

(SCKP = 1)

Write to

TXREG Reg

Write Word 1

Write Word 2

TXIF bit

(Interrupt Flag)

TRMT bit

‘1’

TXEN bit

Note:

Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.

FIGURE 25-11:

SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RX/DT pin

bit 0

bit 2

bit 1

bit 6

bit 7

TX/CK pin

Write to

TXREG reg

TXIF bit

TRMT bit

TXEN bit

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 309

PIC16F/LF1826/27

TABLE 25-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER

TRANSMISSION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

APFCON0

APFCON1

BAUDCON

INTCON

PIE1

RXDTSEL SDO1SEL SS1SEL P2BSEL

CCP2SEL

—

P1DSEL

—

P1CSEL CCP1SEL

122

298

101

102

—

TXCKSEL

ABDEN

IOCIF

ABDOVF

GIE

RCIDL

PEIE

ADIE

ADIF

SCKP

INTE

TXIE

TXIF

BRG16

IOCIE

SSPIE

SSPIF

—

WUE

TMR0IE

RCIE

RCIF

TMR0IF

CCP1IE

CCP1IF

INTF

TMR1GIE

TMR1GIF

TMR2IE

TMR2IF

TMR1IE

TMR1IF

PIR1

105

297

RCSTA

SPBRGL

SPBRGH

TRISB

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

BRG<7:0>

299*

129

BRG<15:8>

TRISB7

CSRC

TRISB6

TX9

TRISB5

TRISB4

TRISB3

TRISB2

TRISB1

TRMT

TRISB0

TX9D

TXREG

TXSTA

EUSART Transmit Data Register

TXEN SYNC SENDB

289*

296

BRGH

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Transmission.

*

Page provides register information.

Note 1: PIC16F/LF1827 only.

DS41391C-page 310

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

will be received until the error is cleared. The OERR bit

can only be cleared by clearing the overrun condition.

If the overrun error occurred when the SREN bit is set

and CREN is clear then the error is cleared by reading

RCREG. If the overrun occurred when the CREN bit is

set then the error condition is cleared by either clearing

the CREN bit of the RCSTA register or by clearing the

SPEN bit which resets the EUSART.

25.4.1.5

Synchronous Master Reception

Data is received at the RX/DT pin. The RX/DT pin

output driver is automatically disabled when the

EUSART is configured for synchronous master receive

operation.

In Synchronous mode, reception is enabled by setting

either the Single Receive Enable bit (SREN of the

RCSTA register) or the Continuous Receive Enable bit

(CREN of the RCSTA register).

25.4.1.8

Receiving 9-bit Characters

When SREN is set and CREN is clear, only as many

clock cycles are generated as there are data bits in a

single character. The SREN bit is automatically cleared

at the completion of one character. When CREN is set,

clocks are continuously generated until CREN is

cleared. If CREN is cleared in the middle of a character

the CK clock stops immediately and the partial charac-

ter is discarded. If SREN and CREN are both set, then

SREN is cleared at the completion of the first character

and CREN takes precedence.

The EUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set the EUSART

will shift 9-bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth, and Most Significant, data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the 8 Least Significant bits from

the RCREG.

25.4.1.9

Synchronous Master Reception

Set-up:

To initiate reception, set either SREN or CREN. Data is

sampled at the RX/DT pin on the trailing edge of the

TX/CK clock pin and is shifted into the Receive Shift

1. Initialize the SPBRGH, SPBRGL register pair for

the appropriate baud rate. Set or clear the

BRGH and BRG16 bits, as required, to achieve

the desired baud rate.

Register (RSR). When

a complete character is

received into the RSR, the RCIF bit is set and the char-

acter is automatically transferred to the two character

receive FIFO. The Least Significant eight bits of the top

character in the receive FIFO are available in RCREG.

The RCIF bit remains set as long as there are unread

characters in the receive FIFO.

2. Clear the ANSEL bit for the RX pin (if applicable).

3. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

4. Ensure bits CREN and SREN are clear.

Note:

If the RX/DT function is on an analog pin,

the corresponding ANSEL bit must be

cleared for the receiver to function.

5. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

6. If 9-bit reception is desired, set bit RX9.

25.4.1.6

Slave Clock

7. Start reception by setting the SREN bit or for

continuous reception, set the CREN bit.

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device configured

as a slave receives the clock on the TX/CK line. The

TX/CK pin output driver is automatically disabled when

the device is configured for synchronous slave transmit

or receive operation. Serial data bits change on the

leading edge to ensure they are valid at the trailing edge

of each clock. One data bit is transferred for each clock

cycle. Only as many clock cycles should be received as

there are data bits.

8. Interrupt flag bit RCIF will be set when reception

of a character is complete. An interrupt will be

generated if the enable bit RCIE was set.

9. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

10. Read the 8-bit received data by reading the

RCREG register.

11. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

register or by clearing the SPEN bit which resets

the EUSART.

Note:

If the device is configured as a slave and

the TX/CK function is on an analog pin, the

corresponding ANSEL bit must be cleared.

25.4.1.7

Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its

entirety, is received before RCREG is read to access

the FIFO. When this happens the OERR bit of the

RCSTA register is set. Previous data in the FIFO will

not be overwritten. The two characters in the FIFO

buffer can be read, however, no additional characters

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 311

PIC16F/LF1826/27

FIGURE 25-12:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

RX/DT

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

TX/CK pin

(SCKP = 0)

TX/CK pin

(SCKP = 1)

Write to

bit SREN

SREN bit

‘0’

CREN bit

RCIF bit

(Interrupt)

Read

RCREG

Note:

Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.

TABLE 25-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER

RECEPTION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

APFCON0

APFCON1

BAUDCON

INTCON

PIE1

RXDTSEL SDO1SEL SS1SEL P2BSEL

CCP2SEL

—

P1DSEL

—

P1CSEL CCP1SEL

122

298

101

102

105

292*

297

299*

129

296

—

TXCKSEL

ABDEN

IOCIF

ABDOVF

GIE

RCIDL

PEIE

ADIE

ADIF

SCKP

INTE

TXIE

TXIF

BRG16

IOCIE

SSPIE

SSPIF

—

WUE

TMR0IE

RCIE

RCIF

TMR0IF

CCP1IE

CCP1IF

INTF

TMR1GIE

TMR1GIF

TMR2IE

TMR2IF

TMR1IE

TMR1IF

PIR1

RCREG

RCSTA

EUSART Receive Data Register

CREN ADDEN

BRG<7:0>

BRG<15:8>

SPEN

RX9

SREN

FERR

OERR

RX9D

SPBRGL

SPBRGH

TRISB

TRISB7

CSRC

TRISB6

TX9

TRISB5

TXEN

TRISB4

SYNC

TRISB3

SENDB

TRISB2

BRGH

TRISB1

TRMT

TRISB0

TX9D

TXSTA

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Reception.

*

Page provides register information.

Note 1: PIC16F/LF1827 only.

DS41391C-page 312

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

If two words are written to the TXREG and then the

SLEEPinstruction is executed, the following will occur:

25.4.2

SYNCHRONOUS SLAVE MODE

The following bits are used to configure the EUSART

for Synchronous slave operation:

1. The first character will immediately transfer to

the TSR register and transmit.

• SYNC = 1

2. The second word will remain in TXREG register.

3. The TXIF bit will not be set.

• CSRC = 0

• SREN = 0(for transmit); SREN = 1(for receive)

• CREN = 0(for transmit); CREN = 1(for receive)

• SPEN = 1

4. After the first character has been shifted out of

TSR, the TXREG register will transfer the second

character to the TSR and the TXIF bit will now be

set.

Setting the SYNC bit of the TXSTA register configures the

device for synchronous operation. Clearing the CSRC bit

of the TXSTA register configures the device as a slave.

Clearing the SREN and CREN bits of the RCSTA register

ensures that the device is in the Transmit mode,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

EUSART.

5. If the PEIE and TXIE bits are set, the interrupt

will wake the device from Sleep and execute the

next instruction. If the GIE bit is also set, the

program will call the Interrupt Service Routine.

25.4.2.2

Synchronous Slave Transmission

Set-up:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

25.4.2.1

EUSART Synchronous Slave

Transmit

2. Clear the ANSEL bit for the CK pin (if applicable).

3. Clear the CREN and SREN bits.

The operation of the Synchronous Master and Slave

modes are identical (see Section 25.4.1.3

“Synchronous Master Transmission”), except in the

4. If interrupts are desired, set the TXIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

case of the Sleep mode.

5. If 9-bit transmission is desired, set the TX9 bit.

6. Enable transmission by setting the TXEN bit.

7. If 9-bit transmission is selected, insert the Most

Significant bit into the TX9D bit.

8. Start transmission by writing the Least

Significant 8 bits to the TXREG register.

TABLE 25-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE

TRANSMISSION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

APFCON0

APFCON1

BAUDCON

INTCON

PIE1

RXDTSEL SDO1SEL SS1SEL P2BSEL

CCP2SEL

—

P1DSEL

—

P1CSEL CCP1SEL

122

298

101

102

—

TXCKSEL

ABDEN

IOCIF

ABDOVF

GIE

RCIDL

PEIE

ADIE

ADIF

SCKP

INTE

TXIE

TXIF

BRG16

IOCIE

SSPIE

SSPIF

—

WUE

TMR0IE

RCIE

RCIF

TMR0IF

CCP1IE

CCP1IF

INTF

TMR1GIE

TMR1GIF

TMR2IE

TMR2IF

TMR1IE

TMR1IF

PIR1

105

297

129

289*

296

RX9

SREN

CREN

ADDEN

TRISB3

FERR

OERR

RX9D

RCSTA

SPEN

TRISB

TRISB7

TRISB6

TRISB5

TRISB4

TRISB2

TRISB1

TRISB0

TXREG

EUSART Transmit Data Register

TXEN SYNC SENDB

TXSTA

CSRC

TX9

BRGH

TRMT

TX9D

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.

*

Page provides register information.

Note 1: PIC16F/LF1827 only.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 313

PIC16F/LF1826/27

25.4.2.3

EUSART Synchronous Slave

Reception

25.4.2.4

Synchronous Slave Reception

Set-up:

The operation of the Synchronous Master and Slave

modes is identical (Section 25.4.1.5 “Synchronous

Master Reception”), with the following exceptions:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. Clear the ANSEL bit for both the CK and DT pins

(if applicable).

• Sleep

3. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

• CREN bit is always set, therefore the receiver is

never Idle

• SREN bit, which is a “don’t care” in Slave mode

4. If 9-bit reception is desired, set the RX9 bit.

5. Set the CREN bit to enable reception.

A character may be received while in Sleep mode by

setting the CREN bit prior to entering Sleep. Once the

word is received, the RSR register will transfer the data

to the RCREG register. If the RCIE enable bit is set, the

interrupt generated will wake the device from Sleep

and execute the next instruction. If the GIE bit is also

set, the program will branch to the interrupt vector.

6. The RCIF bit will be set when reception is

complete. An interrupt will be generated if the

RCIE bit was set.

7. If 9-bit mode is enabled, retrieve the Most

Significant bit from the RX9D bit of the RCSTA

register.

8. Retrieve the 8 Least Significant bits from the

receive FIFO by reading the RCREG register.

9. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

register or by clearing the SPEN bit which resets

the EUSART.

TABLE 25-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE

RECEPTION

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

APFCON0

APFCON1

BAUDCON

INTCON

PIE1

RXDTSEL SDO1SEL SS1SEL P2BSEL

CCP2SEL

—

P1DSEL

—

P1CSEL CCP1SEL

122

298

101

102

—

TXCKSEL

ABDEN

IOCIF

ABDOVF

GIE

RCIDL

PEIE

ADIE

ADIF

SCKP

INTE

TXIE

TXIF

BRG16

IOCIE

SSPIE

SSPIF

—

WUE

TMR0IE

RCIE

RCIF

TMR0IF

CCP1IE

CCP1IF

INTF

TMR1GIE

TMR1GIF

TMR2IE

TMR2IF

TMR1IE

TMR1IF

PIR1

105

292*

297

129

296

RCREG

RCSTA

EUSART Receive Data Register

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

SPEN

TRISB

TXSTA

TRISB7

CSRC

TRISB6

TX9

TRISB5

TXEN

TRISB4

SYNC

TRISB3

SENDB

TRISB2

BRGH

TRISB1

TRMT

TRISB0

TX9D

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.

*

Page provides register information.

Note 1: PIC16F/LF1827 only.

DS41391C-page 314

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

25.5.2

SYNCHRONOUS TRANSMIT

DURING SLEEP

25.5 EUSART Operation During Sleep

The EUSART will remain active during Sleep only in the

Synchronous Slave mode. All other modes require the

system clock and therefore cannot generate the neces-

sary signals to run the Transmit or Receive Shift regis-

ters during Sleep.

To transmit during Sleep, all the following conditions

must be met before entering Sleep mode:

• RCSTA and TXSTA Control registers must be

configured for Synchronous Slave Transmission

(see Section 25.4.2.2 “Synchronous Slave

Transmission Set-up:”).

Synchronous Slave mode uses an externally generated

clock to run the Transmit and Receive Shift registers.

•

The TXIF interrupt flag must be cleared by writing

the output data to the TXREG, thereby filling the

TSR and transmit buffer.

25.5.1

SYNCHRONOUS RECEIVE DURING

SLEEP

• If interrupts are desired, set the TXIE bit of the

PIE1 register and the PEIE bit of the INTCON reg-

ister.

To receive during Sleep, all the following conditions

must be met before entering Sleep mode:

• RCSTA and TXSTA Control registers must be

configured for Synchronous Slave Reception (see

Section 25.4.2.4 “Synchronous Slave

Reception Set-up:”).

• Interrupt enable bits TXIE of the PIE1 register and

PEIE of the INTCON register must set.

Upon entering Sleep mode, the device will be ready to

accept clocks on TX/CK pin and transmit data on the

RX/DT pin. When the data word in the TSR has been

completely clocked out by the external device, the

pending byte in the TXREG will transfer to the TSR and

the TXIF flag will be set. Thereby, waking the processor

from Sleep. At this point, the TXREG is available to

accept another character for transmission, which will

clear the TXIF flag.

• If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

• The RCIF interrupt flag must be cleared by read-

ing RCREG to unload any pending characters in

the receive buffer.

Upon entering Sleep mode, the device will be ready to

accept data and clocks on the RX/DT and TX/CK pins,

respectively. When the data word has been completely

clocked in by the external device, the RCIF interrupt

flag bit of the PIR1 register will be set. Thereby, waking

the processor from Sleep.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the Global

Interrupt Enable (GIE) bit is also set then the Interrupt

Service Routine at address 0004h will be called.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the GIE global

interrupt enable bit of the INTCON register is also set,

then the Interrupt Service Routine at address 004h will

be called.

25.5.3

ALTERNATE PIN LOCATIONS

This module incorporates I/O pins that can be moved to

other locations with the use of the alternate pin function

registers, APFCON0 and APFCON1. To determine

which pins can be moved and what their default loca-

tions are upon a Reset, see Section 12.1 “Alternate

Pin Function” for more information.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 315

PIC16F/LF1826/27

NOTES:

DS41391C-page 316

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

26.0 CAPACITIVE SENSING

MODULE

The capacitive sensing module allows for an interaction

with an end user without a mechanical interface. In a

typical application, the capacitive sensing module is

attached to a pad on a Printed Circuit Board (PCB),

which is electrically isolated from the end user. When the

end user places their finger over the PCB pad, a

capacitive load is added, causing a frequency shift in the

capacitive sensing module. The capacitive sensing

module requires software and at least one timer

resource to determine the change in frequency. Key

features of this module include:

• Analog MUX for monitoring multiple inputs

• Capacitive sensing oscillator

• Multiple timer resources

• Software control

• Operation during Sleep

FIGURE 26-1:

CAPACITIVE SENSING BLOCK DIAGRAM

Timer0 Module

Set

TMR0IF

TMR0CS

T0XCS

T0CKI

FOSC/4

0

1

Overflow

0

1

TMR0

CPSCH<3:0>

CPSON⁽¹⁾

CPS0

CPS1

CPS2

CPS3

CPS4

CPS5

CPS6

CPS7

CPS8

CPS9

CPS10

CPS11

Timer1 Module

CPSON

T1CS<1:0>

FOSC

Capacitive

Sensing

Oscillator

FOSC/4

CPSCLK

TMR1H:TMR1L

EN

T1OSC/

T1CKI

CPSOSC

CPSOUT

T1GSEL<1:0>

T1G

CPSRNG<1:0>

Timer1 Gate

Control Logic

SYNCC1OUT

SYNCC2OUT

Note 1: If CPSON = 0, disabling capacitive sensing, no channel is selected.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 317

PIC16F/LF1826/27

26.4.1

TIMER0

26.1 Analog MUX

To select Timer0 as the timer resource for the capacitive

sensing module:

The capacitive sensing module can monitor up to 12

inputs. The capacitive sensing inputs are defined as

CPS<11:0>. To determine if a frequency change has

occurred the user must:

• Set the T0XCS bit of the CPSCON0 register

• Clear the TMR0CS bit of the OPTION register

• Select the appropriate CPS pin by setting the

CPSCH<3:0> bits of the CPSCON1 register

When Timer0 is chosen as the timer resource, the

capacitive sensing oscillator will be the clock source for

Timer0. Refer to Section 19.0 “Timer0 Module” for

additional information.

• Set the corresponding ANSEL bit

• Set the corresponding TRIS bit

• Run the software algorithm

26.4.2

TIMER1

Selection of the CPSx pin while the module is enabled

will cause the capacitive sensing oscillator to be on the

CPSx pin. Failure to set the corresponding ANSEL and

TRIS bits can cause the capacitive sensing oscillator to

stop, leading to false frequency readings.

To select Timer1 as the timer resource for the

capacitive sensing module, set the TMR1CS<1:0> of

the T1CON register to ‘11’. When Timer1 is chosen as

the timer resource, the capacitive sensing oscillator will

be the clock source for Timer1. Because the Timer1

module has a gate control, developing a time base for

the frequency measurement can be simplified by using

the Timer0 overflow flag.

26.2 Capacitive Sensing Oscillator

The capacitive sensing oscillator consists of a constant

current source and a constant current sink, to produce

It is recommend that the Timer0 overflow flag, in con-

junction with the Toggle mode of the Timer1 Gate, be

used to develop the fixed time base required by the

software portion of the capacitive sensing module.

Refer to Section 20.6.3 “Timer1 Gate Toggle Mode”

for additional information.

a

triangle waveform. The CPSOUT bit of the

CPSCON0 register shows the status of the capacitive

sensing oscillator, whether it is a sinking or sourcing

current. The oscillator is designed to drive a capacitive

load (single PCB pad) and at the same time, be a clock

source to either Timer0 or Timer1. The oscillator has

three different current settings as defined by

CPSRNG<1:0> of the CPSCON0 register. The different

current settings for the oscillator serve two purposes:

TABLE 26-1: TIMER1 ENABLE FUNCTION

TMR1ON

TMR1GE

Timer1 Operation

0

1

0

1

0

Off

On

• Maximize the number of counts in a timer for a

fixed time base

• Maximize the count differential in the timer during

a change in frequency

1

Count Enabled by input

26.3 Timer resources

To measure the change in frequency of the capacitive

sensing oscillator, a fixed time base is required. For the

period of the fixed time base, the capacitive sensing

oscillator is used to clock either Timer0 or Timer1. The

frequency of the capacitive sensing oscillator is equal

to the number of counts in the timer divided by the

period of the fixed time base.

26.4 Fixed Time Base

To measure the frequency of the capacitive sensing

oscillator, a fixed time base is required. Any timer

resource or software loop can be used to establish the

fixed time base. It is up to the end user to determine the

method in which the fixed time base is generated.

Note:

The fixed time base can not be generated

by the timer resource that the capacitive

sensing oscillator is clocking.

DS41391C-page 318

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

26.5.3

FREQUENCY THRESHOLD

26.5 Software Control

The frequency threshold should be placed midway

between the value of nominal frequency and the

reduced frequency of the capacitive sensing oscillator.

Refer to Application Note AN1103, “Software Handling

for Capacitive Sensing” (DS01103) for more detailed

information on the software required for capacitive

sensing module.

The software portion of the capacitive sensing module

is required to determine the change in frequency of the

capacitive sensing oscillator. This is accomplished by

the following:

• Setting a fixed time base to acquire counts on

Timer0 or Timer1

• Establishing the nominal frequency for the

capacitive sensing oscillator

Note:

For more information on general capacitive

sensing refer to Application Notes:

• Establishing the reduced frequency for the

capacitive sensing oscillator due to an additional

capacitive load

• AN1101, “Introduction to Capacitive

Sensing” (DS01101)

• AN1102, “Layout and Physical Design

Guidelines for Capacitive Sensing”

(DS01102)

• Set the frequency threshold

26.5.1

NOMINAL FREQUENCY

(NO CAPACITIVE LOAD)

26.6 Operation during Sleep

To determine the nominal frequency of the capacitive

sensing oscillator:

The capacitive sensing oscillator will continue to run as

long as the module is enabled, independent of the part

being in Sleep. In order for the software to determine if

a frequency change has occurred, the part must be

awake. However, the part does not have to be awake

when the timer resource is acquiring counts.

• Remove any extra capacitive load on the selected

CPSx pin

• At the start of the fixed time base, clear the timer

resource

• At the end of the fixed time base save the value in

the timer resource

Note:

Timer0 does not operate when in Sleep,

and therefore cannot be used for

capacitive sense measurements in Sleep.

The value of the timer resource is the number of

oscillations of the capacitive sensing oscillator for the

given time base. The frequency of the capacitive

sensing oscillator is equal to the number of counts on

in the timer divided by the period of the fixed time base.

26.5.2

REDUCED FREQUENCY

(ADDITIONAL CAPACITIVE LOAD)

The extra capacitive load will cause the frequency of the

capacitive sensing oscillator to decrease. To determine

the reduced frequency of the capacitive sensing

oscillator:

• Add a typical capacitive load on the selected

CPSx pin

• Use the same fixed time base as the nominal

frequency measurement

• At the start of the fixed time base, clear the timer

resource

• At the end of the fixed time base save the value in

the timer resource

The value of the timer resource is the number of oscil-

lations of the capacitive sensing oscillator with an addi-

tional capacitive load. The frequency of the capacitive

sensing oscillator is equal to the number of counts on

in the timer divided by the period of the fixed time base.

This frequency should be less than the value obtained

during the nominal frequency measurement.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 319

PIC16F/LF1826/27

REGISTER 26-1: CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0

R/W-0/0

CPSON

U-0

—

U-0

—

U-0

—

R/W-0/0

R-0/0

R/W-0/0

T0XCS

CPSRNG1

CPSRNG0

CPSOUT

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

CPSON: Capacitive Sensing Module Enable bit

1= Capacitive sensing module is enabled

0= Capacitive sensing module is disabled

bit 6-4

bit 3-2

Unimplemented: Read as ‘0’

CPSRNG<1:0>: Capacitive Sensing Oscillator Range bits

00= Oscillator is off

01= Oscillator is in low range. Charge/discharge current is nominally 0.1 µA.

10= Oscillator is in medium range. Charge/discharge current is nominally 1.2 µA.

11= Oscillator is in high range. Charge/discharge current is nominally 18 µA.

bit 1

bit 0

CPSOUT: Capacitive Sensing Oscillator Status bit

1= Oscillator is sourcing current (Current flowing out the pin)

0= Oscillator is sinking current (Current flowing into the pin)

T0XCS: Timer0 External Clock Source Select bit

If TMR0CS = 1

The T0XCS bit controls which clock external to the core/Timer0 module supplies Timer0:

1= Timer0 clock source is the capacitive sensing oscillator

0= Timer0 clock source is the T0CKI pin

If TMR0CS = 0

Timer0 clock source is controlled by the core/Timer0 module and is FOSC/4

DS41391C-page 320

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

REGISTER 26-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

CPSCH3

CPSCH2

CPSCH1

CPSCH0

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

CPSCH<3:0>: Capacitive Sensing Channel Select bits

If CPSON = 0:

These bits are ignored. No channel is selected.

If CPSON = 1:

0000= channel 0, (CPS0)

0001= channel 1, (CPS1)

0010= channel 2, (CPS2)

0011= channel 3, (CPS3)

0100= channel 4, (CPS4)

0101= channel 5, (CPS5)

0110= channel 6, (CPS6)

0111= channel 7, (CPS7)

1000= channel 8, (CPS8)

1001= channel 9, (CPS9)

1010= channel 10, (CPS10)

1011= channel 11, (CPS11)

1100= Reserved. Do not use.

1101= Reserved. Do not use.

1110= Reserved. Do not use.

1111= Reserved. Do not use.

TABLE 26-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELA

—

ANSB7

CPSON

—

ANSB6

—

ANSB5

—

ANSA4

ANSB4

—

ANSA3

ANSB3

ANSA2

ANSB2

ANSA1

ANSB1

ANSA0

—

125

130

320

321

91

ANSELB

CPSCON0

CPSCON1

INTCON

CPSRNG1 CPSRNG0 CPSOUT

T0XCS

CPSCH0

IOCIF

—

CPSCH3

IOCIE

CPSCH2

TMR0IF

CPSCH1

INTF

GIE

PEIE

TMR0IE

INTE

OPTION_REG WPUEN

INTEDG

ADIE

TMR0CS

RCIE

TMR0SE

TXIE

PSA

PS2

PS1

TMR2IE

TMR2IF

—

PS0

177

92

PIE1

TMR1GIE

TMR1GIF

SSP1IE

SSP1IF

CCP1IE

CCP1IF

TMR1IE

TMR1IF

TMR1ON

PIR1

ADIF

RCIF

TXIF

96

T1CON

TxCON

TRISA

TRISB

TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

187

193

124

129

—

TxOUTPS3 TxOUTPS2 TxOUTPS1 TxOUTPS0 TMRxON TxCKPS1 TxCKPS0

TRISA7

TRISB7

TRISA6

TRISB6

TRISA5

TRISB5

TRISA4

TRISB4

TRISA3

TRISB3

TRISA2

TRISB2

TRISA1

TRISB1

TRISA0

TRISB0

Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the capacitive sensing module.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 321

PIC16F/LF1826/27

NOTES:

DS41391C-page 322

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

NOTES:

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 323

PIC16F/LF1826/27

NOTES:

DS41391C-page 324

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

27.0 IN-CIRCUIT SERIAL

PROGRAMMING™ (ICSP™)

ICSP™ programming allows customers to manufacture

circuit boards with unprogrammed devices. Programming

can be done after the assembly process allowing the

device to be programmed with the most recent firmware

or a custom firmware. Five pins are needed for ICSP™

programming:

• ICSPCLK

• ICSPDAT

• MCLR/VPP

• VDD

• VSS

In Program/Verify mode the Program Memory, User IDs

and the Configuration Words are programmed through

serial communications. The ICSPDAT pin is a bidirec-

tional I/O used for transferring the serial data and the

ICSPCLK pin is the clock input. For more information on

ICSP™ refer to the “PIC16193X/PIC16LF193X Memory

Programming Specification” (DS41360A).

27.1 High-Voltage Programming Entry

Mode

The device is placed into High-Voltage Programming

Entry mode by holding the ICSPCLK and ICSPDAT

pins low then raising the voltage on MCLR/VPP to VIHH.

Some programmers produce VPP greater than VIHH

(9.0V), an external circuit is required to limit the VPP

voltage. See Figure 27-1 for example circuit.

FIGURE 27-1:

VPP LIMITER EXAMPLE CIRCUIT

RJ11-6PIN

6

5

4

3

2

1

VPP

2

VDD

3

VSS

4

ICSP_DATA

ICSP_CLOCK

NC

5

6

1

RJ11-6PIN

R1

To MPLAB^®ICD 2

To Target Board

270 Ohm

LM431BCMX

1

2

K

A

U1

3

6

7

4

5

NC

VREF

8

R2

R3

10k 1%

24k 1%

Note:

The ICD 2 produces a VPP voltage greater

than the maximum VPP specification of the

PIC16F/LF1826/27.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 325

PIC16F/LF1826/27

FIGURE 27-2:

ICD RJ-11 STYLE

CONNECTOR INTERFACE

27.2 Low-Voltage Programming Entry

Mode

The Low-Voltage Programming Entry mode allows the

PIC16F/LF1826/27 devices to be programmed using

VDD only, without high voltage. When the LVP bit of

Configuration Word 2 is set to ‘1’, the low-voltage ICSP

programming entry is enabled. To disable the

Low-Voltage ICSP mode, the LVP bit must be

programmed to ‘0’.

ICSPDAT

NC

2 4 6

VDD

ICSPCLK

1 3

5

Target

PC Board

Bottom Side

Entry into the Low-Voltage Programming Entry mode

requires the following steps:

VPP/MCLR

VSS

1. MCLR is brought to VIL.

2.

A

32-bit key sequence is presented on

Pin Description*

ICSPDAT, while clocking ICSPCLK.

1 = VPP/MCLR

2 = VDD Target

3 = VSS (ground)

4 = ICSPDAT

Once the key sequence is complete, MCLR must be

held at VIL for as long as Program/Verify mode is to be

maintained.

If low-voltage programming is enabled (LVP = 1), the

MCLR Reset function is automatically enabled and

cannot be disabled. See Section 7.3 “MCLR” for more

information.

5 = ICSPCLK

6 = No Connect

The LVP bit can only be reprogrammed to ‘0’ by using

the High-Voltage Programming mode.

Another connector often found in use with the PICkit™

programmers is a standard 6-pin header with 0.1 inch

spacing. Refer to Figure 27-3.

27.3 Common Programming Interfaces

Connection to a target device is typically done through

an ICSP™ header. A commonly found connector on

development tools is the RJ-11 in the 6P6C (6 pin, 6

connector) configuration. See Figure 27-2.

FIGURE 27-3:

PICKIT™ STYLE CONNECTOR INTERFACE

Pin 1 Indicator

Pin Description*

1 = VPP/MCLR

2 = VDD Target

3 = VSS (ground)

4 = ICSPDAT

1

2

3

4

5

6

5 = ICSPCLK

6 = No Connect

*

The 6-pin header (0.100" spacing) accepts 0.025" square pins.

DS41391C-page 326

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

For additional interface recommendations, refer to your

specific device programmer manual prior to PCB

design.

It is recommended that isolation devices be used to

separate the programming pins from other circuitry.

The type of isolation is highly dependent on the specific

application and may include devices such as resistors,

diodes, or even jumpers. See Figure 27-4 for more

information.

FIGURE 27-4:

TYPICAL CONNECTION FOR ICSP™ PROGRAMMING

External

Programming

Signals

Device to be

Programmed

VDD

VPP

VSS

MCLR/VPP

VSS

Data

ICSPDAT

ICSPCLK

Clock

*

To Normal Connections

Isolation devices (as required).

*

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 327

PIC16F/LF1826/27

NOTES:

DS41391C-page 328

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

28.1 Read-Modify-Write Operations

28.0 INSTRUCTION SET SUMMARY

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (R-M-W)

operation. The register is read, the data is modified,

and the result is stored according to either the instruc-

tion, or the destination designator ‘d’. A read operation

is performed on a register even if the instruction writes

to that register.

Each PIC16 instruction is a 14-bit word containing the

operation code (opcode) and all required operands.

The opcodes are broken into three broad categories.

• Byte Oriented

• Bit Oriented

• Literal and Control

The literal and control category contains the most var-

ied instruction word format.

TABLE 28-1: OPCODE FIELD

DESCRIPTIONS

Table 28-3 lists the instructions recognized by the

MPASM^TMassembler.

Field

Description

All instructions are executed within a single instruction

cycle, with the following exceptions, which may take

two or three cycles:

f

W

b

Register file address (0x00 to 0x7F)

Working register (accumulator)

Bit address within an 8-bit file register

Literal field, constant data or label

• Subroutine takes two cycles (CALL, CALLW)

• Returns from interrupts or subroutines take two

cycles (RETURN, RETLW, RETFIE)

k

x

Don’t care location (= 0or 1).

• Program branching takes two cycles (GOTO, BRA,

BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)

• One additional instruction cycle will be used when

any instruction references an indirect file register

and the file select register is pointing to program

memory.

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip software tools.

d

Destination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1.

One instruction cycle consists of 4 oscillator cycles; for

an oscillator frequency of 4 MHz, this gives a nominal

instruction execution rate of 1 MHz.

n

FSR or INDF number. (0-1)

mm

Pre-post increment-decrement mode

selection

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies a

hexadecimal digit.

TABLE 28-2: ABBREVIATION

DESCRIPTIONS

Field

Description

PC

TO

C

Program Counter

Time-out bit

Carry bit

DC

Z

Digit carry bit

Zero bit

PD

Power-down bit

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 329

PIC16F/LF1826/27

FIGURE 28-1:

GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented file register operations

13

8

7

6

0

OPCODE

d

f (FILE #)

d = 0for destination W

d = 1for destination f

f = 7-bit file register address

Bit-oriented file register operations

13 10 9

7 6

0

OPCODE

b (BIT #)

f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

General

13

8

7

0

OPCODE

k (literal)

k = 8-bit immediate value

CALLand GOTOinstructions only

13 11 10

OPCODE

0

k (literal)

k = 11-bit immediate value

MOVLPinstruction only

13

7

6

0

OPCODE

k (literal)

k = 7-bit immediate value

MOVLBinstruction only

13

5 4

OPCODE

k (literal)

k = 5-bit immediate value

BRAinstruction only

13

9

8

0

OPCODE

k (literal)

k = 9-bit immediate value

FSR Offset instructions

13

7

6

5

0

OPCODE

n

k (literal)

n = appropriate FSR

k = 6-bit immediate value

FSRIncrement instructions

13

3

2

n

1

OPCODE

m (mode)

n = appropriate FSR

m = 2-bit mode value

OPCODE only

13

0

OPCODE

DS41391C-page 330

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 28-3: PIC16F/LF1826/27 ENHANCED INSTRUCTION SET

14-Bit Opcode

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

MSb

LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ADDWFC f, d

ANDWF

ASRF

LSLF

f, d

Add W and f

Add with Carry W and f

AND W with f

Arithmetic Right Shift

Logical Left Shift

Logical Right Shift

Clear f

Clear W

Complement f

Decrement f

Increment f

Inclusive OR W with f

Move f

Move W to f

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Subtract with Borrow W from f

Swap nibbles in f

Exclusive OR W with f

1

00 0111 dfff ffff C, DC, Z

11 1101 dfff ffff C, DC, Z

00 0101 dfff ffff Z

11 0111 dfff ffff C, Z

11 0101 dfff ffff C, Z

11 0110 dfff ffff C, Z

2

f, d

f

LSRF

CLRF

CLRW

COMF

DECF

INCF

IORWF

MOVF

MOVWF

RLF

RRF

SUBWF

SUBWFB f, d

SWAPF

XORWF

00 0001 lfff ffff

00 0001 0000 00xx

00 1001 dfff ffff

00 0011 dfff ffff

00 1010 dfff ffff

00 0100 dfff ffff

00 1000 dfff ffff

00 0000 1fff ffff

00 1101 dfff ffff

00 1100 dfff ffff

Z

–

f, d

f

f, d

2

C

00 0010 dfff ffff C, DC, Z

11 1011 dfff ffff C, DC, Z

00 1110 dfff ffff

f, d

00 0110 dfff ffff

Z

BYTE ORIENTED SKIP OPERATIONS

f, d

Decrement f, Skip if 0

Increment f, Skip if 0

1(2)

00

1011 dfff ffff

1111 dfff ffff

1, 2

DECFSZ

INCFSZ

BIT-ORIENTED FILE REGISTER OPERATIONS

f, b

Bit Clear f

Bit Set f

1

01

00bb bfff ffff

01bb bfff ffff

2

BCF

BSF

BIT-ORIENTED SKIP OPERATIONS

BTFSC

BTFSS

f, b

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

01

10bb bfff ffff

11bb bfff ffff

1, 2

LITERAL OPERATIONS

ADDLW

ANDLW

IORLW

MOVLB

MOVLP

MOVLW

SUBLW

XORLW

k

Add literal and W

AND literal with W

Inclusive OR literal with W

Move literal to BSR

Move literal to PCLATH

Move literal to W

1

11

00

11

1110 kkkk kkkk C, DC, Z

1001 kkkk kkkk

1000 kkkk kkkk

0000 001k kkkk

0001 1kkk kkkk

0000 kkkk kkkk

Z

Subtract W from literal

Exclusive OR literal with W

1100 kkkk kkkk C, DC, Z

1010 kkkk kkkk

Z

Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle

is executed as a NOP.

2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one

additional instruction cycle.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 331

PIC16F/LF1826/27

TABLE 28-3: PIC16F/LF1826/27 ENHANCED INSTRUCTION SET (CONTINUED)

14-Bit Opcode

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

MSb

LSb

CONTROL OPERATIONS

BRA

BRW

CALL

CALLW

GOTO

RETFIE

RETLW

RETURN

k

–

k

–

k

–

Relative Branch

Relative Branch with W

Call Subroutine

Call Subroutine with W

Go to address

Return from interrupt

Return with literal in W

Return from Subroutine

2

11

00

10

00

10

00

11

00

001k kkkk kkkk

0000 0000 1011

0kkk kkkk kkkk

0000 0000 1010

1kkk kkkk kkkk

0000 0000 1001

0100 kkkk kkkk

0000 0000 1000

INHERENT OPERATIONS

CLRWDT

NOP

OPTION

RESET

SLEEP

TRIS

–

f

Clear Watchdog Timer

No Operation

Load OPTION_REG register with W

Software device Reset

Go into Standby mode

Load TRIS register with W

1

00

0000 0110 0100 TO, PD

0000 0000 0000

0000 0110 0010

0000 0000 0001

0000 0110 0011 TO, PD

0000 0110 0fff

C-COMPILER OPTIMIZED

ADDFSR n, k

Add Literal k to FSRn

Move Indirect FSRn to W with pre/post inc/dec

modifier, mm

1

11 0001 0nkk kkkk

00 0000 0001 0nmm

kkkk

MOVIW

n mm

Z

2, 3

k[n]

n mm

Move INDFn to W, Indexed Indirect.

Move W to Indirect FSRn with pre/post inc/dec

modifier, mm

1

11 1111 0nkk 1nmm

00 0000 0001 kkkk

2

2, 3

MOVWI

k[n]

Move W to INDFn, Indexed Indirect.

1

11 1111 1nkk

2

Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle

is executed as a NOP.

2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require

one additional instruction cycle.

3: See Table in the MOVIW and MOVWI instruction descriptions.

DS41391C-page 332

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

28.2 Instruction Descriptions

ADDFSR

Add Literal to FSRn

ANDLW

AND literal with W

Syntax:

[ label ] ADDFSR FSRn, k

Syntax:

[ label ] ANDLW

0  k  255

k

Operands:

-32  k  31

n  [ 0, 1]

Operands:

Operation:

Status Affected:

Description:

(W) .AND. (k)  (W)

Operation:

FSR(n) + k  FSR(n)

Z

Status Affected:

Description:

None

The contents of W register are

AND’ed with the eight-bit literal ‘k’.

The result is placed in the W register.

The signed 6-bit literal ‘k’ is added to

the contents of the FSRnH:FSRnL

register pair.

FSRn is limited to the range 0000h -

FFFFh. Moving beyond these bounds

will cause the FSR to wrap around.

ANDWF

AND W with f

ADDLW

Add literal and W

Syntax:

[ label ] ANDWF f,d

Syntax:

[ label ] ADDLW

0  k  255

k

Operands:

0  f  127

d 0,1

Operands:

Operation:

Status Affected:

Description:

(W) + k  (W)

C, DC, Z

Operation:

(W) .AND. (f)  (destination)

Status Affected:

Description:

Z

The contents of the W register are

added to the eight-bit literal ‘k’ and the

result is placed in the W register.

AND the W register with register ‘f’. If

‘d’ is ‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

ASRF

Arithmetic Right Shift

ADDWF

Add W and f

Syntax:

[ label ] ASRF f {,d}

Syntax:

[ label ] ADDWF f,d

Operands:

0  f  127

d [0,1]

Operands:

0  f  127

d 0,1

Operation:

(f<7>) dest<7>

(f<7:1>)  dest<6:0>,

(f<0>)  C,

Operation:

(W) + (f)  (destination)

Status Affected:

Description:

C, DC, Z

Add the contents of the W register

with register ‘f’. If ‘d’ is ‘0’, the result is

stored in the W register. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

Status Affected:

Description:

C, Z

The contents of register ‘f’ are shifted

one bit to the right through the Carry

flag. The MSb remains unchanged. If

‘d’ is ‘0’, the result is placed in W. If ‘d’

is ‘1’, the result is stored back in reg-

ister ‘f’.

ADDWFC

ADD W and CARRY bit to f

C

register f

Syntax:

[ label ] ADDWFC

f {,d}

Operands:

0  f  127

d [0,1]

Operation:

(W) + (f) + (C)  dest

Status Affected:

Description:

C, DC, Z

Add W, the Carry flag and data mem-

ory location ‘f’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed in data memory location ‘f’.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 333

PIC16F/LF1826/27

BTFSC

Bit Test f, Skip if Clear

BCF

Bit Clear f

Syntax:

[ label ] BTFSC f,b

Syntax:

[ label ] BCF f,b

Operands:

0  f  127

0  b  7

Operands:

0  f  127

0  b  7

Operation:

skip if (f<b>) = 0

Operation:

0 (f<b>)

Status Affected:

Description:

None

Status Affected:

Description:

None

If bit ‘b’ in register ‘f’ is ‘1’, the next

instruction is executed.

Bit ‘b’ in register ‘f’ is cleared.

If bit ‘b’, in register ‘f’, is ‘0’, the next

instruction is discarded, and a NOPis

executed instead, making this a

2-cycle instruction.

BTFSS

Bit Test f, Skip if Set

BRA

Relative Branch

Syntax:

[ label ] BTFSS f,b

Syntax:

[ label ] BRA label

[ label ] BRA $+k

Operands:

0  f  127

0  b < 7

Operands:

-256  label - PC + 1  255

-256  k  255

Operation:

skip if (f<b>) = 1

Operation:

(PC) + 1 + k  PC

Status Affected:

Description:

None

Status Affected:

Description:

None

If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is executed.

If bit ‘b’ is ‘1’, then the next

instruction is discarded and a NOPis

executed instead, making this a

2-cycle instruction.

Add the signed 9-bit literal ‘k’ to the

PC. Since the PC will have incre-

mented to fetch the next instruction,

the new address will be PC + 1 + k.

This instruction is a two-cycle instruc-

tion. This branch has a limited range.

BRW

Relative Branch with W

Syntax:

[ label ] BRW

None

Operands:

Operation:

Status Affected:

Description:

(PC) + (W)  PC

None

Add the contents of W (unsigned) to

the PC. Since the PC will have incre-

mented to fetch the next instruction,

the new address will be PC + 1 + (W).

This instruction is a two-cycle instruc-

tion.

BSF

Bit Set f

Syntax:

[ label ] BSF f,b

Operands:

0  f  127

0  b  7

Operation:

1 (f<b>)

Status Affected:

Description:

None

Bit ‘b’ in register ‘f’ is set.

DS41391C-page 334

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

CALL

Call Subroutine

CLRWDT

Clear Watchdog Timer

Syntax:

[ label ] CALL

0  k  2047

k

Syntax:

[ label ] CLRWDT

Operands:

Operation:

Operands:

Operation:

None

(PC)+ 1 TOS,

k  PC<10:0>,

(PCLATH<4:3>)  PC<12:11>

00h  WDT

0 WDT prescaler,

1 TO

1 PD

Status Affected:

Description:

None

Status Affected:

Description:

TO, PD

Call Subroutine. First, return address

(PC + 1) is pushed onto the stack.

The eleven-bit immediate address is

loaded into PC bits <10:0>. The upper

bits of the PC are loaded from

PCLATH. CALLis a two-cycle instruc-

tion.

CLRWDTinstruction resets the Watch-

dog Timer. It also resets the prescaler

of the WDT.

Status bits TO and PD are set.

COMF

Complement f

CALLW

Subroutine Call With W

Syntax:

[ label ] COMF f,d

Syntax:

[ label ] CALLW

Operands:

0  f  127

d  [0,1]

Operands:

Operation:

None

(PC) +1  TOS,

(W)  PC<7:0>,

Operation:

(f)  (destination)

(PCLATH<6:0>) PC<14:8>

Status Affected:

Description:

Z

The contents of register ‘f’ are com-

plemented. If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

Status Affected:

Description:

None

Subroutine call with W. First, the

return address (PC + 1) is pushed

onto the return stack. Then, the con-

tents of W is loaded into PC<7:0>,

and the contents of PCLATH into

PC<14:8>. CALLWis a two-cycle

instruction.

DECF

Decrement f

CLRF

Clear f

Syntax:

[ label ] DECF f,d

Syntax:

[ label ] CLRF

0  f  127

f

Operands:

0  f  127

d  [0,1]

Operands:

Operation:

00h  (f)

1 Z

Operation:

(f) - 1  (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

Decrement register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W

The contents of register ‘f’ are cleared

and the Z bit is set.

register. If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

CLRW

Clear W

Syntax:

[ label ] CLRW

Operands:

Operation:

None

00h  (W)

1 Z

Status Affected:

Description:

Z

W register is cleared. Zero bit (Z) is

set.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 335

PIC16F/LF1826/27

DECFSZ

Decrement f, Skip if 0

INCFSZ

Increment f, Skip if 0

Syntax:

[ label ] DECFSZ f,d

Syntax:

[ label ] INCFSZ f,d

Operands:

0  f  127

d  [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f) - 1  (destination);

skip if result = 0

Operation:

(f) + 1  (destination),

skip if result = 0

Status Affected:

Description:

None

Status Affected:

Description:

None

The contents of register ‘f’ are decre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

The contents of register ‘f’ are incre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

If the result is ‘1’, the next instruction is

executed. If the result is ‘0’, then a

NOPis executed instead, making it a

2-cycle instruction.

If the result is ‘1’, the next instruction is

executed. If the result is ‘0’, a NOPis

executed instead, making it a 2-cycle

instruction.

GOTO

Unconditional Branch

IORLW

Inclusive OR literal with W

Syntax:

[ label ] GOTO

0  k  2047

k

Syntax:

[ label ] IORLW

0  k  255

(W) .OR. k  (W)

Z

k

Operands:

Operation:

Operands:

Operation:

Status Affected:

Description:

k  PC<10:0>

PCLATH<4:3>  PC<12:11>

Status Affected:

Description:

None

The contents of the W register are

OR’ed with the eight-bit literal ‘k’. The

result is placed in the W register.

GOTOis an unconditional branch. The

eleven-bit immediate value is loaded

into PC bits <10:0>. The upper bits of

PC are loaded from PCLATH<4:3>.

GOTOis a two-cycle instruction.

INCF

Increment f

IORWF

Inclusive OR W with f

Syntax:

[ label ] INCF f,d

Syntax:

[ label ] IORWF f,d

Operands:

0  f  127

d  [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f) + 1  (destination)

Operation:

(W) .OR. (f)  (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

The contents of register ‘f’ are incre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

Inclusive OR the W register with regis-

ter ‘f’. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

DS41391C-page 336

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

LSLF

Logical Left Shift

MOVF

Move f

Syntax:

[ label ] LSLF f {,d}

Syntax:

[ label ] MOVF f,d

Operands:

0  f  127

d [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f<7>)  C

Operation:

(f)  (dest)

(f<6:0>)  dest<7:1>

0  dest<0>

Status Affected:

Description:

Z

The contents of register f is moved to

a destination dependent upon the

status of d. If d = 0,

destination is W register. If d = 1, the

destination is file register f itself. d = 1

is useful to test a file register since

status flag Z is affected.

Status Affected:

Description:

C, Z

The contents of register ‘f’ are shifted

one bit to the left through the Carry flag.

A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,

the result is placed in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

Words:

1

C

register f

0

Cycles:

Example:

MOVF

FSR, 0

After Instruction

LSRF

Logical Right Shift

W

Z

=

= 1

value in FSR register

Syntax:

[ label ] LSLF f {,d}

Operands:

0  f  127

d [0,1]

Operation:

0  dest<7>

(f<7:1>)  dest<6:0>,

(f<0>)  C,

Status Affected:

Description:

C, Z

The contents of register ‘f’ are shifted

one bit to the right through the Carry

flag. A ‘0’ is shifted into the MSb. If ‘d’ is

‘0’, the result is placed in W. If ‘d’ is ‘1’,

the result is stored back in register ‘f’.

0

C

register f

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 337

PIC16F/LF1826/27

MOVIW

Move INDFn to W

MOVLP

Move literal to PCLATH

Syntax:

[ label ] MOVIW ++FSRn

[ label ] MOVIW --FSRn

[ label ] MOVIW FSRn++

[ label ] MOVIW FSRn--

[ label ] MOVIW k[FSRn]

[ label ] MOVIW FSRn

Syntax:

[ label ] MOVLP

0  k  127

k  PCLATH

None

k

Operands:

Operation:

Status Affected:

Description:

The seven-bit literal ‘k’ is loaded into the

PCLATH register.

Operands:

Operation:

n  [0,1]

mm  [00, 01, 10, 11].

-32  k  31

If not present, k = 0.

MOVLW

Move literal to W

INDFn  W

Effective address is determined by

Syntax:

[ label ] MOVLW

0  k  255

k  (W)

k

•

FSR + 1 (preincrement)

FSR - 1 (predecrement)

FSR + k (relative offset)

Operands:

Operation:

Status Affected:

Description:

None

After the Move, the FSR value will be

either:

The eight-bit literal ‘k’ is loaded into W

register. The “don’t cares” will assem-

ble as ‘0’s.

•

FSR + 1 (all increments)

FSR - 1 (all decrements)

Unchanged

Words:

1

Status Affected:

Z

Cycles:

Example:

MOVLW

0x5A

Mode

Syntax

mm

00

01

10

11

After Instruction

Preincrement

Predecrement

Postincrement

Postdecrement

++FSRn

--FSRn

FSRn++

FSRn--

W

=

0x5A

MOVWF

Move W to f

[ label ] MOVWF

0  f  127

(W)  (f)

Syntax:

f

Operands:

Operation:

Status Affected:

Description:

This instruction is used to move data

between W and one of the indirect

registers (INDFn). Before/after this

move, the pointer (FSRn) is updated by

pre/post incrementing/decrementing it.

None

Move data from W register to register

‘f’.

Words:

1

Note: The INDFn registers are not

physical registers. Any instruction that

accesses an INDFn register actually

accesses the register at the address

specified by the FSRn.

Cycles:

Example:

1

MOVWF OPTION

Before Instruction

OPTION =

0xFF

0x4F

W

=

FSRn is limited to the range 0000h -

FFFFh. Incrementing/decrementing it

beyond these bounds will cause it to wrap

around.

After Instruction

OPTION =

W

0x4F

=

The increment/decrement operation on

FSRn WILL NOT affect any Status bits.

MOVLB

Move literal to BSR

Syntax:

[ label ] MOVLB

0  k  15

k  BSR

None

k

Operands:

Operation:

Status Affected:

Description:

The five-bit literal ‘k’ is loaded into the

Bank Select Register (BSR).

DS41391C-page 338

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

NOP

No Operation

MOVWI

Move W to INDFn

Syntax:

[ label ] NOP

Syntax:

[ label ] MOVWI ++FSRn

[ label ] MOVWI --FSRn

[ label ] MOVWI FSRn++

[ label ] MOVWI FSRn--

[ label ] MOVWI k[FSRn]

[ label ] MOVWI FSRn

Operands:

Operation:

Status Affected:

Description:

Words:

None

No operation

None

No operation.

Operands:

Operation:

n  [0,1]

mm  [00, 01, 10, 11].

-32  k  31

1

Cycles:

1

If not present, k = 0.

Example:

NOP

W  INDFn

Effective address is determined by

•

FSR + 1 (preincrement)

FSR - 1 (predecrement)

FSR + k (relative offset)

Load OPTION_REG Register

with W

OPTION

After the Move, the FSR value will be

either:

•

Syntax:

[ label ] OPTION

None

FSR + 1 (all increments)

FSR - 1 (all decrements)

Operands:

Operation:

Status Affected:

Description:

Unchanged

(W)  OPTION_REG

None

Status Affected:

None

Move data from W register to

OPTION_REG register.

Mode

Syntax

mm

00

01

10

11

Preincrement

Predecrement

Postincrement

Postdecrement

++FSRn

--FSRn

FSRn++

FSRn--

RESET

Software Reset

Syntax:

[ label ] RESET

Operands:

Operation:

None

Description:

This instruction is used to move data

between W and one of the indirect

registers (INDFn). Before/after this

move, the pointer (FSRn) is updated by

pre/post incrementing/decrementing it.

Execute a device Reset. Resets the

nRI flag of the PCON register.

Status Affected:

Description:

None

This instruction provides a way to

execute a hardware Reset by soft-

ware.

Note: The INDFn registers are not

physical registers. Any instruction that

accesses an INDFn register actually

accesses the register at the address

specified by the FSRn.

FSRn is limited to the range 0000h -

FFFFh. Incrementing/decrementing it

beyond these bounds will cause it to wrap

around.

The increment/decrement operation on

FSRn WILL NOT affect any Status bits.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 339

PIC16F/LF1826/27

RETURN

Return from Subroutine

RETFIE

Syntax:

Return from Interrupt

[ label ] RETFIE

None

Syntax:

[ label ] RETURN

None

Operands:

Operation:

Status Affected:

Description:

Operands:

Operation:

TOS  PC

None

TOS  PC,

1 GIE

Status Affected:

Description:

None

Return from subroutine. The stack is

POPed and the top of the stack (TOS)

is loaded into the program counter.

This is a two-cycle instruction.

Return from Interrupt. Stack is POPed

and Top-of-Stack (TOS) is loaded in

the PC. Interrupts are enabled by

setting Global

Interrupt Enable bit, GIE

(INTCON<7>). This is a two-cycle

instruction.

Words:

1

Cycles:

Example:

2

RETFIE

After Interrupt

PC

=

TOS

GIE =

1

RLF

Rotate Left f through Carry

RETLW

Syntax:

Return with literal in W

Syntax:

Operands:

[ label ]

RLF f,d

[ label ] RETLW

0  k  255

k

0  f  127

d  [0,1]

Operands:

Operation:

k  (W);

TOS  PC

Operation:

See description below

C

Status Affected:

Description:

Status Affected:

Description:

None

The contents of register ‘f’ are rotated

one bit to the left through the Carry

flag. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

The W register is loaded with the eight

bit literal ‘k’. The program counter is

loaded from the top of the stack (the

return address). This is a two-cycle

instruction.

C

Register f

Words:

1

2

Cycles:

Example:

Words:

1

CALL TABLE;W contains table

;offset value

Cycles:

Example:

•

;W now has table value

RLF

REG1,0

TABLE

Before Instruction

REG1

C

=

1110 0110

0

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

•

After Instruction

REG1

W

C

=

1110 0110

1100 1100

1

RETLW kn ; End of table

Before Instruction

W

=

0x07

After Instruction

W

=

value of k8

DS41391C-page 340

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

SUBLW

Subtract W from literal

RRF

Rotate Right f through Carry

Syntax:

[ label ] SUBLW

0 k 255

k

Syntax:

[ label ] RRF f,d

Operands:

Operation:

Status Affected:

Description:

Operands:

0  f  127

d  [0,1]

k - (W) W)

C, DC, Z

Operation:

See description below

C

The W register is subtracted (2’s com-

plement method) from the eight-bit

literal ‘k’. The result is placed in the W

register.

Status Affected:

Description:

The contents of register ‘f’ are rotated

one bit to the right through the Carry

flag. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

C = 0

W  k

C = 1

W  k

C

Register f

DC = 0

DC = 1

W<3:0>  k<3:0>

W<3:0>  k<3:0>

SUBWF

Subtract W from f

SLEEP

Enter Sleep mode

[ label ] SLEEP

None

Syntax:

[ label ] SUBWF f,d

Syntax:

Operands:

0 f 127

d  [0,1]

Operands:

Operation:

00h  WDT,

0 WDT prescaler,

1 TO,

Operation:

(f) - (W) destination)

Status Affected:

Description:

C, DC, Z

0 PD

Subtract (2’s complement method) W

register from register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W

register. If ‘d’ is ‘1’, the result is stored

back in register ‘f.

Status Affected:

Description:

TO, PD

The power-down Status bit, PD is

cleared. Time-out Status bit, TO is

set. Watchdog Timer and its pres-

caler are cleared.

C = 0

W  f

The processor is put into Sleep mode

with the oscillator stopped.

C = 1

W  f

DC = 0

DC = 1

W<3:0>  f<3:0>

W<3:0>  f<3:0>

SUBWFB

Subtract W from f with Borrow

Syntax:

SUBWFB f {,d}

Operands:

0  f  127

d  [0,1]

Operation:

(f) – (W) – (B) dest

Status Affected:

Description:

C, DC, Z

Subtract W and the BORROW flag

(CARRY) from register ‘f’ (2’s comple-

ment method). If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 341

PIC16F/LF1826/27

SWAPF

Swap Nibbles in f

XORLW

Exclusive OR literal with W

Syntax:

[ label ] SWAPF f,d

Syntax:

[ label ] XORLW

0 k 255

k

Operands:

0  f  127

d  [0,1]

Operands:

Operation:

Status Affected:

Description:

(W) .XOR. k W)

Z

Operation:

(f<3:0>)  (destination<7:4>),

(f<7:4>)  (destination<3:0>)

The contents of the W register are

XOR’ed with the eight-bit

literal ‘k’. The result is placed in the

W register.

Status Affected:

Description:

None

The upper and lower nibbles of regis-

ter ‘f’ are exchanged. If ‘d’ is ‘0’, the

result is placed in the W register. If ‘d’

is ‘1’, the result is placed in register ‘f’.

XORWF

Exclusive OR W with f

TRIS

Load TRIS Register with W

Syntax:

[ label ] XORWF f,d

Syntax:

[ label ] TRIS f

5  f  7

Operands:

0  f  127

d  [0,1]

Operands:

Operation:

Status Affected:

Description:

(W)  TRIS register ‘f’

None

Operation:

(W) .XOR. (f) destination)

Status Affected:

Description:

Z

Move data from W register to TRIS

register.

When ‘f’ = 5, TRISA is loaded.

When ‘f’ = 6, TRISB is loaded.

Exclusive OR the contents of the W

register with register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W register. If ‘d’

is ‘1’, the result is stored back in regis-

ter ‘f’.

DS41391C-page 342

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

29.0 ELECTRICAL SPECIFICATIONS

(†)

Absolute Maximum Ratings

Ambient temperature under bias....................................................................................................... -40°C to +125°C

Storage temperature ........................................................................................................................ -65°C to +150°C

Voltage on VDD with respect to VSS, PIC16F1826/27 ........................................................................ -0.3V to +6.5V

Voltage on VDD with respect to VSS, PIC16LF1826/27 ...................................................................... -0.3V to +4.0V

Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V

Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)

Total power dissipation⁽¹⁾...............................................................................................................................800 mW

Maximum current out of VSS pin ...................................................................................................................... 95 mA

Maximum current into VDD pin ......................................................................................................................... 70 mA

Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA

Maximum output current sunk by any I/O pin....................................................................................................25 mA

Maximum output current sourced by any I/O pin .............................................................................................. 25 mA

Maximum current sunk by all ports⁽²⁾, -40°C  TA  +85°C for industrial ........................................................ 200 mA

Maximum current sunk by all ports⁽²⁾, -40°C  TA  +125°C for extended........................................................ 90 mA

Maximum current sourced by all ports⁽²⁾, 40°C  TA  +85°C for industrial ................................................... 140 mA

Maximum current sourced by all ports⁽²⁾, -40°C  TA  +125°C for extended................................................... 65 mA

Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL).

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for

extended periods may affect device reliability.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 343

PIC16F/LF1826/27

FIGURE 29-1:

PIC16F1826/27 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C

5.5

2.5

1.8

0

4

10

16

32

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 29-1 for each Oscillator mode’s supported frequencies.

FIGURE 29-2:

PIC16LF1826/27 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C

3.6

2.5

1.8

0

4

10

16

32

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 29-1 for each Oscillator mode’s supported frequencies.

DS41391C-page 344

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 29-3:

HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE

125

± 5%

± 3%

85

60

25

± 2%

0

-20

± 5%

-40

1.8

2.0

2.5

3.5

4.0

VDD (V)

4.5

5.0

5.5

3.0

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 345

PIC16F/LF1826/27

29.1 DC Characteristics: PIC16F/LF1826/27-I/E (Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

PIC16LF1826/27

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F1826/27

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param.

No.

Sym.

Characteristic

Supply Voltage

Min.

Typ† Max. Units

Conditions

D001

VDD

PIC16LF1826/27

1.8

2.3

—

3.6

V

FOSC  16 MHz:

FOSC  32 MHz (NOTE 2)

D001

PIC16F1826/27

1.8

2.3

—

5.5

V

FOSC  16 MHz:

FOSC  32 MHz (NOTE 2)

D002*

VDR

RAM Data Retention Voltage⁽¹⁾

PIC16LF1826/27

PIC16F1826/27

Power-on Reset Release Voltage

Power-on Reset Rearm Voltage

PIC16LF1826/27

1.5

1.7

—

V

Device in Sleep mode

D002*

D003

VPOR*

1.6

VPORR*

—

0.8

1.7

—

V

Device in Sleep mode

PIC16F1826/27

VADFVR

Fixed Voltage Reference Voltage for

ADC, Initial Accuracy

-7

-8

-7

-8

-7

-8

—

6

%

1.024V, VDD  2.5V, 85°C (NOTE 3)

1.024V, VDD  2.5V, 125°C (NOTE 3)

2.048V, VDD  2.5V, 85°C

2.048V, VDD  2.5V, 125°C

4.096V, VDD  4.75V, 85°C

4.096V, VDD  4.75V, 125°C

D003A VCDAFVR

Fixed Voltage Reference Voltage for

Comparator and DAC, Initial Accu-

racy

-11

—

7

%

1.024V, VDD  2.5V, 85°C

1.024V, VDD  2.5V, 125°C

2.048V, VDD  2.5V, 85°C

2.048V, VDD  2.5V, 125°C

4.096V, VDD  4.75V, 85°C

4.096V, VDD  4.75V, 125°C

D003C* TCVFVR

Temperature Coefficient, Fixed

Voltage Reference

—

-130

0.270

—

ppm/

°C

D003D* VFVR/

VIN

Line Regulation, Fixed Voltage

Reference

—

%/V

D004*

SVDD

VDD Rise Rate to ensure internal

Power-on Reset signal

0.05

V/ms See Section 7.1 “Power-on Reset

(POR)” for details.

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

2: PLL required for 32 MHz operation.

3: For proper operation, the minimum value of the ADC positive voltage reference must be 1.8V or greater. When selecting

the FVR or the VREF+ pin as the source of the ADC positive voltage reference, be aware that the voltage must be 1.8V or

greater.

DS41391C-page 346

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 29-4:

POR AND POR REARM WITH SLOW RISING VDD

VDD

VPOR

VPORR

VSS

NPOR

POR REARM

VSS

(3)

(2)

TPOR

TVLOW

Note 1: When NPOR is low, the device is held in Reset.

2: TPOR 1 s typical.

3: TVLOW 2.7 s typical.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 347

PIC16F/LF1826/27

29.2 DC Characteristics: PIC16F/LF1826/27-I/E (Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

PIC16LF1826/27

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F1826/27

Param

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Conditions

Device

Min.

Typ†

Max.

Units

No.

Characteristics

VDD

Note

(1, 2)

Supply Current (IDD)

D010

—

7.0

9.0

10.0

24

A

1.8

3.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

13

16

FOSC = 32 kHz

LP Oscillator mode, -40°C  TA  +85°C

17

FOSC = 32 kHz

LP Oscillator mode, -40°C  TA  +125°C

18

D010

40

FOSC = 32 kHz

LP Oscillator mode

-40°C  TA  +85°C

30

45

32

50

22

40

FOSC = 32 kHz

LP Oscillator mode

-40°C  TA  +125°C

28

42

33

48

D011

110

220

160

280

390

290

520

450

770

930

32

FOSC = 1 MHz

XT Oscillator mode

190

480

255

475

690

400

700

645

1100

1320

—

FOSC = 1 MHz

XT Oscillator mode

D012

FOSC = 4 MHz

XT Oscillator mode

FOSC = 4 MHz

XT Oscillator mode

D013

FOSC = 500 kHz

EC Oscillator mode, Medium-power mode

60

—

100

180

225

FOSC = 500 kHz

EC Oscillator mode

Low-power mode

180

310

350

*

These parameters are characterized but not tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins as inputs, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: 8 MHz internal RC oscillator with 4x PLL enabled.

4: 8 MHz crystal oscillator with 4x PLL enabled.

5: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended

by the formula IR = VDD/2REXT (mA) with REXT in k.

DS41391C-page 348

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

29.2 DC Characteristics: PIC16F/LF1826/27-I/E (Industrial, Extended) (Continued)

Standard Operating Conditions (unless otherwise stated)

PIC16LF1826/27

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F1826/27

Param

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Conditions

Device

Min.

Typ†

Max.

Units

No.

D014

Characteristics

VDD

Note

(1, 2)

Supply Current (IDD)

—

260

450

A

1.8

3.0

FOSC = 4 MHz

EC Oscillator mode,

Medium-power mode

475

750

—

475

850

980

3.6

4.0

21

A

mA

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

FOSC = 4 MHz

EC Oscillator mode

Medium-power mode

735

1200

1390

10

D015

FOSC = 31 kHz

LFINTOSC mode

13

FOSC = 31 kHz

LFINTOSC mode

35

27

40

28

45

D016

110

150

210

270

0.8

1.3

1.0

1.8

2.0

1.2

2.0

1.7

2.9

3.1

FOSC = 500 kHz

MFINTOSC mode

175

250

345

425

1.1

FOSC = 500 kHz

MFINTOSC mode

D017*

FOSC = 8 MHz

HFINTOSC mode

1.7

FOSC = 8 MHz

HFINTOSC mode

1.48

2.2

2.8

D018

FOSC = 16 MHz

HFINTOSC mode

2.0

2.75

2.23

4.3

FOSC = 16 MHz

HFINTOSC mode

4.6

*

These parameters are characterized but not tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins as inputs, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: 8 MHz internal RC oscillator with 4x PLL enabled.

4: 8 MHz crystal oscillator with 4x PLL enabled.

5: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended

by the formula IR = VDD/2REXT (mA) with REXT in k.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 349

PIC16F/LF1826/27

29.2 DC Characteristics: PIC16F/LF1826/27-I/E (Industrial, Extended) (Continued)

Standard Operating Conditions (unless otherwise stated)

PIC16LF1826/27

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F1826/27

Param

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Conditions

Device

Min.

Typ†

Max.

Units

No.

Characteristics

VDD

Note

(1, 2)

Supply Current (IDD)

D019

D020

D021

—

4.0

4.4

3.9

4.2

3.3

3.6

5.3

6.0

410

710

430

730

860

mA

A

3.0

3.6

3.0

5.0

3.0

3.6

3.0

5.0

1.8

3.0

1.8

3.0

5.0

FOSC = 32 MHz

HFINTOSC mode (Note 3)

—

FOSC = 32 MHz

HFINTOSC mode (Note 3)

—

FOSC = 32 MHz

HS Oscillator mode (Note 4)

7.0

7.5

7.3

8.0

560

990

695

1060

1350

FOSC = 32 MHz

HS Oscillator mode (Note 4)

FOSC = 4 MHz

EXTRC mode (Note 5)

A

FOSC = 4 MHz

EXTRC mode (Note 5)

A

*

These parameters are characterized but not tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins as inputs, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: 8 MHz internal RC oscillator with 4x PLL enabled.

4: 8 MHz crystal oscillator with 4x PLL enabled.

5: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended

by the formula IR = VDD/2REXT (mA) with REXT in k.

DS41391C-page 350

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

29.3 DC Characteristics: PIC16F/LF1826/27-I/E (Power-Down)

Standard Operating Conditions (unless otherwise stated)

PIC16LF1826/27

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F1826/27

Param

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Conditions

Max.

Device Characteristics

Min.

Typ†

Units

No.

+85°C +125°C

VDD

Note

(2)

Power-down Base Current (IPD)

D022

—

0.02

0.03

15

1.0

2.0

35

5.0

7.0

50

A

mA

A

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

WDT, BOR, FVR, and T1OSC

disabled, all Peripherals Inactive

D022

WDT, BOR, FVR, and T1OSC

disabled, all Peripherals Inactive

18

40

60

19

45

70

D023

0.5

0.8

16

3.0

4.0

35

7.0

9.0

50

LPWDT Current (Note 1)

19

40

60

20

45

70

D023A

8.5

32

23

35

FVR current (Note 1)

26

40

50

66

39

72

80

70

120

14

110

17

D024

8.1

34

BOR Current (Note 1)

57

70

67

100

3.0

4.0

35

115

7.0

9.0

45

D025

0.6

0.8

16

T1OSC Current (Note 1)

21

40

50

25

45

55

D026

0.1

16

3.0

4.0

35

7.0

9.0

45

A/D Current (Note 1, Note 3), no

conversion in progress

A/D Current (Note 1, Note 3), no

conversion in progress

21

40

50

25

50

60

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Legend:

TBD = To Be Determined

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins set to inputs state and tied to VDD.

3: A/D oscillator source is FRC.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 351

PIC16F/LF1826/27

29.3 DC Characteristics: PIC16F/LF1826/27-I/E (Power-Down) (Continued)

Standard Operating Conditions (unless otherwise stated)

PIC16LF1826/27

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F1826/27

Param

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Conditions

Max.

Device Characteristics

Min.

Typ†

Units

No.

+85°C +125°C

VDD

Note

(2)

Power-down Base Current (IPD)

D026A*

—

250

280

3.5

7

—

6

—

8

A

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

1.8

3.0

A/D Current (Note 1, Note 3),

conversion in progress

A/D Current (Note 1, Note 3),

conversion in progress

D027

Cap Sense Low Power

Oscillator mode (Note 1)

10

16

19

22

8

14

26

30

35

10

15

26

30

33

15

20

40

70

90

15

16

4.3

5.8

6.3

4.2

6

Cap Sense Low Power

Oscillator mode (Note 1)

D027A

Cap Sense Medium Power

Oscillator mode (Note 1)

12

18

24

27

10

14

28

58

70

11

12

7.4

9.7

10.4

6

Cap Sense Medium Power

Oscillator mode (Note 1)

D027B

Cap Sense High Power

Oscillator mode (Note 1)

10

17

Cap Sense High Power

Oscillator mode (Note 1)

41

50

D028

6.9

7.0

Comparator Current, Low Power

mode, one comparator enabled

(Note 1)

—

9.0

9.3

9.8

7.0

7.2

20

21

22

12

13

24

25

27

16

17

A

1.8

3.0

5.0

1.8

3.0

Comparator Current, Low Power

mode, one comparator enabled

(Note 1)

D028A

Comparator Current, Low Power

mode, two comparators enabled

(Note 1)

—

9.4

9.7

21

22

23

25

26

28

A

1.8

3.0

5.0

Comparator Current, Low Power

mode, two comparators enabled

(Note 1)

11.4

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Legend:

TBD = To Be Determined

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins set to inputs state and tied to VDD.

3: A/D oscillator source is FRC.

DS41391C-page 352

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

29.3 DC Characteristics: PIC16F/LF1826/27-I/E (Power-Down) (Continued)

Standard Operating Conditions (unless otherwise stated)

PIC16LF1826/27

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Standard Operating Conditions (unless otherwise stated)

PIC16F1826/27

Param

Operating temperature

-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Conditions

Max.

Device Characteristics

Min.

Typ†

Units

No.

+85°C +125°C

VDD

Note

(2)

Power-down Base Current (IPD)

D028B

—

24

25

32

35

40

45

A

1.8

3.0

Comparator Current, High Power

mode, one comparator enabled

(Note 1)

D028B

—

27

28

29

40

41

43

44

45

50

53

55

80

83

86

90

95

55

58

A

1.8

3.0

5.0

1.8

3.0

1.8

3.0

5.0

Comparator Current, High Power

mode, one comparator enabled

(Note 1)

60

D028C

90

Comparator Current, High Power

mode, two comparators enabled

95

100

105

110

Comparator Current, High Power

mode, two comparators enabled

(Note 1)

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Legend:

TBD = To Be Determined

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins set to inputs state and tied to VDD.

3: A/D oscillator source is FRC.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 353

PIC16F/LF1826/27

29.4 DC Characteristics: PIC16F/LF1826/27-I/E

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No.

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

VIL

Input Low Voltage

I/O PORT:

D030

D030A

D031

with TTL buffer

—

0.8

V

4.5V  VDD  5.5V

0.15 VDD

0.2 VDD

0.3 VDD

0.8

1.8V  VDD  4.5V

2.0V  VDD  5.5V

with Schmitt Trigger buffer

2

with I C™ levels

with SMBus™ levels

2.7V  VDD  5.5V

(1)

D032

D033

MCLR, OSC1 (RC mode)

0.2 VDD

0.3 VDD

OSC1 (HS mode)

Input High Voltage

I/O ports:

VIH

—

D040

with TTL buffer

2.0

V

4.5V  VDD 5.5V

1.8V  VDD  4.5V

D040A

0.25 VDD +

0.8

D041

with Schmitt Trigger buffer

0.8 VDD

0.7 VDD

2.1

—

V

2.0V  VDD  5.5V

2.7V  VDD  5.5V

2

with I C™ levels

with SMBus™ levels

MCLR

D042

0.8 VDD

0.7 VDD

0.9 VDD

D043A

D043B

OSC1 (HS mode)

OSC1 (RC mode)

(Note 1)

(2)

IIL

Input Leakage Current

D060

I/O ports

—

± 5

± 125

nA

VSS  VPIN  VDD, Pin at high-

impedance at 85°C

± 5

± 1000

± 200

nA 125°C

(3)

D061

MCLR

± 50

nA

A

V

VSS  VPIN  VDD at 85°C

IPUR

VOL

Weak Pull-up Current

D070*

25

100

140

200

300

VDD = 3.3V, VPIN = VSS

VDD = 5.0V, VPIN = VSS

(4)

Output Low Voltage

D080

I/O ports

IOL = 8mA, VDD = 5V

IOL = 6mA, VDD = 3.3V

IOL = 1.8mA, VDD = 1.8V

—

0.6

Legend:

TBD = To Be Determined

These parameters are characterized but not tested.

*

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external

clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

4: Including OSC2 in CLKOUT mode.

DS41391C-page 354

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

29.4 DC Characteristics: PIC16F/LF1826/27-I/E (Continued)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No.

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

(4)

VOH

Output High Voltage

D090

I/O ports

IOH = 3.5mA, VDD = 5V

IOH = 3mA, VDD = 3.3V

IOH = 1mA, VDD = 1.8V

VDD - 0.7

—

V

Capacitive Loading Specs on Output Pins

D101*

COSC2 OSC2 pin

—

15

50

pF

In XT, HS and LP modes when

external clock is used to drive

OSC1

D101A* CIO

All I/O pins

TBD = To Be Determined

These parameters are characterized but not tested.

—

Legend:

*

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external

clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

4: Including OSC2 in CLKOUT mode.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 355

PIC16F/LF1826/27

29.5 Memory Programming Requirements

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

DC CHARACTERISTICS

Param

Sym.

No.

Characteristic

Program Memory

Min.

Typ†

Max.

Units

Conditions

Programming Specifications

D110

D111

VIHH

IDDP

Voltage on MCLR/VPP/RA5 pin

8.0

—

9.0

10

V

(Note 3, Note 4)

Supply Current during

Programming

mA

D112

D113

VDD for Bulk Erase

2.7

—

VDD

max.

V

VPEW

VDD for Write or Row Erase

VDD

min.

VDD

max.

D114

D115

IPPPGM Current on MCLR/VPP during Erase/

Write

—

1.0

mA

IDDPGM Current on VDD during Erase/Write

—

5.0

Data EEPROM Memory

D116

D117

ED

Byte Endurance

100K

—

E/W -40C to +85C

VDD

min.

VDD

max.

VDRW VDD for Read/Write

V

D118

D119

TDEW Erase/Write Cycle Time

TRETD Characteristic Retention

—

4.0

—

5.0

—

ms

40

Year Provided no other

specifications are violated

D120

TREF

Number of Total Erase/Write

Cycles before Refresh

1M

10M

—

E/W -40°C to +85°C

(2)

Program Flash Memory

Cell Endurance

D121

D122

EP

10K

—

E/W -40C to +85C (Note 1)

VDD

min.

VDD

max.

VPR

VDD for Read

V

D123

D124

TIW

Self-timed Write Cycle Time

—

2

2.5

—

ms

TRETD Characteristic Retention

40

—

Year Provided no other

specifications are violated

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Self-write and Block Erase.

2: Refer to Section 11.2 “Using the Data EEPROM” for a more detailed discussion on data EEPROM

endurance.

3: Required only if single-supply programming is disabled.

4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be

placed between the ICD 2 and target system when programming or debugging with the ICD 2.

DS41391C-page 356

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

29.6 Thermal Considerations

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

Param

No.

Sym.

Characteristic

Typ.

Units

Conditions

18-pin PDIP package

TH01

^JA

Thermal Resistance Junction to Ambient

TBD

150

—

C/W

C

18-pin SOIC package

20-pin SSOP package

28-pin UQFN 4x4mm package

28-pin QFN 6x6mm package

18-pin SPDIP package

TH02

^JC

Thermal Resistance Junction to Case

18-pin SOIC package

20-pin SSOP package

28-pin UQFN 4x4mm package

28-pin QFN 6x6mm package

TH03

TH04

TH05

TH06

TH07

Legend:

TJMAX

PD

Maximum Junction Temperature

Power Dissipation

W

PD = PINTERNAL + PI/O

(1)

PINTERNAL Internal Power Dissipation

—

W

PINTERNAL = IDD x VDD

PI/O

I/O Power Dissipation

Derated Power

—

W

PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH))

(2)

PDER

—

W

PDER = PDMAX (TJ - TA)/JA

TBD = To Be Determined

Note 1: IDD is current to run the chip alone without driving any load on the output pins.

2: TA = Ambient Temperature

3: TJ = Junction Temperature

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 357

PIC16F/LF1826/27

29.7

Timing Parameter Symbology

The timing parameter symbols have been created with

one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase letters (pp) and their meanings:

pp

cc

T

Time

CCP1

CLKOUT

CS

osc

rd

OSC1

RD

ck

cs

di

rw

sc

ss

t0

RD or WR

SCKx

SS

SDIx

do

dt

SDO

Data in

I/O PORT

MCLR

T0CKI

T1CKI

WR

io

t1

mc

wr

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (High-impedance)

Low

Valid

L

High-impedance

FIGURE 29-5:

LOAD CONDITIONS

Load Condition

CL

VSS

Legend: CL = 50 pF for all pins, 15 pF for

OSC2 output

DS41391C-page 358

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

29.8 AC Characteristics: PIC16F/LF1826/27-I/E

FIGURE 29-6:

CLOCK TIMING

Q4

Q1

Q2

Q3

Q4

Q1

OSC1/CLKIN

OS02

OS04

OS03

OSC2/CLKOUT

(LP,XT,HS Modes)

OSC2/CLKOUT

(CLKOUT Mode)

TABLE 29-1: CLOCK OSCILLATOR TIMING REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C  TA  +125°C

Param

Sym.

No.

Characteristic

Min.

Typ†

Max.

Units

Conditions

(1)

OS01

FOSC

TOSC

TCY

External CLKIN Frequency

DC

—

0.5

4

MHz EC Oscillator mode (low)

MHz EC Oscillator mode (medium)

MHz EC Oscillator mode (high)

—

32

—

4

(1)

Oscillator Frequency

32.768

—

kHz

LP Oscillator mode

0.1

1

MHz XT Oscillator mode

—

4

MHz HS Oscillator mode, VDD  2.7V

MHz HS Oscillator mode, VDD > 2.7V

MHz RC Oscillator mode

1

—

20

4

DC

27

—

(1)

OS02

External CLKIN Period

—



s

ns

s

ns

s

ns

LP Oscillator mode

XT Oscillator mode

HS Oscillator mode

EC Oscillator mode

LP Oscillator mode

XT Oscillator mode

HS Oscillator mode

RC Oscillator mode

TCY = FOSC/4

250

50

—



—



31.25

—



(1)

Oscillator Period

30.5

—

10,000

1,000

—

DC

—



250

50

—

250

125

2

—

(1)

OS03

Instruction Cycle Time

—

OS04*

TosH,

TosL

External CLKIN High,

External CLKIN Low

—

LP oscillator

100

20

—

XT oscillator

—

HS oscillator

OS05*

TosR,

TosF

External CLKIN Rise,

External CLKIN Fall

0

—

LP oscillator

0

—



XT oscillator

0

—



HS oscillator

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing code.

Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-

sumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external

clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 359

PIC16F/LF1826/27

TABLE 29-2: OSCILLATOR PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C TA +125°C

Param

Sym.

No.

Freq.

Tolerance

Characteristic

Min. Typ† Max. Units

Conditions

OS08

HFOSC

Internal Calibrated HFINTOSC

Frequency

2%

3%

5%

2%

3%

5%

—

16.0

500

5

—

8

MHz 0°C  TA  +60°C, VDD  2.5V

MHz 60°C  TA  +85°C, VDD  2.5V

MHz -40°C  TA  +125°C

kHz 0°C  TA  +60°C, VDD  2.5V

kHz 60°C  TA  +85°C, VDD  2.5V

kHz -40°C  TA  +125°C

s

(2)

OS08A MFOSC

Internal Calibrated MFINTOSC

(2)

Frequency

OS10* TIOSC ST HFINTOSC

Wake-up from Sleep Start-up Time

MFINTOSC

Wake-up from Sleep Start-up Time

—

20

30

s

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing

code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current

consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an

external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 F and 0.01 F values in parallel are recommended.

3: By design.

TABLE 29-3: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.7V TO 5.5V)

Param

Sym.

Characteristic

Min.

Typ†

Max.

Units Conditions

No.

F10

FOSC Oscillator Frequency Range

4

16

—

8

32

MHz

ms

F11

FSYS On-Chip VCO System Frequency

F12

F13*

TRC

PLL Start-up Time (Lock Time)

—

2

CLK CLKOUT Stability (Jitter)

-0.25%

+0.25%

%

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3V, 25C unless otherwise stated. These parameters are for design guidance

only and are not tested.

DS41391C-page 360

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 29-7:

CLKOUT AND I/O TIMING

Cycle

Write

Q4

Fetch

Q1

Read

Q2

Execute

Q3

FOSC

OS12

OS11

OS20

OS21

CLKOUT

OS19

OS13

OS18

OS16

OS17

I/O pin

(Input)

OS14

OS15

I/O pin

(Output)

New Value

Old Value

OS18, OS19

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 361

PIC16F/LF1826/27

TABLE 29-4: CLKOUT AND I/O TIMING PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param

No.

Sym.

Characteristic

Min.

Typ† Max. Units

Conditions

OS11 TosH2ckL FOSC to CLKOUT ⁽¹⁾

OS12 TosH2ckH FOSC to CLKOUT ⁽¹⁾

OS13 TckL2ioV CLKOUT to Port out valid⁽¹⁾

—

70

72

20

ns VDD = 3.3-5.0V

ns

OS14 TioV2ckH Port input valid before CLKOUT⁽¹⁾

OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid

TOSC + 200 ns

—

50

—

70*

—

ns

—

ns VDD = 3.3-5.0V

OS16 TosH2ioI

Fosc (Q2 cycle) to Port input invalid

50

(I/O in hold time)

OS17 TioV2osH Port input valid to Fosc(Q2 cycle)

20

—

ns

(I/O in setup time)

OS18 TioR

OS19 TioF

Port output rise time⁽²⁾

—

40

15

72

32

ns

VDD = 1.8V

VDD = 3.3-5.0V

Port output fall time⁽²⁾

—

28

15

55

30

VDD = 1.8V

VDD = 3.3-5.0V

OS20* Tinp

OS21* Tioc

INT pin input high or low time

25

—

ns

Interrupt-on-change new input level

time

*

†

These parameters are characterized but not tested.

Data in “Typ” column is at 3.0V, 25C unless otherwise stated.

Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.

2: Includes OSC2 in CLKOUT mode.

FIGURE 29-8:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

VDD

MCLR

30

Internal

POR

33

PWRT

Time-out

32

OSC

Start-Up Time

(1)

Internal Reset

Watchdog Timer

(1)

Reset

31

34

I/O pins

Note 1: Asserted low.

DS41391C-page 362

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 29-9:

BROWN-OUT RESET TIMING AND CHARACTERISTICS

VDD

VBOR and VHYST

VBOR

(Device in Brown-out Reset)

(Device not in Brown-out Reset)

37

Reset

(1)

33

(due to BOR)

Note 1: 64 ms delay only if PWRTE bit in the Configuration Word 1 is programmed to ‘0’.

2 ms delay if PWRTE = 0and VREGEN = 1.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 363

PIC16F/LF1826/27

TABLE 29-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param

No.

Sym.

TMCL

Characteristic

Min. Typ† Max. Units

Conditions

30

MCLR Pulse Width (low)

2

5

—

s VDD = 3.3-5V, -40°C to +85°C

s VDD = 3.3-5V

31

TWDTLP Low-Power Watchdog Timer

Time-out Period (No Prescaler)

10

18

27

ms VDD = 3.3V-5V

32

TOST

Oscillator Start-up Timer Period^{(1), (2)}

—

1024

65

—

140

2.0

Tosc (Note 3)

33*

34*

TPWRT Power-up Timer Period, PWRTE = 0 40

ms

TIOZ

I/O high-impedance from MCLR Low

or Watchdog Timer Reset

—

s

35

VBOR

Brown-out Reset Voltage

2.38

1.80

2.5

1.9

2.65

2.05

V

BORV=2.5V

BORV=1.9V

36*

37*

VHYST

Brown-out Reset Hysteresis

0

1

25

3

50

5

mV -40°C to +85°C

TBORDC Brown-out Reset DC Response

Time

s VDD  VBOR

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are

based on characterization data for that particular oscillator type under standard operating conditions with the

device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or

higher than expected current consumption. All devices are tested to operate at “min” values with an external

clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no

clock) for all devices.

2: By design.

3: Period of the slower clock.

4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 F and 0.01 F values in parallel are recommended.

FIGURE 29-10:

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

40

41

42

T1CKI

45

46

49

47

TMR0 or

TMR1

DS41391C-page 364

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 29-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param

No.

Sym.

TT0H

Characteristic

T0CKI High Pulse Width

Min.

Typ†

Max.

Units

Conditions

40*

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5 TCY + 20

—

ns

10

0.5 TCY + 20

10

41*

42*

TT0L

TT0P

T0CKI Low Pulse Width

T0CKI Period

Greater of:

20 or TCY + 40

N

ns N = prescale value

(2, 4, ..., 256)

45*

TT1H

T1CKI High Synchronous, No Prescaler

0.5 TCY + 20

15

—

ns

Time

Synchronous,

with Prescaler

Asynchronous

30

—

ns

46*

47*

TT1L

TT1P

T1CKI Low Synchronous, No Prescaler

0.5 TCY + 20

Time

Synchronous, with Prescaler

Asynchronous

15

30

T1CKI Input Synchronous

Period

Greater of:

30 or TCY + 40

N

ns N = prescale value

(1, 2, 4, 8)

Asynchronous

60

—

ns

48

FT1

Timer1 Oscillator Input Frequency Range

(oscillator enabled by setting bit T1OSCEN)

32.4

32.768

33.1

kHz

49*

TCKEZTMR1 Delay from External Clock Edge to Timer

Increment

2 TOSC

—

7 TOSC

—

Timers in Sync

mode

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

FIGURE 29-11:

CAPTURE/COMPARE/PWM TIMINGS (CCP)

CCPx

(Capture mode)

CC01

CC02

CC03

Note: Refer to Figure 29.5 for load conditions.

TABLE 29-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C  TA  +125°C

Param

No.

Sym.

Characteristic

Min.

Typ† Max. Units

Conditions

CC01* TccL CCPx Input Low Time

CC02* TccH CCPx Input High Time

CC03* TccP CCPx Input Period

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5TCY + 20

—

ns

20

0.5TCY + 20

20

3TCY + 40

N

N = prescale value (1, 4 or 16)

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 365

PIC16F/LF1826/27

TABLE 29-8: PIC16F/LF1826/27 A/D CONVERTER (ADC) CHARACTERISTICS:

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

Param

No.

Sym.

Characteristic

Min.

Typ†

Max. Units

Conditions

AD01 NR

AD02 EIL

AD03 EDL

Resolution

—

10

±1.7

±1

bit

Integral Error

LSb VREF = 3.0V

Differential Error

LSb No missing codes

VREF = 3.0V

AD04 EOFF Offset Error

—

±2

±1.5

VDD

VREF

50

LSb VREF = 3.0V

AD05 EGN Gain Error

(3)

AD06 VREF Reference Voltage

AD07 VAIN Full-Scale Range

1.8

VSS

—

V

VREF = (VREF+ minus VREF-) (NOTE 5)

AD08 ZAIN Recommended Impedance of

Analog Voltage Source

k Can go higher if external 0.01F capacitor is

present on input pin.

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: Total Absolute Error includes integral, differential, offset and gain errors.

2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

3: ADC VREF is from external VREF, VDD pin or FVR, whichever is selected as reference input.

4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification

includes any such leakage from the ADC module.

5: FVR voltage selected must be 2.048V or 4.096V.

TABLE 29-9: PIC16F/LF1826/27 A/D CONVERSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C  TA  +125°C

Param

Sym.

No.

Characteristic

Min.

Typ†

Max. Units

Conditions

AD130* TAD

A/D Clock Period

1.0

—

9.0

6.0

s

TOSC-based

ADCS<1:0> = 11(ADRC mode)

A/D Internal RC Oscillator

Period

1.6

AD131 TCNV Conversion Time (not including

—

11

—

TAD Set GO/DONE bit to conversion

complete

(1)

Acquisition Time)

AD132* TACQ Acquisition Time

—

5.0

s

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: The ADRES register may be read on the following TCY cycle.

DS41391C-page 366

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 29-12:

PIC16F/LF1826/27 A/D CONVERSION TIMING (NORMAL MODE)

BSF ADCON0, GO

1 TCY

(1)

(TOSC/2

AD134

Q4

)

AD131

AD130

A/D CLK

7

6

5

4

3

2

1

0

A/D Data

ADRES

NEW_DATA

1 TCY

OLD_DATA

ADIF

GO

DONE

Sampling Stopped

AD132

Sample

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEPinstruction to be executed.

FIGURE 29-13:

PIC16F/LF1826/27 A/D CONVERSION TIMING (SLEEP MODE)

BSF ADCON0, GO

AD134

Q4

(1)

(TOSC/2 + TCY

1 TCY

)

AD131

AD130

A/D CLK

A/D Data

7

6

5

3

2

1

0

4

NEW_DATA

1 TCY

OLD_DATA

ADRES

ADIF

GO

DONE

Sampling Stopped

AD132

Sample

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEPinstruction to be executed.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 367

PIC16F/LF1826/27

TABLE 29-10: COMPARATOR SPECIFICATIONS

Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated).

Param

No.

Sym.

Characteristics

Input Offset Voltage

Min.

Typ.

Max. Units

Comments

CM01

VIOFF

—

0

±7.5

—

±60

VDD

—

mV

V

CM02

VICM

Input Common Mode Voltage

Common Mode Rejection Ratio

Response Time Rising Edge

Response Time Falling Edge

Response Time Rising Edge

Response Time Falling Edge

CM03

CMRR

—

50

dB

CM04A

CM04B

CM04C

CM04D

CM05

400

200

1200

550

—

800

400

—

ns High Power Mode, Note 1

ns Low Power Mode, Note 1

TRESP

—

ns

Low Power Mode, Note 1

TMC2OV Comparator Mode Change to

Output Valid*

10

s

CM06

CHYSTER Comparator Hysterisis

—

65

—

mV Note 2

*

These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions

from VSS to VDD.

2: Comparator Hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled.

TABLE 29-11: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS

Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated).

Param

No.

Sym.

Characteristics

Step Size⁽²⁾

Min.

Typ.

Max.

Units

Comments

DAC01*

DAC02*

DAC03*

DAC04*

*

CLSB

—

VDD/32

—

 1/2

—

V

LSb



CACC

CR

Absolute Accuracy

Unit Resistor Value (R)

Settling Time⁽¹⁾

TBD

—

CST

10

s

These parameters are characterized but not tested.

Legend: TBD = To Be Determined

Note 1: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’.

TABLE 29-12: PIC16F/LF1826/27 LOW DROPOUT (LDO) REGULATOR CHARACTERISTICS:

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

Param

No.

Sym.

Characteristic

Min.

Typ†

Max. Units

Conditions

LD001

LD002

LDO Regulation Voltage

LDO External Capacitor

—

3.2

—

1

V

0.1

F

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

DS41391C-page 368

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 29-14:

USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

CK

DT

US121

US122

US120

Refer to Figure 29-5 for load conditions.

Note:

TABLE 29-13: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C TA +125°C

Param.

Symbol

No.

Characteristic

Min.

Max.

Units Conditions

US120 TCKH2DTV SYNC XMIT (Master and Slave)

Clock high to data-out valid

3.0-5.5V

1.8-5.5V

3.0-5.5V

1.8-5.5V

3.0-5.5V

1.8-5.5V

—

80

100

45

ns

US121 TCKRF

Clock out rise time and fall time

(Master mode)

50

US122 TDTRF

Data-out rise time and fall time

45

50

FIGURE 29-15:

USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

CK

DT

US125

US126

Note: Refer to Figure 29-5 for load conditions.

TABLE 29-14: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C TA +125°C

Param.

Symbol

No.

Characteristic

Min.

Max. Units

Conditions

US125 TDTV2CKL SYNC RCV (Master and Slave)

Data-hold before CK  (DT hold time)

10

15

—

ns

US126 TCKL2DTL Data-hold after CK  (DT hold time)

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 369

PIC16F/LF1826/27

FIGURE 29-16:

SPI MASTER MODE TIMING (CKE = 0, SMP = 0)

SSx

SP70

SCKx

(CKP = 0)

SP71

SP72

SP78

SP79

SCKx

(CKP = 1)

SP78

LSb

SP80

MSb

bit 6 - - - - - -1

SDOx

SDIx

SP75, SP76

bit 6 - - - -1

MSb In

LSb In

SP74

SP73

Note: Refer to Figure 29-5 for load conditions.

FIGURE 29-17:

SPI MASTER MODE TIMING (CKE = 1, SMP = 1)

SSx

SP81

SCKx

(CKP = 0)

SP71

SP73

SP72

SP79

SCKx

(CKP = 1)

SP80

SP78

LSb

MSb

bit 6 - - - - - -1

SDOx

SDIx

SP75, SP76

bit 6 - - - -1

MSb In

SP74

Note: Refer to Figure 29-5 for load conditions.

LSb In

DS41391C-page 370

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 29-18:

SPI SLAVE MODE TIMING (CKE = 0)

SSx

SP70

SCKx

(CKP = 0)

SP83

SP71

SP72

SP78

SP79

SCKx

(CKP = 1)

SP78

LSb

SP79

SP80

MSb

SDOx

SDIx

bit 6 - - - - - -1

SP77

SP75, SP76

bit 6 - - - -1

MSb In

SP74

SP73

LSb In

Note: Refer to Figure 29-5 for load conditions.

FIGURE 29-19:

SPI SLAVE MODE TIMING (CKE = 1)

SP82

SP70

SSx

SP83

SCKx

(CKP = 0)

SP72

SP71

SCKx

(CKP = 1)

SP80

MSb

bit 6 - - - - - -1

LSb

SDOx

SDIx

SP77

SP75, SP76

bit 6 - - - -1

MSb In

SP74

LSb In

Note: Refer to Figure 29-5 for load conditions.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 371

PIC16F/LF1826/27

TABLE 29-15: SPI MODE REQUIREMENTS

Param

No.

Symbol

Characteristic

Min.

Typ† Max. Units Conditions

SP70* TSSL2SCH, SSx to SCKx or SCKx input

TCY

—

ns

TSSL2SCL

SP71* TSCH

SP72* TSCL

SCKx input high time (Slave mode)

SCKx input low time (Slave mode)

TCY + 20

100

—

ns

SP73* TDIV2SCH, Setup time of SDIx data input to SCKx edge

TDIV2SCL

SP74* TSCH2DIL, Hold time of SDIx data input to SCKx edge

TSCL2DIL

100

—

ns

SP75* TDOR

SDO data output rise time

3.0-5.5V

1.8-5.5V

—

10

—

Tcy

10

25

10

—

10

25

10

—

25

50

25

50

25

50

25

50

145

—

ns

SP76* TDOF

SDOx data output fall time

SP77* TSSH2DOZ SSx to SDOx output high-impedance

SP78* TSCR

SCKx output rise time

(Master mode)

3.0-5.5V

1.8-5.5V

SP79* TSCF

SCKx output fall time (Master mode)

SP80* TSCH2DOV, SDOx data output valid after

TSCL2DOV SCKx edge

3.0-5.5V

1.8-5.5V

SP81* TDOV2SCH, SDOx data output setup to SCKx edge

TDOV2SCL

SP82* TSSL2DOV SDOx data output valid after SS edge

—

50

—

ns

SP83* TSCH2SSH, SSx after SCKx edge

1.5TCY + 40

TSCL2SSH

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

FIGURE 29-20:

I²C™ BUS START/STOP BITS TIMING

SCLx

SP93

SP91

SP90

SP92

SDAx

Stop

Condition

Start

Condition

Note: Refer to Figure 29-5 for load conditions.

DS41391C-page 372

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

FIGURE 29-21:

I²C™ BUS DATA TIMING

SP100

SP103

SP102

SP101

SCLx

SP90

SP106

SP107

SP92

SP91

SDAx

In

SP110

SP109

SDAx

Out

Note: Refer to Figure 29-5 for load conditions.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 373

PIC16F/LF1826/27

TABLE 29-16: I²C™ BUS DATA REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min.

Max. Units

Conditions

SP100* THIGH

Clock high time

100 kHz mode

4.0

—

s

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

0.6

Device must operate at a

minimum of 10 MHz

SSPx module

100 kHz mode

1.5TCY

4.7

—

SP101* TLOW

Clock low time

s

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

1.3

—

s

Device must operate at a

minimum of 10 MHz

SSPx module

100 kHz mode

400 kHz mode

1.5TCY

—

ns

SP102* TR

SP103* TF

SDAx and SCLx

rise time

1000

20 + 0.1CB 300

CB is specified to be from

10-400 pF

SDAx and SCLx fall 100 kHz mode

—

250

ns

time

400 kHz mode

20 + 0.1CB 250

CB is specified to be from

10-400 pF

SP106* THD:DAT Data input hold time 100 kHz mode

400 kHz mode

0

—

0.9

—

ns

s

ns

s

0

SP107* TSU:DAT Data input setup

time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

250

100

—

(Note 2)

(Note 1)

—

SP109* TAA

Output valid from

clock

3500

—

SP110* TBUF

Bus free time

4.7

1.3

—

Time the bus must be free

before a new transmission

can start

—

SP111 CB

Bus capacitive loading

—

400

pF

*

These parameters are characterized but not tested.

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.

2: A Fast mode (400 kHz) I²C™ bus device can be used in a Standard mode (100 kHz) I²C bus system, but

the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does

not stretch the low period of the SCLx signal. If such a device does stretch the low period of the SCLx sig-

nal, it must output the next data bit to the SDAx line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according

to the Standard mode I²C bus specification), before the SCLx line is released.

DS41391C-page 374

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

TABLE 29-17: CAP SENSE OSCILLATOR SPECIFICATIONS

Param.

No.

Symbol

Characteristic

Min.

Typ†

Max. Units

Conditions

CS01

ISRC

Current Source

High

-3

-15

-3

A

-8

Medium

Low

-0.8

-0.1

2.5

0.6

0.1

—

-1.5

-0.3

7.5

-0.4

14

A

CS02

ISNK

Current Sink

High

A

Medium

Low

1.5

2.9

0.6

—

A

0.25

0.8

A

CS03 VCTH

CS04 VCTL

Cap Threshold

mV

—

0.4

—

CS05

VCHYST CAP HYSTERISIS

(VCTH - VCTL)

High

350

250

175

525

375

300

725

500

425

Medium

Low

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

FIGURE 29-22:

CAP SENSE OSCILLATOR

VCTH

VCTL

ISRC

Enabled

ISNK

Enabled

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 375

PIC16F/LF1826/27

NOTES:

DS41391C-page 376

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

30.0 DC AND AC

CHARACTERISTICS GRAPHS

AND CHARTS

Graphs and charts are not available at this time.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 377

PIC16F/LF1826/27

NOTES:

DS41391C-page 378

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

31.1 MPLAB Integrated Development

Environment Software

31.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers and dsPIC^®digital signal

controllers are supported with a full range of software

and hardware development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16/32-bit

microcontroller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• A single graphical interface to all debugging tools

- Simulator

• Compilers/Assemblers/Linkers

- MPLAB C Compiler for Various Device

Families

- Programmer (sold separately)

- In-Circuit Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- HI-TECH C for Various Device Families

- MPASM^TMAssembler

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Customizable data windows with direct edit of

contents

• Simulators

• High-level source code debugging

• Mouse over variable inspection

- MPLAB SIM Software Simulator

• Emulators

• Drag and drop variables from source to watch

windows

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers

• Extensive on-line help

• Integration of select third party tools, such as

IAR C Compilers

- MPLAB ICD 3

- PICkit™ 3 Debug Express

• Device Programmers

- PICkit™ 2 Programmer

- MPLAB PM3 Device Programmer

The MPLAB IDE allows you to:

• Edit your source files (either C or assembly)

• One-touch compile or assemble, and download to

emulator and simulator tools (automatically

updates all project information)

• Low-Cost Demonstration/Development Boards,

Evaluation Kits, and Starter Kits

• Debug using:

- Source files (C or assembly)

- Mixed C and assembly

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 379

PIC16F/LF1826/27

31.2 MPLAB C Compilers for Various

Device Families

31.5 MPLINK Object Linker/

MPLIB Object Librarian

The MPLAB C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC18,

PIC24 and PIC32 families of microcontrollers and the

dsPIC30 and dsPIC33 families of digital signal control-

lers. These compilers provide powerful integration

capabilities, superior code optimization and ease of

use.

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

31.3 HI-TECH C for Various Device

Families

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

The HI-TECH C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC

family of microcontrollers and the dsPIC family of digital

signal controllers. These compilers provide powerful

integration capabilities, omniscient code generation

and ease of use.

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

31.6 MPLAB Assembler, Linker and

Librarian for Various Device

Families

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The compilers include a macro assembler, linker, pre-

processor, and one-step driver, and can run on multiple

platforms.

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC devices. MPLAB C Compiler uses

the assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

31.4 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich directive set

• Flexible macro language

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• MPLAB IDE compatibility

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

source files

• Directives that allow complete control over the

assembly process

DS41391C-page 380

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

31.7 MPLAB SIM Software Simulator

31.9 MPLAB ICD 3 In-Circuit Debugger

System

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC^®DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

MPLAB ICD 3 In-Circuit Debugger System is Micro-

chip's most cost effective high-speed hardware

debugger/programmer for Microchip Flash Digital Sig-

nal Controller (DSC) and microcontroller (MCU)

devices. It debugs and programs PIC^®Flash microcon-

trollers and dsPIC^®DSCs with the powerful, yet easy-

to-use graphical user interface of MPLAB Integrated

Development Environment (IDE).

The MPLAB ICD 3 In-Circuit Debugger probe is con-

nected to the design engineer's PC using a high-speed

USB 2.0 interface and is connected to the target with a

connector compatible with the MPLAB ICD 2 or MPLAB

REAL ICE systems (RJ-11). MPLAB ICD 3 supports all

MPLAB ICD 2 headers.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

31.10 PICkit 3 In-Circuit Debugger/

Programmer and

31.8 MPLAB REAL ICE In-Circuit

Emulator System

PICkit 3 Debug Express

The MPLAB PICkit 3 allows debugging and program-

ming of PIC^®and dsPIC^®Flash microcontrollers at a

most affordable price point using the powerful graphical

user interface of the MPLAB Integrated Development

Environment (IDE). The MPLAB PICkit 3 is connected

to the design engineer's PC using a full speed USB

interface and can be connected to the target via an

Microchip debug (RJ-11) connector (compatible with

MPLAB ICD 3 and MPLAB REAL ICE). The connector

uses two device I/O pins and the reset line to imple-

ment in-circuit debugging and In-Circuit Serial Pro-

gramming™.

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC^®Flash MCUs and dsPIC^®Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated Development Environment (IDE),

included with each kit.

The emulator is connected to the design engineer’s PC

using a high-speed USB 2.0 interface and is connected

to the target with either a connector compatible with in-

circuit debugger systems (RJ11) or with the new high-

speed, noise tolerant, Low-Voltage Differential Signal

(LVDS) interconnection (CAT5).

The PICkit 3 Debug Express include the PICkit 3, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

The emulator is field upgradable through future firmware

downloads in MPLAB IDE. In upcoming releases of

MPLAB IDE, new devices will be supported, and new

features will be added. MPLAB REAL ICE offers signifi-

cant advantages over competitive emulators including

low-cost, full-speed emulation, run-time variable

watches, trace analysis, complex breakpoints, a rugge-

dized probe interface and long (up to three meters) inter-

connection cables.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 381

PIC16F/LF1826/27

31.11 PICkit 2 Development

Programmer/Debugger and

PICkit 2 Debug Express

31.13 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

The PICkit™ 2 Development Programmer/Debugger is

a low-cost development tool with an easy to use inter-

face for programming and debugging Microchip’s Flash

families of microcontrollers. The full featured

Windows^®programming interface supports baseline

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

(PIC10F,

PIC12F5xx,

PIC16F5xx),

midrange

(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,

dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit

microcontrollers, and many Microchip Serial EEPROM

products. With Microchip’s powerful MPLAB Integrated

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

Development Environment (IDE) the PICkit™

2

enables in-circuit debugging on most PIC^®microcon-

trollers. In-Circuit-Debugging runs, halts and single

steps the program while the PIC microcontroller is

embedded in the application. When halted at a break-

point, the file registers can be examined and modified.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

The PICkit 2 Debug Express include the PICkit 2, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

®

for analog filter design, KEELOQ security ICs, CAN,

IrDA^®, PowerSmart battery management, SEEVAL^®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

31.12 MPLAB PM3 Device Programmer

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an MMC card for file

storage and data applications.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

DS41391C-page 382

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

32.0 PACKAGING INFORMATION

32.1 Package Marking Information

18-Lead PDIP

Example

XXXXXXXXXXXXXXXXX

YYWWNNN

PIC16F1826-I/P

1010017

18-Lead SOIC (.300”)

Example

XXXXXXXXXXXX

PIC16C1826-I

/SO

1010017

YYWWNNN

20-Lead SSOP

Example

XXXXXXXXXXX

PIC16F1827

-I/SS

1010017

YYWWNNN

28-Lead QFN/UQFN

Example

XXXXXXXX

YYWWNNN

16F1827

/ML

1010017

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

*

)

3

e

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

*

Standard PICmicro^®device marking consists of Microchip part number, year code, week code and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 383

PIC16F/LF1826/27

32.2 Package Details

The following sections give the technical details of the packages.

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢅꢉꢇꢐꢑꢂꢃꢌꢑꢄꢇꢒꢈꢓꢇMꢇꢔꢕꢕꢇꢖꢌꢉꢇꢗꢘꢆꢙꢇꢚꢈꢎꢐꢈꢛ

ꢜꢘꢋꢄ 3ꢋꢉꢀ&ꢍꢈꢀ'ꢋ!&ꢀꢌ"ꢉꢉꢈꢅ&ꢀꢓꢆꢌ4ꢆꢑꢈꢀ#ꢉꢆ*ꢄꢅꢑ!(ꢀꢓꢇꢈꢆ!ꢈꢀ!ꢈꢈꢀ&ꢍꢈꢀꢔꢄꢌꢉꢋꢌꢍꢄꢓꢀꢃꢆꢌ4ꢆꢑꢄꢅꢑꢀꢐꢓꢈꢌꢄ%ꢄꢌꢆ&ꢄꢋꢅꢀꢇꢋꢌꢆ&ꢈ#ꢀꢆ&ꢀ

ꢍ&&ꢓ255***ꢂ'ꢄꢌꢉꢋꢌꢍꢄꢓꢂꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢄꢅꢑ

ꢀ

N

NOTE 1

E1

2

3

1

D

E

A2

A

L

c

A1

b1

e

b

eB

6ꢅꢄ&!

ꢒꢄ'ꢈꢅ!ꢄꢋꢅꢀ9ꢄ'ꢄ&!

ꢚ7,8.ꢐ

7:ꢔ

ꢁ<

ꢂꢁꢕꢕꢀ1ꢐ,

M

ꢔꢚ7

ꢔꢗ;

7"')ꢈꢉꢀꢋ%ꢀꢃꢄꢅ!

ꢃꢄ&ꢌꢍ

7

ꢈ

ꢗ

ꢙꢋꢓꢀ&ꢋꢀꢐꢈꢆ&ꢄꢅꢑꢀꢃꢇꢆꢅꢈ

M

ꢂꢎꢁꢕ

ꢂꢁꢛꢘ

M

ꢔꢋꢇ#ꢈ#ꢀꢃꢆꢌ4ꢆꢑꢈꢀꢙꢍꢄꢌ4ꢅꢈ!!

1ꢆ!ꢈꢀ&ꢋꢀꢐꢈꢆ&ꢄꢅꢑꢀꢃꢇꢆꢅꢈ

ꢐꢍꢋ"ꢇ#ꢈꢉꢀ&ꢋꢀꢐꢍꢋ"ꢇ#ꢈꢉꢀ>ꢄ#&ꢍ

ꢔꢋꢇ#ꢈ#ꢀꢃꢆꢌ4ꢆꢑꢈꢀ>ꢄ#&ꢍ

: ꢈꢉꢆꢇꢇꢀ9ꢈꢅꢑ&ꢍ

ꢙꢄꢓꢀ&ꢋꢀꢐꢈꢆ&ꢄꢅꢑꢀꢃꢇꢆꢅꢈ

9ꢈꢆ#ꢀꢙꢍꢄꢌ4ꢅꢈ!!

6ꢓꢓꢈꢉꢀ9ꢈꢆ#ꢀ>ꢄ#&ꢍ

ꢗꢎ

ꢗꢁ

.

.ꢁ

ꢒ

9

ꢌ

)ꢁ

)

ꢈ1

ꢂꢁꢁꢘ

ꢂꢕꢁꢘ

ꢂ-ꢕꢕ

ꢂꢎꢖꢕ

ꢂ<<ꢕ

ꢂꢁꢁꢘ

ꢂꢕꢕ<

ꢂꢕꢖꢘ

ꢂꢕꢁꢖ

M

ꢂꢁ-ꢕ

M

ꢂ-ꢁꢕ

ꢂꢎꢘꢕ

ꢂꢛꢕꢕ

ꢂꢁ-ꢕ

ꢂꢕꢁꢕ

ꢂꢕ?ꢕ

ꢂꢕꢁ<

M

ꢂ-ꢎꢘ

ꢂꢎ<ꢕ

ꢂꢛꢎꢕ

ꢂꢁꢘꢕ

ꢂꢕꢁꢖ

ꢂꢕꢜꢕ

ꢂꢕꢎꢎ

ꢂꢖ-ꢕ

9ꢋ*ꢈꢉꢀ9ꢈꢆ#ꢀ>ꢄ#&ꢍ

: ꢈꢉꢆꢇꢇꢀꢝꢋ*ꢀꢐꢓꢆꢌꢄꢅꢑꢀꢀꢏ

ꢜꢘꢋꢄꢊ

ꢁꢂ ꢃꢄꢅꢀꢁꢀ ꢄ!"ꢆꢇꢀꢄꢅ#ꢈ$ꢀ%ꢈꢆ&"ꢉꢈꢀ'ꢆꢊꢀ ꢆꢉꢊ(ꢀ)"&ꢀ'"!&ꢀ)ꢈꢀꢇꢋꢌꢆ&ꢈ#ꢀ*ꢄ&ꢍꢄꢅꢀ&ꢍꢈꢀꢍꢆ&ꢌꢍꢈ#ꢀꢆꢉꢈꢆꢂ

ꢎꢂ ꢏꢀꢐꢄꢑꢅꢄ%ꢄꢌꢆꢅ&ꢀ,ꢍꢆꢉꢆꢌ&ꢈꢉꢄ!&ꢄꢌꢂ

-ꢂ ꢒꢄ'ꢈꢅ!ꢄꢋꢅ!ꢀꢒꢀꢆꢅ#ꢀ.ꢁꢀ#ꢋꢀꢅꢋ&ꢀꢄꢅꢌꢇ"#ꢈꢀ'ꢋꢇ#ꢀ%ꢇꢆ!ꢍꢀꢋꢉꢀꢓꢉꢋ&ꢉ"!ꢄꢋꢅ!ꢂꢀꢔꢋꢇ#ꢀ%ꢇꢆ!ꢍꢀꢋꢉꢀꢓꢉꢋ&ꢉ"!ꢄꢋꢅ!ꢀ!ꢍꢆꢇꢇꢀꢅꢋ&ꢀꢈ$ꢌꢈꢈ#ꢀꢂꢕꢁꢕ/ꢀꢓꢈꢉꢀ!ꢄ#ꢈꢂ

ꢖꢂ ꢒꢄ'ꢈꢅ!ꢄꢋꢅꢄꢅꢑꢀꢆꢅ#ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢄꢅꢑꢀꢓꢈꢉꢀꢗꢐꢔ.ꢀ0ꢁꢖꢂꢘꢔꢂ

1ꢐ,2 1ꢆ!ꢄꢌꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅꢂꢀꢙꢍꢈꢋꢉꢈ&ꢄꢌꢆꢇꢇꢊꢀꢈ$ꢆꢌ&ꢀ ꢆꢇ"ꢈꢀ!ꢍꢋ*ꢅꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ!ꢂ

ꢔꢄꢌꢉꢋꢌꢍꢄꢓ ꢙꢈꢌꢍꢅꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢄꢅꢑ ,ꢕꢖꢞꢕꢕꢜ1

DS41391C-page 384

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇ!ꢖꢅꢉꢉꢇ"ꢏꢋꢉꢌꢑꢄꢇꢒ!"ꢓꢇMꢇ#ꢌꢆꢄ$ꢇ%&'ꢕꢇꢖꢖꢇꢗꢘꢆꢙꢇꢚ!"ꢐ(ꢛ

ꢜꢘꢋꢄ 3ꢋꢉꢀ&ꢍꢈꢀ'ꢋ!&ꢀꢌ"ꢉꢉꢈꢅ&ꢀꢓꢆꢌ4ꢆꢑꢈꢀ#ꢉꢆ*ꢄꢅꢑ!(ꢀꢓꢇꢈꢆ!ꢈꢀ!ꢈꢈꢀ&ꢍꢈꢀꢔꢄꢌꢉꢋꢌꢍꢄꢓꢀꢃꢆꢌ4ꢆꢑꢄꢅꢑꢀꢐꢓꢈꢌꢄ%ꢄꢌꢆ&ꢄꢋꢅꢀꢇꢋꢌꢆ&ꢈ#ꢀꢆ&ꢀ

ꢍ&&ꢓ255***ꢂ'ꢄꢌꢉꢋꢌꢍꢄꢓꢂꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢄꢅꢑ

D

N

E

E1

NOTE 1

1

2

3

b

e

α

h

c

φ

A2

A

β

A1

L

L1

6ꢅꢄ&!

ꢔꢚ99ꢚꢔ.ꢙ.ꢝꢐ

ꢒꢄ'ꢈꢅ!ꢄꢋꢅꢀ9ꢄ'ꢄ&!

ꢔꢚ7

7:ꢔ

ꢔꢗ;

7"')ꢈꢉꢀꢋ%ꢀꢃꢄꢅ!

ꢃꢄ&ꢌꢍ

7

ꢈ

ꢁ<

ꢁꢂꢎꢜꢀ1ꢐ,

: ꢈꢉꢆꢇꢇꢀ8ꢈꢄꢑꢍ&

ꢔꢋꢇ#ꢈ#ꢀꢃꢆꢌ4ꢆꢑꢈꢀꢙꢍꢄꢌ4ꢅꢈ!!

ꢐ&ꢆꢅ#ꢋ%%ꢀꢀꢏ

ꢗ

M

ꢎꢂꢕꢘ

ꢕꢂꢁꢕ

M

ꢎꢂ?ꢘ

M

ꢕꢂ-ꢕ

ꢗꢎ

ꢗꢁ

.

: ꢈꢉꢆꢇꢇꢀ>ꢄ#&ꢍ

ꢁꢕꢂ-ꢕꢀ1ꢐ,

ꢔꢋꢇ#ꢈ#ꢀꢃꢆꢌ4ꢆꢑꢈꢀ>ꢄ#&ꢍ

: ꢈꢉꢆꢇꢇꢀ9ꢈꢅꢑ&ꢍ

,ꢍꢆ'%ꢈꢉꢀ@ꢋꢓ&ꢄꢋꢅꢆꢇA

3ꢋꢋ&ꢀ9ꢈꢅꢑ&ꢍ

.ꢁ

ꢒ

ꢍ

ꢜꢂꢘꢕꢀ1ꢐ,

ꢁꢁꢂꢘꢘꢀ1ꢐ,

ꢕꢂꢎꢘ

ꢕꢂꢖꢕ

M

ꢕꢂꢜꢘ

ꢁꢂꢎꢜ

9

3ꢋꢋ&ꢓꢉꢄꢅ&

3ꢋꢋ&ꢀꢗꢅꢑꢇꢈ

9ꢈꢆ#ꢀꢙꢍꢄꢌ4ꢅꢈ!!

9ꢈꢆ#ꢀ>ꢄ#&ꢍ

ꢔꢋꢇ#ꢀꢒꢉꢆ%&ꢀꢗꢅꢑꢇꢈꢀꢙꢋꢓ

ꢔꢋꢇ#ꢀꢒꢉꢆ%&ꢀꢗꢅꢑꢇꢈꢀ1ꢋ&&ꢋ'

9ꢁ

ꢀ

ꢁꢂꢖꢕꢀꢝ.3

ꢕꢟ

ꢕꢂꢎꢕ

ꢕꢂ-ꢁ

ꢘꢟ

M

<ꢟ

ꢌ

)

ꢁ

ꢕꢂ--

ꢕꢂꢘꢁ

ꢁꢘꢟ

ꢂ

ꢘꢟ

ꢁꢘꢟ

ꢜꢘꢋꢄꢊ

ꢁꢂ ꢃꢄꢅꢀꢁꢀ ꢄ!"ꢆꢇꢀꢄꢅ#ꢈ$ꢀ%ꢈꢆ&"ꢉꢈꢀ'ꢆꢊꢀ ꢆꢉꢊ(ꢀ)"&ꢀ'"!&ꢀ)ꢈꢀꢇꢋꢌꢆ&ꢈ#ꢀ*ꢄ&ꢍꢄꢅꢀ&ꢍꢈꢀꢍꢆ&ꢌꢍꢈ#ꢀꢆꢉꢈꢆꢂ

ꢎꢂ ꢏꢀꢐꢄꢑꢅꢄ%ꢄꢌꢆꢅ&ꢀ,ꢍꢆꢉꢆꢌ&ꢈꢉꢄ!&ꢄꢌꢂ

-ꢂ ꢒꢄ'ꢈꢅ!ꢄꢋꢅ!ꢀꢒꢀꢆꢅ#ꢀ.ꢁꢀ#ꢋꢀꢅꢋ&ꢀꢄꢅꢌꢇ"#ꢈꢀ'ꢋꢇ#ꢀ%ꢇꢆ!ꢍꢀꢋꢉꢀꢓꢉꢋ&ꢉ"!ꢄꢋꢅ!ꢂꢀꢔꢋꢇ#ꢀ%ꢇꢆ!ꢍꢀꢋꢉꢀꢓꢉꢋ&ꢉ"!ꢄꢋꢅ!ꢀ!ꢍꢆꢇꢇꢀꢅꢋ&ꢀꢈ$ꢌꢈꢈ#ꢀꢕꢂꢁꢘꢀ''ꢀꢓꢈꢉꢀ!ꢄ#ꢈꢂ

ꢖꢂ ꢒꢄ'ꢈꢅ!ꢄꢋꢅꢄꢅꢑꢀꢆꢅ#ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢄꢅꢑꢀꢓꢈꢉꢀꢗꢐꢔ.ꢀ0ꢁꢖꢂꢘꢔꢂ

1ꢐ,2 1ꢆ!ꢄꢌꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅꢂꢀꢙꢍꢈꢋꢉꢈ&ꢄꢌꢆꢇꢇꢊꢀꢈ$ꢆꢌ&ꢀ ꢆꢇ"ꢈꢀ!ꢍꢋ*ꢅꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ!ꢂ

ꢝ.32 ꢝꢈ%ꢈꢉꢈꢅꢌꢈꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅ(ꢀ"!"ꢆꢇꢇꢊꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ(ꢀ%ꢋꢉꢀꢄꢅ%ꢋꢉ'ꢆ&ꢄꢋꢅꢀꢓ"ꢉꢓꢋ!ꢈ!ꢀꢋꢅꢇꢊꢂ

ꢔꢄꢌꢉꢋꢌꢍꢄꢓ ꢙꢈꢌꢍꢅꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢄꢅꢑ ,ꢕꢖꢞꢕꢘꢁ1

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 385

PIC16F/LF1826/27

DS41391C-page 386

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

)ꢕꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇ!*+ꢌꢑ,ꢇ!ꢖꢅꢉꢉꢇ"ꢏꢋꢉꢌꢑꢄꢇꢒ!!ꢓꢇMꢇ'&ꢔꢕꢇꢖꢖꢇꢗꢘꢆꢙꢇꢚ!!"ꢈꢛꢇ

ꢜꢘꢋꢄ 3ꢋꢉꢀ&ꢍꢈꢀ'ꢋ!&ꢀꢌ"ꢉꢉꢈꢅ&ꢀꢓꢆꢌ4ꢆꢑꢈꢀ#ꢉꢆ*ꢄꢅꢑ!(ꢀꢓꢇꢈꢆ!ꢈꢀ!ꢈꢈꢀ&ꢍꢈꢀꢔꢄꢌꢉꢋꢌꢍꢄꢓꢀꢃꢆꢌ4ꢆꢑꢄꢅꢑꢀꢐꢓꢈꢌꢄ%ꢄꢌꢆ&ꢄꢋꢅꢀꢇꢋꢌꢆ&ꢈ#ꢀꢆ&ꢀ

ꢍ&&ꢓ255***ꢂ'ꢄꢌꢉꢋꢌꢍꢄꢓꢂꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢄꢅꢑ

D

N

E

E1

NOTE 1

1

2

e

b

c

A2

A

φ

A1

L1

L

6ꢅꢄ&!

ꢔꢚ99ꢚꢔ.ꢙ.ꢝꢐ

ꢒꢄ'ꢈꢅ!ꢄꢋꢅꢀ9ꢄ'ꢄ&!

ꢔꢚ7

7:ꢔ

ꢔꢗ;

7"')ꢈꢉꢀꢋ%ꢀꢃꢄꢅ!

ꢃꢄ&ꢌꢍ

7

ꢈ

ꢎꢕ

ꢕꢂ?ꢘꢀ1ꢐ,

: ꢈꢉꢆꢇꢇꢀ8ꢈꢄꢑꢍ&

ꢔꢋꢇ#ꢈ#ꢀꢃꢆꢌ4ꢆꢑꢈꢀꢙꢍꢄꢌ4ꢅꢈ!!

ꢐ&ꢆꢅ#ꢋ%%ꢀ

: ꢈꢉꢆꢇꢇꢀ>ꢄ#&ꢍ

ꢔꢋꢇ#ꢈ#ꢀꢃꢆꢌ4ꢆꢑꢈꢀ>ꢄ#&ꢍ

: ꢈꢉꢆꢇꢇꢀ9ꢈꢅꢑ&ꢍ

3ꢋꢋ&ꢀ9ꢈꢅꢑ&ꢍ

3ꢋꢋ&ꢓꢉꢄꢅ&

9ꢈꢆ#ꢀꢙꢍꢄꢌ4ꢅꢈ!!

3ꢋꢋ&ꢀꢗꢅꢑꢇꢈ

ꢗ

M

ꢁꢂꢜꢘ

M

ꢜꢂ<ꢕ

ꢘꢂ-ꢕ

ꢜꢂꢎꢕ

ꢕꢂꢜꢘ

ꢁꢂꢎꢘꢀꢝ.3

M

ꢎꢂꢕꢕ

ꢁꢂ<ꢘ

M

<ꢂꢎꢕ

ꢘꢂ?ꢕ

ꢜꢂꢘꢕ

ꢕꢂꢛꢘ

ꢗꢎ

ꢗꢁ

.

.ꢁ

ꢒ

9

9ꢁ

ꢌ

ꢁꢂ?ꢘ

ꢕꢂꢕꢘ

ꢜꢂꢖꢕ

ꢘꢂꢕꢕ

?ꢂꢛꢕ

ꢕꢂꢘꢘ

ꢕꢂꢕꢛ

ꢕꢟ

ꢕꢂꢎꢘ

<ꢟ

ꢀ

ꢖꢟ

9ꢈꢆ#ꢀ>ꢄ#&ꢍ

)

ꢕꢂꢎꢎ

M

ꢕꢂ-<

ꢜꢘꢋꢄꢊ

ꢁꢂ ꢃꢄꢅꢀꢁꢀ ꢄ!"ꢆꢇꢀꢄꢅ#ꢈ$ꢀ%ꢈꢆ&"ꢉꢈꢀ'ꢆꢊꢀ ꢆꢉꢊ(ꢀ)"&ꢀ'"!&ꢀ)ꢈꢀꢇꢋꢌꢆ&ꢈ#ꢀ*ꢄ&ꢍꢄꢅꢀ&ꢍꢈꢀꢍꢆ&ꢌꢍꢈ#ꢀꢆꢉꢈꢆꢂ

ꢎꢂ ꢒꢄ'ꢈꢅ!ꢄꢋꢅ!ꢀꢒꢀꢆꢅ#ꢀ.ꢁꢀ#ꢋꢀꢅꢋ&ꢀꢄꢅꢌꢇ"#ꢈꢀ'ꢋꢇ#ꢀ%ꢇꢆ!ꢍꢀꢋꢉꢀꢓꢉꢋ&ꢉ"!ꢄꢋꢅ!ꢂꢀꢔꢋꢇ#ꢀ%ꢇꢆ!ꢍꢀꢋꢉꢀꢓꢉꢋ&ꢉ"!ꢄꢋꢅ!ꢀ!ꢍꢆꢇꢇꢀꢅꢋ&ꢀꢈ$ꢌꢈꢈ#ꢀꢕꢂꢎꢕꢀ''ꢀꢓꢈꢉꢀ!ꢄ#ꢈꢂ

-ꢂ ꢒꢄ'ꢈꢅ!ꢄꢋꢅꢄꢅꢑꢀꢆꢅ#ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢄꢅꢑꢀꢓꢈꢉꢀꢗꢐꢔ.ꢀ0ꢁꢖꢂꢘꢔꢂ

1ꢐ,2 1ꢆ!ꢄꢌꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅꢂꢀꢙꢍꢈꢋꢉꢈ&ꢄꢌꢆꢇꢇꢊꢀꢈ$ꢆꢌ&ꢀ ꢆꢇ"ꢈꢀ!ꢍꢋ*ꢅꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ!ꢂ

ꢝ.32 ꢝꢈ%ꢈꢉꢈꢅꢌꢈꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅ(ꢀ"!"ꢆꢇꢇꢊꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ(ꢀ%ꢋꢉꢀꢄꢅ%ꢋꢉ'ꢆ&ꢄꢋꢅꢀꢓ"ꢉꢓꢋ!ꢈ!ꢀꢋꢅꢇꢊꢂ

ꢔꢄꢌꢉꢋꢌꢍꢄꢓ ꢙꢈꢌꢍꢅꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢄꢅꢑ ,ꢕꢖꢞꢕꢜꢎ1

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 387

PIC16F/LF1826/27

)ꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇ-ꢏꢅꢆꢇ.ꢉꢅꢋ$ꢇꢜꢘꢇꢃꢄꢅꢆꢇꢈꢅꢍ,ꢅ/ꢄꢇꢒ0ꢃꢓꢇMꢇ121ꢇꢖꢖꢇꢗꢘꢆꢙꢇꢚ-.ꢜꢛ

3ꢌꢋ*ꢇꢕ&''ꢇꢖꢖꢇ(ꢘꢑꢋꢅꢍꢋꢇꢃꢄꢑ/ꢋ*

ꢜꢘꢋꢄ 3ꢋꢉꢀ&ꢍꢈꢀ'ꢋ!&ꢀꢌ"ꢉꢉꢈꢅ&ꢀꢓꢆꢌ4ꢆꢑꢈꢀ#ꢉꢆ*ꢄꢅꢑ!(ꢀꢓꢇꢈꢆ!ꢈꢀ!ꢈꢈꢀ&ꢍꢈꢀꢔꢄꢌꢉꢋꢌꢍꢄꢓꢀꢃꢆꢌ4ꢆꢑꢄꢅꢑꢀꢐꢓꢈꢌꢄ%ꢄꢌꢆ&ꢄꢋꢅꢀꢇꢋꢌꢆ&ꢈ#ꢀꢆ&ꢀ

ꢍ&&ꢓ255***ꢂ'ꢄꢌꢉꢋꢌꢍꢄꢓꢂꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢄꢅꢑ

D

D2

EXPOSED

PAD

e

E

b

E2

2

1

2

1

K

N

NOTE 1

L

BOTTOM VIEW

TOP VIEW

A

A3

A1

6ꢅꢄ&!

ꢒꢄ'ꢈꢅ!ꢄꢋꢅꢀ9ꢄ'ꢄ&!

ꢔꢚ99ꢚꢔ.ꢙ.ꢝꢐ

7:ꢔ

ꢔꢚ7

ꢔꢗ;

7"')ꢈꢉꢀꢋ%ꢀꢃꢄꢅ!

ꢃꢄ&ꢌꢍ

: ꢈꢉꢆꢇꢇꢀ8ꢈꢄꢑꢍ&

ꢐ&ꢆꢅ#ꢋ%%ꢀ

,ꢋꢅ&ꢆꢌ&ꢀꢙꢍꢄꢌ4ꢅꢈ!!

: ꢈꢉꢆꢇꢇꢀ>ꢄ#&ꢍ

.$ꢓꢋ!ꢈ#ꢀꢃꢆ#ꢀ>ꢄ#&ꢍ

: ꢈꢉꢆꢇꢇꢀ9ꢈꢅꢑ&ꢍ

.$ꢓꢋ!ꢈ#ꢀꢃꢆ#ꢀ9ꢈꢅꢑ&ꢍ

,ꢋꢅ&ꢆꢌ&ꢀ>ꢄ#&ꢍ

,ꢋꢅ&ꢆꢌ&ꢀ9ꢈꢅꢑ&ꢍ

,ꢋꢅ&ꢆꢌ&ꢞ&ꢋꢞ.$ꢓꢋ!ꢈ#ꢀꢃꢆ#

7

ꢈ

ꢗ

ꢗꢁ

ꢗ-

.

.ꢎ

ꢒ

ꢎ<

ꢕꢂ?ꢘꢀ1ꢐ,

ꢕꢂꢛꢕ

ꢕꢂ<ꢕ

ꢕꢂꢕꢕ

ꢁꢂꢕꢕ

ꢕꢂꢕꢘ

ꢕꢂꢕꢎ

ꢕꢂꢎꢕꢀꢝ.3

?ꢂꢕꢕꢀ1ꢐ,

-ꢂꢜꢕ

?ꢂꢕꢕꢀ1ꢐ,

-ꢂꢜꢕ

ꢕꢂ-ꢕ

ꢕꢂꢘꢘ

M

-ꢂ?ꢘ

ꢖꢂꢎꢕ

ꢒꢎ

)

9

-ꢂ?ꢘ

ꢕꢂꢎ-

ꢕꢂꢘꢕ

ꢕꢂꢎꢕ

ꢖꢂꢎꢕ

ꢕꢂ-ꢘ

ꢕꢂꢜꢕ

M

C

ꢜꢘꢋꢄꢊ

ꢁꢂ ꢃꢄꢅꢀꢁꢀ ꢄ!"ꢆꢇꢀꢄꢅ#ꢈ$ꢀ%ꢈꢆ&"ꢉꢈꢀ'ꢆꢊꢀ ꢆꢉꢊ(ꢀ)"&ꢀ'"!&ꢀ)ꢈꢀꢇꢋꢌꢆ&ꢈ#ꢀ*ꢄ&ꢍꢄꢅꢀ&ꢍꢈꢀꢍꢆ&ꢌꢍꢈ#ꢀꢆꢉꢈꢆꢂ

ꢎꢂ ꢃꢆꢌ4ꢆꢑꢈꢀꢄ!ꢀ!ꢆ*ꢀ!ꢄꢅꢑ"ꢇꢆ&ꢈ#ꢂ

-ꢂ ꢒꢄ'ꢈꢅ!ꢄꢋꢅꢄꢅꢑꢀꢆꢅ#ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢄꢅꢑꢀꢓꢈꢉꢀꢗꢐꢔ.ꢀ0ꢁꢖꢂꢘꢔꢂ

1ꢐ,2 1ꢆ!ꢄꢌꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅꢂꢀꢙꢍꢈꢋꢉꢈ&ꢄꢌꢆꢇꢇꢊꢀꢈ$ꢆꢌ&ꢀ ꢆꢇ"ꢈꢀ!ꢍꢋ*ꢅꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ!ꢂ

ꢝ.32 ꢝꢈ%ꢈꢉꢈꢅꢌꢈꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅ(ꢀ"!"ꢆꢇꢇꢊꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ(ꢀ%ꢋꢉꢀꢄꢅ%ꢋꢉ'ꢆ&ꢄꢋꢅꢀꢓ"ꢉꢓꢋ!ꢈ!ꢀꢋꢅꢇꢊꢂ

ꢔꢄꢌꢉꢋꢌꢍꢄꢓ ꢙꢈꢌꢍꢅꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢄꢅꢑ ,ꢕꢖꢞꢁꢕꢘ1

DS41391C-page 388

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

)ꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇ-ꢏꢅꢆꢇ.ꢉꢅꢋ$ꢇꢜꢘꢇꢃꢄꢅꢆꢇꢈꢅꢍ,ꢅ/ꢄꢇꢒ0ꢃꢓꢇMꢇ121ꢇꢖꢖꢇꢗꢘꢆꢙꢇꢚ-.ꢜꢛ

3ꢌꢋ*ꢇꢕ&''ꢇꢖꢖꢇ(ꢘꢑꢋꢅꢍꢋꢇꢃꢄꢑ/ꢋ*

ꢜꢘꢋꢄ 3ꢋꢉꢀ&ꢍꢈꢀ'ꢋ!&ꢀꢌ"ꢉꢉꢈꢅ&ꢀꢓꢆꢌ4ꢆꢑꢈꢀ#ꢉꢆ*ꢄꢅꢑ!(ꢀꢓꢇꢈꢆ!ꢈꢀ!ꢈꢈꢀ&ꢍꢈꢀꢔꢄꢌꢉꢋꢌꢍꢄꢓꢀꢃꢆꢌ4ꢆꢑꢄꢅꢑꢀꢐꢓꢈꢌꢄ%ꢄꢌꢆ&ꢄꢋꢅꢀꢇꢋꢌꢆ&ꢈ#ꢀꢆ&ꢀ

ꢍ&&ꢓ255***ꢂ'ꢄꢌꢉꢋꢌꢍꢄꢓꢂꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢄꢅꢑ

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 389

PIC16F/LF1826/27

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS41391C-page 390

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 391

PIC16F/LF1826/27

NOTES:

DS41391C-page 392

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

APPENDIX A: DATA SHEET

REVISION HISTORY

APPENDIX B: MIGRATING FROM

OTHER PIC^®

DEVICES

Revision A

This section provides comparisons when migrating

Original release (06/2009)

from

other

similar

PIC^®

devices

to

the

PIC16F/LF1826/27 family of devices.

Revision B (08/09)

B.1

PIC16F648A to PIC16F/LF1827

Revised Tables 5-3, 6-2, 12-2, 12-3; Updated Electrical

Specifications; Added UQFN Package; Added SOIC

and QFN Land Patterns; Updated Product ID section.

TABLE B-1:

Feature

FEATURE COMPARISON

PIC16F648A PIC16F/LF1827

Max. Operating

Speed

20 MHz

32 MHz

Revision C (06/10)

Updated Electrical Specification and included

Enhanced Core Golden Chapters.

Max. Program

Memory (Words)

4K

Max. SRAM (Bytes)

256

384

256

Max. EEPROM

(Bytes)

A/D Resolution

10-bit

2/1

10-bit

Timers (8/16-bit)

Brown-out Reset

Internal Pull-ups

Interrupt-on-Change

4/1

Y

RB<7:0>

RB<7:4>

RB<7:0>, RA5

RB<7:0>, Edge

Selectable

Comparator

2

1/0

N

2

0/2

Y

AUSART/EUSART

Extended WDT

Software Control

N

Y

Option of WDT/BOR

INTOSC

Frequencies

48 kHz or

4 MHz

31 kHz -

32 MHz

Clock Switching

Capacitive Sensing

CCP/ECCP

Y

N

Y

2/0

N

2/2

Y

Enhanced PIC16

CPU

MSSPx/SSPx

0

N

2/0

Y

Reference Clock

Data Signal

Modulator

Y

SR Latch

N

Y

Voltage Reference

DAC

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 393

PIC16F/LF1826/27

NOTES:

DS41391C-page 394

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

INDEX

EUSART Receive..................................................... 288

EUSART Transmit.................................................... 287

External RC Mode ...................................................... 59

Fail-Safe Clock Monitor (FSCM)................................. 67

Generic I/O Port........................................................ 121

Interrupt Logic............................................................. 85

On-Chip Reset Circuit................................................. 77

Peripheral Interrupt Logic ........................................... 86

PIC16F/LF1826/27 ..................................................... 12

PIC16F193X/LF193X ................................................. 18

PWM (Enhanced) ..................................................... 214

Resonator Operation .................................................. 58

Timer0 ...................................................................... 175

Timer1 ...................................................................... 179

Timer1 Gate.............................................. 184, 185, 186

Timer2/4/6 ................................................................ 191

Voltage Reference.................................................... 137

Voltage Reference Output Buffer Example .............. 156

BORCON Register.............................................................. 79

BRA .................................................................................. 334

Break Character (12-bit) Transmit and Receive ............... 307

Brown-out Reset (BOR)...................................................... 79

Specifications ........................................................... 364

Timing and Characteristics....................................... 363

A

A/D

Specifications............................................................ 366

Absolute Maximum Ratings .............................................. 343

AC Characteristics

Industrial and Extended ............................................ 359

Load Conditions........................................................ 358

ACKSTAT ......................................................................... 268

ACKSTAT Status Flag ...................................................... 268

ADC .................................................................................. 139

Acquisition Requirements ......................................... 149

Associated registers.................................................. 151

Block Diagram........................................................... 139

Calculating Acquisition Time..................................... 149

Channel Selection..................................................... 140

Configuration............................................................. 140

Configuring Interrupt ................................................. 144

Conversion Clock...................................................... 140

Conversion Procedure .............................................. 144

Internal Sampling Switch (RSS) IMPEDANCE .............. 149

Interrupts................................................................... 142

Operation .................................................................. 143

Operation During Sleep ............................................ 143

Port Configuration..................................................... 140

Reference Voltage (VREF)......................................... 140

Source Impedance.................................................... 149

Special Event Trigger................................................ 143

Starting an A/D Conversion ...................................... 142

ADCON0 Register....................................................... 31, 145

ADCON1 Register....................................................... 31, 146

ADDFSR ........................................................................... 333

ADDWFC .......................................................................... 333

ADRESH Register............................................................... 31

ADRESH Register (ADFM = 0)......................................... 147

ADRESH Register (ADFM = 1)......................................... 148

ADRESL Register (ADFM = 0).......................................... 147

ADRESL Register (ADFM = 1).......................................... 148

Alternate Pin Function....................................................... 121

Analog-to-Digital Converter. See ADC

C

C Compilers

MPLAB C18.............................................................. 380

CALL................................................................................. 335

CALLW ............................................................................. 335

Capacitive Sensing........................................................... 317

Associated registers w/ Capacitive Sensing............. 321

Specifications ........................................................... 375

Capture Module. See Enhanced Capture/Compare/

PWM(ECCP)

Capture/Compare/PWM ................................................... 205

Capture/Compare/PWM (CCP)

Associated Registers w/ Capture ............................. 207

Associated Registers w/ Compare ........................... 209

Associated Registers w/ PWM ......................... 213, 227

Capture Mode........................................................... 206

CCPx Pin Configuration............................................ 206

Compare Mode......................................................... 208

CCPx Pin Configuration.................................... 208

Software Interrupt Mode........................... 206, 208

Special Event Trigger....................................... 208

Timer1 Mode Resource............................ 206, 208

Prescaler .................................................................. 206

PWM Mode

ANSELA Register ............................................................. 125

ANSELB Register ............................................................. 130

APFCON0 Register........................................................... 122

APFCON1 Register........................................................... 122

Assembler

MPASM Assembler................................................... 380

B

BAUDCON Register.......................................................... 298

BF ............................................................................. 268, 270

BF Status Flag .......................................................... 268, 270

Block Diagram

Capacitive Sensing ................................................... 317

Block Diagrams

Duty Cycle ........................................................ 211

Effects of Reset................................................ 213

Example PWM Frequencies and

Resolutions, 20 MHZ................................ 212

Example PWM Frequencies and

(CCP) Capture Mode Operation ............................... 206

ADC .......................................................................... 139

ADC Transfer Function ............................................. 150

Analog Input Model........................................... 150, 171

CCP PWM................................................................. 210

Clock Source............................................................... 56

Comparator............................................................... 166

Compare ................................................................... 208

Crystal Operation.................................................. 58, 59

Digital-to-Analog Converter (DAC)............................ 155

Resolutions, 32 MHZ................................ 212

Example PWM Frequencies and

Resolutions, 8 MHz .................................. 212

Operation in Sleep Mode.................................. 213

Resolution ........................................................ 212

System Clock Frequency Changes .................. 213

PWM Operation........................................................ 210

PWM Overview......................................................... 210

PWM Period ............................................................. 211

PWM Setup .............................................................. 211

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 395

PIC16F/LF1826/27

CCP1CON Register ...................................................... 35, 36

CCPR1H Register......................................................... 35, 36

CCPR1L Register.......................................................... 35, 36

CCPTMRS0 Register........................................................229

CCPxAS Register..............................................................230

CCPxCON (ECCPx) Register ...........................................228

CLKRCON Register ............................................................74

Clock Accuracy with Asynchronous Operation .................296

Clock Sources

Device Configuration .......................................................... 49

Code Protection.......................................................... 53

Configuration Word..................................................... 49

User ID ................................................................. 53, 54

Device Overview................................................. 11, 103, 106

Digital-to-Analog Converter (DAC) ................................... 153

Associated Registers................................................ 158

Effects of a Reset ..................................................... 155

Specifications ........................................................... 368

External Modes...........................................................57

EC.......................................................................57

HS.......................................................................57

LP........................................................................57

OST.....................................................................58

RC.......................................................................59

XT .......................................................................57

Internal Modes ............................................................60

HFINTOSC..........................................................60

Internal Oscillator Clock Switch Timing...............62

LFINTOSC ..........................................................61

MFINTOSC .........................................................60

Clock Switching...................................................................64

CMOUT Register...............................................................173

CMxCON0 Register ..........................................................172

CMxCON1 Register ..........................................................173

Code Examples

A/D Conversion.........................................................144

Changing Between Capture Prescalers....................206

Initializing PORTA.....................................................123

Initializing PORTB.....................................................128

Write Verify ...............................................................117

Writing to Flash Program Memory ............................115

Comparator

Associated Registers ................................................174

Operation ..................................................................165

Comparator Module ..........................................................165

Cx Output State Versus Input Conditions .................168

Comparator Specifications................................................368

Comparators

C2OUT as T1 Gate ...................................................181

Compare Module. See Enhanced Capture/Compare/

PWM (ECCP)

CONFIG1 Register..............................................................50

CONFIG2 Register..............................................................52

CPSCON0 Register ..........................................................320

CPSCON1 Register ..........................................................321

Customer Change Notification Service .............................402

Customer Notification Service...........................................402

Customer Support.............................................................402

E

ECCP/CCP. See Enhanced Capture/Compare/PWM

EEADR Registers ............................................................. 107

EEADRH Registers........................................................... 107

EEADRL Register............................................................. 118

EEADRL Registers ........................................................... 107

EECON1 Register..................................................... 107, 119

EECON2 Register..................................................... 107, 120

EEDATH Register............................................................. 118

EEDATL Register ............................................................. 118

EEPROM Data Memory

Avoiding Spurious Write ........................................... 108

Write Verify............................................................... 117

Effects of Reset

PWM mode............................................................... 213

Electrical Specifications.................................................... 343

Enhanced Capture/Compare/PWM (ECCP)..................... 205

Enhanced PWM Mode.............................................. 214

Auto-Restart ..................................................... 223

Auto-shutdown.................................................. 222

Direction Change in Full-Bridge Output Mode.. 220

Full-Bridge Application...................................... 218

Full-Bridge Mode .............................................. 218

Half-Bridge Application..................................... 217

Half-Bridge Application Examples .................... 224

Half-Bridge Mode.............................................. 217

Output Relationships (Active-High and

Active-Low)............................................... 215

Output Relationships Diagram.......................... 216

Programmable Dead Band Delay..................... 224

Shoot-through Current...................................... 224

Start-up Considerations.................................... 226

Specifications ........................................................... 365

Enhanced Mid-range CPU.................................................. 17

Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) .............................. 287

Errata.................................................................................... 9

EUSART ........................................................................... 287

Associated Registers

Baud Rate Generator ....................................... 300

Asynchronous Mode................................................. 289

12-bit Break Transmit and Receive .................. 307

Associated Registers

D

DACCON0 (Digital-to-Analog Converter Control 0)

Register.....................................................................157

DACCON1 (Digital-to-Analog Converter Control 1)

Register.....................................................................157

Data EEPROM Memory....................................................107

Associated Registers ................................................120

Code Protection ........................................................108

Reading.....................................................................108

Writing.......................................................................108

Data Memory.......................................................................22

DC and AC Characteristics ...............................................377

DC Characteristics

Receive .................................................... 295

Transmit.................................................... 291

Auto-Wake-up on Break ................................... 305

Baud Rate Generator (BRG) ............................ 299

Clock Accuracy................................................. 296

Receiver ........................................................... 292

Setting up 9-bit Mode with Address Detect ...... 294

Transmitter ....................................................... 289

Baud Rate Generator (BRG)

Auto Baud Rate Detect..................................... 304

Baud Rate Error, Calculating............................ 299

Baud Rates, Asynchronous Modes .................. 301

Formulas........................................................... 300

Extended and Industrial ............................................354

Industrial and Extended ............................................346

Development Support .......................................................379

DS41391C-page 396

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

High Baud Rate Select (BRGH Bit) .................. 299

Synchronous Master Mode............................... 308, 313

Associated Registers

Receive..................................................... 312

Transmit.................................................... 310

Reception.......................................................... 311

Transmission .................................................... 308

Synchronous Slave Mode

LSRF ........................................................................ 337

MOVF ....................................................................... 337

MOVIW..................................................................... 338

MOVLB..................................................................... 338

MOVWI..................................................................... 339

OPTION.................................................................... 339

Reset ........................................................................ 339

SUBWFB .................................................................. 341

TRIS ......................................................................... 342

BCF .......................................................................... 334

BSF........................................................................... 334

BTFSC...................................................................... 334

BTFSS...................................................................... 334

CALL......................................................................... 335

CLRF ........................................................................ 335

CLRW....................................................................... 335

CLRWDT .................................................................. 335

COMF....................................................................... 335

DECF........................................................................ 335

DECFSZ ................................................................... 336

GOTO....................................................................... 336

INCF ......................................................................... 336

INCFSZ..................................................................... 336

IORLW...................................................................... 336

IORWF...................................................................... 336

MOVLW.................................................................... 338

MOVWF.................................................................... 338

NOP.......................................................................... 339

RETFIE..................................................................... 340

RETLW..................................................................... 340

RETURN................................................................... 340

RLF........................................................................... 340

RRF .......................................................................... 341

SLEEP...................................................................... 341

SUBLW..................................................................... 341

SUBWF..................................................................... 341

SWAPF..................................................................... 342

XORLW .................................................................... 342

XORWF .................................................................... 342

INTCON Register................................................................ 91

Internal Oscillator Block

Associated Registers

Receive..................................................... 314

Transmit.................................................... 313

Reception.......................................................... 314

Transmission .................................................... 313

Extended Instruction Set

ADDFSR ................................................................... 333

F

Fail-Safe Clock Monitor....................................................... 67

Fail-Safe Condition Clearing....................................... 67

Fail-Safe Detection ..................................................... 67

Fail-Safe Operation..................................................... 67

Reset or Wake-up from Sleep..................................... 67

Firmware Instructions........................................................ 329

Fixed Voltage Reference (FVR)

Associated Registers ................................................ 138

Flash Program Memory .................................................... 107

Erasing...................................................................... 112

Modifying................................................................... 116

Writing....................................................................... 112

FSR Register .......... 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40

FVRCON (Fixed Voltage Reference Control) Register..... 138

I

2

I C Mode (MSSPx)

Acknowledge Sequence Timing................................ 272

Bus Collision

During a Repeated Start Condition................... 277

During a Stop Condition.................................... 278

Effects of a Reset...................................................... 273

2

I C Clock Rate w/BRG.............................................. 280

Master Mode

Operation .......................................................... 264

Reception.......................................................... 270

Start Condition Timing .............................. 266, 267

Transmission .................................................... 268

Multi-Master Communication, Bus Collision

and Arbitration .................................................. 273

Multi-Master Mode .................................................... 273

Read/Write Bit Information (R/W Bit) ........................ 249

Slave Mode

INTOSC

Specifications ................................................... 360

Internal Sampling Switch (RSS) IMPEDANCE...................... 149

Internet Address ............................................................... 402

Interrupt-On-Change......................................................... 133

Associated Registers................................................ 135

Interrupts ............................................................................ 85

ADC.......................................................................... 144

Associated registers w/ Interrupts .............................. 99

Configuration Word w/ Clock Sources........................ 71

Configuration Word w/ PORTA................................. 127

Configuration Word w/ Reference Clock Sources ...... 75

TMR1........................................................................ 183

INTOSC Specifications..................................................... 360

IOCBF Register ................................................................ 134

IOCBN Register................................................................ 134

IOCBP Register ................................................................ 134

Transmission .................................................... 254

Sleep Operation........................................................ 273

Stop Condition Timing............................................... 272

INDF Register ......... 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40

Indirect Addressing ............................................................. 44

Instruction Format............................................................. 330

Instruction Set................................................................... 329

ADDLW..................................................................... 333

ADDWF..................................................................... 333

ADDWFC .................................................................. 333

ANDLW..................................................................... 333

ANDWF..................................................................... 333

BRA........................................................................... 334

CALL......................................................................... 335

CALLW...................................................................... 335

LSLF ......................................................................... 337

L

LATA Register .................................................................. 124

LATB Register .................................................................. 129

Load Conditions................................................................ 358

LSLF ................................................................................. 337

LSRF ................................................................................ 337

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 397

PIC16F/LF1826/27

PIE2 Register...................................................................... 93

PIE3 Register...................................................................... 94

PIE4 Register...................................................................... 95

Pin Diagram

PIC16F/LF1826/27, 18-pin PDIP/SOIC ........................ 5

PIC16F/LF1826/27, 28-pin QFN/UQFN........................ 6

Pinout Descriptions

PIC16F/LF1826/27 ..................................................... 13

PIR1 Register ............................................................... 30, 96

PIR2 Register ......................................................... 30, 31, 97

PIR3 Register ..................................................................... 98

PIR4 Register ..................................................................... 99

PORTA ............................................................................. 123

ANSELA Register ..................................................... 123

Associated Registers................................................ 127

PORTA Register................................................... 30, 32

Specifications ........................................................... 362

PORTA Register............................................................... 124

PORTB ............................................................................. 128

Additional Pin Functions

M

Master Synchronous Serial Port. See MSSPx

MCLR..................................................................................80

Internal ........................................................................80

MDCARH Register............................................................202

MDCARL Register.............................................................203

MDCON Register ..............................................................200

MDSRC Register...............................................................201

Memory Organization..........................................................19

Data ............................................................................22

Program ......................................................................19

Microchip Internet Web Site..............................................402

Migrating from other PIC Microcontroller Devices.............393

MOVIW..............................................................................338

MOVLB..............................................................................338

MOVWI..............................................................................339

MPLAB ASM30 Assembler, Linker, Librarian ...................380

MPLAB Integrated Development Environment Software ..379

MPLAB PM3 Device Programmer.....................................382

MPLAB REAL ICE In-Circuit Emulator System.................381

MPLINK Object Linker/MPLIB Object Librarian ................380

MSSPx ..............................................................................233

Weak Pull-up .................................................... 129

ANSELB Register ..................................................... 128

Associated Registers................................................ 132

Interrupt-on-Change ................................................. 128

P1B/P1C/P1D.See Enhanced Capture/Compare/

2

I C Mode...................................................................244

2

I C Mode Operation ..................................................246

SPI Mode ..................................................................236

SSPxBUF Register ...................................................239

SSPxSR Register......................................................239

PWM+ (ECCP+) ............................................... 128

Pin Descriptions and Diagrams ................................ 131

PORTB Register................................................... 30, 32

PORTB Register............................................................... 129

Power-Down Mode (Sleep)............................................... 101

Associated Registers........................................ 102, 203

Power-on Reset.................................................................. 78

Power-up Time-out Sequence............................................ 80

Power-up Timer (PWRT) .................................................... 78

Specifications ........................................................... 364

PR2 Register ................................................................ 30, 38

Precision Internal Oscillator Parameters .......................... 360

Program Memory................................................................ 19

Map and Stack (PIC16F/LF1826)............................... 20

Map and Stack (PIC16F/LF1826/27).................... 19, 20

Programming, Device Instructions.................................... 329

PSTRxCON Register........................................................ 232

PWM (ECCP Module)

O

OPCODE Field Descriptions.............................................329

OPTION ............................................................................339

OPTION Register..............................................................177

OSCCON Register..............................................................69

Oscillator

Associated Registers ..................................................71

Oscillator Module ................................................................55

ECH ............................................................................55

ECL .............................................................................55

ECM ............................................................................55

HS...............................................................................55

INTOSC ......................................................................55

LP................................................................................55

RC...............................................................................55

XT ...............................................................................55

Oscillator Parameters........................................................360

Oscillator Specifications....................................................359

Oscillator Start-up Timer (OST)

Specifications............................................................364

Oscillator Switching

Fail-Safe Clock Monitor...............................................67

Two-Speed Clock Start-up..........................................65

OSCSTAT Register.............................................................70

OSCTUNE Register ............................................................71

PWM Steering........................................................... 225

Steering Synchronization.......................................... 226

PWM Mode. See Enhanced Capture/Compare/PWM...... 214

PWM Steering................................................................... 225

PWMxCON Register......................................................... 231

R

RCREG............................................................................. 294

RCREG Register ................................................................ 33

RCSTA Register ......................................................... 33, 297

Reader Response............................................................. 403

Read-Modify-Write Operations ......................................... 329

Reference Clock ................................................................. 73

Associated Registers.................................................. 75

Registers

P

P1A/P1B/P1C/P1D.See Enhanced Capture/Compare/

PWM (ECCP)............................................................214

Packaging .........................................................................383

Marking .....................................................................383

PDIP Details..............................................................384

PCL and PCLATH...............................................................18

PCL Register...........30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40

PCLATH Register....30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40

PCON Register ............................................................. 31, 83

PIE1 Register................................................................31, 92

ADCON0 (ADC Control 0) ........................................ 145

ADCON1 (ADC Control 1) ........................................ 146

ADRESH (ADC Result High) with ADFM = 0) .......... 147

ADRESH (ADC Result High) with ADFM = 1) .......... 148

ADRESL (ADC Result Low) with ADFM = 0)............ 147

ADRESL (ADC Result Low) with ADFM = 1)............ 148

ANSELA (PORTA Analog Select)............................. 125

ANSELB (PORTB Analog Select)............................. 130

DS41391C-page 398

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

APFCON0 (Alternate Pin Function Control 0)........... 122

APFCON1 (Alternate Pin Function Control 1)........... 122

BAUDCON (Baud Rate Control)............................... 298

BORCON Brown-out Reset Control)........................... 79

CCPTMRS0 (PWM Timer Selection Control 0) ........ 229

CCPxAS (CCPx Auto-Shutdown Control)................. 230

CCPxCON (ECCPx Control)..................................... 228

CLKRCON (Reference Clock Control)........................ 74

CMOUT (Comparator Output)................................... 173

CMxCON0 (Cx Control) ............................................ 172

CMxCON1 (Cx Control 1) ......................................... 173

Configuration Word 1.................................................. 50

Configuration Word 2.................................................. 52

CPSCON0 (Capacitive Sensing Control Register 0) 320

CPSCON1 (Capacitive Sensing Control Register 1) 321

DACCON0 ................................................................ 157

DACCON1 ................................................................ 157

EEADRL (EEPROM Address) .................................. 118

EECON1 (EEPROM Control 1)................................. 119

EECON2 (EEPROM Control 2)................................. 120

EEDATH (EEPROM Data)........................................ 118

EEDATL (EEPROM Data) ........................................ 118

FVRCON................................................................... 138

INTCON (Interrupt Control)......................................... 91

IOCBF (Interrupt-on-Change Flag) ........................... 134

IOCBN (Interrupt-on-Change Negative Edge) .......... 134

IOCBP (Interrupt-on-Change Positive Edge)............ 134

LATA (Data Latch PORTA)....................................... 124

LATB (Data Latch PORTB)....................................... 129

MDCARH (Modulation High Carrier Control

SSPxSTAT (SSPx Status)........................................ 282

STATUS ..................................................................... 23

T1CON (Timer1 Control) .......................................... 187

T1GCON (Timer1 Gate Control)............................... 188

TRISA (Tri-State PORTA) ........................................ 124

TRISB (Tri-State PORTB) ........................................ 129

TXCON..................................................................... 193

TXSTA (Transmit Status and Control)...................... 296

WDTCON (Watchdog Timer Control)....................... 105

WPUB (Weak Pull-up PORTB)......................... 125, 130

Reset .......................................................................... 77, 339

Reset Instruction................................................................. 80

Resets ................................................................................ 77

Associated Registers.................................................. 84

Revision History................................................................ 393

S

Shoot-through Current...................................................... 224

Software Simulator (MPLAB SIM) .................................... 381

SPBRG Register................................................................. 33

SPBRGH Register ............................................................ 299

SPBRGL Register............................................................. 299

Special Event Trigger ....................................................... 143

Special Function Registers (SFRs)..................................... 30

SPI Mode (MSSPx)

Associated Registers................................................ 243

SPI Clock.................................................................. 239

SR Latch........................................................................... 159

Associated registers w/ SR Latch............................. 163

SRCON0 Register ............................................................ 161

SRCON1 Register ............................................................ 162

SSP1ADD Register............................................................. 34

SSP1BUF Register............................................................. 34

SSP1CON Register............................................................ 34

SSP1CON2 Register.......................................................... 34

SSP1CON3 Register.......................................................... 34

SSP1MSK Register ............................................................ 34

SSP1STAT Register........................................................... 34

SSP2ADD Register............................................................. 34

SSP2BUF Register............................................................. 34

SSP2CON1 Register.......................................................... 34

SSP2CON2 Register.......................................................... 34

SSP2CON3 Register.......................................................... 34

SSP2MSK Register ............................................................ 34

SSP2STAT Register........................................................... 34

SSPxADD Register........................................................... 286

SSPxCON1 Register ........................................................ 283

SSPxCON2 Register ........................................................ 284

SSPxCON3 Register ........................................................ 285

SSPxMSK Register........................................................... 286

SSPxOV ........................................................................... 270

SSPxOV Status Flag ........................................................ 270

SSPxSTAT Register ......................................................... 282

R/W Bit ..................................................................... 249

Stack................................................................................... 42

Accessing ................................................................... 42

Reset .......................................................................... 44

Stack Overflow/Underflow .................................................. 80

STATUS Register ............................................................... 23

SUBWFB .......................................................................... 341

Register) ........................................................... 202

MDCARL (Modulation Low Carrier Control Register)203

MDCON (Modulation Control Register) .................... 200

MDSRC (Modulation Source Control Register) ........ 201

OPTION_REG (OPTION) ......................................... 177

OSCCON (Oscillator Control) ..................................... 69

OSCSTAT (Oscillator Status) ..................................... 70

OSCTUNE (Oscillator Tuning).................................... 71

PCON (Power Control Register)................................. 83

PCON (Power Control) ............................................... 83

PIE1 (Peripheral Interrupt Enable 1)........................... 92

PIE2 (Peripheral Interrupt Enable 2)........................... 93

PIE3 (Peripheral Interrupt Enable 3)........................... 94

PIE4 (Peripheral Interrupt Enable 4)........................... 95

PIR1 (Peripheral Interrupt Register 1) ........................ 96

PIR2 (Peripheral Interrupt Request 2) ........................ 97

PIR3 (Peripheral Interrupt Request 3) ........................ 98

PIR4 (Peripheral Interrupt Request 4) ........................ 99

PORTA...................................................................... 124

PORTB...................................................................... 129

PSTRxCON (PWM Steering Control) ....................... 232

PWMxCON (Enhanced PWM Control) ..................... 231

RCREG..................................................................... 304

RCSTA (Receive Status and Control)....................... 297

SPBRGH................................................................... 299

SPBRGL ................................................................... 299

Special Function, Summary........................................ 30

SRCON0 (SR Latch Control 0) ................................. 161

SRCON1 (SR Latch Control 1) ................................. 162

SSPxADD (MSSPx Address and Baud Rate,

2

I C Mode) ......................................................... 286

T

SSPxCON1 (MSSPx Control 1)................................ 283

SSPxCON2 (SSPx Control 2)................................... 284

SSPxCON3 (SSPx Control 3)................................... 285

SSPxMSK (SSPx Mask) ........................................... 286

T1CON Register ......................................................... 30, 187

T1GCON Register ............................................................ 188

T2CON Register ........................................................... 30, 38

Thermal Considerations.................................................... 357

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 399

PIC16F/LF1826/27

2

Timer0....................................................................... 175, 194

Associated Registers ................................................177

Operation ..................................................................175

Specifications............................................................365

Timer1...............................................................................179

Associated registers..................................................189

Asynchronous Counter Mode ...................................181

Reading and Writing .........................................181

Clock Source Selection.............................................180

Interrupt.....................................................................183

Operation ..................................................................180

Operation During Sleep ............................................183

Oscillator...................................................................181

Prescaler...................................................................181

Specifications............................................................365

Timer1 Gate

Selecting Source...............................................181

TMR1H Register .......................................................179

TMR1L Register........................................................179

Timer2

Associated registers..................................................194

Timer2/4/6.........................................................................191

Associated registers..................................................194

Timers

I C Master Mode (7-Bit Reception)........................... 271

2

I C Stop Condition Receive or Transmit Mode......... 273

INT Pin Interrupt ......................................................... 89

Internal Oscillator Switch Timing ................................ 63

PWM Auto-shutdown................................................ 223

Firmware Restart.............................................. 222

PWM Direction Change ............................................ 220

PWM Direction Change at Near 100% Duty Cycle... 221

PWM Output (Active-High) ....................................... 215

PWM Output (Active-Low)........................................ 216

Repeat Start Condition ............................................. 267

Reset Start-up Sequence ........................................... 81

Reset, WDT, OST and Power-up Timer................... 362

Send Break Character Sequence............................. 307

SPI Master Mode (CKE = 1, SMP = 1) ..................... 370

SPI Mode (Master Mode).......................................... 239

SPI Slave Mode (CKE = 0)....................................... 371

SPI Slave Mode (CKE = 1)....................................... 371

Synchronous Reception (Master Mode, SREN) ....... 312

Synchronous Transmission ...................................... 309

Synchronous Transmission (Through TXEN)........... 309

Timer0 and Timer1 External Clock ........................... 364

Timer1 Incrementing Edge ....................................... 183

Two Speed Start-up.................................................... 66

USART Synchronous Receive (Master/Slave) ......... 369

USART Synchronous Transmission (Master/Slave). 369

Wake-up from Interrupt............................................. 102

Timing Diagrams and Specifications

Timer1

T1CON..............................................................187

T1GCON...........................................................188

Timer2/4/6

TXCON .............................................................193

Timing Diagrams

PLL Clock ................................................................. 360

Timing Parameter Symbology .......................................... 358

Timing Requirements

A/D Conversion.........................................................367

A/D Conversion (Sleep Mode) ..................................367

Acknowledge Sequence ...........................................272

Asynchronous Reception ..........................................294

Asynchronous Transmission.....................................290

Asynchronous Transmission (Back to Back) ............290

Auto Wake-up Bit (WUE) During Normal Operation .306

Auto Wake-up Bit (WUE) During Sleep ....................306

Automatic Baud Rate Calibration..............................304

Baud Rate Generator with Clock Arbitration .............265

BRG Reset Due to SDA Arbitration During Start

Condition...........................................................276

Brown-out Reset (BOR)............................................363

Brown-out Reset Situations ........................................79

Bus Collision During a Repeated Start Condition

(Case 1) ............................................................277

Bus Collision During a Repeated Start Condition

(Case 2) ............................................................277

Bus Collision During a Start Condition (SCL = 0) .....276

Bus Collision During a Stop Condition (Case 1) .......278

Bus Collision During a Stop Condition (Case 2) .......278

Bus Collision During Start Condition (SDA only) ......275

Bus Collision for Transmit and Acknowledge............274

CLKOUT and I/O.......................................................361

Clock Synchronization ..............................................262

Clock Timing .............................................................359

Comparator Output ...................................................165

Enhanced Capture/Compare/PWM (ECCP).............365

Fail-Safe Clock Monitor (FSCM).................................68

First Start Bit Timing .................................................266

Full-Bridge PWM Output ...........................................219

Half-Bridge PWM Output .................................. 217, 224

2

I C Bus Data............................................................. 374

SPI Mode.................................................................. 372

TMR0 Register.................................................................... 30

TMR1H Register................................................................. 30

TMR1L Register.................................................................. 30

TMR2 Register.............................................................. 30, 38

TRIS.................................................................................. 342

TRISA Register........................................................... 31, 124

TRISB ............................................................................... 128

TRISB Register........................................................... 31, 129

Two-Speed Clock Start-up Mode........................................ 65

TXCON (Timer2/4/6) Register .......................................... 193

TxCON Register ............................................................... 213

TXREG ............................................................................. 289

TXREG Register................................................................. 33

TXSTA Register.......................................................... 33, 296

BRGH Bit .................................................................. 299

U

USART

Synchronous Master Mode

Requirements, Synchronous Receive .............. 369

Requirements, Synchronous Transmission...... 369

Timing Diagram, Synchronous Receive ........... 369

Timing Diagram, Synchronous Transmission... 369

V

VREF. SEE ADC Reference Voltage

W

Wake-up on Break............................................................ 305

Wake-up Using Interrupts................................................. 102

Watchdog Timer (WDT)...................................................... 80

Modes....................................................................... 104

Specifications ........................................................... 364

2

I C Bus Data.............................................................373

2

I C Bus Start/Stop Bits..............................................372

2

I C Master Mode (7 or 10-Bit Transmission) ............269

DS41391C-page 400

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

WCOL ....................................................... 265, 268, 270, 272

WCOL Status Flag .................................... 265, 268, 270, 272

WDTCON Register ........................................................... 105

WPUB Register......................................................... 125, 130

Write Protection .................................................................. 53

WWW Address.................................................................. 402

WWW, On-Line Support ....................................................... 9

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 401

PIC16F/LF1826/27

NOTES:

DS41391C-page 402

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 403

PIC16F/LF1826/27

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

Technical Publications Manager

Reader Response

Total Pages Sent ________

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

PIC16F/LF1826/27

DS41391C

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS41391C-page 404

Preliminary

 2010 Microchip Technology Inc.

PIC16F/LF1826/27

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

XXX

Examples:

Temperature

Range

Package

Pattern

a)

PIC16F1826 - I/ML 301 = Industrial temp., QFN

package, Extended VDD limits, QTP pattern

#301.

b)

c)

PIC16F1826 - I/P = Industrial temp., PDIP

package, Extended VDD limits.

Device:

PIC16F1826⁽¹⁾, PIC16F1827⁽¹⁾, PIC16F1826T⁽²⁾

PIC16F1827T⁽²⁾

VDD range 1.8V to 5.5V

PIC16LF1826⁽¹⁾, PIC16LF1827⁽¹⁾, PIC16LF1826T⁽²⁾

PIC16LF1827T⁽²⁾

VDD range 1.8V to 3.6V

,

PIC16F1827 - E/SS= Extended temp., SSOP

package, normal VDD limits.

;

,

;

Temperature

Range:

I

E

=

-40C to +85C (Industrial)

-40C to +125C (Extended)

Package:

ML

MV

P

SO

SS

=

Micro Lead Frame (QFN) 6x6

Micro Lead Frame (UQFN) 4x4

Plastic DIP

SOIC

SSOP

Note 1:

2:

F

LF

T

=

Wide Voltage Range

Standard Voltage Range

in tape and reel SOIC, SSOP, and

QFN/UQFN packages only.

Pattern:

QTP, SQTP, Code or Special Requirements

(blank otherwise)

 2010 Microchip Technology Inc.

Preliminary

DS41391C-page 405

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Cleveland

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-6578-300

Fax: 886-3-6578-370

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

01/05/10

DS41391C-page 406

Preliminary

 2010 Microchip Technology Inc.


型号：	PIC16LF1827-I/MV
厂家：	MICROCHIP
描述：	18/20/28-Pin Flash Microcontrollers with nanoWatt XLP Technology 18 /20/ 28引脚闪存单片机采用纳瓦XLP技术闪存微控制器和处理器外围集成电路时钟
文件：	总406页 (文件大小：3969K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC16LF1827-I/MV [MICROCHIP]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E