PIC16LF628T-20I/SS [MICROCHIP]
FLASH-Based 8-Bit CMOS Microcontrollers; 基于闪存的8位CMOS微控制器
| 型号： | PIC16LF628T-20I/SS |
| 厂家： | 
MICROCHIP |
| 描述： | FLASH-Based 8-Bit CMOS Microcontrollers |
| 文件： | 总160页 (文件大小：1657K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC16F62X
FLASH-Based 8-Bit CMOS Microcontrollers
Devices included in this data sheet:
• PIC16F627 • PIC16F628
Special Microcontroller Features:
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
Referred to collectively as PIC16F62X .
High Performance RISC CPU:
• Brown-out Detect (BOD)
• Only 35 instructions to learn
• All single-cycle instructions (200 ns), except for
program branches which are two-cycle
• Operating speed:
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Multiplexed MCLR-pin
• Programmable weak pull-ups on PORTB
• Programmable code protection
• Low voltage programming
• Power saving SLEEP mode
• Selectable oscillator options
- FLASH configuration bits for oscillator options
- ER (External Resistor) oscillator
- Reduced part count
- DC - 20 MHz clock input
- DC - 200 ns instruction cycle
Memory
Device
FLASH
Program
RAM
Data
EEPROM
Data
PIC16F627
PIC16F628
1024 x 14
2048 x 14
224 x 8
224 x 8
128 x 8
128 x 8
• Interrupt capability
• 16 special function hardware registers
• 8-level deep hardware stack
- Dual speed INTRC
- Lower current consumption
- EC External Clock input
• Direct, Indirect and Relative addressing modes
- XT oscillator mode
Peripheral Features:
- HS oscillator mode
• 15 I/O pins with individual direction control
• High current sink/source for direct LED drive
• Analog comparator module with:
- Two analog comparators
- LP oscillator mode
• Serial in-circuit programming (via two pins)
• Four user programmable ID locations
- Programmable on-chip voltage reference
(VREF) module
CMOS Technology:
• Low-power, high-speed CMOS FLASH technology
• Fully static design
• Wide operating voltage range
- PIC16F627 - 3.0V to 5.5V
- Programmable input multiplexing from device
inputs and internal voltage reference
- Comparator outputs are externally accessible
• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
- PIC16F628 - 3.0V to 5.5V
- PIC16LF627 - 2.0V to 5.5V
- PIC16LF628 - 2.0V to 5.5V
• Timer1: 16-bit timer/counter with external crystal/
clock capability
• Timer2: 8-bit timer/counter with 8-bit period regis-
ter, prescaler and postscaler
• Commercial, industrial and extended temperature
range
• Capture, Compare, PWM (CCP) module
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• Low power consumption
- < 2.0 mA @ 5.0V, 4.0 MHz
- 15 µA typical @ 3.0V, 32 kHz
- < 1.0 µA typical standby current @ 3.0V
• Universal Synchronous/Asynchronous Receiver/
Transmitter USART/SCI
• 16 Bytes of common RAM
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 1
PIC16F62X
Pin Diagrams
PDIP, SOIC
RA2/AN2/VREF
RA3/AN3/CMP1
RA4/TOCKI/CMP2
RA1/AN1
RA0/AN0
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD
RB7/T1OSI
RB6/T1OSO/T1CKI
RB5
RB4/PGM
•1
18
17
16
15
14
13
12
11
10
2
3
4
5
6
7
8
9
RA5/MCLR/THV
VSS
RB0/INT
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
SSOP
RA2/AN2/VREF
RA3/AN3/CMP1
RA4/TOCKI/CMP2
RA1/AN1
RA0/AN0
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
•1
20
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
RA5/MCLR/THV
VSS
VSS
VDD
VDD
RB7/T1OSI
RB6/T1OSO/T1CKI
RB5
RB0/INT
RB1/RX/DT
RB2/TX/CK
12
11
10
RB3/CCP1
RB4/PGM
Device Differences
Device
Process
Technology
(Microns)
Voltage
Range
Oscillator
PIC16F627
PIC16F628
PIC16LF627
PIC16LF628
3.0 - 5.5
3.0 - 5.5
2.0 - 5.5
2.0 - 5.5
See Note 1
See Note 1
See Note 1
See Note 1
0.7
0.7
0.7
0.7
Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.
DS40300B-page 2
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
Table of Contents
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
General Description..................................................................................................................................................................... 5
PIC16F62X Device Varieties...................................................................................................................................................... 7
Architectural Overview ................................................................................................................................................................ 9
Memory Organization................................................................................................................................................................ 13
I/O Ports .................................................................................................................................................................................... 27
Timer0 Module .......................................................................................................................................................................... 45
Timer1 Module .......................................................................................................................................................................... 50
Timer2 Module .......................................................................................................................................................................... 54
Comparator Module................................................................................................................................................................... 57
10.0 Capture/Compare/PWM (CCP) Module .................................................................................................................................... 63
11.0 Voltage Reference Module........................................................................................................................................................ 69
12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART).................................................................................... 71
13.0 Data EEPROM Memory ............................................................................................................................................................ 91
14.0 Special Features of the CPU..................................................................................................................................................... 95
15.0 Instruction Set Summary......................................................................................................................................................... 113
16.0 Development Support.............................................................................................................................................................. 125
17.0 Electrical Specifications........................................................................................................................................................... 131
18.0 Device Characterization Information ....................................................................................................................................... 145
19.0 Packaging Information............................................................................................................................................................. 147
Index .................................................................................................................................................................................................. 151
On-Line Support................................................................................................................................................................................. 155
Reader Response.............................................................................................................................................................................. 156
PIC16F62X Product Identification System........................................................................................................................................ 157
To Our Valued Customers
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revi-
sion of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
•
•
•
Microchip’s Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter-
ature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure
that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing
or appears in error, please:
•
•
Fill out and mail in the reader response form in the back of this data sheet.
E-mail us at webmaster@microchip.com.
We appreciate your assistance in making this a better document.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 3
PIC16F62X
NOTES:
DS40300B-page 4
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
1.1
Development Support
1.0
GENERAL DESCRIPTION
The PIC16F62X family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low-cost development programmer and a
full-featured programmer. A Third Party “C” compiler
support tool is also available.
The PIC16F62X are 18-Pin FLASH-based members of
the versatile PIC16CXX family of low-cost,
high-performance,
microcontrollers.
CMOS,
fully-static,
8-bit
All PICmicro® microcontrollers employ an advanced
RISC architecture. The PIC16F62X have enhanced
core features, eight-level deep stack, and multiple inter-
nal and external interrupt sources. The separate
instruction and data buses of the Harvard architecture
allow a 14-bit wide instruction word with the separate
8-bit wide data. The two-stage instruction pipeline
allows all instructions to execute in a single-cycle,
except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set gives
some of the architectural innovations used to achieve a
very high performance.
PIC16F62X microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
PIC16F62X devices have special features to reduce
external components, thus reducing system cost,
enhancing system reliability and reducing power con-
sumption. There are eight oscillator configurations, of
which the single pin ER oscillator provides a low-cost
solution. The LP oscillator minimizes power consump-
tion, XT is a standard crystal, INTRC is a self-contained
internal oscillator and the HS is for High Speed crys-
tals. The SLEEP (power-down) mode offers power sav-
ings. The user can wake up the chip from SLEEP
through several external and internal interrupts and
reset.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software
lock- up.
Table 1-1 shows the features of the PIC16F62X
mid-range microcontroller families.
A simplified block diagram of the PIC16F62X is shown
in Figure 3-1.
The PIC16F62X series fits in applications ranging from
battery chargers to low-power remote sensors. The
FLASH technology makes customization of application
programs (detection levels, pulse generation, timers,
etc.) extremely fast and convenient. The small footprint
packages make this microcontroller series ideal for all
applications with space limitations. Low-cost,
low-power, high-performance, ease of use and I/O flex-
ibility make the PIC16F62X very versatile.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 5
PIC16F62X
TABLE 1-1:
PIC16F62X FAMILY OF DEVICES
PIC16F627
PIC16F628
PIC16LF627
PIC16LF628
Maximum Frequency
of Operation (MHz)
20
20
20
20
Clock
FLASH Program Memory (words) 1024
2048
224
1024
224
2048
Memory
RAM Data Memory (bytes)
EEPROM Data Memory (bytes)
Timer Module(s)
224
128
224
128
128
128
TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2
TMR0, TMR1, TMR2
Comparators(s)
2
2
2
2
Peripherals
Capture/Compare/PWM modules
Serial Communications
Internal Voltage Reference
Interrupt Sources
1
1
1
1
USART
Yes
10
USART
Yes
10
USART
Yes
10
USART
Yes
10
I/O Pins
16
16
16
16
Voltage Range (Volts)
Brown-out Detect
3.0-5.5
Yes
3.0-5.5
Yes
2.0-5.5
Yes
2.0-5.5
Yes
Features
Packages
18-pin DIP,
SOIC;
18-pin DIP,
SOIC;
18-pin DIP,
SOIC;
18-pin DIP,
SOIC;
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
®
All PICmicro Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current
capability. All PIC16F62X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS40300B-page 6
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
2.0
PIC16F62X DEVICE VARIETIES
A variety of frequency ranges and packaging options are
available. Depending on application and production
requirements the proper device option can be selected
using the information in the PIC16F62X Product
Identification System section at the end of this data
sheet. When placing orders, please use this page of the
data sheet to specify the correct part number.
2.1
Flash Devices
These devices are offered in the lower cost plastic
package, even though the device can be erased and
reprogrammed. This allows the same device to be used
for prototype development and pilot programs as well
as production.
A further advantage of the electrically-erasable Flash
version is that it can be erased and reprogrammed
in-circuit, or by device programmers, such as
Microchip’s PICSTART® Plus or PRO MATE® II
programmers.
2.2
Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who chose not to program a medium
to high quantity of units and whose code patterns have
stabilized. The devices are standard FLASH devices
but with all program locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before
production shipments are available. Please contact
your Microchip Technology sales office for more details.
2.3
Serialized
Quick-Turnaround-Production
(SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 7
PIC16F62X
NOTES:
DS40300B-page 8
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
The PIC16F62X devices contain an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16F62X family can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16F62X uses a Harvard architecture, in
which, program and data are accessed from separate
memories using separate busses. This improves
bandwidth over traditional von Neumann architecture
where program and data are fetched from the same
memory. Separating program and data memory further
allows instructions to be sized differently than 8-bit wide
data word. Instruction opcodes are 14-bits wide making
it possible to have all single word instructions. A 14-bit
wide program memory access bus fetches a 14-bit
instruction in a single cycle. A two-stage pipeline over-
laps fetch and execution of instructions. Consequently,
all instructions (35) execute in a single-cycle (200 ns @
20 MHz) except for program branches.
The ALU is 8-bit wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a Borrow and Digit Borrow out bit,
respectively, bit in subtraction. See the SUBLW and
SUBWFinstructions for examples.
The Table below lists program memory (Flash, Data
and EEPROM).
Memory
A simplified block diagram is shown in Figure 3-1, with
a description of the device pins in Table 3-1.
Device
FLASH
Program
RAM
Data
EEPROM
Data
Two types of data memory are provided on the
PIC16F62X devices. Non-volatile EEPROM data
memory is provided for long term storage of data such
as calibration values, look up table data, and any other
data which may require periodic updating in the field.
This data is not lost when power is removed. The other
data memory provided is regular RAM data memory.
Regular RAM data memory is provided for temporary
storage of data during normal operation. It is lost when
power is removed.
PIC16F627
PIC16F628
PIC16LF627
PIC16LF628
1024 x 14
2048 x 14
1024 x 14
2048 x 14
224 x 8
224 x 8
224 x 8
224 x 8
128 x 8
128 x 8
128 x 8
128 x 8
The PIC16F62X can directly or indirectly address its
register files or data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC16F62X have an orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC16F62X simple yet efficient. In addition, the
learning curve is reduced significantly.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 9
PIC16F62X
FIGURE 3-1:
BLOCK DIAGRAM
13
8
Data Bus
RAM
Program Counter
FLASH
Program
Memory
Data EEPROM
8 Level Stack
(13-bit)
File
Registers
Program
Bus
14
PORTA
RAM Addr (1)
9
Addr MUX
RA0/AN0
RA1/AN1
Instruction reg
Indirect
Addr
7
Direct Addr
RA2/AN2/VREF
RA3/AN3/CMP1
RA4/T0CK1/CMP2
RA5/MCLR/THV
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
8
FSR reg
STATUS reg
8
3
PORTB
MUX
Power-up
Timer
RB0/INT
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
RB4/PGM
RB5
Oscillator
Instruction
Decode &
Control
Start-up Timer
ALU
Power-on
Reset
8
Timing
Generation
Watchdog
Timer
RB6/T1OSO/T1CKI
RB7/T1OSI
W reg
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Detect
Low-Voltage
Programming
MCLR VDD, VSS
Timer0
CCP1
Timer1
Timer2
Comparator
USART
VREF
Memory
Device
FLASH
Program
RAM
Data
EEPROM
Data
PIC16F627
1024 x 14
2048 x 14
1024 x 14
2048 x 14
224 x 8
224 x 8
224 x 8
224 x 8
128 x 8
128 x 8
128 x 8
128 x 8
PIC16F628
PIC16LF627
PIC16LF628
Note 1: Higher order bits are from the STATUS register.
DS40300B-page 10
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
TABLE 3-1:
Name
PIC16F62X PINOUT DESCRIPTION
DIP/
SSOP
Pin #
I/O/P
Type
Buffer
Type
SOIC
Pin #
Description
RA0/AN0
17
18
1
19
20
1
I/O
I/O
I/O
ST
ST
ST
Bi-directional I/O port/Analog comparator input
Bi-directional I/O port/Analog comparator input
RA1/AN1
RA2/AN2/VREF
Bi-directional I/O port/Analog comparator input/VREF out-
put
RA3/AN3/CMP1
RA4/T0CKI/CMP2
RA5/MCLR/THV
2
3
4
2
3
4
I/O
I/O
I
ST
ST
ST
Bi-directional I/O port/Analog comparator input/compara-
tor output
Bi-directional I/O port/Can be configured as T0CKI/com-
parator output
Input port/master clear (reset input/programming voltage
input. When configured as MCLR, this pin is an active low
reset to the device. Voltage on MCLR/THV must not
exceed VDD during normal device operation.
RA6/OSC2/CLKOUT
15
17
I/O
ST
ST
Bi-directional I/O port/Oscillator crystal output. Connects
to crystal or resonator in crystal oscillator mode. In ER
mode, OSC2 pin outputs CLKOUT which has 1/4 the fre-
quency of OSC1, and denotes the instruction cycle rate.
RA7/OSC1/CLKIN
RB0/INT
16
6
18
7
I/O
I/O
I/O
Bi-directional I/O port/Oscillator crystal input/external
clock source input. ER biasing pin.
(1)
Bi-directional I/O port/external interrupt. Can be software
programmed for internal weak pull-up.
TTL/ST
(3)
RB1/RX/DT
7
8
TTL/ST
Bi-directional I/O port/ USART receive pin/synchronous
data I/O. Can be software programmed for internal weak
pull-up.
(3)
RB2/TX/CK
8
9
I/O
TTL/ST
Bi-directional I/O port/ USART transmit pin/synchronous
clock I/O. Can be software programmed for internal weak
pull-up.
(4)
(5)
RB3/CCP1
RB4/PGM
9
10
11
I/O
I/O
TTL/ST
Bi-directional I/O port/Capture/Compare/PWM I/O. Can
be software programmed for internal weak pull-up.
10
TTL/ST
Bi-directional I/O port/Low voltage programming input pin.
Wake-up from SLEEP on pin change. Can be software
programmed for internal weak pull-up. When low voltage
programming is enabled, the interrupt on pin change and
weak pull-up resistor are disabled.
RB5
11
12
13
12
13
14
I/O
I/O
I/O
TTL
TTL/ST
TTL/ST
Bi-directional I/O port/Wake-up from SLEEP on pin
change. Can be software programmed for internal weak
pull-up.
(2)
(2)
RB6/T1OSO/T1CKI
RB7/T1OSI
Bi-directional I/O port/Timer1 oscillator output/Timer1
clock input. Wake up from SLEEP on pin change. Can be
software programmed for internal weak pull-up.
Bi-directional I/O port/Timer1 oscillator input. Wake up
from SLEEP on pin change. Can be software programmed
for internal weak pull-up.
VSS
5
5,6
P
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
VDD
14
15,16
P
Legend:
O = output
I/O = input/output
P = power
— = Not used
I = Input
ST = Schmitt Trigger input
TTL = TTL input
I/OD =input/open drain output
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
Note 3: This buffer is a Schmitt Trigger I/O when used in USART/Synchronous mode.
Note 4: This buffer is a Schmitt Trigger I/O when used in CCP mode.
Note 5: This buffer is a Schmitt Trigger input when used in low voltage program mode.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 11
PIC16F62X
3.1
Clocking Scheme/Instruction Cycle
3.2
Instruction Flow/Pipelining
The clock input (OSC1/CLKIN/RA7 pin) is internally
divided by four to generate four non-overlapping
quadrature clocks namely Q1, Q2, Q3 and Q4. Inter-
nally, the program counter (PC) is incremented every
Q1, the instruction is fetched from the program memory
and latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2.
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
phase
clock
Q4
PC
PC
PC+1
PC+2
OSC2/CLKOUT
(ER mode)
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
3. CALL SUB_1
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS40300B-page 12
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
FIGURE 4-2: PROGRAM MEMORY MAP AND
STACK FOR THE PIC16F628
4.0
MEMORY ORGANIZATION
4.1
Program Memory Organization
PC<12:0>
The PIC16F62X has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. Only
the first 1K x 14 (0000h - 03FFh) for the PIC16F627
and 2K x 14 (0000h - 07FFh) for the PIC16F628 are
physically implemented. Accessing a location above
these boundaries will cause a wrap-around within the
first 1K x 14 space (PIC16F627) or 2K x 14 space
(PIC16F628). The reset vector is at 0000h and the
interrupt vector is at 0004h (Figure 4-1 and Figure 4-2).
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
000h
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F627
Interrupt Vector
0004
0005
PC<12:0>
CALL, RETURN
13
RETFIE, RETLW
On-chip Program
Memory
Stack Level 1
Stack Level 2
07FFh
0800h
Stack Level 8
1FFFh
Reset Vector
000h
4.2
Data Memory Organization
The data memory (Figure 4-3) is partitioned into four
Banks which contain the general purpose registers and
the special function registers. The Special Function
Registers are located in the first 32 locations of each
Bank. Register locations 20-7Fh, A0h-FFh, 120h-14Fh,
170h-17Fh and 1F0h-1FFh are general purpose regis-
ters implemented as static RAM.
Interrupt Vector
0004
0005
On-chip Program
Memory
03FFh
0400h
The Table below lists how to access the four banks of
registers:
RP1
RP0
1FFFh
Bank0
Bank1
Bank2
Bank3
0
0
1
1
0
1
0
1
Addresses F0h-FFh, 170h-17Fh and 1F0h-1FFh are
implemented as common RAM and mapped back to
addresses 70h-7Fh.
4.2.1
GENERAL PURPOSE REGISTER FILE
The register file is organized as 224 x 8 in the
PIC16F62X. Each is accessed either directly or indi-
rectly through the File Select Register FSR
(Section 4.4).
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 13
PIC16F62X
FIGURE 4-3: DATA MEMORY MAP OF THE PIC16F627 AND PIC16F628
File
Address
Indirect addr.(*)
Indirect addr.(*)
OPTION
PCL
Indirect addr.(*)
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
Indirect addr.(*)
TMR0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
TMR0
PCL
OPTION
PCL
PCL
STATUS
FSR
STATUS
FSR
STATUS
FSR
STATUS
FSR
PORTA
PORTB
TRISA
TRISB
TRISB
PORTB
PCLATH
INTCON
PCLATH
INTCON
PIR1
PCLATH
INTCON
PCLATH
INTCON
PIE1
TMR1L
TMR1H
T1CON
TMR2
PCON
T2CON
PR2
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
TXSTA
SPBRG
EEDATA
EEADR
EECON1
EECON2*
CMCON
VRCON
11Fh
120h
General
Purpose
Register
48 Bytes
General
Purpose
Register
80 Bytes
A0h
14Fh
150h
General
Purpose
Register
1EFh
1F0h
EFh
F0h
16Fh
170h
96 Bytes
accesses
70h-7Fh
accesses
70h - 7Fh
accesses
70h-7Fh
17Fh
1FFh
7Fh
FFh
Bank 3
Bank 1
Bank 2
Bank 0
Unimplemented data memory locations, read as ’0’.
Not a physical register.
*
DS40300B-page 14
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
4.2.2
SPECIAL FUNCTION REGISTERS
The special registers can be classified into two sets
(core and peripheral). The special function registers
associated with the “core” functions are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.
The special function registers are registers used by the
CPU and Peripheral functions for controlling the
desired operation of the device (Table 4-1). These
registers are static RAM.
TABLE 4-1:
SPECIAL REGISTERS SUMMARY BANK0
Value on
all other
Value on
POR
Reset
Address
Bank 0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
Resets
00h
01h
02h
03h
INDF
TMR0
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module’s Register
xxxx xxxx xxxx xxxx
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
PCL
Program Counter's (PC) Least Significant Byte
STATUS
RP0
TO
PD
Z
DC
C
IRP
RP1
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
FSR
Indirect data memory address pointer
xxxx xxxx uuuu uuuu
xxxx 0000 xxxx 0000
xxxx xxxx uuuu uuuu
PORTA
RA7
RB7
RA6
RB6
RA5
RB5
RA4
RB4
RA3
RB3
RA2
RB2
RA1
RB1
RA0
RB0
PORTB
Unimplemented
Unimplemented
Unimplemented
PCLATH
—
—
—
—
—
—
—
—
—
Write buffer for upper 5 bits of program counter
---0 0000 ---0 0000
0000 000x 0000 000u
0000 -000 0000 -000
INTCON
GIE
PEIE
CMIF
T0IE
INTE
TXIF
RBIE
T0IF
INTF
RBIF
PIR1
EEIF
RCIF
—
CCP1IF
TMR2IF
TMR1IF
Unimplemented
TMR1L
—
—
Holding register for the least significant byte of the 16-bit TMR1
Holding register for the most significant byte of the 16-bit TMR1
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR1H
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
TMR2
TMR2 module’s register
0000 0000 0000 0000
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -uuu uuuu
Unimplemented
Unimplemented
CCPR1L
—
—
—
—
Capture/Compare/PWM register (LSB)
Capture/Compare/PWM register (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCPR1H
CCP1CON
RCSTA
—
—
CCP1X
SREN
CCP1Y
CREN
CCP1M3
ADEN
CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
SPEN
RX9
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0000 0000 0000
TXREG
USART Transmit data register
USART Receive data register
RCREG
Unimplemented
Unimplemented
Unimplemented
Unimplemented
CMCON
—
—
—
—
—
—
—
—
C2OUT C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0000 0000 0000
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: Other (non power-up) resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during
normal operation.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 15
PIC16F62X
TABLE 4-2:
SPECIAL FUNCTION REGISTERS SUMMARY BANK1
Value on
all other
resets(1)
Value on
POR
Reset
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 1
80h
INDF
OPTION
Addressing this location uses contents of FSR to address data memory (not a physical reg- xxxx xxxx
ister)
xxxx xxxx
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
RBPU
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect data memory address pointer
INTEDG
T0CS
T0SE
PSA
PD
PS2
Z
PS1
DC
PS0
C
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
11-1 1111
1111 1111
—
1111 1111
0000 0000
000q quuu
uuuu uuuu
11-1 1111
1111 1111
—
PCL
STATUS
FSR
TRISA
TRISA7 TRISA6
—
TRISA4 TRISA3 TRISA2
TRISA1
TRISB1
TRISA0
TRISB0
TRISB
TRISB7 TRISB6
TRISB5 TRISB4 TRISB3 TRISB2
Unimplemented
Unimplemented
Unimplemented
PCLATH
—
—
—
—
—
—
—
Write buffer for upper 5 bits of program counter
---0 0000
0000 000x
---0 0000
0000 000u
0000 -000
—
INTCON
GIE
EEIE
PEIE
CMIE
T0IE
INTE
TXIE
RBIE
—
T0IF
INTF
RBIF
PIE1
RCIE
CCP1IE
TMR2IE TMR1IE 0000 -000
Unimplemented
PCON
—
—
—
—
—
OSCF
—
POR
BOD
---- 1-0x
---- 1-uq
Unimplemented
Unimplemented
Unimplemented
PR2
—
—
—
—
Timer2 Period Register
11111111
—
11111111
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
TXSTA
—
—
—
—
—
—
—
—
CSRC
TX9
TXEN
SYNC
—
—
BRGH
TRMT
TX9D
0000 -010
0000 0000
xxxx xxxx
xxxx xxxx
---- x000
--------
—
0000 -010
0000 0000
uuuu uuuu
uuuu uuuu
---- q000
--------
—
SPBRG
Baud Rate Generator Register
EEPROM data register
EEDATA
EEADR
—
—
EEPROM address register
EECON1
—
—
WRERR WREN
WR
RD
EECON2
EEPROM control register 2 (not a physical register)
Unimplemented
VRCON
VREN VROE VRR VR3
—
VR2
VR1
VR0
000- 0000
000- 0000
Legend: : — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: Other (non power-up) resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during
normal operation.
DS40300B-page 16
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
TABLE 4-3:
SPECIAL FUNCTION REGISTERS SUMMARY BANK2
Value on
all other
resets(1)
Value on
POR
Reset
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 1
100h
INDF
TMR0
Addressing this location uses contents of FSR to address data memory (not a physical reg- xxxx xxxx
ister)
xxxx xxxx
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
RBPU
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect data memory address pointer
INTEDG
T0CS
T0SE
PSA
PD
PS2
Z
PS1
DC
PS0
C
1111 1111
1111 1111
PCL
0000 0000
0000 0000
STATUS
0001 1xxx
000q quuu
FSR
xxxx xxxx
uuuu uuuu
Unimplemented
PORTB
—
—
TRISB7 TRISB6
TRISB5 TRISB4 TRISB3 TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
Unimplemented
Unimplemented
Unimplemented
PCLATH
—
—
—
—
—
—
—
—
—
Write buffer for upper 5 bits of program counter
INTE RBIE T0IF INTF RBIF
---0 0000
---0 0000
INTCON
GIE
PEIE
T0IE
0000 000x
0000 000u
—
—
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unimplemented
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: Other (non power-up) resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during
normal operation.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 17
PIC16F62X
TABLE 4-4:
SPECIAL FUNCTION REGISTERS SUMMARY BANK3
Value on
all other
resets(1)
Value on
POR
Reset
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 1
180h
INDF
OPTION
Addressing this location uses contents of FSR to address data memory (not a physical reg- xxxx xxxx
ister)
xxxx xxxx
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
RBPU
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect data memory address pointer
INTEDG
T0CS
T0SE
PSA
PD
PS2
Z
PS1
DC
PS0
C
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
—
1111 1111
0000 0000
000q quuu
uuuu uuuu
—
PCL
STATUS
FSR
Unimplemented
TRISB
TRISB7 TRISB6
TRISB5 TRISB4 TRISB3 TRISB2
TRISB1
TRISB0
1111 1111
—
1111 1111
—
Unimplemented
Unimplemented
Unimplemented
PCLATH
—
—
—
—
—
—
—
Write buffer for upper 5 bits of program counter
INTE RBIE T0IF INTF RBIF
---0 0000
0000 000x
---0 0000
0000 000u
INTCON
GIE
PEIE
T0IE
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: Other (non power-up) resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during
normal operation.
DS40300B-page 18
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
4.2.2.1
STATUS REGISTER
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect any status bit. For other instructions, not affecting
any status bits, see the “Instruction Set Summary”.
The STATUS register, shown in Register 4-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory (SRAM).
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUSwill clear the upper-three
bits and set the Z bit. This leaves the status register as
000uu1uu(where u= unchanged).
REGISTER 4-1: STATUS REGISTER (ADDRESS 03H OR 83H)
R/W-0
IRP
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
R = Readable bit
W = Writable bit
bit7
bit0
U = Unimplemented bit,
read as ’0’
-n = Value at POR reset
-x = Unknown at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing)
1= Bank 2, 3 (100h - 1FFh)
0= Bank 0, 1 (00h - FFh)
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11= Bank 3 (180h - 1FFh)
10= Bank 2 (100h - 17Fh)
01= Bank 1 (80h - FFh)
00= Bank 0 (00h - 7Fh)
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)(for borrow the polarity is reversed)
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1= A carry-out from the most significant bit of the result occurred
0= No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 19
PIC16F62X
4.2.2.2
OPTION REGISTER
Note: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT
(PSA = 1). See Section 6.3.1
The OPTION register is a readable and writable
register which contains various control bits to configure
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0, and the weak pull-ups on PORTB.
REGISTER 4-2: OPTION REGISTER (ADDRESS 81H)
R/W-1
RBPU
bit7
R/W-1
R/W-1
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG T0CS
R = Readable bit
W = Writable bit
-n = Value at POR reset
bit0
bit 7:
RBPU: PORTB Pull-up Enable bit
1= PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
bit 6:
bit 5:
bit 4:
bit 3:
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
DS40300B-page 20
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
4.2.2.3
INTCON REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
The INTCON register is a readable and writable
register which contains the various enable and flag bits
for all interrupt sources except the comparator module.
See Section 4.2.2.4 and Section 4.2.2.5 for
description of the comparator enable and flag bits.
a
REGISTER 4-3: INTCON REGISTER (ADDRESS 0BH OR 8BH)
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
bit0
R = Readable bit
W = Writable bit
bit7
U = Unimplemented bit, read
as ’0’
-n = Value at POR reset
-x = Unknown at POR reset
bit 7:
GIE: Global Interrupt Enable bit
1= Enables all un-masked interrupts
0= Disables all interrupts
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
PEIE: Peripheral Interrupt Enable bit
1= Enables all un-masked peripheral interrupts
0= Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1= Enables the RB0/INT external interrupt
0= Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1= The RB0/INT external interrupt occurred (must be cleared in software)
0= The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 21
PIC16F62X
4.2.2.4
PIE1 REGISTER
This register contains interrupt enable bits.
REGISTER 4-4: PIE1 REGISTER (ADDRESS 8CH)
R/W-0
EEIE
bit7
R/W-0
CMIE
R/W-0
RCIE
R/W-0
TXIE
U
R/W-0
R/W-0
R/W-0
-
CCP1IE TMR2IE TMR1IE
R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ’0’
bit0
-n = Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
EEIE: EE Write Complete Interrupt Enable Bit
1= Enables the EE write complete interrupt
0= Disables the EE write complete interrupt
CMIE: Comparator Interrupt Enable bit
1= Enables the comparator interrupt
0= Disables the comparator interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
bit 3:
bit 2:
Unimplemented: Read as ‘0’
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
bit 1:
bit 0:
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
DS40300B-page 22
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
4.2.2.5
PIR1 REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
This register contains interrupt flag bits.
REGISTER 4-5: PIR1 REGISTER (ADDRESS 0CH)
R/W-0
EEIF
bit7
R/W-0
CMIF
R-0
R-0
U
R/W-0
R/W-0
R/W-0
RCIF
TXIF
-
CCP1IF TMR2IF TMR1IF
R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ’0’
bit0
-n = Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
EEIF: EEPROM Write Operation Interrupt Flag bit
1= The write operation completed (must be cleared in software)
0= The write operation has not completed or has not been started
CMIF: Comparator Interrupt Flag bit
1= Comparator input has changed
0= Comparator input has not changed
RCIF: USART Receive Interrupt Flag bit
1= The USART receive buffer is full
0= The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1= The USART transmit buffer is empty
0= The USART transmit buffer is full
bit 3:
bit 2:
Unimplemented: Read as ‘0’
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare Mode
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1:
bit 0:
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 23
PIC16F62X
4.2.2.6
PCON REGISTER
The PCON register contains flag bits to differentiate
between a Power-on Reset, an external MCLR reset,
WDT reset or a Brown-out Detect.
Note: BOD is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent resets to see if BOD is
cleared, indicating
a
brown-out has
occurred. The BOD status bit is a "don’t
care" and is not necessarily predictable if
the brown-out circuit is disabled (by
programming
BOREN
bit
in
the
Configuration word).
REGISTER 4-6: PCON REGISTER (ADDRESS 8Eh)
U-0
—
U-0
U-0
U-0
R/W-1
U-0
R/W-q
R/W-q
BOD
bit0
—
—
—
OSCF
—
POR
R = Readable bit
W = Writable bit
bit7
U = Unimplemented bit, read
as ’0’
-n = Value at POR reset
bit 7-4,2:Unimplemented: Read as '0'
bit 3:
bit 1:
bit 0:
OSCF: INTRC/ER oscillator speed
1= 4 MHz typical(1)
0= 37 KHz typical
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOD: Brown-out Detect Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: When in ER oscillator mode, setting OSCF = 1 will cause the oscillator speed to change to the speed
specified by the external resistor.
DS40300B-page 24
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
4.3.2
STACK
4.3
PCL and PCLATH
The PIC16F62X family has an 8 level deep x 13-bit
wide hardware stack (Figure 4-1 and Figure 4-2). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALLinstruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLWor a RET-
FIEinstruction execution. PCLATH is not affected by a
PUSH or POP operation.
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not directly
readable or writable and comes from PCLATH. On any
reset, the PC is cleared. Figure 4-7 shows the two
situations for the loading of the PC. The upper example in
the figure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the figure
shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> → PCH).
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
FIGURE 4-7: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
Note 1: There are no STATUS bits to
indicate stack overflow or stack
underflow conditions.
12
8
7
0
Instruction with
PCL as
Destination
PC
8
PCLATH<4:0>
PCLATH
5
Note 2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLWand RETFIE
instructions, or the vectoring to an
interrupt address.
ALU result
PCH
12 11 10
PCL
8
7
0
GOTO, CALL
PC
PCLATH<4:3>
PCLATH
11
2
Opcode <10:0>
4.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 25
PIC16F62X
4.4
Indirect Addressing, INDF and FSR
Registers
EXAMPLE 4-1: INDIRECT ADDRESSING
movlw 0x20
movwf FSR
;initialize pointer
;to RAM
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
NEXT
clrf
incf
INDF
FSR
;clear INDF register
;inc pointer
Indirect addressing is possible by using the INDF register.
Any instruction using the INDF register actually accesses
data pointed to by the file select register (FSR). Reading
INDF itself indirectly will produce 00h. Writing to the INDF
register indirectly results in a no-operation (although sta-
tus bits may be affected). An effective 9-bit address is
obtained by concatenating the 8-bit FSR register and the
IRP bit (STATUS<7>), as shown in Figure 4-8.
btfss FSR,4
;all done?
goto
NEXT
;no clear next
;yes continue
CONTINUE:
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 4-1.
FIGURE 4-8: DIRECT/INDIRECT ADDRESSING PIC16F62X
Direct Addressing
Indirect Addressing
from opcode
7
RP1 RP0
bank select
6
0
0
IRP
FSR register
bank select
180h
location select
location select
00
01
10
11
00h
Data
Memory
7Fh
1FFh
Bank 0
Bank 1 Bank 2
Bank 3
For memory map detail see Figure 4-3.
DS40300B-page 26
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
Note 1: On reset, the TRISA register is set to all
inputs. The digital inputs are disabled and
the comparator inputs are forced to
ground to reduce excess current con-
sumption.
5.0
I/O PORTS
The PIC16F62X have two ports, PORTA and PORTB.
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Note 2: When RA6/OSC2/CLKOUT is configured
as CLKOUT, the corresponding TRIS bit is
overridden and the pin is configured as an
output. The PORTA data bit reads 0, and
the PORTA TRIS bit reads 0.
5.1
PORTA and TRISA Registers
PORTA is an 8-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. Port RA4 is multiplexed
with the T0CKI clock input. RA5 is a Schmitt Trigger input
only and has no output drivers. All other RA port pins have
Schmitt Trigger input levels and full CMOS output drivers.
All pins have data direction bits (TRIS registers) which can
configure these pins as input or output.
TRISA controls the direction of the RA pins, even when
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs.
The RA2 pin will also function as the output for the
voltage reference. When in this mode, the VREF pin is a
very high impedance output. The user must configure
TRISA<2> bit as an input and use high impedance
loads.
A ’1’ in the TRISA register puts the corresponding output
driver in a hi- impedance mode. A ’0’ in the TRISA register
puts the contents of the output latch on the selected pin(s).
Reading the PORTA register reads the status of the pins
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then this
value is modified and written to the port data latch.
In one of the comparator modes defined by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA<4:3> bits must be
cleared to enable outputs to use this function.
EXAMPLE 5-1: INITIALIZING PORTA
The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(comparator control register) register and the VRCON
(voltage reference control register) register. When
selected as a comparator input, these pins will read
as ’0’s.
CLRF PORTA
;Initialize PORTA by setting
;output data latches
;Turn comparators off and
;enable pins for I/O
;functions
MOVLW 0X07
MOVWF CMCON
BCF
BSF
STATUS, RP1
STATUS, RP0 ;Select Bank1
MOVLW 0x1F
;Value used to initialize
;data direction
MOVWF TRISA
;Set RA<4:0> as inputs
;TRISA<7:5> are always
;read as ’0’.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 27
PIC16F62X
FIGURE 5-1: BLOCK DIAGRAM OF
RA0/AN0:RA1/AN1 PINS
FIGURE 5-2: BLOCK DIAGRAM OF
RA2/VREF PIN
Data
Bus
Data
Bus
D
Q
Q
D
Q
Q
VDD
VDD
VDD
P
VDD
P
WR
PORTA
WR
PORTA
CK
Data Latch
CK
Data Latch
D
Q
D
Q
RA2 Pin
I/O Pin
N
N
WR
WR
TRISA
TRISA
CK
Q
CK
TRIS Latch
Q
VSS
VSS
VSS
TRIS Latch
VSS
Analog
Input Mode
Analog
Input Mode
Schmitt Trigger
Input Buffer
Schmitt Trigger
Input Buffer
RD TRISA
RD TRISA
Q
D
Q
D
EN
EN
RD PORTA
RD PORTA
To Comparator
VROE
To Comparator
VREF
DS40300B-page 28
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
FIGURE 5-3: BLOCK DIAGRAM OF THE RA3/AN3 PIN
Data
Bus
Comparator Mode = 110
VDD
D
Q
Q
Comparator Output
VDD
WR
PORTA
1
0
CK
Data Latch
P
D
Q
RA3 Pin
N
WR
TRISA
CK
Q
VSS
VSS
TRIS Latch
Analog
Input Mode
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
To Comparator
FIGURE 5-4: BLOCK DIAGRAM OF RA4/T0CKI PIN
Data
Bus
Comparator Mode = 110
D
Q
Q
Comparator Output
WR
PORTA
1
0
CK
Data Latch
D
Q
RA4 Pin
N
WR
TRISA
CK
TRIS Latch
Q
VSS
VSS
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
TMR0 Clock Input
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 29
PIC16F62X
FIGURE 5-5: BLOCK DIAGRAM OF THE RA5/MCLR/THV PIN
MCLRE
MCLR circuit
VDD
MCLR Filter(1)
Program mode
HV Detect
RA5/MCLR/THV
VSS
Data
Bus
VDD
P
D
Q
Q
WR
PORT
CK
Data Latch
D
Q
WR
TRIS
N
CK
TRIS Latch
Q
VSS
RD TRIS
Q
D
EN
RD Port
DS40300B-page 30
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
FIGURE 5-6: BLOCK DIAGRAM OF RA6/OSC2/CLKOUT PIN
(Fosc=101,111)
From OSC1
CLKOUT (FOSC/4)
Oscillator
Circuit
1
0
VDD
RA6/OSC2/CLKOUT Pin
Data
Bus
VDD
P
D
Q
Q
VSS
WR
PORTA
CK
Data Latch
D
Q
WR
TRISA
N
VSS
CK
TRIS Latch
Q
(Fosc=100, 101, 110, 111)
RD TRISA
(Fosc=110, 100)
Schmitt Trigger
Input Buffer
Q
D
EN
RD PORTA
CLKOUT is 1/4 of the Fosc frequency.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 31
PIC16F62X
FIGURE 5-7: BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN
To OSC2
Oscillator
Circuit
VDD
CLKIN to core
VDD
Data
Bus
D
Q
Q
RA7/OSC1/CLKIN Pin
WR
PORTA
P
CK
Data Latch
Schmitt Trigger
VSS
D
Q
WR
TRISA
N
CK
TRIS Latch
Q
(Fosc=101, 100)
VSS
(Fosc=101, 100)
Schmitt Trigger
RD TRISA
Input Buffer
Q
D
EN
RD PORTA
DS40300B-page 32
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
TABLE 5-1:
Name
PORTA FUNCTIONS
Buffer
Bit #
Function
Type
RA0/AN0
bit0
bit1
bit2
bit3
bit4
ST
ST
ST
ST
ST
Bi-directional I/O port/comparator input
Bi-directional I/O port/comparator input
RA1/AN1
RA2/AN2/VREF
RA3/AN3
Bi-directional I/O port/analog/comparator input or VREF output
Bi-directional I/O port/analog/comparator input/comparator output
RA4/T0CKI
Bi-directional I/O port/external clock input for TMR0 or comparator output.
Output is open drain type.
RA5/MCLR/THV
bit5
bit6
ST
ST
Input port/master clear (reset input/programming voltage input. When
configured as MCLR, this pin is an active low reset to the device. Voltage
on MCLR/THV must not exceed VDD during normal device operation.
RA6/OSC2/CLK-
OUT
Bi-directional I/O port/Oscillator crystal output. Connects to crystal or res-
onator in crystal oscillator mode. In ER mode, OSC2 pin outputs CLKOUT
which has 1/4 the frequency of OSC1, and denotes the instruction cycle
rate.
RA7/OSC1/CLKIN
bit7
ST
Bi-directional I/O port/oscillator crystal input/external clock source input.
Legend: ST = Schmitt Trigger input
TABLE 5-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
Value on
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Other
Resets
05h
85h
1Fh
9Fh
PORTA
TRISA
RA7
RA6
RA5
—
RA4
RA3
RA2
RA1
RA0
xxxx 0000 xxxu 0000
TRISA7 TRISA6
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 11-1 1111 11-1 1111
CMCON
VRCON
C2OUT
VREN
C1OUT
VROE
C2INV
VRR
C1INV
—
CIS
CM2
VR2
CM1
VR1
CM0
VR0
0000 0000 0000 0000
000- 0000 000- 0000
VR3
Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown
Note: Shaded bits are not used by PORTA.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 33
PIC16F62X
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
5.2
PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The
corresponding data direction register is TRISB. A ’1’ in
the TRISB register puts the corresponding output driver
in a high impedance mode. A ’0’ in the TRISB register
puts the contents of the output latch on the selected
pin(s).
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
PORTB is multiplexed with the interrupt, USART, CCP
module and the TMR1 clock input/output. The standard
port functions and the alternate port functions are
shown in Table 5-3.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression. (See AN552 in the
Microchip Embedded Control Handbook.)
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
Each of the PORTB pins has a weak internal pull-up
(≈200 µA typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION<7>) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt
on change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RBIF interrupt (flag
latched in INTCON<0>).
DS40300B-page 34
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
FIGURE 5-8: BLOCK DIAGRAM OF RB0/INT PIN
VDD
VDD
RBPU
weak
P
pull-up
RB0/INT pin
Data Bus
D
Q
VSS
WR PORTB
CK
Data Latch
D
Q
WR TRISB
TTL
input
buffer
CK
TRIS Latch
Schmitt Trigger
Buffer
RD TRISB
Q
D
EN
RD PORTB
INT input
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 35
PIC16F62X
FIGURE 5-9: BLOCK DIAGRAM OF RB1/TX/DT PIN
VDD
weak pull-up
RBPU
P
PORT/PERIPHERAL Select(1)
USART data output
0
VDD
P
1
Data Bus
D
Q
Q
VDD
WR PORTB
WR TRISB
CK
Data Latch
RB1/RX/DT
pin
D
Q
Q
N
CK
VSS
TRIS Latch
VSS
RD TRISB
TTL
input
buffer
Peripheral OE(2)
Q
D
RD PORTB
EN
USART receive input
RD PORTB
Schmitt
Trigger
Note 1: Port/Peripheral select signal selects between port data and peripheral output.
Note 2: Peripheral OE( output enable) is only active if peripheral select is active.
DS40300B-page 36
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
FIGURE 5-10: BLOCK DIAGRAM OF RB2/TX/CK PIN
VDD
RBPU
weak pull-up
P
VDD
PORT/PERIPHERAL Select(1)
USART TX/CK output
0
1
VDD
Data Bus
RB2/TX/CK
pin
D
Q
Q
P
WR PORTB
CK
VSS
Data Latch
D
Q
Q
WR TRISB
N
CK
TRIS Latch
Vss
RD TRISB
TTL
input
buffer
Peripheral OE(2)
Q
D
RD PORTB
EN
USART Slave Clock in
RD PORTB
Schmitt
Trigger
Note 1: Port/Peripheral select signal selects between port data and peripheral output.
Note 2: Peripheral OE( output enable) is only active if peripheral select is active.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 37
PIC16F62X
FIGURE 5-11: BLOCK DIAGRAM OF THE RB3/CCP1 PIN
VDD
P
RBPU
weak pull-up
Port/Peripheral Select(1)
PWM/Compare output
0
1
VDD
P
Data Bus
D
Q
Q
VDD
WR PORTB
WR TRISB
CK
Data Latch
RB3/CCP1
pin
D
Q
N
CK
Q
VSS
TRIS Latch
Vss
RD TRISB
TTL
input
buffer
Q
D
RD PORTB
EN
CCP input
Schmitt
Trigger
RD PORTB
Note 1: Peripheral Select is defined by CCP1M3:CCP1M0. (CCP1CON<3:0>)
DS40300B-page 38
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
FIGURE 5-12: BLOCK DIAGRAM OF RB4/PGM PIN
VDD
RBPU
P
weak pull-up
VDD
P
Data Bus
D
Q
Q
VDD
WR PORTB
WR TRISB
CK
Data Latch
RB4/PGM
D
Q
Q
N
CK
VSS
TRIS Latch
VSS
RD TRISB
LVP
RD PORTB
PGM input
TTL
input
buffer
Schmitt
Trigger
Q
D
Q1
EN
Set RBIF
Q
D
From other
RB<7:4> pins
RD Port
Q3
EN
Note:
The low voltage programming disables the interrupt on change and the weak pullups on RB4.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 39
PIC16F62X
FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN
VDD
weak
RBPU
VDD
P
pull-up
Data Bus
D
Q
RB5 pin
WR PORTB
CK
Data Latch
VSS
D
Q
WR TRISB
CK
TRIS Latch
TTL
input
buffer
RD TRISB
Q
D
RD PORTB
Q1
EN
Set RBIF
Q
D
From other
RB<7:4> pins
RD Port
Q3
EN
DS40300B-page 40
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
FIGURE 5-14: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI PIN
VDD
RBPU
P
weak pull-up
VDD
P
Data Bus
D
Q
Q
VDD
WR PORTB
WR TRISB
CK
Data Latch
RB6/
D
Q
Q
T1OSO/
T1CKI
pin
N
CK
VSS
TRIS Latch
VSS
RD TRISB
T1OSCEN
TTL
input
buffer
RD PORTB
TMR1 Clock
Schmitt
Trigger
From RB7
TMR1 oscillator
Serial programming clock
Q
D
Q1
EN
Set RBIF
Q
D
From other
RB<7:4> pins
RD Port
Q3
EN
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 41
PIC16F62X
FIGURE 5-15: BLOCK DIAGRAM OF THE RB7/T1OSI PIN
VDD
RBPU
TMR1 oscillator
weak pull-up
P
To RB6
T1OSCEN
VDD
VDD
P
Data Bus
D
Q
Q
WR PORTB
WR TRISB
RB7/T1OSI
pin
CK
Data Latch
D
Q
Q
VSS
N
CK
TRIS Latch
Vss
RD TRISB
T10SCEN
TTL
input
RD PORTB
buffer
Serial programming input
Schmitt
Trigger
Q
D
Q1
EN
Set RBIF
Q
D
From other
RB<7:4> pins
RD Port
Q3
EN
DS40300B-page 42
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
TABLE 5-3:
PORTB FUNCTIONS
Buffer
Bit #
Name
Function
Type
TTL/ST(1)
bit0
RB0/INT
Bi-directional I/O port/external interrupt. Can be software programmed for
internal weak pull-up.
TTL/ST(3)
bit1
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
RB4/PGM
Bi-directional I/O port/ USART receive pin/synchronous data I/O. Can be
software programmed for internal weak pull-up.
TTL/ST(3)
bit2
Bi-directional I/O port/ USART transmit pin/synchronous clock I/O. Can be
software programmed for internal weak pull-up.
TTL/ST(4)
bit3
Bi-directional I/O port/Capture/Compare/PWM I/O. Can be software pro-
grammed for internal weak pull-up.
TTL/ST(5)
bit4
Bi-directional I/O port/Low voltage programming input pin. Wake-up from
SLEEP on pin change. Can be software programmed for internal weak
pull-up. When low voltage programming is enabled, the interrupt on pin
change and weak pull-up resistor are disabled.
RB5
bit5
bit6
TTL
Bi-directional I/O port/Wake-up from SLEEP on pin change. Can be soft-
ware programmed for internal weak pull-up.
TTL/ST(2)
RB6/T1OSO/T1CKI
Bi-directional I/O port/Timer1 oscillator output/Timer1 clock input. Wake up
from SLEEP on pin change. Can be software programmed for internal weak
pull-up.
TTL/ST(2)
RB7/T1OSI
bit7
Bi-directional I/O port/Timer1 oscillator input. Wake up from SLEEP on pin
change. Can be software programmed for internal weak pull-up.
Legend: ST = Schmitt Trigger, TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
Note 3: This buffer is a Schmitt Trigger I/O when used in USART/synchronous mode.
Note 4: This buffer is a Schmitt Trigger I/O when used in CCP mode.
Note 5: This buffer is a Schmitt Trigger input when used in low voltage program mode.
TABLE 5-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORT
Value on
All Other
Resets
Value on
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
06h
86h
81h
PORTB
TRISB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx uuuu uuuu
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
OPTION
RBPU INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
Legend: u = unchanged, x = unknown
Note: Shaded bits are not used by PORTB.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 43
PIC16F62X
5.3
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
EXAMPLE 5-2: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
5.3.1
I/O PORT
;Initial PORT settings: PORTB<7:4> Inputs
;
Any instruction which writes, operates internally as a
read followed by a write operation. The BCFand BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result back
to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSFoperation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSFoperation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bidirectional I/O pin
(e.g., bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and re-written to the data latch of this
particular pin, overwriting the previous content. As long
as the pin stays in the input mode, no problem occurs.
However, if bit0 is switched into output mode later on,
the content of the data latch may now be unknown.
;
PORTB<3:0> Outputs
;PORTB<7:6> have external pull-up and are not
;connected to other circuitry
;
;
;
PORT latch PORT pins
---------- ----------
BDF STATUS,RPO
BCF PORTB, 7
BCF PORTB, 6
BSF STATUS,RP0
BCF TRISB, 7
BCF TRISB, 6
;
;01pp pppp 11pp pppp
;10pp pppp 11pp pppp
;
;10pp pppp 11pp pppp
;10pp pppp 10pp pppp
;
;Note that the user may have expected the pin
;values to be 00pp pppp. The 2nd BCF caused
;RB7 to be latched as the pin value (High).
5.3.2
SUCCESSIVE OPERATIONS ON I/O PORTS
Reading a port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read modify write instructions
(ex. BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle
(Figure 5-16). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load
dependent) before the next instruction which causes
that file to be read into the CPU is executed. Otherwise,
the previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with a NOP or another
instruction not accessing this I/O port.
Example 5-2 shows the effect of two sequential
read-modify-write instructions (ex., BCF, BSF, etc.) on
an I/O port.
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage
the chip.
FIGURE 5-16: SUCCESSIVE I/O OPERATION
Note:
Q1 Q2 Q3 Q4 Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
1 QQ4 2 4 Q
This example shows write to PORTB
followed by a read from PORTB.
PC
PC + 1
PC + 2
PC
PC
PC
PC + 3
PC
Instruction
MOWF PORTB
MOVF PORTB, W
NOP
NOP
fetched
Note that:
Write to PORTB
Read to PORTB
data setup time = (0.25 TCY - TPD)
where TCY = instruction cycle and
TPD = propagation delay of Q1 cycle
to output valid.
RB<7:0>
Port pin
sampled here
Therefore, at higher clock frequencies,
a write followed by a read may be
problematic.
TPD
Execute
Execute
Execute
MOVWF
MOVWF
NOP
PORTB
PORTB
DS40300B-page 44
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
bit (OPTION<4>). Clearing the T0SE bit selects the
rising edge. Restrictions on the external clock input are
discussed in detail in Section 6.2.
6.0
TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
The prescaler is shared between the Timer0 module
and the Watchdog Timer. The prescaler assignment is
controlled in software by the control bit PSA
(OPTION<3>). Clearing the PSA bit will assign the
prescaler to Timer0. The prescaler is not readable or
writable. When the prescaler is assigned to the Timer0
module, prescale value of 1:2, 1:4, ..., 1:256 are
selectable. Section 6.3 details the operation of the
prescaler.
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 6-1 is a simplified block diagram of the Timer0
module.
6.1
TIMER0 Interrupt
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In timer mode, the TMR0 will increment
every instruction cycle (without prescaler). If Timer0 is
written, the increment is inhibited for the following two
cycles (Figure 6-2 and Figure 6-3). The user can work
around this by writing an adjusted value to TMR0.
Timer0 interrupt is generated when the TMR0 register
timer/counter overflows from FFh to 00h. This overflow
sets the T0IF bit. The interrupt can be masked by
clearing the T0IE bit (INTCON<5>). The T0IF bit
(INTCON<2>) must be cleared in software by the
Timer0 module interrupt service routine before
re-enabling this interrupt. The Timer0 interrupt cannot
wake the processor from SLEEP since the timer is shut
off during SLEEP. See Figure 6-4 for Timer0 interrupt
timing.
Counter mode is selected by setting the T0CS bit. In
this mode Timer0 will increment either on every rising
or falling edge of pin RA4/T0CKI. The incrementing
edge is determined by the source edge (T0SE) control
FIGURE 6-1: TIMER0 BLOCK DIAGRAM
Data bus
RA4/T0CKI
pin
FOSC/4
0
1
PSout
8
1
0
Sync with
Internal
clocks
TMR0
Programmable
Prescaler
PSout
(2 TCY delay)
T0SE
Set Flag bit T0IF
on Overflow
PS2:PS0
PSA
T0CS
Note 1: Bits T0SE, T0CS, PS2, PS1, PS0 and PSA are located in the OPTION register.
2: The prescaler is shared with Watchdog Timer (Figure 6-6)
FIGURE 6-2: TIMER0 (TMR0) TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
Instruction
Fetch
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
NT0
T0
T0+1
T0+2
NT0+1
NT0+2
TMR0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 45
PIC16F62X
FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
Instruction
Fetch
T0
T0+1
NT0+1
NT0
TMR0
Instruction
Execute
Read TMR0
reads NT0
Read TMR0 Read TMR0 Read TMR0
reads NT0 reads NT0 reads NT0
Read TMR0
reads NT0 + 1
Write TMR0
executed
FIGURE 6-4: TIMER0 INTERRUPT TIMING
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
OSC1
CLKOUT(3)
TMR0 timer
FEh
1
FFh
1
00h
01h
02h
T0IF bit
(INTCON<2>)
GIE bit
(INTCON<7>)
Interrupt Latency Time
PC +1
INSTRUCTION FLOW
PC
PC
PC +1
0004h
0005h
Instruction
fetched
Inst (PC)
Inst (PC+1)
Inst (0004h)
Inst (0005h)
Inst (0004h)
Instruction
executed
Inst (PC-1)
Dummy cycle
Dummy cycle
Inst (PC)
Note 1: T0IF interrupt flag is sampled here (every Q1).
2: Interrupt latency = 3TCY, where TCY = instruction cycle time.
3: CLKOUT is available only in ER and INTRC (with clockout) oscillator modes.
DS40300B-page 46
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple-counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4TOSC (and a small RC delay of 40 ns)
divided by the prescaler value. The only requirement on
T0CKI high and low time is that they do not violate the
minimum pulse width requirement of 10 ns. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device.
6.2
Using Timer0 with External Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
6.2.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-5). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small RC delay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
6.2.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the TMR0 is
actually incremented. Figure 6-5 shows the delay from
the external clock edge to the timer incrementing.
FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small pulse
misses sampling
External Clock Input or
(2)
Prescaler output
(1)
(3)
External Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in
measuring the interval between two edges on Timer0 input = ±4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 47
PIC16F62X
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
6.3
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 6-6). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available which is mutually exclusive between the
Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer, and
vice-versa.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1,
MOVWF 1, BSF 1, x....etc.) will clear the pres-
caler. When assigned to WDT, a CLRWDT instruction
will clear the prescaler along with the Watchdog Timer.
The prescaler is not readable or writable.
FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
8
CLKOUT (=Fosc/4)
M
U
X
1
0
0
1
M
U
X
T0CKI
pin
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
Set flag bit T0IF
on Overflow
PSA
0
1
8-bit Prescaler
M
U
X
Watchdog
Timer
8
8-to-1MUX
PS0 - PS2
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
Time-out
Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
DS40300B-page 48
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
6.3.1
SWITCHING PRESCALER ASSIGNMENT
To change prescaler from the WDT to the TMR0
module use the sequence shown in Example 6-2. This
precaution must be taken even if the WDT is disabled.
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution). To avoid an unintended device
EXAMPLE 6-2: CHANGING PRESCALER
RESET,
the
following
instruction
sequence
(WDT→TIMER0)
(Example 6-1) must be executed when changing the
prescaler assignment from Timer0 to WDT.
CLRWDT
;Clear WDT and
;prescaler
EXAMPLE 6-1: CHANGING PRESCALER
BSF
STATUS, RP0
(TIMER0→WDT)
STATUS, RP0 ;Skip if already in
MOVLW
b'xxxx0xxx' ;Select TMR0, new
;prescale value and
;clock source
1.BCF
; Bank 0
2.CLRWDT
3.CLRF
4.BSF
;Clear WDT
;Clear TMR0 & Prescaler
STATUS, RP0 ;Bank 1
MOVWF
BCF
OPTION_REG
STATUS, RP0
TMR0
5.MOVLW '00101111’b ;These 3 lines (5, 6, 7)
6.MOVWF OPTION
; are required only if
; desired PS<2:0> are
; 000 or 001
7.CLRWDT
8.MOVLW '00101xxx’b ;Set Postscaler to
9.MOVWF OPTION ; desired WDT rate
10.BCF STATUS, RP0 ;Return to Bank 0
TABLE 6-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
Value on
POR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Other
Resets
01h
TMR0
Timer0 module register
GIE T0IE
xxxx xxxx uuuu uuuu
0000 000x 0000 000u
1111 1111 1111 1111
0Bh/8Bh/
10Bh/18Bh
INTCON
—
INTE
T0SE
RBIE
PSA
T0IF
PS2
INTF
PS1
RBIF
PS0
81h
85h
OPTION RBPU INTEDG T0CS
TRISA TRISA7 TRISA6
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 11-1 1111 11-1 1111
—
Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown
Note: Shaded bits are not used by TMR0 module.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 49
PIC16F62X
In timer mode, Timer1 increments every instruction
cycle. In counter mode, it increments on every rising
edge of the external clock input.
7.0
TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L) which are
readable and writable. The TMR1 Register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 Interrupt, if enabled,
is generated on overflow which is latched in interrupt
flag bit TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit TMR1IE (PIE1<0>).
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Timer1 also has an internal “reset input”. This reset can
be generated by the CCP module (Section 10.0).
Register 7-1 shows the Timer1 control register.
For the PIC16F627 and PIC16F628, when the Timer1
oscillator is enabled (T1OSCEN is set), the RB7/T1OSI
and RB6/T1OSO/T1CKI pins become inputs. That is,
the TRISB<7:6> value is ignored.
Timer1 can operate in one of two modes:
• As a timer
• As a counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
REGISTER 7-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit0
bit7
- n = Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3:
bit 2:
T1OSCEN: Timer1 Oscillator Enable Control bit
1= Oscillator is enabled
0= Oscillator is shut off
Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1= Do not synchronize external clock input
0= Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1:
bit 0:
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RB6/T1OSO/T1CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
DS40300B-page 50
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
internal phase clock (Tosc) synchronization. Also, there
is a delay in the actual incrementing of TMR1 after syn-
chronization.
7.1
Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect since the internal clock is
always in sync.
When the prescaler is 1:1, the external clock input is
the same as the prescaler output. The synchronization
of T1CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T1CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the appropri-
ate electrical specifications, parameters 45, 46, and 47.
7.2
Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode the timer increments on every rising edge of
clock input on pin RB7/T1OSI when bit T1OSCEN is
set or pin RB6/T1OSO/T1CKI when bit T1OSCEN is
cleared.
When a prescaler other than 1:1 is used, the external
clock input is divided by the asynchronous rip-
ple-counter type prescaler so that the prescaler output
is symmetrical. In order for the external clock to meet
the sampling requirement, the ripple-counter must be
taken into account. Therefore, it is necessary for T1CKI
to have a period of at least 4Tosc (and a small RC delay
of 40 ns) divided by the prescaler value. The only
requirement on T1CKI high and low time is that they do
not violate the minimum pulse width requirements of
10 ns). Refer to the appropriate electrical specifica-
tions, parameters 40, 42, 45, 46, and 47.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The pres-
caler stage is an asynchronous ripple-counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut off. The pres-
caler however will continue to increment.
7.2.1
EXTERNAL CLOCK INPUT TIMING FOR
SYNCHRONIZED COUNTER MODE
When an external clock input is used for Timer1 in syn-
chronized counter mode, it must meet certain require-
ments. The external clock requirement is due to
FIGURE 7-1: TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow
Synchronized
0
TMR1
clock input
TMR1L
TMR1H
T1OSC
1
TMR1ON
on/off
T1SYNC
RB6/T1OSO/T1CKI
RB7/T1OSI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
FOSC/4
Internal
Clock
0
(1)
2
SLEEP input
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 51
PIC16F62X
FIGURE 7-2: TIMER1 INCREMENTING EDGE
T1CKI
(Default high)
T1CKI
(Default low)
Note: Arrows indicate counter increments.
7.3
Timer1 Operation in Asynchronous
Counter Mode
EXAMPLE 7-1: READING A 16-BIT
FREE-RUNNING TIMER
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow which will wake-up
the processor. However, special precautions in soft-
ware are needed to read/write the timer (Section 7.3.2).
; All interrupts are disabled
MOVF
MOVWF TMPH
MOVF TMR1L, W ;Read low byte
MOVWF TMPL
MOVF TMR1H, W ;Read high byte
SUBWF TMPH,
TMR1H, W ;Read high byte
;
;
W
;Sub 1st read
; with 2nd read
BTFSC STATUS,Z ;Is result = 0
GOTO CONTINUE ;Good 16-bit read
In asynchronous counter mode, Timer1 can not be
used as a time-base for capture or compare operations.
;
7.3.1
EXTERNAL CLOCK INPUT TIMING WITH
UNSYNCHRONIZED CLOCK
; TMR1L may have rolled over between the read
; of the high and low bytes. Reading the high
; and low bytes now will read a good value.
;
If control bit T1SYNC is set, the timer will increment
completely asynchronously. The input clock must meet
certain minimum high time and low time requirements.
Refer to the appropriate Electrical Specifications Sec-
tion, timing parameters 45, 46, and 47.
MOVF
MOVWF TMPH
MOVF TMR1L, W ;Read low byte
MOVWF TMPL
; Re-enable the Interrupt (if required)
CONTINUE ;Continue with your code
TMR1H, W ;Read high byte
;
;
7.3.2
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
7.4
Timer1 Oscillator
Reading TMR1H or TMR1L while the timer is running,
from an external asynchronous clock, will guarantee a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself poses certain problems since
the timer may overflow between the reads.
A crystal oscillator circuit is built in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 7-1 shows the capacitor
selection for the Timer1 oscillator.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers while the
register is incrementing. This may produce an unpre-
dictable value in the timer register.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
Reading the 16-bit value requires some care.
Example 7-1 is an example routine to read the 16-bit
timer value. This is useful if the timer cannot be
stopped.
TABLE 7-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
Osc Type
Freq
C1
C2
LP
32 kHz
100 kHz
200 kHz
33 pF
15 pF
15 pF
33 pF
15 pF
15 pF
These values are for design guidance only.
DS40300B-page 52
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
7.5
Resetting Timer1 using a CCP Trigger
Output
7.6
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
If the CCP1 module is configured in compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1.
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other reset except by the CCP1 special
event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other resets, the register is
unaffected.
Note: The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Timer1 must be configured for either timer or synchro-
nized counter mode to take advantage of this feature. If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
7.7
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1, the write will take prece-
dence.
In this mode of operation, the CCPRxH:CCPRxL regis-
ters pair effectively becomes the period register for
Timer1.
TABLE 7-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
Value on
POR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
resets
0000 000x 0000 000u
0Bh/8Bh/
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
10Bh/18Bh
0000 -000 0000 -000
0000 -000 0000 -000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --uu uuuu
0Ch
8Ch
0Eh
0Fh
10h
PIR1
EEIF
CMIF
RCIF
TXIF
—
—
CCP1IF TMR2IF
TMR1IF
PIE1
EEIE
CMIE
RCIE
TXIE
CCP1IE TMR2IE TMR1IE
TMR1L
TMR1H
T1CON
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 53
PIC16F62X
8.1
Timer2 Prescaler and Postscaler
8.0
TIMER2 MODULE
The prescaler and postscaler counters are cleared
when any of the following occurs:
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
PWM mode of the CCP module. The TMR2 register is
readable and writable, and is cleared on any device
reset.
• a write to the TMR2 register
• a write to the T2CON register
• any device reset (Power-on Reset, MCLR reset,
Watchdog Timer reset, or Brown-out Reset)
The input clock (FOSC/4) has a prescale option of 1:1,
1:4
or
1:16,
selected
by
control
bits
TMR2 is not cleared when T2CON is written.
T2CKPS1:T2CKPS0 (T2CON<1:0>).
8.2
Output of TMR2
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is ini-
tialized to FFh upon reset.
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate shift clock.
FIGURE 8-1: TIMER2 BLOCK DIAGRAM
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
Sets flag
TMR2
output (1)
bit TMR2IF
Reset
Prescaler
1:1, 1:4, 1:16
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
TMR2 reg
FOSC/4
Postscaler
1:1 to 1:16
2
Comparator
Register 8-1 shows the Timer2 control register.
EQ
4
PR2 reg
Note 1: TMR2 register output can be software selected
by the SSP Module as a baud clock.
DS40300B-page 54
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
REGISTER 8-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit0
R
= Readable bit
W = Writable bit
U
bit7
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
Unimplemented: Read as '0'
bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2:
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
TABLE 8-1:
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on
all other
resets
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR
0000 000x 0000 000u
0Bh/8Bh/
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
10Bh/18Bh
0000 -000 0000 -000
0000 -000 0000 -000
0000 0000 0000 0000
-000 0000 -000 0000
1111 1111 1111 1111
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
—
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
11h
TMR2
T2CON
PR2
Timer2 module’s register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
12h
—
92h
Legend:
x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 55
PIC16F62X
NOTES:
DS40300B-page 56
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
The CMCON register, shown in Register 9-1, controls
the comparator input and output multiplexers. A block
diagram of the comparator is shown in Figure 9-1.
9.0
COMPARATOR MODULE
The comparator module contains two analog
comparators. The inputs to the comparators are
multiplexed with the RA0 through RA3 pins. The
on-chip Voltage Reference (Section 11.0) can also be
an input to the comparators.
REGISTER 9-1: CMCON REGISTER (ADDRESS 01Fh)
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
CM2
R/W-0
CM1
R/W-0
CM0
bit0
C2OUT C1OUT C2INV C1INV CIS
R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ’0’
bit7
-n = Value at POR reset
bit 7:
C2OUT: Comparator 2 output
When C2INV=0;
1= C2 VIN+ > C2 VIN–
0= C2 VIN+ < C2 VIN–
When C2INV=1;
0= C2 VIN+ > C2 VIN–
1= C2 VIN+ < C2 VIN–
bit 6:
C1OUT: Comparator 1 output
When C1INV=0;
1= C1 VIN+ > C1 VIN–
0= C1 VIN+ < C1 VIN–
When C1INV=1;
0= C1 VIN+ > C1 VIN–
1= C1 VIN+ < C1 VIN–
bit 5:
bit 4:
bit 3:
C2INV: Comparator 2 output inversion
1= C2 Output inverted
0= C2 Output not inverted
C1INV: Comparator 1 output inversion
1= C1 Output inverted
0= C1 Output not inverted
CIS: Comparator Input Switch
When CM2:CM0: = 001:
Then:
1= C1 VIN– connects to RA3
0= C1 VIN– connects to RA0
When CM2:CM0 = 010:
Then:
1= C1 VIN– connects to RA3
C2 VIN– connects to RA2
0= C1 VIN– connects to RA0
C2 VIN– connects to RA1
bit 2-0: CM2:CM0: Comparator mode
Figure 9-1 shows the comparator modes and CM2:CM0 bit settings.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 57
PIC16F62X
mode is changed, the comparator output level may not
be valid for the specified mode change delay shown
in Table 12-2.
9.1
Comparator Configuration
There are eight modes of operation for the
comparators. The CMCON register is used to select
the mode. Figure 9-1 shows the eight possible modes.
The TRISA register controls the data direction of the
comparator pins for each mode. If the comparator
Note: Comparator interrupts should be disabled
during a comparator mode change other-
wise a false interrupt may occur.
FIGURE 9-1: COMPARATOR I/O OPERATING MODES
Comparators Reset (POR Default Value)
CM2:CM0 = 000
Comparators Off
CM2:CM0 = 111
D
D
Vin-
A
A
Vin-
RA0/AN0
RA0/AN0
Off (Read as ’0’)
Off (Read as ’0’)
C1
C2
Off (Read as ’0’)
Off (Read as ’0’)
C1
C2
Vin+
Vin+
RA3/AN3/C10
RA3/AN3/C10
A
A
Vin-
D
D
Vin-
RA1/AN1
RA2/AN2
RA1/AN1
RA2/AN2
Vin+
Vin+
Four Inputs Multiplexed to Two Comparators
CM2:CM0 = 010
Two Independent Comparators
CM2:CM0 = 100
A
RA0/AN0
A
A
Vin-
CIS = 0
CIS = 1
Vin-
RA0/AN0
A
RA3/AN3/C10
C1OUT
C2OUT
C1
Vin+
C1OUT
C1
C2
Vin+
RA3/AN3/C10
A
A
RA1/AN1
RA2/AN2
Vin-
CIS = 0
CIS = 1
A
A
Vin-
RA1/AN1
RA2/AN2
C2OUT
Vin+
C2
Vin+
From Vref Module
Two Common Reference Comparators
CM2:CM0 = 011
Two Common Reference Comparators with Outputs
CM2:CM0 = 110
A
Vin-
RA0/AN0
A
D
Vin-
RA0/AN0
C1OUT
C1
Vin+
D
C1OUT
C2OUT
C1
C2
RA3/AN3/C10
Vin+
RA3/AN3/C10
A
A
Vin-
RA1/AN1
RA2/AN2
A
A
Vin-
RA1/AN1
RA2/AN2
C2OUT
C2
Vin+
Vin+
Open Drain
RA4/T0CKI/C20
One Independent Comparator
CM2:CM0 = 101
Three Inputs Multiplexed to Two Comparators
CM2:CM0 = 001
D
D
Vin-
RA0/AN0
A
RA0/AN0
CIS = 0
CIS = 1
Vin-
Off (Read as ’0’)
C2OUT
C1
Vin+
RA3/AN3/C10
A
RA3/AN3/C10
C1OUT
C2OUT
C1
C2
Vin+
A
A
Vin-
RA1/AN1
RA2/AN2
A
A
Vin-
RA1/AN1
RA2/AN2
C2
Vin+
Vin+
A = Analog Input, port reads zeros always.
D = Digital Input.
CIS (CMCON<3>) is the Comparator Input Switch.
DS40300B-page 58
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
The code example in Example 9-1 depicts the steps
required to configure the comparator module. RA3 and
RA4 are configured as digital output. RA0 and RA1 are
configured as the V- inputs and RA2 as the V+ input to
both comparators.
9.3
Comparator Reference
An external or internal reference signal may be used
depending on the comparator operating mode. The
analog signal that is present at VIN– is compared to the
signal at VIN+, and the digital output of the comparator
is adjusted accordingly (Figure 9-2).
EXAMPLE 9-1: INITIALIZING
COMPARATOR MODULE
FIGURE 9-2: SINGLE COMPARATOR
FLAG_REG EQU
0X20
CLRF
CLRF
FLAG_REG
PORTA
;Init flag register
;Init PORTA
MOVF
CMCON, W
0xC0
;Load comparator bits
;Mask comparator bits
VIN+
+
–
ANDLW
IORWF
MOVLW
MOVWF
BSF
Output
FLAG_REG,F ;Store bits in flag register
0x03
CMCON
VIN–
;Init comparator mode
;CM<2:0> = 011
STATUS,RP0 ;Select Bank1
MOVLW
MOVWF
0x07
TRISA
;Initialize data direction
;Set RA<2:0> as inputs
;RA<4:3> as outputs
V
IN–
IN+
;TRISA<7:5> always read ‘0’
STATUS,RP0 ;Select Bank 0
BCF
CALL
MOVF
BCF
BSF
BSF
BCF
BSF
BSF
DELAY 10
CMCON,F
PIR1,CMIF
;10µs delay
;Read CMCONtoendchangecondition
;Clear pending interrupts
V
STATUS,RP0 ;Select Bank 1
PIE1,CMIE
;Enable comparator interrupts
STATUS,RP0 ;Select Bank 0
INTCON,PEIE ;Enable peripheral interrupts
INTCON,GIE ;Global interrupt enable
Output
9.2
Comparator Operation
9.3.1
EXTERNAL REFERENCE SIGNAL
A single comparator is shown in Figure 9-2 along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN–, the output of the
comparator is a digital low level. When the analog input
at VIN+ is greater than the analog input VIN–, the output
of the comparator is a digital high level. The shaded
areas of the output of the comparator in Figure 9-2
represent the uncertainty due to input offsets and
response time.
When external voltage references are used, the
comparator module can be configured to have the com-
parators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD, and can be applied to either
pin of the comparator(s).
9.3.2
INTERNAL REFERENCE SIGNAL
The comparator module also allows the selection of an
internally generated voltage reference for the
comparators. Section 13, Instruction Sets, contains a
detailed description of the Voltage Reference Module
that provides this signal. The internal reference signal
is used when the comparators are in mode
CM<2:0>=010 (Figure 9-1). In this mode, the internal
voltage reference is applied to the VIN+ pin of both
comparators.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 59
PIC16F62X
9.4
Comparator Response Time
9.5
Comparator Outputs
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is guaranteed to have a valid level.
If the internal reference is changed, the maximum delay
of the internal voltage reference must be considered
when using the comparator outputs. Otherwise the
maximum delay of the comparators should be used
(Table 12-2 ).
The comparator outputs are read through the CMCON
register. These bits are read only. The comparator
outputs may also be directly output to the RA3 and RA4
I/O pins. When the CM<2:0> = 110 or 001, multiplexors
in the output path of the RA3 and RA4/T0CK1 pins will
switch and the output of each pin will be the unsynchro-
nized output of the comparator. The uncertainty of each
of the comparators is related to the input offset voltage
and the response time given in the specifications.
Figure 9-3 shows the comparator output block diagram.
The TRISA bits will still function as an output
enable/disable for the RA3 and RA4/T0CK1 pins while
in this mode.
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as
a ‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog levels on any pin that is defined
as a digital input may cause the input
buffer to consume more current than is
specified.
FIGURE 9-3: MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX
CnINV
To RA3 or RA4/T0CK1 pin
To Data Bus
Q
D
Q1
EN
RD CMCON
Set CMIF bit
Q
D
Q3 * RD CMCON
EN
CL
From other Comparator
NRESET
DS40300B-page 60
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
wake up the device from SLEEP mode when enabled.
While the comparator is powered-up, higher sleep
currents than shown in the power down current
specification will occur. Each comparator that is
operational will consume additional current as shown in
the comparator specifications. To minimize power
consumption while in SLEEP mode, turn off the
comparators, CM<2:0> = 111, before entering sleep. If
the device wakes-up from sleep, the contents of the
CMCON register are not affected.
9.6
Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that has occurred. The
CMIF bit, PIR1<6>, is the comparator interrupt flag.
The CMIF bit must be reset by clearing ‘0’. Since it is
also possible to write a '1' to this register, a simulated
interrupt may be initiated.
9.8
Effects of a RESET
The CMIE bit (PIE1<6>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are clear, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
A device reset forces the CMCON register to its reset
state. This forces the comparator module to be in the
comparator reset mode, CM2:CM0 = 000. This
ensures that all potential inputs are analog inputs.
Device current is minimized when analog inputs are
present at reset time. The comparators will be
powered-down during the reset interval.
Note: If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR1<6>)
interrupt flag may not get set.
9.9
Analog Input Connection
Considerations
The user, in the interrupt service routine, can clear the
interrupt in the following manner:
A simplified circuit for an analog input is shown in
Figure 9-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
a) Any read or write of CMCON. This will end the
mismatch condition.
b) Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition, and
allow flag bit CMIF to be cleared.
maximum
source
impedance
of
10 kΩ
is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
9.7
Comparator Operation During SLEEP
When a comparator is active and the device is placed
in SLEEP mode, the comparator remains active and
the interrupt is functional if enabled. This interrupt will
FIGURE 9-4: ANALOG INPUT MODEL
VDD
VT = 0.6V
RIC
RS < 10K
AIN
ILEAKAGE
±500 nA
CPIN
5 pF
VA
VT = 0.6V
VSS
Legend
CPIN
VT
= Input Capacitance
= Threshold Voltage
ILEAKAGE
RIC
= Leakage Current At The Pin Due To Various Junctions
= Interconnect Resistance
RS
= Source Impedance
VA
= Analog Voltage
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 61
PIC16F62X
TABLE 9-1:
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Value on
All Other
Resets
Value on
POR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1Fh
9Fh
CMCON C2OUT C1OUT C2INV
C1NV
CIS
CM2
CM1
CM0
0000 0000 0000 0000
000- 0000 000- 0000
VRCON
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
0Bh/8Bh/
10Bh/18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
8Ch
85h
PIR1
PIE1
EEIF
EEIE
CMIF
CMIE
RCIF
RCIE
—
TXIF
TXIE
—
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
TRISA
TRISA7 TRISA6
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 11-1 1111 11-1 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as "0"
DS40300B-page 62
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
Additional information on the CCP module is available
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
10.0 CAPTURE/COMPARE/PWM
(CCP) MODULE
The CCP (Capture/Compare/PWM) module contains a
16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register or as a PWM
master/slave Duty Cycle register. Table 10-1 shows the
timer resources of the CCP module modes.
TABLE 10-1
CCP MODE - TIMER
RESOURCE
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
REGISTER 10-1: CCP1CON REGISTER (ADDRESS 17h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ’0’
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1 CCP1M0
bit0
bit7
-n = Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5-4: CCP1X:CCP1Y: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0: CCP1M3:CCP1M0: CCPx Mode Select bits
0000= Capture/Compare/PWM off (resets CCP1 module)
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, set output on match (CCP1IF bit is set)
1001= Compare mode, clear output on match (CCP1IF bit is set)
1010= Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected)
1011= Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1
11xx= PWM mode
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 63
PIC16F62X
10.1.4 CCP PRESCALER
10.1
Capture Mode
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in capture mode,
the prescaler counter is cleared. This means that any
reset will clear the prescaler counter.
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RB3/CCP1. An event is defined as:
• every falling edge
• every rising edge
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 10-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
• every 4th rising edge
• every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
EXAMPLE 10-1: CHANGING BETWEEN
CAPTURE PRESCALERS
10.1.1 CCP PIN CONFIGURATION
CLRF
CCP1CON
;Turn CCP module off
MOVLW NEW_CAPT_PS ;Load the W reg with
; the new prescaler
In Capture mode, the RB3/CCP1 pin should be config-
ured as an input by setting the TRISB<3> bit.
; mode value and CCP ON
MOVWF CCP1CON
;Load CCP1CON with this
; value
Note: If the RB3/CCP1 is configured as an out-
put, a write to the port can cause a capture
condition.
FIGURE 10-1: CAPTURE MODE OPERATION
BLOCK DIAGRAM
Set flag bit CCP1IF
(PIR1<2>)
Prescaler
³ 1, 4, 16
RB3/CCP1
Pin
CCPR1H
CCPR1L
TMR1L
Capture
Enable
and
edge detect
TMR1H
CCP1CON<3:0>
Q’s
10.1.2 TIMER1 MODE SELECTION
Timer1 must be running in timer mode or synchronized
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode, the capture
operation may not work.
10.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
DS40300B-page 64
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
10.2.1 CCP PIN CONFIGURATION
10.2
Compare Mode
The user must configure the RB3/CCP1 pin as an out-
put by clearing the TRISB<3> bit.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RB3/CCP1 pin is:
Note: Clearing the CCP1CON register will force
the RB3/CCP1 compare output latch to the
default low level. This is not the data latch.
• driven High
• driven Low
• remains Unchanged
10.2.2 TIMER1 MODE SELECTION
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
FIGURE 10-2: COMPARE MODE
OPERATION BLOCK
DIAGRAM
10.2.3 SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
Special event trigger will reset Timer1, but not
set interrupt flag bit TMR1IF (PIR1<0>)
10.2.4 SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
Special Event Trigger (CCP2 only)
Set flag bit CCP1IF
(PIR1<2>)
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
CCPR1H CCPR1L
Q
S
R
Output
Logic
Comparator
match
RB3/CCP1
Pin
TRISB<3>
Output Enable
TMR1H TMR1L
CCP1CON<3:0>
Mode Select
TABLE 10-2
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Value on
all other
resets
Value on
POR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh/8Bh/1
0Bh/18Bh
0000 000x 0000 000u
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0Ch
8Ch
87h
0Eh
0Fh
10h
15h
16h
17h
0000 -000 0000 -000
0000 -000 0000 -000
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --uu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
PIR1
PIE1
EEIF CMIF
RCIF
TXIF
—
—
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
EEIE CMIF
RCIE
TXIE
PORTB Data Direction Register
TRISB
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1register
TMR1L
TMR1H
T1CON
CCPR1L
CCPR1H
CCP1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Capture/Compare/PWM register1 (LSB)
Capture/Compare/PWM register1 (MSB)
—
—
CCP1X
CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 65
PIC16F62X
10.3.1 PWM PERIOD
10.3
PWM Mode
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISB<3> bit must be cleared to make the CCP1
pin an output.
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTB I/O data
latch.
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
Figure 10-3 shows a simplified block diagram of the
CCP module in PWM mode.
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 10.3.3.
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
FIGURE 10-3: SIMPLIFIED PWM BLOCK
DIAGRAM
Note: The Timer2 postscaler (see Section 8.0) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different fre-
quency than the PWM output.
CCP1CON<5:4>
Duty cycle registers
CCPR1L
10.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available: the CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
CCPR1H (Slave)
Q
R
S
Comparator
RB3/CCP1
(Note 1)
TMR2
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
TRISB<3>
Comparator
PR2
Tosc • (TMR2 prescale value)
Clear Timer,
CCP1 pin and
latch D.C.
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
A PWM output (Figure 10-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
FIGURE 10-4: PWM OUTPUT
Maximum PWM resolution (bits) for a given PWM
frequency:
Period
Fosc
Fpwm
log
(
)
=
bits
Duty Cycle
log (2)
TMR2 = PR2
Note: If the PWM duty cycle value is longer than
the PWM period the CCP1 pin will not be
cleared.
TMR2 = Duty Cycle
TMR2 = PR2
For an example PWM period and duty cycle calcula-
tion, see the PICmicro™ Mid-Range Reference Manual
(DS33023).
DS40300B-page 66
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
10.3.3 SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 regis-
ter.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISB<3> bit.
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
TABLE 10-3
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
4
1
1
1
1
0xFF
10
0xFF
10
0xFF
10
0x3F
8
0x1F
7
0x17
5.5
Maximum Resolution (bits)
TABLE 10-4
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
all other
resets
Value on
POR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 000x 0000 000u
0Bh/8Bh/
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
10Bh/18Bh
0000 -000 0000 -000
0000 -000 0000 -000
1111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
-000 0000 uuuu uuuu
0Ch
8Ch
87h
11h
92h
12h
PIR1
PIE1
EEIF
CMIF
RCIF
TXIF
—
—
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
EEIE
CMIE
RCIE
TXIE
PORTB Data Direction Register
Timer2 module’s register
TRISB
TMR2
PR2
Timer2 module’s period register
TOUTPS TOUTPS TOUTPS TOUTPS TMR2ON T2CKPS T2CKPS
T2CON
—
3
2
1
0
1
0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
Capture/Compare/PWM register1 (LSB)
Capture/Compare/PWM register1 (MSB)
15h
16h
17h
CCPR1L
CCPR1H
CCP1CON
—
—
CCP1X
CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 67
PIC16F62X
NOTES:
DS40300B-page 68
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
11.1
Configuring the Voltage Reference
11.0 VOLTAGE REFERENCE
MODULE
The Voltage Reference can output 16 distinct voltage
levels for each range.
The Voltage Reference is a 16-tap resistor ladder
network that provides a selectable voltage reference.
The resistor ladder is segmented to provide two ranges
of VREF values and has a power-down function to
conserve power when the reference is not being used.
The VRCON register controls the operation of the
reference as shown in Figure 11-1. The block diagram
is given in Figure 11-2.
The equations used to calculate the output of the
Voltage Reference are as follows:
if VRR = 1: VREF = (VR<3:0>/24) x VDD
if VRR = 0: VREF = (VDD x 1/4) + (VR<3:0>/32) x VDD
The setting time of the Voltage Reference must be
considered when changing the VREF output
(Table 12-2). Example 11-1 shows an example of how
to configure the Voltage Reference for an output volt-
age of 1.25V with VDD = 5.0V.
FIGURE 11-1: VRCON REGISTER(ADDRESS 9Fh)
R/W-0
R/W-0
R/W-0
VRR
U-0
R/W-0
R/W-0
R/W-0
R/W-0
VREN
VROE
—
VR3
VR2
VR1
VR0
R = Readable bit
W = Writable bit
bit7
bit0
U = Unimplemented bit, read
as ’0’
-n = Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
VREN: VREF Enable
1= VREF circuit powered on
0= VREF circuit powered down, no IDD drain
VROE: VREF Output Enable
1= VREF is output on RA2 pin
0= VREF is disconnected from RA2 pin
VRR: VREF Range selection
1= Low Range
0= High Range
Unimplemented: Read as '0'
bit 3-0: VR<3:0>: VREF value selection 0 ≤ VR [3:0] ≤ 15
when VRR = 1: VREF = (VR<3:0>/ 24) * VDD
when VRR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD
FIGURE 11-2: VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
VREN
R
R
R
8R
R
8R
VRR
VR3
VR0
VREF
(From VRCON<3:0>)
16-1 Analog Mux
Note: R is defined in Table 12-3.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 69
PIC16F62X
EXAMPLE 11-1: VOLTAGE REFERENCE
CONFIGURATION
11.4
Effects of a Reset
A device reset disables the Voltage Reference by clear-
ing bit VREN (VRCON<7>). This reset also disconnects
the reference from the RA2 pin by clearing bit VROE
(VRCON<6>) and selects the high voltage range by
clearing bit VRR (VRCON<5>). The VREF value select
bits, VRCON<3:0>, are also cleared.
MOVLW
MOVWF
BSF
0x02
; 4 Inputs Muxed
; to 2 comps.
; go to Bank 1
; RA3-RA0 are
; outputs
CMCON
STATUS,RP0
0x07
MOVLW
MOVWF
MOVLW
MOVWF
TRISA
0xA6
; enable VREF
; low range
11.5
Connection Considerations
Voltage Reference Module
VRCON
; set VR<3:0>=6
; go to Bank 0
; 10µs delay
The
operates
independently of the comparator module. The output of
the reference generator may be connected to the RA2
pin if the TRISA<2> bit is set and the VROE bit,
VRCON<6>, is set. Enabling the Voltage Reference
output onto the RA2 pin with an input signal present will
increase current consumption. Connecting RA2 as a
digital output with VREF enabled will also increase
current consumption.
BCF
STATUS,RP0
DELAY10
CALL
11.2
Voltage Reference Accuracy/Error
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 11-2) keep VREF from approaching VSS or VDD.
The Voltage Reference is VDD derived and therefore,
the VREF output changes with fluctuations in VDD. The
tested absolute accuracy of the Voltage Reference can
be found in Table 17-2.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
Voltage Reference output for external connections to
VREF. Figure 11-3 shows an example buffering
technique.
11.3
Operation During Sleep
When the device wakes up from sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the VRCON register are not affected. To minimize
current consumption in SLEEP mode, the Voltage
Reference should be disabled.
FIGURE 11-3: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
(1)
RA2
R
VREF
Module
+
–
•
VREF Output
•
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.
TABLE 11-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Value On
Value On
All Other
Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR
9Fh
1Fh
85h
VRCON
VREN
VROE
VRR
—
VR3
CIS
VR2
CM2
VR1
CM1
VR0
CM0
000- 0000 000- 0000
0000 0000 0000 0000
CMCON C2OUT C1OUT C2INV
TRISA TRISA7 TRISA6
C1INV
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 11-1 1111 11-1 1111
—
Note: -= Unimplemented, read as "0"
DS40300B-page 70
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
as a half duplex synchronous system that can commu-
nicate with peripheral devices such as A/D or D/A inte-
grated circuits, Serial EEPROMs etc.
12.0 UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The USART can be configured in the following modes:
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Com-
munications Interface or SCI). The USART can be con-
figured as a full duplex asynchronous system that can
communicate with peripheral devices such as CRT ter-
minals and personal computers, or it can be configured
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
Bit SPEN (RCSTA<7>), and bits TRISB<2:1>, have
to be set in order to configure pins RB2/TX/CK and
RB1/RX/DT as the Universal Synchronous Asyn-
chronous Receiver Transmitter.
REGISTER 12-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
—
R/W-0
BRGH
R-1
R/W-0
TX9D
TRMT
R = Readable bit
W = Writable bit
bit7
bit0
U = Unimplemented bit,
read as ’0’
-n = Value at POR reset
bit 7:
CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1= Master mode (Clock generated internally from BRG)
0= Slave mode (Clock from external source)
bit 6:
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
bit 5:
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4:
SYNC: USART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
bit 3:
bit 2:
Unimplemented: Read as '0'
BRGH: High Baud Rate Select bit
Asynchronous mode
1= High speed
0= Low speed
Synchronous mode
Unused in this mode
bit 1:
bit 0:
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of transmit data. Can be parity bit.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 71
PIC16F62X
REGISTER 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
ADEN
R-0
R-0
R-x
FERR
OERR
RX9D
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ’0’
bit7
bit0
-n = Value at POR reset
x = unknown
bit 7:
SPEN: Serial Port Enable bit
(Configures RB1/RX/DT and RB2/TX/CK pins as serial port pins when bits TRISB<2:17> are set)
1= Serial port enabled
0= Serial port disabled
bit 6:
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
bit 5:
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave:
Unused in this mode
bit 4:
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables continuous receive
0= Disables continuous receive
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3:
ADEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection, enable interrupt and load of the receive buffer when RSR<8> is set
0= Disables address detection, all bytes are received, and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9=0):
Unused in this mode
Synchronous mode
Unused in this mode
bit 2:
bit 1:
bit 0:
FERR: Framing Error bit
1= Framing error (Can be updated by reading RCREG register and receive next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (Can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of received data (Can be parity bit)
DS40300B-page 72
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
12.1
USART Baud Rate Generator (BRG)
EXAMPLE 12-1: CALCULATING BAUD RATE
ERROR
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In asynchronous
mode bit BRGH (TXSTA<2>) also controls the baud
rate. In synchronous mode bit BRGH is ignored.
Table 12-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in master mode (internal clock).
Desired Baud rate = Fosc / (64 (X + 1))
9600 =
16000000 /(64 (X + 1))
X
=
Î25.042° = 25
Calculated Baud Rate=16000000 / (64 (25 + 1))
=
=
9615
Error
(Calculated Baud Rate - Desired Baud Rate)
Desired Baud Rate
Given the desired baud rate and Fosc, the nearest inte-
ger value for the SPBRG register can be calculated
using the formula in Table 12-1. From this, the error in
baud rate can be determined.
=
=
(9615 - 9600) / 9600
0.16%
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
Example 12-1 shows the calculation of the baud rate
error for the following conditions:
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
Writing a new value to the SPBRG register, causes the
BRG timer to be reset (or cleared), this ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
SYNC = 0
TABLE 12-1: BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
Baud Rate= FOSC/(16(X+1))
NA
X = value in SPBRG (0 to 255)
TABLE 12-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on Value on all
POR other resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 -010 0000 -010
98h
TXSTA
CSRC TX9 TXEN SYNC
—
BRGH TRMT TX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
18h
99h
RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D
SPBRG Baud Rate Generator Register
Legend: x = unknown, -= unimplemented read as '0'. Shaded cells are not used by the BRG.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 73
PIC16F62X
TABLE 12-3: BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 20 MHz
16 MHz
KBAUD
10 MHz
KBAUD
7.15909 MHz
KBAUD
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
ERROR (decimal)
SPBRG
value
ERROR (decimal)
SPBRG
value
ERROR (decimal)
%
%
%
%
KBAUD
ERROR (decimal)
0.3
1.2
2.4
NA
NA
NA
-
-
-
-
-
-
NA
NA
NA
-
-
-
-
-
-
NA
NA
NA
-
-
-
-
-
-
NA
NA
NA
-
-
-
-
-
-
9.6
NA
-
+1.73
+0.16
+0.16
-1.96
0
-
NA
-
+0.16
+0.16
-0.79
+2.56
0
-
9.766
19.23
75.76
96.15
312.5
500
+1.73
+0.16
-1.36
+0.16
+4.17
0
255
129
32
25
7
4
0
255
9.622
19.24
77.82
94.20
298.3
NA
+0.23
+0.23
+1.32
-1.88
-0.57
-
185
92
22
18
5
-
0
255
19.2
76.8
96
300
500
HIGH
LOW
19.53
76.92
96.15
294.1
500
255
64
51
16
9
19.23
76.92
95.24
307.69
500
207
51
41
12
7
5000
19.53
-
-
0
255
4000
15.625
-
-
0
255
2500
9.766
-
-
1789.8
6.991
-
-
FOSC = 5.0688 MHz
SPBRG
4 MHz
3.579545 MHz
1 MHz
32.768 kHz
BAUD
SPBRG
value
ERROR (decimal)
SPBRG
value KBAUD
ERROR (decimal)
SPBRG
value KBAUD
ERROR (decimal)
SPBRG
value
RATE KBAUD
(K)
%
value KBAUD
%
KBAUD
%
%
%
ERROR (decimal)
ERROR (decimal)
0.3
1.2
2.4
NA
NA
NA
-
-
-
0
-
-
-
NA
NA
NA
-
-
-
-
-
-
NA
NA
NA
9.622
19.04
74.57
99.43
298.3
NA
-
-
-
-
-
-
92
46
11
8
2
-
0
255
NA
1.202
2.404
9.615
19.24
83.34
NA
NA
NA
250
0.9766
-
-
207
103
25
12
2
-
-
-
0
0.303
1.170
NA
NA
NA
NA
NA
NA
NA
+1.14
-2.48
26
6
-
-
-
-
-
-
-
+0.16
+0.16
+0.16
+0.16
-
-
-
-
-
-
-
-
-
9.6
9.6
131
65
15
12
3
-
0
255
9.615
19.231 +0.16
76.923 +0.16
1000
NA
NA
+0.16
103
51
12
9
-
-
+0.23
-0.83
-2.90
+3.57
-0.57
-
19.2
76.8
96
300
500
HIGH
LOW
19.2
79.2
97.48
316.8
NA
0
+3.13
+1.54
+5.60
-
-
-
+8.51
+4.17
-
-
-
-
-
-
-
-
-
1267
4.950
100
3.906
0
255
894.9
3.496
-
-
8.192
0.032
0
255
255
TABLE 12-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz
%
16 MHz
10 MHz
7.15909 MHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
SPBRG
value
SPBRG
value
%
%
%
KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal)
0.3
1.2
2.4
NA
-
-
255
129
32
15
3
2
0
-
0
NA
1.202
2.404
9.615
19.23
83.33
NA
NA
NA
250
0.977
-
-
207
103
25
12
2
-
-
-
0
NA
1.202
2.404
9.766
19.53
78.13
NA
NA
NA
156.3
0.6104
-
-
129
64
15
7
1
-
-
-
NA
1.203
2.380
9.322
18.64
NA
NA
NA
NA
111.9
0.437
-
-
92
46
11
5
-
-
-
-
1.221
2.404
9.469
19.53
78.13
104.2
312.5
NA
+1.73
+0.16
-1.36
+1.73
+1.73
+8.51
+4.17
-
+0.16
+0.16
+0.16
+0.16
+0.16
+0.16
+1.73
+1.73
+0.23
-0.83
-2.90
-2.90
-
-
-
-
-
-
9.6
19.2
76.8
96
300
500
HIGH
LOW
+8.51
+1.73
-
-
-
-
-
-
-
-
-
-
312.5
1.221
-
-
0
255
0
255
255
255
FOSC = 5.0688 MHz
4 MHz
3.579545 MHz
%
1 MHz
32.768 kHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
SPBRG
value
SPBRG
value
SPBRG
value
%
%
%
%
KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal)
0.3
1.2
2.4
0.31
1.2
2.4
+3.13
0
0
+3.13
+3.13
+3.13
-
-
-
-
-
255
65
32
7
3
0
-
-
-
0
0.3005 -0.17
207
51
25
-
-
-
-
-
-
0.301
1.190
2.432
9.322
18.64
NA
NA
NA
NA
55.93
0.2185
+0.23
-0.83
+1.32
-2.90
185
46
22
5
2
-
-
-
-
0
0.300
1.202
2.232
NA
NA
NA
NA
NA
NA
15.63
0.0610
+0.16
+0.16
-6.99
51
12
6
-
-
-
-
-
-
0.256 -14.67
1
-
-
-
-
-
-
-
-
1.202
2.404
NA
+1.67
+1.67
NA
NA
-
-
-
-
-
-
-
-
-
-
9.6
9.9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
NA
19.2
76.8
96
300
500
HIGH
LOW
19.8
79.2
NA
NA
NA
NA
NA
-2.90
NA
-
-
-
-
-
-
NA
NA
NA
NA
NA
NA
NA
79.2
0.3094
62.500
3.906
0
255
0
255
0.512
0.0020
0
255
255
255
DS40300B-page 74
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 20 MHz
%
16 MHz
10 MHz
7.16 MHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
SPBRG
value
SPBRG
value
%
%
%
KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal)
9.6
9.615
19.230
37.878
56.818
+0.16
+0.16
-1.36
-1.36
-1.36
0
129
64
32
21
10
4
9.615
19.230
38.461
58.823
111.111
250
+0.16
+0.16
+0.16
+2.12
-3.55
0
103
51
25
16
8
9.615
18.939
39.062
56.818
125
+0.16
-1.36
+1.7
-1.36
+8.51
-
64
32
15
10
4
9.520
19.454
37.286
55.930
111.860
NA
-0.83
+1.32
-2.90
-2.90
-2.90
-
46
22
11
7
3
-
19.2
38.4
57.6
115.2 113.636
250
625
250
625
3
-
NA
625
-
0
0
1
NA
-
0
NA
-
-
1250
1250
0
0
NA
-
-
NA
-
-
NA
-
-
FOSC = 5.068 MHz
%
4 MHz
3.579 MHz
1 MHz
32.768 kHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
SPBRG
value
SPBRG
value
SPBRG
value
%
%
%
%
KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal)
9.6
19.2
9.6
18.645
0
32
16
NA
1.202
-
-
9.727
18.643 -2.90
+1.32
22
11
8.928
20.833 +8.51
-6.99
6
2
NA
NA
-
-
-
-
-2.94
207
+0.17
+0.13
+0.16
38.4
57.6
115.2
250
625
1250
39.6
52.8
105.6
NA
NA
NA
+3.12
-8.33
-8.33
-
-
-
7
5
2
-
-
-
2.403
9.615
19.231 +0.16
NA
NA
NA
103
25
12
-
-
-
37.286 -2.90
55.930 -2.90
111.860 -2.90
223.721 -10.51
NA
NA
5
3
1
0
-
31.25 -18.61
1
0
-
-
-
NA
NA
NA
NA
NA
NA
-
-
-
-
-
-
-
-
-
-
-
-
62.5
NA
NA
NA
NA
+8.51
-
-
-
-
-
-
-
-
-
-
-
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 75
PIC16F62X
12.1.1 SAMPLING
The data on the RB1/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin. If bit BRGH
(TXSTA<2>) is clear (i.e., at the low baud rates), the
sampling is done on the seventh, eighth and ninth fall-
ing edges of a x16 clock (Figure 12-3). If bit BRGH is
set (i.e., at the high baud rates), the sampling is done
on the 3 clock edges preceding the second rising edge
after the first falling edge of a x4 clock (Figure 12-4 and
Figure 12-5).
FIGURE 12-1: RX PIN SAMPLING SCHEME. BRGH = 0
Start bit
Bit0
RX
(RB1/RX/DT pin)
Baud CLK for all but start bit
baud CLK
x16 CLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
Samples
FIGURE 12-2: RX PIN SAMPLING SCHEME, BRGH = 1
RX pin
bit0
bit1
Start Bit
baud clk
First falling edge after RX pin goes low
Second rising edge
x4 clk
1
2
3
4
1
2
3
4
1
2
Q2, Q4 clk
Samples
Samples
Samples
DS40300B-page 76
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
FIGURE 12-3: RX PIN SAMPLING SCHEME, BRGH = 1
RX pin
Start Bit
bit0
Baud CLK for all but start bit
Baud CLK
First falling edge after RX pin goes low
Second rising edge
x4 CLK
1
2
3
4
Q2, Q4 CLK
Samples
FIGURE 12-4: RX PIN SAMPLING SCHEME, BRGH = 0 OR BRGH = 1
Start bit
Bit0
RX
(RB1/RX/DT pin)
Baud CLK for all but start bit
Baud CLK
x16 CLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
Samples
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 77
PIC16F62X
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicated the sta-
tus of the TXREG register, another bit TRMT
(TXSTA<1>) shows the status of the TSR register. Sta-
tus bit TRMT is a read only bit which is set when the
TSR register is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty.
12.2
USART Asynchronous Mode
In this mode, the USART uses standard nonreturn-to-
zero (NRZ) format (one start bit, eight or nine data bits
and one stop bit). The most common data format is
8-bits. An on-chip dedicated 8-bit baud rate generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LSb first. The USART’s transmitter and receiver are
functionally independent but use the same data format
and baud rate. The baud rate generator produces a
clock either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA<2>). Parity is not supported by
the hardware, but can be implemented in software (and
stored as the ninth data bit). Asynchronous mode is
stopped during SLEEP.
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
Note 2: Flag bit TXIF is set when enable bit TXEN
is set.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift clock (Figure 12-5). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally when transmission
is first started, the TSR register is empty, so a transfer
to the TXREG register will result in an immediate trans-
fer to TSR resulting in an empty TXREG. A back-to-
back transfer is thus possible (Figure 12-7). Clearing
enable bit TXEN during a transmission will cause the
transmission to be aborted and will reset the transmit-
ter. As a result the RB2/TX/CK pin will revert to hi-
impedance.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
12.2.1 USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 12-5. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
flag bit TXIF (PIR1<4>) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
( PIE1<4>). Flag bit TXIF will be set regardless of the
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can result in an immediate transfer of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit maybe loaded in the TSR regis-
ter.
FIGURE 12-5: USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG register
TXIE
8
MSb
(8)
LSb
0
Pin Buffer
and Control
•
•
•
TSR register
RB2/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
DS40300B-page 78
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
Steps to follow when setting up an Asynchronous
Transmission:
4. If 9-bit transmission is desired, then set transmit
bit TX9.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 12.1)
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
7. Load data to the TXREG register (starts trans-
mission).
3. If interrupts are desired, then set enable bit
TXIE.
FIGURE 12-6: ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
Word 1
BRG output
(shift clock)
RB2/TX/CK (pin)
Start Bit
Bit 0
Bit 1
WORD 1
Bit 7/8
Stop Bit
TXIF bit
(Transmit buffer
reg. empty flag)
WORD 1
Transmit Shift Reg
TRMT bit
(Transmit shift
reg. empty flag)
FIGURE 12-7: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG output
(shift clock)
RB2/TX/CK (pin)
Start Bit
Start Bit
WORD 2
Bit 0
Bit 1
Bit 7/8
Bit 0
Stop Bit
TXIF bit
(interrupt reg. flag)
WORD 1
TRMT bit
(Transmit shift
reg. empty flag)
WORD 1
Transmit Shift Reg.
WORD 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 12-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
all other
Resets
Value on
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 -000 0000 -000
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 -000 0000 -000
0000 -010 0000 -010
0000 0000 0000 0000
0Ch
18h
19h
8Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF
FERR OERR RX9D
RCSTA
SPEN
RX9
SREN CREN ADEN
TXREG USART Transmit Register
PIE1
EEIE
CMIE
TX9
RCIE
TXIE
—
—
CCP1IE TMR2IE TMR1IE
BRGH TRMT TX9D
98h
99h
TXSTA
CSRC
TXEN
SYNC
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 79
PIC16F62X
12.2.2 USART ASYNCHRONOUS RECEIVER
ered register, i.e. it is a two deep FIFO. It is possible for
two bytes of data to be received and transferred to the
RCREG FIFO and a third byte begin shifting to the RSR
register. On the detection of the STOP bit of the third
byte, if the RCREG register is still full then overrun error
bit OERR (RCSTA<1>) will be set. The word in the RSR
will be lost. The RCREG register can be read twice to
retrieve the two bytes in the FIFO. Overrun bit OERR
has to be cleared in software. This is done by resetting
the receive logic (CREN is cleared and then set). If bit
OERR is set, transfers from the RSR register to the
RCREG register are inhibited, so it is essential to clear
error bit OERR if it is set. Framing error bit FERR
(RCSTA<2>) is set if a stop bit is detected as clear. Bit
FERR and the 9th receive bit are buffered the same
way as the receive data. Reading the RCREG, will load
bits RX9D and FERR with new values, therefore it is
essential for the user to read the RCSTA register before
reading RCREG register in order not to lose the old
FERR and RX9D information.
The receiver block diagram is shown in Figure 12-8.
The data is received on the RB1/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter oper-
ates at the bit rate or at FOSC.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG register (if
it is empty). If the transfer is complete, flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE (PIE1<5>).
Flag bit RCIF is a read only bit which is cleared by the
hardware. It is cleared when the RCREG register has
been read and is empty. The RCREG is a double buff-
FIGURE 12-8: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
SPBRG
÷ 64
RSR register
LSb
MSb
or
÷ 16
0
Baud Rate Generator
1
7
Stop (8)
Start
• • •
RB1/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
8
SPEN
RX9
Enable
Load of
ADEN
Receive
Buffer
RX9
ADEN
RSR<8>
8
RX9D
RX9D
RCREG register
RCREG register
FIFO
8
RCIF
RCIE
Interrupt
Data Bus
DS40300B-page 80
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
FIGURE 12-9: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
Start
bit
Start
bit
RC7/RX/DT (pin)
bit0
bit1
Stop
bit
bit8 Stop
bit
bit0
bit8
Rcv shift reg
Rcv buffer reg
WORD 1
RCREG
Bit8 = 0, Data Byte
Bit8 = 1, Address Byte
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
’1’
’1’
ADEN = 1
(address match
enable)
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer)
because ADEN = 1 and bit8 = 0.
FIGURE 12-10: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
Start
bit
Start
bit
RC7/RX/DT (pin)
bit0
bit1
Stop
bit
bit8 Stop
bit
bit0
bit8
Rcv shift
reg
Rcv buffer reg
WORD 1
RCREG
Bit8 = 1, Address Byte
Bit8 = 0, Data Byte
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
’1’
’1’
ADEN = 1
(address match
enable)
Note: This timing diagram shows an address byte followed by an data byte. The data byte is not read into the RCREG (receive buffer)
because ADEN was not updated (still = 1) and bit8 = 0.
FIGURE 12-11: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST FOLLOWED BY VALID
DATA BYTE
Start
bit
Start
bit
RC7/RX/DT (pin)
bit0
bit1
Stop
bit
bit8 Stop
bit
bit0
bit8
Rcv shift
reg
Rcv buffer reg
WORD 1
RCREG
WORD 2
RCREG
Bit8 = 1, Address Byte
Bit8 = 0, Data Byte
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
ADEN
(address match
enable)
Note: This timing diagram shows an address byte followed by an data byte. The data byte is read into the RCREG (receive buffer)
because ADEN was updated after an address match, and was cleared to a ‘0’, so the contents of the receive shift register (RSR)
are read into the receive buffer regardless of the value of bit8.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 81
PIC16F62X
Steps to follow when setting up an Asynchronous
Reception:
6. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE was set.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 12.1).
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
2. Enable the asynchronous serial port by clearing
bit SYNC, and setting bit SPEN.
8. Read the 8-bit received data by reading the
RCREG register.
3. If interrupts are desired, then set enable bit
RCIE.
9. If any error occurred, clear the error by clearing
enable bit CREN.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
TABLE 12-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
all other
Resets
Value on
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
RCSTA
SPEN
RX9
SREN CREN ADEN FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
RCREG USART Receive Register
PIE1
EEIE
CMIE
TX9
RCIE
TXIE
—
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
TXSTA
CSRC
TXEN
SYNC
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
DS40300B-page 82
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
12.3.1.1 SETTING UP 9-BIT MODE WITH
12.3
USART Function
ADDRESS DETECT
The USART function is similar to that on the
PIC16C74B, which includes the BRGH = 1 fix.
Steps to follow when setting up an Asynchronous or
Synchronous Reception with Address Detect Enabled:
12.3.1 USART 9-BIT RECEIVER WITH ADDRESS
DETECT
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH.
When the RX9 bit is set in the RCSTA register, 9-bits
are received and the ninth bit is placed in the RX9D bit
of the RCSTA register. The USART module has a spe-
cial provision for multi-processor communication. Mul-
tiprocessor communication is enabled by setting the
ADEN bit (RCSTA<3>) along with the RX9 bit. The port
is now programmed such that when the last bit is
received, the contents of the receive shift register
(RSR) are transferred to the receive buffer, the ninth bit
of the RSR (RSR<8>) is transferred to RX9D, and the
receive interrupt is set if and only if RSR<8> = 1. This
feature can be used in a multi-processor system as fol-
lows:
2. Enable asynchronous or synchronous commu-
nication by setting or clearing bit SYNC and set-
ting bit SPEN.
3. If interrupts are desired, then set enable bit
RCIE.
4. Set bit RX9 to enable 9-bit reception.
5. Set ADEN to enable address detect.
6. Enable the reception by setting enable bit CREN
or SREN.
7. Flag bit RCIF will be set when reception is com-
plete, and an interrupt will be generated if
enable bit RCIE was set.
A master processor intends to transmit a block of data
to one of many slaves. It must first send out an address
byte that identifies the target slave. An address byte is
identified by setting the ninth bit (RSR<8>) to a ’1’
(instead of a ’0’ for a data byte). If the ADEN and RX9
bits are set in the slave’s RCSTA register, enabling mul-
tiprocessor communication, all data bytes will be
ignored. However, if the ninth received bit is equal to a
‘1’, indicating that the received byte is an address, the
slave will be interrupted and the contents of the RSR
register will be transferred into the receive buffer. This
allows the slave to be interrupted only by addresses, so
that the slave can examine the received byte to see if it
is being addressed. The addressed slave will then
clear its ADEN bit and prepare to receive data bytes
from the master.
8. Read the 8-bit received data by reading the
RCREG register to determine if the device is
being addressed.
9. If any error occurred, clear the error by clearing
enable bit CREN if it was already set.
10. If the device has been addressed (RSR<8> = 1
with address match enabled), clear the ADEN
and RCIF bits to allow data bytes and address
bytes to be read into the receive buffer and inter-
rupt the CPU.
When ADEN is enabled (='1'), all data bytes are
ignored. Following the STOP bit, the data will not be
loaded into the receive buffer, and no interrupt will
occur. If another byte is shifted into the RSR register,
the previous data byte will be lost.
The ADEN bit will only take effect when the receiver is
configured in 9-bit mode (RX9 = '1'). When ADEN is
disabled (='0'), all data bytes are received and the 9th
bit can be used as the parity bit.
The receive block diagram is shown in Figure 12-8.
Reception is enabled by setting bit CREN (RCSTA<4>).
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 83
PIC16F62X
TABLE 12-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
all other
Resets
Value on
POR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
EEIF
SPEN
RX7
CMIF
RX9
RX6
CMIE
TX9
RCIF
SREN
RX5
TXIF
CREN
RX4
—
ADEN
RX3
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
RCSTA
RCREG
PIE1
FERR
RX2
OERR
RX1
RX9D
RX0
0000 -00x 0000 -00x
0000 0000 0000 0000
EEIE
CSRC
RCIE
TXEN
TXIE
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
TXSTA
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
ble around the falling edge of the synchronous clock
(Figure 12-12). The transmission can also be started
by first loading the TXREG register and then setting bit
TXEN (Figure 12-13). This is advantageous when slow
baud rates are selected, since the BRG is kept in reset
when bits TXEN, CREN, and SREN are clear. Setting
enable bit TXEN will start the BRG, creating a shift
clock immediately. Normally when transmission is first
started, the TSR register is empty, so a transfer to the
TXREG register will result in an immediate transfer to
TSR resulting in an empty TXREG. Back-to-back trans-
fers are possible.
12.4
USART Synchronous Master Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner, i.e. transmission and reception
do not occur at the same time. When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition enable bit SPEN (RCSTA<7>) is set in order to
configure the RB2/TX/CK and RB1/RX/DT I/O pins to
CK (clock) and DT (data) lines respectively. The Master
mode indicates that the processor transmits the master
clock on the CK line. The Master mode is entered by
setting bit CSRC (TXSTA<7>).
Clearing enable bit TXEN, during a transmission, will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to hi-imped-
ance. If either bit CREN or bit SREN is set, during a
transmission, the transmission is aborted and the DT
pin reverts to a hi-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic however is not
reset although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SREN is set (to interrupt an on-going transmission
and receive a single word), then after the single word is
received, bit SREN will be cleared and the serial port
will revert back to transmitting since bit TXEN is still set.
The DT line will immediately switch from hi-impedance
receive mode to transmit and start driving. To avoid
this, bit TXEN should be cleared.
12.4.1 USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 12-5. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and inter-
rupt bit, TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory so it is not
available to the user.
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is sta-
DS40300B-page 84
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
Steps to follow when setting up a Synchronous Master
Transmission:
4. If 9-bit transmission is desired, then set bit TX9.
5. Enable the transmission by setting bit TXEN.
1. Initialize the SPBRG register for the appropriate
baud rate (Section 12.1).
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
7. Start transmission by loading data to the
TXREG register.
3. If interrupts are desired, then set enable bit
TXIE.
TABLE 12-2:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on
POR
Value on all
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
other Resets
0000 -000
0000 -00x
0000 0000
0000 -000
0000 -010
0000 0000
0000 -000
0000 -00x
0000 0000
0000 -000
0000 -010
0000 0000
0Ch
18h
19h
8Ch
98h
99h
PIR1
EEIF
CMIF RCIF
RX9
TXIF
—
CCP1IF TMR2IF TMR1IF
FERR OERR RX9D
RCSTA
SPEN
SREN CREN ADEN
TXREG USART Transmit Register
PIE1
EEIE
CMIE RCIE
TXIE
—
—
CCP1IE TMR2IE TMR1IE
BRGH TRMT TX9D
TXSTA
CSRC
TX9 TXEN SYNC
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.
FIGURE 12-12: SYNCHRONOUS TRANSMISSION
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4
Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
RB1/RX/DT pin
RB2/TX/CK pin
Bit 0
Bit 1
Bit 2
Bit 7
Bit 0
Bit 1
WORD 2
Bit 7
WORD 1
Write to
TXREG reg
Write word1
Write word2
TXIF bit
(Interrupt flag)
TRMT bit
’1’
Note: Sync master mode; SPBRG = ’0’. Continuous transmission of two 8-bit words
’1’
TXEN bit
FIGURE 12-13: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RB1/RX/DT pin
RB2/TX/CK pin
bit0
bit2
bit1
bit6
bit7
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 85
PIC16F62X
12.4.2 USART SYNCHRONOUS MASTER
RECEPTION
receive bit is buffered the same way as the receive
data. Reading the RCREG register, will load bit RX9D
with a new value, therefore it is essential for the user to
read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN (RCSTA<5>)
or enable bit CREN (RCSTA<4>). Data is sampled on
the RB1/RX/DT pin on the falling edge of the clock. If
enable bit SREN is set, then only a single word is
received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set
then CREN takes precedence. After clocking the last
bit, the received data in the Receive Shift Register
(RSR) is transferred to the RCREG register (if it is
empty). When the transfer is complete, interrupt flag bit
RCIF (PIR1<5>) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit which is
reset by the hardware. In this case it is reset when the
RCREG register has been read and is empty. The
RCREG is a double buffered register, i.e. it is a two
deep FIFO. It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full then overrun error bit OERR
(RCSTA<1>) is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so
it is essential to clear bit OERR if it is set. The 9th
Steps to follow when setting up a Synchronous Master
Reception:
1. Initialize the SPBRG register for the appropriate
baud rate. (Section 12.1)
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
TABLE 12-3: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on:
POR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 -000
0000 -00x
0000 0000
-000 0000
0000 -010
0000 0000
0000 -000
0000 -00x
0000 0000
-000 -000
0000 -010
0000 0000
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
EEIF
CMIF RCIF
RX9
TXIF
—
CCP1IF TMR2IF TMR1IF
FERR OERR RX9D
RCSTA
SPEN
SREN CREN ADEN
RCREG USART Receive Register
PIE1
EEPIE
CSRC
CMIE RCIE
TXIE
—
—
CCP1IE TMR2IE TMR1IE
BRGH TRMT TX9D
TXSTA
TX9 TXEN SYNC
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception.
DS40300B-page 86
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
FIGURE 12-14: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2Q3 Q4Q1Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4Q1Q2 Q3Q4 Q1 Q2Q3Q4Q1Q2 Q3 Q4 Q1 Q2Q3Q4Q1Q2 Q3Q4 Q1Q2 Q3 Q4 Q1 Q2Q3Q4
RB1/RX/DT pin
RB2/TX/CK pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Write to
bit SREN
SREN bit
CREN bit
’0’
’0’
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC master mode with bit SREN = ’1’ and bit BRG = ’0’.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 87
PIC16F62X
12.5.2 USART SYNCHRONOUS SLAVE
RECEPTION
12.5
USART Synchronous Slave Mode
Synchronous slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RB2/TX/CK pin (instead of being supplied internally
in master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
The operation of the synchronous master and slave
modes is identical except in the case of the SLEEP
mode. Also, bit SREN is a don’t care in slave mode.
If receive is enabled, by setting bit CREN, prior to the
SLEEPinstruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
12.5.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the synchronous master and slave
modes are identical except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
Steps to follow when setting up a Synchronous Slave
Reception:
a) The first word will immediately transfer to the
TSR register and transmit.
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
2. If interrupts are desired, then set enable bit
RCIE.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
3. If 9-bit reception is desired, then set bit RX9.
4. To enable reception, set enable bit CREN.
5. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the inter-
rupt vector (0004h).
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Steps to follow when setting up a Synchronous Slave
Transmission:
7. Read the 8-bit received data by reading the
RCREG register.
1. Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
8. If any error occurred, clear the error by clearing
bit CREN.
2. Clear bits CREN and SREN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, then set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
DS40300B-page 88
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
TABLE 12-4: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on
POR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 -000
0000 -00x
0000 0000
0000 -000
0000 -010
0000 0000
0000 -000
0000 -00x
0000 0000
0000 -000
0000 -010
0000 0000
0Ch
18h
19h
8Ch
98h
99h
PIR1
EEIF
CMIF RCIF
RX9
TXIF
—
CCP1IF TMR2IF TMR1IF
FERR OERR RX9D
RCSTA
SPEN
SREN CREN ADEN
TXREG USART Transmit Register
PIE1
EEIE
CMIE RCIE
TXIE
—
—
CCP1IE TMR2IE TMR1IE
BRGH TRMT TX9D
TXSTA
CSRC
TX9 TXEN SYNC
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
TABLE 12-5: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on
POR
Value on all
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
other Resets
0000 -000
0000 -00x
0000 0000
0000 -000
0000 -010
0000 0000
0000 -000
0000 -00x
0000 0000
0000 -000
0000 -010
0000 0000
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
EEIF
CMIF RCIF
RX9
TXIF
—
CCP1IF TMR2IF TMR1IF
FERR OERR RX9D
RCSTA
SPEN
SREN CREN ADEN
RCREG USART Receive Register
PIE1
EEIE
CMIE RCIE
TXIE
—
—
CCP1IE TMR2IE TMR1IE
BRGH TRMT TX9D
TXSTA
CSRC
TX9 TXEN SYNC
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 89
PIC16F62X
NOTES:
DS40300B-page 90
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write). The EEPROM
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The write-
time will vary with voltage and temperature as well as
from chip to chip. Please refer to AC specifications for
exact limits.
13.0 DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during normal operation (full VDD range). This memory
is not directly mapped in the register file space. Instead
it is indirectly addressed through the Special Function
Registers. There are four SFRs used to read and write
this memory. These registers are:
• EECON1
When the device is code protected, the CPU may
continue to read and write the data EEPROM memory.
The device programmer can no longer access
this memory.
• EECON2 (Not a physically implemented register)
• EEDATA
• EEADR
EEDATA holds the 8-bit data for read/write, and EEADR
holds the address of the EEPROM location being
accessed. PIC16F62X devices have 128 bytes of data
EEPROM with an address range from 0h to 7Fh.
Additional information on the Data EEPROM is avail-
able in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
REGISTER 13-1: EEADR REGISTER (ADDRESS 9Bh)
U
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EADR6 EADR5 EADR4 EADR3 EADR2 EADR1 EADR0
bit0
R = Readable bit
W = Writable bit
S = Settable bit
bit7
U = Unimplemented bit, read
as ‘0’
-n = Value at POR reset
bit 7
Unimplemented Address: Must be set to '0'
bit 6:0 EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation
13.1
EEADR
The EEADR register can address up to a maximum of
256 bytes of data EEPROM. Only the first 128 bytes of
data EEPROM are implemented and only seven of the
eight bits in the register (EEADR<6:0>) are required.
The upper bit is address decoded. This means that
this bit should always be ’0’ to ensure that the address
is in the 128 byte memory space.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 91
PIC16F62X
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit
is set when a write operation is interrupted by a MCLR
reset or a WDT time-out reset during normal opera-
tion. In these situations, following reset, the user can
check the WRERR bit and rewrite the location. The
data and address will be unchanged in the EEDATA
and EEADR registers.
13.2
EECON1 AND EECON2 REGISTERS
EECON1 is the control register with five low order bits
physically implemented. The upper-three bits are non-
existent and read as ’0’s.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
Interrupt flag bit EEIF in the PIR1 register is set when
write is complete. This bit must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all ’0’s. The EECON2 register is used
exclusively in the Data EEPROM write sequence.
REGISTER 13-2: EECON1 REGISTER (ADDRESS 9Ch) DEVICES
U
—
U
U
U
R/W-x
R/W-0
R/S-0
R/S-x
RD
—
—
—
WRERR
WREN
WR
R = Readable bit
W = Writable bit
S = Settable bit
bit7
bit0
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7:4 Unimplemented: Read as '0'
bit 3
WRERR: EEPROM Error Flag bit
1= A write operation is prematurely terminated
(any MCLR reset, any WDT reset during normal operation or BOD detect)
0= The write operation completed
bit 2
bit 1
WREN: EEPROM Write Enable bit
1= Allows write cycles
0= Inhibits write to the data EEPROM
WR: Write Control bit
1= initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only
be set (not cleared) in software.
0= Write cycle to the data EEPROM is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only be
set (not cleared) in software).
0= Does not initiate an EEPROM read
DS40300B-page 92
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit in the
PIR1 registers must be cleared by software.
13.3
READING THE EEPROM DATA
MEMORY
To read a data memory location, the user must write
the address to the EEADR register and then set con-
trol bit RD (EECON1<0>). The data is available, in the
very next cycle, in the EEDATA register; therefore it
can be read in the next instruction. EEDATA will hold
this value until another read or until it is written to by
the user (during a write operation).
13.5
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the Data
EEPROM should be verified (Example 13-3) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the specification limit.
EXAMPLE 13-1: DATA EEPROM READ
BCF
STATUS, RP0 ; Bank 0
MOVLW CONFIG_ADDR
;
MOVWF
BSF
BSF
BCF
MOVF
EEADR
; Address to read
STATUS, RP0 ; Bank 1
EECON1, RD ; EE Read
STATUS, RP0 ; Bank 0
EEDATA, W ; W = EEDATA
EXAMPLE 13-3: WRITE VERIFY
BCF
:
STATUS, RP0 ; Bank 0
; Any code can go here
:
;
13.4
WRITING TO THE EEPROM DATA
MEMORY
MOVF EEDATA, W
BSF
BSF
; Must be in Bank 0
STATUS, RP0 ; Bank 1 READ
EECON1, RD ; YES, Read the
; value written
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte.
BCF
STATUS, RP0 ; Bank 0
;
; Is the value written (in W reg) and
; read (in EEDATA) the same?
;
EXAMPLE 13-2: DATA EEPROM WRITE
SUBWF EEDATA, W
;
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
STATUS, RP0
EECON1, WREN
INTCON, GIE
55h
EECON2
AAh
; Bank 1
BTFSS STATUS, Z
GOTO WRITE_ERR
:
:
; Is difference 0?
; NO, Write error
; YES, Good write
; Continue program
; Enable write
; Disable INTs.
;
; Write 55h
;
; Write AAh
; Set WR bit
; begin write
; Enable INTs.
EECON2
EECON1,WR
13.6
PROTECTION AGAINST SPURIOUS
WRITE
BSF
INTCON, GIE
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also,
the Power-up Timer (72 ms duration) prevents
EEPROM write.
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number what is not equal to
the required cycles to execute the required sequence
will cause the data not to be written into the EEPROM.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware
13.7
DATA EEPROM OPERATION DURING
CODE PROTECT
When the device is code protected, the CPU is able to
read and write unscrambled data to the Data
EEPROM.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit
will be inhibited from being set unless the WREN bit is
set.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 93
PIC16F62X
TABLE 13-1
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Value on
Power-on
Reset
Value on all
other resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9Ah
EEDATA
EEADR
EEPROM data register
EEPROM address register
xxxx xxxx
xxxx xxxx
---- x000
---- ----
uuuu uuuu
uuuu uuuu
---- q000
---- ----
9Bh
9Ch
9Dh
EECON1
EECON2(1)
—
—
—
—
WRERR
WREN
WR
RD
EEPROM control register 2
Legend: x= unknown, u= unchanged, -= unimplemented read as ’0’, q= value depends upon condition. Shaded cells are not used
by data EEPROM.
Note 1: EECON2 is not a physical register
DS40300B-page 94
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
The PIC16F62X has a Watchdog Timer which is
controlled by configuration bits. It runs off its own RC
oscillator for added reliability. There are two timers that
offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), intended to keep the
chip in reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only,
designed to keep the part in reset while the power
supply stabilizes. There is also circuitry to reset the
device if a brown-out occurs which provides at least a
72 ms reset. With these three functions on-chip, most
applications need no external reset circuitry.
14.0 SPECIAL FEATURES OF THE
CPU
Special circuits to deal with the needs of real time appli-
cations are what sets a microcontroller apart from other
processors. The PIC16F62X family has a host of such
features intended to maximize system reliability, mini-
mize cost through elimination of external components,
provide power saving operating modes and offer code
protection.
These are:
1. OSC selection
2. Reset
The SLEEP mode is designed to offer a very low
current power-down mode. The user can wake-up from
SLEEP through external reset, Watchdog Timer
wake-up or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The ER oscillator option saves system
cost while the LP crystal option saves power. A set of
configuration bits are used to select various options.
Power-on Reset (POR)
Power-up Timer (PWRT)
Oscillator Start-Up Timer (OST)
Brown-out Reset (BOD)
3. Interrupts
4. Watchdog Timer (WDT)
5. SLEEP
6. Code protection
7. ID Locations
8. In-circuit serial programming
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 95
PIC16F62X
The user will note that address 2007h is beyond
the user program memory space. In fact, it belongs
to the special configuration memory space (2000h
– 3FFFh), which can be accessed only during program-
ming.
14.1
Configuration Bits
The configuration bits can be programmed (read as ’0’)
or left unprogrammed (read as ’1’) to select various
device configurations. These bits are mapped in
program memory location 2007h.
FIGURE 14-1: CONFIGURATION WORD
CP1 CP0
bit13
CP1
CP0
-
CPD LVP BODEN MCLRE FOSC2
PWRTE
WDTE
F0SC1
F0SC0
bit0
Register:CONFIG
Address2007h
bit 13-10:CP1:CP0: Code Protection bits (2)
Code protection for 2K program memory
11= Program memory code protection off
10= 0400h-07FFh code protected
01= 0200h-07FFh code protected
00= 0000h-07FFhcode protected
Code protection for 1K program memory
11= Program memory code protection off
10= Program memory code protection off
01= 0200h-03FFh code protected
00= 0000h-03FFh code protected
bit 8:
bit 7:
bit 6:
bit 5:
bit 3:
bit 2:
CPD: Data Code Protection bit(3)
1= Data memory code protection off
0= Data memory code protected
LVP: Low Voltage Programming Enable
1= RB4/PGM pin has PGM function, low voltage programming enabled
0= RB4/PGM is digital I/O, HV on MCLR must be used for programming
BODEN: Brown-out Detect Enable bit (1)
1= BOD enabled
0= BOD disabled
MCLRE: RA5/MCLR pin function select
1= RA5/MCLR pin function is MCLR
0= RA5/MCLR pin function is digital I/O, MCLR internally tied to VDD
PWRTE: Power-up Timer Enable bit (1)
1= PWRT disabled
0= PWRT enabled
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
bit 4,1-0:FOSC2:FOSC0: Oscillator Selection bits(4)
111= ER oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN
110= ER oscillator: I/O function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN
101= INTRC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
100= INTRC oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
011= EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN
010= HS oscillator: High speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
001= XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
000= LP oscillator: Low power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the
Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
3: The entire data EEPROM will be erased when the code protection is turned off.
4: When MCLR is asserted in INTRC or ER mode, the internal clock oscillator is disabled.
DS40300B-page 96
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
14.2
Oscillator Configurations
TABLE 14-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
14.2.1
OSCILLATOR TYPES
Ranges Characterized:
The PIC16F62X can be operated in eight different
oscillator options. The user can program three
configuration bits (FOSC2 thru FOSC0) to select one of
these eight modes:
Mode
Freq
OSC1(C1)
OSC2(C2)
455 kHz
2.0 MHz
4.0 MHz
22 - 100 pF
15 - 68 pF
15 - 68 pF
22 - 100 pF
15 - 68 pF
15 - 68 pF
XT
• LP
Low Power Crystal
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
• XT
Crystal/Resonator
HS
• HS
• ER
• INTRC
• EC
High Speed Crystal/Resonator
External Resistor (2 modes)
Internal Resistor/Capacitor (2 modes)
External Clock In
Higher capacitance increases the stability of the oscillator
but also increases the start-up time. These values are for
design guidance only. Since each resonator has its own
characteristics, the user should consult the resonator man-
ufacturer for appropriate values of external components.
14.2.2 CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
TABLE 14-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1 and OSC2 pins to establish
oscillation (Figure 14-2). The PIC16F62X oscillator
design requires the use of a parallel cut crystal. Use of
a series cut crystal may give a frequency out of the
crystal manufacturers specifications. When in XT, LP or
HS modes, the device can have an external clock
source to drive the OSC1 pin (Figure 14-3).
Mode
Freq
OSC1(C1)
OSC2(C2)
LP
32 kHz
200 kHz
68 - 100 pF
15 - 30 pF
68 - 100 pF
15 - 30 pF
XT
HS
100 kHz
2 MHz
4 MHz
68 - 150 pF
15 - 30 pF
15 - 30 pF
150 - 200 pF
15 - 30 pF
15 - 30 pF
8 MHz
10 MHz
20 MHz
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
FIGURE 14-2: CRYSTAL OPERATION
(OR CERAMIC RESONATOR)
(HS, XT OR LP OSC
Higher capacitance increases the stability of the oscillator
but also increases the start-up time. These values are for
design guidance only. Rs may be required in HS mode as
well as XT mode to avoid overdriving crystals with low drive
level specification. Since each crystal has its own
characteristics, the user should consult the crystal manu-
facturer for appropriate values of external components.
CONFIGURATION)
OSC1
To internal logic
C1
XTAL
RS
SLEEP
RF
OSC2
see Note
C2
PIC16F62X
See Table 14-1 and Table 14-2 for recommended
values of C1 and C2.
Note: A series resistor may be required for
AT strip cut crystals.
FIGURE 14-3: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
Clock from
ext. system
OSC1
PIC16F62X
OSC2
Open
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 97
PIC16F62X
14.2.3 EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
14.2.4 EXTERNAL CLOCK IN
For applications where a clock is already available else-
where, users may directly drive the PIC16F62X pro-
vided that this external clock source meets the AC/DC
timing requirements listed in Section 17.4. Figure 14-6
below shows how an external clock circuit should be
configured.
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built.
Prepackaged oscillators provide a wide operating
range and better stability. A well-designed crystal
oscillator will provide good performance with TTL
gates. Two types of crystal oscillator circuits can be
used; one with series resonance, or one with parallel
resonance.
FIGURE 14-6: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
Figure 14-4 shows implementation of a parallel reso-
nant oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180° phase shift that a parallel
oscillator requires. The 4.7 kΩ resistor provides the
negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
This could be used for external oscillator designs.
Clock from
OSC1/RA7
ext. system
PIC16F62X
OSC2/RA6
RA6
14.2.5 ER OSCILLATOR
FIGURE 14-4: EXTERNAL PARALLEL
RESONANT CRYSTAL
For timing insensitive applications, the ER (External
Resistor) clock mode offers additional cost savings.
Only one external component, a resistor to VSS, is
needed to set the operating frequency of the internal
oscillator. The resistor draws a DC bias current which
controls the oscillation frequency. In addition to the
resistance value, the oscillator frequency will vary from
unit to unit, and as a function of supply voltage and tem-
perature. Since the controlling parameter is a DC cur-
rent and not a capacitance, the particular package type
and lead frame will not have a significant effect on the
resultant frequency.
OSCILLATOR CIRCUIT
+5V
To other
Devices
10k
74AS04
4.7k
PIC16F62X
CLKIN
74AS04
10k
XTAL
Figure 14-7 shows how the controlling resistor is con-
nected to the PIC16F62X. For Rext values below 38k,
the oscillator operation may become unstable, or stop
completely. For very high Rext values (e.g. 1M), the
oscillator becomes sensitive to noise, humidity and
leakage. Thus, we recommend keeping Rext between
38k and 1M.
10k
20 pF
20 pF
Figure 14-5 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180°
phase shift in a series resonant oscillator circuit. The
330 kΩ resistors provide the negative feedback to bias
the inverters in their linear region.
FIGURE 14-7: EXTERNAL RESISTOR
RA7/OSC1/CLKIN
FIGURE 14-5: EXTERNAL SERIES
RESONANT CRYSTAL
RA6/OSC2/CLKOUT
OSCILLATOR CIRCUIT
To other
Devices
330 kΩ
330 kΩ
PIC16F62X
The Electrical Specification section shows the relation-
ship between the resistance value and the operating
frequency as well as frequency variations due to oper-
ating temperature for given R and VDD values.
74AS04
74AS04
74AS04
CLKIN
0.1 µF
The ER oscillator mode has two options that control the
unused OSC2 pin. The first allows it to be used as a
general purpose I/O port. The other configures the pin
as an output providing the Fosc signal (internal clock
divided by 4) for test or external synchronization pur-
poses.
XTAL
DS40300B-page 98
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
14.2.6 INTERNAL 4 MHZ OSCILLATOR
14.4
Reset
The internal RC oscillator provides a fixed 4 MHz (nom-
inal) system clock at Vdd = 5V and 25°C, see “Electrical
Specifications” section for information on variation over
voltage and temperature.
The PIC16F62X differentiates between various kinds
of reset:
a) Power-on reset (POR)
b) MCLR reset during normal operation
c) MCLR reset during SLEEP
d) WDT reset (normal operation)
e) WDT wake-up (SLEEP)
14.2.7 CLKOUT
The PIC16F62X can be configured to provide a clock
out signal by programming the configuration word. The
oscillator frequency, divided by 4 can be used for test
purposes or to synchronize other logic.
f) Brown-out Detect (BOD)
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on reset, MCLR reset, WDT reset and
MCLR reset during SLEEP. They are not affected by a
WDT wake-up, since this is viewed as the resumption
of normal operation. TO and PD bits are set or cleared
differently in different reset situations as indicated in
Table 14-4. These bits are used in software to deter-
mine the nature of the reset. See Table 14-7 for a full
description of reset states of all registers.
14.3
Special Feature: Dual Speed
Oscillator Modes
A software programmable dual speed oscillator mode
is provided when the PIC16F62X is configured in either
ER or INTRC oscillator modes. This feature allows
users to dynamically toggle the oscillator speed
between 4MHz and 37kHz. In ER mode, the 4MHz set-
ting will vary depending on the size of the external
resistor. Also in ER mode, the 37kHz operation is fixed
and does not vary with resistor size. Applications that
require low current power savings, but cannot tolerate
putting the part into sleep, may use this mode.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 14-8.
The MCLR reset path has a noise filter to detect and
ignore small pulses. See Table 12-6 for pulse width
specification.
The OSCF bit in the PCON register is used to control
dual speed mode. See Section 4.2.2.6, Figure 4-9.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 99
PIC16F62X
FIGURE 14-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/
VPP Pin
SLEEP
WDT
WDT
Module
Time-out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
detect
BODEN
S
R
Q
Q
OST/PWRT
OST
10-bit Ripple-counter
Chip_Reset
OSC1/
CLKIN
Pin
PWRT
10-bit Ripple-counter
(1)
On-chip
ER OSC
Enable PWRT
Enable OST
See Table 14-3 for time-out situations.
Note 1: This is a separate oscillator from the INTRC/EC oscillator.
DS40300B-page 100
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
The Power-Up Time delay will vary from chip to chip
and due to VDD, temperature and process variation.
See DC parameters for details.
14.5
Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST) and Brown-out Detect
(BOD)
14.5.3 OSCILLATOR START-UP TIMER (OST)
14.5.1 POWER-ON RESET (POR)
The Oscillator Start-Up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The on-chip POR circuit holds the chip in reset until
VDD has reached a high enough level for proper opera-
tion. To take advantage of the POR, just tie the MCLR
pin through a resistor to VDD. This will eliminate exter-
nal RC components usually needed to create Power-on
Reset. A maximum rise time for VDD is required. See
Electrical Specifications for details.
The OST time-out is invoked only for XT, LP and HS
modes and only on power-on reset or wake-up from
SLEEP.
14.5.4 BROWN-OUT DETECT (BOD)
The POR circuit does not produce an internal reset
when VDD declines.
The PIC16F62X members have on-chip Brown-out
Detect circuitry. A configuration bit, BODEN, can dis-
able (if clear/programmed) or enable (if set) the
Brown-out Detect circuitry. If VDD falls below 4.0V, refer
to VBOD parameter D005(VBOD) for greater than
parameter (TBOD) in Table 17.1, the brown-out situa-
tion will reset the chip. A reset is not guaranteed to
occur if VDD falls below 4.0V for less than parameter
(TBOD).
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, etc.) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
For additional information, refer to Application Note
AN607 “Power-up Trouble Shooting”.
On any reset (Power-on, Brown-out, Watchdog, etc.)
the chip will remain in Reset until VDD rises above
BVDD. The Power-up Timer will now be invoked and will
keep the chip in reset an additional 72 ms.
14.5.2 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates on an internal RC
oscillator. The chip is kept in reset as long as PWRT is
active. The PWRT delay allows the VDD to rise to an
acceptable level. A configuration bit, PWRTE can
disable (if set) or enable (if cleared or programmed) the
Power-up Timer. The Power-up Timer should always be
enabled when Brown-out Reset is enabled.
If VDD drops below BVDD while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above BVDD, the Power-Up Timer will execute a
72 ms reset. The Power-up Timer should always be
enabled when Brown-out Detect is enabled.
Figure 14-9 shows typical Brown-out situations.
FIGURE 14-9: BROWN-OUT SITUATIONS
VDD
BVDD
Internal
Reset
72 ms
VDD
BVDD
Internal
Reset
<72 ms
72 ms
VDD
BVDD
Internal
Reset
72 ms
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 101
PIC16F62X
14.5.5 TIME-OUT SEQUENCE
14.5.6 POWER CONTROL (PCON)/
STATUS REGISTER
On power-up the time-out sequence is as follows: First
PWRT time-out is invoked after POR has expired. Then
OST is activated. The total time-out will vary based on
oscillator configuration and PWRTE bit status. For
example, in ER mode with PWRTE bit erased (PWRT
disabled), there will be no time-out at all. Figure 14-10,
Figure 14-11 and Figure 14-12 depict time-out
sequences.
The power control/status register, PCON (address
8Eh) has two bits.
Bit0 is BOD (Brown-out). BOD is unknown on
power-on-reset. It must then be set by the user and
checked on subsequent resets to see if BOD = 0
indicating that a brown-out has occurred. The BOD
status bit is a don’t care and is not necessarily
predictable if the brown-out circuit is disabled (by
setting BODEN bit = 0 in the Configuration word).
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 14-11). This is useful for testing purposes
or to synchronize more than one PIC16F62X device
operating in parallel.
Bit1 is POR (Power-on-reset). It is
a ‘0’ on
power-on-reset and unaffected otherwise. The user
must write a ‘1’ to this bit following a power-on-reset.
On a subsequent reset if POR is ‘0’, it will indicate that
a power-on-reset must have occurred (VDD may have
gone too low).
Table 14-6 shows the reset conditions for some special
registers, while Table 14-7 shows the reset conditions
for all the registers.
TABLE 14-3: TIME-OUT IN VARIOUS SITUATIONS
Power-up
Wake-up
Brown-out Reset
Oscillator Configuration
from SLEEP
PWRTE = 0
PWRTE = 1
XT, HS, LP
ER
72 ms + 1024 TOSC
72 ms
1024 TOSC
72 ms + 1024 TOSC
1024 TOSC
—
72 ms
—
TABLE 14-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE
POR
BOD
TO
PD
0
0
0
1
1
1
1
1
X
X
X
0
1
1
1
1
1
0
X
X
0
0
u
1
1
X
0
X
u
0
u
0
Power-on-reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Detect
WDT Reset
WDT Wake-up
MCLR reset during normal operation
MCLR reset during SLEEP
Legend: u = unchanged, x = unknown
TABLE 14-5: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Value on all
other resets(1)
Value on POR
Reset
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0001 1xxx
---- 1-0x
000q quuu
---- u-uq
03h
STATUS
PCON
RPO
TO
PD
Z
DC
C
IRP
RP1
8Eh
—
—
—
—
OSCF
—
POR
BOD
Note 1:
Other (non power-up) resets include MCLR reset, Brown-out Detect and Watchdog Timer Reset during normal operation.
DS40300B-page 102
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
TABLE 14-6: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Condition
Power-on Reset
000h
000h
000h
000h
PC + 1
000h
0001 1xxx
000u uuuu
0001 0uuu
0000 uuuu
uuu0 0uuu
000x xuuu
uuu1 0uuu
---- 1-0x
---- 1-uu
---- 1-uu
---- 1-uu
---- --uu
---- 1-u0
---- --uu
MCLR reset during normal operation
MCLR reset during SLEEP
WDT reset
WDT Wake-up
Brown-out Detect
(1)
Interrupt Wake-up from SLEEP
PC + 1
Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector
(0004h) after execution of PC+1.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 103
PIC16F62X
TABLE 14-7: INITIALIZATION CONDITION FOR REGISTERS
•
•
MCLR Reset during
•
•
Wake up from
SLEEP through
interrupt
Wake up from
SLEEP through
WDT time-out
normal operation
MCLR Reset during
SLEEP
WDT Reset
Brown-out Detect (1)
•
•
Register
Address
Power-on Reset
W
-
xxxx xxxx
-
uuuu uuuu
-
uuuu uuuu
-
INDF
TMR0
PCL
00h
01h
02h
xxxx xxxx
0000 0000
uuuu uuuu
0000 0000
uuuu uuuu
PC + 1(3)
000q quuu(4)
uuuu uuuu
xxxx u000
uuuu uuuu
--uu uuuu
-000 0000
--00 0000
0000 -00x
0000 0000
---0 0000
0000 000u
uuuq quuu(4)
uuuu uuuu
xxxx 0000
uuuu uuuu
STATUS
FSR
03h
04h
05h
06h
10h
12h
17h
18h
1Fh
0Ah
0Bh
0001 1xxx
xxxx xxxx
xxxx 0000
xxxx xxxx
--00 0000
-000 0000
--00 0000
0000 -00x
0000 0000
---0 0000
0000 000x
PORTA
PORTB
T1CON
T2CON
CCP1CON
RCSTA
CMCON
PCLATH
INTCON
uu-- uuuu
---u uuuu
uuuu uqqq(2)
-q-- ----(2,5)
uuuu uuuu
uu-u uuuu
uuuu uuuu
uuuu -uuu
---- --uu
PIR1
OPTION
TRISA
TRISB
PIE1
0Ch
81h
85h
86h
8Ch
8Eh
98h
9Ch
9Fh
0000 -000
1111 1111
11-1 1111
1111 1111
0000 -000
---- 1-0x
0000 -010
---- x000
000- 0000
0000 -000
1111 1111
11-- 1111
1111 1111
0000 -000
---- 1-uq(1,6)
0000 -010
PCON
TXSTA
EECON1
VRCON
---- q000
000- 0000
uuu- uuuu
Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’, q= value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 14-6 for reset value for specific condition.
5: If wake-up was due to comparator input changing, then bit 6 = 1. All other interrupts generating a wake-up will cause
bit 6 = u.
6: If reset was due to brown-out, then bit 0 = 0. All other resets will cause bit 0 = u.
DS40300B-page 104
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
FIGURE 14-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 14-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 14-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 105
PIC16F62X
FIGURE 14-13: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
FIGURE 14-14: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
VDD
33k
VDD
VDD
10k
MCLR
D
R
40k
R1
PIC16F62X
MCLR
PIC16F62X
C
Note 1: External power-on reset circuit is required only
if VDD power-up slope is too slow. The diode D
helps discharge the capacitor quickly when
VDD powers down.
Note 1: This circuit will activate reset when VDD
goes below (Vz + 0.7V) where Vz = Zener
voltage.
2: Internal Brown-out Reset circuitry should be
disabled when using this circuit.
2: < 40 kΩ is recommended to make sure that
voltage drop across R does not violate the
device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current flowing
into MCLR from external capacitor C in the
event of MCLR/VPP pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
FIGURE 14-15: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
VDD
VDD
R1
Q1
MCLR
R2
40k
PIC16F62X
Note 1: This brown-out circuit is less expensive,
albeit less accurate. Transistor Q1 turns off
when VDD is below a certain level such that:
R1
= 0.7 V
VDD x
R1 + R2
2: Internal brown-out reset should be disabled
when using this circuit.
3: Resistors should be adjusted for the charac-
teristics of the transistor.
DS40300B-page 106
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the interrupt service routine the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in soft-
ware before re-enabling interrupts to avoid RB0/INT
recursive interrupts.
14.6
Interrupts
The PIC16F62X has 10 sources of interrupt:
• External Interrupt RB0/INT
• TMR0 Overflow Interrupt
• PortB Change Interrupts (pins RB7:RB4)
• Comparator Interrupt
• USART Interrupt
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs
(Figure 14-17). The latency is the same for one or two
cycle instructions. Once in the interrupt service routine
the source(s) of the interrupt can be determined by poll-
ing the interrupt flag bits. The interrupt flag bit(s) must
be cleared in software before re-enabling interrupts to
avoid multiple interrupt requests. Individual interrupt
flag bits are set regardless of the status of their
corresponding mask bit or the GIE bit.
• CCP Interrupt
• TMR1 Overflow Interrupt
• TMR2 Match Interrupt
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on reset.
Note 1: Individual interrupt flag bits are set
regardless of the status of their
corresponding mask bit or the GIE bit.
The “return from interrupt” instruction, RETFIE, exits
interrupt routine as well as sets the GIE bit, which
re-enable RB0/INT interrupts.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The CPU will execute a
NOP in the cycle immediately following
the instruction which clears the GIE bit.
The interrupts which were ignored are
still pending to be serviced when the GIE
bit is set again.
The INT pin interrupt, the RB port change interrupt and
the TMR0 overflow interrupt flags are contained in the
INTCON register.
The peripheral interrupt flag is contained in the special
register PIR1. The corresponding interrupt enable bit is
contained in special registers PIE1.
FIGURE 14-16: INTERRUPT LOGIC
Wake-up (If in SLEEP mode)
Interrupt to CPU
T0IF
T0IE
TMR1IF
TMR1IE
INTF
INTE
TMR2IF
TMR2IE
RBIF
RBIE
CCP1IF
CCP1IE
CMIF
CMIE
PEIE
TXIF
TXIE
GIE
RCIF
RCIE
EEIF
EEIE
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 107
PIC16F62X
14.6.1 RB0/INT INTERRUPT
14.6.3 PORTB INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION<6>) is set, or fall-
ing, if INTEDG bit is clear. When a valid edge appears
on the RB0/INT pin, the INTF bit (INTCON<1>) is set.
This interrupt can be disabled by clearing the INTE
control bit (INTCON<4>). The INTF bit must be cleared
in software in the interrupt service routine before
re-enabling this interrupt. The RB0/INT interrupt can
wake-up the processor from SLEEP, if the INTE bit was
set prior to going into SLEEP. The status of the GIE bit
decides whether or not the processor branches to the
interrupt vector following wake-up. See Section 14.9 for
details on SLEEP and Figure 14-19 for timing of
wake-up from SLEEP through RB0/INT interrupt.
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/dis-
abled by setting/clearing the RBIE (INTCON<4>) bit.
For operation of PORTB (Section 5.2).
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
14.6.4 COMPARATOR INTERRUPT
See Section 9.6 for complete description of comparator
interrupts.
14.6.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be enabled/disabled by setting/clearing T0IE
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 6.0.
FIGURE 14-17: INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT
3
4
INT pin
1
1
Interrupt Latency
INTF flag
(INTCON<1>)
5
2
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
0004h
PC
PC+1
PC+1
0005h
Instruction
Inst (PC+1)
—
Inst (0004h)
Inst (PC)
Inst (0005h)
Inst (0004h)
fetched
Instruction
executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC-1)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 Tcy. Synchronous latency = 3 Tcy, where Tcy = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in ER oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
TABLE 14-8: SUMMARY OF INTERRUPT REGISTERS
Value on all
other resets(1)
Value on POR
Reset
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh
INTCON
GIE
EEIF
EEIE
PEIE
CMIF
CMIE
T0IE
RCIF
RCIE
INTE
TXIF
TXIE
RBIE
—
T0IF
INTF
RBIF
0000 000x
0000 -000
0000 -000
0000 000u
0000 -000
0000 -000
0Ch
PIR1
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
8Ch
PIE1
—
Note 1:
Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during normal operation.
DS40300B-page 108
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
14.7
Context Saving During Interrupts
14.8
Watchdog Timer (WDT)
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt e.g. W register and STATUS
register. This will have to be implemented in software.
The watchdog timer is a free running on-chip RC oscil-
lator which does not require any external components.
This RC oscillator is separate from the ER oscillator of
the CLKIN pin. That means that the WDT will run, even
if the clock on the OSC1 and OSC2 pins of the device
has been stopped, for example, by execution of a
SLEEP instruction. During normal operation, a WDT
time-out generates a device RESET. If the device is in
SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation. The WDT
can be permanently disabled by programming the con-
figuration bit WDTE as clear (Section 14.1).
Example 14-1 stores and restores the STATUS and W
registers. The user register, W_TEMP, must be defined
in both banks and must be defined at the same offset
from the bank base address (i.e., W_TEMP is defined
at 0x20 in Bank 0 and it must also be defined at 0xA0
in Bank 1). The user register, STATUS_TEMP, must be
defined in Bank 0. The Example 14-1:
• Stores the W register
14.8.1 WDT PERIOD
• Stores the STATUS register in Bank 0
• Executes the ISR code
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with tempera-
ture, VDD and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
• Restores the STATUS (and bank select bit
register)
• Restores the W register
EXAMPLE 14-1: SAVING THE STATUS AND
W REGISTERS IN RAM
MOVWF
W_TEMP
;copy W to temp register,
;could be in either bank
The CLRWDTand SLEEPinstructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
SWAPF
BCF
STATUS,W
;swap status to be saved into W
STATUS,RP0
;change to bank 0 regardless
;of current bank
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
MOVWF
STATUS_TEMP
(ISR)
;save status to bank 0
;register
:
14.8.2 WDT PROGRAMMING CONSIDERATIONS
:
:
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., max.
WDT prescaler) it may take several seconds before a
WDT time-out occurs.
SWAPF
STATUS_TEMP,W ;swap STATUS_TEMP register
;into W, sets bank to original
;state
MOVWF
SWAPF
SWAPF
STATUS
;move W into STATUS register
;swap W_TEMP
W_TEMP,F
W_TEMP,W
;swap W_TEMP into W
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 109
PIC16F62X
FIGURE 14-18: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-6)
0
M
U
X
Postscaler
8
1
Watchdog
Timer
•
PS<2:0>
To TMR0 (Figure 6-6)
PSA
8 - to -1 MUX
PSA
WDT
Enable Bit
•
1
0
MUX
WDT
Time-out
Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
TABLE 14-9: SUMMARY OF WATCHDOG TIMER REGISTERS
Value on Value on
POR
Reset
all other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2007h
81h
Config. bits
OPTION
LVP
BOREN
INTEDG
MCLRE
T0CS
FOSC2
T0SE
PWRTE
PSA
WDTE
PS2
FOSC1
PS1
FOSC0
PS0
uuuu uuuu uuuu uuuu
1111 1111 1111 1111
RBPU
Legend: Shaded cells are not used by the Watchdog Timer.
Note: _ = Unimplemented location, read as “0”
+ = Reserved for future use
DS40300B-page 110
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
The first event will cause a device reset. The two latter
events are considered a continuation of program exe-
cution. The TO and PD bits in the STATUS register can
be used to determine the cause of device reset. PD
bit, which is set on power-up is cleared when SLEEP is
invoked. TO bit is cleared if WDT Wake-up occurred.
14.9
Power-Down Mode (SLEEP)
The Power-down mode is entered by executing a
SLEEPinstruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the STATUS register is
cleared, the TO bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before SLEEP was executed (driving high, low, or
hi-impedance).
When the SLEEP instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the correspond-
ing interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEPinstruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have an NOPafter the SLEEPinstruction.
For lowest current consumption in this mode, all I/O
pins should be either at VDD, or VSS, with no external
circuitry drawing current from the I/O pin and the com-
parators and VREF should be disabled. I/O pins that are
hi-impedance inputs should be pulled high or low exter-
nally to avoid switching currents caused by floating
inputs. The T0CKI input should also be at VDD or VSS
for lowest current consumption. The contribution from
on chip pull-ups on PORTB should be considered.
Note: If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wakeup from sleep. The sleep
instruction is completely executed.
The MCLR pin must be at a logic high level (VIHMC).
Note: It should be noted that a RESET generated
by a WDT time-out does not drive MCLR
pin low.
14.9.1 WAKE-UP FROM SLEEP
The WDT is cleared when the device wakes-up from
sleep, regardless of the source of wake-up.
The device can wake-up from SLEEP through one of
the following events:
1. External reset input on MCLR pin
2. Watchdog Timer Wake-up (if WDT was enabled)
3. Interrupt from RB0/INT pin, RB Port change, or
the Peripheral Interrupt (Comparator).
FIGURE 14-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
TOST(2)
INTF flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
Inst(PC - 1)
fetched
Instruction
executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(0004h)
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale). Approximately 1 µs delay will be there for ER osc mode.
3: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 111
PIC16F62X
14.10 Code Protection
FIGURE 14-20: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
CONNECTION
To Normal
Connections
Note: The entire data EEPROM and FLASH
program memory will be erased when the
code protection is turned off. The INTRC
calibration data is not erased.
External
Connector
Signals
PIC16F62X
+5V
0V
VDD
VSS
14.11 ID Locations
VPP
RA5/MCLR/THV
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are
readable and writable during program/verify. Only the
least significant 4 bits of the ID locations are used.
RB6
RB7
CLK
Data I/O
VDD
14.12 In-Circuit Serial Programming
To Normal
Connections
The PIC16F62X microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
14.13 Low Voltage Programming
The LVP bit of the configuration word, enables the low
voltage programming. This mode allows the microcon-
troller to be programmed via ICSP using only a 5V
source. This mode removes the requirement of VIHH to
be placed on the MCLR pin. The LVP bit is normally
erased to ’1’ which enables the low voltage program-
ming. In this mode, the RB4/PGM pin is dedicated to
the programming function and ceases to be a general
purpose I/O pin. The device will enter programming
mode when a ’1’ is placed on the RB4/PGM pin. The
HV programming mode is still available by placing VIHH
on the MCLR pin.
The device is placed into a program/verify mode by
holding the RB6 and RB7 pins low while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). RB6 becomes the programming clock
and RB7 becomes the programming data. Both RB6
and RB7 are Schmitt Trigger inputs in this mode.
After reset, to place the device into programming/verify
mode, the program counter (PC) is at location 00h. A
6-bit command is then supplied to the device.
Depending on the command, 14-bits of program data
are then supplied to or from the device, depending if the
command was a load or a read. For complete details of
serial programming, please refer to the Programming
Specifications.
Note 1: While in this mode the RB4 pin can no
longer be used as a general purpose I/O
pin.
2: VDD must be 5.0V +10% during erase/pro-
gram operations while in low voltage pro-
gramming mode.
A typical in-circuit serial programming connection is
shown in Figure 14-20.
If Low-voltage programming mode is not used, the LVP
bit can be programmed to a ’0’ and RB4/PGM becomes
a digital I/O pin. To program the device, VIHH must be
placed onto MCLR during programming. The LVP bit
may only be programmed when programming is
entered with VIHH on MCLR. The LVP bit cannot be
programmed when programming is entered with
RB4/PGM.
It should be noted, that once the LVP bit is programmed
to 0, only the high voltage programming mode is avail-
able and only high voltage programming mode can be
used to program the device.
DS40300B-page 112
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
The instruction set is highly orthogonal and is grouped
into three basic categories:
15.0 INSTRUCTION SET SUMMARY
Each PIC16F62X instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16F62X instruc-
tion set summary in Table 15-2 lists byte-oriented,
bit-oriented, and literal and control operations.
Table 15-1 shows the opcode field descriptions.
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of an
instruction. In this case, the execution takes two
instruction cycles with the second cycle executed as a
NOP. One instruction cycle consists of four oscillator
periods. Thus, for an oscillator frequency of 4 MHz, the
For byte-oriented instructions, ’f’ represents a file
register designator and ’d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
normal instruction execution time is 1 µs. If
a
The destination designator specifies where the result of
the operation is to be placed. If ’d’ is zero, the result is
placed in the W register. If ’d’ is one, the result is placed
in the file register specified in the instruction.
conditional test is true or the program counter is
changed as a result of an instruction, the instruction
execution time is 2 µs.
Table 15-1 lists the instructions recognized by the
MPASM assembler.
For bit-oriented instructions, ’b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ’f’ represents the number of the
file in which the bit is located.
Figure 15-1 shows the three general formats that the
instructions can have.
For literal and control operations, ’k’ represents an
eight or eleven bit constant or literal value.
Note: To maintain upward compatibility with
future PICmicro® products, do not use the
OPTIONand TRISinstructions.
TABLE 15-1: OPCODE FIELD
DESCRIPTIONS
All examples use the following format to represent a
hexadecimal number:
Field
Description
0xhh
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
where h signifies a hexadecimal digit.
FIGURE 15-1: GENERAL FORMAT FOR
INSTRUCTIONS
Bit address within an 8-bit file register
Literal field, constant data or label
Don’t care location (= 0 or 1)
Byte-oriented file register operations
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
13
8
7
6
0
OPCODE
d
f (FILE #)
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
label Label name
TOS Top of Stack
PC Program Counter
Bit-oriented file register operations
13 10 9
b (BIT #)
7
6
0
OPCODE
f (FILE #)
PCLATH
Program Counter High Latch
GIE Global Interrupt Enable bit
WDT Watchdog Timer/Counter
TO Time-out bit
b = 3-bit bit address
f = 7-bit file register address
PD Power-down bit
Literal and control operations
dest Destination either the W register or the specified
register file location
General
[ ] Options
13
8
7
0
0
Contents
( )
→
OPCODE
k (literal)
Assigned to
k = 8-bit immediate value
Register bit field
In the set of
< >
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
User defined term (font is courier)
italics
k (literal)
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 113
PIC16F62X
TABLE 15-2: PIC16F62X INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
Status
Affected
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d Add W and f
f, d AND W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111 dfff ffff C,DC,Z
1,2
1,2
2
0101 dfff ffff
0001 lfff ffff
0001 0000 0011
1001 dfff ffff
0011 dfff ffff
1011 dfff ffff
1010 dfff ffff
1111 dfff ffff
0100 dfff ffff
1000 dfff ffff
0000 lfff ffff
0000 0xx0 0000
1101 dfff ffff
1100 dfff ffff
Z
Z
Z
Z
Z
f
-
Clear f
Clear W
f, d Complement f
f, d Decrement f
f, d Decrement f, Skip if 0
f, d Increment f
f, d Increment f, Skip if 0
f, d Inclusive OR W with f
f, d Move f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
DECFSZ
INCF
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
1,2
f
-
Move W to f
No Operation
f, d Rotate Left f through Carry
f, d Rotate Right f through Carry
f, d Subtract W from f
f, d Swap nibbles in f
f, d Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
0010 dfff ffff C,DC,Z
1110 dfff ffff
0110 dfff ffff Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b Bit Clear f
f, b Bit Set f
f, b Bit Test f, Skip if Clear
f, b Bit Test f, Skip if Set
1
1
01
01
00bb bfff ffff
01bb bfff ffff
10bb bfff ffff
11bb bfff ffff
1,2
1,2
3
1 (2) 01
1 (2) 01
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x kkkk kkkk C,DC,Z
1001 kkkk kkkk
0kkk kkkk kkkk
Z
0000 0110 0100 TO,PD
1kkk kkkk kkkk
Inclusive OR literal with W
Move literal to W
1000 kkkk kkkk
00xx kkkk kkkk
0000 0000 1001
01xx kkkk kkkk
0000 0000 1000
Z
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
0000 0110 0011 TO,PD
110x kkkk kkkk C,DC,Z
1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS40300B-page 114
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
15.1
Instruction Descriptions
ANDLW
AND Literal with W
ADDLW
Add Literal and W
Syntax:
[ label ] ANDLW
k
Syntax:
[ label ] ADDLW
k
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
(W) + k → (W)
C, DC, Z
(W) .AND. (k) → (W)
Operation:
Z
Status Affected:
Encoding:
11
1001
kkkk
kkkk
11
111x
kkkk
kkkk
The contents of W register are
AND’ed with the eight bit literal 'k'. The
result is placed in the W register.
The contents of the W register are
added to the eight bit literal ’k’ and the
result is placed in the W register.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
ANDLW
0x5F
ADDLW
0x15
Before Instruction
Before Instruction
W
=
0xA3
0x03
W
=
0x10
0x25
After Instruction
After Instruction
W
=
W
=
ADDWF
Syntax:
Add W and f
ANDWF
Syntax:
AND W with f
[ label ] ADDWF f,d
[ label ] ANDWF f,d
Operands:
0 ≤ f ≤ 127
Operands:
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(W) + (f) → (dest)
Operation:
(W) .AND. (f) → (dest)
Status Affected:
Encoding:
C, DC, Z
Status Affected:
Encoding:
Z
00
0111
dfff
ffff
00
0101
dfff
ffff
Add the contents of the W register
with register ’f’. If ’d’ is 0 the result is
stored in the W register. If ’d’ is 1 the
result is stored back in register ’f’.
AND the W register with register 'f'. If
'd' is 0 the result is stored in the W
register. If 'd' is 1 the result is stored
back in register 'f'.
Description:
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
ADDWF
FSR,
0
ANDWF
FSR, 1
Before Instruction
Before Instruction
W
FSR =
=
0x17
0xC2
W
FSR =
=
0x17
0xC2
After Instruction
After Instruction
W
FSR =
=
0xD9
0xC2
W
FSR =
=
0x17
0x02
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 115
PIC16F62X
BCF
Bit Clear f
BTFSC
Bit Test, Skip if Clear
Syntax:
Operands:
[ label ] BCF f,b
Syntax:
[ label ] BTFSC f,b
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
Status Affected:
Encoding:
Description:
Words:
0 → (f<b>)
Operation:
skip if (f<b>) = 0
None
None
Status Affected:
Encoding:
01
00bb
bfff
ffff
01
10bb
bfff
ffff
If bit ’b’ in register ’f’ is ’0’ then the next
instruction is skipped.
Bit ’b’ in register ’f’ is cleared.
Description:
1
1
If bit ’b’ is ’0’ then the next instruction
fetched during the current instruction
execution is discarded, and a NOPis
executed instead, making this a
two-cycle instruction.
Cycles:
BCF
FLAG_REG, 7
Example
Before Instruction
FLAG_REG = 0xC7
After Instruction
Words:
Cycles:
Example
1
1(2)
FLAG_REG = 0x47
HERE
FALSE
TRUE
BTFSC FLAG,1
GOTO
PROCESS_CODE
•
•
•
Before Instruction
PC
=
address HERE
After Instruction
if FLAG<1> = 0,
PC =
address TRUE
if FLAG<1>=1,
PC =
address FALSE
BSF
Bit Set f
Syntax:
Operands:
[ label ] BSF f,b
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
Status Affected:
Encoding:
Description:
Words:
1 → (f<b>)
None
01
01bb
bfff
ffff
Bit ’b’ in register ’f’ is set.
1
1
Cycles:
BSF
FLAG_REG,
7
Example
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
DS40300B-page 116
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CLRF
f
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
0 ≤ f ≤ 127
00h → (f)
1 → Z
Operation:
skip if (f<b>) = 1
None
Status Affected:
Encoding:
Status Affected:
Encoding:
Z
01
11bb
bfff
ffff
00
0001
1fff
ffff
If bit ’b’ in register ’f’ is ’1’ then the next
instruction is skipped.
If bit ’b’ is ’1’, then the next instruction
fetched during the current instruction
execution, is discarded and a NOPis
executed instead, making this a
two-cycle instruction.
The contents of register ’f’ are cleared
and the Z bit is set.
Description:
Description:
Words:
Cycles:
Example
1
1
CLRF
FLAG_REG
Words:
Cycles:
Example
1
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
Z
1(2)
=
0x5A
HERE
FALSE
TRUE
BTFSS FLAG,1
=
=
0x00
1
GOTO
PROCESS_CODE
•
•
•
Before Instruction
PC
=
address HERE
After Instruction
if FLAG<1> = 0,
PC =
address FALSE
if FLAG<1> = 1,
PC =
address TRUE
CALL
Call Subroutine
[ label ] CALL k
0 ≤ k ≤ 2047
CLRW
Clear W
Syntax:
Syntax:
[ label ] CLRW
None
Operands:
Operation:
Operands:
Operation:
(PC)+ 1→ TOS,
k → PC<10:0>,
00h → (W)
1 → Z
(PCLATH<4:3>) → PC<12:11>
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
None
00
0001
0000
0011
10
0kkk
kkkk
kkkk
W register is cleared. Zero bit (Z) is
set.
Description:
Call Subroutine. First, return address
(PC+1) is pushed onto the stack. The
eleven bit immediate address is loaded
into PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALLis a two-cycle instruction.
Description:
Words:
Cycles:
Example
1
1
CLRW
Words:
Cycles:
Example
1
2
Before Instruction
W
=
0x5A
After Instruction
HERE
CALL THERE
W
=
0x00
1
Before Instruction
Z
=
PC
=
Address HERE
After Instruction
PC
= Address THERE
TOS = Address HERE+1
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 117
PIC16F62X
CLRWDT
Syntax:
Clear Watchdog Timer
DECF
Decrement f
[ label ] DECF f,d
0 ≤ f ≤ 127
[ label ] CLRWDT
None
Syntax:
Operands:
Operands:
Operation:
d
[0,1]
00h → WDT
0 → WDT prescaler,
1 → TO
Operation:
(f) - 1 → (dest)
Status Affected:
Encoding:
Z
1 → PD
00
0011
dfff
ffff
Status Affected:
Encoding:
TO, PD
Decrement register ’f’. If ’d’ is 0 the
result is stored in the W register. If ’d’
is 1 the result is stored back in register
’f’.
Description:
00
0000
0110
0100
CLRWDTinstruction resets the
Description:
Watchdog Timer. It also resets the
prescaler of the WDT. Status bits TO
and PD are set.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
DECF
CNT, 1
1
Before Instruction
CLRWDT
CNT
Z
=
=
0x01
0
Before Instruction
After Instruction
WDT counter
After Instruction
=
=
?
CNT
Z
=
=
0x00
1
WDT counter
0x00
WDT prescaler=
0
1
1
TO
PD
=
=
COMF
Complement f
[ label ] COMF f,d
0 ≤ f ≤ 127
DECFSZ
Syntax:
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0 ≤ f ≤ 127
Syntax:
Operands:
Operands:
d
[0,1]
d
[0,1]
Operation:
(f) → (dest)
Operation:
(f) - 1 → (dest); skip if result = 0
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
None
00
1001
dfff
ffff
00
1011
dfff
ffff
The contents of register ’f’ are
The contents of register ’f’ are
Description:
Description:
decremented. If ’d’ is 0 the result is
placed in the W register. If ’d’ is 1 the
result is placed back in register ’f’.
If the result is 0, the next instruction,
which is already fetched, is discarded. A
NOPis executed instead making it a
two-cycle instruction.
complemented. If ’d’ is 0 the result is
stored in W. If ’d’ is 1 the result is
stored back in register ’f’.
Words:
Cycles:
Example
1
1
COMF
REG1,0
Words:
Cycles:
Example
1
Before Instruction
1(2)
REG1
After Instruction
REG1
=
0x13
HERE
DECFSZ
GOTO
CNT, 1
LOOP
=
=
0x13
0xEC
CONTINUE •
W
•
•
Before Instruction
PC
=
address HERE
After Instruction
CNT
if CNT =
PC
if CNT ≠
PC
=
CNT - 1
0,
address CONTINUE
0,
address HERE+1
=
=
DS40300B-page 118
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
GOTO
Unconditional Branch
[ label ] GOTO k
0 ≤ k ≤ 2047
INCFSZ
Syntax:
Increment f, Skip if 0
Syntax:
[ label ] INCFSZ f,d
Operands:
Operation:
Operands:
0 ≤ f ≤ 127
d
[0,1]
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Operation:
(f) + 1 → (dest), skip if result = 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
10
1kkk
kkkk
kkkk
00
1111
dfff
ffff
GOTOis an unconditional branch. The
eleven bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTOis a two-cycle instruction.
The contents of register ’f’ are
Description:
Description:
incremented. If ’d’ is 0 the result is
placed in the W register. If ’d’ is 1 the
result is placed back in register ’f’.
If the result is 0, the next instruction,
which is already fetched, is discarded.
A NOPis executed instead making it a
two-cycle instruction.
Words:
Cycles:
Example
1
2
Words:
Cycles:
Example
1
GOTO THERE
1(2)
After Instruction
HERE
INCFSZ
GOTO
CNT,
LOOP
1
PC
=
Address THERE
CONTINUE •
•
•
Before Instruction
PC
=
address HERE
After Instruction
CNT
=
CNT + 1
if CNT=
0,
PC
if CNT≠
=
address CONTINUE
0,
PC
=
address HERE +1
INCF
Increment f
IORLW
Inclusive OR Literal with W
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
Operands:
[ label ] INCF f,d
Syntax:
0 ≤ f ≤ 127
Operands:
Operation:
Status Affected:
Encoding:
Description:
d
[0,1]
(W) .OR. k → (W)
Z
Operation:
(f) + 1 → (dest)
Status Affected:
Encoding:
Z
11
1000
kkkk
kkkk
00
1010
dfff
ffff
The contents of the W register is
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
The contents of register ’f’ are
Description:
incremented. If ’d’ is 0 the result is
placed in the W register. If ’d’ is 1 the
result is placed back in register ’f’.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
IORLW
0x35
Before Instruction
INCF
CNT, 1
W
=
0x9A
Before Instruction
After Instruction
CNT
Z
=
=
0xFF
0
W
=
0xBF
1
Z
=
After Instruction
CNT
Z
=
=
0x00
1
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 119
PIC16F62X
IORWF
Inclusive OR W with f
MOVF
Move f
Syntax:
[ label ] IORWF f,d
Syntax:
Operands:
[ label ] MOVF f,d
Operands:
0 ≤ f ≤ 127
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(W) .OR. (f) → (dest)
Operation:
(f) → (dest)
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
Z
00
0100
dfff
ffff
00
1000
dfff
ffff
Inclusive OR the W register with
register ’f’. If ’d’ is 0 the result is placed
in the W register. If ’d’ is 1 the result is
placed back in register ’f’.
The contents of register f is moved to
a destination dependent upon the
status of d. If d = 0, destination is W
register. If d = 1, the destination is file
register f itself. d = 1 is useful to test a
file register since status flag Z is
affected.
Description:
Description:
Words:
Cycles:
Example
1
1
IORWF
RESULT, 0
Words:
Cycles:
Example
1
1
Before Instruction
RESULT =
0x13
0x91
MOVF
FSR, 0
W
=
After Instruction
After Instruction
RESULT =
W
Z
0x13
0x93
1
W = value in FSR register
=
=
Z
= 1
MOVLW
Move Literal to W
[ label ] MOVLW k
0 ≤ k ≤ 255
MOVWF
Move W to f
[ label ] MOVWF
0 ≤ f ≤ 127
(W) → (f)
Syntax:
Syntax:
f
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
Operation:
Status Affected:
Encoding:
Description:
k → (W)
None
None
11
00xx
kkkk
kkkk
00
0000
1fff
ffff
The eight bit literal ’k’ is loaded into W
register. The don’t cares will assemble
as 0’s.
Move data from W register to register
'f'.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
MOVWF
OPTION
MOVLW
0x5A
Before Instruction
After Instruction
OPTION =
0xFF
0x4F
W
=
0x5A
W
=
After Instruction
OPTION =
0x4F
0x4F
W
=
DS40300B-page 120
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
NOP
No Operation
[ label ] NOP
None
RETFIE
Return from Interrupt
Syntax:
Syntax:
[ label ] RETFIE
None
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Operands:
Operation:
No operation
None
TOS → PC,
1 → GIE
Status Affected:
Encoding:
None
00
0000
0xx0
0000
00
0000
0000
1001
No operation.
Return from Interrupt. Stack is POPed
and Top of Stack (TOS) is loaded in
the PC. Interrupts are enabled by
setting Global Interrupt Enable bit,
GIE (INTCON<7>). This is a two-cycle
instruction.
Description:
1
Cycles:
1
NOP
Example
Words:
Cycles:
Example
1
2
RETFIE
After Interrupt
PC
GIE =
=
TOS
1
RETLW
Return with Literal in W
[ label ] RETLW k
0 ≤ k ≤ 255
OPTION
Syntax:
Load Option Register
[ label ] OPTION
None
Syntax:
Operands:
Operation:
Operands:
Operation:
(W) → OPTION
k → (W);
TOS → PC
Status Affected: None
00
0000
0110
0010
Encoding:
Status Affected:
Encoding:
None
The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code
compatibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly
address it.
Description:
11
01xx
kkkk
kkkk
The W register is loaded with the eight
bit literal ’k’. The program counter is
loaded from the top of the stack (the
return address). This is a two-cycle
instruction.
Description:
Words:
Cycles:
Example
1
2
Words:
Cycles:
Example
1
1
CALL TABLE
;W contains table
;offset value
•
;W now has table
To maintain upward compatibility
value
®
with future PICmicro products, do
•
•
TABLE
not use this instruction.
ADDWF PC
RETLW k1
RETLW k2
•
;W = offset
;Begin table
;
•
•
RETLW kn
; End of table
Before Instruction
W
=
0x07
After Instruction
W
=
value of k8
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 121
PIC16F62X
RETURN
Return from Subroutine
RRF
Rotate Right f through Carry
[ label ] RRF f,d
0 ≤ f ≤ 127
Syntax:
[ label ] RETURN
None
Syntax:
Operands:
Operands:
Operation:
Status Affected:
Encoding:
Description:
d
[0,1]
TOS → PC
None
Operation:
See description below
C
Status Affected:
Encoding:
00
0000
0000
1000
00
1100
dfff
ffff
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a two cycle instruction.
The contents of register ’f’ are rotated
one bit to the right through the Carry
Flag. If ’d’ is 0 the result is placed in
the W register. If ’d’ is 1 the result is
placed back in register ’f’.
Description:
Words:
Cycles:
Example
1
2
C
Register f
RETURN
After Interrupt
Words:
Cycles:
Example
1
1
PC
=
TOS
RRF
REG1,0
Before Instruction
REG1
C
=
=
1110 0110
0
After Instruction
REG1
W
C
=
=
=
1110 0110
0111 0011
0
RLF
Rotate Left f through Carry
SLEEP
Syntax:
Operands:
[ label ]
RLF f,d
Syntax:
[ label ] SLEEP
None
0 ≤ f ≤ 127
Operands:
Operation:
d
[0,1]
00h → WDT,
0 → WDT prescaler,
1 → TO,
Operation:
See description below
C
Status Affected:
Encoding:
0 → PD
00
1101
dfff
ffff
Status Affected:
Encoding:
TO, PD
The contents of register ’f’ are rotated
one bit to the left through the Carry
Flag. If ’d’ is 0 the result is placed in
the W register. If ’d’ is 1 the result is
stored back in register ’f’.
Description:
00
0000
0110
0011
The power-down status bit, PD is
cleared. Time-out status bit, TO is
set. Watchdog Timer and its
Description:
C
Register f
prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
See Section 14.9 for more details.
Words:
Cycles:
Example
1
1
Words:
1
RLF
REG1,0
Cycles:
Example:
1
Before Instruction
SLEEP
REG1
=
=
1110 0110
0
C
After Instruction
REG1
W
C
=
=
=
1110 0110
1100 1100
1
DS40300B-page 122
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
SUBLW
Subtract W from Literal
SUBWF
Syntax:
Subtract W from f
Syntax:
[ label ]
SUBLW k
[ label ]
SUBWF f,d
Operands:
Operation:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
d
[0,1]
k - (W) → (W)
Operation:
(f) - (W) → (dest)
Status
C, DC, Z
Affected:
Status
C, DC, Z
Affected:
Encoding:
11
110x
kkkk
kkkk
Encoding:
00
0010
dfff
ffff
The W register is subtracted (2’s com-
plement method) from the eight bit literal
'k'. The result is placed in the W register.
Description:
Subtract (2’s complement method)
Description:
W register from register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is 1
the result is stored back in register 'f'.
Words:
1
1
Cycles:
Words:
1
1
Example 1:
SUBLW
0x02
Cycles:
Before Instruction
Example 1:
SUBWF
REG1,1
W
C
=
=
1
?
Before Instruction
REG1
W
C
=
=
=
3
2
?
After Instruction
W
C
=
=
1
1; result is positive
After Instruction
Example 2:
Example 3:
Before Instruction
REG1
W
C
=
=
=
1
2
W
C
=
=
2
?
1; result is positive
After Instruction
Example 2:
Before Instruction
W
C
=
=
0
REG1
W
=
=
=
2
2
?
1; result is zero
C
Before Instruction
After Instruction
W
C
=
=
3
?
REG1
W
C
=
=
=
0
2
After Instruction
1; result is zero
W
C
=
=
0xFF
0; result is nega-
Example 3:
Before Instruction
tive
REG1
W
C
=
=
=
1
2
?
After Instruction
REG1
W
C
=
=
=
0xFF
2
0; result is negative
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 123
PIC16F62X
SWAPF
Syntax:
Swap Nibbles in f
XORLW
Exclusive OR Literal with W
[ label ] SWAPF f,d
Syntax:
[ label ] XORLW k
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
Operands:
Operation:
Status Affected:
Encoding:
d
[0,1]
(W) .XOR. k → (W)
Z
Operation:
(f<3:0>) → (dest<7:4>),
(f<7:4>) → (dest<3:0>)
11
1010 kkkk kkkk
Status Affected:
Encoding:
None
The contents of the W register are
XOR’ed with the eight bit literal 'k'.
The result is placed in the
W register.
Description:
00
1110
dfff
ffff
The upper and lower nibbles of
Description:
register ’f’ are exchanged. If ’d’ is 0
the result is placed in W register. If ’d’
is 1 the result is placed in register ’f’.
Words:
1
Cycles:
Example:
1
Words:
Cycles:
Example
1
1
XORLW 0xAF
Before Instruction
SWAPF REG,
0
W
=
0xB5
0x1A
Before Instruction
REG1
After Instruction
=
0xA5
W
=
After Instruction
REG1
W
=
=
0xA5
0x5A
TRIS
Load TRIS Register
XORWF
Syntax:
Exclusive OR W with f
[ label ] XORWF f,d
0 ≤ f ≤ 127
Syntax:
[ label ] TRIS
f
Operands:
Operation:
5 ≤ f ≤ 7
Operands:
d
[0,1]
(W) → TRIS register f;
Status Affected: None
Operation:
(W) .XOR. (f) → (dest)
00
Encoding:
0000 0110
0fff
Status Affected:
Encoding:
Z
The instruction is supported for code
compatibility with the PIC16C5X
products. Since TRIS registers are
readable and writable, the user can
directly address them.
Description:
00
0110
dfff
ffff
Exclusive OR the contents of the
W register with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd'
is 1 the result is stored back in register
'f'.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
To maintain upward compatibility
REG
1
XORWF
®
with future PICmicro products, do
Before Instruction
not use this instruction.
REG
W
=
=
0xAF
0xB5
After Instruction
REG
W
=
=
0x1A
0xB5
DS40300B-page 124
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
MPLAB allows you to:
16.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Integrated Development Environment
- MPLAB™ IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASM Assembler
- absolute listing file
- object code
- MPLAB-C17 and MPLAB-C18 C Compilers
- MPLINK/MPLIB Linker/Librarian
• Simulators
The ability to use MPLAB with Microchip’s simulator,
MPLAB-SIM, allows a consistent platform and the abil-
ity to easily switch from the cost-effective simulator to
the full featured emulator with minimal retraining.
- MPLAB-SIM Software Simulator
• Emulators
- MPLAB-ICE Real-Time In-Circuit Emulator
- PICMASTER®/PICMASTER-CE In-Circuit
16.2
MPASM Assembler
Emulator
MPASM is a full featured universal macro assembler for
all PICmicro MCU’s. It can produce absolute code
directly in the form of HEX files for device program-
mers, or it can generate relocatable objects for
MPLINK.
- ICEPIC™
• In-Circuit Debugger
- MPLAB-ICD for PIC16F877
• Device Programmers
MPASM has a command line interface and a Windows
shell and can be used as a standalone application on a
Windows 3.x or greater system. MPASM generates
relocatable object files, Intel standard HEX files, MAP
files to detail memory usage and symbol reference, an
absolute LST file which contains source lines and gen-
erated machine code, and a COD file for MPLAB
debugging.
- PRO MATE II Universal Programmer
- PICSTART Plus Entry-Level Prototype
Programmer
• Low-Cost Demonstration Boards
- SIMICE
- PICDEM-1
- PICDEM-2
- PICDEM-3
MPASM features include:
- PICDEM-17
- SEEVAL
• MPASM and MPLINK are integrated into MPLAB
projects.
- KEELOQ
• MPASM allows user defined macros to be created
for streamlined assembly.
16.1
MPLAB Integrated Development
Environment Software
• MPASM allows conditional assembly for multi pur-
pose source files.
• MPASM directives allow complete control over the
assembly process.
- The MPLAB IDE software brings an ease of
software development previously unseen in
the 8-bit microcontroller market. MPLAB is a
Windows -based application which contains:
16.3
MPLAB-C17 and MPLAB-C18
C Compilers
• Multiple functionality
- editor
The MPLAB-C17 and MPLAB-C18 Code Development
Systems are complete ANSI ‘C’ compilers and inte-
grated development environments for Microchip’s
PIC17CXXX and PIC18CXXX family of microcontrol-
lers, respectively. These compilers provide powerful
integration capabilities and ease of use not found with
other compilers.
- simulator
- programmer (sold separately)
- emulator (sold separately)
• A full featured editor
• A project manager
• Customizable tool bar and key mapping
• A status bar
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• On-line help
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 125
PIC16F62X
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different pro-
cessors. The universal architecture of the MPLAB-ICE
allows expansion to support new PICmicro microcon-
trollers.
16.4
MPLINK/MPLIB Linker/Librarian
MPLINK is a relocatable linker for MPASM and
MPLAB-C17 and MPLAB-C18. It can link relocatable
objects from assembly or C source files along with pre-
compiled libraries using directives from a linker script.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced fea-
tures that are generally found on more expensive devel-
opment tools. The PC platform and Microsoft® Windows
3.x/95/98 environment were chosen to best make these
features available to you, the end user.
MPLIB is a librarian for pre-compiled code to be used
with MPLINK. When a routine from a library is called
from another source file, only the modules that contains
that routine will be linked in with the application. This
allows large libraries to be used efficiently in many dif-
ferent applications. MPLIB manages the creation and
modification of library files.
MPLAB-ICE 2000 is a full-featured emulator system
with enhanced trace, trigger, and data monitoring fea-
tures. Both systems use the same processor modules
and will operate across the full operating speed range
of the PICmicro MCU.
MPLINK features include:
• MPLINK works with MPASM and MPLAB-C17
and MPLAB-C18.
• MPLINK allows all memory areas to be defined as
sections to provide link-time flexibility.
16.7
PICMASTER/PICMASTER CE
The PICMASTER system from Microchip Technology is
a full-featured, professional quality emulator system.
This flexible in-circuit emulator provides a high-quality,
universal platform for emulating Microchip 8-bit
PICmicro microcontrollers (MCUs). PICMASTER sys-
tems are sold worldwide, with a CE compliant model
available for European Union (EU) countries.
MPLIB features include:
• MPLIB makes linking easier because single librar-
ies can be included instead of many smaller files.
• MPLIB helps keep code maintainable by grouping
related modules together.
• MPLIB commands allow libraries to be created
and modules to be added, listed, replaced,
deleted, or extracted.
16.8
ICEPIC
ICEPIC is a low-cost in-circuit emulation solution for the
Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X, and PIC16CXXX families of 8-bit one-time-
programmable (OTP) microcontrollers. The modular
system can support different subsets of PIC16C5X or
PIC16CXXX products through the use of
interchangeable personality modules or daughter
boards. The emulator is capable of emulating without
target application circuitry being present.
16.5
MPLAB-SIM Software Simulator
The MPLAB-SIM Software Simulator allows code
development in a PC host environment by simulating
the PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file or user-defined key press to any of the pins. The
execution can be performed in single step, execute until
break, or trace mode.
16.9
MPLAB-ICD In-Circuit Debugger
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPLAB-C18 and MPASM. The Soft-
ware Simulator offers the flexibility to develop and
debug code outside of the laboratory environment mak-
ing it an excellent multi-project software development
tool.
Microchip’s In-Circuit Debugger, MPLAB-ICD, is a pow-
erful, low-cost run-time development tool. This tool is
based on the flash PIC16F877 and can be used to
develop for this and other PICmicro microcontrollers
from the PIC16CXXX family. MPLAB-ICD utilizes the
In-Circuit Debugging capability built into the
PIC16F87X. This feature, along with Microchip’s In-Cir-
cuit Serial Programming protocol, offers cost-effective
in-circuit flash programming and debugging from the
graphical user interface of the MPLAB Integrated
Development Environment. This enables a designer to
develop and debug source code by watching variables,
single-stepping and setting break points. Running at
full speed enables testing hardware in real-time. The
MPLAB-ICD is also a programmer for the flash
PIC16F87X family.
16.6
MPLAB-ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers (MCUs). Software control of
MPLAB-ICE is provided by the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
DS40300B-page 126
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and download the
firmware to the emulator for testing. Additional proto-
type area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
16.10 PRO MATE II Universal Programmer
The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for instructions and error messages,
keys to enter commands and a modular detachable
socket assembly to support various package types. In
stand-alone mode the PRO MATE II can read, verify or
program PICmicro devices. It can also set code-protect
bits in this mode.
16.14 PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-Plus, and easily test firmware.
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connec-
tion to an LCD module and a keypad.
16.11 PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient.
PICSTART Plus supports all PICmicro devices with up
to 40 pins. Larger pin count devices such as the
PIC16C92X, and PIC17C76X may be supported with
an adapter socket. PICSTART Plus is CE compliant.
16.12 SIMICE Entry-Level
Hardware Simulator
SIMICE is an entry-level hardware development sys-
tem designed to operate in a PC-based environment
with Microchip’s simulator MPLAB-SIM. Both SIMICE
and MPLAB-SIM run under Microchip Technology’s
MPLAB Integrated Development Environment (IDE)
software. Specifically, SIMICE provides hardware sim-
ulation for Microchip’s PIC12C5XX, PIC12CE5XX, and
PIC16C5X families of PICmicro 8-bit microcontrollers.
SIMICE works in conjunction with MPLAB-SIM to pro-
vide non-real-time I/O port emulation. SIMICE enables
a developer to run simulator code for driving the target
system. In addition, the target system can provide input
to the simulator code. This capability allows for simple
and interactive debugging without having to manually
generate MPLAB-SIM stimulus files. SIMICE is a valu-
able debugging tool for entry-level system develop-
ment.
16.15 PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an addi-
tional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
16.13
PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 127
PIC16F62X
16.16 PICDEM-17
The PICDEM-17 is an evaluation board that demon-
strates the capabilities of several Microchip microcon-
trollers,
including
PIC17C752,
PIC17C756,
PIC17C762, and PIC17C766. All necessary hardware
is included to run basic demo programs, which are sup-
plied on a 3.5-inch disk. A programmed sample is
included, and the user may erase it and program it with
the other sample programs using the PRO MATE II or
PICSTART Plus device programmers and easily debug
and test the sample code. In addition, PICDEM-17 sup-
ports down-loading of programs to and executing out of
external FLASH memory on board. The PICDEM-17 is
also usable with the MPLAB-ICE or PICMASTER emu-
lator, and all of the sample programs can be run and
modified using either emulator. Additionally, a gener-
ous prototype area is available for user hardware.
16.17 SEEVAL Evaluation and Programming
System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in trade-
off analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
16.18
KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS eval-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
DS40300B-page 128
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
TABLE 16-1: DEVELOPMENT TOOLS FROM MICROCHIP
5 1 2 0 P M C
X X R X F C M
X X
H C S X
X X C 9 3
/ X X C 2 5
/ X X C 2 4
X X C 8 2 C 1 P I
X X 7 C 7 C 1 P I
X 4 C 7 C 1 P I
X X 9 C 6 C 1 P I
X 8 X 1 6 C I F P
X 8 C 6 C 1 P I
X X 7 C 6 C 1 P I
X 7 C 6 C 1 P I
X 6 2 6 1 F C I P
X X C 6 X C 1 P I
X 6 C 6 C 1 P I
X 5 C 6 C 1 P I
0 0 4 0 1 C I P
X X C 2 X C 1 P I
s l o o e T a r f t o w S s r o t a u l E m e r g g b e u D s m e a r m o g P r r
t i s K v a E l d a n d s a r o B o m e D
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 129
PIC16F62X
NOTES:
DS40300B-page 130
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
17.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings †
Ambient temperature under bias.................................................................................................................-40 to +125°C
Storage temperature.............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ........................................................................................................... -0.3 to +6.5V
Voltage on MCLR and RA4 with respect to VSS ..........................................................................................-0.3 to +14V
Voltage on all other pins with respect to VSS ....................................................................................-0.3V to VDD + 0.3V
Total power dissipation (Note 1)...........................................................................................................................800 mW
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... ± 20 mA
Output clamp current, IOK (Vo < 0 or Vo >VDD)............................................................................................................... ± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA and PORTB....................................................................................................200 mA
Maximum current sourced by PORTA and PORTB ..............................................................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
† NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a "low" level to the MCLR pin rather
than pulling this pin directly to VSS.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 131
PIC16F62X
FIGURE 17-1: PIC16F62X VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +70°C
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 17-2: PIC16F62X VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA < 0°C, +70°C < TA ≤ 85°C
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
DS40300B-page 132
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
FIGURE 17-3: PIC16LF62X VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +70°C
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
20
0
4
10
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 17-4: PIC16LF62X VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA < 0°C, +70°C < TA ≤ 85°C
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 133
PIC16F62X
17.1
DC CHARACTERISTICS:
PIC16F62X-04 (Commercial, Industrial, Extended)
PIC16F62X-20 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature –40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial and
–40°C ≤ TA ≤ +125°C for extended
Param Sym
No.
Characteristic
Min Typ† Max Units
Conditions
D001
D002
VDD
VDR
Supply Voltage
3.0
-
5.5
V
RAM Data Retention
Voltage (Note 1)
–
1.5*
–
V
Device in SLEEP mode
See section on power-on reset for details
D003
D004
D005
VPOR
SVDD
VBOD
IDD
VDD start voltage to
ensure Power-on Reset
–
Vss
–
–
–
V
VDD rise rate to ensure
Power-on Reset
0.05*
V/ms See section on power-on reset for details
Brown-out Detect Voltage
3.7
3.7
4.0
4.0
4.3
4.4
V
BODEN configuration bit is cleared
(Extended)
D010
D013
Supply Current (Note 2, 5)
–
–
0.7
mA FOSC = 4.0 MHZ, VDD = 3.0
–
–
–
4.0
–
–
7.0
6.0
2.0
mA FOSC = 20.0 MHz, VDD = 5.5
mA FOSC = 20.0 MHz, VDD = 4.5
mA FOSC = 10.0 MHz, VDD = 3.0
D020
IPD
Power Down Current (Note 3)
–
–
–
–
–
–
–
–
2.2
5.0
9.0
µA
µA
µA
µA
VDD = 3.0
VDD = 4.5
VDD = 5.5
VDD = 5.5 Extended
15.0
∆IWDT
∆IBOD
WDT Current (Note 4)
–
6.0
20
25
125
50
µA
µA
µA
µA
VDD=4.0V
(125°C)
BOD enabled, VDD = 5.0V
VDD = 4.0V
D023
1A
Brown-out Detect Current (Note 4)
∆ICOMP Comparator Current for each
Comparator (Note 4)
–
–
75
30
∆IVREF VREF Current (Note 4)
–
135
µA
VDD = 4.0V
FOSC
LP Oscillator Operating Frequency
INTRC Oscillator Operating Frequency
XT Oscillator Operating Frequency
HS Oscillator Operating Frequency
0
–
0
0
–
–
–
–
200
4
4
KHz All temperatures
MHz All temperatures
MHz All temperatures
MHz All temperatures
20
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-
sumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with
the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the
base IDD or IPD measurement.
5: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the
formula Ir = VDD/2Rext (mA) with Rext in kΩ.
DS40300B-page 134
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
17.2
DC CHARACTERISTICS:
PIC16LF62X-04 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature –40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial and
–40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC spec Table 17.1 and Table 12-2
Param Sym
No.
Characteristic Min Typ† Max Units Conditions
D001
D002
VDD
VDR
Supply Voltage
2.0
-
5.5
V
RAM Data Retention
Voltage (Note 1)
–
1.5*
–
V
Device in SLEEP mode
D003
D004
VPOR
SVDD
VDD start voltage to
ensure Power-on Reset
–
VSS
–
–
V
See section on Power-on Reset for
details
VDD rise rate to ensure
Power-on Reset
0.05*
–
V/ms See section on Power-on Reset for
details
D005
D010
VBOD
IDD
Brown-out Detect Voltage
Supply Current (Note 2, 5)
3.7
–
4.0
–
4.3
0.6
V
BODEN configuration bit is cleared
mA FOSC = 4.0 MHZ, VDD = 2.5
D013
–
–
–
4.0
–
–
7.0
6.0
2.0
mA FOSC = 20.0 MHz, VDD = 5.5
mA FOSC = 20.0 MHz, VDD = 4.5
mA FOSC = 10.0 MHz, VDD = 3.0
D020
IPD
Power Down Current (Note 2)
–
–
–
–
–
–
–
–
2.0
2.2
5.0
9.0
15.0
µA
µA
µA
µA
µA
VDD = 2.5
VDD = 3.0
VDD = 4.5
VDD = 5.5
VDD = 5.5 Extended
∆IWDT
∆IBOD
∆ICOMP
WDT Current (Note 4)
–
–
6.0
75
15
125
µA
µA
VDD=3.0V
BOD enabled, VDD = 5.0V
D023
1A
Brown-out Detect Current (Note 4)
Comparator Current for each
Comparator (Note 4)
–
–
30
50
135
µA
µA
VDD = 3.0V
VDD = 3.0V
∆IVREF
FOSC
VREF Current (Note 4)
LP Oscillator Operating Frequency
INTRC Oscillator Operating Frequency
XT Oscillator Operating Frequency
HS Oscillator Operating Frequency
0
–
0
0
–
–
–
–
200
4
4
KHz All temperatures
MHz All temperatures
MHz All temperatures
MHz All temperatures
20
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consump-
tion.
The test conditions for all IDD measurements in active operation mode are:
OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the
part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD to VSS.
4: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base
IDD or IPD measurement.
5: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the for-
mula Ir = VDD/2Rext (mA) with Rext in kΩ.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 135
PIC16F62X
17.3 DC CHARACTERISTICS: PIC16F62X (Commercial, Industrial, Extended)
PIC16LF62X (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
–40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial and
–40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC spec Table 17.1 and Table 12-2
Param. Sym
No.
Characteristic
Min
Typ†
Max
Unit
Conditions
VIL
Input Low Voltage
I/O ports
with TTL buffer
D030
VSS
-
-
0.8V
V
VDD = 4.5V to 5.5V
otherwise
0.15VDD
0.2VDD
0.2VDD
D031
D032
with Schmitt Trigger input
MCLR, RA4/T0CKI,OSC1 (in ER
mode)
VSS
Vss
V
V
Note1
D033
OSC1 (in XT and HS)
OSC1 (in LP)
Vss
Vss
-
-
0.3VDD
V
V
0.6VDD-1.0
VIH Input High Voltage
I/O ports
-
-
D040
with TTL buffer
2.0V
.25VDD + 0.8V
0.8VDD
VDD
VDD
VDD
V
VDD = 4.5V to 5.5V
otherwise
D041
D042
D043
D043A
D070
with Schmitt Trigger input
MCLR RA4/T0CKI
OSC1 (XT, HS and LP)
OSC1 (in ER mode)
0.8VDD
0.7VDD
0.9VDD
-
-
VDD
VDD
V
V
Note1
IPURB PORTB weak pull-up current
Input Leakage Current
50
200
400
µA VDD = 5.0V, VPIN = VSS
IIL
(Notes 2, 3)
I/O ports (Except PORTA)
PORTA
±1.0
±0.5
±1.0
±5.0
µA VSS ≤ VPIN ≤ VDD, pin at hi-impedance
µA Vss ≤ VPIN ≤ VDD, pin at hi-impedance
D060
D061
D063
-
-
-
-
-
-
RA4/T0CKI
µA Vss ≤ VPIN ≤ VDD
OSC1, MCLR
µA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc
configuration
VOL Output Low Voltage
D080
D083
I/O ports
-
-
-
-
-
-
-
-
0.6
0.6
0.6
0.6
V
V
V
V
IOL=8.5 mA, VDD=4.5V, -40° to +85°C
IOL=7.0 mA, VDD=4.5V, +125°C
IOL=1.6 mA, VDD=4.5V, -40° to +85°C
IOL=1.2 mA, VDD=4.5V, +125°C
OSC2/CLKOUT (ER only)
VOH Output High Voltage (Note 3)
D090
D092
*D150
I/O ports (Except RA4)
VDD-0.7
VDD-0.7
VDD-0.7
VDD-0.7
-
-
-
-
-
-
V
V
V
V
V
IOH=-3.0 mA, VDD=4.5V, -40° to +85°C
IOH=-2.5 mA, VDD=4.5V, +125°C
IOH=-1.3 mA, VDD=4.5V, -40° to +85°C
IOH=-1.0 mA, VDD=4.5V, +125°C
RA4 pin PIC16F62X, PIC16LF62X
-
OSC2/CLKOUT (ER only)
-
-
VOD Open-Drain High Voltage
Capacitive Loading Specs on
Output Pins
8.5*
D100
COSC2 OSC2 pin
-
-
15
50
pF In XT, HS and LP modes when external
clock used to drive OSC1.
pF
D101
Cio All I/O pins/OSC2 (in ER mode)
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In ER oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16F62X be driven with
external clock in ER mode.
2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operat-
ing conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
DS40300B-page 136
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
TABLE 17-1: COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD <5.5V, -40°C < TA < +125°C, unless otherwise stated.
Param
No.
Characteristics
Sym
Min
Typ
Max
± 10
Units
mV
Comments
D300
Input offset voltage
Input common mode voltage*
VIOFF
VICM
-
± 5.0
D301
D302
0
55
-
-
VDD - 1.5
V
Common Mode Rejection Ratio* CMRR
-
-
db
Response Time(1)*
300
300A
TRESP
150
400
600
ns
ns
16F62X
16LF62X
301
Comparator Mode Change to
Output Valid*
TMC2OV
-
-
10
µs
* These parameters are characterized but not tested.
Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from VSS to VDD.
TABLE 17-2: VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C, unless otherwise stated.
Spec
No.
Characteristics
Resolution
Sym
Min
Typ
Max
Units
Comments
D310
VRES
VDD/24
-
VDD/32 LSb
D311
Absolute Accuracy
VRAA
-
-
-
-
1/4
1/2
LSb
LSb
Low Range (VRR = 1)
High Range (VRR = 0)
D312
310
Unit Resistor Value (R)*
Settling Time(1)*
VRUR
TSET
-
-
2k
-
-
Ω
10
µs
* These parameters are characterized but not tested.
Settling time measured while VRR = 1 and VR<3:0> transitions from 0000to 1111.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 137
PIC16F62X
17.4
Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase subscripts (pp) and their meanings:
pp
ck
T
Time
CLKOUT
I/O port
MCLR
osc
t0
OSC1
T0CKI
io
mc
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-Impedance
FIGURE 17-5: LOAD CONDITIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
TABLE 17-3: DC CHARACTERISTICS: PIC16F62X, PIC16LF62X
Standard Operating Conditions (unless otherwise stated)
DC Characteristics
Parameter
Sym
Characteristic
Min
Typ†
Max Units
Conditions
No.
Data EEPROM Memory
D120
Ed
Endurance
1M*
10M
—
E/W 25°C at 5V
D121
Vdrw VDD for read/write
VMIN
—
5.5
V
VMIN = Minimum operating
voltage
D122
Tdew Erase/Write cycle time
—
4
8*
ms
Program Flash Memory
D130
D131
Ep
Vpr
Endurance
VDD for read
1000*
Vmin
10000
—
—
5.5
E/W
V
VMIN = Minimum operating
voltage
D132
D133
Vpew VDD for erase/write
Tpew Erase/Write cycle time
4.5
—
—
4
5.5
8*
V
ms
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS40300B-page 138
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
17.5
Timing Diagrams and Specifications
FIGURE 17-6: EXTERNAL CLOCK TIMING
Q4
Q3
Q4
4
Q1
Q1
Q2
OSC1
1
3
3
4
2
CLKOUT
TABLE 17-4: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
Sym
Characteristic
Min
Typ†
Max Units
Conditions
No.
Fosc External CLKIN Frequency
(Note 1)
DC
—
4
MHz XT and ER osc mode,
VDD=5.0V
DC
DC
—
—
20
MHz HS osc mode
kHz LP osc mode
200
Oscillator Frequency
(Note 1)
—
—
4
4
MHz ER osc mode, VDD=5.0V
0.1
1
MHz XT osc mode
—
—
20
200
MHz HS osc mode
kHz LP osc mode
4
MHz INTRC mode (fast)
kHz INTRC mode (slow)
37
—
—
—
1
Tosc
External CLKIN Period
(Note 1)
250
50
5
—
—
—
ns
ns
µs
XT and ER osc mode
HS osc mode
LP osc mode
Oscillator Period
(Note 1)
250
250
50
—
—
—
—
ns
ER osc mode
10,000 ns
XT osc mode
1,000 ns
HS osc mode
5
µs
ns
µs
LP osc mode
250
27
INTRC mode (fast)
INTRC mode (slow)
TCY = 4/FOSC
2
3
Tcy
Instruction Cycle Time (Note 1) 1.0
TCY
—
DC
—
ns
ns
TosL, External CLKIN (OSC1) High
TosH External CLKIN Low
100 *
XT oscillator, TOSC L/H duty
cycle
4
5
INTRC Internal Calibrated ER
3.65
4.00
4.28
MHz VDD = 5.0V
VDD = 5.0V
ER
External Biased ER Frequency 10kHz
8MHz
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 139
PIC16F62X
FIGURE 17-7: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
22
23
CLKOUT
13
12
16
19
18
14
I/O Pin
(input)
15
17
I/O Pin
new value
old value
(output)
20, 21
TABLE 17-5: CLKOUT AND I/O TIMING REQUIREMENTS
Parameter
Sym
Characteristic
Min Typ† Max
Units
No.
10
TosH2ckL OSC1↑ to CLKOUT↓
16F62X
16LF62X
16F62X
16LF62X
16F62X
16LF62X
16F62X
16LF62X
—
75
200
ns
10A
11
—
—
—
400
200
ns
ns
TosH2ckH OSC1↑ to CLKOUT↑
75
11A
12
—
—
—
—
—
—
35
—
35
—
400
100
200
100
200
ns
ns
ns
ns
ns
TckR
TckF
CLKOUT rise time
CLKOUT fall time
12A
13
13A
14
15
TckL2ioV
TioV2ckH
CLKOUT ↓ to Port out valid
—
—
—
20
—
ns
ns
Port in valid before
Tosc
16F62X
+200
ns
CLKOUT ↑
Tosc
=400
ns
—
—
ns
16LF62X
16
17
TckH2ioI
Port in hold after CLKOUT ↑
OSC1↑ (Q1 cycle) to
0
—
—
ns
ns
TosH2ioV
—
50
150 *
16F62X
Port out valid
—
—
—
300
—
ns
ns
16LF62X
18
TosH2ioI
OSC1↑ (Q2 cycle) to Port input invalid
100
200
(I/O in hold time)
DS40300B-page 140
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
FIGURE 17-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Timeout
32
OSC
Timeout
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
FIGURE 17-9: BROWN-OUT DETECT TIMING
BVDD
VDD
35
TABLE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Unit
s
Sym
Characteristic
Min
Typ†
Max
Conditions
30
TmcL MCLR Pulse Width (low)
2000
TBD
—
TBD
—
TBD
ns
VDD = 5V, -40°C to +85°C
ms Extended temperature
31
Twdt
Tost
Watchdog Timer Time-out Period
(No Prescaler)
7
TBD
18
TBD
33
TBD
ms VDD = 5V, -40°C to +85°C
ms Extended temperature
32
Oscillation Start-up Timer Period
—
1024TOSC
—
—
TOSC = OSC1 period
33*
Tpwrt Power up Timer Period
28
72
132
ms VDD = 5V, -40°C to +85°C
TBD
TBD
TBD
ms
34
35
TIOZ
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
—
—
2.0
µs
TBOD
Brown-out Detect pulse width
100
—
—
µs
VDD ≤ BVDD (D005)
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 141
PIC16F62X
FIGURE 17-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RB6/T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
DS40300B-page 142
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
TABLE 17-7: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
Sym
Characteristic
Min
Typ† Max Units Conditions
No.
40*
Tt0H
T0CKI High Pulse Width
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
10
41*
42*
Tt0L
Tt0P
T0CKI Low Pulse Width
T0CKI Period
0.5TCY + 20
10
Greater of:
ns N = prescale
TCY + 40
value (2, 4, ...,
N
256)
45*
46*
47*
Tt1H
Tt1L
Tt1P
T1CKI High
Time
Synchronous, No Prescaler
Synchronous, 16F62X
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
15
25
30
50
with Prescaler
16LF62X
Asynchronous 16F62X
16LF62X
Synchronous, No Prescaler
Synchronous, 16F62X
T1CKI Low
Time
0.5TCY + 20
15
25
30
50
with Prescaler
16LF62X
Asynchronous 16F62X
16LF62X
Synchronous 16F62X
ns
ns
T1CKI input
period
Greater of:
TCY + 40
N
ns N = prescale
value (1, 2, 4, 8)
16LF62X
Greater of:
TCY + 40
N
—
—
—
Asynchronous 16F62X
16LF62X
Timer1 oscillator input frequency range
60
100
DC
—
—
—
—
—
ns
ns
Ft1
200 kHz
(oscillator enabled by setting bit T1OSCEN)
48
TCKEZtmr1 Delay from external clock edge to timer
increment
2Tosc
—
7Tos
c
—
* These parameters are characterized but not tested.
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 17-11: CAPTURE/COMPARE/PWM TIMINGS
RB3/CCP1
(Capture Mode)
50
51
52
RB3/CCP1
(Compare or PWM Mode)
53
54
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 143
PIC16F62X
TABLE 17-8: CAPTURE/COMPARE/PWM REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max Units Conditions
50* TccL CCP
No Prescaler
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
input low time
16F62X
10
With Prescaler
No Prescaler
16LF62X
20
0.5TCY + 20
10
51* TccH CCP
input high time
16F62X
With Prescaler
16LF62X
20
52* TccP CCP input period
3TCY + 40
ns N = prescale
value (1,4 or
16)
N
53* TccR CCP output rise time
54* TccF CCP output fall time
16F62X
16LF62X
16F62X
16LF62X
10
25
10
25
25
45
25
45
ns
ns
ns
ns
* These parameters are characterized but not tested.
†Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
FIGURE 17-12: TIMER0 CLOCK TIMING
RA4/T0CKI
41
40
42
TMR0
TABLE 17-9: TIMER0 CLOCK REQUIREMENTS
Parameter Sym Characteristic
No.
Min
Typ† Max Units Conditions
40
41
42
Tt0H T0CKI High Pulse Width
Tt0L T0CKI Low Pulse Width
Tt0P T0CKI Period
No Prescaler
0.5 TCY + 20*
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
With Prescaler
No Prescaler
With Prescaler
0.5 TCY + 20*
10*
TCY + 40*
N = prescale value
(1, 2, 4, ..., 256)
N
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
DS40300B-page 144
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
18.0 DEVICE CHARACTERIZATION
INFORMATION
Not Available at this time.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 145
PIC16F62X
NOTES:
DS40300B-page 146
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
19.0 PACKAGING INFORMATION
19.1
Package Marking Information
18-Lead PDIP
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
PIC16F627
-04I / P456
9923 CBA
AABBCDE
18-Lead SOIC (.300")
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16F627
-04I / S0218
AABBCDE
9918 CDK
20-Lead SSOP
Example
PIC16F627
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
-04I / 218
9951 CBP
Legend: MM...M Microchip part number information
XX...X Customer specific information*
AA
BB
C
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
O = Outside Vendor
C = 5” Line
S = 6” Line
H = 8” Line
D
E
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 147
PIC16F62X
Package Type: K04-007 18-Lead Plastic Dual In-line (P) – 300 mil
E
D
2
α
n
1
E1
A1
L
A
R
c
A2
B1
β
p
B
eB
Units
INCHES*
NOM
0.300
18
MILLIMETERS
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Molded Package Width
Radius to Radius Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
MAX
MIN
NOM
7.62
18
MAX
n
p
B
B1
R
c
A
A1
A2
L
D
E
E1
eB
α
0.100
0.018
0.060
0.005
0.010
0.155
0.095
0.020
0.130
0.895
0.255
0.250
0.349
10
2.54
0.013
0.023
0.33
1.40
0.46
1.52
0.13
0.25
3.94
2.41
0.51
3.30
22.73
6.48
6.35
8.85
10
0.58
†
0.055
0.000
0.005
0.110
0.075
0.000
0.125
0.890
0.245
0.230
0.310
5
0.065
0.010
0.015
0.155
0.115
0.020
0.135
0.900
0.265
0.270
0.387
15
1.65
0.25
0.38
3.94
2.92
0.51
3.43
22.86
6.73
6.86
9.83
15
0.00
0.13
2.79
1.91
0.00
3.18
22.61
6.22
5.84
7.87
5
‡
‡
β
5
10
15
5
10
15
* Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
DS40300B-page 148
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
Package Type: K04-051 18-Lead Plastic Small Outline (SO) – Wide, 300 mil
E1
E
p
D
2
1
B
n
X
α
45°
L
R2
c
A
A1
R1
φ
β
L1
A2
Units
Dimension Limits
Pitch
INCHES*
NOM
0.050
18
MILLIMETERS
MIN
MAX
MIN
NOM
1.27
18
MAX
p
n
A
A1
A2
Number of Pins
Overall Pack. Height
Shoulder Height
Standoff
Molded Package Length
Molded Package Width
Outside Dimension
Chamfer Distance
Shoulder Radius
Gull Wing Radius
Foot Length
0.093
0.099
0.058
0.008
0.456
0.296
0.407
0.020
0.005
0.005
0.016
4
0.104
2.36
1.22
2.50
1.47
0.19
11.58
7.51
10.33
0.50
0.13
0.13
0.41
4
2.64
1.73
0.28
11.73
7.59
10.64
0.74
0.25
0.25
0.53
8
0.048
0.004
0.450
0.292
0.394
0.010
0.005
0.005
0.011
0
0.068
0.011
0.462
0.299
0.419
0.029
0.010
0.010
0.021
8
0.10
11.43
7.42
10.01
0.25
0.13
0.13
0.28
0
‡
D
E
‡
E1
X
R1
R2
L
Foot Angle
φ
Radius Centerline
Lead Thickness
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
*
L1
c
B
α
β
0.010
0.009
0.014
0
0.015
0.011
0.017
12
0.020
0.012
0.019
15
0.25
0.23
0.36
0
0.38
0.27
0.42
12
0.51
0.30
0.48
15
†
0
12
15
0
12
15
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 149
PIC16F62X
Package Type: K04-072 20-Lead Plastic Shrink Small Outline (SS) – 5.30 mm
E1
E
p
D
B
2
n
1
α
L
R2
c
A
A1
R1
φ
L1
A2
β
Units
Dimension Limits
Pitch
INCHES
NOM
0.026
MILLIMETERS*
MIN
MAX
MIN
NOM
0.65
20
MAX
p
n
A
A1
A2
D
E
E1
R1
R2
L
Number of Pins
Overall Pack. Height
Shoulder Height
Standoff
Molded Package Length
Molded Package Width
Outside Dimension
Shoulder Radius
Gull Wing Radius
Foot Length
20
0.073
0.036
0.005
0.283
0.208
0.306
0.005
0.005
0.020
4
0.068
0.078
1.73
0.66
1.86
0.91
0.13
7.20
5.29
7.78
0.13
0.13
0.51
4
1.99
0.026
0.002
0.278
0.205
0.301
0.005
0.005
0.015
0
0.046
0.008
0.289
0.212
0.311
0.010
0.010
0.025
8
1.17
0.21
7.33
5.38
7.90
0.25
0.25
0.64
8
0.05
7.07
5.20
7.65
0.13
0.13
0.38
0
‡
‡
Foot Angle
φ
Radius Centerline
Lead Thickness
Lower Lead Width
Mold Draft Angle Top
L1
c
B
α
β
0.000
0.005
0.010
0
0.005
0.007
0.012
5
0.010
0.009
0.015
10
0.00
0.13
0.25
0
0.13
0.18
0.32
5
0.25
0.22
0.38
10
†
Mold Draft Angle Bottom
0
5
10
0
5
10
*
Controlling Parameter.
†
‡
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
DS40300B-page 150
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
Comparator Interrupts......................................................... 61
Comparator Module............................................................ 57
Comparator Operation........................................................ 59
Comparator Reference ....................................................... 59
Compare (CCP Module) ..................................................... 65
Block Diagram ............................................................ 65
CCP Pin Configuration ............................................... 65
CCPR1H:CCPR1L Registers ..................................... 65
Software Interrupt....................................................... 65
Special Event Trigger ................................................. 65
Timer1 Mode Selection............................................... 65
Configuration Bits ............................................................... 96
Configuring the Voltage Reference..................................... 69
Crystal Operation................................................................ 97
INDEX
A
A/D
Special Event Trigger (CCP)....................................... 65
Absolute Maximum Ratings .............................................. 131
ADDLW Instruction ........................................................... 115
ADDWF Instruction ........................................................... 115
ANDLW Instruction ........................................................... 115
ANDWF Instruction ........................................................... 115
Architectural Overview .......................................................... 9
Assembler
MPASM Assembler................................................... 125
B
Baud Rate Error .................................................................. 73
Baud Rate Formula............................................................. 73
Baud Rates
Asynchronous Mode ................................................... 74
Synchronous Mode..................................................... 74
BCF Instruction ................................................................. 116
Block Diagram
TIMER0....................................................................... 45
TMR0/WDT PRESCALER .......................................... 48
Block Diagrams
D
DATA .................................................................................. 93
Data .................................................................................... 93
Data EEPROM Memory...................................................... 91
EECON1 Register ...................................................... 91
EECON2 Register ...................................................... 91
Data Memory Organization................................................. 13
DECF Instruction .............................................................. 118
DECFSZ Instruction.......................................................... 118
Development Support....................................................... 125
Comparator I/O Operating Modes............................... 58
Comparator Output ..................................................... 60
RA3:RA0 and RA5 Port Pins ...................................... 35
Timer1......................................................................... 51
Timer2......................................................................... 54
USART Receive.......................................................... 80
USART Transmit......................................................... 78
BRGH bit............................................................................. 73
Brown-Out Detect (BOD) .................................................. 101
BSF Instruction ................................................................. 116
BTFSC Instruction............................................................. 116
BTFSS Instruction............................................................. 117
E
EECON1............................................................................. 92
Errata.................................................................................... 3
External Crystal Oscillator Circuit ....................................... 98
G
General purpose Register File............................................ 13
GOTO Instruction.............................................................. 119
I
I/O Ports ............................................................................. 27
I/O Programming Considerations ....................................... 44
ID Locations...................................................................... 112
INCF Instruction................................................................ 119
INCFSZ Instruction ........................................................... 119
In-Circuit Serial Programming........................................... 112
Indirect Addressing, INDF and FSR Registers ................... 26
Instruction Flow/Pipelining.................................................. 12
Instruction Set
C
CALL Instruction ............................................................... 117
Capture (CCP Module) ....................................................... 64
Block Diagram............................................................. 64
CCP Pin Configuration................................................ 64
CCPR1H:CCPR1L Registers...................................... 64
Changing Between Capture Prescalers...................... 64
Software Interrupt ....................................................... 64
Timer1 Mode Selection............................................... 64
Capture/Compare/PWM (CCP)........................................... 63
CCP1 .......................................................................... 63
CCP1CON Register............................................ 63
ADDLW..................................................................... 115
ADDWF .................................................................... 115
ANDLW..................................................................... 115
ANDWF .................................................................... 115
BCF .......................................................................... 116
BSF........................................................................... 116
BTFSC...................................................................... 116
BTFSS...................................................................... 117
CALL......................................................................... 117
CLRF ........................................................................ 117
CLRW....................................................................... 117
CLRWDT .................................................................. 118
COMF....................................................................... 118
DECF........................................................................ 118
DECFSZ ................................................................... 118
GOTO....................................................................... 119
INCF ......................................................................... 119
INCFSZ..................................................................... 119
IORLW...................................................................... 119
IORWF...................................................................... 120
MOVF ....................................................................... 120
MOVLW.................................................................... 120
MOVWF.................................................................... 120
CCPR1H Register............................................... 63
CCPR1L Register ............................................... 63
CCP2 .......................................................................... 63
Timer Resources......................................................... 63
CCP1CON Register ............................................................ 63
CCP1M3:CCP1M0 Bits............................................... 63
CCP1X:CCP1Y Bits.................................................... 63
CCP2CON Register
CCP2M3:CCP2M0 Bits............................................... 63
CCP2X:CCP2Y Bits.................................................... 63
Clocking Scheme/Instruction Cycle .................................... 12
CLRF Instruction............................................................... 117
CLRW Instruction.............................................................. 117
CLRWDT Instruction ......................................................... 118
CMCON Register ................................................................ 57
Code Protection ................................................................ 112
COMF Instruction.............................................................. 118
Comparator Configuration................................................... 58
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 151
PIC16F62X
NOP ..........................................................................121
OPTION ....................................................................121
RETFIE .....................................................................121
RETLW .....................................................................121
RETURN ...................................................................122
RLF ...........................................................................122
RRF...........................................................................122
SLEEP ......................................................................122
SUBLW .....................................................................123
SUBWF.....................................................................123
SWAPF .....................................................................124
TRIS..........................................................................124
XORLW.....................................................................124
XORWF.....................................................................124
Instruction Set Summary...................................................113
INT Interrupt......................................................................108
INTCON Register................................................................21
Interrupt Sources
Capture Complete (CCP)............................................64
Compare Complete (CCP)..........................................65
TMR2 to PR2 Match (PWM) .......................................66
Interrupts...........................................................................107
Interrupts, Enable Bits
CCP1 Enable (CCP1IE Bit).........................................64
Interrupts, Flag Bits
CCP1 Flag (CCP1IF Bit) ....................................... 64, 65
IORLW Instruction.............................................................119
IORWF Instruction.............................................................120
Power-Down Mode (SLEEP) ............................................ 111
Power-On Reset (POR).................................................... 101
Power-up Timer (PWRT) .................................................. 101
PR2 Register ...................................................................... 54
Prescaler............................................................................. 48
Prescaler, Capture.............................................................. 64
Prescaler, Timer2 ............................................................... 66
PRO MATE II Universal Programmer ............................ 127
Program Memory Organization........................................... 13
PROTECTION .................................................................... 93
PWM (CCP Module) ........................................................... 66
Block Diagram ............................................................ 66
CCPR1H:CCPR1L Registers...................................... 66
Duty Cycle .................................................................. 66
Example Frequencies/Resolutions ............................. 67
Output Diagram .......................................................... 66
Period ......................................................................... 66
Set-Up for PWM Operation......................................... 67
TMR2 to PR2 Match ................................................... 66
Q
Q-Clock............................................................................... 66
Quick-Turnaround-Production (QTP) Devices...................... 7
R
RC Oscillator....................................................................... 98
READING ........................................................................... 93
Registers
Maps
PIC16C76........................................................... 14
PIC16C77........................................................... 14
RCSTA
K
KeeLoq Evaluation and Programming Tools..................128
M
Diagram.............................................................. 72
Reset .................................................................................. 99
RETFIE Instruction ........................................................... 121
RETLW Instruction............................................................ 121
RETURN Instruction ......................................................... 122
RLF Instruction ................................................................. 122
RRF Instruction................................................................. 122
Memory Organization
Data EEPROM Memory..............................................91
MOVF Instruction ..............................................................120
MOVLW Instruction...........................................................120
MOVWF Instruction...........................................................120
MPLAB Integrated Development Environment Software ..125
N
S
NOP Instruction.................................................................121
SEEVAL Evaluation and Programming System............. 128
Serialized Quick-Turnaround-Production
O
(SQTP) Devices.................................................................... 7
SLEEP Instruction............................................................. 122
Software Simulator (MPLAB-SIM) .................................... 126
Special................................................................................ 99
Special Features of the CPU .............................................. 95
Special Function Registers................................................. 15
Stack................................................................................... 25
Status Register ................................................................... 19
SUBLW Instruction ........................................................... 123
SUBWF Instruction ........................................................... 123
SWAPF Instruction ........................................................... 124
OPTION Instruction...........................................................121
OPTION Register................................................................20
Oscillator Configurations.....................................................97
Oscillator Start-up Timer (OST) ........................................101
Output of TMR2...................................................................54
P
Package Marking Information ...........................................147
Packaging Information ......................................................147
PCL and PCLATH...............................................................25
PCON Register ...................................................................24
PICDEM-1 Low-Cost PICmicro Demo Board....................127
PICDEM-2 Low-Cost PIC16CXX Demo Board .................127
PICDEM-3 Low-Cost PIC16CXXX Demo Board...............127
PICSTART Plus Entry Level Development System .......127
PIE1 Register......................................................................22
Pin Functions
RC6/TX/CK ...........................................................71–88
RC7/RX/DT........................................................... 71–88
Pinout Description...............................................................11
PIR1 Register......................................................................23
Port RB Interrupt ...............................................................108
PORTA................................................................................27
PORTB................................................................................34
Power Control/Status Register (PCON)............................102
T
T1CKPS0 bit....................................................................... 50
T1CKPS1 bit....................................................................... 50
T1CON Register ................................................................. 50
T1OSCEN bit...................................................................... 50
T1SYNC bit......................................................................... 50
T2CKPS0 bit....................................................................... 55
T2CKPS1 bit....................................................................... 55
T2CON Register ................................................................. 55
DS40300B-page 152
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
Timer0
TIMER0....................................................................... 45
USART
Asynchronous Mode................................................... 78
Asynchronous Receiver.............................................. 80
Asynchronous Reception............................................ 82
Asynchronous Transmission ...................................... 79
Asynchronous Transmitter.......................................... 78
Baud Rate Generator (BRG) ...................................... 73
Sampling..................................................................... 76
Synchronous Master Mode......................................... 84
Synchronous Master Reception ................................. 86
Synchronous Master Transmission ............................ 84
Synchronous Slave Mode........................................... 88
Synchronous Slave Reception ................................... 88
Synchronous Slave Transmit...................................... 88
Transmit Block Diagram ............................................. 78
TIMER0 (TMR0) Interrupt ........................................... 45
TIMER0 (TMR0) Module............................................. 45
TMR0 with External Clock........................................... 47
Timer1
Special Event Trigger (CCP)....................................... 65
Switching Prescaler Assignment................................. 49
Timer2
PR2 Register............................................................... 66
TMR2 to PR2 Match Interrupt..................................... 66
Timers
Timer1
Asynchronous Counter Mode ............................. 52
Block Diagram .................................................... 51
Capacitor Selection............................................. 52
External Clock Input............................................ 51
External Clock Input Timing................................ 52
Operation in Timer Mode .................................... 51
Oscillator............................................................. 52
Prescaler....................................................... 51, 53
Resetting of Timer1 Registers ............................ 53
Resetting Timer1 using a CCP Trigger Output ... 53
Synchronized Counter Mode .............................. 51
T1CON................................................................ 50
TMR1H ............................................................... 52
TMR1L ................................................................ 52
V
Voltage Reference Module ................................................. 69
VRCON Register ................................................................ 69
W
Watchdog Timer (WDT).................................................... 109
WRITE ................................................................................ 93
WRITING ............................................................................ 93
WWW, On-Line Support ....................................................... 3
X
XORLW Instruction........................................................... 124
XORWF Instruction........................................................... 124
Timer2
Block Diagram .................................................... 54
Module ................................................................ 54
Postscaler ........................................................... 54
Prescaler............................................................. 54
T2CON................................................................ 55
Timing Diagrams
Timer0....................................................................... 142
Timer1....................................................................... 142
USART Asynchronous Master Transmission.............. 79
USART RX Pin Sampling...................................... 76, 77
USART Synchronous Reception................................. 87
USART Synchronous Transmission ........................... 85
USART, Asynchronous Reception.............................. 81
Timing Diagrams and Specifications................................. 139
TMR0 Interrupt.................................................................. 108
TMR1CS bit ........................................................................ 50
TMR1ON bit ........................................................................ 50
TMR2ON bit ........................................................................ 55
TOUTPS0 bit....................................................................... 55
TOUTPS1 bit....................................................................... 55
TOUTPS2 bit....................................................................... 55
TOUTPS3 bit....................................................................... 55
TRIS Instruction ................................................................ 124
TRISA ................................................................................. 27
TRISB ................................................................................. 34
TXSTA Register .................................................................. 71
U
Universal Synchronous Asynchronous Receiver
Transmitter (USART) .......................................................... 71
Asynchronous Receiver
Setting Up Reception.......................................... 83
Timing Diagram .................................................. 81
Asynchronous Receiver Mode
Block Diagram .................................................... 83
Section................................................................ 83
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 153
PIC16F62X
DS40300B-page 154
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip’s development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-602-786-7302 for the rest of the world.
981103
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
Trademarks: The Microchip name, logo, PIC, PICmicro,
PICSTART, PICMASTER and PRO MATE are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries. FlexROM, MPLAB and fuzzy-
LAB are trademarks and SQTP is a service mark of Micro-
chip in the U.S.A.
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
All other trademarks mentioned herein are the property of
their respective companies.
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Sys-
tems, technical information and more
• Listing of seminars and events
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 155
PIC16F62X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
Technical Publications Manager
Reader Response
Total Pages Sent
RE:
From:
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Literature Number:
DS40300B
Device:
PIC16F62X
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS40300B-page 156
Preliminary
1999 Microchip Technology Inc.
PIC16F62X
PIC16F62X PRODUCT IDENTIFICATION SYSTEM
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
PART NO. -XX X /XX XXX
Pattern:
3-Digit Pattern Code for QTP (blank otherwise)
Package:
P
SO
SS
=
=
=
PDIP
SOIC (Gull Wing, 300 mil body)
SSOP (209 mil)
Examples:
g) PIC16F627 - 04/P 301 =
Commercial temp., PDIP pack-
age, 4 MHz, normal VDD limits,
QTP pattern #301.
Temperature -
=
=
=
0°C to +70°C
–40°C to +85°C
–40°C to +125°C
Range:
I
E
h) PIC16LF627- 04I/SO =
Industrial temp., SOIC pack-
age, 200kHz, extended VDD
limits.
Frequency 04
=
=
=
200kHz (LP osc)
4 MHz (XT and ER osc)
20 MHz (HS osc)
Range:
04
20
Device:
PIC16F62X :VDD range 3.0V to 5.5V
PIC16F62XT:VDD range 3.0V to 5.5V (Tape and Reel)
PIC16LF62X:VDD range 2.0V to 5.5V
PIC16LF62XT:VDD range 2.0V to 5.5V (Tape and Reel)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 157
PIC16F62X
NOTES:
DS40300B-page 158
1999 Microchip Technology Inc.
PIC16F62X
NOTES:
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 159
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
ASIA/PACIFIC (continued)
Corporate Office
Toronto
Singapore
Microchip Technology Inc.
Microchip Technology Inc.
Microchip Technology Singapore Pte Ltd.
200 Middle Road
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-786-7200 Fax: 480-786-7277
Technical Support: 480-786-7627
Web Address: http://www.microchip.com
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
#07-02 Prime Centre
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
Taiwan, R.O.C
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific
Unit 2101, Tower 2
Atlanta
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Tel: 770-640-0034 Fax: 770-640-0307
Boston
EUROPE
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508-480-9990 Fax: 508-480-8575
Beijing
United Kingdom
Microchip Technology, Beijing
Unit 915, 6 Chaoyangmen Bei Dajie
Dong Erhuan Road, Dongcheng District
New China Hong Kong Manhattan Building
Beijing 100027 PRC
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5858 Fax: 44-118 921-5835
Denmark
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 86-10-85282100 Fax: 86-10-85282104
India
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
4570 Westgrove Drive, Suite 160
Addison, TX 75248
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Tel: 972-818-7423 Fax: 972-818-2924
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip Technology Inc.
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Japan
France
Microchip Technology Intl. Inc.
Benex S-1 6F
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 München, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Shanghai
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Italy
Los Angeles
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
New York
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
11/15/99
San Jose
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明