PIC16LF870/SP [MICROCHIP]
28/40-Pin 8-Bit CMOS FLASH Microcontrollers; 40分之28引脚8位CMOS闪存微控制器
| 型号： | PIC16LF870/SP |
| 厂家： | 
MICROCHIP |
| 描述： | 28/40-Pin 8-Bit CMOS FLASH Microcontrollers |
| 文件： | 总156页 (文件大小：2816K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC16F870/871
28/40-Pin 8-Bit CMOS FLASH Microcontrollers
Devices Included in this Data Sheet:
• PIC16F870 • PIC16F871
Pin Diagram
PDIP
Microcontroller Core Features:
MCLR/VPP/THV
RA0/AN0
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7/PGD
RB6/PGC
2
• High-performance RISC CPU
RA1/AN1
RA2/AN2/VREF-
3
RB5
• Only 35 single word instructions to learn
4
RB4
RA3/AN3/VREF+
RA4/T0CKI
RB3/PGM
RB2
5
• All single cycle instructions except for program
branches which are two cycle
6
RA5/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
7
RB1
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
8
RB0/INT
VDD
9
10
11
12
13
14
15
16
17
18
19
20
VSS
• 2K x 14 words of FLASH Program Memory
128 x 8 bytes of Data Memory (RAM)
64 x 8 bytes of EEPROM Data Memory
RD7/PSP7
VSS
RD6/PSP6
RD5/PSP5
RD4/PSP4
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
• Pinout compatible to the PIC16CXXX 28 and 40-
pin devices
RC7/RX/DT
RC6/TX/CK
RC5
• Interrupt capability (up to 11 sources)
• Eight level deep hardware stack
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
RC3
RC4
RD0/PSP0
RD3/PSP3
RD1/PSP1
RD2/PSP2
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
Peripheral Features:
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Low-power, high-speed CMOS FLASH/EEPROM
technology
• One Capture, Compare, PWM module
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• Fully static design
• In-Circuit Serial Programming (ICSP) via two
pins
• Single 5V In-Circuit Serial Programming capability
• In-Circuit Debugging via two pins
• 10-bit multi-channel Analog-to-Digital converter
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI) with 9-bit address
detection
• Processor read/write access to program memory
• Wide operating voltage range: 2.0V to 5.5V
• High Sink/Source Current: 25 mA
• Commercial and Industrial temperature ranges
• Low-power consumption:
• Parallel Slave Port (PSP) 8-bits wide, with
external RD, WR and CS controls (40/44-pin only)
• Brown-out detection circuitry for
Brown-out Reset (BOR)
- < 1.6 mA typical @ 5V, 4 MHz
- 20 µA typical @ 3V, 32 kHz
- < 1 µA typical standby current
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 1
PIC16F870/871
Pin Diagrams
DIP, SOIC, SSOP
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
MCLR/VPP/THV
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4
RB1
RB0/INT
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
VSS
10
11
RC7/RX/DT
RC6/TX/CK
RC5
12
13
14
RC4
RC3
PLCC
39
38
37
RA4/T0CKI
RB3/PGM
RB2
7
RA5/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
8
RB1
9
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
36
35
34
33
32
31
30
29
10
11
12
13
14
15
16
17
PIC16F871
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CK1
NC
TQFP
NC
33
1
2
3
4
5
6
7
8
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3/PGM
RC0/T1OSO/T1CKI
32
31
30
29
28
27
26
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
PIC16F871
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4
9
10
11
25
24
23
RA4/T0CKI
DS30569A-page 2
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
Key Features
PICmicro™ Mid-Range Reference Manual (DS33023)
PIC16F870
PIC16F871
Operating Frequency
Resets (and Delays)
DC - 20 MHz
DC - 20 MHz
POR, BOR
POR, BOR
(PWRT, OST)
(PWRT, OST)
FLASH Program Memory
(14-bit words)
2K
2K
Data Memory (bytes)
EEPROM Data Memory
Interrupts
128
128
64
64
10
11
I/O Ports
Ports A,B,C
Ports A,B,C,D,E
Timers
3
3
1
Capture/Compare/PWM modules
Serial Communications
Parallel Communications
10-bit Analog-to-Digital Module
Instruction Set
1
USART
USART
—
PSP
5 input channels
35 Instructions
8 input channels
35 Instructions
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 3
PIC16F870/871
Table of Contents
1.0 Device Overview ...................................................................................................................................................5
2.0 Memory Organization..........................................................................................................................................11
3.0 I/O Ports..............................................................................................................................................................27
4.0 Data EEPROM and FLASH Program Memory....................................................................................................39
5.0 Timer0 Module ....................................................................................................................................................47
6.0 Timer1 Module ....................................................................................................................................................51
7.0 Timer2 Module ....................................................................................................................................................55
8.0 Capture/Compare/PWM Module.........................................................................................................................57
9.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ........................................63
10.0 Analog-to-Digital Converter (A/D) Module...........................................................................................................79
11.0 Special Features of the CPU...............................................................................................................................89
12.0 Instruction Set Summary...................................................................................................................................105
13.0 Development Support .......................................................................................................................................113
14.0 Electrical Characteristics...................................................................................................................................119
15.0 DC and AC Characteristics Graphs and Tables................................................................................................135
16.0 Packaging Information ......................................................................................................................................137
Index .......................................................................................................................................................................... 145
On-Line Support..........................................................................................................................................................151
Reader Response .......................................................................................................................................................152
Product Identification System......................................................................................................................................153
To Our Valued Customers
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DS30569A-page 4
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
There are two devices (PIC16F870 and PIC16F871)
covered by this data sheet. The PIC16F870 device
comes in a 28-pin package and the PIC16F871 device
comes in a 40-pin package. The 28-pin device does not
have a Parallel Slave Port implemented.
1.0
DEVICE OVERVIEW
This document contains device-specific information.
Additional information may be found in the PICmicro™
Mid-Range Reference Manual, (DS33023), which may
be obtained from your local Microchip Sales Represen-
tative or downloaded from the Microchip website. The
Reference Manual should be considered a comple-
mentary document to this data sheet, and is highly rec-
ommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
The following two figures are device block diagrams
sorted by pin number; 28-pin for Figure 1-1 and 40-pin
for Figure 1-2. The 28-pin and 40-pin pinouts are listed
in Table 1-1 and Table 1-2, respectively.
FIGURE 1-1: PIC16F870 BLOCK DIAGRAM
Device
Program
FLASH
Data Memory
Data
EEPROM
PIC16F870
2K
128 Bytes
64 Bytes
13
8
PORTA
Data Bus
Program Counter
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4
FLASH
Program
Memory
RAM
File
Registers
8 Level Stack
(13-bit)
Program
Bus
14
RAM Addr (1)
PORTB
9
RB0/INT
RB1
RB2
RB3/PGM
RB4
Addr MUX
Instruction reg
Indirect
Addr
7
Direct Addr
8
RB5
FSR reg
RB6/PGC
RB7/PGD
STATUS reg
PORTC
8
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3
RC4
3
MUX
Power-up
Timer
Oscillator
RC5
RC6/TX/CK
RC7/RX/DT
Instruction
Decode &
Control
Start-up Timer
ALU
Power-on
Reset
8
Timing
Generation
Watchdog
Timer
W reg
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Reset
In-Circuit
Debugger
Low-Voltage
Programming
MCLR VDD, VSS
Timer2
Timer0
Timer1
CCP1
10-bit A/D
Data EEPROM
USART
Note 1: Higher order bits are from the STATUS register.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 5
PIC16F870/871
FIGURE 1-2: PIC16F871 BLOCK DIAGRAM
Device
Program
FLASH
Data Memory
Data
EEPROM
PIC16F871
2K
128 Bytes
64 Bytes
13
8
PORTA
Data Bus
RAM
Program Counter
FLASH
RA0/AN0
RA1/AN1
Program
Memory
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4
8 Level Stack
(13-bit)
File
Registers
Program
Bus
14
RAM Addr (1)
PORTB
9
RB0/INT
RB1
RB2
RB3/PGM
RB4
Addr MUX
Instruction reg
Indirect
Addr
7
Direct Addr
8
RB5
FSR reg
RB6/PGC
RB7/PGD
STATUS reg
PORTC
8
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3
RC4
3
MUX
Power-up
Timer
Oscillator
RC5
RC6/TX/CK
RC7/RX/DT
Instruction
Decode &
Control
Start-up Timer
ALU
Power-on
Reset
8
PORTD
Timing
Generation
Watchdog
Timer
W reg
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Reset
RD7/PSP7:RD0/PSP0
In-Circuit
Debugger
Low-Voltage
Programming
PORTE
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
MCLR VDD, VSS
Timer0
Timer1
CCP1
Timer2
10-bit A/D
Data EEPROM
Parallel Slave Port
USART
Note 1: Higher order bits are from the STATUS register.
DS30569A-page 6
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
TABLE 1-1:
PIC16F870 PINOUT DESCRIPTION
DIP
Pin#
SOIC
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
(3)
OSC1/CLKIN
9
9
I
Oscillator crystal input/external clock source input.
ST/CMOS
OSC2/CLKOUT
10
10
O
—
Oscillator crystal output. Connects to crystal or resonator in crystal
oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT
which has 1/4 the frequency of OSC1, and denotes the instruction
cycle rate.
MCLR/VPP/THV
1
1
I/P
ST
Master clear (reset) input or programming voltage input or high
voltage test mode control. This pin is an active low reset to the
device.
PORTA is a bi-directional I/O port.
RA0 can also be analog input0
RA1 can also be analog input1
RA0/AN0
2
3
4
2
3
4
I/O
I/O
I/O
TTL
TTL
TTL
RA1/AN1
RA2/AN2/VREF-
RA2 can also be analog input2 or negative analog reference
voltage
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4
5
6
7
5
6
7
I/O
I/O
I/O
TTL
ST
RA3 can also be analog input3 or positive analog reference
voltage
RA4 can also be the clock input to the Timer0 module. Output
is open drain type.
TTL
RA5 can also be analog input4
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
RB0/INT
21
21
I/O
RB0 can also be the external interrupt pin.
TTL/ST
TTL
RB1
22
23
24
22
23
24
I/O
I/O
I/O
RB2
TTL
(1)
RB3/PGM
RB3 can also be the low voltage programming input
TTL/ST
TTL
RB4
25
26
27
25
26
27
I/O
I/O
I/O
Interrupt on change pin.
Interrupt on change pin.
RB5
TTL
(2)
(2)
RB6/PGC
Interrupt on change pin or In-Circuit Debugger pin. Serial
programming clock.
TTL/ST
RB7/PGD
28
11
28
11
I/O
I/O
Interrupt on change pin or In-Circuit Debugger pin. Serial
programming data.
TTL/ST
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
ST
RC0 can also be the Timer1 oscillator output or Timer1 clock
input.
RC1/T1OSI
RC2/CCP1
12
13
12
13
I/O
I/O
ST
ST
RC1 can also be the Timer1 oscillator input
RC2 can also be the Capture1 input/Compare1 output/PWM1
output.
RC3
14
15
16
17
14
15
16
17
I/O
I/O
I/O
I/O
ST
ST
ST
ST
RC4
RC5
RC6/TX/CK
RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
18
18
I/O
ST
RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
VSS
8, 19
20
8, 19
20
P
P
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
VDD
Legend: I = input
O = output
— = Not used
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt or LVP mode.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 7
PIC16F870/871
TABLE 1-2:
PIC16F871 PINOUT DESCRIPTION
DIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
(4)
OSC1/CLKIN
13
14
14
15
30
31
I
Oscillator crystal input/external clock source input.
ST/CMOS
OSC2/CLKOUT
O
—
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs CLK-
OUT which has 1/4 the frequency of OSC1, and denotes the
instruction cycle rate.
MCLR/VPP/THV
1
2
18
I/P
ST
Master clear (reset) input or programming voltage input or high
voltage test mode control. This pin is an active low reset to the
device.
PORTA is a bi-directional I/O port.
RA0 can also be analog input0
RA1 can also be analog input1
RA0/AN0
2
3
4
3
4
5
19
20
21
I/O
I/O
I/O
TTL
TTL
TTL
RA1/AN1
RA2/AN2/VREF-
RA2 can also be analog input2 or negative analog
reference voltage
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4
5
6
7
6
7
8
22
23
24
I/O
I/O
I/O
TTL
ST
RA3 can also be analog input3 or positive analog
reference voltage
RA4 can also be the clock input to the Timer0 timer/
counter. Output is open drain type.
TTL
RA5 can also be analog input4
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
RB0/INT
33
36
8
I/O
RB0 can also be the external interrupt pin.
TTL/ST
TTL
RB1
34
35
36
37
38
39
9
I/O
I/O
I/O
RB2
10
11
TTL
(1)
RB3/PGM
RB3 can also be the low voltage programming input
TTL/ST
TTL
RB4
37
38
39
41
42
43
14
15
16
I/O
I/O
I/O
Interrupt on change pin.
Interrupt on change pin.
RB5
TTL
(2)
(2)
RB6/PGC
Interrupt on change pin or In-Circuit Debugger pin. Serial
programming clock.
TTL/ST
RB7/PGD
40
15
44
16
17
32
I/O
I/O
Interrupt on change pin or In-Circuit Debugger pin. Serial
programming data.
TTL/ST
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
ST
RC0 can also be the Timer1 oscillator output or a Timer1
clock input.
RC1/T1OSI
RC2/CCP1
16
17
18
19
35
36
I/O
I/O
ST
ST
RC1 can also be the Timer1 oscillator input
RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3
18
23
24
25
20
25
26
27
37
42
43
44
I/O
I/O
I/O
I/O
ST
ST
ST
ST
RC4
RC5
RC6/TX/CK
RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
26
29
1
I/O
ST
RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
Legend: I = input
O = output
— = Not used
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt or LVP mode.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave
Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS30569A-page 8
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
TABLE 1-2:
PIC16F871 PINOUT DESCRIPTION (CONTINUED)
DIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
PORTD is a bi-directional I/O port or parallel slave port when
interfacing to a microprocessor bus.
(3)
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
19
20
21
22
27
28
29
30
21
22
23
24
30
31
32
33
38
39
40
41
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
(3)
(3)
(3)
(3)
(3)
(3)
(3)
3
4
5
PORTE is a bi-directional I/O port.
(3)
(3)
(3)
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
8
9
9
25
26
27
I/O
I/O
I/O
RE0 can also be read control for the parallel slave port, or
analog input5.
ST/TTL
ST/TTL
ST/TTL
10
11
RE1 can also be write control for the parallel slave port, or
analog input6.
10
RE2 can also be select control for the parallel slave port,
or analog input7.
VSS
VDD
NC
12,31
11,32
—
13,34
6,29
P
—
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
12,35
7,28
P
1,17,28, 12,13,
40 33,34
These pins are not internally connected. These pins should be
left unconnected.
Legend: I = input
O = output
— = Not used
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt or LVP mode.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave
Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 9
PIC16F870/871
NOTES:
DS30569A-page 10
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
2.2
Data Memory Organization
2.0
MEMORY ORGANIZATION
There are three memory blocks in each of these
PICmicro® MCUs. The Program Memory and Data
Memory have separate buses, so that concurrent
access can occur, and is detailed in this section. The
EEPROM data memory block is detailed in
Section 4.0.
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1(STATUS<6>) and
RP0 (STATUS<5>) are the bank select bits.
RP<1:0>
00
Bank
0
1
2
3
Additional information on device memory may be found
01
in the PICmicro
(DS33023).
Mid-Range Reference Manual,
10
11
2.1
Program Memory Organization
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some “high use” Special Function
Registers from one bank may be mirrored in another
bank for code reduction and quicker access.
The PIC16F870/871 devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. The PIC16F870/871 devices have 2K
x 14 words of FLASH program memory. Accessing a
location above the physically implemented address will
cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
Note: EEPROM Data Memory description can be
found in Section 4.0 of this Data Sheet
FIGURE 2-1: PIC16F870/871 PROGRAM
MEMORY MAP AND STACK
2.2.1
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indi-
rectly through the File Select Register FSR.
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
0000h
Interrupt Vector
Page 0
0004h
0005h
On-Chip
Program
Memory
07FFh
0800h
1FFFh
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 11
PIC16F870/871
FIGURE 2-2: PIC16F870/871 REGISTER FILE MAP
File
Address
File
Address
File
Address
File
Address
Indirect addr.(*)
Indirect addr.(*)
OPTION_REG
PCL
Indirect addr.(*)
Indirect addr.(*)
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
80h
TMR0
PCL
TMR0
PCL
OPTION_REG 81h
PCL
STATUS
FSR
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
STATUS
FSR
STATUS
FSR
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(2)
PORTE(2)
PCLATH
INTCON
PIR1
TRISA
TRISB
TRISB
PORTB
TRISC
TRISD(2)
TRISE(2)
PCLATH
INTCON
PCLATH
INTCON
EECON1
EECON2
Reserved(1)
Reserved(1)
PCLATH
INTCON
PIE1
EEDATA
EEADR
PIR2
PIE2
TMR1L
TMR1H
T1CON
TMR2
PCON
EEDATH
EEADRH
T2CON
PR2
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXSTA
SPBRG
TXREG
RCREG
ADRESL
ADCON1
ADRESH
ADCON0
1A0h
120h
A0h
General
Purpose
Register
accesses
A0h - BFh
accesses
20h-7Fh
General
Purpose
Register
32 Bytes
1BFh
1C0h
BFh
C0h
96 Bytes
16Fh
170h
1EFh
1F0h
EFh
F0h
accesses
70h-7Fh
accesses
70h-7Fh
accesses
70h-7Fh
17Fh
1FFh
7Fh
FFh
Bank 3
Bank 1
Bank 2
Bank 0
Unimplemented data memory locations, read as ’0’.
* Not a physical register.
Note 1: These registers are reserved; maintain these registers clear.
2: These registers are not implemented on the PIC16F870.
DS30569A-page 12
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers can be classified into
two sets; core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY
Value on
Value on:
POR,
BOR
all other
resets
(2)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0
00h(4)
01h
INDF
TMR0
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
02h(4)
03h(4)
PCL
Program Counter's (PC) Least Significant Byte
STATUS
FSR
IRP
Indirect data memory address pointer
PORTA Data Latch when written: PORTA pins when read
RP1
RP0
TO
PD
Z
DC
C
04h(4)
05h
PORTA
PORTB
PORTC
—
—
--0x 0000 --0u 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
06h
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
07h
08h(5)
PORTD
PORTE
PCLATH
INTCON
PIR1
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
---0 0000 ---0 0000
0000 000x 0000 000u
09h(5)
0Ah(1,4)
0Bh(4)
0Ch
—
—
—
—
—
—
—
—
RE2
RE1
RE0
Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE
ADIF
—
T0IE
RCIF
—
INTE
TXIF
EEIF
RBIE
—
T0IF
CCP1IF
—
INTF
TMR2IF
—
RBIF
PSPIF(3)
—
TMR1IF 0000 -000 0000 -000
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
PIR2
—
—
---0 ---- ---0 ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR1L
TMR1H
T1CON
TMR2
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Timer2 module’s register
0000 0000 0000 0000
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCPR1L
CCPR1H
CCP1CON
RCSTA
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
CCP1X
SREN
CCP1Y
CREN
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
SPEN
RX9
ADDEN
FERR
OERR
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
0000 0000 0000 0000
TXREG
USART Transmit Data Register
USART Receive Data Register
RCREG
ADRESH
ADCON0
A/D Result Register High Byte
xxxx xxxx uuuu uuuu
0000 00-0 0000 00-0
GO/
DONE
1Fh
ADCS1
ADCS0
CHS2
CHS1
CHS0
—
ADON
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 13
PIC16F870/871
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on
all other
resets
(2)
Value on:
POR,
BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 1
80h(4)
81h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
OPTION_REG
PCL
RBPU
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect data memory address pointer
PORTA Data Direction Register
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
82h(4)
83h(4)
STATUS
FSR
PD
Z
DC
C
84h(4)
85h
TRISA
TRISB
TRISC
TRISD
—
—
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
86h
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
87h
88h(5)
89h(5)
TRISE
PCLATH
INTCON
PIE1
IBF
—
OBF
—
IBOV
—
PSPMODE
—
PORTE Data Direction Bits
0000 -111 0000 -111
---0 0000 ---0 0000
0000 000x 0000 000u
8Ah(1,4)
8Bh(4)
8Ch
Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
PSPIE(3)
ADIE
—
RCIE
—
TXIE
EEIE
—
—
—
—
CCP1IE
TMR2IE
—
TMR1IE 0000 -000 0000 -000
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
PIE2
PCON
—
—
—
—
—
—
---0 ---- ---0 ----
---- --qq ---- --uu
—
—
POR
BOR
Unimplemented
Unimplemented
—
—
—
—
—
PR2
Timer2 Period Register
1111 1111 1111 1111
—
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
TXSTA
SPBRG
—
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
Baud Rate Generator Register
Unimplemented
—
—
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
—
Unimplemented
ADRESL
ADCON1
A/D Result Register Low Byte
xxxx xxxx uuuu uuuu
PCFG0 0---0000 0---0000
ADFM
—
—
—
PCFG3
PCFG2
PCFG1
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
DS30569A-page 14
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on
Value on:
POR,
BOR
all other
resets
(2)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 2
100h(4)
101h
INDF
TMR0
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000
0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
102h(4)
103h(4)
PCL
Program Counter's (PC) Least Significant Byte
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
104h(4)
105h
106h
107h
108h
109h
FSR
—
Indirect data memory address pointer
Unimplemented
xxxx xxxx uuuu uuuu
—
—
PORTB
—
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
10Ah(1,4)
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
INTE RBIE T0IF INTF RBIF
---0 0000 ---0 0000
0000 000x 0000 000u
10Bh(4)
10Ch
10Dh
10Eh
10Fh
INTCON
GIE
PEIE
T0IE
EEDATA
EEADR
EEPROM data register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
EEPROM address register
EEDATH
EEADRH
—
—
—
—
EEPROM data register high byte
EEPROM address register high byte
—
Bank 3
180h(4)
181h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
OPTION_REG
PCL
RBPU
Program Counter's (PC) Least Significant Byte
IRP RP1 RP0 TO
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
182h(4)
183h(4)
STATUS
PD
Z
DC
C
184h(4)
185h
186h
187h
188h
189h
FSR
—
Indirect data memory address pointer
Unimplemented
—
—
TRISB
—
PORTB Data Direction Register
Unimplemented
1111 1111 1111 1111
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
18Ah(1,4)
Write Buffer for the upper 5 bits of the Program Counter
PCLATH
—
—
PEIE
—
—
T0IE
—
---0 0000 ---0 0000
18Bh(4)
18Ch
18Dh
18Eh
18Fh
INTCON
EECON1
EECON2
—
GIE
INTE
—
RBIE
T0IF
INTF
WR
RBIF
RD
0000 000x 0000 000u
x--- x000 x--- u000
---- ---- ---- ----
0000 0000 0000 0000
0000 0000 0000 0000
EEPGD
WRERR
WREN
EEPROM control register2 (not a physical register)
Reserved maintain clear
—
Reserved maintain clear
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 15
PIC16F870/871
2.2.2.1
STATUS REGISTER
For example, CLRF STATUSwill clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
The STATUS Register contains the arithmetic status of
the ALU, the RESET status and the bank select bits for
data memory.
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C or DC bits from the STATUS Register.
For other instructions not affecting any status bits, see
the "Instruction Set Summary."
The STATUS Register can be the destination for any
instruction, as with any other register. If the STATUS
Register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable, therefore, the result of an instruction with the
STATUS Register as destination may be different than
intended.
Note 1: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0
IRP
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
bit0
- n= Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing)
1= Bank 2, 3 (100h - 1FFh)
0= Bank 0, 1 (00h - FFh)
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11= Bank 3 (180h - 1FFh)
10= Bank 2 (100h - 17Fh)
01= Bank 1 (80h - FFh)
00= Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4:
bit 3:
bit 2:
bit 1:
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)
(for borrow the polarity is reversed)
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
bit 0:
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1= A carry-out from the most significant bit of the result occurred
0= No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of
the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order
bit of the source register.
DS30569A-page 16
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
2.2.2.2
OPTION_REG REGISTER
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
The OPTION_REG Register is a readable and writable
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
able register known also as the prescaler), the External
INT Interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h)
R/W-1 R/W-1
RBPU INTEDG
bit7
R/W-1 R/W-1 R/W-1 R/W-1
T0CS T0SE PSA PS2
R/W-1 R/W-1
PS1
PS0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit0
- n= Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
RBPU: PORTB Pull-up Enable bit
1= PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 17
PIC16F870/871
2.2.2.3
INTCON REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The INTCON Register is a readable and writable regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
- n= Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit
1= Enables all un-masked interrupts
0= Disables all interrupts
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
PEIE: Peripheral Interrupt Enable bit
1= Enables all un-masked peripheral interrupts
0= Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1= Enables the RB0/INT external interrupt
0= Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1= The RB0/INT external interrupt occurred (must be cleared in software)
0= The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
DS30569A-page 18
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
2.2.2.4
PIE1 REGISTER
Note: Bit PEIE (INTCON<6>) must be set to
The PIE1 Register contains the individual enable bits
for the peripheral interrupts.
enable any peripheral interrupt.
REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
PSPIE(1) ADIE
R/W-0
R/W-0
RCIE
R/W-0
TXIE
U-0
R/W-0
R/W-0
R/W-0
CCP1IE TMR2IE TMR1IE
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
bit0
- n= Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D converter interrupt
0= Disables the A/D converter interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
bit 3:
bit 2:
Unimplemented: Read as ‘0’
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
bit 1:
bit 0:
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Note 1: PSPIE is reserved on the PIC16F870; always maintain this bit clear.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 19
PIC16F870/871
2.2.2.5
PIR1 REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt bits are clear prior to enabling an
interrupt.
The PIR1 Register contains the individual flag bits for
the peripheral interrupts.
REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)
R/W-0
R/W-0
R-0
R-0
U-0
R/W-0
R/W-0
R/W-0
PSPIF(1) ADIF
RCIF
TXIF
CCP1IF TMR2IF TMR1IF
bit0
R = Readable bit
W = Writable bit
- n= Value at POR reset
bit7
(1)
bit 7:
bit 6:
bit 5:
bit 4:
PSPIF : Parallel Slave Port Read/Write Interrupt Flag bit
1= A read or a write operation has taken place (must be cleared in software)
0= No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed
0= The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1= The USART receive buffer is full
0= The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1= The USART transmit buffer is empty
0= The USART transmit buffer is full
bit 7:
Unimplemented: Read as ‘0’
bit 2:
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare Mode
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1:
bit 0:
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Note 1: PSPIF is reserved on the PIC16F870; always maintain this bit clear.
DS30569A-page 20
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
2.2.2.6
PIE2 REGISTER
The PIE2 Register contains the individual enable bit for
the EEPROM write operation interrupt.
REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh)
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
—
—
—
EEIE
—
—
—
—
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
bit0
- n= Value at POR reset
bit 7-5: Unimplemented: Read as '0'
bit 4:
EEIE: EEPROM Write Operation Interrupt Enable
1= Enable EE Write Interrupt
0= Disable EE Write Interrupt
bit 3-0: Unimplemented: Read as '0'
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 21
PIC16F870/871
.
2.2.2.7
PIR2 REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The PIR2 Register contains the flag bit for the
EEPROM write operation interrupt.
REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh)
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
—
—
—
EEIF
—
—
—
—
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
bit0
- n= Value at POR reset
bit 7-5: Unimplemented: Read as '0'
bit 4: EEIF: EEPROM Write Operation Interrupt Flag bit
1= The write operation completed (must be cleared in software)
0= The write operation is not complete or has not been started
bit 3-0: Unimplemented: Read as '0'
DS30569A-page 22
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
2.2.2.8
PCON REGISTER
Note: BOR is unknown on POR. It must be set by
the user and checked on subsequent rests
to see if BOR is clear, indicating a brown-
out has occurred. The BOR status bit is a
don’t care and is not predictable if the
brown-out circuit is disabled (by clearing
the BODEN bit in the configuration word).
The Power Control (PCON) Register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watch-dog Reset
(WDT) and an external MCLR Reset.
REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
POR
R/W-1
BOR
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
bit0
- n= Value at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1:
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
BOR: Brown-out Reset Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 23
PIC16F870/871
2.3
PCL and PCLATH
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
The Program Counter (PC) is 13-bits wide. The low
byte comes from the PCL Register, which is a readable
and writable register. The upper bits (PC<12:8>) are
not readable, but are indirectly writable through the
PCLATH register. On any reset, the upper bits of the PC
will be cleared. Figure 2-3 shows the two situations for
the loading of the PC. The upper example in the figure
shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the fig-
ure shows how the PC is loaded during a CALLor GOTO
instruction (PCLATH<4:3> → PCH).
2: There are no instructions/mnemonics
called PUSHor POP. These are actions that
occur from the execution of the CALL,
RETURN, RETLW and RETFIE instruc-
tions or the vectoring to an interrupt
address.
2.4
Program Memory Paging
The PIC16FXXX architecture is capable of addressing
a continuous 8K word block of program memory. The
CALL and GOTO instructions provide 11 bits of the
address, which allows branches within any 2K program
memory page. Therefore, the 8K words of program
memory are broken into four pages. Since the
PIC16F872 has only 2K words of program memory or
one page, additional code is not required to ensure that
the correct page is selected before a CALL or GOTO
instruction is executed. The PCLATH<4:3> bits should
always be maintained as zeros. If a return from a CALL
instruction (or interrupt) is executed, the entire 13-bit
PC is popped off the stack. Manipulation of the
PCLATH is not required for the return instructions.
FIGURE 2-3: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
Instruction with
PCL as
PC
Destination
8
PCLATH<4:0>
PCLATH
5
ALU
PCH
12 11 10
PCL
2.5
Indirect Addressing, INDF and FSR
Registers
8
7
0
GOTO,CALL
PC
The INDF Register is not a physical register. Address-
ing the INDF Register will cause indirect addressing.
PCLATH<4:3>
PCLATH
11
2
Opcode <10:0>
Indirect addressing is possible by using the INDF Reg-
ister. Any instruction using the INDF Register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF Register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF Register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR Register and the IRP bit
(STATUS<7>), as shown in Figure 2-4.
2.3.1
COMPUTED GOTO
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-1.
application note, “Implementing
a
Table Read"
(AN556).
EXAMPLE 2-1: INDIRECT ADDRESSING
2.3.2
STACK
movlw
movwf
clrf
incf
btfss
goto
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
The PIC16FXXX family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the stack pointer is
not readable or writable. The PC is PUSHed onto the
stack when a CALLinstruction is executed or an inter-
rupt causes a branch. The stack is POPed in the event
of a RETURN,RETLW or a RETFIE instruction execu-
tion. PCLATH is not affected by a PUSHor POPopera-
tion.
NEXT
CONTINUE
:
;yes continue
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
DS30569A-page 24
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
FIGURE 2-4: DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
from opcode
7
RP1:RP0
6
0
0
IRP
FSR register
bank select
location select
bank select
location select
00
01
80h
10
100h
11
00h
180h
Data
Memory
(1)
7Fh
Bank 0
FFh
Bank 1
17Fh
Bank 2
1FFh
Bank 3
Note 1: For register file map detail see Figure 2-2.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 25
PIC16F870/871
NOTES:
DS30569A-page 26
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
FIGURE 3-1: BLOCK DIAGRAM OF
3.0
I/O PORTS
RA3:RA0 AND RA5 PINS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Data
Bus
D
Q
VDD
WR
Port
Additional information on I/O ports may be found in the
PICmicro™
(DS33023).
Q
CK
Mid-Range
Reference
Manual,
P
Data Latch
D
3.1
PORTA and the TRISA Register
I/O pin(1)
N
Q
PORTA is a 6-bit wide bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISA bit (=0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
WR
TRIS
VSS
Analog
Input
Q
CK
TRIS Latch
Mode
TTL
RD TRIS
Input
Buffer
Reading the PORTA Register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
Q
D
EN
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
RD PORT
To A/D Converter
Note 1: I/O pins have protection diodes to VDD and VSS.
Other PORTA pins are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 Register (A/D Control Register1).
FIGURE 3-2: BLOCK DIAGRAM OF RA4/
T0CKI PIN
Note: On a Power-on Reset, these pins are con-
Data
Bus
figured as analog inputs and read as '0'.
D
Q
Q
The TRISA Register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA Register
are maintained set when using them as analog inputs.
WR
PORT
CK
I/O pin(1)
N
Data Latch
D
Q
VSS
EXAMPLE 3-1: INITIALIZING PORTA
WR
TRIS
BCF
BCF
CLRF
STATUS, RP0
STATUS, RP1
PORTA
;
Schmitt
Trigger
Input
Q
CK
; Bank0
; Initialize PORTA by
; clearing output
; data latches
TRIS Latch
Buffer
BSF
STATUS, RP0
0x06
ADCON1
0xCF
; Select Bank 1
; Configure all pins
; as digital inputs
; Value used to
; initialize data
; direction
RD TRIS
MOVLW
MOVWF
MOVLW
Q
D
EN
RD PORT
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as ’0’.
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 27
PIC16F870/871
TABLE 3-1:
Name
PORTA FUNCTIONS
Bit#
Buffer
Function
RA0/AN0
bit0
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
ST
Input/output or analog input
Input/output or analog input
Input/output or analog input
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
Input/output or analog input or VREF
Input/output or external clock input for Timer0
Output is open drain type
RA5/AN4
bit5
TTL
Input/output or analog input
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 3-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
all
other
resets
Value on:
POR,
BOR
Address Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
--0x 0000 --0u 0000
--11 1111 --11 1111
--0- 0000 --0- 0000
05h
85h
9Fh
PORTA
—
—
—
—
—
RA5
RA4
RA3
RA2
RA1
RA0
TRISA
PORTA Data Direction Register
PCFG3 PCFG2 PCFG1 PCFG0
ADCON1 ADFM
—
—
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by
PORTA.
DS30569A-page 28
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
rupt in the following manner:
3.2
PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
Three pins of PORTB are multiplexed with the Low Volt-
age Programming function; RB3/PGM, RB6/PGC and
RB7/PGD. The alternate functions of these pins are
described in the Special Features Section.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
This interrupt on mismatch feature, together with soft-
ware configurable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key-depression. Refer to the Embedded
Control Handbook, “Implementing Wake-Up on Key
Stroke” (AN552).
FIGURE 3-3: BLOCK DIAGRAM OF
RB3:RB0 PINS
RB0/INT is an external interrupt input pin and is config-
ured using the INTEDG bit (OPTION_REG<6>).
VDD
RBPU(2)
weak
pull-up
RB0/INT is discussed in detail in Section 11.10.1.
P
Data Latch
Data Bus
WR Port
D
Q
FIGURE 3-4: BLOCK DIAGRAM OF
I/O
pin(1)
RB7:RB4 PINS
CK
TRIS Latch
VDD
RBPU(2)
weak
P
D
Q
pull-up
TTL
Data Latch
Data Bus
Input
Buffer
WR TRIS
CK
D
Q
I/O
pin(1)
WR Port
CK
TRIS Latch
RD TRIS
RD Port
D
Q
Q
D
WR TRIS
TTL
Input
Buffer
CK
EN
ST
Buffer
RB0/INT
RB3/PGM
RD TRIS
RD Port
Latch
Schmitt Trigger
Buffer
RD Port
Q
Q
D
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
EN
Q1
Set RBIF
D
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e. any RB7:RB4 pin con-
figured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
From other
RB7:RB4 pins
RD Port
Q3
EN
RB7:RB6 in serial programming mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 29
PIC16F870/871
TABLE 3-3:
PORTB FUNCTIONS
Name
Bit#
Buffer
Function
RB0/INT
bit0
TTL/ST(1)
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1
bit1
bit2
bit3
TTL
TTL
TTL/ST(1)
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
RB2
RB3/PGM
Input/output pin or programming pin in LVP mode. Internal software
programmable weak pull-up.
RB4
bit4
bit5
bit6
bit7
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB5
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB6/PGC
RB7/PGD
TTL/ST(2)
TTL/ST(2)
Input/output pin (with interrupt on change) or In-Circuit Debugger pin.
Internal software programmable weak pull-up. Serial programming clock.
Input/output pin (with interrupt on change) or In-Circuit Debugger pin.
Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt or LVP mode.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 3-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on: Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
POR,
BOR
other
resets
06h, 106h
86h, 186h
81h, 181h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
PS2
RB1
PS1
RB0 xxxx xxxx uuuu uuuu
1111 1111 1111 1111
TRISB
PORTB Data Direction Register
RBPU INTEDG T0CS T0SE PSA
OPTION_REG
PS0 1111 1111 1111 1111
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.
DS30569A-page 30
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
3.3
PORTC and the TRISC Register
PORTC is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (=1) will make the corresponding PORTC pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISC bit (=0) will
make the corresponding PORTC pin an output (i.e., put
the contents of the output latch on the selected pin).
PORTC is multiplexed with several peripheral functions
(Table 3-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
FIGURE 3-5: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE)
PORT/PERIPHERAL Select(2)
Peripheral Data Out
VDD
0
Data Bus
D
Q
Q
P
WR
1
PORT
CK
Data Latch
I/O
pin(1)
D
Q
Q
WR
TRIS
CK
N
TRIS Latch
VSS
Schmitt
Trigger
RD TRIS
Peripheral
OE(3)
Q
D
EN
RD
PORT
Peripheral Input
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port
data and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 31
PIC16F870/871
TABLE 3-5:
Name
PORTC FUNCTIONS
Bit# Buffer Type
Function
RC0/T1OSO/T1CKI bit0
ST
ST
ST
Input/output port pin or Timer1 oscillator output/Timer1 clock input
Input/output port pin or Timer1 oscillator input
RC1/T1OSI
RC2/CCP1
bit1
bit2
Input/output port pin or Capture1 input/Compare1 output/PWM1
output
RC3
bit3
bit4
bit5
bit6
ST
ST
ST
ST
Input/output port pin
Input/output port pin
Input/output port pin
RC4
RC5
RC6/TX/CK
Input/output port pin or USART Asynchronous Transmit or Synchro-
nous Clock
RC7/RX/DT
bit7
ST
Input/output port pin or USART Asynchronous Receive or Synchro-
nous Data
Legend: ST = Schmitt Trigger input
TABLE 3-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on
all
other
resets
Value on:
POR,
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
07h
87h
PORTC RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
TRISC PORTC Data Direction Register
Legend: x= unknown, u= unchanged.
DS30569A-page 32
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
3.4
PORTD and TRISD Registers
FIGURE 3-6: PORTD BLOCK DIAGRAM (IN
I/O PORT MODE)
This section is not applicable to the PIC16F870.
Data
Bus
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.
D
Q
WR
PORT
I/O pin(1)
CK
Data Latch
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL.
D
Q
WR
TRIS
Schmitt
Trigger
Input
CK
TRIS Latch
Buffer
RD TRIS
Q
D
EN
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 3-7:
Name
PORTD FUNCTIONS
Bit#
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Buffer Type
Function
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
Input/output port pin or parallel slave port bit0
Input/output port pin or parallel slave port bit1
Input/output port pin or parallel slave port bit2
Input/output port pin or parallel slave port bit3
Input/output port pin or parallel slave port bit4
Input/output port pin or parallel slave port bit5
Input/output port pin or parallel slave port bit6
Input/output port pin or parallel slave port bit7
Legend: ST = Schmitt Trigger input TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port Mode.
TABLE 3-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on:
POR,
BOR
Value on all
other resets
Address
Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
RD3
—
Bit 2
Bit 1
Bit 0
08h
88h
89h
PORTD
TRISD
TRISE
RD7
RD6
RD5
RD4
RD2
RD1
RD0
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 -111 0000 -111
PORTD Data Direction Register
IBF OBF IBOV PSPMODE
PORTE Data Direction Bits
Legend: x= unknown, u= unchanged, -= unimplemented read as ’0’. Shaded cells are not used by PORTD.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 33
PIC16F870/871
3.5
PORTE and TRISE Register
FIGURE 3-7: PORTE BLOCK DIAGRAM (IN
I/O PORT MODE)
This section is not applicable to the PIC16F870.
Data
Bus
PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7, which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
D
Q
WR
PORT
I/O pin(1)
CK
Data Latch
I/O PORTE becomes control inputs for the micropro-
cessor port when bit PSPMODE (TRISE<4>) is set. In
this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs). Ensure ADCON1 is configured for digital I/O. In
this mode, the input buffers are TTL.
D
Q
WR
TRIS
Schmitt
Trigger
input
CK
TRIS Latch
buffer
Register 3-1 shows the TRISE Register, which also
controls the parallel slave port operation.
RD TRIS
PORTE pins are multiplexed with analog inputs. When
selected as an analog input, these pins will read as ’0’s.
Q
D
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
EN
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
Note: On a Power-on Reset, these pins are con-
figured as analog inputs.
REGISTER 3-1: TRISE REGISTER (ADDRESS 89h)
R-0
IBF
bit7
R-0
R/W-0
IBOV
R/W-0
U-0
R/W-1
R/W-1
R/W-1
bit0
OBF
PSPMODE
—
bit2
bit1
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit0
- n= Value at POR reset
Parallel Slave Port Status/Control Bits
bit 7 :
IBF: Input Buffer Full Status bit
1= A word has been received and is waiting to be read by the CPU
0= No word has been received
bit 6:
bit 5:
bit 4:
OBF: Output Buffer Full Status bit
1= The output buffer still holds a previously written word
0= The output buffer has been read
IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1= A write occurred when a previously input word has not been read (must be cleared in software)
0= No overflow occurred
PSPMODE: Parallel Slave Port Mode Select bit
1= Parallel slave port mode
0= General purpose I/O mode
bit 3:
bit 2:
Unimplemented: Read as ’0’
PORTE Data Direction Bits
Bit2: Direction Control bit for pin RE2/CS/AN7
1= Input
0= Output
bit 1:
bit 0:
Bit1: Direction Control bit for pin RE1/WR/AN6
1= Input
0= Output
Bit0: Direction Control bit for pin RE0/RD/AN5
1= Input
0= Output
DS30569A-page 34
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
TABLE 3-9:
Name
PORTE FUNCTIONS
Bit#
Buffer Type
Function
ST/TTL(1)
Input/output port pin or read control input in parallel slave port mode or
analog input:
RE0/RD/AN5
bit0
RD
1= Not a read operation
0= Read operation. Reads PORTD register (if chip selected)
ST/TTL(1)
ST/TTL(1)
Input/output port pin or write control input in parallel slave port mode or
analog input:
WR
1= Not a write operation
0= Write operation. Writes PORTD register (if chip selected)
RE1/WR/AN6
RE2/CS/AN7
bit1
bit2
Input/output port pin or chip select control input in parallel slave port
mode or analog input:
CS
1= Device is not selected
0= Device is selected
Legend: ST = Schmitt Trigger input TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.
TABLE 3-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on:
POR,
BOR
Value on all
other resets
Addr
Name
Bit 7
Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
09h
89h
9Fh
PORTE
—
—
—
—
—
—
RE2
RE1
RE0
---- -xxx ---- -uuu
0000 -111 0000 -111
TRISE
IBF
OBF IBOV PSPMODE
PORTE Data Direction Bits
ADCON1 ADFM
—
—
—
PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PORTE.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 35
PIC16F870/871
3.6
Parallel Slave Port
FIGURE 3-8: PORTD AND PORTE BLOCK
DIAGRAM (PARALLEL SLAVE
PORT)
The Parallel Slave Port is not implemented on the
PIC16F870.
PORTD operates as an 8-bit wide Parallel Slave Port or
microprocessor port when control bit PSPMODE
(TRISE<4>) is set. In slave mode, it is asynchronously
readable and writable by the external world through RD
control input pin RE0/RD and WR control input pin
RE1/WR.
Data Bus
D
Q
WR
PORT
RDx
pin
CK
TTL
Q
D
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set). The A/D port con-
figuration bits PCFG3:PCFG0 (ADCON1<3:0>) must
be set to configure pins RE2:RE0 as digital I/O.
RD
PORT
EN
One bit of PORTD
Set interrupt flag
PSPIF (PIR1<7>)
There are actually two 8-bit latches. One for data-out
and one for data input. The user writes 8-bit data to the
PORTD data latch and reads data from the port pin
latch (note that they have the same address). In this
mode, the TRISD register is ignored, since the micro-
processor is controlling the direction of data flow.
Read
RD
CS
WR
TTL
Chip Select
TTL
Write
TTL
A write to the PSP occurs when both the CS and WR
lines are first detected low. When either the CS or WR
lines become high (level triggered), the Input Buffer Full
(IBF) status flag bit (TRISE<7>) is set on the Q4 clock
cycle, following the next Q2 cycle, to signal the write is
complete (Figure 3-9). The interrupt flag bit PSPIF
(PIR1<7>) is also set on the same Q4 clock cycle. IBF
can only be cleared by reading the PORTD input latch.
The Input Buffer Overflow (IBOV) status flag bit
(TRISE<5>) is set if a second write to the PSP is
attempted when the previous byte has not been read
out of the buffer.
Note: I/O pin has protection diodes to VDD and VSS.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The Output Buffer Full
(OBF) status flag bit (TRISE<6>) is cleared immedi-
ately (Figure 3-10) indicating that the PORTD latch is
waiting to be read by the external bus. When either the
CS or RD pin becomes high (level triggered), the inter-
rupt flag bit PSPIF is set on the Q4 clock cycle, follow-
ing the next Q2 cycle, indicating that the read is
complete. OBF remains low until data is written to
PORTD by the user firmware.
When not in PSP mode, the IBF and OBF bits are held
clear. However, if flag bit IBOV was previously set, it
must be cleared in firmware.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the user in firmware and the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7>).
DS30569A-page 36
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
FIGURE 3-9: PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 3-10: PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 3-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on:
POR,
BOR
Value on all
other resets
Address
Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
08h
09h
89h
0Ch
8Ch
9Fh
PORTD Port data latch when written: Port pins when read
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
0000 -111 0000 -111
PORTE
TRISE
PIR1
—
—
—
—
—
—
—
—
RE2
RE1
RE0
IBF
OBF IBOV PSPMODE
PORTE Data Direction Bits
PSPIF ADIF RCIF
PSPIE ADIE RCIE
TXIF
TXIE
—
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIE1
ADCON1 ADFM
—
—
PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 37
PIC16F870/871
NOTES:
DS30569A-page 38
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
The value written to program memory does not need to
be a valid instruction. Therefore, up to 14-bit numbers
can be stored in memory for use as calibration param-
eters, serial numbers, packed 7-bit ASCII, etc. Execut-
ing a program memory location containing data that
forms an invalid instruction results in a NOP.
4.0
DATA EEPROM AND FLASH
PROGRAM MEMORY
The Data EEPROM and FLASH Program Memory are
readable and writable during normal operation over the
entire VDD range. A bulk erase operation may not be
issued from user code (which includes removing code
protection). The data memory is not directly mapped in
4.1
EEADR
the register file space.
addressed through the Special Function Registers
(SFR).
Instead, it is indirectly
The address registers can address up to a maximum of
256 bytes of data EEPROM or up to a maximum of 8K
words of program FLASH. However, the PIC16F870/
871 have 64 bytes of data EEPROM and 2K words of
program FLASH.
There are six SFRs used to read and write the program
and data EEPROM memory. These registers are:
• EECON1
• EECON2
• EEDATA
• EEDATH
• EEADR
When selecting a program address value, the MSByte
of the address is written to the EEADRH register and
the LSByte is written to the EEADR register. When
selecting a data address value, only the LSByte of the
address is written to the EEADR register.
On the PIC16F870/871 devices, the upper two bits of
the EEADR must always be cleared to prevent inad-
vertent access to the wrong location in data EEPROM.
This also applies to the program memory. The upper
five MSbits of EEADRH must always be clear during
program FLASH access.
• EEADRH
The EEPROM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed. The
registers EEDATH and EEADRH are not used for data
EEPROM access. The PIC16F870/871 devices have
64 bytes of data EEPROM with an address range from
0h to 3Fh.
4.2
EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the memory write sequence.
The EEPROM data memory is rated for high erase/
write cycles. The write time is controlled by an on-chip
timer. The write time will vary with voltage and temper-
ature, as well as from chip-to-chip. Please refer to the
specifications for exact limits.
Control bit EEPGD determines if the access will be a
program or a data memory access. When clear, any
subsequent operations will operate on the data mem-
ory. When set, any subsequent operations will operate
on the program memory.
The program memory allows word reads and writes.
Program memory access allows for checksum calcula-
tion and calibration table storage. A byte or word write
automatically erases the location and writes the new
data (erase before write). Writing to program memory
will cease operation until the write is complete. The pro-
gram memory cannot be accessed during the write,
therefore code cannot execute. During the write opera-
tion, the oscillator continues to clock the peripherals,
and therefore, they continue to operate. Interrupt
events will be detected and essentially “queued” until
the write is completed. When the write completes, the
next instruction in the pipeline is executed and the
branch to the interrupt vector address will occur.
Control bits RD and WR initiate read and write opera-
tions, respectively. These bits cannot be cleared, only
set, in software. They are cleared in hardware at the
completion of the read or write operation. The inability
to clear the WR bit in software prevents the accidental
or premature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
reset or a WDT time-out reset during normal operation.
In these situations, following reset, the user can check
the WRERR bit and rewrite the location. The value of
the data and address registers and the EEPGD bit
remains unchanged.
When interfacing to the program memory block, the
EEDATH:EEDATA registers form a two byte word,
which holds the 14-bit data for read/write. The
EEADRH:EEADR registers form a two byte word,
which holds the 13-bit address of the FLASH location
being accessed. The PIC16F870/871 devices have 2K
words of program FLASH with an address range from
0h to 7FFh. The unused upper bits in both the EEDATH
and EEDATA registers all read as “0’s”.
Interrupt flag bit EEIF, in the PIR2 register, is set when
write is complete. It must be cleared in software.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 39
PIC16F870/871
REGISTER 4-1: EECON1 REGISTER (ADDRESS 18Ch)
R/W-x
EEPGD
bit7
U-0
U-0
U-0
R/W-x
R/W-0
R/W-0
R/W-0
—
—
—
WRERR WREN
WR
RD
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit0
- n= Value at POR reset
bit 7:
EEPGD: Program / Data EEPROM Select bit
1= Accesses Program memory
0= Accesses data memory
(This bit cannot be changed while a read or write operation is in progress)
bit 6-4: Unimplemented: Read as '0'
bit 3:
WRERR: EEPROM Error Flag bit
1= A write operation is prematurely terminated
(any MCLR reset or any WDT reset during normal operation)
0= The write operation completed
bit 2:
bit 1:
WREN: EEPROM Write Enable bit
1= Allows write cycles
0= Inhibits write to the EEPROM
WR: Write Control bit
1= Initiates a write cycle. (The bit is cleared by hardware once write is complete.) The WR bit can only
be set (not cleared) in software.
0= Write cycle to the EEPROM is complete
bit 0:
RD: Read Control bit
1= Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not cleared) in
software.
0= Does not initiate an EEPROM read
DS30569A-page 40
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
4.3
Reading the Data EEPROM Memory
EXAMPLE 4-1: DATA EEPROM READ
BSF
STATUS, RP1
;
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD con-
trol bit (EECON1<7>) and then set control bit RD
(EECON1<0>). The data is available in the very next
instruction cycle of the EEDATA register, therefore it
can be read by the next instruction. EEDATA will hold
this value until another read operation or until it is writ-
ten to by the user (during a write operation).
BCF
STATUS, RP0 ;Bank 2
MOVLW DATA_EE_ADDR
MOVWF EEADR
;
;Data Memory Address to read
BSF
BCF
BSF
BCF
STATUS, RP0 ;Bank 3
EECON1, EEPGD;Point to DATA memory
EECON1, RD
STATUS, RP0 ;Bank 2
;W = EEDATA
;EEPROM Read
MOVF EEDATA, W
4.4
Writing to the Data EEPROM Memory
To write an EEPROM data location, the address must
first be written to the EEADR register and the data writ-
ten to the EEDATA register. Then the sequence in
Example 4-2 must be followed to initiate the write cycle.
EXAMPLE 4-2: DATA EEPROM WRITE
BSF
STATUS, RP1
STATUS, RP0
DATA_EE_ADDR
EEADR
;
BCF
; Bank 2
;
MOVLW
MOVWF
MOVLW
MOVWF
BSF
; Data Memory Address to write
DATA_EE_DATA
EEDATA
;
; Data Memory Value to write
; Bank 3
STATUS, RP0
BCF
EECON1, EEPGD ; Point to DATA memory
EECON1, WREN ; Enable writes
BSF
BCF
INTCON, GIE
55h
; Disable Interrupts
MOVLW
MOVWF
MOVLW
MOVWF
BSF
;
Required
Sequence
EECON2
; Write 55h
AAh
;
EECON2
; Write AAh
EECON1, WR
INTCON, GIE
; Set WR bit to begin write
; Enable Interrupts
BSF
SLEEP
BCF
; Wait for interrupt to signal write complete
EECON1, WREN ; Disable writes
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
is set. The WREN bit must be set on a previous instruc-
tion. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Write Complete
Interrupt Flag bit (EEIF) is set. EEIF must be cleared by
software.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware
After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 41
PIC16F870/871
data is available in the EEDATA and EEDATH registers
after the second NOP instruction. Therefore, it can be
read as two bytes in the following instructions. The
EEDATA and EEDATH registers will hold this value until
another read operation or until it is written to by the user
(during a write operation).
4.5
Reading the FLASH Program Memory
A program memory location may be read by writing two
bytes of the address to the EEADR and EEADRH reg-
isters, setting the EEPGD control bit (EECON1<7>)
and then setting control bit RD (EECON1<0>). Once
the read control bit is set, the microcontroller will use
the next two instruction cycles to read the data. The
EXAMPLE 4-3: FLASH PROGRAM READ
BSF
STATUS, RP1
STATUS, RP0
ADDRH
;
BCF
; Bank 2
;
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EEADRH
; MSByte of Program Address to read
ADDRL
;
EEADR
; LSByte of Program Address to read
; Bank 3
STATUS, RP0
EECON1, EEPGD
EECON1, RD
BSF
; Point to PROGRAM memory
; EEPROM Read
Required
Sequence
BSF
NOP
NOP
; memory is read in the next two cycles after BSF EECON1,RD
;
BCF
STATUS, RP0
; Bank 2
MOVF
MOVF
EEDATA, W
EEDATH, W
; W = LSByte of Program EEDATA
; W = MSByte of Program EEDATA
DS30569A-page 42
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
trol bit (EECON1<7>), and then set control bit WR
(EECON1<1>). The sequence in Example 4-4 must be
followed to initiate a write to program memory.
4.6
Writing to the FLASH Program
Memory
When the PIC16F870/871 are fully code protected or
not code protected, a word of the FLASH program
memory may be written provided the WRT configura-
tion bit is set. If the PIC16F870/871 are partially code
protected, then a word of FLASH program memory
may be written if the word is in a non-code protected
segment of memory and the WRT configuration bit is
set. To write a FLASH program location, the first two
bytes of the address must be written to the EEADR and
EEADRH registers and two bytes of the data to the
EEDATA and EEDATH registers, set the EEPGD con-
The microcontroller will then halt internal operations
during the next two instruction cycles for the TPEW
(parameter D133) in which the write takes place. This
is not SLEEP mode, as the clocks and peripherals will
continue to run. Therefore, the two instructions follow-
ing the “BSF EECON, WR” should be NOPinstructions.
After the write cycle, the microcontroller will resume
operation with the 3rd instruction after the EECON1
write instruction.
EXAMPLE 4-4: FLASH PROGRAM WRITE
BSF
STATUS, RP1
STATUS, RP0
ADDRH
;
BCF
; Bank 2
;
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EEADRH
; MSByte of Program Address to read
ADDRL
;
EEADR
; LSByte of Program Address to read
DATAH
;
EEDATH
; MS Program Memory Value to write
;
DATAL
EEDATA
; LS Program Memory Value to write
; Bank 3
STATUS, RP0
EECON1, EEPGD
EECON1, WREN
BSF
; Point to PROGRAM memory
; Enable writes
BSF
BCF
INTCON, GIE
55h
; Disable Interrupts
MOVLW
MOVWF
MOVLW
MOVWF
BSF
;
Required
Sequence
EECON2
AAh
; Write 55h
;
EECON2
EECON1, WR
; Write AAh
; Set WR bit to begin write
NOP
NOP
; Instructions here are ignored by the microcontroller
; Microcontroller will halt operation and wait for
; a write complete. After the write
; the microcontroller continues with 3rd instruction
; Enable Interrupts
BSF
BCF
INTCON, GIE
EECON1, WREN
; Disable writes
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 43
PIC16F870/871
4.7
Write Verify
4.9
Operation during Code Protect
Depending on the application, good programming prac-
tice may dictate that the value written to the memory
should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
Each reprogrammable memory block has its own code
protect mechanism. External Read and Write opera-
tions are disabled if either of these mechanisms are
enabled.
4.9.1
DATA EEPROM MEMORY
Generally a write failure will be a bit which was written
as a ’1’, but reads back as a ’0’ (due to leakage off the
bit).
The microcontroller itself can both read and write to the
internal Data EEPROM, regardless of the state of the
code protect configuration bit.
4.8
Protection Against Spurious Write
When data memory is code protected (CONFIG<8>=0)
any further external programming access of program
memory is disabled. To reenable programming access
to program memory, both bulk erase and removal of
code protection must be performed on program and
data memory.
4.8.1
EEPROM DATA MEMORY
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
4.9.2
PROGRAM FLASH MEMORY
The microcontroller can read and execute instructions
out of the internal FLASH program memory, regardless
of the state of the code protect configuration bits. How-
ever, the WRT configuration bit and the code protect
bits have different effects on writing to program mem-
ory. Table 4-1 shows the various configurations and
status of reads and writes. To erase the WRT or code
protection bits in the configuration word requires that
the device be fully erased.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
4.8.2
PROGRAM FLASH MEMORY
To protect against spurious writes to FLASH program
memory, the WRT bit in the configuration word may be
programmed to ‘0’ to prevent writes. The write initiate
sequence must also be followed. WRT and the configu-
ration word cannot be programmed by user code, only
through the use of an external programmer.
TABLE 4-1:
READ/WRITE STATE OF INTERNAL FLASH PROGRAM MEMORY
Configuration Bits
Internal
Read
Internal
Write
Memory Location
ICSP Read ICSP Write
CP1
CP0
WRT
0
0
1
1
0
0
1
1
1
0
0
1
All program memory
All program memory
All program memory
All program memory
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
DS30569A-page 44
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
TABLE 4-2:
REGISTERS ASSOCIATED WITH DATA EEPROM/PROGRAM FLASH
Value on:
POR,
BOR
Value on
all other
resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
10Bh, 18Bh
10Dh
10Fh
10Ch
10Eh
18Ch
18Dh
8Dh
EEADR
EEPROM address register
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
x--- x000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
x--- u000
EEADRH
—
—
—
—
—
EEPROM address high
EEDATA EEPROM data resister
EEDATH
EECON1
—
—
—
EEPROM data resister high
WRERR
EEPGD
—
—
WREN
WR
RD
EECON2 EEPROM control resister2 (not a physical resister)
PIE2
PIR2
—
—
—
—
—
—
EEIE
EEIF
—
—
—
—
—
—
—
—
---0 ----
---0 ----
---0 ----
---0 ----
0Dh
Legend: x= unknown, u= unchanged, r = reserved, -= unimplemented read as ’0’. Shaded cells are not used by the
Timer1 module.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 45
PIC16F870/871
NOTES:
DS30569A-page 46
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed in detail in Section 5.2.
5.0
TIMER0 MODULE
The Timer0 module timer/counter has the following fea-
tures:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
The prescaler is mutually exclusively shared between
the Timer0 module and the watchdog timer. The pres-
caler is not readable or writable. Section 5.3 details the
operation of the prescaler.
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
5.1
Timer0 Interrupt
Additional information on the Timer0 module is available
in the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt ser-
vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In timer mode, the Timer0 mod-
ule will increment every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
8
CLKOUT (= FOSC/4)
M
U
X
1
0
0
1
M
U
X
RA4/T0CKI
Pin
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
Set Flag Bit T0IF
on Overflow
PSA
PRESCALER
0
1
8-bit Prescaler
M
U
X
Watchdog
Timer
8
8 - to - 1MUX
PS2:PS0
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 47
PIC16F870/871
module means that there is no prescaler for the watch-
dog timer, and vice-versa. This prescaler is not readable
or writable (see Figure 5-1).
5.2
Using Timer0 with an External Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>) deter-
mine the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF1, MOVWF1,
BSF1,x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
5.3
Prescaler
Note: Writing to TMR0, when the prescaler is
assigned to Timer0, will clear the prescaler
count, but will not change the prescaler
assignment.
There is only one prescaler available, which is mutually
exclusively shared between the Timer0 module and the
watchdog timer. A prescaler assignment for the Timer0
REGISTER 5-1: OPTION_REG REGISTER
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1 R/W-1 R/W-1
PSA PS2 PS1
R/W-1
PS0
R
= Readable bit
INTEDG
W = Writable bit
U
bit 7
bit 0
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
bit 6:
bit 5:
RBPU
INTEDG
T0CS: TMR0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
bit 4:
bit 3:
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Note: To avoid an unintended device RESET, the instruction sequence shown in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023) must be executed when changing the prescaler assignment from
Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
DS30569A-page 48
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
TABLE 5-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on:
POR,
BOR
Value on all
other resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h,101h
TMR0
INTCON
OPTION_REG RBPU INTEDG T0CS
Timer0 module’s register
xxxx xxxx uuuu uuuu
0Bh,8Bh,
10Bh,18Bh
GIE PEIE T0IE
INTE
T0SE
RBIE
PSA
T0IF
PS2
INTF
PS1
RBIF 0000 000x 0000 000u
81h,181h
PS0 1111 1111 1111 1111
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by Timer0.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 49
PIC16F870/871
NOTES:
DS30569A-page 50
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
In timer mode, Timer1 increments every instruction
cycle. In counter mode, it increments on every rising
edge of the external clock input.
6.0
TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L), which are
readable and writable. The TMR1 Register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 Interrupt, if enabled,
is generated on overflow, which is latched in interrupt
flag bit TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit TMR1IE (PIE1<0>).
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Timer1 also has an internal “reset input”. This reset can
be generated by the CCP module (Section 8.0).
Register 6-1 shows the Timer1 control register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
Timer1 can operate in one of two modes:
• As a timer
Additional information on timer modules is available in
the PICmicro™ Mid-range MCU Family Reference
Manual (DS33023).
• As a counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit0
bit7
- n = Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5-4: T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3:
bit 2:
T1OSCEN: Timer1 Oscillator Enable Control bit
1= Oscillator is enabled
0= Oscillator is shut off (The oscillator inverter is turned off to eliminate power drain)
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1= Do not synchronize external clock input
0= Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1:
bit 0:
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 51
PIC16F870/871
6.1
Timer1 Operation in Timer Mode
6.2
Timer1 Counter Operation
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect since the internal clock is
always in sync.
Timer1 may operate in asynchronous or usynchronous
mode depending on the setting of the TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After
Timer1 is enabled in counter mode, the module must
first have a falling edge before the counter begins to
increment.
FIGURE 6-1: TIMER1 INCREMENTING EDGE
T1CKI
(Default high)
T1CKI
(Default low)
Note: Arrows indicate counter increments.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The pres-
caler stage is an asynchronous ripple-counter.
6.3
Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI, when bit T1OSCEN is
set, or on pin RC0/T1OSO/T1CKI, when bit T1OSCEN
is cleared.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut off. The pres-
caler however will continue to increment.
FIGURE 6-2: TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow
Synchronized
0
TMR1
clock input
TMR1L
TMR1H
T1OSC
1
TMR1ON
on/off
T1SYNC
(2)
RC0/T1OSO/T1CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
FOSC/4
Internal
Clock
0
(1)
(2)
RC1/T1OSI
2
Q Clock
T1CKPS<1:0>
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
2: For the PIC16F870/871, the Schmitt Trigger is not implemented in external clock mode.
DS30569A-page 52
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
6.4
Timer1 Operation in Asynchronous
Counter Mode
TABLE 6-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in soft-
ware are needed to read/write the timer (Section 6.4.1).
Osc Type
Freq
C1
C2
LP
32 kHz
100 kHz
200 kHz
33 pF
15 pF
15 pF
33 pF
15 pF
15 pF
These values are for design guidance only.
Crystals Tested:
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
In asynchronous counter mode, Timer1 can not be used
as a time-base for capture or compare operations.
100 kHz
200 kHz
Epson C-2 100.00 KC-P
STD XTL 200.000 kHz
± 20 PPM
± 20 PPM
6.4.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
Note 1: Higher capacitance increases the stability of
oscillator, but also increases the start-up time.
2: Since each resonator/crystal has its own charac-
teristics, the user should consult the resonator/
crystal manufacturer for appropriate values of
external components.
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will guarantee a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself poses certain problems, since
the timer may overflow between the reads.
6.6
Resetting Timer1 using CCP1 Trigger
Output
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
If the CCP1 module is configured in compare mode to
generate a “special event trigger” (CCP1M<3:0> =
1011), this signal will reset Timer1.
Note: The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Reading the 16-bit value requires some care. Examples
12-2 and 12-3 in the PICmicro™ Mid-Range MCU Fam-
ily Reference Manual (DS33023) show how to read and
write Timer1 when it is running in asynchronous mode.
Timer1 must be configured for either timer or synchro-
nized counter mode to take advantage of this feature. If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
6.5
Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for use with a 32 kHz crystal. Table 6-1 shows the
capacitor selection for the Timer1 oscillator.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1, the write will take prece-
dence.
In this mode of operation, the CCPR1H:CCPR1L regis-
ter pair effectively becomes the period register for
Timer1.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
6.7
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other reset except by the CCP1 special
event trigger.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other resets, the register is
unaffected.
6.8
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 53
PIC16F870/871
TABLE 6-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on:
POR,
BOR
Value on
all other
resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
10Bh,
18Bh
(1)
0Ch
8Ch
0Eh
0Fh
10h
PIR1
PSPIF
ADIF
RCIF
TXIF
—
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
(1)
PIE1
PSPIE
ADIE
RCIE
TXIE
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
DS30569A-page 54
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
7.1
Timer2 Prescaler and Postscaler
7.0
TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mode of the CCP module(s). The TMR2 reg-
ister is readable and writable, and is cleared on any
device reset.
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device reset (POR, MCLR reset, WDT reset
or BOR)
The input clock (FOSC/4) has a prescale option of 1:1,
1:4
or
1:16,
selected
by
control
bits
TMR2 is not cleared when T2CON is written.
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is ini-
tialized to FFh upon reset.
7.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
SSPort module, which optionally uses it to generate
shift clock.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
FIGURE 7-1: TIMER2 BLOCK DIAGRAM
Sets flag
bit TMR2IF
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Prescaler
1:1, 1:4, 1:16
TMR2 reg
FOSC/4
Register 7-1 shows the Timer2 control register.
Postscaler
1:1 to 1:16 EQ
2
Comparator
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
T2CKPS1:
T2CKPS0
4
PR2 reg
T2OUTPS3:
T2OUTPS0
REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit0
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
bit7
- n = Value at POR reset
bit 7:
Unimplemented: Read as '0'
bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
0010= 1:3 Postscale
•
•
•
1111= 1:16 Postscale
bit 2:
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 55
PIC16F870/871
TABLE 7-1:
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on:
POR,
BOR
Value on
all other
resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 000x 0000 000u
0Bh,8Bh,
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
10Bh,18Bh
0000 -000 0000 -000
0000 -000 0000 -000
0000 0000 0000 0000
-000 0000 -000 0000
1111 1111 1111 1111
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
—
—
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
11h
TMR2
T2CON
PR2
Timer2 module’s register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
12h
—
92h
Legend:
x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
DS30569A-page 56
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
the operation of CCP1. The special event trigger is gen-
erated by a compare match and will reset Timer1 and
start an A/D conversion (if the A/D module is enabled).
8.0
CAPTURE/COMPARE/PWM
MODULE
The Capture/Compare/PWM (CCP) module contains a
16-bit register which can operate as a:
Additional information on CCP modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023) and in Application Note 594, “Using
the CCP Modules” (DS00594).
• 16-bit Capture register
• 16-bit Compare register
• PWM master/slave Duty Cycle register
TABLE 8-1:
CCP MODE - TIMER
Table 8-1 shows the resources used by the CCP mod-
ule. In the following sections, the operation of a CCP
module is described.
RESOURCES REQUIRED
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
CCP1 Module:
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
REGISTER 8-1: CCP1CON REGISTER (ADDRESS: 17h)
U-0
—
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
R =Readable bit
W =Writable bit
bit7
bit0
U =Unimplemented bit, read as ‘0’
- n =Value at POR reset
bit 7-6: Unimplemented: Read as ’0’
bit 5-4: CCP1<X:Y>: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
bit 3-0: CCP1M<3:0>: CCPx Mode Select bits
0000= Capture/Compare/PWM off (resets CCP module)
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, set output on match (CCP1IF bit is set)
1001= Compare mode, clear output on match (CCP1IF bit is set)
1010= Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP pin is unaffected)
1011= Compare mode, trigger special event (CCP1IF bit is set, CCP1 pin is unaffected); CCP1 resets
TMR1 and starts an A/D conversion (if A/D module is enabled)
11xx= PWM mode
1999 Microchip Technology Inc.
Preliminary
DS30569A -page 57
PIC16F870/871
8.1.2
TIMER1 MODE SELECTION
8.1
Capture Mode
Timer1 must be running in timer mode or synchronized
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode, the capture
operation may not work.
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as:
• Every falling edge
• Every rising edge
8.1.3
SOFTWARE INTERRUPT
• Every 4th rising edge
• Every 16th rising edge
When the capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
An event is selected by control bits CCP1M<3:0>
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. The
interrupt flag must be cleared in software. If another
capture occurs before the value in register CCPR1 is
read, the old captured value will be lost.
8.1.4
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M<3:0>. Whenever the CCP module is turned off,
or the CCP module is not in capture mode, the pres-
caler counter is cleared. Any reset will clear the pres-
caler counter.
8.1.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
Note: If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a cap-
ture condition.
FIGURE 8-1: CAPTURE MODE OPERATION
BLOCK DIAGRAM
Set flag bit CCP1IF
(PIR1<2>)
Prescaler
÷ 1, 4, 16
EXAMPLE 8-1: CHANGING BETWEEN
CAPTURE PRESCALERS
RC2/CCP1
Pin
CCPR1H
CCPR1L
TMR1L
CLRF
CCP1CON
;Turn CCP module off
MOVLW
NEW_CAPT_PS;Load the W reg with
; the new precscaler
Capture
Enable
and
edge detect
; move value and CCP ON
TMR1H
MOVWF
CCP1CON
;Load CCP1CON with this
; value
CCP1CON<3:0>
Q’s
DS30569A -page 58
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
.
8.2
Compare Mode
Note: The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
8.3
PWM Mode (PWM)
• Driven low
In pulse width modulation mode, the CCP1 pin pro-
duces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiplexed with the PORTC data latch, the
TRISC<2> bit must be cleared to make the CCP1 pin
an output.
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M<3:0> (CCP1CON<3:0>). At the same
time, interrupt flag bit CCP1IF is set.
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
FIGURE 8-2: COMPARE MODE OPERATION
BLOCK DIAGRAM
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
Figure 8-3 shows a simplified block diagram of the CCP
module in PWM mode.
Special Event Trigger
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 8.3.3.
Set flag bit CCP1IF
(PIR1<2>)
CCPR1H CCPR1L
FIGURE 8-3: SIMPLIFIED PWM BLOCK
DIAGRAM
Q
S
R
Output
Logic
Comparator
match
RC2/CCP1
Pin
CCP1CON<5:4>
Duty Cycle Registers
TRISC<2>
Output Enable
TMR1H TMR1L
CCP1CON<3:0>
Mode Select
CCPR1L
8.2.1
CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
CCPR1H (Slave)
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
Q
R
S
Comparator
RC2/CCP1
(Note 1)
TMR2
8.2.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
TRISC<2>
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
8.2.3
SOFTWARE INTERRUPT MODE
or 2 bits of the prescaler to create 10-bit time-base.
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set causing
a CCP interrupt (if enabled).
8.2.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled). This allows the CCPR1 regis-
ter to effectively be a 16-bit programmable period reg-
ister for Timer1.
1999 Microchip Technology Inc.
Preliminary
DS30569A -page 59
PIC16F870/871
A PWM output (Figure 8-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period (1/
period).
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
FIGURE 8-4: PWM OUTPUT
Maximum PWM resolution (bits) for a given PWM
frequency:
Period
FOSC
log( )
FPWM
Resolution
bits
=
Duty Cycle
log(2)
TMR2 = PR2
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TMR2 = Duty Cycle
TMR2 = PR2
8.3.3
SET-UP FOR PWM OPERATION
8.3.1
PWM PERIOD
The following steps should be taken when configuring
the CCP module for PWM operation:
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
1. Set the PWM period by writing to the PR2 register.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
FOSC
— 1
PR2 =
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4 • FPWM • TMR2 Prescale value
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
5. Configure the CCP1 module for PWM operation.
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note: The Timer2 postscaler (see Section 8.1) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different fre-
quency than the PWM output.
8.3.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
Tosc • (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
DS30569A -page 60
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
TABLE 8-2:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Value on: Value on
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
all other
resets
0Bh,8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000u
0Ch
8Ch
87h
0Eh
0Fh
10h
15h
16h
17h
PIR1
PSPIF(1) ADIF
RCIF
TXIF
—
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
1111 1111 1111 1111
PIE1
PSPIE(1) ADIE
RCIE
TXIE
TRISC
TMR1L
TMR1H
T1CON
PORTC Data Direction Register
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCPR1L Capture/Compare/PWM register1 (LSB)
CCPR1H Capture/Compare/PWM register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1CON
—
—
CCP1X
CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, -= unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.
Note 1:The PSP is not implemented on the PIC16F870; always maintain these bits clear.
TABLE 8-3:
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on: Value on
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
all other
resets
0Bh,8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
8Ch
87h
11h
92h
12h
15h
16h
17h
PIR1
PSPIF(1)
PSPIE(1)
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
—
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
1111 1111 1111 1111
PIE1
TRISC
TMR2
PR2
PORTC Data Direction Register
Timer2 module’s register
0000 0000 0000 0000
Timer2 module’s period register
1111 1111 1111 1111
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
-000 0000 -000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
--00 0000 --00 0000
CCPR1L Capture/Compare/PWM register1 (LSB)
CCPR1H Capture/Compare/PWM register1 (MSB)
CCP1CON
—
—
CCP1X
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1:Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
1999 Microchip Technology Inc.
Preliminary
DS30569A -page 61
PIC16F870/871
NOTES:
DS30569A -page 62
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
The USART can be configured in the following modes:
9.0
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to
be set in order to configure pins RC6/TX/CK and
RC7/RX/DT as the Universal Synchronous Asynchro-
nous Receiver Transmitter.
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Com-
munications Interface or SCI). The USART can be con-
figured as a full duplex asynchronous system that can
communicate with peripheral devices such as CRT ter-
minals and personal computers, or it can be configured
as a half duplex synchronous system that can commu-
nicate with peripheral devices such as A/D or D/A inte-
grated circuits, serial EEPROMs etc.
The USART module also has a multi-processor com-
munication capability using 9-bit address detection.
REGISTER 9-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0
CSRC
bit7
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
—
R/W-0
BRGH
R-1
R/W-0
TX9D
bit0
TRMT
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1= Master mode (Clock generated internally from BRG)
0= Slave mode (Clock from external source)
bit 6:
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
bit 5:
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4:
SYNC: USART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
bit 3:
bit 2:
Unimplemented: Read as '0'
BRGH: High Baud Rate Select bit
Asynchronous mode
1= High speed
0= Low speed
Synchronous mode
Unused in this mode
bit 1:
bit 0:
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of transmit data. Can be parity bit.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 63
PIC16F870/871
REGISTER 9-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0
SPEN
bit7
R/W-0
RX9
R/W-0
SREN
R/W-0
R/W-0
R-0
R-0
R-x
RX9D
bit0
CREN ADDEN
FERR
OERR
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
SPEN: Serial Port Enable bit
1= Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0= Serial port disabled
bit 6:
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
bit 5:
SREN: Single Receive Enable bit
Asynchronous mode
Don’t care
Synchronous mode - master
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave
Unused in this mode
bit 4:
CREN: Continuous Receive Enable bit
Asynchronous mode
1= Enables continuous receive
0= Disables continuous receive
Synchronous mode
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3:
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1)
1= Enables address detection, enable interrupt and load of the receive burffer when RSR<8> is set
0= Disables address detection, all bytes are received, and ninth bit can be used as parity bit
bit 2:
bit 1:
bit 0:
FERR: Framing Error bit
1= Framing error (Can be updated by reading RCREG register and receive next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (Can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of received data (Can be parity bit)
DS30569A-page 64
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
9.1
USART Baud Rate Generator (BRG)
The BRG supports both the asynchronous and syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In synchronous mode, bit BRGH is ignored.
Table 9-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in master mode (internal clock).
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
9.1.1
SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
Given the desired baud rate and Fosc, the nearest inte-
ger value for the SPBRG register can be calculated
using the formula in Table 9-1. From this, the error in
baud rate can be determined.
TABLE 9-1:
SYNC
BAUD RATE FORMULA
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
Baud Rate= FOSC/(16(X+1))
NA
X = value in SPBRG (0 to 255)
TABLE 9-2:
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on: Value on all
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
POR,
BOR
other
resets
0000 -010 0000 -010
0000 000x 0000 000x
0000 0000 0000 0000
98h
18h
99h
TXSTA
CSRC TX9 TXEN SYNC
—
BRGH TRMT TX9D
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
SPBRG Baud Rate Generator Register
Legend: x = unknown, -= unimplemented read as '0'. Shaded cells are not used by the BRG.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 65
PIC16F870/871
TABLE 9-3:
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz
FOSC = 16 MHz
FOSC = 10 MHz
BAUD
RATE
(K)
SPBRG
SPBRG
SPBRG
%
%
%
value
value
value
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
(decimal)
(decimal)
(decimal)
0.3
1.2
-
-
-
255
129
31
15
9
-
-
-
207
103
25
12
8
-
-
-
129
64
15
7
1.221
2.404
9.766
19.531
31.250
34.722
62.500
1.221
1.75
0.17
1.73
1.72
8.51
3.34
8.51
-
1.202
0.17
0.17
0.16
0.16
3.55
6.29
8.51
-
1.202
0.17
0.17
1.73
1.72
8.51
6.99
9.58
-
2.4
2.404
2.404
9.6
9.615
9.766
19.2
28.8
33.6
57.6
HIGH
19.231
27.778
35.714
62.500
0.977
19.531
31.250
31.250
52.083
0.610
4
8
6
4
4
3
2
255
0
255
0
255
0
LOW 312.500
-
250.000
-
156.250
-
FOSC = 4 MHz
FOSC = 3.6864 MHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
%
%
ERROR
ERROR
KBAUD
(decimal) KBAUD
(decimal)
0.3
1.2
0.300
1.202
2.404
8.929
20.833
31.250
-
0
207
51
25
6
0.301
1.216
2.432
9.322
18.643
-
0.33
1.33
1.33
2.90
2.90
-
185
46
22
5
0.17
0.17
6.99
8.51
8.51
-
2.4
9.6
19.2
28.8
33.6
57.6
HIGH
LOW
2
2
1
-
-
-
-
-
62.500
0.244
62.500
8.51
-
0
55.930
0.218
55.930
2.90
-
0
255
0
255
0
-
-
-
TABLE 9-4:
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 20 MHz
FOSC = 16 MHz
FOSC = 10 MHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
SPBRG
value
%
%
%
KBAUD
ERROR
KBAUD
ERROR
KBAUD
ERROR
(decimal)
(decimal)
(decimal)
0.3
1.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.4
-
-
-
-
-
-
2.441
9.615
19.531
28.409
32.895
56.818
2.441
625.000
1.71
0.16
1.72
1.36
2.10
1.36
-
255
64
31
21
18
10
255
0
9.6
9.615
19.231
29.070
33.784
59.524
4.883
0.16
0.16
0.94
0.55
3.34
-
129
64
42
36
20
255
0
9.615
19.231
29.412
33.333
58.824
3.906
1000.000
0.16
0.16
2.13
0.79
2.13
-
103
51
33
29
16
255
0
19.2
28.8
33.6
57.6
HIGH
LOW 1250.000
-
-
FOSC = 4 MHz
FOSC = 3.6864 MHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
%
%
ERROR
ERROR
KBAUD
(decimal) KBAUD
(decimal)
0.3
1.2
-
-
-
207
103
25
12
8
-
-
-
185
92
22
11
7
1.202
0.17
0.17
0.16
0.16
3.55
6.29
8.51
-
1.203
0.25
0.25
1.32
2.90
2.90
4.88
2.90
-
2.4
2.404
2.406
9.6
9.615
9.727
19.2
28.8
33.6
57.6
HIGH
LOW
19.231
27.798
35.714
62.500
0.977
18.643
27.965
31.960
55.930
0.874
6
6
3
3
255
0
255
0
250.000
-
273.722
-
DS30569A-page 66
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
( PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. Status bit TRMT
is a read only bit, which is set when the TSR register is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR reg-
ister is empty.
9.2
USART Asynchronous Mode
In this mode, the USART uses standard non-return-to-
zero (NRZ) format (one start bit, eight or nine data bits,
and one stop bit). The most common data format is 8
bits. An on-chip, dedicated, 8-bit baud rate generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LSb first. The USART’s transmitter and receiver are
functionally independent, but use the same data format
and baud rate. The baud rate generator produces a
clock either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA<2>). Parity is not supported by
the hardware, but can be implemented in software (and
stored as the ninth data bit). Asynchronous mode is
stopped during SLEEP.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set. TXIF is cleared by loading TXREG.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift clock (Figure 9-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
transfer to the TXREG register will result in an immedi-
ate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 9-3).
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. As a result, the RC6/TX/CK pin will revert
to hi-impedance.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
9.2.1
USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 9-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
flag bit TXIF (PIR1<4>) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can result in an immediate transfer of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit may be loaded in the TSR
register.
FIGURE 9-1: USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXREG register
TXIF
TXIE
8
MSb
(8)
LSb
0
Pin Buffer
and Control
•
•
•
TSR register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
SPBRG
TRMT
SPEN
TX9
TX9D
Baud Rate Generator
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 67
PIC16F870/871
Steps to follow when setting up an Asynchronous
Transmission:
4. If 9-bit transmission is desired, then set transmit
bit TX9.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 9.1)
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
7. Load data to the TXREG register (starts trans-
mission).
3. If interrupts are desired, then set enable bit
TXIE.
FIGURE 9-2: ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
Start Bit
Bit 0
Bit 1
Word 1
Bit 7/8
Stop Bit
TXIF bit
(Transmit buffer
reg. empty flag)
Word 1
Transmit Shift Reg
TRMT bit
(Transmit shift
reg. empty flag)
FIGURE 9-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
TXIF bit
(interrupt reg. flag)
Start Bit
Start Bit
Word 2
Bit 0
Bit 1
Word 1
Bit 7/8
Bit 0
Stop Bit
TRMT bit
(Transmit shift
reg. empty flag)
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 9-5:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on:
POR,
BOR
Value on
all other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
—
—
0Ch
18h
19h
8Ch
98h
99h
PIR1
PSPIF
ADIF
RCIF
TXIF
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
RCSTA
SPEN
RX9
SREN CREN
FERR
OERR
RX9D 0000 -00x 0000 -00x
TXREG USART Transmit Register
0000 0000 0000 0000
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE
—
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
TXSTA
TXEN
SYNC
BRGH
TRMT
TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
DS30569A-page 68
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
9.2.2
USART ASYNCHRONOUS RECEIVER
for two bytes of data to be received and transferred to
the RCREG FIFO and a third byte to begin shifting to
the RSR register. On the detection of the STOP bit of
the third byte, if the RCREG register is still full, the over-
run error bit OERR (RCSTA<1>) will be set. The word
in the RSR will be lost. The RCREG register can be
read twice to retrieve the two bytes in the FIFO. Over-
run bit OERR has to be cleared in software. This is
done by resetting the receive logic (CREN is cleared
and then set). If bit OERR is set, transfers from the
RSR register to the RCREG register are inhibited, so it
is essential to clear error bit OERR if it is set. Framing
error bit FERR (RCSTA<2>) is set if a stop bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values, therefore it is essential for the user to read the
RCSTA register before reading RCREG register in
order not to lose the old FERR and RX9D information.
The receiver block diagram is shown in Figure 9-4. The
data is received on the RC7/RX/DT pin and drives the
data recovery block. The data recovery block is actually
a high speed shifter operating at x16 times the baud
rate, whereas the main receive serial shifter operates at
the bit rate or at FOSC.
Once asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG register (if
it is empty). If the transfer is complete, flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE (PIE1<5>).
Flag bit RCIF is a read only bit which is cleared by the
hardware. It is cleared when the RCREG register has
been read and is empty. The RCREG is a double buff-
ered register (i.e. it is a two deep FIFO). It is possible
FIGURE 9-4: USART RECEVE BLOCK DIAGRAM
x64 Baud Rate CLK
CREN
FERR
OERR
SPBRG
÷64
RSR register
MSb
LSb
or
÷16
0
Baud Rate Generator
7
1
Stop (8)
Start
• • •
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG Register
FIFO
8
RCIF
RCIE
Interrupt
Data Bus
FIGURE 9-5: ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX (pin)
bit0
bit1
Stop
bit
Stop
bit
bit7/8 Stop
bit
bit0
bit7/8
bit7/8
Rcv shift
reg
Rcv buffer reg
WORD 2
RCREG
WORD 1
RCREG
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 69
PIC16F870/871
Steps to follow when setting up an Asynchronous
Reception:
6. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE is set.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 9.1).
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
8. Read the 8-bit received data by reading the
RCREG register.
3. If interrupts are desired, then set enable bit
RCIE.
9. If any error occurred, clear the error by clearing
enable bit CREN.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
TABLE 9-6:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on:
POR,
BOR
Value on
all other
Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
—
—
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
ADIF
RCIF
TXIF
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
RCSTA
SPEN
RX9
SREN CREN
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
RCREG USART Receive Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE
—
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
TXSTA
TXEN
SYNC
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
DS30569A-page 70
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
9.2.3
SETTING UP 9-BIT MODE WITH ADDRESS
DETECT
• Flag bit RCIF will be set when reception is com-
plete, and an interrupt will be generated if enable
bit RCIE was set.
Steps to follow when setting up an Asynchronous
Reception with Address Detect Enabled:
• Read the RCSTA register to get the ninth bit and
determine if any error occurred during reception.
• Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired, set
bit BRGH.
• Read the 8-bit received data by reading the
RCREG register, to determine if the device is
being addressed.
• Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
• If any error occurred, clear the error by clearing
enable bit CREN.
• If interrupts are desired, then set enable bit RCIE.
• Set bit RX9 to enable 9-bit reception.
• If the device has been addressed, clear the
ADDEN bit to allow data bytes and address bytes
to be read into the receive buffer, and interrupt the
CPU.
• Set ADDEN to enable address detect.
• Enable the reception by setting enable bit CREN.
FIGURE 9-6: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
SPBRG
÷ 64
RSR register
MSb
LSb
or
÷ 16
0
Baud Rate Generator
7
1
Stop (8)
Start
• • •
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
8
SPEN
RX9
Enable
Load of
ADDEN
Receive
Buffer
RX9
ADDEN
RSR<8>
8
RX9D
RCREG Register
FIFO
8
RCIF
RCIE
Interrupt
Data Bus
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 71
PIC16F870/871
FIGURE 9-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
Start
bit
Start
bit
RC7/RX/DT (pin)
bit0
bit1
Stop
bit
bit8 Stop
bit
bit0
bit8
Load RSR
Read
WORD 1
RCREG
Bit8 = 0, Data Byte
Bit8 = 1, Address Byte
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(receive buffer) because ADDEN = 1.
FIGURE 9-8: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
Start
bit
Start
bit
RC7/RX/DT (pin)
bit0
bit1
Stop
bit
bit8 Stop
bit
bit0
bit8
Load RSR
Read
WORD 1
RCREG
Bit8 = 1, Address Byte
Bit8 = 0, Data Byte
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(receive buffer) because ADDEN was not updated and still = 0.
TABLE 9-7:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on:
POR,
BOR
Value on
all other
Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
ADIF
RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D 0000 000x 0000 000x
RCREG USART Receive Register
0000 0000 0000 0000
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE
—
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
TXSTA
TXEN SYNC
BRGH
TRMT
TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
DS30569A-page 72
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
pin reverts to a hi-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic, however, is not
reset, although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SREN is set (to interrupt an on-going transmission
and receive a single word), then after the single word is
received, bit SREN will be cleared and the serial port
will revert back to transmitting, since bit TXEN is still
set. The DT line will immediately switch from hi-imped-
ance receive mode to transmit and start driving. To
avoid this, bit TXEN should be cleared.
9.3
USART Synchronous Master Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manne (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
9.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 9-6. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and inter-
rupt bit TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not
available to the user.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 9.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is sta-
ble around the falling edge of the synchronous clock
(Figure 9-9). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 9-10). This is advantageous when slow
baud rates are selected, since the BRG is kept in reset
when bits TXEN, CREN and SREN are clear. Setting
enable bit TXEN will start the BRG, creating a shift
clock immediately. Normally, when transmission is first
started, the TSR register is empty, so a transfer to the
TXREG register will result in an immediate transfer to
TSR resulting in an empty TXREG. Back-to-back trans-
fers are possible.
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to hi-imped-
ance. If either bit CREN or bit SREN is set during a
transmission, the transmission is aborted and the DT
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 73
PIC16F870/871
TABLE 9-8:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on:
POR,
BOR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Ch
18h
19h
8Ch
98h
99h
PIR1
PSPIF
ADIF
RCIF
TXIF
—
—
CCP1IF TMR2IF TMR1IF 0000 -000
0000 -000
0000 -00x
0000 0000
0000 -000
0000 -010
0000 0000
RCSTA
SPEN
RX9
SREN CREN
FERR
OERR
RX9D
0000 -00x
0000 0000
TXREG USART Transmit Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE
—
—
CCP1IE TMR2IE TMR1IE 0000 -000
TXSTA
TXEN SYNC
BRGH
TRMT
TX9D
0000 -010
0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
FIGURE 9-9: SYNCHRONOUS TRANSMISSION
Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
Q3Q4 Q1Q2 Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3 Q4Q1Q2Q3Q4Q1 Q2Q3 Q4
RC7/RX/DT pin
RC6/TX/CK pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
WORD 2
bit 7
WORD 1
Write to
TXREG reg
Write word1
Write word2
TXIF bit
(Interrupt flag)
T
TRMT bit
’1’
’1’
TXEN bit
Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words
FIGURE 9-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
RC6/TX/CK pin
bit0
bit2
bit1
bit6
bit7
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
DS30569A-page 74
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
9.3.2
USART SYNCHRONOUS MASTER
RECEPTION
OERR if it is set. The ninth receive bit is buffered the
same way as the receive data. Reading the RCREG
register will load bit RX9D with a new value, therefore it
is essential for the user to read the RCSTA register
before reading RCREG in order not to lose the old
RX9D information.
Once synchronous mode is selected, reception is
enabled by setting either enable bit SREN (RCSTA<5>)
or enable bit CREN (RCSTA<4>). Data is sampled on
the RC7/RX/DT pin on the falling edge of the clock. If
enable bit SREN is set, then only a single word is
received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
CREN takes precedence. After clocking the last bit, the
received data in the Receive Shift Register (RSR) is
transferred to the RCREG register (if it is empty). When
the transfer is complete, interrupt flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE (PIE1<5>).
Flag bit RCIF is a read only bit, which is reset by the
hardware. In this case, it is reset when the RCREG reg-
ister has been read and is empty. The RCREG is a dou-
ble buffered register (i.e., it is a two deep FIFO). It is
possible for two bytes of data to be received and trans-
ferred to the RCREG FIFO and a third byte to begin
shifting into the RSR register. On the clocking of the last
bit of the third byte, if the RCREG register is still full,
then overrun error bit OERR (RCSTA<1>) is set. The
word in the RSR will be lost. The RCREG register can
be read twice to retrieve the two bytes in the FIFO. Bit
OERR has to be cleared in software (by clearing bit
CREN). If bit OERR is set, transfers from the RSR to
the RCREG are inhibited, so it is essential to clear bit
Steps to follow when setting up a Synchronous Master
Reception:
1. Initialize the SPBRG register for the appropriate
baud rate. (Section 9.1)
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
TABLE 9-9:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on:
POR,
BOR
Value on all
other Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
ADIF
RCIF
TXIF
—
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
RCSTA
SPEN
RX9
SREN CREN
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
RCREG USART Receive Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE
—
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
TXSTA
TXEN SYNC
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
FIGURE 9-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2Q3Q4 Q1Q2Q3Q4 Q1 Q2Q3Q4 Q1Q2Q3 Q4Q1 Q2Q3 Q4 Q1Q2 Q3Q4Q1Q2Q3 Q4 Q1Q2 Q3Q4Q1 Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4
RC7/RX/DT pin
RC6/TX/CK pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Write to
bit SREN
SREN bit
CREN bit
’0’
’0’
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRG = '0'.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 75
PIC16F870/871
9.4.2
USART SYNCHRONOUS SLAVE
RECEPTION
9.4
USART Synchronous Slave Mode
Synchronous slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
The operation of the synchronous master and slave
modes is identical, except in the case of the SLEEP
mode. Bit SREN is a “don't care” in slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEPinstruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
9.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the synchronous master and slave
modes are identical except in the case of the SLEEP
mode.
Steps to follow when setting up a Synchronous Slave
Reception:
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
5. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the inter-
rupt vector (0004h).
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
Steps to follow when setting up a Synchronous Slave
Transmission:
8. If any error occurred, clear the error by clearing
bit CREN.
1. Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, then set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
DS30569A-page 76
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
TABLE 9-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on:
POR,
BOR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Ch
18h
19h
8Ch
98h
99h
PIR1
PSPIF
ADIF
RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D 0000 000x 0000 000x
TXREG USART Transmit Register
0000 0000 0000 0000
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE
—
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
TXSTA
TXEN SYNC
BRGH
TRMT
TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
TABLE 9-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on:
POR,
BOR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
RCSTA
SREN CREN ADDEN FERR
OERR
RX9D 0000 000x 0000 000x
RCREG USART Receive Register
0000 0000 0000 0000
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE
—
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
TXSTA
TXEN SYNC
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870, always maintain these bits clear.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 77
PIC16F870/871
NOTES:
DS30569A-page 78
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
The A/D module has four registers. These registers
are:
10.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module has five
inputs for the PIC16F870 and eight for the PIC16F871.
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register0 (ADCON0)
• A/D Control Register1 (ADCON1)
The analog input charges a sample and hold capacitor.
The output of the sample and hold capacitor is the
input into the converter. The converter then generates
a digital result of this analog level via successive
approximation. The A/D conversion of the analog input
signal results in a corresponding 10-bit digital number.
The A/D module has high and low voltage reference
input that is software selectable to some combination
of VDD, VSS, RA2 or RA3.
The ADCON0 register, shown in Register 10-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 10-2, configures the func-
tions of the port pins. The port pins can be configured
as analog inputs (RA3 can also be the voltage refer-
ence) or as digital I/O.
Additional information on using the A/D module can be
found in the PICmicro™ Mid-Range MCU Family Ref-
erence Manual (DS33023).
The A/D converter has a unique feature of being able to
operate while the device is in SLEEP mode. To operate
in sleep, the A/D clock must be derived from the A/D’s
internal RC oscillator.
REGISTER 10-1: ADCON0 REGISTER (ADDRESS: 1Fh)
R/W-0
R/W-0
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
U-0
R/W-0
ADON
bit0
ADCS1 ADCS0
GO/DONE
—
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
- n = Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00= FOSC/2
01= FOSC/8
10= FOSC/32
11= FRC (clock derived from an RC oscillation)
bit 5-3: CHS2:CHS0: Analog Channel Select bits
000= channel 0, (RA0/AN0)
001= channel 1, (RA1/AN1)
010= channel 2, (RA2/AN2)
011= channel 3, (RA3/AN3)
100= channel 4, (RA5/AN4)
101= channel 5, (RE0/AN5)
110= channel 6, (RE1/AN6)
111= channel 7, (RE2/AN7)
(1)
(1)
(1)
bit 2:
GO/DONE: A/D Conversion Status bit
If ADON = 1
1= A/D conversion in progress (setting this bit starts the A/D conversion)
0= A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete)
bit 1:
bit 0:
Unimplemented: Read as '0'
ADON: A/D On bit
1= A/D converter module is operating
0= A/D converter module is shutoff and consumes no operating current
Note 1: These channels are not available on the PIC16F870.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 79
PIC16F870/871
REGISTER 10-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0
ADFM
bit7
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG0
bit0
—
—
—
PCFG3
PCFG2
PCFG1
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
ADFM: A/D Result format select
1= Right Justified. 6 most significant bits of ADRESH are read as ‘0’.
0= Left Justified. 6 least significant bits of ADRESL are read as ‘0’.
bit 6-4: Unimplemented: Read as ’0’
bit 3-0: PCFG3:PCFG0: A/D Port Configuration Control bits
(1)
(1)
(1)
PCFG3: AN7
PCFG0
AN6
AN5
AN4
RA5
AN3
RA3
AN2
RA2
AN1
RA1
AN0
RA0
CHAN /
Refs
VREF+
VREF-
(2)
RE2
RE1
RE0
0000
0001
0010
0011
0100
0101
011x
1000
1001
1010
1011
1100
1101
1110
1111
A
A
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
A
A
A
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
VDD
RA3
VDD
RA3
VDD
RA3
VDD
RA3
VDD
RA3
RA3
RA3
RA3
VDD
RA3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RA2
VSS
VSS
RA2
RA2
RA2
VSS
RA2
8/0
7/1
5/0
4/1
3/0
2/1
0/0
6/2
6/0
5/1
4/2
3/2
2/2
1/0
1/2
VREF+
A
A
VREF+
A
A
D
VREF+
D
D
D
VREF+
A
VREF-
A
VREF+
VREF+
VREF+
VREF+
D
A
VREF-
VREF-
VREF-
D
VREF+
VREF-
A = Analog input
D = Digital I/O
Note 1: These channels are not available on the PIC16F870.
2: This column indicates the number of analog channels available as A/D inputs and the numer of analog channels
used as voltage reference inputs.
DS30569A-page 80
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
The ADRESH:ADRESL registers contain the 10-bit
result of the A/D conversion. When the A/D conversion
is complete, the result is loaded into this A/D result reg-
ister pair, the GO/DONE bit (ADCON0<2>) is cleared
and the A/D interrupt flag bit ADIF is set. The block dia-
gram of the A/D module is shown in Figure 10-1.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine sample time, see Section 10.1. After this
acquisition time has elapsed, the A/D conversion can
be started. The following steps should be followed for
doing an A/D conversion:
1. Configure the A/D module:
• Configure analog pins / voltage reference /
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read
A/D
Result
register
pair
(ADRESH:ADRESL), clear bit ADIF if required.
7. For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 81
PIC16F870/871
FIGURE 10-1: A/D BLOCK DIAGRAM
CHS2:CHS0
111
110
101
100
011
010
001
000
(1)
(1)
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4
(1)
VAIN
(Input voltage)
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
A/D
Converter
VDD
RA0/AN0
VREF+
(Reference
voltage)
PCFG3:PCFG0
VREF-
(Reference
voltage)
VSS
PCFG3:PCFG0
Note 1: Not available on PIC16F870.
To calculate the minimum acquisition time,
Equation 10-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
10.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 10-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD), Figure 10-2. The maximum recommended
impedance for analog sources is 10 kΩ. As the
impedance is decreased, the acquisition time may be
decreased. After the analog input channel is selected
(changed), this acquisition must be done before the
conversion can be started.
To calculate the minimum acquisition time, TACQ, see
the PICmicro™ Mid-Range Reference Manual
(DS33023).
DS30569A-page 82
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
EQUATION 10-1: ACQUISITION TIME
TACQ
=
Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
=
=
=
=
=
=
=
TAMP + TC + TCOFF
2µS + TC + [(Temperature -25°C)(0.05µS/°C)]
CHOLD (RIC + RSS + RS) In(1/2047)
- 120pF (1kΩ + 7kΩ + 10kΩ) In(0.0004885)
16.47µS
2µS + 16.47µS + [(50°C -25×C)(0.05µS/×C)
19.72µS
TC
TACQ
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leak-
age specification.
4: After a conversion has completed, a 2.0TAD delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
FIGURE 10-2: ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
RS
CHOLD
CPIN
5 pF
= DAC capacitance
= 120 pF
VA
I LEAKAGE
VT = 0.6V
± 500 nA
VSS
Legend CPIN
VT
= input capacitance
= threshold voltage
6V
5V
I LEAKAGE = leakage current at the pin due to
VDD 4V
3V
various junctions
2V
RIC
SS
= interconnect resistance
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
5 6 7 8 9 1011
Sampling Switch
( kΩ )
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 83
PIC16F870/871
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
10.2
Selecting the A/D Conversion Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires a minimum 12TAD per 10-bit
conversion. The source of the A/D conversion clock is
software selected. The four possible options for TAD
are:
Table 10-1shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
• 2TOSC
• 8TOSC
• 32TOSC
• Internal RC oscillator
TABLE 10-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD)
ADCS1:ADCS0
Maximum Device Frequency
Max.
Operation
2TOSC
8TOSC
00
01
10
11
1.25 MHz
5 MHz
32TOSC
RC(1, 2, 3)
20 MHz
Note 1
Note 1: The RC source has a typical TAD time of 4 µs but can vary between 2-6 µs.
2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recommended for sleep
operation.
3: For extended voltage devices (LC), please refer to the Electrical Specifications section.
10.3
Configuring Analog Port Pins
The ADCON1, and TRIS registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
Note 1: When reading the port register, any pin
configured as an analog input channel will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
2: Analog levels on any pin that is defined as
a digital input (including the AN7:AN0
pins), may cause the input buffer to con-
sume current that is out of the device
specifications.
DS30569A-page 84
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
required before the next acquisition is started. After
this 2TAD wait, acquisition on the selected channel is
automatically started.
10.4
A/D Conversions
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed
In Figure 10-3, after the GO bit is set, the first time seg-
mant has a minimum of TCY and a maximum of TAD.
A/D
conversion
sample.
That
is,
the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is aborted, a 2TAD wait is
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 10-3: A/D CONVERSION TAD CYCLES
TCY to TAD
TAD1
TAD3
b8
TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b6 b5 b4 b3 b2 b1 b0
TAD2
b9
TAD4
b7
Conversion Starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
ADRES is loaded,
GO bit is cleared,
ADIF bit is set,
holding capacitor is connected to analog input.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 85
PIC16F870/871
10.4.1 A/D RESULT REGISTERS
SLEEP. If the A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits
wide. The A/D module gives the flexibility to left or right
justify the 10-bit result in the 16-bit result register. The
A/D Format Select bit (ADFM) controls this justifica-
tion. Figure 10-4 shows the operation of the A/D result
justification. The extra bits are loaded with ’0’s’. When
an A/D result will not overwrite these locations (A/D
disable), these registers may be used as two general
purpose 8-bit registers.
When the A/D clock source is another clock option (not
RC), a SLEEPinstruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To allow the con-
version to occur during SLEEP, ensure the
SLEEPinstruction immediately follows the
instruction that sets the GO/DONE bit.
10.5
A/D Operation During Sleep
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed the GO/DONE bit will be cleared and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
10.6
Effects of a Reset
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off, and any
conversion is aborted.
The value that is in the ADRESH:ADRESL registers is
not modified for
a
Power-on Reset. The
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
FIGURE 10-4: A/D RESULT JUSTIFICATION
10-Bit Result
ADFM = 0
ADFM = 1
0
7
7
2 1 0 7
0 7 6 5
0
0000 00
0000 00
ADRESH
ADRESL
ADRESH
ADRESL
10-bit Result
10-bit Result
Left Justified
Right Justified
DS30569A-page 86
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
TABLE 10-2: REGISTERS/BITS ASSOCIATED WITH A/D
POR,
BOR
MCLR,
WDT
Addr
Name
Bit 7
Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh
0Ch
INTCON
PIR1
GIE
PEIE
ADIF
ADIE
T0IE
RCIF
RCIE
INTE
TXIF
TXIE
RBIE
—
T0IF
INTF
RBIF
0000 000x
0000 -000
0000 000u
0000 -000
PSPIF(1)
PSPIE(1)
CCP1IF
CCP1IE
TMR2IF
TMR1IF
8Ch
1Eh
9Eh
1Fh
9Fh
85h
05h
PIE1
—
TMR2IE TMR1IE
0000 -000
xxxx xxxx
xxxx xxxx
0000 00-0
--0- 0000
--11 1111
--0x 0000
0000 -111
0000 -000
uuuu uuuu
uuuu uuuu
0000 00-0
--0- 0000
--11 1111
--0u 0000
0000 -111
ADRESH
ADRESL
ADCON0
ADCON1
TRISA
A/D Result Register High Byte
A/D Result Register Low Byte
ADCS1
ADFM
—
ADCS0
—
CHS2
—
CHS1
—
CHS0
GO/DONE
PCFG2
—
ADON
PCFG3
PCFG1
PCFG0
—
PORTA Data Direction Register
PORTA Data Latch when written: PORTA pins when read
PORTA
TRISE
—
—
89h(1)
IBF
OBF
IBOV
—
PSPMODE
—
—
—
PORTE Data Direction Bits
RE2 RE1
09h(1)
PORTE
—
—
RE0
---- -xxx
---- -uuu
Legend:
x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: These registers/bits are not available on the PIC16F870.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 87
PIC16F870/871
NOTES:
DS30569A-page 88
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
11.1
Configuration Bits
11.0 SPECIAL FEATURES OF THE
CPU
These devices have a host of features intended to max-
imize system reliability, minimize cost through elimina-
tion of external components, provide power saving
operating modes and offer code protection. These are:
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h -
3FFFh), which can be accessed only during program-
ming.
• OSC Selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-Circuit Serial Programming
• Low Voltage In-Circuit Serial Programming
• In-Circuit Debugger
These devices have a watchdog timer, which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only. It is
designed to keep the part in reset while the power sup-
ply stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
Additional information on special features is available in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 89
PIC16F870/871
REGISTER 11-1: CONFIGURATION WORD
CP1
CP0
DEBUG
—
WRT CPD
LVP
BODEN
CP1
CP0
PWRTE WDTE
F0SC1
F0SC0
bit0
Register: CONFIG
Address 2007h
bit13
bit 13-12:
(2)
bit 5-4: CP<1:0>: Flash Program Memory Code Protection bits
11= Code protection off
10= Not supported
01= Not supported
00= Code protection on
bit 11:
DEBUG: In-Circuit Debugger Mode
1= In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins.
0= In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger.
bit 10:
bit 9:
Unimplemented: Read as ‘1’
WRT: Flash Program Memory Write Enable
1= Unprotected program memory may be written to by EECON control
0= Unprotected program memory may not be written to by EECON control
bit 8:
bit 7:
bit 6:
bit 3:
bit 2:
CPD: Data EE Memory Code Protection
1= Code protection off
0= Data EEPROM memory code protected
LVP: Low Voltage In-Circuit Serial Programming Enable bit
1= RB3/PGM pin has PGM function, low voltage programming enabled
0= RB3 is digital I/O, HV on MCLR must be used for programming
(1)
BODEN: Brown-out Reset Enable bit
1= BOR enabled
0= BOR disabled
(1)
PWRTE: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE. Ensure
the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP<1:0> pairs have to be given the same value to enable the code protection scheme listed.
DS30569A-page 90
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
11.2
Oscillator Configurations
TABLE 11-1: CERAMIC RESONATORS
Ranges Tested:
11.2.1
OSCILLATOR TYPES
Mode
Freq
OSC1
OSC2
The PIC16F870/871 can be operated in four different
oscillator modes. The user can program two configura-
tion bits (FOSC1 and FOSC0) to select one of these
four modes:
XT
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF 68 - 100 pF
15 - 68 pF
15 - 68 pF
15 - 68 pF
15 - 68 pF
• LP
• XT
• HS
• RC
Low Power Crystal
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
Crystal/Resonator
These values are for design guidance only. See
notes at bottom of page.
High Speed Crystal/Resonator
Resistor/Capacitor
Resonators Used:
11.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
455 kHz Panasonic EFO-A455K04B
± 0.3%
± 0.5%
± 0.5%
± 0.5%
± 0.5%
2.0 MHz
4.0 MHz
8.0 MHz
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 11-1). The
PIC16F870/871 oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may give
a frequency out of the crystal manufacturers specifica-
tions. When in XT, LP or HS modes, the device can
have an external clock source to drive the OSC1/
CLKIN pin (Figure 11-2).
16.0 MHz Murata Erie CSA16.00MX
All resonators used did not have built-in capacitors.
FIGURE 11-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
(1)
C1
OSC1
To
internal
logic
XTAL
(3)
RF
OSC2
SLEEP
PIC16F870/871
(2)
RS
(1)
C2
Note 1: See Table 11-1 and Table 11-2 for rec-
ommended values of C1 and C2.
2: A series resistor (RS) may be required
for AT strip cut crystals.
3: RF varies with the crystal chosen.
FIGURE 11-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
OSC1
OSC2
Clock from
ext. system
PIC16F870/871
Open
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 91
PIC16F870/871
11.2.3 RC OSCILLATOR
TABLE 11-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (REXT) and capacitor (CEXT) values, and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C compo-
nents used. Figure 11-3 shows how the R/C combina-
tion is connected to the PIC16F870/871.
Cap.
Range
C2
Crystal
Freq
Cap. Range
C1
Osc Type
LP
32 kHz
200 kHz
200 kHz
1 MHz
33 pF
15 pF
33 pF
15 pF
XT
47-68 pF
15 pF
47-68 pF
15 pF
4 MHz
15 pF
15 pF
HS
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
15-33 pF
15-33 pF
20 MHz
FIGURE 11-3: RC OSCILLATOR MODE
These values are for design guidance only.
See notes at bottom of page.
VDD
Crystals Used
32 kHz
Epson C-001R32.768K-A
± 20 PPM
Rext
Internal
OSC1
200 kHz STD XTL 200.000 kHz
± 20 PPM
± 50 PPM
± 50 PPM
± 30 PPM
Clock
1 MHz
4 MHz
8 MHz
20 MHz
ECS ECS-10-13-1
Cext
VSS
PIC16F870/871
ECS ECS-40-20-1
EPSON CA-301 8.000M-C
OSC2/CLKOUT
FOSC/4
Recommended values:
EPSON CA-301 20.000M-C ± 30 PPM
3 kΩ ≤ Rext ≤ 100 kΩ
Cext > 20pF
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external compo-
nents.
3: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
4: When migrating from other PICmicro
devices, oscillator performance should be
verified.
DS30569A-page 92
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
WDT Reset, on MCLR reset during SLEEP, and Brown-
out Reset (BOR). They are not affected by a WDT
Wake-up, which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared differ-
ently in different reset situations as indicated in
Table 11-4. These bits are used in software to deter-
mine the nature of the reset. See Table 11-6 for a full
description of reset states of all registers.
11.3
Reset
The PIC16F870/871 differentiates between various
kinds of reset:
• Power-on Reset (POR)
• MCLR reset during normal operation
• MCLR reset during SLEEP
• WDT Reset (during normal operation)
• WDT Wake-up (during SLEEP)
• Brown-out Reset (BOR)
A simplified block diagram of the on-chip reset circuit is
shown in Figure 11-4.
These devices have a MCLR noise filter in the MCLR
reset path. The filter will detect and ignore small pulses.
Some registers are not affected in any reset condition.
Their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), on the MCLR and
It should be noted that a WDT Reset does not drive
MCLR pin low.
FIGURE 11-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
SLEEP
WDT
WDT
Module
Time-out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset
S
R
BODEN
OST/PWRT
OST
Chip_Reset
Q
10-bit Ripple counter
OSC1
(1)
On-chip
RC OSC
PWRT
10-bit Ripple counter
Enable PWRT
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 93
PIC16F870/871
11.4
Power-On Reset (POR)
11.8
Time-out Sequence
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, tie the MCLR pin directly
(or through a resistor) to VDD. This will eliminate exter-
nal RC components usually needed to create a Power-
on Reset. A maximum rise time for VDD is specified.
See Electrical Specifications for details.
On power-up, the time-out sequence is as follows: The
PWRT delay starts (if enabled) when a POR reset
occurs. Then OST starts counting 1024 oscillator
cycles when PWRT ends (LP, XT, HS). When the OST
ends, the device comes out of RESET.
If MCLR is kept low long enough, the time-outs will
expire. Bringing MCLR high will begin execution imme-
diately. This is useful for testing purposes or to synchro-
nize more than one PIC16CXX device operating in
parallel.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature,...) must be met to ensure oper-
ation. If these conditions are not met, the device must
be held in reset until the operating conditions are met.
Brown-out Reset may be used to meet the start-up con-
ditions. For additional information, refer to Application
Note, AN007, “Power-up Trouble Shooting”,
(DS00007).
Table 11-5 shows the reset conditions for the STATUS,
PCON and PC registers, while Table 11-6 shows the
reset conditions for all the registers.
11.9
Power Control/Status Register
(PCON)
11.5
Power-up Timer (PWRT)
The Power Control/Status Register, PCON, has up to
two bits depending upon the device.
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in reset as long as the PWRT is active. The
PWRT’s time delay allows VDD to rise to an acceptable
level. A configuration bit is provided to enable/disable
the PWRT.
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent resets to see if bit
BOR cleared, indicating a BOR occurred. The BOR bit
is a "don’t care" bit and is not necessarily predictable if
the Brown-out Reset circuitry is disabled (by clearing
bit BODEN in the Configuration Word).
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation. See DC
parameters for details (TPWRT, parameter #33).
Bit1 is POR (Power-on Reset Status bit). It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
11.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal oscil-
lator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
11.7
Brown-Out Reset (BOR)
The configuration bit, BODEN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(parameter #35, about 100µS), the brown-out situa-
tion will reset the device. If VDD falls below VBOR for
less than TBOR, a reset may not occur.
Once the brown-out occurs, the device will remain in
brown-out reset until VDD rises above VBOR. The
power-up timer then keeps the device in reset for
TPWRT (parameter #33, about 72mS). If VDD should
fall below VBOR during TPWRT, the brown-out reset
process will restart when VDD rises above VBOR with
the power-up timer reset. The power-up timer is
always enabled when the brown-out reset circuit is
enabled regardless of the state of the PWRT configu-
ration bit.
DS30569A-page 94
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
TABLE 11-3: TIME-OUT IN VARIOUS SITUATIONS
Oscillator Configuration
Power-up
PWRTE = 0
Brown-out
Wake-up from
SLEEP
PWRTE = 1
1024TOSC
—
XT, HS, LP
RC
72 ms + 1024TOSC
72 ms
72 ms + 1024TOSC
1024TOSC
72 ms
—
TABLE 11-4: STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
0
0
1
1
1
1
1
x
x
x
0
1
1
1
1
1
0
x
1
0
0
u
1
1
x
0
1
1
0
u
0
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 11-5: RESET CONDITION FOR SPECIAL REGISTERS
Program
STATUS
Register
PCON
Register
Condition
Counter
Power-on Reset
000h
000h
0001 1xxx
000u uuuu
0001 0uuu
0000 1uuu
uuu0 0uuu
0001 1uuu
uuu1 0uuu
---- --0x
---- --uu
---- --uu
---- --uu
---- --uu
---- --u0
---- --uu
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset
000h
000h
WDT Wake-up
PC + 1
Brown-out Reset
000h
PC + 1(1)
Interrupt wake-up from SLEEP
Legend: u= unchanged, x= unknown, -= unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 95
PIC16F870/871
TABLE 11-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
W
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
870 871
xxxx xxxx
N/A
uuuu uuuu
N/A
uuuu uuuu
N/A
INDF
TMR0
xxxx xxxx
0000h
uuuu uuuu
0000h
uuuu uuuu
PC + 1(2)
uuuq quuu(3)
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---u uuuu
uuuu uuuu(1)
ruuu -uuu(1)
uuuu -uuu(1)
---u ----(1)
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uu-u
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
ruuu -uuu
uuuu uuuu
---u ----
---- --uu
1111 1111
uuuu -uuu
uuuu uuuu
uuuu uuuu
PCL
STATUS
FSR
0001 1xxx
xxxx xxxx
--0x 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- -xxx
---0 0000
0000 000x
r000 -000
0000 -000
---0 ----
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
-000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 000x
0000 0000
0000 0000
xxxx xxxx
0000 00-0
1111 1111
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
r000 -000
0000 0000
---0 ----
---- --qq
1111 1111
0000 -010
0000 0000
xxxx xxxx
000q quuu(3)
uuuu uuuu
--0u 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---0 0000
0000 000u
r000 -000
0000 -000
---0 ----
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0000
-000 0000
uuuu uuuu
uuuu uuuu
--00 0000
0000 000x
0000 0000
0000 0000
uuuu uuuu
0000 00-0
1111 1111
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
r000 -000
0000 0000
---0 ----
---- --uu
1111 1111
0000 -010
0000 0000
uuuu uuuu
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
ADRESH
ADCON0
OPTION_REG
TRISA
TRISB
TRISC
TRISD
TRISE
PIE1
PIE2
PCON
PR2
TXSTA
SPBRG
ADRESL
Legend: u = unchanged,
x = unknown, -= unimplemented bit, read as ’0’, q= value depends
on condition, r= reserved maintain clear.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the inter-
rupt vector (0004h).
3: See Table 11-5 for reset value for specific condition.
DS30569A-page 96
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
TABLE 11-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
ADCON1
870 871
870 871
870 871
870 871
870 871
870 871
870 871
0--- 0000
0--- 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
x--- x000
---- ----
0--- 0000
0--- 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
u--- u000
---- ----
u--- uuuu
u--- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u--- uuuu
---- ----
EEDATA
EEADR
EEDATH
EEADRH
EECON1
EECON2
Legend: u = unchanged,
x = unknown, -= unimplemented bit, read as ’0’, q= value depends
on condition, r= reserved maintain clear.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the inter-
rupt vector (0004h).
3: See Table 11-5 for reset value for specific condition.
FIGURE 11-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 97
PIC16F870/871
FIGURE 11-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 11-8: SLOW RISE TIME (MCLR TIED TO VDD)
5V
1V
VDD
0V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30569A-page 98
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
11.10 Interrupts
The PIC16F870/871 family has up to 11 sources of
interrupt. The interrupt control register (INTCON)
records individual interrupt requests in flag bits. It also
has individual and global interrupt enable bits.
The peripheral interrupt flags are contained in the spe-
cial function registers, PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers, PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
Note: Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set regardless of the status of
their corresponding mask bit or the GIE bit
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
FIGURE 11-9: INTERRUPT LOGIC
EEIF
EEIE
PSPIF
PSPIE
Wake-up (If in SLEEP mode)
ADIF
ADIE
T0IF
T0IE
INTF
INTE
RCIF
RCIE
Interrupt to CPU
TXIF
TXIE
RBIF
RBIE
PEIE
GIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
The following table shows which devices have which interrupts.
Device
T0IF
INTF
RBIF
PSPIF
ADIF
RCIF
TXIF
CCP1IF TMR2IF TMR1IF EEIF
PIC16F870
PIC16F871
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 99
PIC16F870/871
11.10.1 INT INTERRUPT
11.10.3 PORTB INTCON CHANGE
External interrupt on the RB0/INT pin is edge triggered,
either rising, if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 11.13 for details on SLEEP mode.
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 3.2)
11.11 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt, (i.e., W register and STATUS
register). This will have to be implemented in software.
Since the upper 16 bytes of each bank are common in
the PIC16F870/871 devices, temporary holding regis-
ters W_TEMP, STATUS_TEMP and PCLATH_TEMP
should be placed in here. These 16 locations don’t
require banking and therefore, make it easier for con-
text save and restore. Example 11-1 can be used to
save and restore context for interrupts.
11.10.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 5.0)
EXAMPLE 11-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
:
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
;Copy W to TEMP register
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
:(ISR)
:
MOVF
MOVWF
SWAPF
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Swap W_TEMP into W
DS30569A-page 100
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
11.12 Watchdog Timer (WDT)
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEPinstruction.
Note: The CLRWDTand SLEEPinstructions clear
the WDT and the postscaler, if assigned to
the WDT, and prevent it from timing out and
generating a device RESET condition.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS register
will be cleared upon a Watchdog Timer time-out.
.
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 11.1).
FIGURE 11-10: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 5-1)
0
Postscaler
8
M
1
U
WDT Timer
X
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 5-1)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
FIGURE 11-11: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
(1)
2007h
Config. bits
(1)
BODEN
CP1
CP0
PWRTE
PSA
WDTE
PS2
FOSC1
PS1
FOSC0
PS0
81h,181h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 11-1 for operation of these bits.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 101
PIC16F870/871
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOPafter the SLEEPinstruction.
11.13 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
11.13.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
• If the interrupt occurs before the execution of a
SLEEPinstruction, the SLEEPinstruction will com-
plete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
• If the interrupt occurs during or after the execu-
tion of a SLEEPinstruction, the device will imme-
diately wake up from sleep. The SLEEPinstruction
will be completely executed before the wake-up.
Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
The MCLR pin must be at a logic high level (VIHMC).
11.13.1 WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
1. External reset input on MCLR pin.
2. Watchdog Timer wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change or some
Peripheral Interrupts.
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up, is cleared when SLEEPis invoked. The TO
bit is cleared if a WDT time-out occurred and caused
wake-up.
To ensure that the WDT is cleared, a CLRWDTinstruc-
tion should be executed before a SLEEPinstruction.
The following peripheral interrupts can wake the device
from SLEEP:
1. PSP read or write.
2. TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
3. CCP capture mode interrupt.
4. Special event trigger (Timer1 in asynchronous
mode using an external clock).
5. USART RX or TX (synchronous slave mode).
6. A/D conversion (when A/D clock source is RC).
7. EEPROM write operation completion
Other peripherals cannot generate interrupts since dur-
ing SLEEP, no on-chip clocks are present.
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
DS30569A-page 102
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
FIGURE 11-12: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(2)
TOST
CLKOUT(4)
INT pin
INTF flag
Interrupt Latency
(Note 2)
(INTCON<1>)
GIE bit
Processor in
SLEEP
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
fetched
Instruction
executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(PC - 1)
Inst(0004h)
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine.
If GIE = ’0’, execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
11.14 In-Circuit Debugger
11.16 ID Locations
When the DEBUG bit in the configuration word is pro-
grammed to a ’0’, the In-Circuit Debugger functionality
is enabled. This function allows simple debugging func-
tions when used with MPLAB. When the microcontrol-
ler has this feature enabled, some of the resources are
not available for general use. Table 11-7 shows which
features are consumed by the background debugger.
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are read-
able and writable during program/verify. It is recom-
mended that only the 4 least significant bits of the ID
location are used.
TABLE 11-7: DEBUGGER RESOURCES
I/O pins
RB6, RB7
Stack
1 level
Program Memory
Address 0000h must be NOP
Last 100h words
Data Memory
0x070(0x0F0, 0x170, 0x1F0)
0x1EB - 0x1EF
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, GND,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.
11.15 Program Verification/Code Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 103
PIC16F870/871
11.17 In-Circuit Serial Programming
11.18 Low Voltage ICSP Programming
PIC16F870/871 microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
The LVP bit of the configuration word enables low volt-
age ICSP programming. This mode allows the micro-
controller to be programmed via ICSP using a VDD
source in the operating voltage range. This only means
that VPP does not have to be brought to VIHH, but can
instead be left at the normal operating voltage. In this
mode, the RB3/PGM pin is dedicated to the program-
ming function and ceases to be a general purpose I/O
pin. During programming, VDD is applied to the MCLR
pin. To enter programming mode, VDD must be applied
to the RB3/PGM provided the LVP bit is set. The LVP
bit defaults to on (‘1’) from the factory.
When using ICSP, the part must be supplied 4.5V to
5.5V if a bulk erase will be executed. This includes
reprogramming of the code protect both from an on-
state to off-state. For all other cases of ICSP, the part
may be programmed at the normal operating voltages.
This means calibration values, unique user IDs or user
code can be reprogrammed or added.
Note 1: The high voltage programming mode is
always available, regardless of the state of
the LVP bit, by applying VIHH to the MCLR
pin.
For complete details of serial programming, please
refer to the In-Circuit Serial Programming (ICSP™)
Guide, (DS30277B).
2: While in low voltage ICSP mode, the RB3
pin can no longer be used as a general
purpose I/O pin.
If low-voltage programming mode is not used, the LVP
bit can be programmed to a '0' and RB3/PGM becomes
a digital I/O pin. However, the LVP bit may only be pro-
grammed when programming is entered with VIHH on
MCLR. The LVP bit can only be charged when using
high voltage on MCLR.
It should be noted, that once the LVP bit is programmed
to 0, only the high voltage programming mode is avail-
able and only high voltage programming mode can be
used to program the device.
When using low voltage ICSP, the part must be sup-
plied 4.5V to 5.5V if a bulk erase will be executed. This
includes reprogramming of the code protect bits from
an on-state to off-state. For all other cases of low volt-
age ICSP, the part may be programmed at the normal
operating voltage. This means calibration values,
unique user IDs or user code can be reprogrammed or
added.
DS30569A-page 104
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.
12.0 INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 12-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 12-1
shows the opcode field descriptions.
Table 12-2 lists the instructions recognized by the
MPASM assembler.
Figure 12-1 shows the general formats that the instruc-
tions can have.
Note: To maintain upward compatibility with
future PIC16CXX products, do not use the
OPTIONand TRISinstructions.
For byte-oriented instructions, ’f’ represents a file reg-
ister designator and ’d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
All examples use the following format to represent a
hexadecimal number:
The destination designator specifies where the result of
the operation is to be placed. If ’d’ is zero, the result is
placed in the W register. If ’d’ is one, the result is placed
in the file register specified in the instruction.
0xhh
where h signifies a hexadecimal digit.
FIGURE 12-1: GENERAL FORMAT FOR
INSTRUCTIONS
For bit-oriented instructions, ’b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ’f’ represents the number of the
file in which the bit is located.
Byte-oriented file register operations
13
8
7
6
0
0
OPCODE
d
f (FILE #)
For literal and control operations, ’k’ represents an
eight or eleven bit constant or literal value.
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
TABLE 12-1: OPCODE FIELD
DESCRIPTIONS
Bit-oriented file register operations
13 10 9
b (BIT #)
Field
Description
7
6
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
OPCODE
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Bit address within an 8-bit file register
Literal field, constant data or label
Literal and control operations
General
Don't care location (= 0or 1)
The assembler will generate code with x = 0. It
is the recommended form of use for compati-
bility with all Microchip software tools.
13
8
7
0
0
OPCODE
k (literal)
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
k = 8-bit immediate value
PC
TO
PD
Program Counter
Time-out bit
CALL and GOTO instructions only
13 11 10
OPCODE
k = 11-bit immediate value
k (literal)
Power-down bit
The instruction set is highly orthogonal and is grouped
into three basic categories:
A description of each instruction is available in the
• Byte-oriented operations
• Bit-oriented operations
PICmicro™
(DS33023).
Mid-Range
Reference
Manual,
• Literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 105
PIC16F870/871
TABLE 12-2: PIC16CXXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles 14-Bit Opcode
MSb
Status
Affected
Notes
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111 dfff ffff
0101 dfff ffff
0001 lfff ffff
0001 0xxx xxxx
1001 dfff ffff
0011 dfff ffff
1011 dfff ffff
1010 dfff ffff
1111 dfff ffff
0100 dfff ffff
1000 dfff ffff
0000 lfff ffff
0000 0xx0 0000
1101 dfff ffff
1100 dfff ffff
0010 dfff ffff
1110 dfff ffff
0110 dfff ffff
C,DC,Z
1,2
1,2
2
Z
Z
Z
Z
Z
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
Z
Z
Z
Move W to f
No Operation
-
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
C,DC,Z
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01 00bb bfff ffff
01 01bb bfff ffff
01 10bb bfff ffff
01 11bb bfff ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11 111x kkkk kkkk C,DC,Z
11 1001 kkkk kkkk
10 0kkk kkkk kkkk
00 0000 0110 0100
10 1kkk kkkk kkkk
11 1000 kkkk kkkk
11 00xx kkkk kkkk
00 0000 0000 1001
11 01xx kkkk kkkk
00 0000 0000 1000
00 0000 0110 0011
Z
TO,PD
Z
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
TO,PD
11 110x kkkk kkkk C,DC,Z
11 1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU Family
Reference Manual (DS33023).
DS30569A-page 106
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
12.1
Instruction Descriptions
Add Literal and W
ADDLW
ANDWF
Syntax:
AND W with f
[label] ANDWF f,d
0 ≤ f ≤ 127
Syntax:
[label] ADDLW
0 ≤ k ≤ 255
k
Operands:
Operation:
Operands:
d
[0,1]
(W) + k → (W)
Operation:
(W) .AND. (f) → (destination)
Status Affected: C, DC, Z
Status Affected:
Description:
Z
Description:
The contents of the W register
are added to the eight bit literal ’k’
and the result is placed in the W
register.
AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W register. If 'd' is 1, the result
is stored back in register 'f'.
BCF
Bit Clear f
ADDWF
Syntax:
Add W and f
Syntax:
Operands:
[label] BCF f,b
[label] ADDWF f,d
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 127
d
[0,1]
Operation:
0 → (f<b>)
Operation:
(W) + (f) → (destination)
Status Affected: None
Status Affected: C, DC, Z
Description:
Bit 'b' in register 'f' is cleared.
Description:
Add the contents of the W register
with register ’f’. If ’d’ is 0, the result
is stored in the W register. If ’d’ is
1, the result is stored back in reg-
ister ’f’.
BSF
Bit Set f
Syntax:
Operands:
[label] BSF f,b
ANDLW
AND Literal with W
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Syntax:
[label] ANDLW
k
Operands:
Operation:
Status Affected:
Description:
0 ≤ k ≤ 255
Operation:
1 → (f<b>)
(W) .AND. (k) → (W)
Status Affected: None
Description: Bit 'b' in register 'f' is set.
Z
The contents of W register are
AND’ed with the eight bit literal
'k'. The result is placed in the W
register.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 107
PIC16F870/871
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[label] BTFSS f,b
Syntax:
[label] CLRF
0 ≤ f ≤ 127
f
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
00h → (f)
1 → Z
Operation:
skip if (f<b>) = 1
Status Affected: None
Status Affected:
Description:
Z
Description:
If bit ’b’ in register ’f’ is ’0’, the next
The contents of register ’f’ are
cleared and the Z bit is set.
instruction is executed.
If bit ’b’ is ’1’, then the next instruc-
tion is discarded and a NOPis exe-
cuted instead making this a 2TCY
instruction.
CLRW
Clear W
Syntax:
[ label ] CLRW
None
BTFSC
Bit Test, Skip if Clear
Operands:
Operation:
Syntax:
[label] BTFSC f,b
00h → (W)
1 → Z
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Status Affected:
Description:
Z
Operation:
skip if (f<b>) = 0
W register is cleared. Zero bit (Z)
is set.
Status Affected: None
Description:
If bit ’b’ in register ’f’ is ’1’, the next
instruction is executed.
If bit ’b’, in register ’f’, is ’0’, the
next instruction is discarded, and
a NOPis executed instead, making
this a 2TCY instruction.
CLRWDT
Syntax:
Clear Watchdog Timer
[ label ] CLRWDT
None
CALL
Call Subroutine
Operands:
Operation:
Syntax:
[ label ] CALL k
00h → WDT
0 → WDT prescaler,
1 → TO
Operands:
Operation:
0 ≤ k ≤ 2047
(PC)+ 1→ TOS,
k → PC<10:0>,
1 → PD
(PCLATH<4:3>) → PC<12:11>
Status Affected: TO, PD
Status Affected: None
Description: CLRWDTinstruction resets the
Watchdog Timer. It also resets
the prescaler of the WDT. Status
bits TO and PD are set.
Description:
Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven bit immedi-
ate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALLis
a two cycle instruction.
DS30569A-page 108
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
COMF
Complement f
[ label ] COMF f,d
0 ≤ f ≤ 127
GOTO
Unconditional Branch
[ label ] GOTO k
0 ≤ k ≤ 2047
Syntax:
Operands:
Syntax:
Operands:
Operation:
d
[0,1]
k → PC<10:0>
Operation:
(f) → (destination)
PCLATH<4:3> → PC<12:11>
Status Affected:
Description:
Z
Status Affected: None
The contents of register ’f’ are
complemented. If ’d’ is 0, the
result is stored in W. If ’d’ is 1, the
result is stored back in register ’f’.
Description:
GOTOis an unconditional branch.
The eleven bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTOis a two
cycle instruction.
DECF
Decrement f
[label] DECF f,d
0 ≤ f ≤ 127
INCF
Increment f
Syntax:
Operands:
Syntax:
Operands:
[ label ] INCF f,d
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(f) - 1 → (destination)
Operation:
(f) + 1 → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Decrement register ’f’. If ’d’ is 0,
the result is stored in the W regis-
ter. If ’d’ is 1, the result is stored
back in register ’f’.
The contents of register ’f’ are
incremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
DECFSZ
Syntax:
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0 ≤ f ≤ 127
INCFSZ
Syntax:
Increment f, Skip if 0
[ label ] INCFSZ f,d
0 ≤ f ≤ 127
Operands:
d
[0,1]
Operands:
Operation:
(f) - 1 → (destination);
skip if result = 0
d
[0,1]
Operation:
(f) + 1 → (destination),
skip if result = 0
Status Affected: None
Description: The contents of register ’f’ are
Status Affected: None
decremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
then a NOPis executed instead
making it a 2TCY instruction.
Description: The contents of register ’f’ are
incremented. If ’d’ is 0, the result is
placed in the W register. If ’d’ is 1,
the result is placed back in regis-
ter ’f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0, a
NOPis executed instead making it
a 2TCY instruction.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 109
PIC16F870/871
IORLW
Inclusive OR Literal with W
MOVLW
Move Literal to W
[ label ] MOVLW k
0 ≤ k ≤ 255
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
(W) .OR. k → (W)
Z
k → (W)
Status Affected: None
The contents of the W register are
OR’ed with the eight bit literal 'k'.
The result is placed in the W reg-
ister.
Description:
The eight bit literal 'k' is loaded
into W register. The don’t cares
will assemble as 0’s.
MOVWF
Syntax:
Move W to f
IORWF
Inclusive OR W with f
[ label ] IORWF f,d
0 ≤ f ≤ 127
[ label ] MOVWF
0 ≤ f ≤ 127
f
Syntax:
Operands:
Operation:
Operands:
(W) → (f)
d
[0,1]
Status Affected: None
Operation:
(W) .OR. (f) → (destination)
Description:
Move data from W register to reg-
ister 'f'.
Status Affected:
Description:
Z
Inclusive OR the W register with
register 'f'. If 'd' is 0 the result is
placed in the W register. If 'd' is 1
the result is placed back in regis-
ter 'f'.
NOP
No Operation
[ label ] NOP
None
Syntax:
MOVF
Move f
Operands:
Operation:
Syntax:
Operands:
[ label ] MOVF f,d
No operation
0 ≤ f ≤ 127
Status Affected: None
Description: No operation.
d
[0,1]
Operation:
(f) → (destination)
Status Affected:
Description:
Z
The contents of register f are
moved to a destination dependant
upon the status of d. If d = 0, des-
tination is W register. If d = 1, the
destination is file register f itself. d
= 1 is useful to test a file register
since status flag Z is affected.
DS30569A-page 110
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
RETFIE
Return from Interrupt
[ label ] RETFIE
None
RLF
Rotate Left f through Carry
[ label ] RLF f,d
0 ≤ f ≤ 127
Syntax:
Syntax:
Operands:
Operands:
Operation:
d
[0,1]
TOS → PC,
1 → GIE
Operation:
See description below
C
Status Affected: None
Status Affected:
Description:
The contents of register ’f’ are
rotated one bit to the left through
the Carry Flag. If ’d’ is 0, the
result is placed in the W register.
If ’d’ is 1, the result is stored back
in register ’f’.
C
Register f
RETLW
Return with Literal in W
Syntax:
[ label ] RETLW k
RRF
Rotate Right f through Carry
[ label ] RRF f,d
0 ≤ f ≤ 127
Operands:
Operation:
0 ≤ k ≤ 255
Syntax:
Operands:
k → (W);
TOS → PC
d
[0,1]
Status Affected: None
Operation:
See description below
C
Description:
The W register is loaded with the
Status Affected:
Description:
eight bit literal ’k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two cycle instruction.
The contents of register ’f’ are
rotated one bit to the right through
the Carry Flag. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
C
Register f
RETURN
Syntax:
Return from Subroutine
[ label ] RETURN
None
SLEEP
Operands:
Operation:
Syntax:
[ label
]
TOS → PC
SLEEP
Status Affected: None
Operands:
Operation:
None
Description: Return from subroutine. The stack
00h → WDT,
0 → WDT prescaler,
1 → TO,
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two cycle
instruction.
0 → PD
Status Affected:
Description:
TO, PD
The power-down status bit, PD is
cleared. Time-out status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 111
PIC16F870/871
SUBLW
Subtract W from Literal
XORLW
Exclusive OR Literal with W
Syntax:
[ label ]
Syntax:
[label]
SUBLW k
XORLW k
Operands:
Operation:
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
k - (W) → (W)
Operation:
(W) .XOR. k → (W)
Status Affected: C, DC, Z
Status Affected:
Description:
Z
Description:
The W register is subtracted (2’s
The contents of the W register
are XOR’ed with the eight bit lit-
eral 'k'. The result is placed in
the W register.
complement method) from the
eight bit literal 'k'. The result is
placed in the W register.
XORWF
Syntax:
Exclusive OR W with f
[label] XORWF f,d
0 ≤ f ≤ 127
SUBWF
Subtract W from f
Syntax:
[ label ]
SUBWF f,d
Operands:
Operands:
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(W) .XOR. (f) → (destination)
Operation:
(f) - (W) → (destination)
Status Affected:
Description:
Z
Status Affected: C, DC, Z
Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0, the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
Description:
Subtract (2’s complement method)
W register from register 'f'. If 'd' is 0,
the result is stored in the W regis-
ter. If 'd' is 1, the result is stored
back in register 'f'.
SWAPF
Syntax:
Swap Nibbles in f
[ label ] SWAPF f,d
0 ≤ f ≤ 127
Operands:
d
[0,1]
Operation:
(f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Status Affected: None
Description:
The upper and lower nibbles of
register 'f' are exchanged. If 'd' is
0, the result is placed in W regis-
ter. If 'd' is 1, the result is placed in
register 'f'.
DS30569A-page 112
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
MPLAB allows you to:
13.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASM Assembler
- absolute listing file
- object code
- MPLAB-C17 and MPLAB-C18 C Compilers
- MPLINK/MPLIB Linker/Librarian
• Simulators
The ability to use MPLAB with Microchip’s simulator,
MPLAB-SIM, allows a consistent platform and the abil-
ity to easily switch from the cost-effective simulator to
the full featured emulator with minimal retraining.
- MPLAB-SIM Software Simulator
• Emulators
- MPLAB-ICE Real-Time In-Circuit Emulator
- PICMASTER®/PICMASTER-CE In-Circuit
13.2
MPASM Assembler
Emulator
MPASM is a full featured universal macro assembler for
all PICmicro MCU’s. It can produce absolute code
directly in the form of HEX files for device program-
mers, or it can generate relocatable objects for
MPLINK.
- ICEPIC™
• In-Circuit Debugger
- MPLAB-ICD for PIC16F877
• Device Programmers
MPASM has a command line interface and a Windows
shell and can be used as a standalone application on a
Windows 3.x or greater system. MPASM generates
relocatable object files, Intel standard HEX files, MAP
files to detail memory usage and symbol reference, an
absolute LST file which contains source lines and gen-
erated machine code, and a COD file for MPLAB
debugging.
- PRO MATE II Universal Programmer
- PICSTART Plus Entry-Level Prototype
Programmer
• Low-Cost Demonstration Boards
- SIMICE
- PICDEM-1
- PICDEM-2
- PICDEM-3
MPASM features include:
- PICDEM-17
- SEEVAL
• MPASM and MPLINK are integrated into MPLAB
projects.
- KEELOQ
• MPASM allows user defined macros to be created
for streamlined assembly.
13.1
MPLAB Integrated Development
Environment Software
• MPASM allows conditional assembly for multi pur-
pose source files.
• MPASM directives allow complete control over the
assembly process.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a Windows -based applica-
tion which contains:
13.3
MPLAB-C17 and MPLAB-C18
C Compilers
• Multiple functionality
- editor
The MPLAB-C17 and MPLAB-C18 Code Development
Systems are complete ANSI ‘C’ compilers and inte-
grated development environments for Microchip’s
PIC17CXXX and PIC18CXXX family of microcontrol-
lers, respectively. These compilers provide powerful
integration capabilities and ease of use not found with
other compilers.
- simulator
- programmer (sold separately)
- emulator (sold separately)
• A full featured editor
• A project manager
• Customizable tool bar and key mapping
• A status bar
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• On-line help
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 113
PIC16F870/871
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different pro-
cessors. The universal architecture of the MPLAB-ICE
allows expansion to support new PICmicro microcon-
trollers.
13.4
MPLINK/MPLIB Linker/Librarian
MPLINK is a relocatable linker for MPASM and
MPLAB-C17 and MPLAB-C18. It can link relocatable
objects from assembly or C source files along with pre-
compiled libraries using directives from a linker script.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced fea-
tures that are generally found on more expensive devel-
opment tools. The PC platform and Microsoft® Windows
3.x/95/98 environment were chosen to best make these
features available to you, the end user.
MPLIB is a librarian for pre-compiled code to be used
with MPLINK. When a routine from a library is called
from another source file, only the modules that contains
that routine will be linked in with the application. This
allows large libraries to be used efficiently in many dif-
ferent applications. MPLIB manages the creation and
modification of library files.
MPLAB-ICE 2000 is a full-featured emulator system
with enhanced trace, trigger, and data monitoring fea-
tures. Both systems use the same processor modules
and will operate across the full operating speed range
of the PICmicro MCU.
MPLINK features include:
• MPLINK works with MPASM and MPLAB-C17
and MPLAB-C18.
• MPLINK allows all memory areas to be defined as
sections to provide link-time flexibility.
13.7
PICMASTER/PICMASTER CE
The PICMASTER system from Microchip Technology is
a full-featured, professional quality emulator system.
This flexible in-circuit emulator provides a high-quality,
universal platform for emulating Microchip 8-bit
PICmicro microcontrollers (MCUs). PICMASTER sys-
tems are sold worldwide, with a CE compliant model
available for European Union (EU) countries.
MPLIB features include:
• MPLIB makes linking easier because single librar-
ies can be included instead of many smaller files.
• MPLIB helps keep code maintainable by grouping
related modules together.
• MPLIB commands allow libraries to be created
and modules to be added, listed, replaced,
deleted, or extracted.
13.8
ICEPIC
ICEPIC is a low-cost in-circuit emulation solution for the
Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X, and PIC16CXXX families of 8-bit one-time-
programmable (OTP) microcontrollers. The modular
system can support different subsets of PIC16C5X or
PIC16CXXX products through the use of
interchangeable personality modules or daughter
boards. The emulator is capable of emulating without
target application circuitry being present.
13.5
MPLAB-SIM Software Simulator
The MPLAB-SIM Software Simulator allows code
development in a PC host environment by simulating
the PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file or user-defined key press to any of the pins. The
execution can be performed in single step, execute until
break, or trace mode.
13.9
MPLAB-ICD In-Circuit Debugger
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPLAB-C18 and MPASM. The Soft-
ware Simulator offers the flexibility to develop and
debug code outside of the laboratory environment mak-
ing it an excellent multi-project software development
tool.
Microchip’s In-Circuit Debugger, MPLAB-ICD, is a pow-
erful, low-cost run-time development tool. This tool is
based on the flash PIC16F877 and can be used to
develop for this and other PICmicro microcontrollers
from the PIC16CXXX family. MPLAB-ICD utilizes the
In-Circuit Debugging capability built into the
PIC16F87X. This feature, along with Microchip’s In-Cir-
cuit Serial Programming protocol, offers cost-effective
in-circuit flash programming and debugging from the
graphical user interface of the MPLAB Integrated
Development Environment. This enables a designer to
develop and debug source code by watching variables,
single-stepping and setting break points. Running at
full speed enables testing hardware in real-time. The
MPLAB-ICD is also a programmer for the flash
PIC16F87X family.
13.6
MPLAB-ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers (MCUs). Software control of
MPLAB-ICE is provided by the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
DS30569A-page 114
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and download the
firmware to the emulator for testing. Additional proto-
type area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
13.10 PRO MATE II Universal Programmer
The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for instructions and error messages,
keys to enter commands and a modular detachable
socket assembly to support various package types. In
stand-alone mode the PRO MATE II can read, verify or
program PICmicro devices. It can also set code-protect
bits in this mode.
13.14 PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-Plus, and easily test firmware.
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connec-
tion to an LCD module and a keypad.
13.11 PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient.
PICSTART Plus supports all PICmicro devices with up
to 40 pins. Larger pin count devices such as the
PIC16C92X, and PIC17C76X may be supported with
an adapter socket. PICSTART Plus is CE compliant.
13.12 SIMICE Entry-Level
Hardware Simulator
SIMICE is an entry-level hardware development sys-
tem designed to operate in a PC-based environment
with Microchip’s simulator MPLAB-SIM. Both SIMICE
and MPLAB-SIM run under Microchip Technology’s
MPLAB Integrated Development Environment (IDE)
software. Specifically, SIMICE provides hardware sim-
ulation for Microchip’s PIC12C5XX, PIC12CE5XX, and
PIC16C5X families of PICmicro 8-bit microcontrollers.
SIMICE works in conjunction with MPLAB-SIM to pro-
vide non-real-time I/O port emulation. SIMICE enables
a developer to run simulator code for driving the target
system. In addition, the target system can provide input
to the simulator code. This capability allows for simple
and interactive debugging without having to manually
generate MPLAB-SIM stimulus files. SIMICE is a valu-
able debugging tool for entry-level system develop-
ment.
13.15 PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an addi-
tional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
13.13 PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 115
PIC16F870/871
13.16 PICDEM-17
The PICDEM-17 is an evaluation board that demon-
strates the capabilities of several Microchip microcon-
trollers,
including
PIC17C752,
PIC17C756,
PIC17C762, and PIC17C766. All necessary hardware
is included to run basic demo programs, which are sup-
plied on a 3.5-inch disk. A programmed sample is
included, and the user may erase it and program it with
the other sample programs using the PRO MATE II or
PICSTART Plus device programmers and easily debug
and test the sample code. In addition, PICDEM-17 sup-
ports down-loading of programs to and executing out of
external FLASH memory on board. The PICDEM-17 is
also usable with the MPLAB-ICE or PICMASTER emu-
lator, and all of the sample programs can be run and
modified using either emulator. Additionally, a gener-
ous prototype area is available for user hardware.
13.17 SEEVAL Evaluation and Programming
System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in trade-
off analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
13.18 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS eval-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
DS30569A-page 116
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
TABLE 13-1: DEVELOPMENT TOOLS FROM MICROCHIP
5 1 2 0 P M C
X X X C R M F
X X
H C S X
X X C 9 3
C 5 X 2 X /
C 4 X 2 X /
X X C 8 2 C 1 P I
X X 7 C 7 C 1 P I
X 4 C 7 C 1 P I
X X 9 C 6 C 1 P I
X 8 X 1 6 C I F P
X 8 C 6 C 1 P I
X X 7 C 6 C 1 P I
X 7 C 6 C 1 P I
X 6 2 6 1 F C I P
X X C 6 X C 1 P I
X 6 C 6 C 1 P I
X 5 C 6 C 1 P I
0 0 4 1 0 C I P
X X C 2 X C 1 P I
s l o o e T a r f t o w S s o r a t u l E m e r g g b e u D s r e m a m r g o P r
t i s K v a l E d a n d s a r o B o m e D
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 117
PIC16F870/871
NOTES:
DS30569A-page 118
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
14.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.................................................................................................................-55 to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4).......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V
Voltage on MCLR with respect to VSS (Note 2).............................................................................................0 to +13.25V
Voltage on RA4 with respect to Vss..................................................................................................................0 to +8.5V
Total power dissipation (Note 1)................................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. ± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3)....................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3) ..............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3)..................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3).............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin, rather than pulling
this pin directly to VSS.
3: PORTD and PORTE are not implemented on the 28-pin devices.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 119
PIC16F870/871
FIGURE 14-1: PIC16FXXX VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
20 MHz
Frequency
FIGURE 14-2: PIC16LFXXX VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
4 MHz
10 MHz
20 MHz
Frequency
Equation 1: FMAX = (6.0 MHz/V) (VDDAPPMIN - 2.0 V) + 4 MHz; VDDAPPMIN = 2.0V - 3.0V
Equation 2: FMAX = (10.0 MHz/V) (VDDAPPMIN - 3.0 V) + 10 MHz; VDDAPPMIN = 3.0V - 4.0V
Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
Note 2: FMAX has a maximum frequency of 10MHz.
DS30569A-page 120
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
14.1
DC Characteristics:
PIC16F870/871 (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
No.
Characteristic
Sym
Min Typ† Max Units
Conditions
D001 Supply Voltage
D001A
VDD
4.0
4.5
VBOR*
-
-
-
5.5
5.5
5.5
V
V
V
XT, RC and LP osc configuration
HS osc configuration
BOR enabled, Fmax = 14MHz (Note 7)
D002* RAM Data Retention
Voltage (Note 1)
VDR
-
-
1.5
-
V
D003
VDD start voltage to
ensure internal Power-on
Reset signal
VPOR
VSS
-
V
See section on Power-on Reset for details
D004* VDD rise rate to ensure
internal Power-on Reset
signal
SVDD
0.05
-
-
V/ms See section on Power-on Reset for details
D005 Brown-out Reset Voltage VBOR
3.7
-
4.0 4.35
V
BODEN bit in configuration word enabled
D010
D013
Supply Current (Note 2,5) IDD
1.6
4
mA XT, RC osc configuration
FOSC = 4 MHz, VDD = 5.5V (Note 4)
-
-
7
15
mA HS osc configuration
FOSC = 20 MHz, VDD = 5.5V
D015* Brown-out Reset Current ∆IBOR
85 200 µA BOR enabled VDD = 5.0V
(Note 6)
D020 Power-down Current
D021 (Note 3,5)
D021A
IPD
-
-
-
10.5 42 µA VDD = 4.0V, WDT enabled, -40°C to +85°C
1.5
1.5
16
19
µA VDD = 4.0V, WDT disabled, -0°C to +70°C
µA VDD = 4.0V, WDT disabled, -40°C to +85°C
D023* Brown-out Reset Current ∆IBOR
-
85 200 µA BOR enabled VDD = 5.0V
(Note 6)
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from character-
ization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 121
PIC16F870/871
14.2
DC Characteristics: PIC16LF870/871 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
DC CHARACTERISTICS
Param
No.
Characteristic
Sym Min Typ† Max Units
Conditions
D001
Supply Voltage
VDD
VDR
2.0
-
-
5.5
-
V
V
LP, XT, RC osc configuration (DC - 4 MHz)
D002* RAM Data Retention
Voltage (Note 1)
1.5
D003
VDD start voltage to
ensure internal Power-on
Reset signal
VPOR
-
VSS
-
-
-
V
See section on Power-on Reset for details
D004* VDD rise rate to ensure
internal Power-on Reset
signal
SVDD 0.05
V/ms See section on Power-on Reset for details
D005
D010
Brown-out Reset Voltage VBOR
3.7
4.0 4.35
V
BODEN bit in configuration word enabled
Supply Current (Note 2,5) IDD
-
0.6
2.0
mA XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
D010A
-
-
20
85
35
µA LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D015* Brown-out Reset Current ∆IBOR
200
µA BOR enabled VDD = 5.0V
(Note 6)
D020
D021
D021A
Power-down Current
(Note 3,5)
IPD
-
-
-
7.5
0.8
0.9
30
4.5
5
µA VDD = 3.0V, WDT enabled, -40°C to +85°C
µA VDD = 3.0V, WDT disabled, 0°C to +70°C
µA VDD = 3.0V, WDT disabled, -40°C to +85°C
D023* Brown-out Reset Current ∆IBOR
-
85
200
µA BOR enabled VDD = 5.0V
(Note 6)
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
DS30569A-page 122
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
14.3
DC Characteristics:
PIC16F870/871 (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Operating voltage VDD range as described in DC spec Section 14.1 and
DC CHARACTERISTICS
Section 14.2.
Param
No.
Characteristic
Sym
Min Typ† Max Units
Conditions
Input Low Voltage
I/O ports
VIL
D030
D030A
D031
D032
D033
with TTL buffer
VSS
VSS
VSS
VSS
VSS
-
-
-
-
-
0.15VDD
0.8V
0.2VDD
0.2VDD
0.3VDD
V
V
V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
MCLR, OSC1 (in RC mode)
OSC1 (in XT, HS and LP)
Ports RC3 and RC4
with Schmitt Trigger buffer
with SMBus
Note1
D034
D034A
VSS
-0.5
-
-
0.3VDD
0.6
V
V
For entire VDD range
for VDD = 4.5 to 5.5V
Input High Voltage
I/O ports
VIH
-
-
-
D040
D040A
with TTL buffer
2.0
0.25VDD
+ 0.8V
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
D041
D042
with Schmitt Trigger buffer
MCLR
0.8VDD
0.8VDD
0.7VDD
0.9VDD
-
-
-
-
VDD
VDD
VDD
VDD
V
V
V
V
For entire VDD range
Note1
D042A OSC1 (XT, HS and LP)
D043
OSC1 (in RC mode)
Ports RC3 and RC4
with Schmitt Trigger buffer
with SMBus
PORTB weak pull-up current
Input Leakage Current
(Notes 2, 3)
D044
D044A
D070
0.7VDD
1.4
50
-
-
VDD
5.5
400
V
V
For entire VDD range
for VDD = 4.5 to 5.5V
IPURB
IIL
250
µA VDD = 5V, VPIN = VSS
D060
I/O ports
-
-
±1
µA Vss ≤ VPIN ≤ VDD, Pin at hi-imped-
ance
D061
D063
MCLR, RA4/T0CKI
OSC1
-
-
-
-
±5
±5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc
configuration
Output Low Voltage
D080
D083
I/O ports
VOL
-
-
-
-
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
OSC2/CLKOUT (RC osc config)
Output High Voltage
D090
D092
I/O ports (Note 3)
VOH VDD - 0.7
VDD - 0.7
-
-
-
-
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
OSC2/CLKOUT (RC osc config)
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F870/871 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 123
PIC16F870/871
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Operating voltage VDD range as described in DC spec Section 14.1 and
DC CHARACTERISTICS
Section 14.2.
Param
No.
Characteristic
Sym
Min Typ† Max Units
Conditions
D150* Open-Drain High Voltage
VOD
-
-
-
-
8.5
V
RA4 pin
Capacitive Loading Specs on
Output Pins
D100
OSC2 pin
COSC2
-
-
15
pF In XT, HS and LP modes when exter-
nal clock is used to drive OSC1.
D101
D102
All I/O pins and OSC2 (in RC
mode) SCL, SDA in I2C mode
Data EEPROM Memory
Endurance
CIO
CB
-
-
-
-
50
400
pF
pF
D120
D121
ED
100K
-
-
-
E/W 25°C at 5V
V
VDD for read/write
VDRW Vmin
5.5
Using EECON to read/write
Vmin = min operating voltage
D122
Erase/write cycle time
Program FLASH Memory
Endurance
TDEW
-
4
8
ms
D130
D131
EP
VPR
1000
Vmin
Vmin
-
-
-
-
E/W 25°C at 5V
V
V
VDD for read
5.5
5.5
Vmin = min operating voltage
using EECON to read/write,
Vmin = min operating voltage
D132a VDD for erase/write
D133 Erase/Write cycle time
TPEW
-
4
8
ms
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F870/871 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS30569A-page 124
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
14.4
Timing Parameter Symbology
The timing parameter symbols have been created fol-
lowing one of the following formats:
(I2C specifications only)
(I2C specifications only)
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
T
Time
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
ST
DAT
STA
Hold
SU
Setup
DATA input hold
START condition
STO
STOP condition
FIGURE 14-3: LOAD CONDITIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF
15 pF
for all pins except OSC2, but including PORTD and PORTE outputs as ports
for OSC2 output
Note: PORTD and PORTE are not implemented on the PIC16F870.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 125
PIC16F870/871
FIGURE 14-4: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
4
Q1
OSC1
1
3
4
3
2
CLKOUT
TABLE 14-1: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter Sym Characteristic
No.
Min Typ†
Max
Units Conditions
FOSC External CLKIN Frequency
DC
DC
DC
DC
DC
0.1
—
—
—
—
—
—
4
4
MHz XT and RC osc mode
MHz HS osc mode (-04)
MHz HS osc mode (-20)
kHz LP osc mode
(Note 1)
20
200
4
Oscillator Frequency
(Note 1)
MHz RC osc mode
4
MHz XT osc mode
4
5
—
—
20
200
MHz HS osc mode
kHz LP osc mode
1
TOSC External CLKIN Period
250
250
50
—
—
—
—
ns XT and RC osc mode
ns HS osc mode (-04)
ns HS osc mode (-20)
µs LP osc mode
(Note 1)
—
—
5
—
—
Oscillator Period
(Note 1)
250
250
250
50
—
—
ns RC osc mode
—
10,000
250
250
—
ns XT osc mode
—
ns HS osc mode (-04)
ns HS osc mode (-20)
µs LP osc mode
—
5
—
2
3
TCY Instruction Cycle Time
200
TCY
DC
ns TCY = 4/FOSC
(Note 1)
TosL, External Clock in (OSC1) High 100
TosH or Low Time
—
—
—
—
—
—
—
—
—
25
50
15
ns XT oscillator
µs LP oscillator
ns HS oscillator
ns XT oscillator
ns LP oscillator
ns HS oscillator
2.5
15
—
4
TosR, External Clock in (OSC1) Rise
TosF or Fall Time
—
—
Legend: † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at "min." values with an external
clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is
"DC" (no clock) for all devices.
DS30569A-page 126
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
FIGURE 14-5: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
14
12
16
18
19
I/O Pin
(input)
15
17
I/O Pin
new value
old value
(output)
20, 21
Note: Refer to Figure 14-3 for load conditions.
TABLE 14-2: CLKOUT AND I/O TIMING REQUIREMENTS
Param Sym
No.
Characteristic
Min
Typ†
Max
Units Conditions
10*
11*
12*
13*
14*
15*
16*
17*
TosH2ckL OSC1↑ to CLKOUT↓
TosH2ckH OSC1↑ to CLKOUT↑
—
75
75
35
35
—
200
200
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
—
TckR
TckF
CLKOUT rise time
CLKOUT fall time
—
100
—
100
TckL2ioV CLKOUT ↓ to Port out valid
TioV2ckH Port in valid before CLKOUT ↑
TckH2ioI Port in hold after CLKOUT ↑
—
0.5TCY + 20
—
TOSC + 200
—
0
—
—
TosH2ioV OSC1↑ (Q1 cycle) to
—
100
255
Port out valid
18*
TosH2ioI OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
Standard (F)
Extended (LF)
100
200
—
—
—
—
ns
ns
19*
20*
TioV2osH Port input valid to OSC1↑ (I/O in setup time)
0
—
—
10
—
10
—
—
—
—
40
ns
ns
ns
ns
ns
ns
ns
TioR
Port output rise time
Port output fall time
INT pin high or low time
Standard (F)
Extended (LF)
Standard (F)
Extended (LF)
—
145
40
21*
TioF
—
—
145
—
22††* Tinp
23††* Trbp
TCY
TCY
RB7:RB4 change INT high or low time
—
Legend:
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 127
PIC16F870/871
FIGURE 14-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note: Refer to Figure 14-3 for load conditions.
FIGURE 14-7: BROWN-OUT RESET TIMING
VBOR
VDD
35
TABLE 14-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ†
Max Units
Conditions
30
TmcL
MCLR Pulse Width (low)
2
—
—
µs
VDD = 5V, -40°C to +85°C
31*
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7
18
33
ms VDD = 5V, -40°C to +85°C
32
Tost
Oscillation Start-up Timer Period
Power up Timer Period
—
28
—
1024 TOSC
—
132
2.1
—
TOSC = OSC1 period
33*
34
Tpwrt
TIOZ
72
—
ms VDD = 5V, -40°C to +85°C
µs
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
35
TBOR
Brown-out Reset pulse width
100
—
—
µs
VDD ≤ VBOR (D005)
Legend:
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS30569A-page 128
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
FIGURE 14-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RC0/T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 14-3 for load conditions.
TABLE 14-4: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max Units Conditions
40*
Tt0H
T0CKI High Pulse Width
No Prescaler
0.5TCY + 20
—
—
ns Must also meet
parameter 42
With Prescaler
No Prescaler
With Prescaler
No Prescaler
10
0.5TCY + 20
10
—
—
—
—
—
—
—
—
—
—
ns
41*
42*
Tt0L
Tt0P
T0CKI Low Pulse Width
T0CKI Period
ns Must also meet
parameter 42
ns
ns
TCY + 40
With Prescaler Greater of:
20 or TCY + 40
ns N = prescale value
(2, 4, ..., 256)
N
0.5TCY + 20
15
45*
46*
47*
Tt1H
Tt1L
Tt1P
T1CKI High Time Synchronous, Prescaler = 1
—
—
—
—
—
—
ns Must also meet
parameter 47
Synchronous, Standard(F)
ns
ns
Prescaler =
2,4,8
Extended(LF)
25
Asynchronous Standard(F)
Extended(LF)
30
—
—
—
—
—
—
—
—
—
—
ns
ns
50
T1CKI Low Time
Synchronous, Prescaler = 1
Synchronous, Standard(F)
0.5TCY + 20
ns Must also meet
parameter 47
15
25
ns
ns
Prescaler =
2,4,8
Extended(LF)
Asynchronous Standard(F)
Extended(LF)
30
50
—
—
—
—
—
—
ns
ns
T1CKI input period Synchronous
Standard(F)
Greater of:
30 OR TCY + 40
ns N = prescale value
(1, 2, 4, 8)
N
Extended(LF) Greater of:
50 OR TCY + 40
N = prescale value
(1, 2, 4, 8)
N
Asynchronous Standard(F)
Extended(LF)
Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN)
60
—
—
—
—
—
ns
ns
100
DC
Ft1
200
kHz
48
*
TCKEZtmr1 Delay from external clock edge to timer increment
2Tosc
—
7Tosc
—
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 129
PIC16F870/871
FIGURE 14-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1)
RC2/CCP1
(Capture Mode)
50
51
52
RC2/CCP1
(Compare or PWM Mode)
53
54
Note: Refer to Figure 14-3 for load conditions.
TABLE 14-5: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1)
Param Sym Characteristic
No.
Min
Typ† Max Units Conditions
50*
TccL CCP1 input
low time
No Prescaler
0.5TCY + 20
—
—
ns
Standard(F)
10
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
With Prescaler
No Prescaler
Extended(LF)
20
51*
TccH
0.5TCY + 20
CCP1 input
high time
Standard(F)
10
20
With Prescaler
Extended(LF)
52*
53*
TccP
3TCY + 40
ns N = prescale
value (1,4 or 16)
CCP1 input period
N
TccR CCP1 output rise time
TccF CCP1 output fall time
Standard(F)
Extended(LF)
Standard(F)
Extended(LF)
—
—
—
—
10
25
10
25
25
50
25
45
ns
ns
ns
ns
54*
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated.
These parameters are for design guidance only and are not tested.
DS30569A-page 130
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
FIGURE 14-10: PARALLEL SLAVE PORT TIMING (PIC16F871 ONLY)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 14-3 for load conditions.
TABLE 14-6: PARALLEL SLAVE PORT REQUIREMENTS (PIC16F871 ONLY)
Parameter
No.
Sym
Characteristic
Min Typ† Max Units Conditions
62
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)
20
25
—
—
—
—
ns
ns
Extended
Range Only
63*
64
TwrH2dtI WR↑ or CS↑ to data–in invalid (hold time) Standard(F)
Extended(LF)
20
35
—
—
—
—
ns
ns
TrdL2dtV RD↓ and CS↓ to data–out valid
—
—
—
—
80
90
ns
ns
Extended
Range Only
65
TrdH2dtI RD↑ or CS↓ to data–out invalid
10
—
30
ns
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 131
PIC16F870/871
FIGURE 14-11: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
121
Pin
121
RC7/RX/DT
Pin
120
122
Note: Refer to Figure 14-3 for load conditions.
TABLE 14-7: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param Sym
No.
Characteristic
Min
Typ† Max Units Conditions
Standard(F)
120
TckH2dtV
SYNC XMIT (MASTER &
SLAVE)
—
—
—
—
—
—
—
—
—
—
—
—
80
100
45
ns
ns
ns
ns
ns
ns
Clock high to data out valid
Extended(LF)
121
122
Tckrf
Tdtrf
Clock out rise time and fall time Standard(F)
(Master Mode)
Extended(LF)
50
Data out rise time and fall time Standard(F)
Extended(LF)
45
50
†:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 14-12: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
125
pin
RC7/RX/DT
pin
126
Note: Refer to Figure 14-3 for load conditions.
TABLE 14-8: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
125
TdtV2ckL
TckL2dtl
SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time)
15
—
—
—
—
ns
ns
126
Data hold after CK ↓ (DT hold time)
15
†:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30569A-page 132
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
TABLE 14-9: PIC16F870/871 (INDUSTRIAL)
PIC16LF870/871 (INDUSTRIAL)
Param Sym Characteristic
No.
Min
Typ†
Max
Units
Conditions
A01
A03
A04
A06
A07
NR
Resolution
—
—
—
—
—
—
—
—
—
—
10-bits
bit
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
EIL
Integral linearity error
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
< ± 1
< ± 1
< ± 1
< ± 1
LSb
LSb
LSb
LSb
EDL Differential linearity error
EOFF Offset error
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
EGN Gain error
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
(3)
A10
A20
—
—
guaranteed
—
—
—
V
VSS ≤ VAIN ≤ VREF
Monotonicity
VREF Reference voltage (VREF+ - VREF-)
2.0V
VDD + 0.3
Absolute minimum electrical
spec. to ensure 10-bit
accuracy.
A21 VREF+ Reference voltage High
VDD - 2.5V
VSS - 0.3V
VSS - 0.3
—
VDD + 0.3V
VREF+ - 2.0V
VREF + 0.3
10.0
V
V
Must meet spec. A20
Must meet spec. A20
A22
A25
A30
VREF- Reference voltage low
VAIN Analog input voltage
—
—
V
ZAIN Recommended impedance of
kΩ
analog voltage source
A40
A50
IAD
A/D conversion cur- Standard(F)
—
—
220
90
—
—
µA Average current consump-
rent (VDD)
tion when A/D is on.
(Note 1)
Extended(LF)
µA
IREF VREF input current (Note 2)
10
—
1000
µA During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD, see Section 10.1.
—
—
10
µA During A/D Conversion cycle
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 133
PIC16F870/871
FIGURE 14-13: A/D CONVERSION TIMING
BSF ADCON0, GO
1 TCY
(1)
(TOSC/2)
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
TABLE 14-10: A/D CONVERSION REQUIREMENTS
Param Sym Characteristic
No.
Min
Typ†
Max
Units
Conditions
Standard(F)
Extended(LF)
Standard(F)
Extended(LF)
130
TAD A/D clock period
1.6
3.0
2.0
3.0
—
—
—
—
µs
µs
TOSC based, VREF ≥ 3.0V
TOSC based, VREF ≥ 2.0V
4.0
6.0
—
6.0
9.0
12
µs A/D RC Mode
µs A/D RC Mode
TAD
131
132
TCNV Conversion time (not including S/H time)
(Note 1)
TACQ Acquisition time
Note 2
10*
40
—
—
—
µs
µs The minimum time is the ampli-
fier settling time. This may be
used if the "new" input voltage
has not changed by more than 1
LSb (i.e., 20.0 mV @ 5.12V)
from the last sampled voltage
(as stated on CHOLD).
134
TGO Q4 to A/D clock start
—
TOSC/2 §
—
—
If the A/D clock source is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 10.1 for min conditions.
DS30569A-page 134
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
15.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
The graphs and tables provided in this section are for
design guidance and are not tested.
In some graphs or tables, the data presented are out-
side specified operating range (i.e., outside specified
VDD range). This is for information only and devices
are ensured to operate properly only within the speci-
fied range.
The data presented in this section is a statistical sum-
mary of data collected on units from different lots over
a period of time and matrix samples. ’Typical’ repre-
sents the mean of the distribution at 25°C. ’Max’ or ’min’
represents (mean + 3σ) or (mean - 3σ) respectively,
where σ is standard deviation, over the whole temper-
ature range.
Graphs and Tables not available at this time.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 135
PIC16F870/871
NOTES:
DS30569A-page 136
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
16.0 PACKAGING INFORMATION
16.1
Package Marking Information
28-Lead PDIP (Skinny DIP)
Example
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
PIC16F870-I/SP
9910SAA
YYWWNNN
28-Lead SOIC
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
PIC16F870-I/SO
9910SAA
YYWWNNN
28-Lead SSOP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16F870-I/SS
9910SAA
YYWWNNN
Legend: MM...M Microchip part number information
XX...X Customer specific information*
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 137
PIC16F870/871
Package Marking Information (Cont’d)
40-Lead PDIP
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
AABBCDE
PIC16F871-I/P
9912SAA
44-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
PIC16F871
-I/PT
9911HAT
AABBCDE
44-Lead PLCC
Example
PIC16F871
-I/L
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
9903SAT
AABBCDE
DS30569A-page 138
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
E
E1
p
D
B
2
1
n
α
A
c
A2
A1
φ
L
β
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.026
.073
.068
.006
.309
.207
.402
.030
.007
4
0.65
Overall Height
A
.068
.064
.002
.299
.201
.396
.022
.004
0
.078
1.73
1.63
1.85
1.73
0.15
7.85
5.25
10.20
0.75
0.18
101.60
0.32
5
1.98
Molded Package Thickness
Standoff
A2
A1
E
.072
.010
.319
.212
.407
.037
.010
8
1.83
0.25
8.10
5.38
10.34
0.94
0.25
203.20
0.38
10
0.05
7.59
5.11
10.06
0.56
0.10
0.00
0.25
0
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
c
Lead Thickness
Foot Angle
φ
Lead Width
B
α
β
.010
0
.013
5
.015
10
Mold Draft Angle Top
Mold Draft Angle Bottom
0
5
10
0
5
10
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-150
Drawing No. C04-073
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 139
PIC16F870/871
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
L
A
c
B1
β
A1
eB
B
p
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.100
.150
.130
2.54
3.81
3.30
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A
A2
A1
E
.140
.160
3.56
4.06
.125
.015
.300
.275
1.345
.125
.008
.040
.016
.320
.135
3.18
0.38
7.62
6.99
34.16
3.18
0.20
1.02
3.43
.310
.285
1.365
.130
.012
.053
.019
.350
10
.325
.295
1.385
.135
.015
.065
.022
.430
15
7.87
7.24
8.26
7.49
35.18
3.43
0.38
1.65
0.56
10.92
15
E1
D
34.67
3.30
Tip to Seating Plane
Lead Thickness
L
c
0.29
Upper Lead Width
B1
B
1.33
Lower Lead Width
0.41
8.13
5
0.48
8.89
10
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
eB
α
5
β
5
10
15
5
10
15
*Controlling Parameter
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
DS30569A-page 140
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
E1
p
D
B
2
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
28
28
.050
.099
.091
.008
.407
.295
.704
.020
.033
4
1.27
2.50
2.31
0.20
10.34
7.49
17.87
0.50
0.84
4
Overall Height
A
.093
.104
2.36
2.64
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.288
.695
.010
.016
0
.094
.012
.420
.299
.712
.029
.050
8
2.24
0.10
10.01
7.32
17.65
0.25
0.41
0
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle Top
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.013
.020
15
0.23
0.36
0
0.28
0.42
12
0.33
0.51
15
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
12
15
0
12
15
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 141
PIC16F870/871
40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)
E1
D
2
α
n
1
E
A2
A
L
c
B1
B
β
A1
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
40
MAX
n
p
Number of Pins
Pitch
40
.100
.175
.150
2.54
Top to Seating Plane
A
.160
.190
.160
4.06
3.56
4.45
3.81
4.83
4.06
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.140
.015
.595
.530
2.045
.120
.008
.030
.014
.620
5
0.38
15.11
13.46
51.94
3.05
0.20
0.76
0.36
15.75
5
.600
.545
2.058
.130
.012
.050
.018
.650
10
.625
.560
2.065
.135
.015
.070
.022
.680
15
15.24
13.84
52.26
3.30
0.29
1.27
0.46
16.51
10
15.88
14.22
52.45
3.43
0.38
1.78
0.56
17.27
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
eB
α
β
5
10
15
5
10
15
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
DS30569A-page 142
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
1
B
n
°
CH x 45
α
A
c
φ
β
A1
A2
L
(F)
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Pins
Pitch
44
.031
11
0.80
11
Pins per Side
Overall Height
n1
A
.039
.037
.002
.018
.043
.039
.004
.024
.039
3.5
.047
1.00
0.95
1.10
1.00
0.10
0.60
1.20
Molded Package Thickness
Standoff
A2
A1
L
(F)
φ
.041
.006
.030
1.05
0.15
0.75
0.05
0.45
1.00
0
Foot Length
Footprint (Reference)
Foot Angle
0
.463
.463
.390
.390
.004
.012
.025
5
7
.482
.482
.398
.398
.008
.017
.045
15
3.5
12.00
12.00
10.00
10.00
0.15
0.38
0.89
10
7
12.25
12.25
10.10
10.10
0.20
0.44
1.14
15
Overall Width
E
D
.472
.472
.394
.394
.006
.015
.035
10
11.75
11.75
9.90
9.90
0.09
0.30
0.64
5
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
CH
α
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
β
5
10
15
5
10
15
*Controlling Parameter
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 143
PIC16F870/871
44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
E
E1
#leads=n1
D
D1
n 1 2
CH2 x 45°
CH1 x 45°
α
A3
A2
A
35°
B1
B
c
A1
β
p
E2
D2
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Pins
Pitch
44
.050
11
1.27
11
Pins per Side
Overall Height
n1
A
.165
.145
.020
.024
.040
.000
.685
.685
.650
.650
.590
.590
.008
.026
.013
0
.173
.153
.028
.029
.045
.005
.690
.690
.653
.653
.620
.620
.011
.029
.020
5
.180
4.19
3.68
0.51
0.61
1.02
0.00
17.40
17.40
16.51
16.51
14.99
14.99
0.20
0.66
0.33
0
4.39
3.87
0.71
0.74
1.14
0.13
17.53
17.53
16.59
16.59
15.75
15.75
0.27
0.74
0.51
5
4.57
Molded Package Thickness
Standoff
A2
A1
A3
CH1
CH2
E
.160
.035
.034
.050
.010
.695
.695
.656
.656
.630
.630
.013
.032
.021
10
4.06
0.89
0.86
1.27
0.25
17.65
17.65
16.66
16.66
16.00
16.00
0.33
0.81
0.53
10
Side 1 Chamfer Height
Corner Chamfer 1
Corner Chamfer (others)
Overall Width
Overall Length
D
Molded Package Width
Molded Package Length
Footprint Width
E1
D1
E2
D2
c
Footprint Length
Lead Thickness
Upper Lead Width
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
B1
B
α
β
0
5
10
0
5
10
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-048
DS30569A-page 144
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
Special Trigger Output of CCP1 ........................ 59
Section ....................................................................... 57
Special Event Trigger and A/D Conversions ............. 59
Capture/Compare/PWM (CCP)
INDEX
A
A/D ..................................................................................... 79
ADCON0 Register ...................................................... 79
ADCON1 Register ...................................................... 80
ADIF bit ...................................................................... 81
Analog Input Model Block Diagram ............................ 83
Analog Port Pins ...................................... 7, 8, 9, 35, 36
Block Diagram ............................................................ 82
Configuring Analog Port Pins ..................................... 84
Configuring the Interrupt ............................................ 81
Configuring the Module .............................................. 81
Conversion Clock ....................................................... 84
Conversions ............................................................... 85
Delays ........................................................................ 83
Effects of a Reset ....................................................... 86
GO/DONE bit ............................................................. 81
Internal Sampling Switch (Rss) Impedence ............... 82
Operation During Sleep ............................................. 86
Sampling Requirements ............................................. 82
Source Impedence ..................................................... 82
Time Delays ............................................................... 83
Absolute Maximum Ratings ............................................. 119
ADRES Register s ........................................................ 13, 79
Application Notes
CCP1
RC2/CCP1 Pin ................................................. 7, 8
CCP2
RC1/T1OSI/CCP2 Pin ..................................... 7, 8
PWM Block Diagram ................................................. 59
PWM Mode ................................................................ 59
CCP1CON ......................................................................... 15
CCP1M0 bit ....................................................................... 57
CCP1M1 bit ....................................................................... 57
CCP1M2 bit ....................................................................... 57
CCP1M3 bit ....................................................................... 57
CCP1X bit .......................................................................... 57
CCP1Y bit .......................................................................... 57
CCP2CON ......................................................................... 15
CCPR1H Register .................................................. 13, 15, 57
CCPR1L Register ........................................................ 15, 57
CCPR2H Register .............................................................. 15
CCPR2L Register .............................................................. 15
Code Examples
Indirect Addressing .................................................... 24
Code Protection ......................................................... 89, 103
Computed GOTO ............................................................... 24
Configuration Bits .............................................................. 89
AN552 (Implementing Wake-up on Key Strokes
Using PIC16CXXX) .................................................... 29
AN556 (Table Reading Using PIC16CXX) ................. 24
Architecture
PIC16F870 Block Diagram .......................................... 5
PIC16F871 Block Diagram .......................................... 6
Assembler
D
Data Memory ..................................................................... 11
Bank Select (RP1:RP0 Bits) ................................ 11, 16
General Purpose Registers ....................................... 11
Register File Map ...................................................... 12
Special Function Registers ........................................ 13
DC Characteristics ........................................................... 121
Development Support ...................................................... 113
Device Overview .................................................................. 5
Direct Addressing .............................................................. 25
MPASM Assembler .................................................. 113
B
Banking, Data Memory ................................................ 11, 16
Block Diagrams
A/D ............................................................................. 82
Analog Input Model .................................................... 83
Capture ...................................................................... 58
Compare .................................................................... 59
PWM .......................................................................... 59
Timer0/WDT Prescaler .............................................. 47
Timer2 ........................................................................ 55
USART Receive ......................................................... 69
USART Transmit ........................................................ 67
BOR. See Brown-out Reset
E
Electrical Characteristics ................................................. 119
Errata ................................................................................... 4
F
Firmware Instructions ...................................................... 105
FSR Register ................................................... 13, 14, 15, 24
I
I/O Ports ............................................................................ 27
ID Locations ............................................................... 89, 103
In-Circuit Serial Programming (ICSP) ........................ 89, 104
INDF .................................................................................. 15
INDF Register ........................................................ 13, 14, 24
Indirect Addressing ...................................................... 24, 25
FSR Register ............................................................. 11
Instruction Format ............................................................ 105
Instruction Set .................................................................. 105
ADDLW .................................................................... 107
ADDWF ................................................................... 107
ANDLW .................................................................... 107
ANDWF ................................................................... 107
BCF ......................................................................... 107
BSF .......................................................................... 107
BTFSC ..................................................................... 108
BTFSS ..................................................................... 108
CALL ........................................................................ 108
CLRF ....................................................................... 108
BRGH bit ............................................................................ 65
Brown-out Reset (BOR) ................................... 89, 93, 95, 96
BOR Status (BOR Bit) ................................................ 23
C
Capture/Compare/PWM
Capture
Block Diagram ................................................... 58
CCP1CON Register ........................................... 57
CCP1IF .............................................................. 58
Mode .................................................................. 58
Prescaler ............................................................ 58
CCP Timer Resources ............................................... 57
Compare
Block Diagram ................................................... 59
Mode .................................................................. 59
Software Interrupt Mode .................................... 59
Special Event Trigger ........................................ 59
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 145
PIC16F870/871
CLRW ......................................................................108
CLRWDT ..................................................................108
COMF ......................................................................109
DECF .......................................................................109
DECFSZ ...................................................................109
GOTO ......................................................................109
INCF .........................................................................109
INCFSZ ....................................................................109
IORLW .....................................................................110
IORWF .....................................................................110
MOVF .......................................................................110
MOVLW ...................................................................110
MOVWF ...................................................................110
NOP .........................................................................110
RETFIE ....................................................................111
RETLW ....................................................................111
RETURN ..................................................................111
RLF ..........................................................................111
RRF ..........................................................................111
SLEEP .....................................................................111
SUBLW ....................................................................112
SUBWF ....................................................................112
SWAPF ....................................................................112
XORLW ....................................................................112
XORWF ....................................................................112
Summary Table ........................................................106
INTCON .............................................................................15
INTCON Register ...............................................................18
GIE Bit ........................................................................18
INTE Bit ......................................................................18
INTF Bit ......................................................................18
PEIE Bit ......................................................................18
RBIE Bit .....................................................................18
RBIF Bit ................................................................18, 29
T0IE Bit ......................................................................18
T0IF Bit ......................................................................18
Internal Sampling Switch (Rss) Impedence .......................82
Interrupt Sources .......................................................... 89, 99
Block Diagram ............................................................99
Interrupt on Change (RB7:RB4 ) ................................29
RB0/INT Pin, External ...................................... 7, 8, 100
TMR0 Overflow ........................................................100
USART Receive/Transmit Complete .........................63
Interrupts, Context Saving During ....................................100
Interrupts, Enable Bits
M
Master Clear (MCLR) ....................................................... 7, 8
MCLR Reset, Normal Operation .................... 93, 95, 96
MCLR Reset, SLEEP ..................................... 93, 95, 96
Memory Organization
Data Memory ............................................................. 11
Program Memory ....................................................... 11
MPLAB Integrated Development Environment Software . 113
O
OPCODE Field Descriptions ............................................ 105
OPTION ............................................................................. 15
OPTION_REG Register ..................................................... 17
INTEDG Bit ................................................................ 17
PS2:PS0 Bits ............................................................. 17
PSA Bit ...................................................................... 17
RBPU Bit ................................................................... 17
T0CS Bit .................................................................... 17
T0SE Bit .................................................................... 17
OSC1/CLKIN Pin ............................................................. 7, 8
OSC2/CLKOUT Pin ......................................................... 7, 8
Oscillator Configuration ............................................... 89, 91
HS ........................................................................ 91, 95
LP ........................................................................ 91, 95
RC ................................................................. 91, 92, 95
XT ........................................................................ 91, 95
Oscillator, WDT ................................................................ 101
Output of TMR2 ................................................................. 55
P
Packaging ........................................................................ 137
Paging, Program Memory ............................................ 11, 24
Parallel Slave Port (PSP) ......................................... 9, 33, 36
Block Diagram ........................................................... 36
RE0/RD/AN5 Pin ............................................. 9, 35, 36
RE1/WR/AN6 Pin ............................................. 9, 35, 36
RE2/CS/AN7 Pin .............................................. 9, 35, 36
Read Waveforms ....................................................... 37
Select (PSPMODE Bit) .................................. 33, 34, 36
Write Waveforms ....................................................... 37
PCL Register ................................................... 13, 14, 15, 24
PCLATH Register ............................................ 13, 14, 15, 24
PCON Register ...................................................... 15, 23, 94
BOR Bit ...................................................................... 23
POR Bit ...................................................................... 23
PIC16F876 Pinout Description ............................................ 7
PICDEM-1 Low-Cost PICmicro Demo Board .................. 115
PICDEM-2 Low-Cost PIC16CXX Demo Board ................ 115
PICDEM-3 Low-Cost PIC16CXXX Demo Board ............. 115
PICSTART Plus Entry Level Development System ...... 115
PIE1 Register ............................................................... 15, 19
PIE2 Register ............................................................... 15, 21
Pinout Descriptions
Global Interrupt Enable (GIE Bit) ......................... 18, 99
Interrupt on Change (RB7:RB4) Enable
(RBIE Bit) ........................................................... 18, 100
Peripheral Interrupt Enable (PEIE Bit) .......................18
RB0/INT Enable (INTE Bit) ........................................18
TMR0 Overflow Enable (T0IE Bit) ..............................18
Interrupts, Flag Bits
Interrupt on Change (RB7:RB4) Flag
(RBIF Bit) ..................................................... 18, 29, 100
RB0/INT Flag (INTF Bit) .............................................18
TMR0 Overflow Flag (T0IF Bit) .......................... 18, 100
PIC16F870 .................................................................. 7
PIC16F871 .................................................................. 8
PIR1 Register .................................................................... 20
PIR2 Register .................................................................... 22
POP ................................................................................... 24
PORTA ...................................................................... 7, 8, 15
Analog Port Pins ...................................................... 7, 8
Initialization ................................................................ 27
PORTA Register ........................................................ 27
RA3,RA0 and RA5 Port Pins ..................................... 27
RA4/T0CKI Pin .................................................. 7, 8, 27
RA5/AN4 Pin ........................................................... 7, 8
TRISA Register .......................................................... 27
K
KeeLoq Evaluation and Programming Tools .................116
L
Loading of PC ....................................................................24
DS30569A-page 146
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
PORTA Register ................................................................ 13
PORTB ....................................................................... 7, 8, 15
PORTB Register ........................................................ 29
Pull-up Enable (RBPU Bit) ......................................... 17
RB0/INT Edge Select (INTEDG Bit) ........................... 17
RB0/INT Pin, External ...................................... 7, 8, 100
RB3:RB0 Port Pins .................................................... 29
RB7:RB4 Interrupt on Change ................................. 100
RB7:RB4 Interrupt on Change Enable
Program Counter
Reset Conditions ....................................................... 95
Program Memory ............................................................... 11
Interrupt Vector .......................................................... 11
Paging ................................................................. 11, 24
Program Memory Map ............................................... 11
Reset Vector .............................................................. 11
Program Verification ........................................................ 103
Programming Pin (VPP) ................................................... 7, 8
Programming, Device Instructions ................................... 105
PUSH ................................................................................. 24
(RBIE Bit) ........................................................... 18, 100
RB7:RB4 Interrupt on Change Flag
(RBIF Bit) ..................................................... 18, 29, 100
RB7:RB4 Port Pins .................................................... 29
TRISB Register .......................................................... 29
PORTB Register ................................................................ 13
PORTC ...................................................................... 7, 8, 15
Block Diagram ............................................................ 31
PORTC Register ........................................................ 31
RC0/T1OSO/T1CKI Pin ........................................... 7, 8
RC1/T1OSI/CCP2 Pin .............................................. 7, 8
RC2/CCP1 Pin ......................................................... 7, 8
RC3 Pin .................................................................... 7, 8
RC4 Pin .................................................................... 7, 8
RC5 Pin .................................................................... 7, 8
RC6/TX/CK Pin .................................................. 7, 8, 64
RC7/RX/DT Pin ............................................ 7, 8, 64, 65
TRISC Register .................................................... 31, 63
PORTC Register ................................................................ 13
PORTD .................................................................... 9, 15, 36
Block Diagram ............................................................ 33
Parallel Slave Port (PSP) Function ............................ 33
PORTD Register ........................................................ 33
TRISD Register .......................................................... 33
PORTD Register ................................................................ 13
PORTE ........................................................................... 9, 15
Analog Port Pins .............................................. 9, 35, 36
Block Diagram ............................................................ 34
Input Buffer Full Status (IBF Bit) ................................ 34
Input Buffer Overflow (IBOV Bit) ................................ 34
Output Buffer Full Status (OBF Bit) ............................ 34
PORTE Register ........................................................ 34
PSP Mode Select (PSPMODE Bit) ................ 33, 34, 36
RE0/RD/AN5 Pin .............................................. 9, 35, 36
RE1/WR/AN6 Pin ............................................. 9, 35, 36
RE2/CS/AN7 Pin .............................................. 9, 35, 36
TRISE Register .......................................................... 34
PORTE Register ................................................................ 13
Postscaler, WDT
R
RAM. See Data Memory
RCREG .............................................................................. 15
RCSTA Register .......................................................... 15, 64
CREN Bit ................................................................... 64
FERR Bit .................................................................... 64
OERR Bit ................................................................... 64
RX9 Bit ...................................................................... 64
RX9D Bit .................................................................... 64
SPEN Bit .............................................................. 63, 64
SREN Bit ................................................................... 64
Register File ....................................................................... 11
Register File Map ............................................................... 12
Registers
FSR Summary ........................................................... 15
INDF Summary .......................................................... 15
INTCON Summary .................................................... 15
OPTION Summary .................................................... 15
PCL Summary ........................................................... 15
PCLATH Summary .................................................... 15
PORTB Summary ...................................................... 15
STATUS Summary .................................................... 15
TMR0 Summary ........................................................ 15
TRISB Summary ........................................................ 15
Reset ........................................................................... 89, 93
Block Diagram ........................................................... 93
Reset Conditions for All Registers ............................. 96
Reset Conditions for PCON Register ........................ 95
Reset Conditions for Program Counter ..................... 95
Reset Conditions for STATUS Register .................... 95
S
SEEVAL Evaluation and Programming System ........... 116
SLEEP ................................................................. 89, 93, 102
Software Simulator (MPLAB-SIM) ................................... 114
SPBRG .............................................................................. 15
SPBRG Register ................................................................ 14
Special Features of the CPU ............................................. 89
Special Function Registers ................................................ 13
Special Function Register Summary ......................... 13
Speed, Operating ................................................................ 1
Stack .................................................................................. 24
Overflows ................................................................... 24
Underflow .................................................................. 24
STATUS Register ........................................................ 15, 16
C Bit ........................................................................... 16
DC Bit ........................................................................ 16
IRP Bit ....................................................................... 16
PD Bit .................................................................. 16, 93
RP1:RP0 Bits ............................................................. 16
TO Bit .................................................................. 16, 93
Z Bit ........................................................................... 16
Assignment (PSA Bit) ................................................ 17
Rate Select (PS2:PS0 Bits) ....................................... 17
Power-down Mode. See SLEEP
Power-on Reset (POR) .............................. 89, 93, 94, 95, 96
Oscillator Start-up Timer (OST) ........................... 89, 94
POR Status (POR Bit) ................................................ 23
Power Control (PCON) Register ................................ 94
Power-down (PD Bit) ........................................... 16, 93
Power-up Timer (PWRT) ..................................... 89, 94
Time-out (TO Bit) ................................................. 16, 93
Time-out Sequence on Power-up ........................ 97, 98
PR2 .................................................................................... 15
PR2 Register ................................................................ 14, 55
Prescaler, Timer0
Assignment (PSA Bit) ................................................ 17
Rate Select (PS2:PS0 Bits) ....................................... 17
PRO MATE II Universal Programmer ........................... 115
Product Identification System .......................................... 193
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 147
PIC16F870/871
TMR0 Register ................................................................... 13
TMR1CS bit ....................................................................... 51
TMR1H .............................................................................. 15
TMR1H Register ................................................................ 13
TMR1L ............................................................................... 15
TMR1L Register ................................................................. 13
TMR1ON bit ....................................................................... 51
TMR2 ................................................................................. 15
TMR2 Register ................................................................... 13
TMR2ON bit ....................................................................... 55
TOUTPS0 bit ..................................................................... 55
TOUTPS1 bit ..................................................................... 55
TOUTPS2 bit ..................................................................... 55
TOUTPS3 bit ..................................................................... 55
TRISA ................................................................................ 15
TRISA Register .................................................................. 14
TRISB ................................................................................ 15
TRISB Register .................................................................. 14
TRISC ................................................................................ 15
TRISC Register .................................................................. 14
TRISD ................................................................................ 15
TRISD Register .................................................................. 14
TRISE ................................................................................ 15
TRISE Register ............................................................ 14, 34
IBF Bit ........................................................................ 34
IBOV Bit ..................................................................... 34
OBF Bit ...................................................................... 34
PSPMODE Bit ................................................ 33, 34, 36
TXREG .............................................................................. 15
TXSTA ............................................................................... 15
TXSTA Register ................................................................. 63
BRGH Bit ................................................................... 63
CSRC Bit ................................................................... 63
SYNC Bit ................................................................... 63
TRMT Bit .................................................................... 63
TX9 Bit ....................................................................... 63
TX9D Bit .................................................................... 63
TXEN Bit .................................................................... 63
T
T1CKPS0 bit ......................................................................51
T1CKPS1 bit ......................................................................51
T1CON ...............................................................................15
T1CON Register ........................................................... 15, 51
T1OSCEN bit .....................................................................51
T1SYNC bit ........................................................................51
T2CKPS0 bit ......................................................................55
T2CKPS1 bit ......................................................................55
T2CON Register ........................................................... 15, 55
TAD .....................................................................................84
Timer0
Clock Source Edge Select (T0SE Bit) ........................17
Clock Source Select (T0CS Bit) .................................17
Overflow Enable (T0IE Bit) ........................................18
Overflow Flag (T0IF Bit) ..................................... 18, 100
Overflow Interrupt ....................................................100
RA4/T0CKI Pin, External Clock ...............................7, 8
Timer1 ................................................................................51
RC0/T1OSO/T1CKI Pin ...........................................7, 8
RC1/T1OSI/CCP2 Pin ..............................................7, 8
Timers
Timer0
External Clock ....................................................48
Interrupt ..............................................................47
Prescaler ............................................................48
Prescaler Block Diagram ...................................47
Section ...............................................................47
T0CKI .................................................................48
Timer1
Asynchronous Counter Mode ............................53
Capacitor Selection ............................................53
Operation in Timer Mode ...................................52
Oscillator ............................................................53
Prescaler ............................................................53
Resetting of Timer1 Registers ...........................53
Resetting Timer1 using a CCP Trigger Output ..53
Synchronized Counter Mode .............................52
T1CON ...............................................................51
TMR1H ...............................................................53
TMR1L ...............................................................53
Timer2
U
Universal Synchronous Asynchronous Receiver
Transmitter (USART)
Asynchronous Receiver
Block Diagram ....................................................55
Postscaler ..........................................................55
Prescaler ............................................................55
T2CON ...............................................................55
Timing Diagrams
Setting Up Reception ......................................... 71
Timing Diagram ................................................. 72
USART ............................................................................... 63
Asynchronous Mode .................................................. 67
Receive Block Diagram ..................................... 71
Asynchronous Receiver ............................................. 69
Asynchronous Reception ........................................... 70
Asynchronous Transmitter ......................................... 67
Baud Rate Generator (BRG) ..................................... 65
Baud Rate Formula ........................................... 65
Baud Rates, Asynchronous Mode (BRGH=0) ... 66
High Baud Rate Select (BRGH Bit) ................... 63
Sampling ............................................................ 65
Clock Source Select (CSRC Bit) ................................ 63
Continuous Receive Enable (CREN Bit) .................... 64
Framing Error (FERR Bit) .......................................... 64
Mode Select (SYNC Bit) ............................................ 63
Overrun Error (OERR Bit) .......................................... 64
RC6/TX/CK Pin ........................................................ 7, 8
RC7/RX/DT Pin ........................................................ 7, 8
RCSTA Register ........................................................ 64
Receive Block Diagram ............................................. 69
Receive Data, 9th bit (RX9D Bit) ............................... 64
A/D Conversion ........................................................134
Brown-out Reset ......................................................128
Capture/Compare/PWM ...........................................130
CLKOUT and I/O ......................................................127
Power-up Timer .......................................................128
Reset ........................................................................128
Start-up Timer ..........................................................128
Time-out Sequence on Power-up ........................97, 98
Timer0 ......................................................................129
Timer1 ......................................................................129
USART Asynchronous Master Transmission .............68
USART Asynchronous Reception ..............................69
USART Synchronous Receive .................................132
USART Synchronous Reception ................................75
USART Synchronous Transmission .................. 74, 132
USART, Asynchronous Reception .............................72
Wake-up from SLEEP via Interrupt ..........................103
Watchdog Timer .......................................................128
TMR0 .................................................................................15
DS30569A-page 148
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
Receive Enable, 9-bit (RX9 Bit) ................................. 64
Serial Port Enable (SPEN Bit) .............................. 63, 64
Single Receive Enable (SREN Bit) ............................ 64
Synchronous Master Mode ........................................ 73
Synchronous Master Reception ................................. 75
Synchronous Master Transmission ............................ 73
Synchronous Slave Mode .......................................... 76
Transmit Block Diagram ............................................. 67
Transmit Data, 9th Bit (TX9D) .................................... 63
Transmit Enable (TXEN Bit) ....................................... 63
Transmit Enable, Nine-bit (TX9 Bit) ........................... 63
Transmit Shift Register Status (TRMT Bit) ................. 63
TXSTA Register ......................................................... 63
W
Wake-up from SLEEP ................................................ 89, 102
Interrupts .............................................................. 95, 96
MCLR Reset .............................................................. 96
Timing Diagram ........................................................ 103
WDT Reset ................................................................ 96
Watchdog Timer (WDT) ............................................. 89, 101
Block Diagram .......................................................... 101
Enable (WDTE Bit) ................................................... 101
Programming Considerations .................................. 101
RC Oscillator ............................................................ 101
Time-out Period ....................................................... 101
WDT Reset, Normal Operation ...................... 93, 95, 96
WDT Reset, SLEEP ....................................... 93, 95, 96
WWW, On-Line Support ...................................................... 4
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 149
PIC16F870/871
NOTES:
DS30569A-page 150
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-786-7302 for the rest of the world.
ConnectingtotheMicrochipInternetWebSite
991103
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
Trademarks: The Microchip name, logo, PIC, PICmicro,
PICSTART, PICMASTER, PRO MATE and MPLAB are regis-
tered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries. FlexROM and fuzzyLAB are
trademarks and SQTP is a service mark of Microchip in the
U.S.A.
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
All other trademarks mentioned herein are the property of
their respective companies.
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Sys-
tems, technical information and more
• Listing of seminars and events
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 151
PIC16F870/871
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
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RE:
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FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
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Literature Number:
DS30569A
Device:
PIC16F870/871
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30569A-page 152
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
PIC16F870/871 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
-X
/XX
XXX
PART NO.
Device
Examples:
a)
PIC16F870-I/SP 301 = Industrial temp., PDIP
Temperature Package
Range
Pattern
package, 20 MHz, normal VDD limits, QTP pat-
tern #301.
b)
c)
d)
PIC16F871-I/PT = Industrial temp., TQFP
package, 20 MHz, Extended VDD limits.
Device
PIC16F870, PIC16F870T ;VDD range 4.0V to 5.5V
PIC16F871, PIC16F871T ;VDD range 4.0V to 5.5V
PIC16LF870X, PIC16LF870T;VDD range 2.0V to 5.5V
PIC16LF871X, PIC16LF871T;VDD range 2.0V to 5.5V
PIC16F871-I/P = Industrial temp., PDIP pack-
age, 20 MHz, normal VDD limits.
PIC16LF870-I/SS = Industrial temp., SSOP
package, DC - 20MHz, extended VDD limits.
F
= Normal VDD limits
LP
T
= Extended VDD limits
= In Tape and Reel - SOIC, SSOP, TQFP and
PLCC packages only.
Temperature Range
Package
blank(3)
I
=
=
0°C to
70°C (Commercial)
-40°C to +85°C (Industrial)
PQ
PT
SO
SP
SS
P
=
=
=
=
=
=
=
MQFP (Metric PQFP)
TQFP (Thin Quad Flatpack)
SOIC
Skinny plastic dip
SSOP
PDIP
PLCC
L
Pattern
QTP, Code or Special Requirements
(blank otherwise)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 153
PIC16F870/871
NOTES:
DS30569A-page 154
Preliminary
1999 Microchip Technology Inc.
PIC16F870/871
NOTES:
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 155
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
ASIA/PACIFIC (continued)
Corporate Office
Toronto
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore 188980
Microchip Technology Inc.
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-786-7200 Fax: 480-786-7277
Technical Support: 480-786-7627
Web Address: http://www.microchip.com
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
Tel: 65-334-8870 Fax: 65-334-8850
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific
Unit 2101, Tower 2
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Taiwan, R.O.C
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Atlanta
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Tel: 770-640-0034 Fax: 770-640-0307
Boston
EUROPE
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508-480-9990 Fax: 508-480-8575
Beijing
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5858 Fax: 44-118 921-5835
Denmark
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Microchip Technology, Beijing
Unit 915, 6 Chaoyangmen Bei Dajie
Dong Erhuan Road, Dongcheng District
New China Hong Kong Manhattan Building
Beijing 100027 PRC
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 86-10-85282100 Fax: 86-10-85282104
India
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
4570 Westgrove Drive, Suite 160
Addison, TX 75248
Tel: 972-818-7423 Fax: 972-818-2924
Japan
France
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 München, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip Technology Inc.
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Italy
Los Angeles
Shanghai
Microchip Technology
Unit B701, Far East International Plaza,
No. 317, Xianxia Road
Shanghai, 200051 P.R.C
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
New York
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
11/23/99
San Jose
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
All rights reserved. © 2000 Microchip Technology Incorporated. Printed in the USA. 1/00
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS30569A-page 156
1999 Microchip Technology Inc.
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