PIC18F2321T-E/PT_技术文档

PIC18F4321 Family

Data Sheet

28/40/44-Pin

Enhanced Flash Microcontrollers with

10-Bit A/D and nanoWatt Technology

Preliminary

DS39689E

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

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Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and

SmartShunt are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable

Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor

and The Embedded Control Solutions Company are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,

MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its PIC^®

MCUs and dsPIC^®DSCs, KEELOQ^®code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

DS39689E-page ii

PIC18F4321 FAMILY

28/40/44-Pin Enhanced Flash Microcontrollers with

10-Bit A/D and nanoWatt Technology

Power-Managed Modes:

Peripheral Highlights (Continued):

• Run: CPU on, peripherals on

• Idle: CPU off, peripherals on

• Master Synchronous Serial Port (MSSP) module

supporting 3-wire SPI (all 4 modes) and I C™

2

• Sleep: CPU off, peripherals off

Master and Slave modes

• Idle mode currents down to 2.5 μA typical

• Sleep mode currents down to 100 nA typical

• Timer1 Oscillator: 1.8 μA, 32 kHz, 2V typical

• Watchdog Timer: 1.4 μA, 2V typical

• Two-Speed Oscillator Start-up

• Enhanced Addressable USART module:

- Supports RS-485, RS-232 and LIN 1.2

- RS-232 operation using internal oscillator

block (no external crystal required)

- Auto-Wake-up on Start bit

- Auto-Baud Detect

Flexible Oscillator Structure:

• 10-bit, up to 13-channel Analog-to-Digital

Converter module (A/D):

- Auto-acquisition capability

- Conversion available during Sleep

• Dual analog comparators with input multiplexing

• Programmable 16-level High/Low-Voltage

Detection (HLVD) module:

• Four Crystal modes, up to 40 MHz

• 4x Phase Lock Loop (PLL) – available for crystal

and internal oscillators

• Two External RC modes, up to 4 MHz

• Two External Clock modes, up to 40 MHz

• Internal oscillator block:

- Supports interrupt on High/Low-Voltage Detection

- 8 user-selectable frequencies, from 31 kHz to

8 MHz

Special Microcontroller Features:

- Provides a complete range of clock speeds

from 31 kHz to 32 MHz when used with PLL

- User-tunable to compensate for frequency drift

• Secondary oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor

• C compiler optimized architecture:

- Optional extended instruction set designed to

optimize re-entrant code

• 100,000 erase/write cycle Enhanced Flash

program memory typical

- Allows for safe shutdown if peripheral clock stops

• 1,000,000 erase/write cycle Data EEPROM

memory typical

Peripheral Highlights:

• Flash/Data EEPROM Retention: 100 years typical

• Self-programmable under software control

• Priority levels for interrupts

• High-current sink/source 25 mA/25 mA

• Three programmable external interrupts

• Four input change interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 131s

• Single-Supply 5V In-Circuit Serial

Programming™ (ICSP™) via two pins

• In-Circuit Debug (ICD) via two pins

• Wide operating voltage range: 2.0V to 5.5V

• Programmable Brown-out Reset (BOR) with

software enable option

• Up to 2 Capture/Compare/PWM (CCP) modules,

one with Auto-Shutdown (28-pin devices)

• Enhanced Capture/Compare/PWM (ECCP)

module (40/44-pin devices only):

- One, two or four PWM outputs

- Selectable polarity

- Programmable dead time

- Auto-Shutdown and Auto-Restart

• Optional dedicated ICD/ICSP port (44-pin devices only)

-

Program Memory

Data Memory

MSSP

CCP/

ECCP

(PWM)

10-bit

A/D (ch)

Timers

8/16-bit

Device

I/O

Comp.

Flash # Single-Word SRAM EEPROM

(bytes) Instructions (bytes) (bytes)

Master

SPI

2

I C™

PIC18F2221

PIC18F2321

PIC18F4221

PIC18F4321

4K

8K

4K

8K

2048

4096

2048

4096

512

256

25

36

10

13

2/0

1/1

Y

1

2

1/3

Preliminary

DS39689E-page 1

PIC18F4321 FAMILY

Pin Diagrams

28-Pin SPDIP, SOIC, SSOP

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RB7/KBI3/PGD

RB6//KBI2/PGC

RB5/KBI1/PGM

RB4/KBI0/AN11

RB3/AN9/CCP2⁽¹⁾

RB2/INT2/AN8

RB1/INT1/AN10

RB0/INT0/FLT0/AN12

VDD

MCLR/VPP/RE3

RA0/AN0

2

3

4

5

RA1/AN1

RA2/AN2/VREF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT

RA5/AN4/SS/HLVDIN/C2OUT

VSS

6

7

8

9

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2⁽¹⁾

RC2/CCP1

VSS

RC7/RX/DT

10

11

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

12

13

14

RC3/SCK/SCL

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

28-Pin QFN

28272625242322

RB3/AN9/CCP2⁽¹⁾

RB2/INT2/AN8

RB1/INT1/AN10

RB0/INT0/FLT0/AN12

VDD

RA2/AN2/VREF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT

RA5/AN4/SS/HLVDIN/C2OUT

V^SS

1

2

3

4

5

6

7

21

20

19

18

17

16

15

PIC18F2221

PIC18F2321

OSC1/CLKI/RA7

OSC2/CLKO/RA6

VSS

RC7/RX/DT

8

9 1011 12 1314

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

DS39689E-page 2

Preliminary

PIC18F4321 FAMILY

Pin Diagrams (Continued)

40-Pin PDIP

MCLR/VPP/RE3

1

2

3

4

5

6

7

8

RB7/KBI3/PGD

RB6/KBI2/PGC

RB5/KBI1/PGM

RB4/KBI0/AN11

RB3/AN9/CCP2⁽¹⁾

RB2/INT2/AN8

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

RA0/AN0

RA1/AN1

RA2/AN2/VREF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT

RA5/AN4/SS/HLVDIN/C2OUT

RE0/RD/AN5

RB1/INT1/AN10

RB0/INT0/FLT0/AN12

VDD

VSS

RE1/WR/AN6

RE2/CS/AN7

9

10

11

12

13

14

15

16

17

18

19

20

VDD

VSS

RD7/PSP7/P1D

RD6/PSP6/P1C

RD5/PSP5/P1B

RD4/PSP4

RC7/RX/DT

RC6/TX/CK

RC5/SDO

OSC1/CLKI/RA7

OSC2/CLKO/RA6

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2⁽¹⁾

RC2/CCP1/P1A

RC3/SCK/SCL

RD0/PSP0

RC4/SDI/SDA

RD3/PSP3

RD1/PSP1

RD2/PSP2

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

44-Pin QFN

RC7/RX/DT

1

OSC2/CLKO/RA6

OSC1/CLKI/RA7

VSS

VDD

RE2/CS/AN7

RE1/WR/AN6

RE0/RD/AN5

RA5/AN4/SS/HLVDIN/C2OUT

RA4/T0CKI/C1OUT

33

RD4/PSP4

2

32

31

30

29

28

27

26

RD5/PSP5/P1B

3

RD6/PSP6/P1C

4

RD7/PSP7/P1D

5

PIC18F4221

PIC18F4321

VSS

VDD

6

7

8

RB0/INT0/FLT0/AN12

RB1/INT1/AN10

RB2/INT2/AN8

9

10

11

25

24

23

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

Preliminary

DS39689E-page 3

PIC18F4321 FAMILY

Pin Diagrams (Continued)

44-Pin TQFP

NC/ICRST⁽²⁾/ICVPP

(2)

33

32

31

30

29

28

27

26

1

2

3

4

5

6

7

8

RC7/RX/DT

RD4/PSP4

RD5/PSP5/P1B

RD6/PSP6/P1C

RD7/PSP7/P1D

VSS

RC0/T1OSO/T13CKI

OSC2/CLKO/RA6

OSC1/CLKI/RA7

VSS

PIC18F4221

PIC18F4321

VDD

RE2/CS/AN7

RE1/WR/AN6

RE0/RD/AN5

VDD

RB0/INT0/FLT0/AN12

RB1/INT1/AN10

RB2/INT2/AN8

RB3/AN9/CCP2⁽¹⁾

9

10

11

25

24

23

RA5/AN4/SS/HLVDIN/C2OUT

RA4/T0CKI/C1OUT

Note 1: RB3 is the alternate pin for CCP2 multiplexing.

2: Special ICPORT features available in select circumstances. See Section 23.9 “Special ICPORT Features

(44-Pin TQFP Packages Only)” for more information.

DS39689E-page 4

Preliminary

PIC18F4321 FAMILY

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 Oscillator Configurations ............................................................................................................................................................ 23

3.0 Power-Managed Modes ............................................................................................................................................................. 33

4.0 Reset.......................................................................................................................................................................................... 41

5.0 Memory Organization................................................................................................................................................................. 53

6.0 Flash Program Memory.............................................................................................................................................................. 73

7.0 Data EEPROM Memory ............................................................................................................................................................. 83

8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 89

9.0 Interrupts .................................................................................................................................................................................... 91

10.0 I/O Ports ................................................................................................................................................................................... 105

11.0 Timer0 Module ......................................................................................................................................................................... 123

12.0 Timer1 Module ......................................................................................................................................................................... 127

13.0 Timer2 Module ......................................................................................................................................................................... 133

14.0 Timer3 Module ......................................................................................................................................................................... 135

15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 139

16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 147

17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 161

18.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 205

19.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 227

20.0 Comparator Module.................................................................................................................................................................. 237

21.0 Comparator Voltage Reference Module................................................................................................................................... 243

22.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 247

23.0 Special Features of the CPU.................................................................................................................................................... 253

24.0 Instruction Set Summary.......................................................................................................................................................... 273

25.0 Development Support............................................................................................................................................................... 323

26.0 Electrical Characteristics.......................................................................................................................................................... 327

27.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 365

28.0 Packaging Information.............................................................................................................................................................. 367

Appendix A: Revision History............................................................................................................................................................. 377

Appendix B: Device Differences ........................................................................................................................................................ 377

Appendix C: Conversion Considerations ........................................................................................................................................... 378

Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 378

Appendix E: Migration From Mid-Range to Enhanced Devices......................................................................................................... 379

Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 379

Index ................................................................................................................................................................................................. 381

The Microchip Web Site..................................................................................................................................................................... 391

Customer Change Notification Service .............................................................................................................................................. 391

Customer Support.............................................................................................................................................................................. 391

Reader Response.............................................................................................................................................................................. 392

PIC18F2221/2321/4221/4321 Product Identification System ............................................................................................................ 393

Preliminary

DS39689E-page 5

PIC18F4321 FAMILY

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DS39689E-page 6

Preliminary

PIC18F4321 FAMILY

1.1.2

MULTIPLE OSCILLATOR OPTIONS

AND FEATURES

1.0

DEVICE OVERVIEW

This document contains device specific information for

the following devices:

All of the devices in the PIC18F4321 family offer ten

different oscillator options, allowing users a wide range

of choices in developing application hardware. These

include:

• PIC18F2221

• PIC18F2321

• PIC18F4221

• PIC18F4321

• PIC18LF2221

• PIC18LF2321

• PIC18LF4221

• PIC18LF4321

• Four Crystal modes, using crystals or ceramic

resonators.

• Two External Clock modes, offering the option of

using two pins (oscillator input and a divide-by-4

clock output) or one pin (oscillator input, with the

second pin reassigned as general I/O).

This family offers the advantages of all PIC18 micro-

controllers – namely, high computational performance at

an economical price – with the addition of high

endurance, Enhanced Flash program memory. On top of

these features, the PIC18F4321 family introduces design

enhancements that make these microcontrollers a logical

choice for many high-performance, power sensitive

applications.

• Two External RC Oscillator modes with the same

pin options as the External Clock modes.

• Two Internal Oscillator modes which provide

an 8 MHz clock and an INTRC source

(approximately 31 kHz), as well as a range of

6 user-selectable clock frequencies, between

125 kHz to 4 MHz, for a total of 8 clock frequencies.

One or both of the oscillator pins can be used for

general purpose I/O.

1.1

New Core Features

1.1.1

nanoWatt TECHNOLOGY

All of the devices in the PIC18F4321 family incorporate

a range of features that can significantly reduce power

consumption during operation. Key items include:

• A Phase Lock Loop (PLL) frequency multiplier,

available to both the high-speed crystal and

internal oscillator modes, which allows clock

speeds of up to 40 MHz. Used with the internal

oscillator, the PLL gives users a complete selection

of clock speeds, from 31 kHz to 32 MHz – all

without using an external crystal or clock circuit.

• Alternate Run Modes: By clocking the controller

from the Timer1 source or the internal oscillator

block, power consumption during code execution

can be reduced by as much as 90%.

• Multiple Idle Modes: The controller can also run

with its CPU core disabled but the peripherals still

active. In these states, power consumption can be

reduced even further, to as little as 4% of normal

operation requirements.

Besides its availability as a clock source, the internal

oscillator block provides a stable reference source that

gives the family additional features for robust

operation:

• Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a reference

signal provided by the internal oscillator. If a clock

failure occurs, the controller is switched to the

internal oscillator block, allowing for continued

low-speed operation or a safe application

shutdown.

• On-the-Fly Mode Switching: The

power-managed modes are invoked by user code

during operation, allowing the user to incorporate

power-saving ideas into their application’s

software design.

• Low Consumption in Key Modules: The

power requirements for both Timer1 and the

Watchdog Timer are minimized. See

Section 26.0 “Electrical Characteristics” for

values.

• Two-Speed Start-up: This option allows the

internal oscillator to serve as the clock source

from Power-on Reset, or wake-up from Sleep

mode, until the primary clock source is available.

Preliminary

DS39689E-page 7

PIC18F4321 FAMILY

1.2

Other Special Features

1.3

Details on Individual Family

Members

• Memory Endurance: The Enhanced Flash cells

for both program memory and data EEPROM are

rated to last for many thousands of erase/write

cycles – up to 100,000 for program memory and

1,000,000 for EEPROM. Data retention without

refresh is conservatively estimated to be greater

than 40 years.

Devices in the PIC18F4321 family are available in 28-pin

and 40/44-pin packages. Block diagrams for the two

groups are shown in Figure 1-1 and Figure 1-2.

The devices are differentiated from each other in five

ways:

1. Flash program memory (4 Kbytes for

PIC18F2221/4221 devices, 8 Kbytes for

PIC18F2321/4321).

• Self-Programmability: These devices can write to

their own program memory spaces under internal

software control. By using a bootloader routine,

located in the protected Boot Block at the top of

program memory, it becomes possible to create an

application that can update itself in the field.

2. A/D channels (10 for 28-pin devices, 13 for

40/44-pin devices).

3. I/O ports (3 bidirectional ports on 28-pin devices,

5 bidirectional ports on 40/44-pin devices).

• Extended Instruction Set: The PIC18F4321

family introduces an optional extension to the

PIC18 instruction set, which adds 8 new

4. CCP and Enhanced CCP implementation

(28-pin devices have

2

standard CCP

instructions and an Indexed Addressing mode.

This extension, enabled as a device configuration

option, has been specifically designed to optimize

re-entrant application code originally developed in

high-level languages, such as C.

modules, 40/44-pin devices have one standard

CCP module and one ECCP module).

5. Parallel Slave Port (present only on 40/44-pin

devices).

All other features for devices in this family are identical.

These are summarized in Table 1-1.

• Enhanced CCP Module: In PWM mode, this

module provides 1, 2 or 4 modulated outputs for

controlling half-bridge and full-bridge drivers.

Other features include auto-shutdown, for

disabling PWM outputs on interrupt or other select

conditions and auto-restart, to reactivate outputs

once the condition has cleared.

The pinouts for all devices are listed in Table 1-2 and

Table 1-3.

Like all Microchip PIC18 devices, members of the

PIC18F4321 family are available as both standard and

low-voltage devices. Standard devices with Enhanced

Flash memory, designated with an “F” in the part

number (such as PIC18F2321), accommodate an

operating VDD range of 4.2V to 5.5V. Low-voltage

parts, designated by “LF” (such as PIC18LF2321),

function over an extended VDD range of 2.0V to 5.5V.

• Enhanced Addressable USART: This serial

communication module is capable of standard

RS-232 operation and provides support for the LIN

bus protocol. Other enhancements include

automatic baud rate detection and a 16-bit Baud

Rate Generator for improved resolution. When the

microcontroller is using the internal oscillator

block, the EUSART provides stable operation for

applications that talk to the outside world without

using an external crystal (or its accompanying

power requirement).

• 10-Bit A/D Converter: This module incorporates

programmable acquisition time, allowing for a

channel to be selected and a conversion to be

initiated without waiting for a sampling period and

thus, reducing code overhead.

• Extended Watchdog Timer (WDT): This

Enhanced version incorporates a 16-bit prescaler,

allowing an extended time-out range that is stable

across operating voltage and temperature. See

Section 26.0 “Electrical Characteristics” for

time-out periods.

• Dedicated ICD/ICSP Port: These devices

introduce the use of debugger and programming

pins that are not multiplexed with other micro-

controller features. Offered as an option in select

packages, this feature allows users to develop I/O

intensive applications while retaining the ability to

program and debug in the circuit.

DS39689E-page 8

Preliminary

PIC18F4321 FAMILY

TABLE 1-1:

DEVICE FEATURES

Features

PIC18F2221

PIC18F2321

PIC18F4221

PIC18F4321

Operating Frequency

Program Memory (Bytes)

Program Memory (Instructions)

Data Memory (Bytes)

Data EEPROM Memory (Bytes)

Interrupt Sources

DC – 40 MHz

4096

2048

512

256

19

8192

4096

512

256

19

4096

2048

512

256

20

8192

4096

512

256

20

I/O Ports

Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E

Timers

4

2

0

4

2

0

4

1

4

1

Capture/Compare/PWM Modules

Enhanced Capture/Compare/

PWM Modules

Serial Communications

MSSP,

Enhanced USART Enhanced USART Enhanced USART Enhanced USART

No No Yes Yes

10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels

POR, BOR, POR, BOR, POR, BOR, POR, BOR,

RESETInstruction, RESETInstruction, RESETInstruction, RESETInstruction,

Parallel Communications (PSP)

10-bit Analog-to-Digital Module

Resets (and Delays)

Stack Full,

Stack Underflow

(PWRT, OST),

MCLR (optional),

WDT

Stack Full,

Stack Underflow

(PWRT, OST),

MCLR (optional),

WDT

Stack Full,

Stack Underflow

(PWRT, OST),

MCLR (optional),

WDT

Stack Full,

Stack Underflow

(PWRT, OST),

MCLR (optional),

WDT

Programmable Low-Voltage

Detect

Yes

Programmable Brown-out Reset

Instruction Set

Yes

75 Instructions;

83 with Extended 83 with Extended 83 with Extended

Instruction Set

enabled

75 Instructions;

83 with Extended

Instruction Set

enabled

Instruction Set

enabled

Instruction Set

enabled

Packages

28-pin SPDIP

28-pin SOIC

28-pin SSOP

28-pin QFN

28-pin SPDIP

28-pin SOIC

28-pin SSOP

28-pin QFN

40-pin PDIP

44-pin QFN

44-pin TQFP

40-pin PDIP

44-pin QFN

44-pin TQFP

Preliminary

DS39689E-page 9

PIC18F4321 FAMILY

FIGURE 1-1:

PIC18F2221/2321 (28-PIN) BLOCK DIAGRAM

Data Bus<8>

Table Pointer<21>

PORTA

Data Latch

8

inc/dec logic

21

RA0/AN0

RA1/AN1

Data Memory

(3.9 Kbytes)

RA2/AN2/VREF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT

RA5/AN4/SS/HLVDIN/C2OUT

OSC2/CLKO⁽³⁾/RA6

OSC1/CLKI⁽³⁾/RA7

PCLATU PCLATH

Address Latch

20

PCU PCH PCL

Program Counter

12

Data Address<12>

31 Level Stack

STKPTR

4

BSR

12

FSR0

FSR1

FSR2

4

Address Latch

Access

Bank

Program Memory

(4 Kbytes)

12

Data Latch

PORTB

RB0/INT0/FLT0/AN12

RB1/INT1/AN10

RB2/INT2/AN8

inc/dec

logic

8

Table Latch

RB3/AN9/CCP2⁽¹⁾

RB4/KBI0/AN11

RB5/KBI1/PGM

RB6/KBI2/PGC

RB7/KBI3/PGD

Address

Decode

ROM Latch

IR

Instruction Bus <16>

8

State Machine

Control Signals

Instruction

Decode &

Control

PRODH PRODL

8 x 8 Multiply

PORTC

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2⁽¹⁾

RC2/CCP1

3

8

W

BITOP

8

RC3/SCK/SCL

RC4/SDI/SDA

8

RC5/SDO

RC6/TX/CK

RC7/RX/DT

OSC1⁽³⁾

OSC2⁽³⁾

T1OSI

Internal

Oscillator

Block

Power-up

Timer

8

Oscillator

Start-up Timer

ALU<8>

8

INTRC

Oscillator

Power-on

Reset

8 MHz

Oscillator

Watchdog

Timer

T1OSO

Precision

Band Gap

Reference

Brown-out

Reset

Fail-Safe

MCLR⁽²⁾

VDD, VSS

Single-Supply

Programming

PORTE

In-Circuit

Debugger

Clock Monitor

MCLR/VPP/RE3⁽²⁾

Data

EEPROM

BOR

LVD

Timer0

Timer1

MSSP

Timer2

Timer3

ADC

10-bit

Comparator

CCP1

CCP2

EUSART

Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set.

2: RE3 is only available when MCLR functionality is disabled.

3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.

Refer to Section 2.0 “Oscillator Configurations” for additional information.

DS39689E-page 10

Preliminary

PIC18F4321 FAMILY

FIGURE 1-2:

PIC18F4221/4321 (40/44-PIN) BLOCK DIAGRAM

Data Bus<8>

PORTA

Table Pointer<21>

RA0/AN0

RA1/AN1

Data Latch

8

inc/dec logic

21

RA2/AN2/VREF-/CVREF

RA3/AN3/VREF+

RA4/T0CKI/C1OUT

RA5/AN4/SS/HLVDIN/C2OUT

OSC2/CLKO⁽³⁾/RA6

OSC1/CLKI⁽³⁾/RA7

Data Memory

(3.9 Kbytes)

PCLATU PCLATH

Address Latch

20

PCU PCH PCL

Program Counter

12

Data Address<12>

PORTB

31 Level Stack

STKPTR

RB0/INT0/FLT0/AN12

RB1/INT1/AN10

RB2/INT2/AN8

4

BSR

12

FSR0

FSR1

FSR2

4

Address Latch

Access

Bank

Program Memory

(8 Kbytes)

RB3/AN9/CCP2⁽¹⁾

RB4/KBI0/AN11

RB5/KBI1/PGM

RB6/KBI2/PGC

RB7/KBI3/PGD

12

Data Latch

inc/dec

logic

8

Table Latch

Address

Decode

PORTC

ROM Latch

IR

RC0/T1OSO/T13CKI

RC1/T1OSI/CCP2⁽¹⁾

RC2/CCP1/P1A

Instruction Bus <16>

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6/TX/CK

RC7/RX/DT

8

State Machine

Control Signals

Instruction

Decode &

Control

PRODH PRODL

8 x 8 Multiply

PORTD

3

8

RD0/PSP0:RD4/PSP4

RD5/PSP5/P1B

RD6/PSP6/P1C

W

BITOP

8

RD7/PSP7/P1D

OSC1⁽³⁾

OSC2⁽³⁾

T1OSI

Internal

Oscillator

Block

Power-up

Timer

8

Oscillator

Start-up Timer

ALU<8>

8

INTRC

Oscillator

Power-on

Reset

8 MHz

Oscillator

Watchdog

Timer

T1OSO

PORTE

RE0/RD/AN5

RE1/WR/AN6

RE2/CS/AN7

Precision

Band Gap

Reference

Brown-out

Reset

Fail-Safe

MCLR⁽²⁾

VDD, VSS

Single-Supply

Programming

In-Circuit

Debugger

MCLR/VPP/RE3⁽²⁾

Clock Monitor

Data

EEPROM

BOR

LVD

Timer0

Timer1

MSSP

Timer2

Timer3

ADC

10-bit

Comparator

ECCP1

CCP2

EUSART

Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set.

2: RE3 is only available when MCLR functionality is disabled.

3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.

Refer to Section 2.0 “Oscillator Configurations” for additional information.

Preliminary

DS39689E-page 11

PIC18F4321 FAMILY

TABLE 1-2:

PIC18F2221/2321 PINOUT I/O DESCRIPTIONS

Pin Number

Pin Buffer

Type Type

SPDIP,

SOIC, QFN

SSOP

Pin Name

Description

MCLR/VPP/RE3

MCLR

1

9

26

6

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low

Reset to the device.

I

ST

VPP

RE3

P

I

Programming voltage input.

Digital input.

OSC1/CLKI/RA7

OSC1

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.

ST buffer when configured in RC mode; CMOS otherwise.

External clock source input. Always associated with

pin function OSC1. (See related OSC1/CLKI,

OSC2/CLKO pins.)

I

Analog

CLKI

RA7

I/O

TTL

General purpose I/O pin.

OSC2/CLKO/RA6

OSC2

10

7

Oscillator crystal or clock output.

O

—

Oscillator crystal output. Connects to crystal or resonator

in Crystal Oscillator mode.

In RC, EC and INTIO modes, OSC2 pin outputs CLKO

which has one-fourth the frequency of OSC1 and denotes

the instruction cycle rate.

CLKO

RA6

I/O

TTL

General purpose I/O pin.

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

I

O

= Input

= Output

P = Power

I²C = ST with I²C™ or SMB levels

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

DS39689E-page 12

Preliminary

PIC18F4321 FAMILY

TABLE 1-2:

PIC18F2221/2321 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Buffer

Type Type

SPDIP,

SOIC, QFN

SSOP

Pin Name

Description

PORTA is a bidirectional I/O port.

RA0/AN0

RA0

2

3

4

27

28

1

I/O

I

TTL

Analog

Digital I/O.

Analog input 0.

AN0

RA1/AN1

RA1

I/O

I

TTL

Analog

Digital I/O.

Analog input 1.

AN1

RA2/AN2/VREF-/CVREF

RA2

I/O

TTL

Digital I/O.

AN2

VREF-

CVREF

I

O

Analog

Analog input 2.

A/D reference voltage (low) input.

Comparator reference voltage output.

RA3/AN3/VREF+

RA3

5

6

7

2

3

4

I/O

I

TTL

Analog

Digital I/O.

Analog input 3.

A/D reference voltage (high) input.

AN3

VREF+

RA4/T0CKI/C1OUT

RA4

I/O

I

O

ST

—

Digital I/O. Open-collector output.

Timer0 external clock input.

Comparator 1 output.

T0CKI

C1OUT

RA5/AN4/SS/HLVDIN/

C2OUT

RA5

I/O

I

O

TTL

Analog

TTL

Analog

—

Digital I/O.

Analog input 4.

SPI slave select input.

High/Low-Voltage Detect input.

Comparator 2 output.

AN4

SS

HLVDIN

C2OUT

RA6

RA7

See the OSC2/CLKO/RA6 pin.

See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

I

O

= Input

= Output

P = Power

I²C = ST with I²C™ or SMB levels

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

Preliminary

DS39689E-page 13

PIC18F4321 FAMILY

TABLE 1-2:

PIC18F2221/2321 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Buffer

Type Type

SPDIP,

SOIC, QFN

SSOP

Pin Name

Description

PORTB is a bidirectional I/O port. PORTB can be software

programmed for internal weak pull-ups on all inputs.

RB0/INT0/FLT0/AN12

21

18

RB0

I/O

TTL

ST

Digital I/O.

INT0

FLT0

AN12

I

External interrupt 0.

PWM Fault input for CCP1.

Analog input 12.

Analog

RB1/INT1/AN10

RB1

22

23

24

25

26

27

28

19

20

21

22

23

24

25

I/O

I

TTL

ST

Analog

Digital I/O.

External interrupt 1.

Analog input 10.

INT1

AN10

RB2/INT2/AN8

RB2

I/O

I

TTL

ST

Analog

Digital I/O.

External interrupt 2.

Analog input 8.

INT2

AN8

RB3/AN9/CCP2

RB3

I/O

I

I/O

TTL

Analog

ST

Digital I/O.

Analog input 9.

Capture 2 input/Compare 2 output/PWM 2 output.

AN9

CCP2⁽²⁾

RB4/KBI0/AN11

RB4

I/O

I

TTL

Analog

Digital I/O.

Interrupt-on-change pin.

Analog input 11.

KBI0

AN11

RB5/KBI1/PGM

RB5

I/O

I

I/O

TTL

ST

Digital I/O.

Interrupt-on-change pin.

Low-Voltage ICSP™ Programming enable pin.

KBI1

PGM

RB6/KBI2/PGC

RB6

I/O

I

I/O

TTL

ST

Digital I/O.

Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming clock pin.

KBI2

PGC

RB7/KBI3/PGD

RB7

I/O

I

I/O

TTL

ST

Digital I/O.

Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming data pin.

KBI3

PGD

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

I

O

= Input

= Output

P = Power

I²C = ST with I²C™ or SMB levels

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

DS39689E-page 14

Preliminary

PIC18F4321 FAMILY

TABLE 1-2:

PIC18F2221/2321 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Buffer

Type Type

SPDIP,

SOIC, QFN

SSOP

Pin Name

Description

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0

11

12

8

9

I/O

O

I

ST

—

ST

Digital I/O.

Timer1 oscillator analog output.

Timer1/Timer3 external clock input.

T1OSO

T13CKI

RC1/T1OSI/CCP2

RC1

I/O

I

I/O

ST

Analog

ST

Digital I/O.

T1OSI

Timer1 oscillator analog input.

Capture 2 input/Compare 2 output/PWM 2 output.

CCP2⁽¹⁾

RC2/CCP1

RC2

13

14

10

11

I/O

ST

Digital I/O.

CCP1

Capture 1 input/Compare 1 output/PWM 1 output.

RC3/SCK/SCL

RC3

I/O

ST

I²C

Digital I/O.

SCK

SCL

Synchronous serial clock input/output for SPI mode.

Synchronous serial clock input/output for I²C™ mode.

RC4/SDI/SDA

RC4

15

12

I/O

I

I/O

ST

I²C

Digital I/O.

SDI

SDA

SPI data in.

I²C data I/O.

RC5/SDO

RC5

16

17

13

14

I/O

O

ST

—

Digital I/O.

SPI data out.

SDO

RC6/TX/CK

RC6

I/O

O

I/O

ST

—

ST

Digital I/O.

TX

CK

EUSART asynchronous transmit.

EUSART synchronous clock (see related RX/DT).

RC7/RX/DT

RC7

18

—

15

—

I/O

I

I/O

ST

Digital I/O.

RX

DT

EUSART asynchronous receive.

EUSART synchronous data (see related TX/CK).

RE3

VSS

VDD

—

P

—

See MCLR/VPP/RE3 pin.

8, 19 5, 16

20 17

Ground reference for logic and I/O pins.

Positive supply for logic and I/O pins.

CMOS = CMOS compatible input or output

P

Legend: TTL = TTL compatible input

ST = Schmitt Trigger input with CMOS levels

I

O

= Input

= Output

P = Power

I²C = ST with I²C™ or SMB levels

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

Preliminary

DS39689E-page 15

PIC18F4321 FAMILY

TABLE 1-3:

Pin Name

PIC18F4221/4321 PINOUT I/O DESCRIPTIONS

Pin Number

Pin Buffer

Type Type

Description

PDIP QFN TQFP

MCLR/VPP/RE3

MCLR

1

18

32

18

30

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low

Reset to the device.

I

ST

VPP

RE3

P

I

Programming voltage input.

Digital input.

ST

OSC1/CLKI/RA7

OSC1

13

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source input.

ST buffer when configured in RC mode;

analog otherwise.

I

Analog

CLKI

Analog

TTL

External clock source input. Always associated with

pin function OSC1. (See related OSC1/CLKI,

OSC2/CLKO pins.)

RA7

I/O

General purpose I/O pin.

OSC2/CLKO/RA6

OSC2

14

33

31

Oscillator crystal or clock output.

O

—

Oscillator crystal output. Connects to crystal

or resonator in Crystal Oscillator mode.

In RC, EC and INTIO modes, OSC2 pin outputs

CLKO which has one-fourth the frequency of OSC1

and denotes the instruction cycle rate.

General purpose I/O pin.

CLKO

RA6

I/O

TTL

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

I

O

= Input

= Output

P = Power

I²C = ST with I²C™ or SMB levels

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

3: Special ICPORT features available in select circumstances. See Section 23.9 “Special ICPORT Features

(44-Pin TQFP Packages Only)” for more information.

DS39689E-page 16

Preliminary

PIC18F4321 FAMILY

TABLE 1-3:

Pin Name

PIC18F4221/4321 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Buffer

Type Type

Description

PDIP QFN TQFP

PORTA is a bidirectional I/O port.

RA0/AN0

RA0

2

3

4

19

20

21

19

20

21

I/O

I

TTL

Analog

Digital I/O.

Analog input 0.

AN0

RA1/AN1

RA1

I/O

I

TTL

Analog

Digital I/O.

Analog input 1.

AN1

RA2/AN2/VREF-/CVREF

RA2

I/O

TTL

Digital I/O.

AN2

VREF-

CVREF

I

O

Analog

Analog input 2.

A/D reference voltage (low) input.

Comparator reference voltage output.

RA3/AN3/VREF+

RA3

5

6

7

22

23

24

22

23

24

I/O

I

TTL

Analog

Digital I/O.

Analog input 3.

A/D reference voltage (high) input.

AN3

VREF+

RA4/T0CKI/C1OUT

RA4

I/O

I

O

ST

—

Digital I/O.

Timer0 external clock input.

Comparator 1 output.

T0CKI

C1OUT

RA5/AN4/SS/HLVDIN/

C2OUT

RA5

I/O

I

O

TTL

Analog

TTL

Analog

—

Digital I/O.

Analog input 4.

SPI slave select input.

High/Low-Voltage Detect input.

Comparator 2 output.

AN4

SS

HLVDIN

C2OUT

RA6

RA7

See the OSC2/CLKO/RA6 pin.

See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

I

O

= Input

= Output

P = Power

I²C = ST with I²C™ or SMB levels

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

3: Special ICPORT features available in select circumstances. See Section 23.9 “Special ICPORT Features

(44-Pin TQFP Packages Only)” for more information.

Preliminary

DS39689E-page 17

PIC18F4321 FAMILY

TABLE 1-3:

Pin Name

PIC18F4221/4321 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Buffer

Type Type

Description

PDIP QFN TQFP

PORTB is a bidirectional I/O port. PORTB can be

software programmed for internal weak pull-ups on all

inputs.

RB0/INT0/FLT0/AN12

33

9

8

RB0

I/O

TTL

ST

Digital I/O.

INT0

FLT0

AN12

I

External interrupt 0.

PWM Fault input for Enhanced CCP1.

Analog input 12.

Analog

RB1/INT1/AN10

RB1

34

35

36

37

38

39

10

11

12

14

15

16

9

I/O

I

TTL

ST

Analog

Digital I/O.

External interrupt 1.

Analog input 10.

INT1

AN10

RB2/INT2/AN8

RB2

10

11

14

15

16

I/O

I

TTL

ST

Analog

Digital I/O.

External interrupt 2.

Analog input 8.

INT2

AN8

RB3/AN9/CCP2

RB3

I/O

I

I/O

TTL

Analog

ST

Digital I/O.

Analog input 9.

Capture 2 input/Compare 2 output/PWM 2 output.

AN9

CCP2⁽²⁾

RB4/KBI0/AN11

RB4

I/O

I

TTL

Analog

Digital I/O.

Interrupt-on-change pin.

Analog input 11.

KBI0

AN11

RB5/KBI1/PGM

RB5

I/O

I

I/O

TTL

ST

Digital I/O.

Interrupt-on-change pin.

Low-Voltage ICSP™ Programming enable pin.

KBI1

PGM

RB6/KBI2/PGC

RB6

I/O

I

I/O

TTL

ST

Digital I/O.

KBI2

PGC

Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming

clock pin.

RB7/KBI3/PGD

RB7

40

17

I/O

I

I/O

TTL

ST

Digital I/O.

KBI3

PGD

Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming

data pin.

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

I

O

= Input

= Output

P = Power

I²C = ST with I²C™ or SMB levels

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

3: Special ICPORT features available in select circumstances. See Section 23.9 “Special ICPORT Features

(44-Pin TQFP Packages Only)” for more information.

DS39689E-page 18

Preliminary

PIC18F4321 FAMILY

TABLE 1-3:

Pin Name

PIC18F4221/4321 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Buffer

Type Type

Description

PDIP QFN TQFP

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0

15

16

17

18

34

35

36

37

32

35

36

37

I/O

O

I

ST

—

ST

Digital I/O.

Timer1 oscillator analog output.

Timer1/Timer3 external clock input.

T1OSO

T13CKI

RC1/T1OSI/CCP2

RC1

I/O

I

I/O

ST

CMOS

ST

Digital I/O.

T1OSI

Timer1 oscillator analog input.

Capture 2 input/Compare 2 output/PWM 2 output.

CCP2⁽¹⁾

RC2/CCP1/P1A

RC2

I/O

O

ST

—

Digital I/O.

CCP1

P1A

Capture 1 input/Compare 1 output/PWM 1 output.

Enhanced CCP1 output.

RC3/SCK/SCL

RC3

I/O

ST

Digital I/O.

Synchronous serial clock input/output for

SCK

SPI mode.

SCL

I/O

I²C

Synchronous serial clock input/output for I²C™

mode.

RC4/SDI/SDA

RC4

23

42

I/O

I

I/O

ST

I²C

Digital I/O.

SPI data in.

I²C data I/O.

SDI

SDA

RC5/SDO

RC5

24

25

43

44

43

44

I/O

O

ST

—

Digital I/O.

SPI data out.

SDO

RC6/TX/CK

RC6

I/O

O

I/O

ST

—

ST

Digital I/O.

TX

CK

EUSART asynchronous transmit.

EUSART synchronous clock (see related RX/DT).

RC7/RX/DT

RC7

26

1

I/O

I

I/O

ST

Digital I/O.

RX

DT

EUSART asynchronous receive.

EUSART synchronous data (see related TX/CK).

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

I

O

= Input

= Output

P = Power

I²C = ST with I²C™ or SMB levels

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

3: Special ICPORT features available in select circumstances. See Section 23.9 “Special ICPORT Features

(44-Pin TQFP Packages Only)” for more information.

Preliminary

DS39689E-page 19

PIC18F4321 FAMILY

TABLE 1-3:

Pin Name

PIC18F4221/4321 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Buffer

Type Type

Description

PDIP QFN TQFP

PORTD is a bidirectional I/O port or a Parallel Slave

Port (PSP) for interfacing to a microprocessor port.

These pins have TTL input buffers when the PSP

module is enabled.

RD0/PSP0

RD0

19

20

21

22

27

28

38

39

40

41

2

38

39

40

41

2

I/O

ST

TTL

Digital I/O.

Parallel Slave Port data.

PSP0

RD1/PSP1

RD1

I/O

ST

TTL

Digital I/O.

Parallel Slave Port data.

PSP1

RD2/PSP2

RD2

I/O

ST

TTL

Digital I/O.

Parallel Slave Port data.

PSP2

RD3/PSP3

RD3

I/O

ST

TTL

Digital I/O.

Parallel Slave Port data.

PSP3

RD4/PSP4

RD4

I/O

ST

TTL

Digital I/O.

Parallel Slave Port data.

PSP4

RD5/PSP5/P1B

RD5

3

I/O

O

ST

TTL

—

Digital I/O.

Parallel Slave Port data.

Enhanced CCP1 output.

PSP5

P1B

RD6/PSP6/P1C

RD6

29

30

4

5

4

5

I/O

O

ST

TTL

—

Digital I/O.

Parallel Slave Port data.

Enhanced CCP1 output.

PSP6

P1C

RD7/PSP7/P1D

RD7

I/O

O

ST

TTL

—

Digital I/O.

Parallel Slave Port data.

Enhanced CCP1 output.

PSP7

P1D

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

I

O

= Input

= Output

P = Power

I²C = ST with I²C™ or SMB levels

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

3: Special ICPORT features available in select circumstances. See Section 23.9 “Special ICPORT Features

(44-Pin TQFP Packages Only)” for more information.

DS39689E-page 20

Preliminary

PIC18F4321 FAMILY

TABLE 1-3:

Pin Name

PIC18F4221/4321 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Number

Pin Buffer

Type Type

Description

PDIP QFN TQFP

PORTE is a bidirectional I/O port.

RE0/RD/AN5

RE0

8

25

26

27

—

25

26

27

—

I/O

I

ST

TTL

Digital I/O.

RD

Read control for Parallel Slave Port

(see also WR and CS pins).

Analog input 5.

AN5

I

Analog

RE1/WR/AN6

RE1

9

I/O

I

ST

TTL

Digital I/O.

WR

Write control for Parallel Slave Port

(see CS and RD pins).

Analog input 6.

AN6

I

Analog

RE2/CS/AN7

RE2

10

—

I/O

I

ST

TTL

Digital I/O.

CS

Chip Select control for Parallel Slave Port

(see related RD and WR).

Analog input 7.

AN7

RE3

I

Analog

—

P

See MCLR/VPP/RE3 pin.

VSS

12, 31 6, 30, 6, 29

31

—

Ground reference for logic and I/O pins.

VDD

11, 32 7, 8, 7, 28

28, 29

P

—

Positive supply for logic and I/O pins.

NC/ICCK/ICPGC

ICCK⁽³⁾

—

12

13

33

34

No Connect or dedicated ICD/ICSP™ port clock.⁽³⁾

In-Circuit Debugger clock.

ICSP™ programming clock.

No Connect or dedicated ICD/ICSP port clock.⁽³⁾

In-Circuit Debugger data.

ICSP programming data.

No Connect or dedicated ICD/ICSP port Reset.⁽³⁾

Master Clear (Reset) input.

I

ST

ICPGC⁽³⁾

NC/ICDT/ICPGD

ICDT⁽³⁾

I/O

ST

ICPGD⁽³⁾

NC/ICRST/ICVPP

ICRST⁽³⁾

I

P

ST

Analog

(3)

ICVPP

Programming voltage input.

NC/ICPORTS

ICPORTS⁽³⁾

P

ST No Connect or 28-pin device emulation.⁽³⁾

Enable 28-pin device emulation when connected

to VSS.

NC

13 12,13,

33, 34

—

No Connect.

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

I

O

= Input

= Output

P = Power

I²C = ST with I²C™ or SMB levels

Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.

2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.

3: Special ICPORT features available in select circumstances. See Section 23.9 “Special ICPORT Features

(44-Pin TQFP Packages Only)” for more information.

Preliminary

DS39689E-page 21

PIC18F4321 FAMILY

NOTES:

DS39689E-page 22

Preliminary

PIC18F4321 FAMILY

FIGURE 2-1:

CRYSTAL/CERAMIC

RESONATOROPERATION

(XT, LP, HS OR HSPLL

CONFIGURATION)

2.0

2.1

OSCILLATOR

CONFIGURATIONS

Oscillator Types

(1)

C1

The PIC18F4321 family of devices can be operated in

ten different oscillator modes. The user can program the

Configuration bits, FOSC3:FOSC0, in Configuration

Register 1H to select one of these ten modes:

OSC1

To

Internal

Logic

(3)

RF

XTAL

1. LP

2. XT

3. HS

Low-Power Crystal

Sleep

(2)

RS

Crystal/Resonator

(1)

PIC18FXXXX

C2

OSC2

High-Speed Crystal/Resonator

4. HSPLL High-Speed Crystal/Resonator

with PLL enabled

Note 1: See Table 2-1 and Table 2-2 for initial values of

C1 and C2.

5. RC

External Resistor/Capacitor with

FOSC/4 output on RA6

2: A series resistor (RS) may be required for AT

strip cut crystals.

6. RCIO

External Resistor/Capacitor with I/O

on RA6

3: RF varies with the oscillator mode chosen.

7. INTIO1 Internal Oscillator with FOSC/4 output

on RA6 and I/O on RA7

TABLE 2-1:

CAPACITOR SELECTION FOR

CERAMIC RESONATORS

8. INTIO2 Internal Oscillator with I/O on RA6

and RA7

Typical Capacitor Values Used:

9. EC

External Clock with FOSC/4 output

External Clock with I/O on RA6

10. ECIO

Mode

Freq

OSC1

OSC2

XT

3.58 MHz

22 pF

2.2

Crystal Oscillator/Ceramic

Resonators

Capacitor values are for design guidance only.

Different capacitor values may be required to produce

acceptable oscillator operation. The user should test

the performance of the oscillator over the expected

VDD and temperature range for the application. Refer

to the following application notes for oscillator specific

information:

In XT, LP, HS or HSPLL Oscillator modes, a crystal or

ceramic resonator is connected to the OSC1 and

OSC2 pins to establish oscillation. Figure 2-1 shows

the pin connections.

The oscillator design requires the use of a parallel cut

crystal.

• AN588, “PIC^®Microcontroller Oscillator Design

Guide”

Note:

Use of a series cut crystal may give a

frequency out of the crystal manufacturer’s

specifications.

• AN826, “Crystal Oscillator Basics and Crystal

Selection for rfPIC^®and PIC^®Devices”

• AN849, “Basic PIC^®Oscillator Design”

• AN943, “Practical PIC^®Oscillator Analysis and

Design”

• AN949, “Making Your Oscillator Work”

See the notes following Table 2-2 for additional

information.

Note:

When using resonators with frequencies

above 3.5 MHz, the use of HS mode,

rather than XT mode, is recommended.

HS mode may be used at any VDD for

which the controller is rated. If HS is

selected, it is possible that the gain of the

oscillator will overdrive the resonator.

Therefore, a series resistor may be placed

between the OSC2 pin and the resonator.

As

a

good starting point, the

recommended value of RS is 330Ω.

Preliminary

DS39689E-page 23

PIC18F4321 FAMILY

An external clock source may also be connected to the

OSC1 pin in the HS mode, as shown in Figure 2-2.

When operated in this mode, parameters D033 and

D043 apply.

TABLE 2-2:

CAPACITOR SELECTION FOR

QUARTZ CRYSTALS

Typical Capacitor Values

Crystal

Freq

Tested:

Osc Type

FIGURE 2-2:

EXTERNAL CLOCK INPUT

OPERATION (HS OSC

CONFIGURATION)

C1

C2

LP

XT

32 kHz

22 pF

1 MHz

4 MHz

22 pF

OSC1

Clock from

Ext. System

HS

4 MHz

10 MHz

20 MHz

25 MHz

22 pF

PIC18FXXXX

(HS Mode)

OSC2

Open

Capacitor values are for design guidance only.

Different capacitor values may be required to produce

acceptable oscillator operation. The user should test

the performance of the oscillator over the expected

VDD and temperature range for the application. Refer

to the following application notes for oscillator specific

information:

2.3

External Clock Input

The EC and ECIO Oscillator modes require an external

clock source to be connected to the OSC1 pin. There is

no oscillator start-up time required after a Power-on

Reset or after an exit from Sleep mode.

• AN588, “PIC^®Microcontroller Oscillator Design

Guide”

In the EC Oscillator mode, the oscillator frequency

divided by 4 is available on the OSC2 pin. This signal

may be used for test purposes or to synchronize other

logic. Figure 2-3 shows the pin connections for the EC

Oscillator mode.

• AN826, “Crystal Oscillator Basics and Crystal

Selection for rfPIC^®and PIC^®Devices”

• AN849, “Basic PIC^®Oscillator Design”

• AN943, “Practical PIC^®Oscillator Analysis and

Design”

FIGURE 2-3:

EXTERNAL CLOCK

INPUT OPERATION

(EC CONFIGURATION)

• AN949, “Making Your Oscillator Work”

See the notes following this table for additional

information.

OSC1/CLKI

Clock from

Ext. System

PIC18FXXXX

OSC2/CLKO

FOSC/4

Note 1: Higher capacitance increases the stability

of the oscillator but also increases the

start-up time.

The ECIO Oscillator mode functions like the EC mode,

except that the OSC2 pin becomes an additional

general purpose I/O pin. The I/O pin becomes bit 6 of

PORTA (RA6). Figure 2-4 shows the pin connections

for the ECIO Oscillator mode. When operated in this

mode, parameters D033A and D043A apply.

2: When operating below 3V VDD, or when

using certain ceramic resonators at any

voltage, it may be necessary to use the

HS mode or switch to a crystal oscillator.

3: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

FIGURE 2-4:

EXTERNAL CLOCK

INPUT OPERATION

(ECIO CONFIGURATION)

appropriate

values

of

external

components.

4: Rs may be required to avoid overdriving

crystals with low drive level specification.

OSC1/CLKI

PIC18FXXXX

I/O (OSC2)

Clock from

Ext. System

5: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

RA6

DS39689E-page 24

Preliminary

PIC18F4321 FAMILY

2.4

RC Oscillator

2.5

PLL Frequency Multiplier

For timing insensitive applications, the RC and RCIO

Oscillator modes offer additional cost savings. The

actual oscillator frequency is a function of several

factors:

A Phase Locked Loop (PLL) circuit is provided as an

option for users who wish to use a lower frequency

oscillator circuit or to clock the device up to its highest

rated frequency from a crystal oscillator. This may be

useful for customers who are concerned with EMI due

to high-frequency crystals or users who require higher

clock speeds from an internal oscillator.

• supply voltage

• values of the external resistor (REXT) and

capacitor (CEXT)

• operating temperature

2.5.1

HSPLL OSCILLATOR MODE

Given the same device, operating voltage, temperature

and component values, there will also be unit-to-unit

frequency variations. These are due to factors such as:

The HSPLL mode makes use of the HS mode oscillator

for frequencies up to 10 MHz. A PLL then multiplies the

oscillator output frequency by 4 to produce an internal

clock frequency up to 40 MHz. The PLLEN bit is not

available when this mode is configured as the primary

clock source.

• normal manufacturing variation

• difference in lead frame capacitance between

package types (especially for low CEXT values)

The PLL is only available to the crystal oscillator when

the FOSC3:FOSC0 Configuration bits are programmed

for HSPLL mode (= 0110).

• variations within the tolerance of limits of REXT

and CEXT

In the RC Oscillator mode, the oscillator frequency

divided by 4 is available on the OSC2 pin. This signal

may be used for test purposes or to synchronize other

logic. Figure 2-5 shows how the R/C combination is

connected.

FIGURE 2-7:

HSPLLBLOCKDIAGRAM

HS Oscillator Enable

PLL Enable

(from Configuration Register 1H)

FIGURE 2-5:

RC OSCILLATOR MODE

VDD

OSC2

Phase

Comparator

HS Mode

Crystal

Osc

FIN

REXT

OSC1

FOUT

Internal

OSC1

Clock

Loop

Filter

CEXT

VSS

PIC18FXXXX

OSC2/CLKO

FOSC/4

÷4

VCO

SYSCLK

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

20 pF ≤ CEXT ≤ 300 pF

The RCIO Oscillator mode (Figure 2-6) functions like

the RC mode, except that the OSC2 pin becomes an

additional general purpose I/O pin. The I/O pin

becomes bit 6 of PORTA (RA6).

2.5.2

PLL AND INTOSC

The PLL is also available to the internal oscillator block

when the internal oscillator block is configured as the

primary clock source. In this configuration, the PLL is

enabled in software and generates a clock output of up

to 32 MHz. The operation of INTOSC with the PLL is

described in Section 2.6.4 “PLL in INTOSC Modes”.

FIGURE 2-6:

RCIO OSCILLATOR MODE

VDD

REXT

Internal

OSC1

Clock

CEXT

PIC18FXXXX

VSS

I/O (OSC2)

RA6

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

20 pF ≤ CEXT ≤ 300 pF

Preliminary

DS39689E-page 25

PIC18F4321 FAMILY

2.6.2

INTOSC OUTPUT FREQUENCY

2.6

Internal Oscillator Block

The internal oscillator block is calibrated at the factory

to produce an INTOSC output frequency of 8 MHz.

The PIC18F4321 family of devices includes an internal

oscillator block which generates two different clock

signals; either can be used as the microcontroller’s

clock source. This may eliminate the need for external

oscillator circuits on the OSC1 and/or OSC2 pins.

The INTRC oscillator operates independently of the

INTOSC source. Any changes in INTOSC across

voltage and temperature are not necessarily reflected

by changes in INTRC or vice versa.

The main output (INTOSC) is an 8 MHz clock source,

which can be used to directly drive the device clock. It

also drives a postscaler, which can provide a range of

clock frequencies from 31 kHz to 4 MHz. The INTOSC

output is enabled when a clock frequency from 125 kHz

to 8 MHz is selected. The INTOSC output can also be

enabled when 31 kHz is selected, depending on the

INTSRC bit (OSCTUNE<7>).

2.6.3

OSCTUNE REGISTER

The INTOSC output has been calibrated at the

factory but can be adjusted in the user’s application.

This is done by writing to TUN4:TUN0

(OSCTUNE<4:0>) in the OSCTUNE register

(Register 2-1).

The other clock source is the internal RC oscillator

(INTRC), which provides a nominal 31 kHz output.

INTRC is enabled if it is selected as the device clock

source; it is also enabled automatically when any of the

following are enabled:

When the OSCTUNE register is modified, the INTOSC

frequency will begin shifting to the new frequency. The

INTOSC clock will stabilize within 1 ms. Code execu-

tion continues during this shift. There is no indication

that the shift has occurred. The INTRC is not affected

by OSCTUNE.

• Power-up Timer

The OSCTUNE register also implements the INTSRC

(OSCTUNE<7>) and PLLEN (OSCTUNE<6>) bits,

which control certain features of the internal oscillator

block. The INTSRC bit allows users to select which

internal oscillator provides the clock source when the

31 kHz frequency option is selected. This is covered in

greater detail in Section 2.7.1 “Oscillator Control

Register”.

• Fail-Safe Clock Monitor

• Watchdog Timer

• Two-Speed Start-up

These features are discussed in greater detail in

Section 23.0 “Special Features of the CPU”.

The clock source frequency (INTOSC direct, INTRC

direct or INTOSC postscaler) is selected by configuring

the IRCF bits of the OSCCON register (page 31).

The PLLEN bit controls the operation of the Phase

Locked Loop (PLL) in Internal Oscillator modes (see

Figure 2-10).

2.6.1

INTIO MODES

Using the internal oscillator as the clock source elimi-

nates the need for up to two external oscillator pins,

which can then be used for digital I/O. Two distinct

configurations are available:

FIGURE 2-10:

INTOSC AND PLL BLOCK

DIAGRAM

8 or 4 MHz

PLLEN

(OSCTUNE<6>)

• In INTIO1 mode, the OSC2 pin outputs FOSC/4,

while OSC1 functions as RA7 (see Figure 2-8) for

digital input and output.

• In INTIO2 mode, OSC1 functions as RA7 and

OSC2 functions as RA6 (see Figure 2-9), both for

digital input and output.

Phase

Comparator

FIN

INTOSC

FOUT

FIGURE 2-8: INTIO1 OSCILLATOR MODE

Loop

Filter

I/O (OSC1)

OSC2

RA7

PIC18FXXXX

FOSC/4

÷4

VCO

SYSCLK

CLKO

OSC2

FIGURE 2-9: INTIO2 OSCILLATOR MODE

I/O (OSC1)

I/O (OSC2)

RA7

RA6

PIC18FXXXX

RA6

DS39689E-page 26

Preliminary

PIC18F4321 FAMILY

2.6.4

PLL IN INTOSC MODES

2.6.5

INTOSC FREQUENCY DRIFT

The 4x Phase Locked Loop (PLL) can be used with the

internal oscillator block to produce faster device clock

speeds than are normally possible with the internal

oscillator sources. When enabled, the PLL produces a

clock speed of 16 MHz or 32 MHz.

The factory calibrates the internal oscillator block

output (INTOSC) for 8 MHz. However, this frequency

may drift as VDD or temperature changes and can

affect the controller operation in a variety of ways. It is

possible to adjust the INTOSC frequency by modifying

the value in the OSCTUNE register. Depending on the

device, this may have no effect on the INTRC clock

source frequency.

Unlike HSPLL mode, the PLL is controlled through

software. The control bit, PLLEN (OSCTUNE<6>), is

used to enable or disable its operation.

Tuning the INTOSC source requires knowing when to

make the adjustment, in which direction it should be

made and in some cases, how large a change is

needed. Three compensation techniques are discussed

in Section 2.6.5.1 “Compensating with the

EUSART”, Section 2.6.5.2 “Compensating with the

Timers” and Section 2.6.5.3 “Compensating with the

CCP Module in Capture Mode” but other techniques

may be used.

The PLL is available when the device is configured to

use the internal oscillator block as its primary clock

source (FOSC3:FOSC0 = 1001or 1000). Additionally,

the PLL will only function when the selected output fre-

quency is either 4 MHz or 8 MHz (OSCCON<6:4> = 111

or 110). If both of these conditions are not met, the PLL

is disabled and the PLLEN bit remains clear (writes are

ignored).

REGISTER 2-1:

OSCTUNE: OSCILLATOR TUNING REGISTER

R/W-0

INTSRC PLLEN⁽¹⁾

R/W-0

U-0

—

R/W-0

TUN4

R/W-0

TUN3

R/W-0

TUN2

R/W-0

TUN1

R/W-0

TUN0

bit 7

bit 0

bit 7

bit 6

INTSRC: Internal Oscillator Low-Frequency Source Select bit

1= 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)

0= 31 kHz device clock derived directly from INTRC internal oscillator

PLLEN: Frequency Multiplier PLL for INTOSC Enable bit⁽¹⁾

1= PLL enabled for INTOSC (4 MHz and 8 MHz only)

0= PLL disabled

Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable

and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC Modes” for details.

bit 5

Unimplemented: Read as ‘0’

TUN4:TUN0: Frequency Tuning bits

01111= Maximum frequency

bit 4-0

•

00001

00000= Center frequency. Oscillator module is running at the calibrated frequency.

11111

•

10000= Minimum frequency

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39689E-page 27

PIC18F4321 FAMILY

2.6.5.1

Compensating with the EUSART

2.6.5.3

Compensating with the CCP Module

in Capture Mode

An adjustment may be required when the EUSART

begins to generate framing errors or receives data with

errors while in Asynchronous mode. Framing errors

indicate that the device clock frequency is too high. To

adjust for this, decrement the value in OSCTUNE to

reduce the clock frequency. On the other hand, errors

in data may suggest that the clock speed is too low. To

compensate, increment OSCTUNE to increase the

clock frequency.

A CCP module can use free running Timer1 (or

Timer3), clocked by the internal oscillator block and an

external event with a known period (i.e., AC power

frequency). The time of the first event is captured in the

CCPRxH:CCPRxL registers and is recorded for use

later. When the second event causes a capture, the

time of the first event is subtracted from the time of the

second event. Since the period of the external event is

known, the time difference between events can be

calculated.

2.6.5.2

Compensating with the Timers

This technique compares device clock speed to some

reference clock. Two timers may be used; one timer is

clocked by the peripheral clock, while the other is

clocked by a fixed reference source, such as the

Timer1 oscillator.

If the measured time is much greater than the

calculated time, the internal oscillator block is running

too fast. To compensate, decrement the OSCTUNE

register. If the measured time is much less than the

calculated time, the internal oscillator block is running

too slow. To compensate, increment the OSCTUNE

register.

Both timers are cleared, but the timer clocked by the

reference generates interrupts. When an interrupt

occurs, the internally clocked timer is read and both

timers are cleared. If the internally clocked timer value

is much greater than expected, then the internal

oscillator block is running too fast. To adjust for this,

decrement the OSCTUNE register.

DS39689E-page 28

Preliminary

PIC18F4321 FAMILY

The secondary oscillators are those external sources

not connected to the OSC1 or OSC2 pins. These

sources may continue to operate even after the

controller is placed in a power-managed mode.

2.7

Clock Sources and Oscillator

Switching

The PIC18F4321 family of devices includes a feature

that allows the device clock source to be switched from

the main oscillator to an alternate clock source. These

devices also offer two alternate clock sources. When

an alternate clock source is enabled, the various

power-managed operating modes are available.

The PIC18F4321 family of devices offers the Timer1

oscillator as a secondary oscillator. This oscillator, in all

power-managed modes, is often the time base for

functions such as a Real-Time Clock.

Most often, a 32.768 kHz watch crystal is connected

between the RC0/T1OSO/T13CKI and RC1/T1OSI

pins. Like the LP mode oscillator circuit, loading

capacitors are also connected from each pin to ground.

Essentially, there are three clock sources for these

devices:

• Primary oscillators

• Secondary oscillators

• Internal oscillator block

The Timer1 oscillator is discussed in greater detail in

Section 12.3 “Timer1 Oscillator”.

The primary oscillators include the External Crystal

and Resonator modes, the External RC modes, the

External Clock modes and the internal oscillator block.

The particular mode is defined by the FOSC3:FOSC0

Configuration bits. The details of these modes are

covered earlier in this chapter.

In addition to being a primary clock source, the internal

oscillator block is available as a power-managed

mode clock source. The INTRC source is also used as

the clock source for several special features, such as

the WDT and Fail-Safe Clock Monitor.

The clock sources for the PIC18F4321 family of devices

are shown in Figure 2-11. See Section 23.0 “Special

Features of the CPU” for Configuration register details.

FIGURE 2-11:

PIC18F4321 FAMILY CLOCK DIAGRAM

PIC18F2221/2321/4221/4321

Primary Oscillator

LP, XT, HS, RC, EC

HSPLL, INTOSC/PLL

T1OSC

OSC2

Sleep

4 x PLL

OSC1

OSCTUNE<6>

Peripherals

Secondary Oscillator

T1OSO

T1OSCEN

Enable

Oscillator

T1OSI

OSCCON<6:4>

Internal Oscillator

CPU

8 MHz

OSCCON<6:4>

111

110

101

4 MHz

2 MHz

Internal

Oscillator

Block

IDLEN

Clock

Control

1 MHz

100

011

010

001

000

8 MHz

Source

500 kHz

250 kHz

125 kHz

31 kHz

8 MHz

(INTOSC)

INTRC

Source

FOSC3:FOSC0 OSCCON<1:0>

Clock Source Option

for other Modules

1

0

31 kHz (INTRC)

OSCTUNE<7>

WDT, PWRT, FSCM

and Two-Speed Start-up

Preliminary

DS39689E-page 29

PIC18F4321 FAMILY

The IDLEN bit controls whether the device goes into

Sleep mode or one of the Idle modes when the SLEEP

instruction is executed.

2.7.1

OSCILLATOR CONTROL REGISTER

The OSCCON register (Register 2-2) controls several

aspects of the device clock’s operation, both in full

power operation and in power-managed modes.

The use of the flag and control bits in the OSCCON

register is discussed in more detail in Section 3.0

“Power-Managed Modes”.

The System Clock Select bits, SCS1:SCS0, select the

clock source. The available clock sources are the

primary clock (defined by the FOSC3:FOSC0 Configu-

ration bits), the secondary clock (Timer1 oscillator) and

the internal oscillator block. The clock source changes

immediately after either of the SCSI:SCSO bits are

changed, following a brief clock transition interval. The

SCS bits are reset on all forms of Reset.

Note 1: The Timer1 oscillator must be enabled to

select the secondary clock source. The

Timer1 oscillator is enabled by setting the

T1OSCEN bit in the Timer1 Control regis-

ter (T1CON<3>). If the Timer1 oscillator

is not enabled, then any attempt to select

a secondary clock source will be ignored.

The Internal Oscillator Frequency Select bits

(IRCF2:IRCF0) select the frequency output of the

internal oscillator block to drive the device clock. The

choices are the INTRC source (31 kHz), the INTOSC

source (8 MHz) or one of the frequencies derived from

the INTOSC postscaler (31.25 kHz to 4 MHz). If the

internal oscillator block is supplying the device clock,

changing the states of these bits will have an immedi-

ate change on the internal oscillator’s output. On

device Resets, the default output frequency of the

internal oscillator block is set at 1 MHz.

2: It is recommended that the Timer1

oscillator be operating and stable before

selecting the secondary clock source or a

very long delay may occur while the

Timer1 oscillator starts.

2.7.2

OSCILLATOR TRANSITIONS

The PIC18F4321 family of devices contains circuitry to

prevent clock “glitches” when switching between clock

sources. A short pause in the device clock occurs dur-

ing the clock switch. The length of this pause is the sum

of two cycles of the old clock source and three to four

cycles of the new clock source. This formula assumes

that the new clock source is stable.

When a nominal output frequency of 31 kHz is selected

(IRCF2:IRCF0 = 000), users may choose which

internal oscillator acts as the source. This is done with

the INTSRC bit in the OSCTUNE register

(OSCTUNE<7>). Setting this bit selects INTOSC as a

31.25 kHz clock source derived from the INTOSC

postscaler. Clearing INTSRC selects INTRC (nominally

31 kHz) as the clock source and disables the INTOSC

to reduce current consumption.

Clock transitions are discussed in greater detail in

Section 3.1.2 “Entering Power-Managed Modes”.

This option allows users to select the tunable and more

precise INTOSC as a clock source, while maintaining

power savings with a very low clock speed. Addition-

ally, the INTOSC source will already be stable should a

switch to a higher frequency be needed quickly.

Regardless of the setting of INTSRC, INTRC always

remains the clock source for features such as the

Watchdog Timer and the Fail-Safe Clock Monitor.

The OSTS, IOFS and T1RUN bits indicate which clock

source is currently providing the device clock. The

OSTS bit indicates that the Oscillator Start-up Timer

and PLL Start-up Timer (if enabled) have timed out and

the primary clock is providing the device clock in

primary clock modes. The IOFS bit indicates when the

internal oscillator block has stabilized and is providing

the device clock in RC Clock modes. The T1RUN bit

(T1CON<6>) indicates when the Timer1 oscillator is

providing the device clock in secondary clock modes.

In power-managed modes, only one of these three bits

will be set at any time. If none of these bits are set, the

INTRC is providing the clock or the internal oscillator

block has just started and is not yet stable.

DS39689E-page 30

Preliminary

PIC18F4321 FAMILY

REGISTER 2-2:

OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0

IDLEN

R/W-1

R/W-0

R⁽¹⁾

R-0

R/W-0

IRCF2⁽⁵⁾IRCF1⁽⁵⁾IRCF0⁽⁵⁾

OSTS

IOFS

SCS1⁽⁴⁾

SCS0⁽⁴⁾

bit 7

bit 0

bit 7

IDLEN: Idle Enable bit

1= Device enters an Idle mode when a SLEEPinstruction is executed

0= Device enters Sleep mode when a SLEEPinstruction is executed

bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits⁽⁵⁾

111= 8 MHz (INTOSC drives clock directly)

110= 4 MHz

101= 2 MHz

100= 1 MHz⁽³⁾

011= 500 kHz

010= 250 kHz

001= 125 kHz

000= 31 kHz (from either INTOSC/256 or INTRC directly)⁽²⁾

bit 3

bit 2

OSTS: Oscillator Start-up Time-out Status bit⁽¹⁾

1= Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running

0= Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready

IOFS: INTOSC Frequency Stable bit

1= INTOSC frequency is stable

0= INTOSC frequency is not stable

bit 1-0 SCS1:SCS0: System Clock Select bits⁽⁴⁾

1x= Internal oscillator block

01= Secondary (Timer1) oscillator

00= Primary oscillator

Note 1: Reset state depends on state of the IESO Configuration bit.

2: Source selected by the INTSRC bit (OSCTUNE<7>), see text.

3: Default output frequency of INTOSC on Reset.

4: Modifying the SCSI:SCSO bits will cause an immediate clock source switch.

5: Modifying the IRCF3:IRCF0 bits will cause an immediate clock frequency switch if

the internal oscillator is providing the device clocks.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39689E-page 31

PIC18F4321 FAMILY

2.8

Effects of Power-Managed Modes

on the Various Clock Sources

2.9

Power-up Delays

Power-up delays are controlled by two or three timers,

so that no external Reset circuitry is required for most

applications. The delays ensure that the device is kept

in Reset until the device power supply is stable under

normal circumstances and the primary clock is operat-

ing and stable. For additional information on power-up

delays, see Section 4.5 “Device Reset Timers”.

When PRI_IDLE mode is selected, the configured

oscillator continues to run without interruption. For all

other power-managed modes, the oscillator using the

OSC1 pin is disabled. The OSC1 pin (and OSC2 pin in

Crystal Oscillator modes) will stop oscillating.

In secondary clock modes (SEC_RUN and

SEC_IDLE), the Timer1 oscillator is operating and

providing the device clock. The Timer1 oscillator may

also run in all power-managed modes if required to

clock Timer1 or Timer3.

The first timer is the Power-up Timer (PWRT) which

provides a fixed delay on power-up (parameter 33,

Table 26-10). It is enabled by clearing (= 0) the

PWRTEN Configuration bit (CONFIG2L<0>).

In internal oscillator modes (RC_RUN and RC_IDLE),

the internal oscillator block provides the device clock

source. The 31 kHz INTRC output can be used directly

to provide the clock and may be enabled to support

various special features, regardless of the power-

managed mode (see Section 23.2 “Watchdog Timer

(WDT)” and Section 23.4 “Fail-Safe Clock Monitor”

for more information). The INTOSC output at 8 MHz

may be used directly to clock the device or may be

divided down by the postscaler. The INTOSC output is

disabled if the clock is provided directly from the INTRC

output. The INTOSC output is also enabled for Two-

Speed Start-up at 1 MHz after Resets and when

configured for wake from Sleep mode.

2.9.1

DELAYS FOR POWER-UP AND

RETURN TO PRIMARY CLOCK

The second timer is the Oscillator Start-up Timer

(OST), intended to delay execution until the crystal

oscillator is stable (LP, XT and HS modes). The OST

does this by counting 1024 oscillator cycles before

allowing the oscillator to clock the device.

When the HSPLL Oscillator mode is selected, a third

timer delays execution for an additional 2 ms following

the HS mode OST delay, so the PLL can lock to the

incoming clock frequency. At the end of these delays,

the OSTS bit (OSCCON<3>) is set.

There is a delay of interval TCSD (parameter 38,

Table 26-10), once execution is allowed to start, when

the controller becomes ready to execute instructions.

This delay runs concurrently with any other delays.

This may be the only delay that occurs when any of the

EC, RC or INTIO modes are used as the primary clock

source.

If the Sleep mode is selected, all clock sources are

stopped. Since all the transistor switching currents

have been stopped, Sleep mode achieves the lowest

current consumption of the device (only leakage

currents).

Enabling any on-chip feature that will operate during

Sleep will increase the current consumed during Sleep.

The INTRC is required to support WDT operation. The

Timer1 oscillator may be operating to support a Real-

Time Clock. Other features may be operating that do

not require a device clock source (i.e., MSSP slave,

PSP, INTn pins and others). Peripherals that may add

significant current consumption are listed in

Section 26.2 “DC Characteristics”.

TABLE 2-3:

OSC1 AND OSC2 PIN STATES IN SLEEP MODE

OSC Mode

OSC1 Pin

OSC2 Pin

RC, INTIO1

RCIO

Floating, external resistor pulls high

Configured as PORTA, bit 7

At logic low (clock/4 output)

Configured as PORTA, bit 6

At logic low (clock/4 output)

INTIO2

ECIO

Floating, driven by external clock

EC

LP, XT and HS

Feedback inverter disabled at quiescent

voltage level

Feedback inverter disabled at quiescent

voltage level

Note:

See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.

DS39689E-page 32

Preliminary

PIC18F4321 FAMILY

3.1.1

CLOCK SOURCES

3.0

POWER-MANAGED MODES

The SCS1:SCS0 bits allow the selection of one of three

clock sources for power-managed modes. They are:

PIC18F4321 family devices offer a total of seven oper-

ating modes for more efficient power-management.

These modes provide a variety of options for selective

power conservation in applications where resources

may be limited (i.e., battery-powered devices).

• the primary clock, as defined by the

FOSC3:FOSC0 Configuration bits

• the secondary clock (the Timer1 oscillator)

• the internal oscillator block (for RC modes)

There are three categories of power-managed modes:

• Run modes

• Idle modes

• Sleep mode

3.1.2

ENTERING POWER-MANAGED

MODES

Switching from one power-managed mode to another

begins by loading the OSCCON register. The

SCS1:SCS0 bits select the clock source and determine

which Run or Idle mode is to be used. Changing these

bits causes an immediate switch to the new clock

source, assuming that it is running. The switch may

also be subject to clock transition delays. These are

discussed in Section 3.1.3 “Clock Transitions and

Status Indicators” and subsequent sections.

These categories define which portions of the device

are clocked and sometimes, what speed. The Run and

Idle modes may use any of the three available clock

sources (primary, secondary or internal oscillator

block); the Sleep mode does not use a clock source.

The power-managed modes include several power-

saving features offered on previous PIC^®devices. One

is the clock switching feature, offered in other PIC18

devices, allowing the controller to use the Timer1 oscil-

lator in place of the primary oscillator. Also included is

the Sleep mode, offered by all PIC devices, where all

device clocks are stopped.

Entry to the power-managed Idle or Sleep modes is

triggered by the execution of a SLEEPinstruction. The

actual mode that results depends on the status of the

IDLEN bit.

Depending on the current mode and the mode being

switched to, a change to a power-managed mode does

not always require setting all of these bits. Many

transitions may be done by changing the oscillator select

bits, or changing the IDLEN bit, prior to issuing a SLEEP

instruction. If the IDLEN bit is already configured

correctly, it may only be necessary to perform a SLEEP

instruction to switch to the desired mode.

3.1

Selecting Power-Managed Modes

Selecting

a power-managed mode requires two

decisions: if the CPU is to be clocked or not and the

selection of clock source. The IDLEN bit

(OSCCON<7>) controls CPU clocking, while the

SCS1:SCS0 bits (OSCCON<1:0>) select the clock

source. The individual modes, bit settings, clock sources

and affected modules are summarized in Table 3-1.

a

TABLE 3-1:

Mode

POWER-MANAGED MODES

OSCCON Bits

Module Clocking

IDLEN⁽¹⁾SCS1:SCS0

Available Clock and Oscillator Source

CPU

Peripherals

<7>

<1:0>

Sleep

0

N/A

Off

None – All clocks are disabled

PRI_RUN

N/A

00

Clocked

Primary – LP, XT, HS, HSPLL, RC, EC and

Internal Oscillator Block.⁽²⁾

This is the normal full power execution mode.

SEC_RUN

RC_RUN

PRI_IDLE

SEC_IDLE

RC_IDLE

N/A

1

01

1x

00

01

1x

Clocked

Off

Clocked

Secondary – Timer1 Oscillator

Internal Oscillator Block⁽²⁾

Primary – LP, XT, HS, HSPLL, RC, EC

Secondary – Timer1 Oscillator

Internal Oscillator Block⁽²⁾

1

Off

1

Off

Note 1: IDLEN reflects its value when the SLEEPinstruction is executed.

2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.

Preliminary

DS39689E-page 33

PIC18F4321 FAMILY

3.1.3

CLOCK TRANSITIONS AND STATUS

INDICATORS

3.2

Run Modes

In the Run modes, clocks to both the core and

peripherals are active. The difference between these

modes is the clock source.

The length of the transition between clock sources is

the sum of two cycles of the old clock source and three

to four cycles of the new clock source. This formula

assumes that the new clock source is stable.

3.2.1

PRI_RUN MODE

Three bits indicate the current clock source and its

status. They are:

The PRI_RUN mode is the normal, full power execution

mode of the microcontroller. This is also the default

mode upon a device Reset unless Two-Speed Start-up

is enabled (see Section 23.3 “Two-Speed Start-up”

or Section 23.4 “Fail-Safe Clock Monitor” for

details). In this mode, the OSTS bit is set. The IOFS bit

may be set if the internal oscillator block is the primary

clock source (see Section 2.7.1 “Oscillator Control

Register”).

• OSTS (OSCCON<3>)

• IOFS (OSCCON<2>)

• T1RUN (T1CON<6>)

In general, only one of these bits will be set while in a

given power-managed mode. When the OSTS bit is

set, the primary clock is providing the device clock.

When the IOFS bit is set, the INTOSC output is

providing a stable 8 MHz clock source to a divider that

actually drives the device clock. When the T1RUN bit is

set, the Timer1 oscillator is providing the clock. If none

of these bits are set, then either the INTRC clock

source is clocking the device, or the INTOSC source is

not yet stable.

3.2.2

SEC_RUN MODE

The SEC_RUN mode is the compatible mode to the

“clock switching” feature offered in other PIC18

devices. In this mode, the CPU and peripherals are

clocked from the Timer1 oscillator. This gives users the

option of lower power consumption while still using a

high accuracy clock source.

If the internal oscillator block is configured as the primary

clock source by the FOSC3:FOSC0 Configuration bits,

then both the OSTS and IOFS bits may be set when in

PRI_RUN or PRI_IDLE modes. This indicates that the

primary clock (INTOSC) is generating a stable 8 MHz

output. Switching the clock source to the Timer1

oscillator would clear the OSTS bit.

SEC_RUN mode is entered by setting the SCS1:SCS0

bits to ‘01’. The device clock source is switched to the

Timer1 oscillator (see Figure 3-1), the primary oscillator

is shut down, the T1RUN bit (T1CON<6>) is set and the

OSTS bit is cleared.

Note:

The Timer1 oscillator should already be

running prior to entering SEC_RUN mode.

If the T1OSCEN bit is not set when the

SCS1:SCS0 bits are set to ‘01’, entry to

SEC_RUN mode will not occur. If the

Timer1 oscillator is enabled, but not yet

running, device clocks will be delayed until

the oscillator has started. In such situa-

tions, initial oscillator operation is far from

stable and unpredictable operation may

result.

Note 1: Caution should be used when modifying a

single IRCF bit. If VDD is less than 3V, it is

possible to select a higher clock speed

than is supported by the low VDD.

Improper device operation may result if

the VDD/FOSC specifications are violated.

2: Executing a SLEEP instruction does not

necessarily place the device into Sleep

mode. It acts as the trigger to place the

controller into either the Sleep mode or

one of the Idle modes, depending on the

setting of the IDLEN bit.

On transitions from SEC_RUN mode to PRI_RUN, the

peripherals and CPU continue to be clocked from the

Timer1 oscillator while the primary clock is started.

When the primary clock becomes ready, a clock switch

back to the primary clock occurs (see Figure 3-2).

When the clock switch is complete, the T1RUN bit is

cleared, the OSTS bit is set and the primary clock is

providing the clock. The IDLEN and SCS bits are not

affected by the wake-up; the Timer1 oscillator

continues to run.

3.1.4

MULTIPLE SLEEP COMMANDS

The power-managed mode that is invoked with the

SLEEP instruction is determined by the setting of the

IDLEN bit at the time the instruction is executed. If

another SLEEPinstruction is executed, the device will

enter the power-managed mode specified by IDLEN at

that time. If IDLEN has changed, the device will enter

the new power-managed mode specified by the new

setting.

DS39689E-page 34

Preliminary

PIC18F4321 FAMILY

FIGURE 3-1:

TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE

Q1 Q2 Q3 Q4 Q1

Q2

Q3

Q4

Q1

Q2

Q3

1

2

3

n-1

n

T1OSI

Clock Transition⁽¹⁾

OSC1

CPU

Clock

Peripheral

Clock

Program

Counter

PC

PC + 2

PC + 4

Note 1: Clock transition typically occurs within 2-4 TOSC.

FIGURE 3-2:

TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)

Q1

Q2

Q3

Q4

Q1

Q2 Q3 Q4 Q1 Q2 Q3

T1OSI

OSC1

(1)

TOST

(1)

TPLL

1

2

n-1

n

PLL Clock

Output

Clock

Transition⁽²⁾

CPU Clock

Peripheral

Clock

Program

Counter

PC

PC + 2

PC + 4

SCS1:SCS0 bits Changed

OSTS bit Set

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

2: Clock transition typically occurs within 2-4 TOSC.

This mode is entered by setting the SCS1 bit to ‘1’.

3.2.3

RC_RUN MODE

Although it is ignored, it is recommended that the SCS0

bit also be cleared; this is to maintain software compat-

ibility with future devices. When the clock source is

switched to the INTOSC multiplexer (see Figure 3-3),

the primary oscillator is shut down and the OSTS bit is

cleared. The IRCF bits may be modified at any time to

immediately change the clock speed.

In RC_RUN mode, the CPU and peripherals are

clocked from the internal oscillator block using the

INTOSC multiplexer. In this mode, the primary clock is

shut down. When using the INTRC source, this mode

provides the best power conservation of all the Run

modes, while still executing code. It works well for user

applications which are not highly timing sensitive or do

not require high-speed clocks at all times.

Note:

Caution should be used when modifying a

single IRCF bit. If VDD is less than 3V, it is

possible to select a higher clock speed

than is supported by the low VDD.

Improper device operation may result if

the VDD/FOSC specifications are violated.

If the primary clock source is the internal oscillator block

(either INTRC or INTOSC), there are no distinguishable

differences between PRI_RUN and RC_RUN modes

during execution. However, a clock switch delay will

occur during entry to and exit from RC_RUN mode.

Therefore, if the primary clock source is the internal

oscillator block, the use of RC_RUN mode is not

recommended.

Preliminary

DS39689E-page 35

PIC18F4321 FAMILY

If the IRCF bits and the INTSRC bit are all clear, the

INTOSC output is not enabled and the IOFS bit will

remain clear; there will be no indication of the current

clock source. The INTRC source is providing the

device clocks.

On transitions from RC_RUN mode to PRI_RUN mode,

the device continues to be clocked from the INTOSC

multiplexer while the primary clock is started. When the

primary clock becomes ready, a clock switch to the

primary clock occurs (see Figure 3-4). When the clock

switch is complete, the IOFS bit is cleared, the OSTS

bit is set and the primary clock is providing the device

clock. The IDLEN and SCS bits are not affected by the

switch. The INTRC source will continue to run if either

the WDT or the Fail-Safe Clock Monitor is enabled.

If the IRCF bits are changed from all clear (thus,

enabling the INTOSC output) or if INTSRC is set, the

IOFS bit becomes set after the INTOSC output

becomes stable. Clocks to the device continue while

the INTOSC source stabilizes after an interval of

TIOBST (parameter 39, Table 26-10).

If the IRCF bits were previously at a non-zero value, or

if INTSRC was set before setting SCS1 and the

INTOSC source was already stable, the IOFS bit will

remain set.

FIGURE 3-3:

TRANSITION TIMING TO RC_RUN MODE

Q1 Q2 Q3 Q4 Q1

Q2

Q3

Q4

Q1

Q2

Q3

1

2

3

n-1

n

INTRC

OSC1

Clock Transition⁽¹⁾

CPU

Clock

Peripheral

Clock

Program

Counter

PC

PC + 2

PC + 4

Note 1: Clock transition typically occurs within 2-4 TOSC.

FIGURE 3-4:

TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE

Q3

Q4

Q1

Q2 Q3 Q4 Q1 Q2 Q3

Q1

Q2

INTOSC

Multiplexer

OSC1

(1)

TPLL

TOST

1

2

n-1

n

PLL Clock

Output

Clock

Transition⁽²⁾

CPU Clock

Peripheral

Clock

Program

Counter

PC

PC + 2

PC + 4

SCS1:SCS0 bits Changed

OSTS bit Set

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

2: Clock transition typically occurs within 2-4 TOSC.

DS39689E-page 36

Preliminary

PIC18F4321 FAMILY

3.3

Sleep Mode

3.4

Idle Modes

The power-managed Sleep mode in the PIC18F4321

family devices is identical to the legacy Sleep mode

offered in all other PIC devices. It is entered by clearing

the IDLEN bit (the default state on device Reset) and

executing the SLEEPinstruction. This shuts down the

selected oscillator (Figure 3-5). All clock source status

bits are cleared.

The Idle modes allow the controller’s CPU to be

selectively shut down while the peripherals continue to

operate. Selecting a particular Idle mode allows users

to further manage power consumption.

If the IDLEN bit is set to a ‘1’ when a SLEEPinstruction is

executed, the peripherals will be clocked from the clock

source selected using the SCS1:SCS0 bits; however, the

CPU will not be clocked. The clock source status bits are

not affected. Setting IDLEN and executing a SLEEP

instruction provides a quick method of switching from a

given Run mode to its corresponding Idle mode.

Entering the Sleep mode from any other mode does not

require a clock switch. This is because no clocks are

needed once the controller has entered Sleep. If the

WDT is selected, the INTRC source will continue to

operate. If the Timer1 oscillator is enabled, it will also

continue to run.

If the WDT is selected, the INTRC source will continue

to operate. If the Timer1 oscillator is enabled, it will also

continue to run.

When a wake event occurs in Sleep mode (by interrupt,

Reset or WDT time-out), the device will not be clocked

until the clock source selected by the SCS1:SCS0 bits

becomes ready (see Figure 3-6), or it will be clocked

from the internal oscillator block if either the Two-

Speed Start-up or the Fail-Safe Clock Monitor are

enabled (see Section 23.0 “Special Features of the

CPU”). In either case, the OSTS bit is set when the

primary clock is providing the device clocks. The

IDLEN and SCS bits are not affected by the wake-up.

Since the CPU is not executing instructions, the only

exits from any of the Idle modes are by interrupt, WDT

time-out or a Reset. When a wake event occurs, CPU

execution is delayed by an interval of TCSD

(parameter 38, Table 26-10) while it becomes ready to

execute code. When the CPU begins executing code,

it resumes with the same clock source for the current

Idle mode. For example, when waking from RC_IDLE

mode, the internal oscillator block will clock the CPU

and peripherals (in other words, RC_RUN mode). The

IDLEN and SCS bits are not affected by the wake-up.

While in any Idle mode or the Sleep mode, a WDT

time-out will result in a WDT wake-up to the Run mode

currently specified by the SCS1:SCS0 bits.

FIGURE 3-5:

TRANSITION TIMING FOR ENTRY TO SLEEP MODE

Q1 Q2 Q3 Q4 Q1

OSC1

CPU

Clock

Peripheral

Clock

Sleep

Program

Counter

PC

PC + 2

FIGURE 3-6:

TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q2 Q3 Q4 Q1 Q2

Q1

OSC1

(1)

TPLL

TOST

PLL Clock

Output

CPU Clock

Peripheral

Clock

Program

Counter

PC

PC + 2

PC + 4

PC + 6

Wake Event

Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

OSTS bit Set

Preliminary

DS39689E-page 37

PIC18F4321 FAMILY

3.4.1

PRI_IDLE MODE

3.4.2

SEC_IDLE MODE

This mode is unique among the three low-power Idle

modes, in that it does not disable the primary device

clock. For timing sensitive applications, this allows for

the fastest resumption of device operation with its more

accurate primary clock source, since the clock source

does not have to “warm-up” or transition from another

oscillator.

In SEC_IDLE mode, the CPU is disabled but the

peripherals continue to be clocked from the Timer1

oscillator. This mode is entered from SEC_RUN by

setting the IDLEN bit and executing

a SLEEP

instruction. If the device is in another Run mode, set the

IDLEN bit first, then set the SCS1:SCS0 bits to ‘01’ and

execute SLEEP. When the clock source is switched to

the Timer1 oscillator, the primary oscillator is shut down,

the OSTS bit is cleared and the T1RUN bit is set.

PRI_IDLE mode is entered from PRI_RUN mode by

setting the IDLEN bit and executing a SLEEPinstruc-

tion. If the device is in another Run mode, set IDLEN

first, then clear the SCS bits and execute SLEEP.

Although the CPU is disabled, the peripherals continue

to be clocked from the primary clock source specified

by the FOSC3:FOSC0 Configuration bits. The OSTS

bit remains set (see Figure 3-7).

When a wake event occurs, the peripherals continue to

be clocked from the Timer1 oscillator. After an interval

of TCSD following the wake event, the CPU begins exe-

cuting code being clocked by the Timer1 oscillator. The

IDLEN and SCS bits are not affected by the wake-up;

the Timer1 oscillator continues to run (see Figure 3-8).

When a wake event occurs, the CPU is clocked from the

primary clock source. A delay of interval TCSD (parame-

ter 38, Table 26-10) is required between the wake event

and when code execution starts. This is required to

allow the CPU to become ready to execute instructions.

After the wake-up, the OSTS bit remains set. The

IDLEN and SCS bits are not affected by the wake-up

(see Figure 3-8).

Note:

The Timer1 oscillator should already be

running prior to entering SEC_IDLE mode.

If the T1OSCEN bit is not set when writing

the SCS<1:0> bits, entry to SEC_IDLE

mode will not occur. If the Timer1 oscillator

is enabled but not yet running, peripheral

clocks will be delayed until the oscillator

has started. In such situations, initial oscil-

lator operation is far from stable and

unpredictable operation may result.

FIGURE 3-7:

TRANSITION TIMING FOR ENTRY TO IDLE MODE

Q3

Q4

Q1

Q2

OSC1

CPU Clock

Peripheral

Clock

Program

Counter

PC

PC + 2

FIGURE 3-8:

TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE

Q1

Q3

Q4

Q2

OSC1

TCSD

CPU Clock

Peripheral

Clock

Program

Counter

PC

Wake Event

DS39689E-page 38

Preliminary

PIC18F4321 FAMILY

On all exits from Idle or Sleep modes by interrupt, code

execution branches to the interrupt vector if the GIE/

GIEH bit (INTCON<7>) is set. Otherwise, code execution

continues or resumes without branching (see

Section 9.0 “Interrupts”).

3.4.3

RC_IDLE MODE

In RC_IDLE mode, the CPU is disabled but the periph-

erals continue to be clocked from the internal oscillator

block using the INTOSC multiplexer. This mode allows

for controllable power conservation during Idle periods.

A fixed delay of interval TCSD following the wake event

is required when leaving Sleep and Idle modes. This

delay is required for the CPU to prepare for execution.

Instruction execution resumes on the first clock cycle

following this delay.

From RC_RUN, this mode is entered by setting the

IDLEN bit and executing a SLEEP instruction. If the

device is in another Run mode, first set IDLEN, then set

the SCS1 bit and execute SLEEP. Although its value is

ignored, it is recommended that SCS0 also be cleared;

this is to maintain software compatibility with future

devices. The INTOSC multiplexer may be used to

select a higher clock frequency by modifying the IRCF

bits before executing the SLEEPinstruction. When the

clock source is switched to the INTOSC multiplexer, the

primary oscillator is shut down and the OSTS bit is

cleared.

3.5.2

EXIT BY WDT TIME-OUT

A WDT time-out will cause different actions depending

on which power-managed mode the device is in when

the time-out occurs.

If the device is not executing code (all Idle modes and

Sleep mode), the time-out will result in an exit from the

power-managed mode (see Section 3.2 “Run

Modes” and Section 3.3 “Sleep Mode”). If the device

is executing code (all Run modes), the time-out will

result in a WDT Reset (see Section 23.2 “Watchdog

Timer (WDT)”).

If the IRCF bits are set to any non-zero value, or the

INTSRC bit is set, the INTOSC output is enabled. The

IOFS bit becomes set, after the INTOSC output

becomes stable, after an interval of TIOBST

(parameter 39, Table 26-10). Clocks to the peripherals

continue while the INTOSC source stabilizes. If the

IRCF bits were previously at a non-zero value, or

INTSRC was set before the SLEEP instruction was

executed and the INTOSC source was already stable,

the IOFS bit will remain set. If the IRCF bits and

INTSRC are all clear, the INTOSC output will not be

enabled, the IOFS bit will remain clear and there will be

no indication of the current clock source.

The WDT timer and postscaler are cleared by

executing a SLEEPor CLRWDTinstruction, the loss of a

currently selected clock source (if the Fail-Safe Clock

Monitor is enabled) and modifying the IRCF bits in the

OSCCON register if the internal oscillator block is the

device clock source.

3.5.3

EXIT BY RESET

When a wake event occurs, the peripherals continue to

be clocked from the INTOSC multiplexer. After a delay of

TCSD following the wake event, the CPU begins execut-

ing code being clocked by the INTOSC multiplexer. The

IDLEN and SCS bits are not affected by the wake-up.

The INTRC source will continue to run if either the WDT

or the Fail-Safe Clock Monitor is enabled.

Normally, the device is held in Reset by the Oscillator

Start-up Timer (OST) until the primary clock becomes

ready. At that time, the OSTS bit is set and the device

begins executing code. If the internal oscillator block is

the new clock source, the IOFS bit is set instead.

The exit delay time from Reset to the start of code

execution depends on both the clock sources before

and after the wake-up and the type of oscillator if the

new clock source is the primary clock. Exit delays are

summarized in Table 3-2.

3.5

Exiting Idle and Sleep Modes

An exit from Sleep mode or any of the Idle modes is

triggered by an interrupt, a Reset or a WDT time-out.

This section discusses the triggers that cause exits

from power-managed modes. The clocking subsystem

actions are discussed in each of the power-managed

modes (see Section 3.2 “Run Modes”, Section 3.3

“Sleep Mode” and Section 3.4 “Idle Modes”).

Code execution can begin before the primary clock

becomes ready. If either the Two-Speed Start-up (see

Section 23.3 “Two-Speed Start-up”) or Fail-Safe

Clock Monitor (see Section 23.4 “Fail-Safe Clock

Monitor”) is enabled, the device may begin execution

as soon as the Reset source has cleared. Execution is

clocked by the INTOSC multiplexer driven by the

internal oscillator block. Execution is clocked by the

internal oscillator block until either the primary clock

becomes ready or a power-managed mode is entered

before the primary clock becomes ready; the primary

clock is then shut down.

3.5.1

EXIT BY INTERRUPT

Any of the available interrupt sources can cause the

device to exit from an Idle mode, or the Sleep mode to

a Run mode. To enable this functionality, an interrupt

source must be enabled by setting its enable bit in one

of the INTCON or PIE registers. The exit sequence is

initiated when the corresponding interrupt flag bit is set.

Preliminary

DS39689E-page 39

PIC18F4321 FAMILY

In these instances, the primary clock source either

does not require an oscillator start-up delay since it is

already running (PRI_IDLE), or normally does not

require an oscillator start-up delay (RC, EC and INTIO

Oscillator modes). However, a fixed delay of interval

TCSD following the wake event is still required when

leaving Sleep and Idle modes to allow the CPU to

prepare for execution. Instruction execution resumes

on the first clock cycle following this delay.

3.5.4

EXIT WITHOUT AN OSCILLATOR

START-UP DELAY

Certain exits from power-managed modes do not

invoke the OST at all. There are two cases:

• PRI_IDLE mode, where the primary clock source

is not stopped; and

• the primary clock source is not any of the LP, XT,

HS or HSPLL modes.

TABLE 3-2:

EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE

(BY CLOCK SOURCES)

Clock Source

before Wake-up

Clock Source

after Wake-up

Clock Ready Status

Bit (OSCCON)

Exit Delay

LP, XT, HS

HSPLL

OSTS

IOFS

OSTS

IOFS

OSTS

IOFS

OSTS

IOFS

Primary Device Clock

(PRI_IDLE mode)

(1)

TCSD

EC, RC

INTOSC⁽²⁾

LP, XT, HS

HSPLL

(3)

TOST

(3)

TOST + t_rc

T1OSC

(1)

EC, RC

TCSD

INTOSC⁽²⁾

LP, XT, HS

HSPLL

TIOBST

(4)

(3)

TOST

(3)

TOST + t_rc

INTOSC⁽³⁾

(1)

EC, RC

TCSD

INTOSC⁽²⁾

LP, XT, HS

HSPLL

None

(3)

TOST

(3)

TOST + t_rc

None

(Sleep mode)

(1)

EC, RC

INTOSC⁽²⁾

TCSD

(4)

TIOBST

Note 1: TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently

with any other required delays (see Section 3.4 “Idle Modes”). On Reset, INTOSC defaults to 1 MHz.

2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.

3: TOST is the Oscillator Start-up Timer (parameter 32). t_rcis the PLL Lock-out Timer (parameter F12); it is

also designated as TPLL.

4: Execution continues during TIOBST (parameter 39), the INTOSC stabilization period.

DS39689E-page 40

Preliminary

PIC18F4321 FAMILY

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 4-1.

4.0

RESET

The PIC18F4321 family devices differentiate between

various kinds of Reset:

4.1

RCON Register

a) Power-on Reset (POR)

Device Reset events are tracked through the RCON

register (Register 4-1). The lower five bits of the regis-

ter indicate that a specific Reset event has occurred. In

most cases, these bits can only be cleared by the event

and must be set by the application after the event. The

state of these flag bits, taken together, can be read to

indicate the type of Reset that just occurred. This is

described in more detail in Section 4.6 “Reset State

of Registers”.

b) MCLR Reset during normal operation

c) MCLR Reset during power-managed modes

d) Watchdog Timer (WDT) Reset (during

execution)

e) Programmable Brown-out Reset (BOR)

f) RESETInstruction

g) Stack Full Reset

h) Stack Underflow Reset

The RCON register also has control bits for setting

interrupt priority (IPEN) and software control of the

BOR (SBOREN). Interrupt priority is discussed in

Section 9.0 “Interrupts”. BOR is covered in

Section 4.4 “Brown-out Reset (BOR)”.

This section discusses Resets generated by MCLR,

POR and BOR and covers the operation of the various

start-up timers. Stack Reset events are covered in

Section 5.1.2.4 “Stack Full and Underflow Resets”.

WDT Resets are covered in Section 23.2 “Watchdog

Timer (WDT)”.

FIGURE 4-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

RESET

Instruction

Stack Full/Underflow Reset

Stack

Pointer

External Reset

MCLRE

MCLR

( )_IDLE

Sleep

WDT

Time-out

VDD Rise

Detect

POR Pulse

BOREN

VDD

Brown-out

Reset

S

OST/PWRT

OST

10-bit Ripple Counter

1024 Cycles

Chip_Reset

Q

R

OSC1

32 μs

65.5 ms

PWRT

11-bit Ripple Counter

INTRC⁽¹⁾

Enable PWRT

(2)

Enable OST

Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.

2: See Table 4-2 for time-out situations.

Preliminary

DS39689E-page 41

PIC18F4321 FAMILY

REGISTER 4-1:

RCON: RESET CONTROL REGISTER

R/W-0

IPEN

R/W-1⁽¹⁾

U-0

—

R/W-1

RI

R-1

TO

R-1

PD

R/W-0⁽²⁾

POR

R/W-0

BOR

SBOREN

bit 7

bit 0

bit 7

bit 6

IPEN: Interrupt Priority Enable bit

1= Enable priority levels on interrupts

0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

SBOREN: BOR Software Enable bit⁽¹⁾

If BOREN1:BOREN0 = 01:

1= BOR is enabled

0= BOR is disabled

If BOREN1:BOREN0 = 00, 10or 11:

Bit is disabled and read as ‘0’.

bit 5

bit 4

Unimplemented: Read as ‘0’

RI: RESETInstruction Flag bit

1= The RESETinstruction was not executed (set by firmware only)

0= The RESETinstruction was executed causing a device Reset (must be set in software after

a Brown-out Reset occurs)

bit 3

bit 2

bit 1

bit 0

TO: Watchdog Time-out Flag bit

1= Set by power-up, CLRWDTinstruction or SLEEPinstruction

0= A WDT time-out occurred

PD: Power-Down Detection Flag bit

1= Set by power-up or by the CLRWDTinstruction

0= Set by execution of the SLEEPinstruction

POR: Power-on Reset Status bit⁽²⁾

1= A Power-on Reset has not occurred (set by firmware only)

0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

BOR: Brown-out Reset Status bit

1= A Brown-out Reset has not occurred (set by firmware only)

0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.

2: The actual Reset value of POR is determined by the type of device Reset. See the

notes following this register and Section 4.6 “Reset State of Registers” for

additional information.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Note 1: It is recommended that the POR bit be set after a Power-on Reset has been

detected so that subsequent Power-on Resets may be detected.

2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming

that POR was set to ‘1’ by software immediately after Power-on Reset).

DS39689E-page 42

Preliminary

PIC18F4321 FAMILY

FIGURE 4-2:

EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

4.2

Master Clear (MCLR)

The MCLR pin provides a method for triggering an

external Reset of the device. A Reset is generated by

holding the pin low. These devices have a noise filter in

the MCLR Reset path which detects and ignores small

pulses.

VDD

D

The MCLR pin is not driven low by any internal Resets,

including the WDT.

R

R1

MCLR

In PIC18F4321 family devices, the MCLR input can be

disabled with the MCLRE Configuration bit. When

MCLR is disabled, the pin becomes a digital input. See

Section 10.5 “PORTE, TRISE and LATE Registers”

for more information.

PIC18FXXXX

C

Note 1: External Power-on Reset circuit is required

only if the VDD power-up slope is too slow.

The diode D helps discharge the capacitor

quickly when VDD powers down.

4.3

Power-on Reset (POR)

A

Power-on Reset pulse is generated on-chip

2: R < 40 kΩ is recommended to make sure that

the voltage drop across R does not violate

the device’s electrical specification.

whenever VDD rises above a certain threshold. This

allows the device to start in the initialized state when

VDD is adequate for operation.

3: R1 ≥ 1 kΩ will limit any current flowing into

MCLR from external capacitor C, in the event

of MCLR/VPP pin breakdown, due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS).

To take advantage of the POR circuitry, tie the MCLR

pin through a resistor (1 kΩ to 10 kΩ) to VDD. This will

eliminate external RC components usually needed to

create a Power-on Reset delay. A minimum rise rate for

VDD is specified (parameter D004). For a slow rise

time, see Figure 4-2.

When the device starts normal operation (i.e., exits the

Reset condition), device operating parameters

(voltage, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

Power-on Reset events are captured by the POR bit

(RCON<1>). The state of the bit is set to ‘0’ whenever

a POR occurs; it does not change for any other Reset

event. POR is not reset to ‘1’ by any hardware event.

To capture multiple events, the user manually resets

the bit to ‘1’ in software following any POR.

Preliminary

DS39689E-page 43

PIC18F4321 FAMILY

change BOR configuration. It also allows the user to

tailor device power consumption in software by elimi-

nating the incremental current that the BOR consumes.

While the BOR current is typically very small, it may

have some impact in low-power applications.

4.4

Brown-out Reset (BOR)

PIC18F4321 family devices implement a BOR circuit

that provides the user with a number of configuration

and power-saving options. The BOR is controlled by

the BORV1:BORV0 and BOREN1:BOREN0 Configu-

ration bits. There are a total of four BOR configurations

which are summarized in Table 4-1.

Note:

Even when BOR is under software control,

the Brown-out Reset voltage level is still

set by the BORV1:BORV0 Configuration

bits. It cannot be changed in software.

The BOR threshold is set by the BORV1:BORV0 bits. If

BOR is enabled (any values of BOREN1:BOREN0,

except ‘00’), any drop of VDD below VBOR (parameter

D005) for greater than TBOR (parameter 35) will reset

the device. A Reset may or may not occur if VDD falls

below VBOR for less than TBOR. The chip will remain in

Brown-out Reset until VDD rises above VBOR.

4.4.2

DETECTING BOR

When Brown-out Reset is enabled, the BOR bit always

resets to ‘0’ on any Brown-out Reset or Power-on

Reset event. This makes it difficult to determine if a

Brown-out Reset event has occurred just by reading

the state of BOR alone. A more reliable method is to

simultaneously check the state of both POR and BOR.

This assumes that the POR bit is reset to ‘1’ in software

immediately after any Power-on Reset event. If BOR is

‘0’ while POR is ‘1’, it can be reliably assumed that a

Brown-out Reset event has occurred.

If the Power-up Timer is enabled, it will be invoked after

VDD rises above VBOR; it then will keep the chip in

Reset for an additional time delay, TPWRT

(parameter 33). If VDD drops below VBOR while the

Power-up Timer is running, the chip will go back into a

Brown-out Reset and the Power-up Timer will be

initialized. Once VDD rises above VBOR, the Power-up

Timer will execute the additional time delay.

4.4.3

DISABLING BOR IN SLEEP MODE

BOR and the Power-on Timer (PWRT) are

independently configured. Enabling BOR Reset does

not automatically enable the PWRT.

When BOREN1:BOREN0 = 10, the BOR remains

under hardware control and operates as previously

described. Whenever the device enters Sleep mode,

however, the BOR is automatically disabled. When the

device returns to any other operating mode, BOR is

automatically re-enabled.

4.4.1

SOFTWARE ENABLED BOR

When BOREN1:BOREN0 = 01, the BOR can be

enabled or disabled by the user in software. This is

done with the control bit, SBOREN (RCON<6>).

Setting SBOREN enables the BOR to function as

previously described. Clearing SBOREN disables the

BOR entirely. The SBOREN bit operates only in this

mode; otherwise it is read as ‘0’.

This mode allows for applications to recover from

brown-out situations, while actively executing code,

when the device requires BOR protection the most. At

the same time, it saves additional power in Sleep mode

by eliminating the small incremental BOR current.

Placing the BOR under software control gives the user

the additional flexibility of tailoring the application to its

environment without having to reprogram the device to

TABLE 4-1:

BOREN1

BOR CONFIGURATIONS

BOR Configuration

Status of

SBOREN

BOR Operation

BOREN0

(RCON<6>)

0

1

0

1

0

Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits.

Available BOR enabled in software; operation controlled by SBOREN.

Unavailable BOR enabled in hardware in Run and Idle modes, disabled during

Sleep mode.

1

Unavailable BOR enabled in hardware; must be disabled by reprogramming the

Configuration bits.

DS39689E-page 44

Preliminary

PIC18F4321 FAMILY

4.5.3

PLL LOCK TIME-OUT

4.5

Device Reset Timers

With the PLL enabled in HSPLL mode, the time-out

sequence following a Power-on Reset is slightly differ-

ent from other oscillator modes. A separate timer is

used to provide a fixed time-out that is sufficient for the

PLL to lock to the main oscillator frequency. This PLL

lock time-out (TPLL) is typically 2 ms and follows the

oscillator start-up time-out.

PIC18F4321 family devices incorporate three separate

on-chip timers that help regulate the Power-on Reset

process. Their main function is to ensure that the device

clock is stable before code is executed. These timers

are:

• Power-up Timer (PWRT)

• Oscillator Start-up Timer (OST)

• PLL Lock Time-out

4.5.4

TIME-OUT SEQUENCE

On power-up, the time-out sequence is as follows:

4.5.1

POWER-UP TIMER (PWRT)

1. After the POR pulse has cleared, PWRT time-out

is invoked (if enabled).

The Power-up Timer (PWRT) of the PIC18F4321

family devices is an 11-bit counter which uses the

INTRC source as the clock input. This yields an

approximate time interval of 2048 x 32 μs = 65.6 ms.

While the PWRT is counting, the device is held in

Reset.

2. Then, the OST is activated.

The total time-out will vary based on oscillator configu-

ration and the status of the PWRT. Figure 4-3,

Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all

depict time-out sequences on power-up, with the

Power-up Timer enabled and the device operating in

HS Oscillator mode. Figures 4-3 through 4-6 also

apply to devices operating in XT or LP modes. For

devices in RC mode and with the PWRT disabled, there

will be no time-out at all.

The power-up time delay depends on the INTRC clock

and will vary from chip to chip due to temperature and

process variation. See DC parameter 33 for details.

The PWRT is enabled by clearing the PWRTEN

Configuration bit.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, all time-outs will expire. Bring-

ing MCLR high will begin execution immediately

(Figure 4-5). This is useful for testing purposes or to

synchronize more than one PIC18FXXXX device

operating in parallel.

4.5.2

OSCILLATOR START-UP TIMER

(OST)

The Oscillator Start-up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over (parameter 33). This ensures that

the crystal oscillator or resonator has started and

stabilized.

The OST time-out is invoked only for XT, LP, HS and

HSPLL modes and only on Power-on Reset, or on exit

from most power-managed modes.

TABLE 4-2:

Oscillator

TIME-OUT IN VARIOUS SITUATIONS

Power-up⁽²⁾and Brown-out Reset

Exit from

Configuration

Power-Managed Mode

PWRTEN = 0

PWRTEN = 1

HSPLL

66 ms⁽¹⁾+ 1024 TOSC + 2 ms⁽²⁾

66 ms⁽¹⁾+ 1024 TOSC

66 ms⁽¹⁾

1024 TOSC + 2 ms⁽²⁾

HS, XT, LP

EC, ECIO

1024 TOSC

—

RC, RCIO

66 ms⁽¹⁾

INTIO1, INTIO2

Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.

2: 2 ms is the nominal time required for the PLL to lock.

Preliminary

DS39689E-page 45

PIC18F4321 FAMILY

FIGURE 4-3:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

FIGURE 4-4:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

FIGURE 4-5:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

DS39689E-page 46

Preliminary

PIC18F4321 FAMILY

FIGURE 4-6:

SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)

5V

0V

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

TOST

OST TIME-OUT

INTERNAL RESET

FIGURE 4-7:

TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD)

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

TPLL

PLL TIME-OUT

INTERNAL RESET

Note:

TOST = 1024 clock cycles.

TPLL ≈ 2 ms max. First three stages of the PWRT timer.

Preliminary

DS39689E-page 47

PIC18F4321 FAMILY

Table 4-4 describes the Reset states for all of the

Special Function Registers. These are categorized by

Power-on and Brown-out Resets, Master Clear and

WDT Resets and WDT wake-ups.

4.6

Reset State of Registers

Most registers are unaffected by a Reset. Their status

is unknown on POR and unchanged by all other

Resets. The other registers are forced to a “Reset

state” depending on the type of Reset that occurred.

Most registers are not affected by a WDT wake-up,

since this is viewed as the resumption of normal oper-

ation. Status bits from the RCON register, RI, TO, PD,

POR and BOR, are set or cleared differently in different

Reset situations, as indicated in Table 4-3. These bits

are used in software to determine the nature of the

Reset.

TABLE 4-3:

STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION

FOR RCON REGISTER

RCON Register

STKPTR Register

Program

Counter

Condition

RI

TO

PD POR BOR STKFUL STKUNF

Power-on Reset

RESETInstruction

Brown-out

0000h

1

0

1

u

1

u

1

u

1

u

0

u

0

u

0

u

0

u

0

u

MCLR during power-managed Run modes

MCLR during power-managed Idle modes

and Sleep mode

WDT Time-out during full power or

power-managed Run mode

0000h

u

0

u

MCLR during full power execution

Stack Full Reset (STVREN = 1)

Stack Underflow Reset (STVREN = 1)

0000h

u

1

u

1

Stack Underflow Error (not an actual Reset,

STVREN = 0)

WDT time-out during power-managed Idle or

Sleep modes

PC + 2

u

0

u

0

u

Interrupt exit from power-managed modes

PC + 2⁽¹⁾

Legend: u= unchanged

Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the

interrupt vector (008h or 0018h).

2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled

(BOREN1:BOREN0 Configuration bits = 01and SBOREN = 1); otherwise, the Reset state is ‘0’.

DS39689E-page 48

Preliminary

PIC18F4321 FAMILY

TABLE 4-4:

INITIALIZATION CONDITIONS FOR ALL REGISTERS

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Register

Applicable Devices

TOSU

2221 2321 4221 4321

---0 0000

0000 0000

00-0 0000

--00 0000

0000 0000

--00 0000

0000 0000

xxxx xxxx

0000 000x

1111 -1-1

11-0 0-00

N/A

---0 0000

0000 0000

uu-0 0000

--00 0000

0000 0000

--00 0000

0000 0000

uuuu uuuu

0000 000u

1111 -1-1

11-0 0-00

N/A

---0 uuuu⁽³⁾

uuuu uuuu⁽³⁾

uu-u uuuu⁽³⁾

--uu uuuu

uuuu uuuu

PC + 2⁽²⁾

--uu uuuu

uuuu uuuu

uuuu uuuu⁽¹⁾

uuuu -u-u⁽¹⁾

uu-u u-uu⁽¹⁾

N/A

TOSH

TOSL

STKPTR

PCLATU

PCLATH

PCL

TBLPTRU

TBLPTRH

TBLPTRL

TABLAT

PRODH

PRODL

INTCON

INTCON2

INTCON3

INDF0

POSTINC0

POSTDEC0

PREINC0

PLUSW0

FSR0H

N/A

---- 0000

xxxx xxxx

N/A

---- 0000

uuuu uuuu

N/A

---- uuuu

uuuu uuuu

N/A

FSR0L

WREG

INDF1

POSTINC1

POSTDEC1

PREINC1

PLUSW1

N/A

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

Preliminary

DS39689E-page 49

PIC18F4321 FAMILY

TABLE 4-4:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Register

Applicable Devices

FSR1H

2221 2321 4221 4321

---- 0000

xxxx xxxx

---- 0000

N/A

---- 0000

uuuu uuuu

---- 0000

N/A

---- uuuu

uuuu uuuu

---- uuuu

N/A

FSR1L

BSR

INDF2

POSTINC2

POSTDEC2

PREINC2

PLUSW2

FSR2H

N/A

---- 0000

xxxx xxxx

---x xxxx

0000 0000

xxxx xxxx

1111 1111

0100 q000

0-00 0101

---- ---0

0q-1 11q0

xxxx xxxx

0000 0000

1111 1111

-000 0000

xxxx xxxx

0000 0000

---- 0000

uuuu uuuu

---u uuuu

0000 0000

uuuu uuuu

1111 1111

0100 q000

0-00 0101

---- ---0

0q-q qquu

uuuu uuuu

u0uu uuuu

0000 0000

1111 1111

-000 0000

uuuu uuuu

0000 0000

---- uuuu

uuuu uuuu

---u uuuu

uuuu uuuu

uuuu uuqu

u-uu uuuu

---- ---u

uq-u qquu

uuuu uuuu

1111 1111

-uuu uuuu

uuuu uuuu

FSR2L

STATUS

TMR0H

TMR0L

T0CON

OSCCON

HLVDCON

WDTCON

RCON⁽⁴⁾

TMR1H

TMR1L

T1CON

TMR2

PR2

T2CON

SSPBUF

SSPADD

SSPSTAT

SSPCON1

SSPCON2

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

DS39689E-page 50

Preliminary

PIC18F4321 FAMILY

TABLE 4-4:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Register

Applicable Devices

ADRESH

ADRESL

ADCON0

ADCON1

ADCON2

CCPR1H

CCPR1L

CCP1CON

2221 2321 4221 4321

xxxx xxxx

--00 0000

--00 0qqq

0-00 0000

xxxx xxxx

0000 0000

--00 0000

xxxx xxxx

--00 0000

0100 0-00

0000 0000

0000 00--

0000 0000

0000 0111

xxxx xxxx

0000 0000

0000 0010

0000 000x

0000 0000

xx-0 x000

uuuu uuuu

--00 0000

--00 0qqq

0-00 0000

uuuu uuuu

0000 0000

--00 0000

uuuu uuuu

--00 0000

0100 0-00

0000 0000

0000 00--

0000 0000

0000 0111

uuuu uuuu

0000 0000

0000 0010

0000 000x

0000 0000

uu-0 u000

uuuu uuuu

--uu uuuu

u-uu uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

uuuu uu--

uuuu uuuu

0000 0000

uu-0 u000

CCPR2H

CCPR2L

CCP2CON

BAUDCON

ECCP1DEL

ECCP1AS

CVRCON

CMCON

TMR3H

TMR3L

T3CON

SPBRGH

SPBRG

RCREG

TXREG

TXSTA

RCSTA

EEADR

EEDATA

EECON2

EECON1

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

Preliminary

DS39689E-page 51

PIC18F4321 FAMILY

TABLE 4-4:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets,

WDT Reset,

RESET Instruction,

Stack Resets

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Register

Applicable Devices

IPR2

PIR2

PIE2

IPR1

2221 2321 4221 4321

11-1 1111

00-0 0000

1111 1111

-111 1111

0000 0000

-000 0000

0000 0000

-000 0000

00-0 0000

0000 -111

1111 1111

1111 1111⁽⁵⁾

---- -xxx

xxxx xxxx

xxxx xxxx⁽⁵⁾

---- xxxx

---- x---

xxxx xxxx

xx0x 0000⁽⁵⁾

11-1 1111

00-0 0000

1111 1111

-111 1111

0000 0000

-000 0000

0000 0000

-000 0000

00-0 0000

0000 -111

1111 1111

1111 1111⁽⁵⁾

---- -uuu

uuuu uuuu

uuuu uuuu⁽⁵⁾

---- uuuu

---- u---

uuuu uuuu

uu0u 0000⁽⁵⁾

uu-u uuuu

uu-u uuuu⁽¹⁾

uu-u uuuu

uuuu uuuu

-uuu uuuu

uuuu uuuu⁽¹⁾

-uuu uuuu⁽¹⁾

uuuu uuuu

-uuu uuuu

uu-u uuuu

uuuu -uuu

uuuu uuuu

uuuu uuuu⁽⁵⁾

---- -uuu

uuuu uuuu

uuuu uuuu⁽⁵⁾

---- uuuu

---- u---

uuuu uuuu

uuuu uuuu⁽⁵⁾

PIR1

PIE1

OSCTUNE

TRISE

TRISD

TRISC

TRISB

TRISA⁽⁵⁾

LATE

LATD

LATC

LATB

LATA⁽⁵⁾

PORTE

PORTD

PORTC

PORTB

PORTA⁽⁵⁾

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 4-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

DS39689E-page 52

Preliminary

PIC18F4321 FAMILY

5.1

Program Memory Organization

5.0

MEMORY ORGANIZATION

PIC18 microcontrollers implement a 21-bit program

counter, which is capable of addressing a 2-Mbyte

program memory space. Accessing a location between

the upper boundary of the physically implemented

memory and the 2-Mbyte address will return all ‘0’s (a

NOPinstruction).

There are three types of memory in PIC18 Enhanced

microcontroller devices:

• Program Memory

• Data RAM

• Data EEPROM

As Harvard architecture devices, the data and program

memories use separate busses; this allows for con-

current access of the two memory spaces. The data

EEPROM, for practical purposes, can be regarded as

a peripheral device, since it is addressed and accessed

through a set of control registers.

The PIC18F2221 and PIC18F4221 each have 4 Kbytes

of Flash memory and can store up to 2048 single-word

instructions. The PIC18F2321 and PIC18F4321 each

have 8 Kbytes of Flash memory and can store up to

4096 single-word instructions.

PIC18 devices have two interrupt vectors. The Reset

vector address is at 0000h and the interrupt vector

addresses are at 0008h and 0018h.

Additional detailed information on the operation of the

Flash program memory is provided in Section 6.0

“Flash Program Memory”. Data EEPROM is

discussed separately in Section 7.0 “Data EEPROM

Memory”.

The program memory maps for PIC18F2221/4221 and

PIC18F2321/4321 devices are shown in Figure 5-1.

FIGURE 5-1:

PROGRAM MEMORY MAP AND STACK FOR PIC18F4321 FAMILY DEVICES

PIC18FX221

PIC18FX321

PC<20:0>

21

CALL,RCALL,RETURN

RETFIE,RETLW

CALL,RCALL,RETURN

RETFIE,RETLW

Stack Level 1

•

Stack Level 31

Reset Vector

Stack Level 31

Reset Vector

0000h

High Priority Interrupt Vector

Low Priority Interrupt Vector

0008h

0018h

High Priority Interrupt Vector

Low Priority Interrupt Vector

0008h

0018h

On-Chip

Program Memory

On-Chip

Program Memory

0FFFh

1000h

1FFFh

2000h

Read ‘0’

1FFFFFh

200000h

1FFFFFh

200000h

Preliminary

DS39689E-page 53

PIC18F4321 FAMILY

The stack operates as a 31-word by 21-bit RAM and a

5-bit Stack Pointer, STKPTR. The stack space is not

part of either program or data space. The Stack Pointer

is readable and writable and the address on the top of

the stack is readable and writable through the Top-of-

Stack Special Function Registers. Data can also be

pushed to, or popped from the stack, using these

registers.

5.1.1

PROGRAM COUNTER

The Program Counter (PC) specifies the address of the

instruction to fetch for execution. The PC is 21 bits wide

and is contained in three separate 8-bit registers. The

low byte, known as the PCL register, is both readable

and writable. The high byte, or PCH register, contains

the PC<15:8> bits; it is not directly readable or writable.

Updates to the PCH register are performed through the

PCLATH register. The upper byte is called PCU. This

register contains the PC<20:16> bits; it is also not

directly readable or writable. Updates to the PCU

register are performed through the PCLATU register.

A CALLtype instruction causes a push onto the stack;

the Stack Pointer is first incremented and the location

pointed to by the Stack Pointer is written with the

contents of the PC (already pointing to the instruction

following the CALL). A RETURNtype instruction causes

a pop from the stack; the contents of the location

pointed to by the STKPTR are transferred to the PC

and then the Stack Pointer is decremented.

The contents of PCLATH and PCLATU are transferred

to the program counter by any operation that writes

PCL. Similarly, the upper two bytes of the program

counter are transferred to PCLATH and PCLATU by an

operation that reads PCL. This is useful for computed

offsets to the PC (see Section 5.1.4.1 “Computed

GOTO”).

The Stack Pointer is initialized to ‘00000’ after all

Resets. There is no RAM associated with the location

corresponding to a Stack Pointer value of ‘00000’; this

is only a Reset value. Status bits indicate if the stack is

full or has overflowed or has underflowed.

The PC addresses bytes in the program memory. To

prevent the PC from becoming misaligned with word

instructions, the Least Significant bit of PCL is fixed to

a value of ‘0’. The PC increments by 2 to address

sequential instructions in the program memory.

5.1.2.1

Only the top of the return address stack (TOS) is

readable and writable. set of three registers,

Top-of-Stack Access

A

The CALL, RCALL, GOTO and program branch

instructions write to the program counter directly. For

these instructions, the contents of PCLATH and

PCLATU are not transferred to the program counter.

TOSU:TOSH:TOSL, hold the contents of the stack

location pointed to by the STKPTR register (Figure 5-2).

This allows users to implement a software stack if

necessary. After a CALL, RCALL or interrupt, the

software can read the pushed value by reading the

TOSU:TOSH:TOSL registers. These values can be

placed on a user-defined software stack. At return time,

the software can return these values to

TOSU:TOSH:TOSL and do a return.

5.1.2

RETURN ADDRESS STACK

The return address stack allows any combination of up

to 31 program calls and interrupts to occur. The PC is

pushed onto the stack when a CALLor RCALLinstruc-

tion is executed or an interrupt is Acknowledged. The

PC value is pulled off the stack on a RETURN, RETLW

or a RETFIEinstruction. PCLATU and PCLATH are not

affected by any of the RETURNor CALLinstructions.

The user must disable the global interrupt enable bits

while accessing the stack to prevent inadvertent stack

corruption.

FIGURE 5-2:

RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

Return Address Stack <20:0>

11111

11110

11101

Top-of-Stack Registers

Stack Pointer

STKPTR<4:0>

TOSU

00h

TOSH

1Ah

TOSL

34h

00010

00011

00010

00001

00000

001A34h

000D58h

Top-of-Stack

DS39689E-page 54

Preliminary

PIC18F4321 FAMILY

When the stack has been popped enough times to

unload the stack, the next pop will return a value of zero

to the PC and sets the STKUNF bit, while the Stack

Pointer remains at zero. The STKUNF bit will remain

set until cleared by software or until a POR occurs.

5.1.2.2

Return Stack Pointer (STKPTR)

The STKPTR register (Register 5-1) contains the Stack

Pointer value, the STKFUL (Stack Full) status bit and

the STKUNF (Stack Underflow) status bits. The value

of the Stack Pointer can be 0 through 31. The Stack

Pointer increments before values are pushed onto the

stack and decrements after values are popped off the

stack. On Reset, the Stack Pointer value will be zero.

The user may read and write the Stack Pointer value.

This feature can be used by a Real-Time Operating

System (RTOS) for return stack maintenance.

Note:

Returning a value of zero to the PC on an

underflow has the effect of vectoring the

program to the Reset vector, where the

stack conditions can be verified and

appropriate actions can be taken. This is

not the same as a Reset, as the contents

of the SFRs are not affected.

After the PC is pushed onto the stack 31 times (without

popping any values off the stack), the STKFUL bit is

set. The STKFUL bit is cleared by software or by a

POR.

5.1.2.3

PUSHand POPInstructions

Since the Top-of-Stack is readable and writable, the

ability to push values onto the stack and pull values off

the stack without disturbing normal program execution

is a desirable feature. The PIC18 instruction set

includes two instructions, PUSH and POP, that permit

the TOS to be manipulated under software control.

TOSU, TOSH and TOSL can be modified to place data

or a return address on the stack.

The action that takes place when the stack becomes

full depends on the state of the STVREN (Stack

Overflow Reset Enable) Configuration bit. (Refer to

Section 23.1 “Configuration Bits” for a description of

the device Configuration bits.) If STVREN is set

(default), the 31st push will push the (PC + 2) value

onto the stack, set the STKFUL bit and reset the

device. The STKFUL bit will remain set and the Stack

Pointer will be set to zero.

The PUSHinstruction places the current PC value onto

the stack. This increments the Stack Pointer and loads

the current PC value onto the stack.

If STVREN is cleared, the STKFUL bit will be set on the

31st push and the Stack Pointer will increment to 31.

Any additional pushes will not overwrite the 31st push

and STKPTR will remain at 31.

The POPinstruction discards the current TOS by decre-

menting the Stack Pointer. The previous value pushed

onto the stack then becomes the TOS value.

REGISTER 5-1:

STKPTR: STACK POINTER REGISTER

R/C-0

U-0

—

R/W-0

SP4

R/W-0

SP3

R/W-0

SP2

R/W-0

SP1

R/W-0

SP0

STKFUL⁽¹⁾STKUNF⁽¹⁾

bit 7

bit 0

bit 7

bit 6

STKFUL: Stack Full Flag bit⁽¹⁾

1= Stack became full or overflowed

0= Stack has not become full or overflowed

STKUNF: Stack Underflow Flag bit⁽¹⁾

1= Stack underflow occurred

0= Stack underflow did not occur

bit 5

Unimplemented: Read as ‘0’

bit 4-0

SP4:SP0: Stack Pointer Location bits

Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented

‘0’ = Bit is cleared

C = Clearable only bit

x = Bit is unknown

Preliminary

DS39689E-page 55

PIC18F4321 FAMILY

5.1.2.4

Stack Full and Underflow Resets

5.1.4

LOOK-UP TABLES IN PROGRAM

MEMORY

Device Resets on stack overflow and stack underflow

conditions are enabled by setting the STVREN bit in

Configuration Register 4L. When STVREN is set, a full

or underflow will set the appropriate STKFUL or

STKUNF bit and then cause a device Reset. When

STVREN is cleared, a full or underflow condition will set

the appropriate STKFUL or STKUNF bit but not cause

a device Reset. The STKFUL or STKUNF bits are

cleared by the user software or a Power-on Reset.

There may be programming situations that require the

creation of data structures, or look-up tables, in

program memory. For PIC18 devices, look-up tables

can be implemented in two ways:

• Computed GOTO

• Table Reads

5.1.4.1

Computed GOTO

5.1.3

FAST REGISTER STACK

A computed GOTOis accomplished by adding an offset

to the program counter. An example is shown in

Example 5-2.

A Fast Register Stack is provided for the STATUS,

WREG and BSR registers, to provide a “fast return”

option for interrupts. The stack for each register is only

one level deep and is neither readable nor writable. It is

loaded with the current value of the corresponding

register when the processor vectors for an interrupt. All

interrupt sources will push values into the stack regis-

ters. The values in the registers are then loaded back

into their associated registers if the RETFIE, FAST

instruction is used to return from the interrupt.

A look-up table can be formed with an ADDWF PCL

instruction and a group of RETLW nninstructions. The

W register is loaded with an offset into the table before

executing a call to that table. The first instruction of the

called routine is the ADDWF PCLinstruction. The next

instruction executed will be one of the RETLW nn

instructions that returns the value ‘nn’ to the calling

function.

If both low and high priority interrupts are enabled, the

stack registers cannot be used reliably to return from

low priority interrupts. If a high priority interrupt occurs

while servicing a low priority interrupt, the stack register

values stored by the low priority interrupt will be

overwritten. In these cases, users must save the key

registers in software during a low priority interrupt.

The offset value (in WREG) specifies the number of

bytes that the program counter should advance and

should be multiples of 2 (LSb = 0).

In this method, only one data byte may be stored in

each instruction location and room on the return

address stack is required.

If interrupt priority is not used, all interrupts may use the

Fast Register Stack for returns from interrupt. If no

interrupts are used, the Fast Register Stack can be

used to restore the STATUS, WREG and BSR registers

at the end of a subroutine call. To use the Fast Register

Stack for a subroutine call, a CALL label, FAST

instruction must be executed to save the STATUS,

WREG and BSR registers to the Fast Register Stack. A

RETURN, FASTinstruction is then executed to restore

these registers from the Fast Register Stack.

EXAMPLE 5-2:

COMPUTED GOTO USING

AN OFFSET VALUE

OFFSET, W

TABLE

MOVF

CALL

ORG

TABLE

nn00h

ADDWF

RETLW

.

PCL

nnh

.

Example 5-1 shows a source code example that uses

the Fast Register Stack during a subroutine call and

return.

.

5.1.4.2

Table Reads and Table Writes

A better method of storing data in program memory

allows two bytes of data to be stored in each instruction

location.

EXAMPLE 5-1:

FAST REGISTER STACK

CODE EXAMPLE

CALL SUB1, FAST

;STATUS, WREG, BSR

;SAVED IN FAST REGISTER

;STACK

Look-up table data may be stored two bytes per

program word by using table reads and writes. The

Table Pointer (TBLPTR) register specifies the byte

address and the Table Latch (TABLAT) register

contains the data that is read from or written to program

memory. Data is transferred to or from program

memory one byte at a time.

•

SUB1

•

RETURN, FAST ;RESTORE VALUES SAVED

;IN FAST REGISTER STACK

Table read and table write operations are discussed

further in Section 6.1 “Table Reads and Table

Writes”.

DS39689E-page 56

Preliminary

PIC18F4321 FAMILY

5.2.2

INSTRUCTION FLOW/PIPELINING

5.2

PIC18 Instruction Cycle

An “Instruction Cycle” consists of four Q cycles: Q1

through Q4. The instruction fetch and execute are

pipelined in such a manner that a fetch takes one

instruction cycle, while the decode and execute take

another instruction cycle. However, due to the pipe-

lining, each instruction effectively executes in one

cycle. If an instruction causes the program counter to

change (e.g., GOTO), then two cycles are required to

complete the instruction (Example 5-3).

5.2.1

CLOCKING SCHEME

The microcontroller clock input, whether from an

internal or external source, is internally divided by four

to generate four non-overlapping quadrature clocks

(Q1, Q2, Q3 and Q4). Internally, the program counter is

incremented on every Q1; the instruction is fetched

from the program memory and latched into the

Instruction Register (IR) during Q4. The instruction is

decoded and executed during the following Q1 through

Q4. The clocks and instruction execution flow are

shown in Figure 5-3.

A fetch cycle begins with the Program Counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the Instruction Register (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3 and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 5-3:

CLOCK/INSTRUCTION CYCLE

Q2

Q3

Q4

Q2

Q3

Q4

Q2

Q3

Q4

Q1

OSC1

Q1

Q2

Q3

Q4

Internal

Phase

Clock

PC

PC + 2

PC + 4

OSC2/CLKO

(RC mode)

Execute INST (PC – 2)

Fetch INST (PC)

Execute INST (PC)

Fetch INST (PC + 2)

Execute INST (PC + 2)

Fetch INST (PC + 4)

EXAMPLE 5-3:

INSTRUCTION PIPELINE FLOW

TCY0

TCY1

TCY2

TCY3

TCY4

TCY5

1. MOVLW 55h

2. MOVWF PORTB

3. BRA SUB_1

Fetch 1

Execute 1

Fetch 2

Execute 2

Fetch 3

Execute 3

Fetch 4

4. BSF

PORTA, BIT3 (Forced NOP)

Flush (NOP)

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction

is “flushed” from the pipeline while the new instruction is being fetched and then executed.

Preliminary

DS39689E-page 57

PIC18F4321 FAMILY

The CALL and GOTO instructions have the absolute

program memory address embedded into the instruc-

tion. Since instructions are always stored on word

boundaries, the data contained in the instruction is a

word address. The word address is written to PC<20:1>,

which accesses the desired byte address in program

memory. Instruction #2 in Figure 5-4 shows how the

instruction GOTO 0006h is encoded in the program

memory. Program branch instructions, which encode a

relative address offset, operate in the same manner. The

offset value stored in a branch instruction represents the

number of single-word instructions that the PC will be

offset by. Section 24.0 “Instruction Set Summary”

provides further details of the instruction set.

5.2.3

INSTRUCTIONS IN PROGRAM

MEMORY

The program memory is addressed in bytes. Instruc-

tions are stored as two bytes or four bytes in program

memory. The Least Significant Byte of an instruction

word is always stored in a program memory location

with an even address (LSb = 0). To maintain alignment

with instruction boundaries, the PC increments in steps

of 2 and the LSb will always read ‘0’ (see Section 5.1.1

“Program Counter”).

Figure 5-4 shows an example of how instruction words

are stored in the program memory.

FIGURE 5-4:

INSTRUCTIONS IN PROGRAM MEMORY

Word Address

LSB = 1

LSB = 0

↓

Program Memory

^{Byte Locations}→

000000h

000002h

000004h

000006h

000008h

00000Ah

00000Ch

00000Eh

000010h

000012h

000014h

Instruction 1:

Instruction 2:

MOVLW

GOTO

055h

0006h

0Fh

EFh

F0h

C1h

F4h

55h

03h

00h

23h

56h

Instruction 3:

MOVFF

123h, 456h

the instruction sequence. If the first word is skipped for

some reason and the second word is executed by itself,

a NOPis executed instead. This is necessary for cases

when the two-word instruction is preceded by a condi-

tional instruction that changes the PC. Example 5-4

shows how this works.

5.2.4

TWO-WORD INSTRUCTIONS

The standard PIC18 instruction set has four two-word

instructions: CALL, MOVFF, GOTO and LSFR. In all

cases, the second word of the instructions always has

‘1111’ as its four Most Significant bits; the other 12 bits

are literal data, usually a data memory address.

Note:

See Section 5.6 “PIC18 Instruction

Execution and the Extended Instruc-

tion Set” for information on two-word

instructions in the extended instruction set.

The use of ‘1111’ in the 4 MSbs of an instruction spec-

ifies a special form of NOP. If the instruction is executed

in proper sequence – immediately after the first word –

the data in the second word is accessed and used by

EXAMPLE 5-4:

CASE 1:

TWO-WORD INSTRUCTIONS

Source Code

Object Code

0110 0110 0000 0000 TSTFSZ

REG1

REG1, REG2 ; No, skip this word

; Execute this word as a NOP

; continue code

; is RAM location 0?

1100 0001 0010 0011

1111 0100 0101 0110

0010 0100 0000 0000

CASE 2:

MOVFF

ADDWF

REG3

Object Code

Source Code

0110 0110 0000 0000

1100 0001 0010 0011

1111 0100 0101 0110

0010 0100 0000 0000

TSTFSZ

MOVFF

REG1

; is RAM location 0?

REG1, REG2 ; Yes, execute this word

; 2nd word of instruction

ADDWF

REG3

; continue code

DS39689E-page 58

Preliminary

PIC18F4321 FAMILY

5.3.1

BANK SELECT REGISTER (BSR)

5.3

Data Memory Organization

Large areas of data memory require an efficient

addressing scheme to make rapid access to any

address possible. Ideally, this means that an entire

address does not need to be provided for each read or

write operation. For PIC18 devices, this is accom-

plished with a RAM banking scheme. This divides the

memory space into 16 contiguous banks of 256 bytes.

Depending on the instruction, each location can be

addressed directly by its full 12-bit address, or an 8-bit

low-order address and a 4-bit Bank Pointer.

Note:

The operation of some aspects of data

memory are changed when the PIC18

extended instruction set is enabled. See

Section 5.5 “Data Memory and the

Extended Instruction Set” for more

information.

The data memory in PIC18 devices is implemented as

static RAM. Each register in the data memory has a

12-bit address, allowing up to 4096 bytes of data

memory. The memory space is divided into as many as

16 banks that contain 256 bytes each; PIC18F4321

family devices implement 2 banks. Figure 5-5 shows

the data memory organization for the PIC18F4321

family devices.

Most instructions in the PIC18 instruction set make use

of the Bank Pointer, known as the Bank Select Register

(BSR). This SFR holds the four Most Significant bits of

a location’s address; the instruction itself includes the

8 Least Significant bits. Only the four lower bits of the

BSR are implemented (BSR3:BSR0). The upper four

bits are unused; they will always read ‘0’ and cannot be

written to. The BSR can be loaded directly by using the

MOVLBinstruction.

The data memory contains Special Function Registers

(SFRs) and General Purpose Registers (GPRs). The

SFRs are used for control and status of the controller

and peripheral functions, while GPRs are used for data

storage and scratchpad operations in the user’s

application. Any read of an unimplemented location will

read as ‘0’s.

The value of the BSR indicates the bank in data

memory; the 8 bits in the instruction show the location

in the bank and can be thought of as an offset from the

bank’s lower boundary. The relationship between the

BSR’s value and the bank division in data memory is

shown in Figure 5-6.

The instruction set and architecture allow operations

across all banks. The entire data memory may be

accessed by Direct, Indirect or Indexed Addressing

modes. Addressing modes are discussed later in this

subsection.

Since up to 16 registers may share the same low-order

address, the user must always be careful to ensure that

the proper bank is selected before performing a data

read or write. For example, writing what should be

program data to an 8-bit address of F9h, while the BSR

is 0Fh, will end up resetting the program counter.

To ensure that commonly used registers (SFRs and

select GPRs) can be accessed in a single cycle, PIC18

devices implement an Access Bank. This is a 256-byte

memory space that provides fast access to SFRs and

the lower portion of GPR Bank 0 without using the

While any bank can be selected, only those banks that

are actually implemented can be read or written to.

Writes to unimplemented banks are ignored, while

reads from unimplemented banks will return ‘0’s. Even

so, the STATUS register will still be affected as if the

operation was successful. The data memory map in

Figure 5-5 indicates which banks are implemented.

BSR. Section 5.3.2 “Access Bank” provides

detailed description of the Access RAM.

a

In the core PIC18 instruction set, only the MOVFF

instruction fully specifies the 12-bit address of the

source and target registers. This instruction ignores the

BSR completely when it executes. All other instructions

include only the low-order address as an operand and

must use either the BSR or the Access Bank to locate

their target registers.

Preliminary

DS39689E-page 59

PIC18F4321 FAMILY

FIGURE 5-5:

DATA MEMORY MAP FOR PIC18F4321 FAMILY DEVICES

When a = 0,

The BSR is ignored and the

Access Bank is used.

The first 128 bytes are

General Purpose RAM

(from Bank 0).

BSR<3:0>

Data Memory Map

The second 128 bytes are

Special Function Registers

(from Bank 15).

000h

07Fh

080h

0FFh

00h

FFh

Access RAM

GPR

= 0000

= 0001

Bank 0

Bank 1

When a = 1,

100h

GPR

The BSR specifies the Bank

used by the instruction.

1FFh

Access Bank

00h

Access RAM Low

7Fh

80h

= 0010

= 1110

Bank 2

to

Bank 14

Access RAM High

(SFRs)

Unused

Read ‘00h’

FFh

EFFh

F00h

F7Fh

F80h

FFFh

00h

FFh

Unused

SFR

= 1111

Bank 15

DS39689E-page 60

Preliminary

PIC18F4321 FAMILY

FIGURE 5-6:

USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)

(2)

(1)

From Opcode

BSR

7

0

7

0

Memory

Data

1

0

1

000h

100h

200h

00h

Bank 0

(2)

FFh

00h

Bank Select

Bank 1

FFh

00h

Bank 2

through

Bank 14

F00h

FFFh

00h

FFh

Bank 15

Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to

the registers of the Access Bank.

2: The MOVFF instruction embeds the entire 12-bit address in the instruction.

however, the instruction is forced to use the Access

Bank address map; the current value of the BSR is

ignored entirely.

5.3.2

ACCESS BANK

While the use of the BSR with an embedded 8-bit

address allows users to address the entire range of

data memory, it also means that the user must always

ensure that the correct bank is selected. Otherwise,

data may be read from or written to the wrong location.

This can be disastrous if a GPR is the intended target

of an operation, but an SFR is written to instead.

Verifying and/or changing the BSR for each read or

write to data memory can become very inefficient.

Using this “forced” addressing allows the instruction to

operate on a data address in a single cycle, without

updating the BSR first. For 8-bit addresses of 80h and

above, this means that users can evaluate and operate

on SFRs more efficiently. The Access RAM below 80h

is a good place for data values that the user might need

to access rapidly, such as immediate computational

results or common program variables. Access RAM

also allows for faster and more code efficient context

saving and switching of variables.

To streamline access for the most commonly used data

memory locations, the data memory is configured with

an Access Bank, which allows users to access a

mapped block of memory without specifying a BSR.

The Access Bank consists of the first 128 bytes of

memory (00h-7Fh) in Bank 0 and the last 128 bytes of

memory (80h-FFh) in Block 15. The lower half is known

as the “Access RAM” and is composed of GPRs. This

upper half is also where the device’s SFRs are

mapped. These two areas are mapped contiguously in

the Access Bank and can be addressed in a linear

fashion by an 8-bit address (Figure 5-5).

The mapping of the Access Bank is slightly different

when the extended instruction set is enabled (XINST

Configuration bit = 1). This is discussed in more detail

in Section 5.5.3 “Mapping the Access Bank in

Indexed Literal Offset Addressing Mode”.

5.3.3

GENERAL PURPOSE

REGISTER FILE

PIC18 devices may have banked memory in the GPR

area. This is data RAM which is available for use by all

instructions. GPRs start at the bottom of Bank 0

(address 000h) and grow upwards towards the bottom of

the SFR area. GPRs are not initialized by a Power-on

Reset and are unchanged on all other Resets.

The Access Bank is used by core PIC18 instructions

that include the Access RAM bit (the ‘a’ parameter in

the instruction). When ‘a’ is equal to ‘1’, the instruction

uses the BSR and the 8-bit address included in the

opcode for the data memory address. When ‘a’ is ‘0’,

Preliminary

DS39689E-page 61

PIC18F4321 FAMILY

The SFRs can be classified into two sets: those associ-

ated with the “core” device functionality (ALU, Resets

and interrupts) and those related to the peripheral

functions. The reset and interrupt registers are

described in their respective chapters, while the ALU’s

STATUS register is described later in this section.

Registers related to the operation of a peripheral feature

are described in the chapter for that peripheral.

5.3.4

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral modules for controlling

the desired operation of the device. These registers are

implemented as static RAM. SFRs start at the top of

data memory (FFFh) and extend downward to occupy

the top half of Bank 15 (F80h to FFFh). A list of these

registers is given in Table 5-1 and Table 5-2.

The SFRs are typically distributed among the

peripherals whose functions they control. Unused SFR

locations are unimplemented and read as ‘0’s.

TABLE 5-1:

Address

SPECIAL FUNCTION REGISTER MAP FOR PIC18F4321 FAMILY DEVICES

Name

Address

Name

Address

FBFh

FBEh

Name

Address

F9Fh

Name

FFFh

FFEh

FFDh

FFCh

FFBh

FFAh

FF9h

FF8h

FF7h

FF6h

FF5h

FF4h

FF3h

FF2h

FF1h

FF0h

FEFh

TOSU

TOSH

FDFh

INDF2⁽¹⁾

CCPR1H

CCPR1L

IPR1

PIR1

PIE1

FDEh POSTINC2⁽¹⁾

FDDh POSTDEC2⁽¹⁾

FDCh PREINC2⁽¹⁾

FDBh PLUSW2⁽¹⁾

F9Eh

F9Dh

F9Ch

TOSL

FBDh CCP1CON

(2)

STKPTR

PCLATU

PCLATH

PCL

FBCh

FBBh

CCPR2H

CCPR2L

—

F9Bh OSCTUNE

(2)

FDAh

FD9h

FD8h

FD7h

FD6h

FD5h

FD4h

FD3h

FSR2H

FSR2L

FBAh CCP2CON

F9Ah

F99h

F98h

F97h

F96h

F95h

F94h

F93h

F92h

F91h

F90h

F8Fh

F8Eh

F8Dh

F8Ch

F8Bh

F8Ah

F89h

F88h

F87h

F86h

F85h

F84h

F83h

F82h

F81h

F80h

—

(2)

FB9h

—

TBLPTRU

TBLPTRH

TBLPTRL

TABLAT

PRODH

PRODL

INTCON

INTCON2

INTCON3

INDF0⁽¹⁾

STATUS

TMR0H

TMR0L

T0CON

FB8h BAUDCON

FB7h ECCP1DEL⁽³⁾

FB6h ECCP1AS⁽³⁾

TRISE⁽³⁾

TRISD⁽³⁾

TRISC

FB5h

FB4h

FB3h

FB2h

FB1h

FB0h

FAFh

FAEh

FADh

FACh

FABh

FAAh

FA9h

FA8h

CVRCON

CMCON

TMR3H

TMR3L

T3CON

SPBRGH

SPBRG

RCREG

TXREG

TXSTA

(2)

—

OSCCON

TRISB

FD2h HLVDCON

TRISA

(2)

FD1h

FD0h

FCFh

FCEh

FCDh

FCCh

FCBh

FCAh

FC9h

FC8h

FC7h

FC6h

FC5h

FC4h

FC3h

FC2h

FC1h

FC0h

WDTCON

RCON

—

(2)

—

(2)

TMR1H

—

FEEh POSTINC0⁽¹⁾

FEDh POSTDEC0⁽¹⁾

FECh PREINC0⁽¹⁾

FEBh PLUSW0⁽¹⁾

TMR1L

—

(2)

T1CON

LATE⁽³⁾

LATD⁽³⁾

LATC

TMR2

PR2

RCSTA

(2)

FEAh

FE9h

FE8h

FE7h

FE6h POSTINC1⁽¹⁾

FE5h POSTDEC1⁽¹⁾

FE4h PREINC1⁽¹⁾

FE3h PLUSW1⁽¹⁾

FSR0H

FSR0L

WREG

INDF1⁽¹⁾

T2CON

—

LATB

SSPBUF

SSPADD

SSPSTAT

SSPCON1

SSPCON2

ADRESH

ADRESL

ADCON0

ADCON1

ADCON2

EEADR

LATA

(2)

EEDATA

—

FA7h EECON2⁽¹⁾

—

(2)

FA6h

FA5h

FA4h

FA3h

FA2h

FA1h

FA0h

EECON1

—

(2)

—

(2)

—

PORTE⁽³⁾

PORTD⁽³⁾

PORTC

PORTB

(2)

—

FE2h

FE1h

FE0h

FSR1H

FSR1L

BSR

IPR2

PIR2

PIE2

PORTA

Note 1: This is not a physical register.

2: Unimplemented registers are read as ‘0’.

3: This register is not available on 28-pin devices.

DS39689E-page 62

Preliminary

PIC18F4321 FAMILY

TABLE 5-2:

File Name

TOSU

REGISTER FILE SUMMARY (PIC18F2221/2321/4221/4321)

Value on Details on

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR, BOR

page:

—

Top-of-Stack Upper Byte (TOS<20:16>)

---0 0000

0000 0000

00-0 0000

--00 0000

0000 0000

--00 0000

0000 0000

xxxx xxxx

0000 000x

1111 -1-1

11-0 0-00

N/A

49, 54

49, 55

49, 54

49, 76

49, 89

49, 93

49, 94

49, 95

49, 68

TOSH

Top-of-Stack High Byte (TOS<15:8>)

TOSL

Top-of-Stack Low Byte (TOS<7:0>)

STKPTR

PCLATU

PCLATH

PCL

STKFUL⁽⁶⁾STKUNF⁽⁶⁾

—

SP4

SP3

SP2

SP1

SP0

—

Holding Register for PC<21:16>

Holding Register for PC<15:8>

PC Low Byte (PC<7:0>)

TBLPTRU

—

bit 21

Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)

TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)

TBLPTRL

TABLAT

PRODH

PRODL

Program Memory Table Pointer Low Byte (TBLPTR<7:0>)

Program Memory Table Latch

Product Register High Byte

Product Register Low Byte

INTCON

INTCON2

INTCON3

INDF0

GIE/GIEH

RBPU

PEIE/GIEL

INTEDG0

INT1IP

TMR0IE

INTEDG1

—

INT0IE

INTEDG2

INT2IE

RBIE

—

TMR0IF

TMR0IP

—

INT0IF

—

RBIF

RBIP

INT2IP

INT1IE

INT2IF

INT1IF

Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)

POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)

POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)

N/A

PREINC0

PLUSW0

Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)

N/A

Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –

value of FSR0 offset by W

N/A

FSR0H

FSR0L

WREG

INDF1

—

Indirect Data Memory Address Pointer 0 High Byte

---- 0000

xxxx xxxx

N/A

49, 68

49

Indirect Data Memory Address Pointer 0 Low Byte

Working Register

Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)

49, 68

POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)

POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)

N/A

PREINC1

PLUSW1

Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)

N/A

Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –

value of FSR1 offset by W

N/A

FSR1H

FSR1L

BSR

—

Indirect Data Memory Address Pointer 1 High Byte

---- 0000

xxxx xxxx

---- 0000

N/A

50, 68

50, 59

50, 68

Indirect Data Memory Address Pointer 1 Low Byte

—

Bank Select Register

INDF2

Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)

POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)

POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)

N/A

PREINC2

PLUSW2

Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)

N/A

Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –

value of FSR2 offset by W

N/A

FSR2H

FSR2L

STATUS

—

Indirect Data Memory Address Pointer 2 High Byte

---- 0000

xxxx xxxx

---x xxxx

50, 68

50, 66

Indirect Data Memory Address Pointer 2 Low Byte

—

N

OV

Z

DC

C

Legend:

x= unknown, u= unchanged, —= unimplemented, q= value depends on condition

Note 1:

The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See

Section 4.4 “Brown-out Reset (BOR)”.

2:

3:

4:

5:

6:

These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;

individual unimplemented bits should be interpreted as ‘-’.

The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in

INTOSC Modes”.

The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is

read-only.

RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.

When disabled, these bits read as ‘0’.

Bit 7 and bit 6 are cleared by user software or by a POR.

Preliminary

DS39689E-page 63

PIC18F4321 FAMILY

TABLE 5-2:

REGISTER FILE SUMMARY (PIC18F2221/2321/4221/4321) (CONTINUED)

Value on Details on

POR, BOR page:

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TMR0H

Timer0 Register High Byte

Timer0 Register Low Byte

0000 0000 50, 125

xxxx xxxx 50, 125

1111 1111 50, 123

TMR0L

T0CON

TMR0ON

IDLEN

T08BIT

IRCF2

—

T0CS

IRCF1

IRVST

—

T0SE

IRCF0

HLVDEN

—

PSA

OSTS

HLVDL3

—

T0PS2

IOFS

T0PS1

SCS1

HLVDL1

—

T0PS0

SCS0

OSCCON

HLVDCON

WDTCON

0100 q000

0-00 0101 50, 247

--- ---0 50, 264

31, 50

VDIRMAG

—

HLVDL2

—

HLVDL0

SWDTEN

—

RCON

TMR1H

TMR1L

T1CON

TMR2

IPEN

SBOREN⁽¹⁾

—

RI

TO

PD

POR

BOR

0q-1 11q0 42, 48, 102

xxxx xxxx 50, 131

Timer1 Register High Byte

Timer1 Register Low Byte

RD16

T1RUN

T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC

TMR2ON

TMR1CS

T2CKPS1

TMR1ON 0000 0000 50, 127

0000 0000 50, 134

Timer2 Register

PR2

Timer2 Period Register

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0

MSSP Receive Buffer/Transmit Register

1111 1111 50, 134

T2CON

SSPBUF

—

T2CKPS0 -000 0000 50, 133

xxxx xxxx 50, 169,

170

SSPADD

SSPSTAT

MSSP Address Register in I²C™ Slave mode. MSSP Baud Rate Reload Register in I²C Master mode.

0000 0000 50, 170

SMP

WCOL

GCEN

CKE

D/A

P

S

R/W

UA

BF

0000 0000 50, 162,

171

SSPCON1

SSPCON2

SSPOV

ACKSTAT

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

SEN

0000 0000 50, 163,

172

ACKDT/

ACKEN/

RCEN/

PEN/

RSEN/

0000 0000 50, 173

ADMSK5

ADMSK4

ADMSK3

ADMSK2

ADMSK1

ADRESH

ADRESL

A/D Result Register High Byte

A/D Result Register Low Byte

xxxx xxxx 51, 236

ADCON0

ADCON1

ADCON2

CCPR1H

CCPR1L

CCP1CON

—

CHS3

VCFG1

ACQT2

CHS2

VCFG0

ACQT1

CHS1

PCFG3

ACQT0

CHS0

PCFG2

ADCS2

GO/DONE

PCFG1

ADON

PCFG0

ADCS0

--00 0000 51, 227

--00 0qqq 51, 228

0-00 0000 51, 229

xxxx xxxx 51, 140

ADFM

ADCS1

Capture/Compare/PWM Register 1 High Byte

Capture/Compare/PWM Register 1 Low Byte

P1M1⁽²⁾

P1M0⁽²⁾

DC1B1

DC1B0

CCP1M3

CCP1M2

CCP1M1

CCP1M0 0000 0000 51, 139,

147

CCPR2H

CCPR2L

CCP2CON

BAUDCON

ECCP1DEL

ECCP1AS

CVRCON

CMCON

Capture/Compare/PWM Register 2 High Byte

Capture/Compare/PWM Register 2 Low Byte

xxxx xxxx 51, 140

—

DC2B1

RXDTP

PDC5⁽²⁾

ECCPAS1

CVRR

DC2B0

TXCKP

PDC4⁽²⁾

ECCPAS0

CVRSS

C1INV

CCP2M3

BRG16

PDC3⁽²⁾

PSSAC1

CVR3

CCP2M2

—

PDC2⁽²⁾

PSSAC0

CVR2

CM2

CCP2M1

WUE

PDC1⁽²⁾

PSSBD1⁽²⁾

CVR1

CCP2M0 --00 0000 51, 139

ABDOVF

PRSEN

ECCPASE

CVREN

C2OUT

RCIDL

ABDEN

PDC0⁽²⁾

0100 0-00 51, 208

0000 0000 51, 156

PSSBD0⁽²⁾0000 0000 51, 157

PDC6⁽²⁾

ECCPAS2

CVROE

C1OUT

CVR0

CM0

0000 0000 51, 243

0000 0111 51, 237

xxxx xxxx 51, 137

C2INV

CIS

CM1

TMR3H

Timer3 Register High Byte

Timer3 Register Low Byte

TMR3L

T3CON

RD16

T3CCP2

T3CKPS1

T3CKPS0

T3CCP1

T3SYNC

TMR3CS

TMR3ON 0000 0000 51, 135

Legend:

x= unknown, u= unchanged, —= unimplemented, q= value depends on condition

Note 1:

The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See

Section 4.4 “Brown-out Reset (BOR)”.

2:

3:

4:

5:

6:

These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;

individual unimplemented bits should be interpreted as ‘-’.

The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in

INTOSC Modes”.

The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is

read-only.

RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.

When disabled, these bits read as ‘0’.

Bit 7 and bit 6 are cleared by user software or by a POR.

DS39689E-page 64

Preliminary

PIC18F4321 FAMILY

TABLE 5-2:

REGISTER FILE SUMMARY (PIC18F2221/2321/4221/4321) (CONTINUED)

Value on Details on

POR, BOR page:

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SPBRGH

SPBRG

RCREG

TXREG

TXSTA

RCSTA

EEADR

EEDATA

EECON2

EECON1

IPR2

EUSART Baud Rate Generator Register High Byte

EUSART Baud Rate Generator Register Low Byte

EUSART Receive Register

0000 0000 51, 210

0000 0000 51, 218

0000 0000 51, 215

0000 0010 51, 206

0000 000x 51, 207

0000 0000 51, 74, 83

xx-0 x000 51, 75, 84

11-1 1111 52, 101

EUSART Transmit Register

CSRC

SPEN

TX9

RX9

TXEN

SREN

SYNC

CREN

SENDB

ADDEN

BRGH

FERR

TRMT

OERR

TX9D

RX9D

EEPROM Address Register

EEPROM Data Register

EEPROM Control Register 2 (not a physical register)

EEPGD

OSCFIP

OSCFIF

OSCFIE

PSPIP⁽²⁾

PSPIF⁽²⁾

PSPIE⁽²⁾

INTSRC

IBF

CFGS

CMIP

CMIF

CMIE

ADIP

—

FREE

EEIP

WRERR

BCLIP

BCLIF

BCLIE

SSPIP

SSPIF

SSPIE

TUN3

—

WREN

HLVDIP

HLVDIF

HLVDIE

CCP1IP

CCP1IF

CCP1IE

TUN2

WR

RD

TMR3IP

TMR3IF

TMR3IE

TMR2IP

TMR2IF

TMR2IE

TUN1

CCP2IP

CCP2IF

CCP2IE

TMR1IP

TMR1IF

TMR1IE

TUN0

PIR2

—

EEIF

00-0 0000

52, 97

52, 99

PIE2

—

EEIE

IPR1

RCIP

RCIF

RCIE

—

TXIP

1111 1111 52, 100

PIR1

ADIF

TXIF

0000 0000

00-0 0000

0000 -111

1111 1111

52, 96

52, 98

27, 52

52, 118

52, 114

52, 111

PIE1

ADIE

PLLEN⁽³⁾

TXIE

OSCTUNE

TRISE⁽²⁾

TRISD⁽²⁾

TRISC

TRISB

TUN4

PSPMODE

OBF

IBOV

TRISE2

TRISE1

TRISE0

PORTD Data Direction Control Register

PORTC Data Direction Control Register

PORTB Data Direction Control Register

1111 1111 52, 108

1111 1111 52, 105

TRISA

TRISA7⁽⁵⁾

TRISA6⁽⁵⁾PORTA Data Direction Control Register

LATE⁽²⁾

—

PORTE Data Latch Register

---- -xxx

52, 117

(Read and Write to Data Latch)

LATD⁽²⁾

LATC

PORTD Data Latch Register (Read and Write to Data Latch)

PORTC Data Latch Register (Read and Write to Data Latch)

PORTB Data Latch Register (Read and Write to Data Latch)

xxxx xxxx

52, 114

52, 111

LATB

xxxx xxxx 52, 108

xxxx xxxx 52, 105

LATA

LATA7⁽⁵⁾

LATA6⁽⁵⁾PORTA Data Latch Register (Read and Write to Data Latch)

PORTE

PORTD⁽²⁾

PORTC

PORTB

PORTA

—

RE3⁽⁴⁾

RD3

RC3

RB3

RE2⁽²⁾

RD2

RC2

RB2

RE1⁽²⁾

RD1

RC1

RB1

RE0⁽²⁾

RD0

RC0

RB0

---- xxxx

xxxx xxxx

52, 117

52, 114

52, 111

RD7

RD6

RC6

RB6

RD5

RC5

RB5

RA5

RD4

RC4

RB4

RA4

RC7

RB7

RA7⁽⁵⁾

xxxx xxxx 52, 108

xx0x 0000 52, 105

RA6⁽⁵⁾

RA3

RA2

RA1

RA0

Legend:

x= unknown, u= unchanged, —= unimplemented, q= value depends on condition

Note 1:

The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See

Section 4.4 “Brown-out Reset (BOR)”.

2:

3:

4:

5:

6:

These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;

individual unimplemented bits should be interpreted as ‘-’.

The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in

INTOSC Modes”.

The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is

read-only.

RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.

When disabled, these bits read as ‘0’.

Bit 7 and bit 6 are cleared by user software or by a POR.

Preliminary

DS39689E-page 65

PIC18F4321 FAMILY

It is recommended that only BCF, BSF, SWAPF, MOVFF

and MOVWFinstructions are used to alter the STATUS

register, because these instructions do not affect the Z,

C, DC, OV or N bits in the STATUS register.

5.3.5

STATUS REGISTER

The STATUS register, shown in Register 5-2, contains

the arithmetic status of the ALU. As with any other SFR,

it can be the operand for any instruction.

For other instructions that do not affect Status bits, see

the instruction set summaries in Table 24-2 and

Table 24-3.

If the STATUS register is the destination for an instruc-

tion that affects the Z, DC, C, OV or N bits, the results

of the instruction are not written; instead, the STATUS

register is updated according to the instruction

performed. Therefore, the result of an instruction with

the STATUS register as its destination may be different

than intended. As an example, CLRF STATUSwill set

Note:

The C and DC bits operate as the borrow

and digit borrow bits, respectively, in

subtraction.

the

Z bit and leave the remaining Status bits

unchanged (‘000u u1uu’).

REGISTER 5-2:

STATUS REGISTER

U-0

—

U-0

—

U-0

—

R/W-x

OV

R/W-x

Z

R/W-x

DC

R/W-x

C

N

bit 7

bit 0

bit 7-5

bit 4

Unimplemented: Read as ‘0’

N: Negative bit

This bit is used for signed arithmetic (2’s complement). It indicates whether the result was

negative (ALU MSB = 1).

1= Result was negative

0= Result was positive

bit 3

OV: Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit

magnitude which causes the sign bit (bit 7 of the result) to change state.

1= Overflow occurred for signed arithmetic (in this arithmetic operation)

0= No overflow occurred

bit 2

bit 1

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit Carry/borrow bit

For ADDWF, ADDLW, SUBLWand SUBWFinstructions:

1= A carry-out from the 4th low-order bit of the result occurred

0= No carry-out from the 4th low-order bit of the result

Note:

For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is

loaded with either bit 4 or bit 3 of the source register.

bit 0

C: Carry/borrow bit

For ADDWF, ADDLW, SUBLWand SUBWFinstructions:

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note:

For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is

loaded with either the high or low-order bit of the source register.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39689E-page 66

Preliminary

PIC18F4321 FAMILY

The Access RAM bit ‘a’ determines how the address is

interpreted. When ‘a’ is ‘1’, the contents of the BSR

(Section 5.3.1 “Bank Select Register (BSR)”) are

used with the address to determine the complete 12-bit

address of the register. When ‘a’ is ‘0’, the address is

interpreted as being a register in the Access Bank.

Addressing that uses the Access RAM is sometimes

also known as Direct Forced Addressing mode.

5.4

Data Addressing Modes

Note:

The execution of some instructions in the

core PIC18 instruction set are changed

when the PIC18 extended instruction set is

enabled. See Section 5.5 “Data Memory

and the Extended Instruction Set” for

more information.

A few instructions, such as MOVFF, include the entire

12-bit address (either source or destination) in their

opcodes. In these cases, the BSR is ignored entirely.

The data memory space can be addressed in several

ways. For most instructions, the addressing mode is

fixed. Other instructions may use up to three modes,

depending on which operands are used and whether or

not the extended instruction set is enabled.

The destination of the operation’s results is determined

by the destination bit ‘d’. When ‘d’ is ‘1’, the results are

stored back in the source register, overwriting its origi-

nal contents. When ‘d’ is ‘0’, the results are stored in

the W register. Instructions without the ‘d’ argument

have a destination that is implicit in the instruction; their

destination is either the target register being operated

on or the W register.

The addressing modes are:

• Inherent

• Literal

• Direct

• Indirect

An additional addressing mode, Indexed Literal Offset,

is available when the extended instruction set is

enabled (XINST Configuration bit = 1). Its operation is

discussed in greater detail in Section 5.5.1 “Indexed

Addressing with Literal Offset”.

5.4.3

INDIRECT ADDRESSING

Indirect addressing allows the user to access a location

in data memory without giving a fixed address in the

instruction. This is done by using File Select Registers

(FSRs) as pointers to the locations to be read or written

to. Since the FSRs are themselves located in RAM as

Special Function Registers, they can also be directly

manipulated under program control. This makes FSRs

very useful in implementing data structures, such as

tables and arrays in data memory.

5.4.1

INHERENT AND LITERAL

ADDRESSING

Many PIC18 control instructions do not need any

argument at all; they either perform an operation that

globally affects the device or they operate implicitly on

one register. This addressing mode is known as Inherent

Addressing. Examples include SLEEP, RESETand DAW.

The registers for indirect addressing are also

implemented with Indirect File Operands (INDFs) that

permit automatic manipulation of the pointer value with

auto-incrementing, auto-decrementing or offsetting

with another value. This allows for efficient code, using

loops, such as the example of clearing an entire RAM

bank in Example 5-5.

Other instructions work in a similar way but require an

additional explicit argument in the opcode. This is

known as Literal Addressing mode because they

require some literal value as an argument. Examples

include ADDLWand MOVLW, which respectively, add or

move a literal value to the W register. Other examples

include CALL and GOTO, which include a 20-bit

program memory address.

EXAMPLE 5-5:

HOW TO CLEAR RAM

(BANK 1) USING

INDIRECT ADDRESSING

5.4.2

DIRECT ADDRESSING

LFSR

FSR0, 100h ;

POSTINC0

; Clear INDF

Direct addressing specifies all or part of the source

and/or destination address of the operation within the

opcode itself. The options are specified by the

arguments accompanying the instruction.

; register then

; inc pointer

; All done with

; Bank1?

; NO, clear next

; YES, continue

BTFSS FSR0H, 1

BRA NEXT

In the core PIC18 instruction set, bit-oriented and byte-

oriented instructions use some version of direct

addressing by default. All of these instructions include

some 8-bit literal address as their Least Significant

Byte. This address specifies either a register address in

one of the banks of data RAM (Section 5.3.3 “General

Purpose Register File”) or a location in the Access

Bank (Section 5.3.2 “Access Bank”) as the data

source for the instruction.

CONTINUE

Preliminary

DS39689E-page 67

PIC18F4321 FAMILY

5.4.3.1

FSR Registers and the

INDF Operand

5.4.3.2

FSR Registers and POSTINC,

POSTDEC, PREINC and PLUSW

At the core of indirect addressing are three sets of

registers: FSR0, FSR1 and FSR2. Each represents a

pair of 8-bit registers, FSRnH and FSRnL. The four

upper bits of the FSRnH register are not used so each

FSR pair holds a 12-bit value. This represents a value

that can address the entire range of the data memory

in a linear fashion. The FSR register pairs, then, serve

as pointers to data memory locations.

In addition to the INDF operand, each FSR register pair

also has four additional indirect operands. Like INDF,

these are “virtual” registers that cannot be indirectly

read or written to. Accessing these registers actually

accesses the associated FSR register pair, but also

performs a specific action on its stored value. They are:

• POSTDEC: accesses the FSR value, then

automatically decrements it by 1 afterwards

Indirect addressing is accomplished with a set of

Indirect File Operands, INDF0 through INDF2. These

can be thought of as “virtual” registers: they are

mapped in the SFR space but are not physically imple-

mented. Reading or writing to a particular INDF register

actually accesses its corresponding FSR register pair.

A read from INDF1, for example, reads the data at the

address indicated by FSR1H:FSR1L. Instructions that

use the INDF registers as operands actually use the

contents of their corresponding FSR as a pointer to the

instruction’s target. The INDF operand is just a

convenient way of using the pointer.

• POSTINC: accesses the FSR value, then

automatically increments it by 1 afterwards

• PREINC: increments the FSR value by 1, then

uses it in the operation

• PLUSW: adds the signed value of the W register

(range of -127 to 128) to that of the FSR and uses

the new value in the operation.

In this context, accessing an INDF register uses the

value in the FSR registers without changing them. Sim-

ilarly, accessing a PLUSW register gives the FSR value

offset by that in the W register; neither value is actually

changed in the operation. Accessing the other virtual

registers changes the value of the FSR registers.

Because indirect addressing uses a full 12-bit address,

data RAM banking is not necessary. Thus, the current

contents of the BSR and the Access RAM bit have no

effect on determining the target address.

Operations on the FSRs with POSTDEC, POSTINC

and PREINC affect the entire register pair; that is, roll-

overs of the FSRnL register from FFh to 00h carry over

to the FSRnH register. On the other hand, results of

these operations do not change the value of any flags

in the STATUS register (e.g., Z, N, OV, etc.).

FIGURE 5-7:

INDIRECT ADDRESSING

000h

Using an instruction with one of the

indirect addressing registers as the

operand....

Bank 0

Bank 1

ADDWF, INDF1, 1

100h

200h

300h

Bank 2

FSR1H:FSR1L

...uses the 12-bit address stored in

the FSR pair associated with that

register....

7

0

7

0

Bank 3

through

Bank 13

x x x x 1 1 1 0

1 1 0 0 1 1 0 0

...to determine the data memory

location to be used in that operation.

E00h

In this case, the FSR1 pair contains

ECCh. This means the contents of

location ECCh will be added to that

of the W register and stored back in

ECCh.

Bank 14

Bank 15

F00h

FFFh

Data Memory

DS39689E-page 68

Preliminary

PIC18F4321 FAMILY

The PLUSW register can be used to implement a form

of indexed addressing in the data memory space. By

manipulating the value in the W register, users can

reach addresses that are fixed offsets from pointer

addresses. In some applications, this can be used to

implement some powerful program control structure,

such as software stacks, inside of data memory.

5.5.1

INDEXED ADDRESSING WITH

LITERAL OFFSET

Enabling the PIC18 extended instruction set changes

the behavior of indirect addressing using the FSR2

register pair within Access RAM. Under the proper

conditions, instructions that use the Access Bank – that

is, most bit-oriented and byte-oriented instructions – can

invoke a form of indexed addressing using an offset

specified in the instruction. This special addressing

mode is known as Indexed Addressing with Literal

Offset, or Indexed Literal Offset mode.

5.4.3.3

Operations by FSRs on FSRs

Indirect addressing operations that target other FSRs

or virtual registers represent special cases. For exam-

ple, using an FSR to point to one of the virtual registers

will not result in successful operations. As a specific

case, assume that FSR0H:FSR0L contains FE7h, the

address of INDF1. Attempts to read the value of the

INDF1 using INDF0 as an operand will return 00h.

Attempts to write to INDF1 using INDF0 as the operand

will result in a NOP.

When using the extended instruction set, this

addressing mode requires the following:

• The use of the Access Bank is forced (‘a’ = 0);

and

• The file address argument is less than or equal to

5Fh.

On the other hand, using the virtual registers to write to

an FSR pair may not occur as planned. In these cases,

the value will be written to the FSR pair but without any

incrementing or decrementing. Thus, writing to INDF2

or POSTDEC2 will write the same value to the

FSR2H:FSR2L.

Under these conditions, the file address of the instruc-

tion is not interpreted as the lower byte of an address

(used with the BSR in direct addressing), or as an 8-bit

address in the Access Bank. Instead, the value is

interpreted as an offset value to an Address Pointer,

specified by FSR2. The offset and the contents of

FSR2 are added to obtain the target address of the

operation.

Since the FSRs are physical registers mapped in the

SFR space, they can be manipulated through all direct

operations. Users should proceed cautiously when

working on these registers, particularly if their code

uses indirect addressing.

5.5.2

INSTRUCTIONS AFFECTED BY

INDEXED LITERAL OFFSET MODE

Any of the core PIC18 instructions that can use direct

addressing are potentially affected by the Indexed

Literal Offset Addressing mode. This includes all

byte-oriented and bit-oriented instructions, or almost

one-half of the standard PIC18 instruction set.

Instructions that only use Inherent or Literal Addressing

modes are unaffected.

Similarly, operations by indirect addressing are generally

permitted on all other SFRs. Users should exercise the

appropriate caution that they do not inadvertently

change settings that might affect the operation of the

device.

5.5

Data Memory and the Extended

Instruction Set

Additionally, byte-oriented and bit-oriented instructions

are not affected if they do not use the Access Bank

(Access RAM bit is ‘1’), or include a file address of 60h

or above. Instructions meeting these criteria will

continue to execute as before. A comparison of the dif-

ferent possible addressing modes when the extended

instruction set is enabled is shown in Figure 5-8.

Enabling the PIC18 extended instruction set (XINST

Configuration bit = 1) significantly changes certain

aspects of data memory and its addressing. Specifically,

the use of the Access Bank for many of the core PIC18

instructions is different. This is due to the introduction of

a new addressing mode for the data memory space.

Those who desire to use bit-oriented or byte-oriented

instructions in the Indexed Literal Offset mode should

note the changes to assembler syntax for this mode.

This is described in more detail in Section 24.2.1

“Extended Instruction Syntax”.

What does not change is just as important. The size of

the data memory space is unchanged, as well as its

linear addressing. The SFR map remains the same.

Core PIC18 instructions can still operate in both Direct

and Indirect Addressing mode; inherent and literal

instructions do not change at all. Indirect addressing

with FSR0 and FSR1 also remain unchanged.

Preliminary

DS39689E-page 69

PIC18F4321 FAMILY

FIGURE 5-8:

COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND

BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)

EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)

000h

When ‘a’ = 0 and ‘f’ ≥ 60h:

The instruction executes in

060h

080h

Direct Forced mode. ‘f’ is inter-

preted as a location in the

Access RAM between 060h

and 0FFh. This is the same as

locations 060h to 07Fh

(Bank 0) and F80h to FFFh

(Bank 15) of data memory.

Bank 0

100h

00h

Bank 1

through

Bank 14

60h

80h

Valid range

for ‘f’

FFh

F00h

Access RAM

Locations below 60h are not

available in this addressing

mode.

Bank 15

SFRs

F80h

FFFh

Data Memory

When ‘a’ = 0 and ‘f’ ≤ 5Fh:

000h

080h

100h

Bank 0

The instruction executes in

Indexed Literal Offset mode. ‘f’

is interpreted as an offset to the

address value in FSR2. The

two are added together to

obtain the address of the target

register for the instruction. The

address can be anywhere in

the data memory space.

001001da ffffffff

Bank 1

through

Bank 14

FSR2H

FSR2L

F00h

F80h

Note that in this mode, the

correct syntax is now:

ADDWF [k], d

Bank 15

SFRs

where ‘k’ is the same as ‘f’.

FFFh

Data Memory

BSR

000h

080h

100h

00000000

When ‘a’ = 1 (all values of ‘f’):

Bank 0

The instruction executes in

Direct mode (also known as

Direct Long mode). ‘f’ is inter-

preted as a location in one of

the 16 banks of the data

memory space. The bank is

designated by the Bank Select

Register (BSR). The address

can be in any implemented

bank in the data memory

space.

001001da ffffffff

Bank 1

through

Bank 14

F00h

F80h

Bank 15

SFRs

FFFh

Data Memory

DS39689E-page 70

Preliminary

PIC18F4321 FAMILY

Remapping of the Access Bank applies only to opera-

tions using the Indexed Literal Offset Addressing

mode. Operations that use the BSR (Access RAM bit is

‘1’) will continue to use direct addressing as before.

5.5.3

MAPPING THE ACCESS BANK IN

INDEXED LITERAL OFFSET

ADDRESSING MODE

The use of Indexed Literal Offset Addressing mode

effectively changes how the first 96 locations of Access

RAM (00h to 5Fh) are mapped. Rather than containing

just the contents of the bottom half of Bank 0, this mode

maps the contents from Bank 0 and a user-defined

“window” that can be located anywhere in the data

memory space. The value of FSR2 establishes the

lower boundary of the addresses mapped into the

window, while the upper boundary is defined by FSR2

plus 95 (5Fh). Addresses in the Access RAM above

5Fh are mapped as previously described (see

Section 5.3.2 “Access Bank”). An example of Access

Bank remapping in this addressing mode is shown in

Figure 5-9.

5.6

PIC18 Instruction Execution and

the Extended Instruction Set

Enabling the extended instruction set adds eight

additional commands to the existing PIC18 instruction

set. These instructions are executed as described in

Section 24.2 “Extended Instruction Set”.

FIGURE 5-9:

REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET

ADDRESSING MODE

Example Situation:

ADDWF f, d, a

000h

Bank 0

05Fh

07Fh

FSR2H:FSR2L = 120h

Bank 0

Bank 1

Window

Locations in the region

from the FSR2 Pointer

(120h) to the pointer plus

05Fh (17Fh) are mapped

to the bottom of the

Access RAM (000h-05Fh).

100h

120h

17Fh

00h

Bank 1

Bank 1 “Window”

200h

5Fh

Locations in Bank 0, from

060h to 07Fh, are mapped

as usual to the middle of

the Access Bank.

Bank 0

7Fh

80h

Bank 2

through

Bank 14

SFRs

Special Function Regis-

ters at F80h through FFFh

are mapped to 80h

through FFh, as usual.

FFh

Access Bank

F00h

Bank 0 addresses below

5Fh can still be addressed

by using the BSR.

Bank 15

SFRs

F80h

FFFh

Data Memory

Preliminary

DS39689E-page 71

PIC18F4321 FAMILY

NOTES:

DS39689E-page 72

Preliminary

PIC18F4321 FAMILY

6.1

Table Reads and Table Writes

6.0

FLASH PROGRAM MEMORY

In order to read and write program memory, there are

two operations that allow the processor to move bytes

between the program memory space and the data RAM:

The Flash program memory is readable, writable and

erasable during normal operation over the entire VDD

range.

• Table Read (TBLRD)

• Table Write (TBLWT)

A read from program memory is executed on one byte

at a time. A write to program memory is executed on

blocks of 8 bytes at a time. Program memory is erased

in blocks of 64 bytes at a time. A bulk erase operation

may not be issued from user code.

The program memory space is 16 bits wide, while the

data RAM space is 8 bits wide. Table reads and table

writes move data between these two memory spaces

through an 8-bit register (TABLAT).

Writing or erasing program memory will cease

instruction fetches until the operation is complete. The

program memory cannot be accessed during the write

or erase, therefore, code cannot execute. An internal

programming timer terminates program memory writes

and erases.

Table read operations retrieve data from program

memory and place it into the data RAM space.

Figure 6-1 shows the operation of a table read with

program memory and data RAM.

Table write operations store data from the data memory

space into holding registers in program memory. The

procedure to write the contents of the holding registers

into program memory is detailed in Section 6.5 “Writing

to Flash Program Memory”. Figure 6-2 shows the

operation of a table write with program memory and data

RAM.

A value written to program memory does not need to be

a valid instruction. Executing a program memory

location that forms an invalid instruction results in a

NOP.

Table operations work with byte entities. A table block

containing data, rather than program instructions, is not

required to be word aligned. Therefore, a table block can

start and end at any byte address. If a table write is being

used to write executable code into program memory,

program instructions will need to be word aligned.

FIGURE 6-1:

TABLE READ OPERATION

Instruction: TBLRD*

Program Memory

(1)

Table Pointer

Table Latch (8-bit)

TABLAT

TBLPTRU TBLPTRH TBLPTRL

Program Memory

(TBLPTR)

Note 1: Table Pointer register points to a byte in program memory.

Preliminary

DS39689E-page 73

PIC18F4321 FAMILY

FIGURE 6-2:

TABLE WRITE OPERATION

Instruction: TBLWT*

Program Memory

Holding Registers

(1)

Table Pointer

Table Latch (8-bit)

TABLAT

TBLPTRU TBLPTRH TBLPTRL

Program Memory

(TBLPTR)

Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by

TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in

Section 6.5 “Writing to Flash Program Memory”.

The FREE bit, when set, will allow a program memory

erase operation. When FREE is set, the erase

operation is initiated on the next WR command. When

FREE is clear, only writes are enabled.

6.2

Control Registers

Several control registers are used in conjunction with

the TBLRDand TBLWTinstructions. These include the:

• EECON1 register

• EECON2 register

• TABLAT register

• TBLPTR registers

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set in hardware when the WR bit is set and cleared

when the internal programming timer expires and the

write operation is complete.

6.2.1

EECON1 AND EECON2 REGISTERS

Note:

During normal operation, the WRERR bit

may read as ‘1’. This can indicate that a

write operation was prematurely termi-

nated by a Reset, or a write operation was

attempted improperly.

The EECON1 register (Register 6-1) is the control

register for memory accesses. The EECON2 register is

not a physical register; it is used exclusively in the

memory write and erase sequences. Reading

EECON2 will read all ‘0’s.

The WR control bit initiates write operations. The bit

cannot be cleared, only set, in software; it is cleared in

hardware at the completion of the write operation.

The EEPGD control bit determines if the access will be

a program or data EEPROM memory access. When

clear, any subsequent operations will operate on the

data EEPROM memory. When set, any subsequent

operations will operate on the program memory.

Note:

The EEIF interrupt flag bit (PIR2<4>) is set

when the write is complete. It must be

cleared in software.

The CFGS control bit determines if the access will be

to the Configuration/Calibration registers or to program

memory/data EEPROM memory. When set,

subsequent operations will operate on Configuration

registers regardless of EEPGD (see Section 23.0

“Special Features of the CPU”). When clear, memory

selection access is determined by EEPGD.

DS39689E-page 74

Preliminary

PIC18F4321 FAMILY

REGISTER 6-1:

EECON1: DATA EEPROM CONTROL REGISTER 1

R/W-x

CFGS

U-0

—

R/W-0

FREE

R/W-x

R/W-0

WREN

R/S-0

WR

R/S-0

RD

EEPGD

WRERR

bit 7

bit 0

bit 7

bit 6

EEPGD: Flash Program or Data EEPROM Memory Select bit

1= Access Flash program memory

0= Access data EEPROM memory

CFGS: Flash Program/Data EEPROM or Configuration Select bit

1= Access Configuration registers

0= Access Flash program or data EEPROM memory

bit 5

bit 4

Unimplemented: Read as ‘0’

FREE: Flash Row Erase Enable bit

1= Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

0= Perform write-only

bit 3

WRERR: Flash Program/Data EEPROM Error Flag bit

1= A write operation is prematurely terminated (any Reset during self-timed programming in

normal operation, or an improper write attempt)

0= The write operation completed

Note:

When a WRERR occurs, the EEPGD and CFGS bits are not cleared.

This allows tracing of the error condition.

bit 2

bit 1

WREN: Flash Program/Data EEPROM Write Enable bit

1= Allows write cycles to Flash program/data EEPROM

0= Inhibits write cycles to Flash program/data EEPROM

WR: Write Control bit

1= Initiates a data EEPROM erase/write cycle or a program memory erase/write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete.

The WR bit can only be set (not cleared) in software.)

0= Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit

1= Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can

only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1or CFGS = 1.)

0= Does not initiate an EEPROM read

Legend:

R = Readable bit

W = Writable bit

S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

Preliminary

DS39689E-page 75

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6.2.2

TABLAT – TABLE LATCH REGISTER

6.2.4

TABLE POINTER BOUNDARIES

The Table Latch (TABLAT) is an 8-bit register mapped

into the SFR space. The Table Latch register is used to

hold 8-bit data during data transfers between program

memory and data RAM.

TBLPTR is used in reads, writes and erases of the

Flash program memory.

When a TBLRDis executed, all 22 bits of the TBLPTR

determine which byte is read from program memory

into TABLAT.

6.2.3

TBLPTR – TABLE POINTER

REGISTER

When a TBLWTis executed, the three LSbs of the Table

Pointer register (TBLPTR<2:0>) determine which of the

8 program memory holding registers is written to. When

the timed write to program memory begins (via the WR

bit), the 19 MSbs of the TBLPTR (TBLPTR<21:3>)

determine which program memory block of 8 bytes is

written to. For more detail, see Section 6.5 “Writing to

Flash Program Memory”.

The Table Pointer (TBLPTR) register addresses a byte

within the program memory. The TBLPTR is comprised

of three SFR registers: Table Pointer Upper Byte, Table

Pointer High Byte and Table Pointer Low Byte

(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-

ters join to form a 22-bit wide pointer. The low-order

21 bits allow the device to address up to 2 Mbytes of

program memory space. The 22nd bit allows access to

the device ID, the user ID and the Configuration bits.

When an erase of program memory is executed, the

16 MSbs of the Table Pointer register (TBLPTR<21:6>)

point to the 64-byte block that will be erased. The Least

Significant bits (TBLPTR<5:0>) are ignored.

The Table Pointer register, TBLPTR, is used by the

TBLRDand TBLWTinstructions. These instructions can

update the TBLPTR in one of four ways based on the

table operation. These operations are shown in

Table 6-1. These operations on the TBLPTR only affect

the low-order 21 bits.

Figure 6-3 describes the relevant boundaries of

TBLPTR based on Flash program memory operations.

TABLE 6-1:

Example

TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

Operation on Table Pointer

TBLRD*

TBLWT*

TBLPTR is not modified

TBLRD*+

TBLWT*+

TBLPTR is incremented after the read/write

TBLPTR is decremented after the read/write

TBLPTR is incremented before the read/write

TBLRD*-

TBLWT*-

TBLRD+*

TBLWT+*

FIGURE 6-3:

TABLE POINTER BOUNDARIES BASED ON OPERATION

21

16 15

TBLPTRH

8

7

TBLPTRL

0

TBLPTRU

TABLE ERASE/WRITE

TBLPTR<21:3>

TABLE WRITE

TBLPTR<2:0>

TABLE READ – TBLPTR<21:0>

DS39689E-page 76

Preliminary

PIC18F4321 FAMILY

TBLPTR points to a byte address in program space.

Executing TBLRD places the byte pointed to into

TABLAT. In addition, TBLPTR can be modified

automatically for the next table read operation.

6.3

Reading the Flash Program

Memory

The TBLRD instruction is used to retrieve data from

program memory and place it into data RAM. Table

reads from program memory are performed one byte at

a time.

The internal program memory is typically organized by

words. The Least Significant bit of the address selects

between the high and low bytes of the word. Figure 6-4

shows the interface between the internal program

memory and the TABLAT.

FIGURE 6-4:

READS FROM FLASH PROGRAM MEMORY

Program Memory

(Even Byte Address)

(Odd Byte Address)

TBLPTR = xxxxx1

TBLPTR = xxxxx0

Instruction Register

(IR)

TABLAT

Read Register

FETCH

TBLRD

EXAMPLE 6-1:

READING A FLASH PROGRAM MEMORY WORD

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

CODE_ADDR_UPPER

TBLPTRU

CODE_ADDR_HIGH

TBLPTRH

CODE_ADDR_LOW

TBLPTRL

; Load TBLPTR with the base

; address of the word

READ_WORD

TBLRD*+

MOVF

MOVWF

TBLRD*+

MOVF

; read into TABLAT and increment

; get data

TABLAT, W

WORD_EVEN

; read into TABLAT and increment

; get data

TABLAT, W

WORD_ODD

MOVWF

Preliminary

DS39689E-page 77

PIC18F4321 FAMILY

6.4.1

FLASH PROGRAM MEMORY

ERASE SEQUENCE

6.4

Erasing Flash Program Memory

The minimum erase block is 32 words or 64 bytes. Only

through the use of an external programmer, or through

ICSP control, can larger blocks of program memory be

bulk erased. Word erase in the Flash array is not

supported.

The sequence of events for erasing a block of internal

program memory location is:

1. Load Table Pointer register with address of row

being erased.

When initiating an erase sequence from the micro-

controller itself, a block of 64 bytes of program memory

is erased. The Most Significant 16 bits of the

TBLPTR<21:6> point to the block being erased.

TBLPTR<5:0> are ignored.

2. Set the EECON1 register for the erase operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set WREN bit to enable writes;

• set FREE bit to enable the erase.

3. Disable interrupts.

The EECON1 register commands the erase operation.

The EEPGD bit must be set to point to the Flash

program memory. The WREN bit must be set to enable

write operations. The FREE bit is set to select an erase

operation.

4. Write 55h to EECON2.

5. Write 0AAh to EECON2.

6. Set the WR bit. This will begin the row erase

cycle.

For protection, the write initiate sequence for EECON2

must be used.

7. The CPU will stall for duration of the erase

(about 2 ms using internal timer).

A long write is necessary for erasing the internal Flash.

Instruction execution is halted while in a long write

cycle. The long write will be terminated by the internal

programming timer.

8. Re-enable interrupts.

EXAMPLE 6-2:

ERASING A FLASH PROGRAM MEMORY ROW

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

CODE_ADDR_UPPER

TBLPTRU

CODE_ADDR_HIGH

TBLPTRH

CODE_ADDR_LOW

TBLPTRL

; load TBLPTR with the base

; address of the memory block

ERASE_ROW

BSF

BCF

BSF

EECON1, EEPGD

EECON1, CFGS

EECON1, WREN

EECON1, FREE

INTCON, GIE

55h

EECON2

0AAh

EECON2

EECON1, WR

INTCON, GIE

; point to Flash program memory

; access Flash program memory

; enable write to memory

; enable Row Erase operation

; disable interrupts

BCF

Required

Sequence

MOVLW

MOVWF

MOVLW

MOVWF

BSF

; write 55h

; write 0AAh

; start erase (CPU stall)

; re-enable interrupts

BSF

DS39689E-page 78

Preliminary

PIC18F4321 FAMILY

The long write is necessary for programming the

internal Flash. Instruction execution is halted while in a

long write cycle. The long write will be terminated by

the internal programming timer.

6.5

Writing to Flash Program Memory

The minimum programming block is 4 words or 8 bytes.

Word or byte programming is not supported.

Table writes are used internally to load the holding

registers needed to program the Flash memory. There

are 8 holding registers used by the table writes for

programming.

The EEPROM on-chip timer controls the write time.

The write/erase voltages are generated by an on-chip

charge pump, rated to operate over the voltage range

of the device.

Since the Table Latch (TABLAT) is only a single byte,

the TBLWTinstruction may need to be executed 8 times

for each programming operation. All of the table write

operations will essentially be short writes because only

the holding registers are written. At the end of updating

the 8 holding registers, the EECON1 register must be

written to in order to start the programming operation with

a long write.

Note:

The default value of the holding registers on

device Resets and after write operations is

FFh. A write of FFh to a holding register

does not modify that byte. This means that

individual bytes of program memory may be

modified, provided that the modification

does not attempt to change any bit from a

‘0’ to a ‘1’. When modifying individual bytes,

it is not necessary to load all 8 holding

registers before executing a write operation.

FIGURE 6-5:

TABLE WRITES TO FLASH PROGRAM MEMORY

TABLAT

Write Register

8

TBLPTR = xxxxx0

TBLPTR = xxxxx1

TBLPTR = xxxxx2

TBLPTR = xxxxx7

Holding Register

Program Memory

9. Write 55h to EECON2.

10. Write 0AAh to EECON2.

6.5.1

FLASH PROGRAM MEMORY

WRITE SEQUENCE

11. Set the WR bit. This will begin the write cycle.

The sequence of events for programming an internal

program memory location should be:

12. The CPU will stall for duration of the write (about

2 ms using internal timer).

1. Read 64 bytes into RAM.

13. Repeat from step 5 seven more times.

14. Re-enable interrupts.

2. Update data values in RAM as necessary.

3. Load Table Pointer register with address being

erased.

15. Verify the memory (table read).

This procedure will require about 18 ms to update one

row of 64 bytes of memory. An example of the required

code is given in Example 6-3.

4. Execute the row erase procedure.

5. Load Table Pointer register with address of first

byte being written.

6. Write the 8 bytes into the holding registers.

7. Set the EECON1 register for the write operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program memory;

• set WREN to enable byte writes.

Note:

Before setting the WR bit, the Table

Pointer address needs to be within the

intended address range of the 8 bytes in

the holding register.

8. Disable interrupts.

Preliminary

DS39689E-page 79

PIC18F4321 FAMILY

EXAMPLE 6-3:

WRITING TO FLASH PROGRAM MEMORY

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

D'64

COUNTER

BUFFER_ADDR_HIGH

FSR0H

BUFFER_ADDR_LOW

FSR0L

CODE_ADDR_UPPER

TBLPTRU

CODE_ADDR_HIGH

TBLPTRH

CODE_ADDR_LOW

TBLPTRL

; number of bytes in erase block

; point to buffer

; Load TBLPTR with the base

; address of the memory block

; 6 LSB = 0

READ_BLOCK

TBLRD*+

MOVFW

; read into TABLAT, and inc

; get data

TABLAT

MOVWF

DECFSZ COUNTER

POSTINC0

; store data and increment FSR0

; done?

GOTO

READ_BLOCK

; repeat

MODIFY_WORD

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

DATA_ADDR_HIGH

FSR0H

DATA_ADDR_LOW

FSR0L

NEW_DATA_LOW

POSTINC0

NEW_DATA_HIGH

INDF0

; point to buffer

; update buffer word and increment FSR0

; update buffer word

ERASE_BLOCK

MOVLW

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

BCF

BSF

BCF

MOVLW

MOVWF

MOVLW

MOVWF

BSF

CODE_ADDR_UPPER

TBLPTRU

CODE_ADDR_HIGH

TBLPTRH

CODE_ADDR_LOW

TBLPTRL

EECON1, CFGS

EECON1, EEPGD

EECON1, WREN

EECON1, FREE

INTCON, GIE

55h

; load TBLPTR with the base

; address of the memory block

; 6 LSB = 0

; point to PROG/EEPROM memory

; point to Flash program memory

; enable write to memory

; enable Row Erase operation

; disable interrupts

; Required sequence

; write 55H

EECON2

AAh

EECON2

EECON1, WR

; write AAH

; start erase (CPU stall)

NOP

BSF

INTCON, GIE

; re-enable interrupts

WRITE_BUFFER_BACK

MOVLW

8

; number of write buffer groups of 8 bytes

; point to buffer

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

COUNTER_HI

BUFFER_ADDR_HIGH

FSR0H

BUFFER_ADDR_LOW

FSR0L

PROGRAM_LOOP

MOVLW

MOVWF

8

; number of bytes in holding register

COUNTER

WRITE_WORD_TO_HREGS

MOVFW

MOVWF

TBLWT+*

POSTINC0

TABLAT

; get low byte of buffer data and increment FSR0

; present data to table latch

; short write

; to internal TBLWT holding register, increment

TBLPTR

DECFSZ COUNTER

GOTO WRITE_WORD_TO_HREGS

; loop until buffers are full

DS39689E-page 80

Preliminary

PIC18F4321 FAMILY

EXAMPLE 6-3:

WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

PROGRAM_MEMORY

BCF

INTCON, GIE

55h

EECON2

AAh

EECON2

EECON1, WR

; disable interrupts

; required sequence

; write 55H

MOVLW

MOVWF

MOVLW

MOVWF

BSF

; write AAH

; start program (CPU stall)

NOP

BSF

INTCON, GIE

; re-enable interrupts

; loop until done

DECFSZ COUNTER_HI

GOTO

BCF

PROGRAM_LOOP

EECON1, WREN

; disable write to memory

6.5.2

WRITE VERIFY

6.5.4

PROTECTION AGAINST

SPURIOUS WRITES

Depending on the application, good programming

practice may dictate that the value written to the

memory should be verified against the original value.

This should be used in applications where excessive

writes can stress bits near the specification limit.

To protect against spurious writes to Flash program

memory, the write initiate sequence must also be

followed. See Section 23.0 “Special Features of the

CPU” for more detail.

6.5.3

UNEXPECTED TERMINATION OF

WRITE OPERATION

6.6

Flash Program Operation During

Code Protection

If a write is terminated by an unplanned event, such as

loss of power or an unexpected Reset, the memory

location just programmed should be verified and repro-

grammed if needed. If the write operation is interrupted

by a MCLR Reset or a WDT Time-out Reset during

normal operation, the user can check the WRERR bit

and rewrite the location(s) as needed.

See Section 23.5 “Program Verification and Code

Protection” for details on code protection of Flash

program memory.

TABLE 6-2:

Name

REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Reset

Valueson

page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TBLPTRU

—

bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)

49

51

52

TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)

TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)

TABLAT

INTCON

Program Memory Table Latch

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

TMR0IF

INT0IF

RBIF

EECON2 EEPROM Control Register 2 (not a physical register)

EECON1

IPR2

EEPGD

OSCFIP

OSCFIF

OSCFIE

CFGS

CMIP

CMIF

CMIE

—

FREE

EEIP

EEIF

EEIE

WRERR

BCLIP

BCLIF

BCLIE

WREN

HLVDIP

HLVDIF

HLVDIE

WR

RD

TMR3IP

TMR3IF

TMR3IE

CCP2IP

CCP2IF

CCP2IE

PIR2

PIE2

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

Preliminary

DS39689E-page 81

PIC18F4321 FAMILY

NOTES:

DS39689E-page 82

Preliminary

PIC18F4321 FAMILY

The EECON1 register (Register 7-1) is the control

register for data and program memory access. Control

bit EEPGD determines if the access will be to program

or data EEPROM memory. When clear, operations will

access the data EEPROM memory. When set, program

memory is accessed.

7.0

DATA EEPROM MEMORY

The data EEPROM is a nonvolatile memory array,

separate from the data RAM and program memory, that

is used for long-term storage of program data. It is not

directly mapped in either the register file or program

memory space but is indirectly addressed through the

Special Function Registers (SFRs). The EEPROM is

readable and writable during normal operation over the

entire VDD range.

Control bit CFGS determines if the access will be to the

Configuration registers or to program memory/data

EEPROM memory. When set, subsequent operations

access Configuration registers. When CFGS is clear,

the EEPGD bit selects either program Flash or data

EEPROM memory.

Four SFRs are used to read and write to the data

EEPROM as well as the program memory. They are:

• EECON1

• EECON2

• EEDATA

• EEADR

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set in hardware when the WREN bit is set and cleared

when the internal programming timer expires and the

write operation is complete.

The data EEPROM allows byte read and write. When

interfacing to the data memory block, EEDATA holds

the 8-bit data for read/write and the EEADR register

holds the address of the EEPROM location being

accessed.

Note:

During normal operation, the WRERR bit

is read as ‘1’. This can indicate that a write

operation was prematurely terminated by

a

Reset, or

a write operation was

attempted improperly.

The EEPROM data memory is rated for high erase/write

cycle endurance. A byte write automatically erases the

location and writes the new data (erase-before-write).

The write time is controlled by an on-chip timer. It will

vary with voltage and temperature as well as from chip

to chip. Please refer to parameter D122 (Table 26-1 in

Section 26.0 “Electrical Characteristics”) for exact

limits.

The WR control bit initiates write operations. The bit

cannot be cleared, only set, in software; it is cleared in

hardware at the completion of the write operation.

Note:

The EEIF interrupt flag bit (PIR2<4>) is set

when the write is complete. It must be

cleared in software.

Control bits, RD and WR, start read and erase/write

operations, respectively. These bits are set by firmware

and cleared by hardware at the completion of the

operation.

7.1

EECON1 and EECON2 Registers

Access to the data EEPROM is controlled by two

registers: EECON1 and EECON2. These are the same

registers which control access to the program memory

and are used in a similar manner for the data

EEPROM.

The RD bit cannot be set when accessing program

memory (EEPGD = 1). Program memory is read using

table read instructions. See Section 6.1 “Table Reads

and Table Writes” regarding table reads.

The EECON2 register is not a physical register. It is

used exclusively in the memory write and erase

sequences. Reading EECON2 will read all ‘0’s.

Preliminary

DS39689E-page 83

PIC18F4321 FAMILY

REGISTER 7-1:

EECON1: DATA EEPROM CONTROL REGISTER 1

R/W-x

CFGS

U-0

—

R/W-0

FREE

R/W-x

R/W-0

WREN

R/S-0

WR

R/S-0

RD

EEPGD

WRERR

bit 7

bit 0

bit 7

bit 6

EEPGD: Flash Program or Data EEPROM Memory Select bit

1= Access Flash program memory

0= Access data EEPROM memory

CFGS: Flash Program/Data EEPROM or Configuration Select bit

1= Access Configuration registers

0= Access Flash program or data EEPROM memory

bit 5

bit 4

Unimplemented: Read as ‘0’

FREE: Flash Row Erase Enable bit

1= Erase the program memory row addressed by TBLPTR on the next WR command (cleared

by completion of erase operation)

0= Perform write only

bit 3

WRERR: Flash Program/Data EEPROM Error Flag bit

1= A write operation is prematurely terminated (any Reset during self-timed programming in

normal operation, or an improper write attempt)

0= The write operation completed

Note:

When a WRERR occurs, the EEPGD and CFGS bits are not cleared.

This allows tracing of the error condition.

bit 2

bit 1

WREN: Flash Program/Data EEPROM Write Enable bit

1= Allows write cycles to Flash program/data EEPROM

0= Inhibits write cycles to Flash program/data EEPROM

WR: Write Control bit

1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle

(The operation is self-timed and the bit is cleared by hardware once write is complete.

The WR bit can only be set (not cleared) in software.)

0= Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit

1= Initiates an EEPROM read

(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)

in software. RD bit cannot be set when EEPGD = 1or CFGS = 1.)

0= Does not initiate an EEPROM read

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39689E-page 84

Preliminary

PIC18F4321 FAMILY

Additionally, the WREN bit in EECON1 must be set to

enable writes. This mechanism prevents accidental

writes to data EEPROM due to unexpected code

execution (i.e., runaway programs). The WREN bit

should be kept clear at all times, except when updating

the EEPROM. The WREN bit is not cleared by

hardware.

7.2

Reading the Data EEPROM

Memory

To read a data memory location, the user must write the

address to the EEADR register, clear the EEPGD

control bit (EECON1<7>) and then set control bit, RD

(EECON1<0>). The data is available on the very next

instruction cycle; therefore, the EEDATA register can

be read by the next instruction. EEDATA will hold this

value until another read operation, or until it is written to

by the user (during a write operation).

After a write sequence has been initiated, EECON1,

EEADR and EEDATA cannot be modified. The WR bit

will be inhibited from being set unless the WREN bit is

set. The WREN bit must be set on a previous instruc-

tion. Both WR and WREN cannot be set with the same

instruction.

The basic process is shown in Example 7-1.

7.3

Writing to the Data EEPROM

Memory

At the completion of the write cycle, the WR bit is

cleared in hardware and the EEPROM Interrupt Flag

bit, EEIF, is set. The user may either enable this

interrupt, or poll this bit. EEIF must be cleared by

software.

To write an EEPROM data location, the address must

first be written to the EEADR register and the data

written to the EEDATA register. The sequence in

Example 7-2 must be followed to initiate the write cycle.

7.4

Write Verify

The write will not begin if this sequence is not exactly

followed (write 55h to EECON2, write 0AAh to

EECON2, then set WR bit) for each byte. It is strongly

recommended that interrupts be disabled during this

code segment.

Depending on the application, good programming

practice may dictate that the value written to the mem-

ory should be verified against the original value. This

should be used in applications where excessive writes

can stress bits near the specification limit.

EXAMPLE 7-1:

DATA EEPROM READ

MOVLW

MOVWF

BCF

BSF

DATA_EE_ADDR

EEADR

EECON1, EEPGD

EECON1, CFGS

EECON1, RD

EEDATA, W

;

; Data Memory Address to read

; Point to DATA memory

; Access EEPROM

; EEPROM Read

; W = EEDATA

MOVF

EXAMPLE 7-2:

DATA EEPROM WRITE

MOVLW

DATA_EE_ADDR

EEADR

DATA_EE_DATA

EEDATA

EECON1, EPGD

EECON1, CFGS

EECON1, WREN

;

MOVWF

MOVLW

MOVWF

BCF

BSF

; Data Memory Address to write

;

; Data Memory Value to write

; Point to DATA memory

; Access EEPROM

; Enable writes

BCF

INTCON, GIE

55h

EECON2

0AAh

EECON2

; Disable Interrupts

;

; Write 55h

;

; Write 0AAh

; Set WR bit to begin write

; Enable Interrupts

MOVLW

MOVWF

MOVLW

MOVWF

BSF

Required

Sequence

EECON1, WR

INTCON, GIE

BSF

; User code execution

BCF

EECON1, WREN

; Disable writes on write complete (EEIF set)

Preliminary

DS39689E-page 85

PIC18F4321 FAMILY

7.5

Operation During Code-Protect

7.7

Using the Data EEPROM

Data EEPROM memory has its own code-protect bits in

Configuration Words. External read and write

operations are disabled if code protection is enabled.

The data EEPROM is a high-endurance, byte

addressable array that has been optimized for the

storage of frequently changing data. Such data is

typically updated at least one time within the number of

writes defined by specification D124. If any location

storing data is not written at least this often, the data

EEPROM array must be refreshed. For this reason,

values that change infrequently, or not at all, should be

stored in Flash program memory.

The microcontroller itself can both read and write to the

internal data EEPROM, regardless of the state of the

code-protect Configuration bit. Refer to Section 23.0

“Special Features of the CPU” for additional

information.

A simple data EEPROM refresh routine is shown in

Example 7-3.

7.6

Protection Against Spurious Write

To protect against spurious EEPROM writes, various

mechanisms have been implemented. On power-up,

the WREN bit is cleared. In addition, writes to the

EEPROM are blocked during the Power-up Timer

period (TPWRT, parameter 33).

Note:

If data EEPROM is used to store either:

1) only constants (i.e., data that is

infrequently or never changed),

or

The write initiate sequence and the WREN bit together

help prevent an accidental write during Brown-out

Reset, power glitch or software malfunction.

2) only frequently changing data, then an

array refresh is likely not required but

should be verified by the user. If a mix-

ture of these types of data are being

stored, it is the responsibility of the

user to determine when an array

refresh is required.

EXAMPLE 7-3:

DATA EEPROM REFRESH ROUTINE

CLRF

BCF

BSF

EEADR

; Start at address 0

; Set for memory

EECON1, CFGS

EECON1, EEPGD

INTCON, GIE

EECON1, WREN

; Set for Data EEPROM

; Disable interrupts

; Enable writes

; Loop to refresh array

; Read current address

;

; Write 55h

;

; Write 0AAh

; Set WR bit to begin write

; Wait for write to complete

Loop

BSF

EECON1, RD

55h

EECON2

0AAh

EECON2

EECON1, WR

$-2

MOVLW

MOVWF

MOVLW

MOVWF

BSF

BTFSC

BRA

INCFSZ EEADR, F

; Increment address

BRA

LOOP

; Not zero, do it again

BCF

BSF

EECON1, WREN

INTCON, GIE

; Disable writes

; Enable interrupts

DS39689E-page 86

Preliminary

PIC18F4321 FAMILY

TABLE 7-1:

Name

REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Reset

Values

on page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

EEPROM Address Register

EEDATA EEPROM Data Register

EECON2 EEPROM Control Register 2 (not a physical register)

RBIE

TMR0IF

INT0IF

RBIF

49

51

52

EEADR

EECON1

IPR2

EEPGD

OSCFIP

OSCFIF

OSCFIE

CFGS

CMIP

CMIF

CMIE

—

FREE

EEIP

EEIF

EEIE

WRERR WREN

WR

RD

BCLIP

BCLIF

BCLIE

HLVDIP

HLVDIF

HLVDIE

TMR3IP

TMR3IF

TMR3IE

CCP2IP

CCP2IF

CCP2IE

PIR2

PIE2

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

Preliminary

DS39689E-page 87

PIC18F4321 FAMILY

NOTES:

DS39689E-page 88

Preliminary

PIC18F4321 FAMILY

EXAMPLE 8-1:

8 x 8 UNSIGNED

MULTIPLY ROUTINE

8.0

8.1

8 x 8 HARDWARE MULTIPLIER

Introduction

MOVF

MULWF

ARG1, W

ARG2

;

; ARG1 * ARG2 ->

; PRODH:PRODL

All PIC18 devices include an 8 x 8 hardware multiplier

as part of the ALU. The multiplier performs an unsigned

operation and yields a 16-bit result that is stored in the

product register pair, PRODH:PRODL. The multiplier’s

operation does not affect any flags in the STATUS

register.

EXAMPLE 8-2:

8 x 8 SIGNED MULTIPLY

ROUTINE

Making multiplication a hardware operation allows it to

be completed in a single instruction cycle. This has the

advantages of higher computational throughput and

reduced code size for multiplication algorithms and

allows the PIC18 devices to be used in many applica-

tions previously reserved for digital signal processors.

A comparison of various hardware and software

multiply operations, along with the savings in memory

and execution time, is shown in Table 8-1.

MOVF

MULWF

ARG1, W

ARG2

; ARG1 * ARG2 ->

; PRODH:PRODL

; Test Sign Bit

; PRODH = PRODH

BTFSC

SUBWF

ARG2, SB

PRODH, F

;

- ARG1

MOVF

BTFSC

SUBWF

ARG2, W

ARG1, SB

PRODH, F

; Test Sign Bit

; PRODH = PRODH

;

- ARG2

8.2

Operation

Example 8-1 shows the instruction sequence for an 8 x 8

unsigned multiplication. Only one instruction is required

when one of the arguments is already loaded in the

WREG register.

Example 8-2 shows the sequence to do an 8 x 8 signed

multiplication. To account for the sign bits of the

arguments, each argument’s Most Significant bit (MSb)

is tested and the appropriate subtractions are done.

TABLE 8-1:

Routine

PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS

Program

Memory

(Words)

Time

Cycles

(Max)

Multiply Method

@ 40 MHz @ 10 MHz @ 4 MHz

Without hardware multiply

Hardware multiply

13

1

69

1

6.9 μs

100 ns

9.1 μs

600 ns

24.2 μs

2.8 μs

25.4 μs

4.0 μs

27.6 μs

400 ns

36.4 μs

2.4 μs

69 μs

1 μs

8 x 8 unsigned

8 x 8 signed

Without hardware multiply

Hardware multiply

33

6

91

6

91 μs

6 μs

Without hardware multiply

Hardware multiply

21

28

52

35

242

28

254

40

96.8 μs

11.2 μs

102.6 μs

16.0 μs

242 μs

28 μs

254 μs

40 μs

16 x 16 unsigned

16 x 16 signed

Without hardware multiply

Hardware multiply

Preliminary

DS39689E-page 89

PIC18F4321 FAMILY

Example 8-3 shows the sequence to do a 16 x 16

unsigned multiplication. Equation 8-1 shows the

algorithm that is used. The 32-bit result is stored in four

registers (RES3:RES0).

EQUATION 8-2:

16 x 16 SIGNED

MULTIPLICATION

ALGORITHM

RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L

16

= (ARG1H • ARG2H • 2 ) +

(ARG1H • ARG2L • 2 ) +

(ARG1L • ARG2H • 2 ) +

(ARG1L • ARG2L) +

(-1 • ARG2H<7> • ARG1H:ARG1L • 2 ) +

(-1 • ARG1H<7> • ARG2H:ARG2L • 2

8

EQUATION 8-1:

16 x 16 UNSIGNED

MULTIPLICATION

ALGORITHM

8

16

RES3:RES0

=

ARG1H:ARG1L • ARG2H:ARG2L

)

16

(ARG1H • ARG2H • 2 ) +

8

(ARG1H • ARG2L • 2 ) +

8

(ARG1L • ARG2H • 2 ) +

EXAMPLE 8-4:

16 x 16 SIGNED

MULTIPLY ROUTINE

(ARG1L • ARG2L)

MOVF

MULWF

ARG1L, W

ARG2L

; ARG1L * ARG2L ->

; PRODH:PRODL

EXAMPLE 8-3:

16 x 16 UNSIGNED

MULTIPLY ROUTINE

MOVFF

PRODH, RES1

PRODL, RES0

;

MOVF

MULWF

ARG1L, W

ARG2L

;

; ARG1L * ARG2L->

MOVF

MULWF

ARG1H, W

ARG2H

; PRODH:PRODL

; ARG1H * ARG2H ->

; PRODH:PRODL

;

MOVFF

PRODH, RES1

PRODL, RES0

;

MOVFF

PRODH, RES3

PRODL, RES2

;

MOVF

MULWF

ARG1H, W

ARG2H

; ARG1H * ARG2H->

MOVF

MULWF

ARG1L, W

ARG2H

; PRODH:PRODL

;

; ARG1L * ARG2H ->

; PRODH:PRODL

;

; Add cross

; products

MOVFF

PRODH, RES3

PRODL, RES2

MOVF

ADDWF

MOVF

PRODL, W

RES1, F

PRODH, W

MOVF

MULWF

ARG1L, W

ARG2H

; ARG1L * ARG2H->

ADDWFC RES2, F

CLRF WREG

ADDWFC RES3, F

;

; PRODH:PRODL

;

; Add cross

; products

MOVF

ADDWF

MOVF

PRODL, W

RES1, F

PRODH, W

;

MOVF

MULWF

ARG1H, W

ARG2L

;

ADDWFC RES2, F

CLRF WREG

ADDWFC RES3, F

;

; ARG1H * ARG2L ->

; PRODH:PRODL

MOVF

ADDWF

MOVF

PRODL, W

RES1, F

PRODH, W

;

; Add cross

; products

MOVF

MULWF

ARG1H, W

ARG2L

;

; ARG1H * ARG2L->

ADDWFC RES2, F

CLRF WREG

ADDWFC RES3, F

;

; PRODH:PRODL

;

; Add cross

; products

;

MOVF

ADDWF

MOVF

ADDWFC RES2, F

CLRF WREG

ADDWFC RES3, F

PRODL, W

RES1, F

PRODH, W

;

BTFSS

BRA

MOVF

SUBWF

MOVF

ARG2H, 7

SIGN_ARG1

ARG1L, W

RES2

; ARG2H:ARG2L neg?

; no, check ARG1

;

ARG1H, W

Example 8-4 shows the sequence to do a 16 x 16

signed multiply. Equation 8-2 shows the algorithm

used. The 32-bit result is stored in four registers

(RES3:RES0). To account for the sign bits of the

arguments, the MSb for each argument pair is tested

and the appropriate subtractions are done.

SUBWFB RES3

SIGN_ARG1

BTFSS

BRA

ARG1H, 7

CONT_CODE

ARG2L, W

RES2

; ARG1H:ARG1L neg?

; no, done

;

MOVF

SUBWF

MOVF

ARG2H, W

SUBWFB RES3

;

CONT_CODE

:

DS39689E-page 90

Preliminary

PIC18F4321 FAMILY

When the IPEN bit is cleared (default state), the

interrupt priority feature is disabled and interrupts are

compatible with PIC^®mid-range devices. In

Compatibility mode, the interrupt priority bits for each

source have no effect. INTCON<6> is the PEIE bit,

which enables/disables all peripheral interrupt sources.

INTCON<7> is the GIE bit, which enables/disables all

interrupt sources. All interrupts branch to address

0008h in Compatibility mode.

9.0

INTERRUPTS

The PIC18F4321 family devices have multiple interrupt

sources and an interrupt priority feature that allows

most interrupt sources to be assigned a high priority

level or a low priority level. The high priority interrupt

vector is at 0008h and the low priority interrupt vector is

at 0018h. High priority interrupt events will interrupt any

low priority interrupts that may be in progress.

There are ten registers which are used to control

interrupt operation. These registers are:

When an interrupt is responded to, the global interrupt

enable bit is cleared to disable further interrupts. If the

IPEN bit is cleared, this is the GIE bit. If interrupt priority

levels are used, this will be either the GIEH or GIEL bit.

High priority interrupt sources can interrupt a low

priority interrupt. Low priority interrupts are not

processed while high priority interrupts are in progress.

• RCON

• INTCON

• INTCON2

• INTCON3

• PIR1, PIR2

• PIE1, PIE2

• IPR1, IPR2

The return address is pushed onto the stack and the

PC is loaded with the interrupt vector address (0008h

or 0018h). Once in the Interrupt Service Routine, the

source(s) of the interrupt can be determined by polling

the interrupt flag bits. The interrupt flag bits must be

cleared in software before re-enabling interrupts to

avoid recursive interrupts.

It is recommended that the Microchip header files

supplied with MPLAB^®IDE be used for the symbolic bit

names in these registers. This allows the assembler/

compiler to automatically take care of the placement of

these bits within the specified register.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine and sets the GIE bit (GIEH or GIEL

if priority levels are used), which re-enables interrupts.

In general, interrupt sources have three bits to control

their operation. They are:

For external interrupt events, such as the INT pins or

the PORTB input change interrupt, the interrupt latency

will be three to four instruction cycles. The exact

latency is the same for one or two-cycle instructions.

Individual interrupt flag bits are set, regardless of the

status of their corresponding enable bit or the GIE bit.

• Flag bit to indicate that an interrupt event

occurred

• Enable bit that allows program execution to

branch to the interrupt vector address when the

flag bit is set

• Priority bit to select high priority or low priority

Note:

Do not use the MOVFFinstruction to modify

any of the interrupt control registers while

any interrupt is enabled. Doing so may

cause erratic microcontroller behavior.

The interrupt priority feature is enabled by setting the

IPEN bit (RCON<7>). When interrupt priority is

enabled, there are two bits which enable interrupts

globally. Setting the GIEH bit (INTCON<7>) enables all

interrupts that have the priority bit set (high priority).

Setting the GIEL bit (INTCON<6>) enables all

interrupts that have the priority bit cleared (low priority).

When the interrupt flag, enable bit and appropriate

global interrupt enable bit are set, the interrupt will vec-

tor immediately to address 0008h or 0018h, depending

on the priority bit setting. Individual interrupts can be

disabled through their corresponding enable bits.

Preliminary

DS39689E-page 91

PIC18F4321 FAMILY

FIGURE 9-1:

PIC18 INTERRUPT LOGIC

Wake-up if in

Idle or Sleep modes

TMR0IF

TMR0IE

TMR0IP

RBIF

RBIE

RBIP

INT0IF

INT0IE

Interrupt to CPU

Vector to Location

0008h

INT1IF

INT1IE

INT1IP

INT2IF

INT2IE

INT2IP

SSPIF

SSPIE

SSPIP

GIE/GIEH

ADIF

ADIE

ADIP

IPEN

RCIF

RCIE

RCIP

PEIE/GIEL

IPEN

Additional Peripheral Interrupts

High Priority Interrupt Generation

Low Priority Interrupt Generation

SSPIF

SSPIE

SSPIP

Interrupt to CPU

Vector to Location

0018h

TMR0IF

TMR0IE

TMR0IP

ADIF

ADIE

ADIP

RBIF

RBIE

RBIP

RCIF

RCIE

RCIP

GIE/GIEH

PEIE/GIEL

INT1IF

INT1IE

INT1IP

Additional Peripheral Interrupts

INT2IF

INT2IE

INT2IP

DS39689E-page 92

Preliminary

PIC18F4321 FAMILY

9.1

INTCON Registers

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

interrupt enable bit. User software should

ensure the appropriate interrupt flag bits

are clear prior to enabling an interrupt.

This feature allows for software polling.

The INTCON registers are readable and writable

registers, which contain various enable, priority and

flag bits.

REGISTER 9-1:

INTCON: INTERRUPT CONTROL REGISTER

R/W-0

RBIE

R/W-0

INT0IF

R/W-x

RBIF

GIE/GIEH PEIE/GIEL TMR0IE

bit 7

INT0IE

TMR0IF

bit 0

bit 7

GIE/GIEH: Global Interrupt Enable bit

When IPEN = 0:

1= Enables all unmasked interrupts

0= Disables all interrupts

When IPEN = 1:

1= Enables all high priority interrupts

0= Disables all interrupts

bit 6

PEIE/GIEL: Peripheral Interrupt Enable bit

When IPEN = 0:

1= Enables all unmasked peripheral interrupts

0= Disables all peripheral interrupts

When IPEN = 1:

1= Enables all low priority peripheral interrupts

0= Disables all low priority peripheral interrupts

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

TMR0IE: TMR0 Overflow Interrupt Enable bit

1= Enables the TMR0 overflow interrupt

0= Disables the TMR0 overflow interrupt

INT0IE: INT0 External Interrupt Enable bit

1= Enables the INT0 external interrupt

0= Disables the INT0 external interrupt

RBIE: RB Port Change Interrupt Enable bit

1= Enables the RB port change interrupt

0= Disables the RB port change interrupt

TMR0IF: TMR0 Overflow Interrupt Flag bit

1= TMR0 register has overflowed (must be cleared in software)

0= TMR0 register did not overflow

INT0IF: INT0 External Interrupt Flag bit

1= The INT0 external interrupt occurred (must be cleared in software)

0= The INT0 external interrupt did not occur

RBIF: RB Port Change Interrupt Flag bit

1= At least one of the RB7:RB4 pins changed state (must be cleared in software)

0= None of the RB7:RB4 pins have changed state

Note:

A mismatch condition will continue to set this bit. Reading PORTB will end the

mismatch condition and allow the bit to be cleared.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39689E-page 93

PIC18F4321 FAMILY

REGISTER 9-2:

INTCON2: INTERRUPT CONTROL REGISTER 2

R/W-1

RBPU

R/W-1

U-0

—

R/W-1

U-0

—

R/W-1

RBIP

INTEDG0 INTEDG1 INTEDG2

TMR0IP

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

RBPU: PORTB Pull-up Enable bit

1= All PORTB pull-ups are disabled

0= PORTB pull-ups are enabled by individual port latch values

INTEDG0: External Interrupt 0 Edge Select bit

1= Interrupt on rising edge

0= Interrupt on falling edge

INTEDG1: External Interrupt 1 Edge Select bit

1= Interrupt on rising edge

0= Interrupt on falling edge

INTEDG2: External Interrupt 2 Edge Select bit

1= Interrupt on rising edge

0= Interrupt on falling edge

bit 3

bit 2

Unimplemented: Read as ‘0’

TMR0IP: TMR0 Overflow Interrupt Priority bit

1= High priority

0= Low priority

bit 1

bit 0

Unimplemented: Read as ‘0’

RBIP: RB Port Change Interrupt Priority bit

1= High priority

0= Low priority

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Note:

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state

of its corresponding enable bit or the global interrupt enable bit. User software

should ensure the appropriate interrupt flag bits are clear prior to enabling an

interrupt. This feature allows for software polling.

DS39689E-page 94

Preliminary

PIC18F4321 FAMILY

REGISTER 9-3:

INTCON3: INTERRUPT CONTROL REGISTER 3

R/W-1

U-0

—

R/W-0

U-0

—

R/W-0

INT2IF

R/W-0

INT1IF

INT2IP

INT1IP

INT2IE

INT1IE

bit 7

bit 0

bit 7

bit 6

INT2IP: INT2 External Interrupt Priority bit

1= High priority

0= Low priority

INT1IP: INT1 External Interrupt Priority bit

1= High priority

0= Low priority

bit 5

bit 4

Unimplemented: Read as ‘0’

INT2IE: INT2 External Interrupt Enable bit

1= Enables the INT2 external interrupt

0= Disables the INT2 external interrupt

bit 3

INT1IE: INT1 External Interrupt Enable bit

1= Enables the INT1 external interrupt

0= Disables the INT1 external interrupt

bit 2

bit 1

Unimplemented: Read as ‘0’

INT2IF: INT2 External Interrupt Flag bit

1= The INT2 external interrupt occurred (must be cleared in software)

0= The INT2 external interrupt did not occur

bit 0

INT1IF: INT1 External Interrupt Flag bit

1= The INT1 external interrupt occurred (must be cleared in software)

0= The INT1 external interrupt did not occur

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Note:

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state

of its corresponding enable bit or the global interrupt enable bit. User software

should ensure the appropriate interrupt flag bits are clear prior to enabling an

interrupt. This feature allows for software polling.

Preliminary

DS39689E-page 95

PIC18F4321 FAMILY

9.2

PIR Registers

Note 1: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE (INTCON<7>).

The PIR registers contain the individual flag bits for the

peripheral interrupts. Due to the number of peripheral

interrupt sources, there are two Peripheral Interrupt

Request (Flag) registers (PIR1 and PIR2).

2: User software should ensure the appropri-

ate interrupt flag bits are cleared prior to

enabling an interrupt and after servicing

that interrupt.

REGISTER 9-4:

PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1

R/W-0

PSPIF⁽¹⁾

bit 7

R/W-0

ADIF

R-0

R/W-0

SSPIF

R/W-0

RCIF

TXIF

CCP1IF

TMR2IF

TMR1IF

bit 0

bit 7

PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit⁽¹⁾

1= A read or a write operation has taken place (must be cleared in software)

0= No read or write has occurred

Note 1: This bit is unimplemented on 28-pin devices and will read as ‘0’.

ADIF: A/D Converter Interrupt Flag bit

bit 6

bit 5

bit 4

bit 3

bit 2

1= An A/D conversion completed (must be cleared in software)

0= The A/D conversion is not complete

RCIF: EUSART Receive Interrupt Flag bit

1= The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)

0= The EUSART receive buffer is empty

TXIF: EUSART Transmit Interrupt Flag bit

1= The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)

0= The EUSART transmit buffer is full

SSPIF: Master Synchronous Serial Port Interrupt Flag bit

1= The transmission/reception is complete (must be cleared in software)

0= Waiting to transmit/receive

CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1= A TMR1 register capture occurred (must be cleared in software)

0= No TMR1 register capture occurred

Compare mode:

1= A TMR1 register compare match occurred (must be cleared in software)

0= No TMR1 register compare match occurred

PWM mode:

Unused in this mode.

bit 1

bit 0

TMR2IF: TMR2-to-PR2 Match Interrupt Flag bit

1= TMR2-to-PR2 match occurred (must be cleared in software)

0= No TMR2-to-PR2 match occurred

TMR1IF: TMR1 Overflow Interrupt Flag bit

1= TMR1 register overflowed (must be cleared in software)

0= TMR1 register did not overflow

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39689E-page 96

Preliminary

PIC18F4321 FAMILY

REGISTER 9-5:

PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2

R/W-0

OSCFIF

bit 7

R/W-0

CMIF

U-0

—

R/W-0

EEIF

R/W-0

BCLIF

R/W-0

HLVDIF

TMR3IF

CCP2IF

bit 0

bit 7

bit 6

OSCFIF: Oscillator Fail Interrupt Flag bit

1= Device oscillator failed, clock input has changed to INTOSC (must be cleared in software)

0= Device clock operating

CMIF: Comparator Interrupt Flag bit

1= Comparator input has changed (must be cleared in software)

0= Comparator input has not changed

bit 5

bit 4

Unimplemented: Read as ‘0’

EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit

1= The write operation is complete (must be cleared in software)

0= The write operation is not complete or has not been started

bit 3

bit 2

BCLIF: Bus Collision Interrupt Flag bit

1= A bus collision occurred (must be cleared in software)

0= No bus collision occurred

HLVDIF: High/Low-Voltage Detect Interrupt Flag bit

1= A high/low-voltage condition occurred; direction determined by VDIRMAG bit

(HLVDCON<7>)

0= A high/low-voltage condition has not occurred

bit 1

bit 0

TMR3IF: TMR3 Overflow Interrupt Flag bit

1= TMR3 register overflowed (must be cleared in software)

0= TMR3 register did not overflow

CCP2IF: CCP2 Interrupt Flag bit

Capture mode:

1= A TMR1 register capture occurred (must be cleared in software)

0= No TMR1 register capture occurred

Compare mode:

1= A TMR1 register compare match occurred (must be cleared in software)

0= No TMR1 register compare match occurred

PWM mode:

Unused in this mode.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39689E-page 97

PIC18F4321 FAMILY

9.3

PIE Registers

The PIE registers contain the individual enable bits for

the peripheral interrupts. Due to the number of periph-

eral interrupt sources, there are two Peripheral Interrupt

Enable registers (PIE1 and PIE2). When IPEN = 0, the

PEIE bit must be set to enable any of these peripheral

interrupts.

REGISTER 9-6:

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0

PSPIE⁽¹⁾

bit 7

R/W-0

ADIE

R/W-0

RCIE

R/W-0

TXIE

R/W-0

SSPIE

R/W-0

TMR1IE

bit 0

CCP1IE

TMR2IE

bit 7

PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit⁽¹⁾

1= Enables the PSP read/write interrupt

0= Disables the PSP read/write interrupt

Note 1: This bit is unimplemented on 28-pin devices and will read as ‘0’.

ADIE: A/D Converter Interrupt Enable bit

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

1= Enables the A/D interrupt

0= Disables the A/D interrupt

RCIE: EUSART Receive Interrupt Enable bit

1= Enables the EUSART receive interrupt

0= Disables the EUSART receive interrupt

TXIE: EUSART Transmit Interrupt Enable bit

1= Enables the EUSART transmit interrupt

0= Disables the EUSART transmit interrupt

SSPIE: Master Synchronous Serial Port Interrupt Enable bit

1= Enables the MSSP interrupt

0= Disables the MSSP interrupt

CCP1IE: CCP1 Interrupt Enable bit

1= Enables the CCP1 interrupt

0= Disables the CCP1 interrupt

TMR2IE: TMR2-to-PR2 Match Interrupt Enable bit

1= Enables the TMR2-to-PR2 match interrupt

0= Disables the TMR2-to-PR2 match interrupt

TMR1IE: TMR1 Overflow Interrupt Enable bit

1= Enables the TMR1 overflow interrupt

0= Disables the TMR1 overflow interrupt

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39689E-page 98

Preliminary

PIC18F4321 FAMILY

REGISTER 9-7:

PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0

OSCFIE

bit 7

R/W-0

CMIE

U-0

—

R/W-0

EEIE

R/W-0

BCLIE

R/W-0

HLVDIE

TMR3IE

CCP2IE

bit 0

bit 7

bit 6

OSCFIE: Oscillator Fail Interrupt Enable bit

1= Enabled

0= Disabled

CMIE: Comparator Interrupt Enable bit

1= Enabled

0= Disabled

bit 5

bit 4

Unimplemented: Read as ‘0’

EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit

1= Enabled

0= Disabled

bit 3

bit 2

bit 1

bit 0

BCLIE: Bus Collision Interrupt Enable bit

1= Enabled

0= Disabled

HLVDIE: High/Low-Voltage Detect Interrupt Enable bit

1= Enabled

0= Disabled

TMR3IE: TMR3 Overflow Interrupt Enable bit

1= Enabled

0= Disabled

CCP2IE: CCP2 Interrupt Enable bit

1= Enabled

0= Disabled

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39689E-page 99

PIC18F4321 FAMILY

9.4

IPR Registers

The IPR registers contain the individual priority bits for

the peripheral interrupts. Due to the number of periph-

eral interrupt sources, there are two Peripheral Interrupt

Priority registers (IPR1 and IPR2). Using the priority bits

requires that the Interrupt Priority Enable (IPEN) bit be

set.

REGISTER 9-8:

IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1

R/W-1

PSPIP⁽¹⁾

bit 7

R/W-1

ADIP

R/W-1

RCIP

R/W-1

TXIP

R/W-1

SSPIP

R/W-1

TMR1IP

bit 0

CCP1IP

TMR2IP

bit 7

PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit⁽¹⁾

1= High priority

0= Low priority

Note 1: This bit is unimplemented on 28-pin devices and will read as ‘0’.

ADIP: A/D Converter Interrupt Priority bit

bit 6

bit 5

bit 4

1= High priority

0= Low priority

RCIP: EUSART Receive Interrupt Priority bit

1= High priority

0= Low priority

TXIP: EUSART Transmit Interrupt Priority bit

1= High priority

0= Low priority

bit 3

bit 2

bit 1

bit 0

SSPIP: Master Synchronous Serial Port Interrupt Priority bit

1= High priority

0= Low priority

CCP1IP: CCP1 Interrupt Priority bit

1= High priority

0= Low priority

TMR2IP: TMR2-to-PR2 Match Interrupt Priority bit

1= High priority

0= Low priority

TMR1IP: TMR1 Overflow Interrupt Priority bit

1= High priority

0= Low priority

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39689E-page 100

Preliminary

PIC18F4321 FAMILY

REGISTER 9-9:

IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2

R/W-1

OSCFIP

bit 7

R/W-1

CMIP

U-0

—

R/W-1

EEIP

R/W-1

BCLIP

R/W-1

HLVDIP

TMR3IP

CCP2IP

bit 0

bit 7

bit 6

OSCFIP: Oscillator Fail Interrupt Priority bit

1= High priority

0= Low priority

CMIP: Comparator Interrupt Priority bit

1= High priority

0= Low priority

bit 5

bit 4

Unimplemented: Read as ‘0’

EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit

1= High priority

0= Low priority

bit 3

bit 2

bit 1

bit 0

BCLIP: Bus Collision Interrupt Priority bit

1= High priority

0= Low priority

HLVDIP: High/Low-Voltage Detect Interrupt Priority bit

1= High priority

0= Low priority

TMR3IP: TMR3 Overflow Interrupt Priority bit

1= High priority

0= Low priority

CCP2IP: CCP2 Interrupt Priority bit

1= High priority

0= Low priority

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39689E-page 101

PIC18F4321 FAMILY

The operation of the SBOREN bit and the Reset flag

bits is discussed in more detail in Section 4.1 “RCON

Register”.

9.5

RCON Register

The RCON register contains flag bits which are used to

determine the cause of the last Reset or wake-up from

Idle or Sleep modes. RCON also contains the IPEN bit

which enables interrupt priorities.

REGISTER 9-10: RCON: RESET CONTROL REGISTER

R/W-0

IPEN

R/W-1⁽¹⁾

U-0

—

R/W-1

RI

R-1

TO

R-1

PD

R/W-0⁽²⁾

POR

R/W-0

BOR

SBOREN

bit 7

bit 0

bit 7

bit 6

IPEN: Interrupt Priority Enable bit

1= Enable priority levels on interrupts

0= Disable priority levels on interrupts (PIC16XXX Compatibility mode)

SBOREN: Software BOR Enable bit⁽¹⁾

For details of bit operation, see Register 4-1.

bit 5

bit 4

Unimplemented: Read as ‘0’

RI: RESETInstruction Flag bit

For details of bit operation, see Register 4-1.

TO: Watchdog Time-out Flag bit

bit 3

bit 2

bit 1

bit 0

For details of bit operation, see Register 4-1.

PD: Power-down Detection Flag bit

For details of bit operation, see Register 4-1.

POR: Power-on Reset Status bit⁽²⁾

For details of bit operation, see Register 4-1.

BOR: Brown-out Reset Status bit

For details of bit operation, see Register 4-1.

Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.

2: Actual Reset values are determined by device configuration and the nature of the

device Reset. See Register 4-1 for additional information.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39689E-page 102

Preliminary

PIC18F4321 FAMILY

9.6

INTn Pin Interrupts

9.7

TMR0 Interrupt

External interrupts on the RB0/INT0, RB1/INT1 and

RB2/INT2 pins are edge-triggered. If the corresponding

INTEDGx bit in the INTCON2 register is set (= 1), the

interrupt is triggered by a rising edge; if the bit is clear,

the trigger is on the falling edge. When a valid edge

appears on the RBx/INTx pin, the corresponding flag

bit, INTxF, is set. This interrupt can be disabled by

clearing the corresponding enable bit, INTxE. Flag bit,

INTxF, must be cleared in software in the Interrupt

Service Routine before re-enabling the interrupt.

In 8-bit mode (which is the default), an overflow in the

TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In

16-bit mode, an overflow in the TMR0H:TMR0L

register pair (FFFFh → 0000h) will set TMR0IF. The

interrupt can be enabled/disabled by setting/clearing

enable bit, TMR0IE (INTCON<5>). Interrupt priority for

Timer0 is determined by the value contained in the

interrupt priority bit, TMR0IP (INTCON2<2>). See

Section 11.0 “Timer0 Module” for further details on

the Timer0 module.

All external interrupts (INT0, INT1 and INT2) can wake-

up the processor from Idle or Sleep modes if bit INTxE

was set prior to going into those modes. If the Global

Interrupt Enable bit, GIE, is set, the processor will

branch to the interrupt vector following wake-up.

9.8

PORTB Interrupt-on-Change

An input change on PORTB<7:4> sets flag bit, RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit, RBIE (INTCON<3>).

Interrupt priority for PORTB interrupt-on-change is

determined by the value contained in the interrupt

priority bit, RBIP (INTCON2<0>).

Interrupt priority for INT1 and INT2 is determined by the

value contained in the interrupt priority bits, INT1IP

(INTCON3<6>) and INT2IP (INTCON3<7>). There is

no priority bit associated with INT0. It is always a high

priority interrupt source.

9.9

Context Saving During Interrupts

During interrupts, the return PC address is saved on

the stack. Additionally, the WREG, STATUS and BSR

registers are saved on the fast return stack. If a fast

return from interrupt is not used (see Section 5.3

“Data Memory Organization”), the user may need to

save the WREG, STATUS and BSR registers on entry

to the Interrupt Service Routine. Depending on the

user’s application, other registers may also need to be

saved. Example 9-1 saves and restores the WREG,

STATUS and BSR registers during an Interrupt Service

Routine.

EXAMPLE 9-1:

SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF

MOVFF

;

W_TEMP

STATUS, STATUS_TEMP

BSR, BSR_TEMP

; W_TEMP is in virtual bank

; STATUS_TEMP located anywhere

; BSR_TMEP located anywhere

; USER ISR CODE

;

MOVFF

MOVF

MOVFF

BSR_TEMP, BSR

W_TEMP, W

STATUS_TEMP, STATUS

; Restore BSR

; Restore WREG

; Restore STATUS

Preliminary

DS39689E-page 103

PIC18F4321 FAMILY

NOTES:

DS39689E-page 104

Preliminary

PIC18F4321 FAMILY

Reading the PORTA register reads the status of the

pins, whereas writing to it, will write to the port latch.

10.0 I/O PORTS

Depending on the device selected and features

enabled, there are up to five ports available. Some pins

of the I/O ports are multiplexed with an alternate

function from the peripheral features on the device. In

general, when a peripheral is enabled, that pin may not

be used as a general purpose I/O pin.

The Data Latch (LATA) register is also memory mapped.

Read-modify-write operations on the LATA register read

and write the latched output value for PORTA.

The RA4 pin is multiplexed with the Timer0 module

clock input and one of the comparator outputs to

become the RA4/T0CKI/C1OUT pin. Pins RA6 and

RA7 are multiplexed with the main oscillator pins. They

are enabled as oscillator or I/O pins by the selection of

the main oscillator in the Configuration register (see

Section 23.1 “Configuration Bits” for details). When

they are not used as port pins, RA6 and RA7 and their

associated TRIS and LAT bits are read as ‘0’.

Each port has three registers for its operation. These

registers are:

• TRIS register (data direction register)

• PORT register (reads the levels on the pins of the

device)

• LAT register (output latch)

The other PORTA pins are multiplexed with analog

inputs, the analog VREF+ and VREF- inputs and the

comparator voltage reference output. The operation of

pins RA3:RA0 and RA5 as A/D converter inputs is

selected by clearing or setting the control bits in the

ADCON1 register (A/D Control Register 1).

The Data Latch (LAT register) is useful for read-modify-

write operations on the value that the I/O pins are

driving.

A simplified model of a generic I/O port, without the

interfaces to other peripherals, is shown in Figure 10-1.

Pins RA0 through RA5 may also be used as comparator

inputs or outputs by setting the appropriate bits in the

CMCON register. To use RA3:RA0 as digital inputs, it is

also necessary to turn off the comparators.

FIGURE 10-1:

GENERIC I/O PORT

OPERATION

RD LAT

Note:

On a Power-on Reset, RA5 and RA3:RA0

are configured as analog inputs and read

as ‘0’. RA4 is configured as a digital input.

Data

Bus

D

Q

WR LAT

I/O pin⁽¹⁾

or

The RA4/T0CKI/C1OUT pin is a Schmitt Trigger input.

All other PORTA pins have TTL input levels and full

CMOS output drivers.

PORT

CK

Data Latch

D

Q

The TRISA register controls the direction of the PORTA

pins, even when they are being used as analog inputs.

The user must ensure the bits in the TRISA register are

maintained set when using them as analog inputs.

WR TRIS

RD TRIS

CK

TRIS Latch

Input

Buffer

EXAMPLE 10-1:

INITIALIZING PORTA

CLRF

PORTA

LATA

0Fh

; Initialize PORTA by

; clearing output

; data latches

; Alternate method

; to clear output

; data latches

Q

D

CLRF

EN

RD PORT

MOVLW

MOVWF

MOVLW

; Configure all A/D

ADCON1 ; for digital inputs

07h

CMCON

0CFh

Note 1: I/O pins have diode protection to VDD and VSS.

; Configure comparators

; for digital input

; Value used to

10.1 PORTA, TRISA and LATA Registers

; initialize data

; direction

PORTA is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISA. Setting a

TRISA bit (= 1) will make the corresponding PORTA pin

an input (i.e., put the corresponding output driver in a

high-impedance mode). Clearing a TRISA bit (= 0) will

make the corresponding PORTA pin an output (i.e., put

the contents of the output latch on the selected pin).

MOVWF

TRISA

; Set RA<7:6,3:0> as inputs

; RA<5:4> as outputs

Preliminary

DS39689E-page 105

PIC18F4321 FAMILY

TABLE 10-1: PORTA I/O SUMMARY

TRIS

Setting

I/O

Type

RA0/AN0

Function

I/O

Description

RA0

0

1

O

I

DIG LATA<0> data output; not affected by analog input.

TTL PORTA<0> data input; disabled when analog input enabled.

AN0

RA1

I

ANA A/D input channel 0 and Comparator C1- input. Default input

configuration on POR; does not affect digital output.

RA1/AN1

0

1

O

I

DIG LATA<1> data output; not affected by analog input.

TTL PORTA<1> data input; disabled when analog input enabled.

AN1

RA2

I

ANA A/D input channel 1 and Comparator C2- input. Default input

configuration on POR; does not affect digital output.

RA2/AN2/

VREF-/CVREF

0

1

O

I

DIG LATA<2> data output; not affected by analog input. Disabled when

CVREF output enabled.

TTL PORTA<2> data input. Disabled when analog functions enabled;

disabled when CVREF output enabled.

AN2

I

ANA A/D input channel 2 and Comparator C2+ input. Default input

configuration on POR; not affected by analog output.

VREF-

1

x

I

ANA A/D and comparator voltage reference low input.

CVREF

O

ANA Comparator voltage reference output. Enabling this feature disables

digital I/O.

RA3/AN3/VREF+

RA3

AN3

0

1

O

I

DIG LATA<3> data output; not affected by analog input.

TTL PORTA<3> data input; disabled when analog input enabled.

I

ANA A/D input channel 3 and Comparator C1+ input. Default input

configuration on POR.

VREF+

RA4

1

0

1

0

1

0

1

x

I

O

I

ANA A/D and comparator voltage reference high input.

DIG LATA<4> data output.

RA4/T0CKI/C1OUT

ST

PORTA<4> data input; default configuration on POR.

Timer0 clock input.

T0CKI

C1OUT

RA5

I

O

I

DIG Comparator 1 output; takes priority over port data.

RA5/AN4/SS/

HLVDIN/C2OUT

DIG LATA<5> data output; not affected by analog input.

TTL PORTA<5> data input; disabled when analog input enabled.

ANA A/D input channel 4. Default configuration on POR.

TTL Slave Select input for MSSP (MSSP module).

AN4

SS

I

HLVDIN

C2OUT

RA6

I

ANA High/Low-Voltage Detect external trip point input.

O

I

DIG Comparator 2 output; takes priority over port data.

OSC2/CLKO/RA6

OSC1/CLKI/RA7

DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.

TTL PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only.

ANA Main oscillator feedback output connection (XT, HS and LP modes).

OSC2

CLKO

O

DIG System cycle clock output (FOSC/4) in RC, INTIO1 and EC Oscillator

modes.

RA7

0

1

x

O

I

DIG LATA<7> data output. Disabled in external oscillator modes.

TTL PORTA<7> data input. Disabled in external oscillator modes.

ANA Main oscillator input connection.

OSC1

CLKI

I

ANA Main clock input connection.

Legend:

DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).

DS39689E-page 106

Preliminary

PIC18F4321 FAMILY

TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTA

RA7⁽¹⁾

RA6⁽¹⁾

RA5

RA4

RA3

RA2

RA1

RA0

52

51

LATA

LATA7⁽¹⁾LATA6⁽¹⁾PORTA Data Latch Register (Read and Write to Data Latch)

TRISA7⁽¹⁾TRISA6⁽¹⁾PORTA Data Direction Control Register

TRISA

ADCON1

CMCON

CVRCON

—

VCFG1

C2INV

CVRR

VCFG0

C1INV

PCFG3

CIS

PCFG2

CM2

PCFG1

CM1

PCFG0

CM0

C2OUT

CVREN

C1OUT

CVROE

CVRSS

CVR3

CVR2

CVR1

CVR0

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.

Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator

configuration; otherwise, they are read as ‘0’.

Preliminary

DS39689E-page 107

PIC18F4321 FAMILY

Four of the PORTB pins (RB7:RB4) have an interrupt-

on-change feature. Only pins configured as inputs can

cause this interrupt to occur (i.e., any RB7:RB4 pin

configured as an output is excluded from the interrupt-

on-change comparison). The input pins (of RB7:RB4)

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of RB7:RB4

are ORed together to generate the RB Port Change

Interrupt with Flag bit, RBIF (INTCON<0>).

10.2 PORTB, TRISB and LATB

Registers

PORTB is an 8-bit wide, bidirectional port. The

corresponding data direction register is TRISB. Setting

a TRISB bit (= 1) will make the corresponding PORTB

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISB bit (= 0)

will make the corresponding PORTB pin an output (i.e.,

put the contents of the output latch on the selected pin).

This interrupt can wake the device from Sleep mode or

any of the Idle modes. The user, in the Interrupt Service

Routine, can clear the interrupt in the following manner:

The Data Latch register (LATB) is also memory

mapped. Read-modify-write operations on the LATB

register read and write the latched output value for

PORTB.

a) Any read or write of PORTB (except with the

MOVFF (ANY), PORTBinstruction).

b) Clear flag bit, RBIF.

EXAMPLE 10-2:

INITIALIZING PORTB

A mismatch condition will continue to set flag bit, RBIF.

Reading PORTB will end the mismatch condition and

allow flag bit, RBIF, to be cleared.

CLRF

PORTB

LATB

07h

; Initialize PORTB by

; clearing output

; data latches

; Alternate method

; to clear output

; data latches

CLRF

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

MOVLW

MOVWF

; Set RB<4:0> as

ADCON1 ; digital I/O pins

; (required if config bit

; PBADEN is set)

; Value used to

; initialize data

; direction

; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

RB3 can be configured by the Configuration bit,

CCP2MX, as the alternate peripheral pin for the CCP2

module (CCP2MX = 0).

MOVLW

MOVWF

0CFh

TRISB

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is

performed by clearing bit, RBPU (INTCON2<7>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are

disabled on a Power-on Reset.

Note:

On a Power-on Reset, RB4:RB0 are

configured as analog inputs by default and

read as ‘0’; RB7:RB5 are configured as

digital inputs.

By clearing the Configuration bit,

PBADEN, RB4:RB0 will alternatively be

configured as digital inputs on POR.

DS39689E-page 108

Preliminary

PIC18F4321 FAMILY

TABLE 10-3: PORTB I/O SUMMARY

TRIS

Setting

I/O

Type

Function

I/O

Description

RB0/INT0/FLT0/

AN12

RB0

0

1

O

I

DIG

TTL

LATB<0> data output; not affected by analog input.

PORTB<0> data input; weak pull-up when RBPU bit is cleared.

(1)

Disabled when analog input enabled.

INT0

FLT0

AN12

RB1

1

0

1

I

ST

External interrupt 0 input.

Enhanced PWM Fault input (ECCP1 module); enabled in software.

(1)

I

ANA

DIG

TTL

A/D input channel 12.

RB1/INT1/AN10

RB2/INT2/AN8

RB3/AN9/CCP2

O

I

LATB<1> data output; not affected by analog input.

PORTB<1> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input enabled.

(1)

INT1

AN10

RB2

1

0

1

I

ST

ANA

DIG

TTL

External interrupt 1 input.

(1)

A/D input channel 10.

O

I

LATB<2> data output; not affected by analog input.

PORTB<2> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input enabled.

(1)

INT2

AN8

RB3

1

0

1

I

ST

ANA

DIG

TTL

External interrupt 2 input.

(1)

A/D input channel 8.

O

I

LATB<3> data output; not affected by analog input.

PORTB<3> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input enabled.

(1)

AN9

1

0

1

0

1

I

O

I

ANA

DIG

ST

A/D input channel 9.

(2)

CCP2

CCP2 compare and PWM output.

CCP2 capture input.

RB4/KBI0/AN11

RB5/KBI1/PGM

RB4

O

I

DIG

TTL

LATB<4> data output; not affected by analog input.

PORTB<4> data input; weak pull-up when RBPU bit is cleared.

Disabled when analog input enabled.

(1)

KBI0

AN11

RB5

1

0

1

x

I

TTL

ANA

DIG

TTL

ST

Interrupt-on-change pin.

(1)

A/D input channel 11.

O

I

LATB<5> data output.

PORTB<5> data input; weak pull-up when RBPU bit is cleared.

Interrupt-on-change pin.

KBI1

PGM

I

Single-Supply Programming mode entry (ICSP™). Enabled by LVP

Configuration bit; all other pin functions disabled.

RB6/KBI2/PGC

RB7/KBI3/PGD

RB6

0

1

x

0

1

x

O

I

DIG

TTL

ST

LATB<6> data output.

PORTB<6> data input; weak pull-up when RBPU bit is cleared.

Interrupt-on-change pin.

KBI2

PGC

RB7

I

(3)

I

Serial execution (ICSP™) clock input for ICSP and ICD operation.

O

I

DIG

TTL

DIG

ST

LATB<7> data output.

PORTB<7> data input; weak pull-up when RBPU bit is cleared.

Interrupt-on-change pin.

KBI3

PGD

I

(3)

O

I

Serial execution data output for ICSP and ICD operation.

(3)

Serial execution data input for ICSP and ICD operation.

Legend:

DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Note 1: Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default

when PBADEN is set and digital inputs when PBADEN is cleared.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1.

3: All other pin functions are disabled when ICSP or ICD are enabled.

Preliminary

DS39689E-page 109

PIC18F4321 FAMILY

TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

52

49

51

LATB

PORTB Data Latch Register (Read and Write to Data Latch)

PORTB Data Direction Control Register

TRISB

INTCON

INTCON2

INTCON3

ADCON1

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

—

TMR0IF

TMR0IP

—

INT0IF

—

RBIF

RBIP

RBPU

INT2IP

—

INTEDG0 INTEDG1 INTEDG2

INT1IP

—

INT2IE

VCFG0

INT1IE

PCFG3

INT2IF

PCFG1

INT1IF

PCFG0

VCFG1

PCFG2

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.

DS39689E-page 110

Preliminary

PIC18F4321 FAMILY

10.3 PORTC, TRISC and LATC

Registers

Note:

On a Power-on Reset, these pins are

configured as digital inputs.

PORTC is an 8-bit wide, bidirectional port. The

corresponding data direction register is TRISC. Setting

a TRISC bit (= 1) will make the corresponding PORTC

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISC bit (= 0)

will make the corresponding PORTC pin an output (i.e.,

put the contents of the output latch on the selected pin).

The contents of the TRISC register are affected by

peripheral overrides. Reading TRISC always returns

the current contents, even though a peripheral device

may be overriding one or more of the pins.

EXAMPLE 10-3:

INITIALIZING PORTC

CLRF

PORTC

; Initialize PORTC by

; clearing output

; data latches

The Data Latch register (LATC) is also memory

mapped. Read-modify-write operations on the LATC

register read and write the latched output value for

PORTC.

CLRF

LATC

; Alternate method

; to clear output

; data latches

PORTC is multiplexed with several peripheral functions

(Table 10-5). The pins have Schmitt Trigger input

buffers. RC1 is normally configured by Configuration

bit, CCP2MX, as the default peripheral pin of the CCP2

module (default/erased state, CCP2MX = 1).

MOVLW

MOVWF

0CFh

; Value used to

; initialize data

; direction

; Set RC<3:0> as inputs

; RC<5:4> as outputs

; RC<7:6> as inputs

TRISC

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTC pin. Some

peripherals override the TRIS bit to make a pin an output,

while other peripherals override the TRIS bit to make a

pin an input. The user should refer to the corresponding

peripheral section for additional information.

Preliminary

DS39689E-page 111

PIC18F4321 FAMILY

TABLE 10-5: PORTC I/O SUMMARY

TRIS

Setting

I/O

Type

Function

I/O

Description

RC0/T1OSO/

T13CKI

RC0

0

1

x

O

I

DIG

ST

LATC<0> data output.

PORTC<0> data input.

T1OSO

O

ANA

Timer1 oscillator output; enabled when Timer1 oscillator enabled.

Disables digital I/O.

T13CKI

RC1

1

0

1

x

I

O

I

ST

DIG

ST

Timer1/Timer3 counter input.

LATC<1> data output.

RC1/T1OSI/CCP2

PORTC<1> data input.

T1OSI

I

ANA

Timer1 oscillator input; enabled when Timer1 oscillator enabled.

Disables digital I/O.

(1)

CCP2

0

1

0

1

0

1

0

O

I

DIG

ST

CCP2 compare and PWM output; takes priority over port data.

CCP2 capture input.

RC2/CCP1/P1A

RC2

O

I

DIG

ST

LATC<2> data output.

PORTC<2> data input.

CCP1

O

I

DIG

ST

CCP1 compare or PWM output; takes priority over port data.

CCP1 capture input.

(2)

P1A

O

DIG

ECCP1 Enhanced PWM output, channel A. May be configured for

tri-state during Enhanced PWM shutdown events. Takes priority over

port data.

RC3/SCK/SCL

RC3

SCK

SCL

RC4

0

1

0

1

0

1

0

1

0

1

0

1

O

I

DIG

ST

LATC<3> data output.

PORTC<3> data input.

O

I

DIG

ST

SPI clock output (MSSP module); takes priority over port data.

SPI clock input (MSSP module).

2

O

I

DIG

I C™ clock output (MSSP module); takes priority over port data.

2

I C/SMB I C clock input (MSSP module); input type depends on module setting.

RC4/SDI/SDA

O

I

DIG

ST

LATC<4> data output.

PORTC<4> data input.

SDI

I

ST

SPI data input (MSSP module).

2

SDA

O

I

DIG

I C data output (MSSP module); takes priority over port data.

2

I C/SMB I C data input (MSSP module); input type depends on module setting.

RC5/SDO

RC5

O

I

DIG

ST

LATC<5> data output.

PORTC<5> data input.

SDO

RC6

O

I

DIG

ST

SPI data output (MSSP module); takes priority over port data.

LATC<6> data output.

RC6/TX/CK

PORTC<6> data input.

TX

CK

O

DIG

Asynchronous serial transmit data output (EUSART module);

takes priority over port data. User must configure as output.

1

O

DIG

Synchronous serial clock output (EUSART module); takes priority

over port data.

1

0

1

I

O

I

ST

DIG

ST

Synchronous serial clock input (EUSART module).

LATC<7> data output.

RC7/RX/DT

RC7

PORTC<7> data input.

RX

DT

I

ST

Asynchronous serial receive data input (EUSART module).

O

DIG

Synchronous serial data output (EUSART module); takes priority over

port data.

1

I

ST

Synchronous serial data input (EUSART module). User must

configure as an input.

Legend:

DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

I C/SMB = I C/SMBus input buffer; x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).

2

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. Alternate assignment is RB3.

2: Enhanced PWM output is available only on PIC18F4221/4321 devices.

DS39689E-page 112

Preliminary

PIC18F4321 FAMILY

TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTC

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

52

LATC

PORTC Data Latch Register (Read and Write to Data Latch)

PORTC Data Direction Control Register

TRISC

Preliminary

DS39689E-page 113

PIC18F4321 FAMILY

PORTD can also be configured as an 8-bit wide micro-

processor port (Parallel Slave Port) by setting control

bit, PSPMODE (TRISE<4>). In this mode, the input

buffers are TTL. See Section 10.6 “Parallel Slave

Port” for additional information on the Parallel Slave

Port (PSP).

10.4 PORTD, TRISD and LATD

Registers

Note:

PORTD is only available on 40/44-pin

devices.

PORTD is an 8-bit wide, bidirectional port. The

corresponding data direction register is TRISD. Setting

a TRISD bit (= 1) will make the corresponding PORTD

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISD bit (= 0)

will make the corresponding PORTD pin an output (i.e.,

put the contents of the output latch on the selected pin).

Note:

When the Enhanced PWM mode is used

with either dual or quad outputs, the PSP

functions of PORTD are automatically

disabled.

EXAMPLE 10-4:

INITIALIZING PORTD

CLRF

PORTD

; Initialize PORTD by

; clearing output

; data latches

; Alternate method

; to clear output

; data latches

; Value used to

; initialize data

; direction

The Data Latch register (LATD) is also memory

mapped. Read-modify-write operations on the LATD

register read and write the latched output value for

PORTD.

CLRF

LATD

All pins on PORTD are implemented with Schmitt Trigger

input buffers. Each pin is individually configurable as an

input or output.

MOVLW

MOVWF

0CFh

Three of the PORTD pins are multiplexed with outputs

P1B, P1C and P1D of the Enhanced CCP module. The

operation of these additional PWM output pins is

covered in greater detail in Section 16.0 “Enhanced

Capture/Compare/PWM (ECCP) Module”.

TRISD

; Set RD<3:0> as inputs

; RD<5:4> as outputs

; RD<7:6> as inputs

Note:

On a Power-on Reset, these pins are

configured as digital inputs.

DS39689E-page 114

Preliminary

PIC18F4321 FAMILY

TABLE 10-7: PORTD I/O SUMMARY

TRIS

Setting

I/O

Type

Function

I/O

Description

RD0/PSP0

RD0

0

1

x

0

1

x

0

1

x

0

1

x

0

1

x

0

1

x

0

O

I

DIG

ST

LATD<0> data output.

PORTD<0> data input.

PSP0

RD1

O

I

DIG

TTL

DIG

ST

PSP read data output (LATD<0>); takes priority over port data.

PSP write data input.

RD1/PSP1

RD2/PSP2

RD3/PSP3

RD4/PSP4

RD5/PSP5/P1B

O

I

LATD<1> data output.

PORTD<1> data input.

PSP1

RD2

O

I

DIG

TTL

DIG

ST

PSP read data output (LATD<1>); takes priority over port data.

PSP write data input.

O

I

LATD<2> data output.

PORTD<2> data input.

PSP2

RD3

O

I

DIG

TTL

DIG

ST

PSP read data output (LATD<2>); takes priority over port data.

PSP write data input.

O

I

LATD<3> data output.

PORTD<3> data input.

PSP3

RD4

O

I

DIG

TTL

DIG

ST

PSP read data output (LATD<3>); takes priority over port data.

PSP write data input.

O

I

LATD<4> data output.

PORTD<4> data input.

PSP4

RD5

O

I

DIG

TTL

DIG

ST

PSP read data output (LATD<4>); takes priority over port data.

PSP write data input.

O

I

LATD<5> data output.

PORTD<5> data input.

PSP5

P1B

O

I

DIG

TTL

DIG

PSP read data output (LATD<5>); takes priority over port data.

PSP write data input.

O

ECCP1 Enhanced PWM output, channel B; takes priority over port and

PSP data. May be configured for tri-state during Enhanced PWM

shutdown events.

RD6/PSP6/P1C

RD6

PSP6

P1C

0

1

x

0

O

I

DIG

ST

LATD<6> data output.

PORTD<6> data input.

O

I

DIG

TTL

DIG

PSP read data output (LATD<6>); takes priority over port data.

PSP write data input.

O

ECCP1 Enhanced PWM output, channel C; takes priority over port and

PSP data. May be configured for tri-state during Enhanced PWM

shutdown events.

RD7/PSP7/P1D

RD7

PSP7

P1D

0

1

x

0

O

I

DIG

ST

LATD<7> data output.

PORTD<7> data input.

O

I

DIG

TTL

DIG

PSP read data output (LATD<7>); takes priority over port data.

PSP write data input.

O

ECCP1 Enhanced PWM output, channel D; takes priority over port and

PSP data. May be configured for tri-state during Enhanced PWM

shutdown events.

Legend:

DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; x= Don’t care

(TRIS bit does not affect port direction or is overridden for this option).

Preliminary

DS39689E-page 115

PIC18F4321 FAMILY

TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTD

LATD

RD7

RD6

RD5

RD4

RD3

RD2

RD1

RD0

52

51

PORTD Data Latch Register (Read and Write to Data Latch)

PORTD Data Direction Control Register

TRISD

TRISE

IBF

OBF

IBOV

PSPMODE

—

TRISE2

TRISE1

TRISE0

CCP1CON

P1M1

P1M0

DC1B1

DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.

DS39689E-page 116

Preliminary

PIC18F4321 FAMILY

The fourth pin of PORTE (MCLR/VPP/RE3) is an input

only pin. Its operation is controlled by the MCLRE Con-

figuration bit. When selected as a port pin (MCLRE = 0),

it functions as a digital input only pin; as such, it does not

have TRIS or LAT bits associated with its operation.

Otherwise, it functions as the device’s Master Clear

input. In either configuration, RE3 also functions as the

programming voltage input during programming.

10.5 PORTE, TRISE and LATE

Registers

Depending on the particular PIC18F4321 family device

selected, PORTE is implemented in two different ways.

For 40/44-pin devices, PORTE is a 4-bit wide port.

Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/

AN7) are individually configurable as inputs or outputs.

These pins have Schmitt Trigger input buffers. When

selected as analog inputs, these pins will read as ‘0’.

Note:

On a Power-on Reset, RE3 is enabled as

digital input only if Master Clear

functionality is disabled.

a

The corresponding data direction register is TRISE.

Setting a TRISE bit (= 1) will make the corresponding

PORTE pin an input (i.e., put the corresponding output

driver in a high-impedance mode). Clearing a TRISE bit

(= 0) will make the corresponding PORTE pin an output

(i.e., put the contents of the output latch on the selected

pin).

EXAMPLE 10-5:

INITIALIZING PORTE

CLRF

PORTE

LATE

0Ah

; Initialize PORTE by

; clearing output

; data latches

; Alternate method

; to clear output

; data latches

CLRF

TRISE controls the direction of the RE pins, even when

they are being used as analog inputs. The user must

make sure to keep the pins configured as inputs when

using them as analog inputs.

MOVLW

MOVWF

MOVLW

; Configure A/D

ADCON1 ; for digital inputs

03h

; Value used to

; initialize data

; direction

; Set RE<0> as inputs

; RE<1> as outputs

; RE<2> as inputs

Note:

On a Power-on Reset, RE2:RE0 are

configured as analog inputs.

MOVWF

TRISE

The upper four bits of the TRISE register also control

the operation of the Parallel Slave Port. Their operation

is explained in Register 10-1.

10.5.1

PORTE IN 28-PIN DEVICES

The Data Latch register (LATE) is also memory

mapped. Read-modify-write operations on the LATE

register, read and write the latched output value for

PORTE.

For 28-pin devices, PORTE is only available when

Master Clear functionality is disabled (MCLRE = 0). In

these cases, PORTE is a single bit, input only port

comprised of RE3 only. The pin operates as previously

described.

Preliminary

DS39689E-page 117

PIC18F4321 FAMILY

REGISTER 10-1: TRISE REGISTER (40/44-PIN DEVICES ONLY)

R-0

IBF

R-0

R/W-0

IBOV

R/W-0

U-0

—

R/W-1

OBF

PSPMODE

TRISE2

TRISE1

TRISE0

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

IBF: Input Buffer Full Status bit

1= A word has been received and waiting to be read by the CPU

0= No word has been received

OBF: Output Buffer Full Status bit

1= The output buffer still holds a previously written word

0= The output buffer has been read

IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)

1= A write occurred when a previously input word has not been read (must be cleared in software)

0= No overflow occurred

PSPMODE: Parallel Slave Port Mode Select bit

1= Parallel Slave Port mode

0= General purpose I/O mode

bit 3

bit 2

Unimplemented: Read as ‘0’

TRISE2: RE2 Direction Control bit

1= Input

0= Output

bit 1

bit 0

TRISE1: RE1 Direction Control bit

1= Input

0= Output

TRISE0: RE0 Direction Control bit

1= Input

0= Output

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39689E-page 118

Preliminary

PIC18F4321 FAMILY

TABLE 10-9: PORTE I/O SUMMARY

TRIS

Setting

I/O

Type

Function

I/O

Description

RE0/RD/AN5

RE0

0

1

0

1

0

1

—

O

I

DIG

ST

LATE<0> data output; not affected by analog input.

PORTE<0> data input; disabled when analog input enabled.

PSP read enable input (PSP enabled).

RD

I

TTL

ANA

DIG

ST

AN5

RE1

I

A/D input channel 5; default input configuration on POR.

LATE<1> data output; not affected by analog input.

PORTE<1> data input; disabled when analog input enabled.

PSP write enable input (PSP enabled).

RE1/WR/AN6

RE2/CS/AN7

MCLR/VPP/RE3

O

I

WR

AN6

RE2

I

TTL

ANA

DIG

ST

I

A/D input channel 6; default input configuration on POR.

LATE<2> data output; not affected by analog input.

PORTE<2> data input; disabled when analog input enabled.

PSP write enable input (PSP enabled).

O

I

CS

AN7

I

TTL

ANA

ST

I

A/D input channel 7; default input configuration on POR.

(1)

MCLR

I

External Master Clear input; enabled when MCLRE Configuration bit

is set.

VPP

—

I

ANA

ST

High-voltage detection; used for ICSP™ mode entry detection. Always

available, regardless of pin mode.

(2)

RE3

—

PORTE<3> data input; enabled when MCLRE Configuration bit is

clear.

Legend:

DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;

x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Note 1: RE3 is available on both 28-pin and 40/44-pin devices. All other PORTE pins are only implemented on 40/44-pin devices.

2: RE3 does not have a corresponding TRIS bit to control data direction.

TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Reset

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Values

on page

PORTE

LATE⁽²⁾

—

RE3^(1,2)

—

RE2

RE1

RE0

52

PORTE Data Latch Register

(Read and Write to Data Latch)

TRISE

IBF

—

OBF

—

IBOV

PSPMODE

VCFG0

—

TRISE2

PCFG2

TRISE1

PCFG1

TRISE0

PCFG0

52

51

ADCON1

VCFG1

PCFG3

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.

Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).

2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are

implemented only when PORTE is implemented (i.e., 40/44-pin devices).

Preliminary

DS39689E-page 119

PIC18F4321 FAMILY

The timing for the control signals in Write and Read

modes is shown in Figure 10-3 and Figure 10-4,

respectively.

10.6 Parallel Slave Port

Note:

The Parallel Slave Port is only available on

40/44-pin devices.

FIGURE 10-2:

PORTD AND PORTE

BLOCK DIAGRAM

(PARALLEL SLAVE PORT)

In addition to its function as a general I/O port, PORTD

can also operate as an 8-bit wide Parallel Slave Port

(PSP) or microprocessor port. PSP operation is

controlled by the 4 upper bits of the TRISE register

(Register 10-1). Setting control bit, PSPMODE

(TRISE<4>), enables PSP operation as long as the

Enhanced CCP module is not operating in Dual Output

or Quad Output PWM mode. In Slave mode, the port is

asynchronously readable and writable by the external

world.

One bit of PORTD

Data Bus

D

Q

RDx pin

WR LATD

or

WR PORTD

CK

Data Latch

TTL

The PSP can directly interface to an 8-bit micro-

processor data bus. The external microprocessor can

read or write the PORTD latch as an 8-bit latch. Setting

the control bit, PSPMODE, enables the PORTE I/O

pins to become control inputs for the microprocessor

port. When set, port pin RE0 is the RD input, RE1 is the

WR input and RE2 is the CS (Chip Select) input. For

this functionality, the corresponding data direction bits

of the TRISE register (TRISE<2:0>) must be config-

ured as inputs (set). The A/D port configuration bits,

PFCG3:PFCG0 (ADCON1<3:0>), must also be set to a

value in the range of ‘1010’ through ‘1111’.

Q

D

RD PORTD

RD LATD

EN

Set Interrupt Flag

PSPIF (PIR1<7>)

A write to the PSP occurs when both the CS and WR

lines are first detected low and ends when either are

detected high. The PSPIF and IBF flag bits are both set

when the write ends.

PORTE Pins

Read

RD

CS

WR

TTL

Chip Select

TTL

A read from the PSP occurs when both the CS and RD

lines are first detected low. The data in PORTD is read

out and the OBF bit is clear. If the user writes new data

to PORTD to set OBF, the data is immediately read out;

however, the OBF bit is not set.

Write

TTL

Note:

I/O pins have diode protection to VDD and VSS.

When either the CS or RD lines are detected high, the

PORTD pins return to the input state and the PSPIF bit

is set. User applications should wait for PSPIF to be set

before servicing the PSP. When this happens, the IBF

and OBF bits can be polled and the appropriate action

taken.

DS39689E-page 120

Preliminary

PIC18F4321 FAMILY

FIGURE 10-3:

PARALLEL SLAVE PORT WRITE WAVEFORMS

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

CS

WR

RD

PORTD<7:0>

IBF

OBF

PSPIF

FIGURE 10-4:

PARALLEL SLAVE PORT READ WAVEFORMS

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

CS

WR

RD

PORTD<7:0>

IBF

OBF

PSPIF

TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT

Reset

Valueson

page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTD

LATD

RD7

RD6

RD5

RD4

RD3

RD2

RD1

RD0

52

PORTD Data Latch Register (Read and Write to Data Latch)

PORTD Data Direction Control Register

TRISD

PORTE

LATE

—

RE3

—

RE2

RE1

RE0

PORTE Data Latch Register

(Read and Write to Data Latch)

TRISE

INTCON

PIR1

IBF

OBF

IBOV

PSPMODE

INT0IE

TXIF

—

TRISE2

TMR0IF

CCP1IF

CCP1IE

CCP1IP

PCFG2

TRISE1

INT0IF

TRISE0

RBIF

52

49

52

51

GIE/GIEH PEIE/GIEL TMR0IF

RBIE

(1)

PSPIF

PSPIE

PSPIP

—

ADIF

ADIE

ADIP

—

RCIF

RCIE

SSPIF

SSPIE

SSPIP

PCFG3

TMR2IF

TMR2IE

TMR2IP

PCFG1

TMR1IF

TMR1IE

TMR1IP

PCFG0

(1)

PIE1

TXIE

IPR1

RCIP

TXIP

ADCON1

VCFG1

VCFG0

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.

Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’.

Preliminary

DS39689E-page 121

PIC18F4321 FAMILY

NOTES:

DS39689E-page 122

Preliminary

PIC18F4321 FAMILY

The T0CON register (Register 11-1) controls all

aspects of the module’s operation, including the

prescale selection. It is both readable and writable.

11.0 TIMER0 MODULE

The Timer0 module incorporates the following features:

• Software selectable operation as a timer or

counter in both 8-bit or 16-bit modes

A simplified block diagram of the Timer0 module in 8-bit

mode is shown in Figure 11-1. Figure 11-2 shows a

simplified block diagram of the Timer0 module in 16-bit

mode.

• Readable and writable registers

• Dedicated 8-bit, software programmable

prescaler

• Selectable clock source (internal or external)

• Edge select for external clock

• Interrupt-on-overflow

REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER

R/W-1

TMR0ON

bit 7

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

T0PS2

R/W-1

T0PS1

R/W-1

T0PS0

T08BIT

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

TMR0ON: Timer0 On/Off Control bit

1= Enables Timer0

0= Stops Timer0

T08BIT: Timer0 8-Bit/16-Bit Control bit

1= Timer0 is configured as an 8-bit timer/counter

0= Timer0 is configured as a 16-bit timer/counter

T0CS: Timer0 Clock Source Select bit

1= Transition on T0CKI pin

0= Internal instruction cycle clock (CLKO)

T0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on T0CKI pin

0= Increment on low-to-high transition on T0CKI pin

PSA: Timer0 Prescaler Assignment bit

1= TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.

0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.

bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits

111= 1:256 Prescale value

110= 1:128 Prescale value

101= 1:64 Prescale value

100= 1:32 Prescale value

011= 1:16 Prescale value

010= 1:8 Prescale value

001= 1:4 Prescale value

000= 1:2 Prescale value

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39689E-page 123

PIC18F4321 FAMILY

internal phase clock (TOSC). There is a delay between

synchronization and the onset of incrementing the

timer/counter.

11.1 Timer0 Operation

Timer0 can operate as either a timer or a counter; the

mode is selected with the T0CS bit (T0CON<5>). In

Timer mode (T0CS = 0), the module increments on

every clock by default unless a different prescaler value

is selected (see Section 11.3 “Prescaler”). If the

TMR0 register is written to, the increment is inhibited

for the following two instruction cycles. The user can

work around this by writing an adjusted value to the

TMR0 register.

11.2 Timer0 Reads and Writes in

16-Bit Mode

TMR0H is not the actual high byte of Timer0 in 16-bit

mode; it is actually a buffered version of the real high

byte of Timer0 which is not directly readable nor

writable (refer to Figure 11-2). TMR0H is updated with

the contents of the high byte of Timer0 during a read of

TMR0L. This provides the ability to read all 16 bits of

Timer0 without having to verify that the read of the high

and low byte were valid, due to a rollover between

successive reads of the high and low byte.

The Counter mode is selected by setting the T0CS bit

(= 1). In this mode, Timer0 increments either on every

rising or falling edge of pin RA4/T0CKI. The increment-

ing edge is determined by the Timer0 Source Edge

Select bit, T0SE (T0CON<4>); clearing this bit selects

the rising edge. Restrictions on the external clock input

are discussed below.

Similarly, a write to the high byte of Timer0 must also

take place through the TMR0H Buffer register. The high

byte is updated with the contents of TMR0H when a

write occurs to TMR0L. This allows all 16 bits of Timer0

to be updated at once.

An external clock source can be used to drive Timer0;

however, it must meet certain requirements to ensure

that the external clock can be synchronized with the

FIGURE 11-1:

TIMER0 BLOCK DIAGRAM (8-BIT MODE)

FOSC/4

0

1

0

Sync with

Internal

Clocks

Set

TMR0L

8

TMR0IF

on Overflow

Programmable

Prescaler

T0CKI pin

(2 TOSC Delay)

T0SE

T0CS

3

T0PS2:T0PS0

PSA

8

Internal Data Bus

Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

FIGURE 11-2:

TIMER0 BLOCK DIAGRAM (16-BIT MODE)

FOSC/4

0

1

Sync with

Internal

Clocks

Set

TMR0

High Byte

1

TMR0L

TMR0IF

Programmable

Prescaler

on Overflow

T0CKI pin

0

8

(2 TOSC Delay)

T0SE

T0CS

3

Read TMR0L

Write TMR0L

T0PS2:T0PS0

PSA

8

TMR0H

8

Internal Data Bus

Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

DS39689E-page 124

Preliminary

PIC18F4321 FAMILY

11.3.1

SWITCHING PRESCALER

ASSIGNMENT

11.3 Prescaler

An 8-bit counter is available as a prescaler for the Timer0

module. The prescaler is not directly readable or writable;

its value is set by the PSA and T0PS2:T0PS0 bits

(T0CON<3:0>) which determine the prescaler

assignment and prescale ratio.

The prescaler assignment is fully under software

control and can be changed “on-the-fly” during program

execution.

11.4 Timer0 Interrupt

Clearing the PSA bit assigns the prescaler to the

Timer0 module. When it is assigned, prescale values

from 1:2 through 1:256 in power-of-2 increments are

selectable.

The TMR0 interrupt is generated when the TMR0

register overflows from FFh to 00h in 8-bit mode, or

from FFFFh to 0000h in 16-bit mode. This overflow sets

the TMR0IF flag bit. The interrupt can be masked by

clearing the TMR0IE bit (INTCON<5>). Before re-

enabling the interrupt, the TMR0IF bit must be cleared

in software by the Interrupt Service Routine.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF TMR0, MOVWF

TMR0, BSF TMR0, etc.) clear the prescaler count.

Note:

Writing to TMR0 when the prescaler is

assigned to Timer0 will clear the prescaler

count but will not change the prescaler

assignment.

Since Timer0 is shut down in Sleep mode, the TMR0

interrupt cannot awaken the processor from Sleep.

TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TMR0L

Timer0 Register Low Byte

Timer0 Register High Byte

50

49

50

52

TMR0H

INTCON

T0CON

TRISA

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

T0SE

RA4

RBIE

PSA

RA3

TMR0IF

T0PS2

RA2

INT0IF

T0PS1

RA1

RBIF

T0PS0

RA0

TMR0ON

RA7⁽¹⁾

T08BIT

RA6⁽¹⁾

T0CS

RA5

Legend: Shaded cells are not used by Timer0.

Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary

oscillator modes. When disabled, these bits read as ‘0’.

Preliminary

DS39689E-page 125

PIC18F4321 FAMILY

NOTES:

DS39689E-page 126

Preliminary

PIC18F4321 FAMILY

A simplified block diagram of the Timer1 module is

shown in Figure 12-1. A block diagram of the module’s

operation in Read/Write mode is shown in Figure 12-2.

12.0 TIMER1 MODULE

The Timer1 timer/counter module incorporates these

features:

The module incorporates its own low-power oscillator

to provide an additional clocking option. The Timer1

oscillator can also be used as a low-power clock source

for the microcontroller in power-managed operation.

• Software selectable operation as a 16-bit timer or

counter

• Readable and writable 8-bit registers (TMR1H

and TMR1L)

Timer1 can also be used to provide Real-Time Clock

(RTC) functionality to applications with only a minimal

addition of external components and code overhead.

• Selectable clock source (internal or external) with

device clock or Timer1 oscillator internal options

• Interrupt-on-overflow

Timer1 is controlled through the T1CON Control

register (Register 12-1). It also contains the Timer1

Oscillator Enable bit (T1OSCEN). Timer1 can be

enabled or disabled by setting or clearing control bit,

TMR1ON (T1CON<0>).

• Reset on CCP Special Event Trigger

• Device clock status flag (T1RUN)

REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0

RD16

R-0

R/W-0

T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 0

bit 7

bit 6

RD16: 16-Bit Read/Write Mode Enable bit

1= Enables register read/write of TImer1 in one 16-bit operation

0= Enables register read/write of Timer1 in two 8-bit operations

T1RUN: Timer1 System Clock Status bit

1= Device clock is derived from Timer1 oscillator

0= Device clock is derived from another source

bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11= 1:8 Prescale value

10= 1:4 Prescale value

01= 1:2 Prescale value

00= 1:1 Prescale value

bit 3

bit 2

T1OSCEN: Timer1 Oscillator Enable bit

1= Timer1 oscillator is enabled

0= Timer1 oscillator is shut off

The oscillator inverter and feedback resistor are turned off to eliminate power drain.

T1SYNC: Timer1 External Clock Input Synchronization Select bit

When TMR1CS = 1:

1= Do not synchronize external clock input

0= Synchronize external clock input

When TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1

bit 0

TMR1CS: Timer1 Clock Source Select bit

1= External clock from pin RC0/T1OSO/T13CKI (on the rising edge)

0= Internal clock (FOSC/4)

TMR1ON: Timer1 On bit

1= Enables Timer1

0= Stops Timer1

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39689E-page 127

PIC18F4321 FAMILY

cycle (Fosc/4). When the bit is set, Timer1 increments

on every rising edge of the Timer1 external clock input

or the Timer1 oscillator, if enabled.

12.1 Timer1 Operation

Timer1 can operate in one of these modes:

• Timer

When Timer1 is enabled, the RC1/T1OSI and RC0/

T1OSO/T13CKI pins become inputs. This means the

values of TRISC<1:0> are ignored and the pins are

read as ‘0’.

• Synchronous Counter

• Asynchronous Counter

The operating mode is determined by the clock select

bit, TMR1CS (T1CON<1>). When TMR1CS is cleared

(= 0), Timer1 increments on every internal instruction

FIGURE 12-1:

TIMER1 BLOCK DIAGRAM

Timer1 Oscillator

Timer1 Clock Input

1

0

On/Off

1

T1OSO/T13CKI

T1OSI

Synchronize

Detect

Prescaler

1, 2, 4, 8

FOSC/4

Internal

Clock

0

2

Peripheral Clock

T1OSCEN⁽¹⁾

T1CKPS1:T1CKPS0

T1SYNC

Timer1

On/Off

TMR1CS

TMR1ON

Set

TMR1

High Byte

Clear TMR1

(CCP Special Event Trigger)

TMR1L

TMR1IF

on Overflow

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

FIGURE 12-2:

TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

Timer1 Oscillator

Timer1 Clock Input

1

0

1

0

T1OSO/T13CKI

T1OSI

Synchronize

Detect

Prescaler

1, 2, 4, 8

FOSC/4

Internal

Clock

2

Peripheral Clock

T1OSCEN⁽¹⁾

T1CKPS1:T1CKPS0

T1SYNC

Timer1

On/Off

TMR1CS

TMR1ON

Set

TMR1IF

on Overflow

TMR1

High Byte

Clear TMR1

(CCP Special Event Trigger)

TMR1L

8

Read TMR1L

Write TMR1L

8

TMR1H

8

Internal Data Bus

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

DS39689E-page 128

Preliminary

PIC18F4321 FAMILY

TABLE 12-1: CAPACITOR SELECTION FOR

THE TIMER OSCILLATOR

12.2 Timer1 16-Bit Read/Write Mode

Timer1 can be configured for 16-bit reads and writes

(see Figure 12-2). When the RD16 control bit

(T1CON<7>) is set, the address for TMR1H is mapped

to a buffer register for the high byte of Timer1. A read

from TMR1L will load the contents of the high byte of

Timer1 into the Timer1 high byte buffer. This provides

the user with the ability to accurately read all 16 bits of

Timer1 without having to determine whether a read of

the high byte, followed by a read of the low byte, has

become invalid due to a rollover between reads.

Osc Type

Freq

C1

C2

LP

32 kHz

27 pF⁽¹⁾

Note 1: Microchip suggests these values as a

starting point in validating the oscillator

circuit.

2: Higher capacitance increases the stability

of the oscillator but also increases the

start-up time.

A write to the high byte of Timer1 must also take place

through the TMR1H Buffer register. The Timer1 high

byte is updated with the contents of TMR1H when a

write occurs to TMR1L. This allows a user to write all

16 bits to both the high and low bytes of Timer1 at once.

3: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

appropriate

values

of

external

components.

The high byte of Timer1 is not directly readable or

writable in this mode. All reads and writes must take

place through the Timer1 High Byte Buffer register.

Writes to TMR1H do not clear the Timer1 prescaler.

The prescaler is only cleared on writes to TMR1L.

4: Capacitor values are for design guidance

only.

12.3.1

USING TIMER1 AS A

CLOCK SOURCE

The Timer1 oscillator is also available as a clock source

in power-managed modes. By setting the clock select

bits, SCS1:SCS0 (OSCCON<1:0>), to ‘01’, the device

switches to SEC_RUN mode; both the CPU and

peripherals are clocked from the Timer1 oscillator. If the

IDLEN bit (OSCCON<7>) is cleared and a SLEEP

instruction is executed, the device enters SEC_IDLE

mode. Additional details are available in Section 3.0

“Power-Managed Modes”.

12.3 Timer1 Oscillator

An on-chip crystal oscillator circuit is incorporated

between pins T1OSI (input) and T1OSO (amplifier

output). It is enabled by setting the Timer1 Oscillator

Enable bit, T1OSCEN (T1CON<3>). The oscillator is a

low-power circuit rated for 32 kHz crystals. It will

continue to run during all power-managed modes. The

circuit for a typical LP oscillator is shown in Figure 12-3.

Table 12-1 shows the capacitor selection for the Timer1

oscillator.

Whenever the Timer1 oscillator is providing the clock

source, the Timer1 system clock status flag, T1RUN

(T1CON<6>), is set. This can be used to determine the

controller’s current clocking mode. It can also indicate

the clock source being currently used by the Fail-Safe

Clock Monitor. If the Clock Monitor is enabled and the

Timer1 oscillator fails while providing the clock, polling

the T1RUN bit will indicate whether the clock is being

provided by the Timer1 oscillator or another source.

The user must provide a software time delay to ensure

proper start-up of the Timer1 oscillator.

FIGURE 12-3:

EXTERNALCOMPONENTS

FOR THE TIMER1

LP OSCILLATOR

C1

27 pF

PIC18FXXXX

12.3.2

LOW-POWER TIMER1 OPTION

T1OSI

The Timer1 oscillator can operate at two distinct levels

of power consumption based on device configuration.

When the LPT1OSC Configuration bit is set, the Timer1

oscillator operates in a low-power mode. When

LPT1OSC is not set, Timer1 operates at a higher power

level. Power consumption for a particular mode is

relatively constant, regardless of the device’s operating

mode. The default Timer1 configuration is the higher

power mode.

XTAL

32.768 kHz

T1OSO

C2

27 pF

Note:

See the Notes with Table 12-1 for additional

information about capacitor selection.

As the low-power Timer1 mode tends to be more

sensitive to interference, high noise environments may

cause some oscillator instability. The low-power option is,

therefore, best suited for low noise applications where

power conservation is an important design consideration.

Preliminary

DS39689E-page 129

PIC18F4321 FAMILY

12.3.3

TIMER1 OSCILLATOR LAYOUT

CONSIDERATIONS

12.5 Resetting Timer1 Using the CCP

Special Event Trigger

The Timer1 oscillator circuit draws very little power

during operation. Due to the low-power nature of the

oscillator, it may also be sensitive to rapidly changing

signals in close proximity.

If either of the CCP modules is configured to use Timer1

and generate a Special Event Trigger in Compare mode

(CCP1M3:CCP1M0 or CCP2M3:CCP2M0 = 1011), this

signal will reset Timer1. The trigger from CCP2 will also

start an A/D conversion if the A/D module is enabled

(see Section 15.3.4 “Special Event Trigger” for more

information).

The oscillator circuit, shown in Figure 12-3, should be

located as close as possible to the microcontroller.

There should be no circuits passing within the oscillator

circuit boundaries other than VSS or VDD.

The module must be configured as either a timer or a

synchronous counter to take advantage of this feature.

When used this way, the CCPRH:CCPRL register pair

effectively becomes a period register for Timer1.

If a high-speed circuit must be located near the

oscillator (such as the CCP1 pin in Output Compare or

PWM mode, or the primary oscillator using the OSC2

pin), a grounded guard ring around the oscillator circuit,

as shown in Figure 12-4, may be helpful when used on

a single-sided PCB or in addition to a ground plane.

If Timer1 is running in Asynchronous Counter mode,

this Reset operation may not work.

In the event that a write to Timer1 coincides with a

Special Event Trigger, the write operation will take

precedence.

FIGURE 12-4:

OSCILLATOR CIRCUIT

WITH GROUNDED

GUARD RING

Note:

The Special Event Triggers from the

CCP2 module will not set the TMR1IF

interrupt flag bit (PIR1<0>).

VDD

VSS

12.6 Using Timer1 as a Real-Time Clock

OSC1

OSC2

Adding an external LP oscillator to Timer1 (such as the

one described in Section 12.3 “Timer1 Oscillator”)

gives users the option to include RTC functionality to

their applications. This is accomplished with an

inexpensive watch crystal to provide an accurate time

base and several lines of application code to calculate

the time. When operating in Sleep mode and using a

battery or supercapacitor as a power source, it can

completely eliminate the need for a separate RTC

device and battery backup.

RC0

RC1

RC2

The application code routine, RTCisr, shown in

Example 12-1, demonstrates a simple method to

increment a counter at one-second intervals using an

Interrupt Service Routine. Incrementing the TMR1

register pair to overflow, triggers the interrupt and calls

the routine, which increments the seconds counter by

one. Additional counters for minutes and hours are

incremented as the previous counter overflow.

Note: Not drawn to scale.

12.4 Timer1 Interrupt

The TMR1 register pair (TMR1H:TMR1L) increments

from 0000h to FFFFh and rolls over to 0000h. The

Timer1 interrupt, if enabled, is generated on overflow

which is latched in interrupt flag bit, TMR1IF

(PIR1<0>). This interrupt can be enabled or disabled

by setting or clearing the Timer1 Interrupt Enable bit,

TMR1IE (PIE1<0>).

Since the register pair is 16 bits wide, counting up to

overflow the register directly from a 32.768 kHz clock

would take 2 seconds. To force the overflow at the

required one-second intervals, it is necessary to

preload it. The simplest method is to set the MSb of

TMR1H with a BSF instruction. Note that the TMR1L

register is never preloaded or altered. Doing so may

introduce cumulative errors over many cycles.

For this method to be accurate, Timer1 must operate in

Asynchronous mode and the Timer1 overflow interrupt

must be enabled (PIE1<0> = 1), as shown in the

routine, RTCinit. The Timer1 oscillator must also be

enabled and running at all times.

DS39689E-page 130

Preliminary

PIC18F4321 FAMILY

EXAMPLE 12-1:

IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE

RTCinit

MOVLW

MOVWF

CLRF

80h

TMR1H

TMR1L

; Preload TMR1 register pair

; for 1 second overflow

MOVLW

MOVWF

CLRF

b’00001111’

T1CON

secs

; Configure for external clock,

; Asynchronous operation, external oscillator

; Initialize timekeeping registers

;

CLRF

mins

MOVLW

MOVWF

BSF

.12

hours

PIE1, TMR1IE

; Enable Timer1 interrupt

RETURN

RTCisr

BSF

BCF

INCF

MOVLW

CPFSGT

RETURN

CLRF

TMR1H, 7

PIR1, TMR1IF

secs, F

.59

; Preload for 1 sec overflow

; Clear interrupt flag

; Increment seconds

; 60 seconds elapsed?

secs

; No, done

secs

mins, F

.59

; Clear seconds

; Increment minutes

; 60 minutes elapsed?

INCF

MOVLW

CPFSGT

RETURN

CLRF

mins

; No, done

mins

hours, F

.23

; clear minutes

; Increment hours

; 24 hours elapsed?

INCF

MOVLW

CPFSGT

RETURN

CLRF

hours

; No, done

; Reset hours

; Done

hours

RETURN

TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF

CCP1IF

CCP1IE

CCP1IP

INT0IF

TMR2IF

TMR2IE

TMR2IP

RBIF

49

52

50

PSPIF⁽¹⁾

PSPIE⁽¹⁾

PSPIP⁽¹⁾

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

TMR1IF

TMR1IE

TMR1IP

PIE1

TXIE

TXIP

IPR1

TMR1L

TMR1H

T1CON

Timer1 Register Low Byte

Timer1 Register High Byte

RD16

T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

Legend: Shaded cells are not used by the Timer1 module.

Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’.

Preliminary

DS39689E-page 131

PIC18F4321 FAMILY

NOTES:

DS39689E-page 132

Preliminary

PIC18F4321 FAMILY

13.1 Timer2 Operation

13.0 TIMER2 MODULE

In normal operation, TMR2 is incremented from 00h on

each clock (FOSC/4). A 4-bit counter/prescaler on the

clock input gives direct input, divide-by-4 and divide-by-

16 prescale options. These are selected by the prescaler

control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The

value of TMR2 is compared to that of the period register,

PR2, on each clock cycle. When the two values match,

the comparator generates a match signal as the timer

output. This signal also resets the value of TMR2 to 00h

on the next cycle and drives the output counter/

postscaler (see Section 13.2 “Timer2 Interrupt”).

The Timer2 timer module incorporates the following

features:

• 8-bit timer and period registers (TMR2 and PR2,

respectively)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4 and

1:16)

• Software programmable postscaler (1:1 through

1:16)

• Interrupt on TMR2-to-PR2 match

• Optional use as the shift clock for the MSSP

module

The TMR2 and PR2 registers are both directly readable

and writable. The TMR2 register is cleared on any

device Reset, while the PR2 register initializes at FFh.

Both the prescaler and postscaler counters are cleared

on the following events:

The module is controlled through the T2CON register

(Register 13-1), which enables or disables the timer

and configures the prescaler and postscaler. Timer2

can be shut off by clearing control bit, TMR2ON

(T2CON<2>), to minimize power consumption.

• a write to the TMR2 register

• a write to the T2CON register

A simplified block diagram of the module is shown in

Figure 13-1.

• any device Reset (Power-on Reset, MCLR Reset,

Watchdog Timer Reset or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER

U-0

—

R/W-0

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 0

bit 7

Unimplemented: Read as ‘0’

bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits

0000= 1:1 Postscale

0001= 1:2 Postscale

•

1111= 1:16 Postscale

bit 2

TMR2ON: Timer2 On bit

1= Timer2 is on

0= Timer2 is off

bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00= Prescaler is 1

01= Prescaler is 4

1x= Prescaler is 16

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39689E-page 133

PIC18F4321 FAMILY

13.2 Timer2 Interrupt

13.3 Timer2 Output

Timer2 can also generate an optional device interrupt.

The Timer2 output signal (TMR2-to-PR2 match)

provides the input for the 4-bit output counter/

postscaler. This counter generates the TMR2 match

interrupt flag which is latched in TMR2IF (PIR1<1>).

The interrupt is enabled by setting the TMR2 Match

Interrupt Enable bit, TMR2IE (PIE1<1>).

The unscaled output of TMR2 is available primarily to

the CCP modules, where it is used as a time base for

operations in PWM mode.

Timer2 can be optionally used as the shift clock source

for the MSSP module operating in SPI mode.

Additional information is provided in Section 17.0

“Master Synchronous Serial Port (MSSP) Module”.

A range of 16 postscale options (from 1:1 through 1:16

inclusive) can be selected with the postscaler control

bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>).

FIGURE 13-1:

TIMER2 BLOCK DIAGRAM

4

1:1 to 1:16

Set TMR2IF

Postscaler

T2OUTPS3:T2OUTPS0

2

TMR2 Output

T2CKPS1:T2CKPS0

(to PWM or MSSP)

TMR2/PR2

Match

Reset

TMR2

1:1, 1:4, 1:16

Prescaler

PR2

FOSC/4

Comparator

8

Internal Data Bus

TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF

CCP1IF

CCP1IE

CCP1IP

INT0IF

TMR2IF

TMR2IE

TMR2IP

RBIF

49

52

50

PIR1

PSPIF⁽¹⁾

PSPIE⁽¹⁾

PSPIP⁽¹⁾

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

TMR1IF

TMR1IE

TMR1IP

PIE1

TXIE

TXIP

IPR1

TMR2

T2CON

PR2

Timer2 Register

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0

Timer2 Period Register

—

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.

Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’.

DS39689E-page 134

Preliminary

PIC18F4321 FAMILY

A simplified block diagram of the Timer3 module is

shown in Figure 14-1. A block diagram of the module’s

operation in Read/Write mode is shown in Figure 14-2.

14.0 TIMER3 MODULE

The Timer3 timer/counter module incorporates these

features:

The Timer3 module is controlled through the T3CON

register (Register 14-1). It also selects the clock source

options for the CCP modules (see Section 15.1.1

“CCP Modules and Timer Resources” for more

information).

• Software selectable operation as a 16-bit timer or

counter

• Readable and writable 8-bit registers (TMR3H

and TMR3L)

• Selectable clock source (internal or external) with

device clock or Timer1 oscillator internal options

• Interrupt-on-overflow

• Module Reset on CCP Special Event Trigger

REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER

R/W-0

RD16

R/W-0

T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON

bit 0

bit 7

RD16: 16-Bit Read/Write Mode Enable bit

1= Enables register read/write of Timer3 in one 16-bit operation

0= Enables register read/write of Timer3 in two 8-bit operations

bit 6,3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits

1x= Timer3 is the capture/compare clock source for the CCP modules

01= Timer3 is the capture/compare clock source for CCP2;

Timer1 is the capture/compare clock source for CCP1

00= Timer1 is the capture/compare clock source for the CCP modules

bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits

11= 1:8 Prescale value

10= 1:4 Prescale value

01= 1:2 Prescale value

00= 1:1 Prescale value

bit 2

T3SYNC: Timer3 External Clock Input Synchronization Control bit

(Not usable if the device clock comes from Timer1/Timer3.)

When TMR3CS = 1:

1= Do not synchronize external clock input

0= Synchronize external clock input

When TMR3CS = 0:

This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.

bit 1

bit 0

TMR3CS: Timer3 Clock Source Select bit

1= External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first

falling edge)

0= Internal clock (FOSC/4)

TMR3ON: Timer3 On bit

1= Enables Timer3

0= Stops Timer3

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39689E-page 135

PIC18F4321 FAMILY

The operating mode is determined by the clock select

bit, TMR3CS (T3CON<1>). When TMR3CS is cleared

(= 0), Timer3 increments on every internal instruction

cycle (FOSC/4). When the bit is set, Timer3 increments

on every rising edge of the Timer1 external clock input

or the Timer1 oscillator, if enabled.

14.1 Timer3 Operation

Timer3 can operate in one of three modes:

• Timer

• Synchronous Counter

• Asynchronous Counter

As with Timer1, the RC1/T1OSI and RC0/T1OSO/

T13CKI pins become inputs when the Timer1 oscillator

is enabled. This means the values of TRISC<1:0> are

ignored and the pins are read as ‘0’.

FIGURE 14-1:

TIMER3 BLOCK DIAGRAM (8-BIT READ/WRITE MODE)

Timer1 Oscillator

Timer1 Clock Input

1

0

1

0

T1OSO/T13CKI

T1OSI

Synchronize

Detect

Prescaler

1, 2, 4, 8

FOSC/4

Internal

Clock

2

Sleep Input

T1OSCEN⁽¹⁾

T3CKPS1:T3CKPS0

T3SYNC

Timer3

On/Off

TMR3CS

TMR3ON

CCP1/CCP2 Special Event Trigger

CCP1/CCP2 Select from T3CON<6,3>

Clear TMR3

Set

TMR3

High Byte

TMR3L

TMR3IF

on Overflow

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

FIGURE 14-2:

TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

Timer1 Oscillator

Timer1 Clock Input

1

0

1

0

T13CKI/T1OSO

T1OSI

Synchronize

Detect

Prescaler

1, 2, 4, 8

FOSC/4

Internal

Clock

2

Sleep Input

T1OSCEN⁽¹⁾

T3CKPS1:T3CKPS0

T3SYNC

Timer3

On/Off

TMR3CS

TMR3ON

CCP1/CCP2 Special Event Trigger

CCP1/CCP2 Select from T3CON<6,3>

Clear TMR3

Set

TMR3IF

on Overflow

TMR3

High Byte

TMR3L

8

Read TMR1L

Write TMR1L

8

TMR3H

8

Internal Data Bus

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

DS39689E-page 136

Preliminary

PIC18F4321 FAMILY

14.2 Timer3 16-Bit Read/Write Mode

14.4 Timer3 Interrupt

Timer3 can be configured for 16-bit reads and writes

(see Figure 14-2). When the RD16 control bit

(T3CON<7>) is set, the address for TMR3H is mapped

to a buffer register for the high byte of Timer3. A read

from TMR3L will load the contents of the high byte of

Timer3 into the Timer3 High Byte Buffer register. This

provides the user with the ability to accurately read all

16 bits of Timer1 without having to determine whether

a read of the high byte, followed by a read of the low

byte, has become invalid due to a rollover between

reads.

The TMR3 register pair (TMR3H:TMR3L) increments

from 0000h to FFFFh and overflows to 0000h. The

Timer3 interrupt, if enabled, is generated on overflow

and is latched in interrupt flag bit, TMR3IF (PIR2<1>).

This interrupt can be enabled or disabled by setting or

clearing the Timer3 Interrupt Enable bit, TMR3IE

(PIE2<1>).

14.5 Resetting Timer3 Using the CCP

Special Event Trigger

If either of the CCP modules is configured to use

Timer3 and to generate a Special Event Trigger

A write to the high byte of Timer3 must also take place

through the TMR3H Buffer register. The Timer3 high

byte is updated with the contents of TMR3H when a

write occurs to TMR3L. This allows a user to write all

16 bits to both the high and low bytes of Timer3 at once.

in Compare

mode

(CCP1M3:CCP1M0

or

CCP2M3:CCP2M0 = 1011), this signal will reset

Timer3. It will also start an A/D conversion if the A/D

module is enabled (see Section 15.3.4 “Special

Event Trigger” for more information).

The high byte of Timer3 is not directly readable or

writable in this mode. All reads and writes must take

place through the Timer3 High Byte Buffer register.

The module must be configured as either a timer or

synchronous counter to take advantage of this feature.

When used this way, the CCPR2H:CCPR2L register

pair effectively becomes a period register for Timer3.

Writes to TMR3H do not clear the Timer3 prescaler.

The prescaler is only cleared on writes to TMR3L.

If Timer3 is running in Asynchronous Counter mode,

the Reset operation may not work.

14.3 Using the Timer1 Oscillator as the

Timer3 Clock Source

In the event that a write to Timer3 coincides with a

Special Event Trigger from a CCP module, the write will

take precedence.

The Timer1 internal oscillator may be used as the clock

source for Timer3. The Timer1 oscillator is enabled by

setting the T1OSCEN (T1CON<3>) bit. To use it as the

Timer3 clock source, the TMR3CS bit must also be set.

As previously noted, this also configures Timer3 to

increment on every rising edge of the oscillator source.

Note:

The Special Event Triggers from the

CCP2 module will not set the TMR3IF

interrupt flag bit (PIR2<1>).

The Timer1 oscillator is described in Section 12.0

“Timer1 Module”.

TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR2

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

EEIF

RBIE

BCLIF

BCLIE

BCLIP

TMR0IF

HLVDIF

HLVDIE

HLVDIP

INT0IF

TMR3IF

TMR3IE

TMR3IP

RBIF

49

52

51

50

51

OSCFIF

OSCFIE

OSCFIP

CMIF

CMIE

CMIP

—

CCP2IF

CCP2IE

CCP2IP

PIE2

EEIE

EEIP

IPR2

TMR3L

TMR3H

T1CON

T3CON

Timer3 Register Low Byte

Timer3 Register High Byte

RD16

T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.

Preliminary

DS39689E-page 137

PIC18F4321 FAMILY

NOTES:

DS39689E-page 138

Preliminary

PIC18F4321 FAMILY

The Capture and Compare operations described in this

chapter apply to all standard and Enhanced CCP

modules.

15.0 CAPTURE/COMPARE/PWM

(CCP) MODULES

PIC18F4321 family devices all have two CCP

(Capture/Compare/PWM) modules. Each module con-

tains a 16-bit register which can operate as a 16-bit

Capture register, a 16-bit Compare register or a PWM

Master/Slave Duty Cycle register.

Note: Throughout this section and Section 16.0

“Enhanced Capture/Compare/PWM (ECCP)

Module”, references to the register and bit

names for CCP modules are referred to

generically by the use of ‘x’ or ‘y’ in place

of the specific module number. Thus,

“CCPxCON” might refer to the control regis-

ter for CCP1, CCP2 or ECCP1. “CCPxCON”

is used throughout these sections to refer to

the module control register, regardless of

whether the CCP module is a standard or

Enhanced implementation.

In 28-pin devices, the two standard CCP modules

(CCP1 and CCP2) operate as described in this

chapter. In 40/44-pin devices, CCP1 is implemented

as an Enhanced CCP module with standard Capture

and Compare modes and Enhanced PWM modes.

The ECCP implementation is discussed in

Section 16.0 “Enhanced Capture/Compare/PWM

(ECCP) Module”.

REGISTER 15-1: CCPxCON REGISTER (CCP2 MODULE, CCP1 MODULE IN 28-PIN DEVICES)

U-0

—

U-0

—

R/W-0

DCxB1

DCxB0

CCPxM3 CCPxM2 CCPxM1 CCPxM0

bit 0

bit 7

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs

(DCx9:DCx2) of the duty cycle are found in CCPRxL.

bit 3-0 CCPxM3:CCPxM0: CCPx Module Mode Select bits

0000= Capture/Compare/PWM disabled (resets CCP module)

0001= Reserved

0010= Compare mode, toggle output on match (CCPxIF bit is set)

0011= Reserved

0100= Capture mode, every falling edge

0101= Capture mode, every rising edge

0110= Capture mode, every 4th rising edge

0111= Capture mode, every 16th rising edge

1000= Compare mode: initialize CCP pin low; on compare match, force CCP pin high

(CCPxIF bit is set)

1001= Compare mode: initialize CCP pin high; on compare match, force CCP pin low

(CCPxIF bit is set)

1010= Compare mode: generate software interrupt on compare match (CCPxIF bit is set,

CCP pin reflects I/O state)

1011= Compare mode: trigger special event, reset timer, start A/D conversion on

CCPx match (CCPxIF bit is set)

11xx= PWM mode

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39689E-page 139

PIC18F4321 FAMILY

The assignment of a particular timer to a module is

determined by the Timer to CCP enable bits in the

T3CON register (Register 14-1). Both modules may be

active at any given time and may share the same timer

resource if they are configured to operate in the same

mode (Capture/Compare or PWM) at the same time. The

interactions between the two modules are summarized in

Figure 15-1 and Figure 15-2. In Timer1 in Asynchronous

Counter mode, the capture operation will not work.

15.1 CCP Module Configuration

Each Capture/Compare/PWM module is associated

with a control register (generically, CCPxCON) and a

data register (CCPRx). The data register, in turn, is

comprised of two 8-bit registers: CCPRxL (low byte)

and CCPRxH (high byte). All registers are both

readable and writable.

15.1.1

CCP MODULES AND TIMER

RESOURCES

15.1.2

CCP2 PIN ASSIGNMENT

The CCP modules utilize Timers 1, 2 or 3, depending

on the mode selected. Timer1 and Timer3 are available

to modules in Capture or Compare modes, while

Timer2 is available for modules in PWM mode.

The pin assignment for CCP2 (Capture input, Compare

and PWM output) can change, based on device config-

uration. The CCP2MX Configuration bit determines

which pin CCP2 is multiplexed to. By default, it is

assigned to RC1 (CCP2MX = 1). If the Configuration bit

is cleared, CCP2 is multiplexed with RB3.

TABLE 15-1: CCP MODE – TIMER

RESOURCES

Changing the pin assignment of CCP2 does not

automatically change any requirements for configuring

the port pin. Users must always verify that the appropri-

ate TRIS register is configured correctly for CCP2

operation, regardless of where it is located.

CCP/ECCP Mode

Timer Resource

Capture

Compare

PWM

Timer1 or Timer3

Timer2

TABLE 15-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES

CCP1 Mode CCP2 Mode

Interaction

Capture

Each module can use TMR1 or TMR3 as the time base. The time base can be different

for each CCP.

Capture

Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3

(depending upon which time base is used). Automatic A/D conversions on trigger event

can also be done. Operation of CCP1 could be affected if it is using the same timer as a

time base.

Compare

Capture

CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3

(depending upon which time base is used). Operation of CCP2 could be affected if it is

using the same timer as a time base.

Compare Either module can be configured for the Special Event Trigger to reset the time base.

Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if

both modules are using the same time base.

Capture

Compare

PWM⁽¹⁾

Capture

None

Compare None

PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt).

Note 1: Includes standard and Enhanced PWM operation.

DS39689E-page 140

Preliminary

PIC18F4321 FAMILY

15.2.3

SOFTWARE INTERRUPT

15.2 Capture Mode

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCPxIE interrupt enable bit clear to avoid false

interrupts. The interrupt flag bit, CCPxIF, should also be

cleared following any such change in operating mode.

In Capture mode, the CCPRxH:CCPRxL register pair

captures the 16-bit value of the TMR1 or TMR3

registers when an event occurs on the corresponding

CCPx pin. An event is defined as one of the following:

• every falling edge

• every rising edge

15.2.4

CCP PRESCALER

• every 4th rising edge

• every 16th rising edge

There are four prescaler settings in Capture mode.

They are specified as part of the operating mode

selected by the mode select bits (CCPxM3:CCPxM0).

Whenever the CCP module is turned off or Capture

mode is disabled, the prescaler counter is cleared. This

means that any Reset will clear the prescaler counter.

The event is selected by the mode select bits,

CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture

is made, the interrupt request flag bit, CCPxIF, is set; it

must be cleared in software. If another capture occurs

before the value in register CCPRx is read, the old

captured value is overwritten by the new captured value.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared; therefore, the first capture may be from

15.2.1

CCP PIN CONFIGURATION

a

non-zero prescaler. Example 15-1 shows the

recommended method for switching between capture

prescalers. This example also clears the prescaler

counter and will not generate the “false” interrupt.

In Capture mode, the appropriate CCPx pin should be

configured as an input by setting the corresponding

TRIS direction bit.

Note:

If RB3/CCP2 or RC1/CCP2 is configured

as an output, a write to the port can cause

a capture condition.

EXAMPLE 15-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

(CCP2 SHOWN)

CLRF

CCP2CON

; Turn CCP module off

15.2.2

TIMER1/TIMER3 MODE SELECTION

MOVLW NEW_CAPT_PS ; Load WREG with the

; new prescaler mode

The timers that are to be used with the capture feature

(Timer1 and/or Timer3) must be running in Timer mode or

Synchronized Counter mode. In Asynchronous Counter

mode, the capture operation will not work. The timer to be

used with each CCP module is selected in the T3CON

register (see Section 15.1.1 “CCP Modules and Timer

Resources”).

; value and CCP ON

; Load CCP2CON with

; this value

MOVWF CCP2CON

FIGURE 15-1:

CAPTURE MODE OPERATION BLOCK DIAGRAM

TMR3H

TMR3L

Set CCP1IF

T3CCP2

TMR3

Enable

CCP1 pin

Prescaler

÷ 1, 4, 16

and

Edge Detect

CCPR1H

CCPR1L

TMR1

Enable

T3CCP2

TMR1H

TMR3H

TMR1L

TMR3L

4

CCP1CON<3:0>

Q1:Q4

Set CCP2IF

4

CCP2CON<3:0>

T3CCP1

T3CCP2

TMR3

Enable

CCP2 pin

Prescaler

÷ 1, 4, 16

and

Edge Detect

CCPR2H

CCPR2L

TMR1L

TMR1

Enable

T3CCP2

T3CCP1

TMR1H

Preliminary

DS39689E-page 141

PIC18F4321 FAMILY

15.3.2

TIMER1/TIMER3 MODE SELECTION

15.3 Compare Mode

Timer1 and/or Timer3 must be running in Timer mode

or Synchronized Counter mode if the CCP module is

using the compare feature. In Asynchronous Counter

mode, the compare operation may not work.

In Compare mode, the 16-bit CCPRx register value is

constantly compared against either the TMR1 or TMR3

register pair value. When a match occurs, the CCPx pin

can be:

• driven high

15.3.3

SOFTWARE INTERRUPT MODE

• driven low

When the Generate Software Interrupt mode is chosen

(CCPxM3:CCPxM0 = 1010), the corresponding CCPx

pin is not affected. Only a CCP interrupt is generated,

if enabled and the CCPxIE bit is set.

• toggled (high-to-low or low-to-high)

• remain unchanged (that is, reflects the state of the

I/O latch)

The action on the pin is based on the value of the mode

select bits (CCPxM3:CCPxM0). At the same time, the

interrupt flag bit, CCPxIF, is set.

15.3.4

SPECIAL EVENT TRIGGER

Both CCP modules are equipped with a Special Event

Trigger. This is an internal hardware signal generated

in Compare mode to trigger actions by other modules.

The Special Event Trigger is enabled by selecting

the Compare Special Event Trigger mode

(CCPxM3:CCPxM0 = 1011).

15.3.1

CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the appropriate TRIS bit.

Note:

Clearing the CCP2CON register will force

the RB3 or RC1 compare output latch

(depending on device configuration) to the

default low level. This is not the PORTB or

PORTC I/O data latch.

For either CCP module, the Special Event Trigger resets

the Timer register pair for whichever timer resource is

currently assigned as the module’s time base. This

allows the CCPRx registers to serve as a programmable

period register for either timer.

The Special Event Trigger for CCP2 can also start an

A/D conversion. In order to do this, the A/D converter

must already be enabled.

FIGURE 15-2:

COMPARE MODE OPERATION BLOCK DIAGRAM

Special Event Trigger

(Timer1/Timer3 Reset)

Set CCP1IF

CCPR1H

CCPR1L

CCP1 pin

S

R

Q

Output

Logic

Compare

Match

Comparator

TRIS

Output Enable

4

CCP1CON<3:0>

TMR1H

TMR3H

TMR1L

TMR3L

0

1

Special Event Trigger

(Timer1/Timer3 Reset, A/D Trigger)

T3CCP1

T3CCP2

Set CCP2IF

CCP2 pin

S

R

Q

Compare

Match

Output

Logic

Comparator

TRIS

Output Enable

4

CCPR2H

CCPR2L

CCP2CON<3:0>

DS39689E-page 142

Preliminary

PIC18F4321 FAMILY

TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3

Reset

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Values

on page

INTCON

RCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RI

RBIE

TO

TMR0IF

PD

INT0IF

POR

RBIF

49

48

52

50

51

(1)

IPEN

SBOREN

ADIF

—

RCIF

RCIE

RCIP

—

BOR

PSPIF⁽²⁾

PSPIE⁽²⁾

PSPIP⁽²⁾

OSCFIF

OSCFIE

OSCFIP

TXIF

TXIE

TXIP

EEIF

EEIE

EEIP

SSPIF

SSPIE

SSPIP

BCLIF

BCLIE

BCLIP

CCP1IF

CCP1IE

CCP1IP

HLVDIF

HLVDIE

HLVDIP

TMR2IF

TMR2IE

TMR2IP

TMR3IF

TMR3IE

TMR3IP

TMR1IF

TMR1IE

TMR1IP

CCP2IF

CCP2IE

CCP2IP

PIE1

ADIE

IPR1

ADIP

PIR2

CMIF

CMIE

CMIP

PIE2

—

IPR2

—

TRISB

TRISC

TMR1L

TMR1H

T1CON

TMR3H

TMR3L

T3CON

PORTB Data Direction Control Register

PORTC Data Direction Control Register

Timer1 Register Low Byte

Timer1 Register High Byte

RD16

T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

Timer3 Register High Byte

Timer3 Register Low Byte

RD16

T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON

CCPR1L Capture/Compare/PWM Register 1 Low Byte

CCPR1H Capture/Compare/PWM Register 1 High Byte

CCP1CON P1M1⁽²⁾

P1M0⁽²⁾

DC1B1

DC1B0

CCP1M3 CCP1M2 CCP1M1 CCP1M0

CCPR2L Capture/Compare/PWM Register 2 Low Byte

CCPR2H Capture/Compare/PWM Register 2 High Byte

CCP2CON

—

DC2B1

DC2B0

CCP2M3 CCP2M2 CCP2M1 CCP2M0

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3.

Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is

disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.

2: These bits are unimplemented on 28-pin devices and read as ‘0’.

Preliminary

DS39689E-page 143

PIC18F4321 FAMILY

15.4.1

PWM PERIOD

15.4 PWM Mode

The PWM period is specified by writing to the PR2

register. The PWM period can be calculated using the

following formula:

In Pulse-Width Modulation (PWM) mode, the CCPx pin

produces up to a 10-bit resolution PWM output. Since

the CCP2 pin is multiplexed with a PORTB or PORTC

data latch, the appropriate TRIS bit must be cleared to

make the CCP2 pin an output.

EQUATION 15-1:

PWM Period = [(PR2) + 1] • 4 • TOSC •

(TMR2 Prescale Value)

Note:

Clearing the CCP2CON register will force

the RB3 or RC1 output latch (depending on

device configuration) to the default low

level. This is not the PORTB or PORTC I/O

data latch.

PWM frequency is defined as 1/[PWM period].

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

Figure 15-3 shows a simplified block diagram of the

CCP module in PWM mode.

• TMR2 is cleared

For a step-by-step procedure on how to set up the CCP

module for PWM operation, see Section 15.4.4

“Setup for PWM Operation”.

• The CCPx pin is set (exception: if PWM duty

cycle = 0%, the CCPx pin will not be set)

• The PWM duty cycle is latched from CCPRxL into

CCPRxH

FIGURE 15-3:

SIMPLIFIED PWM BLOCK

DIAGRAM

Note:

The Timer2 postscalers (see Section 13.0

“Timer2 Module”) are not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

CCPxCON<5:4>

Duty Cycle Registers

CCPRxL

15.4.2

PWM DUTY CYCLE

CCPRxH (Slave)

Comparator

CCPx Output

The PWM duty cycle is specified by writing to the

CCPRxL register and to the CCPxCON<5:4> bits. Up

to 10-bit resolution is available. The CCPRxL contains

the eight MSbs and the CCPxCON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPRxL:CCPxCON<5:4>. The following equation is

used to calculate the PWM duty cycle in time:

Q

R

S

(Note 1)

TMR2

Corresponding

TRIS bit

Comparator

PR2

Clear Timer,

CCPx pin and

latch D.C.

EQUATION 15-2:

PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) •

TOSC • (TMR2 Prescale Value)

Note 1: The 8-bit TMR2 value is concatenated with the 2-bit

internal Q clock, or 2 bits of the prescaler, to create the

10-bit time base.

CCPRxL and CCPxCON<5:4> can be written to at any

time, but the duty cycle value is not latched into

CCPRxH until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPRxH is a read-only register.

A PWM output (Figure 15-4) has a time base (period)

and a time that the output stays high (duty cycle).

The frequency of the PWM is the inverse of the

period (1/period).

FIGURE 15-4:

PWM OUTPUT

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

DS39689E-page 144

Preliminary

PIC18F4321 FAMILY

The CCPRxH register and a 2-bit internal latch are

used to double-buffer the PWM duty cycle. This

double-buffering is essential for glitchless PWM

operation.

EQUATION 15-3:

FOSC

⎛

⎝

⎞

⎠

---------------

log

FPWM

PWM Resolution (max)

= ----------------------------- b i t s

log(2)

When the CCPRxH and 2-bit latch match TMR2,

concatenated with an internal 2-bit Q clock or 2 bits of

the TMR2 prescaler, the CCPx pin is cleared.

Note:

If the PWM duty cycle value is longer than

the PWM period, the CCPx pin will not be

cleared.

The maximum PWM resolution (bits) for a given PWM

frequency is given by the equation:

TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

PWM Frequency

2.44 kHz

9.77 kHz

39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz

Timer Prescaler (1, 4, 16)

PR2 Value

16

FFh

10

4

1

3Fh

8

1

1Fh

7

1

FFh

10

FFh

10

17h

6.58

Maximum Resolution (bits)

15.4.3

PWM AUTO-SHUTDOWN

(CCP1 ONLY)

15.4.4

SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

The PWM auto-shutdown features of the Enhanced CCP

module are also available to CCP1 in 28-pin devices. The

operation of this feature is discussed in detail in

Section 16.4.7 “Enhanced PWM Auto-Shutdown”.

1. Set the PWM period by writing to the PR2

register.

2. Set the PWM duty cycle by writing to the

CCPRxL register and CCPxCON<5:4> bits.

Auto-shutdown features are not available for CCP2.

3. Make the CCPx pin an output by clearing the

appropriate TRIS bit.

4. Set the TMR2 prescale value, then enable

Timer2 by writing to T2CON.

5. Configure the CCPx module for PWM operation.

Preliminary

DS39689E-page 145

PIC18F4321 FAMILY

TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

RCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RI

RBIE

TO

TMR0IF

PD

INT0IF

POR

RBIF

BOR

49

48

52

50

51

IPEN

SBOREN⁽¹⁾

—

PSPIF⁽²⁾

PSPIE⁽²⁾

PSPIP⁽²⁾

ADIF

RCIF

RCIE

RCIP

TXIF

TXIE

TXIP

SSPIF

SSPIE

SSPIP

CCP1IF

TMR2IF

TMR1IF

TMR1IE

TMR1IP

PIE1

ADIE

CCP1IE TMR2IE

CCP1IP TMR2IP

IPR1

ADIP

TRISB

TRISC

TMR2

PR2

PORTB Data Direction Control Register

PORTC Data Direction Control Register

Timer2 Register

Timer2 Period Register

T2CON

CCPR1L

—

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0

Capture/Compare/PWM Register 1 Low Byte

CCPR1H Capture/Compare/PWM Register 1 High Byte

CCP1CON P1M1⁽²⁾P1M0⁽²⁾

DC1B1 DC1B0

CCPR2L Capture/Compare/PWM Register 2 Low Byte

CCPR2H Capture/Compare/PWM Register 2 High Byte

CCP2CON DC2B1 DC2B0

ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1⁽²⁾PSSBD0⁽²⁾

ECCP1DEL PRSEN

PDC6⁽²⁾PDC5⁽²⁾PDC4⁽²⁾PDC3⁽²⁾PDC2⁽²⁾PDC1⁽²⁾PDC0⁽²⁾

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.

CCP1M3 CCP1M2 CCP1M1 CCP1M0

CCP2M3 CCP2M2 CCP2M1 CCP2M0

—

Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is

disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.

2: These bits are unimplemented on 28-pin devices and read as ‘0’.

DS39689E-page 146

Preliminary

PIC18F4321 FAMILY

Enhanced features are discussed in detail in

Section 16.4 “Enhanced PWM Mode”. Capture,

Compare and single-output PWM functions of the

ECCP module are the same as described for the

standard CCP module.

16.0 ENHANCED CAPTURE/

COMPARE/PWM (ECCP)

MODULE

Note:

The ECCP module is implemented only in

40/44-pin devices.

The control register for the Enhanced CCP module is

shown in Register 16-1. It differs from the CCPxCON

registers in PIC18F2221/2321 devices in that the two

Most Significant bits are implemented to control PWM

functionality.

In PIC18F4221/4321 devices, CCP1 is implemented

as a standard CCP module with Enhanced PWM

capabilities. These include the provision for 2 or 4

output channels, user-selectable polarity, dead-band

control and automatic shutdown and restart. The

REGISTER 16-1: CCP1CON REGISTER (ECCP1 MODULE, 40/44-PIN DEVICES)

R/W-0

P1M1

R/W-0

P1M0

R/W-0

DC1B1

DC1B0

CCP1M3 CCP1M2 CCP1M1 CCP1M0

bit 0

bit 7

bit 7-6

P1M1:P1M0: Enhanced PWM Output Configuration bits

If CCP1M3:CCP1M2 = 00, 01, 10:

xx= P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins

If CCP1M3:CCP1M2 = 11:

00= Single output: P1A modulated; P1B, P1C, P1D assigned as port pins

01= Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive

10= Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned

as port pins

11= Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive

bit 5-4

DC1B1:DC1B0: PWM Duty Cycle bit 1 and bit 0

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are

found in CCPR1L.

bit 3-0

CCP1M3:CCP1M0: Enhanced CCP Mode Select bits

0000= Capture/Compare/PWM off (resets ECCP module)

0001= Reserved

0010= Compare mode, toggle output on match

0011= Capture mode

0100= Capture mode, every falling edge

0101= Capture mode, every rising edge

0110= Capture mode, every 4th rising edge

0111= Capture mode, every 16th rising edge

1000= Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF)

1001= Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF)

1010= Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state

1011= Compare mode, trigger special event (ECCP resets TMR1 or TMR3, sets CC1IF bit)

1100= PWM mode; P1A, P1C active-high; P1B, P1D active-high

1101= PWM mode; P1A, P1C active-high; P1B, P1D active-low

1110= PWM mode; P1A, P1C active-low; P1B, P1D active-high

1111= PWM mode; P1A, P1C active-low; P1B, P1D active-low

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39689E-page 147

PIC18F4321 FAMILY

In addition to the expanded range of modes available

through the CCP1CON and ECCP1AS registers, the

ECCP module has an additional register associated

with Enhanced PWM operation and auto-shutdown

features; it is:

16.2 Capture and Compare Modes

Except for the operation of the Special Event Trigger

discussed below, the Capture and Compare modes of

the ECCP module are identical in operation to that of

CCP2. These are discussed in detail in Section 15.2

“Capture Mode” and Section 15.3 “Compare

Mode”. No changes are required when moving

between 28-pin and 40/44-pin devices.

• ECCP1DEL (Dead-band delay)

16.1 ECCP Outputs and Configuration

The Enhanced CCP module may have up to four PWM

outputs, depending on the selected operating mode.

These outputs, designated P1A through P1D, are

multiplexed with I/O pins on PORTC and PORTD. The

outputs that are active depend on the CCP operating

mode selected. The pin assignments are summarized

in Table 16-1.

16.2.1

SPECIAL EVENT TRIGGER

The Special Event Trigger output of ECCP1 resets the

TMR1 or TMR3 register pair, depending on which timer

resource is currently selected. This allows the CCPR1

register to effectively be a 16-bit programmable period

register for Timer1 or Timer3.

To configure the I/O pins as PWM outputs, the proper

PWM mode must be selected by setting the

P1M1:P1M0 and CCP1M3:CCP1M0 bits. The

appropriate TRISC and TRISD direction bits for the port

pins must also be set as outputs.

16.3 Standard PWM Mode

When configured in Single Output mode, the ECCP

module functions identically to the standard CCP

module in PWM mode, as described in Section 15.4

“PWM Mode”. This is also sometimes referred to as

“Compatible CCP” mode, as in Table 16-1.

16.1.1

ECCP MODULES AND TIMER

RESOURCES

Note:

When setting up single output PWM

operations, users are free to use either

Like the standard CCP modules, the ECCP module can

utilize Timers 1, 2 or 3, depending on the mode

selected. Timer1 and Timer3 are available for modules

in Capture or Compare modes, while Timer2 is avail-

able for modules in PWM mode. Interactions between

the standard and Enhanced CCP modules are identical

to those described for standard CCP modules.

Additional details on timer resources are provided in

of

the

processes

described

in

Section 15.4.4 “Setup for PWM

Operation” or Section 16.4.9 “Setup

for PWM Operation”. The latter is more

generic and will work for either single or

multi-output PWM.

Section 15.1.1

“CCP

Modules

and

Timer

Resources”.

TABLE 16-1: PIN ASSIGNMENTS FOR VARIOUS ECCP1 MODES

CCP1CON

ECCP Mode

RC2

RD5

RD6

RD7

Configuration

All 40/44-pin devices:

Compatible CCP

Dual PWM

00xx 11xx

10xx 11xx

x1xx 11xx

CCP1

P1A

RD5/PSP5

P1B

RD6/PSP6

P1C

RD7/PSP7

P1D

Quad PWM

P1A

P1B

Legend: x= Don’t care. Shaded cells indicate pin assignments not used by ECCP1 in a given mode.

DS39689E-page 148

Preliminary

PIC18F4321 FAMILY

16.4.1

PWM PERIOD

16.4 Enhanced PWM Mode

The PWM period is specified by writing to the PR2

register. The PWM period can be calculated using the

following equation.

The Enhanced PWM mode provides additional PWM

output options for a broader range of control applica-

tions. The module is a backward compatible version of

the standard CCP module and offers up to four outputs,

designated P1A through P1D. Users are also able to

select the polarity of the signal (either active-high or

active-low). The module’s output mode and polarity are

configured by setting the P1M1:P1M0 and

CCP1M3:CCP1M0 bits of the CCP1CON register.

EQUATION 16-1:

PWM Period = [(PR2) + 1] • 4 • TOSC •

(TMR2 Prescale Value)

PWM frequency is defined as 1/[PWM period]. When

TMR2 is equal to PR2, the following three events occur

on the next increment cycle:

Figure 16-1 shows a simplified block diagram of PWM

operation. All control registers are double-buffered and

are loaded at the beginning of a new PWM cycle (the

period boundary when Timer2 resets) in order to

prevent glitches on any of the outputs. The exception is

the PWM Dead-Band Delay register, ECCP1DEL,

which is loaded at either the duty cycle boundary or the

period boundary (whichever comes first). Because of

the buffering, the module waits until the assigned timer

resets, instead of starting immediately. This means that

Enhanced PWM waveforms do not exactly match the

standard PWM waveforms, but are instead offset by

one full instruction cycle (4 TOSC).

• TMR2 is cleared

• The CCP1 pin is set (if PWM duty cycle = 0%, the

CCP1 pin will not be set)

• The PWM duty cycle is copied from CCPR1L into

CCPR1H

Note:

The Timer2 postscaler (see Section 13.0

“Timer2 Module”) is not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

As before, the user must manually configure the

appropriate TRIS bits for output.

FIGURE 16-1:

SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE

CCP1CON<5:4>

P1M1<1:0>

CCP1M<3:0>

4

Duty Cycle Registers

2

CCPR1L

CCP1/P1A

P1B

TRISx<x>

CCPR1H (Slave)

Comparator

P1B

Output

Controller

R

S

Q

P1C

P1D

(Note 1)

TMR2

P1D

Comparator

PR2

Clear Timer,

set CCP1 pin and

latch D.C.

ECCP1DEL

Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit

time base.

Preliminary

DS39689E-page 149

PIC18F4321 FAMILY

16.4.2

PWM DUTY CYCLE

EQUATION 16-3:

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10-bit resolution is available. The CCPR1L contains

the eight MSbs and the CCP1CON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. The PWM duty cycle is

calculated by the following equation.

FOSC

FPWM

log

(

)

bits

PWM Resolution (max) =

log(2)

Note:

If the PWM duty cycle value is longer than

the PWM period, the CCP1 pin will not be

cleared.

EQUATION 16-2:

PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •

TOSC • (TMR2 Prescale Value)

16.4.3

PWM OUTPUT CONFIGURATIONS

The P1M1:P1M0 bits in the CCP1CON register allow

one of four configurations:

CCPR1L and CCP1CON<5:4> can be written to at any

time, but the duty cycle value is not copied into

CCPR1H until a match between PR2 and TMR2 occurs

(i.e., the period is complete). In PWM mode, CCPR1H

is a read-only register.

• Single Output

• Half-Bridge Output

• Full-Bridge Output, Forward mode

• Full-Bridge Output, Reverse mode

The CCPR1H register and a 2-bit internal latch are

used to double-buffer the PWM duty cycle. This

double-buffering is essential for glitchless PWM

operation. When the CCPR1H and 2-bit latch match

TMR2, concatenated with an internal 2-bit Q clock or

two bits of the TMR2 prescaler, the CCP1 pin is

cleared. The maximum PWM resolution (bits) for a

given PWM frequency is given by the following

equation.

The Single Output mode is the standard PWM mode

discussed in Section 16.4 “Enhanced PWM Mode”.

The Half-Bridge and Full-Bridge Output modes are

covered in detail in the sections that follow.

The general relationship of the outputs in all

configurations is summarized in Figure 16-2.

TABLE 16-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

PWM Frequency

2.44 kHz

9.77 kHz

39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz

Timer Prescaler (1, 4, 16)

PR2 Value

16

FFh

10

4

1

3Fh

8

1

1Fh

7

1

FFh

10

FFh

10

17h

6.58

Maximum Resolution (bits)

DS39689E-page 150

Preliminary

PIC18F4321 FAMILY

FIGURE 16-2:

PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)

0

PR2 + 1

Duty

Cycle

SIGNAL

CCP1CON

<7:6>

Period

P1A Modulated

P1B Modulated

P1A Active

(Single Output)

00

10

(1)

Delay

(Half-Bridge)

P1B Inactive

P1C Inactive

P1D Modulated

P1A Inactive

P1B Modulated

P1C Active

(Full-Bridge,

Forward)

01

(Full-Bridge,

Reverse)

11

P1D Inactive

FIGURE 16-3:

PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)

0

PR2 + 1

SIGNAL

CCP1CON

Duty

Cycle

<7:6>

Period

P1A Modulated

P1B Modulated

P1A Active

(Single Output)

00

10

(1)

Delay

(Half-Bridge)

P1B Inactive

P1C Inactive

P1D Modulated

P1A Inactive

P1B Modulated

P1C Active

(Full-Bridge,

Forward)

01

(Full-Bridge,

Reverse)

11

P1D Inactive

Relationships:

•

Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)

Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)

Delay = 4 * TOSC * (ECCP1DEL<6:0>)

Note 1: Dead-band delay is programmed using the ECCP1DEL register (see Section 16.4.6 “Programmable

Dead-Band Delay”).

Preliminary

DS39689E-page 151

PIC18F4321 FAMILY

16.4.4

HALF-BRIDGE MODE

FIGURE 16-4:

HALF-BRIDGE PWM

OUTPUT

In the Half-Bridge Output mode, two pins are used as

outputs to drive push-pull loads. The PWM output signal

is output on the P1A pin, while the complementary PWM

output signal is output on the P1B pin (Figure 16-4). This

mode can be used for half-bridge applications, as shown

in Figure 16-5, or for full-bridge applications where four

power switches are being modulated with two PWM

signals.

Period

Duty Cycle

(2)

P1A

td

P1B

In Half-Bridge Output mode, the programmable dead-

band delay can be used to prevent shoot-through

current in half-bridge power devices. The value of bits,

PDC6:PDC0, sets the number of instruction cycles

before the output is driven active. If the value is greater

than the duty cycle, the corresponding output remains

inactive during the entire cycle. See Section 16.4.6

“Programmable Dead-Band Delay” for more details

of the dead-band delay operations.

(1)

td = Dead-Band Delay

Note 1: At this time, the TMR2 register is equal to the

PR2 register.

2: Output signals are shown as active-high.

Since the P1A and P1B outputs are multiplexed with

the PORTC<2> and PORTD<5> data latches, the

TRISC<2> and TRISD<5> bits must be cleared to

configure P1A and P1B as outputs.

FIGURE 16-5:

EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS

V+

Standard Half-Bridge Circuit (“Push-Pull”)

PIC18F4X21

P1A

FET

Driver

+

V

-

Load

FET

Driver

+

V

-

P1B

V-

Half-Bridge Output Driving a Full-Bridge Circuit

V+

PIC18F4X21

FET

Driver

P1A

Load

FET

Driver

P1B

V-

DS39689E-page 152

Preliminary

PIC18F4321 FAMILY

P1A, P1B, P1C and P1D outputs are multiplexed with

the PORTC<2> and PORTD<7:5> data latches. The

TRISC<2> and TRISD<7:5> bits must be cleared to

make the P1A, P1B, P1C and P1D pins outputs.

16.4.5

FULL-BRIDGE MODE

In Full-Bridge Output mode, four pins are used as

outputs; however, only two outputs are active at a time.

In the Forward mode, pin P1A is continuously active

and pin P1D is modulated. In the Reverse mode, pin

P1C is continuously active and pin P1B is modulated.

These are illustrated in Figure 16-6.

FIGURE 16-6:

FULL-BRIDGE PWM OUTPUT

Forward Mode

Period

(2)

P1A

Duty Cycle

(2)

P1B

P1C

(2)

P1D

(1)

Reverse Mode

Period

Duty Cycle

(2)

P1A

(2)

P1B

(2)

P1C

(2)

P1D

(1)

Note 1: At this time, the TMR2 register is equal to the PR2 register.

Note 2: Output signal is shown as active-high.

Preliminary

DS39689E-page 153

PIC18F4321 FAMILY

FIGURE 16-7:

EXAMPLE OF FULL-BRIDGE APPLICATION

V+

PIC18F4X21

QC

QA

FET

Driver

FET

Driver

P1A

Load

P1B

FET

Driver

FET

Driver

P1C

P1D

QD

QB

V-

Figure 16-9 shows an example where the PWM

direction changes from forward to reverse at a near

100% duty cycle. At time t1, the outputs P1A and P1D

become inactive, while output P1C becomes active. In

this example, since the turn-off time of the power

devices is longer than the turn-on time, a shoot-through

current may flow through power devices, QC and QD

(see Figure 16-7), for the duration of ‘t’. The same

phenomenon will occur to power devices, QA and QB,

for PWM direction change from reverse to forward.

16.4.5.1

Direction Change in Full-Bridge Mode

In the Full-Bridge Output mode, the P1M1 bit in the

CCP1CON register allows user to control the forward/

reverse direction. When the application firmware

changes this direction control bit, the module will

assume the new direction on the next PWM cycle.

Just before the end of the current PWM period, the

modulated outputs (P1B and P1D) are placed in their

inactive state, while the unmodulated outputs (P1A and

P1C) are switched to drive in the opposite direction.

This occurs in a time interval of 4 TOSC * (Timer2

Prescale Value) before the next PWM period begins.

The Timer2 prescaler will be either 1, 4 or 16, depend-

ing on the value of the T2CKPS1:T2CKPS0 bits

(T2CON<1:0>). During the interval from the switch of

the unmodulated outputs to the beginning of the next

period, the modulated outputs (P1B and P1D) remain

inactive. This relationship is shown in Figure 16-8.

If changing PWM direction at high duty cycle is required

for an application, one of the following requirements

must be met:

1. Reduce PWM for

changing directions.

a PWM period before

2. Use switch drivers that can drive the switches off

faster than they can drive them on.

Other options to prevent shoot-through current may

exist.

Note that in the Full-Bridge Output mode, the ECCP1

module does not provide any dead-band delay. In

general, since only one output is modulated at all times,

dead-band delay is not required. However, there is a

situation where a dead-band delay might be required.

This situation occurs when both of the following

conditions are true:

1. The direction of the PWM output changes when

the duty cycle of the output is at or near 100%.

2. The turn-off time of the power switch, including

the power device and driver circuit, is greater

than the turn-on time.

DS39689E-page 154

Preliminary

PIC18F4321 FAMILY

FIGURE 16-8:

PWM DIRECTION CHANGE

(1)

Period

SIGNAL

P1A (Active-High)

P1B (Active-High)

DC

P1C (Active-High)

P1D (Active-High)

(Note 2)

DC

Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle.

2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals

of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals

are inactive at this time.

FIGURE 16-9:

PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE

Forward Period

Reverse Period

t1

(1)

P1A

P1B

DC

(1)

P1C

P1D

DC

(2)

t

ON

(1)

External Switch C

External Switch D

(3)

t

OFF

(2,3)

Potential

t = t

– t

ON

OFF

Shoot-Through

(1)

Current

Note 1: All signals are shown as active-high.

2:

3:

t

is the turn-on delay of power switch QC and its driver.

ON

is the turn-off delay of power switch QD and its driver.

OFF

Preliminary

DS39689E-page 155

PIC18F4321 FAMILY

A shutdown event can be caused by either of the

comparator modules, a low level on the Fault input pin

(FLT0) or any combination of these three sources. The

comparators may be used to monitor a voltage input

proportional to a current being monitored in the bridge

16.4.6

PROGRAMMABLE DEAD-BAND

DELAY

Note:

Programmable dead-band delay is not

implemented in 28-pin devices with

standard CCP modules.

circuit. If the voltage exceeds

a threshold, the

comparator switches state and triggers a shutdown.

Alternatively, a low digital signal on FLT0 can also trigger

a shutdown. The auto-shutdown feature can be disabled

by not selecting any auto-shutdown sources. The auto-

shutdown sources to be used are selected using the

ECCPAS2:ECCPAS0 bits (ECCP1AS<6:4>).

In half-bridge applications, where all power switches

are modulated at the PWM frequency at all times, the

power switches normally require more time to turn off

than to turn on. If both the upper and lower power

switches are switched at the same time (one turned on

and the other turned off), both switches may be on for

a short period of time until one switch completely turns

off. During this brief interval, a very high current (shoot-

through current) may flow through both power

switches, shorting the bridge supply. To avoid this

potentially destructive shoot-through current from

flowing during switching, turning on either of the power

switches is normally delayed to allow the other switch

to completely turn off.

When a shutdown occurs, the output pins are asyn-

chronously placed in their shutdown states, specified

by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits

(ECCP1AS<3:0>). Each pin pair (P1A/P1C and P1B/

P1D) may be set to drive high, drive low or be tri-stated

(not driving). The ECCPASE bit (ECCP1AS<7>) is also

set to hold the Enhanced PWM outputs in their

shutdown states.

In the Half-Bridge Output mode, a digitally programmable

dead-band delay is available to avoid shoot-through

current from destroying the bridge power switches. The

delay occurs at the signal transition from the nonactive

state to the active state (see Figure 16-4 for illustration).

Bits PDC6:PDC0 of the ECCP1DEL register

(Register 16-2) set the delay period in terms of micro-

controller instruction cycles (TCY or 4 TOSC). These bits

are not available on 28-pin devices as the standard CCP

module does not support half-bridge operation.

The ECCPASE bit is set by hardware when a shutdown

event occurs. If automatic restarts are not enabled, the

ECCPASE bit is cleared by firmware when the cause of

the shutdown clears. If automatic restarts are enabled,

the ECCPASE bit is automatically cleared when the

cause of the auto-shutdown has cleared.

If the ECCPASE bit is set when a PWM period begins,

the PWM outputs remain in their shutdown state for that

entire PWM period. When the ECCPASE bit is cleared,

the PWM outputs will return to normal operation at the

beginning of the next PWM period.

16.4.7

ENHANCED PWM AUTO-SHUTDOWN

Note:

Writing to the ECCPASE bit is disabled

while a shutdown condition is active.

When the ECCP1 is programmed for any of the

Enhanced PWM modes, the active output pins may be

configured for auto-shutdown. Auto-shutdown immedi-

ately places the Enhanced PWM output pins into a

defined shutdown state when a shutdown event occurs.

REGISTER 16-2: ECCP1DEL: PWM DEAD-BAND DELAY REGISTER

R/W-0

PRSEN

PDC6⁽¹⁾

PDC5⁽¹⁾

PDC4⁽¹⁾

PDC3⁽¹⁾

PDC2⁽¹⁾

PDC1⁽¹⁾

PDC0⁽¹⁾

bit 7

bit 0

bit 7

PRSEN: PWM Restart Enable bit

1= Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event

goes away; the PWM restarts automatically

0= Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM

bit 6-0

PDC6:PDC0: PWM Delay Count bits⁽¹⁾

Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for

a PWM signal to transition to active.

Note 1: Unimplemented on 28-pin devices; bits read ‘0’.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39689E-page 156

Preliminary

PIC18F4321 FAMILY

REGISTER 16-3: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN

CONTROL REGISTER

R/W-0

ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1⁽¹⁾PSSBD0⁽¹⁾

bit 7

bit 0

bit 7

ECCPASE: ECCP Auto-Shutdown Event Status bit

1= A shutdown event has occurred; ECCP outputs are in shutdown state

0= ECCP outputs are operating

bit 6-4

ECCPAS2:ECCPAS0: ECCP Auto-Shutdown Source Select bits

111= FLT0 or Comparator 1 or Comparator 2

110= FLT0 or Comparator 2

101= FLT0 or Comparator 1

100= FLT0

011= Either Comparator 1 or 2

010= Comparator 2 output

001= Comparator 1 output

000= Auto-shutdown is disabled

bit 3-2

bit 1-0

PSSAC1:PSSAC0: Pins A and C Shutdown State Control bits

1x= Pins A and C are tri-state (40/44-pin devices);

PWM output is tri-state (28-pin devices)

01= Drive Pins A and C to ‘1’

00= Drive Pins A and C to ‘0’

PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits⁽¹⁾

1x= Pins B and D tri-state

01= Drive Pins B and D to ‘1’

00= Drive Pins B and D to ‘0’

Note 1: Unimplemented on 28-pin devices; bits read as ‘0’.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39689E-page 157

PIC18F4321 FAMILY

16.4.7.1

Auto-Shutdown and

Automatic Restart

16.4.8

START-UP CONSIDERATIONS

When the ECCP module is used in the PWM mode, the

application hardware must use the proper external pull-

up and/or pull-down resistors on the PWM output pins.

When the microcontroller is released from Reset, all of

the I/O pins are in the high-impedance state. The

external circuits must keep the power switch devices in

the OFF state until the microcontroller drives the I/O

pins with the proper signal levels, or activates the PWM

output(s).

The auto-shutdown feature can be configured to allow

automatic restarts of the module following a shutdown

event. This is enabled by setting the PRSEN bit of the

ECCP1DEL register (ECCP1DEL<7>).

In Shutdown mode with PRSEN = 1(Figure 16-10), the

ECCPASE bit will remain set for as long as the cause

of the shutdown continues. When the shutdown condi-

tion clears, the ECCP1ASE bit is cleared. If PRSEN = 0

(Figure 16-11), once a shutdown condition occurs, the

ECCPASE bit will remain set until it is cleared by

firmware. Once ECCPASE is cleared, the Enhanced

PWM will resume at the beginning of the next PWM

period.

The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow

the user to choose whether the PWM output signals are

active-high or active-low for each pair of PWM output

pins (P1A/P1C and P1B/P1D). The PWM output

polarities must be selected before the PWM pins are

configured as outputs. Changing the polarity configura-

tion while the PWM pins are configured as outputs is

not recommended, since it may result in damage to the

application circuits.

Note:

Writing to the ECCPASE bit is disabled

while a shutdown condition is active.

Independent of the PRSEN bit setting, if the auto-

shutdown source is one of the comparators, the

shutdown condition is a level. The ECCPASE bit

cannot be cleared as long as the cause of the shutdown

persists.

The P1A, P1B, P1C and P1D output latches may not be

in the proper states when the PWM module is initialized.

Enabling the PWM pins for output at the same time as

the ECCP module may cause damage to the applica-

tion circuit. The ECCP module must be enabled in the

proper output mode and complete a full PWM cycle

before configuring the PWM pins as outputs. The com-

pletion of a full PWM cycle is indicated by the TMR2IF

bit being set as the second PWM period begins.

The Auto-Shutdown mode can be forced by writing a ‘1’

to the ECCPASE bit.

FIGURE 16-10:

PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)

PWM Period

PWM Activity

Dead Time

Duty Cycle

Dead Time

Duty Cycle

Dead Time

Duty Cycle

Shutdown Event

ECCPASE bit

FIGURE 16-11:

PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)

PWM Period

PWM Activity

Dead Time

Duty Cycle

Dead Time

Duty Cycle

Dead Time

Duty Cycle

Shutdown Event

ECCPASE bit

ECCPASE

Cleared by Firmware

DS39689E-page 158

Preliminary

PIC18F4321 FAMILY

16.4.9

SETUP FOR PWM OPERATION

16.4.10 OPERATION IN POWER-MANAGED

MODES

The following steps should be taken when configuring

the ECCP module for PWM operation:

In Sleep mode, all clock sources are disabled. Timer2

will not increment and the state of the module will not

change. If the ECCP pin is driving a value, it will continue

to drive that value. When the device wakes up, it will

continue from this state. If Two-Speed Start-ups are

enabled, the initial start-up frequency from INTOSC and

the postscaler may not be stable immediately.

1. Configure the PWM pins, P1A and P1B (and

P1C and P1D, if used), as inputs by setting the

corresponding TRIS bits.

2. Set the PWM period by loading the PR2 register.

3. If auto-shutdown is required, do the following:

• Disable auto-shutdown (ECCPASE = 0)

In PRI_IDLE mode, the primary clock will continue to

clock the ECCP module without change. In all other

power-managed modes, the selected power-managed

mode clock will clock Timer2. Other power-managed

mode clocks will most likely be different than the

primary clock frequency.

• Configure source (FLT0, Comparator 1 or

Comparator 2)

• Wait for non-shutdown condition

4. Configure the ECCP module for the desired

PWM mode and configuration by loading the

CCP1CON register with the appropriate values:

16.4.10.1 Operation with Fail-Safe

Clock Monitor

• Select one of the available output

configurations and direction with the

P1M1:P1M0 bits.

If the Fail-Safe Clock Monitor is enabled, a clock failure

will force the device into the power-managed RC_RUN

mode and the OSCFIF bit (PIR2<7>) will be set. The

ECCP will then be clocked from the internal oscillator

clock source, which may have a different clock

frequency than the primary clock.

• Select the polarities of the PWM output

signals with the CCP1M3:CCP1M0 bits.

5. Set the PWM duty cycle by loading the CCPR1L

register and CCP1CON<5:4> bits.

6. For Half-Bridge Output mode, set the dead-

band delay by loading ECCP1DEL<6:0> with

the appropriate value.

See the previous section for additional details.

16.4.11 EFFECTS OF A RESET

7. If auto-shutdown operation is required, load the

ECCP1AS register:

Both Power-on Reset and subsequent Resets will force

all ports to Input mode and the CCP registers to their

Reset states.

• Select the auto-shutdown sources using the

ECCPAS2:ECCPAS0 bits.

• Select the shutdown states of the PWM

output pins using the PSSAC1:PSSAC0 and

PSSBD1:PSSBD0 bits.

This forces the Enhanced CCP module to reset to a

state compatible with the standard CCP module.

• Set the ECCPASE bit (ECCP1AS<7>).

• Configure the comparators using the CMCON

register.

• Configure the comparator inputs as analog

inputs.

8. If auto-restart operation is required, set the

PRSEN bit (ECCP1DEL<7>).

9. Configure and start TMR2:

• Clear the TMR2 interrupt flag bit by clearing

the TMR2IF bit (PIR1<1>).

• Set the TMR2 prescale value by loading the

T2CKPS bits (T2CON<1:0>).

• Enable Timer2 by setting the TMR2ON bit

(T2CON<2>).

10. Enable PWM outputs after a new PWM cycle

has started:

• Wait until TMRn overflows (TMRnIF bit is set).

• Enable the CCP1/P1A, P1B, P1C and/or P1D

pin outputs by clearing the respective TRIS

bits.

• Clear the ECCPASE bit (ECCP1AS<7>).

Preliminary

DS39689E-page 159

PIC18F4321 FAMILY

TABLE 16-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

RCON

PIR1

GIE/GIEH PEIE/GIEL

TMR0IE

—

INT0IE

RI

RBIE

TO

TMR0IF

PD

INT0IF

POR

RBIF

49

48

52

50

51

(1)

IPEN

SBOREN

ADIF

BOR

(2)

PSPIF

PSPIE

PSPIP

RCIF

RCIE

RCIP

—

TXIF

TXIE

TXIP

EEIF

EEIE

EEIP

SSPIF

SSPIE

SSPIP

BCLIF

BCLIE

BCLIP

CCP1IF

CCP1IE

CCP1IP

HLVDIF

HLVDIE

HLVDIP

TMR2IF

TMR2IE

TMR2IP

TMR3IF

TMR3IE

TMR3IP

TMR1IF

TMR1IE

TMR1IP

CCP2IF

CCP2IE

CCP2IP

(2)

PIE1

ADIE

IPR1

ADIP

PIR2

OSCFIF

OSCFIE

OSCFIP

CMIF

CMIE

CMIP

PIE2

—

IPR2

—

TRISB

TRISC

PORTB Data Direction Control Register

PORTC Data Direction Control Register

PORTD Data Direction Control Register

Timer1 Register Low Byte

(2)

TRISD

TMR1L

TMR1H

T1CON

TMR2

Timer1 Register High Byte

RD16

Timer2 Register

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0

T1RUN

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

T2CON

PR2

—

Timer2 Period Register

Timer3 Register Low Byte

Timer3 Register High Byte

TMR3L

TMR3H

T3CON

CCPR1L

CCPR1H

CCP1CON

RD16

T3CCP2

T3CKPS1 T3CKPS0

T3CCP1

T3SYNC TMR3CS TMR3ON

CCP1M2 CCP1M1 CCP1M0

Capture/Compare/PWM Register 1 Low Byte

Capture/Compare/PWM Register 1 High Byte

(2)

P1M1

P1M0

DC1B1

DC1B0

CCP1M3

PSSAC1

(2)

ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0

PSSAC0 PSSBD1

PSSBD0

(2)

ECCP1DEL

PRSEN

PDC6

PDC5

PDC4

PDC3

PDC2

PDC1

PDC0

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.

Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled

and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.

2: These registers and/or bits are unimplemented on 28-pin devices; always maintain these bits clear.

DS39689E-page 160

Preliminary

PIC18F4321 FAMILY

17.3 SPI Mode

17.0 MASTER SYNCHRONOUS

SERIAL PORT (MSSP)

MODULE

The SPI mode allows 8 bits of data to be synchronously

transmitted and received simultaneously. All four SPI

modes are supported. To accomplish communication,

typically three pins are used:

17.1 Master SSP (MSSP) Module

Overview

• Serial Data Out (SDO) – RC5/SDO

• Serial Data In (SDI) – RC4/SDI/SDA

• Serial Clock (SCK) – RC3/SCK/SCL

The Master Synchronous Serial Port (MSSP) module is

a serial interface, useful for communicating with other

peripheral or microcontroller devices. These peripheral

devices may be serial EEPROMs, shift registers,

display drivers, A/D converters, etc. The MSSP module

can operate in one of two modes:

Additionally, a fourth pin may be used when in a Slave

mode of operation:

• Slave Select (SS) – RA5/AN4/SS/HLVDIN/C2OUT

Figure 17-1 shows the block diagram of the MSSP

module when operating in SPI mode.

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I²C™)

- Full Master mode

FIGURE 17-1:

MSSP BLOCK DIAGRAM

(SPI MODE)

- Slave mode (with address masking for both

10-bit and 7-bit addressing)

The I²C interface supports the following modes in

hardware:

Internal

Data Bus

Read

Write

• Master mode

• Multi-Master mode

• Slave mode

SSPBUF reg

SSPSR reg

RC4/SDI/SDA

RC5/SDO

17.2 Control Registers

Shift

Clock

The MSSP module has three associated registers.

These include a status register (SSPSTAT) and two

control registers (SSPCON1 and SSPCON2). The use

of these registers and their individual Configuration bits

differ significantly depending on whether the MSSP

module is operated in SPI or I²C mode.

bit 0

RA5/AN4/SS/

HLVDIN/C2OUT

Control

Enable

SS

Additional details are provided under the individual

sections.

Edge

Select

2

Clock Select

SSPM3:SSPM0

SMP:CKE

2

4

TMR2 Output

RC3/SCK/

SCL

(

)

2

Edge

Select

TOSC

Prescaler

4, 16, 64

Data to TX/RX in SSPSR

TRIS bit

Preliminary

DS39689E-page 161

PIC18F4321 FAMILY

SSPSR is the shift register used for shifting data in or

out. SSPBUF is the buffer register to which data bytes

are written to or read from.

17.3.1

REGISTERS

The MSSP module has four registers for SPI mode

operation. These are:

In receive operations, SSPSR and SSPBUF together

create a double-buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

• MSSP Control Register 1 (SSPCON1)

• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer Register

(SSPBUF)

During transmission, the SSPBUF is not double-

buffered. A write to SSPBUF will write to both SSPBUF

and SSPSR.

• MSSP Shift Register (SSPSR) – Not directly

accessible

SSPCON1 and SSPSTAT are the control and status

registers in SPI mode operation. The SSPCON1 register

is readable and writable. The lower 6 bits of the

SSPSTAT are read-only. The upper two bits of the

SSPSTAT are read/write.

REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)

R/W-0

SMP

R/W-0

CKE

R-0

D/A

R-0

P

R-0

S

R-0

UA

R-0

BF

R/W

bit 7

bit 0

bit 7

bit 6

SMP: Sample bit

SPI Master mode:

1= Input data sampled at end of data output time

0= Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode.

CKE: SPI Clock Select bit

1= Transmit occurs on transition from active to Idle clock state

0= Transmit occurs on transition from Idle to active clock state

Note:

Polarity of clock state is set by the CKP bit (SSPCON1<4>).

bit 5

bit 4

D/A: Data/Address bit

Used in I²C™ mode only.

P: Stop bit

Used in I²C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is

cleared.

bit 3

bit 2

bit 1

bit 0

S: Start bit

Used in I²C mode only.

R/W: Read/Write Information bit

Used in I²C mode only.

UA: Update Address bit

Used in I²C mode only.

BF: Buffer Full Status bit (Receive mode only)

1= Receive complete, SSPBUF is full

0= Receive not complete, SSPBUF is empty

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39689E-page 162

Preliminary

PIC18F4321 FAMILY

REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)

R/W-0

WCOL

R/W-0

CKP

R/W-0

SSPOV

SSPEN

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

bit 7

bit 6

WCOL: Write Collision Detect bit (Transmit mode only)

1= The SSPBUF register is written while it is still transmitting the previous word

(must be cleared in software)

0= No collision

SSPOV: Receive Overflow Indicator bit

SPI Slave mode:

1= A new byte is received while the SSPBUF register is still holding the previous data. In case

of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user

must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be

cleared in software).

0= No overflow

Note:

In Master mode, the overflow bit is not set since each new reception (and

transmission) is initiated by writing to the SSPBUF register.

bit 5

bit 4

SSPEN: Synchronous Serial Port Enable bit

1= Enables serial port and configures SCK, SDO, SDI and SS as serial port pins

0= Disables serial port and configures these pins as I/O port pins

Note:

When enabled, these pins must be properly configured as input or output.

CKP: Clock Polarity Select bit

1= Idle state for clock is a high level

0= Idle state for clock is a low level

bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0101= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin

0100= SPI Slave mode, clock = SCK pin, SS pin control enabled

0011= SPI Master mode, clock = TMR2 output/2

0010= SPI Master mode, clock = FOSC/64

0001= SPI Master mode, clock = FOSC/16

0000= SPI Master mode, clock = FOSC/4

Note:

Bit combinations not specifically listed here are either reserved or implemented in

I²C™ mode only.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39689E-page 163

PIC18F4321 FAMILY

reading the data that was just received. Any write to the

SSPBUF register during transmission/reception of data

will be ignored and the write collision detect bit, WCOL

(SSPCON1<7>), will be set. User software must clear

the WCOL bit so that it can be determined if the following

write(s) to the SSPBUF register completed successfully.

17.3.2

OPERATION

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPCON1<5:0> and SSPSTAT<7:6>).

These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data to transfer is written to the SSPBUF. The

Buffer Full bit, BF (SSPSTAT<0>), indicates when

SSPBUF has been loaded with the received data

(transmission is complete). When the SSPBUF is read,

the BF bit is cleared. This data may be irrelevant if the

SPI is only a transmitter. Generally, the MSSP interrupt

is used to determine when the transmission/reception

has completed. The SSPBUF must be read and/or

written. If the interrupt method is not going to be used,

then software polling can be done to ensure that a write

collision does not occur. Example 17-1 shows the

loading of the SSPBUF (SSPSR) for data transmission.

• Data Input Sample Phase (middle or end of data

output time)

• Clock Edge (output data on rising/falling edge

of SCK)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

The MSSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR

until the received data is ready. Once the 8 bits of data

have been received, that byte is moved to the SSPBUF

register. Then, the Buffer Full detect bit, BF

(SSPSTAT<0>) and the interrupt flag bit, SSPIF, are

set. This double-buffering of the received data

(SSPBUF) allows the next byte to start reception before

The SSPSR is not directly readable or writable and can

only be accessed by addressing the SSPBUF register.

Additionally, the MSSP status register (SSPSTAT)

indicates the various status conditions.

EXAMPLE 17-1:

LOADING THE SSPBUF (SSPSR) REGISTER

LOOP

BTFSS

BRA

SSPSTAT, BF

LOOP

;Has data been received (transmit complete)?

;No

MOVF

SSPBUF, W

;WREG reg = contents of SSPBUF

MOVWF

RXDATA

;Save in user RAM, if data is meaningful

MOVF

MOVWF

TXDATA, W

SSPBUF

;W reg = contents of TXDATA

;New data to xmit

DS39689E-page 164

Preliminary

PIC18F4321 FAMILY

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

17.3.3

ENABLING SPI I/O

To enable the serial port, MSSP Enable bit, SSPEN

(SSPCON1<5>), must be set. To reset or reconfigure

SPI mode, clear the SSPEN bit, reinitialize the

SSPCON registers and then set the SSPEN bit. This

configures the SDI, SDO, SCK and SS pins as serial

port pins. For the pins to behave as the serial port

function, some must have their data direction bits (in

the TRIS register) appropriately programmed as

follows:

17.3.4

TYPICAL CONNECTION

Figure 17-2 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their pro-

grammed clock edge and latched on the opposite edge

of the clock. Both processors should be programmed to

the same Clock Polarity (CKP), then both controllers

would send and receive data at the same time.

Whether the data is meaningful (or dummy data)

depends on the application software. This leads to

three scenarios for data transmission:

• SDI is automatically controlled by the SPI module

• SDO must have TRISC<5> bit cleared

• SCK (Master mode) must have TRISC<3> bit

cleared

• SCK (Slave mode) must have TRISC<3> bit set

• SS must have TRISA<5> bit set

• Master sends data – Slave sends dummy data

• Master sends data – Slave sends data

• Master sends dummy data – Slave sends data

FIGURE 17-2:

SPI MASTER/SLAVE CONNECTION

SPI Master SSPM3:SSPM0 = 00xxb

SPI Slave SSPM3:SSPM0 = 010xb

SDO

SDI

Serial Input Buffer

(SSPBUF)

Serial Input Buffer

(SSPBUF)

SDI

SDO

Shift Register

(SSPSR)

Shift Register

(SSPSR)

LSb

MSb

LSb

Serial Clock

SCK

PROCESSOR 1

PROCESSOR 2

Preliminary

DS39689E-page 165

PIC18F4321 FAMILY

The clock polarity is selected by appropriately

programming the CKP bit (SSPCON1<4>). This then,

would give waveforms for SPI communication as

shown in Figure 17-3, Figure 17-5 and Figure 17-6,

where the MSB is transmitted first. In Master mode, the

SPI clock rate (bit rate) is user-programmable to be one

of the following:

17.3.5

MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCK. The master determines

when the slave (Processor 2, Figure 17-2) is to

broadcast data by the software protocol.

In Master mode, the data is transmitted/received as

soon as the SSPBUF register is written to. If the SPI

operation is only going to receive, the SDO output

could be disabled (programmed as an input). The

SSPSR register will continue to shift in the signal

present on the SDI pin at the programmed clock rate.

As each byte is received, it will be loaded into the

SSPBUF register as if a normal received byte (inter-

rupts and status bits appropriately set). This could be

useful in receiver applications as a “Line Activity

Monitor” mode.

• FOSC/4 (or TCY)

• FOSC/16 (or 4 • TCY)

• FOSC/64 (or 16 • TCY)

• Timer2 output/2

This allows a maximum data rate (at 40 MHz) of

10.00 Mbps.

Figure 17-3 shows the waveforms for Master mode.

When the CKE bit is set, the SDO data is valid before

there is a clock edge on SCK. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSPBUF is loaded with the received

data is shown.

FIGURE 17-3:

SPI MODE WAVEFORM (MASTER MODE)

Write to

SSPBUF

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

4 Clock

Modes

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

(CKE = 0)

bit 7

bit 3

SDO

(CKE = 1)

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SDI

(SMP = 1)

bit 0

bit 7

Input

Sample

(SMP = 1)

SSPIF

Next Q4 Cycle

after Q2↓

SSPSR to

SSPBUF

DS39689E-page 166

Preliminary

PIC18F4321 FAMILY

SDO pin is driven. When the SS pin goes high, the SDO

pin is no longer driven, even if in the middle of a

transmitted byte and becomes a floating output. External

pull-up/pull-down resistors may be desirable depending

on the application.

17.3.6

SLAVE MODE

In Slave mode, the data is transmitted and received as

the external clock pulses appear on SCK. When the

last bit is latched, the SSPIF interrupt flag bit is set.

Before enabling the module in SPI Slave mode, the

clock line must match the proper Idle state. The clock

line can be observed by reading the SCK pin. The Idle

state is determined by the CKP bit (SSPCON1<4>).

Note 1: When the SPI interface is in Slave mode

with

SS

control

enabled

(SSPCON1<3:0> = 0100), the SPI mod-

ule will reset if the SS pin is set to VDD.

While in Slave mode, the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times as

specified in the electrical specifications.

2: If the SPI interface is used in Slave mode

with CKE set, then the SS pin control

must be enabled.

When the SPI module resets, the bit counter is forced

to ‘0’. This can be done by either forcing the SS pin to

a high level or clearing the SSPEN bit.

While in Sleep mode, the slave can transmit/receive

data. When a byte is received, the device will wake-up

from Sleep.

To emulate two-wire communication, the SDO pin can

be connected to the SDI pin. When the SPI needs to

operate as a receiver, the SDO pin can be configured

as an input. This disables transmissions from the SDO.

The SDI can always be left as an input (SDI function)

since it cannot create a bus conflict.

17.3.7

SLAVE SELECT

SYNCHRONIZATION

The SS pin allows a Synchronous Slave mode. The SPI

operation must be in Slave mode with the SS pin control

enabled (SSPCON1<3:0> = 04h). When the SS pin is

low, transmission and reception are enabled and the

FIGURE 17-4:

SLAVE SYNCHRONIZATION WAVEFORM

SS

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

bit 6

bit 7

bit 0

SDO

bit 7

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 Cycle

after Q2↓

SSPSR to

SSPBUF

Preliminary

DS39689E-page 167

PIC18F4321 FAMILY

FIGURE 17-5:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

SS

Optional

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

bit 6

bit 2

bit 5

bit 4

bit 3

bit 1

bit 0

SDO

bit 7

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 Cycle

after Q2↓

SSPSR to

SSPBUF

FIGURE 17-6:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SS

Not Optional

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

Write to

SSPBUF

bit 6

bit 3

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

bit 7

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 Cycle

after Q2↓

SSPSR to

SSPBUF

DS39689E-page 168

Preliminary

PIC18F4321 FAMILY

17.3.8

OPERATION IN POWER-MANAGED

MODES

17.3.9

EFFECTS OF A RESET

A Reset disables the MSSP module and terminates the

current transfer.

In SPI Master mode, module clocks may be operating

at a different speed than when in full power mode. In

the case of Sleep mode, all clocks are halted.

17.3.10 BUS MODE COMPATIBILITY

Table 17-1 shows the compatibility between the

standard SPI modes and the states of the CKP and

CKE control bits.

In Idle modes, a clock is provided to the peripherals.

That clock should be from the primary clock source, the

secondary clock (Timer1 oscillator at 32.768 kHz) or

the INTOSC source. See Section 2.7 “Clock Sources

and Oscillator Switching” for additional information.

TABLE 17-1: SPI BUS MODES

Control Bits State

Standard SPI Mode

In most cases, the speed that the master clocks SPI

data is not important; however, this should be

evaluated for each system.

Terminology

CKP

CKE

0, 0

0, 1

1, 0

1, 1

0

1

0

1

0

If MSSP interrupts are enabled, they can wake the

controller from Sleep mode, or one of the Idle modes,

when the master completes sending data. If an exit

from Sleep or Idle mode is not desired, MSSP

interrupts should be disabled.

There is also an SMP bit which controls when the data

is sampled.

If the Sleep mode is selected, all module clocks are

halted and the transmission/reception will remain in

that state until the devices wakes. After the device

returns to Run mode, the module will resume

transmitting and receiving data.

In SPI Slave mode, the SPI Transmit/Receive Shift

register operates asynchronously to the device. This

allows the device to be placed in any power-managed

mode and data to be shifted into the SPI Transmit/

Receive Shift register. When all 8 bits have been

received, the MSSP interrupt flag bit will be set and if

enabled, will wake the device.

TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF

CCP1IF

CCP1IE

CCP1IP

INT0IF

RBIF

49

52

50

PSPIF⁽¹⁾

PSPIE⁽¹⁾

PSPIP⁽¹⁾

ADIF

ADIE

ADIP

RCIF

RCIE

RCIP

TMR2IF

TMR1IF

PIE1

TXIE

TMR2IE TMR1IE

TMR2IP TMR1IP

IPR1

TXIP

TRISA

TRISA7⁽²⁾TRISA6⁽²⁾PORTA Data Direction Control Register

TRISC

SSPBUF

SSPCON1

SSPSTAT

PORTC Data Direction Control Register

MSSP Receive Buffer/Transmit Register

WCOL

SMP

SSPOV

CKE

SSPEN

D/A

CKP

P

SSPM3

S

SSPM2

R/W

SSPM1

UA

SSPM0

BF

Legend: Shaded cells are not used by the MSSP in SPI mode.

Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’.

2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary

oscillator modes. When disabled, these bits read as ‘0’.

Preliminary

DS39689E-page 169

PIC18F4321 FAMILY

2

17.4.1

REGISTERS

17.4 I C Mode

The MSSP module has six registers for I²C operation.

These are:

The MSSP module in I²C mode fully implements all

master and slave functions (including general call

support) and provides interrupts on Start and Stop bits

in hardware to determine a free bus (multi-master

function). The MSSP module implements the standard

mode specifications, as well as 7-bit and 10-bit

addressing.

• MSSP Control Register 1 (SSPCON1)

• MSSP Control Register 2 (SSPCON2)

• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer Register

(SSPBUF)

Two pins are used for data transfer:

• MSSP Shift Register (SSPSR) – Not directly

accessible

• Serial clock (SCL) – RC3/SCK/SCL

• Serial data (SDA) – RC4/SDI/SDA

• MSSP Address Register (SSPADD)

The user must configure these pins as inputs or outputs

through the TRISC<4:3> bits.

SSPCON1, SSPCON2 and SSPSTAT are the control

and status registers in I²C mode operation. The

SSPCON1 and SSPCON2 registers are readable and

writable. The lower 6 bits of the SSPSTAT are read-only.

The upper two bits of the SSPSTAT are read/write.

FIGURE 17-7:

MSSP BLOCK DIAGRAM

(I²C™ MODE)

SSPSR is the shift register used for shifting data in or

out. SSPBUF is the buffer register to which data bytes

are written to or read from.

Internal

Data Bus

Read

Write

SSPADD register holds the slave device address when

the MSSP is configured in I²C Slave mode. When the

MSSP is configured in Master mode, the lower seven

bits of SSPADD act as the Baud Rate Generator reload

value.

SSPBUF reg

RC3/SCK/SCL

Shift

Clock

In receive operations, SSPSR and SSPBUF together

create a double-buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

SSPSR reg

RC4/SDI/

SDA

MSb

LSb

Match Detect

Addr Match

During transmission, the SSPBUF is not double-

buffered. A write to SSPBUF will write to both SSPBUF

and SSPSR.

SSPADD reg

Start and

Set, Reset

S, P bits

(SSPSTAT reg)

Stop bit Detect

DS39689E-page 170

Preliminary

PIC18F4321 FAMILY

REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I²C™ MODE)

R/W-0

SMP

R/W-0

CKE

R-0

D/A

R-0

P

R-0

S

R-0

UA

R-0

BF

R/W

bit 7

bit 0

bit 7

SMP: Slew Rate Control bit

In Master or Slave mode:

1= Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)

0= Slew rate control enabled for High-Speed mode (400 kHz)

bit 6

bit 5

CKE: SMBus Select bit

In Master or Slave mode:

1= Enable SMBus specific inputs

0= Disable SMBus specific inputs

D/A: Data/Address bit

In Master mode:

Reserved.

In Slave mode:

1= Indicates that the last byte received or transmitted was data

0= Indicates that the last byte received or transmitted was address

bit 4

bit 3

bit 2

P: Stop bit

1= Indicates that a Stop bit has been detected last

0= Stop bit was not detected last

Note:

This bit is cleared on Reset and when SSPEN is cleared.

S: Start bit

1= Indicates that a Start bit has been detected last

0= Start bit was not detected last

Note:

This bit is cleared on Reset and when SSPEN is cleared.

R/W: Read/Write Information bit (I²C mode only)

In Slave mode:

1= Read

0= Write

Note:

This bit holds the R/W bit information following the last address match. This bit is

only valid from the address match to the next Start bit, Stop bit or not ACK bit.

In Master mode:

1= Transmit is in progress

0= Transmit is not in progress

Note:

ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is

in Active mode.

bit 1

bit 0

UA: Update Address bit (10-bit Slave mode only)

1= Indicates that the user needs to update the address in the SSPADD register

0= Address does not need to be updated

BF: Buffer Full Status bit

In Transmit mode:

1= SSPBUF is full

0= SSPBUF is empty

In Receive mode:

1= SSPBUF is full (does not include the ACK and Stop bits)

0= SSPBUF is empty (does not include the ACK and Stop bits)

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39689E-page 171

PIC18F4321 FAMILY

REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I²C™ MODE)

R/W-0

WCOL

R/W-0

CKP

R/W-0

SSPOV

SSPEN

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

bit 7

WCOL: Write Collision Detect bit

In Master Transmit mode:

1= A write to the SSPBUF register was attempted while the I²C conditions were not valid for a

transmission to be started (must be cleared in software)

0= No collision

In Slave Transmit mode:

1= The SSPBUF register is written while it is still transmitting the previous word (must be

cleared in software)

0= No collision

In Receive mode (Master or Slave modes):

This is a “don’t care” bit.

bit 6

SSPOV: Receive Overflow Indicator bit

In Receive mode:

1= A byte is received while the SSPBUF register is still holding the previous byte (must be

cleared in software)

0= No overflow

In Transmit mode:

This is a “don’t care” bit in Transmit mode.

bit 5

bit 4

SSPEN: Master Synchronous Serial Port Enable bit

1= Enables the serial port and configures the SDA and SCL pins as the serial port pins

0= Disables serial port and configures these pins as I/O port pins

Note:

When enabled, the SDA and SCL pins must be properly configured as inputs.

CKP: SCK Release Control bit

In Slave mode:

1= Release clock

0= Holds clock low (clock stretch), used to ensure data setup time

In Master mode:

Unused in this mode.

bit 3-0 SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits

1111= I²C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

1110= I²C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

1011= I²C Firmware Controlled Master mode (slave Idle)

1000= I²C Master mode, clock = FOSC/(4 * (SSPADD + 1))

0111= I²C Slave mode, 10-bit address

0110= I²C Slave mode, 7-bit address

Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39689E-page 172

Preliminary

PIC18F4321 FAMILY

REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I²C™ MODE)

R/W-0

GCEN

R/W-0

ACKDT/ ACKEN⁽¹⁾

R/W-0

RCEN⁽¹⁾

R/W-0

PEN⁽¹⁾

R/W-0

RSEN⁽¹⁾

/

R/W-0

SEN⁽¹⁾

ACKSTAT

/

ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1

bit 7

bit 0

bit 7

bit 6

bit 5

GCEN: General Call Enable bit (Slave mode only)

1= Enable interrupt when a general call address (0000h) is received in the SSPSR

0= General call address disabled

ACKSTAT: Acknowledge Status bit (Master Transmit mode only)

1= Acknowledge was not received from slave

0= Acknowledge was received from slave

ACKDT/ADMSK5: Acknowledge Data bit

In Master Receive mode:

1= Not Acknowledge

0= Acknowledge

Note:

Value that will be transmitted when the user initiates an Acknowledge sequence at

the end of a receive.

In Slave mode:

1= Address masking of ADD5 enabled

0= Address masking of ADD5 disabled

bit 4

ACKEN/ADMSK4: Acknowledge Sequence Enable bit

In Master Receive mode:⁽¹⁾

1= Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.

Automatically cleared by hardware.

0= Acknowledge sequence Idle

In Slave mode:

1= Address masking of ADD4 enabled

0= Address masking of ADD4 disabled

bit 3

RCEN/ADMSK3: Receive Enable bit

In Master Receive mode:⁽¹⁾

1= Enables Receive mode for I²C

0= Receive Idle

In Slave mode:

1= Address masking of ADD3 enabled

0= Address masking of ADD3 disabled

bit 2

PEN/ADMSK2: Stop Condition Enable bit

In Master mode:⁽¹⁾

1= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.

0= Stop condition Idle

In Slave mode:

1= Address masking of ADD2 enabled

0= Address masking of ADD2 disabled

bit 1

RSEN/ADMSK1: Repeated Start Condition Enable bit

In Master mode:⁽¹⁾

1= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.

0= Repeated Start condition Idle

In Slave mode (7-bit Address mode):

1= Address masking of ADD1 enabled

0= Address masking of ADD1 disabled

In Slave mode (10-bit Address mode):

1= Address masking of ADD1 and ADD0 enabled

0= Address masking of ADD1 and ADD0 disabled

Preliminary

DS39689E-page 173

PIC18F4321 FAMILY

REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I²C™ MODE) – CONTINUED

R/W-0

GCEN

R/W-0

ACKDT/ ACKEN⁽¹⁾

R/W-0

RCEN⁽¹⁾

R/W-0

PEN⁽¹⁾

R/W-0

RSEN⁽¹⁾

/

R/W-0

SEN⁽¹⁾

ACKSTAT

/

ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1

bit 7

bit 0

SEN: Start Condition Enable/Stretch Enable bit⁽¹⁾

In Master mode:

1= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.

0= Start condition Idle

In Slave mode:

1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)

0= Clock stretching is disabled

Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I²C module is active, these bits

may not be set (no spooling) and the SSPBUF may not be written (or writes to the

SSPBUF are disabled).

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

REGISTER 17-6: SSPADD: MSSP ADDRESS REGISTER⁽¹⁾

R/W-0

ADD7

R/W-0

ADD6

R/W-0

ADD5

R/W-0

ADD4

R/W-0

ADD3

R/W-0

ADD2

R/W-0

ADD1

R/W-0

ADD0

bit 7

bit 0

bit 7-0 ADD<7:0>: MSSP Address bits

Note 1: MSSP Address register in 1²C Slave mode. MSSP Baud Rate register in I²C Master

mode.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39689E-page 174

Preliminary

PIC18F4321 FAMILY

17.4.2

OPERATION

17.4.3.1

Addressing

The MSSP module functions are enabled by setting

MSSP Enable bit, SSPEN (SSPCON1<5>).

The SSPCON1 register allows control of the I²C

operation. Four mode selection bits (SSPCON1<3:0>)

allow one of the following I²C modes to be selected:

• I²C Master mode clock

• I²C Slave mode (7-bit address)

• I²C Slave mode (10-bit address)

Once the MSSP module has been enabled, it waits for

a Start condition to occur. Following the Start condition,

the 8 bits are shifted into the SSPSR register. All incom-

ing bits are sampled with the rising edge of the clock

(SCL) line. The value of register SSPSR<7:1> is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match and the BF

and SSPOV bits are clear, the following events occur:

• I²C Slave mode (7-bit address) with Start and

Stop bit interrupts enabled

• I²C Slave mode (10-bit address) with Start and

Stop bit interrupts enabled

1. The SSPSR register value is loaded into the

SSPBUF register.

2. The Buffer Full bit, BF, is set.

3. An ACK pulse is generated.

• I²C Firmware Controlled Master mode, slave is Idle

4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is

set (interrupt is generated, if enabled) on the

falling edge of the ninth SCL pulse.

Selection of any I²C mode with the SSPEN bit set,

forces the SCL and SDA pins to be open-drain,

provided these pins are programmed to inputs by

setting the appropriate TRISC bits. To ensure proper

operation of the module, pull-up resistors must be

provided externally to the SCL and SDA pins.

In 10-bit Address mode, two address bytes need to be

received by the slave. The five Most Significant bits

(MSbs) of the first address byte specify if this is a 10-bit

address. Bit R/W (SSPSTAT<2>) must specify a write so

the slave device will receive the second address byte.

For a 10-bit address, the first byte would equal ‘11110

A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the

address. The sequence of events for 10-bit address is as

follows, with steps 7 through 9 for the slave-transmitter:

17.4.3

SLAVE MODE

In Slave mode, the SCL and SDA pins must be config-

ured as inputs (TRISC<4:3> set). The MSSP module

will override the input state with the output data when

required (slave-transmitter).

The I²C Slave mode hardware will always generate an

interrupt on an address match. Address masking will

allow the hardware to generate an interrupt for more

than one address (up to 31 in 7-bit Addressing mode

and up to 63 in 10-bit Addressing mode). Through the

mode select bits, the user can also choose to interrupt

on Start and Stop bits

1. Receive first (high) byte of address (bits SSPIF,

BF and UA (SSPSTAT<1>) are set).

2. Update the SSPADD register with second (low)

byte of address (clears bit UA and releases the

SCL line).

3. Read the SSPBUF register (clears bit BF) and

clear flag bit, SSPIF.

4. Receive second (low) byte of address (bits

SSPIF, BF and UA are set).

When an address is matched, or the data transfer after

an address match is received, the hardware auto-

matically will generate the Acknowledge (ACK) pulse

and load the SSPBUF register with the received value

currently in the SSPSR register.

5. Update the SSPADD register with the first (high)

byte of address. If match releases SCL line, this

will clear bit UA.

6. Read the SSPBUF register (clears bit BF) and

clear flag bit, SSPIF.

Any combination of the following conditions will cause

the MSSP module not to give this ACK pulse:

7. Receive Repeated Start condition.

• The Buffer Full bit, BF (SSPSTAT<0>), was set

before the transfer was received.

8. Receive first (high) byte of address (bits SSPIF

and BF are set).

• The overflow bit, SSPOV (SSPCON1<6>), was

set before the transfer was received.

9. Read the SSPBUF register (clears bit BF) and

clear flag bit, SSPIF.

In this case, the SSPSR register value is not loaded

into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The

BF bit is cleared by reading the SSPBUF register, while

bit SSPOV is cleared through software.

The SCL clock input must have a minimum high and

low for proper operation. The high and low times of the

I²C specification, as well as the requirement of the

MSSP module, are shown in timing parameter 100 and

parameter 101.

Preliminary

DS39689E-page 175

PIC18F4321 FAMILY

• 10-bit Address mode

17.4.3.2

Address Masking

Address mask bits, ADMSK<5:2>, mask the

corresponding address bits in the SSPADD register. In

addition, ADMSK<1> simultaneously masks the two

LSBs of the address, ADD<1:0>. For any ADMSK bits

that are active (ADMSK<n> = 1), the corresponding

address bit is ignored (ADD<n> = x). Also note that

although in 10-bit Addressing mode, the upper address

bits reuse part of the SSPADD register bits, the address

mask bits do not interact with those bits. They only

affect the lower address bits.

Masking an address bit causes that bit to become a

“don’t care”. When one address bit is masked, two

addresses will be Acknowledged and cause an inter-

rupt. It is possible to mask more than one address bit at

a time, which makes it possible to Acknowledge up to

31 addresses in 7-bit Addressing mode and up to 63

addresses in 10-bit Addressing mode (see

Example 17-2).

The I²C slave behaves the same way whether address

masking is used or not. However, when address mask-

ing is used, the I²C slave can Acknowledge multiple

addresses and cause interrupts. When this occurs, it is

necessary to determine which address caused the

interrupt by checking the SSPBUF register.

Note 1: ADMSK<1> masks the two Least

Significant bits of the address.

2: The two Most Significant bits of the

address are not affected by address

masking.

• 7-bit Address mode

Address mask bits, ADMSK<5:1>, mask the corre-

sponding address bits in the SSPADD register. For any

ADMSK bits that are active (ADMSK<n> = 1), the

corresponding address bit is ignored (ADD<n> = x). For

the module to issue an address Acknowledge, it is suffi-

cient to match only on addresses that do not have an

active address mask.

EXAMPLE 17-2:

ADDRESS MASKING

7-bit Addressing mode:

SSPADD<7:1> = 1010 0000

ADMSK<5:1> = 00 111

Addresses Acknowledged = 0xA0, 0xA2, 0xA4, 0xA6, 0xA8, 0xAA, 0xAC, 0xAE

10-bit Addressing mode:

SSPADD<7:0> = 1010 0000(The two MSbs are ignored in this example since they are not affected)

ADMSK<5:1> = 00 111

Addresses Acknowledged = 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB,

0xAC, 0xAD, 0xAE, 0xAF

The upper two bits are not affected by the address masking.

DS39689E-page 176

Preliminary

PIC18F4321 FAMILY

17.4.3.3

Reception

17.4.3.4

Transmission

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

register is cleared. The received address is loaded into

the SSPBUF register and the SDA line is held low

(ACK).

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit and pin RC3/SCK/SCL is held

low regardless of SEN (see Section 17.4.4 “Clock

Stretching” for more detail). By stretching the clock,

the master will be unable to assert another clock pulse

until the slave is done preparing the transmit data. The

transmit data must be loaded into the SSPBUF register

which also loads the SSPSR register. Then pin RC3/

SCK/SCL should be enabled by setting bit, CKP

(SSPCON1<4>). The eight data bits are shifted out on

the falling edge of the SCL input. This ensures that the

SDA signal is valid during the SCL high time

(Figure 17-10).

When the address byte overflow condition exists, then

the no Acknowledge (ACK) pulse is given. An overflow

condition is defined as either bit BF (SSPSTAT<0>) is

set, or bit SSPOV (SSPCON1<6>) is set.

An MSSP interrupt is generated for each data transfer

byte. Flag bit, SSPIF (PIR1<3>), must be cleared in

software. The SSPSTAT register is used to determine

the status of the byte.

If SEN is enabled (SSPCON2<0> = 1), RC3/SCK/SCL

will be held low (clock stretch) following each data

transfer. The clock must be released by setting bit,

CKP (SSPCON1<4>). See Section 17.4.4 “Clock

Stretching” for more detail.

The ACK pulse from the master-receiver is latched on

the rising edge of the ninth SCL input pulse. If the SDA

line is high (not ACK), then the data transfer is

complete. In this case, when the ACK is latched by the

slave, the slave logic is reset (resets SSPSTAT

register) and the slave monitors for another occurrence

of the Start bit. If the SDA line was low (ACK), the next

transmit data must be loaded into the SSPBUF register.

Again, pin RC3/SCK/SCL must be enabled by setting

bit CKP.

An MSSP interrupt is generated for each data transfer

byte. The SSPIF bit must be cleared in software and

the SSPSTAT register is used to determine the status

of the byte. The SSPIF bit is set on the falling edge of

the ninth clock pulse.

Preliminary

DS39689E-page 177

PIC18F4321 FAMILY

2

FIGURE 17-8:

I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)

DS39689E-page 178

Preliminary

PIC18F4321 FAMILY

2

FIGURE 17-9:

I C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011

(RECEPTION, 7-BIT ADDRESS)

Preliminary

DS39689E-page 179

PIC18F4321 FAMILY

2

FIGURE 17-10:

I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)

DS39689E-page 180

Preliminary

PIC18F4321 FAMILY

FIGURE 17-11:

I²C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK = 01001

(RECEPTION, 10-BIT ADDRESS)

Preliminary

DS39689E-page 181

PIC18F4321 FAMILY

FIGURE 17-12:

I²C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)

DS39689E-page 182

Preliminary

PIC18F4321 FAMILY

2

FIGURE 17-13:

I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)

Preliminary

DS39689E-page 183

PIC18F4321 FAMILY

17.4.4

CLOCK STRETCHING

17.4.4.3

Clock Stretching for 7-bit Slave

Transmit Mode

Both 7-bit and 10-bit Slave modes implement

automatic clock stretching during a transmit sequence.

7-bit Slave Transmit mode implements clock stretching

by clearing the CKP bit after the falling edge of the

ninth clock if the BF bit is clear. This occurs regardless

of the state of the SEN bit.

The SEN bit (SSPCON2<0>) allows clock stretching to

be enabled during receives. Setting SEN will cause

the SCL pin to be held low at the end of each data

receive sequence.

The user’s ISR must set the CKP bit before transmis-

sion is allowed to continue. By holding the SCL line

low, the user has time to service the ISR and load the

contents of the SSPBUF before the master device can

initiate another transmit sequence (see Figure 17-10).

17.4.4.1

Clock Stretching for 7-bit Slave

Receive Mode (SEN = 1)

In 7-bit Slave Receive mode, on the falling edge of the

ninth clock at the end of the ACK sequence if the BF

bit is set, the CKP bit in the SSPCON1 register is

automatically cleared, forcing the SCL output to be

held low. The CKP bit being cleared to ‘0’ will assert

the SCL line low. The CKP bit must be set in the user’s

ISR before reception is allowed to continue. By holding

the SCL line low, the user has time to service the ISR

and read the contents of the SSPBUF before the

master device can initiate another receive sequence.

This will prevent buffer overruns from occurring (see

Figure 17-15).

Note 1: If the user loads the contents of SSPBUF,

setting the BF bit before the falling edge of

the ninth clock, the CKP bit will not be

cleared and clock stretching will not occur.

2: The CKP bit can be set in software

regardless of the state of the BF bit.

17.4.4.4

Clock Stretching for 10-bit Slave

Transmit Mode

In 10-bit Slave Transmit mode, clock stretching is

controlled during the first two address sequences by

the state of the UA bit, just as it is in 10-bit Slave

Receive mode. The first two addresses are followed

by a third address sequence which contains the high-

order bits of the 10-bit address and the R/W bit set to

‘1’. After the third address sequence is performed, the

UA bit is not set, the module is now configured in

Transmit mode and clock stretching is controlled by

the BF flag as in 7-bit Slave Transmit mode (see

Figure 17-13).

Note 1: If the user reads the contents of the

SSPBUF before the falling edge of the

ninth clock, thus clearing the BF bit, the

CKP bit will not be cleared and clock

stretching will not occur.

2: The CKP bit can be set in software

regardless of the state of the BF bit. The

user should be careful to clear the BF bit

in the ISR before the next receive

sequence in order to prevent an overflow

condition.

17.4.4.2

Clock Stretching for 10-bit Slave

Receive Mode (SEN = 1)

In 10-bit Slave Receive mode during the address

sequence, clock stretching automatically takes place

but CKP is not cleared. During this time, if the UA bit is

set after the ninth clock, clock stretching is initiated.

The UA bit is set after receiving the upper byte of the

10-bit address and following the receive of the second

byte of the 10-bit address with the R/W bit cleared to

‘0’. The release of the clock line occurs upon updating

SSPADD. Clock stretching will occur on each data

receive sequence as described in 7-bit mode.

Note:

If the user polls the UA bit and clears it by

updating the SSPADD register before the

falling edge of the ninth clock occurs and if

the user hasn’t cleared the BF bit by read-

ing the SSPBUF register before that time,

then the CKP bit will still NOT be asserted

low. Clock stretching on the basis of the

state of the BF bit only occurs during a

data sequence, not an address sequence.

DS39689E-page 184

Preliminary

PIC18F4321 FAMILY

already asserted the SCL line. The SCL output will

remain low until the CKP bit is set and all other

devices on the I²C bus have deasserted SCL. This

ensures that a write to the CKP bit will not violate the

minimum high time requirement for SCL (see

Figure 17-14).

17.4.4.5

Clock Synchronization and

the CKP bit

When the CKP bit is cleared, the SCL output is forced

to ‘0’. However, clearing the CKP bit will not assert the

SCL output low until the SCL output is already

sampled low. Therefore, the CKP bit will not assert the

SCL line until an external I²C master device has

FIGURE 17-14:

CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDA

SCL

DX

DX – 1

Master device

asserts clock

CKP

Master device

deasserts clock

WR

SSPCON

Preliminary

DS39689E-page 185

PIC18F4321 FAMILY

2

FIGURE 17-15:

I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)

DS39689E-page 186

Preliminary

PIC18F4321 FAMILY

FIGURE 17-16:

I²C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)

Preliminary

DS39689E-page 187

PIC18F4321 FAMILY

If the general call address matches, the SSPSR is

transferred to the SSPBUF, the BF flag bit is set (eighth

bit) and on the falling edge of the ninth bit (ACK bit), the

SSPIF interrupt flag bit is set.

17.4.5

GENERAL CALL ADDRESS

SUPPORT

The addressing procedure for the I²C bus is such that

the first byte after the Start condition usually

determines which device will be the slave addressed by

the master. The exception is the general call address

which can address all devices. When this address is

used, all devices should, in theory, respond with an

Acknowledge.

When the interrupt is serviced, the source for the

interrupt can be checked by reading the contents of the

SSPBUF. The value can be used to determine if the

address was device specific or a general call address.

In 10-bit mode, the SSPADD is required to be updated

for the second half of the address to match and the UA

bit (SSPSTAT<1>) is set. If the general call address is

sampled when the GCEN bit is set, while the slave is

configured in 10-bit Address mode, then the second

half of the address is not necessary, the UA bit will not

be set and the slave will begin receiving data after the

Acknowledge (Figure 17-17).

The general call address is one of eight addresses

reserved for specific purposes by the I²C protocol. It

consists of all ‘0’s with R/W = 0.

The general call address is recognized when the

General Call Enable bit, GCEN, is enabled

(SSPCON2<7> is set). Following a Start bit detect,

8 bits are shifted into the SSPSR and the address is

compared against the SSPADD. It is also compared to

the general call address and fixed in hardware.

FIGURE 17-17:

SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

(7 OR 10-BIT ADDRESS MODE)

Address is compared to General Call Address

after ACK, set interrupt

Receiving Data

D5 D4 D3 D2 D1

ACK

R/W = 0

General Call Address

ACK

9

SDA

SCL

D7 D6

D0

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

9

S

SSPIF

BF (SSPSTAT<0>)

Cleared in software

SSPBUF is read

SSPOV (SSPCON1<6>)

GCEN (SSPCON2<7>)

‘0’

‘1’

DS39689E-page 188

Preliminary

PIC18F4321 FAMILY

17.4.6

MASTER MODE

Note:

The MSSP module, when configured in

I²C Master mode, does not allow queueing

of events. For instance, the user is not

allowed to initiate a Start condition and

immediately write the SSPBUF register to

initiate transmission before the Start

condition is complete. In this case, the

SSPBUF will not be written to and the

WCOL bit will be set, indicating that a write

to the SSPBUF did not occur.

Master mode is enabled by setting and clearing the

appropriate SSPM bits in SSPCON1 and by setting the

SSPEN bit. In Master mode, the SCL and SDA lines

are manipulated by the MSSP hardware.

Master mode of operation is supported by interrupt

generation on the detection of the Start and Stop

conditions. The Stop (P) and Start (S) bits are cleared

from a Reset or when the MSSP module is disabled.

Control of the I²C bus may be taken when the P bit is

set, or the bus is Idle, with both the S and P bits clear.

The following events will cause the MSSP Interrupt

Flag bit, SSPIF, to be set (MSSP interrupt, if enabled):

In Firmware Controlled Master mode, user code

conducts all I²C bus operations based on Start and

Stop bit conditions.

• Start condition

• Stop condition

Once Master mode is enabled, the user has six

options.

• Data transfer byte transmitted/received

• Acknowledge transmit

• Repeated Start

1. Assert a Start condition on SDA and SCL.

2. Assert a Repeated Start condition on SDA and

SCL.

3. Write to the SSPBUF register initiating

transmission of data/address.

4. Configure the I²C port to receive data.

5. Generate an Acknowledge condition at the end

of a received byte of data.

6. Generate a Stop condition on SDA and SCL.

2

FIGURE 17-18:

MSSP BLOCK DIAGRAM (I C™ MASTER MODE)

Internal

Data Bus

SSPM3:SSPM0

SSPADD<6:0>

Read

Write

SSPBUF

SSPSR

Baud

Rate

Generator

SDA

Shift

Clock

SDA In

MSb

LSb

Start bit, Stop bit,

Acknowledge

Generate

SCL

Start bit Detect

Stop bit Detect

Write Collision Detect

Clock Arbitration

State Counter for

end of XMIT/RCV

SCL In

Bus Collision

Set/Reset, S, P, WCOL (SSPSTAT)

Set SSPIF, BCLIF

Reset ACKSTAT, PEN (SSPCON2)

Preliminary

DS39689E-page 189

PIC18F4321 FAMILY

I²C Master Mode Operation

A typical transmit sequence would go as follows:

17.4.6.1

1. The user generates a Start condition by setting

the Start Enable bit, SEN (SSPCON2<0>).

The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the beginning of the next serial transfer, the I²C bus will

not be released.

2. SSPIF is set. The MSSP module will wait the

required start time before any other operation

takes place.

3. The user loads the SSPBUF with the slave

address to transmit.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the Read/Write (R/W) bit.

In this case, the R/W bit will be logic ‘0’. Serial data is

transmitted 8 bits at a time. After each byte is transmit-

ted, an Acknowledge bit is received. Start and Stop

conditions are output to indicate the beginning and the

end of a serial transfer.

4. Address is shifted out the SDA pin until all 8 bits

are transmitted.

5. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

SSPCON2 register.

6. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

In Master Receive mode, the first byte transmitted

contains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case, the R/W bit will be

logic ‘1’. Thus, the first byte transmitted is a 7-bit slave

address followed by a ‘1’ to indicate the receive bit.

Serial data is received via SDA, while SCL outputs the

serial clock. Serial data is received 8 bits at a time. After

each byte is received, an Acknowledge bit is transmit-

ted. Start and Stop conditions indicate the beginning

and end of transmission.

7. The user loads the SSPBUF with eight bits of

data.

8. Data is shifted out the SDA pin until all 8 bits are

transmitted.

9. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

SSPCON2 register.

10. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

The Baud Rate Generator used for the SPI mode

operation is used to set the SCL clock frequency for

either 100 kHz, 400 kHz or 1 MHz I²C operation. See

Section 17.4.7 “Baud Rate” for more detail.

11. The user generates a Stop condition by setting

the Stop Enable bit, PEN (SSPCON2<2>).

12. Interrupt is generated once the Stop condition is

complete.

DS39689E-page 190

Preliminary

PIC18F4321 FAMILY

Once the given operation is complete (i.e., transmis-

sion of the last data bit is followed by ACK), the internal

clock will automatically stop counting and the SCL pin

will remain in its last state.

17.4.7

BAUD RATE

In I²C Master mode, the Baud Rate Generator (BRG)

reload value is placed in the lower 7 bits of the

SSPADD register (Figure 17-19). When a write occurs

to SSPBUF, the Baud Rate Generator will automatically

begin counting. The BRG counts down to 0 and stops

until another reload has taken place. The BRG count is

decremented twice per instruction cycle (TCY) on the

Q2 and Q4 clocks. In I²C Master mode, the BRG is

reloaded automatically.

Table 17-3 demonstrates clock rates based on

instruction cycles and the BRG value loaded into

SSPADD.

FIGURE 17-19:

BAUD RATE GENERATOR BLOCK DIAGRAM

SSPM3:SSPM0

SSPADD<6:0>

SSPM3:SSPM0

SCL

Reload

Control

Reload

CLKO

BRG Down Counter

FOSC/4

TABLE 17-3: I²C™ CLOCK RATE W/BRG

FSCL

Fosc

FCY

FCY * 2

BRG Value

(2 Rollovers of BRG)

40 MHz

16 MHz

4 MHz

10 MHz

4 MHz

1 MHz

20 MHz

8 MHz

2 MHz

18h

1Fh

63h

09h

0Ch

27h

02h

09h

00h

400 kHz⁽¹⁾

312.5 kHz

100 kHz

400 kHz⁽¹⁾

308 kHz

100 kHz

333 kHz⁽¹⁾

4 MHz

100 kHz

1 MHz⁽¹⁾

4 MHz

Note 1: The I²C™ interface does not conform to the 400 kHz I²C specification (which applies to rates greater than

100 kHz) in all details, but may be used with care where higher rates are required by the application.

Preliminary

DS39689E-page 191

PIC18F4321 FAMILY

SCL pin is sampled high, the Baud Rate Generator is

reloaded with the contents of SSPADD<6:0> and

begins counting. This ensures that the SCL high time

will always be at least one BRG rollover count in the

event that the clock is held low by an external device

(Figure 17-20).

17.4.7.1

Clock Arbitration

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,

deasserts the SCL pin (SCL allowed to float high).

When the SCL pin is allowed to float high, the Baud

Rate Generator (BRG) is suspended from counting

until the SCL pin is actually sampled high. When the

FIGURE 17-20:

BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDA

DX

DX – 1

SCL allowed to transition high

SCL deasserted but slave holds

SCL low (clock arbitration)

SCL

BRG decrements on

Q2 and Q4 cycles

BRG

Value

03h

02h

01h

00h (hold off)

03h

02h

SCL is sampled high, reload takes

place and BRG starts its count

BRG

Reload

DS39689E-page 192

Preliminary

PIC18F4321 FAMILY

17.4.8

I²C MASTER MODE START

CONDITION TIMING

Note:

If at the beginning of the Start condition,

the SDA and SCL pins are already sam-

pled low, or if during the Start condition, the

SCL line is sampled low before the SDA

line is driven low, a bus collision occurs,

the Bus Collision Interrupt Flag, BCLIF, is

set, the Start condition is aborted and the

I²C module is reset into its Idle state.

To initiate a Start condition, the user sets the Start

Enable bit, SEN (SSPCON2<0>). If the SDA and SCL

pins are sampled high, the Baud Rate Generator is

reloaded with the contents of SSPADD<6:0> and starts

its count. If SCL and SDA are both sampled high when

the Baud Rate Generator times out (TBRG), the SDA

pin is driven low. The action of the SDA being driven

low while SCL is high is the Start condition and causes

the S bit (SSPSTAT<3>) to be set. Following this, the

Baud Rate Generator is reloaded with the contents of

SSPADD<6:0> and resumes its count. When the Baud

Rate Generator times out (TBRG), the SEN bit

(SSPCON2<0>) will be automatically cleared by

hardware; the Baud Rate Generator is suspended,

leaving the SDA line held low and the Start condition is

complete.

17.4.8.1

WCOL Status Flag

If the user writes the SSPBUF when a Start sequence

is in progress, the WCOL is set and the contents of the

buffer are unchanged (the write doesn’t occur).

Note:

Because queueing of events is not

allowed, writing to the lower 5 bits of

SSPCON2 is disabled until the Start

condition is complete.

FIGURE 17-21:

FIRST START BIT TIMING

Set S bit (SSPSTAT<3>)

At completion of Start bit,

Write to SEN bit occurs here

SDA = 1,

SCL = 1

hardware clears SEN bit

and sets SSPIF bit

TBRG

Write to SSPBUF occurs here

2nd bit

1st bit

SDA

TBRG

SCL

TBRG

S

Preliminary

DS39689E-page 193

PIC18F4321 FAMILY

17.4.9

I²C MASTER MODE REPEATED

START CONDITION TIMING

Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.

A Repeated Start condition occurs when the RSEN bit

(SSPCON2<1>) is programmed high and the I²C logic

module is in the Idle state. When the RSEN bit is set,

the SCL pin is asserted low. When the SCL pin is

sampled low, the Baud Rate Generator is loaded with

the contents of SSPADD<5:0> and begins counting.

The SDA pin is released (brought high) for one Baud

Rate Generator count (TBRG). When the Baud Rate

Generator times out, if SDA is sampled high, the SCL

pin will be deasserted (brought high). When SCL is

sampled high, the Baud Rate Generator is reloaded

with the contents of SSPADD<6:0> and begins count-

ing. SDA and SCL must be sampled high for one TBRG.

This action is then followed by assertion of the SDA pin

(SDA = 0) for one TBRG while SCL is high. Following

this, the RSEN bit (SSPCON2<1>) will be automatically

cleared and the Baud Rate Generator will not be

reloaded, leaving the SDA pin held low. As soon as a

Start condition is detected on the SDA and SCL pins,

the S bit (SSPSTAT<3>) will be set. The SSPIF bit will

not be set until the Baud Rate Generator has timed out.

2: A bus collision during the Repeated Start

condition occurs if:

• SDA is sampled low when SCL goes

from low-to-high.

• SCL goes low before SDA is

asserted low. This may indicate that

another master is attempting to

transmit a data ‘1’.

Immediately following the SSPIF bit getting set, the user

may write the SSPBUF with the 7-bit address in 7-bit

mode, or the default first address in 10-bit mode. After

the first eight bits are transmitted and an ACK is

received, the user may then transmit an additional eight

bits of address (10-bit mode) or eight bits of data (7-bit

mode).

17.4.9.1

WCOL Status Flag

If the user writes the SSPBUF when a Repeated Start

sequence is in progress, the WCOL is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

Note:

Because queueing of events is not

allowed, writing of the lower 5 bits of

SSPCON2 is disabled until the Repeated

Start condition is complete.

FIGURE 17-22:

REPEAT START CONDITION WAVEFORM

S bit set by hardware

Write to SSPCON2

occurs here.

SDA = 1,

SCL (no change).

SDA = 1,

SCL = 1

At completion of Start bit,

hardware clears RSEN bit

and sets SSPIF

TBRG

1st bit

SDA

RSEN bit set by hardware

on falling edge of ninth clock,

end of Xmit

Write to SSPBUF occurs here

TBRG

SCL

TBRG

Sr = Repeated Start

DS39689E-page 194

Preliminary

PIC18F4321 FAMILY

17.4.10 I²C MASTER MODE TRANSMISSION

17.4.10.3 ACKSTAT Status Flag

Transmission of a data byte, a 7-bit address or the

other half of a 10-bit address is accomplished by simply

writing a value to the SSPBUF register. This action will

set the Buffer Full flag bit, BF and allow the Baud Rate

Generator to begin counting and start the next

transmission. Each bit of address/data will be shifted

out onto the SDA pin after the falling edge of SCL is

asserted (see data hold time specification

parameter 106). SCL is held low for one Baud Rate

Generator rollover count (TBRG). Data should be valid

before SCL is released high (see data setup time

specification parameter 107). When the SCL pin is

released high, it is held that way for TBRG. The data on

the SDA pin must remain stable for that duration and

some hold time after the next falling edge of SCL. After

the eighth bit is shifted out (the falling edge of the eighth

clock), the BF flag is cleared and the master releases

SDA. This allows the slave device being addressed to

respond with an ACK bit during the ninth bit time if an

address match occurred, or if data was received

properly. The status of ACK is written into the ACKDT

bit on the falling edge of the ninth clock. If the master

receives an Acknowledge, the Acknowledge Status bit,

ACKSTAT, is cleared. If not, the bit is set. After the ninth

clock, the SSPIF bit is set and the master clock (Baud

Rate Generator) is suspended until the next data byte

is loaded into the SSPBUF, leaving SCL low and SDA

unchanged (Figure 17-23).

In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is

cleared when the slave has sent an Acknowledge

(ACK = 0) and is set when the slave does not Acknowl-

edge (ACK = 1). A slave sends an Acknowledge when

it has recognized its address (including a general call),

or when the slave has properly received its data.

17.4.11 I²C MASTER MODE RECEPTION

Master mode reception is enabled by programming the

Receive Enable bit, RCEN (SSPCON2<3>).

Note:

The MSSP module must be in an Idle state

before the RCEN bit is set or the RCEN bit

will be disregarded.

The Baud Rate Generator begins counting and on each

rollover, the state of the SCL pin changes (high-to-low/

low-to-high) and data is shifted into the SSPSR. After

the falling edge of the eighth clock, the receive enable

flag is automatically cleared, the contents of the

SSPSR are loaded into the SSPBUF, the BF flag bit is

set, the SSPIF flag bit is set and the Baud Rate Gener-

ator is suspended from counting, holding SCL low. The

MSSP is now in Idle state awaiting the next command.

When the buffer is read by the CPU, the BF flag bit is

automatically cleared. The user can then send an

Acknowledge bit at the end of reception by setting the

Acknowledge Sequence Enable bit, ACKEN

(SSPCON2<4>).

After the write to the SSPBUF, each bit of the address

will be shifted out on the falling edge of SCL until all

seven address bits and the R/W bit are completed. On

the falling edge of the eighth clock, the master will

deassert the SDA pin, allowing the slave to respond

with an Acknowledge. On the falling edge of the ninth

clock, the master will sample the SDA pin to see if the

address was recognized by a slave. The status of the

ACK bit is loaded into the ACKSTAT status bit

(SSPCON2<6>). Following the falling edge of the ninth

clock transmission of the address, the SSPIF is set, the

BF flag is cleared and the Baud Rate Generator is

turned off until another write to the SSPBUF takes

place, holding SCL low and allowing SDA to float.

17.4.11.1 BF Status Flag

In receive operation, the BF bit is set when an address

or data byte is loaded into SSPBUF from SSPSR. It is

cleared when the SSPBUF register is read.

17.4.11.2 SSPOV Status Flag

In receive operation, the SSPOV bit is set when 8 bits

are received into the SSPSR and the BF flag bit is

already set from a previous reception.

17.4.11.3 WCOL Status Flag

If the user writes the SSPBUF when a receive is

already in progress (i.e., SSPSR is still shifting in a data

byte), the WCOL bit is set and the contents of the buffer

are unchanged (the write doesn’t occur).

17.4.10.1 BF Status Flag

In Transmit mode, the BF bit (SSPSTAT<0>) is set

when the CPU writes to SSPBUF and is cleared when

all 8 bits are shifted out.

17.4.10.2 WCOL Status Flag

If the user writes the SSPBUF when a transmit is

already in progress (i.e., SSPSR is still shifting out a

data byte), the WCOL flag is set and the contents of the

buffer are unchanged (the write doesn’t occur) after

2 TCY after the SSPBUF write. If SSPBUF is rewritten

within 2 TCY, the WCOL bit is set and SSPBUF is

updated. This may result in a corrupted transfer. The

user should verify that the WCOL flag is clear after

each write to SSPBUF to ensure the transfer is correct.

Preliminary

DS39689E-page 195

PIC18F4321 FAMILY

2

FIGURE 17-23:

I C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)

DS39689E-page 196

Preliminary

PIC18F4321 FAMILY

2

FIGURE 17-24:

I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

Preliminary

DS39689E-page 197

PIC18F4321 FAMILY

17.4.12 ACKNOWLEDGE SEQUENCE

TIMING

17.4.13 STOP CONDITION TIMING

A Stop bit is asserted on the SDA pin at the end of a

receive/transmit by setting the Stop Sequence Enable

bit, PEN (SSPCON2<2>). At the end of a receive/

transmit, the SCL line is held low after the falling edge

of the ninth clock. When the PEN bit is set, the master

will assert the SDA line low. When the SDA line is

sampled low, the Baud Rate Generator is reloaded and

counts down to 0. When the Baud Rate Generator

times out, the SCL pin will be brought high and one

TBRG (Baud Rate Generator rollover count) later, the

SDA pin will be deasserted. When the SDA pin is

An Acknowledge sequence is enabled by setting the

Acknowledge Sequence Enable bit, ACKEN

(SSPCON2<4>). When this bit is set, the SCL pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDA pin. If the user wishes to gen-

erate an Acknowledge, then the ACKDT bit should be

cleared. If not, the user should set the ACKDT bit before

starting an Acknowledge sequence. The Baud Rate

Generator then counts for one rollover period (TBRG)

and the SCL pin is deasserted (pulled high). When the

SCL pin is sampled high (clock arbitration), the Baud

Rate Generator counts for TBRG. The SCL pin is then

pulled low. Following this, the ACKEN bit is automatically

cleared, the Baud Rate Generator is turned off and the

MSSP module then goes into Idle mode (Figure 17-25).

sampled high while SCL is high, the

(SSPSTAT<4>) is set. A TBRG later, the PEN bit is

cleared and the SSPIF bit is set (Figure 17-26).

P

bit

17.4.13.1 WCOL Status Flag

If the user writes the SSPBUF when a Stop sequence

is in progress, then the WCOL bit is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

17.4.12.1 WCOL Status Flag

If the user writes the SSPBUF when an Acknowledge

sequence is in progress, then WCOL is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

FIGURE 17-25:

ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here,

write to SSPCON2

ACKEN automatically cleared

ACKEN = 1, ACKDT = 0

TBRG

SDA

SCL

D0

ACK

8

9

SSPIF

Cleared in

software

SSPIF set at the end

of Acknowledge sequence

SSPIF set at

the end of receive

Cleared in

software

Note: TBRG = one Baud Rate Generator period.

FIGURE 17-26:

STOP CONDITION RECEIVE OR TRANSMIT MODE

SCL = 1for TBRG, followed by SDA = 1for TBRG

after SDA sampled high. P bit (SSPSTAT<4>) is set.

Write to SSPCON2,

set PEN

PEN bit (SSPCON2<2>) is cleared by

hardware and the SSPIF bit is set

Falling edge of

9th clock

TBRG

SCL

ACK

SDA

P

TBRG

SCL brought high after TBRG

SDA asserted low before rising edge of clock

to setup Stop condition

Note: TBRG = one Baud Rate Generator period.

DS39689E-page 198

Preliminary

PIC18F4321 FAMILY

17.4.14 SLEEP OPERATION

17.4.17 MULTI -MASTER COMMUNICATION,

BUS COLLISION AND BUS

While in Sleep mode, the I²C module can receive

addresses or data and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if the MSSP interrupt is enabled).

ARBITRATION

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDA pin, arbitration takes place when the master

outputs a ‘1’ on SDA, by letting SDA float high and

another master asserts a ‘0’. When the SCL pin floats

high, data should be stable. If the expected data on

SDA is a ‘1’ and the data sampled on the SDA pin = 0,

then a bus collision has taken place. The master will set

the Bus Collision Interrupt Flag, BCLIF and reset the

I²C port to its Idle state (Figure 17-27).

17.4.15 EFFECTS OF A RESET

A Reset disables the MSSP module and terminates the

current transfer.

17.4.16 MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the

MSSP module is disabled. Control of the I²C bus may

be taken when the P bit (SSPSTAT<4>) is set, or the

bus is Idle, with both the S and P bits clear. When the

bus is busy, enabling the MSSP interrupt will generate

the interrupt when the Stop condition occurs.

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDA and SCL lines are deasserted and the

SSPBUF can be written to. When the user services the

bus collision Interrupt Service Routine and if the I²C

bus is free, the user can resume communication by

asserting a Start condition.

In multi-master operation, the SDA line must be

monitored for arbitration to see if the signal level is the

expected output level. This check is performed in

hardware with the result placed in the BCLIF bit.

If a Start, Repeated Start, Stop or Acknowledge

condition was in progress when the bus collision

occurred, the condition is aborted, the SDA and SCL

lines are deasserted and the respective control bits in

the SSPCON2 register are cleared. When the user ser-

vices the bus collision Interrupt Service Routine and if

the I²C bus is free, the user can resume communication

by asserting a Start condition.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

• A Start Condition

The master will continue to monitor the SDA and SCL

pins. If a Stop condition occurs, the SSPIF bit will be set.

• A Repeated Start Condition

• An Acknowledge Condition

A write to the SSPBUF will start the transmission of

data at the first data bit, regardless of where the

transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detection of Start and Stop conditions allows the

determination of when the bus is free. Control of the I²C

bus can be taken when the P bit is set in the SSPSTAT

register, or the bus is Idle and the S and P bits are

cleared.

FIGURE 17-27:

BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Sample SDA. While SCL is high,

data doesn’t match what is driven

by the master.

Data changes

while SCL = 0

SDA line pulled low

by another source

Bus collision has occurred.

SDA released

by master

SDA

SCL

Set bus collision

interrupt (BCLIF)

BCLIF

Preliminary

DS39689E-page 199

PIC18F4321 FAMILY

If the SDA pin is sampled low during this count, the

BRG is reset and the SDA line is asserted early

(Figure 17-30). If, however, a ‘1’ is sampled on the SDA

pin, the SDA pin is asserted low at the end of the BRG

count. The Baud Rate Generator is then reloaded and

counts down to 0; if the SCL pin is sampled as ‘0’

during this time, a bus collision does not occur. At the

end of the BRG count, the SCL pin is asserted low.

17.4.17.1 Bus Collision During a

Start Condition

During a Start condition, a bus collision occurs if:

a) SDA or SCL are sampled low at the beginning of

the Start condition (Figure 17-28).

b) SCL is sampled low before SDA is asserted low

(Figure 17-29).

During a Start condition, both the SDA and the SCL

pins are monitored.

Note:

The reason that bus collision is not a factor

during a Start condition is that no two bus

masters can assert a Start condition at the

exact same time. Therefore, one master

will always assert SDA before the other.

This condition does not cause a bus

collision because the two masters must be

allowed to arbitrate the first address

following the Start condition. If the address

is the same, arbitration must be allowed to

continue into the data portion, Repeated

Start or Stop conditions.

If the SDA pin is already low, or the SCL pin is already

low, then all of the following occur:

• the Start condition is aborted,

• the BCLIF flag is set and

•

the MSSP module is reset to its Idle state

(Figure 17-28).

The Start condition begins with the SDA and SCL pins

deasserted. When the SDA pin is sampled high, the

Baud Rate Generator is loaded from SSPADD<6:0>

and counts down to 0. If the SCL pin is sampled low

while SDA is high, a bus collision occurs because it is

assumed that another master is attempting to drive a

data ‘1’ during the Start condition.

FIGURE 17-28:

BUS COLLISION DURING START CONDITION (SDA ONLY)

SDA goes low before the SEN bit is set.

Set BCLIF,

S bit and SSPIF set because

SDA = 0, SCL = 1.

SDA

SCL

SEN

Set SEN, enable Start

condition if SDA = 1, SCL = 1

SEN cleared automatically because of bus collision.

MSSP module reset into Idle state.

SDA sampled low before

Start condition. Set BCLIF.

S bit and SSPIF set because

SDA = 0, SCL = 1.

BCLIF

SSPIF and BCLIF are

cleared in software

S

SSPIF

SSPIF and BCLIF are

cleared in software

DS39689E-page 200

Preliminary

PIC18F4321 FAMILY

FIGURE 17-29:

BUS COLLISION DURING START CONDITION (SCL = 0)

SDA = 0, SCL = 1

TBRG

SDA

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

SCL

SEN

SCL = 0before SDA = 0,

bus collision occurs. Set BCLIF.

SCL = 0before BRG time-out,

bus collision occurs. Set BCLIF.

BCLIF

Interrupt cleared

in software

S

‘0’

SSPIF

FIGURE 17-30:

BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDA = 0, SCL = 1

Set S

Set SSPIF

Less than TBRG

TBRG

SDA pulled low by other master.

Reset BRG and assert SDA.

SDA

SCL

S

SCL pulled low after BRG

time-out

SEN

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

BCLIF

‘0’

S

SSPIF

Interrupts cleared

in software

SDA = 0, SCL = 1,

set SSPIF

Preliminary

DS39689E-page 201

PIC18F4321 FAMILY

If SDA is low, a bus collision has occurred (i.e., another

master is attempting to transmit a data ‘0’, Figure 17-31).

If SDA is sampled high, the BRG is reloaded and begins

counting. If SDA goes from high-to-low before the BRG

times out, no bus collision occurs because no two

masters can assert SDA at exactly the same time.

17.4.17.2 Bus Collision During a Repeated

Start Condition

During a Repeated Start condition, a bus collision

occurs if:

a) A low level is sampled on SDA when SCL goes

from low level to high level.

If SCL goes from high-to-low before the BRG times out

and SDA has not already been asserted, a bus collision

occurs. In this case, another master is attempting to

transmit a data ‘1’ during the Repeated Start condition,

see Figure 17-32.

b) SCL goes low before SDA is asserted low,

indicating that another master is attempting to

transmit a data ‘1’.

When the user deasserts SDA and the pin is allowed to

float high, the BRG is loaded with SSPADD<6:0> and

counts down to 0. The SCL pin is then deasserted and

when sampled high, the SDA pin is sampled.

If, at the end of the BRG time-out, both SCL and SDA

are still high, the SDA pin is driven low and the BRG is

reloaded and begins counting. At the end of the count,

regardless of the status of the SCL pin, the SCL pin is

driven low and the Repeated Start condition is

complete.

FIGURE 17-31:

BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

SDA

SCL

Sample SDA when SCL goes high.

If SDA = 0, set BCLIF and release SDA and SCL.

RSEN

BCLIF

Cleared in software

‘0’

S

‘0’

SSPIF

FIGURE 17-32:

BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

TBRG

SDA

SCL

SCL goes low before SDA,

BCLIF

RSEN

set BCLIF. Release SDA and SCL.

Interrupt cleared

in software

‘0’

S

SSPIF

DS39689E-page 202

Preliminary

PIC18F4321 FAMILY

The Stop condition begins with SDA asserted low.

When SDA is sampled low, the SCL pin is allowed to

float. When the pin is sampled high (clock arbitration),

the Baud Rate Generator is loaded with SSPADD<6:0>

and counts down to 0. After the BRG times out, SDA is

sampled. If SDA is sampled low, a bus collision has

occurred. This is due to another master attempting to

drive a data ‘0’ (Figure 17-33). If the SCL pin is

sampled low before SDA is allowed to float high, a bus

collision occurs. This is another case of another master

attempting to drive a data ‘0’ (Figure 17-34).

17.4.17.3 Bus Collision During a Stop

Condition

Bus collision occurs during a Stop condition if:

a) After the SDA pin has been deasserted and

allowed to float high, SDA is sampled low after

the BRG has timed out.

b) After the SCL pin is deasserted, SCL is sampled

low before SDA goes high.

FIGURE 17-33:

BUS COLLISION DURING A STOP CONDITION (CASE 1)

SDA sampled

low after TBRG,

set BCLIF

TBRG

SDA

SDA asserted low

SCL

PEN

BCLIF

P

‘0’

SSPIF

FIGURE 17-34:

BUS COLLISION DURING A STOP CONDITION (CASE 2)

TBRG

SDA

SCL goes low before SDA goes high,

set BCLIF

Assert SDA

SCL

PEN

BCLIF

P

‘0’

SSPIF

Preliminary

DS39689E-page 203

PIC18F4321 FAMILY

TABLE 17-4: REGISTERS ASSOCIATED WITH I²C™ OPERATION

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE

SSPIF

SSPIE

SSPIP

BCLIF

BCLIE

BCLIP

TRISC3

TRISD3

TMR0IF

CCP1IF

CCP1IE

CCP1IP

HLVDIF

HLVDIE

HLVDIP

TRISC2

TRISD2

INT0IF

RBIF

49

52

50

PSPIF

PSPIE

ADIF

ADIE

RCIF

RCIE

RCIP

—

TMR2IF

TMR1IF

PIE1

TXIE

TMR2IE TMR1IE

TMR2IP TMR1IP

IPR1

PSPIP

ADIP

TXIP

PIR2

OSCFIF

OSCFIE

OSCFIP

TRISC7

TRISD7

CMIF

EEIF

TMR3IF

TMR3IE

TMR3IP

TRISC1

TRISD1

CCP2IF

CCP2IE

CCP2IP

TRISC0

TRISD0

PIE2

CMIE

—

EEIE

IPR2

CMIP

—

EEIP

TRISC

TRISD

SSPBUF

SSPADD

TMR2

TRISC6

TRISD6

TRISC5

TRISD5

TRISC4

TRISD4

MSSP Receive Buffer/Transmit Register

ADD7

ADD6

ADD5

ADD4

ADD3

ADD2

ADD1

ADD0

Timer2 Register

PR2

Timer2 Period Register

SSPCON1

SSPCON2

WCOL

GCEN

SSPOV

SSPEN

CKP

SSPM3

RCEN/

SSPM2

PEN/

SSPM1

RSEN/

SSPM0

SEN

ACKSTAT ACKDT/ ACKEN/

ADMSK5 ADMSK5 ADMSK5 ADMSK5 ADMSK5

SSPSTAT

SMP

CKE

D/A R/W UA

P

S

BF

50

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I²C mode.

DS39689E-page 204

Preliminary

PIC18F4321 FAMILY

The pins of the Enhanced USART are multiplexed

with PORTC. In order to configure RC6/TX/CK and

RC7/RX/DT as an EUSART:

18.0 ENHANCED UNIVERSAL

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (EUSART)

• bit SPEN (RCSTA<7>) must be set (= 1)

• bit TRISC<7> must be set (= 1)

• bit TRISC<6> must be set (= 1)

The Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) module is one of the

two serial I/O modules. (Generically, the USART is also

known as a Serial Communications Interface or SCI.)

The EUSART can be configured as a full-duplex

asynchronous system that can communicate with

peripheral devices, such as CRT terminals and

personal computers. It can also be configured as a half-

duplex synchronous system that can communicate

with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs, etc.

Note:

The EUSART control will automatically

reconfigure the pin from input to output as

needed.

The operation of the Enhanced USART module is

controlled through three registers:

• Transmit Status and Control (TXSTA)

• Receive Status and Control (RCSTA)

• Baud Rate Control (BAUDCON)

These are detailed on the following pages in

Register 18-1, Register 18-2 and Register 18-3,

respectively.

The Enhanced USART module implements additional

features, including automatic baud rate detection and

calibration, automatic wake-up on Sync Break recep-

tion and 12-bit Break character transmit. These make it

ideally suited for use in Local Interconnect Network bus

(LIN bus) systems.

The EUSART can be configured in the following

modes:

• Asynchronous (full duplex) with:

- Auto-wake-up on Break signal

- Auto-baud calibration

- 12-bit Break character transmission

• Synchronous – Master (half duplex) with

selectable clock polarity

• Synchronous – Slave (half duplex) with selectable

clock polarity

Preliminary

DS39689E-page 205

PIC18F4321 FAMILY

REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-0

CSRC

R/W-0

TX9

R/W-0

TXEN

R/W-0

SYNC

R/W-0

BRGH

R-1

R/W-0

TX9D

SENDB

TRMT

bit 7

bit 0

bit 7

CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care.

Synchronous mode:

1= Master mode (clock generated internally from BRG)

0= Slave mode (clock from external source)

bit 6

bit 5

TX9: 9-bit Transmit Enable bit

1= Selects 9-bit transmission

0= Selects 8-bit transmission

TXEN: Transmit Enable bit

1= Transmit enabled

0= Transmit disabled

Note:

SREN/CREN overrides TXEN in Sync mode.

bit 4

bit 3

SYNC: EUSART Mode Select bit

1= Synchronous mode

0= Asynchronous mode

SENDB: Send Break Character bit

Asynchronous mode:

1= Send Sync Break on next transmission (cleared by hardware upon completion)

0= Sync Break transmission completed

Synchronous mode:

Don’t care.

bit 2

BRGH: High Baud Rate Select bit

Asynchronous mode:

1= High speed

0= Low speed

Synchronous mode:

Unused in this mode.

bit 1

bit 0

TRMT: Transmit Shift Register Status bit

1= TSR empty

0= TSR full

TX9D: 9th bit of Transmit Data

Can be address/data bit or a parity bit.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39689E-page 206

Preliminary

PIC18F4321 FAMILY

REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER

R/W-0

SPEN

R/W-0

RX9

R/W-0

SREN

R/W-0

CREN

R/W-0

R-0

R-x

ADDEN

FERR

OERR

RX9D

bit 7

bit 0

bit 7

bit 6

bit 5

SPEN: Serial Port Enable bit

1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

0= Serial port disabled (held in Reset)

RX9: 9-bit Receive Enable bit

1= Selects 9-bit reception

0= Selects 8-bit reception

SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care.

Synchronous mode – Master:

1= Enables single receive

0= Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave:

Don’t care.

bit 4

CREN: Continuous Receive Enable bit

Asynchronous mode:

1= Enables receiver

0= Disables receiver

Synchronous mode:

1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0= Disables continuous receive

bit 3

ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1= Enables address detection, enables interrupt and loads the receive buffer when RSR<8>

is set

0= Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 9-bit (RX9 = 0):

Don’t care.

bit 2

bit 1

bit 0

FERR: Framing Error bit

1= Framing error (can be updated by reading RCREG register and receiving next valid byte)

0= No framing error

OERR: Overrun Error bit

1= Overrun error (can be cleared by clearing bit CREN)

0= No overrun error

RX9D: 9th bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39689E-page 207

PIC18F4321 FAMILY

REGISTER 18-3: BAUDCON: BAUD RATE CONTROL REGISTER

R/W-0

ABDOVF

bit 7

R-1

R/W-0

U-0

—

R/W-0

WUE

R/W-0

RCIDL

RXDTP

TXCKP

BRG16

ABDEN

bit 0

bit 7

ABDOVF: Auto-Baud Acquisition Rollover Status bit

1= A BRG rollover has occurred during Auto-Baud Rate Detect mode

(must be cleared in software)

0= No BRG rollover has occurred

bit 6

bit 5

RCIDL: Receive Operation Idle Status bit

1= Receive operation is Idle

0= Receive operation is active

RXDTP: Received Data Polarity Select bit

Asynchronous mode:

1= RX data is inverted

0= RX data received is not inverted

Synchronous modes:

1= CK clocks are inverted

0= CK clocks are not inverted

bit 4

TXCKP: Clock and Data Polarity Select bit

Asynchronous mode:

1= TX data is inverted

0= TX data is not inverted

Synchronous modes:

1= CK clocks are inverted

0= CK clocks are not inverted

bit 3

BRG16: 16-bit Baud Rate Register Enable bit

1= 16-bit Baud Rate Generator – SPBRGH and SPBRG

0= 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored

bit 2

bit 1

Unimplemented: Read as ‘0’

WUE: Wake-up Enable bit

Asynchronous mode:

1= EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit

cleared in hardware on following rising edge

0= RX pin not monitored or rising edge detected

Synchronous mode:

Unused in this mode.

bit 0

ABDEN: Auto-Baud Detect Enable bit

Asynchronous mode:

1= Enable baud rate measurement on the next character. Requires reception of a Sync field

(55h); cleared in hardware upon completion

0= Baud rate measurement disabled or completed

Synchronous mode:

Unused in this mode.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39689E-page 208

Preliminary

PIC18F4321 FAMILY

to use the high baud rate (BRGH = 1) or the 16-bit BRG

to reduce the baud rate error, or achieve a slow baud

rate for a fast oscillator frequency.

18.1 Baud Rate Generator (BRG)

The BRG is a dedicated 8-bit or 16-bit generator that

supports both the Asynchronous and Synchronous

modes of the EUSART. By default, the BRG operates

in 8-bit mode; setting the BRG16 bit (BAUDCON<3>)

selects 16-bit mode.

Writing a new value to the SPBRGH:SPBRG registers

causes the BRG timer to be reset (or cleared). This

ensures the BRG does not wait for a timer overflow

before outputting the new baud rate.

The SPBRGH:SPBRG register pair controls the period

of a free running timer. In Asynchronous mode, bits

BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also

control the baud rate. In Synchronous mode, BRGH is

ignored. Table 18-1 shows the formula for computation

of the baud rate for different EUSART modes which

only apply in Master mode (internally generated clock).

18.1.1

OPERATION IN POWER-MANAGED

MODES

The device clock is used to generate the desired baud

rate. When one of the power-managed modes is

entered, the new clock source may be operating at a

different frequency. This may require an adjustment to

the value in the SPBRG register pair.

Given the desired baud rate and FOSC, the nearest

integer value for the SPBRGH:SPBRG registers can be

calculated using the formulas in Table 18-1. From this,

the error in baud rate can be determined. An example

calculation is shown in Example 18-1. Typical baud

rates and error values for the various Asynchronous

modes are shown in Table 18-2. It may be advantageous

18.1.2

SAMPLING

The data on the RX pin is sampled three times by a

majority detect circuit to determine if a high or a low

level is present at the RX pin.

TABLE 18-1: BAUD RATE FORMULAS

Configuration Bits

BRG/EUSART Mode

Baud Rate Formula

SYNC

BRG16

BRGH

0

1

0

1

0

1

0

1

0

1

x

8-bit/Asynchronous

16-bit/Asynchronous

8-bit/Synchronous

16-bit/Synchronous

FOSC/[64 (n + 1)]

FOSC/[16 (n + 1)]

FOSC/[4 (n + 1)]

Legend: x= Don’t care, n = value of SPBRGH:SPBRG register pair

Preliminary

DS39689E-page 209

PIC18F4321 FAMILY

EXAMPLE 18-1:

CALCULATING BAUD RATE ERROR

For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:

Desired Baud Rate

= FOSC/(64 ([SPBRGH:SPBRG] + 1))

Solving for SPBRGH:SPBRG:

X

=

((FOSC/Desired Baud Rate)/64) – 1

((16000000/9600)/64) – 1

[25.042] = 25

16000000/(64 (25 + 1))

9615

Calculated Baud Rate

Error

(Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate

(9615 – 9600)/9600 = 0.16%

TABLE 18-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Reset Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TXSTA

RCSTA

CSRC

SPEN

TX9

RX9

TXEN

SREN

SYNC

CREN

TXCKP

SENDB

ADDEN

BRG16

BRGH

FERR

—

TRMT

OERR

WUE

TX9D

RX9D

51

BAUDCON ABDOVF RCIDL

RXDTP

ABDEN

SPBRGH EUSART Baud Rate Generator Register High Byte

SPBRG EUSART Baud Rate Generator Register Low Byte

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.

DS39689E-page 210

Preliminary

PIC18F4321 FAMILY

TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0

BAUD

RATE

(K)

FOSC = 40.000 MHz

FOSC = 20.000 MHz FOSC = 10.000 MHz

FOSC = 8.000 MHz

Actual

Rate

(K)

SPBRG Actual

value

SPBRG Actual

value

(decimal)

SPBRG

value

(decimal)

%

Error

%

Error

%

Error

Rate

(K)

value

Rate

(K)

Rate

(K)

Error

(decimal)

0.3

1.2

—

255

129

31

15

4

—

129

64

15

7

—

1.201

2.403

9.615

—

-0.16

—

103

51

12

—

1.221

1.73

0.16

1.73

8.51

-9.58

1.202

2.404

9.766

19.531

52.083

78.125

0.16

1.73

-9.58

-32.18

2.4

2.441

9.615

19.531

56.818

125.000

1.73

0.16

1.73

-1.36

8.51

255

64

31

10

4

2.404

9.6

9.766

19.2

57.6

115.2

19.531

62.500

104.167

2

—

2

1

—

SYNC = 0, BRGH = 0, BRG16 = 0

BAUD

RATE

(K)

FOSC = 4.000 MHz

FOSC = 2.000 MHz

FOSC = 1.000 MHz

Actual

Rate

(K)

SPBRG Actual

value

SPBRG Actual

value

(decimal)

SPBRG

value

(decimal)

%

Error

%

Error

Rate

(K)

Rate

(K)

Error

(decimal)

0.3

1.2

0.300

1.202

0.16

207

51

25

6

0.300

1.201

2.403

—

-0.16

—

103

25

12

—

0.300

1.201

—

-0.16

—

51

12

—

2.4

2.404

0.16

9.6

8.929

-6.99

8.51

—

19.2

57.6

115.2

20.833

62.500

2

—

8.51

0

—

-45.75

0

—

SYNC = 0, BRGH = 1, BRG16 = 0

BAUD

RATE

(K)

FOSC = 40.000 MHz

FOSC = 20.000 MHz

FOSC = 10.000 MHz

FOSC = 8.000 MHz

Actual

Rate

(K)

SPBRG Actual

value

(decimal)

SPBRG Actual

value

(decimal)

SPBRG Actual

value

(decimal)

SPBRG

value

%

Error

%

Error

%

Error

%

Error

Rate

(K)

Rate

(K)

Rate

(K)

(decimal)

0.3

1.2

—

2.4

—

2.441

9.615

19.531

56.818

125.000

1.73

0.16

1.73

-1.36

8.51

255

64

31

10

4

2.403

9.615

19.230

55.555

—

-0.16

3.55

—

207

51

25

8

9.6

9.766

19.231

58.140

113.636

1.73

0.16

0.94

-1.36

255

129

42

9.615

19.231

56.818

113.636

0.16

-1.36

129

64

21

10

19.2

57.6

115.2

21

—

SYNC = 0, BRGH = 1, BRG16 = 0

BAUD

RATE

(K)

FOSC = 4.000 MHz

FOSC = 2.000 MHz

FOSC = 1.000 MHz

Actual

Rate

(K)

SPBRG Actual

value

SPBRG Actual

value

(decimal)

SPBRG

value

(decimal)

%

Error

%

Error

Rate

(K)

Rate

(K)

Error

(decimal)

0.3

1.2

—

207

103

25

12

3

—

1.201

2.403

9.615

—

-0.16

—

103

51

12

—

0.300

1.201

2.403

—

-0.16

—

207

51

25

—

1.202

0.16

8.51

2.4

2.404

9.6

9.615

19.2

57.6

115.2

19.231

62.500

125.000

—

1

—

Preliminary

DS39689E-page 211

PIC18F4321 FAMILY

TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

SYNC = 0, BRGH = 0, BRG16 = 1

BAUD

RATE

(K)

FOSC = 40.000 MHz

FOSC = 20.000 MHz

FOSC = 10.000 MHz

FOSC = 8.000 MHz

Actual

Rate

(K)

SPBRG Actual

value

SPBRG Actual

value

(decimal)

SPBRG Actual

value

(decimal)

SPBRG

value

(decimal)

%

Error

%

Error

%

Error

Rate

(K)

Rate

(K)

Rate

(K)

Error

(decimal)

0.3

1.2

0.300

1.200

0.00

0.02

0.06

0.16

0.94

-1.36

8332

2082

1040

259

129

42

0.300

1.200

0.02

-0.03

0.16

4165

1041

520

129

64

0.300

1.200

0.02

-0.03

0.16

1.73

-1.36

8.51

2082

520

259

64

0.300

1.201

2.403

9.615

19.230

55.555

—

-0.04

-0.16

3.55

—

1665

415

207

51

2.4

2.402

2.399

2.404

9.6

9.615

19.2

57.6

115.2

19.231

58.140

113.636

19.231

56.818

113.636

0.16

19.531

56.818

125.000

31

25

-1.36

21

10

8

21

10

4

—

SYNC = 0, BRGH = 0, BRG16 = 1

BAUD

RATE

(K)

FOSC = 4.000 MHz

FOSC = 2.000 MHz

FOSC = 1.000 MHz

Actual

Rate

(K)

SPBRG Actual

value

SPBRG Actual

value

(decimal)

SPBRG

value

(decimal)

%

Error

%

Error

Rate

(K)

Rate

(K)

Error

(decimal)

0.3

1.2

0.300

1.202

0.04

0.16

8.51

832

207

103

25

12

3

0.300

1.201

2.403

9.615

—

-0.16

—

415

103

51

12

—

0.300

1.201

2.403

—

-0.16

—

207

51

25

—

2.4

2.404

9.6

9.615

19.2

57.6

115.2

19.231

62.500

125.000

—

1

—

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 20.000 MHz FOSC = 10.000 MHz

BAUD

RATE

(K)

FOSC = 40.000 MHz

FOSC = 8.000 MHz

Actual

Rate

(K)

SPBRG Actual

value

SPBRG

value

(decimal)

%

Error

%

Error

value

(decimal)

Rate

(K)

value

Rate

(K)

Rate

(K)

Error

(decimal)

0.3

1.2

0.300

1.200

0.00

0.02

0.06

-0.03

0.35

-0.22

33332

8332

4165

1040

520

0.300

1.200

0.00

0.02

-0.03

0.16

-0.22

0.94

16665

4165

2082

520

259

86

0.300

1.200

0.00

0.02

0.06

0.16

0.94

-1.36

8332

2082

1040

259

129

42

0.300

1.200

-0.01

-0.04

-0.16

0.79

6665

1665

832

207

103

34

2.4

2.400

2.402

2.400

9.6

9.606

9.596

9.615

19.2

57.6

115.2

19.193

57.803

114.943

19.231

57.471

116.279

19.231

58.140

113.636

19.230

57.142

117.647

172

86

42

21

-2.12

16

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

BAUD

RATE

(K)

Actual

Rate

(K)

SPBRG Actual

SPBRG

value

(decimal)

%

Error

%

Error

%

Error

value

Rate

(K)

value

Rate

(K)

(decimal)

0.3

1.2

0.300

1.200

0.01

0.04

0.16

2.12

-3.55

3332

832

415

103

51

0.300

1.201

2.403

9.615

19.230

55.555

—

-0.04

-0.16

3.55

—

1665

415

207

51

0.300

1.201

2.403

9.615

19.230

—

-0.04

-0.16

—

832

207

103

25

2.4

2.404

9.6

9.615

19.2

57.6

115.2

19.231

58.824

111.111

25

12

16

8

—

8

—

DS39689E-page 212

Preliminary

PIC18F4321 FAMILY

18.1.3

AUTO-BAUD RATE DETECT

Note 1: If the WUE bit is set with the ABDEN bit,

Auto-Baud Rate Detection will occur on

the byte following the Break character.

The Enhanced USART module supports the automatic

detection and calibration of baud rate. This feature is

active only in Asynchronous mode and while the WUE

bit is clear.

2: It is up to the user to determine that the

incoming character baud rate is within the

range of the selected BRG clock source.

Some combinations of oscillator frequency

and EUSART baud rates are not possible

due to bit error rates. Overall system

timing and communication baud rates

must be taken into consideration when

using the Auto-Baud Rate Detection

feature.

The automatic baud rate measurement sequence

(Figure 18-1) begins whenever a Start bit is received

and the ABDEN bit is set. The calculation is

self-averaging.

In the Auto-Baud Rate Detect (ABD) mode, the clock to

the BRG is reversed. Rather than the BRG clocking the

incoming RX signal, the RX signal is timing the BRG. In

ABD mode, the internal Baud Rate Generator is used

as a counter to time the bit period of the incoming serial

byte stream.

TABLE 18-4: BRG COUNTER

CLOCK RATES

Once the ABDEN bit is set, the state machine will clear

the BRG and look for a Start bit. The Auto-Baud Rate

Detect must receive a byte with the value 55h (ASCII

“U”, which is also the LIN bus Sync character) in order to

calculate the proper bit rate. The measurement is taken

over both a low and a high bit time in order to minimize

any effects caused by asymmetry of the incoming signal.

After a Start bit, the SPBRG begins counting up, using

the preselected clock source on the first rising edge of

RX. After eight bits on the RX pin, or the fifth rising edge,

an accumulated value totalling the proper BRG period is

left in the SPBRGH:SPBRG register pair. Once the 5th

edge is seen (this should correspond to the Stop bit), the

ABDEN bit is automatically cleared.

BRG16 BRGH

BRG Counter Clock

0

1

0

1

0

1

FOSC/512

FOSC/128

FOSC/32

Note: During the ABD sequence, SPBRG and

SPBRGH are both used as a 16-bit counter,

independent of BRG16 setting.

18.1.3.1

ABD and EUSART Transmission

Since the BRG clock is reversed during ABD acquisi-

tion, the EUSART transmitter cannot be used during

ABD. This means that whenever the ABDEN bit is set,

TXREG cannot be written to. Users should also ensure

that ABDEN does not become set during a transmit

sequence. Failing to do this may result in unpredictable

EUSART operation.

If a rollover of the BRG occurs (an overflow from FFFFh

to 0000h), the event is trapped by the ABDOVF status

bit (BAUDCON<7>). It is set in hardware by BRG

rollovers and can be set or cleared by the user in

software. ABD mode remains active after rollover

events and the ABDEN bit remains set (Figure 18-2).

While calibrating the baud rate period, the BRG

registers are clocked at 1/8th the preconfigured clock

rate. Note that the BRG clock will be configured by the

BRG16 and BRGH bits. Independent of the BRG16 bit

setting, both the SPBRG and SPBRGH will be used as

a 16-bit counter. This allows the user to verify that no

carry occurred for 8-bit modes by checking for 00h in

the SPBRGH register. Refer to Table 18-4 for counter

clock rates to the BRG.

While the ABD sequence takes place, the EUSART

state machine is held in Idle. The RCIF interrupt is set

once the fifth rising edge on RX is detected. The value

in the RCREG needs to be read to clear the RCIF

interrupt. ThecontentsofRCREG shouldbediscarded.

Preliminary

DS39689E-page 213

PIC18F4321 FAMILY

FIGURE 18-1:

AUTOMATIC BAUD RATE CALCULATION

BRG Value

RX pin

XXXXh

0000h

001Ch

Edge #5

Stop Bit

Edge #2

Bit 3

Edge #3

Bit 5

Edge #4

Bit 7

Bit 6

Edge #1

Bit 1

Start

Bit 0

Bit 2

Bit 4

BRG Clock

Auto-Cleared

Set by User

ABDEN bit

RCIF bit

(Interrupt)

Read

RCREG

XXXXh

1Ch

00h

SPBRG

SPBRGH

Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.

FIGURE 18-2:

BRG OVERFLOW SEQUENCE

BRG Clock

ABDEN bit

RX pin

Start

Bit 0

ABDOVF bit

BRG Value

FFFFh

XXXXh

0000h

DS39689E-page 214

Preliminary

PIC18F4321 FAMILY

Once the TXREG register transfers the data to the TSR

register (occurs in one TCY), the TXREG register is empty

and the TXIF flag bit (PIR1<4>) is set. This interrupt can

be enabled or disabled by setting or clearing the interrupt

enable bit, TXIE (PIE1<4>). TXIF will be set regardless of

the state of TXIE; it cannot be cleared in software. TXIF

is also not cleared immediately upon loading TXREG, but

becomes valid in the second instruction cycle following

the load instruction. Polling TXIF immediately following a

load of TXREG will return invalid results.

18.2 EUSART Asynchronous Mode

The Asynchronous mode of operation is selected by

clearing the SYNC bit (TXSTA<4>). In this mode, the

EUSART uses standard Non-Return-to-Zero (NRZ)

format (one Start bit, eight or nine data bits and one

Stop bit). The most common data format is 8 bits. An

on-chip dedicated 8-bit/16-bit Baud Rate Generator

can be used to derive standard baud rate frequencies

from the oscillator.

The EUSART transmits and receives the LSb first. The

EUSART’s transmitter and receiver are functionally

independent but use the same data format and baud

rate. The Baud Rate Generator produces a clock, either

x16 or x64 of the bit shift rate depending on the BRGH

and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity

is not supported by the hardware but can be

implemented in software and stored as the 9th data bit.

While TXIF indicates the status of the TXREG register,

another bit, TRMT (TXSTA<1>), shows the status of

the TSR register. TRMT is a read-only bit which is set

when the TSR register is empty. No interrupt logic is

tied to this bit so the user has to poll this bit in order to

determine if the TSR register is empty.

The TXCKP bit (BAUDCON<4>) allows the TX signal to

be inverted (polarity reversed). Devices that buffer sig-

nals from TTL to RS-232 levels also invert the signal

(when TTL = 1, RS-232 = negative). Inverting the polar-

ity of the TX pin data by setting the TXCKP bit allows for

use of circuits that provide buffering without inverting the

signal.

The

TXCKP

(BAUDCON<4>)

and

RXDTP

(BAUDCON<5>) bits allow the TX and RX signals to be

inverted (polarity reversed). Devices that buffer signals

between TTL and RS-232 levels also invert the signal.

Setting the TXCKP and RXDTP bits allows for the use of

circuits that provide buffering without inverting the signal.

Note 1: The TSR register is not mapped in data

When operating in Asynchronous mode, the EUSART

module consists of the following important elements:

memory so it is not available to the user.

2: Flag bit TXIF is set when enable bit TXEN

• Baud Rate Generator

is set.

• Sampling Circuit

• Asynchronous Transmitter

• Asynchronous Receiver

• Auto-Wake-up on Break signal

• 12-bit Break Character Transmit

• Auto-Baud Rate Detection

• Pin State Polarity

To set up an Asynchronous Transmission:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate.

2. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

3. If the signal from the TX pin is to be inverted, set

the TXCKP bit.

18.2.1

EUSART ASYNCHRONOUS

TRANSMITTER

4. If interrupts are desired, set enable bit TXIE.

The EUSART transmitter block diagram is shown in

Figure 18-3. The heart of the transmitter is the Transmit

(Serial) Shift Register (TSR). The Shift register obtains

its data from the Read/Write Transmit Buffer register,

TXREG. The TXREG register is loaded with data in

software. The TSR register is not loaded until the Stop

bit has been transmitted from the previous load. As

soon as the Stop bit is transmitted, the TSR is loaded

with new data from the TXREG register (if available).

5. If 9-bit transmission is desired, set transmit bit

TX9. Can be used as address/data bit.

6. Enable the transmission by setting bit TXEN

which will also set bit TXIF.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

8. Load data to the TXREG register (starts

transmission).

9. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

Preliminary

DS39689E-page 215

PIC18F4321 FAMILY

FIGURE 18-3:

EUSART TRANSMIT BLOCK DIAGRAM

Data Bus

TXREG Register

TXIF

TXCKP

TXIE

8

MSb

(8)

LSb

0

Pin Buffer

and Control

•

TSR Register

TX pin

Interrupt

Baud Rate CLK

SPBRG

TXEN

TRMT

SPEN

BRG16

SPBRGH

TX9

Baud Rate Generator

TX9D

FIGURE 18-4:

ASYNCHRONOUS TRANSMISSION, TXCKP = 0 (TX NOT INVERTED)

Write to TXREG

Word 1

BRG Output

(Shift Clock)

TX (pin)

Start bit

bit 0

bit 1

Word 1

bit 7/8

Stop bit

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

1 TCY

Word 1

Transmit Shift Reg

TRMT bit

(Transmit Shift

Reg. Empty Flag)

FIGURE 18-5:

ASYNCHRONOUS TRANSMISSION (BACK TO BACK),

TXCKP = 0 (TX NOT INVERTED)

Write to TXREG

Word 2

Start bit

Word 1

BRG Output

(Shift Clock)

TX (pin)

Start bit

Word 2

bit 0

bit 1

Word 1

bit 7/8

bit 0

Stop bit

1 TCY

TXIF bit

(Interrupt Reg. Flag)

1 TCY

Word 1

Transmit Shift Reg.

Word 2

Transmit Shift Reg.

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Note: This timing diagram shows two consecutive transmissions.

DS39689E-page 216

Preliminary

PIC18F4321 FAMILY

TABLE 18-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE

SSPIF

SSPIE

SSPIP

ADDEN

TMR0IF

INT0IF

RBIF

49

52

51

PSPIF⁽¹⁾

PSPIE⁽¹⁾

PSPIP⁽¹⁾

SPEN

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

SREN

CCP1IF TMR2IF TMR1IF

CCP1IE TMR2IE TMR1IE

CCP1IP TMR2IP TMR1IP

PIE1

TXIE

IPR1

TXIP

RCSTA

TXREG

TXSTA

BAUDCON

SPBRGH

SPBRG

CREN

FERR

OERR

RX9D

EUSART Transmit Register

CSRC

TX9

TXEN

SYNC

SENDB

BRG16

BRGH

—

TRMT

WUE

TX9D

ABDOVF

RCIDL

RXDTP

TXCKP

ABDEN

EUSART Baud Rate Generator Register High Byte

EUSART Baud Rate Generator Register Low Byte

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.

Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’.

Preliminary

DS39689E-page 217

PIC18F4321 FAMILY

18.2.2

EUSART ASYNCHRONOUS

RECEIVER

18.2.3

SETTING UP 9-BIT MODE WITH

ADDRESS DETECT

The receiver block diagram is shown in Figure 18-6.

The data is received on the RX pin and drives the data

recovery block. The data recovery block is actually a

high-speed shifter operating at x16 times the baud rate,

whereas the main receive serial shifter operates at the

bit rate or at FOSC. This mode would typically be used

in RS-232 systems.

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate.

The RXDTP bit (BAUDCON<5>) allows the RX signal to

be inverted (polarity reversed). Devices that buffer sig-

nals from RS-232 to TTL levels also perform an inver-

sion of the signal (when RS-232 = positive, TTL = 0).

Inverting the polarity of the RX pin data by setting the

RXDTP bit allows for the use of circuits that provide

buffering without inverting the signal.

2. Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

3. If the signal at the RX pin is to be inverted, set

the RXDTP bit. If the signal from the TX pin is to

be inverted, set the TXCKP bit.

4. If interrupts are required, set the RCEN bit and

select the desired priority level with the RCIP bit.

To set up an Asynchronous Reception:

5. Set the RX9 bit to enable 9-bit reception.

6. Set the ADDEN bit to enable address detect.

7. Enable reception by setting the CREN bit.

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate.

8. The RCIF bit will be set when reception is

complete. The interrupt will be Acknowledged if

the RCIE and GIE bits are set.

2. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

9. Read the RCSTA register to determine if any

error occurred during reception, as well as read

bit 9 of data (if applicable).

3. If the signal at the RX pin is to be inverted, set

the RXDTP bit.

4. If interrupts are desired, set enable bit RCIE.

5. If 9-bit reception is desired, set bit RX9.

6. Enable the reception by setting bit CREN.

10. Read RCREG to determine if the device is being

addressed.

11. If any error occurred, clear the CREN bit.

7. Flag bit, RCIF, will be set when reception is

complete and an interrupt will be generated if

enable bit, RCIE, was set.

12. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and interrupt the CPU.

8. Read the RCSTA register to get the 9th bit (if

enabled) and determine if any error occurred

during reception.

9. Read the 8-bit received data by reading the

RCREG register.

10. If any error occurred, clear the error by clearing

enable bit CREN.

11. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

DS39689E-page 218

Preliminary

PIC18F4321 FAMILY

FIGURE 18-6:

EUSART RECEIVE BLOCK DIAGRAM

CREN

OERR

FERR

x64 Baud Rate CLK

SPBRGH SPBRG

÷ 64

or

RSR Register

• • •

MSb

Stop

LSb

Start

BRG16

÷ 16

(8)

7

1

0

or

÷ 4

Baud Rate Generator

RX9

Pin Buffer

and Control

Data

Recovery

RX

RX9D

RCREG Register

FIFO

RXDTP

SPEN

8

Data Bus

Interrupt

RCIF

RCIE

FIGURE 18-7:

ASYNCHRONOUS RECEPTION, TXCKP = 0 (TX NOT INVERTED)

Start

bit

Start

bit

Start

bit

RX (pin)

Stop

bit

Stop

bit

Stop

bit

bit 0 bit 1

bit 7/8

bit 0

bit 7/8

Rcv Shift Reg

Rcv Buffer Reg

Word 2

RCREG

Word 1

RCREG

Read Rcv

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causing

the OERR (overrun) bit to be set.

TABLE 18-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Reset

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Values

on page

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE

SSPIF

SSPIE

SSPIP

ADDEN

TMR0IF

INT0IF

RBIF

49

52

51

PSPIF⁽¹⁾

PSPIE⁽¹⁾

PSPIP⁽¹⁾

SPEN

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

SREN

CCP1IF TMR2IF TMR1IF

CCP1IE TMR2IE TMR1IE

CCP1IP TMR2IP TMR1IP

PIE1

TXIE

IPR1

TXIP

RCSTA

RCREG

TXSTA

CREN

FERR

OERR

RX9D

EUSART Receive Register

CSRC

TX9

TXEN

SYNC

SENDB

BRG16

BRGH

—

TRMT

WUE

TX9D

BAUDCON ABDOVF

RCIDL

RXDTP

TXCKP

ABDEN

SPBRGH

SPBRG

EUSART Baud Rate Generator Register High Byte

EUSART Baud Rate Generator Register Low Byte

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.

Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’.

Preliminary

DS39689E-page 219

PIC18F4321 FAMILY

character and cause data or framing errors. To work

properly, therefore, the initial character in the trans-

mission must be all ‘0’s. This can be 00h (8 bytes) for

standard RS-232 devices or 000h (12 bits) for LIN bus.

18.2.4

AUTO-WAKE-UP ON SYNC

BREAK CHARACTER

During Sleep mode, all clocks to the EUSART are

suspended. Because of this, the Baud Rate Generator

is inactive and a proper byte reception cannot be per-

formed. The auto-wake-up feature allows the controller

to wake-up due to activity on the RX/DT line while the

EUSART is operating in Asynchronous mode.

Oscillator start-up time must also be considered,

especially in applications using oscillators with longer

start-up intervals (i.e., XT or HS mode). The Sync

Break (or Wake-up Signal) character must be of

sufficient length and be followed by a sufficient interval

to allow enough time for the selected oscillator to start

and provide proper initialization of the EUSART.

The auto-wake-up feature is enabled by setting the

WUE bit (BAUDCON<1>). Once set, the typical receive

sequence on RX/DT is disabled and the EUSART

remains in an Idle state, monitoring for a wake-up event

independent of the CPU mode. A wake-up event

consists of a high-to-low transition on the RX/DT line.

(This coincides with the start of a Sync Break or a

Wake-up Signal character for the LIN protocol.)

18.2.4.2

Special Considerations Using

the WUE Bit

The timing of WUE and RCIF events may cause some

confusion when it comes to determining the validity of

received data. As noted, setting the WUE bit places the

EUSART in an Idle mode. The wake-up event causes a

receive interrupt by setting the RCIF bit. The WUE bit is

cleared after this when a rising edge is seen on RX/DT.

The interrupt condition is then cleared by reading the

RCREG register. Ordinarily, the data in RCREG will be

dummy data and should be discarded.

Following a wake-up event, the module generates an

RCIF interrupt. The interrupt is generated synchro-

nously to the Q clocks in normal operating modes

(Figure 18-8) and asynchronously, if the device is in

Sleep mode (Figure 18-9). The interrupt condition is

cleared by reading the RCREG register.

The WUE bit is automatically cleared once a low-to-

high transition is observed on the RX line following the

wake-up event. At this point, the EUSART module is in

Idle mode and returns to normal operation. This signals

to the user that the Sync Break event is over.

The fact that the WUE bit has been cleared (or is still

set) and the RCIF flag is set should not be used as an

indicator of the integrity of the data in RCREG. Users

should consider implementing a parallel method in

firmware to verify received data integrity.

To assure that no actual data is lost, check the RCIDL

bit to verify that a receive operation is not in process. If

a receive operation is not occurring, the WUE bit may

then be set just prior to entering the Sleep mode.

18.2.4.1

Special Considerations Using

Auto-Wake-up

Since auto-wake-up functions by sensing rising edge

transitions on RX/DT, information with any state

changes before the Stop bit may signal a false end-of-

FIGURE 18-8:

AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

WUE bit⁽¹⁾

RX/DT Line

RCIF

Bit set by user

Auto-Cleared

Cleared due to user read of RCREG

Note 1: The EUSART remains in Idle while the WUE bit is set.

FIGURE 18-9:

AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1

Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

WUE bit⁽²⁾

RX/DT Line

RCIF

Bit set by user

Auto-Cleared

Note 1

Cleared due to user read of RCREG

Sleep Ends

Sleep Command Executed

Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This

sequence should not depend on the presence of Q clocks.

2: The EUSART remains in Idle while the WUE bit is set.

DS39689E-page 220

Preliminary

PIC18F4321 FAMILY

1. Configure the EUSART for the desired mode.

18.2.5

BREAK CHARACTER SEQUENCE

2. Set the TXEN and SENDB bits to set up the

Break character.

The EUSART module has the capability of sending the

special Break character sequences that are required by

the LIN bus standard. The Break character transmit

consists of a Start bit, followed by twelve ‘0’ bits and a

Stop bit. The Frame Break character is sent whenever

the SENDB and TXEN bits (TXSTA<3> and

TXSTA<5>) are set while the Transmit Shift register is

loaded with data. Note that the value of data written to

TXREG will be ignored and all ‘0’s will be transmitted.

3. Load the TXREG with a dummy character to

initiate transmission (the value is ignored).

4. Write ‘55h’ to TXREG to load the Sync character

into the transmit FIFO buffer.

5. After the Break has been sent, the SENDB bit is

reset by hardware. The Sync character now

transmits in the preconfigured mode.

The SENDB bit is automatically reset by hardware after

the corresponding Stop bit is sent. This allows the user

to preload the transmit FIFO with the next transmit byte

following the Break character (typically, the Sync

character in the LIN specification).

When the TXREG becomes empty, as indicated by the

TXIF, the next data byte can be written to TXREG.

18.2.6

RECEIVING A BREAK CHARACTER

The Enhanced USART module can receive a Break

character in two ways.

Note that the data value written to the TXREG for the

Break character is ignored. The write simply serves the

purpose of initiating the proper sequence.

The first method forces configuration of the baud rate

at a frequency of 9/13 the typical speed. This allows for

the Stop bit transition to be at the correct sampling loca-

tion (13 bits for Break versus Start bit and 8 data bits for

typical data).

The TRMT bit indicates when the transmit operation is

active or Idle, just as it does during normal transmis-

sion. See Figure 18-10 for the timing of the Break

character sequence.

The second method uses the auto-wake-up feature

described in Section 18.2.4 “Auto-Wake-up on Sync

Break Character”. By enabling this feature, the

EUSART will sample the next two transitions on RX/DT,

cause an RCIF interrupt and receive the next data byte

followed by another interrupt.

18.2.5.1

Break and Sync Transmit Sequence

The following sequence will send a message frame

header made up of a Break, followed by an Auto-Baud

Sync byte. This sequence is typical of a LIN bus

master.

Note that following a Break character, the user will

typically want to enable the Auto-Baud Rate Detect

feature. For both methods, the user can set the ABD bit

once the TXIF interrupt is observed.

FIGURE 18-10:

SEND BREAK CHARACTER SEQUENCE

Write to TXREG

Dummy Write

BRG Output

(Shift Clock)

TX (pin)

Start Bit

Bit 0

Bit 1

Break

Bit 11

Stop Bit

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

SENDB sampled here

Auto-Cleared

SENDB

(Transmit Shift

Reg. Empty Flag)

Preliminary

DS39689E-page 221

PIC18F4321 FAMILY

Once the TXREG register transfers the data to the TSR

register (occurs in one TCY), the TXREG is empty and

the TXIF flag bit (PIR1<4>) is set. The interrupt can be

enabled or disabled by setting or clearing the interrupt

enable bit, TXIE (PIE1<4>). TXIF is set regardless of

the state of enable bit TXIE; it cannot be cleared in soft-

ware. It will reset only when new data is loaded into the

TXREG register.

18.3 EUSART Synchronous

Master Mode

The Synchronous Master mode is entered by setting

the CSRC bit (TXSTA<7>). In this mode, the data is

transmitted in a half-duplex manner (i.e., transmission

and reception do not occur at the same time). When

transmitting data, the reception is inhibited and vice

versa. Synchronous mode is entered by setting bit

SYNC (TXSTA<4>). In addition, enable bit SPEN

(RCSTA<7>) is set in order to configure the TX and RX

pins to CK (clock) and DT (data) lines, respectively.

While flag bit TXIF indicates the status of the TXREG

register, another bit, TRMT (TXSTA<1>), shows the

status of the TSR register. TRMT is a read-only bit which

is set when the TSR is empty. No interrupt logic is tied to

this bit so the user has to poll this bit in order to deter-

mine if the TSR register is empty. The TSR is not

mapped in data memory so it is not available to the user.

The Master mode indicates that the processor

transmits the master clock on the CK line.

Clock polarity (CK) is selected with the TXCKP bit

(BAUDCON<4>). Setting TXCKP sets the Idle state on

CK as high, while clearing the bit sets the Idle state as

low. Data polarity (DT) is selected with the RXDTP bit

(BAUDCON<5>). Setting RXDTP sets the Idle state on

DT as high, while clearing the bit sets the Idle state as

low. DT is sampled when CK returns to its idle state.

This option is provided to support Microwire devices

with this module.

To set up a Synchronous Master Transmission:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRG16

bit, as required, to achieve the desired baud rate.

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. If the signal from the CK pin is to be inverted, set

the TXCKP bit. If the signal from the DT pin is to

be inverted, set the RXDTP bit.

18.3.1

EUSART SYNCHRONOUS MASTER

TRANSMISSION

4. If interrupts are desired, set enable bit TXIE.

5. If 9-bit transmission is desired, set bit TX9.

6. Enable the transmission by setting bit TXEN.

The EUSART transmitter block diagram is shown in

Figure 18-3. The heart of the transmitter is the Transmit

(Serial) Shift Register (TSR). The Shift register obtains

its data from the Read/Write Transmit Buffer register,

TXREG. The TXREG register is loaded with data in

software. The TSR register is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new data from the TXREG (if available).

7. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

8. Start transmission by loading data to the TXREG

register.

9. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

FIGURE 18-11:

SYNCHRONOUS TRANSMISSION

Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4

Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3 Q4 Q1 Q2Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4

RC7/RX/DT

bit 0

bit 1

bit 2

bit 7

bit 0

bit 1

bit 7

Word 2

Word 1

RC6/TX/CK pin

(TXCKP = 0)

RC6/TX/CK pin

(TXCKP = 1)

Write to

TXREG Reg

Write Word 1

Write Word 2

TXIF bit

(Interrupt Flag)

TRMT bit

TXEN bit

‘1’

Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.

DS39689E-page 222

Preliminary

PIC18F4321 FAMILY

FIGURE 18-12:

SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RC7/RX/DT pin

bit 0

bit 2

bit 1

bit 6

bit 7

RC6/TX/CK pin

Write to

TXREG reg

TXIF bit

TRMT bit

TXEN bit

TABLE 18-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE

SSPIF

SSPIE

SSPIP

ADDEN

TMR0IF

INT0IF

RBIF

49

52

51

PSPIF⁽¹⁾

PSPIE⁽¹⁾

PSPIP⁽¹⁾

SPEN

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

SREN

CCP1IF TMR2IF TMR1IF

CCP1IE TMR2IE TMR1IE

CCP1IP TMR2IP TMR1IP

PIE1

TXIE

IPR1

TXIP

RCSTA

TXREG

TXSTA

CREN

FERR

OERR

RX9D

EUSART Transmit Register

CSRC

TX9

TXEN

SYNC

SENDB

BRG16

BRGH

—

TRMT

WUE

TX9D

BAUDCON ABDOVF

RCIDL

RXDTP

TXCKP

ABDEN

SPBRGH

SPBRG

EUSART Baud Rate Generator Register High Byte

EUSART Baud Rate Generator Register Low Byte

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.

Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’.

Preliminary

DS39689E-page 223

PIC18F4321 FAMILY

4. If the signal from the CK pin is to be inverted, set

the TXCKP bit. If the signal from the DT pin is to

be inverted, set the RXDTP bit.

18.3.2

EUSART SYNCHRONOUS

MASTER RECEPTION

Once Synchronous mode is selected, reception is

enabled by setting either the Single Receive Enable bit,

SREN (RCSTA<5>), or the Continuous Receive

Enable bit, CREN (RCSTA<4>). Data is sampled on the

RX pin on the falling edge of the clock.

5. If interrupts are desired, set enable bit RCIE.

6. If 9-bit reception is desired, set bit RX9.

7. If a single reception is required, set bit SREN.

For continuous reception, set bit CREN.

8. Interrupt flag bit, RCIF, will be set when reception

is complete and an interrupt will be generated if

the enable bit, RCIE, was set.

If enable bit SREN is set, only a single word is received.

If enable bit CREN is set, the reception is continuous

until CREN is cleared. If both bits are set, then CREN

takes precedence.

9. Read the RCSTA register to get the 9th bit (if

enabled) and determine if any error occurred

during reception.

To set up a Synchronous Master Reception:

1. Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRG16

bit, as required, to achieve the desired baud rate.

10. Read the 8-bit received data by reading the

RCREG register.

11. If any error occurred, clear the error by clearing

bit CREN.

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

12. If using interrupts, ensure that the GIE and PEIE bits

in the INTCON register (INTCON<7:6>) are set.

3. Ensure bits CREN and SREN are clear.

FIGURE 18-13:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

RC7/RX/DT

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

RC6/TX/CK pin

(TXCKP = 0)

RC6/TX/CK pin

(TXCKP = 1)

Write to

bit SREN

SREN bit

CREN bit

‘0’

RCIF bit

(Interrupt)

Read

RXREG

Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.

TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Reset Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

SSPIF

SSPIE

SSPIP

ADDEN

TMR0IF

INT0IF

RBIF

49

52

51

PSPIF⁽¹⁾

PSPIE⁽¹⁾

PSPIP⁽¹⁾

SPEN

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

SREN

TXIF

TXIE

CCP1IF TMR2IF TMR1IF

CCP1IE TMR2IE TMR1IE

CCP1IP TMR2IP TMR1IP

PIE1

IPR1

TXIP

RCSTA

RCREG

TXSTA

CREN

FERR

OERR

RX9D

EUSART Receive Register

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

—

TRMT

WUE

TX9D

BAUDCON ABDOVF

RCIDL

RXDTP TXCKP BRG16

ABDEN

SPBRGH EUSART Baud Rate Generator Register High Byte

SPBRG EUSART Baud Rate Generator Register Low Byte

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.

Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’.

DS39689E-page 224

Preliminary

PIC18F4321 FAMILY

To set up a Synchronous Slave Transmission:

18.4 EUSART Synchronous

Slave Mode

1. Enable the synchronous slave serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

Synchronous Slave mode is entered by clearing bit,

CSRC (TXSTA<7>). This mode differs from the

Synchronous Master mode in that the shift clock is sup-

plied externally at the CK pin (instead of being supplied

internally in Master mode). This allows the device to

transfer or receive data while in any power-managed

mode.

2. Clear bits CREN and SREN.

3. If interrupts are desired, set enable bit TXIE.

4. If the signal from the CK pin is to be inverted, set

the TXCKP bit. If the signal from the DT pin is to

be inverted, set the RXDTP bit.

5. If 9-bit transmission is desired, set bit TX9.

18.4.1

EUSART SYNCHRONOUS

SLAVE TRANSMISSION

6. Enable the transmission by setting enable bit

TXEN.

The operation of the Synchronous Master and Slave

modes are identical, except in the case of the Sleep

mode.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

8. Start transmission by loading data to the

TXREGx register.

If two words are written to the TXREG and then the

SLEEPinstruction is executed, the following will occur:

9. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

a) The first word will immediately transfer to the

TSR register and transmit.

b) The second word will remain in the TXREG

register.

c) Flag bit, TXIF, will not be set.

d) When the first word has been shifted out of TSR,

the TXREG register will transfer the second word

to the TSR and flag bit, TXIF, will now be set.

e) If enable bit TXIE is set, the interrupt will wake the

chip from Sleep. If the global interrupt is enabled,

the program will branch to the interrupt vector.

TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE

SSPIF

SSPIE

SSPIP

ADDEN

TMR0IF

CCP1IF

INT0IF

RBIF

49

52

51

PSPIF⁽¹⁾

PSPIE⁽¹⁾

PSPIP⁽¹⁾

SPEN

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

SREN

TMR2IF TMR1IF

PIE1

TXIE

CCP1IE TMR2IE TMR1IE

CCP1IP TMR2IP TMR1IP

IPR1

TXIP

RCSTA

TXREG

TXSTA

CREN

FERR

OERR

RX9D

EUSART Transmit Register

CSRC

TX9

TXEN

SYNC

SENDB

BRG16

BRGH

—

TRMT

WUE

TX9D

BAUDCON ABDOVF

RCIDL

RXDTP

TXCKP

ABDEN

SPBRGH

SPBRG

EUSART Baud Rate Generator Register High Byte

EUSART Baud Rate Generator Register Low Byte

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.

Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’.

Preliminary

DS39689E-page 225

PIC18F4321 FAMILY

To set up a Synchronous Slave Reception:

18.4.2

EUSART SYNCHRONOUS SLAVE

RECEPTION

1. Enable the synchronous master serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

The operation of the Synchronous Master and Slave

modes is identical, except in the case of Sleep, or any

Idle mode and bit SREN, which is a “don’t care” in

Slave mode.

2. If interrupts are desired, set enable bit RCIE.

3. If the signal from the CK pin is to be inverted, set

the TXCKP bit. If the signal from the DT pin is to

be inverted, set the RXDTP bit.

If receive is enabled by setting the CREN bit prior to

entering Sleep or any Idle mode, then a word may be

received while in this low-power mode. Once the word

is received, the RSR register will transfer the data to the

RCREG register; if the RCIE enable bit is set, the

interrupt generated will wake the chip from the low-

power mode. If the global interrupt is enabled, the

program will branch to the interrupt vector.

4. If 9-bit reception is desired, set bit RX9.

5. To enable reception, set enable bit CREN.

6. Flag bit, RCIF, will be set when reception is

complete. An interrupt will be generated if

enable bit, RCIE, was set.

7. Read the RCSTA register to get the 9th bit (if

enabled) and determine if any error occurred

during reception.

8. Read the 8-bit received data by reading the

RCREG register.

9. If any error occurred, clear the error by clearing

bit CREN.

10. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

RBIE

SSPIF

SSPIE

SSPIP

ADDEN

TMR0IF

CCP1IF

INT0IF

RBIF

49

52

51

PSPIF⁽¹⁾

PSPIE⁽¹⁾

PSPIP⁽¹⁾

SPEN

ADIF

ADIE

ADIP

RX9

RCIF

RCIE

RCIP

SREN

TMR2IF TMR1IF

PIE1

TXIE

CCP1IE TMR2IE TMR1IE

CCP1IP TMR2IP TMR1IP

IPR1

TXIP

RCSTA

RCREG

TXSTA

CREN

FERR

OERR

RX9D

EUSART Receive Register

CSRC

TX9

TXEN

SYNC

SENDB

BRG16

BRGH

—

TRMT

WUE

TX9D

BAUDCON ABDOVF

RCIDL

RXDTP

TXCKP

ABDEN

SPBRGH

SPBRG

EUSART Baud Rate Generator Register High Byte

EUSART Baud Rate Generator Register Low Byte

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.

Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’.

DS39689E-page 226

Preliminary

PIC18F4321 FAMILY

The ADCON0 register, shown in Register 19-1,

controls the operation of the A/D module. The

ADCON1 register, shown in Register 19-2, configures

the functions of the port pins. The ADCON2 register,

shown in Register 19-3, configures the A/D clock

source, programmed acquisition time and justification.

19.0 10-BIT ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

The Analog-to-Digital (A/D) converter module has

10 inputs for the 28-pin devices and 13 for the 40/44-pin

devices. This module allows conversion of an analog

input signal to a corresponding 10-bit digital number.

The module has five registers:

• A/D Result High Register (ADRESH)

• A/D Result Low Register (ADRESL)

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

• A/D Control Register 2 (ADCON2)

REGISTER 19-1: ADCON0: A/D CONTROL REGISTER 0

U-0

—

U-0

—

R/W-0

CHS3

R/W-0

CHS2

R/W-0

CHS1

R/W-0

CHS0

R/W-0

ADON

GO/DONE

bit 7

bit 0

bit 7-6

bit 5-2

Unimplemented: Read as ‘0’

CHS3:CHS0: Analog Channel Select bits

0000= Channel 0 (AN0)

0001= Channel 1 (AN1)

0010= Channel 2 (AN2)

0011= Channel 3 (AN3)

0100= Channel 4 (AN4)

0101= Channel 5 (AN5)^(1,2)

0110= Channel 6 (AN6)^(1,2)

0111= Channel 7 (AN7)^(1,2)

1000= Channel 8 (AN8)

1001= Channel 9 (AN9)

1010= Channel 10 (AN10)

1011= Channel 11 (AN11)

1100= Channel 12 (AN12

1101= Unimplemented⁽²⁾

1110= Unimplemented⁽²⁾

1111= Unimplemented⁽²⁾

Note 1: These channels are not implemented on 28-pin devices.

2: Performing a conversion on unimplemented channels will return a floating input

measurement.

bit 1

bit 0

GO/DONE: A/D Conversion Status bit

When ADON = 1:

1= A/D conversion in progress

0= A/D Idle

ADON: A/D On bit

1= A/D converter module is enabled

0= A/D converter module is disabled

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39689E-page 227

PIC18F4321 FAMILY

REGISTER 19-2: ADCON1: A/D CONTROL REGISTER 1

U-0

—

U-0

—

R/W-0

R/W-0⁽¹⁾

PCFG3

R/W⁽¹⁾

VCFG1

VCFG0

PCFG2

PCFG1

PCFG0

bit 7

bit 0

bit 7-6

bit 5

Unimplemented: Read as ‘0’

VCFG1: Voltage Reference Configuration bit (VREF- source)

1= VREF- (AN2)

0= VSS

bit 4

VCFG0: Voltage Reference Configuration bit (VREF+ source)

1= VREF+ (AN3)

0= VDD

bit 3-0

PCFG3:PCFG0: A/D Port Configuration Control bits

PCFG3:

PCFG0

0000⁽¹⁾

0001

0010

0011

0100

0101

0110

A

D

A

D

A

D

A

D

A

D

A

0111⁽¹⁾

1000

1001

1010

1011

1100

1101

1110

1111

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A = Analog input

D = Digital I/O

Note 1: The POR value of the PCFG bits depends on the value of the PBADEN con-

figuration bit. When PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0,

PCFG<3:0> = 0111.

2: AN5 through AN7 are available only on 40/44-pin devices.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39689E-page 228

Preliminary

PIC18F4321 FAMILY

REGISTER 19-3: ADCON2: A/D CONTROL REGISTER 2

R/W-0

ADFM

U-0

—

R/W-0

ACQT2

ACQT1

ACQT0

ADCS2

ADCS1

ADCS0

bit 7

bit 0

bit 7

ADFM: A/D Result Format Select bit

1= Right justified

0= Left justified

bit 6

Unimplemented: Read as ‘0’

bit 5-3

ACQT2:ACQT0: A/D Acquisition Time Select bits

111= 20 TAD

110= 16 TAD

101= 12 TAD

100= 8 TAD

011= 6 TAD

010= 4 TAD

001= 2 TAD

(1)

000= 0 TAD

bit 2-0

ADCS2:ADCS0: A/D Conversion Clock Select bits

111= FRC (clock derived from A/D RC oscillator)⁽¹⁾

110= FOSC/64

101= FOSC/16

100= FOSC/4

011= FRC (clock derived from A/D RC oscillator)⁽¹⁾

010= FOSC/32

001= FOSC/8

000= FOSC/2

Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is

added before the A/D clock starts. This allows the SLEEPinstruction to be executed

before starting a conversion.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39689E-page 229

PIC18F4321 FAMILY

The analog reference voltage is software selectable to

either the device’s positive and negative supply voltage

(VDD and VSS), or the voltage level on the RA3/AN3/

VREF+ and RA2/AN2/VREF-/CVREF pins.

A device Reset forces all registers to their Reset state.

This forces the A/D module to be turned off and any

conversion in progress is aborted.

Each port pin associated with the A/D converter can be

configured as an analog input, or as a digital I/O. The

ADRESH and ADRESL registers contain the result of

the A/D conversion. When the A/D conversion is

The A/D converter has a unique feature of being able

to operate while the device is in Sleep mode. To

operate in Sleep, the A/D conversion clock must be

derived from the A/D’s internal RC oscillator.

complete,

the

result

is

loaded

into

the

ADRESH:ADRESL register pair, the GO/DONE bit

(ADCON0 register) is cleared and A/D Interrupt Flag bit,

ADIF, is set. The block diagram of the A/D module is

shown in Figure 19-1.

The output of the sample and hold is the input into the

converter, which generates the result via successive

approximation.

FIGURE 19-1:

A/D BLOCK DIAGRAM

CHS3:CHS0

1100

AN12

1011

AN11

1010

AN10

1001

AN9

1000

AN8

0111

AN7⁽¹⁾

0110

AN6⁽¹⁾

0101

AN5⁽¹⁾

0100

AN4

VAIN

0011

(Input Voltage)

10-Bit

Converter

A/D

AN3

0010

AN2

0001

VCFG1:VCFG0

AN1

0000

VDD

AN0

X0

X1

1X

VREF+

VREF-

Reference

Voltage

0X

VSS

Note 1: Channels AN5 through AN7 are not available on 28-pin devices.

2: I/O pins have diode protection to VDD and VSS.

DS39689E-page 230

Preliminary

PIC18F4321 FAMILY

The value in the ADRESH:ADRESL registers is not

modified for a Power-on Reset. The ADRESH:ADRESL

registers will contain unknown data after a Power-on

Reset.

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared

OR

• Waiting for the A/D interrupt

After the A/D module has been configured as desired,

the selected channel must be acquired before the

conversion is started. The analog input channels must

have their corresponding TRIS bits selected as an

input. To determine acquisition time, see Section 19.1

“A/D Acquisition Requirements”. After this acquisi-

tion time has elapsed, the A/D conversion can be

started. An acquisition time can be programmed to

occur between setting the GO/DONE bit and the actual

start of the conversion.

6. Read A/D Result registers (ADRESH:ADRESL);

clear bit ADIF, if required.

7. For next conversion, go to step 1 or step 2, as

required. The A/D conversion time per bit is

defined as TAD. A minimum wait of 2 TAD is

required before the next acquisition starts.

FIGURE 19-2:

A/D TRANSFER FUNCTION

The following steps should be followed to perform an A/D

conversion:

3FFh

3FEh

1. Configure the A/D module:

• Configure analog pins, voltage reference and

digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D acquisition time (ADCON2)

• Select A/D conversion clock (ADCON2)

• Turn on A/D module (ADCON0)

2. Configure A/D interrupt (if desired):

• Clear ADIF bit

003h

002h

001h

000h

• Set ADIE bit

• Set GIE bit

3. Wait the required acquisition time (if required).

4. Start conversion:

Analog Input Voltage

• Set GO/DONE bit (ADCON0 register)

FIGURE 19-3:

ANALOG INPUT MODEL

VDD

Sampling

Switch

VT = 0.6V

ANx

SS

RIC ≤ 1k

RSS

Rs

CPIN

VAIN

ILEAKAGE

±100 nA

CHOLD = 25 pF

VT = 0.6V

5 pF

VSS

Legend: CPIN

= Input Capacitance

= Threshold Voltage

VT

6V

5V

4V

3V

2V

ILEAKAGE = Leakage Current at the pin due to

various junctions

VDD

RIC

= Interconnect Resistance

SS

= Sampling Switch

CHOLD

RSS

= Sample/Hold Capacitance (from DAC)

= Sampling Switch Resistance

1

2

3

4

(kΩ)

Sampling Switch

Preliminary

DS39689E-page 231

PIC18F4321 FAMILY

To calculate the minimum acquisition time,

Equation 19-1 may be used. This equation assumes

that 1/2 LSb error is used (1024 steps for the A/D). The

1/2 LSb error is the maximum error allowed for the A/D

to meet its specified resolution.

19.1 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 19-3. The

source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor CHOLD. The sampling

switch (RSS) impedance varies over the device voltage

(VDD). The source impedance affects the offset voltage

at the analog input (due to pin leakage current). The

maximum recommended impedance for analog

sources is 2.5 kΩ. After the analog input channel is

selected (changed), the channel must be sampled for

at least the minimum acquisition time before starting a

conversion.

Example 19-3 shows the calculation of the minimum

required acquisition time TACQ. This calculation is

based on the following application system

assumptions:

CHOLD

Rs

Conversion Error

VDD

Temperature

=

≤

=

25 pF

2.5 kΩ

1/2 LSb

5V → Rss = 2 kΩ

85°C (system max.)

Note:

When the conversion is started, the

holding capacitor is disconnected from the

input pin.

EQUATION 19-1: ACQUISITION TIME

TACQ

=

Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient

TAMP + TC + TCOFF

EQUATION 19-2: A/D MINIMUM CHARGING TIME

VHOLD

or

TC

=

(VREF – (VREF/2048)) • (1 – e^{(-TC/CHOLD(RIC + RSS + RS))}

)

-(CHOLD)(RIC + RSS + RS) ln(1/2048)

EQUATION 19-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

TACQ

TAMP

TCOFF

=

TAMP + TC + TCOFF

0.2 μs

(Temp – 25°C)(0.02 μs/°C)

(85°C – 25°C)(0.02 μs/°C)

1.2 μs

Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 ms.

TC

=

-(CHOLD)(RIC + RSS + RS) ln(1/2047)

-(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883)

1.05 μs

TACQ

=

0.2 μs + 1 μs + 1.2 μs

2.4 μs

DS39689E-page 232

Preliminary

PIC18F4321 FAMILY

19.2 Selecting and Configuring

Acquisition Time

19.3 Selecting the A/D Conversion

Clock

The ADCON2 register allows the user to select an

acquisition time that occurs each time the GO/DONE

bit is set. It also gives users the option to use an

automatically determined acquisition time.

The A/D conversion time per bit is defined as TAD. The

A/D conversion requires 11 TAD per 10-bit conversion.

The source of the A/D conversion clock is software

selectable. There are seven possible options for TAD:

Acquisition time may be set with the ACQT2:ACQT0

bits (ADCON2<5:3>), which provides a range of 2 to

20 TAD. When the GO/DONE bit is set, the A/D module

continues to sample the input for the selected acquisi-

tion time, then automatically begins a conversion.

Since the acquisition time is programmed, there may

be no need to wait for an acquisition time between

selecting a channel and setting the GO/DONE bit.

• 2 TOSC

• 4 TOSC

• 8 TOSC

• 16 TOSC

• 32 TOSC

• 64 TOSC

• Internal RC Oscillator

Manual

acquisition

is

selected

when

For correct A/D conversions, the A/D conversion clock

(TAD) must be as short as possible, but greater than the

minimum TAD (see parameter 130 for more

information).

ACQT2:ACQT0 = 000. When the GO/DONE bit is set,

sampling is stopped and a conversion begins. The user

is responsible for ensuring the required acquisition time

has passed between selecting the desired input

channel and setting the GO/DONE bit. This option is

also the default Reset state of the ACQT2:ACQT0 bits

and is compatible with devices that do not offer

programmable acquisition times.

Table 19-1 shows the resultant TAD times derived from

the device operating frequencies and the A/D clock

source selected.

In either case, when the conversion is completed, the

GO/DONE bit is cleared, the ADIF flag is set and the

A/D begins sampling the currently selected channel

again. If an acquisition time is programmed, there is

nothing to indicate if the acquisition time has ended or

if the conversion has begun.

TABLE 19-1: TAD vs. DEVICE OPERATING FREQUENCIES

AD Clock Source (TAD)

Maximum Device Frequency

Operation

ADCS2:ADCS0

PIC18F2X21/4X21

PIC18LF2X21/4X21⁽⁴⁾

2 TOSC

4 TOSC

8 TOSC

16 TOSC

32 TOSC

64 TOSC

RC⁽³⁾

000

100

001

101

010

110

x11

2.86 MHz

5.71 MHz

11.43 MHz

22.86 MHz

40.0 MHz

1.00 MHz⁽¹⁾

1.43 kHz

2.86 MHz

5.72 MHz

11.43 MHz

22.86 MHz

1.00 MHz⁽²⁾

Note 1: The RC source has a typical TAD time of 1.2 μs.

2: The RC source has a typical TAD time of 2.5 μs.

3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D

accuracy may be out of specification.

4: Low-power (PIC18LFXXXX) devices only.

Preliminary

DS39689E-page 233

PIC18F4321 FAMILY

19.4 Operation in Power-Managed

Modes

19.5 Configuring Analog Port Pins

The ADCON1, TRISA, TRISB and TRISE registers all

configure the A/D port pins. The port pins needed as

analog inputs must have their corresponding TRIS bits

set (input). If the TRIS bit is cleared (output), the digital

output level (VOH or VOL) will be converted.

The selection of the automatic acquisition time and A/D

conversion clock is determined in part by the clock

source and frequency while in a power-managed mode.

If the A/D is expected to operate while the device is in

a power-managed mode, the ACQT2:ACQT0 and

ADCS2:ADCS0 bits in ADCON2 should be updated in

accordance with the clock source to be used in that

mode. After entering the mode, an A/D acquisition or

conversion may be started. Once started, the device

should continue to be clocked by the same clock

source until the conversion has been completed.

The A/D operation is independent of the state of the

CHS3:CHS0 bits and the TRIS bits.

Note 1: When reading the Port register, all pins

configured as analog input channels will

read as cleared (a low level). Pins

configured as digital inputs will convert as

analog inputs. Analog levels on a digitally

configured input will be accurately

converted.

If desired, the device may be placed into the

corresponding Idle mode during the conversion. If the

device clock frequency is less than 1 MHz, the A/D RC

clock source should be selected.

2: Analog levels on any pin defined as a

digital input may cause the digital input

buffer to consume current out of the

device’s specification limits.

Operation in Sleep mode requires the A/D FRC clock to

be selected. If bits ACQT2:ACQT0 are set to ‘000’ and

a conversion is started, the conversion will be delayed

one instruction cycle to allow execution of the SLEEP

instruction and entry to Sleep mode. The IDLEN bit

(OSCCON<7>) must have already been cleared prior

to starting the conversion.

3: The PBADEN bit in Configuration

Register 3H configures PORTB pins to

reset as analog or digital pins by control-

ling how the PCFG<3:0> bits in ADCON1

are reset.

DS39689E-page 234

Preliminary

PIC18F4321 FAMILY

After the A/D conversion is completed or aborted, a

2 TAD wait is required before the next acquisition can be

started. After this wait, acquisition on the selected

channel is automatically started.

19.6 A/D Conversions

Figure 19-4 shows the operation of the A/D converter

after the GO/DONE bit has been set and the

ACQT2:ACQT0 bits are cleared. A conversion is

started after the following instruction to allow entry into

Sleep mode before the conversion begins.

Note:

The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

Figure 19-5 shows the operation of the A/D converter

after the GO/DONE bit has been set and the

ACQT2:ACQT0 bits are set to ‘010’ and selecting a

4 TAD acquisition time before the conversion starts.

19.7 Discharge

The discharge phase is used to initialize the value of

the capacitor array. The array is discharged before

every sample. This feature helps to optimize the unity-

gain amplifier, as the circuit always needs to charge the

capacitor array, rather than charge/discharge based on

previous measure values.

Clearing the GO/DONE bit during a conversion will abort

the current conversion. The A/D Result register pair will

NOT be updated with the partially completed A/D

conversion sample. This means the ADRESH:ADRESL

registers will continue to contain the value of the last

completed conversion (or the last value written to the

ADRESH:ADRESL registers).

FIGURE 19-4:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

TCY - TAD

TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD1

TAD1 TAD2 TAD3 TAD4 TAD5

b7

b6

b4

b1

b0

b9

b8

b5

b3

b2

Conversion starts

Discharge

Holding capacitor is disconnected from analog input (typically 100 ns)

Set GO/DONE bit

On the following cycle:

ADRESH:ADRESL is loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

FIGURE 19-5:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

TAD Cycles

TACQT Cycles

7

8

9

10

b1

11 TAD1

b0

1

2

3

4

1

2

3

4

5

6

b7

b6

b3

b2

b8

b5

b4

b9

Automatic

Acquisition

Time

Discharge

Conversion starts

(Holding capacitor is disconnected)

Set GO/DONE bit

(Holding capacitor continues

acquiring input)

On the following cycle:

ADRESH:ADRESL is loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

Preliminary

DS39689E-page 235

PIC18F4321 FAMILY

desired location). The appropriate analog input

channel must be selected and the minimum acquisition

period is either timed by the user, or an appropriate

TACQ time selected before the Special Event Trigger

sets the GO/DONE bit (starts a conversion).

19.8 Use of the CCP2 Trigger

An A/D conversion can be started by the Special Event

Trigger of the CCP2 module. This requires that the

CCP2M3:CCP2M0

bits

(CCP2CON<3:0>)

be

programmed as ‘1011’ and that the A/D module is

enabled (ADON bit is set). When the trigger occurs, the

GO/DONE bit will be set, starting the A/D acquisition

and conversion and the Timer1 (or Timer3) counter will

be reset to zero. Timer1 (or Timer3) is reset to automat-

ically repeat the A/D acquisition period with minimal

software overhead (moving ADRESH:ADRESL to the

If the A/D module is not enabled (ADON is cleared), the

Special Event Trigger will be ignored by the A/D

module but will still reset the Timer1 (or Timer3)

counter.

TABLE 19-2: REGISTERS ASSOCIATED WITH A/D OPERATION

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

PIE1

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

TXIF

TXIE

TXIP

EEIF

EEIE

EEIP

RBIE

SSPIF

SSPIE

SSPIP

BCLIF

BCLIE

BCLIP

TMR0IF

CCP1IF

CCP1IE

CCP1IP

HLVDIF

HLVDIE

HLVDIP

INT0IF

TMR2IF

TMR2IE

TMR2IP

TMR3IF

TMR3IE

TMR3IP

RBIF

49

52

51

52

PSPIF⁽¹⁾

PSPIE⁽¹⁾

PSPIP⁽¹⁾

OSCFIF

OSCFIE

OSCFIP

ADIF

ADIE

ADIP

CMIF

CMIE

CMIP

RCIF

RCIE

RCIP

—

TMR1IF

TMR1IE

TMR1IP

CCP2IF

CCP2IE

CCP2IP

IPR1

PIR2

PIE2

—

IPR2

—

ADRESH A/D Result Register High Byte

ADRESL A/D Result Register Low Byte

ADCON0

ADCON1

ADCON2

PORTA

TRISA

—

CHS3

VCFG1

ACQT2

RA5

CHS2

VCFG0

ACQT1

RA4

CHS1

PCFG3

ACQT0

RA3

CHS0 GO/DONE ADON

—

PCFG2

ADCS2

RA2

PCFG1

ADCS1

RA1

PCFG0

ADCS0

RA0

ADFM

RA7⁽²⁾

—

RA6⁽²⁾

TRISA7⁽²⁾TRISA6⁽²⁾PORTA Data Direction Control Register

PORTB

TRISB

RB7

PORTB Data Direction Control Register

PORTB Data Latch Register (Read and Write to Data Latch)

RB6

RB5

RB4

RB3

RB2

RB1

RB0

LATB

PORTE

TRISE⁽¹⁾

LATE⁽¹⁾

—

IBF

—

OBF

—

IBOV

—

PSPMODE

—

RE3⁽³⁾

RE2⁽¹⁾

RE1⁽¹⁾

RE0⁽¹⁾

—

TRISE2

TRISE1

TRISE0

—

PORTE Data Latch Register

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.

Note 1: These registers and/or bits are unimplemented on 28-pin devices and are read as ‘0’.

2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary

oscillator modes. When disabled, these bits read as ‘0’.

3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.

DS39689E-page 236

Preliminary

PIC18F4321 FAMILY

The CMCON register (Register 20-1) selects the

comparator input and output configuration. Block

diagrams of the various comparator configurations are

shown in Figure 20-1.

20.0 COMPARATOR MODULE

The analog comparator module contains two

comparators that can be configured in a variety of

ways. The inputs can be selected from the analog

inputs multiplexed with pins RA0 through RA5, as well

as the on-chip voltage reference (see Section 21.0

“Comparator Voltage Reference Module”). The digi-

tal outputs (normal or inverted) are available at the pin

level and can also be read through the control register.

REGISTER 20-1: CMCON: COMPARATOR CONTROL REGISTER

R-0

R/W-0

C2INV

R/W-0

C1INV

R/W-0

CIS

R/W-1

CM2

R/W-1

CM1

R/W-1

CM0

C2OUT

C1OUT

bit 7

bit 0

bit 7

C2OUT: Comparator 2 Output bit

When C2INV = 0:

1= C2 VIN+ > C2 VIN-

0= C2 VIN+ < C2 VIN-

When C2INV = 1:

1= C2 VIN+ < C2 VIN-

0= C2 VIN+ > C2 VIN-

bit 6

C1OUT: Comparator 1 Output bit

When C1INV = 0:

1= C1 VIN+ > C1 VIN-

0= C1 VIN+ < C1 VIN-

When C1INV = 1:

1= C1 VIN+ < C1 VIN-

0= C1 VIN+ > C1 VIN-

bit 5

bit 4

bit 3

C2INV: Comparator 2 Output Inversion bit

1= C2 output inverted

0= C2 output not inverted

C1INV: Comparator 1 Output Inversion bit

1= C1 output inverted

0= C1 output not inverted

CIS: Comparator Input Switch bit

When CM2:CM0 = 110:

1= C1 VIN- connects to RA3/AN3/VREF+

C2 VIN- connects to RA2/AN2/VREF-/CVREF

0= C1 VIN- connects to RA0/AN0

C2 VIN- connects to RA1/AN1

bit 2-0

CM2:CM0: Comparator Mode bits

Figure 20-1 shows the Comparator modes and the CM2:CM0 bit settings.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39689E-page 237

PIC18F4321 FAMILY

changed, the comparator output level may not be valid

for the specified mode change delay shown in

Section 26.0 “Electrical Characteristics”.

20.1 Comparator Configuration

There are eight modes of operation for the compara-

tors, shown in Figure 20-1. Bits CM2:CM0 of the

CMCON register are used to select these modes. The

TRISA register controls the data direction of the com-

parator pins for each mode. If the Comparator mode is

Note:

Comparator interrupts should be disabled

during Comparator mode change;

otherwise, a false interrupt may occur.

a

FIGURE 20-1:

COMPARATOR I/O OPERATING MODES

Comparators Reset

Comparators Off (POR Default Value)

CM2:CM0 = 000

CM2:CM0 = 111

A

D

VIN-

RA0/AN0

Off (Read as ‘0’)

C1

C2

C1

C2

VIN+

A

D

RA3/AN3/

VREF+

RA3/AN3/

VREF+

A

D

VIN-

RA1/AN1

VIN+

A

RA2/AN2/

VREF-/CVREF

RA2/AN2/

VREF-/CVREF

Two Independent Comparators

Two Independent Comparators with Outputs

CM2:CM0 = 010

CM2:CM0 = 011

A

VIN-

RA0/AN0

C1OUT

C2OUT

C1OUT

C2OUT

C1

C2

C1

C2

VIN+

RA3/AN3/

VREF+

VIN+

A

RA3/AN3/

VREF+

RA4/T0CKI/C1OUT*

A

VIN-

RA1/AN1

RA2/AN2/

A

VIN-

RA1/AN1

VIN+

RA2/AN2/

VREF-/CVREF

VIN+

VREF-/CVREF

RA5/AN4/SS/HLVDIN/C2OUT*

Two Common Reference Comparators

Two Common Reference Comparators with Outputs

CM2:CM0 = 100

CM2:CM0 = 101

A

VIN-

RA0/AN0

C1OUT

C2OUT

C1OUT

C1

C2

C1

VIN+

A

RA3/AN3/

VREF+

RA3/AN3/

VREF+

RA4/T0CKI/C1OUT*

A

D

VIN-

RA1/AN1

RA2/AN2/

A

VIN-

RA1/AN1

VIN+

C2OUT

RA2/AN2/

D

C2

VIN+

VREF-/CVREF

RA5/AN4/SS/HLVDIN/C2OUT*

Four Inputs Multiplexed to Two Comparators

One Independent Comparator with Output

CM2:CM0 = 110

CM2:CM0 = 001

A

VIN-

RA0/AN0

CIS = 0

CIS = 1

VIN-

A

C1OUT

C1

RA3/AN3/

VREF+

VIN+

RA3/AN3/

VREF+

C1OUT

C2OUT

C1

C2

VIN+

A

RA4/T0CKI/C1OUT*

RA1/AN1

VIN-

CIS = 0

CIS = 1

RA2/AN2/

VREF-/CVREF

VIN+

D

VIN-

RA1/AN1

RA2/AN2/

Off (Read as ‘0’)

C2

VIN+

CVREF

From VREF Module

VREF-/CVREF

A = Analog Input, port reads zeros always

D = Digital Input

CIS (CMCON<3>) is the Comparator Input Switch

* Setting the TRISA<5:4> bits will disable the comparator outputs by configuring the pins as inputs.

DS39689E-page 238

Preliminary

PIC18F4321 FAMILY

20.3.2

INTERNAL REFERENCE SIGNAL

20.2 Comparator Operation

The comparator module also allows the selection of an

internally generated voltage reference from the

comparator voltage reference module. This module is

described in more detail in Section 21.0 “Comparator

Voltage Reference Module”.

A single comparator is shown in Figure 20-2, along with

the relationship between the analog input levels and

the digital output. When the analog input at VIN+ is less

than the analog input VIN-, the output of the comparator

is a digital low level. When the analog input at VIN+ is

greater than the analog input VIN-, the output of the

comparator is a digital high level. The shaded areas of

the output of the comparator in Figure 20-2 represent

the uncertainty, due to input offsets and response time.

The internal reference is only available in the mode

where four inputs are multiplexed to two comparators

(CM2:CM0 = 110). In this mode, the internal voltage

reference is applied to the VIN+ pin of both

comparators.

20.3 Comparator Reference

20.4 Comparator Response Time

Depending on the comparator operating mode, either

an external or internal voltage reference may be used.

The analog signal present at VIN- is compared to the

signal at VIN+ and the digital output of the comparator

is adjusted accordingly (Figure 20-2).

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comparator output has a valid level. If the internal ref-

erence is changed, the maximum delay of the internal

voltage reference must be considered when using the

comparator outputs. Otherwise, the maximum delay of

the comparators should be used (see Section 26.0

“Electrical Characteristics”).

FIGURE 20-2:

SINGLE COMPARATOR

VIN+

VIN-

+

20.5 Comparator Outputs

Output

–

The comparator outputs are read through the CMCON

register. These bits are read-only. The comparator

outputs may also be directly output to the RA4 and RA5

I/O pins. When enabled, multiplexors in the output path

of the RA4 and RA5 pins will switch and the output of

each pin will be the unsynchronized output of the

comparator. The uncertainty of each of the

comparators is related to the input offset voltage and

the response time given in the specifications.

Figure 20-3 shows the comparator output block

diagram.

VIN-

VIN+

Output

The TRISA bits will still function as an output enable/

disable for the RA4 and RA5 pins while in this mode.

The polarity of the comparator outputs can be changed

using the C2INV and C1INV bits (CMCON<5:4>).

20.3.1

EXTERNAL REFERENCE SIGNAL

Note 1: When reading the Port register, all pins

configured as analog inputs will read as a

‘0’. Pins configured as digital inputs will

convert an analog input according to the

Schmitt Trigger input specification.

When external voltage references are used, the

comparator module can be configured to have the

comparators operate from the same or different

reference sources. However, threshold detector

applications may require the same reference. The

reference signal must be between VSS and VDD and

can be applied to either pin of the comparator(s).

2: Analog levels on any pin defined as a

digital input may cause the input buffer to

consume more current than is specified.

Preliminary

DS39689E-page 239

PIC18F4321 FAMILY

FIGURE 20-3:

COMPARATOR OUTPUT BLOCK DIAGRAM

Port pins

To RA4 or

RA5 pin

D

Q

Bus

Data

CxINV

EN

Read CMCON

D

Q

Set

CMIF

bit

EN

CL

From

other

Comparator

Reset

20.6 Comparator Interrupts

20.7 Comparator Operation

During Sleep

The comparator interrupt flag is set whenever there is

a change in the output value of either comparator.

Software will need to maintain information about the

status of the output bits, as read from CMCON<7:6>, to

determine the actual change that occurred. The CMIF

bit (PIR2<6>) is the Comparator Interrupt Flag. The

CMIF bit must be reset by clearing it. Since it is also

possible to write a ‘1’ to this register, a simulated

interrupt may be initiated.

When a comparator is active and the device is placed

in Sleep mode, the comparator remains active and the

interrupt is functional if enabled. This interrupt will

wake-up the device from Sleep mode, when enabled.

Each operational comparator will consume additional

current, as shown in the comparator specifications. To

minimize power consumption while in Sleep mode, turn

off the comparators (CM2:CM0 = 111) before entering

Sleep. If the device wakes up from Sleep, the contents

of the CMCON register are not affected.

Both the CMIE bit (PIE2<6>) and the PEIE bit

(INTCON<6>) must be set to enable the interrupt. In

addition, the GIE bit (INTCON<7>) must also be set. If

any of these bits are clear, the interrupt is not enabled,

though the CMIF bit will still be set if an interrupt

condition occurs.

20.8 Effects of a Reset

A device Reset forces the CMCON register to its Reset

state, causing the comparator modules to be turned off

(CM2:CM0 = 111). However, the input pins (RA0

through RA3) are configured as analog inputs by

default on device Reset. The I/O configuration for these

pins is determined by the setting of the PCFG3:PCFG0

bits (ADCON1<3:0>). Therefore, device current is

minimized when analog inputs are present at Reset

time.

Note:

If a change in the CMCON register

(C1OUT or C2OUT) should occur when a

read operation is being executed (start of

the Q2 cycle), then the CMIF (PIR2

register) interrupt flag may not get set.

The user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

a) Any read or write of CMCON will end the

mismatch condition.

b) Clear flag bit CMIF.

A mismatch condition will continue to set flag bit CMIF.

Reading CMCON will end the mismatch condition and

allow flag bit CMIF to be cleared.

DS39689E-page 240

Preliminary

PIC18F4321 FAMILY

range by more than 0.6V in either direction, one of the

diodes is forward biased and a latch-up condition may

occur. A maximum source impedance of 10 kΩ is

recommended for the analog sources. Any external

component connected to an analog input pin, such as

a capacitor or a Zener diode, should have very little

leakage current.

20.9 Analog Input Connection

Considerations

A simplified circuit for an analog input is shown in

Figure 20-4. Since the analog pins are connected to a

digital output, they have reverse biased diodes to VDD

and VSS. The analog input, therefore, must be between

VSS and VDD. If the input voltage deviates from this

FIGURE 20-4:

COMPARATOR ANALOG INPUT MODEL

VDD

VT = 0.6V

RIC

RS < 10k

AIN

Comparator

Input

ILEAKAGE

±500 nA

CPIN

5 pF

VA

VT = 0.6V

VSS

Legend: CPIN

=

Input Capacitance

Threshold Voltage

VT

ILEAKAGE = Leakage Current at the pin due to various junctions

RIC

RS

VA

=

Interconnect Resistance

Source Impedance

Analog Voltage

TABLE 20-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Reset

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Values

on page

CMCON

CVRCON

INTCON

PIR2

C2OUT

CVREN

C1OUT

CVROE

C2INV

CVRR

C1INV

CVRSS

INT0IE

EEIF

CIS

CM2

CM1

CVR1

INT0IF

CM0

CVR0

RBIF

51

52

CVR3

RBIE

BCLIF

BCLIE

BCLIP

RA3

CVR2

GIE/GIEH PEIE/GIEL TMR0IE

TMR0IF

HLVDIF

OSCFIF

OSCFIE

OSCFIP

RA7⁽¹⁾

CMIF

CMIE

CMIP

RA6⁽¹⁾

—

TMR3IF CCP2IF

PIE2

EEIE

HLVDIE TMR3IE CCP2IE

HLVDIP TMR3IP CCP2IP

IPR2

—

EEIP

PORTA

LATA

RA5

RA4

RA2

RA1

RA0

LATA7⁽¹⁾

LATA6⁽¹⁾PORTA Data Latch Register (Read and Write to Data Latch)

TRISA

TRISA7⁽¹⁾TRISA6⁽¹⁾PORTA Data Direction Control Register

Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.

Note 1: PORTA<7:6> and their direction and latch bits are individually configured as port pins based on various

primary oscillator modes. When disabled, these bits read as ‘0’.

Preliminary

DS39689E-page 241

PIC18F4321 FAMILY

NOTES:

DS39689E-page 242

Preliminary

PIC18F4321 FAMILY

used is selected by the CVRR bit (CVRCON<5>). The

primary difference between the ranges is the size of the

steps selected by the CVREF selection bits

(CVR3:CVR0), with one range offering finer resolution.

The equations used to calculate the output of the

comparator voltage reference are as follows:

21.0 COMPARATOR VOLTAGE

REFERENCE MODULE

The comparator voltage reference is a 16-tap resistor

ladder network that provides a selectable reference

voltage. Although its primary purpose is to provide a

reference for the analog comparators, it may also be

used independently of them.

If CVRR = 1:

CVREF = ((CVR3:CVR0)/24) x CVRSRC

A block diagram of the module is shown in Figure 21-1.

The resistor ladder is segmented to provide two ranges

of CVREF values and has a power-down function to

conserve power when the reference is not being used.

The module’s supply reference can be provided from

either device VDD/VSS or an external voltage reference.

If CVRR = 0:

CVREF = (CVRSRC x 1/4) + (((CVR3:CVR0)/32) x

CVRSRC)

The comparator reference supply voltage can come

from either VDD and VSS, or the external VREF+ and

VREF- that are multiplexed with RA2 and RA3. The

voltage source is selected by the CVRSS bit

(CVRCON<4>).

21.1 Configuring the Comparator

Voltage Reference

The settling time of the comparator voltage reference

must be considered when changing the CVREF

output (see Table 26-3 in Section 26.0 “Electrical

Characteristics”).

The voltage reference module is controlled through the

CVRCON register (Register 21-1). The comparator

voltage reference provides two ranges of output

voltage, each with 16 distinct levels. The range to be

REGISTER 21-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER

R/W-0

CVREN CVROE⁽¹⁾

bit 7

R/W-0

CVRR

R/W-0

CVR3

R/W-0

CVR2

R/W-0

CVR1

R/W-0

CVR0

CVRSS

bit 0

bit 7

bit 6

CVREN: Comparator Voltage Reference Enable bit

1= CVREF circuit powered on

0= CVREF circuit powered down

CVROE: Comparator VREF Output Enable bit⁽¹⁾

1= CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF pin

0= CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF pin

Note 1: CVROE overrides the TRISA<2> bit setting.

CVRR: Comparator VREF Range Selection bit

bit 5

1= 0.000 CVRSRC to 0.625 CVRSRC, with CVRSRC/24 step size (low range)

0= 0.250 CVRSRC to 0.719 CVRSRC, with CVRSRC/32 step size (high range)

bit 4

CVRSS: Comparator VREF Source Selection bit

1= Comparator reference source, CVRSRC = (VREF+) – (VREF-)

0= Comparator reference source, CVRSRC = VDD – VSS

bit 3-0

CVR3:CVR0: Comparator VREF Value Selection bits (0 ≤ (CVR3:CVR0) ≤ 15)

When CVRR = 1:

CVREF = ((CVR3:CVR0)/24) • (CVRSRC)

When CVRR = 0:

CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) • (CVRSRC)

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39689E-page 243

PIC18F4321 FAMILY

FIGURE 21-1:

COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

CVRSS = 1

CVRSS = 0

VREF+

VDD

8R

CVR3:CVR0

R

CVREN

R

16 Steps

CVREF

R

CVRR

VREF-

8R

CVRSS = 1

CVRSS = 0

21.2 Voltage Reference Accuracy/Error

21.4 Effects of a Reset

The full range of voltage reference cannot be realized

due to the construction of the module. The transistors

on the top and bottom of the resistor ladder network

(Figure 21-1) keep CVREF from approaching the

reference source rails. The voltage reference is derived

from the reference source; therefore, the CVREF output

changes with fluctuations in that source. The tested

absolute accuracy of the voltage reference can be

found in Section 26.0 “Electrical Characteristics”.

A device Reset disables the voltage reference by

clearing bit, CVREN (CVRCON<7>). This Reset also

disconnects the reference from the RA2 pin by clearing

bit, CVROE (CVRCON<6>) and selects the high-voltage

range by clearing bit, CVRR (CVRCON<5>). The CVR

value select bits are also cleared.

21.5 Connection Considerations

The voltage reference module operates independently

of the comparator module. The output of the reference

generator may be connected to the RA2 pin if the

CVROE bit is set. Enabling the voltage reference

output onto RA2 when it is configured as a digital input

will increase current consumption. Connecting RA2 as

a digital output with CVRSS enabled will also increase

current consumption.

21.3 Operation During Sleep

When the device wakes up from Sleep through an

interrupt or a Watchdog Timer time-out, the contents of

the CVRCON register are not affected. To minimize

current consumption in Sleep mode, the voltage

reference should be disabled.

The RA2 pin can be used as a simple D/A output with

limited drive capability. Due to the limited current drive

capability, a buffer must be used on the voltage

reference output for external connections to VREF.

Figure 21-2 shows an example buffering technique.

DS39689E-page 244

Preliminary

PIC18F4321 FAMILY

FIGURE 21-2:

COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

PIC18FXXXX

CVREF

Module

(1)

R

+

–

CVREF Output

RA2

Voltage

Reference

Output

Impedance

Note 1: R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>.

TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CVRCON

CMCON

TRISA

CVREN

C2OUT

CVROE

C1OUT

CVRR

C2INV

CVRSS

C1INV

CVR3

CIS

CVR2

CM2

CVR1

CM1

CVR0

CM0

51

52

TRISA7⁽¹⁾TRISA6⁽¹⁾PORTA Data Direction Control Register

Legend: Shaded cells are not used with the comparator voltage reference.

Note 1: PORTA pins are enabled based on oscillator configuration.

Preliminary

DS39689E-page 245

PIC18F4321 FAMILY

NOTES:

DS39689E-page 246

Preliminary

PIC18F4321 FAMILY

The High/Low-Voltage Detect Control register

(Register 22-1) completely controls the operation of the

HLVD module. This allows the circuitry to be “turned

off” by the user under software control, which

minimizes the current consumption for the device.

22.0 HIGH/LOW-VOLTAGE DETECT

(HLVD)

PIC18F4321 family devices have a High/Low-Voltage

Detect module (HLVD). This is a programmable circuit

that allows the user to specify both a device voltage trip

point and the direction of change from that point. If the

device experiences an excursion past the trip point in

that direction, an interrupt flag is set. If the interrupt is

enabled, the program execution will branch to the

interrupt vector address and the software can then

respond to the interrupt.

The block diagram for the HLVD module is shown in

Figure 22-1.

REGISTER 22-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER

R/W-0

VDIRMAG

bit 7

U-0

—

R-0

R/W-0

R/W-1

R/W-0

R/W-1

IRVST

HLVDEN HLVDL3

HLVDL2

HLVDL1

HLVDL0

bit 0

bit 7

VDIRMAG: Voltage Direction Magnitude Select bit

1= Event occurs when voltage equals or exceeds trip point (HLVDL3:HLDVL0)

0= Event occurs when voltage equals or falls below trip point (HLVDL3:HLVDL0)

bit 6

bit 5

Unimplemented: Read as ‘0’

IRVST: Internal Reference Voltage Stable Flag bit

1= Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage

range

0= Indicates that the voltage detect logic will not generate the interrupt flag at the specified

voltage range and the HLVD interrupt should not be enabled

bit 4

HLVDEN: High/Low-Voltage Detect Power Enable bit

1= HLVD enabled

0= HLVD disabled

bit 3-0

HLVDL3:HLVDL0: Voltage Detection Limit bits

1111= External analog input is used (input comes from the HLVDIN pin)

1110= Maximum setting

.

0000= Minimum setting

Note:

See Table 26-4 in Section 26.0 “Electrical Characteristics” for the specifications.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

The module is enabled by setting the HLVDEN bit.

Each time that the HLVD module is enabled, the

circuitry requires some time to stabilize. The IRVST bit

is a read-only bit and is used to indicate when the circuit

is stable. The module can only generate an interrupt

after the circuit is stable and IRVST is set.

The VDIRMAG bit determines the overall operation of

the module. When VDIRMAG is cleared, the module

monitors for drops in VDD below a predetermined set

point. When the bit is set, the module monitors for rises

in VDD above the set point.

Preliminary

DS39689E-page 247

PIC18F4321 FAMILY

The trip point voltage is software programmable to

any one of 16 values. The trip point is selected

22.1 Operation

When the HLVD module is enabled, a comparator uses

an internally generated reference voltage as the set

point. The set point is compared with the trip point,

where each node in the resistor divider represents a

trip point voltage. The “trip point” voltage is the voltage

level at which the device detects a high or low-voltage

event, depending on the configuration of the module.

When the supply voltage is equal to the trip point, the

voltage tapped off of the resistor array is equal to the

internal reference voltage generated by the voltage

reference module. The comparator then generates an

interrupt signal by setting the HLVDIF bit.

by programming

(HLVDCON<3:0>).

the

HLVDL3:HLVDL0

bits

The HLVD module has an additional feature that allows

the user to supply the trip voltage to the module from an

external source. This mode is enabled when bits

HLVDL3:HLVDL0 are set to ‘1111’. In this state, the

comparator input is multiplexed from the external input

pin, HLVDIN. This gives users flexibility because it

allows them to configure the High/Low-Voltage Detect

interrupt to occur at any voltage in the valid operating

range.

FIGURE 22-1:

HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT)

Externally Generated

Trip Point

VDD

HLVDL3:HLVDL0

HLVDCON

Register

HLVDIN

VDIRMAG

HLVDEN

HLVDIN

Set

HLVDIF

HLVDEN

BOREN

Internal Voltage

Reference

DS39689E-page 248

Preliminary

PIC18F4321 FAMILY

Depending on the application, the HLVD module does

not need to be operating constantly. To decrease the

current requirements, the HLVD circuitry may only

need to be enabled for short periods where the voltage

is checked. After doing the check, the HLVD module

may be disabled.

22.2 HLVD Setup

The following steps are needed to set up the HLVD

module:

1. Disable the module by clearing the HLVDEN bit

(HLVDCON<4>).

2. Write the value to the HLVDL3:HLVDL0 bits that

selects the desired HLVD trip point.

22.4 HLVD Start-up Time

3. Set the VDIRMAG bit to detect high voltage

The internal reference voltage of the HLVD module,

specified in electrical specification parameter D420,

may be used by other internal circuitry, such as the

Programmable Brown-out Reset. If the HLVD or other

circuits using the voltage reference are disabled to

lower the device’s current consumption, the reference

voltage circuit will require time to become stable before

a low or high-voltage condition can be reliably

detected. This start-up time, TIRVST, is an interval that

is independent of device clock speed. It is specified in

electrical specification parameter 36.

(VDIRMAG = 1) or low voltage (VDIRMAG = 0).

4. Enable the HLVD module by setting the

HLVDEN bit.

5. Clear the HLVD interrupt flag (PIR2<2>), which

may have been set from a previous interrupt.

6. Enable the HLVD interrupt if interrupts are

desired by setting the HLVDIE and GIE bits

(PIE<2> and INTCON<7>). An interrupt will not

be generated until the IRVST bit is set.

The HLVD interrupt flag is not enabled until TIRVST has

expired and a stable reference voltage is reached. For

this reason, brief excursions beyond the set point may

not be detected during this interval. Refer to

Figure 22-2 or Figure 22-3.

22.3 Current Consumption

When the module is enabled, the HLVD comparator

and voltage divider are enabled and will consume static

current. The total current consumption, when enabled,

is specified in electrical specification parameter D022B.

FIGURE 22-2:

LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0)

CASE 1:

HLVDIF may not be set

VDD

VLVD

HLVDIF

Enable HLVD

IRVST

TIRVST

HLVDIF cleared in software

Internal Reference is stable

CASE 2:

VDD

VLVD

HLVDIF

Enable HLVD

TIRVST

IRVST

Internal Reference is stable

HLVDIF cleared in software

HLVDIF cleared in software,

HLVDIF remains set since HLVD condition still exists

Preliminary

DS39689E-page 249

PIC18F4321 FAMILY

FIGURE 22-3:

HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1)

CASE 1:

HLVDIF may not be set

VLVD

VDD

HLVDIF

Enable HLVD

IRVST

TIRVST

HLVDIF cleared in software

Internal Reference is stable

CASE 2:

VLVD

VDD

HLVDIF

Enable HLVD

TIRVST

IRVST

Internal Reference is stable

HLVDIF cleared in software

HLVDIF cleared in software,

HLVDIF remains set since HLVD condition still exists

FIGURE 22-4:

TYPICAL LOW-VOLTAGE

DETECT APPLICATION

22.5 Applications

In many applications, the ability to detect a drop below

or rise above a particular threshold is desirable. For

example, the HLVD module could be periodically

enabled to detect a Universal Serial Bus (USB) attach

or detach. This assumes the device is powered by a

lower voltage source than the USB when detached. An

attach would indicate a high-voltage detect from, for

example, 3.3V to 5V (the voltage on USB) and vice

versa for a detach. This feature could save a design a

few extra components and an attach signal (input pin).

VA

VB

For general battery applications, Figure 22-4 shows a

possible voltage curve. Over time, the device voltage

decreases. When the device voltage reaches voltage

VA, the HLVD logic generates an interrupt at time TA.

The interrupt could cause the execution of an ISR,

which would allow the application to perform “house-

keeping tasks” and perform a controlled shutdown

before the device voltage exits the valid operating

range at TB. The HLVD, thus, would give the applica-

tion a time window, represented by the difference

between TA and TB, to safely exit.

TB

VA = HLVD trip point

VB = Minimum valid device

operating voltage

TA

Time

Legend:

DS39689E-page 250

Preliminary

PIC18F4321 FAMILY

22.6 Operation During Sleep

22.7 Effects of a Reset

When enabled, the HLVD circuitry continues to operate

during Sleep. If the device voltage crosses the trip

point, the HLVDIF bit will be set and the device will

wake-up from Sleep. Device execution will continue

from the interrupt vector address if interrupts have

been globally enabled.

A device Reset forces all registers to their Reset state.

This forces the HLVD module to be turned off.

TABLE 22-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE

Reset

Values

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

HLVDCON VDIRMAG

—

IRVST

HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0

50

49

52

INTCON

PIR2

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

EEIF

RBIE

BCLIF

BCLIE

BCLIP

TMR0IF

HLVDIF

INT0IF

RBIF

OSCFIF

OSCFIE

OSCFIP

CMIF

CMIE

CMIP

—

TMR3IF CCP2IF

PIE2

EEIE

EEIP

HLVDIE TMR3IE CCP2IE

HLVDIP TMR3IP CCP2IP

IPR2

Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module.

Preliminary

DS39689E-page 251

PIC18F4321 FAMILY

NOTES:

DS39689E-page 252

Preliminary

PIC18F4321 FAMILY

The inclusion of an internal RC oscillator also provides

the additional benefits of a Fail-Safe Clock Monitor

(FSCM) and Two-Speed Start-up. FSCM provides for

background monitoring of the peripheral clock and

automatic switchover in the event of its failure. Two-

Speed Start-up enables code to be executed almost

immediately on start-up, while the primary clock source

completes its start-up delays.

23.0 SPECIAL FEATURES OF THE

CPU

PIC18F4321 family devices include several features

intended to maximize reliability and minimize cost

through elimination of external components. These are:

• Oscillator Selection

• Resets:

All of these features are enabled and configured by

setting the appropriate Configuration register bits.

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

23.1 Configuration Bits

The Configuration bits can be programmed (read as

‘0’) or left unprogrammed (read as ‘1’) to select various

device configurations. These bits are mapped starting

at program memory location 300000h.

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor

• Two-Speed Start-up

• Code Protection

The user will note that address 300000h is beyond the

user program memory space. In fact, it belongs to the

configuration memory space (300000h-3FFFFFh), which

can only be accessed using table reads and table writes.

• ID Locations

• In-Circuit Serial Programming

Programming the Configuration registers is done in a

manner similar to programming the Flash memory. The

WR bit in the EECON1 register starts a self-timed write

to the Configuration register. In normal operation mode,

a TBLWT instruction with the TBLPTR pointing to the

Configuration register sets up the address and the data

for the Configuration register write. Setting the WR bit

starts a long write to the Configuration register. The

Configuration registers are written a byte at a time. To

write or erase a configuration cell, a TBLWTinstruction

can write a ‘1’ or a ‘0’ into the cell. For additional details

on Flash programming, refer to Section 6.5 “Writing

to Flash Program Memory”.

The oscillator can be configured for the application

depending on frequency, power, accuracy and cost. All

of the options are discussed in detail in Section 2.0

“Oscillator Configurations”.

A complete discussion of device Resets and interrupts

is available in previous sections of this data sheet.

In addition to their Power-up and Oscillator Start-up

Timers provided for Resets, PIC18F4321 family

devices have a Watchdog Timer, which is either perma-

nently enabled via the Configuration bits or software

controlled (if configured as disabled).

TABLE 23-1: CONFIGURATION BITS AND DEVICE IDs

Default/

Unprogrammed

Value

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

300001h CONFIG1H

300002h CONFIG2L

300003h CONFIG2H

IESO

—

FCMEN

—

FOSC3

FOSC2

FOSC1

FOSC0

00-- 0111

---1 1111

1--- -011

1000 -1-1

---- --11

11-- ----

---- --11

111- ----

---- --11

-1-- ----

—

BORV1

BORV0 BOREN1 BOREN0 PWRTEN

—

WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN

300005h CONFIG3H MCLRE

—

ICPORT

—

LPT1OSC PBADEN CCP2MX

300006h CONFIG4L DEBUG XINST BBSIZ1 BBSIZ0

LVP

—

CP1

—

STVREN

CP0

300008h CONFIG5L

300009h CONFIG5H

30000Ah CONFIG6L

—

CPD

—

CPB

—

WRT1

—

WRT0

—

30000Bh CONFIG6H WRTD

WRTB

—

WRTC

—

30000Ch CONFIG7L

30000Dh CONFIG7H

—

EBTR1

—

EBTR0

—

EBTRB

DEV1

DEV9

—

(1)

(2)

3FFFFEh DEVID1

DEV2

DEV10

DEV0

DEV8

REV4

DEV7

REV3

DEV6

REV2

DEV5

REV1

DEV4

REV0

DEV3

xxxx xxxx

(1)

3FFFFFh DEVID2

0000 1100

Legend:

x= unknown, u= unchanged, -= unimplemented, q= value depends on condition.

Shaded cells are unimplemented, read as ‘0’.

Note 1: Unimplemented in PIC18F2221/4221 devices; maintain these bits set.

2: See Register 23-14 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.

Preliminary

DS39689E-page 253

PIC18F4321 FAMILY

REGISTER 23-1: CONFIG1H:CONFIGURATIONREGISTER1HIGH(BYTEADDRESS300001h)

R/P-0

IESO

R/P-0

U-0

—

U-0

—

R/P-0

R/P-1

FCMEN

FOSC3

FOSC2

FOSC1

FOSC0

bit 7

bit 0

bit 7

bit 6

IESO: Internal/External Oscillator Switchover bit

1= Oscillator Switchover mode enabled

0= Oscillator Switchover mode disabled

FCMEN: Fail-Safe Clock Monitor Enable bit

1= Fail-Safe Clock Monitor enabled

0= Fail-Safe Clock Monitor disabled

bit 5-4 Unimplemented: Read as ‘0’

bit 3-0 FOSC3:FOSC0: Oscillator Selection bits

11xx= External RC oscillator, CLKO function on RA6

101x= External RC oscillator, CLKO function on RA6

1001= Internal oscillator block, CLKO function on RA6, port function on RA7

1000= Internal oscillator block, port function on RA6 and RA7

0111= External RC oscillator, port function on RA6

0110= HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)

0101= EC oscillator, port function on RA6

0100= EC oscillator, CLKO function on RA6

0011= External RC oscillator, CLKO function on RA6

0010= HS oscillator

0001= XT oscillator

0000= LP oscillator

Legend:

R = Readable bit

P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed

u = Unchanged from programmed state

DS39689E-page 254

Preliminary

PIC18F4321 FAMILY

REGISTER 23-2: CONFIG2L:CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS300002h)

U-0

—

U-0

—

U-0

—

R/P-1

BORV1⁽¹⁾BORV0⁽¹⁾BOREN1⁽²⁾BOREN0⁽²⁾PWRTEN⁽²⁾

bit 7

bit 0

bit 7-5 Unimplemented: Read as ‘0’

bit 4-3 BORV1:BORV0: Brown-out Reset Voltage bits⁽¹⁾

11= Minimum setting

.

00= Maximum setting

bit 2-1 BOREN1:BOREN0: Brown-out Reset Enable bits⁽²⁾

11= Brown-out Reset enabled in hardware only (SBOREN is disabled)

10= Brown-out Reset enabled in hardware only and disabled in Sleep mode

(SBOREN is disabled)

01= Brown-out Reset enabled and controlled by software (SBOREN is enabled)

00= Brown-out Reset disabled in hardware and software

bit 0

PWRTEN: Power-up Timer Enable bit⁽²⁾

1= PWRT disabled

0= PWRT enabled

Note 1: See Section 26.1 “DC Characteristics” for the specifications.

2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to

be independently controlled.

Legend:

R = Readable bit

P = Programmable bit U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

-n = Value when device is unprogrammed

Preliminary

DS39689E-page 255

PIC18F4321 FAMILY

REGISTER 23-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)

U-0

—

U-0

—

U-0

—

R/P-1

WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN

bit 0

bit 7

bit 7-5

bit 4-1

Unimplemented: Read as ‘0’

WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits

1111= 1:32,768

1110= 1:16,384

1101= 1:8,192

1100= 1:4,096

1011= 1:2,048

1010= 1:1,024

1001= 1:512

1000= 1:256

0111= 1:128

0110= 1:64

0101= 1:32

0100= 1:16

0011= 1:8

0010= 1:4

0001= 1:2

0000= 1:1

bit 0

WDTEN: Watchdog Timer Enable bit

1= WDT enabled

0= WDT disabled (control is placed on the SWDTEN bit)

Legend:

R = Readable bit

P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed

u = Unchanged from programmed state

DS39689E-page 256

Preliminary

PIC18F4321 FAMILY

REGISTER 23-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)

R/P-1

U-0

—

U-0

—

U-0

—

U-0

—

R/P-0

R/P-1

MCLRE

LPT1OSC PBADEN CCP2MX

bit 0

bit 7

MCLRE: MCLR Pin Enable bit

1= MCLR pin enabled; RE3 input pin disabled

0= RE3 input pin enabled; MCLR disabled

bit 6-3 Unimplemented: Read as ‘0’

bit 2

LPT1OSC: Low-Power Timer1 Oscillator Enable bit

1= Timer1 configured for low-power operation

0= Timer1 configured for higher power operation

bit 1

PBADEN: PORTB A/D Enable bit

(Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.)

1= PORTB<4:0> pins are configured as analog input channels on Reset

0= PORTB<4:0> pins are configured as digital I/O on Reset

bit 0

CCP2MX: CCP2 Mux bit

1= CCP2 input/output is multiplexed with RC1

0= CCP2 input/output is multiplexed with RB3

Legend:

R = Readable bit

P = Programmable bit U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

-n = Value when device is unprogrammed

Preliminary

DS39689E-page 257

PIC18F4321 FAMILY

REGISTER 23-5: CONFIG4L:CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS300006h)

R/P-1

R/P-0

U-0

R/P-1

LVP

U-0

—

R/P-1

STVREN

bit 0

DEBUG

XINST

BBSIZ1

BBSIZ0 ICPORT⁽¹⁾

bit 7

bit 6

DEBUG: Background Debugger Enable bit

1= Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins

0= Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug

XINST: Extended Instruction Set Enable bit

1= Instruction set extension and Indexed Addressing mode enabled

0= Instruction set extension and Indexed Addressing mode disabled (Legacy mode)

bit 5-4 BBSIZ1:BBSIZ0: Boot Block Size Select bits

PIC18F4221/4321 Devices:

1x= 1024 Words

01= 512 Words

00= 256 Words

PIC18F2221/2321 Devices:

1x= 512 Words

x1= 512 Words

00= 256 Words

bit 3

bit 2

ICPORT: Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit⁽¹⁾

1= ICPORT enabled

0= ICPORT disabled

LVP: Single-Supply ICSP™ Enable bit

1= Single-Supply ICSP enabled

0= Single-Supply ICSP disabled

bit 1

bit 0

Unimplemented: Read as ‘0’

STVREN: Stack Full/Underflow Reset Enable bit

1= Stack full/underflow will cause Reset

0= Stack full/underflow will not cause Reset

Note 1: Available only on PIC18F4221/4321 devices in 44-pin TQFP packages. Always

leave this bit clear in all other devices.

Legend:

R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed

u = Unchanged from programmed state

DS39689E-page 258

Preliminary

PIC18F4321 FAMILY

REGISTER 23-6: CONFIG5L:CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS300008h)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/C-1

CP1

R/C-1

CP0

bit 7

bit 0

bit 7-2 Unimplemented: Read as ‘0’

bit 1

CP1: Code Protection bit

1= Block 1 not code-protected⁽¹⁾

0= Block 1 code-protected⁽¹⁾

bit 0

CP0: Code Protection bit

1= Block 0 not code-protected⁽¹⁾

0= Block 0 code-protected⁽¹⁾

Note 1: See Figure 23-5 for variable block boundaries.

Legend:

R = Readable bit

-n = Value when device is unprogrammed

C = Clearable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

REGISTER 23-7: CONFIG5H:CONFIGURATIONREGISTER5HIGH(BYTEADDRESS300009h)

R/C-1

CPD

R/C-1

CPB

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

bit 7

bit 6

CPD: Data EEPROM Code Protection bit

1= Data EEPROM not code-protected

0= Data EEPROM code-protected

CPB: Boot Block Code Protection bit

1= Boot block not code-protected⁽¹⁾

0= Boot block code-protected⁽¹⁾

bit 5-0 Unimplemented: Read as ‘0’

Note 1: See Figure 23-5 for variable block boundaries.

Legend:

R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

-n = Value when device is unprogrammed

Preliminary

DS39689E-page 259

PIC18F4321 FAMILY

REGISTER 23-8: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/C-1

WRT1

R/C-1

WRT0

bit 7

bit 0

bit 7-2 Unimplemented: Read as ‘0’

bit 1

WRT1: Write Protection bit

1= Block 1 not write-protected⁽¹⁾

0= Block 1 write-protected⁽¹⁾

bit 0

WRT0: Write Protection bit

1= Block 0 not write-protected⁽¹⁾

0= Block 0 write-protected⁽¹⁾

Note 1: See Figure 23-5 for variable block boundaries.

Legend:

R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

-n = Value when device is unprogrammed

REGISTER 23-9: CONFIG6H:CONFIGURATION REGISTER6 HIGH(BYTEADDRESS30000Bh)

R/C-1

R-1

WRTC⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

WRTD

WRTB

—

bit 7

bit 0

bit 7

bit 6

bit 5

WRTD: Data EEPROM Write Protection bit

1= Data EEPROM not write-protected

0= Data EEPROM write-protected

WRTB: Boot Block Write Protection bit

1= Boot block not write-protected⁽²⁾

0= Boot block write-protected⁽²⁾

WRTC: Configuration Register Write Protection bit⁽¹⁾

1= Configuration registers (300000-3000FFh) not write-protected

0= Configuration registers (300000-3000FFh) write-protected

bit 4-0 Unimplemented: Read as ‘0’

Note 1: This bit is read-only in normal execution mode; it can be written only in Program mode.

2: See Figure 23-5 for block boundaries.

Legend:

R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed

u = Unchanged from programmed state

DS39689E-page 260

Preliminary

PIC18F4321 FAMILY

REGISTER 23-10: CONFIG7L:CONFIGURATIONREGISTER7LOW(BYTEADDRESS30000Ch)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/C-1

EBTR1

EBTR0

bit 7

bit 0

bit 7-2 Unimplemented: Read as ‘0’

bit 1

EBTR1: Table Read Protection bit

1= Block 1 not protected from table reads executed in other blocks⁽¹⁾

0= Block 1 protected from table reads executed in other blocks⁽¹⁾

bit 0

EBTR0: Table Read Protection bit

1= Block 0 not protected from table reads executed in other blocks⁽¹⁾

0= Block 0 protected from table reads executed in other blocks⁽¹⁾

Note 1: See Figure 23-5 for variable block boundaries.

Legend:

R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

-n = Value when device is unprogrammed

REGISTER 23-11: CONFIG7H:CONFIGURATION REGISTER7 HIGH(BYTEADDRESS30000Dh)

U-0

—

R/C-1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

EBTRB

—

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as ‘0’

EBTRB: Boot Block Table Read Protection bit

1= Boot block not protected from table reads executed in other blocks⁽¹⁾

0= Boot block protected from table reads executed in other blocks⁽¹⁾

bit 5-0 Unimplemented: Read as ‘0’

Note 1: See Figure 23-5 for variable block boundaries.

Legend:

R = Readable bit

C = Clearable bit

U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed

u = Unchanged from programmed state

Preliminary

DS39689E-page 261

PIC18F4321 FAMILY

REGISTER 23-12: DEVID1:DEVICE ID REGISTER 1 FOR PIC18F2221/2321/4221/4321 DEVICES

R

DEV2

DEV1

DEV0

REV4

REV3

REV2

REV1

REV0

bit 7

bit 0

bit 7-5 DEV2:DEV0: Device ID bits

000= PIC18F4321

010= PIC18F4221

001= PIC18F2321

011= PIC18F2221

bit 4-0 REV4:REV0: Revision ID bits

These bits are used to indicate the device revision.

Legend:

R = Read-only bit

P = Programmable bit U = Unimplemented bit, read as ‘0’

u = Unchanged from programmed state

-n = Value when device is unprogrammed

REGISTER 23-13: DEVID2:DEVICE ID REGISTER 2 FOR PIC18F2221/2321/4221/4321 DEVICES

R

DEV10

DEV9

DEV8

DEV7

DEV6

DEV5

DEV4

DEV3

bit 0

bit 7

bit 7-0 DEV10:DEV3: Device ID bits

These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the

part number.

0010 0001= PIC18F2221/2321/4221/4321 devices

Note:

These values for DEV10:DEV3 may be shared with other devices. The specific

device is always identified by using the entire DEV10:DEV0 bit sequence.

Legend:

R = Read-only bit

P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed

u = Unchanged from programmed state

DS39689E-page 262

Preliminary

PIC18F4321 FAMILY

23.2 Watchdog Timer (WDT)

Note 1: The CLRWDT and SLEEP instructions

clear the WDT and postscaler counts

when executed.

For PIC18F4321 family devices, the WDT is driven by

the INTRC source. When the WDT is enabled, the

clock source is also enabled. The nominal WDT period

is 4 ms and has the same stability as the INTRC

oscillator.

2: Changing the setting of the IRCF bits

(OSCCON<6:4>) clears the WDT and

postscaler counts.

The 4 ms period of the WDT is multiplied by a 16-bit

postscaler. Any output of the WDT postscaler is

selected by a multiplexer, controlled by bits in Configu-

ration Register 2H. Available periods range from 4 ms

to 131.072 seconds (2.18 minutes). The WDT and

postscaler are cleared when any of the following events

occur: a SLEEPor CLRWDTinstruction is executed, the

IRCF bits (OSCCON<6:4>) are changed or a clock

failure has occurred.

3: When a CLRWDTinstruction is executed,

the postscaler count will be cleared.

23.2.1

CONTROL REGISTER

Register 23-14 shows the WDTCON register. This is a

readable and writable register which contains a control

bit that allows software to override the WDT enable

Configuration bit, but only if the Configuration bit has

disabled the WDT.

FIGURE 23-1:

WDT BLOCK DIAGRAM

Enable WDT

SWDTEN

WDTEN

WDT Counter

Wake-up from

Power-Managed

Modes

÷128

INTRC Source

Change on IRCF bits

CLRWDT

WDT

Reset

Programmable Postscaler

1:1 to 1:32,768

All Device Resets

4

WDTPS<3:0>

Sleep

Preliminary

DS39689E-page 263

PIC18F4321 FAMILY

REGISTER 23-14: WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

SWDTEN⁽¹⁾

bit 0

bit 7

bit 7-1 Unimplemented: Read as ‘0’

bit 0

SWDTEN: Software Controlled Watchdog Timer Enable bit⁽¹⁾

1= Watchdog Timer is on

0= Watchdog Timer is off

Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.

Legend:

R = Readable bit

U = Unimplemented bit, read as ‘0’

W = Writable bit

-n = Value at POR

TABLE 23-2: SUMMARY OF WATCHDOG TIMER REGISTERS

Reset

Values

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RCON

WDTCON

IPEN

—

SBOREN⁽¹⁾

—

RI

—

TO

—

PD

—

POR

—

BOR

50

SWDTEN

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.

Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is

disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.

DS39689E-page 264

Preliminary

PIC18F4321 FAMILY

In all other power-managed modes, Two-Speed Start-

up is not used. The device will be clocked by the

currently selected clock source until the primary clock

source becomes available. The setting of the IESO bit

is ignored.

23.3 Two-Speed Start-up

The Two-Speed Start-up feature helps to minimize the

latency period from oscillator start-up to code execution

by allowing the microcontroller to use the INTOSC

oscillator as a clock source until the primary clock

source is available. It is enabled by setting the IESO

Configuration bit.

23.3.1

SPECIAL CONSIDERATIONS FOR

USING TWO-SPEED START-UP

Two-Speed Start-up should be enabled only if the

primary oscillator mode is LP, XT, HS or HSPLL

(crystal-based modes). Other sources do not require

an OST start-up delay; for these, Two-Speed Start-up

should be disabled.

While using the INTOSC oscillator in Two-Speed Start-

up, the device still obeys the normal command

sequences for entering power-managed modes,

including multiple SLEEP instructions (refer to

Section 3.1.4 “Multiple Sleep Commands”). In

practice, this means that user code can change the

SCS1:SCS0 bit settings or issue SLEEP instructions

before the OST times out. This would allow an applica-

tion to briefly wake-up, perform routine “housekeeping”

tasks and return to Sleep before the device starts to

operate from the primary oscillator.

When enabled, Resets and wake-ups from Sleep mode

cause the device to configure itself to run from the

internal oscillator block as the clock source, following

the time-out of the Power-up Timer after a Power-on

Reset is enabled. This allows almost immediate code

execution while the primary oscillator starts and the

OST is running. Once the OST times out, the device

automatically switches to PRI_RUN mode.

User code can also check if the primary clock source is

currently providing the device clocking by checking the

status of the OSTS bit (OSCCON<3>). If the bit is set,

the primary oscillator is providing the clock. Otherwise,

the internal oscillator block is providing the clock during

wake-up from Reset or Sleep mode.

To use a higher clock speed on wake-up, the INTOSC

or postscaler clock sources can be selected to provide

a higher clock speed by setting bits, IRCF2:IRCF0,

immediately after Reset. For wake-ups from Sleep, the

INTOSC or postscaler clock sources can be selected

by setting the IRCF2:IRCF0 bits prior to entering Sleep

mode.

FIGURE 23-2:

TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)

Q3

Q4

Q1

Q2 Q3 Q4 Q1 Q2 Q3

Q1

Q2

INTOSC

Multiplexer

OSC1

(1)

TPLL

TOST

1

2

n-1

n

PLL Clock

Output

Clock

Transition⁽²⁾

CPU Clock

Peripheral

Clock

Program

Counter

PC + 4

PC + 6

PC

PC + 2

Wake from Interrupt Event

OSTS bit Set

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

2: Clock transition typically occurs within 2-4 TOSC.

Preliminary

DS39689E-page 265

PIC18F4321 FAMILY

To use a higher clock speed on wake-up, the INTOSC

or postscaler clock sources can be selected to provide

a higher clock speed by setting bits, IRCF2:IRCF0,

immediately after Reset. For wake-ups from Sleep, the

INTOSC or postscaler clock sources can be selected

by setting the IRCF2:IRCF0 bits prior to entering Sleep

mode.

23.4 Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the

microcontroller to continue operation in the event of an

external oscillator failure by automatically switching the

device clock to the internal oscillator block. The FSCM

function is enabled by setting the FCMEN Configuration

bit.

The FSCM will detect failures of the primary or second-

ary clock sources only. If the internal oscillator block

fails, no failure would be detected, nor would any action

be possible.

When FSCM is enabled, the INTRC oscillator runs at

all times to monitor clocks to peripherals and provide a

backup clock in the event of a clock failure. Clock

monitoring (shown in Figure 23-3) is accomplished by

creating a sample clock signal, which is the INTRC

output divided by 64. This allows ample time between

FSCM sample clocks for a peripheral clock edge to

occur. The peripheral device clock and the sample

clock are presented as inputs to the Clock Monitor latch

(CM). The CM is set on the falling edge of the device

clock source, but cleared on the rising edge of the

sample clock.

23.4.1

FSCM AND THE WATCHDOG TIMER

Both the FSCM and the WDT are clocked by the

INTRC oscillator. Since the WDT operates with a

separate divider and counter, disabling the WDT has

no effect on the operation of the INTRC oscillator when

the FSCM is enabled.

As already noted, the clock source is switched to the

INTOSC clock when a clock failure is detected.

Depending on the frequency selected by the

IRCF2:IRCF0 bits, this may mean a substantial change

in the speed of code execution. If the WDT is enabled

with a small prescale value, a decrease in clock speed

allows a WDT time-out to occur and a subsequent

device Reset. For this reason, fail-safe clock events

also reset the WDT and postscaler, allowing it to start

timing from when execution speed was changed and

decreasing the likelihood of an erroneous time-out.

FIGURE 23-3:

FSCM BLOCK DIAGRAM

Clock Monitor

Latch (CM)

(edge-triggered)

Peripheral

Clock

S

Q

INTRC

Source

C

÷ 64

23.4.2

EXITING FAIL-SAFE OPERATION

(32 μs)

488 Hz

(2.048 ms)

The fail-safe condition is terminated by either a device

Reset or by entering a power-managed mode. On

Reset, the controller starts the primary clock source

specified in Configuration Register 1H (with any

required start-up delays that are required for the

oscillator mode, such as OST or PLL timer). The

INTOSC multiplexer provides the device clock until the

primary clock source becomes ready (similar to a Two-

Speed Start-up). The clock source is then switched to

the primary clock (indicated by the OSTS bit in the

OSCCON register becoming set). The Fail-Safe Clock

Monitor then resumes monitoring the peripheral clock.

Clock

Failure

Detected

Clock failure is tested for on the falling edge of the

sample clock. If a sample clock falling edge occurs

while CM is still set, a clock failure has been detected

(Figure 23-4). This causes the following:

• the FSCM generates an oscillator fail interrupt by

setting bit, OSCFIF (PIR2<7>);

• the device clock source is switched to the internal

oscillator block (OSCCON is not updated to show

the current clock source – this is the fail-safe

condition); and

The primary clock source may never become ready

during start-up. In this case, operation is clocked by the

INTOSC multiplexer. The OSCCON register will remain

in its Reset state until a power-managed mode is

entered.

• the WDT is reset.

During switchover, the postscaler frequency from the

internal oscillator block may not be sufficiently stable

for timing sensitive applications. In these cases, it may

be desirable to select another clock configuration and

enter an alternate power-managed mode. This can be

done to attempt a partial recovery or execute a

controlled shutdown. See Section 3.1.4 “Multiple

Sleep Commands” and Section 23.3.1 “Special

Considerations for Using Two-Speed Start-up” for

more details.

DS39689E-page 266

Preliminary

PIC18F4321 FAMILY

FIGURE 23-4:

FSCM TIMING DIAGRAM

Sample Clock

Oscillator

Failure

Device

Clock

Output

CM Output

(Q)

Failure

Detected

OSCFIF

CM Test

Note:

The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this

example have been chosen for clarity.

23.4.3

FSCM INTERRUPTS IN

23.4.4

POR OR WAKE FROM SLEEP

POWER-MANAGED MODES

The FSCM is designed to detect oscillator failure at any

point after the device has exited Power-on Reset

(POR) or low-power Sleep mode. When the primary

device clock is EC, RC or INTRC modes, monitoring

can begin immediately following these events.

By entering a power-managed mode, the clock

multiplexer selects the clock source selected by the

OSCCON register. Fail-Safe Monitoring of the power-

managed clock source resumes in the power-managed

mode.

For oscillator modes involving a crystal or resonator

(HS, HSPLL, LP or XT), the situation is somewhat

different. Since the oscillator may require a start-up

time considerably longer than the FCSM sample clock

time, a false clock failure may be detected. To prevent

this, the internal oscillator block is automatically config-

ured as the device clock and functions until the primary

clock is stable (the OST and PLL timers have timed

out). This is identical to Two-Speed Start-up mode.

Once the primary clock is stable, the INTRC returns to

its role as the FSCM source.

If an oscillator failure occurs during power-managed

operation, the subsequent events depend on whether

or not the oscillator failure interrupt is enabled. If

enabled (OSCFIF = 1), code execution will be clocked

by the INTOSC multiplexer. An automatic transition

back to the failed clock source will not occur.

If the interrupt is disabled, subsequent interrupts while

in Idle mode will cause the CPU to begin executing

instructions while being clocked by the INTOSC

source.

Note:

The same logic that prevents false oscilla-

tor failure interrupts on POR, or wake from

Sleep, will also prevent the detection of

the oscillator’s failure to start at all follow-

ing these events. This can be avoided by

monitoring the OSTS bit and using a

timing routine to determine if the oscillator

is taking too long to start. Even so, no

oscillator failure interrupt will be flagged.

As noted in Section 23.3.1 “Special Considerations

for Using Two-Speed Start-up”, it is also possible to

select another clock configuration and enter an

alternate power-managed mode while waiting for the

primary clock to become stable. When the new power-

managed mode is selected, the primary clock is

disabled.

Preliminary

DS39689E-page 267

PIC18F4321 FAMILY

Each of the three blocks has three code protection bits

associated with them. They are:

23.5 Program Verification and

Code Protection

• Code-Protect bit (CPn)

The overall structure of the code protection on the

PIC18 Flash devices differs significantly from other

PIC^®devices.

• Write-Protect bit (WRTn)

• External Block Table Read bit (EBTRn)

Figure 23-5 shows the program memory organization

for 4 and 8-Kbyte devices and the specific code

protection bit associated with each block. The actual

locations of the bits are summarized in Table 23-3.

The user program memory is divided into three blocks.

One of these is a boot block of variable size. The

remainder of the memory is divided into two blocks on

binary boundaries.

FIGURE 23-5:

CODE-PROTECTED PROGRAM MEMORY FOR PIC18F4321 FAMILY DEVICES

Address

Range

Block Code Protection

Controlled By:

MEMORY SIZE/DEVICE

8 Kbytes

4 Kbytes

(PIC18FX321)

(PIC18FX221)

BBSIZ<1:0>

11/10

01

00

11/10/01

00

000000h

Boot Block

256 words

Boot Block

256 words

CPB, WRTB, EBTRB

Boot Block

512 words

Boot Block

512 words

0001FFh

000200h

Boot Block

1K word

0003FFh

000400h

Block 0

0.75K words

Block 0

0.5K words

CP0, WRT0, EBTR0

0007FFh

000800h

Block 0

1.75K words

Block 0

1.5K words

Block 0

Block 1

1K word

000FFFh

001000h

CP1, WRT1, EBTR1

Block 1

2K words

Unimplemented

Reads all ‘0’s

001FFFh

002000h

Unimplemented

Reads all ‘0’s

(Unimplemented Memory

Space)

1FFFFFh

DS39689E-page 268

Preliminary

PIC18F4321 FAMILY

TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

300008h CONFIG5L

300009h CONFIG5H

30000Ah CONFIG6L

—

CPD

—

CPB

—

CP1

—

CP0

—

WRT1

—

WRT0

—

30000Bh CONFIG6H WRTD

WRTB

—

WRTC

—

30000Ch CONFIG7L

30000Dh CONFIG7H

—

EBTR1

—

EBTR0

—

EBTRB

—

Legend: Shaded cells are unimplemented.

A table read instruction that executes from a location

outside of that block is not allowed to read and will result

in reading ‘0’s. Figures 23-6 through 23-8 illustrate table

write and table read protection.

23.5.1

PROGRAM MEMORY

CODE PROTECTION

The program memory may be read to or written from

any location using the table read and table write

instructions. The device ID may be read with table

reads. The Configuration registers may be read and

written with the table read and table write instructions.

Note:

Code protection bits may only be written to

a ‘0’ from a ‘1’ state. It is not possible to

write a ‘1’ to a bit in the ‘0’ state. Code

protection bits are only set to ‘1’ by a full

chip erase or block erase function. The full

chip erase and block erase functions can

only be initiated via ICSP operation or an

external programmer.

In normal execution mode, the CPn bits have no direct

effect. CPn bits inhibit external reads and writes. A

block of user memory may be protected from table

writes if the WRTn Configuration bit is ‘0’. The EBTRn

bits control table reads. For a block of user memory

with the EBTRn bit set to ‘0’, a table read instruction

that executes from within that block is allowed to read.

FIGURE 23-6:

TABLE WRITE (WRTn) DISALLOWED

Program Memory⁽¹⁾

Register Values

Configuration Bit Settings

Boot Block

WRTB, EBTRB = 11

TBLPTR = 0008FFh

PC = 003FFEh

Block 0

WRT0, EBTR0 = 01

WRT1, EBTR1 = 11

TBLWT*

Block 1

PC = 00BFFEh

TBLWT*

Results: All table writes disabled to Blockn whenever WRTn = 0.

Note 1: See Figure 23-5 for block boundaries.

Preliminary

DS39689E-page 269

PIC18F4321 FAMILY

FIGURE 23-7:

EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED

Register Values

Program Memory⁽¹⁾

Configuration Bit Settings

Boot Block

WRTB, EBTRB = 11

TBLPTR = 0008FFh

PC = 007FFEh

Block 0

WRT0, EBTR0 = 10

WRT1, EBTR1 = 11

Block 1

TBLRD*

Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.

TABLAT register returns a value of ‘0’.

Note 1: See Figure 23-5 for block boundaries.

FIGURE 23-8:

EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED

Register Values

Program Memory⁽¹⁾

Configuration Bit Settings

WRTB, EBTRB = 11

WRT0, EBTR0 = 10

Boot Block

TBLPTR = 0008FFh

PC = 003FFEh

Block 0

TBLRD*

Block 1

WRT1, EBTR1 = 11

Results: Table reads permitted within Blockn, even when EBTRBn = 0.

TABLAT register returns the value of the data at the location TBLPTR.

Note 1: See Figure 23-5 for block boundaries.

DS39689E-page 270

Preliminary

PIC18F4321 FAMILY

To use the In-Circuit Debugger function of the micro-

controller, the design must implement In-Circuit Serial

Programming connections to MCLR/VPP/RE3, VDD,

VSS, RB7 and RB6. This will interface to the In-Circuit

Debugger module available from Microchip or one of

the third party development tool companies.

23.5.2

DATA EEPROM

CODE PROTECTION

The entire data EEPROM is protected from external

reads and writes by two bits: CPD and WRTD. CPD

inhibits external reads and writes of data EEPROM.

WRTD inhibits internal and external writes to data

EEPROM. The CPU can always read data EEPROM

under normal operation, regardless of the protection bit

settings.

23.9 Special ICPORT Features

(44-Pin TQFP Packages Only)

Under specific circumstances, the No Connect (NC)

pins of PIC18F4221/4321 devices in 44-pin TQFP

packages can provide additional functionality. These

features are controlled by device Configuration bits and

are available only in this package type and pin count.

23.5.3

CONFIGURATION REGISTER

PROTECTION

The Configuration registers can be write-protected.

The WRTC bit controls protection of the Configuration

registers. In normal execution mode, the WRTC bit is

readable only. WRTC can only be written via ICSP

operation or an external programmer.

23.9.1

DEDICATED ICD/ICSP PORT

The 44-pin TQFP devices can use NC pins to provide

an alternate port for In-Circuit Debugging (ICD) and In-

Circuit Serial Programming (ICSP). These pins are

collectively known as the dedicated ICSP/ICD port,

since they are not shared with any other function of the

device.

23.6 ID Locations

Eight memory locations (200000h-200007h) are

designated as ID locations, where the user can store

checksum or other code identification numbers. These

locations are both readable and writable during normal

execution through the TBLRD and TBLWT instructions

or during program/verify. The ID locations can be read

when the device is code-protected.

When implemented, the dedicated port activates three

NC pins to provide an alternate device Reset, data and

clock ports. None of these ports overlap with standard

I/O pins, making the I/O pins available to the user’s

application.

23.7

In-Circuit Serial Programming

The dedicated ICSP/ICD port is enabled by setting the

ICPRT Configuration bit. The port functions the same

way as the legacy ICSP/ICD port on RB6/RB7.

Table 23-5 identifies the functionally equivalent pins for

ICSP and ICD purposes.

PIC18F4321 family microcontrollers can be serially

programmed while in the end application circuit. This is

simply done with two lines for clock and data and three

other lines for power, ground and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware or a custom

firmware to be programmed.

TABLE 23-5: EQUIVALENT PINS FOR

LEGACY AND DEDICATED

ICD/ICSP™ PORTS

Pin Name

Pin Function

Legacy

Port

Dedicated

Port

Type

23.8 In-Circuit Debugger

When the DEBUG Configuration bit is programmed to

a ‘0’, the In-Circuit Debugger functionality is enabled.

This function allows simple debugging functions when

used with MPLAB^®IDE. When the microcontroller has

this feature enabled, some resources are not available

for general use. Table 23-4 shows which resources are

required by the background debugger.

MCLR/VPP/ NC/ICRST/

P

Device Reset and

Programming

Enable

RE3

ICVPP

RB6/KBI2/

PGC

NC/ICCK/

ICPGC

I

Serial Clock

RB7/KBI3/

PGD

NC/ICDT/

ICPGD

I/O Serial Data

Legend: I = Input, O = Output, P = Power

TABLE 23-4: DEBUGGER RESOURCES

I/O pins:

RB6, RB7

2 levels

Stack:

Program Memory:

Data Memory:

512 bytes

10 bytes

Preliminary

DS39689E-page 271

PIC18F4321 FAMILY

Even when the dedicated port is enabled, the ICSP and

ICD functions remain available through the legacy port.

When VIH is seen on the MCLR/VPP/RE3 pin, the state

of the ICRST/ICVPP pin is ignored.

23.10 Single-Supply ICSP Programming

The LVP Configuration bit enables Single-Supply ICSP

Programming (formerly known as Low-Voltage ICSP

Programming or LVP). When Single-Supply Program-

ming is enabled, the microcontroller can be programmed

without requiring high voltage being applied to the

MCLR/VPP/RE3 pin, but the RB5/KBI1/PGM pin is then

dedicated to controlling Program mode entry and is not

available as a general purpose I/O pin.

Note 1: The ICPORT Configuration bit can only

be programmed through the default ICSP

port.

2: The ICPORT Configuration bit must be

maintained clear for all 28-pin and 40-pin

devices; otherwise, unexpected operation

may occur.

While programming, using Single-Supply Program-

ming, VDD is applied to the MCLR/VPP/RE3 pin as in

normal execution mode. To enter Programming mode,

VDD is applied to the PGM pin.

23.9.2

28-PIN EMULATION

PIC18F4221/4321 devices in 44-pin TQFP packages

also have the ability to change their configuration under

external control for debugging purposes. This allows

the device to behave as if it were a PIC18F2221/2321

28-pin device.

Note 1: High-voltage programming is always

available, regardless of the state of the

LVP bit or the PGM pin, by applying VIHH

to the MCLR pin.

2: By default, Single-Supply ICSP Program-

ming is enabled in unprogrammed

devices (as supplied from Microchip) and

erased devices.

This 28-pin Configuration mode is controlled through a

single pin, NC/ICPORTS. Connecting this pin to VSS

forces the device to function as a 28-pin device; fea-

tures normally associated with the 40/44-pin devices

are disabled, along with their corresponding control

registers and bits. This includes PORTD and PORTE,

the SPP and the Enhanced PWM functionality of

CCP1. On the other hand, connecting the pin to VDD

forces the device to function in its default configuration.

3: When Single-Supply ICSP Programming

is enabled, the RB5 pin can no longer be

used as a general purpose I/O pin.

4: When LVP is enabled, externally pull the

PGM pin to VSS to allow normal program

execution.

The configuration option is only available when back-

ground debugging and the dedicated ICD/ICSP port

are both enabled (DEBUG Configuration bit is clear

and ICPRT Configuration bit is set). When disabled,

NC/ICPORTS is a No Connect pin.

If Single-Supply ICSP Programming mode will not be

used, the LVP bit can be cleared. RB5/KBI1/PGM then

becomes available as the digital I/O pin, RB5. The LVP

bit may be set or cleared only when using standard

high-voltage programming (VIHH applied to the MCLR/

VPP/RE3 pin). Once LVP has been disabled, only the

standard high-voltage programming is available and

must be used to program the device.

Memory that is not code-protected can be erased using

either a block erase, or erased row by row, then written

at any specified VDD. If code-protected memory is to be

erased, a block erase is required. If a block erase is to

be performed when using Single-Supply ICSP

Programming, the device must be supplied with VDD of

4.5V to 5.5V.

DS39689E-page 272

Preliminary

PIC18F4321 FAMILY

The literal instructions may use some of the following

operands:

24.0 INSTRUCTION SET SUMMARY

PIC18F4321 family devices incorporate the standard set

of 75 PIC18 core instructions, as well as an extended set

of 8 new instructions, for the optimization of code that is

recursive or that utilizes a software stack. The extended

set is discussed later in this section.

• A literal value to be loaded into a file register

(specified by ‘k’)

• The desired FSR register to load the literal value

into (specified by ‘f’)

• No operand required

(specified by ‘—’)

24.1 Standard Instruction Set

The control instructions may use some of the following

operands:

The standard PIC18 instruction set adds many

enhancements to the previous PIC^®instruction sets,

while maintaining an easy migration from these PIC

instruction sets. Most instructions are a single program

memory word (16 bits), but there are four instructions

that require two program memory locations.

• A program memory address (specified by ‘n’)

• The mode of the CALLor RETURNinstructions

(specified by ‘s’)

• The mode of the table read and table write

instructions (specified by ‘m’)

Each single-word instruction is a 16-bit word divided

into an opcode, which specifies the instruction type and

one or more operands, which further specify the

operation of the instruction.

• No operand required

(specified by ‘—’)

All instructions are a single word, except for four

double-word instructions. These instructions were

made double-word to contain the required information

in 32 bits. In the second word, the 4 MSbs are ‘1’s. If

this second word is executed as an instruction (by

itself), it will execute as a NOP.

The instruction set is highly orthogonal and is grouped

into four basic categories:

• Byte-oriented operations

• Bit-oriented operations

• Literal operations

All single-word instructions are executed in a single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of the instruc-

tion. In these cases, the execution takes two instruction

cycles, with the additional instruction cycle(s) executed

as a NOP.

• Control operations

The PIC18 instruction set summary in Table 24-2 lists

byte-oriented, bit-oriented, literal and control

operations. Table 24-1 shows the opcode field

descriptions.

Most byte-oriented instructions have three operands:

The double-word instructions execute in two instruction

cycles.

1. The file register (specified by ‘f’)

One instruction cycle consists of four oscillator periods.

Thus, for an oscillator frequency of 4 MHz, the normal

instruction execution time is 1 μs. If a conditional test is

true, or the program counter is changed as a result of

an instruction, the instruction execution time is 2 μs.

Two-word branch instructions (if true) would take 3 μs.

2. The destination of the result (specified by ‘d’)

3. The accessed memory (specified by ‘a’)

The file register designator ‘f’ specifies which file

register is to be used by the instruction. The destination

designator ‘d’ specifies where the result of the opera-

tion is to be placed. If ‘d’ is zero, the result is placed in

the WREG register. If ‘d’ is one, the result is placed in

the file register specified in the instruction.

Figure 24-1 shows the general formats that the instruc-

tions can have. All examples use the convention ‘nnh’

to represent a hexadecimal number.

All bit-oriented instructions have three operands:

The Instruction Set Summary, shown in Table 24-2,

lists the standard instructions recognized by the

Microchip MPASM™ Assembler.

1. The file register (specified by ‘f’)

2. The bit in the file register (specified by ‘b’)

3. The accessed memory (specified by ‘a’)

Section 24.1.1 “Standard Instruction Set” provides

The bit field designator ‘b’ selects the number of the bit

affected by the operation, while the file register

designator ‘f’ represents the number of the file in which

the bit is located.

a description of each instruction.

Preliminary

DS39689E-page 273

PIC18F4321 FAMILY

TABLE 24-1: OPCODE FIELD DESCRIPTIONS

Field

Description

a

RAM access bit

a = 0: RAM location in Access RAM (BSR register is ignored)

a = 1: RAM bank is specified by BSR register

bbb

Bit address within an 8-bit file register (0 to 7).

BSR

Bank Select Register. Used to select the current RAM bank.

ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.

C, DC, Z, OV, N

d

Destination select bit

d = 0: store result in WREG

d = 1: store result in file register f

dest

f

Destination: either the WREG register or the specified register file location.

8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).

12-bit Register file address (000h to FFFh). This is the source address.

12-bit Register file address (000h to FFFh). This is the destination address.

Global Interrupt Enable bit.

f

s

d

GIE

k

Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).

Label name.

label

mm

The mode of the TBLPTR register for the table read and table write instructions.

Only used with table read and table write instructions:

*

No change to register (such as TBLPTR with table reads and writes)

Post-Increment register (such as TBLPTR with table reads and writes)

Post-Decrement register (such as TBLPTR with table reads and writes)

Pre-Increment register (such as TBLPTR with table reads and writes)

*+

*-

+*

n

The relative address (2’s complement number) for relative branch instructions or the direct address for

Call/Branch and Return instructions.

PC

Program Counter.

PCL

Program Counter Low Byte.

Program Counter High Byte.

Program Counter High Byte Latch.

Program Counter Upper Byte Latch.

Power-down bit.

PCH

PCLATH

PCLATU

PD

PRODH

PRODL

s

Product of Multiply High Byte.

Product of Multiply Low Byte.

Fast Call/Return mode select bit

s = 0: do not update into/from shadow registers

s = 1: certain registers loaded into/from shadow registers (Fast mode)

TBLPTR

TABLAT

TO

21-bit Table Pointer (points to a Program Memory location).

8-bit Table Latch.

Time-out bit.

TOS

u

Top-of-Stack.

Unused or unchanged.

Watchdog Timer.

WDT

WREG

x

Working register (accumulator).

Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for

compatibility with all Microchip software tools.

z

{

7-bit offset value for indirect addressing of register files (source).

7-bit offset value for indirect addressing of register files (destination).

Optional argument.

s

d

}

[text]

(text)

[expr]<n>

→

Indicates an indexed address.

The contents of text.

Specifies bit nof the register indicated by the pointer expr.

Assigned to.

< >

Register bit field.

∈

In the set of.

italics

User defined term (font is Courier).

DS39689E-page 274

Preliminary

PIC18F4321 FAMILY

FIGURE 24-1:

GENERAL FORMAT FOR INSTRUCTIONS

Byte-oriented file register operations

15 10

OPCODE f (FILE #)

Example Instruction

9

8

7

0

ADDWF MYREG, W, B

d

a

d = 0for result destination to be WREG register

d = 1for result destination to be file register (f)

a = 0to force Access Bank

a = 1for BSR to select bank

f = 8-bit file register address

Byte to Byte move operations (2-word)

15

12 11

0

OPCODE

f (Source FILE #)

MOVFF MYREG1, MYREG2

15

12 11

1111

f (Destination FILE #)

f = 12-bit file register address

Bit-oriented file register operations

15 12 11 9 8

OPCODE b (BIT #)

7

0

BSF MYREG, bit, B

a

f (FILE #)

b = 3-bit position of bit in file register (f)

a = 0to force Access Bank

a = 1for BSR to select bank

f = 8-bit file register address

Literal operations

15

8

7

0

MOVLW 7Fh

OPCODE

k (literal)

k = 8-bit immediate value

Control operations

CALL, GOTO and Branch operations

15

8 7

0

GOTO Label

OPCODE

12 11

n<7:0> (literal)

15

0

1111

n<19:8> (literal)

n = 20-bit immediate value

15

8

7

0

CALL MYFUNC

OPCODE

12 11

n<7:0> (literal)

S

0

1111

n<19:8> (literal)

S = Fast bit

15

11 10

0

BRA MYFUNC

BC MYFUNC

OPCODE

n<10:0> (literal)

15

OPCODE

8 7

n<7:0> (literal)

Preliminary

DS39689E-page 275

PIC18F4321 FAMILY

TABLE 24-2: PIC18FXXXX INSTRUCTION SET

16-Bit Instruction Word

MSb LSb

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

BYTE-ORIENTED OPERATIONS

ADDWF f, d, a Add WREG and f

ADDWFC f, d, a Add WREG and CARRY bit to f

1

0010 01da

ffff

ffff C, DC, Z, OV, N

ffff Z, N

1, 2

1,2

2

1, 2

4

1, 2

1, 2, 3, 4

1, 2

1, 2, 3, 4

4

1, 2

1

0010 00da

0001 01da

0110 101a

0001 11da

ANDWF

CLRF

COMF

f, d, a AND WREG with f

f, a Clear f

f, d, a Complement f

ffff

Z

ffff Z, N

ffff None

ffff C, DC, Z, OV, N

ffff None

ffff C, DC, Z, OV, N

ffff None

ffff Z, N

ffff None

ffff

ffff None

CPFSEQ

CPFSGT

CPFSLT

DECF

f, a

Compare f with WREG, skip =

Compare f with WREG, skip >

Compare f with WREG, skip <

1 (2 or 3) 0110 001a

1 (2 or 3) 0110 010a

1 (2 or 3) 0110 000a

f, d, a Decrement f

1

0000 01da

DECFSZ

DCFSNZ

INCF

f, d, a Decrement f, Skip if 0

f, d, a Decrement f, Skip if Not 0

f, d, a Increment f

1 (2 or 3) 0010 11da

1 (2 or 3) 0100 11da

1

1 (2 or 3) 0011 11da

1 (2 or 3) 0100 10da

1

2

0010 10da

INCFSZ

INFSNZ

IORWF

MOVF

f, d, a Increment f, Skip if 0

f, d, a Increment f, Skip if Not 0

f, d, a Inclusive OR WREG with f

f, d, a Move f

0001 00da

0101 00da

1100 ffff

1111 ffff

0110 111a

0000 001a

0110 110a

0011 01da

0100 01da

0011 00da

0100 00da

0110 100a

0101 01da

MOVFF

f , f

Move f (source) to 1st word

s

d

s

f (destination) 2nd word

d

MOVWF

MULWF

NEGF

f, a

Move WREG to f

Multiply WREG with f

Negate f

1

1, 2

ffff C, DC, Z, OV, N

ffff C, Z, N

ffff Z, N

ffff C, Z, N

ffff Z, N

RLCF

RLNCF

RRCF

RRNCF

SETF

f, d, a Rotate Left f through Carry

f, d, a Rotate Left f (No Carry)

f, d, a Rotate Right f through Carry

f, d, a Rotate Right f (No Carry)

f, a

Set f

ffff None

ffff C, DC, Z, OV, N

1, 2

SUBFWB f, d, a Subtract f from WREG with

borrow

SUBWF

f, d, a Subtract WREG from f

1

0101 11da

0101 10da

ffff

ffff C, DC, Z, OV, N

SUBWFB f, d, a Subtract WREG from f with

borrow

SWAPF

TSTFSZ

XORWF

f, d, a Swap nibbles in f

f, a Test f, skip if 0

f, d, a Exclusive OR WREG with f

1

0011 10da

ffff

ffff None

ffff Z, N

4

1, 2

1 (2 or 3) 0110 011a

0001 10da

1

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an

external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if

assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOPunless the

first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory

locations have a valid instruction.

DS39689E-page 276

Preliminary

PIC18F4321 FAMILY

TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)

16-Bit Instruction Word

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

MSb LSb

BIT-ORIENTED OPERATIONS

BCF

BSF

BTFSC

BTFSS

BTG

f, b, a Bit Clear f

f, b, a Bit Set f

f, b, a Bit Test f, Skip if Clear

f, b, a Bit Test f, Skip if Set

f, b, a Bit Toggle f

1

1001 bbba

1000 bbba

ffff

ffff None

1, 2

3, 4

1, 2

1 (2 or 3) 1011 bbba

1 (2 or 3) 1010 bbba

1

0111 bbba

CONTROL OPERATIONS

BC

BN

n

Branch if Carry

1 (2)

2

1110 0010

1110 0110

1110 0011

1110 0111

1110 0101

1110 0001

1110 0100

1101 0nnn

1110 0000

1110 110s

1111 kkkk

0000 0000

1110 1111

1111 kkkk

0000 0000

1111 xxxx

0000 0000

1101 1nnn

0000 0000

nnnn

kkkk

0000

kkkk

0000

xxxx

0000

nnnn

1111

0001

nnnn None

kkkk None

kkkk

Branch if Negative

Branch if Not Carry

Branch if Not Negative

Branch if Not Overflow

Branch if Not Zero

Branch if Overflow

Branch Unconditionally

Branch if Zero

Call subroutine 1st word

2nd word

Clear Watchdog Timer

Decimal Adjust WREG

Go to address 1st word

2nd word

BNC

BNN

BNOV

BNZ

BOV

BRA

BZ

n

n, s

1 (2)

2

CALL

CLRWDT

DAW

GOTO

—

n

1

2

0100 TO, PD

0111

C

kkkk None

kkkk

NOP

POP

PUSH

RCALL

RESET

RETFIE

—

n

No Operation

1

2

1

2

0000 None

xxxx None

0110 None

0101 None

nnnn None

1111 All

4

Pop top of return stack (TOS)

Push top of return stack (TOS)

Relative Call

Software device Reset

Return from interrupt enable

s

000s GIE/GIEH,

PEIE/GIEL

RETLW

RETURN

SLEEP

k

s

—

Return with literal in WREG

Return from Subroutine

Go into Standby mode

2

1

0000 1100

0000 0000

kkkk

0001

0000

kkkk None

001s None

0011 TO, PD

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an

external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if

assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOPunless the

first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory

locations have a valid instruction.

Preliminary

DS39689E-page 277

PIC18F4321 FAMILY

TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED)

16-Bit Instruction Word

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

MSb

LSb

LITERAL OPERATIONS

ADDLW

ANDLW

IORLW

LFSR

k

f, k

Add literal and WREG

AND literal with WREG

Inclusive OR literal with WREG

Move literal (12-bit) 2nd word

1

2

0000 1111 kkkk

0000 1011 kkkk

0000 1001 kkkk

1110 1110 00ff

1111 0000 kkkk

0000 0001 0000

0000 1110 kkkk

0000 1101 kkkk

0000 1100 kkkk

0000 1000 kkkk

0000 1010 kkkk

kkkk C, DC, Z, OV, N

kkkk Z, N

kkkk None

kkkk

kkkk None

kkkk C, DC, Z, OV, N

kkkk Z, N

to FSR(f)

1st word

MOVLB

MOVLW

MULLW

RETLW

SUBLW

XORLW

k

Move literal to BSR<3:0>

Move literal to WREG

Multiply literal with WREG

Return with literal in WREG

Subtract WREG from literal

Exclusive OR literal with WREG

1

2

1

DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS

TBLRD*

Table Read

2

0000 0000 0000

1000 None

1001 None

1010 None

1011 None

1100 None

1101 None

1110 None

1111 None

TBLRD*+

TBLRD*-

TBLRD+*

TBLWT*

TBLWT*+

TBLWT*-

TBLWT+*

Table Read with post-increment

Table Read with post-decrement

Table Read with pre-increment

Table Write

Table Write with post-increment

Table Write with post-decrement

Table Write with pre-increment

2

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an

external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if

assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOPunless the

first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory

locations have a valid instruction.

DS39689E-page 278

Preliminary

PIC18F4321 FAMILY

24.1.1

STANDARD INSTRUCTION SET

ADDLW

ADD Literal to W

ADDWF

ADD W to f

Syntax:

ADDLW

k

Syntax:

ADDWF

f {,d {,a}}

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 ≤ k ≤ 255

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(W) + k → W

N, OV, C, DC, Z

Operation:

(W) + (f) → dest

0000

1111

kkkk

Status Affected:

Encoding:

N, OV, C, DC, Z

The contents of W are added to the

8-bit literal ‘k’ and the result is placed in

W.

0010

01da

ffff

Description:

Add W to register ‘f’. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

Words:

Cycles:

1

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write to W

Example:

ADDLW

15h

Before Instruction

10h

After Instruction

25h

W

=

Words:

Cycles:

1

W

=

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Example:

ADDWF

REG, 0, 0

Before Instruction

W

=

17h

REG

=

0C2h

After Instruction

W

REG

=

0D9h

0C2h

Note:

All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in

symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).

Preliminary

DS39689E-page 279

PIC18F4321 FAMILY

ADDWFC

ADD W and CARRY bit to f

ANDLW

AND Literal with W

Syntax:

ADDWFC

f {,d {,a}}

Syntax:

ANDLW

k

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 ≤ k ≤ 255

(W) .AND. k → W

N, Z

Operation:

(W) + (f) + (C) → dest

0000

1011

kkkk

Status Affected:

Encoding:

N,OV, C, DC, Z

The contents of W are ANDed with the

8-bit literal ‘k’. The result is placed in W.

0010

00da

ffff

Description:

Add W, the Carry flag and data memory

location ‘f’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed in data memory

Words:

1

Cycles:

Q Cycle Activity:

Q1

location ‘f’.

Q2

Q3

Q4

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

Decode

Read literal

‘k’

Process

Data

Write to W

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Example:

ANDLW

05Fh

Before Instruction

W

=

A3h

03h

After Instruction

W

=

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Example:

ADDWFC

REG, 0, 1

Before Instruction

Carry bit

REG

W

=

1

02h

4Dh

After Instruction

Carry bit

REG

W

=

0

02h

50h

DS39689E-page 280

Preliminary

PIC18F4321 FAMILY

ANDWF

AND W with f

BC

Branch if Carry

Syntax:

ANDWF

f {,d {,a}}

Syntax:

BC

n

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

Operation:

-128 ≤ n ≤ 127

if Carry bit is ‘1’

(PC) + 2 + 2n → PC

Operation:

(W) .AND. (f) → dest

Status Affected:

Encoding:

None

Status Affected:

Encoding:

N, Z

1110

0010

nnnn

0001

01da

ffff

Description:

If the Carry bit is ‘1’, then the program

will branch.

Description:

The contents of W are ANDed with

register ‘f’. If ‘d’ is ‘0’, the result is stored

in W. If ‘d’ is ‘1’, the result is stored back

in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1

1(2)

Q Cycle Activity:

If Jump:

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

Write to PC

Words:

1

Cycles:

No

operation

Q Cycle Activity:

Q1

If No Jump:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Decode

Read literal

‘n’

Process

Data

No

operation

Example:

ANDWF

REG, 0, 0

Example:

HERE

BC

5

Before Instruction

W

REG

=

17h

C2h

PC

=

address (HERE)

After Instruction

If Carry

PC

If Carry

PC

=

1;

address (HERE + 12)

0;

address (HERE + 2)

W

REG

=

02h

C2h

Preliminary

DS39689E-page 281

PIC18F4321 FAMILY

BCF

Bit Clear f

BN

Branch if Negative

Syntax:

BCF f, b {,a}

Syntax:

BN

n

Operands:

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operands:

Operation:

-128 ≤ n ≤ 127

if Negative bit is ‘1’

(PC) + 2 + 2n → PC

Operation:

0 → f

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1110

0110

nnnn

1001

bbba

ffff

Description:

If the Negative bit is ‘1’, then the

Description:

Bit ‘b’ in register ‘f’ is cleared.

program will branch.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words:

Cycles:

1

1(2)

Q Cycle Activity:

If Jump:

Words:

Cycles:

1

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

Write to PC

Q Cycle Activity:

Q1

Q2

Q3

Q4

No

Decode

Read

register ‘f’

Process

Data

Write

register ‘f’

operation

If No Jump:

Q1

Q2

Q3

Q4

Example:

BCF

FLAG_REG, 7, 0

C7h

47h

Decode

Read literal

‘n’

Process

Data

No

operation

Before Instruction

FLAG_REG =

After Instruction

FLAG_REG =

Example:

HERE

BN Jump

Before Instruction

PC

=

address (HERE)

After Instruction

If Negative

PC

If Negative

PC

=

1;

address (Jump)

0;

address (HERE + 2)

DS39689E-page 282

Preliminary

PIC18F4321 FAMILY

BNC

Branch if Not Carry

BNN

Branch if Not Negative

Syntax:

BNC

n

Syntax:

BNN

n

Operands:

Operation:

-128 ≤ n ≤ 127

Operands:

Operation:

-128 ≤ n ≤ 127

if Carry bit is ‘0’

(PC) + 2 + 2n → PC

if Negative bit is ‘0’

(PC) + 2 + 2n → PC

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1110

0011

nnnn

1110

0111

nnnn

Description:

If the Carry bit is ‘0’, then the program

will branch.

Description:

If the Negative bit is ‘0’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Q Cycle Activity:

If Jump:

Q Cycle Activity:

If Jump:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

Write to PC

Decode

Read literal

‘n’

Process

Data

Write to PC

No

operation

If No Jump:

Q1

If No Jump:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

No

operation

Decode

Read literal

‘n’

Process

Data

No

operation

Example:

HERE

BNC Jump

Example:

HERE

BNN Jump

Before Instruction

PC

=

address (HERE)

PC

=

address (HERE)

After Instruction

If Carry

PC

If Carry

PC

=

0;

If Negative

PC

If Negative

PC

=

0;

address (Jump)

1;

address (HERE + 2)

Preliminary

DS39689E-page 283

PIC18F4321 FAMILY

BNOV

Branch if Not Overflow

BNZ

Branch if Not Zero

Syntax:

BNOV

n

Syntax:

BNZ

n

Operands:

Operation:

-128 ≤ n ≤ 127

Operands:

Operation:

-128 ≤ n ≤ 127

if Overflow bit is ‘0’

(PC) + 2 + 2n → PC

if Zero bit is ‘0’

(PC) + 2 + 2n → PC

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1110

0101

nnnn

1110

0001

nnnn

Description:

If the Overflow bit is ‘0’, then the

program will branch.

Description:

If the Zero bit is ‘0’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Q Cycle Activity:

If Jump:

Q Cycle Activity:

If Jump:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

Write to PC

Decode

Read literal

‘n’

Process

Data

Write to PC

No

operation

If No Jump:

Q1

If No Jump:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

No

operation

Decode

Read literal

‘n’

Process

Data

No

operation

Example:

HERE

BNOV Jump

Example:

HERE

BNZ Jump

Before Instruction

PC

=

address (HERE)

PC

=

address (HERE)

After Instruction

If Overflow

PC

If Overflow

PC

=

0;

If Zero

PC

If Zero

PC

=

0;

address (Jump)

1;

address (HERE + 2)

DS39689E-page 284

Preliminary

PIC18F4321 FAMILY

BRA

Unconditional Branch

BSF

Bit Set f

Syntax:

BRA

n

Syntax:

BSF f, b {,a}

Operands:

Operation:

-1024 ≤ n ≤ 1023

Operands:

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

(PC) + 2 + 2n → PC

Status Affected: None

Operation:

1 → f

Encoding:

1101

0nnn

nnnn

Status Affected:

Encoding:

None

Description:

Add the 2’s complement number ‘2n’ to

the PC. Since the PC will have

1000

bbba

ffff

incremented to fetch the next instruction,

the new address will be PC + 2 + 2n. This

instruction is a two-cycle instruction.

Description:

Bit ‘b’ in register ‘f’ is set.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

Write to PC

No

operation

No

operation

No

operation

No

operation

Words:

Cycles:

1

Q Cycle Activity:

Q1

Example:

HERE

BRA Jump

Q2

Q3

Q4

Before Instruction

Decode

Read

register ‘f’

Process

Data

Write

register ‘f’

PC

=

address (HERE)

address (Jump)

After Instruction

PC

Example:

BSF

FLAG_REG, 7, 1

0Ah

8Ah

Before Instruction

FLAG_REG

After Instruction

FLAG_REG

=

Preliminary

DS39689E-page 285

PIC18F4321 FAMILY

BTFSC

Bit Test File, Skip if Clear

BTFSS

Bit Test File, Skip if Set

Syntax:

BTFSC f, b {,a}

Syntax:

BTFSS f, b {,a}

Operands:

0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

0 ≤ b < 7

a ∈ [0,1]

Operation:

skip if (f) = 0

Operation:

skip if (f) = 1

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1011

bbba

ffff

1010

bbba

ffff

Description:

If bit ‘b’ in register ‘f’ is ‘0’, then the next

instruction is skipped. If bit ‘b’ is ‘0’, then

the next instruction fetched during the

current instruction execution is discarded

and a NOPis executed instead, making

this a two-cycle instruction.

Description:

If bit ‘b’ in register ‘f’ is ‘1’, then the next

instruction is skipped. If bit ‘b’ is ‘1’, then

the next instruction fetched during the

current instruction execution is discarded

and a NOPis executed instead, making

this a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected. If

‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’, the Access Bank is selected. If

‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates in

Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh).

See Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh).

See Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

No

operation

Decode

Read

register ‘f’

Process

Data

No

operation

If skip:

Q1

If skip:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

No

operation

No

operation

Example:

HERE

FALSE

TRUE

BTFSC

:

FLAG, 1, 0

Example:

HERE

FALSE

TRUE

BTFSS

:

FLAG, 1, 0

Before Instruction

PC

Before Instruction

PC

=

address (HERE)

=

address (HERE)

After Instruction

If FLAG<1>

PC

If FLAG<1>

PC

=

0;

If FLAG<1>

PC

If FLAG<1>

PC

=

0;

address (TRUE)

1;

address (FALSE)

1;

address (FALSE)

address (TRUE)

DS39689E-page 286

Preliminary

PIC18F4321 FAMILY

BTG

Bit Toggle f

BOV

Branch if Overflow

Syntax:

BTG f, b {,a}

Syntax:

BOV

n

Operands:

0 ≤ f ≤ 255

0 ≤ b < 7

a ∈ [0,1]

Operands:

Operation:

-128 ≤ n ≤ 127

if Overflow bit is ‘1’

(PC) + 2 + 2n → PC

Operation:

(f) → f

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

1110

0100

nnnn

0111

bbba

ffff

Description:

If the Overflow bit is ‘1’, then the

Description:

Bit ‘b’ in data memory location ‘f’ is

inverted.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words:

Cycles:

1

1(2)

Q Cycle Activity:

If Jump:

Words:

Cycles:

1

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

Write to PC

Q Cycle Activity:

Q1

No

operation

No

operation

No

operation

No

operation

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write

register ‘f’

If No Jump:

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

No

operation

Example:

BTG

PORTC, 4, 0

Before Instruction:

PORTC

After Instruction:

PORTC

=

0111 0101 [75h]

0110 0101 [65h]

Example:

HERE

BOV Jump

Before Instruction

=

PC

=

address (HERE)

After Instruction

If Overflow

PC

If Overflow

PC

=

1;

address (Jump)

0;

address (HERE + 2)

Preliminary

DS39689E-page 287

PIC18F4321 FAMILY

BZ

Branch if Zero

CALL

Subroutine Call

Syntax:

BZ

n

Syntax:

CALL k {,s}

Operands:

Operation:

-128 ≤ n ≤ 127

Operands:

0 ≤ k ≤ 1048575

s ∈ [0,1]

if Zero bit is ‘1’

(PC) + 2 + 2n → PC

Operation:

(PC) + 4 → TOS,

k → PC<20:1>,

if s = 1

Status Affected:

Encoding:

None

1110

0000

nnnn

(W) → WS,

(STATUS) → STATUSS,

(BSR) → BSRS

Description:

If the Zero bit is ‘1’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Status Affected:

None

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>)

1110

1111

110s

k kkk

kkkk

7

0

8

k

kkk kkkk

19

Description:

Subroutine call of entire 2-Mbyte

memory range. First, return address

(PC + 4) is pushed onto the return

stack. If ‘s’ = 1, the W, STATUS and

Words:

Cycles:

1

1(2)

BSR registers are also pushed into their

respective shadow registers, WS,

STATUSS and BSRS. If ‘s’ = 0, no

update occurs (default). Then, the

20-bit value ‘k’ is loaded into PC<20:1>.

CALLis a two-cycle instruction.

Q Cycle Activity:

If Jump:

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

Write to PC

No

operation

No

operation

No

operation

No

operation

Words:

Cycles:

2

If No Jump:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Decode

Read literal

‘n’

Process

Data

No

operation

Q2

Q3

Q4

Decode

Read literal PUSH PC to Read literal

‘k’<7:0>,

stack

‘k’<19:8>,

Write to PC

Example:

HERE

BZ Jump

No

operation

No

operation

No

operation

No

operation

Before Instruction

PC

=

address (HERE)

After Instruction

If Zero

PC

If Zero

PC

=

1;

Example:

HERE

CALL THERE, 1

address (Jump)

Before Instruction

PC

After Instruction

0;

address (HERE + 2)

=

address (HERE)

PC

TOS

WS

BSRS

STATUSS =

=

address (THERE)

=

address (HERE + 4)

W

BSR

STATUS

DS39689E-page 288

Preliminary

PIC18F4321 FAMILY

CLRF

Clear f

CLRWDT

Clear Watchdog Timer

Syntax:

CLRF f {,a}

Syntax:

CLRWDT

None

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operands:

Operation:

000h → WDT,

000h → WDT postscaler,

1 → TO,

Operation:

000h → f

1 → Z

1 → PD

Status Affected:

Encoding:

Z

Status Affected:

Encoding:

TO, PD

0110

101a

ffff

0000

0100

Description:

Clears the contents of the specified

register.

Description:

CLRWDTinstruction resets the

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

Watchdog Timer. It also resets the

postscaler of the WDT. Status bits, TO

and PD, are set.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

No

Process

Data

No

operation

Words:

Cycles:

1

Example:

CLRWDT

Q Cycle Activity:

Q1

Before Instruction

Q2

Q3

Q4

WDT Counter

After Instruction

WDT Counter

WDT Postscaler

TO

=

?

Decode

Read

register ‘f’

Process

Data

Write

register ‘f’

=

00h

0

1

Example:

CLRF

FLAG_REG, 1

PD

1

Before Instruction

FLAG_REG

After Instruction

FLAG_REG

=

5Ah

00h

Preliminary

DS39689E-page 289

PIC18F4321 FAMILY

CPFSEQ

Compare f with W, Skip if f = W

COMF

Complement f

Syntax:

CPFSEQ f {,a}

Syntax:

COMF f {,d {,a}}

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f) – (W),

skip if (f) = (W)

(unsigned comparison)

Operation:

(f) → dest

Status Affected:

Encoding:

N, Z

Status Affected:

Encoding:

None

0001

11da

ffff

0110

001a

ffff

Description:

The contents of register ‘f’ are

Description:

Compares the contents of data memory

location ‘f’ to the contents of W by

performing an unsigned subtraction.

If ‘f’ = W, then the fetched instruction is

discarded and a NOPis executed

instead, making this a two-cycle

instruction.

complemented. If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Words:

Cycles:

1

Q2

Q3

Q4

1(2)

Decode

Read

register ‘f’

Process

Data

Write to

destination

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Example:

COMF

REG, 0, 0

Q2

Q3

Q4

Before Instruction

Decode

Read

register ‘f’

Process

Data

No

operation

REG

=

13h

After Instruction

If skip:

REG

W

=

13h

ECh

Q1

No

Q2

No

Q3

No

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

No

Q2

No

Q3

No

Q4

No

operation

No

operation

No

operation

No

operation

No

operation

Example:

HERE

CPFSEQ REG, 0

NEQUAL

EQUAL

:

Before Instruction

PC Address

=

HERE

W

REG

=

?

After Instruction

If REG

PC

=

W;

Address (EQUAL)

If REG

PC

≠

=

W;

Address (NEQUAL)

DS39689E-page 290

Preliminary

PIC18F4321 FAMILY

CPFSGT

Compare f with W, Skip if f > W

CPFSLT

Compare f with W, Skip if f < W

Syntax:

CPFSGT f {,a}

Syntax:

CPFSLT f {,a}

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operation:

(f) – (W),

skip if (f) > (W)

(unsigned comparison)

Operation:

(f) – (W),

skip if (f) < (W)

(unsigned comparison)

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

0110

010a

ffff

0110

000a

ffff

Description:

Compares the contents of data memory

location ‘f’ to the contents of the W by

performing an unsigned subtraction.

If the contents of ‘f’ are greater than the

^{contents of WREG}, then the fetched

instruction is discarded and a NOPis

executed instead, making this a

Description:

Compares the contents of data memory

location ‘f’ to the contents of W by

performing an unsigned subtraction.

If the contents of ‘f’ are less than the

contents of W, then the fetched

instruction is discarded and a NOPis

executed instead, making this a

two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

Words:

Cycles:

1

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Words:

Cycles:

1

Decode

Read

register ‘f’

Process

Data

No

operation

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

If skip:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

No

operation

No

operation

No

operation

No

operation

Q2

Q3

Q4

No

operation

Decode

Read

register ‘f’

Process

Data

If skip and followed by 2-word instruction:

If skip:

Q1

Q2

Q3

Q4

Q1

No

Q2

No

Q3

No

Q4

No

operation

No

operation

No

operation

No

operation

No

If skip and followed by 2-word instruction:

operation

Q1

No

operation

No

Q2

No

operation

No

Q3

No

operation

No

Q4

No

operation

No

Example:

HERE

NLESS

LESS

CPFSLT REG, 1

:

operation

Before Instruction

PC

W

=

Address (HERE)

Example:

HERE

NGREATER

GREATER

CPFSGT REG, 0

:

?

After Instruction

If REG

PC

If REG

PC

<

=

≥

=

W;

Before Instruction

Address (LESS)

W;

Address (NLESS)

PC

W

=

Address (HERE)

?

After Instruction

If REG

PC

>

=

W;

Address (GREATER)

If REG

PC

≤

=

W;

Address (NGREATER)

Preliminary

DS39689E-page 291

PIC18F4321 FAMILY

DAW

Decimal Adjust W Register

DECF

Decrement f

Syntax:

DAW

None

Syntax:

DECF f {,d {,a}}

Operands:

Operation:

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

If [W<3:0> > 9] or [DC = 1] then

(W<3:0>) + 6 → W<3:0>;

else

Operation:

(f) – 1 → dest

(W<3:0>) → W<3:0>

Status Affected:

Encoding:

C, DC, N, OV, Z

0000

01da

ffff

If [W<7:4> + DC > 9] or [C = 1] then

(W<7:4>) + 6 + DC → W<7:4>;

else

Description:

Decrement register ‘f’. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

(W<7:4>) + DC → W<7:4>

Status Affected:

Encoding:

C

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

0000

0111

Description:

DAW adjusts the eight-bit value in W,

resulting from the earlier addition of two

variables (each in packed BCD format)

and produces a correct packed BCD

result.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Words:

Cycles:

1

Q2

Q3

Q4

Decode

Read

register W

Process

Data

Write

W

Q Cycle Activity:

Q1

Q2

Q3

Q4

Example 1:

Decode

Read

register ‘f’

Process

Data

Write to

destination

DAW

Before Instruction

W

C

DC

=

A5h

0

Example:

DECF

CNT,

1, 0

Before Instruction

After Instruction

CNT

Z

After Instruction

=

01h

0

=

W

=

05h

1

0

C

DC

=

CNT

Z

=

00h

1

Example 2:

Before Instruction

W

=

CEh

C

DC

=

0

After Instruction

W

=

34h

C

DC

=

1

0

DS39689E-page 292

Preliminary

PIC18F4321 FAMILY

DECFSZ

Decrement f, Skip if 0

DCFSNZ

Decrement f, Skip if Not 0

Syntax:

DECFSZ f {,d {,a}}

Syntax:

DCFSNZ f {,d {,a}}

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f) – 1 → dest,

Operation:

(f) – 1 → dest,

skip if result = 0

skip if result ≠ 0

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

0010

11da

ffff

0100

11da

ffff

Description:

The contents of register ‘f’ are

Description:

The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is ‘0’, the next instruction,

which is already fetched, is discarded

and a NOPis executed instead, making

it a two-cycle instruction.

decremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is not ‘0’, the next

instruction, which is already fetched, is

discarded and a NOPis executed

instead, making it a two-cycle

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Decode

Read

Process

Data

Write to

destination

register ‘f’

If skip:

Q1

If skip:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

No

operation

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

No

operation

No

operation

No

operation

No

operation

Example:

HERE

DECFSZ

GOTO

CNT, 1, 1

LOOP

Example:

HERE

ZERO

NZERO

DCFSNZ TEMP, 1, 0

:

CONTINUE

Before Instruction

PC

After Instruction

Before Instruction

TEMP

After Instruction

=

Address (HERE)

=

?

CNT

=

CNT – 1

0;

If CNT

=

≠

=

TEMP

If TEMP

PC

If TEMP

PC

=

≠

=

TEMP – 1,

0;

Address (ZERO)

0;

Address (NZERO)

PC

Address (CONTINUE)

0;

If CNT

PC

Address (HERE + 2)

Preliminary

DS39689E-page 293

PIC18F4321 FAMILY

GOTO

Unconditional Branch

INCF

Increment f

Syntax:

GOTO

k

Syntax:

INCF f {,d {,a}}

Operands:

Operation:

Status Affected:

0 ≤ k ≤ 1048575

k → PC<20:1>

None

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f) + 1 → dest

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>)

Status Affected:

Encoding:

C, DC, N, OV, Z

1110

1111

kkk

k kkk

kkkk

7

0

8

k

0010

10da

ffff

19

Description:

GOTOallows an unconditional branch

anywhere within entire

2-Mbyte memory range. The 20-bit

value ‘k’ is loaded into PC<20:1>.

GOTOis always a two-cycle

instruction.

Description:

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read literal

‘k’<7:0>,

No

operation

Read literal

‘k’<19:8>,

Write to PC

Words:

Cycles:

1

No

operation

No

operation

Q Cycle Activity:

Q1

Example:

GOTO THERE

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

After Instruction

PC

=

Address (THERE)

Example:

INCF

CNT, 1, 0

Before Instruction

CNT

Z

=

FFh

0

=

C

?

DC

?

After Instruction

CNT

Z

=

00h

1

=

C

1

DC

1

DS39689E-page 294

Preliminary

PIC18F4321 FAMILY

INFSNZ

Increment f, Skip if Not 0

INCFSZ

Increment f, Skip if 0

Syntax:

INFSNZ f {,d {,a}}

Syntax:

INCFSZ f {,d {,a}}

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f) + 1 → dest,

skip if result ≠ 0

Operation:

(f) + 1 → dest,

skip if result = 0

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

0100

10da

ffff

0011

11da

ffff

Description:

The contents of register ‘f’ are

Description:

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is not ‘0’, the next

instruction, which is already fetched, is

discarded and a NOPis executed

instead, making it a two-cycle

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If the result is ‘0’, the next instruction,

which is already fetched, is discarded

and a NOPis executed instead, making

it a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1

Words:

Cycles:

1

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Decode

Read

register ‘f’

Process

Data

Write to

destination

If skip:

Q1

If skip:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

No

operation

No

operation

Example:

HERE

NZERO

ZERO

INCFSZ

:

CNT, 1, 0

Example:

HERE

ZERO

NZERO

INFSNZ REG, 1, 0

Before Instruction

PC

After Instruction

Before Instruction

PC

After Instruction

=

Address (HERE)

=

Address (HERE)

REG

If REG

PC

If REG

PC

=

REG + 1

0;

Address (NZERO)

0;

Address (ZERO)

CNT

If CNT

PC

If CNT

PC

=

CNT + 1

≠

=

≠

=

0;

Address (ZERO)

0;

Address (NZERO)

Preliminary

DS39689E-page 295

PIC18F4321 FAMILY

IORLW

Inclusive OR Literal with W

IORWF

Inclusive OR W with f

Syntax:

IORLW

k

Syntax:

IORWF f {,d {,a}}

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 ≤ k ≤ 255

(W) .OR. k → W

N, Z

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(W) .OR. (f) → dest

0000

1001

kkkk

Status Affected:

Encoding:

N, Z

The contents of W are ORed with the

eight-bit literal ‘k’. The result is placed in

W.

0001

00da

ffff

Description:

Inclusive OR W with register ‘f’. If ‘d’ is

‘0’, the result is placed in W. If ‘d’ is ‘1’,

the result is placed back in register ‘f’

(default).

Words:

Cycles:

1

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write to W

Example:

IORLW

35h

Before Instruction

W

=

9Ah

BFh

After Instruction

Words:

Cycles:

1

W

=

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Example:

IORWF RESULT, 0, 1

Before Instruction

RESULT =

13h

91h

W

=

After Instruction

RESULT =

13h

93h

W

=

DS39689E-page 296

Preliminary

PIC18F4321 FAMILY

LFSR

Load FSR

MOVF

Move f

Syntax:

LFSR f, k

Syntax:

MOVF f {,d {,a}}

Operands:

0 ≤ f ≤ 2

0 ≤ k ≤ 4095

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

k → FSRf

Operation:

f → dest

Status Affected:

Encoding:

None

Status Affected:

Encoding:

N, Z

1110

1111

1110

0000

00ff

k kkk

11

kkkk

0101

00da

ffff

7

Description:

The 12-bit literal ‘k’ is loaded into the

File Select Register pointed to by ‘f’.

Description:

The contents of register ‘f’ are moved to

a destination dependent upon the

status of ‘d’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

Location ‘f’ can be anywhere in the

256-byte bank.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read literal

‘k’ MSB

Process

Data

Write

literal ‘k’

MSB to

FSRfH

Decode

Read literal

‘k’ LSB

Process

Data

Write literal

‘k’ to FSRfL

Example:

LFSR 2, 3ABh

After Instruction

Words:

Cycles:

1

FSR2H

FSR2L

=

03h

ABh

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write W

Example:

MOVF

REG, 0, 0

Before Instruction

REG

W

=

22h

FFh

After Instruction

REG

W

=

22h

Preliminary

DS39689E-page 297

PIC18F4321 FAMILY

MOVFF

Move f to f

MOVLB

Move Literal to Low Nibble in BSR

Syntax:

MOVFF f ,f

Syntax:

MOVLW k

s

d

Operands:

0 ≤ f ≤ 4095

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 ≤ k ≤ 255

k → BSR

None

s

0 ≤ f ≤ 4095

d

Operation:

(f ) → f

s

d

Status Affected:

None

0000

0001

kkkk

Encoding:

1st word (source)

2nd word (destin.)

The eight-bit literal ‘k’ is loaded into the

Bank Select Register (BSR). The value of

BSR<7:4> always remains ‘0’, regardless

1100

1111

ffff

ffff_s

ffff_d

Description:

The contents of source register ‘f ’ are

of the value of k :k .

s

7 4

moved to destination register ‘f ’.

d

Words:

Cycles:

1

Location of source ‘f ’ can be anywhere

s

in the 4096-byte data space (000h to

FFFh) and location of destination ‘f ’

can also be anywhere from 000h to

FFFh.

Either source or destination can be W

(a useful special situation).

d

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write literal

‘k’ to BSR

MOVFFis particularly useful for

transferring a data memory location to a

peripheral register (such as the transmit

buffer or an I/O port).

The MOVFFinstruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

Example:

MOVLB

5

Before Instruction

BSR Register =

After Instruction

BSR Register =

02h

05h

Words:

Cycles:

2

2 (3)

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

(src)

Process

Data

No

operation

Decode

No

operation

No

operation

Write

register ‘f’

(dest)

No dummy

read

Example:

MOVFF

REG1, REG2

Before Instruction

REG1

REG2

=

33h

11h

After Instruction

REG1

REG2

=

33h

DS39689E-page 298

Preliminary

PIC18F4321 FAMILY

MOVLW

Move Literal to W

MOVWF

Move W to f

Syntax:

MOVLW

k

Syntax:

MOVWF f {,a}

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

0 ≤ k ≤ 255

k → W

None

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operation:

(W) → f

Status Affected:

Encoding:

None

0000

1110

kkkk

0110

111a

ffff

The eight-bit literal ‘k’ is loaded into W.

Description:

Move data from W to register ‘f’.

Location ‘f’ can be anywhere in the

256-byte bank.

1

Cycles:

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write to W

Example:

MOVLW

5Ah

After Instruction

W

=

5Ah

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write

register ‘f’

Example:

MOVWF

REG, 0

Before Instruction

W

REG

=

4Fh

FFh

After Instruction

W

REG

=

4Fh

Preliminary

DS39689E-page 299

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MULLW

Multiply Literal with W

MULWF

Multiply W with f

Syntax:

MULLW

k

Syntax:

MULWF f {,a}

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 ≤ k ≤ 255

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

(W) x k → PRODH:PRODL

Operation:

(W) x (f) → PRODH:PRODL

None

Status Affected:

Encoding:

None

0000

1101

kkkk

0000

001a

ffff

An unsigned multiplication is carried

out between the contents of W and the

8-bit literal ‘k’. The 16-bit result is

placed in the PRODH:PRODL register

pair. PRODH contains the high byte.

W is unchanged.

None of the Status flags are affected.

Note that neither overflow nor carry is

possible in this operation. A zero result

is possible but not detected.

Description:

An unsigned multiplication is carried

out between the contents of W and the

register file location ‘f’. The 16-bit

result is stored in the PRODH:PRODL

register pair. PRODH contains the

high byte. Both W and ‘f’ are

unchanged.

None of the Status flags are affected.

Note that neither overflow nor carry is

possible in this operation. A zero

result is possible but not detected.

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used

to select the GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write

registers

PRODH:

PRODL

f ≤ 95 (5Fh). See Section 24.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” for details.

Example:

MULLW

0C4h

Before Instruction

Words:

Cycles:

1

W

PRODH

PRODL

=

E2h

?

Q Cycle Activity:

Q1

After Instruction

Q2

Q3

Q4

W

PRODH

PRODL

=

E2h

ADh

08h

Decode

Read

register ‘f’

Process

Data

Write

registers

PRODH:

PRODL

Example:

MULWF

REG, 1

Before Instruction

W

REG

PRODH

PRODL

=

C4h

B5h

?

=

After Instruction

W

=

C4h

REG

PRODH

PRODL

=

B5h

8Ah

94h

DS39689E-page 300

Preliminary

PIC18F4321 FAMILY

NEGF

Negate f

NOP

No Operation

Syntax:

NEGF f {,a}

Syntax:

NOP

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operands:

Operation:

Status Affected:

Encoding:

None

No operation

None

Operation:

( f ) + 1 → f

Status Affected:

Encoding:

N, OV, C, DC, Z

0000

1111

0000

xxxx

0000

xxxx

0000

xxxx

0110

110a

ffff

Description:

Location ‘f’ is negated using two’s

complement. The result is placed in the

data memory location ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Description:

Words:

No operation.

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

No

Q4

Decode

No

operation

No

operation

Example:

None.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write

register ‘f’

Example:

NEGF

REG, 1

Before Instruction

REG

After Instruction

REG

=

0011 1010 [3Ah]

1100 0110 [C6h]

=

Preliminary

DS39689E-page 301

PIC18F4321 FAMILY

POP

Pop Top of Return Stack

PUSH

Push Top of Return Stack

Syntax:

POP

Syntax:

PUSH

Operands:

Operation:

Status Affected:

Encoding:

Description:

None

Operands:

Operation:

Status Affected:

Encoding:

Description:

None

(TOS) → bit bucket

(PC + 2) → TOS

None

0000

0110

0000

0101

The TOS value is pulled off the return

stack and is discarded. The TOS value

then becomes the previous value that

was pushed onto the return stack.

This instruction is provided to enable

the user to properly manage the return

stack to incorporate a software stack.

The PC + 2 is pushed onto the top of

the return stack. The previous TOS

value is pushed down on the stack.

This instruction allows implementing a

software stack by modifying TOS and

then pushing it onto the return stack.

Words:

Cycles:

1

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

PUSH

No

Decode

No

operation

POP TOS

value

No

operation

PC + 2 onto

return stack

operation

Example:

POP

Example:

PUSH

GOTO

NEW

Before Instruction

TOS

Stack (1 level down)

TOS

PC

=

345Ah

0124h

=

0031A2h

014332h

After Instruction

PC

=

0126h

345Ah

TOS

PC

=

014332h

NEW

Stack (1 level down)

DS39689E-page 302

Preliminary

PIC18F4321 FAMILY

RCALL

Relative Call

RESET

Reset

Syntax:

RCALL

n

Syntax:

RESET

None

Operands:

Operation:

-1024 ≤ n ≤ 1023

Operands:

Operation:

(PC) + 2 → TOS,

(PC) + 2 + 2n → PC

Reset all registers and flags that are

affected by a MCLR Reset.

Status Affected:

Encoding:

None

Status Affected:

Encoding:

All

1101

1nnn

nnnn

0000

1111

Description:

Subroutine call with a jump up to 1K

from the current location. First, return

address (PC + 2) is pushed onto the

stack. Then, add the 2’s complement

number ‘2n’ to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is a

two-cycle instruction.

Description:

This instruction provides a way to

execute a MCLR Reset in software.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Start

No

Reset

operation

Words:

Cycles:

1

2

Example:

RESET

Q Cycle Activity:

Q1

After Instruction

Registers =

Q2

Q3

Q4

Reset Value

Flags*

=

Decode

Read literal

‘n’

Process

Data

Write to PC

PUSH PCto

stack

No

operation

Example:

HERE

RCALL Jump

Before Instruction

PC

After Instruction

PC

TOS =

=

Address (HERE)

=

Address (Jump)

Address (HERE + 2)

Preliminary

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RETFIE

Return from Interrupt

RETLW

Return Literal to W

Syntax:

RETFIE {s}

Syntax:

RETLW k

Operands:

Operation:

s ∈ [0,1]

Operands:

Operation:

0 ≤ k ≤ 255

(TOS) → PC,

k → W,

1 → GIE/GIEH or PEIE/GIEL,

if s = 1

(TOS) → PC,

PCLATU, PCLATH are unchanged

(WS) → W,

(STATUSS) → STATUS,

(BSRS) → BSR,

Status Affected:

Encoding:

None

0000

1100

kkkk

PCLATU, PCLATH are unchanged

Description:

W is loaded with the eight-bit literal ‘k’.

The program counter is loaded from the

top of the stack (the return address).

The high address latch (PCLATH)

remains unchanged.

Status Affected:

Encoding:

GIE/GIEH, PEIE/GIEL.

0000

0001

000s

Description:

Return from interrupt. Stack is popped

and Top-of-Stack (TOS) is loaded into

the PC. Interrupts are enabled by

setting either the high or low priority

global interrupt enable bit. If ‘s’ = 1, the

contents of the shadow registers, WS,

STATUSS and BSRS, are loaded into

their corresponding registers, W,

Words:

Cycles:

1

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

POP PC

from stack,

Write to W

STATUS and BSR. If ‘s’ = 0, no update

of these registers occurs (default).

No

operation

No

operation

No

operation

No

operation

Words:

Cycles:

1

2

Q Cycle Activity:

Q1

Example:

Q2

Q3

Q4

CALL TABLE ; W contains table

; offset value

Decode

No

operation

No

operation

POP PC

from stack

; W now has

; table value

Set GIEH or

GIEL

:

No

operation

No

operation

No

operation

No

operation

TABLE

ADDWF PCL ; W = offset

RETLW k0

RETLW k1

; Begin table

;

Example:

RETFIE

1

:

After Interrupt

PC

W

=

TOS

WS

RETLW kn

; End of table

BSR

STATUS

GIE/GIEH, PEIE/GIEL

BSRS

STATUSS

1

Before Instruction

W

=

07h

After Instruction

W

=

value of kn

DS39689E-page 304

Preliminary

PIC18F4321 FAMILY

RETURN

Return from Subroutine

RLCF

Rotate Left f through Carry

Syntax:

RETURN {s}

Syntax:

RLCF f {,d {,a}}

Operands:

Operation:

s ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

(TOS) → PC,

if s = 1

(WS) → W,

Operation:

(f<n>) → dest<n + 1>,

(f<7>) → C,

(C) → dest<0>

(STATUSS) → STATUS,

(BSRS) → BSR,

PCLATU, PCLATH are unchanged

Status Affected:

Encoding:

C, N, Z

Status Affected:

Encoding:

None

0011

01da

ffff

0000

0001

001s

Description:

The contents of register ‘f’ are rotated

one bit to the left through the Carry

flag. If ‘d’ is ‘0’, the result is placed in

W. If ‘d’ is ‘1’, the result is stored back

in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used to

select the GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

Description:

Return from subroutine. The stack is

popped and the top of the stack (TOS)

is loaded into the program counter. If

‘s’= 1, the contents of the shadow

registers, WS, STATUSS and BSRS,

are loaded into their corresponding

registers, W, STATUS and BSR. If

‘s’ = 0, no update of these registers

occurs (default).

Words:

Cycles:

1

2

f ≤ 95 (5Fh). See Section 24.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” for details.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

No

operation

Process

Data

POP PC

from stack

register f

C

No

Words:

Cycles:

1

operation

Q Cycle Activity:

Q1

Example:

RETURN

Q2

Q3

Q4

After Instruction:

PC = TOS

Decode

Read

register ‘f’

Process

Data

Write to

destination

Example:

RLCF

REG, 0, 0

Before Instruction

REG

C

=

1110 0110

0

After Instruction

REG

=

1110 0110

W

C

=

1100 1100

1

Preliminary

DS39689E-page 305

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RLNCF

Rotate Left f (No Carry)

RRCF

Rotate Right f through Carry

Syntax:

RLNCF f {,d {,a}}

Syntax:

RRCF f {,d {,a}}

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f<n>) → dest<n + 1>,

(f<7>) → dest<0>

Operation:

(f<n>) → dest<n – 1>,

(f<0>) → C,

(C) → dest<7>

Status Affected:

Encoding:

N, Z

Status Affected:

Encoding:

C, N, Z

0100

01da

ffff

0011

00da

ffff

Description:

The contents of register ‘f’ are rotated

one bit to the left. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Description:

The contents of register ‘f’ are rotated

one bit to the right through the Carry

flag. If ‘d’ is ‘0’, the result is placed in W.

If ‘d’ is ‘1’, the result is placed back in

register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

register f

C

Words:

Cycles:

1

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q Cycle Activity:

Q1

Decode

Read

register ‘f’

Process

Data

Write to

destination

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Example:

RLNCF

REG, 1, 0

Before Instruction

REG

After Instruction

Example:

RRCF

REG, 0, 0

=

1010 1011

0101 0111

Before Instruction

REG

=

REG

C

=

1110 0110

0

After Instruction

REG

=

1110 0110

W

C

=

0111 0011

0

DS39689E-page 306

Preliminary

PIC18F4321 FAMILY

RRNCF

Rotate Right f (No Carry)

SETF

Set f

Syntax:

RRNCF f {,d {,a}}

Syntax:

SETF f {,a}

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operation:

FFh → f

Operation:

(f<n>) → dest<n – 1>,

(f<0>) → dest<7>

Status Affected:

Encoding:

None

0110

100a

ffff

Status Affected:

Encoding:

N, Z

Description:

The contents of the specified register

are set to FFh.

0100

00da

ffff

Description:

The contents of register ‘f’ are rotated

one bit to the right. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank will be

selected, overriding the BSR value. If ‘a’

is ‘1’, then the bank will be selected as

per the BSR value (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

register f

Decode

Read

register ‘f’

Process

Data

Write

register ‘f’

Words:

Cycles:

1

Example:

SETF

REG, 1

Q Cycle Activity:

Q1

Before Instruction

REG

After Instruction

REG

=

5Ah

FFh

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Example 1:

RRNCF

REG, 1, 0

Before Instruction

REG

After Instruction

REG

=

1101 0111

1110 1011

RRNCF REG, 0, 0

=

Example 2:

Before Instruction

W

REG

=

?

1101 0111

After Instruction

W

REG

=

1110 1011

1101 0111

Preliminary

DS39689E-page 307

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SLEEP

Enter Sleep mode

SUBFWB

Subtract f from W with Borrow

Syntax:

SLEEP

None

Syntax:

SUBFWB f {,d {,a}}

Operands:

Operation:

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

00h → WDT,

0 → WDT postscaler,

1 → TO,

Operation:

(W) – (f) – (C) → dest

0 → PD

Status Affected:

Encoding:

N, OV, C, DC, Z

Status Affected:

Encoding:

TO, PD

0101

01da

ffff

0000

0011

Description:

Subtract register ‘f’ and Carry flag

(borrow) from W (2’s complement

method). If ‘d’ is ‘0’, the result is stored

in W. If ‘d’ is ‘1’, the result is stored in

register ‘f’ (default).

Description:

The Power-Down status bit (PD) is

cleared. The Time-out status bit (TO)

is set. Watchdog Timer and its

postscaler are cleared.

The processor is put into Sleep mode

with the oscillator stopped.

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used

to select the GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f ≤ 95 (5Fh). See Section 24.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” for details.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

No

operation

Process

Data

Go to

Sleep

Example:

SLEEP

Words:

Cycles:

1

Before Instruction

TO

PD

=

?

Q Cycle Activity:

Q1

Q2

Q3

Q4

After Instruction

Decode

Read

register ‘f’

Process

Data

Write to

destination

TO

PD

=

1†

0

Example 1:

SUBFWB

REG, 1, 0

†

If WDT causes wake-up, this bit is cleared.

Before Instruction

REG

W

C

=

3

2

1

After Instruction

REG

W

C

=

FF

2

=

0

Z

0

1

N

; result is negative

Example 2:

Before Instruction

SUBFWB

REG, 0, 0

REG

W

=

2

5

1

C

After Instruction

REG

W

C

=

2

3

1

0

=

Z

N

0

; result is positive

Example 3:

Before Instruction

SUBFWB

REG, 1, 0

REG

W

=

1

2

0

C

After Instruction

REG

W

C

=

0

2

1

0

=

Z

; result is zero

N

DS39689E-page 308

Preliminary

PIC18F4321 FAMILY

SUBLW

Subtract W from Literal

SUBWF

Subtract W from f

Syntax:

SUBLW

k

Syntax:

SUBWF f {,d {,a}}

Operands:

Operation:

Status Affected:

Encoding:

Description

0 ≤ k ≤ 255

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

k – (W) → W

N, OV, C, DC, Z

Operation:

(f) – (W) → dest

0000

1000

kkkk

Status Affected:

Encoding:

N, OV, C, DC, Z

W is subtracted from the eight-bit

literal ‘k’. The result is placed in W.

0101

11da

ffff

Description:

Subtract W from register ‘f’ (2’s

complement method). If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used

to select the GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

f ≤ 95 (5Fh). See Section 24.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” for details.

Decode

Read

literal ‘k’

Process

Data

Write to W

Example 1:

SUBLW 02h

Before Instruction

W

C

=

01h

?

After Instruction

W

C

Z

=

01h

=

1

0

; result is positive

N

Words:

Cycles:

1

Example 2:

SUBLW 02h

Before Instruction

Q Cycle Activity:

Q1

W

C

=

02h

?

Q2

Q3

Q4

After Instruction

Decode

Read

register ‘f’

Process

Data

Write to

destination

W

C

Z

=

00h

=

1

0

; result is zero

N

Example 1:

SUBWF

REG, 1, 0

Before Instruction

Example 3:

Before Instruction

SUBLW 02h

REG

W

C

=

3

2

?

=

W

C

=

03h

?

After Instruction

REG

W

C

=

1

2

1

0

W

C

Z

=

FFh ; (2’s complement)

=

0

1

; result is negative

; result is positive

Z

N

Example 2:

SUBWF

REG, 0, 0

Before Instruction

REG

W

=

2

?

C

After Instruction

REG

W

C

=

2

0

1

0

=

; result is zero

Z

N

Example 3:

Before Instruction

SUBWF

REG, 1, 0

REG

W

=

1

2

?

C

After Instruction

REG

W

C

=

FFh ;(2’s complement)

2

0

1

=

; result is negative

Z

N

Preliminary

DS39689E-page 309

PIC18F4321 FAMILY

SUBWFB

Subtract W from f with Borrow

SWAPF

Swap f

Syntax:

SUBWFB f {,d {,a}}

Syntax:

SWAPF f {,d {,a}}

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(f) – (W) – (C) → dest

Operation:

(f<3:0>) → dest<7:4>,

(f<7:4>) → dest<3:0>

Status Affected:

Encoding:

N, OV, C, DC, Z

0101

10da

ffff

Status Affected:

Encoding:

None

Description:

Subtract W and the Carry flag (borrow)

from register ‘f’ (2’s

complement method). If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’

(default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

0011

10da

ffff

Description:

The upper and lower nibbles of register

‘f’ are exchanged. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result is

placed in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

1

Words:

Cycles:

1

Cycles:

Q Cycle Activity:

Q1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Decode

Read

register ‘f’

Process

Data

Write to

destination

Example 1:

SUBWFB REG, 1, 0

Before Instruction

Example:

SWAPF

REG, 1, 0

REG

W

=

19h

0Dh

1

(0001 1001)

(0000 1101)

Before Instruction

C

REG

=

53h

35h

After Instruction

REG

=

0Ch

0Dh

1

0

(0000 1011)

(0000 1101)

REG

=

W

=

C

Z

N

; result is positive

Example 2:

Before Instruction

SUBWFB REG, 0, 0

REG

W

=

1Bh

1Ah

0

(0001 1011)

(0001 1010)

C

After Instruction

REG

W

C

=

1Bh

00h

1

(0001 1011)

=

Z

1

; result is zero

N

0

Example 3:

Before Instruction

SUBWFB REG, 1, 0

REG

=

03h

0Eh

1

(0000 0011)

(0000 1101)

W

C

After Instruction

REG

=

F5h

(1111 0100)

; [2’s comp]

W

=

0Eh

0

1

(0000 1101)

C

Z

N

; result is negative

DS39689E-page 310

Preliminary

PIC18F4321 FAMILY

TBLRD

Table Read

TBLRD

Table Read (Continued)

Syntax:

TBLRD ( *; *+; *-; +*)

None

Example 1:

TBLRD *+ ;

Operands:

Operation:

Before Instruction

TABLAT

TBLPTR

MEMORY (00A356h)

=

55h

00A356h

34h

if TBLRD *,

(Prog Mem (TBLPTR)) → TABLAT;

TBLPTR – No Change;

if TBLRD *+,

(Prog Mem (TBLPTR)) → TABLAT;

(TBLPTR) + 1 → TBLPTR;

if TBLRD *-,

(Prog Mem (TBLPTR)) → TABLAT;

(TBLPTR) – 1 → TBLPTR;

if TBLRD +*,

(TBLPTR) + 1 → TBLPTR;

(Prog Mem (TBLPTR)) → TABLAT;

After Instruction

TABLAT

TBLPTR

=

34h

00A357h

Example 2:

TBLRD +* ;

Before Instruction

TABLAT

TBLPTR

MEMORY (01A357h)

MEMORY (01A358h)

After Instruction

=

AAh

01A357h

12h

34h

TABLAT

TBLPTR

=

34h

01A358h

Status Affected: None

Encoding:

0000

10nn

nn=0 *

=1 *+

=2 *-

=3 +*

Description:

This instruction is used to read the contents

of Program Memory (P.M.). To address the

program memory, a pointer called Table

Pointer (TBLPTR) is used.

The TBLPTR (a 21-bit pointer) points to

each byte in the program memory. TBLPTR

has a 2-Mbyte address range.

TBLPTR[0] = 0: LeastSignificantByte

of Program Memory

Word

TBLPTR[0] = 1: Most Significant Byte

of Program Memory

Word

The TBLRDinstruction can modify the value

of TBLPTR as follows:

•

no change

post-increment

post-decrement

pre-increment

Words:

Cycles:

1

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

No

operation

No

No operation

No

No operation

operation (Read Program operation (Write TABLAT)

Memory)

Preliminary

DS39689E-page 311

PIC18F4321 FAMILY

TBLWT

Table Write

TBLWT

Table Write (Continued)

Syntax:

TBLWT ( *; *+; *-; +*)

None

Example 1:

TBLWT *+;

Operands:

Operation:

Before Instruction

if TBLWT*,

TABLAT

TBLPTR

HOLDING REGISTER

(00A356h)

=

55h

00A356h

(TABLAT) → Holding Register;

TBLPTR – No Change;

if TBLWT*+,

(TABLAT) → Holding Register;

(TBLPTR) + 1 → TBLPTR;

if TBLWT*-,

(TABLAT) → Holding Register;

(TBLPTR) – 1 → TBLPTR;

if TBLWT+*,

(TBLPTR) + 1 → TBLPTR;

(TABLAT) → Holding Register;

=

FFh

After Instructions (table write completion)

TABLAT

TBLPTR

HOLDING REGISTER

(00A356h)

=

55h

00A357h

=

55h

Example 2:

TBLWT +*;

Before Instruction

TABLAT

TBLPTR

HOLDING REGISTER

(01389Ah)

HOLDING REGISTER

(01389Bh)

=

34h

01389Ah

Status Affected: None

=

FFh

Encoding:

0000

11nn

nn=0 *

=1 *+

=2 *-

=3 +*

After Instruction (table write completion)

TABLAT

TBLPTR

=

34h

01389Bh

HOLDING REGISTER

(01389Ah)

HOLDING REGISTER

(01389Bh)

Description:

This instruction uses the 3 LSBs of

TBLPTR to determine which of the

8 holding registers the TABLAT is written

to. The holding registers are used to

program the contents of Program

Memory (P.M.). (Refer to Section 6.0

“Flash Program Memory” for additional

details on programming Flash memory.)

The TBLPTR (a 21-bit pointer) points to

each byte in the program memory.

TBLPTR has a 2-Mbyte address range.

The LSb of the TBLPTR selects which

byte of the program memory location to

access.

=

FFh

34h

TBLPTR[0] = 0: Least Significant

Byte of Program

Memory Word

TBLPTR[0] = 1: Most Significant

Byte of Program

Memory Word

The TBLWT instruction can modify the

value of TBLPTR as follows:

•

no change

post-increment

post-decrement

pre-increment

Words:

1

2

Cycles:

Q Cycle Activity:

Q1

Q2

No

Q3

No

Q4

No

Decode

operation operation operation

No

No No No

operation operation operation operation

(Read

TABLAT)

(Write to

Holding

Register )

DS39689E-page 312

Preliminary

PIC18F4321 FAMILY

TSTFSZ

Test f, Skip if 0

XORLW

Exclusive OR Literal with W

Syntax:

TSTFSZ f {,a}

Syntax:

XORLW k

Operands:

0 ≤ f ≤ 255

a ∈ [0,1]

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 ≤ k ≤ 255

(W) .XOR. k → W

N, Z

Operation:

skip if f = 0

Status Affected:

Encoding:

None

0000

1010

kkkk

0110

011a

ffff

The contents of W are XORed with

the 8-bit literal ‘k’. The result is placed

in W.

Description:

If ‘f’ = 0, the next instruction fetched

during the current instruction execution

is discarded and a NOPis executed,

making this a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write to W

Example:

XORLW

0AFh

Before Instruction

W

=

B5h

1Ah

Words:

Cycles:

1

After Instruction

1(2)

W

=

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

No

operation

If skip:

Q1

Q2

Q3

Q4

No

operation

If skip and followed by 2-word instruction:

Q1

Q2

Q3

Q4

No

operation

No

operation

Example:

HERE

NZERO

ZERO

TSTFSZ CNT, 1

:

Before Instruction

PC

=

Address (HERE)

After Instruction

If CNT

PC

If CNT

PC

=

≠

=

00h,

Address (ZERO)

00h,

Address (NZERO)

Preliminary

DS39689E-page 313

PIC18F4321 FAMILY

XORWF

Exclusive OR W with f

Syntax:

XORWF f {,d {,a}}

Operands:

0 ≤ f ≤ 255

d ∈ [0,1]

a ∈ [0,1]

Operation:

(W) .XOR. (f) → dest

Status Affected:

Encoding:

N, Z

0001

10da

ffff

Description:

Exclusive OR the contents of W with

register ‘f’. If ‘d’ is ‘0’, the result is stored

in W. If ‘d’ is ‘1’, the result is stored back

in the register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f ≤ 95 (5Fh). See

Section 24.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Example:

XORWF

REG, 1, 0

Before Instruction

REG

W

=

AFh

B5h

After Instruction

REG

W

=

1Ah

B5h

DS39689E-page 314

Preliminary

PIC18F4321 FAMILY

A summary of the instructions in the extended instruction

set is provided in Table 24-3. Detailed descriptions are

provided in Section 24.2.2 “Extended Instruction

Set”. The opcode field descriptions in Table 24-1

(page 274) apply to both the standard and extended

PIC18 instruction sets.

24.2 Extended Instruction Set

In addition to the standard 75 instructions of the PIC18

instruction set, PIC18F4321 family devices also

provide an optional extension to the core CPU function-

ality. The added features include eight additional

instructions that augment indirect and indexed

addressing operations and the implementation of

Indexed Literal Offset Addressing mode for many of the

standard PIC18 instructions.

Note:

The instruction set extension and the

Indexed Literal Offset Addressing mode

were designed for optimizing applications

written in C; the user may likely never use

these instructions directly in assembler.

The syntax for these commands is

provided as a reference for users who may

be reviewing code that has been

generated by a compiler.

The additional features of the extended instruction set

are disabled by default. To enable them, users must set

the XINST Configuration bit.

The instructions in the extended set (with the exception

of CALLW, MOVSFand MOVSS) can all be classified as

literal operations, which either manipulate the File

Select Registers, or use them for indexed addressing.

Two of the instructions, ADDFSR and SUBFSR, each

have an additional special instantiation for using FSR2.

These versions (ADDULNK and SUBULNK) allow for

automatic return after execution.

24.2.1

EXTENDED INSTRUCTION SYNTAX

Most of the extended instructions use indexed

arguments, using one of the File Select Registers and

some offset to specify a source or destination register.

When an argument for an instruction serves as part of

indexed addressing, it is enclosed in square brackets

(“[ ]”). This is done to indicate that the argument is used

as an index or offset. The MPASM™ Assembler will

flag an error if it determines that an index or offset value

is not bracketed.

The extended instructions are specifically implemented

to optimize re-entrant program code (that is, code that

is recursive or that uses a software stack) written in

high-level languages, particularly C. Among other

things, they allow users working in high-level

languages to perform certain operations on data

structures more efficiently. These include:

When the extended instruction set is enabled, brackets

are also used to indicate index arguments in byte-

oriented and bit-oriented instructions. This is in addition

to other changes in their syntax. For more details, see

Section 24.2.3.1 “Extended Instruction Syntax with

Standard PIC18 Commands”.

• dynamic allocation and deallocation of software

stack space when entering and leaving

subroutines

• function pointer invocation

• software Stack Pointer manipulation

Note:

In the past, square brackets have been

used to denote optional arguments in the

PIC18 and earlier instruction sets. In this

text and going forward, optional

arguments are denoted by braces (“{ }”).

• manipulation of variables located in a software

stack

TABLE 24-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET

16-Bit Instruction Word

MSb LSb

Mnemonic,

Operands

Status

Affected

Description

Cycles

ADDFSR

ADDULNK

CALLW

f, k

k

Add literal to FSR

Add literal to FSR2 and return

Call subroutine using WREG

1

2

1110 1000 ffkk kkkk

1110 1000 11kk kkkk

0000 0000 0001 0100

1110 1011 0zzz zzzz

1111 ffff ffff ffff

1110 1011 1zzz zzzz

1111 xxxx xzzz zzzz

1110 1010 kkkk kkkk

None

MOVSF

z_s, f_dMove z_s(source) to 1st word

f_d(destination)2nd word

z_s, z_dMove z_s(source) to 1st word

z_d(destination)2nd word

MOVSS

PUSHL

2

1

None

k

Store literal at FSR2,

decrement FSR2

SUBFSR

SUBULNK

f, k

k

Subtract literal from FSR

Subtract literal from FSR2 and

return

1

2

1110 1001 ffkk kkkk

1110 1001 11kk kkkk

None

Preliminary

DS39689E-page 315

PIC18F4321 FAMILY

24.2.2

EXTENDED INSTRUCTION SET

ADDFSR

Add Literal to FSR

ADDULNK

Add Literal to FSR2 and Return

Syntax:

ADDFSR f, k

Syntax:

ADDULNK k

Operands:

0 ≤ k ≤ 63

f ∈ [ 0, 1, 2 ]

FSR(f) + k → FSR(f)

None

Operands:

Operation:

0 ≤ k ≤ 63

FSR2 + k → FSR2,

(TOS) → PC

None

Operation:

Status Affected:

Encoding:

Status Affected:

Encoding:

1110

1000

ffkk

kkkk

1110

1000

11kk

kkkk

Description:

The 6-bit literal ‘k’ is added to the

contents of the FSR specified by ‘f’.

Description:

The 6-bit literal ‘k’ is added to the

contents of FSR2. A RETURNis then

executed by loading the PC with the

TOS.

Words:

1

Cycles:

The instruction takes two cycles to

execute; a NOPis performed during

the second cycle.

This may be thought of as a special

case of the ADDFSRinstruction,

where f = 3 (binary ‘11’); it operates

only on FSR2.

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write to

FSR

ADDFSR 2, 23h

Example:

Words:

Cycles:

1

2

Before Instruction

FSR2

After Instruction

FSR2

=

03FFh

0422h

Q Cycle Activity:

Q1

=

Q2

Q3

Q4

Decode

Read

literal ‘k’

Process

Data

Write to

FSR

No

Operation

ADDULNK 23h

Example:

Before Instruction

FSR2

PC

=

03FFh

0100h

After Instruction

FSR2

PC

=

0422h

(TOS)

Note:

All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in

symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).

DS39689E-page 316

Preliminary

PIC18F4321 FAMILY

CALLW

Subroutine Call Using WREG

MOVSF

Move Indexed to f

Syntax:

CALLW

None

Syntax:

MOVSF [z ], f

s

d

Operands:

Operation:

Operands:

0 ≤ z ≤ 127

s

0 ≤ f ≤ 4095

d

(PC + 2) → TOS,

(W) → PCL,

Operation:

((FSR2) + z ) → f

s

d

(PCLATH) → PCH,

(PCLATU) → PCU

Status Affected:

None

Encoding:

1st word (source)

2nd word (destin.)

Status Affected:

Encoding:

None

1110

1111

1011

ffff

0zzz

ffff

zzzz

ffff

s

0000

0001

0100

d

Description

First, the return address (PC + 2) is

pushed onto the return stack. Next, the

contents of W are written to PCL; the

existing value is discarded. Then, the

contents of PCLATH and PCLATU are

latched into PCH and PCU,

respectively. The second cycle is

executed as a NOPinstruction while the

new next instruction is fetched.

Description:

The contents of the source register are

moved to destination register ‘f ’. The

d

actual address of the source register is

determined by adding the 7-bit literal

offset ‘z ’ in the first word to the value of

s

FSR2. The address of the destination

register is specified by the 12-bit literal

‘f ’ in the second word. Both addresses

d

can be anywhere in the 4096-byte data

space (000h to FFFh).

The MOVSFinstruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

If the resultant source address points to

an indirect addressing register, the

value returned will be 00h.

Unlike CALL, there is no option to

update W, Status or BSR.

Words:

Cycles:

1

2

Q Cycle Activity:

Q1

Q2

Q3

Q4

Words:

Cycles:

2

Decode

Read

WREG

PUSH PC to

stack

No

operation

No

operation

No

operation

No

operation

No

operation

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Determine

Read

source addr source addr source reg

Example:

HERE

CALLW

Decode

No

operation

No

operation

Write

register ‘f’

(dest)

Before Instruction

PC

=

address (HERE)

PCLATH =

PCLATU =

10h

00h

06h

No dummy

read

W

=

After Instruction

PC

TOS

=

001006h

address (HERE + 2)

Example:

MOVSF

[05h], REG2

PCLATH =

PCLATU =

10h

00h

06h

Before Instruction

FSR2

=

80h

33h

W

=

Contents

of 85h

REG2

=

11h

After Instruction

FSR2

=

80h

Contents

of 85h

REG2

=

33h

Preliminary

DS39689E-page 317

PIC18F4321 FAMILY

MOVSS

Move Indexed to Indexed

PUSHL

Store Literal at FSR2, Decrement FSR2

Syntax:

MOVSS [z ], [z ]

Syntax:

PUSHL k

s

d

Operands:

0 ≤ z ≤ 127

s

Operands:

Operation:

0 ≤ k ≤ 255

0 ≤ z ≤ 127

d

k → (FSR2),

FSR2 – 1 → FSR2

Operation:

((FSR2) + z ) → ((FSR2) + z )

s d

Status Affected:

None

Status Affected: None

Encoding:

1st word (source)

2nd word (dest.)

Encoding:

1111

1010

kkkk

1110

1111

1011

xxxx

1zzz

xzzz

zzzz

s

d

Description:

The 8-bit literal ‘k’ is written to the data

memory address specified by FSR2. FSR2

is decremented by 1 after the operation.

This instruction allows users to push values

onto a software stack.

Description

The contents of the source register are

moved to the destination register. The

addresses of the source and destination

registers are determined by adding the

7-bit literal offsets ‘z ’ or ‘z ’,

Words:

Cycles:

1

s

d

respectively, to the value of FSR2. Both

registers can be located anywhere in

the 4096-byte data memory space

(000h to FFFh).

Q Cycle Activity:

Q1

Q2

Q3

Q4

The MOVSSinstruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

Decode

Read ‘k’

Process

data

Write to

destination

If the resultant source address points to

an indirect addressing register, the

value returned will be 00h. If the

resultant destination address points to

an indirect addressing register, the

instruction will execute as a NOP.

Example:

PUSHL 08h

Before Instruction

FSR2H:FSR2L

Memory (01ECh)

=

01ECh

00h

Words:

2

After Instruction

FSR2H:FSR2L

Memory (01ECh)

=

01EBh

08h

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Determine

Read

source addr source addr source reg

Decode

Determine

dest addr

Determine

dest addr

Write

to dest reg

Example:

MOVSS [05h], [06h]

Before Instruction

FSR2

=

80h

33h

11h

Contents

of 85h

Contents

of 86h

After Instruction

FSR2

=

80h

33h

Contents

of 85h

Contents

of 86h

DS39689E-page 318

Preliminary

PIC18F4321 FAMILY

SUBFSR

Subtract Literal from FSR

SUBULNK

Subtract Literal from FSR2 and Return

Syntax:

SUBFSR f, k

0 ≤ k ≤ 63

f ∈ [ 0, 1, 2 ]

FSR(f – k) → FSR(f)

None

Syntax:

SUBULNK k

Operands:

Operation:

0 ≤ k ≤ 63

FSR2 – k → FSR2

(TOS) → PC

Operation:

Status Affected:

Encoding:

Status Affected: None

1110

1001

ffkk

kkkk

Encoding:

1110

1001

11kk

kkkk

Description:

The 6-bit literal ‘k’ is subtracted from

the contents of the FSR specified

by ‘f’.

Description:

The 6-bit literal ‘k’ is subtracted from the

contents of the FSR2. A RETURNis then

executed by loading the PC with the TOS.

The instruction takes two cycles to

execute; a NOPis performed during the

second cycle.

This may be thought of as a special case of

the SUBFSRinstruction, where f = 3 (binary

‘11’); it operates only on FSR2.

Words:

1

Cycles:

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Words:

1

2

Cycles:

Q Cycle Activity:

Q1

Example:

SUBFSR 2, 23h

03FFh

Q2

Q3

Q4

Before Instruction

FSR2

After Instruction

FSR2

Decode

Read

register ‘f’

Process

Data

Write to

destination

=

No

Operation

No

Operation

No

Operation

No

Operation

=

03DCh

Example:

SUBULNK 23h

Before Instruction

FSR2

PC

=

03FFh

0100h

After Instruction

FSR2

PC

=

03DCh

(TOS)

Preliminary

DS39689E-page 319

PIC18F4321 FAMILY

24.2.3

BYTE-ORIENTED AND

BIT-ORIENTED INSTRUCTIONS IN

INDEXED LITERAL OFFSET MODE

24.2.3.1

Extended Instruction Syntax with

Standard PIC18 Commands

When the extended instruction set is enabled, the file

register argument, ‘f’, in the standard byte-oriented and

bit-oriented commands is replaced with the literal offset

value, ‘k’. As already noted, this occurs only when ‘f’ is

less than or equal to 5Fh. When an offset value is used,

it must be indicated by square brackets (“[ ]”). As with

the extended instructions, the use of brackets indicates

to the compiler that the value is to be interpreted as an

index or an offset. Omitting the brackets, or using a

value greater than 5Fh within brackets, will generate an

error in the MPASM Assembler.

Note: Enabling the PIC18 instruction set

extension may cause legacy applications

to behave erratically or fail entirely.

In addition to eight new commands in the extended set,

enabling the extended instruction set also enables

Indexed Literal Offset Addressing mode (Section 5.5.1

“Indexed Addressing with Literal Offset”). This has

a significant impact on the way that many commands of

the standard PIC18 instruction set are interpreted.

When the extended set is disabled, addresses embed-

ded in opcodes are treated as literal memory locations:

either as a location in the Access Bank (‘a’ = 0) or in a

GPR bank designated by the BSR (‘a’ = 1). When the

extended instruction set is enabled and ‘a’ = 0,

however, a file register argument of 5Fh or less is

interpreted as an offset from the pointer value in FSR2

and not as a literal address. For practical purposes, this

means that all instructions that use the Access RAM bit

as an argument – that is, all byte-oriented and bit-

oriented instructions, or almost half of the core PIC18

If the index argument is properly bracketed for Indexed

Literal Offset Addressing mode, the Access RAM

argument is never specified; it will automatically be

assumed to be ‘0’. This is in contrast to standard

operation (extended instruction set disabled) when ‘a’

is set on the basis of the target address. Declaring the

Access RAM bit in this mode will also generate an error

in the MPASM Assembler.

The destination argument, ‘d’, functions as before.

In the latest versions of the MPASM assembler,

language support for the extended instruction set must

be explicitly invoked. This is done with either the

command line option, /y, or the PE directive in the

source listing.

instructions

– may behave differently when the

extended instruction set is enabled.

When the content of FSR2 is 00h, the boundaries of the

Access RAM are essentially remapped to their original

values. This may be useful in creating backward

compatible code. If this technique is used, it may be

necessary to save the value of FSR2 and restore it

when moving back and forth between C and assembly

routines in order to preserve the Stack Pointer. Users

must also keep in mind the syntax requirements of the

extended instruction set (see Section 24.2.3.1

“Extended Instruction Syntax with Standard PIC18

Commands”).

24.2.4

CONSIDERATIONS WHEN

ENABLING THE EXTENDED

INSTRUCTION SET

It is important to note that the extensions to the instruc-

tion set may not be beneficial to all users. In particular,

users who are not writing code that uses a software

stack may not benefit from using the extensions to the

instruction set.

Although the Indexed Literal Offset Addressing mode

can be very useful for dynamic stack and pointer

manipulation, it can also be very annoying if a simple

arithmetic operation is carried out on the wrong

register. Users who are accustomed to the PIC18

programming must keep in mind that, when the

extended instruction set is enabled, register addresses

of 5Fh or less are used for Indexed Literal Offset

Addressing mode.

Additionally, the Indexed Literal Offset Addressing

mode may create issues with legacy applications

written to the PIC18 assembler. This is because

instructions in the legacy code may attempt to address

registers in the Access Bank below 5Fh. Since these

addresses are interpreted as literal offsets to FSR2

when the instruction set extension is enabled, the

application may read or write to the wrong data

addresses.

Representative examples of typical byte-oriented and

bit-oriented instructions in the Indexed Literal Offset

Addressing mode are provided on the following page to

show how execution is affected. The operand

conditions shown in the examples are applicable to all

instructions of these types.

When porting an application to the PIC18F4321 family,

it is very important to consider the type of code. A large,

re-entrant application that is written in ‘C’ and would

benefit from efficient compilation will do well when

using the instruction set extensions. Legacy applica-

tions that heavily use the Access Bank will most likely

not benefit from using the extended instruction set.

DS39689E-page 320

Preliminary

PIC18F4321 FAMILY

ADD W to Indexed

(Indexed Literal Offset mode)

Bit Set Indexed

(Indexed Literal Offset mode)

ADDWF

BSF

Syntax:

ADDWF

[k] {,d}

Syntax:

BSF [k], b

Operands:

0 ≤ k ≤ 95

d ∈ [0,1]

Operands:

0 ≤ f ≤ 95

0 ≤ b ≤ 7

Operation:

(W) + ((FSR2) + k) → dest

Operation:

1 → ((FSR2) + k)

Status Affected:

Encoding:

N, OV, C, DC, Z

Status Affected:

Encoding:

None

0010

01d0

kkkk

1000

bbb0

kkkk

Description:

The contents of W are added to the

contents of the register indicated by

FSR2, offset by the value ‘k’.

If ‘d’ is ‘0’, the result is stored in W. If ‘d’

is ‘1’, the result is stored back in

register ‘f’ (default).

Description:

Bit ‘b’ of the register indicated by FSR2,

offset by the value ‘k’, is set.

Words:

1

Cycles:

Q Cycle Activity:

Q1

Words:

Cycles:

1

Q2

Q3

Q4

Decode

Read

register ‘f’

Process

Data

Write to

destination

Q Cycle Activity:

Q1

Q2

Q3

Q4

Example:

BSF

[FLAG_OFST], 7

Decode

Read ‘k’

Process

Data

Write to

destination

Before Instruction

FLAG_OFST

FSR2

Contents

of 0A0Ah

=

0Ah

0A00h

Example:

ADDWF

[OFST], 0

=

55h

D5h

Before Instruction

After Instruction

W

OFST

FSR2

=

17h

2Ch

0A00h

Contents

of 0A0Ah

=

Contents

of 0A2Ch

=

20h

After Instruction

W

=

37h

20h

Set Indexed

(Indexed Literal Offset mode)

Contents

of 0A2Ch

SETF

Syntax:

SETF [k]

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 ≤ k ≤ 95

FFh → ((FSR2) + k)

None

0110

1000

kkkk

The contents of the register indicated by

FSR2, offset by ‘k’, are set to FFh.

Words:

Cycles:

1

Q Cycle Activity:

Q1

Q2

Q3

Q4

Decode

Read ‘k’

Process

Data

Write

register

Example:

SETF

[OFST]

2Ch

Before Instruction

OFST

=

FSR2

0A00h

Contents

of 0A2Ch

=

00h

After Instruction

Contents

of 0A2Ch

=

FFh

Preliminary

DS39689E-page 321

PIC18F4321 FAMILY

To develop software for the extended instruction set,

the user must enable support for the instructions and

the Indexed Addressing mode in their language tool(s).

Depending on the environment being used, this may be

done in several ways:

24.2.5

SPECIAL CONSIDERATIONS WITH

MICROCHIP MPLAB^®IDE TOOLS

The latest versions of Microchip’s software tools have

been designed to fully support the extended instruction

set of the PIC18F4321 family family of devices. This

includes the MPLAB C18

assembly language and

Development Environment (IDE).

• A menu option, or dialog box within the

environment, that allows the user to configure the

language tool and its settings for the project

C

compiler, MPASM

MPLAB Integrated

• A command line option

When selecting target device for software

a

• A directive in the source code

development, MPLAB IDE will automatically set default

Configuration bits for that device. The default setting for

the XINST Configuration bit is ‘0’, disabling the

extended instruction set and Indexed Literal Offset

Addressing mode. For proper execution of applications

developed to take advantage of the extended

instruction set, XINST must be set during

programming.

These options vary between different compilers,

assemblers and development environments. Users are

encouraged to review the documentation accompany-

ing their development systems for the appropriate

information.

DS39689E-page 322

Preliminary

PIC18F4321 FAMILY

25.1 MPLAB Integrated Development

Environment Software

25.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers are supported with a full

range of hardware and software development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• Assemblers/Compilers/Linkers

- MPASM^TMAssembler

• A single graphical interface to all debugging tools

- Simulator

- MPLAB C18 and MPLAB C30 C Compilers

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- Programmer (sold separately)

- Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

• Emulators

• Customizable data windows with direct edit of

contents

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debugger

• High-level source code debugging

• Visual device initializer for easy register

initialization

- MPLAB ICD 2

• Mouse over variable inspection

• Device Programmers

• Drag and drop variables from source to watch

windows

- PICSTART^®Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Extensive on-line help

• Integration of select third party tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

The MPLAB IDE allows you to:

• Edit your source files (either assembly or C)

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools

(automatically updates all project information)

• Debug using:

- Source files (assembly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

Preliminary

DS39689E-page 323

PIC18F4321 FAMILY

25.2 MPASM Assembler

25.5 MPLAB ASM30 Assembler, Linker

and Librarian

The MPASM Assembler is a full-featured, universal

macro assembler for all PIC MCUs.

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• User-defined macros to streamline

assembly code

• Rich directive set

• Conditional assembly for multi-purpose

source files

• Flexible macro language

• MPLAB IDE compatibility

• Directives that allow complete control over the

assembly process

25.6 MPLAB SIM Software Simulator

25.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC^®DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI

C

compilers for

Microchip’s PIC18 family of microcontrollers and the

dsPIC30, dsPIC33 and PIC24 family of digital signal

controllers. These compilers provide powerful integra-

tion capabilities, superior code optimization and ease

of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

25.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

DS39689E-page 324

Preliminary

PIC18F4321 FAMILY

25.7 MPLAB ICE 2000

High-Performance

25.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash PIC

MCUs and can be used to develop for these and other

PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes

the in-circuit debugging capability built into the Flash

devices. This feature, along with Microchip’s In-Circuit

Serial Programming^TM(ICSP^TM) protocol, offers cost-

effective, in-circuit Flash debugging from the graphical

user interface of the MPLAB Integrated Development

Environment. This enables a designer to develop and

debug source code by setting breakpoints, single step-

ping and watching variables, and CPU status and

peripheral registers. Running at full speed enables

testing hardware and applications in real time. MPLAB

ICD 2 also serves as a development programmer for

selected PIC devices.

In-Circuit Emulator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PIC

microcontrollers. Software control of the MPLAB ICE

2000 In-Circuit Emulator is advanced by the MPLAB

Integrated Development Environment, which allows

editing, building, downloading and source debugging

from a single environment.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing features. Interchangeable processor modules allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PIC microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft^®Windows^®32-bit operating system were

chosen to best make these features available in a

simple, unified application.

25.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an SD/MMC card for

file storage and secure data applications.

25.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC^®and MCU devices. It debugs and

programs PIC^®and dsPIC^®Flash microcontrollers with

the easy-to-use, powerful graphical user interface of the

MPLAB Integrated Development Environment (IDE),

included with each kit.

The MPLAB REAL ICE probe is connected to the design

engineer’s PC using a high-speed USB 2.0 interface and

is connected to the target with either a connector

compatible with the popular MPLAB ICD 2 system

(RJ11) or with the new high speed, noise tolerant, low-

voltage differential signal (LVDS) interconnection

(CAT5).

MPLAB REAL ICE is field upgradeable through future

firmware downloads in MPLAB IDE. In upcoming

releases of MPLAB IDE, new devices will be supported,

and new features will be added, such as software break-

points and assembly code trace. MPLAB REAL ICE

offers significant advantages over competitive emulators

including low-cost, full-speed emulation, real-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables.

Preliminary

DS39689E-page 325

PIC18F4321 FAMILY

25.11 PICSTART Plus Development

Programmer

25.13 Demonstration, Development and

Evaluation Boards

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PIC devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76X, may be supported with an adapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

25.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer and selected Flash device debugger with

an easy-to-use interface for programming many of

Microchip’s baseline, mid-range and PIC18F families of

Flash memory microcontrollers. The PICkit 2 Starter Kit

includes a prototyping development board, twelve

sequential lessons, software and HI-TECH’s PICC™

Lite C compiler, and is designed to help get up to speed

quickly using PIC^®microcontrollers. The kit provides

everything needed to program, evaluate and develop

applications using Microchip’s powerful, mid-range

Flash memory family of microcontrollers.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

®

for analog filter design, KEELOQ security ICs, CAN,

IrDA^®, PowerSmart^®battery management, SEEVAL^®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

and the latest “Product Selector Guide” (DS00148) for

the complete list of demonstration, development and

evaluation kits.

DS39689E-page 326

Preliminary

PIC18F4321 FAMILY

26.0 ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

Ambient temperature under bias.............................................................................................................-40°C to +125°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V)

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V

Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V

Total power dissipation (Note 1) ...............................................................................................................................1.0W

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin ..............................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA

Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by all ports .......................................................................................................................200 mA

Maximum current sourced by all ports ..................................................................................................................200 mA

Note 1: Power dissipation is calculated as follows:

Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)

2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause

latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/

RE3 pin, rather than pulling this pin directly to VSS.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Preliminary

DS39689E-page 327

PIC18F4321 FAMILY

FIGURE 26-1:

PIC18F2221/2321/4221/4321 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

6.0V

5.5V

5.0V

4.5V

4.0V

PIC18F2X21/4X21

4.2V

3.5V

3.0V

2.5V

2.0V

40 MHz

Frequency

FIGURE 26-2:

PIC18F2221/2321/4221/4321 VOLTAGE-FREQUENCY GRAPH (EXTENDED)

6.0V

5.5V

PIC18F2X21/4X21

5.0V

4.5V

4.0V

4.2V

3.5V

3.0V

2.5V

2.0V

25 MHz

Frequency

DS39689E-page 328

Preliminary

PIC18F4321 FAMILY

FIGURE 26-3:

PIC18LF2221/2321/4221/4321 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

6.0V

5.5V

5.0V

4.5V

4.0V

PIC18LF2X21/4X21

4.2V

3.5V

3.0V

2.5V

2.0V

4 MHz

25 MHz

40 MHz

Frequency

FMAX = (9.54 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz

Note: VDDAPPMIN is the minimum voltage of the PIC^®device in the application.

Preliminary

DS39689E-page 329

PIC18F4321 FAMILY

26.1 DC Characteristics: Supply Voltage

PIC18F2221/2321/4221/4321 (Industrial)

PIC18LF2221/2321/4221/4321 (Industrial)

PIC18LF2221/2321/4221/4321

Standard Operating Conditions (unless otherwise stated)

(Industrial)

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

PIC18F2221/2321/4221/4321

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

(Industrial, Extended)

Param

No.

Symbol

Characteristic

Min Typ Max Units

Conditions

D001

VDD

Supply Voltage

PIC18LF2X21/4X21 2.0

PIC18F2X21/4X21 4.2

—

5.5

—

V

HS, XT, RC and LP Oscillator mode

D002

D003

VDR

RAM Data Retention

Voltage

1.5

(1)

VPOR

VDD Start Voltage

to ensure internal

Power-on Reset signal

—

0.7

—

V

See section on Power-on Reset for details

D004

SVDD

VBOR

VDD Rise Rate

to ensure internal

Power-on Reset signal

0.05

V/ms See section on Power-on Reset for details

Brown-out Reset Voltage

PIC18LF2X21/4X21

BORV1:BORV0 = 11

BORV1:BORV0 = 10

All devices

D005

2.00 2.05 2.16

2.65 2.79 2.93

V

BORV1:BORV0 = 01

BORV1:BORV0 = 00

4.11 4.33 4.55

4.36 4.59 4.82

V

Legend: Shading of rows is to assist in readability of the table.

Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.

DS39689E-page 330

Preliminary

PIC18F4321 FAMILY

26.2 DC Characteristics: Power-Down and Supply Current

PIC18F2221/2321/4221/4321 (Industrial)

PIC18LF2221/2321/4221/4321 (Industrial)

PIC18LF2221/2321/4221/4321

Standard Operating Conditions (unless otherwise stated)

(Industrial)

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

PIC18F2221/2321/4221/4321

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

(Industrial, Extended)

Param

Device

No.

Typ

Max Units

Conditions

(1)

Power-Down Current (IPD)

PIC18LF2X21/4X21 0.5

0.7

1.7

0.9

1.9

2.0

6.5

50

μA

-40°C

+25°C

+85°C

-40°C

VDD = 2.0V

(Sleep mode)

0.5

PIC18LF2X21/4X21 0.6

VDD = 3.0V

(Sleep mode)

0.6

+25°C

+85°C

-40°C

0.6

All devices 0.9

0.9

+25°C

+85°C

+125°C

VDD = 5.0V

(Sleep mode)

Extended devices only 7.5

Legend: Shading of rows is to assist in readability of the table.

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that

add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;

MCLR = VDD; WDT enabled/disabled as specified.

3: Low-power Timer1 oscillator selected.

4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less

than the sum of both specifications.

Preliminary

DS39689E-page 331

PIC18F4321 FAMILY

26.2 DC Characteristics: Power-Down and Supply Current

PIC18F2221/2321/4221/4321 (Industrial)

PIC18LF2221/2321/4221/4321 (Industrial) (Continued)

PIC18LF2221/2321/4221/4321

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

(Industrial)

Standard Operating Conditions (unless otherwise stated)

PIC18F2221/2321/4221/4321

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

(Industrial, Extended)

Param

Device

No.

Typ

Max Units

Conditions

(2)

Supply Current (IDD)

PIC18LF2X21/4X21 13

15

45

35

30

115

95

75

μA

-40°C

13

+25°C

+85°C

-40°C

VDD = 2.0V

VDD = 3.0V

13

PIC18LF2X21/4X21 41

FOSC = 31 kHz

(RC_RUN mode,

INTRC source)

34

+25°C

+85°C

-40°C

27

All devices 104

86

67

+25°C

+85°C

+125°C

-40°C

VDD = 5.0V

Extended devices only 68

μA

PIC18LF2X21/4X21 0.31 0.35

0.31 0.35

mA

+25°C

+85°C

-40°C

VDD = 2.0V

VDD = 3.0V

0.31 0.35

PIC18LF2X21/4X21 0.55 0.60

0.51 0.60

FOSC = 1 MHz

(RC_RUN mode,

INTOSC source)

+25°C

+85°C

-40°C

0.47 0.60

All devices 1.0

1.1

0.94 1.05

0.88 0.95

+25°C

+85°C

+125°C

VDD = 5.0V

Extended devices only 0.88 0.95

Legend: Shading of rows is to assist in readability of the table.

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that

add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;

MCLR = VDD; WDT enabled/disabled as specified.

3: Low-power Timer1 oscillator selected.

4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less

than the sum of both specifications.

DS39689E-page 332

Preliminary

PIC18F4321 FAMILY

26.2 DC Characteristics: Power-Down and Supply Current

PIC18F2221/2321/4221/4321 (Industrial)

PIC18LF2221/2321/4221/4321 (Industrial) (Continued)

PIC18LF2221/2321/4221/4321

Standard Operating Conditions (unless otherwise stated)

(Industrial)

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

PIC18F2221/2321/4221/4321

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

(Industrial, Extended)

Param

Device

No.

Typ

Max Units

Conditions

(2)

Supply Current (IDD)

PIC18LF2X21/4X21 0.69 0.81

0.70 0.80

mA

μA

-40°C

+25°C

+85°C

-40°C

VDD = 2.0V

VDD = 3.0V

0.71 0.79

PIC18LF2X21/4X21 1.17 1.25

1.15 1.25

FOSC = 4 MHz

(RC_RUN mode,

INTOSC source)

+25°C

+85°C

-40°C

1.14 1.25

All devices 2.24 2.35

2.20 2.30

+25°C

+85°C

+125°C

-40°C

VDD = 5.0V

2.16 2.30

Extended devices only 2.18 2.30

PIC18LF2X21/4X21

3

4

5

+25°C

+85°C

-40°C

VDD = 2.0V

VDD = 3.0V

5

6

FOSC = 31 kHz

(RC_IDLE mode,

INTRC source)

7

+25°C

+85°C

-40°C

7

All devices 10

12

25

10

+25°C

+85°C

+125°C

VDD = 5.0V

Extended devices only 17

μA

Legend: Shading of rows is to assist in readability of the table.

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that

add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;

MCLR = VDD; WDT enabled/disabled as specified.

3: Low-power Timer1 oscillator selected.

4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less

than the sum of both specifications.

Preliminary

DS39689E-page 333

PIC18F4321 FAMILY

26.2 DC Characteristics: Power-Down and Supply Current

PIC18F2221/2321/4221/4321 (Industrial)

PIC18LF2221/2321/4221/4321 (Industrial) (Continued)

PIC18LF2221/2321/4221/4321

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

(Industrial)

Standard Operating Conditions (unless otherwise stated)

PIC18F2221/2321/4221/4321

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

(Industrial, Extended)

Param

Device

No.

Typ

Max Units

Conditions

(2)

Supply Current (IDD)

PIC18LF2X21/4X21 0.16 0.20

0.17 0.20

mA

-40°C

+25°C

+85°C

-40°C

VDD = 2.0V

VDD = 3.0V

0.17 0.20

PIC18LF2X21/4X21 0.22 0.25

0.24 0.30

FOSC = 1 MHz

(RC_IDLE mode,

INTOSC source)

+25°C

+85°C

-40°C

0.25 0.30

All devices 0.41 0.45

0.42 0.45

+25°C

+85°C

+125°C

-40°C

VDD = 5.0V

0.43 0.45

Extended devices only 0.45 0.50

PIC18LF2X21/4X21 0.31 0.40

0.33 0.40

+25°C

+85°C

-40°C

VDD = 2.0V

VDD = 3.0V

0.34 0.40

PIC18LF2X21/4X21 0.48 0.75

0.50 0.75

FOSC = 4 MHz

(RC_IDLE mode,

INTOSC source)

+25°C

+85°C

-40°C

0.52 0.75

All devices 0.91 1.00

0.93 1.05

+25°C

+85°C

+125°C

VDD = 5.0V

0.96 1.10

Extended devices only 0.98 1.05

Legend: Shading of rows is to assist in readability of the table.

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that

add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;

MCLR = VDD; WDT enabled/disabled as specified.

3: Low-power Timer1 oscillator selected.

4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less

than the sum of both specifications.

DS39689E-page 334

Preliminary

PIC18F4321 FAMILY

26.2 DC Characteristics: Power-Down and Supply Current

PIC18F2221/2321/4221/4321 (Industrial)

PIC18LF2221/2321/4221/4321 (Industrial) (Continued)

PIC18LF2221/2321/4221/4321

Standard Operating Conditions (unless otherwise stated)

(Industrial)

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

PIC18F2221/2321/4221/4321

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

(Industrial, Extended)

Param

Device

No.

Typ

Max Units

Conditions

(2)

Supply Current (IDD)

PIC18LF2X21/4X21 0.22 0.25

0.22 0.25

mA

-40°C

+25°C

+85°C

-40°C

VDD = 2.0V

VDD = 3.0V

0.21 0.25

PIC18LF2X21/4X21 0.51 0.55

0.45 0.50

FOSC = 1 MHz

(PRI_RUN,

EC oscillator)

+25°C

+85°C

-40°C

0.39 0.45

All devices 1.14 1.25

0.99 1.05

+25°C

+85°C

+125°C

-40°C

VDD = 5.0V

0.83 1.00

Extended devices only 0.80 0.90

PIC18LF2X21/4X21 0.61 0.75

0.61 0.75

+25°C

+85°C

-40°C

VDD = 2.0V

VDD = 3.0V

0.61 0.75

PIC18LF2X21/4X21 1.13 1.50

1.10 1.50

FOSC = 4 MHz

(PRI_RUN,

EC oscillator)

+25°C

+85°C

-40°C

1.07 1.50

All devices 2.35 2.50

2.24 2.40

+25°C

+85°C

+125°C

VDD = 5.0V

2.14 2.30

Extended devices only 2.14 2.30

Extended devices only

9

15

20

VDD = 4.2V

VDD = 5.0V

FOSC = 25 MHz

(PRI_RUN,

EC oscillator)

12

All devices 14

22

20

mA

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

14

VDD = 4.2V

VDD = 5.0V

FOSC = 40 MHz

(PRI_RUN,

EC oscillator)

16

All devices 17

17

Legend: Shading of rows is to assist in readability of the table.

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that

add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;

MCLR = VDD; WDT enabled/disabled as specified.

3: Low-power Timer1 oscillator selected.

4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less

than the sum of both specifications.

Preliminary

DS39689E-page 335

PIC18F4321 FAMILY

26.2 DC Characteristics: Power-Down and Supply Current

PIC18F2221/2321/4221/4321 (Industrial)

PIC18LF2221/2321/4221/4321 (Industrial) (Continued)

PIC18LF2221/2321/4221/4321

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

(Industrial)

Standard Operating Conditions (unless otherwise stated)

PIC18F2221/2321/4221/4321

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

(Industrial, Extended)

Param

Device

No.

Typ

Max Units

Conditions

(2)

Supply Current (IDD)

All devices

8

7

8

16

25

21

35

40

mA

-40°C

FOSC = 4 MHz,

16 MHz internal

(PRI_RUN HS+PLL)

+25°C

VDD = 4.2V

+85°C

Extended devices only

+125°C

-40°C

All devices 10

FOSC = 4 MHz,

16 MHz internal

(PRI_RUN HS+PLL)

10

+25°C

+85°C

+125°C

-40°C

VDD = 5.0V

10

Extended devices only 10

All devices 17

FOSC = 10 MHz,

40 MHz internal

(PRI_RUN HS+PLL)

17

+25°C

+85°C

-40°C

VDD = 4.2V

VDD = 5.0V

17

All devices 23

FOSC = 10 MHz,

40 MHz internal

(PRI_RUN HS+PLL)

23

+25°C

+85°C

Legend: Shading of rows is to assist in readability of the table.

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that

add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;

MCLR = VDD; WDT enabled/disabled as specified.

3: Low-power Timer1 oscillator selected.

4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less

than the sum of both specifications.

DS39689E-page 336

Preliminary

PIC18F4321 FAMILY

26.2 DC Characteristics: Power-Down and Supply Current

PIC18F2221/2321/4221/4321 (Industrial)

PIC18LF2221/2321/4221/4321 (Industrial) (Continued)

PIC18LF2221/2321/4221/4321

Standard Operating Conditions (unless otherwise stated)

(Industrial)

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

PIC18F2221/2321/4221/4321

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

(Industrial, Extended)

Param

Device

No.

Typ

Max Units

Conditions

(2)

Supply Current (IDD)

PIC18LF2X21/4X21 51

65

70

μA

-40°C

54

+25°C

+85°C

-40°C

VDD = 2.0V

VDD = 3.0V

60

105

90

PIC18LF2X21/4X21 83

μA

FOSC = 1 MHz

(PRI_IDLE mode,

EC oscillator)

88

93

95

μA

+25°C

+85°C

-40°C

100

All devices 0.18 0.20

0.18 0.20

mA

+25°C

+85°C

+125°C

-40°C

VDD = 5.0V

0.18 0.20

Extended devices only 0.19 0.22

PIC18LF2X21/4X21 0.21 0.25

0.22 0.25

+25°C

+85°C

-40°C

VDD = 2.0V

VDD = 3.0V

0.23 0.25

PIC18LF2X21/4X21 0.35 0.40

0.36 0.40

FOSC = 4 MHz

(PRI_IDLE mode,

EC oscillator)

+25°C

+85°C

-40°C

0.37 0.40

All devices 0.69 0.75

0.70 0.78

+25°C

+85°C

+125°C

VDD = 5.0V

0.72 0.90

Extended devices only 0.74 0.80

Extended devices only 3.7

4.6

4.0

5.0

VDD = 4.2V

VDD = 5.0V

FOSC = 25 MHz

(PRI_IDLE mode,

EC oscillator)

All devices 6.0

16

mA

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

6.2

VDD = 4.2V

VDD = 5.0V

FOSC = 40 MHz

(PRI_IDLE mode,

EC oscillator)

6.6

16

All devices 6.8

7.0

7.2

7.3

7.0

7.1

Legend: Shading of rows is to assist in readability of the table.

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that

add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;

MCLR = VDD; WDT enabled/disabled as specified.

3: Low-power Timer1 oscillator selected.

4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less

than the sum of both specifications.

Preliminary

DS39689E-page 337

PIC18F4321 FAMILY

26.2 DC Characteristics: Power-Down and Supply Current

PIC18F2221/2321/4221/4321 (Industrial)

PIC18LF2221/2321/4221/4321 (Industrial) (Continued)

PIC18LF2221/2321/4221/4321

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

(Industrial)

Standard Operating Conditions (unless otherwise stated)

PIC18F2221/2321/4221/4321

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

(Industrial, Extended)

Param

Device

No.

Typ

Max Units

Conditions

(2)

Supply Current (IDD)

PIC18LF2X21/4X21 12

15

μA

-40°C

13

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

VDD = 2.0V

VDD = 3.0V

VDD = 5.0V

VDD = 2.0V

VDD = 3.0V

VDD = 5.0V

13

15

(3)

PIC18LF2X21/4X21 40

45

FOSC = 32 kHz

33

45

(SEC_RUN mode,

Timer1 as clock)

27

45

All devices 101

115

95

83

65

70

PIC18LF2X21/4X21 2.5

3.6

3.9

4.3

5.5

5.8

6.2

9.5

9.9

3.0

3.5

(3)

PIC18LF2X21/4X21 3.9

FOSC = 32 kHz

4.5

(SEC_IDLE mode,

Timer1 as clock)

5.2

All devices 7.5

8.0

8.6

Legend: Shading of rows is to assist in readability of the table.

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that

add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;

MCLR = VDD; WDT enabled/disabled as specified.

3: Low-power Timer1 oscillator selected.

4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less

than the sum of both specifications.

DS39689E-page 338

Preliminary

PIC18F4321 FAMILY

26.2 DC Characteristics: Power-Down and Supply Current

PIC18F2221/2321/4221/4321 (Industrial)

PIC18LF2221/2321/4221/4321 (Industrial) (Continued)

PIC18LF2221/2321/4221/4321

Standard Operating Conditions (unless otherwise stated)

(Industrial)

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

Standard Operating Conditions (unless otherwise stated)

PIC18F2221/2321/4221/4321

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

(Industrial, Extended)

Param

Device

No.

Typ

Max Units

Conditions

Module Differential Currents (ΔIWDT, ΔIBOR, ΔILVD, ΔIOSCB, ΔIAD)

D022

(ΔIWDT)

Watchdog Timer 1.6

1.9

1.8

1.7

2.8

2.6

2.4

4.1

4.6

5.2

45

μA

-40°C

+25°C

1.6

1.5

2.3

2.2

2.1

3.4

3.9

4.4

VDD = 2.0V

VDD = 3.0V

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

VDD = 5.0V

+85°C

4.5

+125°C

-40°C to +85°C

(4)

D022A

(ΔIBOR)

Brown-out Reset

34

40

42

VDD = 3.0V

VDD = 5.0V

50

μA -40°C to +125°C

D022B

(ΔILVD)

High/Low-Voltage 23

35

μA

-40°C to +85°C

VDD = 2.0V

VDD = 3.0V

(4)

Detect

23

35

28

35

VDD = 5.0V

30

40

μA -40°C to +125°C

D025

(ΔIOSCB)

Timer1 Oscillator 2.1

4.5

6.0

8.0

2.0

8.0

μA

-40°C

1.8

+25°C

VDD = 2.0V

2.1

+85°C

2.2

-40°C

32 kHz Tuning Fork

Crystal on Timer1

2.6

+25°C

VDD = 3.0V

VDD = 5.0V

(3)

Oscillator

2.9

+85°C

3.0

-40°C

3.2

+25°C

3.4

+85°C

D026

(ΔIAD)

A/D Converter 1.0

-40°C to +85°C

VDD = 2.0V

VDD = 3.0V

1.0

2.0

A/D on, not converting

VDD = 5.0V

μA -40°C to +125°C

Legend: Shading of rows is to assist in readability of the table.

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured

with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that

add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin

loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have

an impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS;

MCLR = VDD; WDT enabled/disabled as specified.

3: Low-power Timer1 oscillator selected.

4: BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less

than the sum of both specifications.

Preliminary

DS39689E-page 339

PIC18F4321 FAMILY

26.3 DC Characteristics: PIC18F2221/2321/4221/4321 (Industrial)

PIC18LF2221/2321/4221/4321 (Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

DC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min

Max

Units

Conditions

VIL

Input Low Voltage

I/O ports:

with TTL buffer

D030

D030A

D031

D032

D033

VSS

—

0.15 VDD

0.8

V

VDD < 4.5V

4.5V ≤ VDD ≤ 5.5V

with Schmitt Trigger buffer

MCLR

VSS

0.2 VDD

0.3 VDD

OSC1

HS, HSPLL modes

D033A

D033B

D034

OSC1

T13CKI

VSS

0.2 VDD

0.3

V

RC, EC modes⁽¹⁾

XT, LP modes

VIH

Input High Voltage

I/O ports:

D040

with TTL buffer

0.25 VDD +

0.8V

VDD

V

VDD < 4.5V

D040A

D041

D042

D043

2.0

VDD

V

4.5V ≤ VDD ≤ 5.5V

with Schmitt Trigger buffer

0.8 VDD

0.7 VDD

MCLR

OSC1

HS, HSPLL modes

D043A

D043B

D043C

D044

OSC1

T13CKI

0.8 VDD

0.9 VDD

1.6

VDD

V

EC mode

RC mode⁽¹⁾

XT, LP modes

1.6

IIL

Input Leakage Current^(2,3)

D060

I/O ports

—

1

μA VSS ≤ VPIN ≤ VDD,

Pin at high-impedance

D061

D063

MCLR

—

5

μA Vss ≤ VPIN ≤ VDD

OSC1

IPU

Weak Pull-up Current

PORTB weak pull-up current

D070

IPURB

50

400

μA VDD = 5V, VPIN = VSS

Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the

PIC^®device be driven with an external clock while in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

DS39689E-page 340

Preliminary

PIC18F4321 FAMILY

26.3 DC Characteristics: PIC18F2221/2321/4221/4321 (Industrial)

PIC18LF2221/2321/4221/4321 (Industrial) (Continued)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

DC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min

Max

Units

Conditions

VOL

Output Low Voltage

I/O ports

D080

D083

—

0.6

V

IOL = 8.5 mA, VDD = 4.5V,

-40°C to +85°C

OSC2/CLKO

IOL = 1.6 mA, VDD = 4.5V,

(RC, RCIO, EC, ECIO modes)

-40°C to +85°C

VOH

Output High Voltage⁽³⁾

D090

D092

I/O ports

VDD – 0.7

—

V

IOH = -3.0 mA, VDD = 4.5V,

-40°C to +85°C

OSC2/CLKO

IOH = -1.3 mA, VDD = 4.5V,

(RC, RCIO, EC, ECIO modes)

-40°C to +85°C

Capacitive Loading Specs

on Output Pins

—

COSC2 OSC2 pin

15

50

pF In XT, HS and LP modes

when external clock is used

to drive OSC1

D100

D101

CIO

CB

All I/O pins and OSC2

(in RC mode)

pF Maximum that allows the

AC Timing Specifications to

be met

D102

SCL, SDA

400

pF Maximum bus capacitance

permitted by I²C™

Specification

Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the

PIC^®device be driven with an external clock while in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

Preliminary

DS39689E-page 341

PIC18F4321 FAMILY

TABLE 26-1: MEMORY PROGRAMMING REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

DC CHARACTERISTICS

Param

Sym

No.

Characteristic

Min

Typ†

Max

Units

Conditions

Data EEPROM Memory

D120

ED

Byte Endurance

1M

10M

—

E/W -40°C to +85°C

D121 VDRW VDD for Read/Write

VMIN

5.5

V

Using EECON to read/write,

VMIN = Minimum operating

voltage

D122 TDEW Erase/Write Cycle Time

D123 TRETD Characteristic Retention

—

4

—

ms

40

—

Year Provided no other

specifications are violated

D124

D125

TREF

IDDP

Number of Total Erase/Write

Cycles before Refresh⁽¹⁾

100K

—

1M

10

—

E/W -40°C to +85°C

Supply Current during

Programming

mA

Program Flash Memory

Cell Endurance

D130

D131

EP

10K

100K

—

E/W -40°C to +85°C

VPR

VDD for Read

VMIN

5.5

V

VMIN = Minimum operating

voltage

D132

VIE

VDD for Block Erase

3.0

—

5.5

V

Using ICSP™ port, 25°C

D132B VPEW VDD for Self-Timed Write

VMIN

VMIN = Minimum operating

voltage

D133A TIW

Self-Timed Write Cycle Time

—

2

—

ms

D134 TRETD Characteristic Retention

40

100

Year Provided no other

specifications are violated

D135

IDDP

Supply Current during

Programming

—

10

—

mA

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Refer to Section 7.7 “Using the Data EEPROM” for a more detailed discussion on data EEPROM

endurance.

DS39689E-page 342

Preliminary

PIC18F4321 FAMILY

TABLE 26-2: COMPARATOR SPECIFICATIONS

Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated).

Param

No.

Sym

Characteristics

Input Offset Voltage

Min

Typ

Max

Units

Comments

D300

VIOFF

—

0

±5.0

—

±10

VDD – 1.5

—

mV

V

D301

D302

300

VICM

Input Common Mode Voltage

Common Mode Rejection Ratio

Response Time⁽¹⁾

CMRR

TRESP

55

—

dB

ns

150

400

PIC18FXXXX

300A

600

PIC18LFXXXX,

VDD = 2.0V

301

TMC2OV Comparator Mode Change to

Output Valid

—

10

μs

Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions

from VSS to VDD.

TABLE 26-3: VOLTAGE REFERENCE SPECIFICATIONS

Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated).

Param

No.

Sym

Characteristics

Resolution

Min

Typ

Max

Units

Comments

D310

VRES

VDD/24

—

2k

—

VDD/32

1/2

LSb

Ω

D311

D312

310

VRAA

VRUR

TSET

Absolute Accuracy

Unit Resistor Value (R)

Settling Time⁽¹⁾

—

10

μs

Note 1: Settling time measured while CVRR = 1and CVR3:CVR0 transitions from ‘0000’ to ‘1111’.

Preliminary

DS39689E-page 343

PIC18F4321 FAMILY

FIGURE 26-4:

HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS

VDD

(HLVDIF can be

cleared in software)

VLVD

(HLVDIF set by hardware)

HLVDIF⁽¹⁾

Note 1: VDIRMAG = 0.

TABLE 26-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

Param

No.

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

D420

HLVD Voltage on VDD LVV = 0000 2.06

2.17

2.23

2.36

2.44

2.60

2.79

2.89

3.12

3.39

3.55

3.71

3.90

4.11

4.33

4.59

1.20

2.28

2.34

2.48

2.56

2.73

2.93

3.04

3.28

3.56

3.73

3.90

4.10

4.32

4.55

4.82

1.30

V

Transition High to Low

LVV = 0001 2.12

LVV = 0010 2.24

LVV = 0011 2.32

LVV = 0100 2.47

LVV = 0101 2.65

LVV = 0110 2.74

LVV = 0111 2.96

LVV = 1000 3.22

LVV = 1001 3.37

LVV = 1010 3.52

LVV = 1011 3.70

LVV = 1100 3.90

LVV = 1101 4.11

LVV = 1110 4.36

LVV = 1111 1.10

HLVDIN input/internal

reference voltage

DS39689E-page 344

Preliminary

PIC18F4321 FAMILY

26.4 AC (Timing) Characteristics

26.4.1 TIMING PARAMETER SYMBOLOGY

The timing parameter symbols have been created

using one of the following formats:

1. TppS2ppS

2. TppS

T

3. TCC:ST

4. Ts

(I²C specifications only)

F

Frequency

T

Time

Lowercase letters (pp) and their meanings:

pp

cc

ck

cs

di

CCP1

CLKO

CS

osc

rd

OSC1

RD

rw

sc

ss

t0

RD or WR

SCK

SDI

do

dt

SDO

SS

Data in

I/O port

MCLR

T0CKI

T13CKI

WR

io

t1

mc

wr

Uppercase letters and their meanings:

S

F

Fall

P

R

V

Z

Period

H

High

Rise

I

L

Invalid (High-impedance)

Low

Valid

High-impedance

I²C only

AA

output access

Bus free

High

Low

High

Low

BUF

TCC:ST (I²C specifications only)

CC

HD

Hold

SU

Setup

ST

DAT

STA

DATA input hold

Start condition

STO

Stop condition

Preliminary

DS39689E-page 345

PIC18F4321 FAMILY

26.4.2

TIMING CONDITIONS

Note:

Because of space limitations, the generic

terms “PIC18FXXXX” and “PIC18LFXXXX”

are used throughout this section to refer to

the PIC18F2221/2321/4221/4321 and

PIC18LF2221/2321/4221/4321 families of

devices specifically and only those devices.

The temperature and voltages specified in Table 26-5

apply to all timing specifications unless otherwise

noted. Figure 26-5 specifies the load conditions for the

timing specifications.

TABLE 26-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

AC CHARACTERISTICS

Operating voltage VDD range as described in DC spec Section 26.1 and

Section 26.3.

LF parts operate for industrial temperatures only.

FIGURE 26-5:

LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 1 Load Condition 2

VDD/2

CL

RL

VSS

CL

RL = 464Ω

CL = 50 pF for all pins except OSC2/CLKO

and including D and E outputs as ports

VSS

DS39689E-page 346

Preliminary

PIC18F4321 FAMILY

26.4.3

TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 26-6:

EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)

Q4

Q1

1

Q2

Q3

Q4

Q1

OSC1

CLKO

3

4

3

4

2

TABLE 26-6: EXTERNAL CLOCK TIMING REQUIREMENTS

Param.

Symbol

Characteristic

Min

Max

Units

Conditions

No.

1A

FOSC

External CLKI Frequency⁽¹⁾

DC

0.1

4

1

25

50

4

MHz XT, RC Oscillator mode

MHz HS Oscillator mode

kHz LP Oscillator mode

MHz RC Oscillator mode

MHz XT Oscillator mode

MHz HS Oscillator mode

kHz LP Oscillator mode

Oscillator Frequency⁽¹⁾

4

25

200

—

1

5

1

TOSC

External CLKI Period⁽¹⁾

Oscillator Period⁽¹⁾

1000

40

ns

μs

ns

μs

ns

μs

ns

μs

ns

XT, RC Oscillator mode

HS Oscillator mode

LP Oscillator mode

RC Oscillator mode

XT Oscillator mode

HS Oscillator mode

LP Oscillator mode

TCY = 4/FOSC, Industrial

TCY = 4/FOSC, Extended

XT Oscillator mode

LP Oscillator mode

HS Oscillator mode

XT Oscillator mode

LP Oscillator mode

HS Oscillator mode

32

250

—

40

20

—

20

50

7.5

—

2

3

TCY

Instruction Cycle Time⁽¹⁾

100

160

30

TOSL,

TOSH

External Clock in (OSC1)

High or Low Time

2.5

10

4

TOSR,

TOSF

External Clock in (OSC1)

Rise or Fall Time

—

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations

except PLL. All specified values are based on characterization data for that particular oscillator type under

standard operating conditions with the device executing code. Exceeding these specified limits may result

in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested

to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock

input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.

Preliminary

DS39689E-page 347

PIC18F4321 FAMILY

TABLE 26-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V)

Param

Sym

Characteristic

Min

Typ†

Max

Units Conditions

No.

F10

FOSC Oscillator Frequency Range

4

—

10

40

2

MHz HS mode only

F11

F12

F13

FSYS On-Chip VCO System Frequency

16

—

-2

MHz HS mode only

t_rc

PLL Start-up Time (Lock Time)

ms

%

ΔCLK CLKO Stability (Jitter)

+2

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

TABLE 26-8: AC CHARACTERISTICS: INTERNAL RC ACCURACY

PIC18F2221/2321/4221/4321 (INDUSTRIAL)

PIC18LF2221/2321/4221/4321 (INDUSTRIAL)

PIC18LF2221/2321/4221/4321

Standard Operating Conditions (unless otherwise stated)

(Industrial)

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

PIC18F2221/2321/4221/4321

Standard Operating Conditions (unless otherwise stated)

(Industrial)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

Param

Device

No.

Min

Typ

Max

Units

Conditions

(1)

INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 31 kHz

PIC18LF2221/2321/4221/4321

-2

-5

+/-1

—

2

5

%

+25°C

VDD = 2.0-5.5V

VDD = 4.2-5.5V

-10°C to +85°C

-40°C to +85°C

+25°C

-10

-2

+/-1

—

10

2

PIC18F2221/2321/4221/4321

-5

5

-10°C to +85°C

-40°C to +85°C

-10

+/-1

10

(2,3)

INTRC Accuracy @ Freq = 31 kHz

PIC18LF2221/2321/4221/4321 26.562

PIC18F2221/2321/4221/4321 26.562

—

35.938

kHz

-40°C to +85°C

VDD = 2.0-5.5V

VDD = 4.2-5.5V

Legend: Shading of rows is to assist in readability of the table.

Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift.

2: INTRC frequency after calibration.

3: Change of INTRC frequency as VDD changes.

DS39689E-page 348

Preliminary

PIC18F4321 FAMILY

FIGURE 26-7:

CLKO AND I/O TIMING

Q1

Q2

Q3

Q4

OSC1

11

10

CLKO

13

14

12

19

18

16

I/O pin

(Input)

15

17

I/O pin

(Output)

New Value

Old Value

20, 21

Refer to Figure 26-5 for load conditions.

Note:

TABLE 26-9: CLKO AND I/O TIMING REQUIREMENTS

Param

Symbol

Characteristic

Min

Typ

Max

Units Conditions

No.

10

TosH2ckL OSC1 ↑ to CLKO ↓

TosH2ckH OSC1 ↑ to CLKO ↑

—

75

35

—

50

—

200

100

ns

(Note 1)

11

12

13

14

15

16

17

18

18A

TckR

TckF

CLKO Rise Time

CLKO Fall Time

TckL2ioV CLKO ↓ to Port Out Valid

TioV2ckH Port In Valid before CLKO ↑

TckH2ioI Port In Hold after CLKO ↑

TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid

0.5 TCY + 20 ns

0.25 TCY + 25

—

ns

0

—

150

—

TosH2ioI OSC1 ↑ (Q2 cycle) to

Port Input Invalid

PIC18FXXXX

100

200

PIC18LFXXXX

—

ns VDD = 2.0V

(I/O in hold time)

19

TioV2osH Port Input Valid to OSC1 ↑ (I/O in setup time)

0

—

10

—

10

—

25

60

25

60

—

ns

20

TioR

Port Output Rise Time

Port Output Fall Time

INT pin High or Low Time

PIC18FXXXX

PIC18LFXXXX

PIC18FXXXX

PIC18LFXXXX

—

ns

20A

21

—

ns VDD = 2.0V

TioF

—

ns

21A

22†

23†

—

ns VDD = 2.0V

TINP

TCY

ns

TRBP

RB7:RB4 Change INT High or Low Time

†

These parameters are asynchronous events not related to any internal clock edges.

Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.

Preliminary

DS39689E-page 349

PIC18F4321 FAMILY

FIGURE 26-8:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND

POWER-UP TIMER TIMING

VDD

MCLR

30

Internal

POR

33

PWRT

Time-out

32

OSC

Time-out

Internal

Reset

Watchdog

Timer

Reset

31

34

I/O pins

Note:

Refer to Figure 26-5 for load conditions.

FIGURE 26-9:

BROWN-OUT RESET TIMING

BVDD

VDD

35

VIRVST

Enable Internal

Reference Voltage

Internal Reference

Voltage Stable

36

TABLE 26-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

30

TmcL

TWDT

MCLR Pulse Width (low)

2

—

μs

31

Watchdog Timer Time-out Period

(no postscaler)

3.56

4.19

4.82

ms

32

33

34

TOST

Oscillation Start-up Timer Period

1024 TOSC

—

67

2

1024 TOSC

—

ms

μs

TOSC = OSC1 period

TPWRT Power-up Timer Period

57

—

77

—

TIOZ

I/O High-Impedance from MCLR

Low or Watchdog Timer Reset

35

36

TBOR

Brown-out Reset Pulse Width

200

—

μs VDD ≤ BVDD (see D005)

μs

TIRVST Time for Internal Reference

Voltage to become Stable

20

50

37

38

39

TLVD

TCSD

High/Low-Voltage Detect Pulse Width

CPU Start-up Time

200

—

10

1

—

μs

VDD ≤ VLVD

TIOBST Time for INTOSC to Stabilize

—

DS39689E-page 350

Preliminary

PIC18F4321 FAMILY

FIGURE 26-10:

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

41

40

42

T1OSO/T13CKI

46

45

47

48

TMR0 or

TMR1

Note:

Refer to Figure 26-5 for load conditions.

TABLE 26-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

Symbol

Characteristic

Min

Max Units Conditions

No.

40

Tt0H

T0CKI High Pulse Width

No prescaler

With prescaler

No prescaler

With prescaler

No prescaler

With prescaler

0.5 TCY + 20

10

—

ns

41

42

Tt0L

Tt0P

T0CKI Low Pulse Width

T0CKI Period

0.5 TCY + 20

10

TCY + 10

Greater of:

20 ns or

ns N = prescale

value

(TCY + 40)/N

(1, 2, 4,..., 256)

45

46

Tt1H

Tt1L

T13CKI

High Time

Synchronous, no prescaler

0.5 TCY + 20

—

ns

Synchronous,

with prescaler

PIC18FXXXX

10

ns

PIC18LFXXXX

25

ns VDD = 2.0V

Asynchronous PIC18FXXXX

PIC18LFXXXX

30

ns

50

ns VDD = 2.0V

T13CKI

Low Time

Synchronous, no prescaler

0.5 TCY + 5

ns

Synchronous,

with prescaler

PIC18FXXXX

10

25

30

50

ns

PIC18LFXXXX

ns VDD = 2.0V

ns

Asynchronous PIC18FXXXX

PIC18LFXXXX

ns VDD = 2.0V

47

48

Tt1P

Ft1

T13CKI

Input

Period

Synchronous

Greater of:

20 ns or

(TCY + 40)/N

ns N = prescale

value (1, 2, 4, 8)

Asynchronous

60

DC

—

50

ns

kHz

—

T13CKI Oscillator Input Frequency Range

Tcke2tmrI Delay from External T13CKI Clock Edge to

Timer Increment

2 TOSC

7 TOSC

Preliminary

DS39689E-page 351

PIC18F4321 FAMILY

FIGURE 26-11:

CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES)

CCPx

(Capture Mode)

50

51

52

54

CCPx

(Compare or PWM Mode)

53

Refer to Figure 26-5 for load conditions.

Note:

TABLE 26-12: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)

Param

Symbol

Characteristic

Min

Max

Units

Conditions

No.

50

TccL

CCPx Input Low No prescaler

0.5 TCY + 20

—

ns

Time

With

PIC18FXXXX

10

prescaler

PIC18LFXXXX

20

VDD = 2.0V

51

TccH

CCPx Input

High Time

No prescaler

0.5 TCY + 20

With

PIC18FXXXX

10

20

prescaler

PIC18LFXXXX

52

53

TccP

TccR

CCPx Input Period

3 TCY + 40

N

N = prescale

value (1, 4 or 16)

CCPx Output Fall Time

PIC18FXXXX

PIC18LFXXXX

PIC18FXXXX

PIC18LFXXXX

—

25

45

25

45

ns

VDD = 2.0V

54

TccF

CCPx Output Fall Time

DS39689E-page 352

Preliminary

PIC18F4321 FAMILY

FIGURE 26-12:

PARALLEL SLAVE PORT TIMING (PIC18F4221/4321)

RE2/CS

RE0/RD

RE1/WR

65

RD7:RD0

62

64

63

Note:

Refer to Figure 26-5 for load conditions.

TABLE 26-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4221/4321)

Param.

Symbol

Characteristic

Min

Max Units

Conditions

No.

62

TdtV2wrH

TwrH2dtI

Data In Valid before WR ↑ or CS ↑ (setup time)

20

—

ns

63

WR ↑ or CS ↑ to Data–In

Invalid (hold time)

PIC18FXXXX

PIC18LFXXXX 35

—

ns VDD = 2.0V

64

65

66

TrdL2dtV

TrdH2dtI

TibfINH

RD ↓ and CS ↓ to Data–Out Valid

RD ↑ or CS ↓ to Data–Out Invalid

—

10

—

80

ns

30

Inhibit of the IBF Flag bit being Cleared from

3 TCY

WR ↑ or CS ↑

Preliminary

DS39689E-page 353

PIC18F4321 FAMILY

FIGURE 26-13:

EXAMPLE SPI MASTER MODE TIMING (CKE = 0)

SS

70

SCK

(CKP = 0)

71

72

78

79

SCK

(CKP = 1)

78

80

MSb

bit 6 - - - - - -1

LSb

SDO

SDI

75, 76

MSb In

74

bit 6 - - - -1

LSb In

73

Note: Refer to Figure 26-5 for load conditions.

TABLE 26-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

Param

No.

Symbol

Characteristic

Min

Max Units Conditions

70

TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input

TssL2scL

TCY

—

ns

71

TscH

SCK Input High Time

(Slave mode)

Continuous

Single Byte

Continuous

Single Byte

1.25 TCY + 30

—

ns

71A

72

40

1.25 TCY + 30

40

ns (Note 1)

TscL

SCK Input Low Time

(Slave mode)

ns

72A

73

ns (Note 1)

TdiV2scH, Setup Time of SDI Data Input to SCK Edge

TdiV2scL

100

ns

73A

74

Tb2b

Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40

of Byte 2

—

ns (Note 2)

TscH2diL, Hold Time of SDI Data Input to SCK Edge

TscL2diL

100

ns

75

TdoR

SDO Data Output Rise Time PIC18FXXXX

PIC18LFXXXX

—

25

45

25

45

25

50

100

ns

ns VDD = 2.0V

76

78

TdoF

TscR

SDO Data Output Fall Time

ns

SCK Output Rise Time

(Master mode)

PIC18FXXXX

PIC18LFXXXX

ns

ns VDD = 2.0V

79

80

TscF

SCK Output Fall Time (Master mode)

ns

TscH2doV, SDO Data Output Valid after PIC18FXXXX

TscL2doV SCK Edge

ns

PIC18LFXXXX

ns VDD = 2.0V

Note 1: Requires the use of Parameter #73A.

2: Only if Parameter #71A and #72A are used.

DS39689E-page 354

Preliminary

PIC18F4321 FAMILY

FIGURE 26-14:

EXAMPLE SPI MASTER MODE TIMING (CKE = 1)

SS

81

SCK

(CKP = 0)

71

72

79

78

73

SCK

(CKP = 1)

80

LSb

MSb

bit 6 - - - - - -1

SDO

SDI

75, 76

MSb In

74

bit 6 - - - -1

LSb In

Note: Refer to Figure 26-5 for load conditions.

TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)

Param.

No.

Symbol

TscH

TscL

Characteristic

Min

Max Units Conditions

71

SCK Input High Time

Continuous

Single Byte

Continuous

Single Byte

1.25 TCY + 30

—

ns

(Slave mode)

71A

72

40

1.25 TCY + 30

40

ns (Note 1)

SCK Input Low Time

(Slave mode)

ns

72A

73

ns (Note 1)

TdiV2scH, Setup Time of SDI Data Input to SCK Edge

TdiV2scL

100

ns

73A

74

Tb2b

Last Clock Edge of Byte 1 to the 1st Clock Edge

of Byte 2

1.5 TCY + 40

—

ns (Note 2)

TscH2diL,

TscL2diL

Hold Time of SDI Data Input to SCK Edge

100

—

ns

75

TdoR

SDO Data Output Rise Time PIC18FXXXX

PIC18LFXXXX

25

45

25

45

25

50

100

—

ns

ns VDD = 2.0V

76

78

TdoF

TscR

SDO Data Output Fall Time

—

ns

SCK Output Rise Time

(Master mode)

PIC18FXXXX

ns

PIC18LFXXXX

ns VDD = 2.0V

79

80

TscF

SCK Output Fall Time (Master mode)

—

ns

TscH2doV, SDO Data Output Valid after PIC18FXXXX

TscL2doV SCK Edge

ns

PIC18LFXXXX

ns VDD = 2.0V

ns

81

TdoV2scH, SDO Data Output Setup to SCK Edge

TdoV2scL

TCY

Note 1: Requires the use of Parameter #73A.

2: Only if Parameter #71A and #72A are used.

Preliminary

DS39689E-page 355

PIC18F4321 FAMILY

FIGURE 26-15:

EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)

SS

70

SCK

(CKP = 0)

83

71

72

78

79

78

SCK

(CKP = 1)

80

MSb

bit 6 - - - - - -1

LSb

SDO

SDI

77

75, 76

MSb In

74

bit 6 - - - -1

LSb In

73

Note:

Refer to Figure 26-5 for load conditions.

TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)

Param

No.

Symbol

Characteristic

Min

Max Units Conditions

70

TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input

TssL2scL

TCY

—

ns

71

TscH

SCK Input High Time

(Slave mode)

Continuous

Single Byte

Continuous

Single Byte

1.25 TCY + 30

—

ns

71A

72

40

1.25 TCY + 30

40

ns (Note 1)

TscL

SCK Input Low Time

(Slave mode)

ns

72A

73

ns (Note 1)

TdiV2scH, Setup Time of SDI Data Input to SCK Edge

TdiV2scL

100

ns

73A

74

Tb2b

Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40

—

ns (Note 2)

TscH2diL, Hold Time of SDI Data Input to SCK Edge

TscL2diL

100

ns

75

TdoR

SDO Data Output Rise Time

PIC18FXXXX

—

25

45

25

50

25

45

25

50

100

—

ns

PIC18LFXXXX

ns VDD = 2.0V

76

77

78

TdoF

SDO Data Output Fall Time

—

10

—

ns

TssH2doZ SS ↑ to SDO Output High-Impedance

TscR

ns

SCK Output Rise Time (Master mode) PIC18FXXXX

PIC18LFXXXX

ns

ns VDD = 2.0V

79

80

TscF

SCK Output Fall Time (Master mode)

—

ns

TscH2doV, SDO Data Output Valid after SCK Edge PIC18FXXXX

TscL2doV

ns

PIC18LFXXXX

ns VDD = 2.0V

ns

83

TscH2ssH, SS ↑ after SCK edge

TscL2ssH

1.5 TCY + 40

Note 1: Requires the use of Parameter #73A.

2: Only if Parameter #71A and #72A are used.

DS39689E-page 356

Preliminary

PIC18F4321 FAMILY

FIGURE 26-16:

EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)

82

SS

70

SCK

83

(CKP = 0)

71

72

SCK

(CKP = 1)

80

MSb

bit 6 - - - - - -1

bit 6 - - - -1

LSb

SDO

SDI

75, 76

77

MSb In

74

LSb In

Note: Refer to Figure 26-5 for load conditions.

TABLE 26-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)

Param

No.

Symbol

Characteristic

Min

Max Units Conditions

70

TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input

TssL2scL

TCY

—

ns

71

TscH

TscL

Tb2b

SCK Input High Time

(Slave mode)

Continuous

Single Byte

Continuous

Single Byte

1.25 TCY + 30

—

ns

71A

72

40

1.25 TCY + 30

40

ns (Note 1)

ns

SCK Input Low Time

(Slave mode)

72A

73A

74

ns (Note 1)

ns (Note 2)

ns

Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40

TscH2diL, Hold Time of SDI Data Input to SCK Edge

TscL2diL

100

75

TdoR

SDO Data Output Rise Time

PIC18FXXXX

—

25

45

25

50

25

45

25

50

100

50

100

—

ns

PIC18LFXXXX

ns VDD = 2.0V

76

77

78

TdoF

SDO Data Output Fall Time

—

ns

TssH2doZ SS ↑ to SDO Output High-Impedance

TscR

10

ns

SCK Output Rise Time

(Master mode)

PIC18FXXXX

—

ns

PIC18LFXXXX

—

ns VDD = 2.0V

79

80

TscF

SCK Output Fall Time (Master mode)

—

ns

TscH2doV, SDO Data Output Valid after SCK PIC18FXXXX

TscL2doV Edge

—

ns

PIC18LFXXXX

—

ns VDD = 2.0V

82

83

TssL2doV SDO Data Output Valid after SS ↓ PIC18FXXXX

—

ns

Edge

PIC18LFXXXX

ns VDD = 2.0V

ns

TscH2ssH, SS ↑ after SCK Edge

TscL2ssH

1.5 TCY + 40

Note 1: Requires the use of Parameter #73A.

2: Only if Parameter #71A and #72A are used.

Preliminary

DS39689E-page 357

PIC18F4321 FAMILY

FIGURE 26-17:

I²C™ BUS START/STOP BITS TIMING

SCL

91

93

90

92

SDA

Stop

Condition

Start

Condition

Note: Refer to Figure 26-5 for load conditions.

TABLE 26-18: I²C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)

Param.

Symbol

Characteristic

Min

Max

Units

Conditions

No.

90

TSU:STA Start Condition

Setup Time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

4700

600

—

ns

Only relevant for Repeated

Start condition

91

92

93

THD:STA Start Condition

Hold Time

4000

600

ns

After this period, the first

clock pulse is generated

TSU:STO Stop Condition

Setup Time

4700

600

THD:STO Stop Condition

Hold Time

4000

600

FIGURE 26-18:

I²C™ BUS DATA TIMING

103

102

100

101

SCL

90

106

107

91

92

SDA

In

110

109

SDA

Out

Note: Refer to Figure 26-5 for load conditions.

DS39689E-page 358

Preliminary

PIC18F4321 FAMILY

TABLE 26-19: I²C™ BUS DATA REQUIREMENTS (SLAVE MODE)

Param.

No.

Symbol

Characteristic

Min

Max Units

Conditions

100

101

THIGH

Clock High Time

Clock Low Time

100 kHz mode

4.0

0.6

—

μs

400 kHz mode

MSSP Module

100 kHz mode

400 kHz mode

MSSP Module

1.5 TCY

4.7

—

TLOW

—

μs

1.3

—

1.5 TCY

—

102

103

TR

TF

SDA and SCL Rise 100 kHz mode

Time

1000

ns

400 kHz mode

20 + 0.1 CB 300

CB is specified to be from

10 to 400 pF

SDA and SCL Fall 100 kHz mode

Time

—

300

ns

400 kHz mode

20 + 0.1 CB 300

CB is specified to be from

10 to 400 pF

90

TSU:STA Start Condition

Setup Time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

4.7

0.6

4.0

0.6

0

—

μs

ns

μs

ns

μs

ns

μs

Only relevant for Repeated

Start condition

91

THD:STA Start Condition

Hold Time

—

After this period, the first

clock pulse is generated

—

106

107

92

THD:DAT Data Input Hold

Time

—

0

0.9

—

TSU:DAT Data Input Setup

Time

250

100

4.7

0.6

—

(Note 2)

—

TSU:STO Stop Condition

Setup Time

—

109

110

TAA

Output Valid from

Clock

3500

—

(Note 1)

—

TBUF

Bus Free Time

4.7

1.3

—

Time the bus must be free

before a new transmission

can start

—

D102

CB

Bus Capacitive Loading

—

400

pF

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A Fast mode I²C bus device can be used in a Standard mode I²C bus system, but the requirement

TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the

LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must

output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the

Standard mode I²C bus specification), before the SCL line is released.

Preliminary

DS39689E-page 359

PIC18F4321 FAMILY

FIGURE 26-19:

MASTER SSP I²C™ BUS START/STOP BITS TIMING WAVEFORMS

SCL

SDA

93

91

90

92

Stop

Condition

Start

Condition

Note: Refer to Figure 26-5 for load conditions.

TABLE 26-20: MASTER SSP I²C™ BUS START/STOP BITS REQUIREMENTS

Param.

Symbol

Characteristic

Min

Max Units

Conditions

No.

90

TSU:STA Start Condition

Setup Time

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾2(TOSC)(BRG + 1)

2(TOSC)(BRG + 1)

—

ns Only relevant for

Repeated Start

condition

91

92

93

THD:STA Start Condition

Hold Time

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾2(TOSC)(BRG + 1)

2(TOSC)(BRG + 1)

ns After this period, the

first clock pulse is

generated

2(TOSC)(BRG + 1)

TSU:STO Stop Condition

Setup Time

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾2(TOSC)(BRG + 1)

2(TOSC)(BRG + 1)

ns

2(TOSC)(BRG + 1)

THD:STO Stop Condition

Hold Time

100 kHz mode

400 kHz mode

2(TOSC)(BRG + 1)

ns

2(TOSC)(BRG + 1)

1 MHz mode⁽¹⁾2(TOSC)(BRG + 1)

Note 1: Maximum pin capacitance = 10 pF for all I²C pins.

FIGURE 26-20:

MASTER SSP I²C™ BUS DATA TIMING

103

102

100

101

SCL

90

106

91

92

107

SDA

In

110

109

SDA

Out

Note: Refer to Figure 26-5 for load conditions.

DS39689E-page 360

Preliminary

PIC18F4321 FAMILY

TABLE 26-21: MASTER SSP I²C™ BUS DATA REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min

Max Units

Conditions

100

101

102

103

90

THIGH

Clock High Time 100 kHz mode

400 kHz mode

2(TOSC)(BRG + 1)

—

ms

ns

1 MHz mode⁽¹⁾2(TOSC)(BRG + 1)

—

TLOW

TR

Clock Low Time 100 kHz mode

400 kHz mode

2(TOSC)(BRG + 1)

—

2(TOSC)(BRG + 1)

—

1 MHz mode⁽¹⁾2(TOSC)(BRG + 1)

—

SDA and SCL

Rise Time

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

—

1000

300

100

—

CB is specified to be from

10 to 400 pF

20 + 0.1 CB

ns

—

ns

TF

SDA and SCL

Fall Time

ns

CB is specified to be from

10 to 400 pF

20 + 0.1 CB

—

ns

TSU:STA Start Condition 100 kHz mode

2(TOSC)(BRG + 1)

ms Only relevant for

Setup Time

Repeated Start

condition

ms

400 kHz mode

1 MHz mode⁽¹⁾2(TOSC)(BRG + 1)

2(TOSC)(BRG + 1)

—

ms

—

91

THD:STA Start Condition 100 kHz mode

2(TOSC)(BRG + 1)

—

ms After this period, the first

Hold Time

clock pulse is generated

400 kHz mode

2(TOSC)(BRG + 1)

—

ms

1 MHz mode⁽¹⁾2(TOSC)(BRG + 1)

—

ms

ns

106

107

92

THD:DAT Data Input

Hold Time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

0

—

0

0.9

—

ms

TSU:DAT Data Input

Setup Time

250

ns

(Note 2)

100

—

TSU:STO Stop Condition

Setup Time

2(TOSC)(BRG + 1)

—

ms

ns

—

1 MHz mode⁽¹⁾2(TOSC)(BRG + 1)

—

109

TAA

Output Valid

from Clock

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

—

3500

1000

—

ns

—

ns

110

TBUF

CB

Bus Free Time

4.7

1.3

—

ms Time the bus must be free

before a new transmission

—

ms

can start

pF

D102

Bus Capacitive Loading

—

400

Note 1: Maximum pin capacitance = 10 pF for all I²C pins.

2: A Fast mode I²C bus device can be used in a Standard mode I²C bus system, but parameter 107 ≥ 250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the

SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit

to the SDA line, parameter 102 + parameter 107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the

SCL line is released.

Preliminary

DS39689E-page 361

PIC18F4321 FAMILY

FIGURE 26-21:

EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

RC6/TX/CK

121

RC7/RX/DT

120

Note: Refer to Figure 26-5 for load conditions.

122

TABLE 26-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Param

Symbol

Characteristic

Min

Max

Units Conditions

No.

120

TckH2dtV SYNC XMIT (MASTER & SLAVE)

Clock High to Data Out Valid

PIC18FXXXX

—

40

100

20

ns

PIC18LFXXXX

ns VDD = 2.0V

ns

121

122

Tckrf

Tdtrf

Clock Out Rise Time and Fall Time PIC18FXXXX

(Master mode)

PIC18LFXXXX

50

ns VDD = 2.0V

ns

Data Out Rise Time and Fall Time

PIC18FXXXX

20

PIC18LFXXXX

50

ns VDD = 2.0V

FIGURE 26-22:

EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

RC6/TX/CK

125

RC7/RX/DT

126

Note: Refer to Figure 26-5 for load conditions.

TABLE 26-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS

Param.

Symbol

Characteristic

Min

Max

Units

Conditions

No.

125

TdtV2ckl SYNC RCV (MASTER & SLAVE)

Data Hold before CK ↓ (DT hold time)

10

15

—

ns

126

TckL2dtl

Data Hold after CK ↓ (DT hold time)

DS39689E-page 362

Preliminary

PIC18F4321 FAMILY

TABLE 26-24: A/D CONVERTER CHARACTERISTICS: PIC18F2221/2321/4221/4321 (INDUSTRIAL)

PIC18LF2221/2321/4221/4321 (INDUSTRIAL)

Param

No.

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

A01

NR

Resolution

—

10

<±1

bit ΔVREF ≥ 3.0V

A03

A04

A06

A07

A10

A20

EIL

Integral Linearity Error

Differential Linearity Error

Offset Error

—

LSb ΔVREF ≥ 3.0V

EDL

EOFF

EGN

—

<±1

—

<±1.5

<±1

Gain Error

—

Monotonicity

Guaranteed⁽¹⁾

—

VSS ≤ VAIN ≤ VREF

VDD < 3.0V

VDD ≥ 3.0V

ΔVREF Reference Voltage Range

1.8

3

—

V

(VREFH – VREFL)

A21

A22

A25

A30

VREFH Reference Voltage High

—

VSS – 0.3V

VREFL

—

VDD + 3.0V

—

V

VREFL

VAIN

Reference Voltage Low

Analog Input Voltage

VREFH

2.5

V

ZAIN

Recommended Impedance of

Analog Voltage Source

kΩ

A50

IREF

VREF Input Current⁽²⁾

—

5

150

μA During VAIN acquisition.

μA During A/D conversion

cycle.

Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.

VREFL current is from RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.

Preliminary

DS39689E-page 363

PIC18F4321 FAMILY

FIGURE 26-23:

A/D CONVERSION TIMING

BSF ADCON0, GO

(Note 2)

131

130

Q4

A/D CLK⁽¹⁾

132

. . .

9

8

7

2

1

0

A/D DATA

ADRES

NEW_DATA

TCY

OLD_DATA

ADIF

GO

DONE

SAMPLING STOPPED

SAMPLE

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.

This allows the SLEEPinstruction to be executed.

2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

TABLE 26-25: A/D CONVERSION REQUIREMENTS

Param

Symbol

Characteristic

Min

Max

Units

Conditions

No.

130

TAD

A/D Clock Period

PIC18FXXXX

0.7

1.4

25.0⁽¹⁾

μs TOSC based, VREF ≥ 3.0V

PIC18LFXXXX

μs VDD = 2.0V;

TOSC based, VREF full range

PIC18FXXXX

TBD

11

1

3

μs A/D RC mode

μs VDD = 2.0V; A/D RC mode

TAD

PIC18LFXXXX

131

132

TCNV

TACQ

Conversion Time

12

(not including acquisition time)⁽²⁾

Acquisition Time⁽³⁾

1.4

TBD

—

μs -40°C to +85°C

μs

0°C ≤ to ≤ +85°C

135

136

TSWC

TDIS

Switching Time from Convert → Sample

—

(Note 4)

Discharge Time

0.2

—

μs

Legend: TBD = To Be Determined

Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.

2: ADRES register may be read on the following TCY cycle.

3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale

after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.

4: On the following cycle of the device clock.

DS39689E-page 364

Preliminary

PIC18F4321 FAMILY

27.0 DC AND AC

CHARACTERISTICS GRAPHS

AND TABLES

Graphs and tables are not available at this time.

Preliminary

DS39689E-page 365

PIC18F4321 FAMILY

NOTES:

DS39689E-page 366

Preliminary

PIC18F4321 FAMILY

28.0 PACKAGING INFORMATION

28.1 Package Marking Information

28-Lead SPDIP

Example

e

3

PIC18F2321-I/SP

0710017

XXXXXXXXXXXXXXXXX

YYWWNNN

28-Lead SOIC

Example

e

3

XXXXXXXXXXXXXXXXXXXX

PIC18F2321-E/SO

0710017

YYWWNNN

28-Lead QFN

Example

XXXXXXXX

YYWWNNN

18F2321

/MM

0710017

e

3

28-Lead SSOP

Example

XXXXXXXXXXXX

PIC18F2321

-I/SS

e

3

YYWWNNN

0710017

Legend: XX...X Customer-specific information

Y

YY

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

Preliminary

DS39689E-page 367

PIC18F4321 FAMILY

28.1 Package Marking Information (Continued)

40-Lead PDIP

Example

XXXXXXXXXXXXXXXXXX

YYWWNNN

e

3

PIC18F4321-I/P

0710017

44-Lead QFN

Example

-I/ML

XXXXXXXXXX

YYWWNNN

PIC18F4321

e

3

0710017

44-Lead TQFP

Example

XXXXXXXXXX

YYWWNNN

PIC18F4321

-I/PT

0710017

e

3

DS39689E-page 368

Preliminary

PIC18F4321 FAMILY

28-Lead Skinny Plastic Dual In-Line (SP or PJ) – 300 mil Body [SPDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

NOTE 1

E1

1

2 3

D

E

A2

A

L

c

b1

A1

b

e

eB

Units

INCHES

NOM

28

Dimension Limits

MIN

MAX

Number of Pins

Pitch

N

e

.100 BSC

–

Top to Seating Plane

A

–

.200

.150

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.120

.015

.290

.240

1.345

.110

.008

.040

.014

–

.135

–

.310

.285

1.365

.130

.010

.050

.018

–

.335

.295

1.400

.150

.015

.070

.022

.430

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

b1

b

Lower Lead Width

Overall Row Spacing §

eB

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-070B

Preliminary

DS39689E-page 369

PIC18F4321 FAMILY

28-Lead Plastic Small Outline (SO or OI) – Wide, 7.50 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

1

2

3

e

b

h

α

h

c

φ

A2

A

L

A1

L1

β

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

28

1.27 BSC

Overall Height

A

–

2.65

–

Molded Package Thickness

Standoff §

A2

A1

E

2.05

0.10

–

0.30

Overall Width

10.30 BSC

Molded Package Width

Overall Length

Chamfer (optional)

Foot Length

E1

D

h

7.50 BSC

17.90 BSC

0.25

0.40

–

0.75

1.27

L

–

Footprint

L1

φ

1.40 REF

Foot Angle Top

Lead Thickness

Lead Width

0°

0.18

0.31

5°

–

8°

c

0.33

0.51

15°

b

Mold Draft Angle Top

Mold Draft Angle Bottom

α

β

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-052B

DS39689E-page 370

Preliminary

PIC18F4321 FAMILY

28-Lead Plastic Quad Flat, No Lead Package (MM) – 6x6x0.9 mm Body [QFN-S]

with 0.40 mm Contact Length

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D2

D

EXPOSED

PAD

e

E2

E

b

2

1

2

1

K

N

L

NOTE 1

BOTTOM VIEW

TOP VIEW

A

A3

A1

Units

MILLIMETERS

NOM

Dimension Limits

MIN

MAX

Number of Pins

N

e

28

Pitch

0.65 BSC

0.90

Overall Height

Standoff

A

0.80

0.00

1.00

0.05

A1

A3

E

0.02

Contact Thickness

Overall Width

0.20 REF

6.00 BSC

3.70

Exposed Pad Width

Overall Length

Exposed Pad Length

Contact Width

Contact Length

Contact-to-Exposed Pad

E2

D

3.65

4.70

6.00 BSC

3.70

D2

b

3.65

0.23

0.30

0.20

4.70

0.43

0.50

–

0.38

L

0.40

K

–

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-124B

Preliminary

DS39689E-page 371

PIC18F4321 FAMILY

28-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

1

2

b

NOTE 1

e

c

A2

A

φ

A1

L

L1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

28

0.65 BSC

Overall Height

Molded Package Thickness

Standoff

A

–

1.75

–

2.00

1.85

–

A2

A1

E

1.65

0.05

7.40

5.00

9.90

0.55

Overall Width

Molded Package Width

Overall Length

Foot Length

7.80

5.30

10.20

0.75

1.25 REF

–

8.20

5.60

10.50

0.95

E1

D

L

Footprint

L1

c

Lead Thickness

Foot Angle

0.09

0°

0.25

8°

φ

4°

Lead Width

b

0.22

–

0.38

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-073B

DS39689E-page 372

Preliminary

PIC18F4321 FAMILY

40-Lead Plastic Dual In-Line (P or PL) – 600 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

NOTE 1

E1

1 2 3

D

E

A2

A

L

c

b1

b

A1

e

eB

Units

INCHES

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

40

.100 BSC

Top to Seating Plane

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A

–

.250

.195

–

A2

A1

E

.125

.015

.590

.485

1.980

.115

.008

.030

.014

–

.625

.580

2.095

.200

.015

.070

.023

.700

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

b1

b

Lower Lead Width

Overall Row Spacing §

eB

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-016B

Preliminary

DS39689E-page 373

PIC18F4321 FAMILY

44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D2

D

EXPOSED

PAD

e

b

K

E

E2

2

1

2

1

N

NOTE 1

L

TOP VIEW

BOTTOM VIEW

A

A3

A1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

44

MAX

Number of Pins

N

e

Pitch

0.65 BSC

0.90

Overall Height

Standoff

A

0.80

0.00

1.00

0.05

A1

A3

E

0.02

Contact Thickness

Overall Width

0.20 REF

8.00 BSC

6.45

Exposed Pad Width

Overall Length

Exposed Pad Length

Contact Width

Contact Length

Contact-to-Exposed Pad

E2

D

6.30

6.80

8.00 BSC

6.45

D2

b

6.30

0.25

0.30

0.20

6.80

0.38

0.50

–

0.30

L

0.40

K

–

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-103B

DS39689E-page 374

Preliminary

PIC18F4321 FAMILY

44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

D1

E

e

E1

N

b

NOTE 1

1 2 3

NOTE 2

α

A

c

φ

A2

β

A1

L

L1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

44

MAX

Number of Leads

Lead Pitch

N

e

0.80 BSC

–

Overall Height

A

–

1.20

1.05

0.15

0.75

Molded Package Thickness

Standoff

A2

A1

L

0.95

0.05

0.45

1.00

–

Foot Length

0.60

Footprint

L1

φ

1.00 REF

3.5°

Foot Angle

0°

7°

Overall Width

E

12.00 BSC

10.00 BSC

–

Overall Length

D

Molded Package Width

Molded Package Length

Lead Thickness

Lead Width

E1

D1

c

0.09

0.30

11°

0.20

0.45

13°

b

0.37

Mold Draft Angle Top

Mold Draft Angle Bottom

α

β

12°

11°

12°

13°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

Preliminary

DS39689E-page 375

PIC18F4321 FAMILY

NOTES:

DS39689E-page 376

Preliminary

PIC18F4321 FAMILY

Revision E (February 2007)

APPENDIX A: REVISION HISTORY

Revision A (July 2005)

This revision includes updates to the packaging

diagrams.

Original data sheet for PIC18F2221/2321/4221/4321

devices.

APPENDIX B: DEVICE

DIFFERENCES

Revision B (August 2006)

Updated Section 26.0 “Electrical Characteristic”.

The differences between the devices listed in this data

sheet are shown in Table B-1.

Revision C (October 2006)

This revision includes updates to the packaging

diagrams.

Revision D (January 2007)

This revision includes updates to the packaging

diagrams.

TABLE B-1:

DEVICE DIFFERENCES

Features

PIC18F2221

PIC18F2321

PIC18F4221

PIC18F4321

Program Memory (Bytes)

Program Memory (Instructions)

Interrupt Sources

4096

8192

4096

19

4096

2048

20

8192

4096

20

2048

19

I/O Ports

Ports A, B, C, (E)

Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E

Capture/Compare/PWM Modules

2

0

2

0

1

Enhanced Capture/Compare/

PWM Modules

Parallel Communications (PSP)

10-Bit Analog-to-Digital Module

Packages

No

Yes

10 input channels 10 input channels 13 input channels 13 input channels

28-pin SPDIP

28-pin SOIC

28-pin SSOP

28-pin QFN

28-pin SPDIP

28-pin SOIC

28-pin SSOP

28-pin QFN

40-pin PDIP

44-pin TQFP

44-pin QFN

40-pin PDIP

44-pin TQFP

44-pin QFN

Preliminary

DS39689E-page 377

PIC18F4321 FAMILY

APPENDIX C: CONVERSION

CONSIDERATIONS

APPENDIX D: MIGRATION FROM

BASELINE TO

ENHANCED DEVICES

This appendix discusses the considerations for

converting from previous versions of a device to the

ones listed in this data sheet. Typically, these changes

are due to the differences in the process technology

used. An example of this type of conversion is from a

PIC16C74A to a PIC16C74B.

This section discusses how to migrate from a Baseline

device (i.e., PIC16C5X) to an Enhanced MCU device

(i.e., PIC18FXXX).

The following are the list of modifications over the

PIC16C5X microcontroller family:

The PIC18F4321 family of devices is functionally the

same as the PIC18F4320 family. Code written for a

PIC18F4320 will generally work on a PIC18F4321 with

few or no changes.

Not Currently Available

The following is a list of changes the user should be

aware of when migrating an application from the

PIC18F4320 to the PIC18F4321. Code written for the

PIC18F4321 may not run as expected due to these

differences.

1. Entry to power-managed modes has changed.

Modifyingthe SCS1:SCS0 bits (OSCCON<1:0>)

immediately changes the current clock source. It

is not necessary to execute a SLEEPinstruction

to change clock sources. Refer to Section 3.1.2

“Entering Power-Managed Modes” for details.

2. Exit from power-managed modes has changed.

A WDT wake or interrupt does not cause an

automatic return to PRI_RUN mode. The

controller will execute code while continuing to

use the current clock source. If the controller

was operating in RC_IDLE or RC_RUN mode,

an interrupt will cause entry to RC_RUN mode

until code selects another power-managed

mode. Refer to Section 3.4 “Idle Modes” for

details.

3. The extended instruction set can be con-

figured as enabled using the XINST bit

(CONFIG4L<6>). The access memory map is

also modified when the extended instruction set

is enabled. Refer to Section 5.5 “Data Memory

and the Extended Instruction Set” and

Section 24.2 “Extended Instruction Set” for

details.

4. There may also be changes to the electrical spec-

ifications. Refer to Section 26.0 “Electrical

Characteristics” for details.

DS39689E-page 378

Preliminary

PIC18F4321 FAMILY

APPENDIX E: MIGRATION FROM

MID-RANGE TO

APPENDIX F: MIGRATION FROM

HIGH-END TO

ENHANCED DEVICES

A detailed discussion of the differences between the

mid-range MCU devices (i.e., PIC16CXXX) and the

Enhanced devices (i.e., PIC18FXXX) is provided in

AN716, “Migrating Designs from PIC16C74A/74B to

PIC18C442”. The changes discussed, while device

specific, are generally applicable to all mid-range to

Enhanced device migrations.

A detailed discussion of the migration pathway and

differences between the high-end MCU devices (i.e.,

PIC17CXXX) and the Enhanced devices (i.e.,

PIC18FXXX) is provided in AN726, “PIC17CXXX to

PIC18CXXX Migration”.

This Application Note is available as Literature Number

DS00726.

This Application Note is available as Literature Number

DS00716.

Preliminary

DS39689E-page 379

PIC18F4321 FAMILY

NOTES:

DS39689E-page 380

Preliminary

PIC18F4321 FAMILY

INDEX

BF .................................................................................... 195

BF Status Flag ................................................................. 195

Block Diagrams

A

A/D ................................................................................... 227

A/D Converter Interrupt, Configuring ....................... 231

Acquisition Requirements ........................................ 232

ADCON0 Register .................................................... 227

ADCON1 Register .................................................... 227

ADCON2 Register .................................................... 227

ADRESH Register ............................................ 227, 230

ADRESL Register .................................................... 227

Analog Port Pins, Configuring .................................. 234

Associated Registers ............................................... 236

Calculating the Minimum Required

A/D ........................................................................... 230

Analog Input Model .................................................. 231

Baud Rate Generator .............................................. 191

Capture Mode Operation ......................................... 141

Comparator Analog Input Model .............................. 241

Comparator I/O Operating Modes ........................... 238

Comparator Output .................................................. 240

Comparator Voltage Reference ............................... 244

Comparator Voltage Reference

Output Buffer Example .................................... 245

Compare Mode Operation ....................................... 142

Device Clock .............................................................. 29

Enhanced PWM ....................................................... 149

EUSART Receive .................................................... 219

EUSART Transmit ................................................... 216

External Power-on Reset Circuit

(Slow VDD Power-up) ........................................ 43

Fail-Safe Clock Monitor ........................................... 266

Generic I/O Port ....................................................... 105

High/Low-Voltage Detect with

Acquisition Time .............................................. 232

Configuring the Module ............................................ 231

Conversion Clock (TAD) ........................................... 233

Conversion Requirements ....................................... 364

Conversion Status (GO/DONE Bit) .......................... 230

Conversions ............................................................. 235

Converter Characteristics ........................................ 363

Discharge ................................................................. 235

Operation in Power-Managed Modes ...................... 234

Selecting and Configuring Acquisition Time ............ 233

Special Event Trigger (CCP) .................................... 236

Special Event Trigger (ECCP) ................................. 148

Use of the CCP2 Trigger .......................................... 236

Absolute Maximum Ratings ............................................. 327

AC (Timing) Characteristics ............................................. 345

Load Conditions for Device

External Input .................................................. 248

HSPLL ....................................................................... 25

Interrupt Logic ............................................................ 92

INTOSC and PLL ....................................................... 26

2

MSSP (I C Master Mode) ........................................ 189

2

MSSP (I C Mode) .................................................... 170

Timing Specifications ....................................... 346

Parameter Symbology ............................................. 345

Temperature and Voltage Specifications ................. 346

Timing Conditions .................................................... 346

AC Characteristics

MSSP (SPI Mode) ................................................... 161

On-Chip Reset Circuit ................................................ 41

PIC18F2221/2321 ..................................................... 10

PIC18F4221/4321 ..................................................... 11

PORTD and PORTE (Parallel Slave Port) ............... 120

PWM Operation (Simplified) .................................... 144

Reads from Flash Program Memory ......................... 77

Single Comparator ................................................... 239

Table Read Operation ............................................... 73

Table Write Operation ............................................... 74

Table Writes to Flash Program Memory .................... 79

Timer0 in 16-Bit Mode ............................................. 124

Timer0 in 8-Bit Mode ............................................... 124

Timer1 ..................................................................... 128

Timer1 (16-Bit Read/Write Mode) ............................ 128

Timer2 ..................................................................... 134

Timer3 ..................................................................... 136

Timer3 (16-Bit Read/Write Mode) ............................ 136

Watchdog Timer ...................................................... 263

BN .................................................................................... 282

BNC ................................................................................. 283

BNN ................................................................................. 283

BNOV .............................................................................. 284

BNZ ................................................................................. 284

BOR. See Brown-out Reset.

Internal RC Accuracy ............................................... 348

Access Bank

Mapping with Indexed Literal Offset

Addressing Mode ............................................... 71

ACKSTAT ........................................................................ 195

ACKSTAT Status Flag ..................................................... 195

ADCON0 Register ............................................................ 227

GO/DONE Bit ........................................................... 230

ADCON1 Register ............................................................ 227

ADCON2 Register ............................................................ 227

ADDFSR .......................................................................... 316

ADDLW ............................................................................ 279

ADDULNK ........................................................................ 316

ADDWF ............................................................................ 279

ADDWFC ......................................................................... 280

ADRESH Register ............................................................ 227

ADRESL Register .................................................... 227, 230

Analog-to-Digital Converter. See A/D.

ANDLW ............................................................................ 280

ANDWF ............................................................................ 281

Assembler

MPASM Assembler .................................................. 324

Auto-Wake-up on Sync Break Character ......................... 220

BOV ................................................................................. 287

BRA ................................................................................. 285

Break Character (12-Bit) Transmit

and Receive ............................................................. 221

BRG. See Baud Rate Generator.

Brown-out Reset (BOR) ..................................................... 44

Detecting ................................................................... 44

Disabling in Sleep Mode ............................................ 44

Software Enabled ...................................................... 44

B

Bank Select Register (BSR) ............................................... 59

Baud Rate Generator ....................................................... 191

BC .................................................................................... 281

BCF .................................................................................. 282

Preliminary

DS39689E-page 381

PIC18F4321 FAMILY

BSF ..................................................................................285

BTFSC .............................................................................286

BTFSS ..............................................................................286

BTG ..................................................................................287

BZ .....................................................................................288

COMF .............................................................................. 290

Comparator ...................................................................... 237

Analog Input Connection Considerations ................ 241

Associated Registers ............................................... 241

Configuration ........................................................... 238

Effects of a Reset .................................................... 240

Interrupts ................................................................. 240

Operation ................................................................. 239

Operation During Sleep ........................................... 240

Outputs .................................................................... 239

Reference ................................................................ 239

External Signal ................................................ 239

C

C Compilers

MPLAB C18 .............................................................324

MPLAB C30 .............................................................324

CALL ................................................................................288

CALLW .............................................................................317

Capture (CCP Module) .....................................................141

Associated Registers ...............................................143

CCP Pin Configuration .............................................141

CCPRxH:CCPRxL Registers ...................................141

Prescaler ..................................................................141

Software Interrupt ....................................................141

Timer1/Timer3 Mode Selection ................................141

Capture (ECCP Module) ..................................................148

Capture/Compare/PWM (CCP) ........................................139

Capture Mode. See Capture.

Internal Signal .................................................. 239

Response Time ........................................................ 239

Comparator Specifications ............................................... 343

Comparator Voltage Reference ....................................... 243

Accuracy and Error .................................................. 244

Associated Registers ............................................... 245

Configuring .............................................................. 243

Connection Considerations ...................................... 244

Effects of a Reset .................................................... 244

Operation During Sleep ........................................... 244

Compare (CCP Module) .................................................. 142

Associated Registers ............................................... 143

CCPRx Register ...................................................... 142

Pin Configuration ..................................................... 142

Software Interrupt .................................................... 142

Special Event Trigger .............................. 137, 142, 236

Timer1/Timer3 Mode Selection ................................ 142

Compare (ECCP Module) ................................................ 148

Special Event Trigger .............................................. 148

Computed GOTO ............................................................... 56

Configuration Bits ............................................................ 253

Context Saving During Interrupts ..................................... 103

Conversion Considerations .............................................. 378

CPFSEQ .......................................................................... 290

CPFSGT .......................................................................... 291

CPFSLT ........................................................................... 291

Crystal Oscillator/Ceramic Resonator ................................ 23

Customer Change Notification Service ............................ 391

Customer Notification Service ......................................... 391

Customer Support ............................................................ 391

CCPRxH Register ....................................................140

CCPRxL Register .....................................................140

Compare Mode. See Compare.

Interaction of Two CCP Modules .............................140

Module Configuration ...............................................140

Pin Assignment ........................................................140

Timer Resources ......................................................140

Clock Sources ....................................................................29

Selecting the 31 kHz Source ......................................30

Selection Using OSCCON Register ...........................30

CLRF ................................................................................289

CLRWDT ..........................................................................289

Code Examples

16 x 16 Signed Multiply Routine ................................90

16 x 16 Unsigned Multiply Routine ............................90

8 x 8 Signed Multiply Routine ....................................89

8 x 8 Unsigned Multiply Routine ................................89

Address Masking .....................................................176

Changing Between Capture Prescalers ...................141

Computed GOTO Using an Offset Value ...................56

Data EEPROM Read .................................................85

Data EEPROM Refresh Routine ................................86

Data EEPROM Write .................................................85

Erasing a Flash Program Memory Row .....................78

Fast Register Stack ....................................................56

How to Clear RAM (Bank 1) Using

D

Data Addressing Modes .................................................... 67

Comparing Options with the

Extended Instruction Set Enabled ..................... 70

Direct ......................................................................... 67

Indexed Literal Offset ................................................ 69

Instructions Affected .......................................... 69

Indirect ....................................................................... 67

Inherent and Literal .................................................... 67

Data EEPROM Memory ..................................................... 83

Associated Registers ................................................. 87

EEADR Register ........................................................ 83

EECON1 and EECON2 Registers ............................. 83

EEDATA Register ...................................................... 83

Operation During Code-Protect ................................. 86

Protection Against Spurious Write ............................. 86

Reading ..................................................................... 85

Using ......................................................................... 86

Write Verify ................................................................ 85

Writing ....................................................................... 85

Indirect Addressing ............................................67

Implementing a Real-Time Clock

Using a Timer1 Interrupt Service .....................131

Initializing PORTA ....................................................105

Initializing PORTB ....................................................108

Initializing PORTC ....................................................111

Initializing PORTD ....................................................114

Initializing PORTE ....................................................117

Loading the SSPBUF (SSPSR) Register .................164

Reading a Flash Program Memory Word ..................77

Saving STATUS, WREG and

BSR Registers in RAM .....................................103

Writing to Flash Program Memory ....................... 80–81

Code Protection ....................................................... 253, 268

Associated Registers ...............................................269

Configuration Register Protection ............................271

Data EEPROM .........................................................271

Program Memory .....................................................269

DS39689E-page 382

Preliminary

PIC18F4321 FAMILY

Data Memory ..................................................................... 59

Access Bank .............................................................. 61

and the Extended Instruction Set ............................... 69

Bank Select Register (BSR) ....................................... 59

General Purpose Registers ........................................ 61

Map for PIC18F4321 Family ...................................... 60

Special Function Registers ........................................ 62

DAW ................................................................................. 292

DC and AC Characteristics

Graphs and Tables .................................................. 365

DC Characteristics ........................................................... 340

Power-Down and Supply Current ............................ 331

Supply Voltage ......................................................... 330

DCFSNZ .......................................................................... 293

DECF ............................................................................... 292

DECFSZ ........................................................................... 293

Dedicated ICD/ICSP Port ................................................. 271

Development Support ...................................................... 323

Device Differences ........................................................... 377

Device Overview .................................................................. 7

Details on Individual Family Members ......................... 8

Features (table) ............................................................ 9

New Core Features ...................................................... 7

Other Special Features ................................................ 8

Device Reset Timers .......................................................... 45

Oscillator Start-up Timer (OST) ................................. 45

PLL Lock Time-out ..................................................... 45

Power-up Timer (PWRT) ........................................... 45

Time-out Sequence .................................................... 45

Direct Addressing ............................................................... 68

Baud Rate Generator (BRG) ................................... 209

Associated Registers ....................................... 210

Auto-Baud Rate Detect .................................... 213

Baud Rate Error, Calculating ........................... 210

Baud Rates, Asynchronous Modes ................. 211

High Baud Rate Select (BRGH Bit) ................. 209

Sampling ......................................................... 209

Synchronous Master Mode ...................................... 222

Associated Registers, Receive ........................ 224

Associated Registers, Transmit ....................... 223

Reception ........................................................ 224

Transmission ................................................... 222

Synchronous Slave Mode ........................................ 225

Associated Registers, Receive ........................ 226

Associated Registers, Transmit ....................... 225

Reception ........................................................ 226

Transmission ................................................... 225

Extended Instruction Set

ADDFSR .................................................................. 316

ADDULNK ............................................................... 316

and Using MPLAB IDE Tools .................................. 322

CALLW .................................................................... 317

Considerations for Use ............................................ 320

MOVSF .................................................................... 317

MOVSS .................................................................... 318

PUSHL ..................................................................... 318

SUBFSR .................................................................. 319

SUBULNK ................................................................ 319

Syntax ...................................................................... 315

External Clock Input ........................................................... 24

E

F

Effect on Standard PIC Instructions ................................. 320

Effects of Power-Managed Modes on

Fail-Safe Clock Monitor ........................................... 253, 266

Exiting Operation ..................................................... 266

Interrupts in Power-Managed Modes ...................... 267

POR or Wake from Sleep ........................................ 267

WDT During Oscillator Failure ................................. 266

Fast Register Stack ........................................................... 56

Firmware Instructions ...................................................... 273

Flash Program Memory ..................................................... 73

Associated Registers ................................................. 81

Control Registers ....................................................... 74

EECON1 and EECON2 ..................................... 74

TABLAT (Table Latch) Register ........................ 76

TBLPTR (Table Pointer) Register ...................... 76

Erase Sequence ........................................................ 78

Erasing ...................................................................... 78

Operation During Code-Protect ................................. 81

Reading ..................................................................... 77

Table Pointer

Boundaries ........................................................ 76

Boundaries Based on Operation ....................... 76

Operations with TBLRD and TBLWT (table) ..... 76

Table Reads and Table Writes .................................. 73

Write Sequence ......................................................... 79

Writing ....................................................................... 79

Protection Against Spurious Writes ................... 81

Unexpected Termination ................................... 81

Write Verify ........................................................ 81

FSCM. See Fail-Safe Clock Monitor.

Various Clock Sources ............................................... 32

Electrical Characteristics .................................................. 327

Enhanced Capture/Compare/PWM (ECCP) .................... 147

Associated Registers ............................................... 160

Capture and Compare Modes .................................. 148

Capture Mode. See Capture (ECCP Module).

Outputs and Configuration ....................................... 148

Pin Configurations for ECCP1 ................................. 148

PWM Mode. See PWM (ECCP Module).

Standard PWM Mode ............................................... 148

Timer Resources ...................................................... 148

Enhanced PWM Mode. See PWM (ECCP Module).

Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART). See EUSART.

Equations

A/D Acquisition Time ................................................ 232

A/D Minimum Charging Time ................................... 232

Errata ................................................................................... 6

EUSART

Asynchronous Mode ................................................ 215

12-Bit Break Transmit and Receive ................. 221

Associated Registers, Receive ........................ 219

Associated Registers, Transmit ....................... 217

Auto-Wake-up on Sync Break ......................... 220

Receiver ........................................................... 218

Setting up 9-Bit Mode with

Address Detect ........................................ 218

Transmitter ....................................................... 215

Baud Rate Generator

G

GOTO .............................................................................. 294

Operation in Power-Managed Mode ................ 209

Preliminary

DS39689E-page 383

PIC18F4321 FAMILY

Indexed Literal Offset Addressing

H

and Standard PIC18 Instructions ............................. 320

Indexed Literal Offset Mode ............................................. 320

Indirect Addressing ............................................................ 68

INFSNZ ............................................................................ 295

Initialization Conditions for all Registers ...................... 49–52

Instruction Cycle ................................................................ 57

Clocking Scheme ....................................................... 57

Instruction Flow/Pipelining ................................................. 57

Instruction Set .................................................................. 273

ADDLW .................................................................... 279

ADDWF .................................................................... 279

ADDWF (Indexed Literal Offset Mode) .................... 321

ADDWFC ................................................................. 280

ANDLW .................................................................... 280

ANDWF .................................................................... 281

BC ............................................................................ 281

BCF ......................................................................... 282

BN ............................................................................ 282

BNC ......................................................................... 283

BNN ......................................................................... 283

BNOV ...................................................................... 284

BNZ ......................................................................... 284

BOV ......................................................................... 287

BRA ......................................................................... 285

BSF .......................................................................... 285

BSF (Indexed Literal Offset Mode) .......................... 321

BTFSC ..................................................................... 286

BTFSS ..................................................................... 286

BTG ......................................................................... 287

BZ ............................................................................ 288

CALL ........................................................................ 288

CLRF ....................................................................... 289

CLRWDT ................................................................. 289

COMF ...................................................................... 290

CPFSEQ .................................................................. 290

CPFSGT .................................................................. 291

CPFSLT ................................................................... 291

DAW ........................................................................ 292

DCFSNZ .................................................................. 293

DECF ....................................................................... 292

DECFSZ .................................................................. 293

Extended Instruction Set ......................................... 315

General Format ........................................................ 275

GOTO ...................................................................... 294

INCF ........................................................................ 294

INCFSZ .................................................................... 295

INFSNZ .................................................................... 295

IORLW ..................................................................... 296

IORWF ..................................................................... 296

LFSR ....................................................................... 297

MOVF ...................................................................... 297

MOVFF .................................................................... 298

MOVLB .................................................................... 298

MOVLW ................................................................... 299

MOVWF ................................................................... 299

MULLW .................................................................... 300

MULWF .................................................................... 300

NEGF ....................................................................... 301

NOP ......................................................................... 301

Opcode Field Descriptions ....................................... 274

POP ......................................................................... 302

PUSH ....................................................................... 302

RCALL ..................................................................... 303

RESET ..................................................................... 303

Hardware Multiplier ............................................................89

Introduction ................................................................89

Operation ...................................................................89

Performance Comparison ..........................................89

High/Low-Voltage Detect .................................................247

Applications ..............................................................250

Associated Registers ...............................................251

Characteristics .........................................................344

Current Consumption ...............................................249

Effects of a Reset .....................................................251

Operation .................................................................248

During Sleep ....................................................251

Setup ........................................................................249

Start-up Time ...........................................................249

Typical Application ...................................................250

HLVD. See High/Low-Voltage Detect.

I

I/O Ports ...........................................................................105

2

I C Mode (MSSP)

Acknowledge Sequence Timing ...............................198

Associated Registers ...............................................204

Baud Rate Generator ...............................................191

Bus Collision

During a Repeated Start Condition ..................202

During a Start Condition ...................................200

During a Stop Condition ...................................203

Clock Arbitration .......................................................192

Clock Stretching .......................................................184

10-Bit Slave Receive Mode (SEN = 1) .............184

10-Bit Slave Transmit Mode .............................184

7-Bit Slave Receive Mode (SEN = 1) ...............184

7-Bit Slave Transmit Mode ...............................184

Clock Synchronization and the CKP Bit ...................185

Effects of a Reset .....................................................199

General Call Address Support .................................188

2

I C Clock Rate w/BRG .............................................191

Master Mode ............................................................189

Operation .........................................................190

Reception .........................................................195

Repeated Start Condition Timing .....................194

Start Condition Timing .....................................193

Transmission ....................................................195

Multi-Master Communication, Bus Collision

and Arbitration ..................................................199

Multi-Master Mode ...................................................199

Operation .................................................................175

Read/Write Bit

Information (R/W Bit) .......................................175

Read/Write Bit Information (R/W Bit) .......................177

Registers ..................................................................170

Serial Clock (RC3/SCK/SCL) ...................................177

Slave Mode ..............................................................175

Address Masking .............................................176

Addressing .......................................................175

Reception .........................................................177

Transmission ....................................................177

Sleep Operation .......................................................199

Stop Condition Timing ..............................................198

ID Locations ............................................................. 253, 271

INCF .................................................................................294

INCFSZ ............................................................................295

In-Circuit Debugger ..........................................................271

In-Circuit Serial Programming (ICSP) ......................253, 271

DS39689E-page 384

Preliminary

PIC18F4321 FAMILY

RETFIE .................................................................... 304

RETLW .................................................................... 304

RETURN .................................................................. 305

RLCF ........................................................................ 305

RLNCF ..................................................................... 306

RRCF ....................................................................... 306

RRNCF .................................................................... 307

SETF ........................................................................ 307

SETF (Indexed Literal Offset Mode) ........................ 321

SLEEP ..................................................................... 308

Standard Instructions ............................................... 273

SUBFWB .................................................................. 308

SUBLW .................................................................... 309

SUBWF .................................................................... 309

SUBWFB .................................................................. 310

SWAPF .................................................................... 310

TBLRD ..................................................................... 311

TBLWT ..................................................................... 312

TSTFSZ ................................................................... 313

XORLW .................................................................... 313

XORWF .................................................................... 314

INTCON Registers ....................................................... 93–95

Memory Programming Requirements .............................. 342

Microchip Internet Web Site ............................................. 391

Migration from Baseline to Enhanced Devices ................ 378

Migration from High-End to Enhanced Devices ............... 379

Migration from Mid-Range to Enhanced Devices ............ 379

MOVF .............................................................................. 297

MOVFF ............................................................................ 298

MOVLB ............................................................................ 298

MOVLW ........................................................................... 299

MOVSF ............................................................................ 317

MOVSS ............................................................................ 318

MOVWF ........................................................................... 299

MPLAB ASM30 Assembler, Linker, Librarian .................. 324

MPLAB ICD 2 In-Circuit Debugger .................................. 325

MPLAB ICE 2000 High-Performance Universal

In-Circuit Emulator ................................................... 325

MPLAB ICE 4000 High-Performance Universal

In-Circuit Emulator ................................................... 325

MPLAB Integrated Development

Environment Software ............................................. 323

MPLAB PM3 Device Programmer ................................... 325

MPLINK Object Linker/MPLIB Object Librarian ............... 324

MSSP

2

Inter-Integrated Circuit. See I C.

Internal Oscillator Block ..................................................... 26

Adjustment ................................................................. 26

INTIO Modes .............................................................. 26

INTOSC Frequency Drift ............................................ 27

INTOSC Output Frequency ........................................ 26

OSCTUNE Register ................................................... 26

PLL in INTOSC Modes .............................................. 27

Internal RC Oscillator

Use with WDT .......................................................... 263

Internet Address ............................................................... 391

Interrupt Sources ............................................................. 253

A/D Conversion Complete ....................................... 231

Capture Complete (CCP) ......................................... 141

Compare Complete (CCP) ....................................... 142

Interrupt-on-Change (RB7:RB4) .............................. 108

INTn Pin ................................................................... 103

PORTB, Interrupt-on-Change .................................. 103

TMR0 ....................................................................... 103

TMR0 Overflow ........................................................ 125

TMR1 Overflow ........................................................ 127

TMR2-to-PR2 Match (PWM) ............................ 144, 149

TMR3 Overflow ................................................ 135, 137

Interrupts ............................................................................ 91

Interrupts, Flag Bits

ACK Pulse ....................................................... 175, 177

Control Registers (general) ..................................... 161

I C Mode. See I C Mode.

Module Overview ..................................................... 161

SPI Master/Slave Connection .................................. 165

SPI Mode. See SPI Mode.

2

SSPBUF Register .................................................... 166

SSPSR Register ...................................................... 166

MULLW ............................................................................ 300

MULWF ............................................................................ 300

N

NEGF ............................................................................... 301

NOP ................................................................................. 301

O

Oscillator Configuration ..................................................... 23

EC .............................................................................. 23

ECIO .......................................................................... 23

HS .............................................................................. 23

HSPLL ....................................................................... 23

Internal Oscillator Block ............................................. 26

INTIO1 ....................................................................... 23

INTIO2 ....................................................................... 23

LP .............................................................................. 23

RC ............................................................................. 23

RCIO .......................................................................... 23

XT .............................................................................. 23

Oscillator Selection .......................................................... 253

Oscillator Start-up Timer (OST) ................................... 32, 45

Oscillator Switching ........................................................... 29

Oscillator Transitions ......................................................... 30

Oscillator, Timer1 ..................................................... 127, 137

Oscillator, Timer3 ............................................................. 135

Interrupt-on-Change (RB7:RB4)

Flag (RBIF Bit) ................................................. 108

INTOSC, INTRC. See Internal Oscillator Block.

IORLW ............................................................................. 296

IORWF ............................................................................. 296

IPR Registers ................................................................... 100

L

LFSR ................................................................................ 297

Low-Voltage ICSP Programming. See Single-Supply

ICSP Programming.

P

M

Packaging Information ..................................................... 367

Details ...................................................................... 369

Marking .................................................................... 367

Master Clear (MCLR) ......................................................... 43

Master Synchronous Serial Port (MSSP). See MSSP.

Memory Organization ......................................................... 53

Data Memory ............................................................. 59

Program Memory ....................................................... 53

Preliminary

DS39689E-page 385

PIC18F4321 FAMILY

Parallel Slave Port (PSP) .........................................114, 120

Associated Registers ...............................................121

CS (Chip Select) ......................................................120

PORTD ....................................................................120

RD (Read Input) .......................................................120

Select (PSPMODE Bit) .................................... 114, 120

WR (Write Input) ......................................................120

PICSTART Plus Development Programmer ....................326

PIE Registers .....................................................................98

Pin Functions

PORTA

Associated Registers ............................................... 107

LATA Register ......................................................... 105

PORTA Register ...................................................... 105

TRISA Register ........................................................ 105

PORTB

Associated Registers ............................................... 110

LATB Register ......................................................... 108

PORTB Register ...................................................... 108

RB7:RB4 Interrupt-on-Change Flag

MCLR/VPP/RE3 .................................................... 12, 16

NC/ICCK/ICPGC ........................................................21

NC/ICDT/ICPGD ........................................................21

NC/ICPORTS .............................................................21

NC/ICRST/ICVPP .......................................................21

OSC1/CLKI/RA7 .................................................. 12, 16

OSC2/CLKO/RA6 ................................................ 12, 16

RA0/AN0 .............................................................. 13, 17

RA1/AN1 .............................................................. 13, 17

RA2/AN2/VREF-/CVREF ........................................ 13, 17

RA3/AN3/VREF+ ................................................... 13, 17

RA4/T0CKI/C1OUT .............................................. 13, 17

RA5/AN4/SS/HLVDIN/C2OUT ............................. 13, 17

RB0/INT0/FLT0/AN12 .......................................... 14, 18

RB1/INT1/AN10 ................................................... 14, 18

RB2/INT2/AN8 ..................................................... 14, 18

RB3/AN9/CCP2 ................................................... 14, 18

RB4/KBI0/AN11 ................................................... 14, 18

RB5/KBI1/PGM .................................................... 14, 18

RB6/KBI2/PGC .................................................... 14, 18

RB7/KBI3/PGD .................................................... 14, 18

RC0/T1OSO/T13CKI ...........................................15, 19

RC1/T1OSI/CCP2 ................................................ 15, 19

RC2/CCP1 .................................................................15

RC2/CCP1/P1A .........................................................19

RC3/SCK/SCL ..................................................... 15, 19

RC4/SDI/SDA ...................................................... 15, 19

RC5/SDO ............................................................. 15, 19

RC6/TX/CK .......................................................... 15, 19

RC7/RX/DT .......................................................... 15, 19

RD0/PSP0 ..................................................................20

RD1/PSP1 ..................................................................20

RD2/PSP2 ..................................................................20

RD3/PSP3 ..................................................................20

RD4/PSP4 ..................................................................20

RD5/PSP5/P1B ..........................................................20

RD6/PSP6/P1C ..........................................................20

RD7/PSP7/P1D ..........................................................20

RE0/RD/AN5 ..............................................................21

RE1/WR/AN6 .............................................................21

RE2/CS/AN7 ..............................................................21

VDD ....................................................................... 15, 21

VSS ....................................................................... 15, 21

Pinout I/O Descriptions

(RBIF Bit) ......................................................... 108

TRISB Register ........................................................ 108

PORTC

Associated Registers ............................................... 113

LATC Register ......................................................... 111

PORTC Register ...................................................... 111

RC3/SCK/SCL Pin ................................................... 177

TRISC Register ........................................................ 111

PORTD

Associated Registers ............................................... 116

LATD Register ......................................................... 114

Parallel Slave Port (PSP) Function .......................... 114

PORTD Register ...................................................... 114

TRISD Register ........................................................ 114

PORTE

Associated Registers ............................................... 119

LATE Register ......................................................... 117

PORTE Register ...................................................... 117

PSP Mode Select (PSPMODE Bit) .......................... 114

TRISE Register ........................................................ 117

Power-Managed Modes ..................................................... 33

and A/D Operation ................................................... 234

and EUSART Operation .......................................... 209

and PWM Operation ................................................ 159

and SPI Operation ................................................... 169

Clock Sources ............................................................ 33

Clock Transitions and Status Indicators .................... 34

Effects on Clock Sources ........................................... 32

Entering ..................................................................... 33

Exiting Idle and Sleep Modes .................................... 39

By Interrupt ........................................................ 39

By Reset ............................................................ 39

By WDT Time-out .............................................. 39

Without an Oscillator Start-up Delay ................. 40

Idle Modes ................................................................. 37

PRI_IDLE ........................................................... 38

RC_IDLE ........................................................... 39

SEC_IDLE ......................................................... 38

Multiple Sleep Commands ......................................... 34

Run Modes ................................................................ 34

PRI_RUN ........................................................... 34

RC_RUN ............................................................ 35

SEC_RUN ......................................................... 34

Sleep Mode ............................................................... 37

Summary (table) ........................................................ 33

Power-on Reset (POR) ...................................................... 43

Power-up Timer (PWRT) ........................................... 45

Time-out Sequence ................................................... 45

Power-up Delays ............................................................... 32

Power-up Timer (PWRT) ................................................... 32

Prescaler

PIC18F2221/2321 ......................................................12

PIC18F4221/4321 ......................................................16

PIR Registers .....................................................................96

PLL Frequency Multiplier ...................................................25

HSPLL Oscillator Mode ..............................................25

Use with INTOSC .......................................................25

POP ..................................................................................302

POR. See Power-on Reset.

Timer2 ..................................................................... 150

DS39689E-page 386

Preliminary

PIC18F4321 FAMILY

Prescaler, Timer0 ............................................................. 125

Prescaler, Timer2 ............................................................. 145

PRI_IDLE Mode ................................................................. 38

PRI_RUN Mode ................................................................. 34

Program Counter ............................................................... 54

PCL, PCH and PCU Registers ................................... 54

PCLATH and PCLATU Registers .............................. 54

Program Memory

and Extended Instruction Set ..................................... 71

Instructions ................................................................. 58

Two-Word .......................................................... 58

Interrupt Vector .......................................................... 53

Look-up Tables .......................................................... 56

Map and Stack (diagram) ........................................... 53

Reset Vector .............................................................. 53

Program Verification ........................................................ 268

Programming, Device Instructions ................................... 273

PSP. See Parallel Slave Port.

Reader Response ............................................................ 392

Register File ....................................................................... 61

Register File Summary ................................................ 63–65

Registers

ADCON0 (A/D Control 0) ......................................... 227

ADCON1 (A/D Control 1) ......................................... 228

ADCON2 (A/D Control 2) ......................................... 229

BAUDCON (Baud Rate Control) .............................. 208

CCP1CON (Enhanced Capture/Compare/PWM

Control 1) ......................................................... 147

CCPxCON (CCPx Control) ...................................... 139

CMCON (Comparator Control) ................................ 237

CONFIG1H (Configuration 1 High) .......................... 254

CONFIG2H (Configuration 2 High) .......................... 256

CONFIG2L (Configuration 2 Low) ........................... 255

CONFIG3H (Configuration 3 High) .......................... 257

CONFIG4L (Configuration 4 Low) ........................... 258

CONFIG5H (Configuration 5 High) .......................... 259

CONFIG5L (Configuration 5 Low) ........................... 259

CONFIG6H (Configuration 6 High) .......................... 260

CONFIG6L (Configuration 6 Low) ........................... 260

CONFIG7H (Configuration 7 High) .......................... 261

CONFIG7L (Configuration 7 Low) ........................... 261

CVRCON (Comparator Voltage

Pulse-Width Modulation. See PWM (CCP Module)

and PWM (ECCP Module).

PUSH ............................................................................... 302

PUSH and POP Instructions .............................................. 55

PUSHL ............................................................................. 318

PWM (CCP Module)

Associated Registers ............................................... 146

Auto-Shutdown (CCP1 Only) ................................... 145

Duty Cycle ................................................................ 144

Example Frequencies/Resolutions .......................... 145

Operation Setup ....................................................... 145

Period ....................................................................... 144

TMR2-to-PR2 Match ........................................ 144, 149

PWM (ECCP Module) ...................................................... 149

CCPR1H:CCPR1L Registers ................................... 149

Duty Cycle ................................................................ 150

Effects of a Reset ..................................................... 159

Enhanced PWM Auto-Shutdown ............................. 156

Example Frequencies/Resolutions .......................... 150

Full-Bridge Application Example .............................. 154

Full-Bridge Mode ...................................................... 153

Direction Change ............................................. 154

Half-Bridge Mode ..................................................... 152

Half-Bridge Output Mode Applications

Reference Control) .......................................... 243

DEVID1 (Device ID 1) .............................................. 262

DEVID2 (Device ID 2) .............................................. 262

ECCP1AS (ECCP Auto-Shutdown Control) ............ 157

ECCP1DEL (PWM Dead-Band Delay) .................... 156

EECON1 (Data EEPROM Control 1) ................... 75, 84

HLVDCON (High/Low-Voltage

Detect Control) ................................................ 247

INTCON (Interrupt Control) ....................................... 93

INTCON2 (Interrupt Control 2) .................................. 94

INTCON3 (Interrupt Control 3) .................................. 95

IPR1 (Peripheral Interrupt Priority 1) ....................... 100

IPR2 (Peripheral Interrupt Priority 2) ....................... 101

OSCCON (Oscillator Control) .................................... 31

OSCTUNE (Oscillator Tuning) ................................... 27

PIE1 (Peripheral Interrupt Enable 1) ......................... 98

PIE2 (Peripheral Interrupt Enable 2) ......................... 99

PIR1 (Peripheral Interrupt

Example ........................................................... 152

Operation in Power-Managed Modes ...................... 159

Operation with Fail-Safe Clock Monitor ................... 159

Output Configurations .............................................. 150

Output Relationships (Active-High) .......................... 151

Output Relationships (Active-Low) ........................... 151

Period ....................................................................... 149

Programmable Dead-Band Delay ............................ 156

Setup for PWM Operation ........................................ 159

Start-up Considerations ........................................... 158

Request (Flag) 1) ............................................... 96

PIR2 (Peripheral Interrupt

Request (Flag) 2) ............................................... 97

RCON (Reset Control) ....................................... 42, 102

RCSTA (Receive Status and Control) ..................... 207

SSPADD(MSSP Address) ....................................... 174

2

SSPCON1 (MSSP Control 1, I C Mode) ................. 172

SSPCON1 (MSSP Control 1, SPI Mode) ................ 163

2

SSPCON2 (MSSP Control 2, I C Mode) ................. 173

2

SSPSTAT (MSSP Status, I C Mode) ...................... 171

SSPSTAT (MSSP Status, SPI Mode) ...................... 162

STATUS .................................................................... 66

STKPTR (Stack Pointer) ............................................ 55

T0CON (Timer0 Control) ......................................... 123

T1CON (Timer1 Control) ......................................... 127

T2CON (Timer2 Control) ......................................... 133

T3CON (Timer3 Control) ......................................... 135

TRISE (PORTE/PSP Control) ................................. 118

TXSTA (Transmit Status and Control) ..................... 206

WDTCON (Watchdog Timer Control) ...................... 264

RESET ............................................................................. 303

Reset State of Registers .................................................... 48

Q

Q Clock .................................................................... 145, 150

R

RAM. See Data Memory.

RBIF Bit ............................................................................ 108

RC Oscillator ...................................................................... 25

RCIO Oscillator Mode ................................................ 25

RC_IDLE Mode .................................................................. 39

RC_RUN Mode .................................................................. 35

RCALL ............................................................................. 303

RCON Register

Bit Status During Initialization .................................... 48

Preliminary

DS39689E-page 387

PIC18F4321 FAMILY

Resets ........................................................................ 41, 253

Brown-out Reset (BOR) ...........................................253

Oscillator Start-up Timer (OST) ...............................253

Power-on Reset (POR) ............................................253

Power-up Timer (PWRT) .........................................253

RETFIE ............................................................................304

RETLW .............................................................................304

RETURN ..........................................................................305

Return Address Stack ........................................................54

Associated Registers .................................................54

Return Stack Pointer (STKPTR) ........................................55

Revision History ...............................................................377

RLCF ................................................................................305

RLNCF .............................................................................306

RRCF ...............................................................................306

RRNCF .............................................................................307

SUBULNK ........................................................................ 319

SUBWF ............................................................................ 309

SUBWFB ......................................................................... 310

SWAPF ............................................................................ 310

T

Table Reads/Table Writes ................................................. 56

TBLRD ............................................................................. 311

TBLWT ............................................................................. 312

Time-out in Various Situations (table) ................................ 45

Timer0 .............................................................................. 123

Associated Registers ............................................... 125

Operation ................................................................. 124

Overflow Interrupt .................................................... 125

Prescaler ................................................................. 125

Prescaler Assignment (PSA Bit) .............................. 125

Prescaler Select (T0PS2:T0PS0 Bits) ..................... 125

Prescaler. See Prescaler, Timer0.

S

SCK ..................................................................................161

SDI ...................................................................................161

SDO .................................................................................161

SEC_IDLE Mode ................................................................38

SEC_RUN Mode ................................................................34

Serial Clock, SCK .............................................................161

Serial Data In (SDI) ..........................................................161

Serial Data Out (SDO) .....................................................161

Serial Peripheral Interface. See SPI Mode.

SETF ................................................................................307

Single-Supply ICSP Programming.

Slave Select (SS) .............................................................161

SLEEP ..............................................................................308

Sleep

Reads and Writes in 16-Bit Mode ............................ 124

Source Edge Select (T0SE Bit) ............................... 124

Source Select (T0CS Bit) ......................................... 124

Switching Prescaler Assignment ............................. 125

Timer1 .............................................................................. 127

16-Bit Read/Write Mode .......................................... 129

Associated Registers ............................................... 131

Interrupt ................................................................... 130

Operation ................................................................. 128

Oscillator .......................................................... 127, 129

Layout Considerations ..................................... 130

Low-Power Option ........................................... 129

Overflow Interrupt .................................................... 127

Resetting, Using the CCP

OSC1 and OSC2 Pin States ......................................32

Software Simulator (MPLAB SIM) ....................................324

Special Event Trigger. See Compare (CCP Mode).

Special Event Trigger. See Compare (ECCP Module).

Special Features of the CPU ............................................253

Special Function Registers ................................................62

Map ............................................................................62

Special ICPORT Features ................................................271

SPI Mode (MSSP)

Associated Registers ...............................................169

Bus Mode Compatibility ...........................................169

Effects of a Reset .....................................................169

Enabling SPI I/O ......................................................165

Master Mode ............................................................166

Master/Slave Connection .........................................165

Operation .................................................................164

Operation in Power-Managed Modes ......................169

Serial Clock ..............................................................161

Serial Data In ...........................................................161

Serial Data Out ........................................................161

Slave Mode ..............................................................167

Slave Select .............................................................161

Slave Select Synchronization ..................................167

SPI Clock .................................................................166

Typical Connection ..................................................165

SS ....................................................................................161

SSPOV .............................................................................195

SSPOV Status Flag ..........................................................195

SSPSTAT Register

Special Event Trigger ...................................... 130

Special Event Trigger (ECCP) ................................. 148

TMR1H Register ...................................................... 127

TMR1L Register ....................................................... 127

Use as a Real-Time Clock ....................................... 130

Timer2 .............................................................................. 133

Associated Registers ............................................... 134

Interrupt ................................................................... 134

Operation ................................................................. 133

Output ...................................................................... 134

PR2 Register ................................................... 144, 149

TMR2-to-PR2 Match Interrupt ......................... 144, 149

Timer3 .............................................................................. 135

16-Bit Read/Write Mode .......................................... 137

Associated Registers ............................................... 137

Operation ................................................................. 136

Oscillator .......................................................... 135, 137

Overflow Interrupt ............................................ 135, 137

Special Event Trigger (CCP) ................................... 137

TMR3H Register ...................................................... 135

TMR3L Register ....................................................... 135

Timing Diagrams

A/D Conversion ........................................................ 364

Acknowledge Sequence .......................................... 198

Asynchronous Reception ......................................... 219

Asynchronous Transmission .................................... 216

Asynchronous Transmission

(Back to Back) ................................................. 216

Automatic Baud Rate Calculation ............................ 214

Auto-Wake-up Bit (WUE) During

Normal Operation ............................................ 220

Auto-Wake-up Bit (WUE) During Sleep ................... 220

Baud Rate Generator with Clock Arbitration ............ 192

BRG Overflow Sequence ......................................... 214

R/W Bit ............................................................. 175, 177

Stack Full/Underflow Resets ..............................................56

SUBFSR ...........................................................................319

SUBFWB ..........................................................................308

SUBLW ............................................................................309

DS39689E-page 388

Preliminary

PIC18F4321 FAMILY

BRG Reset Due to SDA Arbitration

PWM Auto-Shutdown (PRSEN = 1,

During Start Condition ..................................... 201

Brown-out Reset (BOR) ........................................... 350

Bus Collision During a Repeated

Auto-Restart Enabled) ..................................... 158

PWM Direction Change ........................................... 155

PWM Direction Change at Near

Start Condition (Case 1) .................................. 202

Bus Collision During a Repeated

Start Condition (Case 2) .................................. 202

Bus Collision During a

100% Duty Cycle ............................................. 155

PWM Output ............................................................ 144

Repeat Start Condition ............................................ 194

Reset, Watchdog Timer (WDT), Oscillator

Start Condition (SCL = 0) ................................. 201

Bus Collision During a

Stop Condition (Case 1) .................................. 203

Bus Collision During a

Stop Condition (Case 2) .................................. 203

Bus Collision During

Start Condition (SDA Only) .............................. 200

Bus Collision for Transmit and

Acknowledge ................................................... 199

Capture/Compare/PWM (All CCP Modules) ............ 352

CLKO and I/O .......................................................... 349

Clock Synchronization ............................................. 185

Clock/Instruction Cycle .............................................. 57

EUSART Synchronous Receive

Start-up Timer (OST),

Power-up Timer (PWRT) ................................. 350

Send Break Character Sequence ............................ 221

Slave Synchronization ............................................. 167

Slow Rise Time (MCLR Tied to VDD,

VDD Rise > TPWRT) ............................................ 47

SPI Mode (Master Mode) ........................................ 166

SPI Mode (Slave Mode, CKE = 0) ........................... 168

SPI Mode (Slave Mode, CKE = 1) ........................... 168

Synchronous Reception

(Master Mode, SREN) ..................................... 224

Synchronous Transmission ..................................... 222

Synchronous Transmission (Through TXEN) .......... 223

Time-out Sequence on POR w/PLL Enabled

(MCLR Tied to VDD) .......................................... 47

Time-out Sequence on Power-up

(Master/Slave) ................................................. 362

EUSART Synchronous Transmission

(Master/Slave) ................................................. 362

Example SPI Master Mode (CKE = 0) ..................... 354

Example SPI Master Mode (CKE = 1) ..................... 355

Example SPI Slave Mode (CKE = 0) ....................... 356

Example SPI Slave Mode (CKE = 1) ....................... 357

External Clock (All Modes Except PLL) ................... 347

Fail-Safe Clock Monitor ............................................ 267

First Start Bit Timing ................................................ 193

Full-Bridge PWM Output .......................................... 153

Half-Bridge PWM Output ......................................... 152

High/Low-Voltage Detect Characteristics ................ 344

High-Voltage Detect Operation

(MCLR Not Tied to VDD, Case 1) ...................... 46

Time-out Sequence on Power-up

(MCLR Not Tied to VDD, Case 2) ...................... 46

Time-out Sequence on Power-up

(MCLR Tied to VDD, VDD Rise < TPWRT) ........... 46

Timer0 and Timer1 External Clock .......................... 351

Transition for Entry to Idle Mode ............................... 38

Transition for Entry to SEC_RUN Mode .................... 35

Transition for Entry to Sleep Mode ............................ 37

Transition for Two-Speed Start-up

(INTOSC to HSPLL) ........................................ 265

Transition for Wake from Idle to Run Mode ............... 38

Transition for Wake from Sleep (HSPLL) .................. 37

Transition from RC_RUN Mode to

(VDIRMAG = 1) ................................................ 250

I C Bus Data ............................................................ 358

I C Bus Start/Stop Bits ............................................. 358

I C Master Mode (7 or 10-Bit Transmission) ........... 196

I C Master Mode (7-Bit Reception) .......................... 197

I C Slave Mode (10-Bit Reception, SEN = 0) .......... 182

I C Slave Mode (10-Bit Reception,

2

PRI_RUN Mode ................................................. 36

Transition from SEC_RUN Mode to

2

PRI_RUN Mode (HSPLL) .................................. 35

Transition to RC_RUN Mode ..................................... 36

Timing Diagrams and Specifications ............................... 347

Capture/Compare/PWM Requirements

2

SEN = 0, ADMSK = 01001) ............................. 181

I C Slave Mode (10-Bit Reception,

2

(All CCP Modules) ........................................... 352

CLKO and I/O Requirements ................................... 349

EUSART Synchronous Receive

Requirements .................................................. 362

EUSART Synchronous Transmission

Requirements .................................................. 362

Example SPI Mode Requirements

(Master Mode, CKE = 0) .................................. 354

Example SPI Mode Requirements

(Master Mode, CKE = 1) .................................. 355

Example SPI Mode Requirements

(Slave Mode, CKE = 0) .................................... 356

Example SPI Mode Requirements

SEN = 1) .......................................................... 187

I C Slave Mode (10-Bit Transmission) ..................... 183

I C Slave Mode (7-Bit Reception,

2

SEN = 0) .......................................................... 178

I C Slave Mode (7-bit Reception,

2

SEN = 0, ADMSK = 01011) ............................. 179

I C Slave Mode (7-Bit Reception, SEN = 1) ............ 186

I C Slave Mode (7-Bit Transmission) ....................... 180

I C Slave Mode General Call Address

2

Sequence (7 or 10-Bit Address Mode) ............ 188

I C Stop Condition Receive or

2

Transmit Mode ................................................. 198

Low-Voltage Detect Operation (VDIRMAG = 0) ...... 249

(Slave Mode, CKE = 1) .................................... 357

External Clock Requirements .................................. 347

2

Master SSP I C Bus Data ........................................ 360

2

Master SSP I C Bus Start/Stop Bits ........................ 360

I C Bus Data Requirements (Slave Mode) .............. 359

2

Parallel Slave Port (PIC18F4221/4321) ................... 353

Parallel Slave Port (PSP) Read ............................... 121

Parallel Slave Port (PSP) Write ............................... 121

PWM Auto-Shutdown (PRSEN = 0,

Master SSP I C Bus Data Requirements ................ 361

2

Master SSP I C Bus Start/Stop Bits

Requirements .................................................. 360

Parallel Slave Port Requirements

Auto-Restart Disabled) .................................... 158

(PIC18F4221/4321) ......................................... 353

Preliminary

DS39689E-page 389

PIC18F4321 FAMILY

PLL Clock .................................................................348

Reset, Watchdog Timer, Oscillator

V

Voltage Reference Specifications .................................... 343

Start-up Timer, Power-up Timer and

Brown-out Reset Requirements .......................350

Timer0 and Timer1 External

Clock Requirements .........................................351

Top-of-Stack Access ..........................................................54

TQFP Packages and Special Features ............................271

TRISE Register

PSPMODE Bit ..........................................................114

TSTFSZ ............................................................................313

Two-Speed Start-up ................................................. 253, 265

Two-Word Instructions

Example Cases ..........................................................58

TXSTA Register

W

Watchdog Timer (WDT) ........................................... 253, 263

Associated Registers ............................................... 264

Control Register ....................................................... 263

During Oscillator Failure .......................................... 266

Programming Considerations .................................. 263

WCOL ...................................................... 193, 194, 195, 198

WCOL Status Flag ................................... 193, 194, 195, 198

WWW Address ................................................................ 391

WWW, On-Line Support ...................................................... 6

X

BRGH Bit .................................................................209

XORLW ............................................................................ 313

XORWF ........................................................................... 314

DS39689E-page 390

Preliminary

PIC18F4321 FAMILY

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

Preliminary

DS39689E-page 391

PIC18F4321 FAMILY

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

Technical Publications Manager

Reader Response

Total Pages Sent ________

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

PIC18F4321 Family

DS39689E

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS39689E-page 392

Preliminary

PIC18F4321 FAMILY

PIC18F2221/2321/4221/4321 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

XXX

Examples:

Temperature

Range

Package

Pattern

a)

PIC18F4321-I/P 301 = Industrial temp., PDIP

package, Extended VDD limits, QTP pattern

#301.

b)

c)

PIC18LF2321-I/SO = Industrial temp., SOIC

package, Extended VDD limits.

Device

PIC18F2221/2321⁽¹⁾, PIC18F4221/4321⁽¹⁾

,

PIC18LF4321-I/P = Industrial temp., PDIP

package, normal VDD limits.

PIC18F2221/2321T⁽²⁾, PIC18F4221/4321T⁽²⁾

VDD range 4.2V to 5.5V

;

PIC18LF2221/2321⁽¹⁾, PIC18LF4221/4321⁽¹⁾

,

PIC18LF2221/2321T⁽²⁾, PIC18LF4221/4321T⁽²⁾

VDD range 2.0V to 5.5V

;

Temperature Range

Package

I

E

=

-40°C to +85°C (Industrial)

-40°C to +125°C (Extended)

PT

SO

SS

SP

P

MM

ML

=

TQFP (Thin Quad Flatpack)

Note 1:

2:

F

LF

T

=

Standard Voltage Range

Wide Voltage Range

in tape and reel TQFP

packages only.

SOIC

SSOP

Skinny Plastic DIP

PDIP

28L QFN

44L QFN

Pattern

QTP, SQTP, Code or Special Requirements

(blank otherwise)

Preliminary

DS39689E-page 393

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Habour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

12/08/06

DS39689E-page 394

Preliminary


型号：	PIC18F2321T-E/PT
厂家：	MICROCHIP
描述：	28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术闪存微控制器
文件：	总396页 (文件大小：6360K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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